add input / output stage missing modules

diff --git a/src/soc/fu/logical/input_stage.py b/src/soc/fu/logical/input_stage.py
new file mode 100644 (file)
index 0000000..df28187
--- /dev/null
+++ b/src/soc/fu/logical/input_stage.py
@@ -0,0 +1,27 @@
+# This stage is intended to adjust the input data before sending it to
+# the actual Logical pipeline. Things like handling inverting the input, xer_ca
+# generation for subtraction, and handling of immediates should happen
+# here
+from soc.fu.common_input_stage import CommonInputStage
+from soc.fu.logical.pipe_data import LogicalInputData
+
+
+class LogicalInputStage(CommonInputStage):
+    def __init__(self, pspec):
+        super().__init__(pspec, "input")
+
+    def ispec(self):
+        return LogicalInputData(self.pspec)
+
+    def ospec(self):
+        return LogicalInputData(self.pspec)
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform) # covers A-invert, carry, excludes SO
+        comb = m.d.comb
+        ctx = self.i.ctx
+
+        # operand b
+        comb += self.o.b.eq(self.i.b)
+
+        return m

diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py
new file mode 100644 (file)
index 0000000..7f833b3
--- /dev/null
+++ b/src/soc/fu/logical/output_stage.py
@@ -0,0 +1,19 @@
+# This stage is intended to handle the gating of carry and overflow
+# out, summary overflow generation, and updating the condition
+# register
+from nmigen import (Module, Signal, Cat, Repl)
+from nmutil.pipemodbase import PipeModBase
+from soc.fu.common_output_stage import CommonOutputStage
+from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData
+from ieee754.part.partsig import PartitionedSignal
+from soc.decoder.power_enums import InternalOp
+
+
+class LogicalOutputStage(CommonOutputStage):
+
+    def ispec(self):
+        return LogicalOutputData(self.pspec)
+
+    def ospec(self):
+        return LogicalOutputData(self.pspec)
+