commented-out and disabled the set_dcbz_addr function, it is the wrong

approach.

it is much better to add an extra parameter to set_wr_addr
"dcbz".

this to be added right across all set_wr_addr functions
(6 places)

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 89a5187fe10acfd7d4de9af1cb106e05c8d1b573..3db68c176cc1fafa2b07dc751ef89219302ceb23 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -260,7 +260,12 @@ class PortInterfaceBase(Elaboratable):
         # to memory, acknowledge address, and send out LD data
         with m.If(dcbz_active.q):
             ##comb += Display("dcbz active")
-            self.set_dcbz_addr(m, pi.addr.data)
+            # XXX Please don't do it this way, not without discussion
+            # the exact same address is required to be set by both
+            # dcbz and stores, so use the exact same function.
+            # it would be better to add an extra argument to
+            # set_wr_addr to indicate "dcbz mode".
+            self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data)
 
         # if now in "ST" mode: likewise do the same but with "ST"
         # to memory, acknowledge address, and send out LD data

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index a318b6f0ac06a2ce10d1c08d6a0d671328c38546..c377a6cd5edd7ccf381bb82d82440de4977b9e41 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -119,7 +119,12 @@ class LoadStore1(PortInterfaceBase):
         #self.nia           = Signal(64)
         #self.srr1          = Signal(16)
 
-    def set_dcbz_addr(self, m, addr):
+    # XXX please don't do it this way (and ask in future).
+    # the exact same logic is required for setting store addresses
+    # as for dcbz addresses, therefore why duplicate code?
+    # it would be better to add an argument to set_wr_addr to
+    # specifiy that it requires dcbz mode to be set.
+    def __please_remove_and_use_set_wr_addr_instead_set_dcbz_addr(self, m, addr):
         m.d.comb += self.req.load.eq(0) #not a load operation
         m.d.comb += self.req.dcbz.eq(1)
         #m.d.comb += self.req.byte_sel.eq(mask)
@@ -130,6 +135,7 @@ class LoadStore1(PortInterfaceBase):
         #m.d.comb += self.req.align_intr.eq(misalign)
         return None
 
+    # XXX please add a dcbz argument to all set_wr_addr functions instead.
     def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
         m.d.comb += self.req.load.eq(0) # store operation
         m.d.comb += self.req.byte_sel.eq(mask)