sigh. because POWER. CR index inversion

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 241dc94e7a3f0b54d02241e2d0b73a16f48a68b7..31d79a87e51ab499a1c6d55b9feb3638d1d2301d 100644 (file)
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -56,14 +56,15 @@ def regspec_decode(e, regfile, name):
 
     if regfile == 'CR':
         # CRRegs register numbering is *unary* encoded
+        # *sigh*.  numbering inverted on part-CRs.  because POWER.
         if name == 'full_cr': # full CR
             return e.read_cr_whole, 0b11111111, 0b11111111
         if name == 'cr_a': # CR A
-            return e.read_cr1.ok, 1<<e.read_cr1.data, 1<<e.write_cr.data
+            return e.read_cr1.ok, 1<<(7-e.read_cr1.data), 1<<(7-e.write_cr.data)
         if name == 'cr_b': # CR B
-            return e.read_cr2.ok, 1<<e.read_cr2.data, None
+            return e.read_cr2.ok, 1<<(7-e.read_cr2.data), None
         if name == 'cr_c': # CR C
-            return e.read_cr3.ok, 1<<e.read_cr2.data, None
+            return e.read_cr3.ok, 1<<(7-e.read_cr2.data), None
 
     if regfile == 'XER':
         # XERRegs register numbering is *unary* encoded

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 47d3e0d8c86d8ac3aebf38cdbb805de8f2a99333..564c6f3b751e753e3c68781c5baa0450c94e1ee4 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -154,14 +154,9 @@ class TestRunner(FHDLTestCase):
 
                 # set up CR regfile, "direct" write across all CRs
                 cr = test.cr
-                # sigh.  Because POWER
-                cr = int('{:032b}'.format(test.cr)[::-1], 2)
                 print ("cr reg", hex(cr))
                 for i in range(8):
-                    j = i
                     cri = (cr>>(j*4)) & 0xf
-                    # sigh.  Because POWER
-                    cri = int('{:04b}'.format(cri)[::-1], 2)
                     print ("cr reg", hex(cri), i,
                             core.regs.cr.regs[i].reg.shape())
                     yield core.regs.cr.regs[i].reg.eq(cri)