comment read ack in sram

diff --git a/src/soc/bus/sram.py b/src/soc/bus/sram.py
index 1575e6ae692f1fe198077a01487eb7710b5c0b64..7d63490901a041279fd16315e73a2ecd5f1353d1 100644 (file)
--- a/src/soc/bus/sram.py
+++ b/src/soc/bus/sram.py
@@ -71,7 +71,9 @@ class SRAM(Elaboratable):
         if self.memory.width > len(self.bus.dat_r):
             raise NotImplementedError
 
-        # read
+        # read - this relies on the read port producing data
+        # with one clock delay. the "ack" goes out on a sync
+        # which matches that
         m.submodules.rdport = rdport = self.memory.read_port()
         m.d.comb += [
             rdport.addr.eq(self.bus.adr[:len(rdport.addr)]),