logic/if tidyup

diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py
index 0eda61cc622b6c94cba1a72e4ea5a7a6b186bd5c..d6fa7460d2db89760957f7c410539bcfbaf13c3a 100755 (executable)
--- a/experiments7/doAlu16.py
+++ b/experiments7/doAlu16.py
@@ -80,21 +80,22 @@ class ALU16(Module):
         :param plug_name: name of the plug to use to guess the bit index,
         :return: boolean, True if the instance has been matched.
         """
-        matched = False
+        if not inst.getMasterCell().getName().startswith(op):
+            return False
         re_net_index = re.compile(r'[^(]+\((?P<index>[\d]+)\)$')
-        if inst.getMasterCell().getName().startswith(op):
-            for plug in inst.getPlugs():
-                if plug.getMasterNet().getName() == plug_name:
-                    m = re_net_index.match(plug.getNet().getName())
-                    if m:
-                        bit_slice = datapath_insts[int(m.group('index'))]
-                        for column in bit_slice:
-                            if column[0] == op:
-                                column[1] = inst
-                                matched = True
-                                break
-                        break
-        return matched
+        for plug in inst.getPlugs():
+            if plug.getMasterNet().getName() != plug_name:
+                continue
+            m = re_net_index.match(plug.getNet().getName())
+            if not m:
+                continue
+            bit_slice = datapath_insts[int(m.group('index'))]
+            for column in bit_slice:
+                if column[0] == op:
+                    column[1] = inst
+                    return True
+            break
+        return False
 
     def place_datapath(self, datapath_insts, x_orig, y_orig, fold):
         channel_sff1 = self.to_dbu(0)
@@ -125,9 +126,10 @@ class ALU16(Module):
             datapath_insts.append([['nmx2', None], ['no2', None], ['sff1', None]])
 
         for inst in self.cell.getInstances():
-            if ALU16.match_instance(datapath_insts, 'nmx2', 'i0', inst): continue
-            if ALU16.match_instance(datapath_insts, 'no2', 'nq', inst): continue
-            if ALU16.match_instance(datapath_insts, 'sff1', 'i', inst): continue
+            if (ALU16.match_instance(datapath_insts, 'nmx2', 'i0', inst) or
+                ALU16.match_instance(datapath_insts, 'no2', 'nq', inst) or
+                ALU16.match_instance(datapath_insts, 'sff1', 'i', inst)):
+                continue
 
         # place to right of add
         add, sub = self.submodules