TODO mention OP_MTMSR/OP_MFMSR

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 690f60c016464a2969de1565740cd6e9890bbc75..105060c71282662fab6221899bf400838ccd7706 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -1,3 +1,7 @@
+"""Trap Pipeline
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=325
+"""
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
 from nmutil.pipemodbase import PipeModBase
@@ -83,6 +87,9 @@ class TrapMainStage(PipeModBase):
                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
                     comb += self.o.srr0.ok.eq(1)
 
+            # XXX TODO, needs the lines adding to the CSV files first
+            #with m.Case(InternalOp.OP_MTMSR):
+            #with m.Case(InternalOp.OP_MFMSR):
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m