port minerva cache fixes

commit 3a0158919144757a2b369c9b750c72339e912f1d
Author: Jean-François Nguyen <jf@lambdaconcept.com>
Date:   Wed Sep 11 01:34:46 2019 +0200

    fetch,loadstore: Fix `{f,m}_busy` signal in case of a cache miss.

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index b7cdad11bf3528c848f2a10ce62918f6933fec5c..04e1f58d51664dad25a8e74ad1e4c4638c922e29 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -178,7 +178,7 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable):
             ]
         with m.Elif(f_icache_select):
             m.d.comb += [
-                self.f_busy_o.eq(icache.s2_re & icache.s2_miss),
+                self.f_busy_o.eq(icache.s2_miss),
                 self.f_instr_o.eq(icache.s2_rdata)
             ]
         with m.Else():

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index a4d76d1972359d5edcbfbe4c720febcb5eb21d54..499daf216857f601e983bad8ca1b5242bcdddde8 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -257,9 +257,9 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                 self.m_busy_o.eq(0),
                 self.m_ld_data_o.eq(0)
             ]
-        with m.Elif(m_dcache_select):
+        with m.Elif(self.m_load & m_dcache_select):
             m.d.comb += [
-                self.m_busy_o.eq(dcache.s2_re & dcache.s2_miss),
+                self.m_busy_o.eq(dcache.s2_miss),
                 self.m_ld_data_o.eq(dcache.s2_rdata)
             ]
         with m.Else():