split out TLBRecord, correct number of valid bits

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index d477d3408480c91f909913c9d189f05a351b9b3f..d337ffc80e49f2a8c6cd119c0c82f1119ee6cbed 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -195,13 +195,19 @@ def TLBTagEAArray():
     return Array(Signal(TLB_EA_TAG_BITS, name="tlbtagea%d" % x) \
                 for x in range (TLB_NUM_WAYS))
 
-def TLBArray():
+def TLBRecord(name):
     tlb_layout = [('valid', 1),
                   ('tag', TLB_TAG_WAY_BITS),
                   ('pte', TLB_PTE_WAY_BITS)
                  ]
-    return Array(Record(tlb_layout, name="tlb%d" % x) \
-                        for x in range(TLB_SET_SIZE))
+    return Record(tlb_layout, name=name)
+
+def TLBArray():
+    tlb_layout = [('valid', TLB_NUM_WAYS),
+                  ('tag', TLB_TAG_WAY_BITS),
+                  ('pte', TLB_PTE_WAY_BITS)
+                 ]
+    return Array(TLBRecord(name="tlb%d" % x) for x in range(TLB_SET_SIZE))
 
 def HitWaySet():
     return Array(Signal(WAY_BITS, name="hitway_%d" % x) \