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add coresync_clk to list of HTree
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:09:54 +0000 (11:09 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:09:54 +0000 (11:09 +0000)
experiments10_verilog/doDesign.py patch | blob | history

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index f7ee17d861c756505f1bf0c90beda9d3f3ea7aae..74a5be1d645bc188ed2de6f90fcbe297b4033ea5 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -85,6 +85,7 @@ def scriptMain ( **kw ):
         adderConf.chipConf.name = 'chip'
         #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
         adderConf.chipConf.ioPadGauge = 'niolib'
+        adderConf.useHTree('coresync_clk')
         adderConf.useHTree('jtag_tck_from_pad')
         adderConf.useHTree('sys_clk_from_pad')
         adderConf.coreSize = ( l(coreSize), l(coreSize) )