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syntax error
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Jul 2020 13:58:30 +0000 (14:58 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Jul 2020 22:17:51 +0000 (23:17 +0100)
src/soc/fu/trap/main_stage.py patch | blob | history

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 0adb2b0cde5c22e64350ed1beffea8655c8481a2..5eeddd5b31c8d6e49e3a0ecc79520c4c0c8726c4 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -212,7 +212,7 @@ class TrapMainStage(PipeModBase):
 
                 # don't understand but it's in the spec.  again: bits 32-34
                 # are copied from srr1_i and need *restoring* to msr_i
-                bits = range(63-31:63-29+1) # bits 29, 30, 31 (Power notation)
+                bits = range(63-31,63-29+1) # bits 29, 30, 31 (Power notation)
                 with m.If((msr_i[bits] == Const(0b010, 3)) &
                           (srr1_i[bits] == Const(0b000, 3))):
                     comb += msr_o.data[bits].eq(msr_i[bits])