annoying syntax error

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index 1c7fcd75246a27dfc8f56e1a13e43065add0d90a..41183b5bc43a4eecce857e4b9289a273de124c29 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -118,9 +118,9 @@ class LogicalMainStage(PipeModBase):
                 comb += a32.eq(a[0:32])
 
                 with m.If(op.is_32bit):
-                    comb += cntz_i.eq(Mux(count_right, a32[::-1], a32)
+                    comb += cntz_i.eq(Mux(count_right, a32[::-1], a32))
                 with m.Else():
-                    comb += cntz_i.eq(Mux(count_right, a[::-1], a)
+                    comb += cntz_i.eq(Mux(count_right, a[::-1], a))
 
                 m.submodules.clz = clz = CLZ(64)
                 comb += clz.sig_in.eq(cntz_i)