freedreno/regs: update UBWC related bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 3f482edca4a07fd30ea3a054c7036a6f81ac7fbe..fe5b6adc37ba7fe11a0f3d8f159a929558f3faf0 100644 (file)
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -3294,7 +3294,12 @@ to upconvert to 32b float internally?
                 -->
                <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
                <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
-               <bitfield name="UNK27" pos="27" type="boolean"/>
+               <!--
+               by default levels with w < 16 are linear
+               TILE_ALL makes all levels have tiling
+               seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
+                -->
+               <bitfield name="TILE_ALL" pos="27" type="boolean"/>
                <bitfield name="FLAG" pos="28" type="boolean"/>
        </reg32>
        <reg32 offset="4" name="4">
@@ -3315,11 +3320,10 @@ to upconvert to 32b float internally?
                <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
        </reg32>
        <reg32 offset="10" name="10">
-               <!--
-               I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
-               don't seem to be particularly sensible... or needed for UBWC to work
-                -->
                <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
+               <!-- log2 size of the first level, required for mipmapping -->
+               <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
+               <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
        </reg32>
        <reg32 offset="11" name="11"/>
        <reg32 offset="12" name="12"/>

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
index 3b476440856fabc7e449216727c42c460edde8bb..b6d3837994586d4082ad077f6a263b293d974d5a 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
@@ -183,7 +183,7 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img)
                A6XX_TEX_CONST_2_TYPE(img->type) |
                A6XX_TEX_CONST_2_PITCH(img->pitch));
        OUT_RING(ring, A6XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch) |
-               COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
+               COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL));
        if (img->bo) {
                OUT_RELOC(ring, img->bo, img->offset,
                                (uint64_t)A6XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0);

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
index 5df197c62c9dcbb035cd4a88c03189f87736aeb7..6ef7b16ab87a90906574d3dfcfd637a451106cf2 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
@@ -318,7 +318,7 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
        }
 
        if (so->ubwc_enabled) {
-               so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27;
+               so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL;
        }
 
        return &so->base;