move alu_hier to own directory

diff --git a/Makefile b/Makefile
deleted file mode 100755 (executable)
index 2a56df5..0000000
--- a/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
-
-        LOGICAL_SYNTHESIS = Yosys
-       PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
-#           YOSYS_FLATTEN = Yes
-            USE_CLOCKTREE = Yes
-                USE_DEBUG = No
-                 USE_KITE = No
-
-                 NETLISTS = $(shell cat nets.txt)
-
-
- include ./mk/design-flow.mk
-
-
-blif:      alu_hier.blif
-vst:       alu_hier.vst
-layout:    alu_hier_cts_r.ap
-gds:       alu_hier_cts_r.gds
-
-lvx:       lvx-alu_hier_cts_r
-druc:      druc-alu_hier_cts_r
-view:      cgt-alu_hier_cts_r

diff --git a/coriolis2/__init__.py b/coriolis2/__init__.py
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/coriolis2/katana.py b/coriolis2/katana.py
deleted file mode 100644 (file)
index 442b2fc..0000000
--- a/coriolis2/katana.py
+++ /dev/null
@@ -1,12 +0,0 @@
-
-from Hurricane import DebugSession
-
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
-#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )

diff --git a/coriolis2/settings.py b/coriolis2/settings.py
deleted file mode 100644 (file)
index 95cc039..0000000
--- a/coriolis2/settings.py
+++ /dev/null
@@ -1,56 +0,0 @@
-# -*- Mode:Python -*-
-
-import os
-import Cfg
-import CRL
-import Viewer
-#import node180.scn6m_deep_09
-import symbolic.cmos
-from   helpers       import l, u, n
-
-
-Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
-
-
-Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
- 
-Cfg.getParamBool      ( 'misc.catchCore'              ).setBool      ( False   )
-Cfg.getParamBool      ( 'misc.info'                   ).setBool      ( False   )
-Cfg.getParamBool      ( 'misc.paranoid'               ).setBool      ( False   )
-Cfg.getParamBool      ( 'misc.bug'                    ).setBool      ( False   )
-Cfg.getParamBool      ( 'misc.logMode'                ).setBool      ( True   )
-Cfg.getParamBool      ( 'misc.verboseLevel1'          ).setBool      ( True    )
-Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
-Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
-Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
-Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
-Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 20.0    )
-Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
-Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
-Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )
-Cfg.getParamInt       ( 'anabatic.edgeWidth'          ).setInt       ( 8       )
-Cfg.getParamString    ( 'anabatic.topRoutingLayer'    ).setString    ( 'METAL5')
-Cfg.getParamInt       ( 'katana.eventsLimit'          ).setInt       ( 1000000 )
-Cfg.getParamInt       ( 'katana.hTracksReservedLocal' ).setInt       ( 7       )
-Cfg.getParamInt       ( 'katana.vTracksReservedLocal' ).setInt       ( 6       )
-#Cfg.getParamInt       ( 'clockTree.minimumSide'       ).setInt       ( l(1000) )
-
-Cfg.Configuration.popDefaultPriority()
-
-#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
-if os.environ.has_key('CELLS_TOP'):
-  cellsTop = os.environ['CELLS_TOP']
-else:
-  cellsTop = '../../../cells'
-
-af  = CRL.AllianceFramework.get()
-env = af.getEnvironment()
-env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
-env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
-env.setCLOCK( '^clk$|m_clock' )
-env.setPOWER( 'vdd' )
-env.setGROUND( 'vss' )
-
-
-print 'Successfully read user configuration'
-

diff --git a/examples/alu_hier.py b/examples/alu_hier.py
deleted file mode 100644 (file)
index b42fb1d..0000000
--- a/examples/alu_hier.py
+++ /dev/null
@@ -1,68 +0,0 @@
-from nmigen import *
-from nmigen.cli import rtlil
-
-
-class Adder(Elaboratable):
-    def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.o.eq(self.a + self.b)
-        return m
-
-
-class Subtractor(Elaboratable):
-    def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.o.eq(self.a - self.b)
-        return m
-
-
-class ALU(Elaboratable):
-    def __init__(self, width):
-        self.op  = Signal()
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-        self.add = Adder(width)
-        self.sub = Subtractor(width)
-
-    def elaborate(self, platform):
-
-        m = Module()
-        #m.domains.sync = ClockDomain()
-        #m.d.comb += ClockSignal().eq(self.m_clock)
-
-        m.submodules.add = self.add
-        m.submodules.sub = self.sub
-        m.d.comb += [
-            self.add.a.eq(self.a),
-            self.sub.a.eq(self.a),
-            self.add.b.eq(self.b),
-            self.sub.b.eq(self.b),
-        ]
-        with m.If(self.op):
-            m.d.sync += self.o.eq(self.sub.o)
-        with m.Else():
-            m.d.sync += self.o.eq(self.add.o)
-        return m
-
-
-def create_ilang(dut, ports, test_name):
-    vl = rtlil.convert(dut, name=test_name, ports=ports)
-    with open("%s.il" % test_name, "w") as f:
-        f.write(vl)
-
-if __name__ == "__main__":
-    alu = ALU(width=16)
-    create_ilang(alu, [#alu.m_clock, alu.p_reset,
-                       alu.op, alu.a, alu.b, alu.o], "alu_hier")

diff --git a/experiments/Makefile b/experiments/Makefile
new file mode 100755 (executable)
index 0000000..2a56df5
--- /dev/null
+++ b/experiments/Makefile
@@ -0,0 +1,25 @@
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = sxlib
+
+#           YOSYS_FLATTEN = Yes
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+
+                 NETLISTS = $(shell cat nets.txt)
+
+
+ include ./mk/design-flow.mk
+
+
+blif:      alu_hier.blif
+vst:       alu_hier.vst
+layout:    alu_hier_cts_r.ap
+gds:       alu_hier_cts_r.gds
+
+lvx:       lvx-alu_hier_cts_r
+druc:      druc-alu_hier_cts_r
+view:      cgt-alu_hier_cts_r

diff --git a/experiments/alu_hier.py b/experiments/alu_hier.py
new file mode 100644 (file)
index 0000000..b42fb1d
--- /dev/null
+++ b/experiments/alu_hier.py
@@ -0,0 +1,68 @@
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class Adder(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.o.eq(self.a + self.b)
+        return m
+
+
+class Subtractor(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.o.eq(self.a - self.b)
+        return m
+
+
+class ALU(Elaboratable):
+    def __init__(self, width):
+        self.op  = Signal()
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+        self.add = Adder(width)
+        self.sub = Subtractor(width)
+
+    def elaborate(self, platform):
+
+        m = Module()
+        #m.domains.sync = ClockDomain()
+        #m.d.comb += ClockSignal().eq(self.m_clock)
+
+        m.submodules.add = self.add
+        m.submodules.sub = self.sub
+        m.d.comb += [
+            self.add.a.eq(self.a),
+            self.sub.a.eq(self.a),
+            self.add.b.eq(self.b),
+            self.sub.b.eq(self.b),
+        ]
+        with m.If(self.op):
+            m.d.sync += self.o.eq(self.sub.o)
+        with m.Else():
+            m.d.sync += self.o.eq(self.add.o)
+        return m
+
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+if __name__ == "__main__":
+    alu = ALU(width=16)
+    create_ilang(alu, [#alu.m_clock, alu.p_reset,
+                       alu.op, alu.a, alu.b, alu.o], "alu_hier")

diff --git a/experiments/coriolis2/__init__.py b/experiments/coriolis2/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/experiments/coriolis2/katana.py b/experiments/coriolis2/katana.py
new file mode 100644 (file)
index 0000000..442b2fc
--- /dev/null
+++ b/experiments/coriolis2/katana.py
@@ -0,0 +1,12 @@
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )

diff --git a/experiments/coriolis2/settings.py b/experiments/coriolis2/settings.py
new file mode 100644 (file)
index 0000000..95cc039
--- /dev/null
+++ b/experiments/coriolis2/settings.py
@@ -0,0 +1,56 @@
+# -*- Mode:Python -*-
+
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos
+from   helpers       import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+ 
+Cfg.getParamBool      ( 'misc.catchCore'              ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.info'                   ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.paranoid'               ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.bug'                    ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.logMode'                ).setBool      ( True   )
+Cfg.getParamBool      ( 'misc.verboseLevel1'          ).setBool      ( True    )
+Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
+Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
+Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
+Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
+Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 20.0    )
+Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
+Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
+Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )
+Cfg.getParamInt       ( 'anabatic.edgeWidth'          ).setInt       ( 8       )
+Cfg.getParamString    ( 'anabatic.topRoutingLayer'    ).setString    ( 'METAL5')
+Cfg.getParamInt       ( 'katana.eventsLimit'          ).setInt       ( 1000000 )
+Cfg.getParamInt       ( 'katana.hTracksReservedLocal' ).setInt       ( 7       )
+Cfg.getParamInt       ( 'katana.vTracksReservedLocal' ).setInt       ( 6       )
+#Cfg.getParamInt       ( 'clockTree.minimumSide'       ).setInt       ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
+if os.environ.has_key('CELLS_TOP'):
+  cellsTop = os.environ['CELLS_TOP']
+else:
+  cellsTop = '../../../cells'
+
+af  = CRL.AllianceFramework.get()
+env = af.getEnvironment()
+env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
+env.setCLOCK( '^clk$|m_clock' )
+env.setPOWER( 'vdd' )
+env.setGROUND( 'vss' )
+
+
+print 'Successfully read user configuration'
+

diff --git a/experiments/nets.txt b/experiments/nets.txt
new file mode 100644 (file)
index 0000000..320e403
--- /dev/null
+++ b/experiments/nets.txt
@@ -0,0 +1 @@
+alu_hier add sub

diff --git a/nets.txt b/nets.txt
deleted file mode 100644 (file)
index 320e403..0000000
--- a/nets.txt
+++ /dev/null
@@ -1 +0,0 @@
-alu_hier add sub