xdr=4 missing on ddr3 platform request for VERSA_ECP5

diff --git a/src/ls2.py b/src/ls2.py
index dcdc0de38a61335c2ec7f5a254507c2a9f361fc4..4197bec85b68b9aafefde98767e63a310195d4db 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -357,7 +357,8 @@ if __name__ == "__main__":
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"clk":4, "a":4, "ba":4, "clk_en":4,
-                                         "odt":4, "ras":4, "cas":4, "we":4})
+                                         "odt":4, "ras":4, "cas":4, "we":4,
+                                         "cs": 4})
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,