product in multiply, not tot (was from add)

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 65b74bff25c84a953c76dd581a03c111112b2f8b..4e136f17a0de1b51effa0b926eeebaf14afde1cd 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -24,7 +24,8 @@ class FPMUL(FPBase):
         b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
-        tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
+        mw = (self.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        product = Signal(mw)
 
         of = Overflow()