get issue logic working for issue unit array

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 3d360956d88ae8e64137b7b38564c8a435cb551b..9fcdfb07f69fd1fd5422593220c6f9d8ef612343 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -349,7 +349,7 @@ class Scoreboard(Elaboratable):
         # INT/FP Issue Unit
         regdecode = RegDecode(self.n_regs)
         m.submodules.regdecode = regdecode
-        aluissue = IssueUnitGroup(n_intfus)
+        aluissue = IssueUnitGroup(4)
         brissue = IssueUnitGroup(1)
         issueunit = IssueUnitArray([aluissue, brissue])
         m.submodules.issueunit = issueunit
@@ -795,7 +795,7 @@ def scoreboard_sim(dut, alusim):
 
     seed(0)
 
-    for i in range(1):
+    for i in range(20):
 
         # set random values in the registers
         for i in range(1, dut.n_regs):
@@ -807,12 +807,19 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
+        if True:
+            instrs = create_random_ops(dut, 10, True, 3)
+
         if False:
-            instrs = create_random_ops(dut, 10, True, 4)
+            instrs.append( (4, 3, 5, 1, (0, 0)) )
+            instrs.append( (5, 2, 3, 4, (0, 0)) )
 
-        if True:
+        if False:
             instrs.append((2, 3, 3, 0, (0, 0)))
-            instrs.append((5, 4, 4, 1, (0, 0)))
+            instrs.append((5, 3, 3, 1, (0, 0)))
+            instrs.append((3, 5, 5, 2, (0, 0)))
+            instrs.append((5, 3, 3, 3, (0, 0)))
+            instrs.append((3, 5, 5, 0, (0, 0)))
 
         if False:
             instrs.append((5, 6, 2, 1))

diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py
index 94963cdb842928cdeef529f4b630736f3421c481..fb7578d9732d8afa0a2f8a6dd8e01a41be9b4662 100644 (file)
--- a/src/scoreboard/issue_unit.py
+++ b/src/scoreboard/issue_unit.py
@@ -101,17 +101,16 @@ class IssueUnitGroup(Elaboratable):
 
         # temporaries
         allissue = Signal(self.n_insns, reset_less=True)
-        all1 = Const(-1, self.n_insns)
 
         m.d.comb += allissue.eq(Repl(self.insn_i, self.n_insns))
         # Pick one (and only one) of the units to proceed in this cycle
         m.d.comb += pick.i.eq(~self.busy_i & allissue)
 
         # "Safe to issue" condition is basically when all units are not busy
-        m.d.comb += self.busy_o.eq((self.busy_i == all1))
+        m.d.comb += self.busy_o.eq(~((~self.busy_i).bool()))
 
         # Picker only raises one signal, therefore it's also the fn_issue
-        m.d.comb += self.fn_issue_o.eq(pick.o)
+        m.d.comb += self.fn_issue_o.eq(pick.o & Repl(~self.busy_o, self.n_insns))
 
         return m
 
@@ -151,9 +150,9 @@ class IssueUnitArray(Elaboratable):
         fn_issue_o = []
         for u in self.units:
             busy_i.append(u.busy_i)
-            g_issue_o.append(~u.busy_o)
+            g_issue_o.append(u.busy_o)
             fn_issue_o.append(u.fn_issue_o)
-        m.d.comb += self.issue_o.eq(Cat(*g_issue_o).bool())
+        m.d.comb += self.issue_o.eq(~(Cat(*g_issue_o).bool()))
         m.d.comb += self.fn_issue_o.eq(Cat(*fn_issue_o))
         m.d.comb += Cat(*busy_i).eq(self.busy_i)