up arty a7 frequency to 40 mhz

diff --git a/src/ls2.py b/src/ls2.py
index e4589897f192cc57ecb8d124c964247c5b204d45..7d79c245edd4b06c4e7fe9ed90537e4dfbe3ae3d 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -589,7 +589,7 @@ def build_platform(fpga, firmware):
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
-        clk_freq = 25.0e6
+        clk_freq = 40.0e6
 
     # select a firmware address
     fw_addr = None