mmu.py remove class AddrShifter

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index cf54b7a7c9ed0b67c6a959579377c9f8fbcb2465..a1d848dd970a80d70a2179bba051945495d02e43 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -227,98 +227,6 @@ def elaborate(self, platform):
         sync += r.eq(rin)
 # end process;
 
-# -- Shift address bits 61--12 right by 0--47 bits and
-# -- supply the least significant 16 bits of the result.
-# -- addrshifter: process(all)
-# Shift address bits 61--12 right by 0--47 bits and
-# supply the least significant 16 bits of the result.
-class AddrShifter(Elaboratable, MMU):
-    def __init__(self):
-#       variable sh1 : std_ulogic_vector(30 downto 0);
-#       variable sh2 : std_ulogic_vector(18 downto 0);
-#       variable result : std_ulogic_vector(15 downto 0);
-        super().__init__()
-        self.sh1 = Signal(31)
-        self.sh2 = Signal(19)
-        self.result = Signal(16)
-
-#   begin
-    def elaborate(self, platform):
-
-        m = Module()
-
-        comb = m.d.comb
-        sync = m.d.sync
-
-        rst = ResetSignal()
-
-        r      = self.r
-        addrsh = self.addrsh
-
-        sh1    = self.sh1
-        sh2    = self.sh2
-        result = self.result
-
-#       case r.shift(5 downto 4) is
-        with m.Switch(r.shift[4:6]):
-#           when "00" =>
-#               sh1 := r.addr(42 downto 12);
-            with m.Case(Const(0b00, 2)):
-                comb += sh1.eq(r.addr[12:43])
-#           when "01" =>
-#               sh1 := r.addr(58 downto 28);
-            with m.Case(Const(0b01, 2)):
-                comb += sh1.eq(r.addr[28:59])
-#           when others =>
-#               sh1 := "0000000000000" & r.addr(61 downto 44);
-            with m.Default():
-                comb += sh1.eq(Cat(r.addr[44:62],
-                               Const(0b0000000000000, 13))
-#       end case;
-
-#       case r.shift(3 downto 2) is
-        with m.Switch(r.shift[2:4]):
-#           when "00" =>
-#               sh2 := sh1(18 downto 0);
-            with m.Case(Const(0b00, 2)):
-                comb += sh2.eq(sh1[0:19])
-#           when "01" =>
-#               sh2 := sh1(22 downto 4);
-            with m.Case(Const(0b01, 2)):
-                comb += sh2.eq(sh1[4:23])
-#           when "10" =>
-#               sh2 := sh1(26 downto 8);
-            with m.Case(Const(0b10, 2)):
-                comb += sh2.eq(sh1[8:27])
-#           when others =>
-#               sh2 := sh1(30 downto 12);
-            with m.Default():
-                comb += sh2.eq(sh1[12:31])
-#       end case;
-
-#       case r.shift(1 downto 0) is
-        with m.Switch(r.shift[0:2]):
-#           when "00" =>
-#               result := sh2(15 downto 0);
-            with m.Case(Const(0b00, 2)):
-                comb += result.eq(sh1[0:16])
-#           when "01" =>
-#               result := sh2(16 downto 1);
-            with m.Case(Const(0b01, 2)):
-                comb += result.eq(sh1[1:17])
-#           when "10" =>
-#               result := sh2(17 downto 2);
-            with m.Case(Const(0b10, 2)):
-                comb += result.eq(sh1[2:18])
-#           when others =>
-#               result := sh2(18 downto 3);
-            with m.Default():
-                comb += result.eq(sh1[3:19])
-#       end case;
-#       addrsh <= result;
-        comb += addrsh.eq(result)
-#   end process;
-
 # -- generate mask for extracting address fields for PTE address
 # -- generation
 # addrmaskgen: process(all)