set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD

disable DDR3 temporarily with a hack on versa_ecp5 platform

diff --git a/src/ls2.py b/src/ls2.py
index 291b061b8169742bd76f8dd267a472c653fb0279..22cc7e35ae3fb04d087b2f58ca1aa25e971c7dd1 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -577,7 +577,7 @@ if __name__ == "__main__":
     if fpga == 'sim':
         clk_freq = 100e6
     if fpga == 'versa_ecp5':
-        clk_freq = 55e6
+        clk_freq = 50e6 # crank right down to test hyperram
 
     # select a firmware file
     firmware = None
@@ -592,9 +592,10 @@ if __name__ == "__main__":
     else:
         uart_pins = Record([('tx', 1), ('rx', 1)], name="uart_0")
 
-    # get DDR resource pins
+    # get DDR resource pins, disable if clock frequency is below 50 mhz for now
     ddr_pins = None
-    if platform is not None and fpga in ['versa_ecp5', 'arty_a7', 'isim']:
+    if (clk_freq > 50e6 and platform is not None and
+        fpga in ['versa_ecp5', 'arty_a7', 'isim']):
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"rst": 4, "clk":4, "a":4,
@@ -622,7 +623,7 @@ if __name__ == "__main__":
         hyperram_ios = HyperRAMResource(0, cs_n="B13",
                                         dq="E14 C10 B10 E12 D12 A9 D11 D14",
                                         rwds="C14", rst_n="E13", ck_p="D13",
-                                        attrs=Attrs(IOSTANDARD="LVCMOS33"))
+                                        attrs=Attrs(IO_TYPE="LVCMOS33"))
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")
     else: