add Makefile to generate Cam.v verilog

diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py
index bea7ce5467161beb9da40296599f4525581149e0..62b5462a138adc5825dd65fee9066789db981b03 100644 (file)
--- a/TLB/src/Cam.py
+++ b/TLB/src/Cam.py
@@ -1,6 +1,7 @@
 from nmigen import Array, Module, Signal
 from nmigen.lib.coding import Encoder, Decoder
 from nmigen.compat.fhdl.structure import ClockDomain
+from nmigen.cli import main #, verilog
 
 from CamEntry import CamEntry
 
@@ -107,3 +108,10 @@ class Cam():
             m.d.comb += self.data_hit.eq(0)
 
         return m
+
+if __name__ == '__main__':
+    cam = Cam(4, 4, 4)
+    main(cam, ports=[cam.command, cam.address,
+                     cam.key_in, cam.data_in,
+                     cam.data_hit, cam.data_out])
+

diff --git a/TLB/src/Makefile b/TLB/src/Makefile
new file mode 100644 (file)
index 0000000..1eb67ac
--- /dev/null
+++ b/TLB/src/Makefile
@@ -0,0 +1,2 @@
+verilog:
+       python3 Cam.py generate -t v > Cam.v