whoops tlb_valids in ICache is a combinatorial-get/set

set SRLatch sync=False

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 20853127d21711cb3558675491199c47be8bea64..2f0af7a28b4e9e1ea184a2d79d892ad728e36b90 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -801,7 +801,7 @@ class ICache(FetchUnitInterface, Elaboratable):
 
         # TLB Array
         itlb            = TLBArray()
-        vec = SRLatch(sync=True, llen=TLB_SIZE, name="tlbvalids")
+        vec = SRLatch(sync=False, llen=TLB_SIZE, name="tlbvalids")
         m.submodules.itlb_valids = itlb_valid = vec
 
         # TODO to be passed to nmigen as ram attributes