add TODO comment, bug #71, replace PLRU with LFSR

diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index 20957b7874f465500c24db284b1ba39f6ba06ed8..d2aa6f47e4b62baa0129b53ee891a4330794a491 100644 (file)
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -7,6 +7,10 @@ from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 
 from AddressEncoder import AddressEncoder
+
+# TODO: use a LFSR that advances continuously and picking the bottom
+# few bits from it to select which cache line to replace, instead of PLRU
+# http://bugs.libre-riscv.org/show_bug.cgi?id=71
 from plru import PLRU
 
 SA_NA = "00" # no action (none)