remove sync (not needed)

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
index cf52529395d07d1edd50b1334700c0dfb7468322..0492a5d7a87422087f968d56b1c5d2a0f66153d1 100644 (file)
--- a/src/soc/regfile/virtual_port.py
+++ b/src/soc/regfile/virtual_port.py
@@ -37,7 +37,7 @@ class VirtualRegPort(RegFileArray):
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
-        comb, sync = m.d.comb, m.d.sync
+        comb = m.d.comb
 
         # connect up: detect if read is requested on large (full) port
         # nothing fancy needed because reads are same-cycle