take last bit of a1 mantissa as potential sticky, not last bit of z

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 129f4de84cd6c916ed1fafe3e1f303f7dc1a475e..787a4bbcd3db76766acd0622f6ab826747633b0a 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -82,12 +82,6 @@ class FPCVTSpecialCasesMod(Elaboratable):
         m.d.comb += exp_sub_n126.eq(a1.e - N126)
         m.d.comb += exp_gt127.eq(a1.e > P127)
 
-        # overflow
-        m.d.comb += self.o.of.guard.eq(a1.m[-self.o.z.rmw-2])
-        m.d.comb += self.o.of.round_bit.eq(a1.m[-self.o.z.rmw-3])
-        m.d.comb += self.o.of.sticky.eq(a1.m[:-self.o.z.rmw-1] != 0)
-        m.d.comb += self.o.of.m0.eq(self.o.z.m[0])
-
         # if a zero, return zero (signed)
         with m.If(a1.exp_n127):
             m.d.comb += self.o.z.zero(a1.s)
@@ -95,6 +89,11 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # if a range outside z's min range (-126)
         with m.Elif(exp_sub_n126 < 0):
+            m.d.comb += self.o.of.guard.eq(a1.m[-self.o.z.rmw-2])
+            m.d.comb += self.o.of.round_bit.eq(a1.m[-self.o.z.rmw-3])
+            m.d.comb += self.o.of.sticky.eq(a1.m[:-self.o.z.rmw-1] != 0)
+            m.d.comb += self.o.of.m0.eq(self.o.z.m[0])
+
             m.d.comb += self.o.z.s.eq(a1.s)
             m.d.comb += self.o.z.e.eq(a1.e)
             m.d.comb += self.o.z.m.eq(a1.m[-self.o.z.rmw-1:])
@@ -118,11 +117,19 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # ok after all that, anything else should fit fine (whew)
         with m.Else():
+            me = a1.rmw
+            ms = a1.rmw - self.o.z.rmw
+            print ("ms-me", ms, me)
+            m.d.comb += self.o.of.guard.eq(a1.m[ms-1])
+            m.d.comb += self.o.of.round_bit.eq(a1.m[ms-2])
+            m.d.comb += self.o.of.sticky.eq(a1.m[:ms-2].bool())
+            m.d.comb += self.o.of.m0.eq(a1.m[ms]) # last bit of a1 NOT z
+
             # XXX TODO: this is basically duplicating FPRoundMod. hmmm...
             print ("alen", a1.e_start, z1.fp.N126, N126)
             print ("m1", self.o.z.rmw, a1.m[-self.o.z.rmw-1:])
             mo = Signal(self.o.z.m_width-1)
-            m.d.comb += mo.eq(a1.m[-self.o.z.rmw-1:])
+            m.d.comb += mo.eq(a1.m[ms:me])
             with m.If(self.o.of.roundz):
                 with m.If((~mo == 0)): # all 1s
                     m.d.comb += self.o.z.create(a1.s, a1.e+1, mo+1)

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index c604de566db818a2c4a4413eac6cbe0ec2aedb45..76d52ddbfca2ef57e46eb67cecf3b8378ed33df8 100644 (file)
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -132,9 +132,11 @@ class InputTestRandom(InputTest):
                     #op1 = 0xe98646d7
                     #op1 = 0x3340f2a7
                     #op1 = 0xfff13f05
-                    #op1 = 0xc53eb000
+                    #op1 = 0x453eb000
                     #op1 = 0x3a05de50
                     #op1 = 0xc27ff989
+                    #op1 = 0x41689000
+                    #op1 = 0xbbc0edec
                     vals.append((op1,))
                 else:
                     op1 = randint(0, (1<<width)-1)