# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os)
-autoidx 15059
+autoidx 14799
attribute \src "libresoc.v:5.1-333.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21041.7-21041.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 6 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21103.7-21103.15"
wire \initial
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 33 \cr_a_ok
wire input 18 \alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 28 \cr_a
wire input 13 \br_op__lk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 20 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0"
attribute \generator "nMigen"
module \alu_cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 12 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0"
attribute \generator "nMigen"
module \alu_div0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 35 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 27 \cr_a
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26073.7-26073.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26135.7-26135.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26197.7-26197.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26259.7-26259.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26321.7-26321.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26383.7-26383.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26445.7-26445.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26507.7-26507.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26569.7-26569.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26631.7-26631.15"
wire \initial
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0"
attribute \generator "nMigen"
module \alu_logical0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0"
attribute \generator "nMigen"
module \alu_mul0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 21 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0"
attribute \generator "nMigen"
module \alu_shift_rot0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0"
attribute \generator "nMigen"
module \alu_spr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 28 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 output 16 \fast1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0"
attribute \generator "nMigen"
module \alu_trap0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 output 19 \fast1
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31347.7-31347.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31409.7-31409.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31471.7-31471.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31533.7-31533.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31595.7-31595.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31657.7-31657.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31719.7-31719.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31781.7-31781.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31843.7-31843.15"
wire \initial
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 11 \cu_busy_o
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "libresoc.v:34308.7-34308.15"
wire \initial
wire width 3 input 27 \core_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95"
wire output 2 \corebusy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 96 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182"
wire width 2 \counter
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 14 \data_i
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 24 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 22 \cr_a_ok
connect \all_rd_dly$next \all_rd
connect \all_rd \$11
end
-attribute \src "libresoc.v:50534.1-50697.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec"
-attribute \generator "nMigen"
-module \crin_svdec
- attribute \src "libresoc.v:50683.3-50694.6"
- wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:50632.3-50648.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:50649.3-50665.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:50666.3-50682.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:50535.7-50535.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:50573.3-50631.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:50683.3-50694.6"
- wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:50632.3-50648.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50649.3-50665.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:50666.3-50682.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:50573.3-50631.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:50632.3-50648.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:50649.3-50665.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:50666.3-50682.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:50573.3-50631.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:50573.3-50631.6"
- wire width 3 $3\spec[2:0]
- attribute \src "libresoc.v:50572.17-50572.121"
- wire width 7 $pos$libresoc.v:50572$3273_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- wire width 7 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 input 4 \cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 output 5 \cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 3 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 2 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 1 \idx
- attribute \src "libresoc.v:50535.7-50535.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire output 6 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148"
- wire width 2 \spec_aug
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- cell $pos $pos$libresoc.v:50572$3273
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
- connect \A { 2'00 \spec_aug \cr_in }
- connect \Y $pos$libresoc.v:50572$3273_Y
- end
- attribute \src "libresoc.v:50535.7-50535.20"
- process $proc$libresoc.v:50535$3279
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:50573.3-50631.6"
- process $proc$libresoc.v:50573$3274
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:50574.5-50574.29"
- switch \initial
- attribute \src "libresoc.v:50574.9-50574.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:50632.3-50648.6"
- process $proc$libresoc.v:50632$3275
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50633.5-50633.29"
- switch \initial
- attribute \src "libresoc.v:50633.9-50633.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:50649.3-50665.6"
- process $proc$libresoc.v:50649$3276
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:50650.5-50650.29"
- switch \initial
- attribute \src "libresoc.v:50650.9-50650.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:50666.3-50682.6"
- process $proc$libresoc.v:50666$3277
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:50667.5-50667.29"
- switch \initial
- attribute \src "libresoc.v:50667.9-50667.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:50683.3-50694.6"
- process $proc$libresoc.v:50683$3278
- assign { } { }
- assign $0\cr_out[6:0] $1\cr_out[6:0]
- attribute \src "libresoc.v:50684.5-50684.29"
- switch \initial
- attribute \src "libresoc.v:50684.9-50684.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\cr_out[6:0] \$1
- end
- sync always
- update \cr_out $0\cr_out[6:0]
- end
- connect \$1 $pos$libresoc.v:50572$3273_Y
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:50701.1-50864.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_b"
-attribute \generator "nMigen"
-module \crin_svdec_b
- attribute \src "libresoc.v:50850.3-50861.6"
- wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:50799.3-50815.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:50816.3-50832.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:50833.3-50849.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:50702.7-50702.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:50740.3-50798.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:50850.3-50861.6"
- wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:50799.3-50815.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50816.3-50832.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:50833.3-50849.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:50740.3-50798.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:50799.3-50815.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:50816.3-50832.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:50833.3-50849.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:50740.3-50798.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:50740.3-50798.6"
- wire width 3 $3\spec[2:0]
- attribute \src "libresoc.v:50739.17-50739.121"
- wire width 7 $pos$libresoc.v:50739$3280_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- wire width 7 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 input 4 \cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 output 5 \cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 3 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 2 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 1 \idx
- attribute \src "libresoc.v:50702.7-50702.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire output 6 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148"
- wire width 2 \spec_aug
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- cell $pos $pos$libresoc.v:50739$3280
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
- connect \A { 2'00 \spec_aug \cr_in }
- connect \Y $pos$libresoc.v:50739$3280_Y
- end
- attribute \src "libresoc.v:50702.7-50702.20"
- process $proc$libresoc.v:50702$3286
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:50740.3-50798.6"
- process $proc$libresoc.v:50740$3281
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:50741.5-50741.29"
- switch \initial
- attribute \src "libresoc.v:50741.9-50741.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:50799.3-50815.6"
- process $proc$libresoc.v:50799$3282
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50800.5-50800.29"
- switch \initial
- attribute \src "libresoc.v:50800.9-50800.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:50816.3-50832.6"
- process $proc$libresoc.v:50816$3283
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:50817.5-50817.29"
- switch \initial
- attribute \src "libresoc.v:50817.9-50817.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:50833.3-50849.6"
- process $proc$libresoc.v:50833$3284
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:50834.5-50834.29"
- switch \initial
- attribute \src "libresoc.v:50834.9-50834.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:50850.3-50861.6"
- process $proc$libresoc.v:50850$3285
- assign { } { }
- assign $0\cr_out[6:0] $1\cr_out[6:0]
- attribute \src "libresoc.v:50851.5-50851.29"
- switch \initial
- attribute \src "libresoc.v:50851.9-50851.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\cr_out[6:0] \$1
- end
- sync always
- update \cr_out $0\cr_out[6:0]
- end
- connect \$1 $pos$libresoc.v:50739$3280_Y
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:50868.1-51031.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_o"
-attribute \generator "nMigen"
-module \crin_svdec_o
- attribute \src "libresoc.v:51017.3-51028.6"
- wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:50966.3-50982.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:50983.3-50999.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:51000.3-51016.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:50869.7-50869.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:50907.3-50965.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:51017.3-51028.6"
- wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:50966.3-50982.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50983.3-50999.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:51000.3-51016.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:50907.3-50965.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:50966.3-50982.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:50983.3-50999.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:51000.3-51016.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:50907.3-50965.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:50907.3-50965.6"
- wire width 3 $3\spec[2:0]
- attribute \src "libresoc.v:50906.17-50906.121"
- wire width 7 $pos$libresoc.v:50906$3287_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- wire width 7 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 input 4 \cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 output 5 \cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 3 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 2 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 1 \idx
- attribute \src "libresoc.v:50869.7-50869.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire output 6 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148"
- wire width 2 \spec_aug
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- cell $pos $pos$libresoc.v:50906$3287
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
- connect \A { 2'00 \spec_aug \cr_in }
- connect \Y $pos$libresoc.v:50906$3287_Y
- end
- attribute \src "libresoc.v:50869.7-50869.20"
- process $proc$libresoc.v:50869$3293
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:50907.3-50965.6"
- process $proc$libresoc.v:50907$3288
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:50908.5-50908.29"
- switch \initial
- attribute \src "libresoc.v:50908.9-50908.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:50966.3-50982.6"
- process $proc$libresoc.v:50966$3289
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:50967.5-50967.29"
- switch \initial
- attribute \src "libresoc.v:50967.9-50967.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:50983.3-50999.6"
- process $proc$libresoc.v:50983$3290
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:50984.5-50984.29"
- switch \initial
- attribute \src "libresoc.v:50984.9-50984.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:51000.3-51016.6"
- process $proc$libresoc.v:51000$3291
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:51001.5-51001.29"
- switch \initial
- attribute \src "libresoc.v:51001.9-51001.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:51017.3-51028.6"
- process $proc$libresoc.v:51017$3292
- assign { } { }
- assign $0\cr_out[6:0] $1\cr_out[6:0]
- attribute \src "libresoc.v:51018.5-51018.29"
- switch \initial
- attribute \src "libresoc.v:51018.9-51018.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\cr_out[6:0] \$1
- end
- sync always
- update \cr_out $0\cr_out[6:0]
- end
- connect \$1 $pos$libresoc.v:50906$3287_Y
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:51035.1-51198.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.crout_svdec"
-attribute \generator "nMigen"
-module \crout_svdec
- attribute \src "libresoc.v:51184.3-51195.6"
- wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:51133.3-51149.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:51150.3-51166.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:51167.3-51183.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:51036.7-51036.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:51074.3-51132.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:51184.3-51195.6"
- wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:51133.3-51149.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:51150.3-51166.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:51167.3-51183.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:51074.3-51132.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:51133.3-51149.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:51150.3-51166.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:51167.3-51183.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:51074.3-51132.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:51074.3-51132.6"
- wire width 3 $3\spec[2:0]
- attribute \src "libresoc.v:51073.17-51073.121"
- wire width 7 $pos$libresoc.v:51073$3294_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- wire width 7 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 input 4 \cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 output 5 \cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 3 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 2 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 6 \idx
- attribute \src "libresoc.v:51036.7-51036.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire output 1 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148"
- wire width 2 \spec_aug
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157"
- cell $pos $pos$libresoc.v:51073$3294
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
- connect \A { 2'00 \spec_aug \cr_in }
- connect \Y $pos$libresoc.v:51073$3294_Y
- end
- attribute \src "libresoc.v:51036.7-51036.20"
- process $proc$libresoc.v:51036$3300
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:51074.3-51132.6"
- process $proc$libresoc.v:51074$3295
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:51075.5-51075.29"
- switch \initial
- attribute \src "libresoc.v:51075.9-51075.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:51133.3-51149.6"
- process $proc$libresoc.v:51133$3296
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:51134.5-51134.29"
- switch \initial
- attribute \src "libresoc.v:51134.9-51134.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:51150.3-51166.6"
- process $proc$libresoc.v:51150$3297
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:51151.5-51151.29"
- switch \initial
- attribute \src "libresoc.v:51151.9-51151.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:51167.3-51183.6"
- process $proc$libresoc.v:51167$3298
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:51168.5-51168.29"
- switch \initial
- attribute \src "libresoc.v:51168.9-51168.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:51184.3-51195.6"
- process $proc$libresoc.v:51184$3299
- assign { } { }
- assign $0\cr_out[6:0] $1\cr_out[6:0]
- attribute \src "libresoc.v:51185.5-51185.29"
- switch \initial
- attribute \src "libresoc.v:51185.9-51185.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\cr_out[6:0] \$1
- end
- sync always
- update \cr_out $0\cr_out[6:0]
- end
- connect \$1 $pos$libresoc.v:51073$3294_Y
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:51202.1-51251.10"
+attribute \src "libresoc.v:50534.1-50583.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l"
attribute \generator "nMigen"
module \cyc_l
- attribute \src "libresoc.v:51203.7-51203.20"
+ attribute \src "libresoc.v:50535.7-50535.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51239.3-51247.6"
- wire $0\q_int$next[0:0]$3308
- attribute \src "libresoc.v:51237.3-51238.27"
+ attribute \src "libresoc.v:50571.3-50579.6"
+ wire $0\q_int$next[0:0]$3280
+ attribute \src "libresoc.v:50569.3-50570.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:51239.3-51247.6"
- wire $1\q_int$next[0:0]$3309
- attribute \src "libresoc.v:51221.7-51221.19"
+ attribute \src "libresoc.v:50571.3-50579.6"
+ wire $1\q_int$next[0:0]$3281
+ attribute \src "libresoc.v:50553.7-50553.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:51234.17-51234.96"
- wire $and$libresoc.v:51234$3303_Y
- attribute \src "libresoc.v:51233.17-51233.92"
- wire $not$libresoc.v:51233$3302_Y
- attribute \src "libresoc.v:51236.17-51236.92"
- wire $not$libresoc.v:51236$3305_Y
- attribute \src "libresoc.v:51232.17-51232.98"
- wire $or$libresoc.v:51232$3301_Y
- attribute \src "libresoc.v:51235.17-51235.97"
- wire $or$libresoc.v:51235$3304_Y
+ attribute \src "libresoc.v:50566.17-50566.96"
+ wire $and$libresoc.v:50566$3275_Y
+ attribute \src "libresoc.v:50565.17-50565.92"
+ wire $not$libresoc.v:50565$3274_Y
+ attribute \src "libresoc.v:50568.17-50568.92"
+ wire $not$libresoc.v:50568$3277_Y
+ attribute \src "libresoc.v:50564.17-50564.98"
+ wire $or$libresoc.v:50564$3273_Y
+ attribute \src "libresoc.v:50567.17-50567.97"
+ wire $or$libresoc.v:50567$3276_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:51203.7-51203.15"
+ attribute \src "libresoc.v:50535.7-50535.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire output 4 \q_cyc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_cyc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:51234$3303
+ cell $and $and$libresoc.v:50566$3275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:51234$3303_Y
+ connect \Y $and$libresoc.v:50566$3275_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:51233$3302
+ cell $not $not$libresoc.v:50565$3274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_cyc
- connect \Y $not$libresoc.v:51233$3302_Y
+ connect \Y $not$libresoc.v:50565$3274_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:51236$3305
+ cell $not $not$libresoc.v:50568$3277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_cyc
- connect \Y $not$libresoc.v:51236$3305_Y
+ connect \Y $not$libresoc.v:50568$3277_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:51232$3301
+ cell $or $or$libresoc.v:50564$3273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_cyc
connect \B \q_int
- connect \Y $or$libresoc.v:51232$3301_Y
+ connect \Y $or$libresoc.v:50564$3273_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:51235$3304
+ cell $or $or$libresoc.v:50567$3276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_cyc
- connect \Y $or$libresoc.v:51235$3304_Y
+ connect \Y $or$libresoc.v:50567$3276_Y
end
- attribute \src "libresoc.v:51203.7-51203.20"
- process $proc$libresoc.v:51203$3310
+ attribute \src "libresoc.v:50535.7-50535.20"
+ process $proc$libresoc.v:50535$3282
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:51221.7-51221.19"
- process $proc$libresoc.v:51221$3311
+ attribute \src "libresoc.v:50553.7-50553.19"
+ process $proc$libresoc.v:50553$3283
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:51237.3-51238.27"
- process $proc$libresoc.v:51237$3306
+ attribute \src "libresoc.v:50569.3-50570.27"
+ process $proc$libresoc.v:50569$3278
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:51239.3-51247.6"
- process $proc$libresoc.v:51239$3307
+ attribute \src "libresoc.v:50571.3-50579.6"
+ process $proc$libresoc.v:50571$3279
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$3308 $1\q_int$next[0:0]$3309
- attribute \src "libresoc.v:51240.5-51240.29"
+ assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281
+ attribute \src "libresoc.v:50572.5-50572.29"
switch \initial
- attribute \src "libresoc.v:51240.9-51240.17"
+ attribute \src "libresoc.v:50572.9-50572.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$3309 1'0
+ assign $1\q_int$next[0:0]$3281 1'0
case
- assign $1\q_int$next[0:0]$3309 \$5
+ assign $1\q_int$next[0:0]$3281 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$3308
+ update \q_int$next $0\q_int$next[0:0]$3280
end
- connect \$9 $or$libresoc.v:51232$3301_Y
- connect \$1 $not$libresoc.v:51233$3302_Y
- connect \$3 $and$libresoc.v:51234$3303_Y
- connect \$5 $or$libresoc.v:51235$3304_Y
- connect \$7 $not$libresoc.v:51236$3305_Y
+ connect \$9 $or$libresoc.v:50564$3273_Y
+ connect \$1 $not$libresoc.v:50565$3274_Y
+ connect \$3 $and$libresoc.v:50566$3275_Y
+ connect \$5 $or$libresoc.v:50567$3276_Y
+ connect \$7 $not$libresoc.v:50568$3277_Y
connect \qlq_cyc \$9
connect \qn_cyc \$7
connect \q_cyc \q_int
end
-attribute \src "libresoc.v:51255.1-51969.10"
+attribute \src "libresoc.v:50587.1-51319.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dbg"
attribute \generator "nMigen"
module \dbg
- attribute \src "libresoc.v:51785.3-51794.6"
+ attribute \src "libresoc.v:51132.3-51141.6"
wire $0\d_cr_req[0:0]
- attribute \src "libresoc.v:51592.3-51601.6"
+ attribute \src "libresoc.v:50939.3-50948.6"
wire $0\d_gpr_req[0:0]
- attribute \src "libresoc.v:51795.3-51804.6"
+ attribute \src "libresoc.v:51142.3-51151.6"
wire $0\d_xer_req[0:0]
- attribute \src "libresoc.v:51574.3-51591.6"
+ attribute \src "libresoc.v:50921.3-50938.6"
wire $0\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51805.3-51835.6"
+ attribute \src "libresoc.v:51152.3-51185.6"
wire width 64 $0\dmi_dout[63:0]
- attribute \src "libresoc.v:51776.3-51784.6"
- wire $0\dmi_read_log_data$next[0:0]$3425
- attribute \src "libresoc.v:51552.3-51553.51"
+ attribute \src "libresoc.v:51123.3-51131.6"
+ wire $0\dmi_read_log_data$next[0:0]$3398
+ attribute \src "libresoc.v:50899.3-50900.51"
wire $0\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:51767.3-51775.6"
- wire $0\dmi_read_log_data_1$next[0:0]$3422
- attribute \src "libresoc.v:51554.3-51555.55"
+ attribute \src "libresoc.v:51114.3-51122.6"
+ wire $0\dmi_read_log_data_1$next[0:0]$3395
+ attribute \src "libresoc.v:50901.3-50902.55"
wire $0\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:51602.3-51610.6"
- wire $0\dmi_req_i_1$next[0:0]$3388
- attribute \src "libresoc.v:51564.3-51565.39"
+ attribute \src "libresoc.v:50949.3-50957.6"
+ wire $0\dmi_req_i_1$next[0:0]$3361
+ attribute \src "libresoc.v:50911.3-50912.39"
wire $0\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:51926.3-51959.6"
- wire $0\do_dmi_log_rd$next[0:0]$3452
- attribute \src "libresoc.v:51566.3-51567.43"
+ attribute \src "libresoc.v:51276.3-51309.6"
+ wire $0\do_dmi_log_rd$next[0:0]$3425
+ attribute \src "libresoc.v:50913.3-50914.43"
wire $0\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $0\do_icreset$next[0:0]$3445
- attribute \src "libresoc.v:51568.3-51569.37"
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $0\do_icreset$next[0:0]$3418
+ attribute \src "libresoc.v:50915.3-50916.37"
wire $0\do_icreset[0:0]
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $0\do_reset$next[0:0]$3438
- attribute \src "libresoc.v:51570.3-51571.33"
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $0\do_reset$next[0:0]$3411
+ attribute \src "libresoc.v:50917.3-50918.33"
wire $0\do_reset[0:0]
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $0\do_step$next[0:0]$3431
- attribute \src "libresoc.v:51572.3-51573.31"
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $0\do_step$next[0:0]$3404
+ attribute \src "libresoc.v:50919.3-50920.31"
wire $0\do_step[0:0]
- attribute \src "libresoc.v:51705.3-51732.6"
- wire width 7 $0\gspr_index$next[6:0]$3410
- attribute \src "libresoc.v:51558.3-51559.37"
+ attribute \src "libresoc.v:51052.3-51079.6"
+ wire width 7 $0\gspr_index$next[6:0]$3383
+ attribute \src "libresoc.v:50905.3-50906.37"
wire width 7 $0\gspr_index[6:0]
- attribute \src "libresoc.v:51256.7-51256.20"
+ attribute \src "libresoc.v:50588.7-50588.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51733.3-51766.6"
- wire width 32 $0\log_dmi_addr$next[31:0]$3416
- attribute \src "libresoc.v:51556.3-51557.41"
+ attribute \src "libresoc.v:51080.3-51113.6"
+ wire width 32 $0\log_dmi_addr$next[31:0]$3389
+ attribute \src "libresoc.v:50903.3-50904.41"
wire width 32 $0\log_dmi_addr[31:0]
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $0\stopping$next[0:0]$3401
- attribute \src "libresoc.v:51560.3-51561.33"
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $0\stopping$next[0:0]$3374
+ attribute \src "libresoc.v:50907.3-50908.33"
wire $0\stopping[0:0]
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $0\terminated$next[0:0]$3391
- attribute \src "libresoc.v:51562.3-51563.37"
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $0\terminated$next[0:0]$3364
+ attribute \src "libresoc.v:50909.3-50910.37"
wire $0\terminated[0:0]
- attribute \src "libresoc.v:51785.3-51794.6"
+ attribute \src "libresoc.v:51132.3-51141.6"
wire $1\d_cr_req[0:0]
- attribute \src "libresoc.v:51592.3-51601.6"
+ attribute \src "libresoc.v:50939.3-50948.6"
wire $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:51795.3-51804.6"
+ attribute \src "libresoc.v:51142.3-51151.6"
wire $1\d_xer_req[0:0]
- attribute \src "libresoc.v:51574.3-51591.6"
+ attribute \src "libresoc.v:50921.3-50938.6"
wire $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51805.3-51835.6"
+ attribute \src "libresoc.v:51152.3-51185.6"
wire width 64 $1\dmi_dout[63:0]
- attribute \src "libresoc.v:51776.3-51784.6"
- wire $1\dmi_read_log_data$next[0:0]$3426
- attribute \src "libresoc.v:51429.7-51429.31"
+ attribute \src "libresoc.v:51123.3-51131.6"
+ wire $1\dmi_read_log_data$next[0:0]$3399
+ attribute \src "libresoc.v:50775.7-50775.31"
wire $1\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:51767.3-51775.6"
- wire $1\dmi_read_log_data_1$next[0:0]$3423
- attribute \src "libresoc.v:51433.7-51433.33"
+ attribute \src "libresoc.v:51114.3-51122.6"
+ wire $1\dmi_read_log_data_1$next[0:0]$3396
+ attribute \src "libresoc.v:50779.7-50779.33"
wire $1\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:51602.3-51610.6"
- wire $1\dmi_req_i_1$next[0:0]$3389
- attribute \src "libresoc.v:51439.7-51439.25"
+ attribute \src "libresoc.v:50949.3-50957.6"
+ wire $1\dmi_req_i_1$next[0:0]$3362
+ attribute \src "libresoc.v:50785.7-50785.25"
wire $1\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:51926.3-51959.6"
- wire $1\do_dmi_log_rd$next[0:0]$3453
- attribute \src "libresoc.v:51445.7-51445.27"
+ attribute \src "libresoc.v:51276.3-51309.6"
+ wire $1\do_dmi_log_rd$next[0:0]$3426
+ attribute \src "libresoc.v:50791.7-50791.27"
wire $1\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $1\do_icreset$next[0:0]$3446
- attribute \src "libresoc.v:51449.7-51449.24"
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $1\do_icreset$next[0:0]$3419
+ attribute \src "libresoc.v:50795.7-50795.24"
wire $1\do_icreset[0:0]
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $1\do_reset$next[0:0]$3439
- attribute \src "libresoc.v:51453.7-51453.22"
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $1\do_reset$next[0:0]$3412
+ attribute \src "libresoc.v:50799.7-50799.22"
wire $1\do_reset[0:0]
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $1\do_step$next[0:0]$3432
- attribute \src "libresoc.v:51457.7-51457.21"
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $1\do_step$next[0:0]$3405
+ attribute \src "libresoc.v:50803.7-50803.21"
wire $1\do_step[0:0]
- attribute \src "libresoc.v:51705.3-51732.6"
- wire width 7 $1\gspr_index$next[6:0]$3411
- attribute \src "libresoc.v:51461.13-51461.31"
+ attribute \src "libresoc.v:51052.3-51079.6"
+ wire width 7 $1\gspr_index$next[6:0]$3384
+ attribute \src "libresoc.v:50807.13-50807.31"
wire width 7 $1\gspr_index[6:0]
- attribute \src "libresoc.v:51733.3-51766.6"
- wire width 32 $1\log_dmi_addr$next[31:0]$3417
- attribute \src "libresoc.v:51467.14-51467.34"
+ attribute \src "libresoc.v:51080.3-51113.6"
+ wire width 32 $1\log_dmi_addr$next[31:0]$3390
+ attribute \src "libresoc.v:50813.14-50813.34"
wire width 32 $1\log_dmi_addr[31:0]
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $1\stopping$next[0:0]$3402
- attribute \src "libresoc.v:51479.7-51479.22"
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $1\stopping$next[0:0]$3375
+ attribute \src "libresoc.v:50825.7-50825.22"
wire $1\stopping[0:0]
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $1\terminated$next[0:0]$3392
- attribute \src "libresoc.v:51485.7-51485.24"
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $1\terminated$next[0:0]$3365
+ attribute \src "libresoc.v:50831.7-50831.24"
wire $1\terminated[0:0]
- attribute \src "libresoc.v:51926.3-51959.6"
- wire $2\do_dmi_log_rd$next[0:0]$3454
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $2\do_icreset$next[0:0]$3447
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $2\do_reset$next[0:0]$3440
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $2\do_step$next[0:0]$3433
- attribute \src "libresoc.v:51705.3-51732.6"
- wire width 7 $2\gspr_index$next[6:0]$3412
- attribute \src "libresoc.v:51733.3-51766.6"
- wire width 32 $2\log_dmi_addr$next[31:0]$3418
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $2\stopping$next[0:0]$3403
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $2\terminated$next[0:0]$3393
- attribute \src "libresoc.v:51926.3-51959.6"
- wire $3\do_dmi_log_rd$next[0:0]$3455
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $3\do_icreset$next[0:0]$3448
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $3\do_reset$next[0:0]$3441
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $3\do_step$next[0:0]$3434
- attribute \src "libresoc.v:51705.3-51732.6"
- wire width 7 $3\gspr_index$next[6:0]$3413
- attribute \src "libresoc.v:51733.3-51766.6"
- wire width 32 $3\log_dmi_addr$next[31:0]$3419
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $3\stopping$next[0:0]$3404
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $3\terminated$next[0:0]$3394
- attribute \src "libresoc.v:51926.3-51959.6"
- wire $4\do_dmi_log_rd$next[0:0]$3456
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $4\do_icreset$next[0:0]$3449
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $4\do_reset$next[0:0]$3442
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $4\do_step$next[0:0]$3435
- attribute \src "libresoc.v:51705.3-51732.6"
- wire width 7 $4\gspr_index$next[6:0]$3414
- attribute \src "libresoc.v:51733.3-51766.6"
- wire width 32 $4\log_dmi_addr$next[31:0]$3420
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $4\stopping$next[0:0]$3405
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $4\terminated$next[0:0]$3395
- attribute \src "libresoc.v:51896.3-51925.6"
- wire $5\do_icreset$next[0:0]$3450
- attribute \src "libresoc.v:51866.3-51895.6"
- wire $5\do_reset$next[0:0]$3443
- attribute \src "libresoc.v:51836.3-51865.6"
- wire $5\do_step$next[0:0]$3436
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $5\stopping$next[0:0]$3406
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $5\terminated$next[0:0]$3396
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $6\stopping$next[0:0]$3407
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $6\terminated$next[0:0]$3397
- attribute \src "libresoc.v:51661.3-51704.6"
- wire $7\stopping$next[0:0]$3408
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $7\terminated$next[0:0]$3398
- attribute \src "libresoc.v:51611.3-51660.6"
- wire $8\terminated$next[0:0]$3399
- attribute \src "libresoc.v:51499.19-51499.110"
- wire width 3 $add$libresoc.v:51499$3321_Y
- attribute \src "libresoc.v:51490.17-51490.109"
- wire $and$libresoc.v:51490$3312_Y
- attribute \src "libresoc.v:51493.19-51493.103"
- wire $and$libresoc.v:51493$3315_Y
- attribute \src "libresoc.v:51495.19-51495.113"
- wire $and$libresoc.v:51495$3317_Y
- attribute \src "libresoc.v:51502.19-51502.103"
- wire $and$libresoc.v:51502$3324_Y
- attribute \src "libresoc.v:51504.19-51504.102"
- wire $and$libresoc.v:51504$3326_Y
- attribute \src "libresoc.v:51509.18-51509.101"
- wire $and$libresoc.v:51509$3331_Y
- attribute \src "libresoc.v:51511.18-51511.111"
- wire $and$libresoc.v:51511$3333_Y
- attribute \src "libresoc.v:51516.18-51516.101"
- wire $and$libresoc.v:51516$3338_Y
- attribute \src "libresoc.v:51518.18-51518.111"
- wire $and$libresoc.v:51518$3340_Y
- attribute \src "libresoc.v:51524.18-51524.101"
- wire $and$libresoc.v:51524$3346_Y
- attribute \src "libresoc.v:51526.18-51526.111"
- wire $and$libresoc.v:51526$3348_Y
- attribute \src "libresoc.v:51530.17-51530.99"
- wire $and$libresoc.v:51530$3352_Y
- attribute \src "libresoc.v:51532.18-51532.101"
- wire $and$libresoc.v:51532$3354_Y
- attribute \src "libresoc.v:51534.18-51534.111"
- wire $and$libresoc.v:51534$3356_Y
- attribute \src "libresoc.v:51539.18-51539.101"
- wire $and$libresoc.v:51539$3361_Y
- attribute \src "libresoc.v:51542.18-51542.111"
- wire $and$libresoc.v:51542$3364_Y
- attribute \src "libresoc.v:51547.18-51547.101"
- wire $and$libresoc.v:51547$3369_Y
- attribute \src "libresoc.v:51549.18-51549.111"
- wire $and$libresoc.v:51549$3371_Y
- attribute \src "libresoc.v:51491.18-51491.103"
- wire $eq$libresoc.v:51491$3313_Y
- attribute \src "libresoc.v:51496.19-51496.104"
- wire $eq$libresoc.v:51496$3318_Y
- attribute \src "libresoc.v:51497.19-51497.104"
- wire $eq$libresoc.v:51497$3319_Y
- attribute \src "libresoc.v:51498.19-51498.104"
- wire $eq$libresoc.v:51498$3320_Y
- attribute \src "libresoc.v:51500.19-51500.104"
- wire $eq$libresoc.v:51500$3322_Y
- attribute \src "libresoc.v:51501.18-51501.103"
- wire $eq$libresoc.v:51501$3323_Y
- attribute \src "libresoc.v:51505.18-51505.103"
- wire $eq$libresoc.v:51505$3327_Y
- attribute \src "libresoc.v:51506.18-51506.103"
- wire $eq$libresoc.v:51506$3328_Y
- attribute \src "libresoc.v:51512.18-51512.103"
- wire $eq$libresoc.v:51512$3334_Y
- attribute \src "libresoc.v:51513.18-51513.103"
- wire $eq$libresoc.v:51513$3335_Y
- attribute \src "libresoc.v:51514.18-51514.103"
- wire $eq$libresoc.v:51514$3336_Y
- attribute \src "libresoc.v:51520.18-51520.103"
- wire $eq$libresoc.v:51520$3342_Y
- attribute \src "libresoc.v:51521.18-51521.103"
- wire $eq$libresoc.v:51521$3343_Y
- attribute \src "libresoc.v:51522.18-51522.103"
- wire $eq$libresoc.v:51522$3344_Y
- attribute \src "libresoc.v:51527.18-51527.103"
- wire $eq$libresoc.v:51527$3349_Y
- attribute \src "libresoc.v:51528.18-51528.103"
- wire $eq$libresoc.v:51528$3350_Y
- attribute \src "libresoc.v:51529.18-51529.103"
- wire $eq$libresoc.v:51529$3351_Y
- attribute \src "libresoc.v:51535.18-51535.103"
- wire $eq$libresoc.v:51535$3357_Y
- attribute \src "libresoc.v:51536.18-51536.103"
- wire $eq$libresoc.v:51536$3358_Y
- attribute \src "libresoc.v:51537.18-51537.103"
- wire $eq$libresoc.v:51537$3359_Y
- attribute \src "libresoc.v:51543.18-51543.103"
- wire $eq$libresoc.v:51543$3365_Y
- attribute \src "libresoc.v:51544.18-51544.103"
- wire $eq$libresoc.v:51544$3366_Y
- attribute \src "libresoc.v:51545.18-51545.103"
- wire $eq$libresoc.v:51545$3367_Y
- attribute \src "libresoc.v:51550.18-51550.103"
- wire $eq$libresoc.v:51550$3372_Y
- attribute \src "libresoc.v:51551.18-51551.103"
- wire $eq$libresoc.v:51551$3373_Y
- attribute \src "libresoc.v:51492.19-51492.99"
- wire $not$libresoc.v:51492$3314_Y
- attribute \src "libresoc.v:51494.19-51494.105"
- wire $not$libresoc.v:51494$3316_Y
- attribute \src "libresoc.v:51503.19-51503.95"
- wire $not$libresoc.v:51503$3325_Y
- attribute \src "libresoc.v:51507.18-51507.98"
- wire $not$libresoc.v:51507$3329_Y
- attribute \src "libresoc.v:51510.18-51510.104"
- wire $not$libresoc.v:51510$3332_Y
- attribute \src "libresoc.v:51515.18-51515.98"
- wire $not$libresoc.v:51515$3337_Y
- attribute \src "libresoc.v:51517.18-51517.104"
- wire $not$libresoc.v:51517$3339_Y
- attribute \src "libresoc.v:51519.17-51519.97"
- wire $not$libresoc.v:51519$3341_Y
- attribute \src "libresoc.v:51523.18-51523.98"
- wire $not$libresoc.v:51523$3345_Y
- attribute \src "libresoc.v:51525.18-51525.104"
- wire $not$libresoc.v:51525$3347_Y
- attribute \src "libresoc.v:51531.18-51531.98"
- wire $not$libresoc.v:51531$3353_Y
- attribute \src "libresoc.v:51533.18-51533.104"
- wire $not$libresoc.v:51533$3355_Y
- attribute \src "libresoc.v:51538.18-51538.98"
- wire $not$libresoc.v:51538$3360_Y
- attribute \src "libresoc.v:51540.18-51540.104"
- wire $not$libresoc.v:51540$3362_Y
- attribute \src "libresoc.v:51541.17-51541.103"
- wire $not$libresoc.v:51541$3363_Y
- attribute \src "libresoc.v:51546.18-51546.98"
- wire $not$libresoc.v:51546$3368_Y
- attribute \src "libresoc.v:51548.18-51548.104"
- wire $not$libresoc.v:51548$3370_Y
- attribute \src "libresoc.v:51508.17-51508.126"
- wire width 64 $pos$libresoc.v:51508$3330_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
+ attribute \src "libresoc.v:51276.3-51309.6"
+ wire $2\do_dmi_log_rd$next[0:0]$3427
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $2\do_icreset$next[0:0]$3420
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $2\do_reset$next[0:0]$3413
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $2\do_step$next[0:0]$3406
+ attribute \src "libresoc.v:51052.3-51079.6"
+ wire width 7 $2\gspr_index$next[6:0]$3385
+ attribute \src "libresoc.v:51080.3-51113.6"
+ wire width 32 $2\log_dmi_addr$next[31:0]$3391
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $2\stopping$next[0:0]$3376
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $2\terminated$next[0:0]$3366
+ attribute \src "libresoc.v:51276.3-51309.6"
+ wire $3\do_dmi_log_rd$next[0:0]$3428
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $3\do_icreset$next[0:0]$3421
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $3\do_reset$next[0:0]$3414
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $3\do_step$next[0:0]$3407
+ attribute \src "libresoc.v:51052.3-51079.6"
+ wire width 7 $3\gspr_index$next[6:0]$3386
+ attribute \src "libresoc.v:51080.3-51113.6"
+ wire width 32 $3\log_dmi_addr$next[31:0]$3392
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $3\stopping$next[0:0]$3377
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $3\terminated$next[0:0]$3367
+ attribute \src "libresoc.v:51276.3-51309.6"
+ wire $4\do_dmi_log_rd$next[0:0]$3429
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $4\do_icreset$next[0:0]$3422
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $4\do_reset$next[0:0]$3415
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $4\do_step$next[0:0]$3408
+ attribute \src "libresoc.v:51052.3-51079.6"
+ wire width 7 $4\gspr_index$next[6:0]$3387
+ attribute \src "libresoc.v:51080.3-51113.6"
+ wire width 32 $4\log_dmi_addr$next[31:0]$3393
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $4\stopping$next[0:0]$3378
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $4\terminated$next[0:0]$3368
+ attribute \src "libresoc.v:51246.3-51275.6"
+ wire $5\do_icreset$next[0:0]$3423
+ attribute \src "libresoc.v:51216.3-51245.6"
+ wire $5\do_reset$next[0:0]$3416
+ attribute \src "libresoc.v:51186.3-51215.6"
+ wire $5\do_step$next[0:0]$3409
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $5\stopping$next[0:0]$3379
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $5\terminated$next[0:0]$3369
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $6\stopping$next[0:0]$3380
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $6\terminated$next[0:0]$3370
+ attribute \src "libresoc.v:51008.3-51051.6"
+ wire $7\stopping$next[0:0]$3381
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $7\terminated$next[0:0]$3371
+ attribute \src "libresoc.v:50958.3-51007.6"
+ wire $8\terminated$next[0:0]$3372
+ attribute \src "libresoc.v:50846.19-50846.110"
+ wire width 3 $add$libresoc.v:50846$3294_Y
+ attribute \src "libresoc.v:50840.19-50840.103"
+ wire $and$libresoc.v:50840$3288_Y
+ attribute \src "libresoc.v:50842.19-50842.113"
+ wire $and$libresoc.v:50842$3290_Y
+ attribute \src "libresoc.v:50847.18-50847.110"
+ wire $and$libresoc.v:50847$3295_Y
+ attribute \src "libresoc.v:50849.19-50849.103"
+ wire $and$libresoc.v:50849$3297_Y
+ attribute \src "libresoc.v:50851.19-50851.102"
+ wire $and$libresoc.v:50851$3299_Y
+ attribute \src "libresoc.v:50857.18-50857.101"
+ wire $and$libresoc.v:50857$3305_Y
+ attribute \src "libresoc.v:50859.18-50859.111"
+ wire $and$libresoc.v:50859$3307_Y
+ attribute \src "libresoc.v:50864.18-50864.101"
+ wire $and$libresoc.v:50864$3312_Y
+ attribute \src "libresoc.v:50867.18-50867.111"
+ wire $and$libresoc.v:50867$3315_Y
+ attribute \src "libresoc.v:50872.18-50872.101"
+ wire $and$libresoc.v:50872$3320_Y
+ attribute \src "libresoc.v:50874.18-50874.111"
+ wire $and$libresoc.v:50874$3322_Y
+ attribute \src "libresoc.v:50880.18-50880.101"
+ wire $and$libresoc.v:50880$3328_Y
+ attribute \src "libresoc.v:50882.18-50882.111"
+ wire $and$libresoc.v:50882$3330_Y
+ attribute \src "libresoc.v:50887.18-50887.101"
+ wire $and$libresoc.v:50887$3335_Y
+ attribute \src "libresoc.v:50888.17-50888.99"
+ wire $and$libresoc.v:50888$3336_Y
+ attribute \src "libresoc.v:50890.18-50890.111"
+ wire $and$libresoc.v:50890$3338_Y
+ attribute \src "libresoc.v:50895.18-50895.101"
+ wire $and$libresoc.v:50895$3343_Y
+ attribute \src "libresoc.v:50897.18-50897.111"
+ wire $and$libresoc.v:50897$3345_Y
+ attribute \src "libresoc.v:50837.18-50837.103"
+ wire $eq$libresoc.v:50837$3285_Y
+ attribute \src "libresoc.v:50838.19-50838.104"
+ wire $eq$libresoc.v:50838$3286_Y
+ attribute \src "libresoc.v:50843.19-50843.104"
+ wire $eq$libresoc.v:50843$3291_Y
+ attribute \src "libresoc.v:50844.19-50844.104"
+ wire $eq$libresoc.v:50844$3292_Y
+ attribute \src "libresoc.v:50845.19-50845.104"
+ wire $eq$libresoc.v:50845$3293_Y
+ attribute \src "libresoc.v:50848.19-50848.104"
+ wire $eq$libresoc.v:50848$3296_Y
+ attribute \src "libresoc.v:50852.18-50852.103"
+ wire $eq$libresoc.v:50852$3300_Y
+ attribute \src "libresoc.v:50853.18-50853.103"
+ wire $eq$libresoc.v:50853$3301_Y
+ attribute \src "libresoc.v:50854.18-50854.103"
+ wire $eq$libresoc.v:50854$3302_Y
+ attribute \src "libresoc.v:50860.18-50860.103"
+ wire $eq$libresoc.v:50860$3308_Y
+ attribute \src "libresoc.v:50861.18-50861.103"
+ wire $eq$libresoc.v:50861$3309_Y
+ attribute \src "libresoc.v:50862.18-50862.103"
+ wire $eq$libresoc.v:50862$3310_Y
+ attribute \src "libresoc.v:50868.18-50868.103"
+ wire $eq$libresoc.v:50868$3316_Y
+ attribute \src "libresoc.v:50869.18-50869.103"
+ wire $eq$libresoc.v:50869$3317_Y
+ attribute \src "libresoc.v:50870.18-50870.103"
+ wire $eq$libresoc.v:50870$3318_Y
+ attribute \src "libresoc.v:50875.18-50875.103"
+ wire $eq$libresoc.v:50875$3323_Y
+ attribute \src "libresoc.v:50876.18-50876.103"
+ wire $eq$libresoc.v:50876$3324_Y
+ attribute \src "libresoc.v:50878.18-50878.103"
+ wire $eq$libresoc.v:50878$3326_Y
+ attribute \src "libresoc.v:50883.18-50883.103"
+ wire $eq$libresoc.v:50883$3331_Y
+ attribute \src "libresoc.v:50884.18-50884.103"
+ wire $eq$libresoc.v:50884$3332_Y
+ attribute \src "libresoc.v:50885.18-50885.103"
+ wire $eq$libresoc.v:50885$3333_Y
+ attribute \src "libresoc.v:50891.18-50891.103"
+ wire $eq$libresoc.v:50891$3339_Y
+ attribute \src "libresoc.v:50892.18-50892.103"
+ wire $eq$libresoc.v:50892$3340_Y
+ attribute \src "libresoc.v:50893.18-50893.103"
+ wire $eq$libresoc.v:50893$3341_Y
+ attribute \src "libresoc.v:50898.18-50898.103"
+ wire $eq$libresoc.v:50898$3346_Y
+ attribute \src "libresoc.v:50836.17-50836.103"
+ wire $not$libresoc.v:50836$3284_Y
+ attribute \src "libresoc.v:50839.19-50839.99"
+ wire $not$libresoc.v:50839$3287_Y
+ attribute \src "libresoc.v:50841.19-50841.105"
+ wire $not$libresoc.v:50841$3289_Y
+ attribute \src "libresoc.v:50850.19-50850.95"
+ wire $not$libresoc.v:50850$3298_Y
+ attribute \src "libresoc.v:50856.18-50856.98"
+ wire $not$libresoc.v:50856$3304_Y
+ attribute \src "libresoc.v:50858.18-50858.104"
+ wire $not$libresoc.v:50858$3306_Y
+ attribute \src "libresoc.v:50863.18-50863.98"
+ wire $not$libresoc.v:50863$3311_Y
+ attribute \src "libresoc.v:50865.18-50865.104"
+ wire $not$libresoc.v:50865$3313_Y
+ attribute \src "libresoc.v:50871.18-50871.98"
+ wire $not$libresoc.v:50871$3319_Y
+ attribute \src "libresoc.v:50873.18-50873.104"
+ wire $not$libresoc.v:50873$3321_Y
+ attribute \src "libresoc.v:50877.17-50877.97"
+ wire $not$libresoc.v:50877$3325_Y
+ attribute \src "libresoc.v:50879.18-50879.98"
+ wire $not$libresoc.v:50879$3327_Y
+ attribute \src "libresoc.v:50881.18-50881.104"
+ wire $not$libresoc.v:50881$3329_Y
+ attribute \src "libresoc.v:50886.18-50886.98"
+ wire $not$libresoc.v:50886$3334_Y
+ attribute \src "libresoc.v:50889.18-50889.104"
+ wire $not$libresoc.v:50889$3337_Y
+ attribute \src "libresoc.v:50894.18-50894.98"
+ wire $not$libresoc.v:50894$3342_Y
+ attribute \src "libresoc.v:50896.18-50896.104"
+ wire $not$libresoc.v:50896$3344_Y
+ attribute \src "libresoc.v:50855.17-50855.126"
+ wire width 64 $pos$libresoc.v:50855$3303_Y
+ attribute \src "libresoc.v:50866.17-50866.245"
+ wire width 64 $pos$libresoc.v:50866$3314_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
wire width 64 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- wire width 3 \$115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- wire width 3 \$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
- wire \$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ wire \$115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240"
+ wire width 3 \$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240"
+ wire width 3 \$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
wire \$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
wire \$122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
wire \$124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
+ wire \$126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
+ wire width 64 \$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
wire \$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
wire \$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
wire \$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
wire \$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 24 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 30 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
+ wire width 7 input 13 \core_dbg_core_dbg_dststep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31"
+ wire width 7 input 16 \core_dbg_core_dbg_maxvl
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
+ wire width 7 input 14 \core_dbg_core_dbg_srcstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27"
+ wire width 2 input 12 \core_dbg_core_dbg_subvl
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26"
+ wire width 2 input 11 \core_dbg_core_dbg_svstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
+ wire width 7 input 15 \core_dbg_core_dbg_vl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
- wire width 64 input 11 \core_dbg_msr
+ wire width 64 input 17 \core_dbg_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire width 64 input 10 \core_dbg_pc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99"
+ wire output 7 \core_rst_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
- wire output 8 \core_rst_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97"
- wire output 12 \core_stop_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
- wire input 13 \core_stopped_i
+ wire output 18 \core_stop_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104"
+ wire input 19 \core_stopped_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
+ wire input 26 \d_cr_ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
+ wire width 64 input 25 \d_cr_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
- wire input 20 \d_cr_ack
+ wire output 24 \d_cr_req
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
+ wire input 23 \d_gpr_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
- wire width 64 input 19 \d_cr_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
- wire output 18 \d_cr_req
+ wire width 7 output 21 \d_gpr_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
+ wire width 64 input 22 \d_gpr_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
- wire input 17 \d_gpr_ack
+ wire output 20 \d_gpr_req
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
- wire width 7 output 15 \d_gpr_addr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
- wire width 64 input 16 \d_gpr_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
- wire output 14 \d_gpr_req
+ wire input 29 \d_xer_ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
+ wire width 64 input 28 \d_xer_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
- wire input 23 \d_xer_ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
- wire width 64 input 22 \d_xer_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
- wire output 21 \d_xer_req
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
- wire output 6 \dmi_ack_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
- wire width 4 input 2 \dmi_addr_i
+ wire output 27 \d_xer_req
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63"
+ wire output 5 \dmi_ack_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
- wire width 64 input 5 \dmi_din
+ wire width 4 input 1 \dmi_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
- wire width 64 output 7 \dmi_dout
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
+ wire width 64 input 4 \dmi_din
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
+ wire width 64 output 6 \dmi_dout
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
wire \dmi_read_log_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
- wire \dmi_read_log_data$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
+ wire \dmi_read_log_data$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150"
wire \dmi_read_log_data_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150"
wire \dmi_read_log_data_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
- wire input 3 \dmi_req_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
+ wire input 2 \dmi_req_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132"
wire \dmi_req_i_1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132"
wire \dmi_req_i_1$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
- wire input 4 \dmi_we_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
+ wire input 3 \dmi_we_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
wire \do_dmi_log_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
wire \do_dmi_log_rd$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
wire \do_icreset
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
wire \do_icreset$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
wire \do_reset
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
wire \do_reset$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
wire \do_step
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
wire \do_step$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144"
wire width 7 \gspr_index
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144"
wire width 7 \gspr_index$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100"
wire \icache_rst_o
- attribute \src "libresoc.v:51256.7-51256.15"
+ attribute \src "libresoc.v:50588.7-50588.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146"
wire width 32 \log_dmi_addr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
- wire width 32 \log_dmi_addr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146"
+ wire width 32 \log_dmi_addr$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
wire width 64 \log_dmi_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120"
wire width 32 \log_write_addr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 8 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135"
wire width 64 \stat_reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
wire \stopping
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
wire \stopping$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
wire input 9 \terminate_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142"
wire \terminated
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142"
wire \terminated$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123"
wire \terminated_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $add $add$libresoc.v:51499$3321
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240"
+ cell $add $add$libresoc.v:50846$3294
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \log_dmi_addr [1:0]
connect \B 1'1
- connect \Y $add$libresoc.v:51499$3321_Y
+ connect \Y $add$libresoc.v:50846$3294_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51490$3312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50840$3288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_read_log_data_1
- connect \B \$7
- connect \Y $and$libresoc.v:51490$3312_Y
+ connect \A \dmi_req_i
+ connect \B \$103
+ connect \Y $and$libresoc.v:50840$3288_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51493$3315
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50842$3290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_req_i
- connect \B \$101
- connect \Y $and$libresoc.v:51493$3315_Y
+ connect \A \dmi_read_log_data_1
+ connect \B \$107
+ connect \Y $and$libresoc.v:50842$3290_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51495$3317
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50847$3295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$105
- connect \Y $and$libresoc.v:51495$3317_Y
+ connect \B \$9
+ connect \Y $and$libresoc.v:50847$3295_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
- cell $and $and$libresoc.v:51502$3324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
+ cell $and $and$libresoc.v:50849$3297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$118
- connect \Y $and$libresoc.v:51502$3324_Y
+ connect \B \$120
+ connect \Y $and$libresoc.v:50849$3297_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
- cell $and $and$libresoc.v:51504$3326
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
+ cell $and $and$libresoc.v:50851$3299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \stopping
- connect \B \$122
- connect \Y $and$libresoc.v:51504$3326_Y
+ connect \B \$124
+ connect \Y $and$libresoc.v:50851$3299_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51509$3331
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50857$3305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$17
- connect \Y $and$libresoc.v:51509$3331_Y
+ connect \B \$19
+ connect \Y $and$libresoc.v:50857$3305_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51511$3333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50859$3307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$21
- connect \Y $and$libresoc.v:51511$3333_Y
+ connect \B \$23
+ connect \Y $and$libresoc.v:50859$3307_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51516$3338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50864$3312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$31
- connect \Y $and$libresoc.v:51516$3338_Y
+ connect \B \$33
+ connect \Y $and$libresoc.v:50864$3312_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51518$3340
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50867$3315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$35
- connect \Y $and$libresoc.v:51518$3340_Y
+ connect \B \$37
+ connect \Y $and$libresoc.v:50867$3315_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51524$3346
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50872$3320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$45
- connect \Y $and$libresoc.v:51524$3346_Y
+ connect \B \$47
+ connect \Y $and$libresoc.v:50872$3320_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51526$3348
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50874$3322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$49
- connect \Y $and$libresoc.v:51526$3348_Y
+ connect \B \$51
+ connect \Y $and$libresoc.v:50874$3322_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51530$3352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50880$3328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$3
- connect \Y $and$libresoc.v:51530$3352_Y
+ connect \B \$61
+ connect \Y $and$libresoc.v:50880$3328_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51532$3354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50882$3330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_req_i
- connect \B \$59
- connect \Y $and$libresoc.v:51532$3354_Y
+ connect \A \dmi_read_log_data_1
+ connect \B \$65
+ connect \Y $and$libresoc.v:50882$3330_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51534$3356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50887$3335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_read_log_data_1
- connect \B \$63
- connect \Y $and$libresoc.v:51534$3356_Y
+ connect \A \dmi_req_i
+ connect \B \$75
+ connect \Y $and$libresoc.v:50887$3335_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51539$3361
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50888$3336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$73
- connect \Y $and$libresoc.v:51539$3361_Y
+ connect \B \$5
+ connect \Y $and$libresoc.v:50888$3336_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51542$3364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50890$3338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$77
- connect \Y $and$libresoc.v:51542$3364_Y
+ connect \B \$79
+ connect \Y $and$libresoc.v:50890$3338_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:51547$3369
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $and $and$libresoc.v:50895$3343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i
- connect \B \$87
- connect \Y $and$libresoc.v:51547$3369_Y
+ connect \B \$89
+ connect \Y $and$libresoc.v:50895$3343_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:51549$3371
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $and $and$libresoc.v:50897$3345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
- connect \B \$91
- connect \Y $and$libresoc.v:51549$3371_Y
+ connect \B \$93
+ connect \Y $and$libresoc.v:50897$3345_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50837$3285
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A \dmi_addr_i
+ connect \B 3'100
+ connect \Y $eq$libresoc.v:50837$3285_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51491$3313
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50838$3286
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51491$3313_Y
+ connect \Y $eq$libresoc.v:50838$3286_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51496$3318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50843$3291
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51496$3318_Y
+ connect \Y $eq$libresoc.v:50843$3291_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51497$3319
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50844$3292
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51497$3319_Y
+ connect \Y $eq$libresoc.v:50844$3292_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51498$3320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50845$3293
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51498$3320_Y
+ connect \Y $eq$libresoc.v:50845$3293_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
- cell $eq $eq$libresoc.v:51500$3322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245"
+ cell $eq $eq$libresoc.v:50848$3296
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'111
- connect \Y $eq$libresoc.v:51500$3322_Y
+ connect \Y $eq$libresoc.v:50848$3296_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51501$3323
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50852$3300
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51501$3323_Y
+ connect \Y $eq$libresoc.v:50852$3300_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51505$3327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50853$3301
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51505$3327_Y
+ connect \Y $eq$libresoc.v:50853$3301_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51506$3328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50854$3302
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51506$3328_Y
+ connect \Y $eq$libresoc.v:50854$3302_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51512$3334
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50860$3308
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51512$3334_Y
+ connect \Y $eq$libresoc.v:50860$3308_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51513$3335
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50861$3309
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51513$3335_Y
+ connect \Y $eq$libresoc.v:50861$3309_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51514$3336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50862$3310
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51514$3336_Y
+ connect \Y $eq$libresoc.v:50862$3310_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51520$3342
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50868$3316
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51520$3342_Y
+ connect \Y $eq$libresoc.v:50868$3316_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51521$3343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50869$3317
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51521$3343_Y
+ connect \Y $eq$libresoc.v:50869$3317_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51522$3344
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50870$3318
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51522$3344_Y
+ connect \Y $eq$libresoc.v:50870$3318_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51527$3349
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50875$3323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51527$3349_Y
+ connect \Y $eq$libresoc.v:50875$3323_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51528$3350
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50876$3324
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51528$3350_Y
+ connect \Y $eq$libresoc.v:50876$3324_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51529$3351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50878$3326
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51529$3351_Y
+ connect \Y $eq$libresoc.v:50878$3326_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51535$3357
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50883$3331
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51535$3357_Y
+ connect \Y $eq$libresoc.v:50883$3331_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51536$3358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50884$3332
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51536$3358_Y
+ connect \Y $eq$libresoc.v:50884$3332_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51537$3359
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50885$3333
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51537$3359_Y
+ connect \Y $eq$libresoc.v:50885$3333_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51543$3365
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50891$3339
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51543$3365_Y
+ connect \Y $eq$libresoc.v:50891$3339_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51544$3366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
+ cell $eq $eq$libresoc.v:50892$3340
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:51544$3366_Y
+ connect \Y $eq$libresoc.v:50892$3340_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:51545$3367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230"
+ cell $eq $eq$libresoc.v:50893$3341
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:51545$3367_Y
+ connect \Y $eq$libresoc.v:50893$3341_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:51550$3372
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ cell $eq $eq$libresoc.v:50898$3346
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:51550$3372_Y
+ connect \Y $eq$libresoc.v:50898$3346_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:51551$3373
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50836$3284
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_addr_i
- connect \B 3'100
- connect \Y $eq$libresoc.v:51551$3373_Y
+ connect \A \dmi_read_log_data
+ connect \Y $not$libresoc.v:50836$3284_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51492$3314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50839$3287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51492$3314_Y
+ connect \Y $not$libresoc.v:50839$3287_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51494$3316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50841$3289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51494$3316_Y
+ connect \Y $not$libresoc.v:50841$3289_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
- cell $not $not$libresoc.v:51503$3325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257"
+ cell $not $not$libresoc.v:50850$3298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \do_step
- connect \Y $not$libresoc.v:51503$3325_Y
+ connect \Y $not$libresoc.v:50850$3298_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51507$3329
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50856$3304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51507$3329_Y
+ connect \Y $not$libresoc.v:50856$3304_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51510$3332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50858$3306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51510$3332_Y
+ connect \Y $not$libresoc.v:50858$3306_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51515$3337
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50863$3311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51515$3337_Y
+ connect \Y $not$libresoc.v:50863$3311_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51517$3339
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50865$3313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51517$3339_Y
+ connect \Y $not$libresoc.v:50865$3313_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51519$3341
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50871$3319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51519$3341_Y
+ connect \Y $not$libresoc.v:50871$3319_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51523$3345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50873$3321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51523$3345_Y
+ connect \A \dmi_read_log_data
+ connect \Y $not$libresoc.v:50873$3321_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51525$3347
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50877$3325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51525$3347_Y
+ connect \A \dmi_req_i_1
+ connect \Y $not$libresoc.v:50877$3325_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51531$3353
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50879$3327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51531$3353_Y
+ connect \Y $not$libresoc.v:50879$3327_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51533$3355
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50881$3329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51533$3355_Y
+ connect \Y $not$libresoc.v:50881$3329_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51538$3360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50886$3334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51538$3360_Y
+ connect \Y $not$libresoc.v:50886$3334_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51540$3362
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51540$3362_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51541$3363
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50889$3337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51541$3363_Y
+ connect \Y $not$libresoc.v:50889$3337_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:51546$3368
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ cell $not $not$libresoc.v:50894$3342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:51546$3368_Y
+ connect \Y $not$libresoc.v:50894$3342_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:51548$3370
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
+ cell $not $not$libresoc.v:50896$3344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:51548$3370_Y
+ connect \Y $not$libresoc.v:50896$3344_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
- cell $pos $pos$libresoc.v:51508$3330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+ cell $pos $pos$libresoc.v:50855$3303
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping }
- connect \Y $pos$libresoc.v:51508$3330_Y
+ connect \Y $pos$libresoc.v:50855$3303_Y
end
- attribute \src "libresoc.v:51256.7-51256.20"
- process $proc$libresoc.v:51256$3457
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
+ cell $pos $pos$libresoc.v:50866$3314
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep }
+ connect \Y $pos$libresoc.v:50866$3314_Y
+ end
+ attribute \src "libresoc.v:50588.7-50588.20"
+ process $proc$libresoc.v:50588$3430
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:51429.7-51429.31"
- process $proc$libresoc.v:51429$3458
+ attribute \src "libresoc.v:50775.7-50775.31"
+ process $proc$libresoc.v:50775$3431
assign { } { }
assign $1\dmi_read_log_data[0:0] 1'0
sync always
sync init
update \dmi_read_log_data $1\dmi_read_log_data[0:0]
end
- attribute \src "libresoc.v:51433.7-51433.33"
- process $proc$libresoc.v:51433$3459
+ attribute \src "libresoc.v:50779.7-50779.33"
+ process $proc$libresoc.v:50779$3432
assign { } { }
assign $1\dmi_read_log_data_1[0:0] 1'0
sync always
sync init
update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0]
end
- attribute \src "libresoc.v:51439.7-51439.25"
- process $proc$libresoc.v:51439$3460
+ attribute \src "libresoc.v:50785.7-50785.25"
+ process $proc$libresoc.v:50785$3433
assign { } { }
assign $1\dmi_req_i_1[0:0] 1'0
sync always
sync init
update \dmi_req_i_1 $1\dmi_req_i_1[0:0]
end
- attribute \src "libresoc.v:51445.7-51445.27"
- process $proc$libresoc.v:51445$3461
+ attribute \src "libresoc.v:50791.7-50791.27"
+ process $proc$libresoc.v:50791$3434
assign { } { }
assign $1\do_dmi_log_rd[0:0] 1'0
sync always
sync init
update \do_dmi_log_rd $1\do_dmi_log_rd[0:0]
end
- attribute \src "libresoc.v:51449.7-51449.24"
- process $proc$libresoc.v:51449$3462
+ attribute \src "libresoc.v:50795.7-50795.24"
+ process $proc$libresoc.v:50795$3435
assign { } { }
assign $1\do_icreset[0:0] 1'0
sync always
sync init
update \do_icreset $1\do_icreset[0:0]
end
- attribute \src "libresoc.v:51453.7-51453.22"
- process $proc$libresoc.v:51453$3463
+ attribute \src "libresoc.v:50799.7-50799.22"
+ process $proc$libresoc.v:50799$3436
assign { } { }
assign $1\do_reset[0:0] 1'0
sync always
sync init
update \do_reset $1\do_reset[0:0]
end
- attribute \src "libresoc.v:51457.7-51457.21"
- process $proc$libresoc.v:51457$3464
+ attribute \src "libresoc.v:50803.7-50803.21"
+ process $proc$libresoc.v:50803$3437
assign { } { }
assign $1\do_step[0:0] 1'0
sync always
sync init
update \do_step $1\do_step[0:0]
end
- attribute \src "libresoc.v:51461.13-51461.31"
- process $proc$libresoc.v:51461$3465
+ attribute \src "libresoc.v:50807.13-50807.31"
+ process $proc$libresoc.v:50807$3438
assign { } { }
assign $1\gspr_index[6:0] 7'0000000
sync always
sync init
update \gspr_index $1\gspr_index[6:0]
end
- attribute \src "libresoc.v:51467.14-51467.34"
- process $proc$libresoc.v:51467$3466
+ attribute \src "libresoc.v:50813.14-50813.34"
+ process $proc$libresoc.v:50813$3439
assign { } { }
assign $1\log_dmi_addr[31:0] 0
sync always
sync init
update \log_dmi_addr $1\log_dmi_addr[31:0]
end
- attribute \src "libresoc.v:51479.7-51479.22"
- process $proc$libresoc.v:51479$3467
+ attribute \src "libresoc.v:50825.7-50825.22"
+ process $proc$libresoc.v:50825$3440
assign { } { }
assign $1\stopping[0:0] 1'0
sync always
sync init
update \stopping $1\stopping[0:0]
end
- attribute \src "libresoc.v:51485.7-51485.24"
- process $proc$libresoc.v:51485$3468
+ attribute \src "libresoc.v:50831.7-50831.24"
+ process $proc$libresoc.v:50831$3441
assign { } { }
assign $1\terminated[0:0] 1'0
sync always
sync init
update \terminated $1\terminated[0:0]
end
- attribute \src "libresoc.v:51552.3-51553.51"
- process $proc$libresoc.v:51552$3374
+ attribute \src "libresoc.v:50899.3-50900.51"
+ process $proc$libresoc.v:50899$3347
assign { } { }
assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next
sync posedge \clk
update \dmi_read_log_data $0\dmi_read_log_data[0:0]
end
- attribute \src "libresoc.v:51554.3-51555.55"
- process $proc$libresoc.v:51554$3375
+ attribute \src "libresoc.v:50901.3-50902.55"
+ process $proc$libresoc.v:50901$3348
assign { } { }
assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next
sync posedge \clk
update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0]
end
- attribute \src "libresoc.v:51556.3-51557.41"
- process $proc$libresoc.v:51556$3376
+ attribute \src "libresoc.v:50903.3-50904.41"
+ process $proc$libresoc.v:50903$3349
assign { } { }
assign $0\log_dmi_addr[31:0] \log_dmi_addr$next
sync posedge \clk
update \log_dmi_addr $0\log_dmi_addr[31:0]
end
- attribute \src "libresoc.v:51558.3-51559.37"
- process $proc$libresoc.v:51558$3377
+ attribute \src "libresoc.v:50905.3-50906.37"
+ process $proc$libresoc.v:50905$3350
assign { } { }
assign $0\gspr_index[6:0] \gspr_index$next
sync posedge \clk
update \gspr_index $0\gspr_index[6:0]
end
- attribute \src "libresoc.v:51560.3-51561.33"
- process $proc$libresoc.v:51560$3378
+ attribute \src "libresoc.v:50907.3-50908.33"
+ process $proc$libresoc.v:50907$3351
assign { } { }
assign $0\stopping[0:0] \stopping$next
sync posedge \clk
update \stopping $0\stopping[0:0]
end
- attribute \src "libresoc.v:51562.3-51563.37"
- process $proc$libresoc.v:51562$3379
+ attribute \src "libresoc.v:50909.3-50910.37"
+ process $proc$libresoc.v:50909$3352
assign { } { }
assign $0\terminated[0:0] \terminated$next
sync posedge \clk
update \terminated $0\terminated[0:0]
end
- attribute \src "libresoc.v:51564.3-51565.39"
- process $proc$libresoc.v:51564$3380
+ attribute \src "libresoc.v:50911.3-50912.39"
+ process $proc$libresoc.v:50911$3353
assign { } { }
assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next
sync posedge \clk
update \dmi_req_i_1 $0\dmi_req_i_1[0:0]
end
- attribute \src "libresoc.v:51566.3-51567.43"
- process $proc$libresoc.v:51566$3381
+ attribute \src "libresoc.v:50913.3-50914.43"
+ process $proc$libresoc.v:50913$3354
assign { } { }
assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next
sync posedge \clk
update \do_dmi_log_rd $0\do_dmi_log_rd[0:0]
end
- attribute \src "libresoc.v:51568.3-51569.37"
- process $proc$libresoc.v:51568$3382
+ attribute \src "libresoc.v:50915.3-50916.37"
+ process $proc$libresoc.v:50915$3355
assign { } { }
assign $0\do_icreset[0:0] \do_icreset$next
sync posedge \clk
update \do_icreset $0\do_icreset[0:0]
end
- attribute \src "libresoc.v:51570.3-51571.33"
- process $proc$libresoc.v:51570$3383
+ attribute \src "libresoc.v:50917.3-50918.33"
+ process $proc$libresoc.v:50917$3356
assign { } { }
assign $0\do_reset[0:0] \do_reset$next
sync posedge \clk
update \do_reset $0\do_reset[0:0]
end
- attribute \src "libresoc.v:51572.3-51573.31"
- process $proc$libresoc.v:51572$3384
+ attribute \src "libresoc.v:50919.3-50920.31"
+ process $proc$libresoc.v:50919$3357
assign { } { }
assign $0\do_step[0:0] \do_step$next
sync posedge \clk
update \do_step $0\do_step[0:0]
end
- attribute \src "libresoc.v:51574.3-51591.6"
- process $proc$libresoc.v:51574$3385
+ attribute \src "libresoc.v:50921.3-50938.6"
+ process $proc$libresoc.v:50921$3358
assign { } { }
assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:51575.5-51575.29"
+ attribute \src "libresoc.v:50922.5-50922.29"
switch \initial
- attribute \src "libresoc.v:51575.9-51575.17"
+ attribute \src "libresoc.v:50922.9-50922.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
sync always
update \dmi_ack_o $0\dmi_ack_o[0:0]
end
- attribute \src "libresoc.v:51592.3-51601.6"
- process $proc$libresoc.v:51592$3386
+ attribute \src "libresoc.v:50939.3-50948.6"
+ process $proc$libresoc.v:50939$3359
assign { } { }
assign { } { }
assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:51593.5-51593.29"
+ attribute \src "libresoc.v:50940.5-50940.29"
switch \initial
- attribute \src "libresoc.v:51593.9-51593.17"
+ attribute \src "libresoc.v:50940.9-50940.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
sync always
update \d_gpr_req $0\d_gpr_req[0:0]
end
- attribute \src "libresoc.v:51602.3-51610.6"
- process $proc$libresoc.v:51602$3387
+ attribute \src "libresoc.v:50949.3-50957.6"
+ process $proc$libresoc.v:50949$3360
assign { } { }
assign { } { }
- assign $0\dmi_req_i_1$next[0:0]$3388 $1\dmi_req_i_1$next[0:0]$3389
- attribute \src "libresoc.v:51603.5-51603.29"
+ assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362
+ attribute \src "libresoc.v:50950.5-50950.29"
switch \initial
- attribute \src "libresoc.v:51603.9-51603.17"
+ attribute \src "libresoc.v:50950.9-50950.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_req_i_1$next[0:0]$3389 1'0
+ assign $1\dmi_req_i_1$next[0:0]$3362 1'0
case
- assign $1\dmi_req_i_1$next[0:0]$3389 \dmi_req_i
+ assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i
end
sync always
- update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3388
+ update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361
end
- attribute \src "libresoc.v:51611.3-51660.6"
- process $proc$libresoc.v:51611$3390
+ attribute \src "libresoc.v:50958.3-51007.6"
+ process $proc$libresoc.v:50958$3363
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\terminated$next[0:0]$3391 $8\terminated$next[0:0]$3399
- attribute \src "libresoc.v:51612.5-51612.29"
+ assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372
+ attribute \src "libresoc.v:50959.5-50959.29"
switch \initial
- attribute \src "libresoc.v:51612.9-51612.17"
+ attribute \src "libresoc.v:50959.9-50959.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$65 \$61 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$67 \$63 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\terminated$next[0:0]$3392 $2\terminated$next[0:0]$3393
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\terminated$next[0:0]$3393 $3\terminated$next[0:0]$3394
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$71 \$69 \$67 }
+ assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$73 \$71 \$69 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
assign { } { }
assign { } { }
- assign $3\terminated$next[0:0]$3394 $6\terminated$next[0:0]$3397
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
+ assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
switch \dmi_din [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\terminated$next[0:0]$3395 1'0
+ assign $4\terminated$next[0:0]$3368 1'0
case
- assign $4\terminated$next[0:0]$3395 \terminated
+ assign $4\terminated$next[0:0]$3368 \terminated
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\terminated$next[0:0]$3396 1'0
+ assign $5\terminated$next[0:0]$3369 1'0
case
- assign $5\terminated$next[0:0]$3396 $4\terminated$next[0:0]$3395
+ assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221"
switch \dmi_din [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\terminated$next[0:0]$3397 1'0
+ assign $6\terminated$next[0:0]$3370 1'0
case
- assign $6\terminated$next[0:0]$3397 $5\terminated$next[0:0]$3396
+ assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369
end
case
- assign $3\terminated$next[0:0]$3394 \terminated
+ assign $3\terminated$next[0:0]$3367 \terminated
end
case
- assign $2\terminated$next[0:0]$3393 \terminated
+ assign $2\terminated$next[0:0]$3366 \terminated
end
case
- assign $1\terminated$next[0:0]$3392 \terminated
+ assign $1\terminated$next[0:0]$3365 \terminated
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250"
switch \terminate_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\terminated$next[0:0]$3398 1'1
+ assign $7\terminated$next[0:0]$3371 1'1
case
- assign $7\terminated$next[0:0]$3398 $1\terminated$next[0:0]$3392
+ assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\terminated$next[0:0]$3399 1'0
+ assign $8\terminated$next[0:0]$3372 1'0
case
- assign $8\terminated$next[0:0]$3399 $7\terminated$next[0:0]$3398
+ assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371
end
sync always
- update \terminated$next $0\terminated$next[0:0]$3391
+ update \terminated$next $0\terminated$next[0:0]$3364
end
- attribute \src "libresoc.v:51661.3-51704.6"
- process $proc$libresoc.v:51661$3400
+ attribute \src "libresoc.v:51008.3-51051.6"
+ process $proc$libresoc.v:51008$3373
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\stopping$next[0:0]$3401 $7\stopping$next[0:0]$3408
- attribute \src "libresoc.v:51662.5-51662.29"
+ assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381
+ attribute \src "libresoc.v:51009.5-51009.29"
switch \initial
- attribute \src "libresoc.v:51662.9-51662.17"
+ attribute \src "libresoc.v:51009.9-51009.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$79 \$75 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$81 \$77 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\stopping$next[0:0]$3402 $2\stopping$next[0:0]$3403
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\stopping$next[0:0]$3403 $3\stopping$next[0:0]$3404
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$85 \$83 \$81 }
+ assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$87 \$85 \$83 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
assign { } { }
- assign $3\stopping$next[0:0]$3404 $5\stopping$next[0:0]$3406
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+ assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214"
switch \dmi_din [0]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\stopping$next[0:0]$3405 1'1
+ assign $4\stopping$next[0:0]$3378 1'1
case
- assign $4\stopping$next[0:0]$3405 \stopping
+ assign $4\stopping$next[0:0]$3378 \stopping
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221"
switch \dmi_din [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\stopping$next[0:0]$3406 1'0
+ assign $5\stopping$next[0:0]$3379 1'0
case
- assign $5\stopping$next[0:0]$3406 $4\stopping$next[0:0]$3405
+ assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378
end
case
- assign $3\stopping$next[0:0]$3404 \stopping
+ assign $3\stopping$next[0:0]$3377 \stopping
end
case
- assign $2\stopping$next[0:0]$3403 \stopping
+ assign $2\stopping$next[0:0]$3376 \stopping
end
case
- assign $1\stopping$next[0:0]$3402 \stopping
+ assign $1\stopping$next[0:0]$3375 \stopping
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250"
switch \terminate_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\stopping$next[0:0]$3407 1'1
+ assign $6\stopping$next[0:0]$3380 1'1
case
- assign $6\stopping$next[0:0]$3407 $1\stopping$next[0:0]$3402
+ assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\stopping$next[0:0]$3408 1'0
+ assign $7\stopping$next[0:0]$3381 1'0
case
- assign $7\stopping$next[0:0]$3408 $6\stopping$next[0:0]$3407
+ assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380
end
sync always
- update \stopping$next $0\stopping$next[0:0]$3401
+ update \stopping$next $0\stopping$next[0:0]$3374
end
- attribute \src "libresoc.v:51705.3-51732.6"
- process $proc$libresoc.v:51705$3409
+ attribute \src "libresoc.v:51052.3-51079.6"
+ process $proc$libresoc.v:51052$3382
assign { } { }
assign { } { }
assign { } { }
- assign $0\gspr_index$next[6:0]$3410 $4\gspr_index$next[6:0]$3414
- attribute \src "libresoc.v:51706.5-51706.29"
+ assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387
+ attribute \src "libresoc.v:51053.5-51053.29"
switch \initial
- attribute \src "libresoc.v:51706.9-51706.17"
+ attribute \src "libresoc.v:51053.9-51053.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$93 \$89 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$95 \$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\gspr_index$next[6:0]$3411 $2\gspr_index$next[6:0]$3412
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\gspr_index$next[6:0]$3412 $3\gspr_index$next[6:0]$3413
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$99 \$97 \$95 }
+ assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$101 \$99 \$97 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\gspr_index$next[6:0]$3413 \gspr_index
+ assign $3\gspr_index$next[6:0]$3386 \gspr_index
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $3\gspr_index$next[6:0]$3413 \dmi_din [6:0]
+ assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0]
case
- assign $3\gspr_index$next[6:0]$3413 \gspr_index
+ assign $3\gspr_index$next[6:0]$3386 \gspr_index
end
case
- assign $2\gspr_index$next[6:0]$3412 \gspr_index
+ assign $2\gspr_index$next[6:0]$3385 \gspr_index
end
case
- assign $1\gspr_index$next[6:0]$3411 \gspr_index
+ assign $1\gspr_index$next[6:0]$3384 \gspr_index
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\gspr_index$next[6:0]$3414 7'0000000
+ assign $4\gspr_index$next[6:0]$3387 7'0000000
case
- assign $4\gspr_index$next[6:0]$3414 $1\gspr_index$next[6:0]$3411
+ assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384
end
sync always
- update \gspr_index$next $0\gspr_index$next[6:0]$3410
+ update \gspr_index$next $0\gspr_index$next[6:0]$3383
end
- attribute \src "libresoc.v:51733.3-51766.6"
- process $proc$libresoc.v:51733$3415
+ attribute \src "libresoc.v:51080.3-51113.6"
+ process $proc$libresoc.v:51080$3388
assign { } { }
assign { } { }
assign { } { }
- assign $0\log_dmi_addr$next[31:0]$3416 $4\log_dmi_addr$next[31:0]$3420
- attribute \src "libresoc.v:51734.5-51734.29"
+ assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393
+ attribute \src "libresoc.v:51081.5-51081.29"
switch \initial
- attribute \src "libresoc.v:51734.9-51734.17"
+ attribute \src "libresoc.v:51081.9-51081.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$107 \$103 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$109 \$105 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\log_dmi_addr$next[31:0]$3417 $2\log_dmi_addr$next[31:0]$3418
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\log_dmi_addr$next[31:0]$3418 $3\log_dmi_addr$next[31:0]$3419
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$113 \$111 \$109 }
+ assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$115 \$113 \$111 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\log_dmi_addr$next[31:0]$3419 \dmi_din [31:0]
+ assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0]
case
- assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr
+ assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr
end
case
- assign $2\log_dmi_addr$next[31:0]$3418 \log_dmi_addr
+ assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
- assign $1\log_dmi_addr$next[31:0]$3417 [31:2] \log_dmi_addr [31:2]
- assign $1\log_dmi_addr$next[31:0]$3417 [1:0] \$115 [1:0]
+ assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2]
+ assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0]
case
- assign $1\log_dmi_addr$next[31:0]$3417 \log_dmi_addr
+ assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\log_dmi_addr$next[31:0]$3420 0
+ assign $4\log_dmi_addr$next[31:0]$3393 0
case
- assign $4\log_dmi_addr$next[31:0]$3420 $1\log_dmi_addr$next[31:0]$3417
+ assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390
end
sync always
- update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3416
+ update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389
end
- attribute \src "libresoc.v:51767.3-51775.6"
- process $proc$libresoc.v:51767$3421
+ attribute \src "libresoc.v:51114.3-51122.6"
+ process $proc$libresoc.v:51114$3394
assign { } { }
assign { } { }
- assign $0\dmi_read_log_data_1$next[0:0]$3422 $1\dmi_read_log_data_1$next[0:0]$3423
- attribute \src "libresoc.v:51768.5-51768.29"
+ assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396
+ attribute \src "libresoc.v:51115.5-51115.29"
switch \initial
- attribute \src "libresoc.v:51768.9-51768.17"
+ attribute \src "libresoc.v:51115.9-51115.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_read_log_data_1$next[0:0]$3423 1'0
+ assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0
case
- assign $1\dmi_read_log_data_1$next[0:0]$3423 \dmi_read_log_data
+ assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data
end
sync always
- update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3422
+ update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395
end
- attribute \src "libresoc.v:51776.3-51784.6"
- process $proc$libresoc.v:51776$3424
+ attribute \src "libresoc.v:51123.3-51131.6"
+ process $proc$libresoc.v:51123$3397
assign { } { }
assign { } { }
- assign $0\dmi_read_log_data$next[0:0]$3425 $1\dmi_read_log_data$next[0:0]$3426
- attribute \src "libresoc.v:51777.5-51777.29"
+ assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399
+ attribute \src "libresoc.v:51124.5-51124.29"
switch \initial
- attribute \src "libresoc.v:51777.9-51777.17"
+ attribute \src "libresoc.v:51124.9-51124.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi_read_log_data$next[0:0]$3426 1'0
+ assign $1\dmi_read_log_data$next[0:0]$3399 1'0
case
- assign $1\dmi_read_log_data$next[0:0]$3426 \$120
+ assign $1\dmi_read_log_data$next[0:0]$3399 \$122
end
sync always
- update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3425
+ update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398
end
- attribute \src "libresoc.v:51785.3-51794.6"
- process $proc$libresoc.v:51785$3427
+ attribute \src "libresoc.v:51132.3-51141.6"
+ process $proc$libresoc.v:51132$3400
assign { } { }
assign { } { }
assign $0\d_cr_req[0:0] $1\d_cr_req[0:0]
- attribute \src "libresoc.v:51786.5-51786.29"
+ attribute \src "libresoc.v:51133.5-51133.29"
switch \initial
- attribute \src "libresoc.v:51786.9-51786.17"
+ attribute \src "libresoc.v:51133.9-51133.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
sync always
update \d_cr_req $0\d_cr_req[0:0]
end
- attribute \src "libresoc.v:51795.3-51804.6"
- process $proc$libresoc.v:51795$3428
+ attribute \src "libresoc.v:51142.3-51151.6"
+ process $proc$libresoc.v:51142$3401
assign { } { }
assign { } { }
assign $0\d_xer_req[0:0] $1\d_xer_req[0:0]
- attribute \src "libresoc.v:51796.5-51796.29"
+ attribute \src "libresoc.v:51143.5-51143.29"
switch \initial
- attribute \src "libresoc.v:51796.9-51796.17"
+ attribute \src "libresoc.v:51143.9-51143.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
sync always
update \d_xer_req $0\d_xer_req[0:0]
end
- attribute \src "libresoc.v:51805.3-51835.6"
- process $proc$libresoc.v:51805$3429
+ attribute \src "libresoc.v:51152.3-51185.6"
+ process $proc$libresoc.v:51152$3402
assign { } { }
assign { } { }
assign $0\dmi_dout[63:0] $1\dmi_dout[63:0]
- attribute \src "libresoc.v:51806.5-51806.29"
+ attribute \src "libresoc.v:51153.5-51153.29"
switch \initial
- attribute \src "libresoc.v:51806.9-51806.17"
+ attribute \src "libresoc.v:51153.9-51153.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
assign { } { }
assign $1\dmi_dout[63:0] \core_dbg_msr
attribute \src "libresoc.v:0.0-0.0"
+ case 4'1010
+ assign { } { }
+ assign $1\dmi_dout[63:0] \$3
+ attribute \src "libresoc.v:0.0-0.0"
case 4'0101
assign { } { }
assign $1\dmi_dout[63:0] \d_gpr_data
sync always
update \dmi_dout $0\dmi_dout[63:0]
end
- attribute \src "libresoc.v:51836.3-51865.6"
- process $proc$libresoc.v:51836$3430
+ attribute \src "libresoc.v:51186.3-51215.6"
+ process $proc$libresoc.v:51186$3403
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_step$next[0:0]$3431 $5\do_step$next[0:0]$3436
- attribute \src "libresoc.v:51837.5-51837.29"
+ assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409
+ attribute \src "libresoc.v:51187.5-51187.29"
switch \initial
- attribute \src "libresoc.v:51837.9-51837.17"
+ attribute \src "libresoc.v:51187.9-51187.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$9 \$5 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$11 \$7 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_step$next[0:0]$3432 $2\do_step$next[0:0]$3433
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_step$next[0:0]$3433 $3\do_step$next[0:0]$3434
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$15 \$13 \$11 }
+ assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$17 \$15 \$13 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_step$next[0:0]$3434 $4\do_step$next[0:0]$3435
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
+ assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_step$next[0:0]$3435 1'1
+ assign $4\do_step$next[0:0]$3408 1'1
case
- assign $4\do_step$next[0:0]$3435 1'0
+ assign $4\do_step$next[0:0]$3408 1'0
end
case
- assign $3\do_step$next[0:0]$3434 1'0
+ assign $3\do_step$next[0:0]$3407 1'0
end
case
- assign $2\do_step$next[0:0]$3433 1'0
+ assign $2\do_step$next[0:0]$3406 1'0
end
case
- assign $1\do_step$next[0:0]$3432 1'0
+ assign $1\do_step$next[0:0]$3405 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_step$next[0:0]$3436 1'0
+ assign $5\do_step$next[0:0]$3409 1'0
case
- assign $5\do_step$next[0:0]$3436 $1\do_step$next[0:0]$3432
+ assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405
end
sync always
- update \do_step$next $0\do_step$next[0:0]$3431
+ update \do_step$next $0\do_step$next[0:0]$3404
end
- attribute \src "libresoc.v:51866.3-51895.6"
- process $proc$libresoc.v:51866$3437
+ attribute \src "libresoc.v:51216.3-51245.6"
+ process $proc$libresoc.v:51216$3410
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_reset$next[0:0]$3438 $5\do_reset$next[0:0]$3443
- attribute \src "libresoc.v:51867.5-51867.29"
+ assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416
+ attribute \src "libresoc.v:51217.5-51217.29"
switch \initial
- attribute \src "libresoc.v:51867.9-51867.17"
+ attribute \src "libresoc.v:51217.9-51217.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$23 \$19 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$25 \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_reset$next[0:0]$3439 $2\do_reset$next[0:0]$3440
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_reset$next[0:0]$3440 $3\do_reset$next[0:0]$3441
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$29 \$27 \$25 }
+ assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$31 \$29 \$27 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_reset$next[0:0]$3441 $4\do_reset$next[0:0]$3442
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
+ assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
switch \dmi_din [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_reset$next[0:0]$3442 1'1
+ assign $4\do_reset$next[0:0]$3415 1'1
case
- assign $4\do_reset$next[0:0]$3442 1'0
+ assign $4\do_reset$next[0:0]$3415 1'0
end
case
- assign $3\do_reset$next[0:0]$3441 1'0
+ assign $3\do_reset$next[0:0]$3414 1'0
end
case
- assign $2\do_reset$next[0:0]$3440 1'0
+ assign $2\do_reset$next[0:0]$3413 1'0
end
case
- assign $1\do_reset$next[0:0]$3439 1'0
+ assign $1\do_reset$next[0:0]$3412 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_reset$next[0:0]$3443 1'0
+ assign $5\do_reset$next[0:0]$3416 1'0
case
- assign $5\do_reset$next[0:0]$3443 $1\do_reset$next[0:0]$3439
+ assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412
end
sync always
- update \do_reset$next $0\do_reset$next[0:0]$3438
+ update \do_reset$next $0\do_reset$next[0:0]$3411
end
- attribute \src "libresoc.v:51896.3-51925.6"
- process $proc$libresoc.v:51896$3444
+ attribute \src "libresoc.v:51246.3-51275.6"
+ process $proc$libresoc.v:51246$3417
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_icreset$next[0:0]$3445 $5\do_icreset$next[0:0]$3450
- attribute \src "libresoc.v:51897.5-51897.29"
+ assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423
+ attribute \src "libresoc.v:51247.5-51247.29"
switch \initial
- attribute \src "libresoc.v:51897.9-51897.17"
+ attribute \src "libresoc.v:51247.9-51247.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$37 \$33 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$39 \$35 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_icreset$next[0:0]$3446 $2\do_icreset$next[0:0]$3447
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_icreset$next[0:0]$3447 $3\do_icreset$next[0:0]$3448
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$43 \$41 \$39 }
+ assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$45 \$43 \$41 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_icreset$next[0:0]$3448 $4\do_icreset$next[0:0]$3449
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
+ assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219"
switch \dmi_din [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_icreset$next[0:0]$3449 1'1
+ assign $4\do_icreset$next[0:0]$3422 1'1
case
- assign $4\do_icreset$next[0:0]$3449 1'0
+ assign $4\do_icreset$next[0:0]$3422 1'0
end
case
- assign $3\do_icreset$next[0:0]$3448 1'0
+ assign $3\do_icreset$next[0:0]$3421 1'0
end
case
- assign $2\do_icreset$next[0:0]$3447 1'0
+ assign $2\do_icreset$next[0:0]$3420 1'0
end
case
- assign $1\do_icreset$next[0:0]$3446 1'0
+ assign $1\do_icreset$next[0:0]$3419 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_icreset$next[0:0]$3450 1'0
+ assign $5\do_icreset$next[0:0]$3423 1'0
case
- assign $5\do_icreset$next[0:0]$3450 $1\do_icreset$next[0:0]$3446
+ assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419
end
sync always
- update \do_icreset$next $0\do_icreset$next[0:0]$3445
+ update \do_icreset$next $0\do_icreset$next[0:0]$3418
end
- attribute \src "libresoc.v:51926.3-51959.6"
- process $proc$libresoc.v:51926$3451
+ attribute \src "libresoc.v:51276.3-51309.6"
+ process $proc$libresoc.v:51276$3424
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_dmi_log_rd$next[0:0]$3452 $4\do_dmi_log_rd$next[0:0]$3456
- attribute \src "libresoc.v:51927.5-51927.29"
+ assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429
+ attribute \src "libresoc.v:51277.5-51277.29"
switch \initial
- attribute \src "libresoc.v:51927.9-51927.17"
+ attribute \src "libresoc.v:51277.9-51277.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$51 \$47 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203"
+ switch { \$53 \$49 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$3453 $2\do_dmi_log_rd$next[0:0]$3454
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+ assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_dmi_log_rd$next[0:0]$3454 $3\do_dmi_log_rd$next[0:0]$3455
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$57 \$55 \$53 }
+ assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210"
+ switch { \$59 \$57 \$55 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\do_dmi_log_rd$next[0:0]$3455 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\do_dmi_log_rd$next[0:0]$3455 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\do_dmi_log_rd$next[0:0]$3455 1'1
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'1
case
- assign $3\do_dmi_log_rd$next[0:0]$3455 1'0
+ assign $3\do_dmi_log_rd$next[0:0]$3428 1'0
end
case
- assign $2\do_dmi_log_rd$next[0:0]$3454 1'0
+ assign $2\do_dmi_log_rd$next[0:0]$3427 1'0
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$3453 1'1
+ assign $1\do_dmi_log_rd$next[0:0]$3426 1'1
case
- assign $1\do_dmi_log_rd$next[0:0]$3453 1'0
+ assign $1\do_dmi_log_rd$next[0:0]$3426 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_dmi_log_rd$next[0:0]$3456 1'0
- case
- assign $4\do_dmi_log_rd$next[0:0]$3456 $1\do_dmi_log_rd$next[0:0]$3453
- end
- sync always
- update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3452
- end
- connect \$9 $and$libresoc.v:51490$3312_Y
- connect \$99 $eq$libresoc.v:51491$3313_Y
- connect \$101 $not$libresoc.v:51492$3314_Y
- connect \$103 $and$libresoc.v:51493$3315_Y
- connect \$105 $not$libresoc.v:51494$3316_Y
- connect \$107 $and$libresoc.v:51495$3317_Y
- connect \$109 $eq$libresoc.v:51496$3318_Y
- connect \$111 $eq$libresoc.v:51497$3319_Y
- connect \$113 $eq$libresoc.v:51498$3320_Y
- connect \$116 $add$libresoc.v:51499$3321_Y
- connect \$118 $eq$libresoc.v:51500$3322_Y
- connect \$11 $eq$libresoc.v:51501$3323_Y
- connect \$120 $and$libresoc.v:51502$3324_Y
- connect \$122 $not$libresoc.v:51503$3325_Y
- connect \$124 $and$libresoc.v:51504$3326_Y
- connect \$13 $eq$libresoc.v:51505$3327_Y
- connect \$15 $eq$libresoc.v:51506$3328_Y
- connect \$17 $not$libresoc.v:51507$3329_Y
- connect \$1 $pos$libresoc.v:51508$3330_Y
- connect \$19 $and$libresoc.v:51509$3331_Y
- connect \$21 $not$libresoc.v:51510$3332_Y
- connect \$23 $and$libresoc.v:51511$3333_Y
- connect \$25 $eq$libresoc.v:51512$3334_Y
- connect \$27 $eq$libresoc.v:51513$3335_Y
- connect \$29 $eq$libresoc.v:51514$3336_Y
- connect \$31 $not$libresoc.v:51515$3337_Y
- connect \$33 $and$libresoc.v:51516$3338_Y
- connect \$35 $not$libresoc.v:51517$3339_Y
- connect \$37 $and$libresoc.v:51518$3340_Y
- connect \$3 $not$libresoc.v:51519$3341_Y
- connect \$39 $eq$libresoc.v:51520$3342_Y
- connect \$41 $eq$libresoc.v:51521$3343_Y
- connect \$43 $eq$libresoc.v:51522$3344_Y
- connect \$45 $not$libresoc.v:51523$3345_Y
- connect \$47 $and$libresoc.v:51524$3346_Y
- connect \$49 $not$libresoc.v:51525$3347_Y
- connect \$51 $and$libresoc.v:51526$3348_Y
- connect \$53 $eq$libresoc.v:51527$3349_Y
- connect \$55 $eq$libresoc.v:51528$3350_Y
- connect \$57 $eq$libresoc.v:51529$3351_Y
- connect \$5 $and$libresoc.v:51530$3352_Y
- connect \$59 $not$libresoc.v:51531$3353_Y
- connect \$61 $and$libresoc.v:51532$3354_Y
- connect \$63 $not$libresoc.v:51533$3355_Y
- connect \$65 $and$libresoc.v:51534$3356_Y
- connect \$67 $eq$libresoc.v:51535$3357_Y
- connect \$69 $eq$libresoc.v:51536$3358_Y
- connect \$71 $eq$libresoc.v:51537$3359_Y
- connect \$73 $not$libresoc.v:51538$3360_Y
- connect \$75 $and$libresoc.v:51539$3361_Y
- connect \$77 $not$libresoc.v:51540$3362_Y
- connect \$7 $not$libresoc.v:51541$3363_Y
- connect \$79 $and$libresoc.v:51542$3364_Y
- connect \$81 $eq$libresoc.v:51543$3365_Y
- connect \$83 $eq$libresoc.v:51544$3366_Y
- connect \$85 $eq$libresoc.v:51545$3367_Y
- connect \$87 $not$libresoc.v:51546$3368_Y
- connect \$89 $and$libresoc.v:51547$3369_Y
- connect \$91 $not$libresoc.v:51548$3370_Y
- connect \$93 $and$libresoc.v:51549$3371_Y
- connect \$95 $eq$libresoc.v:51550$3372_Y
- connect \$97 $eq$libresoc.v:51551$3373_Y
- connect \$115 \$116
+ assign $4\do_dmi_log_rd$next[0:0]$3429 1'0
+ case
+ assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426
+ end
+ sync always
+ update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425
+ end
+ connect \$9 $not$libresoc.v:50836$3284_Y
+ connect \$99 $eq$libresoc.v:50837$3285_Y
+ connect \$101 $eq$libresoc.v:50838$3286_Y
+ connect \$103 $not$libresoc.v:50839$3287_Y
+ connect \$105 $and$libresoc.v:50840$3288_Y
+ connect \$107 $not$libresoc.v:50841$3289_Y
+ connect \$109 $and$libresoc.v:50842$3290_Y
+ connect \$111 $eq$libresoc.v:50843$3291_Y
+ connect \$113 $eq$libresoc.v:50844$3292_Y
+ connect \$115 $eq$libresoc.v:50845$3293_Y
+ connect \$118 $add$libresoc.v:50846$3294_Y
+ connect \$11 $and$libresoc.v:50847$3295_Y
+ connect \$120 $eq$libresoc.v:50848$3296_Y
+ connect \$122 $and$libresoc.v:50849$3297_Y
+ connect \$124 $not$libresoc.v:50850$3298_Y
+ connect \$126 $and$libresoc.v:50851$3299_Y
+ connect \$13 $eq$libresoc.v:50852$3300_Y
+ connect \$15 $eq$libresoc.v:50853$3301_Y
+ connect \$17 $eq$libresoc.v:50854$3302_Y
+ connect \$1 $pos$libresoc.v:50855$3303_Y
+ connect \$19 $not$libresoc.v:50856$3304_Y
+ connect \$21 $and$libresoc.v:50857$3305_Y
+ connect \$23 $not$libresoc.v:50858$3306_Y
+ connect \$25 $and$libresoc.v:50859$3307_Y
+ connect \$27 $eq$libresoc.v:50860$3308_Y
+ connect \$29 $eq$libresoc.v:50861$3309_Y
+ connect \$31 $eq$libresoc.v:50862$3310_Y
+ connect \$33 $not$libresoc.v:50863$3311_Y
+ connect \$35 $and$libresoc.v:50864$3312_Y
+ connect \$37 $not$libresoc.v:50865$3313_Y
+ connect \$3 $pos$libresoc.v:50866$3314_Y
+ connect \$39 $and$libresoc.v:50867$3315_Y
+ connect \$41 $eq$libresoc.v:50868$3316_Y
+ connect \$43 $eq$libresoc.v:50869$3317_Y
+ connect \$45 $eq$libresoc.v:50870$3318_Y
+ connect \$47 $not$libresoc.v:50871$3319_Y
+ connect \$49 $and$libresoc.v:50872$3320_Y
+ connect \$51 $not$libresoc.v:50873$3321_Y
+ connect \$53 $and$libresoc.v:50874$3322_Y
+ connect \$55 $eq$libresoc.v:50875$3323_Y
+ connect \$57 $eq$libresoc.v:50876$3324_Y
+ connect \$5 $not$libresoc.v:50877$3325_Y
+ connect \$59 $eq$libresoc.v:50878$3326_Y
+ connect \$61 $not$libresoc.v:50879$3327_Y
+ connect \$63 $and$libresoc.v:50880$3328_Y
+ connect \$65 $not$libresoc.v:50881$3329_Y
+ connect \$67 $and$libresoc.v:50882$3330_Y
+ connect \$69 $eq$libresoc.v:50883$3331_Y
+ connect \$71 $eq$libresoc.v:50884$3332_Y
+ connect \$73 $eq$libresoc.v:50885$3333_Y
+ connect \$75 $not$libresoc.v:50886$3334_Y
+ connect \$77 $and$libresoc.v:50887$3335_Y
+ connect \$7 $and$libresoc.v:50888$3336_Y
+ connect \$79 $not$libresoc.v:50889$3337_Y
+ connect \$81 $and$libresoc.v:50890$3338_Y
+ connect \$83 $eq$libresoc.v:50891$3339_Y
+ connect \$85 $eq$libresoc.v:50892$3340_Y
+ connect \$87 $eq$libresoc.v:50893$3341_Y
+ connect \$89 $not$libresoc.v:50894$3342_Y
+ connect \$91 $and$libresoc.v:50895$3343_Y
+ connect \$93 $not$libresoc.v:50896$3344_Y
+ connect \$95 $and$libresoc.v:50897$3345_Y
+ connect \$97 $eq$libresoc.v:50898$3346_Y
+ connect \$117 \$118
connect \log_write_addr_o 0
connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000
connect \terminated_o \terminated
connect \icache_rst_o \do_icreset
connect \core_rst_o \do_reset
- connect \core_stop_o \$124
+ connect \core_stop_o \$126
connect \d_gpr_addr \gspr_index
connect \stat_reg \$1
end
-attribute \src "libresoc.v:51973.1-54017.10"
+attribute \src "libresoc.v:51323.1-53367.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec"
attribute \generator "nMigen"
module \dec
- attribute \src "libresoc.v:53578.3-53611.6"
+ attribute \src "libresoc.v:52928.3-52961.6"
wire width 3 $0\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53612.3-53645.6"
+ attribute \src "libresoc.v:52962.3-52995.6"
wire width 3 $0\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53238.3-53271.6"
+ attribute \src "libresoc.v:52588.3-52621.6"
wire width 2 $0\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53340.3-53373.6"
+ attribute \src "libresoc.v:52690.3-52723.6"
wire $0\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53442.3-53475.6"
+ attribute \src "libresoc.v:52792.3-52825.6"
wire width 13 $0\ALU_function_unit[12:0]
- attribute \src "libresoc.v:53510.3-53543.6"
+ attribute \src "libresoc.v:52860.3-52893.6"
wire width 3 $0\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53544.3-53577.6"
+ attribute \src "libresoc.v:52894.3-52927.6"
wire width 4 $0\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53476.3-53509.6"
+ attribute \src "libresoc.v:52826.3-52859.6"
wire width 7 $0\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53272.3-53305.6"
+ attribute \src "libresoc.v:52622.3-52655.6"
wire $0\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53306.3-53339.6"
+ attribute \src "libresoc.v:52656.3-52689.6"
wire $0\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53374.3-53407.6"
+ attribute \src "libresoc.v:52724.3-52757.6"
wire $0\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53646.3-53679.6"
+ attribute \src "libresoc.v:52996.3-53029.6"
wire width 4 $0\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53204.3-53237.6"
+ attribute \src "libresoc.v:52554.3-52587.6"
wire width 2 $0\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53408.3-53441.6"
+ attribute \src "libresoc.v:52758.3-52791.6"
wire $0\ALU_sgn[0:0]
- attribute \src "libresoc.v:51974.7-51974.20"
+ attribute \src "libresoc.v:51324.7-51324.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:53578.3-53611.6"
+ attribute \src "libresoc.v:52928.3-52961.6"
wire width 3 $1\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53612.3-53645.6"
+ attribute \src "libresoc.v:52962.3-52995.6"
wire width 3 $1\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53238.3-53271.6"
+ attribute \src "libresoc.v:52588.3-52621.6"
wire width 2 $1\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53340.3-53373.6"
+ attribute \src "libresoc.v:52690.3-52723.6"
wire $1\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53442.3-53475.6"
+ attribute \src "libresoc.v:52792.3-52825.6"
wire width 13 $1\ALU_function_unit[12:0]
- attribute \src "libresoc.v:53510.3-53543.6"
+ attribute \src "libresoc.v:52860.3-52893.6"
wire width 3 $1\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53544.3-53577.6"
+ attribute \src "libresoc.v:52894.3-52927.6"
wire width 4 $1\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53476.3-53509.6"
+ attribute \src "libresoc.v:52826.3-52859.6"
wire width 7 $1\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53272.3-53305.6"
+ attribute \src "libresoc.v:52622.3-52655.6"
wire $1\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53306.3-53339.6"
+ attribute \src "libresoc.v:52656.3-52689.6"
wire $1\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53374.3-53407.6"
+ attribute \src "libresoc.v:52724.3-52757.6"
wire $1\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53646.3-53679.6"
+ attribute \src "libresoc.v:52996.3-53029.6"
wire width 4 $1\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53204.3-53237.6"
+ attribute \src "libresoc.v:52554.3-52587.6"
wire width 2 $1\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53408.3-53441.6"
+ attribute \src "libresoc.v:52758.3-52791.6"
wire $1\ALU_sgn[0:0]
- attribute \src "libresoc.v:53169.17-53169.211"
- wire width 32 $ternary$libresoc.v:53169$3469_Y
+ attribute \src "libresoc.v:52519.17-52519.211"
+ wire width 32 $ternary$libresoc.v:52519$3442_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:51974.7-51974.15"
+ attribute \src "libresoc.v:51324.7-51324.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:53169$3469
+ cell $mux $ternary$libresoc.v:52519$3442
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:53169$3469_Y
+ connect \Y $ternary$libresoc.v:52519$3442_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:53170.13-53186.4"
+ attribute \src "libresoc.v:52520.13-52536.4"
cell \ALU_dec19 \ALU_dec19
connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in
connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out
connect \opcode_in \ALU_dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:53187.13-53203.4"
+ attribute \src "libresoc.v:52537.13-52553.4"
cell \ALU_dec31 \ALU_dec31
connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in
connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out
connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn
connect \opcode_in \ALU_dec31_opcode_in
end
- attribute \src "libresoc.v:51974.7-51974.20"
- process $proc$libresoc.v:51974$3484
+ attribute \src "libresoc.v:51324.7-51324.20"
+ process $proc$libresoc.v:51324$3457
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:53204.3-53237.6"
- process $proc$libresoc.v:53204$3470
+ attribute \src "libresoc.v:52554.3-52587.6"
+ process $proc$libresoc.v:52554$3443
assign { } { }
assign { } { }
assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0]
- attribute \src "libresoc.v:53205.5-53205.29"
+ attribute \src "libresoc.v:52555.5-52555.29"
switch \initial
- attribute \src "libresoc.v:53205.9-53205.17"
+ attribute \src "libresoc.v:52555.9-52555.17"
case 1'1
case
end
sync always
update \ALU_rc_sel $0\ALU_rc_sel[1:0]
end
- attribute \src "libresoc.v:53238.3-53271.6"
- process $proc$libresoc.v:53238$3471
+ attribute \src "libresoc.v:52588.3-52621.6"
+ process $proc$libresoc.v:52588$3444
assign { } { }
assign { } { }
assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0]
- attribute \src "libresoc.v:53239.5-53239.29"
+ attribute \src "libresoc.v:52589.5-52589.29"
switch \initial
- attribute \src "libresoc.v:53239.9-53239.17"
+ attribute \src "libresoc.v:52589.9-52589.17"
case 1'1
case
end
sync always
update \ALU_cry_in $0\ALU_cry_in[1:0]
end
- attribute \src "libresoc.v:53272.3-53305.6"
- process $proc$libresoc.v:53272$3472
+ attribute \src "libresoc.v:52622.3-52655.6"
+ process $proc$libresoc.v:52622$3445
assign { } { }
assign { } { }
assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0]
- attribute \src "libresoc.v:53273.5-53273.29"
+ attribute \src "libresoc.v:52623.5-52623.29"
switch \initial
- attribute \src "libresoc.v:53273.9-53273.17"
+ attribute \src "libresoc.v:52623.9-52623.17"
case 1'1
case
end
sync always
update \ALU_inv_a $0\ALU_inv_a[0:0]
end
- attribute \src "libresoc.v:53306.3-53339.6"
- process $proc$libresoc.v:53306$3473
+ attribute \src "libresoc.v:52656.3-52689.6"
+ process $proc$libresoc.v:52656$3446
assign { } { }
assign { } { }
assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0]
- attribute \src "libresoc.v:53307.5-53307.29"
+ attribute \src "libresoc.v:52657.5-52657.29"
switch \initial
- attribute \src "libresoc.v:53307.9-53307.17"
+ attribute \src "libresoc.v:52657.9-52657.17"
case 1'1
case
end
sync always
update \ALU_inv_out $0\ALU_inv_out[0:0]
end
- attribute \src "libresoc.v:53340.3-53373.6"
- process $proc$libresoc.v:53340$3474
+ attribute \src "libresoc.v:52690.3-52723.6"
+ process $proc$libresoc.v:52690$3447
assign { } { }
assign { } { }
assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0]
- attribute \src "libresoc.v:53341.5-53341.29"
+ attribute \src "libresoc.v:52691.5-52691.29"
switch \initial
- attribute \src "libresoc.v:53341.9-53341.17"
+ attribute \src "libresoc.v:52691.9-52691.17"
case 1'1
case
end
sync always
update \ALU_cry_out $0\ALU_cry_out[0:0]
end
- attribute \src "libresoc.v:53374.3-53407.6"
- process $proc$libresoc.v:53374$3475
+ attribute \src "libresoc.v:52724.3-52757.6"
+ process $proc$libresoc.v:52724$3448
assign { } { }
assign { } { }
assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0]
- attribute \src "libresoc.v:53375.5-53375.29"
+ attribute \src "libresoc.v:52725.5-52725.29"
switch \initial
- attribute \src "libresoc.v:53375.9-53375.17"
+ attribute \src "libresoc.v:52725.9-52725.17"
case 1'1
case
end
sync always
update \ALU_is_32b $0\ALU_is_32b[0:0]
end
- attribute \src "libresoc.v:53408.3-53441.6"
- process $proc$libresoc.v:53408$3476
+ attribute \src "libresoc.v:52758.3-52791.6"
+ process $proc$libresoc.v:52758$3449
assign { } { }
assign { } { }
assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0]
- attribute \src "libresoc.v:53409.5-53409.29"
+ attribute \src "libresoc.v:52759.5-52759.29"
switch \initial
- attribute \src "libresoc.v:53409.9-53409.17"
+ attribute \src "libresoc.v:52759.9-52759.17"
case 1'1
case
end
sync always
update \ALU_sgn $0\ALU_sgn[0:0]
end
- attribute \src "libresoc.v:53442.3-53475.6"
- process $proc$libresoc.v:53442$3477
+ attribute \src "libresoc.v:52792.3-52825.6"
+ process $proc$libresoc.v:52792$3450
assign { } { }
assign { } { }
assign $0\ALU_function_unit[12:0] $1\ALU_function_unit[12:0]
- attribute \src "libresoc.v:53443.5-53443.29"
+ attribute \src "libresoc.v:52793.5-52793.29"
switch \initial
- attribute \src "libresoc.v:53443.9-53443.17"
+ attribute \src "libresoc.v:52793.9-52793.17"
case 1'1
case
end
sync always
update \ALU_function_unit $0\ALU_function_unit[12:0]
end
- attribute \src "libresoc.v:53476.3-53509.6"
- process $proc$libresoc.v:53476$3478
+ attribute \src "libresoc.v:52826.3-52859.6"
+ process $proc$libresoc.v:52826$3451
assign { } { }
assign { } { }
assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0]
- attribute \src "libresoc.v:53477.5-53477.29"
+ attribute \src "libresoc.v:52827.5-52827.29"
switch \initial
- attribute \src "libresoc.v:53477.9-53477.17"
+ attribute \src "libresoc.v:52827.9-52827.17"
case 1'1
case
end
sync always
update \ALU_internal_op $0\ALU_internal_op[6:0]
end
- attribute \src "libresoc.v:53510.3-53543.6"
- process $proc$libresoc.v:53510$3479
+ attribute \src "libresoc.v:52860.3-52893.6"
+ process $proc$libresoc.v:52860$3452
assign { } { }
assign { } { }
assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0]
- attribute \src "libresoc.v:53511.5-53511.29"
+ attribute \src "libresoc.v:52861.5-52861.29"
switch \initial
- attribute \src "libresoc.v:53511.9-53511.17"
+ attribute \src "libresoc.v:52861.9-52861.17"
case 1'1
case
end
sync always
update \ALU_in1_sel $0\ALU_in1_sel[2:0]
end
- attribute \src "libresoc.v:53544.3-53577.6"
- process $proc$libresoc.v:53544$3480
+ attribute \src "libresoc.v:52894.3-52927.6"
+ process $proc$libresoc.v:52894$3453
assign { } { }
assign { } { }
assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0]
- attribute \src "libresoc.v:53545.5-53545.29"
+ attribute \src "libresoc.v:52895.5-52895.29"
switch \initial
- attribute \src "libresoc.v:53545.9-53545.17"
+ attribute \src "libresoc.v:52895.9-52895.17"
case 1'1
case
end
sync always
update \ALU_in2_sel $0\ALU_in2_sel[3:0]
end
- attribute \src "libresoc.v:53578.3-53611.6"
- process $proc$libresoc.v:53578$3481
+ attribute \src "libresoc.v:52928.3-52961.6"
+ process $proc$libresoc.v:52928$3454
assign { } { }
assign { } { }
assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0]
- attribute \src "libresoc.v:53579.5-53579.29"
+ attribute \src "libresoc.v:52929.5-52929.29"
switch \initial
- attribute \src "libresoc.v:53579.9-53579.17"
+ attribute \src "libresoc.v:52929.9-52929.17"
case 1'1
case
end
sync always
update \ALU_cr_in $0\ALU_cr_in[2:0]
end
- attribute \src "libresoc.v:53612.3-53645.6"
- process $proc$libresoc.v:53612$3482
+ attribute \src "libresoc.v:52962.3-52995.6"
+ process $proc$libresoc.v:52962$3455
assign { } { }
assign { } { }
assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0]
- attribute \src "libresoc.v:53613.5-53613.29"
+ attribute \src "libresoc.v:52963.5-52963.29"
switch \initial
- attribute \src "libresoc.v:53613.9-53613.17"
+ attribute \src "libresoc.v:52963.9-52963.17"
case 1'1
case
end
sync always
update \ALU_cr_out $0\ALU_cr_out[2:0]
end
- attribute \src "libresoc.v:53646.3-53679.6"
- process $proc$libresoc.v:53646$3483
+ attribute \src "libresoc.v:52996.3-53029.6"
+ process $proc$libresoc.v:52996$3456
assign { } { }
assign { } { }
assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0]
- attribute \src "libresoc.v:53647.5-53647.29"
+ attribute \src "libresoc.v:52997.5-52997.29"
switch \initial
- attribute \src "libresoc.v:53647.9-53647.17"
+ attribute \src "libresoc.v:52997.9-52997.17"
case 1'1
case
end
sync always
update \ALU_ldst_len $0\ALU_ldst_len[3:0]
end
- connect \$1 $ternary$libresoc.v:53169$3469_Y
+ connect \$1 $ternary$libresoc.v:52519$3442_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \ALU_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:54021.1-55480.10"
+attribute \src "libresoc.v:53371.1-54830.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec"
attribute \generator "nMigen"
module \dec$138
- attribute \src "libresoc.v:55104.3-55116.6"
+ attribute \src "libresoc.v:54454.3-54466.6"
wire width 3 $0\CR_cr_in[2:0]
- attribute \src "libresoc.v:55117.3-55129.6"
+ attribute \src "libresoc.v:54467.3-54479.6"
wire width 3 $0\CR_cr_out[2:0]
- attribute \src "libresoc.v:55078.3-55090.6"
+ attribute \src "libresoc.v:54428.3-54440.6"
wire width 13 $0\CR_function_unit[12:0]
- attribute \src "libresoc.v:55091.3-55103.6"
+ attribute \src "libresoc.v:54441.3-54453.6"
wire width 7 $0\CR_internal_op[6:0]
- attribute \src "libresoc.v:55130.3-55142.6"
+ attribute \src "libresoc.v:54480.3-54492.6"
wire width 2 $0\CR_rc_sel[1:0]
- attribute \src "libresoc.v:54022.7-54022.20"
+ attribute \src "libresoc.v:53372.7-53372.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:55104.3-55116.6"
+ attribute \src "libresoc.v:54454.3-54466.6"
wire width 3 $1\CR_cr_in[2:0]
- attribute \src "libresoc.v:55117.3-55129.6"
+ attribute \src "libresoc.v:54467.3-54479.6"
wire width 3 $1\CR_cr_out[2:0]
- attribute \src "libresoc.v:55078.3-55090.6"
+ attribute \src "libresoc.v:54428.3-54440.6"
wire width 13 $1\CR_function_unit[12:0]
- attribute \src "libresoc.v:55091.3-55103.6"
+ attribute \src "libresoc.v:54441.3-54453.6"
wire width 7 $1\CR_internal_op[6:0]
- attribute \src "libresoc.v:55130.3-55142.6"
+ attribute \src "libresoc.v:54480.3-54492.6"
wire width 2 $1\CR_rc_sel[1:0]
- attribute \src "libresoc.v:55061.17-55061.211"
- wire width 32 $ternary$libresoc.v:55061$3485_Y
+ attribute \src "libresoc.v:54411.17-54411.211"
+ wire width 32 $ternary$libresoc.v:54411$3458_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:54022.7-54022.15"
+ attribute \src "libresoc.v:53372.7-53372.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 10 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:55061$3485
+ cell $mux $ternary$libresoc.v:54411$3458
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:55061$3485_Y
+ connect \Y $ternary$libresoc.v:54411$3458_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:55062.12-55069.4"
+ attribute \src "libresoc.v:54412.12-54419.4"
cell \CR_dec19 \CR_dec19
connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in
connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out
connect \opcode_in \CR_dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:55070.12-55077.4"
+ attribute \src "libresoc.v:54420.12-54427.4"
cell \CR_dec31 \CR_dec31
connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in
connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out
connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel
connect \opcode_in \CR_dec31_opcode_in
end
- attribute \src "libresoc.v:54022.7-54022.20"
- process $proc$libresoc.v:54022$3491
+ attribute \src "libresoc.v:53372.7-53372.20"
+ process $proc$libresoc.v:53372$3464
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:55078.3-55090.6"
- process $proc$libresoc.v:55078$3486
+ attribute \src "libresoc.v:54428.3-54440.6"
+ process $proc$libresoc.v:54428$3459
assign { } { }
assign { } { }
assign $0\CR_function_unit[12:0] $1\CR_function_unit[12:0]
- attribute \src "libresoc.v:55079.5-55079.29"
+ attribute \src "libresoc.v:54429.5-54429.29"
switch \initial
- attribute \src "libresoc.v:55079.9-55079.17"
+ attribute \src "libresoc.v:54429.9-54429.17"
case 1'1
case
end
sync always
update \CR_function_unit $0\CR_function_unit[12:0]
end
- attribute \src "libresoc.v:55091.3-55103.6"
- process $proc$libresoc.v:55091$3487
+ attribute \src "libresoc.v:54441.3-54453.6"
+ process $proc$libresoc.v:54441$3460
assign { } { }
assign { } { }
assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0]
- attribute \src "libresoc.v:55092.5-55092.29"
+ attribute \src "libresoc.v:54442.5-54442.29"
switch \initial
- attribute \src "libresoc.v:55092.9-55092.17"
+ attribute \src "libresoc.v:54442.9-54442.17"
case 1'1
case
end
sync always
update \CR_internal_op $0\CR_internal_op[6:0]
end
- attribute \src "libresoc.v:55104.3-55116.6"
- process $proc$libresoc.v:55104$3488
+ attribute \src "libresoc.v:54454.3-54466.6"
+ process $proc$libresoc.v:54454$3461
assign { } { }
assign { } { }
assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0]
- attribute \src "libresoc.v:55105.5-55105.29"
+ attribute \src "libresoc.v:54455.5-54455.29"
switch \initial
- attribute \src "libresoc.v:55105.9-55105.17"
+ attribute \src "libresoc.v:54455.9-54455.17"
case 1'1
case
end
sync always
update \CR_cr_in $0\CR_cr_in[2:0]
end
- attribute \src "libresoc.v:55117.3-55129.6"
- process $proc$libresoc.v:55117$3489
+ attribute \src "libresoc.v:54467.3-54479.6"
+ process $proc$libresoc.v:54467$3462
assign { } { }
assign { } { }
assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0]
- attribute \src "libresoc.v:55118.5-55118.29"
+ attribute \src "libresoc.v:54468.5-54468.29"
switch \initial
- attribute \src "libresoc.v:55118.9-55118.17"
+ attribute \src "libresoc.v:54468.9-54468.17"
case 1'1
case
end
sync always
update \CR_cr_out $0\CR_cr_out[2:0]
end
- attribute \src "libresoc.v:55130.3-55142.6"
- process $proc$libresoc.v:55130$3490
+ attribute \src "libresoc.v:54480.3-54492.6"
+ process $proc$libresoc.v:54480$3463
assign { } { }
assign { } { }
assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0]
- attribute \src "libresoc.v:55131.5-55131.29"
+ attribute \src "libresoc.v:54481.5-54481.29"
switch \initial
- attribute \src "libresoc.v:55131.9-55131.17"
+ attribute \src "libresoc.v:54481.9-54481.17"
case 1'1
case
end
sync always
update \CR_rc_sel $0\CR_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:55061$3485_Y
+ connect \$1 $ternary$libresoc.v:54411$3458_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \CR_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:55484.1-56925.10"
+attribute \src "libresoc.v:54834.1-56275.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec"
attribute \generator "nMigen"
module \dec$141
- attribute \src "libresoc.v:56509.3-56524.6"
+ attribute \src "libresoc.v:55859.3-55874.6"
wire width 3 $0\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56525.3-56540.6"
+ attribute \src "libresoc.v:55875.3-55890.6"
wire width 3 $0\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56461.3-56476.6"
+ attribute \src "libresoc.v:55811.3-55826.6"
wire width 13 $0\BRANCH_function_unit[12:0]
- attribute \src "libresoc.v:56493.3-56508.6"
+ attribute \src "libresoc.v:55843.3-55858.6"
wire width 4 $0\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56477.3-56492.6"
+ attribute \src "libresoc.v:55827.3-55842.6"
wire width 7 $0\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56557.3-56572.6"
+ attribute \src "libresoc.v:55907.3-55922.6"
wire $0\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56573.3-56588.6"
+ attribute \src "libresoc.v:55923.3-55938.6"
wire $0\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56541.3-56556.6"
+ attribute \src "libresoc.v:55891.3-55906.6"
wire width 2 $0\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:55485.7-55485.20"
+ attribute \src "libresoc.v:54835.7-54835.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:56509.3-56524.6"
+ attribute \src "libresoc.v:55859.3-55874.6"
wire width 3 $1\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56525.3-56540.6"
+ attribute \src "libresoc.v:55875.3-55890.6"
wire width 3 $1\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56461.3-56476.6"
+ attribute \src "libresoc.v:55811.3-55826.6"
wire width 13 $1\BRANCH_function_unit[12:0]
- attribute \src "libresoc.v:56493.3-56508.6"
+ attribute \src "libresoc.v:55843.3-55858.6"
wire width 4 $1\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56477.3-56492.6"
+ attribute \src "libresoc.v:55827.3-55842.6"
wire width 7 $1\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56557.3-56572.6"
+ attribute \src "libresoc.v:55907.3-55922.6"
wire $1\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56573.3-56588.6"
+ attribute \src "libresoc.v:55923.3-55938.6"
wire $1\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56541.3-56556.6"
+ attribute \src "libresoc.v:55891.3-55906.6"
wire width 2 $1\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:56449.17-56449.211"
- wire width 32 $ternary$libresoc.v:56449$3492_Y
+ attribute \src "libresoc.v:55799.17-55799.211"
+ wire width 32 $ternary$libresoc.v:55799$3465_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:55485.7-55485.15"
+ attribute \src "libresoc.v:54835.7-54835.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 21 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:56449$3492
+ cell $mux $ternary$libresoc.v:55799$3465
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:56449$3492_Y
+ connect \Y $ternary$libresoc.v:55799$3465_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:56450.16-56460.4"
+ attribute \src "libresoc.v:55800.16-55810.4"
cell \BRANCH_dec19 \BRANCH_dec19
connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in
connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out
connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel
connect \opcode_in \BRANCH_dec19_opcode_in
end
- attribute \src "libresoc.v:55485.7-55485.20"
- process $proc$libresoc.v:55485$3501
+ attribute \src "libresoc.v:54835.7-54835.20"
+ process $proc$libresoc.v:54835$3474
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:56461.3-56476.6"
- process $proc$libresoc.v:56461$3493
+ attribute \src "libresoc.v:55811.3-55826.6"
+ process $proc$libresoc.v:55811$3466
assign { } { }
assign { } { }
assign $0\BRANCH_function_unit[12:0] $1\BRANCH_function_unit[12:0]
- attribute \src "libresoc.v:56462.5-56462.29"
+ attribute \src "libresoc.v:55812.5-55812.29"
switch \initial
- attribute \src "libresoc.v:56462.9-56462.17"
+ attribute \src "libresoc.v:55812.9-55812.17"
case 1'1
case
end
sync always
update \BRANCH_function_unit $0\BRANCH_function_unit[12:0]
end
- attribute \src "libresoc.v:56477.3-56492.6"
- process $proc$libresoc.v:56477$3494
+ attribute \src "libresoc.v:55827.3-55842.6"
+ process $proc$libresoc.v:55827$3467
assign { } { }
assign { } { }
assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0]
- attribute \src "libresoc.v:56478.5-56478.29"
+ attribute \src "libresoc.v:55828.5-55828.29"
switch \initial
- attribute \src "libresoc.v:56478.9-56478.17"
+ attribute \src "libresoc.v:55828.9-55828.17"
case 1'1
case
end
sync always
update \BRANCH_internal_op $0\BRANCH_internal_op[6:0]
end
- attribute \src "libresoc.v:56493.3-56508.6"
- process $proc$libresoc.v:56493$3495
+ attribute \src "libresoc.v:55843.3-55858.6"
+ process $proc$libresoc.v:55843$3468
assign { } { }
assign { } { }
assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0]
- attribute \src "libresoc.v:56494.5-56494.29"
+ attribute \src "libresoc.v:55844.5-55844.29"
switch \initial
- attribute \src "libresoc.v:56494.9-56494.17"
+ attribute \src "libresoc.v:55844.9-55844.17"
case 1'1
case
end
sync always
update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0]
end
- attribute \src "libresoc.v:56509.3-56524.6"
- process $proc$libresoc.v:56509$3496
+ attribute \src "libresoc.v:55859.3-55874.6"
+ process $proc$libresoc.v:55859$3469
assign { } { }
assign { } { }
assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0]
- attribute \src "libresoc.v:56510.5-56510.29"
+ attribute \src "libresoc.v:55860.5-55860.29"
switch \initial
- attribute \src "libresoc.v:56510.9-56510.17"
+ attribute \src "libresoc.v:55860.9-55860.17"
case 1'1
case
end
sync always
update \BRANCH_cr_in $0\BRANCH_cr_in[2:0]
end
- attribute \src "libresoc.v:56525.3-56540.6"
- process $proc$libresoc.v:56525$3497
+ attribute \src "libresoc.v:55875.3-55890.6"
+ process $proc$libresoc.v:55875$3470
assign { } { }
assign { } { }
assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0]
- attribute \src "libresoc.v:56526.5-56526.29"
+ attribute \src "libresoc.v:55876.5-55876.29"
switch \initial
- attribute \src "libresoc.v:56526.9-56526.17"
+ attribute \src "libresoc.v:55876.9-55876.17"
case 1'1
case
end
sync always
update \BRANCH_cr_out $0\BRANCH_cr_out[2:0]
end
- attribute \src "libresoc.v:56541.3-56556.6"
- process $proc$libresoc.v:56541$3498
+ attribute \src "libresoc.v:55891.3-55906.6"
+ process $proc$libresoc.v:55891$3471
assign { } { }
assign { } { }
assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0]
- attribute \src "libresoc.v:56542.5-56542.29"
+ attribute \src "libresoc.v:55892.5-55892.29"
switch \initial
- attribute \src "libresoc.v:56542.9-56542.17"
+ attribute \src "libresoc.v:55892.9-55892.17"
case 1'1
case
end
sync always
update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0]
end
- attribute \src "libresoc.v:56557.3-56572.6"
- process $proc$libresoc.v:56557$3499
+ attribute \src "libresoc.v:55907.3-55922.6"
+ process $proc$libresoc.v:55907$3472
assign { } { }
assign { } { }
assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0]
- attribute \src "libresoc.v:56558.5-56558.29"
+ attribute \src "libresoc.v:55908.5-55908.29"
switch \initial
- attribute \src "libresoc.v:56558.9-56558.17"
+ attribute \src "libresoc.v:55908.9-55908.17"
case 1'1
case
end
sync always
update \BRANCH_is_32b $0\BRANCH_is_32b[0:0]
end
- attribute \src "libresoc.v:56573.3-56588.6"
- process $proc$libresoc.v:56573$3500
+ attribute \src "libresoc.v:55923.3-55938.6"
+ process $proc$libresoc.v:55923$3473
assign { } { }
assign { } { }
assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0]
- attribute \src "libresoc.v:56574.5-56574.29"
+ attribute \src "libresoc.v:55924.5-55924.29"
switch \initial
- attribute \src "libresoc.v:56574.9-56574.17"
+ attribute \src "libresoc.v:55924.9-55924.17"
case 1'1
case
end
sync always
update \BRANCH_lk $0\BRANCH_lk[0:0]
end
- connect \$1 $ternary$libresoc.v:56449$3492_Y
+ connect \$1 $ternary$libresoc.v:55799$3465_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \BRANCH_dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:56929.1-58702.10"
+attribute \src "libresoc.v:56279.1-58052.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec"
attribute \generator "nMigen"
module \dec$145
- attribute \src "libresoc.v:58254.3-58281.6"
+ attribute \src "libresoc.v:57604.3-57631.6"
wire width 3 $0\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58282.3-58309.6"
+ attribute \src "libresoc.v:57632.3-57659.6"
wire width 3 $0\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:57974.3-58001.6"
+ attribute \src "libresoc.v:57324.3-57351.6"
wire width 2 $0\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:58058.3-58085.6"
+ attribute \src "libresoc.v:57408.3-57435.6"
wire $0\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:58142.3-58169.6"
+ attribute \src "libresoc.v:57492.3-57519.6"
wire width 13 $0\LOGICAL_function_unit[12:0]
- attribute \src "libresoc.v:58198.3-58225.6"
+ attribute \src "libresoc.v:57548.3-57575.6"
wire width 3 $0\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58226.3-58253.6"
+ attribute \src "libresoc.v:57576.3-57603.6"
wire width 4 $0\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58170.3-58197.6"
+ attribute \src "libresoc.v:57520.3-57547.6"
wire width 7 $0\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:58002.3-58029.6"
+ attribute \src "libresoc.v:57352.3-57379.6"
wire $0\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:58030.3-58057.6"
+ attribute \src "libresoc.v:57380.3-57407.6"
wire $0\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:58086.3-58113.6"
+ attribute \src "libresoc.v:57436.3-57463.6"
wire $0\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:58310.3-58337.6"
+ attribute \src "libresoc.v:57660.3-57687.6"
wire width 4 $0\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58338.3-58365.6"
+ attribute \src "libresoc.v:57688.3-57715.6"
wire width 2 $0\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:58114.3-58141.6"
+ attribute \src "libresoc.v:57464.3-57491.6"
wire $0\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:56930.7-56930.20"
+ attribute \src "libresoc.v:56280.7-56280.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:58254.3-58281.6"
+ attribute \src "libresoc.v:57604.3-57631.6"
wire width 3 $1\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58282.3-58309.6"
+ attribute \src "libresoc.v:57632.3-57659.6"
wire width 3 $1\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:57974.3-58001.6"
+ attribute \src "libresoc.v:57324.3-57351.6"
wire width 2 $1\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:58058.3-58085.6"
+ attribute \src "libresoc.v:57408.3-57435.6"
wire $1\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:58142.3-58169.6"
+ attribute \src "libresoc.v:57492.3-57519.6"
wire width 13 $1\LOGICAL_function_unit[12:0]
- attribute \src "libresoc.v:58198.3-58225.6"
+ attribute \src "libresoc.v:57548.3-57575.6"
wire width 3 $1\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58226.3-58253.6"
+ attribute \src "libresoc.v:57576.3-57603.6"
wire width 4 $1\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58170.3-58197.6"
+ attribute \src "libresoc.v:57520.3-57547.6"
wire width 7 $1\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:58002.3-58029.6"
+ attribute \src "libresoc.v:57352.3-57379.6"
wire $1\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:58030.3-58057.6"
+ attribute \src "libresoc.v:57380.3-57407.6"
wire $1\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:58086.3-58113.6"
+ attribute \src "libresoc.v:57436.3-57463.6"
wire $1\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:58310.3-58337.6"
+ attribute \src "libresoc.v:57660.3-57687.6"
wire width 4 $1\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58338.3-58365.6"
+ attribute \src "libresoc.v:57688.3-57715.6"
wire width 2 $1\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:58114.3-58141.6"
+ attribute \src "libresoc.v:57464.3-57491.6"
wire $1\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:57956.17-57956.211"
- wire width 32 $ternary$libresoc.v:57956$3502_Y
+ attribute \src "libresoc.v:57306.17-57306.211"
+ wire width 32 $ternary$libresoc.v:57306$3475_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:56930.7-56930.15"
+ attribute \src "libresoc.v:56280.7-56280.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:57956$3502
+ cell $mux $ternary$libresoc.v:57306$3475
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:57956$3502_Y
+ connect \Y $ternary$libresoc.v:57306$3475_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:57957.17-57973.4"
+ attribute \src "libresoc.v:57307.17-57323.4"
cell \LOGICAL_dec31 \LOGICAL_dec31
connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in
connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out
connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn
connect \opcode_in \LOGICAL_dec31_opcode_in
end
- attribute \src "libresoc.v:56930.7-56930.20"
- process $proc$libresoc.v:56930$3517
+ attribute \src "libresoc.v:56280.7-56280.20"
+ process $proc$libresoc.v:56280$3490
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:57974.3-58001.6"
- process $proc$libresoc.v:57974$3503
+ attribute \src "libresoc.v:57324.3-57351.6"
+ process $proc$libresoc.v:57324$3476
assign { } { }
assign { } { }
assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0]
- attribute \src "libresoc.v:57975.5-57975.29"
+ attribute \src "libresoc.v:57325.5-57325.29"
switch \initial
- attribute \src "libresoc.v:57975.9-57975.17"
+ attribute \src "libresoc.v:57325.9-57325.17"
case 1'1
case
end
sync always
update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0]
end
- attribute \src "libresoc.v:58002.3-58029.6"
- process $proc$libresoc.v:58002$3504
+ attribute \src "libresoc.v:57352.3-57379.6"
+ process $proc$libresoc.v:57352$3477
assign { } { }
assign { } { }
assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0]
- attribute \src "libresoc.v:58003.5-58003.29"
+ attribute \src "libresoc.v:57353.5-57353.29"
switch \initial
- attribute \src "libresoc.v:58003.9-58003.17"
+ attribute \src "libresoc.v:57353.9-57353.17"
case 1'1
case
end
sync always
update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0]
end
- attribute \src "libresoc.v:58030.3-58057.6"
- process $proc$libresoc.v:58030$3505
+ attribute \src "libresoc.v:57380.3-57407.6"
+ process $proc$libresoc.v:57380$3478
assign { } { }
assign { } { }
assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0]
- attribute \src "libresoc.v:58031.5-58031.29"
+ attribute \src "libresoc.v:57381.5-57381.29"
switch \initial
- attribute \src "libresoc.v:58031.9-58031.17"
+ attribute \src "libresoc.v:57381.9-57381.17"
case 1'1
case
end
sync always
update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0]
end
- attribute \src "libresoc.v:58058.3-58085.6"
- process $proc$libresoc.v:58058$3506
+ attribute \src "libresoc.v:57408.3-57435.6"
+ process $proc$libresoc.v:57408$3479
assign { } { }
assign { } { }
assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0]
- attribute \src "libresoc.v:58059.5-58059.29"
+ attribute \src "libresoc.v:57409.5-57409.29"
switch \initial
- attribute \src "libresoc.v:58059.9-58059.17"
+ attribute \src "libresoc.v:57409.9-57409.17"
case 1'1
case
end
sync always
update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0]
end
- attribute \src "libresoc.v:58086.3-58113.6"
- process $proc$libresoc.v:58086$3507
+ attribute \src "libresoc.v:57436.3-57463.6"
+ process $proc$libresoc.v:57436$3480
assign { } { }
assign { } { }
assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0]
- attribute \src "libresoc.v:58087.5-58087.29"
+ attribute \src "libresoc.v:57437.5-57437.29"
switch \initial
- attribute \src "libresoc.v:58087.9-58087.17"
+ attribute \src "libresoc.v:57437.9-57437.17"
case 1'1
case
end
sync always
update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0]
end
- attribute \src "libresoc.v:58114.3-58141.6"
- process $proc$libresoc.v:58114$3508
+ attribute \src "libresoc.v:57464.3-57491.6"
+ process $proc$libresoc.v:57464$3481
assign { } { }
assign { } { }
assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0]
- attribute \src "libresoc.v:58115.5-58115.29"
+ attribute \src "libresoc.v:57465.5-57465.29"
switch \initial
- attribute \src "libresoc.v:58115.9-58115.17"
+ attribute \src "libresoc.v:57465.9-57465.17"
case 1'1
case
end
sync always
update \LOGICAL_sgn $0\LOGICAL_sgn[0:0]
end
- attribute \src "libresoc.v:58142.3-58169.6"
- process $proc$libresoc.v:58142$3509
+ attribute \src "libresoc.v:57492.3-57519.6"
+ process $proc$libresoc.v:57492$3482
assign { } { }
assign { } { }
assign $0\LOGICAL_function_unit[12:0] $1\LOGICAL_function_unit[12:0]
- attribute \src "libresoc.v:58143.5-58143.29"
+ attribute \src "libresoc.v:57493.5-57493.29"
switch \initial
- attribute \src "libresoc.v:58143.9-58143.17"
+ attribute \src "libresoc.v:57493.9-57493.17"
case 1'1
case
end
sync always
update \LOGICAL_function_unit $0\LOGICAL_function_unit[12:0]
end
- attribute \src "libresoc.v:58170.3-58197.6"
- process $proc$libresoc.v:58170$3510
+ attribute \src "libresoc.v:57520.3-57547.6"
+ process $proc$libresoc.v:57520$3483
assign { } { }
assign { } { }
assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0]
- attribute \src "libresoc.v:58171.5-58171.29"
+ attribute \src "libresoc.v:57521.5-57521.29"
switch \initial
- attribute \src "libresoc.v:58171.9-58171.17"
+ attribute \src "libresoc.v:57521.9-57521.17"
case 1'1
case
end
sync always
update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0]
end
- attribute \src "libresoc.v:58198.3-58225.6"
- process $proc$libresoc.v:58198$3511
+ attribute \src "libresoc.v:57548.3-57575.6"
+ process $proc$libresoc.v:57548$3484
assign { } { }
assign { } { }
assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0]
- attribute \src "libresoc.v:58199.5-58199.29"
+ attribute \src "libresoc.v:57549.5-57549.29"
switch \initial
- attribute \src "libresoc.v:58199.9-58199.17"
+ attribute \src "libresoc.v:57549.9-57549.17"
case 1'1
case
end
sync always
update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0]
end
- attribute \src "libresoc.v:58226.3-58253.6"
- process $proc$libresoc.v:58226$3512
+ attribute \src "libresoc.v:57576.3-57603.6"
+ process $proc$libresoc.v:57576$3485
assign { } { }
assign { } { }
assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0]
- attribute \src "libresoc.v:58227.5-58227.29"
+ attribute \src "libresoc.v:57577.5-57577.29"
switch \initial
- attribute \src "libresoc.v:58227.9-58227.17"
+ attribute \src "libresoc.v:57577.9-57577.17"
case 1'1
case
end
sync always
update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0]
end
- attribute \src "libresoc.v:58254.3-58281.6"
- process $proc$libresoc.v:58254$3513
+ attribute \src "libresoc.v:57604.3-57631.6"
+ process $proc$libresoc.v:57604$3486
assign { } { }
assign { } { }
assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0]
- attribute \src "libresoc.v:58255.5-58255.29"
+ attribute \src "libresoc.v:57605.5-57605.29"
switch \initial
- attribute \src "libresoc.v:58255.9-58255.17"
+ attribute \src "libresoc.v:57605.9-57605.17"
case 1'1
case
end
sync always
update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0]
end
- attribute \src "libresoc.v:58282.3-58309.6"
- process $proc$libresoc.v:58282$3514
+ attribute \src "libresoc.v:57632.3-57659.6"
+ process $proc$libresoc.v:57632$3487
assign { } { }
assign { } { }
assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0]
- attribute \src "libresoc.v:58283.5-58283.29"
+ attribute \src "libresoc.v:57633.5-57633.29"
switch \initial
- attribute \src "libresoc.v:58283.9-58283.17"
+ attribute \src "libresoc.v:57633.9-57633.17"
case 1'1
case
end
sync always
update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0]
end
- attribute \src "libresoc.v:58310.3-58337.6"
- process $proc$libresoc.v:58310$3515
+ attribute \src "libresoc.v:57660.3-57687.6"
+ process $proc$libresoc.v:57660$3488
assign { } { }
assign { } { }
assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0]
- attribute \src "libresoc.v:58311.5-58311.29"
+ attribute \src "libresoc.v:57661.5-57661.29"
switch \initial
- attribute \src "libresoc.v:58311.9-58311.17"
+ attribute \src "libresoc.v:57661.9-57661.17"
case 1'1
case
end
sync always
update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0]
end
- attribute \src "libresoc.v:58338.3-58365.6"
- process $proc$libresoc.v:58338$3516
+ attribute \src "libresoc.v:57688.3-57715.6"
+ process $proc$libresoc.v:57688$3489
assign { } { }
assign { } { }
assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0]
- attribute \src "libresoc.v:58339.5-58339.29"
+ attribute \src "libresoc.v:57689.5-57689.29"
switch \initial
- attribute \src "libresoc.v:58339.9-58339.17"
+ attribute \src "libresoc.v:57689.9-57689.17"
case 1'1
case
end
sync always
update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:57956$3502_Y
+ connect \$1 $ternary$libresoc.v:57306$3475_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \LOGICAL_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:58706.1-60037.10"
+attribute \src "libresoc.v:58056.1-59387.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec"
attribute \generator "nMigen"
module \dec$150
- attribute \src "libresoc.v:59661.3-59670.6"
+ attribute \src "libresoc.v:59011.3-59020.6"
wire width 3 $0\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59671.3-59680.6"
+ attribute \src "libresoc.v:59021.3-59030.6"
wire width 3 $0\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59641.3-59650.6"
+ attribute \src "libresoc.v:58991.3-59000.6"
wire width 13 $0\SPR_function_unit[12:0]
- attribute \src "libresoc.v:59651.3-59660.6"
+ attribute \src "libresoc.v:59001.3-59010.6"
wire width 7 $0\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59691.3-59700.6"
+ attribute \src "libresoc.v:59041.3-59050.6"
wire $0\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59681.3-59690.6"
+ attribute \src "libresoc.v:59031.3-59040.6"
wire width 2 $0\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:58707.7-58707.20"
+ attribute \src "libresoc.v:58057.7-58057.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:59661.3-59670.6"
+ attribute \src "libresoc.v:59011.3-59020.6"
wire width 3 $1\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59671.3-59680.6"
+ attribute \src "libresoc.v:59021.3-59030.6"
wire width 3 $1\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59641.3-59650.6"
+ attribute \src "libresoc.v:58991.3-59000.6"
wire width 13 $1\SPR_function_unit[12:0]
- attribute \src "libresoc.v:59651.3-59660.6"
+ attribute \src "libresoc.v:59001.3-59010.6"
wire width 7 $1\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59691.3-59700.6"
+ attribute \src "libresoc.v:59041.3-59050.6"
wire $1\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59681.3-59690.6"
+ attribute \src "libresoc.v:59031.3-59040.6"
wire width 2 $1\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:59631.17-59631.211"
- wire width 32 $ternary$libresoc.v:59631$3518_Y
+ attribute \src "libresoc.v:58981.17-58981.211"
+ wire width 32 $ternary$libresoc.v:58981$3491_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:58707.7-58707.15"
+ attribute \src "libresoc.v:58057.7-58057.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 11 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:59631$3518
+ cell $mux $ternary$libresoc.v:58981$3491
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:59631$3518_Y
+ connect \Y $ternary$libresoc.v:58981$3491_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:59632.13-59640.4"
+ attribute \src "libresoc.v:58982.13-58990.4"
cell \SPR_dec31 \SPR_dec31
connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in
connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out
connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel
connect \opcode_in \SPR_dec31_opcode_in
end
- attribute \src "libresoc.v:58707.7-58707.20"
- process $proc$libresoc.v:58707$3525
+ attribute \src "libresoc.v:58057.7-58057.20"
+ process $proc$libresoc.v:58057$3498
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:59641.3-59650.6"
- process $proc$libresoc.v:59641$3519
+ attribute \src "libresoc.v:58991.3-59000.6"
+ process $proc$libresoc.v:58991$3492
assign { } { }
assign { } { }
assign $0\SPR_function_unit[12:0] $1\SPR_function_unit[12:0]
- attribute \src "libresoc.v:59642.5-59642.29"
+ attribute \src "libresoc.v:58992.5-58992.29"
switch \initial
- attribute \src "libresoc.v:59642.9-59642.17"
+ attribute \src "libresoc.v:58992.9-58992.17"
case 1'1
case
end
sync always
update \SPR_function_unit $0\SPR_function_unit[12:0]
end
- attribute \src "libresoc.v:59651.3-59660.6"
- process $proc$libresoc.v:59651$3520
+ attribute \src "libresoc.v:59001.3-59010.6"
+ process $proc$libresoc.v:59001$3493
assign { } { }
assign { } { }
assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0]
- attribute \src "libresoc.v:59652.5-59652.29"
+ attribute \src "libresoc.v:59002.5-59002.29"
switch \initial
- attribute \src "libresoc.v:59652.9-59652.17"
+ attribute \src "libresoc.v:59002.9-59002.17"
case 1'1
case
end
sync always
update \SPR_internal_op $0\SPR_internal_op[6:0]
end
- attribute \src "libresoc.v:59661.3-59670.6"
- process $proc$libresoc.v:59661$3521
+ attribute \src "libresoc.v:59011.3-59020.6"
+ process $proc$libresoc.v:59011$3494
assign { } { }
assign { } { }
assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0]
- attribute \src "libresoc.v:59662.5-59662.29"
+ attribute \src "libresoc.v:59012.5-59012.29"
switch \initial
- attribute \src "libresoc.v:59662.9-59662.17"
+ attribute \src "libresoc.v:59012.9-59012.17"
case 1'1
case
end
sync always
update \SPR_cr_in $0\SPR_cr_in[2:0]
end
- attribute \src "libresoc.v:59671.3-59680.6"
- process $proc$libresoc.v:59671$3522
+ attribute \src "libresoc.v:59021.3-59030.6"
+ process $proc$libresoc.v:59021$3495
assign { } { }
assign { } { }
assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0]
- attribute \src "libresoc.v:59672.5-59672.29"
+ attribute \src "libresoc.v:59022.5-59022.29"
switch \initial
- attribute \src "libresoc.v:59672.9-59672.17"
+ attribute \src "libresoc.v:59022.9-59022.17"
case 1'1
case
end
sync always
update \SPR_cr_out $0\SPR_cr_out[2:0]
end
- attribute \src "libresoc.v:59681.3-59690.6"
- process $proc$libresoc.v:59681$3523
+ attribute \src "libresoc.v:59031.3-59040.6"
+ process $proc$libresoc.v:59031$3496
assign { } { }
assign { } { }
assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0]
- attribute \src "libresoc.v:59682.5-59682.29"
+ attribute \src "libresoc.v:59032.5-59032.29"
switch \initial
- attribute \src "libresoc.v:59682.9-59682.17"
+ attribute \src "libresoc.v:59032.9-59032.17"
case 1'1
case
end
sync always
update \SPR_rc_sel $0\SPR_rc_sel[1:0]
end
- attribute \src "libresoc.v:59691.3-59700.6"
- process $proc$libresoc.v:59691$3524
+ attribute \src "libresoc.v:59041.3-59050.6"
+ process $proc$libresoc.v:59041$3497
assign { } { }
assign { } { }
assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0]
- attribute \src "libresoc.v:59692.5-59692.29"
+ attribute \src "libresoc.v:59042.5-59042.29"
switch \initial
- attribute \src "libresoc.v:59692.9-59692.17"
+ attribute \src "libresoc.v:59042.9-59042.17"
case 1'1
case
end
sync always
update \SPR_is_32b $0\SPR_is_32b[0:0]
end
- connect \$1 $ternary$libresoc.v:59631$3518_Y
+ connect \$1 $ternary$libresoc.v:58981$3491_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \SPR_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:60041.1-61562.10"
+attribute \src "libresoc.v:59391.1-60912.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec"
attribute \generator "nMigen"
module \dec$153
- attribute \src "libresoc.v:61186.3-61195.6"
+ attribute \src "libresoc.v:60536.3-60545.6"
wire width 3 $0\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61196.3-61205.6"
+ attribute \src "libresoc.v:60546.3-60555.6"
wire width 3 $0\DIV_cr_out[2:0]
- attribute \src "libresoc.v:61086.3-61095.6"
+ attribute \src "libresoc.v:60436.3-60445.6"
wire width 2 $0\DIV_cry_in[1:0]
- attribute \src "libresoc.v:61116.3-61125.6"
+ attribute \src "libresoc.v:60466.3-60475.6"
wire $0\DIV_cry_out[0:0]
- attribute \src "libresoc.v:61146.3-61155.6"
+ attribute \src "libresoc.v:60496.3-60505.6"
wire width 13 $0\DIV_function_unit[12:0]
- attribute \src "libresoc.v:61166.3-61175.6"
+ attribute \src "libresoc.v:60516.3-60525.6"
wire width 3 $0\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61176.3-61185.6"
+ attribute \src "libresoc.v:60526.3-60535.6"
wire width 4 $0\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61156.3-61165.6"
+ attribute \src "libresoc.v:60506.3-60515.6"
wire width 7 $0\DIV_internal_op[6:0]
- attribute \src "libresoc.v:61096.3-61105.6"
+ attribute \src "libresoc.v:60446.3-60455.6"
wire $0\DIV_inv_a[0:0]
- attribute \src "libresoc.v:61106.3-61115.6"
+ attribute \src "libresoc.v:60456.3-60465.6"
wire $0\DIV_inv_out[0:0]
- attribute \src "libresoc.v:61126.3-61135.6"
+ attribute \src "libresoc.v:60476.3-60485.6"
wire $0\DIV_is_32b[0:0]
- attribute \src "libresoc.v:61206.3-61215.6"
+ attribute \src "libresoc.v:60556.3-60565.6"
wire width 4 $0\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61216.3-61225.6"
+ attribute \src "libresoc.v:60566.3-60575.6"
wire width 2 $0\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:61136.3-61145.6"
+ attribute \src "libresoc.v:60486.3-60495.6"
wire $0\DIV_sgn[0:0]
- attribute \src "libresoc.v:60042.7-60042.20"
+ attribute \src "libresoc.v:59392.7-59392.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:61186.3-61195.6"
+ attribute \src "libresoc.v:60536.3-60545.6"
wire width 3 $1\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61196.3-61205.6"
+ attribute \src "libresoc.v:60546.3-60555.6"
wire width 3 $1\DIV_cr_out[2:0]
- attribute \src "libresoc.v:61086.3-61095.6"
+ attribute \src "libresoc.v:60436.3-60445.6"
wire width 2 $1\DIV_cry_in[1:0]
- attribute \src "libresoc.v:61116.3-61125.6"
+ attribute \src "libresoc.v:60466.3-60475.6"
wire $1\DIV_cry_out[0:0]
- attribute \src "libresoc.v:61146.3-61155.6"
+ attribute \src "libresoc.v:60496.3-60505.6"
wire width 13 $1\DIV_function_unit[12:0]
- attribute \src "libresoc.v:61166.3-61175.6"
+ attribute \src "libresoc.v:60516.3-60525.6"
wire width 3 $1\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61176.3-61185.6"
+ attribute \src "libresoc.v:60526.3-60535.6"
wire width 4 $1\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61156.3-61165.6"
+ attribute \src "libresoc.v:60506.3-60515.6"
wire width 7 $1\DIV_internal_op[6:0]
- attribute \src "libresoc.v:61096.3-61105.6"
+ attribute \src "libresoc.v:60446.3-60455.6"
wire $1\DIV_inv_a[0:0]
- attribute \src "libresoc.v:61106.3-61115.6"
+ attribute \src "libresoc.v:60456.3-60465.6"
wire $1\DIV_inv_out[0:0]
- attribute \src "libresoc.v:61126.3-61135.6"
+ attribute \src "libresoc.v:60476.3-60485.6"
wire $1\DIV_is_32b[0:0]
- attribute \src "libresoc.v:61206.3-61215.6"
+ attribute \src "libresoc.v:60556.3-60565.6"
wire width 4 $1\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61216.3-61225.6"
+ attribute \src "libresoc.v:60566.3-60575.6"
wire width 2 $1\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:61136.3-61145.6"
+ attribute \src "libresoc.v:60486.3-60495.6"
wire $1\DIV_sgn[0:0]
- attribute \src "libresoc.v:61068.17-61068.211"
- wire width 32 $ternary$libresoc.v:61068$3526_Y
+ attribute \src "libresoc.v:60418.17-60418.211"
+ wire width 32 $ternary$libresoc.v:60418$3499_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:60042.7-60042.15"
+ attribute \src "libresoc.v:59392.7-59392.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 27 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:61068$3526
+ cell $mux $ternary$libresoc.v:60418$3499
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:61068$3526_Y
+ connect \Y $ternary$libresoc.v:60418$3499_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:61069.13-61085.4"
+ attribute \src "libresoc.v:60419.13-60435.4"
cell \DIV_dec31 \DIV_dec31
connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in
connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out
connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn
connect \opcode_in \DIV_dec31_opcode_in
end
- attribute \src "libresoc.v:60042.7-60042.20"
- process $proc$libresoc.v:60042$3541
+ attribute \src "libresoc.v:59392.7-59392.20"
+ process $proc$libresoc.v:59392$3514
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:61086.3-61095.6"
- process $proc$libresoc.v:61086$3527
+ attribute \src "libresoc.v:60436.3-60445.6"
+ process $proc$libresoc.v:60436$3500
assign { } { }
assign { } { }
assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0]
- attribute \src "libresoc.v:61087.5-61087.29"
+ attribute \src "libresoc.v:60437.5-60437.29"
switch \initial
- attribute \src "libresoc.v:61087.9-61087.17"
+ attribute \src "libresoc.v:60437.9-60437.17"
case 1'1
case
end
sync always
update \DIV_cry_in $0\DIV_cry_in[1:0]
end
- attribute \src "libresoc.v:61096.3-61105.6"
- process $proc$libresoc.v:61096$3528
+ attribute \src "libresoc.v:60446.3-60455.6"
+ process $proc$libresoc.v:60446$3501
assign { } { }
assign { } { }
assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0]
- attribute \src "libresoc.v:61097.5-61097.29"
+ attribute \src "libresoc.v:60447.5-60447.29"
switch \initial
- attribute \src "libresoc.v:61097.9-61097.17"
+ attribute \src "libresoc.v:60447.9-60447.17"
case 1'1
case
end
sync always
update \DIV_inv_a $0\DIV_inv_a[0:0]
end
- attribute \src "libresoc.v:61106.3-61115.6"
- process $proc$libresoc.v:61106$3529
+ attribute \src "libresoc.v:60456.3-60465.6"
+ process $proc$libresoc.v:60456$3502
assign { } { }
assign { } { }
assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0]
- attribute \src "libresoc.v:61107.5-61107.29"
+ attribute \src "libresoc.v:60457.5-60457.29"
switch \initial
- attribute \src "libresoc.v:61107.9-61107.17"
+ attribute \src "libresoc.v:60457.9-60457.17"
case 1'1
case
end
sync always
update \DIV_inv_out $0\DIV_inv_out[0:0]
end
- attribute \src "libresoc.v:61116.3-61125.6"
- process $proc$libresoc.v:61116$3530
+ attribute \src "libresoc.v:60466.3-60475.6"
+ process $proc$libresoc.v:60466$3503
assign { } { }
assign { } { }
assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0]
- attribute \src "libresoc.v:61117.5-61117.29"
+ attribute \src "libresoc.v:60467.5-60467.29"
switch \initial
- attribute \src "libresoc.v:61117.9-61117.17"
+ attribute \src "libresoc.v:60467.9-60467.17"
case 1'1
case
end
sync always
update \DIV_cry_out $0\DIV_cry_out[0:0]
end
- attribute \src "libresoc.v:61126.3-61135.6"
- process $proc$libresoc.v:61126$3531
+ attribute \src "libresoc.v:60476.3-60485.6"
+ process $proc$libresoc.v:60476$3504
assign { } { }
assign { } { }
assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0]
- attribute \src "libresoc.v:61127.5-61127.29"
+ attribute \src "libresoc.v:60477.5-60477.29"
switch \initial
- attribute \src "libresoc.v:61127.9-61127.17"
+ attribute \src "libresoc.v:60477.9-60477.17"
case 1'1
case
end
sync always
update \DIV_is_32b $0\DIV_is_32b[0:0]
end
- attribute \src "libresoc.v:61136.3-61145.6"
- process $proc$libresoc.v:61136$3532
+ attribute \src "libresoc.v:60486.3-60495.6"
+ process $proc$libresoc.v:60486$3505
assign { } { }
assign { } { }
assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0]
- attribute \src "libresoc.v:61137.5-61137.29"
+ attribute \src "libresoc.v:60487.5-60487.29"
switch \initial
- attribute \src "libresoc.v:61137.9-61137.17"
+ attribute \src "libresoc.v:60487.9-60487.17"
case 1'1
case
end
sync always
update \DIV_sgn $0\DIV_sgn[0:0]
end
- attribute \src "libresoc.v:61146.3-61155.6"
- process $proc$libresoc.v:61146$3533
+ attribute \src "libresoc.v:60496.3-60505.6"
+ process $proc$libresoc.v:60496$3506
assign { } { }
assign { } { }
assign $0\DIV_function_unit[12:0] $1\DIV_function_unit[12:0]
- attribute \src "libresoc.v:61147.5-61147.29"
+ attribute \src "libresoc.v:60497.5-60497.29"
switch \initial
- attribute \src "libresoc.v:61147.9-61147.17"
+ attribute \src "libresoc.v:60497.9-60497.17"
case 1'1
case
end
sync always
update \DIV_function_unit $0\DIV_function_unit[12:0]
end
- attribute \src "libresoc.v:61156.3-61165.6"
- process $proc$libresoc.v:61156$3534
+ attribute \src "libresoc.v:60506.3-60515.6"
+ process $proc$libresoc.v:60506$3507
assign { } { }
assign { } { }
assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0]
- attribute \src "libresoc.v:61157.5-61157.29"
+ attribute \src "libresoc.v:60507.5-60507.29"
switch \initial
- attribute \src "libresoc.v:61157.9-61157.17"
+ attribute \src "libresoc.v:60507.9-60507.17"
case 1'1
case
end
sync always
update \DIV_internal_op $0\DIV_internal_op[6:0]
end
- attribute \src "libresoc.v:61166.3-61175.6"
- process $proc$libresoc.v:61166$3535
+ attribute \src "libresoc.v:60516.3-60525.6"
+ process $proc$libresoc.v:60516$3508
assign { } { }
assign { } { }
assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0]
- attribute \src "libresoc.v:61167.5-61167.29"
+ attribute \src "libresoc.v:60517.5-60517.29"
switch \initial
- attribute \src "libresoc.v:61167.9-61167.17"
+ attribute \src "libresoc.v:60517.9-60517.17"
case 1'1
case
end
sync always
update \DIV_in1_sel $0\DIV_in1_sel[2:0]
end
- attribute \src "libresoc.v:61176.3-61185.6"
- process $proc$libresoc.v:61176$3536
+ attribute \src "libresoc.v:60526.3-60535.6"
+ process $proc$libresoc.v:60526$3509
assign { } { }
assign { } { }
assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0]
- attribute \src "libresoc.v:61177.5-61177.29"
+ attribute \src "libresoc.v:60527.5-60527.29"
switch \initial
- attribute \src "libresoc.v:61177.9-61177.17"
+ attribute \src "libresoc.v:60527.9-60527.17"
case 1'1
case
end
sync always
update \DIV_in2_sel $0\DIV_in2_sel[3:0]
end
- attribute \src "libresoc.v:61186.3-61195.6"
- process $proc$libresoc.v:61186$3537
+ attribute \src "libresoc.v:60536.3-60545.6"
+ process $proc$libresoc.v:60536$3510
assign { } { }
assign { } { }
assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0]
- attribute \src "libresoc.v:61187.5-61187.29"
+ attribute \src "libresoc.v:60537.5-60537.29"
switch \initial
- attribute \src "libresoc.v:61187.9-61187.17"
+ attribute \src "libresoc.v:60537.9-60537.17"
case 1'1
case
end
sync always
update \DIV_cr_in $0\DIV_cr_in[2:0]
end
- attribute \src "libresoc.v:61196.3-61205.6"
- process $proc$libresoc.v:61196$3538
+ attribute \src "libresoc.v:60546.3-60555.6"
+ process $proc$libresoc.v:60546$3511
assign { } { }
assign { } { }
assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0]
- attribute \src "libresoc.v:61197.5-61197.29"
+ attribute \src "libresoc.v:60547.5-60547.29"
switch \initial
- attribute \src "libresoc.v:61197.9-61197.17"
+ attribute \src "libresoc.v:60547.9-60547.17"
case 1'1
case
end
sync always
update \DIV_cr_out $0\DIV_cr_out[2:0]
end
- attribute \src "libresoc.v:61206.3-61215.6"
- process $proc$libresoc.v:61206$3539
+ attribute \src "libresoc.v:60556.3-60565.6"
+ process $proc$libresoc.v:60556$3512
assign { } { }
assign { } { }
assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0]
- attribute \src "libresoc.v:61207.5-61207.29"
+ attribute \src "libresoc.v:60557.5-60557.29"
switch \initial
- attribute \src "libresoc.v:61207.9-61207.17"
+ attribute \src "libresoc.v:60557.9-60557.17"
case 1'1
case
end
sync always
update \DIV_ldst_len $0\DIV_ldst_len[3:0]
end
- attribute \src "libresoc.v:61216.3-61225.6"
- process $proc$libresoc.v:61216$3540
+ attribute \src "libresoc.v:60566.3-60575.6"
+ process $proc$libresoc.v:60566$3513
assign { } { }
assign { } { }
assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0]
- attribute \src "libresoc.v:61217.5-61217.29"
+ attribute \src "libresoc.v:60567.5-60567.29"
switch \initial
- attribute \src "libresoc.v:61217.9-61217.17"
+ attribute \src "libresoc.v:60567.9-60567.17"
case 1'1
case
end
sync always
update \DIV_rc_sel $0\DIV_rc_sel[1:0]
end
- connect \$1 $ternary$libresoc.v:61068$3526_Y
+ connect \$1 $ternary$libresoc.v:60418$3499_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \DIV_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:61566.1-62983.10"
+attribute \src "libresoc.v:60916.1-62333.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec"
attribute \generator "nMigen"
module \dec$158
- attribute \src "libresoc.v:62582.3-62594.6"
+ attribute \src "libresoc.v:61932.3-61944.6"
wire width 3 $0\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62595.3-62607.6"
+ attribute \src "libresoc.v:61945.3-61957.6"
wire width 3 $0\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62543.3-62555.6"
+ attribute \src "libresoc.v:61893.3-61905.6"
wire width 13 $0\MUL_function_unit[12:0]
- attribute \src "libresoc.v:62569.3-62581.6"
+ attribute \src "libresoc.v:61919.3-61931.6"
wire width 4 $0\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62556.3-62568.6"
+ attribute \src "libresoc.v:61906.3-61918.6"
wire width 7 $0\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62621.3-62633.6"
+ attribute \src "libresoc.v:61971.3-61983.6"
wire $0\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62608.3-62620.6"
+ attribute \src "libresoc.v:61958.3-61970.6"
wire width 2 $0\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62634.3-62646.6"
+ attribute \src "libresoc.v:61984.3-61996.6"
wire $0\MUL_sgn[0:0]
- attribute \src "libresoc.v:61567.7-61567.20"
+ attribute \src "libresoc.v:60917.7-60917.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:62582.3-62594.6"
+ attribute \src "libresoc.v:61932.3-61944.6"
wire width 3 $1\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62595.3-62607.6"
+ attribute \src "libresoc.v:61945.3-61957.6"
wire width 3 $1\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62543.3-62555.6"
+ attribute \src "libresoc.v:61893.3-61905.6"
wire width 13 $1\MUL_function_unit[12:0]
- attribute \src "libresoc.v:62569.3-62581.6"
+ attribute \src "libresoc.v:61919.3-61931.6"
wire width 4 $1\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62556.3-62568.6"
+ attribute \src "libresoc.v:61906.3-61918.6"
wire width 7 $1\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62621.3-62633.6"
+ attribute \src "libresoc.v:61971.3-61983.6"
wire $1\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62608.3-62620.6"
+ attribute \src "libresoc.v:61958.3-61970.6"
wire width 2 $1\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62634.3-62646.6"
+ attribute \src "libresoc.v:61984.3-61996.6"
wire $1\MUL_sgn[0:0]
- attribute \src "libresoc.v:62531.17-62531.211"
- wire width 32 $ternary$libresoc.v:62531$3542_Y
+ attribute \src "libresoc.v:61881.17-61881.211"
+ wire width 32 $ternary$libresoc.v:61881$3515_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:61567.7-61567.15"
+ attribute \src "libresoc.v:60917.7-60917.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 20 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:62531$3542
+ cell $mux $ternary$libresoc.v:61881$3515
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:62531$3542_Y
+ connect \Y $ternary$libresoc.v:61881$3515_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:62532.13-62542.4"
+ attribute \src "libresoc.v:61882.13-61892.4"
cell \MUL_dec31 \MUL_dec31
connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in
connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out
connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn
connect \opcode_in \MUL_dec31_opcode_in
end
- attribute \src "libresoc.v:61567.7-61567.20"
- process $proc$libresoc.v:61567$3551
+ attribute \src "libresoc.v:60917.7-60917.20"
+ process $proc$libresoc.v:60917$3524
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:62543.3-62555.6"
- process $proc$libresoc.v:62543$3543
+ attribute \src "libresoc.v:61893.3-61905.6"
+ process $proc$libresoc.v:61893$3516
assign { } { }
assign { } { }
assign $0\MUL_function_unit[12:0] $1\MUL_function_unit[12:0]
- attribute \src "libresoc.v:62544.5-62544.29"
+ attribute \src "libresoc.v:61894.5-61894.29"
switch \initial
- attribute \src "libresoc.v:62544.9-62544.17"
+ attribute \src "libresoc.v:61894.9-61894.17"
case 1'1
case
end
sync always
update \MUL_function_unit $0\MUL_function_unit[12:0]
end
- attribute \src "libresoc.v:62556.3-62568.6"
- process $proc$libresoc.v:62556$3544
+ attribute \src "libresoc.v:61906.3-61918.6"
+ process $proc$libresoc.v:61906$3517
assign { } { }
assign { } { }
assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0]
- attribute \src "libresoc.v:62557.5-62557.29"
+ attribute \src "libresoc.v:61907.5-61907.29"
switch \initial
- attribute \src "libresoc.v:62557.9-62557.17"
+ attribute \src "libresoc.v:61907.9-61907.17"
case 1'1
case
end
sync always
update \MUL_internal_op $0\MUL_internal_op[6:0]
end
- attribute \src "libresoc.v:62569.3-62581.6"
- process $proc$libresoc.v:62569$3545
+ attribute \src "libresoc.v:61919.3-61931.6"
+ process $proc$libresoc.v:61919$3518
assign { } { }
assign { } { }
assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0]
- attribute \src "libresoc.v:62570.5-62570.29"
+ attribute \src "libresoc.v:61920.5-61920.29"
switch \initial
- attribute \src "libresoc.v:62570.9-62570.17"
+ attribute \src "libresoc.v:61920.9-61920.17"
case 1'1
case
end
sync always
update \MUL_in2_sel $0\MUL_in2_sel[3:0]
end
- attribute \src "libresoc.v:62582.3-62594.6"
- process $proc$libresoc.v:62582$3546
+ attribute \src "libresoc.v:61932.3-61944.6"
+ process $proc$libresoc.v:61932$3519
assign { } { }
assign { } { }
assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0]
- attribute \src "libresoc.v:62583.5-62583.29"
+ attribute \src "libresoc.v:61933.5-61933.29"
switch \initial
- attribute \src "libresoc.v:62583.9-62583.17"
+ attribute \src "libresoc.v:61933.9-61933.17"
case 1'1
case
end
sync always
update \MUL_cr_in $0\MUL_cr_in[2:0]
end
- attribute \src "libresoc.v:62595.3-62607.6"
- process $proc$libresoc.v:62595$3547
+ attribute \src "libresoc.v:61945.3-61957.6"
+ process $proc$libresoc.v:61945$3520
assign { } { }
assign { } { }
assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0]
- attribute \src "libresoc.v:62596.5-62596.29"
+ attribute \src "libresoc.v:61946.5-61946.29"
switch \initial
- attribute \src "libresoc.v:62596.9-62596.17"
+ attribute \src "libresoc.v:61946.9-61946.17"
case 1'1
case
end
sync always
update \MUL_cr_out $0\MUL_cr_out[2:0]
end
- attribute \src "libresoc.v:62608.3-62620.6"
- process $proc$libresoc.v:62608$3548
+ attribute \src "libresoc.v:61958.3-61970.6"
+ process $proc$libresoc.v:61958$3521
assign { } { }
assign { } { }
assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0]
- attribute \src "libresoc.v:62609.5-62609.29"
+ attribute \src "libresoc.v:61959.5-61959.29"
switch \initial
- attribute \src "libresoc.v:62609.9-62609.17"
+ attribute \src "libresoc.v:61959.9-61959.17"
case 1'1
case
end
sync always
update \MUL_rc_sel $0\MUL_rc_sel[1:0]
end
- attribute \src "libresoc.v:62621.3-62633.6"
- process $proc$libresoc.v:62621$3549
+ attribute \src "libresoc.v:61971.3-61983.6"
+ process $proc$libresoc.v:61971$3522
assign { } { }
assign { } { }
assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0]
- attribute \src "libresoc.v:62622.5-62622.29"
+ attribute \src "libresoc.v:61972.5-61972.29"
switch \initial
- attribute \src "libresoc.v:62622.9-62622.17"
+ attribute \src "libresoc.v:61972.9-61972.17"
case 1'1
case
end
sync always
update \MUL_is_32b $0\MUL_is_32b[0:0]
end
- attribute \src "libresoc.v:62634.3-62646.6"
- process $proc$libresoc.v:62634$3550
+ attribute \src "libresoc.v:61984.3-61996.6"
+ process $proc$libresoc.v:61984$3523
assign { } { }
assign { } { }
assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0]
- attribute \src "libresoc.v:62635.5-62635.29"
+ attribute \src "libresoc.v:61985.5-61985.29"
switch \initial
- attribute \src "libresoc.v:62635.9-62635.17"
+ attribute \src "libresoc.v:61985.9-61985.17"
case 1'1
case
end
sync always
update \MUL_sgn $0\MUL_sgn[0:0]
end
- connect \$1 $ternary$libresoc.v:62531$3542_Y
+ connect \$1 $ternary$libresoc.v:61881$3515_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \MUL_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:62987.1-64735.10"
+attribute \src "libresoc.v:62337.1-64085.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec"
attribute \generator "nMigen"
module \dec$162
- attribute \src "libresoc.v:64310.3-64331.6"
+ attribute \src "libresoc.v:63660.3-63681.6"
wire width 3 $0\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64332.3-64353.6"
+ attribute \src "libresoc.v:63682.3-63703.6"
wire width 3 $0\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64376.3-64397.6"
+ attribute \src "libresoc.v:63726.3-63747.6"
wire width 2 $0\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64178.3-64199.6"
+ attribute \src "libresoc.v:63528.3-63549.6"
wire $0\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64244.3-64265.6"
+ attribute \src "libresoc.v:63594.3-63615.6"
wire width 13 $0\SHIFT_ROT_function_unit[12:0]
- attribute \src "libresoc.v:64288.3-64309.6"
+ attribute \src "libresoc.v:63638.3-63659.6"
wire width 4 $0\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64266.3-64287.6"
+ attribute \src "libresoc.v:63616.3-63637.6"
wire width 7 $0\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64156.3-64177.6"
+ attribute \src "libresoc.v:63506.3-63527.6"
wire $0\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64200.3-64221.6"
+ attribute \src "libresoc.v:63550.3-63571.6"
wire $0\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64354.3-64375.6"
+ attribute \src "libresoc.v:63704.3-63725.6"
wire width 2 $0\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64222.3-64243.6"
+ attribute \src "libresoc.v:63572.3-63593.6"
wire $0\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:62988.7-62988.20"
+ attribute \src "libresoc.v:62338.7-62338.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:64310.3-64331.6"
+ attribute \src "libresoc.v:63660.3-63681.6"
wire width 3 $1\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64332.3-64353.6"
+ attribute \src "libresoc.v:63682.3-63703.6"
wire width 3 $1\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64376.3-64397.6"
+ attribute \src "libresoc.v:63726.3-63747.6"
wire width 2 $1\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64178.3-64199.6"
+ attribute \src "libresoc.v:63528.3-63549.6"
wire $1\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64244.3-64265.6"
+ attribute \src "libresoc.v:63594.3-63615.6"
wire width 13 $1\SHIFT_ROT_function_unit[12:0]
- attribute \src "libresoc.v:64288.3-64309.6"
+ attribute \src "libresoc.v:63638.3-63659.6"
wire width 4 $1\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64266.3-64287.6"
+ attribute \src "libresoc.v:63616.3-63637.6"
wire width 7 $1\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64156.3-64177.6"
+ attribute \src "libresoc.v:63506.3-63527.6"
wire $1\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64200.3-64221.6"
+ attribute \src "libresoc.v:63550.3-63571.6"
wire $1\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64354.3-64375.6"
+ attribute \src "libresoc.v:63704.3-63725.6"
wire width 2 $1\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64222.3-64243.6"
+ attribute \src "libresoc.v:63572.3-63593.6"
wire $1\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:64127.17-64127.211"
- wire width 32 $ternary$libresoc.v:64127$3552_Y
+ attribute \src "libresoc.v:63477.17-63477.211"
+ wire width 32 $ternary$libresoc.v:63477$3525_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:62988.7-62988.15"
+ attribute \src "libresoc.v:62338.7-62338.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 24 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:64127$3552
+ cell $mux $ternary$libresoc.v:63477$3525
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:64127$3552_Y
+ connect \Y $ternary$libresoc.v:63477$3525_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:64128.19-64141.4"
+ attribute \src "libresoc.v:63478.19-63491.4"
cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30
connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in
connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out
connect \opcode_in \SHIFT_ROT_dec30_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:64142.19-64155.4"
+ attribute \src "libresoc.v:63492.19-63505.4"
cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31
connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in
connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out
connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn
connect \opcode_in \SHIFT_ROT_dec31_opcode_in
end
- attribute \src "libresoc.v:62988.7-62988.20"
- process $proc$libresoc.v:62988$3564
+ attribute \src "libresoc.v:62338.7-62338.20"
+ process $proc$libresoc.v:62338$3537
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:64156.3-64177.6"
- process $proc$libresoc.v:64156$3553
+ attribute \src "libresoc.v:63506.3-63527.6"
+ process $proc$libresoc.v:63506$3526
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0]
- attribute \src "libresoc.v:64157.5-64157.29"
+ attribute \src "libresoc.v:63507.5-63507.29"
switch \initial
- attribute \src "libresoc.v:64157.9-64157.17"
+ attribute \src "libresoc.v:63507.9-63507.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0]
end
- attribute \src "libresoc.v:64178.3-64199.6"
- process $proc$libresoc.v:64178$3554
+ attribute \src "libresoc.v:63528.3-63549.6"
+ process $proc$libresoc.v:63528$3527
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0]
- attribute \src "libresoc.v:64179.5-64179.29"
+ attribute \src "libresoc.v:63529.5-63529.29"
switch \initial
- attribute \src "libresoc.v:64179.9-64179.17"
+ attribute \src "libresoc.v:63529.9-63529.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0]
end
- attribute \src "libresoc.v:64200.3-64221.6"
- process $proc$libresoc.v:64200$3555
+ attribute \src "libresoc.v:63550.3-63571.6"
+ process $proc$libresoc.v:63550$3528
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0]
- attribute \src "libresoc.v:64201.5-64201.29"
+ attribute \src "libresoc.v:63551.5-63551.29"
switch \initial
- attribute \src "libresoc.v:64201.9-64201.17"
+ attribute \src "libresoc.v:63551.9-63551.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0]
end
- attribute \src "libresoc.v:64222.3-64243.6"
- process $proc$libresoc.v:64222$3556
+ attribute \src "libresoc.v:63572.3-63593.6"
+ process $proc$libresoc.v:63572$3529
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0]
- attribute \src "libresoc.v:64223.5-64223.29"
+ attribute \src "libresoc.v:63573.5-63573.29"
switch \initial
- attribute \src "libresoc.v:64223.9-64223.17"
+ attribute \src "libresoc.v:63573.9-63573.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0]
end
- attribute \src "libresoc.v:64244.3-64265.6"
- process $proc$libresoc.v:64244$3557
+ attribute \src "libresoc.v:63594.3-63615.6"
+ process $proc$libresoc.v:63594$3530
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_function_unit[12:0] $1\SHIFT_ROT_function_unit[12:0]
- attribute \src "libresoc.v:64245.5-64245.29"
+ attribute \src "libresoc.v:63595.5-63595.29"
switch \initial
- attribute \src "libresoc.v:64245.9-64245.17"
+ attribute \src "libresoc.v:63595.9-63595.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[12:0]
end
- attribute \src "libresoc.v:64266.3-64287.6"
- process $proc$libresoc.v:64266$3558
+ attribute \src "libresoc.v:63616.3-63637.6"
+ process $proc$libresoc.v:63616$3531
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0]
- attribute \src "libresoc.v:64267.5-64267.29"
+ attribute \src "libresoc.v:63617.5-63617.29"
switch \initial
- attribute \src "libresoc.v:64267.9-64267.17"
+ attribute \src "libresoc.v:63617.9-63617.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0]
end
- attribute \src "libresoc.v:64288.3-64309.6"
- process $proc$libresoc.v:64288$3559
+ attribute \src "libresoc.v:63638.3-63659.6"
+ process $proc$libresoc.v:63638$3532
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0]
- attribute \src "libresoc.v:64289.5-64289.29"
+ attribute \src "libresoc.v:63639.5-63639.29"
switch \initial
- attribute \src "libresoc.v:64289.9-64289.17"
+ attribute \src "libresoc.v:63639.9-63639.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0]
end
- attribute \src "libresoc.v:64310.3-64331.6"
- process $proc$libresoc.v:64310$3560
+ attribute \src "libresoc.v:63660.3-63681.6"
+ process $proc$libresoc.v:63660$3533
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0]
- attribute \src "libresoc.v:64311.5-64311.29"
+ attribute \src "libresoc.v:63661.5-63661.29"
switch \initial
- attribute \src "libresoc.v:64311.9-64311.17"
+ attribute \src "libresoc.v:63661.9-63661.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0]
end
- attribute \src "libresoc.v:64332.3-64353.6"
- process $proc$libresoc.v:64332$3561
+ attribute \src "libresoc.v:63682.3-63703.6"
+ process $proc$libresoc.v:63682$3534
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0]
- attribute \src "libresoc.v:64333.5-64333.29"
+ attribute \src "libresoc.v:63683.5-63683.29"
switch \initial
- attribute \src "libresoc.v:64333.9-64333.17"
+ attribute \src "libresoc.v:63683.9-63683.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0]
end
- attribute \src "libresoc.v:64354.3-64375.6"
- process $proc$libresoc.v:64354$3562
+ attribute \src "libresoc.v:63704.3-63725.6"
+ process $proc$libresoc.v:63704$3535
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0]
- attribute \src "libresoc.v:64355.5-64355.29"
+ attribute \src "libresoc.v:63705.5-63705.29"
switch \initial
- attribute \src "libresoc.v:64355.9-64355.17"
+ attribute \src "libresoc.v:63705.9-63705.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0]
end
- attribute \src "libresoc.v:64376.3-64397.6"
- process $proc$libresoc.v:64376$3563
+ attribute \src "libresoc.v:63726.3-63747.6"
+ process $proc$libresoc.v:63726$3536
assign { } { }
assign { } { }
assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0]
- attribute \src "libresoc.v:64377.5-64377.29"
+ attribute \src "libresoc.v:63727.5-63727.29"
switch \initial
- attribute \src "libresoc.v:64377.9-64377.17"
+ attribute \src "libresoc.v:63727.9-63727.17"
case 1'1
case
end
sync always
update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0]
end
- connect \$1 $ternary$libresoc.v:64127$3552_Y
+ connect \$1 $ternary$libresoc.v:63477$3525_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \SHIFT_ROT_dec30_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:64739.1-67240.10"
+attribute \src "libresoc.v:64089.1-66590.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec"
attribute \generator "nMigen"
module \dec$166
- attribute \src "libresoc.v:66322.3-66379.6"
+ attribute \src "libresoc.v:65672.3-65729.6"
wire $0\LDST_br[0:0]
- attribute \src "libresoc.v:66786.3-66843.6"
+ attribute \src "libresoc.v:66136.3-66193.6"
wire width 3 $0\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66844.3-66901.6"
+ attribute \src "libresoc.v:66194.3-66251.6"
wire width 3 $0\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66554.3-66611.6"
+ attribute \src "libresoc.v:65904.3-65961.6"
wire width 13 $0\LDST_function_unit[12:0]
- attribute \src "libresoc.v:66670.3-66727.6"
+ attribute \src "libresoc.v:66020.3-66077.6"
wire width 3 $0\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66728.3-66785.6"
+ attribute \src "libresoc.v:66078.3-66135.6"
wire width 4 $0\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66612.3-66669.6"
+ attribute \src "libresoc.v:65962.3-66019.6"
wire width 7 $0\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66438.3-66495.6"
+ attribute \src "libresoc.v:65788.3-65845.6"
wire $0\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66148.3-66205.6"
+ attribute \src "libresoc.v:65498.3-65555.6"
wire width 4 $0\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66264.3-66321.6"
+ attribute \src "libresoc.v:65614.3-65671.6"
wire width 2 $0\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66496.3-66553.6"
+ attribute \src "libresoc.v:65846.3-65903.6"
wire $0\LDST_sgn[0:0]
- attribute \src "libresoc.v:66380.3-66437.6"
+ attribute \src "libresoc.v:65730.3-65787.6"
wire $0\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66206.3-66263.6"
+ attribute \src "libresoc.v:65556.3-65613.6"
wire width 2 $0\LDST_upd[1:0]
- attribute \src "libresoc.v:64740.7-64740.20"
+ attribute \src "libresoc.v:64090.7-64090.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:66322.3-66379.6"
+ attribute \src "libresoc.v:65672.3-65729.6"
wire $1\LDST_br[0:0]
- attribute \src "libresoc.v:66786.3-66843.6"
+ attribute \src "libresoc.v:66136.3-66193.6"
wire width 3 $1\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66844.3-66901.6"
+ attribute \src "libresoc.v:66194.3-66251.6"
wire width 3 $1\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66554.3-66611.6"
+ attribute \src "libresoc.v:65904.3-65961.6"
wire width 13 $1\LDST_function_unit[12:0]
- attribute \src "libresoc.v:66670.3-66727.6"
+ attribute \src "libresoc.v:66020.3-66077.6"
wire width 3 $1\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66728.3-66785.6"
+ attribute \src "libresoc.v:66078.3-66135.6"
wire width 4 $1\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66612.3-66669.6"
+ attribute \src "libresoc.v:65962.3-66019.6"
wire width 7 $1\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66438.3-66495.6"
+ attribute \src "libresoc.v:65788.3-65845.6"
wire $1\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66148.3-66205.6"
+ attribute \src "libresoc.v:65498.3-65555.6"
wire width 4 $1\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66264.3-66321.6"
+ attribute \src "libresoc.v:65614.3-65671.6"
wire width 2 $1\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66496.3-66553.6"
+ attribute \src "libresoc.v:65846.3-65903.6"
wire $1\LDST_sgn[0:0]
- attribute \src "libresoc.v:66380.3-66437.6"
+ attribute \src "libresoc.v:65730.3-65787.6"
wire $1\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66206.3-66263.6"
+ attribute \src "libresoc.v:65556.3-65613.6"
wire width 2 $1\LDST_upd[1:0]
- attribute \src "libresoc.v:66099.17-66099.211"
- wire width 32 $ternary$libresoc.v:66099$3565_Y
+ attribute \src "libresoc.v:65449.17-65449.211"
+ wire width 32 $ternary$libresoc.v:65449$3538_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
- attribute \src "libresoc.v:64740.7-64740.15"
+ attribute \src "libresoc.v:64090.7-64090.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 output 2 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 26 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:66099$3565
+ cell $mux $ternary$libresoc.v:65449$3538
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:66099$3565_Y
+ connect \Y $ternary$libresoc.v:65449$3538_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:66100.14-66115.4"
+ attribute \src "libresoc.v:65450.14-65465.4"
cell \LDST_dec31 \LDST_dec31
connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br
connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in
connect \opcode_in \LDST_dec31_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:66116.14-66131.4"
+ attribute \src "libresoc.v:65466.14-65481.4"
cell \LDST_dec58 \LDST_dec58
connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br
connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in
connect \opcode_in \LDST_dec58_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:66132.14-66147.4"
+ attribute \src "libresoc.v:65482.14-65497.4"
cell \LDST_dec62 \LDST_dec62
connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br
connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in
connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd
connect \opcode_in \LDST_dec62_opcode_in
end
- attribute \src "libresoc.v:64740.7-64740.20"
- process $proc$libresoc.v:64740$3579
+ attribute \src "libresoc.v:64090.7-64090.20"
+ process $proc$libresoc.v:64090$3552
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:66148.3-66205.6"
- process $proc$libresoc.v:66148$3566
+ attribute \src "libresoc.v:65498.3-65555.6"
+ process $proc$libresoc.v:65498$3539
assign { } { }
assign { } { }
assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0]
- attribute \src "libresoc.v:66149.5-66149.29"
+ attribute \src "libresoc.v:65499.5-65499.29"
switch \initial
- attribute \src "libresoc.v:66149.9-66149.17"
+ attribute \src "libresoc.v:65499.9-65499.17"
case 1'1
case
end
sync always
update \LDST_ldst_len $0\LDST_ldst_len[3:0]
end
- attribute \src "libresoc.v:66206.3-66263.6"
- process $proc$libresoc.v:66206$3567
+ attribute \src "libresoc.v:65556.3-65613.6"
+ process $proc$libresoc.v:65556$3540
assign { } { }
assign { } { }
assign $0\LDST_upd[1:0] $1\LDST_upd[1:0]
- attribute \src "libresoc.v:66207.5-66207.29"
+ attribute \src "libresoc.v:65557.5-65557.29"
switch \initial
- attribute \src "libresoc.v:66207.9-66207.17"
+ attribute \src "libresoc.v:65557.9-65557.17"
case 1'1
case
end
sync always
update \LDST_upd $0\LDST_upd[1:0]
end
- attribute \src "libresoc.v:66264.3-66321.6"
- process $proc$libresoc.v:66264$3568
+ attribute \src "libresoc.v:65614.3-65671.6"
+ process $proc$libresoc.v:65614$3541
assign { } { }
assign { } { }
assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0]
- attribute \src "libresoc.v:66265.5-66265.29"
+ attribute \src "libresoc.v:65615.5-65615.29"
switch \initial
- attribute \src "libresoc.v:66265.9-66265.17"
+ attribute \src "libresoc.v:65615.9-65615.17"
case 1'1
case
end
sync always
update \LDST_rc_sel $0\LDST_rc_sel[1:0]
end
- attribute \src "libresoc.v:66322.3-66379.6"
- process $proc$libresoc.v:66322$3569
+ attribute \src "libresoc.v:65672.3-65729.6"
+ process $proc$libresoc.v:65672$3542
assign { } { }
assign { } { }
assign $0\LDST_br[0:0] $1\LDST_br[0:0]
- attribute \src "libresoc.v:66323.5-66323.29"
+ attribute \src "libresoc.v:65673.5-65673.29"
switch \initial
- attribute \src "libresoc.v:66323.9-66323.17"
+ attribute \src "libresoc.v:65673.9-65673.17"
case 1'1
case
end
sync always
update \LDST_br $0\LDST_br[0:0]
end
- attribute \src "libresoc.v:66380.3-66437.6"
- process $proc$libresoc.v:66380$3570
+ attribute \src "libresoc.v:65730.3-65787.6"
+ process $proc$libresoc.v:65730$3543
assign { } { }
assign { } { }
assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0]
- attribute \src "libresoc.v:66381.5-66381.29"
+ attribute \src "libresoc.v:65731.5-65731.29"
switch \initial
- attribute \src "libresoc.v:66381.9-66381.17"
+ attribute \src "libresoc.v:65731.9-65731.17"
case 1'1
case
end
sync always
update \LDST_sgn_ext $0\LDST_sgn_ext[0:0]
end
- attribute \src "libresoc.v:66438.3-66495.6"
- process $proc$libresoc.v:66438$3571
+ attribute \src "libresoc.v:65788.3-65845.6"
+ process $proc$libresoc.v:65788$3544
assign { } { }
assign { } { }
assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0]
- attribute \src "libresoc.v:66439.5-66439.29"
+ attribute \src "libresoc.v:65789.5-65789.29"
switch \initial
- attribute \src "libresoc.v:66439.9-66439.17"
+ attribute \src "libresoc.v:65789.9-65789.17"
case 1'1
case
end
sync always
update \LDST_is_32b $0\LDST_is_32b[0:0]
end
- attribute \src "libresoc.v:66496.3-66553.6"
- process $proc$libresoc.v:66496$3572
+ attribute \src "libresoc.v:65846.3-65903.6"
+ process $proc$libresoc.v:65846$3545
assign { } { }
assign { } { }
assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0]
- attribute \src "libresoc.v:66497.5-66497.29"
+ attribute \src "libresoc.v:65847.5-65847.29"
switch \initial
- attribute \src "libresoc.v:66497.9-66497.17"
+ attribute \src "libresoc.v:65847.9-65847.17"
case 1'1
case
end
sync always
update \LDST_sgn $0\LDST_sgn[0:0]
end
- attribute \src "libresoc.v:66554.3-66611.6"
- process $proc$libresoc.v:66554$3573
+ attribute \src "libresoc.v:65904.3-65961.6"
+ process $proc$libresoc.v:65904$3546
assign { } { }
assign { } { }
assign $0\LDST_function_unit[12:0] $1\LDST_function_unit[12:0]
- attribute \src "libresoc.v:66555.5-66555.29"
+ attribute \src "libresoc.v:65905.5-65905.29"
switch \initial
- attribute \src "libresoc.v:66555.9-66555.17"
+ attribute \src "libresoc.v:65905.9-65905.17"
case 1'1
case
end
sync always
update \LDST_function_unit $0\LDST_function_unit[12:0]
end
- attribute \src "libresoc.v:66612.3-66669.6"
- process $proc$libresoc.v:66612$3574
+ attribute \src "libresoc.v:65962.3-66019.6"
+ process $proc$libresoc.v:65962$3547
assign { } { }
assign { } { }
assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0]
- attribute \src "libresoc.v:66613.5-66613.29"
+ attribute \src "libresoc.v:65963.5-65963.29"
switch \initial
- attribute \src "libresoc.v:66613.9-66613.17"
+ attribute \src "libresoc.v:65963.9-65963.17"
case 1'1
case
end
sync always
update \LDST_internal_op $0\LDST_internal_op[6:0]
end
- attribute \src "libresoc.v:66670.3-66727.6"
- process $proc$libresoc.v:66670$3575
+ attribute \src "libresoc.v:66020.3-66077.6"
+ process $proc$libresoc.v:66020$3548
assign { } { }
assign { } { }
assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0]
- attribute \src "libresoc.v:66671.5-66671.29"
+ attribute \src "libresoc.v:66021.5-66021.29"
switch \initial
- attribute \src "libresoc.v:66671.9-66671.17"
+ attribute \src "libresoc.v:66021.9-66021.17"
case 1'1
case
end
sync always
update \LDST_in1_sel $0\LDST_in1_sel[2:0]
end
- attribute \src "libresoc.v:66728.3-66785.6"
- process $proc$libresoc.v:66728$3576
+ attribute \src "libresoc.v:66078.3-66135.6"
+ process $proc$libresoc.v:66078$3549
assign { } { }
assign { } { }
assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0]
- attribute \src "libresoc.v:66729.5-66729.29"
+ attribute \src "libresoc.v:66079.5-66079.29"
switch \initial
- attribute \src "libresoc.v:66729.9-66729.17"
+ attribute \src "libresoc.v:66079.9-66079.17"
case 1'1
case
end
sync always
update \LDST_in2_sel $0\LDST_in2_sel[3:0]
end
- attribute \src "libresoc.v:66786.3-66843.6"
- process $proc$libresoc.v:66786$3577
+ attribute \src "libresoc.v:66136.3-66193.6"
+ process $proc$libresoc.v:66136$3550
assign { } { }
assign { } { }
assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0]
- attribute \src "libresoc.v:66787.5-66787.29"
+ attribute \src "libresoc.v:66137.5-66137.29"
switch \initial
- attribute \src "libresoc.v:66787.9-66787.17"
+ attribute \src "libresoc.v:66137.9-66137.17"
case 1'1
case
end
sync always
update \LDST_cr_in $0\LDST_cr_in[2:0]
end
- attribute \src "libresoc.v:66844.3-66901.6"
- process $proc$libresoc.v:66844$3578
+ attribute \src "libresoc.v:66194.3-66251.6"
+ process $proc$libresoc.v:66194$3551
assign { } { }
assign { } { }
assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0]
- attribute \src "libresoc.v:66845.5-66845.29"
+ attribute \src "libresoc.v:66195.5-66195.29"
switch \initial
- attribute \src "libresoc.v:66845.9-66845.17"
+ attribute \src "libresoc.v:66195.9-66195.17"
case 1'1
case
end
sync always
update \LDST_cr_out $0\LDST_cr_out[2:0]
end
- connect \$1 $ternary$libresoc.v:66099$3565_Y
+ connect \$1 $ternary$libresoc.v:65449$3538_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \LDST_dec31_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:67244.1-74801.10"
+attribute \src "libresoc.v:66594.1-74144.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec"
attribute \generator "nMigen"
module \dec$171
- attribute \src "libresoc.v:70058.3-70199.6"
+ attribute \src "libresoc.v:69401.3-69542.6"
wire width 2 $0\SV_Etype[1:0]
- attribute \src "libresoc.v:70200.3-70341.6"
+ attribute \src "libresoc.v:69543.3-69684.6"
wire width 2 $0\SV_Ptype[1:0]
- attribute \src "libresoc.v:69919.3-70057.6"
+ attribute \src "libresoc.v:69262.3-69400.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:73040.3-73181.6"
+ attribute \src "libresoc.v:72383.3-72524.6"
wire $0\br[0:0]
- attribute \src "libresoc.v:70910.3-71051.6"
+ attribute \src "libresoc.v:70253.3-70394.6"
wire width 3 $0\cr_in[2:0]
- attribute \src "libresoc.v:71052.3-71193.6"
+ attribute \src "libresoc.v:70395.3-70536.6"
wire width 3 $0\cr_out[2:0]
- attribute \src "libresoc.v:72472.3-72613.6"
+ attribute \src "libresoc.v:71815.3-71956.6"
wire width 2 $0\cry_in[1:0]
- attribute \src "libresoc.v:72898.3-73039.6"
+ attribute \src "libresoc.v:72241.3-72382.6"
wire $0\cry_out[0:0]
- attribute \src "libresoc.v:74318.3-74459.6"
+ attribute \src "libresoc.v:73661.3-73802.6"
wire width 5 $0\form[4:0]
- attribute \src "libresoc.v:74034.3-74175.6"
+ attribute \src "libresoc.v:73377.3-73518.6"
wire width 13 $0\function_unit[12:0]
- attribute \src "libresoc.v:70342.3-70483.6"
+ attribute \src "libresoc.v:69685.3-69826.6"
wire width 3 $0\in1_sel[2:0]
- attribute \src "libresoc.v:70484.3-70625.6"
+ attribute \src "libresoc.v:69827.3-69968.6"
wire width 4 $0\in2_sel[3:0]
- attribute \src "libresoc.v:70626.3-70767.6"
+ attribute \src "libresoc.v:69969.3-70110.6"
wire width 2 $0\in3_sel[1:0]
- attribute \src "libresoc.v:67245.7-67245.20"
+ attribute \src "libresoc.v:66595.7-66595.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:74176.3-74317.6"
+ attribute \src "libresoc.v:73519.3-73660.6"
wire width 7 $0\internal_op[6:0]
- attribute \src "libresoc.v:72614.3-72755.6"
+ attribute \src "libresoc.v:71957.3-72098.6"
wire $0\inv_a[0:0]
- attribute \src "libresoc.v:72756.3-72897.6"
+ attribute \src "libresoc.v:72099.3-72240.6"
wire $0\inv_out[0:0]
- attribute \src "libresoc.v:73466.3-73607.6"
+ attribute \src "libresoc.v:72809.3-72950.6"
wire $0\is_32b[0:0]
- attribute \src "libresoc.v:72046.3-72187.6"
+ attribute \src "libresoc.v:71389.3-71530.6"
wire width 4 $0\ldst_len[3:0]
- attribute \src "libresoc.v:73750.3-73891.6"
+ attribute \src "libresoc.v:73093.3-73234.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:70768.3-70909.6"
+ attribute \src "libresoc.v:70111.3-70252.6"
wire width 2 $0\out_sel[1:0]
- attribute \src "libresoc.v:72330.3-72471.6"
+ attribute \src "libresoc.v:71673.3-71814.6"
wire width 2 $0\rc_sel[1:0]
- attribute \src "libresoc.v:73324.3-73465.6"
+ attribute \src "libresoc.v:72667.3-72808.6"
wire $0\rsrv[0:0]
- attribute \src "libresoc.v:73892.3-74033.6"
+ attribute \src "libresoc.v:73235.3-73376.6"
wire $0\sgl_pipe[0:0]
- attribute \src "libresoc.v:73608.3-73749.6"
+ attribute \src "libresoc.v:72951.3-73092.6"
wire $0\sgn[0:0]
- attribute \src "libresoc.v:73182.3-73323.6"
+ attribute \src "libresoc.v:72525.3-72666.6"
wire $0\sgn_ext[0:0]
- attribute \src "libresoc.v:71762.3-71903.6"
+ attribute \src "libresoc.v:71105.3-71246.6"
wire width 3 $0\sv_cr_in[2:0]
- attribute \src "libresoc.v:71904.3-72045.6"
+ attribute \src "libresoc.v:71247.3-71388.6"
wire width 3 $0\sv_cr_out[2:0]
- attribute \src "libresoc.v:71194.3-71335.6"
+ attribute \src "libresoc.v:70537.3-70678.6"
wire width 3 $0\sv_in1[2:0]
- attribute \src "libresoc.v:71336.3-71477.6"
+ attribute \src "libresoc.v:70679.3-70820.6"
wire width 3 $0\sv_in2[2:0]
- attribute \src "libresoc.v:71478.3-71619.6"
+ attribute \src "libresoc.v:70821.3-70962.6"
wire width 3 $0\sv_in3[2:0]
- attribute \src "libresoc.v:71620.3-71761.6"
+ attribute \src "libresoc.v:70963.3-71104.6"
wire width 3 $0\sv_out[2:0]
- attribute \src "libresoc.v:72188.3-72329.6"
+ attribute \src "libresoc.v:71531.3-71672.6"
wire width 2 $0\upd[1:0]
- attribute \src "libresoc.v:70058.3-70199.6"
+ attribute \src "libresoc.v:69401.3-69542.6"
wire width 2 $1\SV_Etype[1:0]
- attribute \src "libresoc.v:70200.3-70341.6"
+ attribute \src "libresoc.v:69543.3-69684.6"
wire width 2 $1\SV_Ptype[1:0]
- attribute \src "libresoc.v:69919.3-70057.6"
+ attribute \src "libresoc.v:69262.3-69400.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:73040.3-73181.6"
+ attribute \src "libresoc.v:72383.3-72524.6"
wire $1\br[0:0]
- attribute \src "libresoc.v:70910.3-71051.6"
+ attribute \src "libresoc.v:70253.3-70394.6"
wire width 3 $1\cr_in[2:0]
- attribute \src "libresoc.v:71052.3-71193.6"
+ attribute \src "libresoc.v:70395.3-70536.6"
wire width 3 $1\cr_out[2:0]
- attribute \src "libresoc.v:72472.3-72613.6"
+ attribute \src "libresoc.v:71815.3-71956.6"
wire width 2 $1\cry_in[1:0]
- attribute \src "libresoc.v:72898.3-73039.6"
+ attribute \src "libresoc.v:72241.3-72382.6"
wire $1\cry_out[0:0]
- attribute \src "libresoc.v:74318.3-74459.6"
+ attribute \src "libresoc.v:73661.3-73802.6"
wire width 5 $1\form[4:0]
- attribute \src "libresoc.v:74034.3-74175.6"
+ attribute \src "libresoc.v:73377.3-73518.6"
wire width 13 $1\function_unit[12:0]
- attribute \src "libresoc.v:70342.3-70483.6"
+ attribute \src "libresoc.v:69685.3-69826.6"
wire width 3 $1\in1_sel[2:0]
- attribute \src "libresoc.v:70484.3-70625.6"
+ attribute \src "libresoc.v:69827.3-69968.6"
wire width 4 $1\in2_sel[3:0]
- attribute \src "libresoc.v:70626.3-70767.6"
+ attribute \src "libresoc.v:69969.3-70110.6"
wire width 2 $1\in3_sel[1:0]
- attribute \src "libresoc.v:74176.3-74317.6"
+ attribute \src "libresoc.v:73519.3-73660.6"
wire width 7 $1\internal_op[6:0]
- attribute \src "libresoc.v:72614.3-72755.6"
+ attribute \src "libresoc.v:71957.3-72098.6"
wire $1\inv_a[0:0]
- attribute \src "libresoc.v:72756.3-72897.6"
+ attribute \src "libresoc.v:72099.3-72240.6"
wire $1\inv_out[0:0]
- attribute \src "libresoc.v:73466.3-73607.6"
+ attribute \src "libresoc.v:72809.3-72950.6"
wire $1\is_32b[0:0]
- attribute \src "libresoc.v:72046.3-72187.6"
+ attribute \src "libresoc.v:71389.3-71530.6"
wire width 4 $1\ldst_len[3:0]
- attribute \src "libresoc.v:73750.3-73891.6"
+ attribute \src "libresoc.v:73093.3-73234.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:70768.3-70909.6"
+ attribute \src "libresoc.v:70111.3-70252.6"
wire width 2 $1\out_sel[1:0]
- attribute \src "libresoc.v:72330.3-72471.6"
+ attribute \src "libresoc.v:71673.3-71814.6"
wire width 2 $1\rc_sel[1:0]
- attribute \src "libresoc.v:73324.3-73465.6"
+ attribute \src "libresoc.v:72667.3-72808.6"
wire $1\rsrv[0:0]
- attribute \src "libresoc.v:73892.3-74033.6"
+ attribute \src "libresoc.v:73235.3-73376.6"
wire $1\sgl_pipe[0:0]
- attribute \src "libresoc.v:73608.3-73749.6"
+ attribute \src "libresoc.v:72951.3-73092.6"
wire $1\sgn[0:0]
- attribute \src "libresoc.v:73182.3-73323.6"
+ attribute \src "libresoc.v:72525.3-72666.6"
wire $1\sgn_ext[0:0]
- attribute \src "libresoc.v:71762.3-71903.6"
+ attribute \src "libresoc.v:71105.3-71246.6"
wire width 3 $1\sv_cr_in[2:0]
- attribute \src "libresoc.v:71904.3-72045.6"
+ attribute \src "libresoc.v:71247.3-71388.6"
wire width 3 $1\sv_cr_out[2:0]
- attribute \src "libresoc.v:71194.3-71335.6"
+ attribute \src "libresoc.v:70537.3-70678.6"
wire width 3 $1\sv_in1[2:0]
- attribute \src "libresoc.v:71336.3-71477.6"
+ attribute \src "libresoc.v:70679.3-70820.6"
wire width 3 $1\sv_in2[2:0]
- attribute \src "libresoc.v:71478.3-71619.6"
+ attribute \src "libresoc.v:70821.3-70962.6"
wire width 3 $1\sv_in3[2:0]
- attribute \src "libresoc.v:71620.3-71761.6"
+ attribute \src "libresoc.v:70963.3-71104.6"
wire width 3 $1\sv_out[2:0]
- attribute \src "libresoc.v:72188.3-72329.6"
+ attribute \src "libresoc.v:71531.3-71672.6"
wire width 2 $1\upd[1:0]
- attribute \src "libresoc.v:70058.3-70199.6"
+ attribute \src "libresoc.v:69401.3-69542.6"
wire width 2 $2\SV_Etype[1:0]
- attribute \src "libresoc.v:70200.3-70341.6"
+ attribute \src "libresoc.v:69543.3-69684.6"
wire width 2 $2\SV_Ptype[1:0]
- attribute \src "libresoc.v:69919.3-70057.6"
+ attribute \src "libresoc.v:69262.3-69400.6"
wire width 8 $2\asmcode[7:0]
- attribute \src "libresoc.v:73040.3-73181.6"
+ attribute \src "libresoc.v:72383.3-72524.6"
wire $2\br[0:0]
- attribute \src "libresoc.v:70910.3-71051.6"
+ attribute \src "libresoc.v:70253.3-70394.6"
wire width 3 $2\cr_in[2:0]
- attribute \src "libresoc.v:71052.3-71193.6"
+ attribute \src "libresoc.v:70395.3-70536.6"
wire width 3 $2\cr_out[2:0]
- attribute \src "libresoc.v:72472.3-72613.6"
+ attribute \src "libresoc.v:71815.3-71956.6"
wire width 2 $2\cry_in[1:0]
- attribute \src "libresoc.v:72898.3-73039.6"
+ attribute \src "libresoc.v:72241.3-72382.6"
wire $2\cry_out[0:0]
- attribute \src "libresoc.v:74318.3-74459.6"
+ attribute \src "libresoc.v:73661.3-73802.6"
wire width 5 $2\form[4:0]
- attribute \src "libresoc.v:74034.3-74175.6"
+ attribute \src "libresoc.v:73377.3-73518.6"
wire width 13 $2\function_unit[12:0]
- attribute \src "libresoc.v:70342.3-70483.6"
+ attribute \src "libresoc.v:69685.3-69826.6"
wire width 3 $2\in1_sel[2:0]
- attribute \src "libresoc.v:70484.3-70625.6"
+ attribute \src "libresoc.v:69827.3-69968.6"
wire width 4 $2\in2_sel[3:0]
- attribute \src "libresoc.v:70626.3-70767.6"
+ attribute \src "libresoc.v:69969.3-70110.6"
wire width 2 $2\in3_sel[1:0]
- attribute \src "libresoc.v:74176.3-74317.6"
+ attribute \src "libresoc.v:73519.3-73660.6"
wire width 7 $2\internal_op[6:0]
- attribute \src "libresoc.v:72614.3-72755.6"
+ attribute \src "libresoc.v:71957.3-72098.6"
wire $2\inv_a[0:0]
- attribute \src "libresoc.v:72756.3-72897.6"
+ attribute \src "libresoc.v:72099.3-72240.6"
wire $2\inv_out[0:0]
- attribute \src "libresoc.v:73466.3-73607.6"
+ attribute \src "libresoc.v:72809.3-72950.6"
wire $2\is_32b[0:0]
- attribute \src "libresoc.v:72046.3-72187.6"
+ attribute \src "libresoc.v:71389.3-71530.6"
wire width 4 $2\ldst_len[3:0]
- attribute \src "libresoc.v:73750.3-73891.6"
+ attribute \src "libresoc.v:73093.3-73234.6"
wire $2\lk[0:0]
- attribute \src "libresoc.v:70768.3-70909.6"
+ attribute \src "libresoc.v:70111.3-70252.6"
wire width 2 $2\out_sel[1:0]
- attribute \src "libresoc.v:72330.3-72471.6"
+ attribute \src "libresoc.v:71673.3-71814.6"
wire width 2 $2\rc_sel[1:0]
- attribute \src "libresoc.v:73324.3-73465.6"
+ attribute \src "libresoc.v:72667.3-72808.6"
wire $2\rsrv[0:0]
- attribute \src "libresoc.v:73892.3-74033.6"
+ attribute \src "libresoc.v:73235.3-73376.6"
wire $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:73608.3-73749.6"
+ attribute \src "libresoc.v:72951.3-73092.6"
wire $2\sgn[0:0]
- attribute \src "libresoc.v:73182.3-73323.6"
+ attribute \src "libresoc.v:72525.3-72666.6"
wire $2\sgn_ext[0:0]
- attribute \src "libresoc.v:71762.3-71903.6"
+ attribute \src "libresoc.v:71105.3-71246.6"
wire width 3 $2\sv_cr_in[2:0]
- attribute \src "libresoc.v:71904.3-72045.6"
+ attribute \src "libresoc.v:71247.3-71388.6"
wire width 3 $2\sv_cr_out[2:0]
- attribute \src "libresoc.v:71194.3-71335.6"
+ attribute \src "libresoc.v:70537.3-70678.6"
wire width 3 $2\sv_in1[2:0]
- attribute \src "libresoc.v:71336.3-71477.6"
+ attribute \src "libresoc.v:70679.3-70820.6"
wire width 3 $2\sv_in2[2:0]
- attribute \src "libresoc.v:71478.3-71619.6"
+ attribute \src "libresoc.v:70821.3-70962.6"
wire width 3 $2\sv_in3[2:0]
- attribute \src "libresoc.v:71620.3-71761.6"
+ attribute \src "libresoc.v:70963.3-71104.6"
wire width 3 $2\sv_out[2:0]
- attribute \src "libresoc.v:72188.3-72329.6"
+ attribute \src "libresoc.v:71531.3-71672.6"
wire width 2 $2\upd[1:0]
- attribute \src "libresoc.v:69743.17-69743.211"
- wire width 32 $ternary$libresoc.v:69743$3580_Y
+ attribute \src "libresoc.v:69086.17-69086.211"
+ wire width 32 $ternary$libresoc.v:69086$3553_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
wire width 32 \$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 5 \A_XO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 33 \BA
+ wire width 5 output 26 \BA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 32 \BB
+ wire width 5 output 25 \BB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 38 \BC
+ wire width 5 output 31 \BC
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 14 \BD
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 2 \BH
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 37 \BI
+ wire width 5 output 30 \BI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 36 \BO
+ wire width 5 output 29 \BO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 34 \BT
+ wire width 5 output 27 \BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \B_AA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 3 \EVS_BFA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 8 output 35 \FXM
+ wire width 8 output 28 \FXM
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \I_AA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 5 \M_SH
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire output 31 \OE
+ wire output 24 \OE
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 28 \RA
+ wire width 5 output 21 \RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 29 \RB
+ wire width 5 output 22 \RB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 26 \RS
+ wire width 5 output 19 \RS
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 output 27 \RT
+ wire width 5 output 20 \RT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire output 30 \Rc
+ wire output 23 \Rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 7 \SC_LEV
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \enum_value_01 "EXTRA2"
attribute \enum_value_10 "EXTRA3"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 2 output 19 \SV_Etype
+ wire width 2 \SV_Etype
attribute \enum_base_type "SVPtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "P1"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 5 \XL_BO_1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 5 output 41 \XL_BT
+ wire width 5 output 34 \XL_BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \XL_LK
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \XL_S
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 10 output 42 \XL_XO
+ wire width 10 output 35 \XL_XO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \XO_OE
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire \X_A
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 3 output 39 \X_BF
+ wire width 3 output 32 \X_BF
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 3 output 40 \X_BFA
+ wire width 3 output 33 \X_BFA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 5 \X_BO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 6 \all_PO
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 8 output 24 \asmcode
+ wire width 8 output 17 \asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
- wire input 43 \bigendian
+ wire input 36 \bigendian
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196"
wire \br
attribute \enum_base_type "CRInSel"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 15 \in1_sel
+ wire width 3 output 13 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 4 output 16 \in2_sel
+ wire width 4 output 14 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 2 output 17 \in3_sel
- attribute \src "libresoc.v:67245.7-67245.15"
+ wire width 2 output 15 \in3_sel
+ attribute \src "libresoc.v:66595.7-66595.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 2 output 18 \out_sel
+ wire width 2 output 16 \out_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 1 \raw_opcode_in
attribute \enum_base_type "RC"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 14 \sv_cr_in
+ wire width 3 \sv_cr_in
attribute \enum_base_type "SVEXTRA"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "Idx0"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 13 \sv_cr_out
+ wire width 3 \sv_cr_out
attribute \enum_base_type "SVEXTRA"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "Idx0"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 20 \sv_in1
+ wire width 3 \sv_in1
attribute \enum_base_type "SVEXTRA"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "Idx0"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 21 \sv_in2
+ wire width 3 \sv_in2
attribute \enum_base_type "SVEXTRA"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "Idx0"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 22 \sv_in3
+ wire width 3 \sv_in3
attribute \enum_base_type "SVEXTRA"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "Idx0"
attribute \enum_value_100 "Idx3"
attribute \enum_value_101 "Idx_1_2"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 output 23 \sv_out
+ wire width 3 \sv_out
attribute \enum_base_type "LDSTMode"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "update"
attribute \enum_value_10 "cix"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 2 output 25 \upd
+ wire width 2 output 18 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504"
- cell $mux $ternary$libresoc.v:69743$3580
+ cell $mux $ternary$libresoc.v:69086$3553
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:69743$3580_Y
+ connect \Y $ternary$libresoc.v:69086$3553_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69744.9-69778.4"
+ attribute \src "libresoc.v:69087.9-69121.4"
cell \dec19 \dec19
connect \dec19_SV_Etype \dec19_dec19_SV_Etype
connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype
connect \opcode_in \dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69779.9-69813.4"
+ attribute \src "libresoc.v:69122.9-69156.4"
cell \dec30 \dec30
connect \dec30_SV_Etype \dec30_dec30_SV_Etype
connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype
connect \opcode_in \dec30_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69814.9-69848.4"
+ attribute \src "libresoc.v:69157.9-69191.4"
cell \dec31 \dec31
connect \dec31_SV_Etype \dec31_dec31_SV_Etype
connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype
connect \opcode_in \dec31_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69849.9-69883.4"
+ attribute \src "libresoc.v:69192.9-69226.4"
cell \dec58 \dec58
connect \dec58_SV_Etype \dec58_dec58_SV_Etype
connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype
connect \opcode_in \dec58_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:69884.9-69918.4"
+ attribute \src "libresoc.v:69227.9-69261.4"
cell \dec62 \dec62
connect \dec62_SV_Etype \dec62_dec62_SV_Etype
connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype
connect \dec62_upd \dec62_dec62_upd
connect \opcode_in \dec62_opcode_in
end
- attribute \src "libresoc.v:67245.7-67245.20"
- process $proc$libresoc.v:67245$3613
+ attribute \src "libresoc.v:66595.7-66595.20"
+ process $proc$libresoc.v:66595$3586
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:69919.3-70057.6"
- process $proc$libresoc.v:69919$3581
+ attribute \src "libresoc.v:69262.3-69400.6"
+ process $proc$libresoc.v:69262$3554
assign { } { }
assign { } { }
assign { } { }
assign $0\asmcode[7:0] $2\asmcode[7:0]
- attribute \src "libresoc.v:69920.5-69920.29"
+ attribute \src "libresoc.v:69263.5-69263.29"
switch \initial
- attribute \src "libresoc.v:69920.9-69920.17"
+ attribute \src "libresoc.v:69263.9-69263.17"
case 1'1
case
end
sync always
update \asmcode $0\asmcode[7:0]
end
- attribute \src "libresoc.v:70058.3-70199.6"
- process $proc$libresoc.v:70058$3582
+ attribute \src "libresoc.v:69401.3-69542.6"
+ process $proc$libresoc.v:69401$3555
assign { } { }
assign { } { }
assign { } { }
assign $0\SV_Etype[1:0] $2\SV_Etype[1:0]
- attribute \src "libresoc.v:70059.5-70059.29"
+ attribute \src "libresoc.v:69402.5-69402.29"
switch \initial
- attribute \src "libresoc.v:70059.9-70059.17"
+ attribute \src "libresoc.v:69402.9-69402.17"
case 1'1
case
end
sync always
update \SV_Etype $0\SV_Etype[1:0]
end
- attribute \src "libresoc.v:70200.3-70341.6"
- process $proc$libresoc.v:70200$3583
+ attribute \src "libresoc.v:69543.3-69684.6"
+ process $proc$libresoc.v:69543$3556
assign { } { }
assign { } { }
assign { } { }
assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0]
- attribute \src "libresoc.v:70201.5-70201.29"
+ attribute \src "libresoc.v:69544.5-69544.29"
switch \initial
- attribute \src "libresoc.v:70201.9-70201.17"
+ attribute \src "libresoc.v:69544.9-69544.17"
case 1'1
case
end
sync always
update \SV_Ptype $0\SV_Ptype[1:0]
end
- attribute \src "libresoc.v:70342.3-70483.6"
- process $proc$libresoc.v:70342$3584
+ attribute \src "libresoc.v:69685.3-69826.6"
+ process $proc$libresoc.v:69685$3557
assign { } { }
assign { } { }
assign { } { }
assign $0\in1_sel[2:0] $2\in1_sel[2:0]
- attribute \src "libresoc.v:70343.5-70343.29"
+ attribute \src "libresoc.v:69686.5-69686.29"
switch \initial
- attribute \src "libresoc.v:70343.9-70343.17"
+ attribute \src "libresoc.v:69686.9-69686.17"
case 1'1
case
end
sync always
update \in1_sel $0\in1_sel[2:0]
end
- attribute \src "libresoc.v:70484.3-70625.6"
- process $proc$libresoc.v:70484$3585
+ attribute \src "libresoc.v:69827.3-69968.6"
+ process $proc$libresoc.v:69827$3558
assign { } { }
assign { } { }
assign { } { }
assign $0\in2_sel[3:0] $2\in2_sel[3:0]
- attribute \src "libresoc.v:70485.5-70485.29"
+ attribute \src "libresoc.v:69828.5-69828.29"
switch \initial
- attribute \src "libresoc.v:70485.9-70485.17"
+ attribute \src "libresoc.v:69828.9-69828.17"
case 1'1
case
end
sync always
update \in2_sel $0\in2_sel[3:0]
end
- attribute \src "libresoc.v:70626.3-70767.6"
- process $proc$libresoc.v:70626$3586
+ attribute \src "libresoc.v:69969.3-70110.6"
+ process $proc$libresoc.v:69969$3559
assign { } { }
assign { } { }
assign { } { }
assign $0\in3_sel[1:0] $2\in3_sel[1:0]
- attribute \src "libresoc.v:70627.5-70627.29"
+ attribute \src "libresoc.v:69970.5-69970.29"
switch \initial
- attribute \src "libresoc.v:70627.9-70627.17"
+ attribute \src "libresoc.v:69970.9-69970.17"
case 1'1
case
end
sync always
update \in3_sel $0\in3_sel[1:0]
end
- attribute \src "libresoc.v:70768.3-70909.6"
- process $proc$libresoc.v:70768$3587
+ attribute \src "libresoc.v:70111.3-70252.6"
+ process $proc$libresoc.v:70111$3560
assign { } { }
assign { } { }
assign { } { }
assign $0\out_sel[1:0] $2\out_sel[1:0]
- attribute \src "libresoc.v:70769.5-70769.29"
+ attribute \src "libresoc.v:70112.5-70112.29"
switch \initial
- attribute \src "libresoc.v:70769.9-70769.17"
+ attribute \src "libresoc.v:70112.9-70112.17"
case 1'1
case
end
sync always
update \out_sel $0\out_sel[1:0]
end
- attribute \src "libresoc.v:70910.3-71051.6"
- process $proc$libresoc.v:70910$3588
+ attribute \src "libresoc.v:70253.3-70394.6"
+ process $proc$libresoc.v:70253$3561
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_in[2:0] $2\cr_in[2:0]
- attribute \src "libresoc.v:70911.5-70911.29"
+ attribute \src "libresoc.v:70254.5-70254.29"
switch \initial
- attribute \src "libresoc.v:70911.9-70911.17"
+ attribute \src "libresoc.v:70254.9-70254.17"
case 1'1
case
end
sync always
update \cr_in $0\cr_in[2:0]
end
- attribute \src "libresoc.v:71052.3-71193.6"
- process $proc$libresoc.v:71052$3589
+ attribute \src "libresoc.v:70395.3-70536.6"
+ process $proc$libresoc.v:70395$3562
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_out[2:0] $2\cr_out[2:0]
- attribute \src "libresoc.v:71053.5-71053.29"
+ attribute \src "libresoc.v:70396.5-70396.29"
switch \initial
- attribute \src "libresoc.v:71053.9-71053.17"
+ attribute \src "libresoc.v:70396.9-70396.17"
case 1'1
case
end
sync always
update \cr_out $0\cr_out[2:0]
end
- attribute \src "libresoc.v:71194.3-71335.6"
- process $proc$libresoc.v:71194$3590
+ attribute \src "libresoc.v:70537.3-70678.6"
+ process $proc$libresoc.v:70537$3563
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in1[2:0] $2\sv_in1[2:0]
- attribute \src "libresoc.v:71195.5-71195.29"
+ attribute \src "libresoc.v:70538.5-70538.29"
switch \initial
- attribute \src "libresoc.v:71195.9-71195.17"
+ attribute \src "libresoc.v:70538.9-70538.17"
case 1'1
case
end
sync always
update \sv_in1 $0\sv_in1[2:0]
end
- attribute \src "libresoc.v:71336.3-71477.6"
- process $proc$libresoc.v:71336$3591
+ attribute \src "libresoc.v:70679.3-70820.6"
+ process $proc$libresoc.v:70679$3564
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in2[2:0] $2\sv_in2[2:0]
- attribute \src "libresoc.v:71337.5-71337.29"
+ attribute \src "libresoc.v:70680.5-70680.29"
switch \initial
- attribute \src "libresoc.v:71337.9-71337.17"
+ attribute \src "libresoc.v:70680.9-70680.17"
case 1'1
case
end
sync always
update \sv_in2 $0\sv_in2[2:0]
end
- attribute \src "libresoc.v:71478.3-71619.6"
- process $proc$libresoc.v:71478$3592
+ attribute \src "libresoc.v:70821.3-70962.6"
+ process $proc$libresoc.v:70821$3565
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_in3[2:0] $2\sv_in3[2:0]
- attribute \src "libresoc.v:71479.5-71479.29"
+ attribute \src "libresoc.v:70822.5-70822.29"
switch \initial
- attribute \src "libresoc.v:71479.9-71479.17"
+ attribute \src "libresoc.v:70822.9-70822.17"
case 1'1
case
end
sync always
update \sv_in3 $0\sv_in3[2:0]
end
- attribute \src "libresoc.v:71620.3-71761.6"
- process $proc$libresoc.v:71620$3593
+ attribute \src "libresoc.v:70963.3-71104.6"
+ process $proc$libresoc.v:70963$3566
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_out[2:0] $2\sv_out[2:0]
- attribute \src "libresoc.v:71621.5-71621.29"
+ attribute \src "libresoc.v:70964.5-70964.29"
switch \initial
- attribute \src "libresoc.v:71621.9-71621.17"
+ attribute \src "libresoc.v:70964.9-70964.17"
case 1'1
case
end
sync always
update \sv_out $0\sv_out[2:0]
end
- attribute \src "libresoc.v:71762.3-71903.6"
- process $proc$libresoc.v:71762$3594
+ attribute \src "libresoc.v:71105.3-71246.6"
+ process $proc$libresoc.v:71105$3567
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0]
- attribute \src "libresoc.v:71763.5-71763.29"
+ attribute \src "libresoc.v:71106.5-71106.29"
switch \initial
- attribute \src "libresoc.v:71763.9-71763.17"
+ attribute \src "libresoc.v:71106.9-71106.17"
case 1'1
case
end
sync always
update \sv_cr_in $0\sv_cr_in[2:0]
end
- attribute \src "libresoc.v:71904.3-72045.6"
- process $proc$libresoc.v:71904$3595
+ attribute \src "libresoc.v:71247.3-71388.6"
+ process $proc$libresoc.v:71247$3568
assign { } { }
assign { } { }
assign { } { }
assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0]
- attribute \src "libresoc.v:71905.5-71905.29"
+ attribute \src "libresoc.v:71248.5-71248.29"
switch \initial
- attribute \src "libresoc.v:71905.9-71905.17"
+ attribute \src "libresoc.v:71248.9-71248.17"
case 1'1
case
end
sync always
update \sv_cr_out $0\sv_cr_out[2:0]
end
- attribute \src "libresoc.v:72046.3-72187.6"
- process $proc$libresoc.v:72046$3596
+ attribute \src "libresoc.v:71389.3-71530.6"
+ process $proc$libresoc.v:71389$3569
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_len[3:0] $2\ldst_len[3:0]
- attribute \src "libresoc.v:72047.5-72047.29"
+ attribute \src "libresoc.v:71390.5-71390.29"
switch \initial
- attribute \src "libresoc.v:72047.9-72047.17"
+ attribute \src "libresoc.v:71390.9-71390.17"
case 1'1
case
end
sync always
update \ldst_len $0\ldst_len[3:0]
end
- attribute \src "libresoc.v:72188.3-72329.6"
- process $proc$libresoc.v:72188$3597
+ attribute \src "libresoc.v:71531.3-71672.6"
+ process $proc$libresoc.v:71531$3570
assign { } { }
assign { } { }
assign { } { }
assign $0\upd[1:0] $2\upd[1:0]
- attribute \src "libresoc.v:72189.5-72189.29"
+ attribute \src "libresoc.v:71532.5-71532.29"
switch \initial
- attribute \src "libresoc.v:72189.9-72189.17"
+ attribute \src "libresoc.v:71532.9-71532.17"
case 1'1
case
end
sync always
update \upd $0\upd[1:0]
end
- attribute \src "libresoc.v:72330.3-72471.6"
- process $proc$libresoc.v:72330$3598
+ attribute \src "libresoc.v:71673.3-71814.6"
+ process $proc$libresoc.v:71673$3571
assign { } { }
assign { } { }
assign { } { }
assign $0\rc_sel[1:0] $2\rc_sel[1:0]
- attribute \src "libresoc.v:72331.5-72331.29"
+ attribute \src "libresoc.v:71674.5-71674.29"
switch \initial
- attribute \src "libresoc.v:72331.9-72331.17"
+ attribute \src "libresoc.v:71674.9-71674.17"
case 1'1
case
end
sync always
update \rc_sel $0\rc_sel[1:0]
end
- attribute \src "libresoc.v:72472.3-72613.6"
- process $proc$libresoc.v:72472$3599
+ attribute \src "libresoc.v:71815.3-71956.6"
+ process $proc$libresoc.v:71815$3572
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_in[1:0] $2\cry_in[1:0]
- attribute \src "libresoc.v:72473.5-72473.29"
+ attribute \src "libresoc.v:71816.5-71816.29"
switch \initial
- attribute \src "libresoc.v:72473.9-72473.17"
+ attribute \src "libresoc.v:71816.9-71816.17"
case 1'1
case
end
sync always
update \cry_in $0\cry_in[1:0]
end
- attribute \src "libresoc.v:72614.3-72755.6"
- process $proc$libresoc.v:72614$3600
+ attribute \src "libresoc.v:71957.3-72098.6"
+ process $proc$libresoc.v:71957$3573
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_a[0:0] $2\inv_a[0:0]
- attribute \src "libresoc.v:72615.5-72615.29"
+ attribute \src "libresoc.v:71958.5-71958.29"
switch \initial
- attribute \src "libresoc.v:72615.9-72615.17"
+ attribute \src "libresoc.v:71958.9-71958.17"
case 1'1
case
end
sync always
update \inv_a $0\inv_a[0:0]
end
- attribute \src "libresoc.v:72756.3-72897.6"
- process $proc$libresoc.v:72756$3601
+ attribute \src "libresoc.v:72099.3-72240.6"
+ process $proc$libresoc.v:72099$3574
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_out[0:0] $2\inv_out[0:0]
- attribute \src "libresoc.v:72757.5-72757.29"
+ attribute \src "libresoc.v:72100.5-72100.29"
switch \initial
- attribute \src "libresoc.v:72757.9-72757.17"
+ attribute \src "libresoc.v:72100.9-72100.17"
case 1'1
case
end
sync always
update \inv_out $0\inv_out[0:0]
end
- attribute \src "libresoc.v:72898.3-73039.6"
- process $proc$libresoc.v:72898$3602
+ attribute \src "libresoc.v:72241.3-72382.6"
+ process $proc$libresoc.v:72241$3575
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_out[0:0] $2\cry_out[0:0]
- attribute \src "libresoc.v:72899.5-72899.29"
+ attribute \src "libresoc.v:72242.5-72242.29"
switch \initial
- attribute \src "libresoc.v:72899.9-72899.17"
+ attribute \src "libresoc.v:72242.9-72242.17"
case 1'1
case
end
sync always
update \cry_out $0\cry_out[0:0]
end
- attribute \src "libresoc.v:73040.3-73181.6"
- process $proc$libresoc.v:73040$3603
+ attribute \src "libresoc.v:72383.3-72524.6"
+ process $proc$libresoc.v:72383$3576
assign { } { }
assign { } { }
assign { } { }
assign $0\br[0:0] $2\br[0:0]
- attribute \src "libresoc.v:73041.5-73041.29"
+ attribute \src "libresoc.v:72384.5-72384.29"
switch \initial
- attribute \src "libresoc.v:73041.9-73041.17"
+ attribute \src "libresoc.v:72384.9-72384.17"
case 1'1
case
end
sync always
update \br $0\br[0:0]
end
- attribute \src "libresoc.v:73182.3-73323.6"
- process $proc$libresoc.v:73182$3604
+ attribute \src "libresoc.v:72525.3-72666.6"
+ process $proc$libresoc.v:72525$3577
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn_ext[0:0] $2\sgn_ext[0:0]
- attribute \src "libresoc.v:73183.5-73183.29"
+ attribute \src "libresoc.v:72526.5-72526.29"
switch \initial
- attribute \src "libresoc.v:73183.9-73183.17"
+ attribute \src "libresoc.v:72526.9-72526.17"
case 1'1
case
end
sync always
update \sgn_ext $0\sgn_ext[0:0]
end
- attribute \src "libresoc.v:73324.3-73465.6"
- process $proc$libresoc.v:73324$3605
+ attribute \src "libresoc.v:72667.3-72808.6"
+ process $proc$libresoc.v:72667$3578
assign { } { }
assign { } { }
assign { } { }
assign $0\rsrv[0:0] $2\rsrv[0:0]
- attribute \src "libresoc.v:73325.5-73325.29"
+ attribute \src "libresoc.v:72668.5-72668.29"
switch \initial
- attribute \src "libresoc.v:73325.9-73325.17"
+ attribute \src "libresoc.v:72668.9-72668.17"
case 1'1
case
end
sync always
update \rsrv $0\rsrv[0:0]
end
- attribute \src "libresoc.v:73466.3-73607.6"
- process $proc$libresoc.v:73466$3606
+ attribute \src "libresoc.v:72809.3-72950.6"
+ process $proc$libresoc.v:72809$3579
assign { } { }
assign { } { }
assign { } { }
assign $0\is_32b[0:0] $2\is_32b[0:0]
- attribute \src "libresoc.v:73467.5-73467.29"
+ attribute \src "libresoc.v:72810.5-72810.29"
switch \initial
- attribute \src "libresoc.v:73467.9-73467.17"
+ attribute \src "libresoc.v:72810.9-72810.17"
case 1'1
case
end
sync always
update \is_32b $0\is_32b[0:0]
end
- attribute \src "libresoc.v:73608.3-73749.6"
- process $proc$libresoc.v:73608$3607
+ attribute \src "libresoc.v:72951.3-73092.6"
+ process $proc$libresoc.v:72951$3580
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn[0:0] $2\sgn[0:0]
- attribute \src "libresoc.v:73609.5-73609.29"
+ attribute \src "libresoc.v:72952.5-72952.29"
switch \initial
- attribute \src "libresoc.v:73609.9-73609.17"
+ attribute \src "libresoc.v:72952.9-72952.17"
case 1'1
case
end
sync always
update \sgn $0\sgn[0:0]
end
- attribute \src "libresoc.v:73750.3-73891.6"
- process $proc$libresoc.v:73750$3608
+ attribute \src "libresoc.v:73093.3-73234.6"
+ process $proc$libresoc.v:73093$3581
assign { } { }
assign { } { }
assign { } { }
assign $0\lk[0:0] $2\lk[0:0]
- attribute \src "libresoc.v:73751.5-73751.29"
+ attribute \src "libresoc.v:73094.5-73094.29"
switch \initial
- attribute \src "libresoc.v:73751.9-73751.17"
+ attribute \src "libresoc.v:73094.9-73094.17"
case 1'1
case
end
sync always
update \lk $0\lk[0:0]
end
- attribute \src "libresoc.v:73892.3-74033.6"
- process $proc$libresoc.v:73892$3609
+ attribute \src "libresoc.v:73235.3-73376.6"
+ process $proc$libresoc.v:73235$3582
assign { } { }
assign { } { }
assign { } { }
assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:73893.5-73893.29"
+ attribute \src "libresoc.v:73236.5-73236.29"
switch \initial
- attribute \src "libresoc.v:73893.9-73893.17"
+ attribute \src "libresoc.v:73236.9-73236.17"
case 1'1
case
end
sync always
update \sgl_pipe $0\sgl_pipe[0:0]
end
- attribute \src "libresoc.v:74034.3-74175.6"
- process $proc$libresoc.v:74034$3610
+ attribute \src "libresoc.v:73377.3-73518.6"
+ process $proc$libresoc.v:73377$3583
assign { } { }
assign { } { }
assign { } { }
assign $0\function_unit[12:0] $2\function_unit[12:0]
- attribute \src "libresoc.v:74035.5-74035.29"
+ attribute \src "libresoc.v:73378.5-73378.29"
switch \initial
- attribute \src "libresoc.v:74035.9-74035.17"
+ attribute \src "libresoc.v:73378.9-73378.17"
case 1'1
case
end
sync always
update \function_unit $0\function_unit[12:0]
end
- attribute \src "libresoc.v:74176.3-74317.6"
- process $proc$libresoc.v:74176$3611
+ attribute \src "libresoc.v:73519.3-73660.6"
+ process $proc$libresoc.v:73519$3584
assign { } { }
assign { } { }
assign { } { }
assign $0\internal_op[6:0] $2\internal_op[6:0]
- attribute \src "libresoc.v:74177.5-74177.29"
+ attribute \src "libresoc.v:73520.5-73520.29"
switch \initial
- attribute \src "libresoc.v:74177.9-74177.17"
+ attribute \src "libresoc.v:73520.9-73520.17"
case 1'1
case
end
sync always
update \internal_op $0\internal_op[6:0]
end
- attribute \src "libresoc.v:74318.3-74459.6"
- process $proc$libresoc.v:74318$3612
+ attribute \src "libresoc.v:73661.3-73802.6"
+ process $proc$libresoc.v:73661$3585
assign { } { }
assign { } { }
assign { } { }
assign $0\form[4:0] $2\form[4:0]
- attribute \src "libresoc.v:74319.5-74319.29"
+ attribute \src "libresoc.v:73662.5-73662.29"
switch \initial
- attribute \src "libresoc.v:74319.9-74319.17"
+ attribute \src "libresoc.v:73662.9-73662.17"
case 1'1
case
end
sync always
update \form $0\form[4:0]
end
- connect \$2 $ternary$libresoc.v:69743$3580_Y
+ connect \$2 $ternary$libresoc.v:69086$3553_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:74805.1-76806.10"
+attribute \src "libresoc.v:74148.1-76149.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19"
attribute \generator "nMigen"
module \dec19
- attribute \src "libresoc.v:76493.3-76544.6"
+ attribute \src "libresoc.v:75836.3-75887.6"
wire width 2 $0\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:76545.3-76596.6"
+ attribute \src "libresoc.v:75888.3-75939.6"
wire width 2 $0\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:75869.3-75920.6"
+ attribute \src "libresoc.v:75212.3-75263.6"
wire width 8 $0\dec19_asmcode[7:0]
- attribute \src "libresoc.v:76077.3-76128.6"
+ attribute \src "libresoc.v:75420.3-75471.6"
wire $0\dec19_br[0:0]
- attribute \src "libresoc.v:75193.3-75244.6"
+ attribute \src "libresoc.v:74536.3-74587.6"
wire width 3 $0\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75245.3-75296.6"
+ attribute \src "libresoc.v:74588.3-74639.6"
wire width 3 $0\dec19_cr_out[2:0]
- attribute \src "libresoc.v:75817.3-75868.6"
+ attribute \src "libresoc.v:75160.3-75211.6"
wire width 2 $0\dec19_cry_in[1:0]
- attribute \src "libresoc.v:76025.3-76076.6"
+ attribute \src "libresoc.v:75368.3-75419.6"
wire $0\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76285.3-76336.6"
+ attribute \src "libresoc.v:75628.3-75679.6"
wire width 5 $0\dec19_form[4:0]
- attribute \src "libresoc.v:75141.3-75192.6"
+ attribute \src "libresoc.v:74484.3-74535.6"
wire width 13 $0\dec19_function_unit[12:0]
- attribute \src "libresoc.v:76597.3-76648.6"
+ attribute \src "libresoc.v:75940.3-75991.6"
wire width 3 $0\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:76649.3-76700.6"
+ attribute \src "libresoc.v:75992.3-76043.6"
wire width 4 $0\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:76701.3-76752.6"
+ attribute \src "libresoc.v:76044.3-76095.6"
wire width 2 $0\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:75713.3-75764.6"
+ attribute \src "libresoc.v:75056.3-75107.6"
wire width 7 $0\dec19_internal_op[6:0]
- attribute \src "libresoc.v:75921.3-75972.6"
+ attribute \src "libresoc.v:75264.3-75315.6"
wire $0\dec19_inv_a[0:0]
- attribute \src "libresoc.v:75973.3-76024.6"
+ attribute \src "libresoc.v:75316.3-75367.6"
wire $0\dec19_inv_out[0:0]
- attribute \src "libresoc.v:76233.3-76284.6"
+ attribute \src "libresoc.v:75576.3-75627.6"
wire $0\dec19_is_32b[0:0]
- attribute \src "libresoc.v:75609.3-75660.6"
+ attribute \src "libresoc.v:74952.3-75003.6"
wire width 4 $0\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:76389.3-76440.6"
+ attribute \src "libresoc.v:75732.3-75783.6"
wire $0\dec19_lk[0:0]
- attribute \src "libresoc.v:76753.3-76804.6"
+ attribute \src "libresoc.v:76096.3-76147.6"
wire width 2 $0\dec19_out_sel[1:0]
- attribute \src "libresoc.v:75765.3-75816.6"
+ attribute \src "libresoc.v:75108.3-75159.6"
wire width 2 $0\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:76181.3-76232.6"
+ attribute \src "libresoc.v:75524.3-75575.6"
wire $0\dec19_rsrv[0:0]
- attribute \src "libresoc.v:76441.3-76492.6"
+ attribute \src "libresoc.v:75784.3-75835.6"
wire $0\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:76337.3-76388.6"
+ attribute \src "libresoc.v:75680.3-75731.6"
wire $0\dec19_sgn[0:0]
- attribute \src "libresoc.v:76129.3-76180.6"
+ attribute \src "libresoc.v:75472.3-75523.6"
wire $0\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:75505.3-75556.6"
+ attribute \src "libresoc.v:74848.3-74899.6"
wire width 3 $0\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:75557.3-75608.6"
+ attribute \src "libresoc.v:74900.3-74951.6"
wire width 3 $0\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:75297.3-75348.6"
+ attribute \src "libresoc.v:74640.3-74691.6"
wire width 3 $0\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75349.3-75400.6"
+ attribute \src "libresoc.v:74692.3-74743.6"
wire width 3 $0\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75401.3-75452.6"
+ attribute \src "libresoc.v:74744.3-74795.6"
wire width 3 $0\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:75453.3-75504.6"
+ attribute \src "libresoc.v:74796.3-74847.6"
wire width 3 $0\dec19_sv_out[2:0]
- attribute \src "libresoc.v:75661.3-75712.6"
+ attribute \src "libresoc.v:75004.3-75055.6"
wire width 2 $0\dec19_upd[1:0]
- attribute \src "libresoc.v:74806.7-74806.20"
+ attribute \src "libresoc.v:74149.7-74149.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:76493.3-76544.6"
+ attribute \src "libresoc.v:75836.3-75887.6"
wire width 2 $1\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:76545.3-76596.6"
+ attribute \src "libresoc.v:75888.3-75939.6"
wire width 2 $1\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:75869.3-75920.6"
+ attribute \src "libresoc.v:75212.3-75263.6"
wire width 8 $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:76077.3-76128.6"
+ attribute \src "libresoc.v:75420.3-75471.6"
wire $1\dec19_br[0:0]
- attribute \src "libresoc.v:75193.3-75244.6"
+ attribute \src "libresoc.v:74536.3-74587.6"
wire width 3 $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75245.3-75296.6"
+ attribute \src "libresoc.v:74588.3-74639.6"
wire width 3 $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:75817.3-75868.6"
+ attribute \src "libresoc.v:75160.3-75211.6"
wire width 2 $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:76025.3-76076.6"
+ attribute \src "libresoc.v:75368.3-75419.6"
wire $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76285.3-76336.6"
+ attribute \src "libresoc.v:75628.3-75679.6"
wire width 5 $1\dec19_form[4:0]
- attribute \src "libresoc.v:75141.3-75192.6"
+ attribute \src "libresoc.v:74484.3-74535.6"
wire width 13 $1\dec19_function_unit[12:0]
- attribute \src "libresoc.v:76597.3-76648.6"
+ attribute \src "libresoc.v:75940.3-75991.6"
wire width 3 $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:76649.3-76700.6"
+ attribute \src "libresoc.v:75992.3-76043.6"
wire width 4 $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:76701.3-76752.6"
+ attribute \src "libresoc.v:76044.3-76095.6"
wire width 2 $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:75713.3-75764.6"
+ attribute \src "libresoc.v:75056.3-75107.6"
wire width 7 $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:75921.3-75972.6"
+ attribute \src "libresoc.v:75264.3-75315.6"
wire $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:75973.3-76024.6"
+ attribute \src "libresoc.v:75316.3-75367.6"
wire $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:76233.3-76284.6"
+ attribute \src "libresoc.v:75576.3-75627.6"
wire $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:75609.3-75660.6"
+ attribute \src "libresoc.v:74952.3-75003.6"
wire width 4 $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:76389.3-76440.6"
+ attribute \src "libresoc.v:75732.3-75783.6"
wire $1\dec19_lk[0:0]
- attribute \src "libresoc.v:76753.3-76804.6"
+ attribute \src "libresoc.v:76096.3-76147.6"
wire width 2 $1\dec19_out_sel[1:0]
- attribute \src "libresoc.v:75765.3-75816.6"
+ attribute \src "libresoc.v:75108.3-75159.6"
wire width 2 $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:76181.3-76232.6"
+ attribute \src "libresoc.v:75524.3-75575.6"
wire $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:76441.3-76492.6"
+ attribute \src "libresoc.v:75784.3-75835.6"
wire $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:76337.3-76388.6"
+ attribute \src "libresoc.v:75680.3-75731.6"
wire $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:76129.3-76180.6"
+ attribute \src "libresoc.v:75472.3-75523.6"
wire $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:75505.3-75556.6"
+ attribute \src "libresoc.v:74848.3-74899.6"
wire width 3 $1\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:75557.3-75608.6"
+ attribute \src "libresoc.v:74900.3-74951.6"
wire width 3 $1\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:75297.3-75348.6"
+ attribute \src "libresoc.v:74640.3-74691.6"
wire width 3 $1\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75349.3-75400.6"
+ attribute \src "libresoc.v:74692.3-74743.6"
wire width 3 $1\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75401.3-75452.6"
+ attribute \src "libresoc.v:74744.3-74795.6"
wire width 3 $1\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:75453.3-75504.6"
+ attribute \src "libresoc.v:74796.3-74847.6"
wire width 3 $1\dec19_sv_out[2:0]
- attribute \src "libresoc.v:75661.3-75712.6"
+ attribute \src "libresoc.v:75004.3-75055.6"
wire width 2 $1\dec19_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec19_upd
- attribute \src "libresoc.v:74806.7-74806.15"
+ attribute \src "libresoc.v:74149.7-74149.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 10 \opcode_switch
- attribute \src "libresoc.v:74806.7-74806.20"
- process $proc$libresoc.v:74806$3646
+ attribute \src "libresoc.v:74149.7-74149.20"
+ process $proc$libresoc.v:74149$3619
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:75141.3-75192.6"
- process $proc$libresoc.v:75141$3614
+ attribute \src "libresoc.v:74484.3-74535.6"
+ process $proc$libresoc.v:74484$3587
assign { } { }
assign { } { }
assign $0\dec19_function_unit[12:0] $1\dec19_function_unit[12:0]
- attribute \src "libresoc.v:75142.5-75142.29"
+ attribute \src "libresoc.v:74485.5-74485.29"
switch \initial
- attribute \src "libresoc.v:75142.9-75142.17"
+ attribute \src "libresoc.v:74485.9-74485.17"
case 1'1
case
end
sync always
update \dec19_function_unit $0\dec19_function_unit[12:0]
end
- attribute \src "libresoc.v:75193.3-75244.6"
- process $proc$libresoc.v:75193$3615
+ attribute \src "libresoc.v:74536.3-74587.6"
+ process $proc$libresoc.v:74536$3588
assign { } { }
assign { } { }
assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:75194.5-75194.29"
+ attribute \src "libresoc.v:74537.5-74537.29"
switch \initial
- attribute \src "libresoc.v:75194.9-75194.17"
+ attribute \src "libresoc.v:74537.9-74537.17"
case 1'1
case
end
sync always
update \dec19_cr_in $0\dec19_cr_in[2:0]
end
- attribute \src "libresoc.v:75245.3-75296.6"
- process $proc$libresoc.v:75245$3616
+ attribute \src "libresoc.v:74588.3-74639.6"
+ process $proc$libresoc.v:74588$3589
assign { } { }
assign { } { }
assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:75246.5-75246.29"
+ attribute \src "libresoc.v:74589.5-74589.29"
switch \initial
- attribute \src "libresoc.v:75246.9-75246.17"
+ attribute \src "libresoc.v:74589.9-74589.17"
case 1'1
case
end
sync always
update \dec19_cr_out $0\dec19_cr_out[2:0]
end
- attribute \src "libresoc.v:75297.3-75348.6"
- process $proc$libresoc.v:75297$3617
+ attribute \src "libresoc.v:74640.3-74691.6"
+ process $proc$libresoc.v:74640$3590
assign { } { }
assign { } { }
assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0]
- attribute \src "libresoc.v:75298.5-75298.29"
+ attribute \src "libresoc.v:74641.5-74641.29"
switch \initial
- attribute \src "libresoc.v:75298.9-75298.17"
+ attribute \src "libresoc.v:74641.9-74641.17"
case 1'1
case
end
sync always
update \dec19_sv_in1 $0\dec19_sv_in1[2:0]
end
- attribute \src "libresoc.v:75349.3-75400.6"
- process $proc$libresoc.v:75349$3618
+ attribute \src "libresoc.v:74692.3-74743.6"
+ process $proc$libresoc.v:74692$3591
assign { } { }
assign { } { }
assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0]
- attribute \src "libresoc.v:75350.5-75350.29"
+ attribute \src "libresoc.v:74693.5-74693.29"
switch \initial
- attribute \src "libresoc.v:75350.9-75350.17"
+ attribute \src "libresoc.v:74693.9-74693.17"
case 1'1
case
end
sync always
update \dec19_sv_in2 $0\dec19_sv_in2[2:0]
end
- attribute \src "libresoc.v:75401.3-75452.6"
- process $proc$libresoc.v:75401$3619
+ attribute \src "libresoc.v:74744.3-74795.6"
+ process $proc$libresoc.v:74744$3592
assign { } { }
assign { } { }
assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0]
- attribute \src "libresoc.v:75402.5-75402.29"
+ attribute \src "libresoc.v:74745.5-74745.29"
switch \initial
- attribute \src "libresoc.v:75402.9-75402.17"
+ attribute \src "libresoc.v:74745.9-74745.17"
case 1'1
case
end
sync always
update \dec19_sv_in3 $0\dec19_sv_in3[2:0]
end
- attribute \src "libresoc.v:75453.3-75504.6"
- process $proc$libresoc.v:75453$3620
+ attribute \src "libresoc.v:74796.3-74847.6"
+ process $proc$libresoc.v:74796$3593
assign { } { }
assign { } { }
assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0]
- attribute \src "libresoc.v:75454.5-75454.29"
+ attribute \src "libresoc.v:74797.5-74797.29"
switch \initial
- attribute \src "libresoc.v:75454.9-75454.17"
+ attribute \src "libresoc.v:74797.9-74797.17"
case 1'1
case
end
sync always
update \dec19_sv_out $0\dec19_sv_out[2:0]
end
- attribute \src "libresoc.v:75505.3-75556.6"
- process $proc$libresoc.v:75505$3621
+ attribute \src "libresoc.v:74848.3-74899.6"
+ process $proc$libresoc.v:74848$3594
assign { } { }
assign { } { }
assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0]
- attribute \src "libresoc.v:75506.5-75506.29"
+ attribute \src "libresoc.v:74849.5-74849.29"
switch \initial
- attribute \src "libresoc.v:75506.9-75506.17"
+ attribute \src "libresoc.v:74849.9-74849.17"
case 1'1
case
end
sync always
update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:75557.3-75608.6"
- process $proc$libresoc.v:75557$3622
+ attribute \src "libresoc.v:74900.3-74951.6"
+ process $proc$libresoc.v:74900$3595
assign { } { }
assign { } { }
assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0]
- attribute \src "libresoc.v:75558.5-75558.29"
+ attribute \src "libresoc.v:74901.5-74901.29"
switch \initial
- attribute \src "libresoc.v:75558.9-75558.17"
+ attribute \src "libresoc.v:74901.9-74901.17"
case 1'1
case
end
sync always
update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:75609.3-75660.6"
- process $proc$libresoc.v:75609$3623
+ attribute \src "libresoc.v:74952.3-75003.6"
+ process $proc$libresoc.v:74952$3596
assign { } { }
assign { } { }
assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:75610.5-75610.29"
+ attribute \src "libresoc.v:74953.5-74953.29"
switch \initial
- attribute \src "libresoc.v:75610.9-75610.17"
+ attribute \src "libresoc.v:74953.9-74953.17"
case 1'1
case
end
sync always
update \dec19_ldst_len $0\dec19_ldst_len[3:0]
end
- attribute \src "libresoc.v:75661.3-75712.6"
- process $proc$libresoc.v:75661$3624
+ attribute \src "libresoc.v:75004.3-75055.6"
+ process $proc$libresoc.v:75004$3597
assign { } { }
assign { } { }
assign $0\dec19_upd[1:0] $1\dec19_upd[1:0]
- attribute \src "libresoc.v:75662.5-75662.29"
+ attribute \src "libresoc.v:75005.5-75005.29"
switch \initial
- attribute \src "libresoc.v:75662.9-75662.17"
+ attribute \src "libresoc.v:75005.9-75005.17"
case 1'1
case
end
sync always
update \dec19_upd $0\dec19_upd[1:0]
end
- attribute \src "libresoc.v:75713.3-75764.6"
- process $proc$libresoc.v:75713$3625
+ attribute \src "libresoc.v:75056.3-75107.6"
+ process $proc$libresoc.v:75056$3598
assign { } { }
assign { } { }
assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:75714.5-75714.29"
+ attribute \src "libresoc.v:75057.5-75057.29"
switch \initial
- attribute \src "libresoc.v:75714.9-75714.17"
+ attribute \src "libresoc.v:75057.9-75057.17"
case 1'1
case
end
sync always
update \dec19_internal_op $0\dec19_internal_op[6:0]
end
- attribute \src "libresoc.v:75765.3-75816.6"
- process $proc$libresoc.v:75765$3626
+ attribute \src "libresoc.v:75108.3-75159.6"
+ process $proc$libresoc.v:75108$3599
assign { } { }
assign { } { }
assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:75766.5-75766.29"
+ attribute \src "libresoc.v:75109.5-75109.29"
switch \initial
- attribute \src "libresoc.v:75766.9-75766.17"
+ attribute \src "libresoc.v:75109.9-75109.17"
case 1'1
case
end
sync always
update \dec19_rc_sel $0\dec19_rc_sel[1:0]
end
- attribute \src "libresoc.v:75817.3-75868.6"
- process $proc$libresoc.v:75817$3627
+ attribute \src "libresoc.v:75160.3-75211.6"
+ process $proc$libresoc.v:75160$3600
assign { } { }
assign { } { }
assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:75818.5-75818.29"
+ attribute \src "libresoc.v:75161.5-75161.29"
switch \initial
- attribute \src "libresoc.v:75818.9-75818.17"
+ attribute \src "libresoc.v:75161.9-75161.17"
case 1'1
case
end
sync always
update \dec19_cry_in $0\dec19_cry_in[1:0]
end
- attribute \src "libresoc.v:75869.3-75920.6"
- process $proc$libresoc.v:75869$3628
+ attribute \src "libresoc.v:75212.3-75263.6"
+ process $proc$libresoc.v:75212$3601
assign { } { }
assign { } { }
assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:75870.5-75870.29"
+ attribute \src "libresoc.v:75213.5-75213.29"
switch \initial
- attribute \src "libresoc.v:75870.9-75870.17"
+ attribute \src "libresoc.v:75213.9-75213.17"
case 1'1
case
end
sync always
update \dec19_asmcode $0\dec19_asmcode[7:0]
end
- attribute \src "libresoc.v:75921.3-75972.6"
- process $proc$libresoc.v:75921$3629
+ attribute \src "libresoc.v:75264.3-75315.6"
+ process $proc$libresoc.v:75264$3602
assign { } { }
assign { } { }
assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:75922.5-75922.29"
+ attribute \src "libresoc.v:75265.5-75265.29"
switch \initial
- attribute \src "libresoc.v:75922.9-75922.17"
+ attribute \src "libresoc.v:75265.9-75265.17"
case 1'1
case
end
sync always
update \dec19_inv_a $0\dec19_inv_a[0:0]
end
- attribute \src "libresoc.v:75973.3-76024.6"
- process $proc$libresoc.v:75973$3630
+ attribute \src "libresoc.v:75316.3-75367.6"
+ process $proc$libresoc.v:75316$3603
assign { } { }
assign { } { }
assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:75974.5-75974.29"
+ attribute \src "libresoc.v:75317.5-75317.29"
switch \initial
- attribute \src "libresoc.v:75974.9-75974.17"
+ attribute \src "libresoc.v:75317.9-75317.17"
case 1'1
case
end
sync always
update \dec19_inv_out $0\dec19_inv_out[0:0]
end
- attribute \src "libresoc.v:76025.3-76076.6"
- process $proc$libresoc.v:76025$3631
+ attribute \src "libresoc.v:75368.3-75419.6"
+ process $proc$libresoc.v:75368$3604
assign { } { }
assign { } { }
assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:76026.5-76026.29"
+ attribute \src "libresoc.v:75369.5-75369.29"
switch \initial
- attribute \src "libresoc.v:76026.9-76026.17"
+ attribute \src "libresoc.v:75369.9-75369.17"
case 1'1
case
end
sync always
update \dec19_cry_out $0\dec19_cry_out[0:0]
end
- attribute \src "libresoc.v:76077.3-76128.6"
- process $proc$libresoc.v:76077$3632
+ attribute \src "libresoc.v:75420.3-75471.6"
+ process $proc$libresoc.v:75420$3605
assign { } { }
assign { } { }
assign $0\dec19_br[0:0] $1\dec19_br[0:0]
- attribute \src "libresoc.v:76078.5-76078.29"
+ attribute \src "libresoc.v:75421.5-75421.29"
switch \initial
- attribute \src "libresoc.v:76078.9-76078.17"
+ attribute \src "libresoc.v:75421.9-75421.17"
case 1'1
case
end
sync always
update \dec19_br $0\dec19_br[0:0]
end
- attribute \src "libresoc.v:76129.3-76180.6"
- process $proc$libresoc.v:76129$3633
+ attribute \src "libresoc.v:75472.3-75523.6"
+ process $proc$libresoc.v:75472$3606
assign { } { }
assign { } { }
assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:76130.5-76130.29"
+ attribute \src "libresoc.v:75473.5-75473.29"
switch \initial
- attribute \src "libresoc.v:76130.9-76130.17"
+ attribute \src "libresoc.v:75473.9-75473.17"
case 1'1
case
end
sync always
update \dec19_sgn_ext $0\dec19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:76181.3-76232.6"
- process $proc$libresoc.v:76181$3634
+ attribute \src "libresoc.v:75524.3-75575.6"
+ process $proc$libresoc.v:75524$3607
assign { } { }
assign { } { }
assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:76182.5-76182.29"
+ attribute \src "libresoc.v:75525.5-75525.29"
switch \initial
- attribute \src "libresoc.v:76182.9-76182.17"
+ attribute \src "libresoc.v:75525.9-75525.17"
case 1'1
case
end
sync always
update \dec19_rsrv $0\dec19_rsrv[0:0]
end
- attribute \src "libresoc.v:76233.3-76284.6"
- process $proc$libresoc.v:76233$3635
+ attribute \src "libresoc.v:75576.3-75627.6"
+ process $proc$libresoc.v:75576$3608
assign { } { }
assign { } { }
assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:76234.5-76234.29"
+ attribute \src "libresoc.v:75577.5-75577.29"
switch \initial
- attribute \src "libresoc.v:76234.9-76234.17"
+ attribute \src "libresoc.v:75577.9-75577.17"
case 1'1
case
end
sync always
update \dec19_is_32b $0\dec19_is_32b[0:0]
end
- attribute \src "libresoc.v:76285.3-76336.6"
- process $proc$libresoc.v:76285$3636
+ attribute \src "libresoc.v:75628.3-75679.6"
+ process $proc$libresoc.v:75628$3609
assign { } { }
assign { } { }
assign $0\dec19_form[4:0] $1\dec19_form[4:0]
- attribute \src "libresoc.v:76286.5-76286.29"
+ attribute \src "libresoc.v:75629.5-75629.29"
switch \initial
- attribute \src "libresoc.v:76286.9-76286.17"
+ attribute \src "libresoc.v:75629.9-75629.17"
case 1'1
case
end
sync always
update \dec19_form $0\dec19_form[4:0]
end
- attribute \src "libresoc.v:76337.3-76388.6"
- process $proc$libresoc.v:76337$3637
+ attribute \src "libresoc.v:75680.3-75731.6"
+ process $proc$libresoc.v:75680$3610
assign { } { }
assign { } { }
assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:76338.5-76338.29"
+ attribute \src "libresoc.v:75681.5-75681.29"
switch \initial
- attribute \src "libresoc.v:76338.9-76338.17"
+ attribute \src "libresoc.v:75681.9-75681.17"
case 1'1
case
end
sync always
update \dec19_sgn $0\dec19_sgn[0:0]
end
- attribute \src "libresoc.v:76389.3-76440.6"
- process $proc$libresoc.v:76389$3638
+ attribute \src "libresoc.v:75732.3-75783.6"
+ process $proc$libresoc.v:75732$3611
assign { } { }
assign { } { }
assign $0\dec19_lk[0:0] $1\dec19_lk[0:0]
- attribute \src "libresoc.v:76390.5-76390.29"
+ attribute \src "libresoc.v:75733.5-75733.29"
switch \initial
- attribute \src "libresoc.v:76390.9-76390.17"
+ attribute \src "libresoc.v:75733.9-75733.17"
case 1'1
case
end
sync always
update \dec19_lk $0\dec19_lk[0:0]
end
- attribute \src "libresoc.v:76441.3-76492.6"
- process $proc$libresoc.v:76441$3639
+ attribute \src "libresoc.v:75784.3-75835.6"
+ process $proc$libresoc.v:75784$3612
assign { } { }
assign { } { }
assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:76442.5-76442.29"
+ attribute \src "libresoc.v:75785.5-75785.29"
switch \initial
- attribute \src "libresoc.v:76442.9-76442.17"
+ attribute \src "libresoc.v:75785.9-75785.17"
case 1'1
case
end
sync always
update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:76493.3-76544.6"
- process $proc$libresoc.v:76493$3640
+ attribute \src "libresoc.v:75836.3-75887.6"
+ process $proc$libresoc.v:75836$3613
assign { } { }
assign { } { }
assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0]
- attribute \src "libresoc.v:76494.5-76494.29"
+ attribute \src "libresoc.v:75837.5-75837.29"
switch \initial
- attribute \src "libresoc.v:76494.9-76494.17"
+ attribute \src "libresoc.v:75837.9-75837.17"
case 1'1
case
end
sync always
update \dec19_SV_Etype $0\dec19_SV_Etype[1:0]
end
- attribute \src "libresoc.v:76545.3-76596.6"
- process $proc$libresoc.v:76545$3641
+ attribute \src "libresoc.v:75888.3-75939.6"
+ process $proc$libresoc.v:75888$3614
assign { } { }
assign { } { }
assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0]
- attribute \src "libresoc.v:76546.5-76546.29"
+ attribute \src "libresoc.v:75889.5-75889.29"
switch \initial
- attribute \src "libresoc.v:76546.9-76546.17"
+ attribute \src "libresoc.v:75889.9-75889.17"
case 1'1
case
end
sync always
update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:76597.3-76648.6"
- process $proc$libresoc.v:76597$3642
+ attribute \src "libresoc.v:75940.3-75991.6"
+ process $proc$libresoc.v:75940$3615
assign { } { }
assign { } { }
assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:76598.5-76598.29"
+ attribute \src "libresoc.v:75941.5-75941.29"
switch \initial
- attribute \src "libresoc.v:76598.9-76598.17"
+ attribute \src "libresoc.v:75941.9-75941.17"
case 1'1
case
end
sync always
update \dec19_in1_sel $0\dec19_in1_sel[2:0]
end
- attribute \src "libresoc.v:76649.3-76700.6"
- process $proc$libresoc.v:76649$3643
+ attribute \src "libresoc.v:75992.3-76043.6"
+ process $proc$libresoc.v:75992$3616
assign { } { }
assign { } { }
assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:76650.5-76650.29"
+ attribute \src "libresoc.v:75993.5-75993.29"
switch \initial
- attribute \src "libresoc.v:76650.9-76650.17"
+ attribute \src "libresoc.v:75993.9-75993.17"
case 1'1
case
end
sync always
update \dec19_in2_sel $0\dec19_in2_sel[3:0]
end
- attribute \src "libresoc.v:76701.3-76752.6"
- process $proc$libresoc.v:76701$3644
+ attribute \src "libresoc.v:76044.3-76095.6"
+ process $proc$libresoc.v:76044$3617
assign { } { }
assign { } { }
assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:76702.5-76702.29"
+ attribute \src "libresoc.v:76045.5-76045.29"
switch \initial
- attribute \src "libresoc.v:76702.9-76702.17"
+ attribute \src "libresoc.v:76045.9-76045.17"
case 1'1
case
end
sync always
update \dec19_in3_sel $0\dec19_in3_sel[1:0]
end
- attribute \src "libresoc.v:76753.3-76804.6"
- process $proc$libresoc.v:76753$3645
+ attribute \src "libresoc.v:76096.3-76147.6"
+ process $proc$libresoc.v:76096$3618
assign { } { }
assign { } { }
assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0]
- attribute \src "libresoc.v:76754.5-76754.29"
+ attribute \src "libresoc.v:76097.5-76097.29"
switch \initial
- attribute \src "libresoc.v:76754.9-76754.17"
+ attribute \src "libresoc.v:76097.9-76097.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:76810.1-79734.10"
+attribute \src "libresoc.v:76153.1-78359.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2"
attribute \generator "nMigen"
module \dec2
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $0\cia[63:0]
- attribute \src "libresoc.v:79508.3-79517.6"
- wire width 3 $0\cr_a_idx[2:0]
- attribute \src "libresoc.v:79518.3-79527.6"
- wire width 3 $0\cr_b_idx[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\cr_in1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire width 7 $0\cr_in2$1[6:0]$3727
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire width 7 $0\cr_in2$1[6:0]$3680
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\cr_in2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\cr_in2_ok$2[0:0]$3728
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\cr_in2_ok$2[0:0]$3681
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\cr_out[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\cr_out_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $0\cr_rd[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $0\cr_wr[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\ea[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\ea_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$3[0:0]$3730
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$4[0:0]$3731
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$5[0:0]$3732
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$6[0:0]$3733
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$7[0:0]$3734
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$8[0:0]$3735
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal$9[0:0]$3736
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $0\exc_$signal[0:0]$3729
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$3[0:0]$3683
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$4[0:0]$3684
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$5[0:0]$3685
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$6[0:0]$3686
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$7[0:0]$3687
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$8[0:0]$3688
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal$9[0:0]$3689
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $0\exc_$signal[0:0]$3682
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $0\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $0\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $0\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $0\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\fasto2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $0\fn_unit[12:0]
- attribute \src "libresoc.v:76811.7-76811.20"
+ attribute \src "libresoc.v:76154.7-76154.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 2 $0\input_carry[1:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 32 $0\insn[31:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\insn_type[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\is_32bit[0:0]
- attribute \src "libresoc.v:79316.3-79339.6"
+ attribute \src "libresoc.v:78099.3-78122.6"
wire $0\is_priv_insn[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\reg1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\reg1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\reg2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\reg2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\reg3[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\reg3_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $0\rego[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\rego_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $0\spr1[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $0\spro[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\spro_ok[0:0]
- attribute \src "libresoc.v:79173.3-79195.6"
- wire width 7 $0\tmp_cr_in1[6:0]
- attribute \src "libresoc.v:79234.3-79256.6"
- wire width 7 $0\tmp_cr_in2$19[6:0]$3718
- attribute \src "libresoc.v:79196.3-79218.6"
- wire width 7 $0\tmp_cr_in2[6:0]
- attribute \src "libresoc.v:79257.3-79279.6"
- wire width 7 $0\tmp_cr_out[6:0]
- attribute \src "libresoc.v:79589.3-79600.6"
- wire width 7 $0\tmp_ea[6:0]
- attribute \src "libresoc.v:79528.3-79539.6"
- wire width 7 $0\tmp_reg1[6:0]
- attribute \src "libresoc.v:79540.3-79551.6"
- wire width 7 $0\tmp_reg2[6:0]
- attribute \src "libresoc.v:79552.3-79563.6"
- wire width 7 $0\tmp_reg3[6:0]
- attribute \src "libresoc.v:79577.3-79588.6"
- wire width 7 $0\tmp_rego[6:0]
- attribute \src "libresoc.v:79219.3-79233.6"
+ attribute \src "libresoc.v:78025.3-78039.6"
wire width 13 $0\tmp_tmp_fn_unit[12:0]
- attribute \src "libresoc.v:79564.3-79576.6"
+ attribute \src "libresoc.v:78050.3-78062.6"
wire width 7 $0\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79498.3-79507.6"
+ attribute \src "libresoc.v:78040.3-78049.6"
wire $0\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79306.3-79315.6"
+ attribute \src "libresoc.v:78089.3-78098.6"
wire width 13 $0\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79280.3-79295.6"
+ attribute \src "libresoc.v:78063.3-78078.6"
wire width 3 $0\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79296.3-79305.6"
+ attribute \src "libresoc.v:78079.3-78088.6"
wire $0\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $0\trapaddr[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $0\traptype[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $0\xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $0\xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $1\cia[63:0]
- attribute \src "libresoc.v:79508.3-79517.6"
- wire width 3 $1\cr_a_idx[2:0]
- attribute \src "libresoc.v:79518.3-79527.6"
- wire width 3 $1\cr_b_idx[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\cr_in1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire width 7 $1\cr_in2$1[6:0]$3737
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire width 7 $1\cr_in2$1[6:0]$3690
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\cr_in2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\cr_in2_ok$2[0:0]$3738
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\cr_in2_ok$2[0:0]$3691
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\cr_out[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\cr_out_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $1\cr_rd[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $1\cr_wr[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\ea[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\ea_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$3[0:0]$3740
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$4[0:0]$3741
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$5[0:0]$3742
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$6[0:0]$3743
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$7[0:0]$3744
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$8[0:0]$3745
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal$9[0:0]$3746
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $1\exc_$signal[0:0]$3739
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$3[0:0]$3693
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$4[0:0]$3694
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$5[0:0]$3695
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$6[0:0]$3696
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$7[0:0]$3697
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$8[0:0]$3698
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal$9[0:0]$3699
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $1\exc_$signal[0:0]$3692
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $1\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $1\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $1\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $1\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\fasto2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $1\fn_unit[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 2 $1\input_carry[1:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 32 $1\insn[31:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\insn_type[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\is_32bit[0:0]
- attribute \src "libresoc.v:79316.3-79339.6"
+ attribute \src "libresoc.v:78099.3-78122.6"
wire $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\rc_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\reg1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\reg1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\reg2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\reg2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\reg3[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\reg3_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $1\rego[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\rego_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $1\spr1[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $1\spro[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\spro_ok[0:0]
- attribute \src "libresoc.v:79173.3-79195.6"
- wire width 7 $1\tmp_cr_in1[6:0]
- attribute \src "libresoc.v:79234.3-79256.6"
- wire width 7 $1\tmp_cr_in2$19[6:0]$3719
- attribute \src "libresoc.v:79196.3-79218.6"
- wire width 7 $1\tmp_cr_in2[6:0]
- attribute \src "libresoc.v:79257.3-79279.6"
- wire width 7 $1\tmp_cr_out[6:0]
- attribute \src "libresoc.v:79589.3-79600.6"
- wire width 7 $1\tmp_ea[6:0]
- attribute \src "libresoc.v:79528.3-79539.6"
- wire width 7 $1\tmp_reg1[6:0]
- attribute \src "libresoc.v:79540.3-79551.6"
- wire width 7 $1\tmp_reg2[6:0]
- attribute \src "libresoc.v:79552.3-79563.6"
- wire width 7 $1\tmp_reg3[6:0]
- attribute \src "libresoc.v:79577.3-79588.6"
- wire width 7 $1\tmp_rego[6:0]
- attribute \src "libresoc.v:79219.3-79233.6"
+ attribute \src "libresoc.v:78025.3-78039.6"
wire width 13 $1\tmp_tmp_fn_unit[12:0]
- attribute \src "libresoc.v:79564.3-79576.6"
+ attribute \src "libresoc.v:78050.3-78062.6"
wire width 7 $1\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79498.3-79507.6"
+ attribute \src "libresoc.v:78040.3-78049.6"
wire $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79306.3-79315.6"
+ attribute \src "libresoc.v:78089.3-78098.6"
wire width 13 $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79280.3-79295.6"
+ attribute \src "libresoc.v:78063.3-78078.6"
wire width 3 $1\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79296.3-79305.6"
+ attribute \src "libresoc.v:78079.3-78088.6"
wire $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $1\trapaddr[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $1\traptype[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $1\xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $1\xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $2\asmcode[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $2\cia[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\cr_in1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire width 7 $2\cr_in2$1[6:0]$3747
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire width 7 $2\cr_in2$1[6:0]$3700
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\cr_in2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\cr_in2_ok$2[0:0]$3748
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\cr_in2_ok$2[0:0]$3701
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\cr_out[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\cr_out_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $2\cr_rd[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $2\cr_wr[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\ea[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\ea_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$3[0:0]$3750
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$4[0:0]$3751
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$5[0:0]$3752
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$6[0:0]$3753
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$7[0:0]$3754
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$8[0:0]$3755
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal$9[0:0]$3756
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $2\exc_$signal[0:0]$3749
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$3[0:0]$3703
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$4[0:0]$3704
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$5[0:0]$3705
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$6[0:0]$3706
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$7[0:0]$3707
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$8[0:0]$3708
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal$9[0:0]$3709
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $2\exc_$signal[0:0]$3702
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $2\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $2\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $2\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $2\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\fasto2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $2\fn_unit[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 2 $2\input_carry[1:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 32 $2\insn[31:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\insn_type[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\is_32bit[0:0]
- attribute \src "libresoc.v:79316.3-79339.6"
+ attribute \src "libresoc.v:78099.3-78122.6"
wire $2\is_priv_insn[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\lk[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $2\msr[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\oe_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\rc[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\rc_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\reg1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\reg1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\reg2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\reg2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\reg3[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\reg3_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $2\rego[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\rego_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $2\spr1[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\spr1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $2\spro[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\spro_ok[0:0]
- attribute \src "libresoc.v:79173.3-79195.6"
- wire width 7 $2\tmp_cr_in1[6:0]
- attribute \src "libresoc.v:79234.3-79256.6"
- wire width 7 $2\tmp_cr_in2$19[6:0]$3720
- attribute \src "libresoc.v:79196.3-79218.6"
- wire width 7 $2\tmp_cr_in2[6:0]
- attribute \src "libresoc.v:79257.3-79279.6"
- wire width 7 $2\tmp_cr_out[6:0]
- attribute \src "libresoc.v:79280.3-79295.6"
+ attribute \src "libresoc.v:78063.3-78078.6"
wire width 3 $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $2\trapaddr[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $2\traptype[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $2\xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $2\xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $3\asmcode[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $3\cia[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\cr_in1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire width 7 $3\cr_in2$1[6:0]$3757
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire width 7 $3\cr_in2$1[6:0]$3710
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\cr_in2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\cr_in2_ok$2[0:0]$3758
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\cr_in2_ok$2[0:0]$3711
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\cr_out[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\cr_out_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $3\cr_rd[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $3\cr_wr[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\ea[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\ea_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$3[0:0]$3760
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$4[0:0]$3761
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$5[0:0]$3762
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$6[0:0]$3763
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$7[0:0]$3764
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$8[0:0]$3765
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal$9[0:0]$3766
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $3\exc_$signal[0:0]$3759
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$3[0:0]$3713
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$4[0:0]$3714
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$5[0:0]$3715
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$6[0:0]$3716
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$7[0:0]$3717
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$8[0:0]$3718
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal$9[0:0]$3719
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $3\exc_$signal[0:0]$3712
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $3\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $3\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $3\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $3\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\fasto2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $3\fn_unit[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 2 $3\input_carry[1:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 32 $3\insn[31:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\insn_type[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\is_32bit[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\lk[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $3\msr[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\oe[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\oe_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\rc[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\rc_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\reg1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\reg1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\reg2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\reg2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\reg3[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\reg3_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $3\rego[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\rego_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $3\spr1[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\spr1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $3\spro[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\spro_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $3\trapaddr[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $3\traptype[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $3\xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $3\xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $4\asmcode[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $4\cia[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\cr_in1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\cr_in1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire width 7 $4\cr_in2$1[6:0]$3767
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire width 7 $4\cr_in2$1[6:0]$3720
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\cr_in2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\cr_in2_ok$2[0:0]$3768
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\cr_in2_ok$2[0:0]$3721
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\cr_in2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\cr_out[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\cr_out_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $4\cr_rd[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\cr_rd_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $4\cr_wr[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\cr_wr_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\ea[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\ea_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$3[0:0]$3770
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$4[0:0]$3771
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$5[0:0]$3772
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$6[0:0]$3773
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$7[0:0]$3774
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$8[0:0]$3775
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal$9[0:0]$3776
- attribute \src "libresoc.v:79340.3-79497.6"
- wire $4\exc_$signal[0:0]$3769
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$3[0:0]$3723
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$4[0:0]$3724
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$5[0:0]$3725
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$6[0:0]$3726
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$7[0:0]$3727
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$8[0:0]$3728
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal$9[0:0]$3729
+ attribute \src "libresoc.v:78123.3-78280.6"
+ wire $4\exc_$signal[0:0]$3722
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $4\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $4\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $4\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $4\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\fasto2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $4\fn_unit[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 2 $4\input_carry[1:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 32 $4\insn[31:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\insn_type[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\is_32bit[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\lk[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 64 $4\msr[63:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\oe[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\oe_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\rc[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\rc_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\reg1[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\reg1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\reg2[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\reg2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\reg3[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\reg3_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 7 $4\rego[6:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\rego_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $4\spr1[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\spr1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 10 $4\spro[9:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\spro_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 13 $4\trapaddr[12:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 8 $4\traptype[7:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $4\xer_in[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $4\xer_out[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $5\fast1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $5\fast1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $5\fast2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $5\fast2_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $5\fasto1[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $5\fasto1_ok[0:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire width 3 $5\fasto2[2:0]
- attribute \src "libresoc.v:79340.3-79497.6"
+ attribute \src "libresoc.v:78123.3-78280.6"
wire $5\fasto2_ok[0:0]
- attribute \src "libresoc.v:78885.19-78885.127"
- wire width 8 $add$libresoc.v:78885$3647_Y
- attribute \src "libresoc.v:78886.19-78886.125"
- wire width 8 $add$libresoc.v:78886$3648_Y
- attribute \src "libresoc.v:78887.19-78887.126"
- wire width 8 $add$libresoc.v:78887$3649_Y
- attribute \src "libresoc.v:78894.19-78894.114"
- wire width 8 $add$libresoc.v:78894$3656_Y
- attribute \src "libresoc.v:78895.19-78895.114"
- wire width 8 $add$libresoc.v:78895$3657_Y
- attribute \src "libresoc.v:78896.19-78896.127"
- wire width 8 $add$libresoc.v:78896$3658_Y
- attribute \src "libresoc.v:78899.19-78899.114"
- wire width 8 $add$libresoc.v:78899$3661_Y
- attribute \src "libresoc.v:78900.19-78900.114"
- wire width 8 $add$libresoc.v:78900$3662_Y
- attribute \src "libresoc.v:78901.19-78901.129"
- wire width 8 $add$libresoc.v:78901$3663_Y
- attribute \src "libresoc.v:78904.19-78904.114"
- wire width 8 $add$libresoc.v:78904$3666_Y
- attribute \src "libresoc.v:78905.19-78905.114"
- wire width 8 $add$libresoc.v:78905$3667_Y
- attribute \src "libresoc.v:78906.19-78906.129"
- wire width 8 $add$libresoc.v:78906$3668_Y
- attribute \src "libresoc.v:78909.19-78909.114"
- wire width 8 $add$libresoc.v:78909$3671_Y
- attribute \src "libresoc.v:78910.19-78910.114"
- wire width 8 $add$libresoc.v:78910$3672_Y
- attribute \src "libresoc.v:78911.19-78911.128"
- wire width 8 $add$libresoc.v:78911$3673_Y
- attribute \src "libresoc.v:78950.18-78950.126"
- wire width 8 $add$libresoc.v:78950$3712_Y
- attribute \src "libresoc.v:78951.18-78951.126"
- wire width 8 $add$libresoc.v:78951$3713_Y
- attribute \src "libresoc.v:78916.19-78916.122"
- wire $and$libresoc.v:78916$3678_Y
- attribute \src "libresoc.v:78917.19-78917.125"
- wire $and$libresoc.v:78917$3679_Y
- attribute \src "libresoc.v:78918.19-78918.126"
- wire $and$libresoc.v:78918$3680_Y
- attribute \src "libresoc.v:78925.18-78925.114"
- wire $and$libresoc.v:78925$3687_Y
- attribute \src "libresoc.v:78926.18-78926.116"
- wire $and$libresoc.v:78926$3688_Y
- attribute \src "libresoc.v:78928.18-78928.114"
- wire $and$libresoc.v:78928$3690_Y
- attribute \src "libresoc.v:78930.18-78930.110"
- wire $and$libresoc.v:78930$3692_Y
- attribute \src "libresoc.v:78942.18-78942.114"
- wire $and$libresoc.v:78942$3704_Y
- attribute \src "libresoc.v:78943.18-78943.116"
- wire $and$libresoc.v:78943$3705_Y
- attribute \src "libresoc.v:78945.18-78945.114"
- wire $and$libresoc.v:78945$3707_Y
- attribute \src "libresoc.v:78947.18-78947.110"
- wire $and$libresoc.v:78947$3709_Y
- attribute \src "libresoc.v:78892.19-78892.129"
- wire $eq$libresoc.v:78892$3654_Y
- attribute \src "libresoc.v:78893.19-78893.129"
- wire $eq$libresoc.v:78893$3655_Y
- attribute \src "libresoc.v:78897.19-78897.129"
- wire $eq$libresoc.v:78897$3659_Y
- attribute \src "libresoc.v:78898.19-78898.129"
- wire $eq$libresoc.v:78898$3660_Y
- attribute \src "libresoc.v:78902.19-78902.129"
- wire $eq$libresoc.v:78902$3664_Y
- attribute \src "libresoc.v:78903.19-78903.129"
- wire $eq$libresoc.v:78903$3665_Y
- attribute \src "libresoc.v:78907.19-78907.130"
- wire $eq$libresoc.v:78907$3669_Y
- attribute \src "libresoc.v:78908.19-78908.130"
- wire $eq$libresoc.v:78908$3670_Y
- attribute \src "libresoc.v:78912.19-78912.124"
- wire $eq$libresoc.v:78912$3674_Y
- attribute \src "libresoc.v:78913.19-78913.124"
- wire $eq$libresoc.v:78913$3675_Y
- attribute \src "libresoc.v:78914.19-78914.124"
- wire $eq$libresoc.v:78914$3676_Y
- attribute \src "libresoc.v:78915.19-78915.124"
- wire $eq$libresoc.v:78915$3677_Y
- attribute \src "libresoc.v:78919.19-78919.124"
- wire $eq$libresoc.v:78919$3681_Y
- attribute \src "libresoc.v:78920.18-78920.117"
- wire $eq$libresoc.v:78920$3682_Y
- attribute \src "libresoc.v:78921.18-78921.117"
- wire $eq$libresoc.v:78921$3683_Y
- attribute \src "libresoc.v:78923.18-78923.117"
- wire $eq$libresoc.v:78923$3685_Y
- attribute \src "libresoc.v:78924.18-78924.127"
- wire $eq$libresoc.v:78924$3686_Y
- attribute \src "libresoc.v:78927.18-78927.127"
- wire $eq$libresoc.v:78927$3689_Y
- attribute \src "libresoc.v:78931.18-78931.122"
- wire $eq$libresoc.v:78931$3693_Y
- attribute \src "libresoc.v:78932.18-78932.122"
- wire $eq$libresoc.v:78932$3694_Y
- attribute \src "libresoc.v:78934.18-78934.110"
- wire $eq$libresoc.v:78934$3696_Y
- attribute \src "libresoc.v:78935.18-78935.110"
- wire $eq$libresoc.v:78935$3697_Y
- attribute \src "libresoc.v:78937.18-78937.112"
- wire $eq$libresoc.v:78937$3699_Y
- attribute \src "libresoc.v:78939.18-78939.110"
- wire $eq$libresoc.v:78939$3701_Y
- attribute \src "libresoc.v:78941.18-78941.127"
- wire $eq$libresoc.v:78941$3703_Y
- attribute \src "libresoc.v:78944.18-78944.127"
- wire $eq$libresoc.v:78944$3706_Y
- attribute \src "libresoc.v:78948.18-78948.119"
- wire $eq$libresoc.v:78948$3710_Y
- attribute \src "libresoc.v:78949.18-78949.119"
- wire $eq$libresoc.v:78949$3711_Y
- attribute \src "libresoc.v:78889.19-78889.107"
- wire $not$libresoc.v:78889$3651_Y
- attribute \src "libresoc.v:78891.19-78891.107"
- wire $not$libresoc.v:78891$3653_Y
- attribute \src "libresoc.v:78929.18-78929.110"
- wire $not$libresoc.v:78929$3691_Y
- attribute \src "libresoc.v:78946.18-78946.110"
- wire $not$libresoc.v:78946$3708_Y
- attribute \src "libresoc.v:78922.18-78922.111"
- wire $or$libresoc.v:78922$3684_Y
- attribute \src "libresoc.v:78933.18-78933.110"
- wire $or$libresoc.v:78933$3695_Y
- attribute \src "libresoc.v:78936.18-78936.110"
- wire $or$libresoc.v:78936$3698_Y
- attribute \src "libresoc.v:78938.18-78938.110"
- wire $or$libresoc.v:78938$3700_Y
- attribute \src "libresoc.v:78940.18-78940.110"
- wire $or$libresoc.v:78940$3702_Y
- attribute \src "libresoc.v:78888.19-78888.213"
- wire $reduce_or$libresoc.v:78888$3650_Y
- attribute \src "libresoc.v:78890.19-78890.154"
- wire $reduce_or$libresoc.v:78890$3652_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1069"
- wire \$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1069"
+ attribute \src "libresoc.v:77847.19-77847.122"
+ wire $and$libresoc.v:77847$3630_Y
+ attribute \src "libresoc.v:77848.19-77848.125"
+ wire $and$libresoc.v:77848$3631_Y
+ attribute \src "libresoc.v:77849.19-77849.126"
+ wire $and$libresoc.v:77849$3632_Y
+ attribute \src "libresoc.v:77856.18-77856.114"
+ wire $and$libresoc.v:77856$3639_Y
+ attribute \src "libresoc.v:77857.18-77857.116"
+ wire $and$libresoc.v:77857$3640_Y
+ attribute \src "libresoc.v:77859.18-77859.114"
+ wire $and$libresoc.v:77859$3642_Y
+ attribute \src "libresoc.v:77861.18-77861.110"
+ wire $and$libresoc.v:77861$3644_Y
+ attribute \src "libresoc.v:77873.18-77873.114"
+ wire $and$libresoc.v:77873$3656_Y
+ attribute \src "libresoc.v:77874.18-77874.116"
+ wire $and$libresoc.v:77874$3657_Y
+ attribute \src "libresoc.v:77876.18-77876.114"
+ wire $and$libresoc.v:77876$3659_Y
+ attribute \src "libresoc.v:77878.18-77878.110"
+ wire $and$libresoc.v:77878$3661_Y
+ attribute \src "libresoc.v:77843.19-77843.124"
+ wire $eq$libresoc.v:77843$3626_Y
+ attribute \src "libresoc.v:77844.19-77844.124"
+ wire $eq$libresoc.v:77844$3627_Y
+ attribute \src "libresoc.v:77845.19-77845.124"
+ wire $eq$libresoc.v:77845$3628_Y
+ attribute \src "libresoc.v:77846.19-77846.124"
+ wire $eq$libresoc.v:77846$3629_Y
+ attribute \src "libresoc.v:77850.19-77850.124"
+ wire $eq$libresoc.v:77850$3633_Y
+ attribute \src "libresoc.v:77851.18-77851.117"
+ wire $eq$libresoc.v:77851$3634_Y
+ attribute \src "libresoc.v:77852.18-77852.117"
+ wire $eq$libresoc.v:77852$3635_Y
+ attribute \src "libresoc.v:77854.18-77854.117"
+ wire $eq$libresoc.v:77854$3637_Y
+ attribute \src "libresoc.v:77855.18-77855.127"
+ wire $eq$libresoc.v:77855$3638_Y
+ attribute \src "libresoc.v:77858.18-77858.127"
+ wire $eq$libresoc.v:77858$3641_Y
+ attribute \src "libresoc.v:77862.18-77862.122"
+ wire $eq$libresoc.v:77862$3645_Y
+ attribute \src "libresoc.v:77863.18-77863.122"
+ wire $eq$libresoc.v:77863$3646_Y
+ attribute \src "libresoc.v:77865.18-77865.110"
+ wire $eq$libresoc.v:77865$3648_Y
+ attribute \src "libresoc.v:77866.18-77866.110"
+ wire $eq$libresoc.v:77866$3649_Y
+ attribute \src "libresoc.v:77868.18-77868.112"
+ wire $eq$libresoc.v:77868$3651_Y
+ attribute \src "libresoc.v:77870.18-77870.110"
+ wire $eq$libresoc.v:77870$3653_Y
+ attribute \src "libresoc.v:77872.18-77872.127"
+ wire $eq$libresoc.v:77872$3655_Y
+ attribute \src "libresoc.v:77875.18-77875.127"
+ wire $eq$libresoc.v:77875$3658_Y
+ attribute \src "libresoc.v:77840.19-77840.124"
+ wire width 7 $extend$libresoc.v:77840$3620_Y
+ attribute \src "libresoc.v:77841.19-77841.124"
+ wire width 7 $extend$libresoc.v:77841$3622_Y
+ attribute \src "libresoc.v:77842.19-77842.123"
+ wire width 7 $extend$libresoc.v:77842$3624_Y
+ attribute \src "libresoc.v:77879.18-77879.111"
+ wire width 7 $extend$libresoc.v:77879$3662_Y
+ attribute \src "libresoc.v:77880.18-77880.111"
+ wire width 7 $extend$libresoc.v:77880$3664_Y
+ attribute \src "libresoc.v:77881.18-77881.111"
+ wire width 7 $extend$libresoc.v:77881$3666_Y
+ attribute \src "libresoc.v:77882.18-77882.113"
+ wire width 7 $extend$libresoc.v:77882$3668_Y
+ attribute \src "libresoc.v:77883.18-77883.121"
+ wire width 7 $extend$libresoc.v:77883$3670_Y
+ attribute \src "libresoc.v:77860.18-77860.110"
+ wire $not$libresoc.v:77860$3643_Y
+ attribute \src "libresoc.v:77877.18-77877.110"
+ wire $not$libresoc.v:77877$3660_Y
+ attribute \src "libresoc.v:77853.18-77853.111"
+ wire $or$libresoc.v:77853$3636_Y
+ attribute \src "libresoc.v:77864.18-77864.110"
+ wire $or$libresoc.v:77864$3647_Y
+ attribute \src "libresoc.v:77867.18-77867.110"
+ wire $or$libresoc.v:77867$3650_Y
+ attribute \src "libresoc.v:77869.18-77869.110"
+ wire $or$libresoc.v:77869$3652_Y
+ attribute \src "libresoc.v:77871.18-77871.110"
+ wire $or$libresoc.v:77871$3654_Y
+ attribute \src "libresoc.v:77840.19-77840.124"
+ wire width 7 $pos$libresoc.v:77840$3621_Y
+ attribute \src "libresoc.v:77841.19-77841.124"
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wire \$110
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wire \$114
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1116"
- wire \$173
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1120"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1143"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1144"
- wire \$179
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1145"
- wire \$181
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1194"
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wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195"
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wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195"
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wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204"
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wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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wire \$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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wire \$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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wire \$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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wire \$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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wire \$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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wire \$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007"
- wire \$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007"
- wire \$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- wire width 8 \$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ wire width 7 \$92
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+ wire width 7 \$94
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+ wire width 7 \$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ wire width 7 \$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
- wire width 8 output 7 \asmcode
+ wire width 8 output 5 \asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464"
wire input 1 \bigendian
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
- wire width 64 output 41 \cia
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1000"
- wire width 3 \cr_a_idx
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1001"
- wire width 3 \cr_b_idx
+ wire width 64 output 39 \cia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 32 \cr_in1
+ wire width 7 output 30 \cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 33 \cr_in1_ok
+ wire output 31 \cr_in1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 34 \cr_in2
+ wire width 7 output 32 \cr_in2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 36 \cr_in2$1
+ wire width 7 output 34 \cr_in2$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 35 \cr_in2_ok
+ wire output 33 \cr_in2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 37 \cr_in2_ok$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904"
- wire \cr_in_b_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903"
- wire \cr_in_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905"
- wire \cr_in_o_isvec
+ wire output 35 \cr_in2_ok$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 38 \cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:902"
- wire \cr_out_isvec
+ wire width 7 output 36 \cr_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 39 \cr_out_ok
+ wire output 37 \cr_out_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 8 output 61 \cr_rd
+ wire width 8 output 59 \cr_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 62 \cr_rd_ok
+ wire output 60 \cr_rd_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 8 output 63 \cr_wr
+ wire width 8 output 61 \cr_wr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 64 \cr_wr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 \crin_svdec_b_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 \crin_svdec_b_cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \crin_svdec_b_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \crin_svdec_b_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \crin_svdec_b_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire \crin_svdec_b_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 \crin_svdec_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 \crin_svdec_cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \crin_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \crin_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \crin_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire \crin_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 \crin_svdec_o_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 \crin_svdec_o_cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \crin_svdec_o_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \crin_svdec_o_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \crin_svdec_o_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire \crin_svdec_o_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130"
- wire width 3 \crout_svdec_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131"
- wire width 7 \crout_svdec_cr_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \crout_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \crout_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \crout_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132"
- wire \crout_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
- wire width 7 input 5 \cur_cur_srcstep
+ wire output 62 \cr_wr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
- wire width 64 input 66 \cur_dec
+ wire width 64 input 64 \cur_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18"
- wire input 67 \cur_eint
+ wire input 65 \cur_eint
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
wire width 64 input 3 \cur_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire \dec_Rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 10 \dec_SPR
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 2 \dec_SV_Etype
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
wire width 5 \dec_XL_BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
attribute \enum_value_111 "CR1"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516"
wire width 3 \dec_cr_in_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522"
- wire width 2 \dec_cr_in_sv_override
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "CR1"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591"
wire width 3 \dec_cr_out_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595"
- wire width 2 \dec_cr_out_sv_override
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 \dec_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1172"
wire \dec_irq_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196"
wire \dec_is_32b
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_cr_in
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_cr_out
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_in1
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_in2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_in3
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 3 \dec_sv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 9 input 6 \dec_svp64__extra
attribute \enum_base_type "LDSTMode"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "update"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 \dec_upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 10 \ea
+ wire width 7 output 8 \ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 11 \ea_ok
+ wire output 9 \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 52 \exc_$signal
+ wire output 50 \exc_$signal
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 53 \exc_$signal$3
+ wire output 51 \exc_$signal$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 54 \exc_$signal$4
+ wire output 52 \exc_$signal$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 55 \exc_$signal$5
+ wire output 53 \exc_$signal$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 56 \exc_$signal$6
+ wire output 54 \exc_$signal$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 57 \exc_$signal$7
+ wire output 55 \exc_$signal$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 58 \exc_$signal$8
+ wire output 56 \exc_$signal$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
- wire output 59 \exc_$signal$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1137"
+ wire output 57 \exc_$signal$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171"
wire \ext_irq_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 24 \fast1
+ wire width 3 output 22 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 25 \fast1_ok
+ wire output 23 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 26 \fast2
+ wire width 3 output 24 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 27 \fast2_ok
+ wire output 25 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 28 \fasto1
+ wire width 3 output 26 \fasto1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 29 \fasto1_ok
+ wire output 27 \fasto1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 30 \fasto2
+ wire width 3 output 28 \fasto2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 31 \fasto2_ok
+ wire output 29 \fasto2_ok
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \enum_value_0000000000010 "ALU"
attribute \enum_value_0100000000000 "MMU"
attribute \enum_value_1000000000000 "SV"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
- wire width 13 output 44 \fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1140"
+ wire width 13 output 42 \fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1174"
wire \illeg_ok
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \in1_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \in1_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \in1_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire \in1_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 \in1_svdec_reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 \in1_svdec_reg_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \in2_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \in2_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \in2_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire \in2_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 \in2_svdec_reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 \in2_svdec_reg_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \in3_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \in3_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \in3_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire \in3_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 \in3_svdec_reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 \in3_svdec_reg_out
- attribute \src "libresoc.v:76811.7-76811.15"
+ attribute \src "libresoc.v:76154.7-76154.15"
wire \initial
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
- wire width 2 output 50 \input_carry
+ wire width 2 output 48 \input_carry
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
- wire width 32 output 42 \insn
+ wire width 32 output 40 \insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
- wire width 7 output 43 \insn_type
+ wire width 7 output 41 \insn_type
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
- wire output 65 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ wire output 63 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51"
wire \is_priv_insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
- wire output 45 \lk
+ wire output 43 \lk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
- wire width 64 output 40 \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911"
- wire \no_in_vec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912"
- wire \no_out_vec
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \o2_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \o2_svdec_extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire \o2_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 \o2_svdec_reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 \o2_svdec_reg_out
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 \o_svdec_etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 \o_svdec_extra
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \o_svdec_idx
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire \o_svdec_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 \o_svdec_reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 \o_svdec_reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 48 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 49 \oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1139"
+ wire width 64 output 38 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ wire output 46 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ wire output 47 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173"
wire \priv_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 4 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 46 \rc
+ wire output 44 \rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 47 \rc_ok
+ wire output 45 \rc_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 12 \reg1
+ wire width 7 output 10 \reg1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 13 \reg1_ok
+ wire output 11 \reg1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 14 \reg2
+ wire width 7 output 12 \reg2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 15 \reg2_ok
+ wire output 13 \reg2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 16 \reg3
+ wire width 7 output 14 \reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 17 \reg3_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906"
- wire \reg_a_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:907"
- wire \reg_b_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:908"
- wire \reg_c_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910"
- wire \reg_o2_isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909"
- wire \reg_o_isvec
+ wire output 15 \reg3_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 7 output 8 \rego
+ wire width 7 output 6 \rego
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 9 \rego_ok
+ wire output 7 \rego_ok
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389"
wire width 2 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 10 output 20 \spr1
+ wire width 10 output 18 \spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 21 \spr1_ok
+ wire output 19 \spr1_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 10 output 18 \spro
+ wire width 10 output 16 \spro
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 19 \spro_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1030"
- wire width 7 \srcstep
+ wire output 17 \spro_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
wire width 8 \tmp_asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire \tmp_xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
- wire width 13 output 60 \trapaddr
+ wire width 13 output 58 \trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
- wire width 8 output 51 \traptype
+ wire width 8 output 49 \traptype
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
- wire width 3 output 22 \xer_in
+ wire width 3 output 20 \xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
- wire output 23 \xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- cell $add $add$libresoc.v:78885$3647
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \in3_svdec_reg_out
- connect \Y $add$libresoc.v:78885$3647_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- cell $add $add$libresoc.v:78886$3648
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \o_svdec_reg_out
- connect \Y $add$libresoc.v:78886$3648_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- cell $add $add$libresoc.v:78887$3649
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \o2_svdec_reg_out
- connect \Y $add$libresoc.v:78887$3649_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099"
- cell $add $add$libresoc.v:78894$3656
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'0
- connect \Y $add$libresoc.v:78894$3656_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102"
- cell $add $add$libresoc.v:78895$3657
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'1
- connect \Y $add$libresoc.v:78895$3657_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104"
- cell $add $add$libresoc.v:78896$3658
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \crin_svdec_cr_out
- connect \Y $add$libresoc.v:78896$3658_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099"
- cell $add $add$libresoc.v:78899$3661
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'0
- connect \Y $add$libresoc.v:78899$3661_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102"
- cell $add $add$libresoc.v:78900$3662
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'1
- connect \Y $add$libresoc.v:78900$3662_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104"
- cell $add $add$libresoc.v:78901$3663
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \crin_svdec_b_cr_out
- connect \Y $add$libresoc.v:78901$3663_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099"
- cell $add $add$libresoc.v:78904$3666
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'0
- connect \Y $add$libresoc.v:78904$3666_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102"
- cell $add $add$libresoc.v:78905$3667
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'1
- connect \Y $add$libresoc.v:78905$3667_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104"
- cell $add $add$libresoc.v:78906$3668
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \crin_svdec_o_cr_out
- connect \Y $add$libresoc.v:78906$3668_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099"
- cell $add $add$libresoc.v:78909$3671
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'0
- connect \Y $add$libresoc.v:78909$3671_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102"
- cell $add $add$libresoc.v:78910$3672
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B 1'1
- connect \Y $add$libresoc.v:78910$3672_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104"
- cell $add $add$libresoc.v:78911$3673
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \crout_svdec_cr_out
- connect \Y $add$libresoc.v:78911$3673_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- cell $add $add$libresoc.v:78950$3712
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \in1_svdec_reg_out
- connect \Y $add$libresoc.v:78950$3712_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047"
- cell $add $add$libresoc.v:78951$3713
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A \srcstep
- connect \B \in2_svdec_reg_out
- connect \Y $add$libresoc.v:78951$3713_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1143"
- cell $and $and$libresoc.v:78916$3678
+ wire output 21 \xer_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177"
+ cell $and $and$libresoc.v:77847$3630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_eint
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:78916$3678_Y
+ connect \Y $and$libresoc.v:77847$3630_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1144"
- cell $and $and$libresoc.v:78917$3679
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1178"
+ cell $and $and$libresoc.v:77848$3631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_dec [63]
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:78917$3679_Y
+ connect \Y $and$libresoc.v:77848$3631_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1145"
- cell $and $and$libresoc.v:78918$3680
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179"
+ cell $and $and$libresoc.v:77849$3632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_priv_insn
connect \B \cur_msr [14]
- connect \Y $and$libresoc.v:78918$3680_Y
+ connect \Y $and$libresoc.v:77849$3632_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:78925$3687
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:77856$3639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$37
- connect \Y $and$libresoc.v:78925$3687_Y
+ connect \Y $and$libresoc.v:77856$3639_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:78926$3688
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:77857$3640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:78926$3688_Y
+ connect \Y $and$libresoc.v:77857$3640_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:78928$3690
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:77859$3642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$43
- connect \Y $and$libresoc.v:78928$3690_Y
+ connect \Y $and$libresoc.v:77859$3642_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:78930$3692
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:77861$3644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$45
connect \B \$47
- connect \Y $and$libresoc.v:78930$3692_Y
+ connect \Y $and$libresoc.v:77861$3644_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:78942$3704
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:77873$3656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$71
- connect \Y $and$libresoc.v:78942$3704_Y
+ connect \Y $and$libresoc.v:77873$3656_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:78943$3705
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:77874$3657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:78943$3705_Y
+ connect \Y $and$libresoc.v:77874$3657_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:78945$3707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:77876$3659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$77
- connect \Y $and$libresoc.v:78945$3707_Y
+ connect \Y $and$libresoc.v:77876$3659_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:78947$3709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:77878$3661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$79
connect \B \$81
- connect \Y $and$libresoc.v:78947$3709_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- cell $eq $eq$libresoc.v:78892$3654
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 1'1
- connect \Y $eq$libresoc.v:78892$3654_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100"
- cell $eq $eq$libresoc.v:78893$3655
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 2'10
- connect \Y $eq$libresoc.v:78893$3655_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- cell $eq $eq$libresoc.v:78897$3659
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 1'1
- connect \Y $eq$libresoc.v:78897$3659_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100"
- cell $eq $eq$libresoc.v:78898$3660
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 2'10
- connect \Y $eq$libresoc.v:78898$3660_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- cell $eq $eq$libresoc.v:78902$3664
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 1'1
- connect \Y $eq$libresoc.v:78902$3664_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100"
- cell $eq $eq$libresoc.v:78903$3665
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \dec_cr_in_sv_override
- connect \B 2'10
- connect \Y $eq$libresoc.v:78903$3665_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- cell $eq $eq$libresoc.v:78907$3669
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \dec_cr_out_sv_override
- connect \B 1'1
- connect \Y $eq$libresoc.v:78907$3669_Y
+ connect \Y $and$libresoc.v:77878$3661_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100"
- cell $eq $eq$libresoc.v:78908$3670
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \dec_cr_out_sv_override
- connect \B 2'10
- connect \Y $eq$libresoc.v:78908$3670_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1112"
- cell $eq $eq$libresoc.v:78912$3674
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146"
+ cell $eq $eq$libresoc.v:77843$3626
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:78912$3674_Y
+ connect \Y $eq$libresoc.v:77843$3626_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1114"
- cell $eq $eq$libresoc.v:78913$3675
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1148"
+ cell $eq $eq$libresoc.v:77844$3627
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0001010
- connect \Y $eq$libresoc.v:78913$3675_Y
+ connect \Y $eq$libresoc.v:77844$3627_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1116"
- cell $eq $eq$libresoc.v:78914$3676
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150"
+ cell $eq $eq$libresoc.v:77845$3628
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:78914$3676_Y
+ connect \Y $eq$libresoc.v:77845$3628_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1120"
- cell $eq $eq$libresoc.v:78915$3677
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154"
+ cell $eq $eq$libresoc.v:77846$3629
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0111111
- connect \Y $eq$libresoc.v:78915$3677_Y
+ connect \Y $eq$libresoc.v:77846$3629_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146"
- cell $eq $eq$libresoc.v:78919$3681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1180"
+ cell $eq $eq$libresoc.v:77850$3633
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0000000
- connect \Y $eq$libresoc.v:78919$3681_Y
+ connect \Y $eq$libresoc.v:77850$3633_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1194"
- cell $eq $eq$libresoc.v:78920$3682
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228"
+ cell $eq $eq$libresoc.v:77851$3634
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'0111111
- connect \Y $eq$libresoc.v:78920$3682_Y
+ connect \Y $eq$libresoc.v:77851$3634_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195"
- cell $eq $eq$libresoc.v:78921$3683
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229"
+ cell $eq $eq$libresoc.v:77852$3635
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
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attribute \module_not_derived 1
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cell \dec$171 \dec
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connect \Rc \dec_Rc
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connect \XL_BT \dec_XL_BT
connect \XL_XO \dec_XL_XO
connect \X_BF \dec_X_BF
connect \out_sel \dec_out_sel
connect \raw_opcode_in \raw_opcode_in
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attribute \module_not_derived 1
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cell \dec_a \dec_a
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end
attribute \module_not_derived 1
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attribute \module_not_derived 1
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attribute \module_not_derived 1
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cell \dec_cr_in \dec_cr_in$10
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attribute \module_not_derived 1
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cell \dec_cr_out \dec_cr_out$11
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connect \XL_BT \dec_XL_BT
connect \internal_op \dec_internal_op
connect \rc_in \dec_cr_out_rc_in
connect \sel_in \dec_cr_out_sel_in
- connect \sv_override \dec_cr_out_sv_override
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79097.9-79110.4"
+ attribute \src "libresoc.v:77988.9-78001.4"
cell \dec_o \dec_o
connect \BO \dec_BO
connect \RA \dec_RA
connect \spr_o_ok \dec_o_spr_o_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79111.10-79120.4"
+ attribute \src "libresoc.v:78002.10-78011.4"
cell \dec_o2 \dec_o2
connect \RA \dec_RA
connect \fast_o2 \dec_o2_fast_o2
connect \upd \dec_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79121.16-79127.4"
+ attribute \src "libresoc.v:78012.16-78018.4"
cell \dec_oe$173 \dec_oe
connect \OE \dec_OE
connect \internal_op \dec_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:79128.16-79133.4"
+ attribute \src "libresoc.v:78019.16-78024.4"
cell \dec_rc$172 \dec_rc
connect \Rc \dec_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:79134.13-79141.4"
- cell \in1_svdec \in1_svdec
- connect \etype \in1_svdec_etype
- connect \extra \in1_svdec_extra
- connect \idx \in1_svdec_idx
- connect \isvec \in1_svdec_isvec
- connect \reg_in \in1_svdec_reg_in
- connect \reg_out \in1_svdec_reg_out
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:79142.13-79149.4"
- cell \in2_svdec \in2_svdec
- connect \etype \in2_svdec_etype
- connect \extra \in2_svdec_extra
- connect \idx \in2_svdec_idx
- connect \isvec \in2_svdec_isvec
- connect \reg_in \in2_svdec_reg_in
- connect \reg_out \in2_svdec_reg_out
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:79150.13-79157.4"
- cell \in3_svdec \in3_svdec
- connect \etype \in3_svdec_etype
- connect \extra \in3_svdec_extra
- connect \idx \in3_svdec_idx
- connect \isvec \in3_svdec_isvec
- connect \reg_in \in3_svdec_reg_in
- connect \reg_out \in3_svdec_reg_out
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:79158.12-79164.4"
- cell \o2_svdec \o2_svdec
- connect \etype \o2_svdec_etype
- connect \extra \o2_svdec_extra
- connect \isvec \o2_svdec_isvec
- connect \reg_in \o2_svdec_reg_in
- connect \reg_out \o2_svdec_reg_out
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:79165.11-79172.4"
- cell \o_svdec \o_svdec
- connect \etype \o_svdec_etype
- connect \extra \o_svdec_extra
- connect \idx \o_svdec_idx
- connect \isvec \o_svdec_isvec
- connect \reg_in \o_svdec_reg_in
- connect \reg_out \o_svdec_reg_out
- end
- attribute \src "libresoc.v:76811.7-76811.20"
- process $proc$libresoc.v:76811$3786
+ attribute \src "libresoc.v:76154.7-76154.20"
+ process $proc$libresoc.v:76154$3730
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:79173.3-79195.6"
- process $proc$libresoc.v:79173$3714
- assign { } { }
- assign $0\tmp_cr_in1[6:0] $1\tmp_cr_in1[6:0]
- attribute \src "libresoc.v:79174.5-79174.29"
- switch \initial
- attribute \src "libresoc.v:79174.9-79174.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093"
- switch \crin_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_cr_in1[6:0] $2\tmp_cr_in1[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- switch { \$119 \$117 }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $2\tmp_cr_in1[6:0] \$121 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $2\tmp_cr_in1[6:0] \$124 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\tmp_cr_in1[6:0] \$127 [6:0]
- end
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_cr_in1[6:0] \crin_svdec_cr_out
- end
- sync always
- update \tmp_cr_in1 $0\tmp_cr_in1[6:0]
- end
- attribute \src "libresoc.v:79196.3-79218.6"
- process $proc$libresoc.v:79196$3715
- assign { } { }
- assign $0\tmp_cr_in2[6:0] $1\tmp_cr_in2[6:0]
- attribute \src "libresoc.v:79197.5-79197.29"
- switch \initial
- attribute \src "libresoc.v:79197.9-79197.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093"
- switch \crin_svdec_b_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_cr_in2[6:0] $2\tmp_cr_in2[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- switch { \$132 \$130 }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $2\tmp_cr_in2[6:0] \$134 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $2\tmp_cr_in2[6:0] \$137 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\tmp_cr_in2[6:0] \$140 [6:0]
- end
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_cr_in2[6:0] \crin_svdec_b_cr_out
- end
- sync always
- update \tmp_cr_in2 $0\tmp_cr_in2[6:0]
- end
- attribute \src "libresoc.v:79219.3-79233.6"
- process $proc$libresoc.v:79219$3716
+ attribute \src "libresoc.v:78025.3-78039.6"
+ process $proc$libresoc.v:78025$3672
assign { } { }
assign $0\tmp_tmp_fn_unit[12:0] $1\tmp_tmp_fn_unit[12:0]
- attribute \src "libresoc.v:79220.5-79220.29"
+ attribute \src "libresoc.v:78026.5-78026.29"
switch \initial
- attribute \src "libresoc.v:79220.9-79220.17"
+ attribute \src "libresoc.v:78026.9-78026.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$83 \$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[12:0]
end
- attribute \src "libresoc.v:79234.3-79256.6"
- process $proc$libresoc.v:79234$3717
+ attribute \src "libresoc.v:78040.3-78049.6"
+ process $proc$libresoc.v:78040$3673
assign { } { }
- assign $0\tmp_cr_in2$19[6:0]$3718 $1\tmp_cr_in2$19[6:0]$3719
- attribute \src "libresoc.v:79235.5-79235.29"
+ assign { } { }
+ assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0]
+ attribute \src "libresoc.v:78041.5-78041.29"
switch \initial
- attribute \src "libresoc.v:79235.9-79235.17"
+ attribute \src "libresoc.v:78041.9-78041.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093"
- switch \crin_svdec_o_isvec
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863"
+ switch \dec_lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\tmp_cr_in2$19[6:0]$3719 $2\tmp_cr_in2$19[6:0]$3720
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- switch { \$145 \$143 }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $2\tmp_cr_in2$19[6:0]$3720 \$147 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $2\tmp_cr_in2$19[6:0]$3720 \$150 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\tmp_cr_in2$19[6:0]$3720 \$153 [6:0]
- end
- attribute \src "libresoc.v:0.0-0.0"
+ assign $1\tmp_tmp_lk[0:0] \dec_LK
case
- assign { } { }
- assign $1\tmp_cr_in2$19[6:0]$3719 \crin_svdec_o_cr_out
+ assign $1\tmp_tmp_lk[0:0] 1'0
end
sync always
- update \tmp_cr_in2$19 $0\tmp_cr_in2$19[6:0]$3718
+ update \tmp_tmp_lk $0\tmp_tmp_lk[0:0]
end
- attribute \src "libresoc.v:79257.3-79279.6"
- process $proc$libresoc.v:79257$3721
+ attribute \src "libresoc.v:78050.3-78062.6"
+ process $proc$libresoc.v:78050$3674
+ assign { } { }
assign { } { }
- assign $0\tmp_cr_out[6:0] $1\tmp_cr_out[6:0]
- attribute \src "libresoc.v:79258.5-79258.29"
+ assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0]
+ attribute \src "libresoc.v:78051.5-78051.29"
switch \initial
- attribute \src "libresoc.v:79258.9-79258.17"
+ attribute \src "libresoc.v:78051.9-78051.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093"
- switch \crout_svdec_isvec
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ switch { \$49 \$41 }
attribute \src "libresoc.v:0.0-0.0"
- case 1'1
+ case 2'-1
assign { } { }
- assign $1\tmp_cr_out[6:0] $2\tmp_cr_out[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097"
- switch { \$158 \$156 }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $2\tmp_cr_out[6:0] \$160 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $2\tmp_cr_out[6:0] \$163 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\tmp_cr_out[6:0] \$166 [6:0]
- end
+ assign $1\tmp_tmp_insn_type[6:0] 7'0000000
attribute \src "libresoc.v:0.0-0.0"
- case
+ case 2'1-
assign { } { }
- assign $1\tmp_cr_out[6:0] \crout_svdec_cr_out
+ assign $1\tmp_tmp_insn_type[6:0] 7'0000000
+ case
+ assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op
end
sync always
- update \tmp_cr_out $0\tmp_cr_out[6:0]
+ update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0]
end
- attribute \src "libresoc.v:79280.3-79295.6"
- process $proc$libresoc.v:79280$3722
+ attribute \src "libresoc.v:78063.3-78078.6"
+ process $proc$libresoc.v:78063$3675
assign { } { }
assign { } { }
assign { } { }
assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:79281.5-79281.29"
+ attribute \src "libresoc.v:78064.5-78064.29"
switch \initial
- attribute \src "libresoc.v:79281.9-79281.17"
+ attribute \src "libresoc.v:78064.9-78064.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1112"
- switch \$169
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146"
+ switch \$106
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
case
assign $1\tmp_xer_in[2:0] 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1114"
- switch \$171
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1148"
+ switch \$108
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \tmp_xer_in $0\tmp_xer_in[2:0]
end
- attribute \src "libresoc.v:79296.3-79305.6"
- process $proc$libresoc.v:79296$3723
+ attribute \src "libresoc.v:78079.3-78088.6"
+ process $proc$libresoc.v:78079$3676
assign { } { }
assign { } { }
assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:79297.5-79297.29"
+ attribute \src "libresoc.v:78080.5-78080.29"
switch \initial
- attribute \src "libresoc.v:79297.9-79297.17"
+ attribute \src "libresoc.v:78080.9-78080.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1116"
- switch \$173
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150"
+ switch \$110
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \tmp_xer_out $0\tmp_xer_out[0:0]
end
- attribute \src "libresoc.v:79306.3-79315.6"
- process $proc$libresoc.v:79306$3724
+ attribute \src "libresoc.v:78089.3-78098.6"
+ process $proc$libresoc.v:78089$3677
assign { } { }
assign { } { }
assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:79307.5-79307.29"
+ attribute \src "libresoc.v:78090.5-78090.29"
switch \initial
- attribute \src "libresoc.v:79307.9-79307.17"
+ attribute \src "libresoc.v:78090.9-78090.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1120"
- switch \$175
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154"
+ switch \$112
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0]
end
- attribute \src "libresoc.v:79316.3-79339.6"
- process $proc$libresoc.v:79316$3725
+ attribute \src "libresoc.v:78099.3-78122.6"
+ process $proc$libresoc.v:78099$3678
assign { } { }
assign { } { }
assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:79317.5-79317.29"
+ attribute \src "libresoc.v:78100.5-78100.29"
switch \initial
- attribute \src "libresoc.v:79317.9-79317.17"
+ attribute \src "libresoc.v:78100.9-78100.17"
case 1'1
case
end
sync always
update \is_priv_insn $0\is_priv_insn[0:0]
end
- attribute \src "libresoc.v:79340.3-79497.6"
- process $proc$libresoc.v:79340$3726
+ attribute \src "libresoc.v:78123.3-78280.6"
+ process $proc$libresoc.v:78123$3679
assign { } { }
assign { } { }
assign { } { }
assign $0\msr[63:0] $1\msr[63:0]
assign $0\ea_ok[0:0] $1\ea_ok[0:0]
assign $0\ea[6:0] $1\ea[6:0]
- assign $0\cr_out[6:0] $1\cr_out[6:0]
assign { } { }
+ assign $0\cr_out[6:0] $1\cr_out[6:0]
assign $0\lk[0:0] $1\lk[0:0]
assign $0\cia[63:0] $1\cia[63:0]
assign $0\cr_in1[6:0] $1\cr_in1[6:0]
assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0]
assign $0\cr_in2[6:0] $1\cr_in2[6:0]
- assign $0\cr_in2$1[6:0]$3727 $1\cr_in2$1[6:0]$3737
+ assign $0\cr_in2$1[6:0]$3680 $1\cr_in2$1[6:0]$3690
assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0]
- assign $0\cr_in2_ok$2[0:0]$3728 $1\cr_in2_ok$2[0:0]$3738
+ assign $0\cr_in2_ok$2[0:0]$3681 $1\cr_in2_ok$2[0:0]$3691
assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0]
assign $0\cr_rd[7:0] $1\cr_rd[7:0]
assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0]
assign $0\cr_wr[7:0] $1\cr_wr[7:0]
assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0]
- assign $0\exc_$signal[0:0]$3729 $1\exc_$signal[0:0]$3739
- assign $0\exc_$signal$3[0:0]$3730 $1\exc_$signal$3[0:0]$3740
- assign $0\exc_$signal$4[0:0]$3731 $1\exc_$signal$4[0:0]$3741
- assign $0\exc_$signal$5[0:0]$3732 $1\exc_$signal$5[0:0]$3742
- assign $0\exc_$signal$6[0:0]$3733 $1\exc_$signal$6[0:0]$3743
- assign $0\exc_$signal$7[0:0]$3734 $1\exc_$signal$7[0:0]$3744
- assign $0\exc_$signal$8[0:0]$3735 $1\exc_$signal$8[0:0]$3745
- assign $0\exc_$signal$9[0:0]$3736 $1\exc_$signal$9[0:0]$3746
+ assign $0\exc_$signal[0:0]$3682 $1\exc_$signal[0:0]$3692
+ assign $0\exc_$signal$3[0:0]$3683 $1\exc_$signal$3[0:0]$3693
+ assign $0\exc_$signal$4[0:0]$3684 $1\exc_$signal$4[0:0]$3694
+ assign $0\exc_$signal$5[0:0]$3685 $1\exc_$signal$5[0:0]$3695
+ assign $0\exc_$signal$6[0:0]$3686 $1\exc_$signal$6[0:0]$3696
+ assign $0\exc_$signal$7[0:0]$3687 $1\exc_$signal$7[0:0]$3697
+ assign $0\exc_$signal$8[0:0]$3688 $1\exc_$signal$8[0:0]$3698
+ assign $0\exc_$signal$9[0:0]$3689 $1\exc_$signal$9[0:0]$3699
assign { } { }
assign { } { }
assign { } { }
assign $0\fast2[2:0] $5\fast2[2:0]
assign $0\fast2_ok[0:0] $5\fast2_ok[0:0]
assign $0\asmcode[7:0] \dec_asmcode
- attribute \src "libresoc.v:79341.5-79341.29"
+ attribute \src "libresoc.v:78124.5-78124.29"
switch \initial
- attribute \src "libresoc.v:79341.9-79341.17"
+ attribute \src "libresoc.v:78124.9-78124.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1184"
switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal }
attribute \src "libresoc.v:0.0-0.0"
case 5'----1
assign $1\msr[63:0] $2\msr[63:0]
assign $1\ea_ok[0:0] $2\ea_ok[0:0]
assign $1\ea[6:0] $2\ea[6:0]
- assign $1\cr_out[6:0] $2\cr_out[6:0]
assign $1\asmcode[7:0] $2\asmcode[7:0]
+ assign $1\cr_out[6:0] $2\cr_out[6:0]
assign $1\lk[0:0] $2\lk[0:0]
assign $1\cia[63:0] $2\cia[63:0]
assign $1\cr_in1[6:0] $2\cr_in1[6:0]
assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0]
assign $1\cr_in2[6:0] $2\cr_in2[6:0]
- assign $1\cr_in2$1[6:0]$3737 $2\cr_in2$1[6:0]$3747
+ assign $1\cr_in2$1[6:0]$3690 $2\cr_in2$1[6:0]$3700
assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0]
- assign $1\cr_in2_ok$2[0:0]$3738 $2\cr_in2_ok$2[0:0]$3748
+ assign $1\cr_in2_ok$2[0:0]$3691 $2\cr_in2_ok$2[0:0]$3701
assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0]
assign $1\cr_rd[7:0] $2\cr_rd[7:0]
assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0]
assign $1\cr_wr[7:0] $2\cr_wr[7:0]
assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0]
- assign $1\exc_$signal[0:0]$3739 $2\exc_$signal[0:0]$3749
- assign $1\exc_$signal$3[0:0]$3740 $2\exc_$signal$3[0:0]$3750
- assign $1\exc_$signal$4[0:0]$3741 $2\exc_$signal$4[0:0]$3751
- assign $1\exc_$signal$5[0:0]$3742 $2\exc_$signal$5[0:0]$3752
- assign $1\exc_$signal$6[0:0]$3743 $2\exc_$signal$6[0:0]$3753
- assign $1\exc_$signal$7[0:0]$3744 $2\exc_$signal$7[0:0]$3754
- assign $1\exc_$signal$8[0:0]$3745 $2\exc_$signal$8[0:0]$3755
- assign $1\exc_$signal$9[0:0]$3746 $2\exc_$signal$9[0:0]$3756
+ assign $1\exc_$signal[0:0]$3692 $2\exc_$signal[0:0]$3702
+ assign $1\exc_$signal$3[0:0]$3693 $2\exc_$signal$3[0:0]$3703
+ assign $1\exc_$signal$4[0:0]$3694 $2\exc_$signal$4[0:0]$3704
+ assign $1\exc_$signal$5[0:0]$3695 $2\exc_$signal$5[0:0]$3705
+ assign $1\exc_$signal$6[0:0]$3696 $2\exc_$signal$6[0:0]$3706
+ assign $1\exc_$signal$7[0:0]$3697 $2\exc_$signal$7[0:0]$3707
+ assign $1\exc_$signal$8[0:0]$3698 $2\exc_$signal$8[0:0]$3708
+ assign $1\exc_$signal$9[0:0]$3699 $2\exc_$signal$9[0:0]$3709
assign $1\fasto1[2:0] $2\fasto1[2:0]
assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0]
assign $1\fasto2[2:0] $2\fasto2[2:0]
assign $1\traptype[7:0] $2\traptype[7:0]
assign $1\xer_in[2:0] $2\xer_in[2:0]
assign $1\xer_out[0:0] $2\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185"
switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3756 $2\exc_$signal$8[0:0]$3755 $2\exc_$signal$7[0:0]$3754 $2\exc_$signal$6[0:0]$3753 $2\exc_$signal$5[0:0]$3752 $2\exc_$signal$4[0:0]$3751 $2\exc_$signal$3[0:0]$3750 $2\exc_$signal[0:0]$3749 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3748 $2\cr_in2$1[6:0]$3747 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3709 $2\exc_$signal$8[0:0]$3708 $2\exc_$signal$7[0:0]$3707 $2\exc_$signal$6[0:0]$3706 $2\exc_$signal$5[0:0]$3705 $2\exc_$signal$4[0:0]$3704 $2\exc_$signal$3[0:0]$3703 $2\exc_$signal[0:0]$3702 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3701 $2\cr_in2$1[6:0]$3700 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $2\insn[31:0] \dec_opcode_in
assign $2\insn_type[6:0] 7'0111111
assign $2\fn_unit[12:0] 13'0000010000000
assign $2\msr[63:0] $3\msr[63:0]
assign $2\ea_ok[0:0] $3\ea_ok[0:0]
assign $2\ea[6:0] $3\ea[6:0]
- assign $2\cr_out[6:0] $3\cr_out[6:0]
assign $2\asmcode[7:0] $3\asmcode[7:0]
+ assign $2\cr_out[6:0] $3\cr_out[6:0]
assign $2\lk[0:0] $3\lk[0:0]
assign $2\cia[63:0] $3\cia[63:0]
assign $2\cr_in1[6:0] $3\cr_in1[6:0]
assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0]
assign $2\cr_in2[6:0] $3\cr_in2[6:0]
- assign $2\cr_in2$1[6:0]$3747 $3\cr_in2$1[6:0]$3757
+ assign $2\cr_in2$1[6:0]$3700 $3\cr_in2$1[6:0]$3710
assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0]
- assign $2\cr_in2_ok$2[0:0]$3748 $3\cr_in2_ok$2[0:0]$3758
+ assign $2\cr_in2_ok$2[0:0]$3701 $3\cr_in2_ok$2[0:0]$3711
assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0]
assign $2\cr_rd[7:0] $3\cr_rd[7:0]
assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0]
assign $2\cr_wr[7:0] $3\cr_wr[7:0]
assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0]
- assign $2\exc_$signal[0:0]$3749 $3\exc_$signal[0:0]$3759
- assign $2\exc_$signal$3[0:0]$3750 $3\exc_$signal$3[0:0]$3760
- assign $2\exc_$signal$4[0:0]$3751 $3\exc_$signal$4[0:0]$3761
- assign $2\exc_$signal$5[0:0]$3752 $3\exc_$signal$5[0:0]$3762
- assign $2\exc_$signal$6[0:0]$3753 $3\exc_$signal$6[0:0]$3763
- assign $2\exc_$signal$7[0:0]$3754 $3\exc_$signal$7[0:0]$3764
- assign $2\exc_$signal$8[0:0]$3755 $3\exc_$signal$8[0:0]$3765
- assign $2\exc_$signal$9[0:0]$3756 $3\exc_$signal$9[0:0]$3766
+ assign $2\exc_$signal[0:0]$3702 $3\exc_$signal[0:0]$3712
+ assign $2\exc_$signal$3[0:0]$3703 $3\exc_$signal$3[0:0]$3713
+ assign $2\exc_$signal$4[0:0]$3704 $3\exc_$signal$4[0:0]$3714
+ assign $2\exc_$signal$5[0:0]$3705 $3\exc_$signal$5[0:0]$3715
+ assign $2\exc_$signal$6[0:0]$3706 $3\exc_$signal$6[0:0]$3716
+ assign $2\exc_$signal$7[0:0]$3707 $3\exc_$signal$7[0:0]$3717
+ assign $2\exc_$signal$8[0:0]$3708 $3\exc_$signal$8[0:0]$3718
+ assign $2\exc_$signal$9[0:0]$3709 $3\exc_$signal$9[0:0]$3719
assign $2\fasto1[2:0] $3\fasto1[2:0]
assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0]
assign $2\fasto2[2:0] $3\fasto2[2:0]
assign $2\traptype[7:0] $3\traptype[7:0]
assign $2\xer_in[2:0] $3\xer_in[2:0]
assign $2\xer_out[0:0] $3\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1188"
switch \dec2_exc_$signal$14
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3766 $3\exc_$signal$8[0:0]$3765 $3\exc_$signal$7[0:0]$3764 $3\exc_$signal$6[0:0]$3763 $3\exc_$signal$5[0:0]$3762 $3\exc_$signal$4[0:0]$3761 $3\exc_$signal$3[0:0]$3760 $3\exc_$signal[0:0]$3759 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3758 $3\cr_in2$1[6:0]$3757 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $3\insn[31:0] \dec_opcode_in
assign $3\insn_type[6:0] 7'0111111
assign $3\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3758 $3\cr_in2$1[6:0]$3757 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $3\insn[31:0] \dec_opcode_in
assign $3\insn_type[6:0] 7'0111111
assign $3\fn_unit[12:0] 13'0000010000000
assign $3\trapaddr[12:0] 13'0000001000000
assign $3\traptype[7:0] 8'01000000
- assign { $3\exc_$signal$9[0:0]$3766 $3\exc_$signal$8[0:0]$3765 $3\exc_$signal$7[0:0]$3764 $3\exc_$signal$6[0:0]$3763 $3\exc_$signal$5[0:0]$3762 $3\exc_$signal$4[0:0]$3761 $3\exc_$signal$3[0:0]$3760 $3\exc_$signal[0:0]$3759 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal }
+ assign { $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal }
assign $3\msr[63:0] \cur_msr
assign $3\cia[63:0] \cur_pc
end
assign $2\msr[63:0] $4\msr[63:0]
assign $2\ea_ok[0:0] $4\ea_ok[0:0]
assign $2\ea[6:0] $4\ea[6:0]
- assign $2\cr_out[6:0] $4\cr_out[6:0]
assign $2\asmcode[7:0] $4\asmcode[7:0]
+ assign $2\cr_out[6:0] $4\cr_out[6:0]
assign $2\lk[0:0] $4\lk[0:0]
assign $2\cia[63:0] $4\cia[63:0]
assign $2\cr_in1[6:0] $4\cr_in1[6:0]
assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0]
assign $2\cr_in2[6:0] $4\cr_in2[6:0]
- assign $2\cr_in2$1[6:0]$3747 $4\cr_in2$1[6:0]$3767
+ assign $2\cr_in2$1[6:0]$3700 $4\cr_in2$1[6:0]$3720
assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0]
- assign $2\cr_in2_ok$2[0:0]$3748 $4\cr_in2_ok$2[0:0]$3768
+ assign $2\cr_in2_ok$2[0:0]$3701 $4\cr_in2_ok$2[0:0]$3721
assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0]
assign $2\cr_rd[7:0] $4\cr_rd[7:0]
assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0]
assign $2\cr_wr[7:0] $4\cr_wr[7:0]
assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0]
- assign $2\exc_$signal[0:0]$3749 $4\exc_$signal[0:0]$3769
- assign $2\exc_$signal$3[0:0]$3750 $4\exc_$signal$3[0:0]$3770
- assign $2\exc_$signal$4[0:0]$3751 $4\exc_$signal$4[0:0]$3771
- assign $2\exc_$signal$5[0:0]$3752 $4\exc_$signal$5[0:0]$3772
- assign $2\exc_$signal$6[0:0]$3753 $4\exc_$signal$6[0:0]$3773
- assign $2\exc_$signal$7[0:0]$3754 $4\exc_$signal$7[0:0]$3774
- assign $2\exc_$signal$8[0:0]$3755 $4\exc_$signal$8[0:0]$3775
- assign $2\exc_$signal$9[0:0]$3756 $4\exc_$signal$9[0:0]$3776
+ assign $2\exc_$signal[0:0]$3702 $4\exc_$signal[0:0]$3722
+ assign $2\exc_$signal$3[0:0]$3703 $4\exc_$signal$3[0:0]$3723
+ assign $2\exc_$signal$4[0:0]$3704 $4\exc_$signal$4[0:0]$3724
+ assign $2\exc_$signal$5[0:0]$3705 $4\exc_$signal$5[0:0]$3725
+ assign $2\exc_$signal$6[0:0]$3706 $4\exc_$signal$6[0:0]$3726
+ assign $2\exc_$signal$7[0:0]$3707 $4\exc_$signal$7[0:0]$3727
+ assign $2\exc_$signal$8[0:0]$3708 $4\exc_$signal$8[0:0]$3728
+ assign $2\exc_$signal$9[0:0]$3709 $4\exc_$signal$9[0:0]$3729
assign $2\fasto1[2:0] $4\fasto1[2:0]
assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0]
assign $2\fasto2[2:0] $4\fasto2[2:0]
assign $2\traptype[7:0] $4\traptype[7:0]
assign $2\xer_in[2:0] $4\xer_in[2:0]
assign $2\xer_out[0:0] $4\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1160"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1194"
switch \dec2_exc_$signal$14
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3776 $4\exc_$signal$8[0:0]$3775 $4\exc_$signal$7[0:0]$3774 $4\exc_$signal$6[0:0]$3773 $4\exc_$signal$5[0:0]$3772 $4\exc_$signal$4[0:0]$3771 $4\exc_$signal$3[0:0]$3770 $4\exc_$signal[0:0]$3769 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3768 $4\cr_in2$1[6:0]$3767 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $4\insn[31:0] \dec_opcode_in
assign $4\insn_type[6:0] 7'0111111
assign $4\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3776 $4\exc_$signal$8[0:0]$3775 $4\exc_$signal$7[0:0]$3774 $4\exc_$signal$6[0:0]$3773 $4\exc_$signal$5[0:0]$3772 $4\exc_$signal$4[0:0]$3771 $4\exc_$signal$3[0:0]$3770 $4\exc_$signal[0:0]$3769 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3768 $4\cr_in2$1[6:0]$3767 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $4\insn[31:0] \dec_opcode_in
assign $4\insn_type[6:0] 7'0111111
assign $4\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[12:0] 13'0000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229"
switch \$32
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $5\fasto2[2:0] $1\fasto2[2:0]
assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1238"
switch \$34
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \msr $0\msr[63:0]
update \ea_ok $0\ea_ok[0:0]
update \ea $0\ea[6:0]
- update \cr_out $0\cr_out[6:0]
update \asmcode $0\asmcode[7:0]
+ update \cr_out $0\cr_out[6:0]
update \lk $0\lk[0:0]
update \cia $0\cia[63:0]
update \cr_in1 $0\cr_in1[6:0]
update \cr_in1_ok $0\cr_in1_ok[0:0]
update \cr_in2 $0\cr_in2[6:0]
- update \cr_in2$1 $0\cr_in2$1[6:0]$3727
+ update \cr_in2$1 $0\cr_in2$1[6:0]$3680
update \cr_in2_ok $0\cr_in2_ok[0:0]
- update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3728
+ update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3681
update \cr_out_ok $0\cr_out_ok[0:0]
update \cr_rd $0\cr_rd[7:0]
update \cr_rd_ok $0\cr_rd_ok[0:0]
update \cr_wr $0\cr_wr[7:0]
update \cr_wr_ok $0\cr_wr_ok[0:0]
- update \exc_$signal $0\exc_$signal[0:0]$3729
- update \exc_$signal$3 $0\exc_$signal$3[0:0]$3730
- update \exc_$signal$4 $0\exc_$signal$4[0:0]$3731
- update \exc_$signal$5 $0\exc_$signal$5[0:0]$3732
- update \exc_$signal$6 $0\exc_$signal$6[0:0]$3733
- update \exc_$signal$7 $0\exc_$signal$7[0:0]$3734
- update \exc_$signal$8 $0\exc_$signal$8[0:0]$3735
- update \exc_$signal$9 $0\exc_$signal$9[0:0]$3736
+ update \exc_$signal $0\exc_$signal[0:0]$3682
+ update \exc_$signal$3 $0\exc_$signal$3[0:0]$3683
+ update \exc_$signal$4 $0\exc_$signal$4[0:0]$3684
+ update \exc_$signal$5 $0\exc_$signal$5[0:0]$3685
+ update \exc_$signal$6 $0\exc_$signal$6[0:0]$3686
+ update \exc_$signal$7 $0\exc_$signal$7[0:0]$3687
+ update \exc_$signal$8 $0\exc_$signal$8[0:0]$3688
+ update \exc_$signal$9 $0\exc_$signal$9[0:0]$3689
update \fasto1 $0\fasto1[2:0]
update \fasto1_ok $0\fasto1_ok[0:0]
update \fasto2 $0\fasto2[2:0]
update \xer_in $0\xer_in[2:0]
update \xer_out $0\xer_out[0:0]
end
- attribute \src "libresoc.v:79498.3-79507.6"
- process $proc$libresoc.v:79498$3777
- assign { } { }
- assign { } { }
- assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:79499.5-79499.29"
- switch \initial
- attribute \src "libresoc.v:79499.9-79499.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:857"
- switch \dec_lk
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_tmp_lk[0:0] \dec_LK
- case
- assign $1\tmp_tmp_lk[0:0] 1'0
- end
- sync always
- update \tmp_tmp_lk $0\tmp_tmp_lk[0:0]
- end
- attribute \src "libresoc.v:79508.3-79517.6"
- process $proc$libresoc.v:79508$3778
- assign { } { }
- assign { } { }
- assign $0\cr_a_idx[2:0] $1\cr_a_idx[2:0]
- attribute \src "libresoc.v:79509.5-79509.29"
- switch \initial
- attribute \src "libresoc.v:79509.9-79509.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007"
- switch \$90
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_a_idx[2:0] 3'010
- case
- assign $1\cr_a_idx[2:0] \dec_sv_cr_in
- end
- sync always
- update \cr_a_idx $0\cr_a_idx[2:0]
- end
- attribute \src "libresoc.v:79518.3-79527.6"
- process $proc$libresoc.v:79518$3779
- assign { } { }
- assign { } { }
- assign $0\cr_b_idx[2:0] $1\cr_b_idx[2:0]
- attribute \src "libresoc.v:79519.5-79519.29"
- switch \initial
- attribute \src "libresoc.v:79519.9-79519.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007"
- switch \$92
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\cr_b_idx[2:0] 3'011
- case
- assign $1\cr_b_idx[2:0] 3'000
- end
- sync always
- update \cr_b_idx $0\cr_b_idx[2:0]
- end
- attribute \src "libresoc.v:79528.3-79539.6"
- process $proc$libresoc.v:79528$3780
- assign { } { }
- assign $0\tmp_reg1[6:0] $1\tmp_reg1[6:0]
- attribute \src "libresoc.v:79529.5-79529.29"
- switch \initial
- attribute \src "libresoc.v:79529.9-79529.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046"
- switch \in1_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_reg1[6:0] \$94 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_reg1[6:0] \in1_svdec_reg_out
- end
- sync always
- update \tmp_reg1 $0\tmp_reg1[6:0]
- end
- attribute \src "libresoc.v:79540.3-79551.6"
- process $proc$libresoc.v:79540$3781
- assign { } { }
- assign $0\tmp_reg2[6:0] $1\tmp_reg2[6:0]
- attribute \src "libresoc.v:79541.5-79541.29"
- switch \initial
- attribute \src "libresoc.v:79541.9-79541.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046"
- switch \in2_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_reg2[6:0] \$97 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_reg2[6:0] \in2_svdec_reg_out
- end
- sync always
- update \tmp_reg2 $0\tmp_reg2[6:0]
- end
- attribute \src "libresoc.v:79552.3-79563.6"
- process $proc$libresoc.v:79552$3782
- assign { } { }
- assign $0\tmp_reg3[6:0] $1\tmp_reg3[6:0]
- attribute \src "libresoc.v:79553.5-79553.29"
- switch \initial
- attribute \src "libresoc.v:79553.9-79553.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046"
- switch \in3_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_reg3[6:0] \$100 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_reg3[6:0] \in3_svdec_reg_out
- end
- sync always
- update \tmp_reg3 $0\tmp_reg3[6:0]
- end
- attribute \src "libresoc.v:79564.3-79576.6"
- process $proc$libresoc.v:79564$3783
- assign { } { }
- assign { } { }
- assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0]
- attribute \src "libresoc.v:79565.5-79565.29"
- switch \initial
- attribute \src "libresoc.v:79565.9-79565.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- switch { \$49 \$41 }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\tmp_tmp_insn_type[6:0] 7'0000000
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\tmp_tmp_insn_type[6:0] 7'0000000
- case
- assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op
- end
- sync always
- update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0]
- end
- attribute \src "libresoc.v:79577.3-79588.6"
- process $proc$libresoc.v:79577$3784
- assign { } { }
- assign $0\tmp_rego[6:0] $1\tmp_rego[6:0]
- attribute \src "libresoc.v:79578.5-79578.29"
- switch \initial
- attribute \src "libresoc.v:79578.9-79578.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046"
- switch \o_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_rego[6:0] \$103 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_rego[6:0] \o_svdec_reg_out
- end
- sync always
- update \tmp_rego $0\tmp_rego[6:0]
- end
- attribute \src "libresoc.v:79589.3-79600.6"
- process $proc$libresoc.v:79589$3785
- assign { } { }
- assign $0\tmp_ea[6:0] $1\tmp_ea[6:0]
- attribute \src "libresoc.v:79590.5-79590.29"
- switch \initial
- attribute \src "libresoc.v:79590.9-79590.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046"
- switch \o2_svdec_isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\tmp_ea[6:0] \$106 [6:0]
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\tmp_ea[6:0] \o2_svdec_reg_out
- end
- sync always
- update \tmp_ea $0\tmp_ea[6:0]
- end
- connect \$101 $add$libresoc.v:78885$3647_Y
- connect \$104 $add$libresoc.v:78886$3648_Y
- connect \$107 $add$libresoc.v:78887$3649_Y
- connect \$110 $reduce_or$libresoc.v:78888$3650_Y
- connect \$109 $not$libresoc.v:78889$3651_Y
- connect \$114 $reduce_or$libresoc.v:78890$3652_Y
- connect \$113 $not$libresoc.v:78891$3653_Y
- connect \$117 $eq$libresoc.v:78892$3654_Y
- connect \$119 $eq$libresoc.v:78893$3655_Y
- connect \$122 $add$libresoc.v:78894$3656_Y
- connect \$125 $add$libresoc.v:78895$3657_Y
- connect \$128 $add$libresoc.v:78896$3658_Y
- connect \$130 $eq$libresoc.v:78897$3659_Y
- connect \$132 $eq$libresoc.v:78898$3660_Y
- connect \$135 $add$libresoc.v:78899$3661_Y
- connect \$138 $add$libresoc.v:78900$3662_Y
- connect \$141 $add$libresoc.v:78901$3663_Y
- connect \$143 $eq$libresoc.v:78902$3664_Y
- connect \$145 $eq$libresoc.v:78903$3665_Y
- connect \$148 $add$libresoc.v:78904$3666_Y
- connect \$151 $add$libresoc.v:78905$3667_Y
- connect \$154 $add$libresoc.v:78906$3668_Y
- connect \$156 $eq$libresoc.v:78907$3669_Y
- connect \$158 $eq$libresoc.v:78908$3670_Y
- connect \$161 $add$libresoc.v:78909$3671_Y
- connect \$164 $add$libresoc.v:78910$3672_Y
- connect \$167 $add$libresoc.v:78911$3673_Y
- connect \$169 $eq$libresoc.v:78912$3674_Y
- connect \$171 $eq$libresoc.v:78913$3675_Y
- connect \$173 $eq$libresoc.v:78914$3676_Y
- connect \$175 $eq$libresoc.v:78915$3677_Y
- connect \$177 $and$libresoc.v:78916$3678_Y
- connect \$179 $and$libresoc.v:78917$3679_Y
- connect \$181 $and$libresoc.v:78918$3680_Y
- connect \$183 $eq$libresoc.v:78919$3681_Y
- connect \$28 $eq$libresoc.v:78920$3682_Y
- connect \$30 $eq$libresoc.v:78921$3683_Y
- connect \$32 $or$libresoc.v:78922$3684_Y
- connect \$34 $eq$libresoc.v:78923$3685_Y
- connect \$37 $eq$libresoc.v:78924$3686_Y
- connect \$39 $and$libresoc.v:78925$3687_Y
- connect \$41 $and$libresoc.v:78926$3688_Y
- connect \$43 $eq$libresoc.v:78927$3689_Y
- connect \$45 $and$libresoc.v:78928$3690_Y
- connect \$47 $not$libresoc.v:78929$3691_Y
- connect \$49 $and$libresoc.v:78930$3692_Y
- connect \$51 $eq$libresoc.v:78931$3693_Y
- connect \$53 $eq$libresoc.v:78932$3694_Y
- connect \$55 $or$libresoc.v:78933$3695_Y
- connect \$57 $eq$libresoc.v:78934$3696_Y
- connect \$59 $eq$libresoc.v:78935$3697_Y
- connect \$61 $or$libresoc.v:78936$3698_Y
- connect \$63 $eq$libresoc.v:78937$3699_Y
- connect \$65 $or$libresoc.v:78938$3700_Y
- connect \$67 $eq$libresoc.v:78939$3701_Y
- connect \$69 $or$libresoc.v:78940$3702_Y
- connect \$71 $eq$libresoc.v:78941$3703_Y
- connect \$73 $and$libresoc.v:78942$3704_Y
- connect \$75 $and$libresoc.v:78943$3705_Y
- connect \$77 $eq$libresoc.v:78944$3706_Y
- connect \$79 $and$libresoc.v:78945$3707_Y
- connect \$81 $not$libresoc.v:78946$3708_Y
- connect \$83 $and$libresoc.v:78947$3709_Y
- connect \$90 $eq$libresoc.v:78948$3710_Y
- connect \$92 $eq$libresoc.v:78949$3711_Y
- connect \$95 $add$libresoc.v:78950$3712_Y
- connect \$98 $add$libresoc.v:78951$3713_Y
- connect \$94 \$95
- connect \$97 \$98
- connect \$100 \$101
- connect \$103 \$104
- connect \$106 \$107
- connect \$121 \$122
- connect \$124 \$125
- connect \$127 \$128
- connect \$134 \$135
- connect \$137 \$138
- connect \$140 \$141
- connect \$147 \$148
- connect \$150 \$151
- connect \$153 \$154
- connect \$160 \$161
- connect \$163 \$164
- connect \$166 \$167
+ connect \$100 $pos$libresoc.v:77840$3621_Y
+ connect \$102 $pos$libresoc.v:77841$3623_Y
+ connect \$104 $pos$libresoc.v:77842$3625_Y
+ connect \$106 $eq$libresoc.v:77843$3626_Y
+ connect \$108 $eq$libresoc.v:77844$3627_Y
+ connect \$110 $eq$libresoc.v:77845$3628_Y
+ connect \$112 $eq$libresoc.v:77846$3629_Y
+ connect \$114 $and$libresoc.v:77847$3630_Y
+ connect \$116 $and$libresoc.v:77848$3631_Y
+ connect \$118 $and$libresoc.v:77849$3632_Y
+ connect \$120 $eq$libresoc.v:77850$3633_Y
+ connect \$28 $eq$libresoc.v:77851$3634_Y
+ connect \$30 $eq$libresoc.v:77852$3635_Y
+ connect \$32 $or$libresoc.v:77853$3636_Y
+ connect \$34 $eq$libresoc.v:77854$3637_Y
+ connect \$37 $eq$libresoc.v:77855$3638_Y
+ connect \$39 $and$libresoc.v:77856$3639_Y
+ connect \$41 $and$libresoc.v:77857$3640_Y
+ connect \$43 $eq$libresoc.v:77858$3641_Y
+ connect \$45 $and$libresoc.v:77859$3642_Y
+ connect \$47 $not$libresoc.v:77860$3643_Y
+ connect \$49 $and$libresoc.v:77861$3644_Y
+ connect \$51 $eq$libresoc.v:77862$3645_Y
+ connect \$53 $eq$libresoc.v:77863$3646_Y
+ connect \$55 $or$libresoc.v:77864$3647_Y
+ connect \$57 $eq$libresoc.v:77865$3648_Y
+ connect \$59 $eq$libresoc.v:77866$3649_Y
+ connect \$61 $or$libresoc.v:77867$3650_Y
+ connect \$63 $eq$libresoc.v:77868$3651_Y
+ connect \$65 $or$libresoc.v:77869$3652_Y
+ connect \$67 $eq$libresoc.v:77870$3653_Y
+ connect \$69 $or$libresoc.v:77871$3654_Y
+ connect \$71 $eq$libresoc.v:77872$3655_Y
+ connect \$73 $and$libresoc.v:77873$3656_Y
+ connect \$75 $and$libresoc.v:77874$3657_Y
+ connect \$77 $eq$libresoc.v:77875$3658_Y
+ connect \$79 $and$libresoc.v:77876$3659_Y
+ connect \$81 $not$libresoc.v:77877$3660_Y
+ connect \$83 $and$libresoc.v:77878$3661_Y
+ connect \$90 $pos$libresoc.v:77879$3663_Y
+ connect \$92 $pos$libresoc.v:77880$3665_Y
+ connect \$94 $pos$libresoc.v:77881$3667_Y
+ connect \$96 $pos$libresoc.v:77882$3669_Y
+ connect \$98 $pos$libresoc.v:77883$3671_Y
connect \dec2_exc_$signal 1'0
connect \dec2_exc_$signal$12 1'0
connect \dec2_exc_$signal$13 1'0
connect \tmp_tmp_exc_$signal$25 1'0
connect \tmp_tmp_exc_$signal$26 1'0
connect \tmp_tmp_exc_$signal$27 1'0
- connect \illeg_ok \$183
- connect \priv_ok \$181
- connect \dec_irq_ok \$179
- connect \ext_irq_ok \$177
- connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok
- connect \crout_svdec_cr_in \dec_cr_out_cr_bitfield
- connect \crout_svdec_etype \dec_SV_Etype
- connect \crout_svdec_extra \dec_svp64__extra
- connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok
- connect \crin_svdec_o_cr_in \dec_cr_in_cr_bitfield_o
- connect \crin_svdec_o_etype \dec_SV_Etype
- connect \crin_svdec_o_extra \dec_svp64__extra
- connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok
- connect \crin_svdec_b_cr_in \dec_cr_in_cr_bitfield_b
- connect \crin_svdec_b_etype \dec_SV_Etype
- connect \crin_svdec_b_extra \dec_svp64__extra
- connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok
- connect \crin_svdec_cr_in \dec_cr_in_cr_bitfield
- connect \crin_svdec_etype \dec_SV_Etype
- connect \crin_svdec_extra \dec_svp64__extra
+ connect \illeg_ok \$120
+ connect \priv_ok \$118
+ connect \dec_irq_ok \$116
+ connect \ext_irq_ok \$114
connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o2_ok \dec_o2_fast_o2 }
connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o }
connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b }
connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a }
connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o }
connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a }
- connect \no_out_vec \$113
- connect \no_in_vec \$109
- connect \reg_o2_isvec \o2_svdec_isvec
- connect \reg_o_isvec \o_svdec_isvec
- connect \reg_c_isvec \in3_svdec_isvec
- connect \reg_b_isvec \in2_svdec_isvec
- connect \reg_a_isvec \in1_svdec_isvec
- connect \o_svdec_idx \dec_sv_out
- connect \in3_svdec_idx \dec_sv_in3
- connect \in2_svdec_idx \dec_sv_in2
- connect \in1_svdec_idx \dec_sv_in1
+ connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok
+ connect \tmp_cr_out \$104
+ connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok
+ connect \tmp_cr_in2$19 \$102
+ connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok
+ connect \tmp_cr_in2 \$100
+ connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok
+ connect \tmp_cr_in1 \$98
connect \tmp_ea_ok \dec_o2_reg_o2_ok
- connect \o2_svdec_reg_in \dec_o2_reg_o2
- connect \o2_svdec_etype \dec_SV_Etype
- connect \o2_svdec_extra \dec_svp64__extra
+ connect \tmp_ea \$96
connect \tmp_rego_ok \dec_o_reg_o_ok
- connect \o_svdec_reg_in \dec_o_reg_o
- connect \o_svdec_etype \dec_SV_Etype
- connect \o_svdec_extra \dec_svp64__extra
+ connect \tmp_rego \$94
connect \tmp_reg3_ok \dec_c_reg_c_ok
- connect \in3_svdec_reg_in \dec_c_reg_c
- connect \in3_svdec_etype \dec_SV_Etype
- connect \in3_svdec_extra \dec_svp64__extra
+ connect \tmp_reg3 \$92
connect \tmp_reg2_ok \dec_b_reg_b_ok
- connect \in2_svdec_reg_in \dec_b_reg_b [4:0]
- connect \in2_svdec_etype \dec_SV_Etype
- connect \in2_svdec_extra \dec_svp64__extra
+ connect \tmp_reg2 \dec_b_reg_b
connect \tmp_reg1_ok \dec_a_reg_a_ok
- connect \in1_svdec_reg_in \dec_a_reg_a
- connect \in1_svdec_etype \dec_SV_Etype
- connect \in1_svdec_extra \dec_svp64__extra
- connect \srcstep \cur_cur_srcstep
+ connect \tmp_reg1 \$90
connect \dec_o2_lk \tmp_tmp_lk
connect \sel_in \dec_out_sel
connect \dec_o_sel_in \dec_out_sel
connect \dec_c_sel_in \dec_in3_sel
connect \dec_b_sel_in \dec_in2_sel
connect \dec_a_sel_in \dec_in1_sel
- connect \crin_svdec_o_idx \dec_sv_cr_out
- connect \crin_svdec_b_idx \cr_b_idx
- connect \crin_svdec_idx \cr_a_idx
- connect \cr_in_o_isvec \crin_svdec_o_isvec
- connect \cr_in_b_isvec \crin_svdec_b_isvec
- connect \cr_in_isvec \crin_svdec_isvec
- connect \cr_out_isvec \crout_svdec_isvec
- connect \crout_svdec_idx \dec_sv_cr_out
connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm }
connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm }
connect \dec_cr_out_rc_in \dec_rc_rc
connect \insn_in$36 \dec_opcode_in
connect \insn_in \dec_opcode_in
end
-attribute \src "libresoc.v:79738.1-81259.10"
+attribute \src "libresoc.v:78363.1-79884.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30"
attribute \generator "nMigen"
module \dec30
- attribute \src "libresoc.v:81036.3-81072.6"
+ attribute \src "libresoc.v:79661.3-79697.6"
wire width 2 $0\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81073.3-81109.6"
+ attribute \src "libresoc.v:79698.3-79734.6"
wire width 2 $0\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:80592.3-80628.6"
+ attribute \src "libresoc.v:79217.3-79253.6"
wire width 8 $0\dec30_asmcode[7:0]
- attribute \src "libresoc.v:80740.3-80776.6"
+ attribute \src "libresoc.v:79365.3-79401.6"
wire $0\dec30_br[0:0]
- attribute \src "libresoc.v:80111.3-80147.6"
+ attribute \src "libresoc.v:78736.3-78772.6"
wire width 3 $0\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80148.3-80184.6"
+ attribute \src "libresoc.v:78773.3-78809.6"
wire width 3 $0\dec30_cr_out[2:0]
- attribute \src "libresoc.v:80555.3-80591.6"
+ attribute \src "libresoc.v:79180.3-79216.6"
wire width 2 $0\dec30_cry_in[1:0]
- attribute \src "libresoc.v:80703.3-80739.6"
+ attribute \src "libresoc.v:79328.3-79364.6"
wire $0\dec30_cry_out[0:0]
- attribute \src "libresoc.v:80888.3-80924.6"
+ attribute \src "libresoc.v:79513.3-79549.6"
wire width 5 $0\dec30_form[4:0]
- attribute \src "libresoc.v:80074.3-80110.6"
+ attribute \src "libresoc.v:78699.3-78735.6"
wire width 13 $0\dec30_function_unit[12:0]
- attribute \src "libresoc.v:81110.3-81146.6"
+ attribute \src "libresoc.v:79735.3-79771.6"
wire width 3 $0\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81147.3-81183.6"
+ attribute \src "libresoc.v:79772.3-79808.6"
wire width 4 $0\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81184.3-81220.6"
+ attribute \src "libresoc.v:79809.3-79845.6"
wire width 2 $0\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:80481.3-80517.6"
+ attribute \src "libresoc.v:79106.3-79142.6"
wire width 7 $0\dec30_internal_op[6:0]
- attribute \src "libresoc.v:80629.3-80665.6"
+ attribute \src "libresoc.v:79254.3-79290.6"
wire $0\dec30_inv_a[0:0]
- attribute \src "libresoc.v:80666.3-80702.6"
+ attribute \src "libresoc.v:79291.3-79327.6"
wire $0\dec30_inv_out[0:0]
- attribute \src "libresoc.v:80851.3-80887.6"
+ attribute \src "libresoc.v:79476.3-79512.6"
wire $0\dec30_is_32b[0:0]
- attribute \src "libresoc.v:80407.3-80443.6"
+ attribute \src "libresoc.v:79032.3-79068.6"
wire width 4 $0\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:80962.3-80998.6"
+ attribute \src "libresoc.v:79587.3-79623.6"
wire $0\dec30_lk[0:0]
- attribute \src "libresoc.v:81221.3-81257.6"
+ attribute \src "libresoc.v:79846.3-79882.6"
wire width 2 $0\dec30_out_sel[1:0]
- attribute \src "libresoc.v:80518.3-80554.6"
+ attribute \src "libresoc.v:79143.3-79179.6"
wire width 2 $0\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:80814.3-80850.6"
+ attribute \src "libresoc.v:79439.3-79475.6"
wire $0\dec30_rsrv[0:0]
- attribute \src "libresoc.v:80999.3-81035.6"
+ attribute \src "libresoc.v:79624.3-79660.6"
wire $0\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:80925.3-80961.6"
+ attribute \src "libresoc.v:79550.3-79586.6"
wire $0\dec30_sgn[0:0]
- attribute \src "libresoc.v:80777.3-80813.6"
+ attribute \src "libresoc.v:79402.3-79438.6"
wire $0\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:80333.3-80369.6"
+ attribute \src "libresoc.v:78958.3-78994.6"
wire width 3 $0\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80370.3-80406.6"
+ attribute \src "libresoc.v:78995.3-79031.6"
wire width 3 $0\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80185.3-80221.6"
+ attribute \src "libresoc.v:78810.3-78846.6"
wire width 3 $0\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80222.3-80258.6"
+ attribute \src "libresoc.v:78847.3-78883.6"
wire width 3 $0\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80259.3-80295.6"
+ attribute \src "libresoc.v:78884.3-78920.6"
wire width 3 $0\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80296.3-80332.6"
+ attribute \src "libresoc.v:78921.3-78957.6"
wire width 3 $0\dec30_sv_out[2:0]
- attribute \src "libresoc.v:80444.3-80480.6"
+ attribute \src "libresoc.v:79069.3-79105.6"
wire width 2 $0\dec30_upd[1:0]
- attribute \src "libresoc.v:79739.7-79739.20"
+ attribute \src "libresoc.v:78364.7-78364.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:81036.3-81072.6"
+ attribute \src "libresoc.v:79661.3-79697.6"
wire width 2 $1\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81073.3-81109.6"
+ attribute \src "libresoc.v:79698.3-79734.6"
wire width 2 $1\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:80592.3-80628.6"
+ attribute \src "libresoc.v:79217.3-79253.6"
wire width 8 $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:80740.3-80776.6"
+ attribute \src "libresoc.v:79365.3-79401.6"
wire $1\dec30_br[0:0]
- attribute \src "libresoc.v:80111.3-80147.6"
+ attribute \src "libresoc.v:78736.3-78772.6"
wire width 3 $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80148.3-80184.6"
+ attribute \src "libresoc.v:78773.3-78809.6"
wire width 3 $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:80555.3-80591.6"
+ attribute \src "libresoc.v:79180.3-79216.6"
wire width 2 $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:80703.3-80739.6"
+ attribute \src "libresoc.v:79328.3-79364.6"
wire $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:80888.3-80924.6"
+ attribute \src "libresoc.v:79513.3-79549.6"
wire width 5 $1\dec30_form[4:0]
- attribute \src "libresoc.v:80074.3-80110.6"
+ attribute \src "libresoc.v:78699.3-78735.6"
wire width 13 $1\dec30_function_unit[12:0]
- attribute \src "libresoc.v:81110.3-81146.6"
+ attribute \src "libresoc.v:79735.3-79771.6"
wire width 3 $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81147.3-81183.6"
+ attribute \src "libresoc.v:79772.3-79808.6"
wire width 4 $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81184.3-81220.6"
+ attribute \src "libresoc.v:79809.3-79845.6"
wire width 2 $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:80481.3-80517.6"
+ attribute \src "libresoc.v:79106.3-79142.6"
wire width 7 $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:80629.3-80665.6"
+ attribute \src "libresoc.v:79254.3-79290.6"
wire $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:80666.3-80702.6"
+ attribute \src "libresoc.v:79291.3-79327.6"
wire $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:80851.3-80887.6"
+ attribute \src "libresoc.v:79476.3-79512.6"
wire $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:80407.3-80443.6"
+ attribute \src "libresoc.v:79032.3-79068.6"
wire width 4 $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:80962.3-80998.6"
+ attribute \src "libresoc.v:79587.3-79623.6"
wire $1\dec30_lk[0:0]
- attribute \src "libresoc.v:81221.3-81257.6"
+ attribute \src "libresoc.v:79846.3-79882.6"
wire width 2 $1\dec30_out_sel[1:0]
- attribute \src "libresoc.v:80518.3-80554.6"
+ attribute \src "libresoc.v:79143.3-79179.6"
wire width 2 $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:80814.3-80850.6"
+ attribute \src "libresoc.v:79439.3-79475.6"
wire $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:80999.3-81035.6"
+ attribute \src "libresoc.v:79624.3-79660.6"
wire $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:80925.3-80961.6"
+ attribute \src "libresoc.v:79550.3-79586.6"
wire $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:80777.3-80813.6"
+ attribute \src "libresoc.v:79402.3-79438.6"
wire $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:80333.3-80369.6"
+ attribute \src "libresoc.v:78958.3-78994.6"
wire width 3 $1\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80370.3-80406.6"
+ attribute \src "libresoc.v:78995.3-79031.6"
wire width 3 $1\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80185.3-80221.6"
+ attribute \src "libresoc.v:78810.3-78846.6"
wire width 3 $1\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80222.3-80258.6"
+ attribute \src "libresoc.v:78847.3-78883.6"
wire width 3 $1\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80259.3-80295.6"
+ attribute \src "libresoc.v:78884.3-78920.6"
wire width 3 $1\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80296.3-80332.6"
+ attribute \src "libresoc.v:78921.3-78957.6"
wire width 3 $1\dec30_sv_out[2:0]
- attribute \src "libresoc.v:80444.3-80480.6"
+ attribute \src "libresoc.v:79069.3-79105.6"
wire width 2 $1\dec30_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec30_upd
- attribute \src "libresoc.v:79739.7-79739.15"
+ attribute \src "libresoc.v:78364.7-78364.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 4 \opcode_switch
- attribute \src "libresoc.v:79739.7-79739.20"
- process $proc$libresoc.v:79739$3819
+ attribute \src "libresoc.v:78364.7-78364.20"
+ process $proc$libresoc.v:78364$3763
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:80074.3-80110.6"
- process $proc$libresoc.v:80074$3787
+ attribute \src "libresoc.v:78699.3-78735.6"
+ process $proc$libresoc.v:78699$3731
assign { } { }
assign { } { }
assign $0\dec30_function_unit[12:0] $1\dec30_function_unit[12:0]
- attribute \src "libresoc.v:80075.5-80075.29"
+ attribute \src "libresoc.v:78700.5-78700.29"
switch \initial
- attribute \src "libresoc.v:80075.9-80075.17"
+ attribute \src "libresoc.v:78700.9-78700.17"
case 1'1
case
end
sync always
update \dec30_function_unit $0\dec30_function_unit[12:0]
end
- attribute \src "libresoc.v:80111.3-80147.6"
- process $proc$libresoc.v:80111$3788
+ attribute \src "libresoc.v:78736.3-78772.6"
+ process $proc$libresoc.v:78736$3732
assign { } { }
assign { } { }
assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:80112.5-80112.29"
+ attribute \src "libresoc.v:78737.5-78737.29"
switch \initial
- attribute \src "libresoc.v:80112.9-80112.17"
+ attribute \src "libresoc.v:78737.9-78737.17"
case 1'1
case
end
sync always
update \dec30_cr_in $0\dec30_cr_in[2:0]
end
- attribute \src "libresoc.v:80148.3-80184.6"
- process $proc$libresoc.v:80148$3789
+ attribute \src "libresoc.v:78773.3-78809.6"
+ process $proc$libresoc.v:78773$3733
assign { } { }
assign { } { }
assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:80149.5-80149.29"
+ attribute \src "libresoc.v:78774.5-78774.29"
switch \initial
- attribute \src "libresoc.v:80149.9-80149.17"
+ attribute \src "libresoc.v:78774.9-78774.17"
case 1'1
case
end
sync always
update \dec30_cr_out $0\dec30_cr_out[2:0]
end
- attribute \src "libresoc.v:80185.3-80221.6"
- process $proc$libresoc.v:80185$3790
+ attribute \src "libresoc.v:78810.3-78846.6"
+ process $proc$libresoc.v:78810$3734
assign { } { }
assign { } { }
assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0]
- attribute \src "libresoc.v:80186.5-80186.29"
+ attribute \src "libresoc.v:78811.5-78811.29"
switch \initial
- attribute \src "libresoc.v:80186.9-80186.17"
+ attribute \src "libresoc.v:78811.9-78811.17"
case 1'1
case
end
sync always
update \dec30_sv_in1 $0\dec30_sv_in1[2:0]
end
- attribute \src "libresoc.v:80222.3-80258.6"
- process $proc$libresoc.v:80222$3791
+ attribute \src "libresoc.v:78847.3-78883.6"
+ process $proc$libresoc.v:78847$3735
assign { } { }
assign { } { }
assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0]
- attribute \src "libresoc.v:80223.5-80223.29"
+ attribute \src "libresoc.v:78848.5-78848.29"
switch \initial
- attribute \src "libresoc.v:80223.9-80223.17"
+ attribute \src "libresoc.v:78848.9-78848.17"
case 1'1
case
end
sync always
update \dec30_sv_in2 $0\dec30_sv_in2[2:0]
end
- attribute \src "libresoc.v:80259.3-80295.6"
- process $proc$libresoc.v:80259$3792
+ attribute \src "libresoc.v:78884.3-78920.6"
+ process $proc$libresoc.v:78884$3736
assign { } { }
assign { } { }
assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0]
- attribute \src "libresoc.v:80260.5-80260.29"
+ attribute \src "libresoc.v:78885.5-78885.29"
switch \initial
- attribute \src "libresoc.v:80260.9-80260.17"
+ attribute \src "libresoc.v:78885.9-78885.17"
case 1'1
case
end
sync always
update \dec30_sv_in3 $0\dec30_sv_in3[2:0]
end
- attribute \src "libresoc.v:80296.3-80332.6"
- process $proc$libresoc.v:80296$3793
+ attribute \src "libresoc.v:78921.3-78957.6"
+ process $proc$libresoc.v:78921$3737
assign { } { }
assign { } { }
assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0]
- attribute \src "libresoc.v:80297.5-80297.29"
+ attribute \src "libresoc.v:78922.5-78922.29"
switch \initial
- attribute \src "libresoc.v:80297.9-80297.17"
+ attribute \src "libresoc.v:78922.9-78922.17"
case 1'1
case
end
sync always
update \dec30_sv_out $0\dec30_sv_out[2:0]
end
- attribute \src "libresoc.v:80333.3-80369.6"
- process $proc$libresoc.v:80333$3794
+ attribute \src "libresoc.v:78958.3-78994.6"
+ process $proc$libresoc.v:78958$3738
assign { } { }
assign { } { }
assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0]
- attribute \src "libresoc.v:80334.5-80334.29"
+ attribute \src "libresoc.v:78959.5-78959.29"
switch \initial
- attribute \src "libresoc.v:80334.9-80334.17"
+ attribute \src "libresoc.v:78959.9-78959.17"
case 1'1
case
end
sync always
update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:80370.3-80406.6"
- process $proc$libresoc.v:80370$3795
+ attribute \src "libresoc.v:78995.3-79031.6"
+ process $proc$libresoc.v:78995$3739
assign { } { }
assign { } { }
assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0]
- attribute \src "libresoc.v:80371.5-80371.29"
+ attribute \src "libresoc.v:78996.5-78996.29"
switch \initial
- attribute \src "libresoc.v:80371.9-80371.17"
+ attribute \src "libresoc.v:78996.9-78996.17"
case 1'1
case
end
sync always
update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:80407.3-80443.6"
- process $proc$libresoc.v:80407$3796
+ attribute \src "libresoc.v:79032.3-79068.6"
+ process $proc$libresoc.v:79032$3740
assign { } { }
assign { } { }
assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:80408.5-80408.29"
+ attribute \src "libresoc.v:79033.5-79033.29"
switch \initial
- attribute \src "libresoc.v:80408.9-80408.17"
+ attribute \src "libresoc.v:79033.9-79033.17"
case 1'1
case
end
sync always
update \dec30_ldst_len $0\dec30_ldst_len[3:0]
end
- attribute \src "libresoc.v:80444.3-80480.6"
- process $proc$libresoc.v:80444$3797
+ attribute \src "libresoc.v:79069.3-79105.6"
+ process $proc$libresoc.v:79069$3741
assign { } { }
assign { } { }
assign $0\dec30_upd[1:0] $1\dec30_upd[1:0]
- attribute \src "libresoc.v:80445.5-80445.29"
+ attribute \src "libresoc.v:79070.5-79070.29"
switch \initial
- attribute \src "libresoc.v:80445.9-80445.17"
+ attribute \src "libresoc.v:79070.9-79070.17"
case 1'1
case
end
sync always
update \dec30_upd $0\dec30_upd[1:0]
end
- attribute \src "libresoc.v:80481.3-80517.6"
- process $proc$libresoc.v:80481$3798
+ attribute \src "libresoc.v:79106.3-79142.6"
+ process $proc$libresoc.v:79106$3742
assign { } { }
assign { } { }
assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:80482.5-80482.29"
+ attribute \src "libresoc.v:79107.5-79107.29"
switch \initial
- attribute \src "libresoc.v:80482.9-80482.17"
+ attribute \src "libresoc.v:79107.9-79107.17"
case 1'1
case
end
sync always
update \dec30_internal_op $0\dec30_internal_op[6:0]
end
- attribute \src "libresoc.v:80518.3-80554.6"
- process $proc$libresoc.v:80518$3799
+ attribute \src "libresoc.v:79143.3-79179.6"
+ process $proc$libresoc.v:79143$3743
assign { } { }
assign { } { }
assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:80519.5-80519.29"
+ attribute \src "libresoc.v:79144.5-79144.29"
switch \initial
- attribute \src "libresoc.v:80519.9-80519.17"
+ attribute \src "libresoc.v:79144.9-79144.17"
case 1'1
case
end
sync always
update \dec30_rc_sel $0\dec30_rc_sel[1:0]
end
- attribute \src "libresoc.v:80555.3-80591.6"
- process $proc$libresoc.v:80555$3800
+ attribute \src "libresoc.v:79180.3-79216.6"
+ process $proc$libresoc.v:79180$3744
assign { } { }
assign { } { }
assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:80556.5-80556.29"
+ attribute \src "libresoc.v:79181.5-79181.29"
switch \initial
- attribute \src "libresoc.v:80556.9-80556.17"
+ attribute \src "libresoc.v:79181.9-79181.17"
case 1'1
case
end
sync always
update \dec30_cry_in $0\dec30_cry_in[1:0]
end
- attribute \src "libresoc.v:80592.3-80628.6"
- process $proc$libresoc.v:80592$3801
+ attribute \src "libresoc.v:79217.3-79253.6"
+ process $proc$libresoc.v:79217$3745
assign { } { }
assign { } { }
assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:80593.5-80593.29"
+ attribute \src "libresoc.v:79218.5-79218.29"
switch \initial
- attribute \src "libresoc.v:80593.9-80593.17"
+ attribute \src "libresoc.v:79218.9-79218.17"
case 1'1
case
end
sync always
update \dec30_asmcode $0\dec30_asmcode[7:0]
end
- attribute \src "libresoc.v:80629.3-80665.6"
- process $proc$libresoc.v:80629$3802
+ attribute \src "libresoc.v:79254.3-79290.6"
+ process $proc$libresoc.v:79254$3746
assign { } { }
assign { } { }
assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:80630.5-80630.29"
+ attribute \src "libresoc.v:79255.5-79255.29"
switch \initial
- attribute \src "libresoc.v:80630.9-80630.17"
+ attribute \src "libresoc.v:79255.9-79255.17"
case 1'1
case
end
sync always
update \dec30_inv_a $0\dec30_inv_a[0:0]
end
- attribute \src "libresoc.v:80666.3-80702.6"
- process $proc$libresoc.v:80666$3803
+ attribute \src "libresoc.v:79291.3-79327.6"
+ process $proc$libresoc.v:79291$3747
assign { } { }
assign { } { }
assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:80667.5-80667.29"
+ attribute \src "libresoc.v:79292.5-79292.29"
switch \initial
- attribute \src "libresoc.v:80667.9-80667.17"
+ attribute \src "libresoc.v:79292.9-79292.17"
case 1'1
case
end
sync always
update \dec30_inv_out $0\dec30_inv_out[0:0]
end
- attribute \src "libresoc.v:80703.3-80739.6"
- process $proc$libresoc.v:80703$3804
+ attribute \src "libresoc.v:79328.3-79364.6"
+ process $proc$libresoc.v:79328$3748
assign { } { }
assign { } { }
assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:80704.5-80704.29"
+ attribute \src "libresoc.v:79329.5-79329.29"
switch \initial
- attribute \src "libresoc.v:80704.9-80704.17"
+ attribute \src "libresoc.v:79329.9-79329.17"
case 1'1
case
end
sync always
update \dec30_cry_out $0\dec30_cry_out[0:0]
end
- attribute \src "libresoc.v:80740.3-80776.6"
- process $proc$libresoc.v:80740$3805
+ attribute \src "libresoc.v:79365.3-79401.6"
+ process $proc$libresoc.v:79365$3749
assign { } { }
assign { } { }
assign $0\dec30_br[0:0] $1\dec30_br[0:0]
- attribute \src "libresoc.v:80741.5-80741.29"
+ attribute \src "libresoc.v:79366.5-79366.29"
switch \initial
- attribute \src "libresoc.v:80741.9-80741.17"
+ attribute \src "libresoc.v:79366.9-79366.17"
case 1'1
case
end
sync always
update \dec30_br $0\dec30_br[0:0]
end
- attribute \src "libresoc.v:80777.3-80813.6"
- process $proc$libresoc.v:80777$3806
+ attribute \src "libresoc.v:79402.3-79438.6"
+ process $proc$libresoc.v:79402$3750
assign { } { }
assign { } { }
assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:80778.5-80778.29"
+ attribute \src "libresoc.v:79403.5-79403.29"
switch \initial
- attribute \src "libresoc.v:80778.9-80778.17"
+ attribute \src "libresoc.v:79403.9-79403.17"
case 1'1
case
end
sync always
update \dec30_sgn_ext $0\dec30_sgn_ext[0:0]
end
- attribute \src "libresoc.v:80814.3-80850.6"
- process $proc$libresoc.v:80814$3807
+ attribute \src "libresoc.v:79439.3-79475.6"
+ process $proc$libresoc.v:79439$3751
assign { } { }
assign { } { }
assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:80815.5-80815.29"
+ attribute \src "libresoc.v:79440.5-79440.29"
switch \initial
- attribute \src "libresoc.v:80815.9-80815.17"
+ attribute \src "libresoc.v:79440.9-79440.17"
case 1'1
case
end
sync always
update \dec30_rsrv $0\dec30_rsrv[0:0]
end
- attribute \src "libresoc.v:80851.3-80887.6"
- process $proc$libresoc.v:80851$3808
+ attribute \src "libresoc.v:79476.3-79512.6"
+ process $proc$libresoc.v:79476$3752
assign { } { }
assign { } { }
assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:80852.5-80852.29"
+ attribute \src "libresoc.v:79477.5-79477.29"
switch \initial
- attribute \src "libresoc.v:80852.9-80852.17"
+ attribute \src "libresoc.v:79477.9-79477.17"
case 1'1
case
end
sync always
update \dec30_is_32b $0\dec30_is_32b[0:0]
end
- attribute \src "libresoc.v:80888.3-80924.6"
- process $proc$libresoc.v:80888$3809
+ attribute \src "libresoc.v:79513.3-79549.6"
+ process $proc$libresoc.v:79513$3753
assign { } { }
assign { } { }
assign $0\dec30_form[4:0] $1\dec30_form[4:0]
- attribute \src "libresoc.v:80889.5-80889.29"
+ attribute \src "libresoc.v:79514.5-79514.29"
switch \initial
- attribute \src "libresoc.v:80889.9-80889.17"
+ attribute \src "libresoc.v:79514.9-79514.17"
case 1'1
case
end
sync always
update \dec30_form $0\dec30_form[4:0]
end
- attribute \src "libresoc.v:80925.3-80961.6"
- process $proc$libresoc.v:80925$3810
+ attribute \src "libresoc.v:79550.3-79586.6"
+ process $proc$libresoc.v:79550$3754
assign { } { }
assign { } { }
assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:80926.5-80926.29"
+ attribute \src "libresoc.v:79551.5-79551.29"
switch \initial
- attribute \src "libresoc.v:80926.9-80926.17"
+ attribute \src "libresoc.v:79551.9-79551.17"
case 1'1
case
end
sync always
update \dec30_sgn $0\dec30_sgn[0:0]
end
- attribute \src "libresoc.v:80962.3-80998.6"
- process $proc$libresoc.v:80962$3811
+ attribute \src "libresoc.v:79587.3-79623.6"
+ process $proc$libresoc.v:79587$3755
assign { } { }
assign { } { }
assign $0\dec30_lk[0:0] $1\dec30_lk[0:0]
- attribute \src "libresoc.v:80963.5-80963.29"
+ attribute \src "libresoc.v:79588.5-79588.29"
switch \initial
- attribute \src "libresoc.v:80963.9-80963.17"
+ attribute \src "libresoc.v:79588.9-79588.17"
case 1'1
case
end
sync always
update \dec30_lk $0\dec30_lk[0:0]
end
- attribute \src "libresoc.v:80999.3-81035.6"
- process $proc$libresoc.v:80999$3812
+ attribute \src "libresoc.v:79624.3-79660.6"
+ process $proc$libresoc.v:79624$3756
assign { } { }
assign { } { }
assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:81000.5-81000.29"
+ attribute \src "libresoc.v:79625.5-79625.29"
switch \initial
- attribute \src "libresoc.v:81000.9-81000.17"
+ attribute \src "libresoc.v:79625.9-79625.17"
case 1'1
case
end
sync always
update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:81036.3-81072.6"
- process $proc$libresoc.v:81036$3813
+ attribute \src "libresoc.v:79661.3-79697.6"
+ process $proc$libresoc.v:79661$3757
assign { } { }
assign { } { }
assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0]
- attribute \src "libresoc.v:81037.5-81037.29"
+ attribute \src "libresoc.v:79662.5-79662.29"
switch \initial
- attribute \src "libresoc.v:81037.9-81037.17"
+ attribute \src "libresoc.v:79662.9-79662.17"
case 1'1
case
end
sync always
update \dec30_SV_Etype $0\dec30_SV_Etype[1:0]
end
- attribute \src "libresoc.v:81073.3-81109.6"
- process $proc$libresoc.v:81073$3814
+ attribute \src "libresoc.v:79698.3-79734.6"
+ process $proc$libresoc.v:79698$3758
assign { } { }
assign { } { }
assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0]
- attribute \src "libresoc.v:81074.5-81074.29"
+ attribute \src "libresoc.v:79699.5-79699.29"
switch \initial
- attribute \src "libresoc.v:81074.9-81074.17"
+ attribute \src "libresoc.v:79699.9-79699.17"
case 1'1
case
end
sync always
update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:81110.3-81146.6"
- process $proc$libresoc.v:81110$3815
+ attribute \src "libresoc.v:79735.3-79771.6"
+ process $proc$libresoc.v:79735$3759
assign { } { }
assign { } { }
assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:81111.5-81111.29"
+ attribute \src "libresoc.v:79736.5-79736.29"
switch \initial
- attribute \src "libresoc.v:81111.9-81111.17"
+ attribute \src "libresoc.v:79736.9-79736.17"
case 1'1
case
end
sync always
update \dec30_in1_sel $0\dec30_in1_sel[2:0]
end
- attribute \src "libresoc.v:81147.3-81183.6"
- process $proc$libresoc.v:81147$3816
+ attribute \src "libresoc.v:79772.3-79808.6"
+ process $proc$libresoc.v:79772$3760
assign { } { }
assign { } { }
assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:81148.5-81148.29"
+ attribute \src "libresoc.v:79773.5-79773.29"
switch \initial
- attribute \src "libresoc.v:81148.9-81148.17"
+ attribute \src "libresoc.v:79773.9-79773.17"
case 1'1
case
end
sync always
update \dec30_in2_sel $0\dec30_in2_sel[3:0]
end
- attribute \src "libresoc.v:81184.3-81220.6"
- process $proc$libresoc.v:81184$3817
+ attribute \src "libresoc.v:79809.3-79845.6"
+ process $proc$libresoc.v:79809$3761
assign { } { }
assign { } { }
assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:81185.5-81185.29"
+ attribute \src "libresoc.v:79810.5-79810.29"
switch \initial
- attribute \src "libresoc.v:81185.9-81185.17"
+ attribute \src "libresoc.v:79810.9-79810.17"
case 1'1
case
end
sync always
update \dec30_in3_sel $0\dec30_in3_sel[1:0]
end
- attribute \src "libresoc.v:81221.3-81257.6"
- process $proc$libresoc.v:81221$3818
+ attribute \src "libresoc.v:79846.3-79882.6"
+ process $proc$libresoc.v:79846$3762
assign { } { }
assign { } { }
assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0]
- attribute \src "libresoc.v:81222.5-81222.29"
+ attribute \src "libresoc.v:79847.5-79847.29"
switch \initial
- attribute \src "libresoc.v:81222.9-81222.17"
+ attribute \src "libresoc.v:79847.9-79847.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [4:1]
end
-attribute \src "libresoc.v:81263.1-89603.10"
+attribute \src "libresoc.v:79888.1-88228.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31"
attribute \generator "nMigen"
module \dec31
- attribute \src "libresoc.v:87875.3-87935.6"
+ attribute \src "libresoc.v:86500.3-86560.6"
wire width 2 $0\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:87936.3-87996.6"
+ attribute \src "libresoc.v:86561.3-86621.6"
wire width 2 $0\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:87814.3-87874.6"
+ attribute \src "libresoc.v:86439.3-86499.6"
wire width 8 $0\dec31_asmcode[7:0]
- attribute \src "libresoc.v:89156.3-89216.6"
+ attribute \src "libresoc.v:87781.3-87841.6"
wire $0\dec31_br[0:0]
- attribute \src "libresoc.v:88241.3-88301.6"
+ attribute \src "libresoc.v:86866.3-86926.6"
wire width 3 $0\dec31_cr_in[2:0]
- attribute \src "libresoc.v:88302.3-88362.6"
+ attribute \src "libresoc.v:86927.3-86987.6"
wire width 3 $0\dec31_cr_out[2:0]
- attribute \src "libresoc.v:88912.3-88972.6"
+ attribute \src "libresoc.v:87537.3-87597.6"
wire width 2 $0\dec31_cry_in[1:0]
- attribute \src "libresoc.v:89095.3-89155.6"
+ attribute \src "libresoc.v:87720.3-87780.6"
wire $0\dec31_cry_out[0:0]
- attribute \src "libresoc.v:87753.3-87813.6"
+ attribute \src "libresoc.v:86378.3-86438.6"
wire width 5 $0\dec31_form[4:0]
- attribute \src "libresoc.v:87631.3-87691.6"
+ attribute \src "libresoc.v:86256.3-86316.6"
wire width 13 $0\dec31_function_unit[12:0]
- attribute \src "libresoc.v:87997.3-88057.6"
+ attribute \src "libresoc.v:86622.3-86682.6"
wire width 3 $0\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:88058.3-88118.6"
+ attribute \src "libresoc.v:86683.3-86743.6"
wire width 4 $0\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88119.3-88179.6"
+ attribute \src "libresoc.v:86744.3-86804.6"
wire width 2 $0\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:87692.3-87752.6"
+ attribute \src "libresoc.v:86317.3-86377.6"
wire width 7 $0\dec31_internal_op[6:0]
- attribute \src "libresoc.v:88973.3-89033.6"
+ attribute \src "libresoc.v:87598.3-87658.6"
wire $0\dec31_inv_a[0:0]
- attribute \src "libresoc.v:89034.3-89094.6"
+ attribute \src "libresoc.v:87659.3-87719.6"
wire $0\dec31_inv_out[0:0]
- attribute \src "libresoc.v:89339.3-89399.6"
+ attribute \src "libresoc.v:87964.3-88024.6"
wire $0\dec31_is_32b[0:0]
- attribute \src "libresoc.v:88729.3-88789.6"
+ attribute \src "libresoc.v:87354.3-87414.6"
wire width 4 $0\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:89461.3-89521.6"
+ attribute \src "libresoc.v:88086.3-88146.6"
wire $0\dec31_lk[0:0]
- attribute \src "libresoc.v:88180.3-88240.6"
+ attribute \src "libresoc.v:86805.3-86865.6"
wire width 2 $0\dec31_out_sel[1:0]
- attribute \src "libresoc.v:88851.3-88911.6"
+ attribute \src "libresoc.v:87476.3-87536.6"
wire width 2 $0\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:89278.3-89338.6"
+ attribute \src "libresoc.v:87903.3-87963.6"
wire $0\dec31_rsrv[0:0]
- attribute \src "libresoc.v:89522.3-89582.6"
+ attribute \src "libresoc.v:88147.3-88207.6"
wire $0\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:89400.3-89460.6"
+ attribute \src "libresoc.v:88025.3-88085.6"
wire $0\dec31_sgn[0:0]
- attribute \src "libresoc.v:89217.3-89277.6"
+ attribute \src "libresoc.v:87842.3-87902.6"
wire $0\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:88607.3-88667.6"
+ attribute \src "libresoc.v:87232.3-87292.6"
wire width 3 $0\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:88668.3-88728.6"
+ attribute \src "libresoc.v:87293.3-87353.6"
wire width 3 $0\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:88363.3-88423.6"
+ attribute \src "libresoc.v:86988.3-87048.6"
wire width 3 $0\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:88424.3-88484.6"
+ attribute \src "libresoc.v:87049.3-87109.6"
wire width 3 $0\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:88485.3-88545.6"
+ attribute \src "libresoc.v:87110.3-87170.6"
wire width 3 $0\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:88546.3-88606.6"
+ attribute \src "libresoc.v:87171.3-87231.6"
wire width 3 $0\dec31_sv_out[2:0]
- attribute \src "libresoc.v:88790.3-88850.6"
+ attribute \src "libresoc.v:87415.3-87475.6"
wire width 2 $0\dec31_upd[1:0]
- attribute \src "libresoc.v:81264.7-81264.20"
+ attribute \src "libresoc.v:79889.7-79889.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:87875.3-87935.6"
+ attribute \src "libresoc.v:86500.3-86560.6"
wire width 2 $1\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:87936.3-87996.6"
+ attribute \src "libresoc.v:86561.3-86621.6"
wire width 2 $1\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:87814.3-87874.6"
+ attribute \src "libresoc.v:86439.3-86499.6"
wire width 8 $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:89156.3-89216.6"
+ attribute \src "libresoc.v:87781.3-87841.6"
wire $1\dec31_br[0:0]
- attribute \src "libresoc.v:88241.3-88301.6"
+ attribute \src "libresoc.v:86866.3-86926.6"
wire width 3 $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:88302.3-88362.6"
+ attribute \src "libresoc.v:86927.3-86987.6"
wire width 3 $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:88912.3-88972.6"
+ attribute \src "libresoc.v:87537.3-87597.6"
wire width 2 $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:89095.3-89155.6"
+ attribute \src "libresoc.v:87720.3-87780.6"
wire $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:87753.3-87813.6"
+ attribute \src "libresoc.v:86378.3-86438.6"
wire width 5 $1\dec31_form[4:0]
- attribute \src "libresoc.v:87631.3-87691.6"
+ attribute \src "libresoc.v:86256.3-86316.6"
wire width 13 $1\dec31_function_unit[12:0]
- attribute \src "libresoc.v:87997.3-88057.6"
+ attribute \src "libresoc.v:86622.3-86682.6"
wire width 3 $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:88058.3-88118.6"
+ attribute \src "libresoc.v:86683.3-86743.6"
wire width 4 $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88119.3-88179.6"
+ attribute \src "libresoc.v:86744.3-86804.6"
wire width 2 $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:87692.3-87752.6"
+ attribute \src "libresoc.v:86317.3-86377.6"
wire width 7 $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:88973.3-89033.6"
+ attribute \src "libresoc.v:87598.3-87658.6"
wire $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:89034.3-89094.6"
+ attribute \src "libresoc.v:87659.3-87719.6"
wire $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:89339.3-89399.6"
+ attribute \src "libresoc.v:87964.3-88024.6"
wire $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:88729.3-88789.6"
+ attribute \src "libresoc.v:87354.3-87414.6"
wire width 4 $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:89461.3-89521.6"
+ attribute \src "libresoc.v:88086.3-88146.6"
wire $1\dec31_lk[0:0]
- attribute \src "libresoc.v:88180.3-88240.6"
+ attribute \src "libresoc.v:86805.3-86865.6"
wire width 2 $1\dec31_out_sel[1:0]
- attribute \src "libresoc.v:88851.3-88911.6"
+ attribute \src "libresoc.v:87476.3-87536.6"
wire width 2 $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:89278.3-89338.6"
+ attribute \src "libresoc.v:87903.3-87963.6"
wire $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:89522.3-89582.6"
+ attribute \src "libresoc.v:88147.3-88207.6"
wire $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:89400.3-89460.6"
+ attribute \src "libresoc.v:88025.3-88085.6"
wire $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:89217.3-89277.6"
+ attribute \src "libresoc.v:87842.3-87902.6"
wire $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:88607.3-88667.6"
+ attribute \src "libresoc.v:87232.3-87292.6"
wire width 3 $1\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:88668.3-88728.6"
+ attribute \src "libresoc.v:87293.3-87353.6"
wire width 3 $1\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:88363.3-88423.6"
+ attribute \src "libresoc.v:86988.3-87048.6"
wire width 3 $1\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:88424.3-88484.6"
+ attribute \src "libresoc.v:87049.3-87109.6"
wire width 3 $1\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:88485.3-88545.6"
+ attribute \src "libresoc.v:87110.3-87170.6"
wire width 3 $1\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:88546.3-88606.6"
+ attribute \src "libresoc.v:87171.3-87231.6"
wire width 3 $1\dec31_sv_out[2:0]
- attribute \src "libresoc.v:88790.3-88850.6"
+ attribute \src "libresoc.v:87415.3-87475.6"
wire width 2 $1\dec31_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_upd
- attribute \src "libresoc.v:81264.7-81264.15"
+ attribute \src "libresoc.v:79889.7-79889.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347"
wire width 5 \opc_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 10 \opcode_switch
attribute \module_not_derived 1
- attribute \src "libresoc.v:87001.18-87035.4"
+ attribute \src "libresoc.v:85626.18-85660.4"
cell \dec31_dec_sub0 \dec31_dec_sub0
connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype
connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype
connect \opcode_in \dec31_dec_sub0_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87036.19-87070.4"
+ attribute \src "libresoc.v:85661.19-85695.4"
cell \dec31_dec_sub10 \dec31_dec_sub10
connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype
connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype
connect \opcode_in \dec31_dec_sub10_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87071.19-87105.4"
+ attribute \src "libresoc.v:85696.19-85730.4"
cell \dec31_dec_sub11 \dec31_dec_sub11
connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype
connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype
connect \opcode_in \dec31_dec_sub11_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87106.19-87140.4"
+ attribute \src "libresoc.v:85731.19-85765.4"
cell \dec31_dec_sub15 \dec31_dec_sub15
connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype
connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype
connect \opcode_in \dec31_dec_sub15_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87141.19-87175.4"
+ attribute \src "libresoc.v:85766.19-85800.4"
cell \dec31_dec_sub16 \dec31_dec_sub16
connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype
connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype
connect \opcode_in \dec31_dec_sub16_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87176.19-87210.4"
+ attribute \src "libresoc.v:85801.19-85835.4"
cell \dec31_dec_sub18 \dec31_dec_sub18
connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype
connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype
connect \opcode_in \dec31_dec_sub18_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87211.19-87245.4"
+ attribute \src "libresoc.v:85836.19-85870.4"
cell \dec31_dec_sub19 \dec31_dec_sub19
connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype
connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype
connect \opcode_in \dec31_dec_sub19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87246.19-87280.4"
+ attribute \src "libresoc.v:85871.19-85905.4"
cell \dec31_dec_sub20 \dec31_dec_sub20
connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype
connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype
connect \opcode_in \dec31_dec_sub20_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87281.19-87315.4"
+ attribute \src "libresoc.v:85906.19-85940.4"
cell \dec31_dec_sub21 \dec31_dec_sub21
connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype
connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype
connect \opcode_in \dec31_dec_sub21_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87316.19-87350.4"
+ attribute \src "libresoc.v:85941.19-85975.4"
cell \dec31_dec_sub22 \dec31_dec_sub22
connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype
connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype
connect \opcode_in \dec31_dec_sub22_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87351.19-87385.4"
+ attribute \src "libresoc.v:85976.19-86010.4"
cell \dec31_dec_sub23 \dec31_dec_sub23
connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype
connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype
connect \opcode_in \dec31_dec_sub23_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87386.19-87420.4"
+ attribute \src "libresoc.v:86011.19-86045.4"
cell \dec31_dec_sub24 \dec31_dec_sub24
connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype
connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype
connect \opcode_in \dec31_dec_sub24_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87421.19-87455.4"
+ attribute \src "libresoc.v:86046.19-86080.4"
cell \dec31_dec_sub26 \dec31_dec_sub26
connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype
connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype
connect \opcode_in \dec31_dec_sub26_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87456.19-87490.4"
+ attribute \src "libresoc.v:86081.19-86115.4"
cell \dec31_dec_sub27 \dec31_dec_sub27
connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype
connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype
connect \opcode_in \dec31_dec_sub27_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87491.19-87525.4"
+ attribute \src "libresoc.v:86116.19-86150.4"
cell \dec31_dec_sub28 \dec31_dec_sub28
connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype
connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype
connect \opcode_in \dec31_dec_sub28_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87526.18-87560.4"
+ attribute \src "libresoc.v:86151.18-86185.4"
cell \dec31_dec_sub4 \dec31_dec_sub4
connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype
connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype
connect \opcode_in \dec31_dec_sub4_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87561.18-87595.4"
+ attribute \src "libresoc.v:86186.18-86220.4"
cell \dec31_dec_sub8 \dec31_dec_sub8
connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype
connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype
connect \opcode_in \dec31_dec_sub8_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:87596.18-87630.4"
+ attribute \src "libresoc.v:86221.18-86255.4"
cell \dec31_dec_sub9 \dec31_dec_sub9
connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype
connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype
connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd
connect \opcode_in \dec31_dec_sub9_opcode_in
end
- attribute \src "libresoc.v:81264.7-81264.20"
- process $proc$libresoc.v:81264$3852
+ attribute \src "libresoc.v:79889.7-79889.20"
+ process $proc$libresoc.v:79889$3796
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:87631.3-87691.6"
- process $proc$libresoc.v:87631$3820
+ attribute \src "libresoc.v:86256.3-86316.6"
+ process $proc$libresoc.v:86256$3764
assign { } { }
assign { } { }
assign $0\dec31_function_unit[12:0] $1\dec31_function_unit[12:0]
- attribute \src "libresoc.v:87632.5-87632.29"
+ attribute \src "libresoc.v:86257.5-86257.29"
switch \initial
- attribute \src "libresoc.v:87632.9-87632.17"
+ attribute \src "libresoc.v:86257.9-86257.17"
case 1'1
case
end
sync always
update \dec31_function_unit $0\dec31_function_unit[12:0]
end
- attribute \src "libresoc.v:87692.3-87752.6"
- process $proc$libresoc.v:87692$3821
+ attribute \src "libresoc.v:86317.3-86377.6"
+ process $proc$libresoc.v:86317$3765
assign { } { }
assign { } { }
assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:87693.5-87693.29"
+ attribute \src "libresoc.v:86318.5-86318.29"
switch \initial
- attribute \src "libresoc.v:87693.9-87693.17"
+ attribute \src "libresoc.v:86318.9-86318.17"
case 1'1
case
end
sync always
update \dec31_internal_op $0\dec31_internal_op[6:0]
end
- attribute \src "libresoc.v:87753.3-87813.6"
- process $proc$libresoc.v:87753$3822
+ attribute \src "libresoc.v:86378.3-86438.6"
+ process $proc$libresoc.v:86378$3766
assign { } { }
assign { } { }
assign $0\dec31_form[4:0] $1\dec31_form[4:0]
- attribute \src "libresoc.v:87754.5-87754.29"
+ attribute \src "libresoc.v:86379.5-86379.29"
switch \initial
- attribute \src "libresoc.v:87754.9-87754.17"
+ attribute \src "libresoc.v:86379.9-86379.17"
case 1'1
case
end
sync always
update \dec31_form $0\dec31_form[4:0]
end
- attribute \src "libresoc.v:87814.3-87874.6"
- process $proc$libresoc.v:87814$3823
+ attribute \src "libresoc.v:86439.3-86499.6"
+ process $proc$libresoc.v:86439$3767
assign { } { }
assign { } { }
assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:87815.5-87815.29"
+ attribute \src "libresoc.v:86440.5-86440.29"
switch \initial
- attribute \src "libresoc.v:87815.9-87815.17"
+ attribute \src "libresoc.v:86440.9-86440.17"
case 1'1
case
end
sync always
update \dec31_asmcode $0\dec31_asmcode[7:0]
end
- attribute \src "libresoc.v:87875.3-87935.6"
- process $proc$libresoc.v:87875$3824
+ attribute \src "libresoc.v:86500.3-86560.6"
+ process $proc$libresoc.v:86500$3768
assign { } { }
assign { } { }
assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0]
- attribute \src "libresoc.v:87876.5-87876.29"
+ attribute \src "libresoc.v:86501.5-86501.29"
switch \initial
- attribute \src "libresoc.v:87876.9-87876.17"
+ attribute \src "libresoc.v:86501.9-86501.17"
case 1'1
case
end
sync always
update \dec31_SV_Etype $0\dec31_SV_Etype[1:0]
end
- attribute \src "libresoc.v:87936.3-87996.6"
- process $proc$libresoc.v:87936$3825
+ attribute \src "libresoc.v:86561.3-86621.6"
+ process $proc$libresoc.v:86561$3769
assign { } { }
assign { } { }
assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0]
- attribute \src "libresoc.v:87937.5-87937.29"
+ attribute \src "libresoc.v:86562.5-86562.29"
switch \initial
- attribute \src "libresoc.v:87937.9-87937.17"
+ attribute \src "libresoc.v:86562.9-86562.17"
case 1'1
case
end
sync always
update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:87997.3-88057.6"
- process $proc$libresoc.v:87997$3826
+ attribute \src "libresoc.v:86622.3-86682.6"
+ process $proc$libresoc.v:86622$3770
assign { } { }
assign { } { }
assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:87998.5-87998.29"
+ attribute \src "libresoc.v:86623.5-86623.29"
switch \initial
- attribute \src "libresoc.v:87998.9-87998.17"
+ attribute \src "libresoc.v:86623.9-86623.17"
case 1'1
case
end
sync always
update \dec31_in1_sel $0\dec31_in1_sel[2:0]
end
- attribute \src "libresoc.v:88058.3-88118.6"
- process $proc$libresoc.v:88058$3827
+ attribute \src "libresoc.v:86683.3-86743.6"
+ process $proc$libresoc.v:86683$3771
assign { } { }
assign { } { }
assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:88059.5-88059.29"
+ attribute \src "libresoc.v:86684.5-86684.29"
switch \initial
- attribute \src "libresoc.v:88059.9-88059.17"
+ attribute \src "libresoc.v:86684.9-86684.17"
case 1'1
case
end
sync always
update \dec31_in2_sel $0\dec31_in2_sel[3:0]
end
- attribute \src "libresoc.v:88119.3-88179.6"
- process $proc$libresoc.v:88119$3828
+ attribute \src "libresoc.v:86744.3-86804.6"
+ process $proc$libresoc.v:86744$3772
assign { } { }
assign { } { }
assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:88120.5-88120.29"
+ attribute \src "libresoc.v:86745.5-86745.29"
switch \initial
- attribute \src "libresoc.v:88120.9-88120.17"
+ attribute \src "libresoc.v:86745.9-86745.17"
case 1'1
case
end
sync always
update \dec31_in3_sel $0\dec31_in3_sel[1:0]
end
- attribute \src "libresoc.v:88180.3-88240.6"
- process $proc$libresoc.v:88180$3829
+ attribute \src "libresoc.v:86805.3-86865.6"
+ process $proc$libresoc.v:86805$3773
assign { } { }
assign { } { }
assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0]
- attribute \src "libresoc.v:88181.5-88181.29"
+ attribute \src "libresoc.v:86806.5-86806.29"
switch \initial
- attribute \src "libresoc.v:88181.9-88181.17"
+ attribute \src "libresoc.v:86806.9-86806.17"
case 1'1
case
end
sync always
update \dec31_out_sel $0\dec31_out_sel[1:0]
end
- attribute \src "libresoc.v:88241.3-88301.6"
- process $proc$libresoc.v:88241$3830
+ attribute \src "libresoc.v:86866.3-86926.6"
+ process $proc$libresoc.v:86866$3774
assign { } { }
assign { } { }
assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:88242.5-88242.29"
+ attribute \src "libresoc.v:86867.5-86867.29"
switch \initial
- attribute \src "libresoc.v:88242.9-88242.17"
+ attribute \src "libresoc.v:86867.9-86867.17"
case 1'1
case
end
sync always
update \dec31_cr_in $0\dec31_cr_in[2:0]
end
- attribute \src "libresoc.v:88302.3-88362.6"
- process $proc$libresoc.v:88302$3831
+ attribute \src "libresoc.v:86927.3-86987.6"
+ process $proc$libresoc.v:86927$3775
assign { } { }
assign { } { }
assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:88303.5-88303.29"
+ attribute \src "libresoc.v:86928.5-86928.29"
switch \initial
- attribute \src "libresoc.v:88303.9-88303.17"
+ attribute \src "libresoc.v:86928.9-86928.17"
case 1'1
case
end
sync always
update \dec31_cr_out $0\dec31_cr_out[2:0]
end
- attribute \src "libresoc.v:88363.3-88423.6"
- process $proc$libresoc.v:88363$3832
+ attribute \src "libresoc.v:86988.3-87048.6"
+ process $proc$libresoc.v:86988$3776
assign { } { }
assign { } { }
assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0]
- attribute \src "libresoc.v:88364.5-88364.29"
+ attribute \src "libresoc.v:86989.5-86989.29"
switch \initial
- attribute \src "libresoc.v:88364.9-88364.17"
+ attribute \src "libresoc.v:86989.9-86989.17"
case 1'1
case
end
sync always
update \dec31_sv_in1 $0\dec31_sv_in1[2:0]
end
- attribute \src "libresoc.v:88424.3-88484.6"
- process $proc$libresoc.v:88424$3833
+ attribute \src "libresoc.v:87049.3-87109.6"
+ process $proc$libresoc.v:87049$3777
assign { } { }
assign { } { }
assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0]
- attribute \src "libresoc.v:88425.5-88425.29"
+ attribute \src "libresoc.v:87050.5-87050.29"
switch \initial
- attribute \src "libresoc.v:88425.9-88425.17"
+ attribute \src "libresoc.v:87050.9-87050.17"
case 1'1
case
end
sync always
update \dec31_sv_in2 $0\dec31_sv_in2[2:0]
end
- attribute \src "libresoc.v:88485.3-88545.6"
- process $proc$libresoc.v:88485$3834
+ attribute \src "libresoc.v:87110.3-87170.6"
+ process $proc$libresoc.v:87110$3778
assign { } { }
assign { } { }
assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0]
- attribute \src "libresoc.v:88486.5-88486.29"
+ attribute \src "libresoc.v:87111.5-87111.29"
switch \initial
- attribute \src "libresoc.v:88486.9-88486.17"
+ attribute \src "libresoc.v:87111.9-87111.17"
case 1'1
case
end
sync always
update \dec31_sv_in3 $0\dec31_sv_in3[2:0]
end
- attribute \src "libresoc.v:88546.3-88606.6"
- process $proc$libresoc.v:88546$3835
+ attribute \src "libresoc.v:87171.3-87231.6"
+ process $proc$libresoc.v:87171$3779
assign { } { }
assign { } { }
assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0]
- attribute \src "libresoc.v:88547.5-88547.29"
+ attribute \src "libresoc.v:87172.5-87172.29"
switch \initial
- attribute \src "libresoc.v:88547.9-88547.17"
+ attribute \src "libresoc.v:87172.9-87172.17"
case 1'1
case
end
sync always
update \dec31_sv_out $0\dec31_sv_out[2:0]
end
- attribute \src "libresoc.v:88607.3-88667.6"
- process $proc$libresoc.v:88607$3836
+ attribute \src "libresoc.v:87232.3-87292.6"
+ process $proc$libresoc.v:87232$3780
assign { } { }
assign { } { }
assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0]
- attribute \src "libresoc.v:88608.5-88608.29"
+ attribute \src "libresoc.v:87233.5-87233.29"
switch \initial
- attribute \src "libresoc.v:88608.9-88608.17"
+ attribute \src "libresoc.v:87233.9-87233.17"
case 1'1
case
end
sync always
update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:88668.3-88728.6"
- process $proc$libresoc.v:88668$3837
+ attribute \src "libresoc.v:87293.3-87353.6"
+ process $proc$libresoc.v:87293$3781
assign { } { }
assign { } { }
assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0]
- attribute \src "libresoc.v:88669.5-88669.29"
+ attribute \src "libresoc.v:87294.5-87294.29"
switch \initial
- attribute \src "libresoc.v:88669.9-88669.17"
+ attribute \src "libresoc.v:87294.9-87294.17"
case 1'1
case
end
sync always
update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:88729.3-88789.6"
- process $proc$libresoc.v:88729$3838
+ attribute \src "libresoc.v:87354.3-87414.6"
+ process $proc$libresoc.v:87354$3782
assign { } { }
assign { } { }
assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:88730.5-88730.29"
+ attribute \src "libresoc.v:87355.5-87355.29"
switch \initial
- attribute \src "libresoc.v:88730.9-88730.17"
+ attribute \src "libresoc.v:87355.9-87355.17"
case 1'1
case
end
sync always
update \dec31_ldst_len $0\dec31_ldst_len[3:0]
end
- attribute \src "libresoc.v:88790.3-88850.6"
- process $proc$libresoc.v:88790$3839
+ attribute \src "libresoc.v:87415.3-87475.6"
+ process $proc$libresoc.v:87415$3783
assign { } { }
assign { } { }
assign $0\dec31_upd[1:0] $1\dec31_upd[1:0]
- attribute \src "libresoc.v:88791.5-88791.29"
+ attribute \src "libresoc.v:87416.5-87416.29"
switch \initial
- attribute \src "libresoc.v:88791.9-88791.17"
+ attribute \src "libresoc.v:87416.9-87416.17"
case 1'1
case
end
sync always
update \dec31_upd $0\dec31_upd[1:0]
end
- attribute \src "libresoc.v:88851.3-88911.6"
- process $proc$libresoc.v:88851$3840
+ attribute \src "libresoc.v:87476.3-87536.6"
+ process $proc$libresoc.v:87476$3784
assign { } { }
assign { } { }
assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:88852.5-88852.29"
+ attribute \src "libresoc.v:87477.5-87477.29"
switch \initial
- attribute \src "libresoc.v:88852.9-88852.17"
+ attribute \src "libresoc.v:87477.9-87477.17"
case 1'1
case
end
sync always
update \dec31_rc_sel $0\dec31_rc_sel[1:0]
end
- attribute \src "libresoc.v:88912.3-88972.6"
- process $proc$libresoc.v:88912$3841
+ attribute \src "libresoc.v:87537.3-87597.6"
+ process $proc$libresoc.v:87537$3785
assign { } { }
assign { } { }
assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:88913.5-88913.29"
+ attribute \src "libresoc.v:87538.5-87538.29"
switch \initial
- attribute \src "libresoc.v:88913.9-88913.17"
+ attribute \src "libresoc.v:87538.9-87538.17"
case 1'1
case
end
sync always
update \dec31_cry_in $0\dec31_cry_in[1:0]
end
- attribute \src "libresoc.v:88973.3-89033.6"
- process $proc$libresoc.v:88973$3842
+ attribute \src "libresoc.v:87598.3-87658.6"
+ process $proc$libresoc.v:87598$3786
assign { } { }
assign { } { }
assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:88974.5-88974.29"
+ attribute \src "libresoc.v:87599.5-87599.29"
switch \initial
- attribute \src "libresoc.v:88974.9-88974.17"
+ attribute \src "libresoc.v:87599.9-87599.17"
case 1'1
case
end
sync always
update \dec31_inv_a $0\dec31_inv_a[0:0]
end
- attribute \src "libresoc.v:89034.3-89094.6"
- process $proc$libresoc.v:89034$3843
+ attribute \src "libresoc.v:87659.3-87719.6"
+ process $proc$libresoc.v:87659$3787
assign { } { }
assign { } { }
assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:89035.5-89035.29"
+ attribute \src "libresoc.v:87660.5-87660.29"
switch \initial
- attribute \src "libresoc.v:89035.9-89035.17"
+ attribute \src "libresoc.v:87660.9-87660.17"
case 1'1
case
end
sync always
update \dec31_inv_out $0\dec31_inv_out[0:0]
end
- attribute \src "libresoc.v:89095.3-89155.6"
- process $proc$libresoc.v:89095$3844
+ attribute \src "libresoc.v:87720.3-87780.6"
+ process $proc$libresoc.v:87720$3788
assign { } { }
assign { } { }
assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:89096.5-89096.29"
+ attribute \src "libresoc.v:87721.5-87721.29"
switch \initial
- attribute \src "libresoc.v:89096.9-89096.17"
+ attribute \src "libresoc.v:87721.9-87721.17"
case 1'1
case
end
sync always
update \dec31_cry_out $0\dec31_cry_out[0:0]
end
- attribute \src "libresoc.v:89156.3-89216.6"
- process $proc$libresoc.v:89156$3845
+ attribute \src "libresoc.v:87781.3-87841.6"
+ process $proc$libresoc.v:87781$3789
assign { } { }
assign { } { }
assign $0\dec31_br[0:0] $1\dec31_br[0:0]
- attribute \src "libresoc.v:89157.5-89157.29"
+ attribute \src "libresoc.v:87782.5-87782.29"
switch \initial
- attribute \src "libresoc.v:89157.9-89157.17"
+ attribute \src "libresoc.v:87782.9-87782.17"
case 1'1
case
end
sync always
update \dec31_br $0\dec31_br[0:0]
end
- attribute \src "libresoc.v:89217.3-89277.6"
- process $proc$libresoc.v:89217$3846
+ attribute \src "libresoc.v:87842.3-87902.6"
+ process $proc$libresoc.v:87842$3790
assign { } { }
assign { } { }
assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:89218.5-89218.29"
+ attribute \src "libresoc.v:87843.5-87843.29"
switch \initial
- attribute \src "libresoc.v:89218.9-89218.17"
+ attribute \src "libresoc.v:87843.9-87843.17"
case 1'1
case
end
sync always
update \dec31_sgn_ext $0\dec31_sgn_ext[0:0]
end
- attribute \src "libresoc.v:89278.3-89338.6"
- process $proc$libresoc.v:89278$3847
+ attribute \src "libresoc.v:87903.3-87963.6"
+ process $proc$libresoc.v:87903$3791
assign { } { }
assign { } { }
assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:89279.5-89279.29"
+ attribute \src "libresoc.v:87904.5-87904.29"
switch \initial
- attribute \src "libresoc.v:89279.9-89279.17"
+ attribute \src "libresoc.v:87904.9-87904.17"
case 1'1
case
end
sync always
update \dec31_rsrv $0\dec31_rsrv[0:0]
end
- attribute \src "libresoc.v:89339.3-89399.6"
- process $proc$libresoc.v:89339$3848
+ attribute \src "libresoc.v:87964.3-88024.6"
+ process $proc$libresoc.v:87964$3792
assign { } { }
assign { } { }
assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:89340.5-89340.29"
+ attribute \src "libresoc.v:87965.5-87965.29"
switch \initial
- attribute \src "libresoc.v:89340.9-89340.17"
+ attribute \src "libresoc.v:87965.9-87965.17"
case 1'1
case
end
sync always
update \dec31_is_32b $0\dec31_is_32b[0:0]
end
- attribute \src "libresoc.v:89400.3-89460.6"
- process $proc$libresoc.v:89400$3849
+ attribute \src "libresoc.v:88025.3-88085.6"
+ process $proc$libresoc.v:88025$3793
assign { } { }
assign { } { }
assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:89401.5-89401.29"
+ attribute \src "libresoc.v:88026.5-88026.29"
switch \initial
- attribute \src "libresoc.v:89401.9-89401.17"
+ attribute \src "libresoc.v:88026.9-88026.17"
case 1'1
case
end
sync always
update \dec31_sgn $0\dec31_sgn[0:0]
end
- attribute \src "libresoc.v:89461.3-89521.6"
- process $proc$libresoc.v:89461$3850
+ attribute \src "libresoc.v:88086.3-88146.6"
+ process $proc$libresoc.v:88086$3794
assign { } { }
assign { } { }
assign $0\dec31_lk[0:0] $1\dec31_lk[0:0]
- attribute \src "libresoc.v:89462.5-89462.29"
+ attribute \src "libresoc.v:88087.5-88087.29"
switch \initial
- attribute \src "libresoc.v:89462.9-89462.17"
+ attribute \src "libresoc.v:88087.9-88087.17"
case 1'1
case
end
sync always
update \dec31_lk $0\dec31_lk[0:0]
end
- attribute \src "libresoc.v:89522.3-89582.6"
- process $proc$libresoc.v:89522$3851
+ attribute \src "libresoc.v:88147.3-88207.6"
+ process $proc$libresoc.v:88147$3795
assign { } { }
assign { } { }
assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:89523.5-89523.29"
+ attribute \src "libresoc.v:88148.5-88148.29"
switch \initial
- attribute \src "libresoc.v:89523.9-89523.17"
+ attribute \src "libresoc.v:88148.9-88148.17"
case 1'1
case
end
connect \opc_in \opcode_switch [4:0]
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:89607.1-90552.10"
+attribute \src "libresoc.v:88232.1-89177.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0"
attribute \generator "nMigen"
module \dec31_dec_sub0
- attribute \src "libresoc.v:90437.3-90455.6"
+ attribute \src "libresoc.v:89062.3-89080.6"
wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:90456.3-90474.6"
+ attribute \src "libresoc.v:89081.3-89099.6"
wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:90209.3-90227.6"
+ attribute \src "libresoc.v:88834.3-88852.6"
wire width 8 $0\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:90285.3-90303.6"
+ attribute \src "libresoc.v:88910.3-88928.6"
wire $0\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:89962.3-89980.6"
+ attribute \src "libresoc.v:88587.3-88605.6"
wire width 3 $0\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:89981.3-89999.6"
+ attribute \src "libresoc.v:88606.3-88624.6"
wire width 3 $0\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:90190.3-90208.6"
+ attribute \src "libresoc.v:88815.3-88833.6"
wire width 2 $0\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:90266.3-90284.6"
+ attribute \src "libresoc.v:88891.3-88909.6"
wire $0\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:90361.3-90379.6"
+ attribute \src "libresoc.v:88986.3-89004.6"
wire width 5 $0\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:89943.3-89961.6"
+ attribute \src "libresoc.v:88568.3-88586.6"
wire width 13 $0\dec31_dec_sub0_function_unit[12:0]
- attribute \src "libresoc.v:90475.3-90493.6"
+ attribute \src "libresoc.v:89100.3-89118.6"
wire width 3 $0\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:90494.3-90512.6"
+ attribute \src "libresoc.v:89119.3-89137.6"
wire width 4 $0\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:90513.3-90531.6"
+ attribute \src "libresoc.v:89138.3-89156.6"
wire width 2 $0\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:90152.3-90170.6"
+ attribute \src "libresoc.v:88777.3-88795.6"
wire width 7 $0\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:90228.3-90246.6"
+ attribute \src "libresoc.v:88853.3-88871.6"
wire $0\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:90247.3-90265.6"
+ attribute \src "libresoc.v:88872.3-88890.6"
wire $0\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:90342.3-90360.6"
+ attribute \src "libresoc.v:88967.3-88985.6"
wire $0\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:90114.3-90132.6"
+ attribute \src "libresoc.v:88739.3-88757.6"
wire width 4 $0\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:90399.3-90417.6"
+ attribute \src "libresoc.v:89024.3-89042.6"
wire $0\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:90532.3-90550.6"
+ attribute \src "libresoc.v:89157.3-89175.6"
wire width 2 $0\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:90171.3-90189.6"
+ attribute \src "libresoc.v:88796.3-88814.6"
wire width 2 $0\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:90323.3-90341.6"
+ attribute \src "libresoc.v:88948.3-88966.6"
wire $0\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:90418.3-90436.6"
+ attribute \src "libresoc.v:89043.3-89061.6"
wire $0\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:90380.3-90398.6"
+ attribute \src "libresoc.v:89005.3-89023.6"
wire $0\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:90304.3-90322.6"
+ attribute \src "libresoc.v:88929.3-88947.6"
wire $0\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:90076.3-90094.6"
+ attribute \src "libresoc.v:88701.3-88719.6"
wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:90095.3-90113.6"
+ attribute \src "libresoc.v:88720.3-88738.6"
wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:90000.3-90018.6"
+ attribute \src "libresoc.v:88625.3-88643.6"
wire width 3 $0\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90019.3-90037.6"
+ attribute \src "libresoc.v:88644.3-88662.6"
wire width 3 $0\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90038.3-90056.6"
+ attribute \src "libresoc.v:88663.3-88681.6"
wire width 3 $0\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:90057.3-90075.6"
+ attribute \src "libresoc.v:88682.3-88700.6"
wire width 3 $0\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:90133.3-90151.6"
+ attribute \src "libresoc.v:88758.3-88776.6"
wire width 2 $0\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:89608.7-89608.20"
+ attribute \src "libresoc.v:88233.7-88233.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:90437.3-90455.6"
+ attribute \src "libresoc.v:89062.3-89080.6"
wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:90456.3-90474.6"
+ attribute \src "libresoc.v:89081.3-89099.6"
wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:90209.3-90227.6"
+ attribute \src "libresoc.v:88834.3-88852.6"
wire width 8 $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:90285.3-90303.6"
+ attribute \src "libresoc.v:88910.3-88928.6"
wire $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:89962.3-89980.6"
+ attribute \src "libresoc.v:88587.3-88605.6"
wire width 3 $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:89981.3-89999.6"
+ attribute \src "libresoc.v:88606.3-88624.6"
wire width 3 $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:90190.3-90208.6"
+ attribute \src "libresoc.v:88815.3-88833.6"
wire width 2 $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:90266.3-90284.6"
+ attribute \src "libresoc.v:88891.3-88909.6"
wire $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:90361.3-90379.6"
+ attribute \src "libresoc.v:88986.3-89004.6"
wire width 5 $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:89943.3-89961.6"
+ attribute \src "libresoc.v:88568.3-88586.6"
wire width 13 $1\dec31_dec_sub0_function_unit[12:0]
- attribute \src "libresoc.v:90475.3-90493.6"
+ attribute \src "libresoc.v:89100.3-89118.6"
wire width 3 $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:90494.3-90512.6"
+ attribute \src "libresoc.v:89119.3-89137.6"
wire width 4 $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:90513.3-90531.6"
+ attribute \src "libresoc.v:89138.3-89156.6"
wire width 2 $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:90152.3-90170.6"
+ attribute \src "libresoc.v:88777.3-88795.6"
wire width 7 $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:90228.3-90246.6"
+ attribute \src "libresoc.v:88853.3-88871.6"
wire $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:90247.3-90265.6"
+ attribute \src "libresoc.v:88872.3-88890.6"
wire $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:90342.3-90360.6"
+ attribute \src "libresoc.v:88967.3-88985.6"
wire $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:90114.3-90132.6"
+ attribute \src "libresoc.v:88739.3-88757.6"
wire width 4 $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:90399.3-90417.6"
+ attribute \src "libresoc.v:89024.3-89042.6"
wire $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:90532.3-90550.6"
+ attribute \src "libresoc.v:89157.3-89175.6"
wire width 2 $1\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:90171.3-90189.6"
+ attribute \src "libresoc.v:88796.3-88814.6"
wire width 2 $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:90323.3-90341.6"
+ attribute \src "libresoc.v:88948.3-88966.6"
wire $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:90418.3-90436.6"
+ attribute \src "libresoc.v:89043.3-89061.6"
wire $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:90380.3-90398.6"
+ attribute \src "libresoc.v:89005.3-89023.6"
wire $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:90304.3-90322.6"
+ attribute \src "libresoc.v:88929.3-88947.6"
wire $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:90076.3-90094.6"
+ attribute \src "libresoc.v:88701.3-88719.6"
wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:90095.3-90113.6"
+ attribute \src "libresoc.v:88720.3-88738.6"
wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:90000.3-90018.6"
+ attribute \src "libresoc.v:88625.3-88643.6"
wire width 3 $1\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90019.3-90037.6"
+ attribute \src "libresoc.v:88644.3-88662.6"
wire width 3 $1\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90038.3-90056.6"
+ attribute \src "libresoc.v:88663.3-88681.6"
wire width 3 $1\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:90057.3-90075.6"
+ attribute \src "libresoc.v:88682.3-88700.6"
wire width 3 $1\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:90133.3-90151.6"
+ attribute \src "libresoc.v:88758.3-88776.6"
wire width 2 $1\dec31_dec_sub0_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub0_upd
- attribute \src "libresoc.v:89608.7-89608.15"
+ attribute \src "libresoc.v:88233.7-88233.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:89608.7-89608.20"
- process $proc$libresoc.v:89608$3885
+ attribute \src "libresoc.v:88233.7-88233.20"
+ process $proc$libresoc.v:88233$3829
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:89943.3-89961.6"
- process $proc$libresoc.v:89943$3853
+ attribute \src "libresoc.v:88568.3-88586.6"
+ process $proc$libresoc.v:88568$3797
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_function_unit[12:0] $1\dec31_dec_sub0_function_unit[12:0]
- attribute \src "libresoc.v:89944.5-89944.29"
+ attribute \src "libresoc.v:88569.5-88569.29"
switch \initial
- attribute \src "libresoc.v:89944.9-89944.17"
+ attribute \src "libresoc.v:88569.9-88569.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[12:0]
end
- attribute \src "libresoc.v:89962.3-89980.6"
- process $proc$libresoc.v:89962$3854
+ attribute \src "libresoc.v:88587.3-88605.6"
+ process $proc$libresoc.v:88587$3798
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:89963.5-89963.29"
+ attribute \src "libresoc.v:88588.5-88588.29"
switch \initial
- attribute \src "libresoc.v:89963.9-89963.17"
+ attribute \src "libresoc.v:88588.9-88588.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0]
end
- attribute \src "libresoc.v:89981.3-89999.6"
- process $proc$libresoc.v:89981$3855
+ attribute \src "libresoc.v:88606.3-88624.6"
+ process $proc$libresoc.v:88606$3799
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:89982.5-89982.29"
+ attribute \src "libresoc.v:88607.5-88607.29"
switch \initial
- attribute \src "libresoc.v:89982.9-89982.17"
+ attribute \src "libresoc.v:88607.9-88607.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0]
end
- attribute \src "libresoc.v:90000.3-90018.6"
- process $proc$libresoc.v:90000$3856
+ attribute \src "libresoc.v:88625.3-88643.6"
+ process $proc$libresoc.v:88625$3800
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0]
- attribute \src "libresoc.v:90001.5-90001.29"
+ attribute \src "libresoc.v:88626.5-88626.29"
switch \initial
- attribute \src "libresoc.v:90001.9-90001.17"
+ attribute \src "libresoc.v:88626.9-88626.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0]
end
- attribute \src "libresoc.v:90019.3-90037.6"
- process $proc$libresoc.v:90019$3857
+ attribute \src "libresoc.v:88644.3-88662.6"
+ process $proc$libresoc.v:88644$3801
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0]
- attribute \src "libresoc.v:90020.5-90020.29"
+ attribute \src "libresoc.v:88645.5-88645.29"
switch \initial
- attribute \src "libresoc.v:90020.9-90020.17"
+ attribute \src "libresoc.v:88645.9-88645.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0]
end
- attribute \src "libresoc.v:90038.3-90056.6"
- process $proc$libresoc.v:90038$3858
+ attribute \src "libresoc.v:88663.3-88681.6"
+ process $proc$libresoc.v:88663$3802
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0]
- attribute \src "libresoc.v:90039.5-90039.29"
+ attribute \src "libresoc.v:88664.5-88664.29"
switch \initial
- attribute \src "libresoc.v:90039.9-90039.17"
+ attribute \src "libresoc.v:88664.9-88664.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0]
end
- attribute \src "libresoc.v:90057.3-90075.6"
- process $proc$libresoc.v:90057$3859
+ attribute \src "libresoc.v:88682.3-88700.6"
+ process $proc$libresoc.v:88682$3803
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0]
- attribute \src "libresoc.v:90058.5-90058.29"
+ attribute \src "libresoc.v:88683.5-88683.29"
switch \initial
- attribute \src "libresoc.v:90058.9-90058.17"
+ attribute \src "libresoc.v:88683.9-88683.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0]
end
- attribute \src "libresoc.v:90076.3-90094.6"
- process $proc$libresoc.v:90076$3860
+ attribute \src "libresoc.v:88701.3-88719.6"
+ process $proc$libresoc.v:88701$3804
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0]
- attribute \src "libresoc.v:90077.5-90077.29"
+ attribute \src "libresoc.v:88702.5-88702.29"
switch \initial
- attribute \src "libresoc.v:90077.9-90077.17"
+ attribute \src "libresoc.v:88702.9-88702.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:90095.3-90113.6"
- process $proc$libresoc.v:90095$3861
+ attribute \src "libresoc.v:88720.3-88738.6"
+ process $proc$libresoc.v:88720$3805
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0]
- attribute \src "libresoc.v:90096.5-90096.29"
+ attribute \src "libresoc.v:88721.5-88721.29"
switch \initial
- attribute \src "libresoc.v:90096.9-90096.17"
+ attribute \src "libresoc.v:88721.9-88721.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:90114.3-90132.6"
- process $proc$libresoc.v:90114$3862
+ attribute \src "libresoc.v:88739.3-88757.6"
+ process $proc$libresoc.v:88739$3806
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:90115.5-90115.29"
+ attribute \src "libresoc.v:88740.5-88740.29"
switch \initial
- attribute \src "libresoc.v:90115.9-90115.17"
+ attribute \src "libresoc.v:88740.9-88740.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0]
end
- attribute \src "libresoc.v:90133.3-90151.6"
- process $proc$libresoc.v:90133$3863
+ attribute \src "libresoc.v:88758.3-88776.6"
+ process $proc$libresoc.v:88758$3807
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:90134.5-90134.29"
+ attribute \src "libresoc.v:88759.5-88759.29"
switch \initial
- attribute \src "libresoc.v:90134.9-90134.17"
+ attribute \src "libresoc.v:88759.9-88759.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0]
end
- attribute \src "libresoc.v:90152.3-90170.6"
- process $proc$libresoc.v:90152$3864
+ attribute \src "libresoc.v:88777.3-88795.6"
+ process $proc$libresoc.v:88777$3808
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:90153.5-90153.29"
+ attribute \src "libresoc.v:88778.5-88778.29"
switch \initial
- attribute \src "libresoc.v:90153.9-90153.17"
+ attribute \src "libresoc.v:88778.9-88778.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0]
end
- attribute \src "libresoc.v:90171.3-90189.6"
- process $proc$libresoc.v:90171$3865
+ attribute \src "libresoc.v:88796.3-88814.6"
+ process $proc$libresoc.v:88796$3809
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:90172.5-90172.29"
+ attribute \src "libresoc.v:88797.5-88797.29"
switch \initial
- attribute \src "libresoc.v:90172.9-90172.17"
+ attribute \src "libresoc.v:88797.9-88797.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0]
end
- attribute \src "libresoc.v:90190.3-90208.6"
- process $proc$libresoc.v:90190$3866
+ attribute \src "libresoc.v:88815.3-88833.6"
+ process $proc$libresoc.v:88815$3810
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:90191.5-90191.29"
+ attribute \src "libresoc.v:88816.5-88816.29"
switch \initial
- attribute \src "libresoc.v:90191.9-90191.17"
+ attribute \src "libresoc.v:88816.9-88816.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0]
end
- attribute \src "libresoc.v:90209.3-90227.6"
- process $proc$libresoc.v:90209$3867
+ attribute \src "libresoc.v:88834.3-88852.6"
+ process $proc$libresoc.v:88834$3811
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:90210.5-90210.29"
+ attribute \src "libresoc.v:88835.5-88835.29"
switch \initial
- attribute \src "libresoc.v:90210.9-90210.17"
+ attribute \src "libresoc.v:88835.9-88835.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0]
end
- attribute \src "libresoc.v:90228.3-90246.6"
- process $proc$libresoc.v:90228$3868
+ attribute \src "libresoc.v:88853.3-88871.6"
+ process $proc$libresoc.v:88853$3812
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:90229.5-90229.29"
+ attribute \src "libresoc.v:88854.5-88854.29"
switch \initial
- attribute \src "libresoc.v:90229.9-90229.17"
+ attribute \src "libresoc.v:88854.9-88854.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0]
end
- attribute \src "libresoc.v:90247.3-90265.6"
- process $proc$libresoc.v:90247$3869
+ attribute \src "libresoc.v:88872.3-88890.6"
+ process $proc$libresoc.v:88872$3813
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:90248.5-90248.29"
+ attribute \src "libresoc.v:88873.5-88873.29"
switch \initial
- attribute \src "libresoc.v:90248.9-90248.17"
+ attribute \src "libresoc.v:88873.9-88873.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0]
end
- attribute \src "libresoc.v:90266.3-90284.6"
- process $proc$libresoc.v:90266$3870
+ attribute \src "libresoc.v:88891.3-88909.6"
+ process $proc$libresoc.v:88891$3814
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:90267.5-90267.29"
+ attribute \src "libresoc.v:88892.5-88892.29"
switch \initial
- attribute \src "libresoc.v:90267.9-90267.17"
+ attribute \src "libresoc.v:88892.9-88892.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0]
end
- attribute \src "libresoc.v:90285.3-90303.6"
- process $proc$libresoc.v:90285$3871
+ attribute \src "libresoc.v:88910.3-88928.6"
+ process $proc$libresoc.v:88910$3815
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:90286.5-90286.29"
+ attribute \src "libresoc.v:88911.5-88911.29"
switch \initial
- attribute \src "libresoc.v:90286.9-90286.17"
+ attribute \src "libresoc.v:88911.9-88911.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0]
end
- attribute \src "libresoc.v:90304.3-90322.6"
- process $proc$libresoc.v:90304$3872
+ attribute \src "libresoc.v:88929.3-88947.6"
+ process $proc$libresoc.v:88929$3816
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:90305.5-90305.29"
+ attribute \src "libresoc.v:88930.5-88930.29"
switch \initial
- attribute \src "libresoc.v:90305.9-90305.17"
+ attribute \src "libresoc.v:88930.9-88930.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0]
end
- attribute \src "libresoc.v:90323.3-90341.6"
- process $proc$libresoc.v:90323$3873
+ attribute \src "libresoc.v:88948.3-88966.6"
+ process $proc$libresoc.v:88948$3817
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:90324.5-90324.29"
+ attribute \src "libresoc.v:88949.5-88949.29"
switch \initial
- attribute \src "libresoc.v:90324.9-90324.17"
+ attribute \src "libresoc.v:88949.9-88949.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0]
end
- attribute \src "libresoc.v:90342.3-90360.6"
- process $proc$libresoc.v:90342$3874
+ attribute \src "libresoc.v:88967.3-88985.6"
+ process $proc$libresoc.v:88967$3818
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:90343.5-90343.29"
+ attribute \src "libresoc.v:88968.5-88968.29"
switch \initial
- attribute \src "libresoc.v:90343.9-90343.17"
+ attribute \src "libresoc.v:88968.9-88968.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0]
end
- attribute \src "libresoc.v:90361.3-90379.6"
- process $proc$libresoc.v:90361$3875
+ attribute \src "libresoc.v:88986.3-89004.6"
+ process $proc$libresoc.v:88986$3819
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:90362.5-90362.29"
+ attribute \src "libresoc.v:88987.5-88987.29"
switch \initial
- attribute \src "libresoc.v:90362.9-90362.17"
+ attribute \src "libresoc.v:88987.9-88987.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0]
end
- attribute \src "libresoc.v:90380.3-90398.6"
- process $proc$libresoc.v:90380$3876
+ attribute \src "libresoc.v:89005.3-89023.6"
+ process $proc$libresoc.v:89005$3820
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:90381.5-90381.29"
+ attribute \src "libresoc.v:89006.5-89006.29"
switch \initial
- attribute \src "libresoc.v:90381.9-90381.17"
+ attribute \src "libresoc.v:89006.9-89006.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0]
end
- attribute \src "libresoc.v:90399.3-90417.6"
- process $proc$libresoc.v:90399$3877
+ attribute \src "libresoc.v:89024.3-89042.6"
+ process $proc$libresoc.v:89024$3821
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:90400.5-90400.29"
+ attribute \src "libresoc.v:89025.5-89025.29"
switch \initial
- attribute \src "libresoc.v:90400.9-90400.17"
+ attribute \src "libresoc.v:89025.9-89025.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0]
end
- attribute \src "libresoc.v:90418.3-90436.6"
- process $proc$libresoc.v:90418$3878
+ attribute \src "libresoc.v:89043.3-89061.6"
+ process $proc$libresoc.v:89043$3822
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:90419.5-90419.29"
+ attribute \src "libresoc.v:89044.5-89044.29"
switch \initial
- attribute \src "libresoc.v:90419.9-90419.17"
+ attribute \src "libresoc.v:89044.9-89044.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:90437.3-90455.6"
- process $proc$libresoc.v:90437$3879
+ attribute \src "libresoc.v:89062.3-89080.6"
+ process $proc$libresoc.v:89062$3823
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0]
- attribute \src "libresoc.v:90438.5-90438.29"
+ attribute \src "libresoc.v:89063.5-89063.29"
switch \initial
- attribute \src "libresoc.v:90438.9-90438.17"
+ attribute \src "libresoc.v:89063.9-89063.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0]
end
- attribute \src "libresoc.v:90456.3-90474.6"
- process $proc$libresoc.v:90456$3880
+ attribute \src "libresoc.v:89081.3-89099.6"
+ process $proc$libresoc.v:89081$3824
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0]
- attribute \src "libresoc.v:90457.5-90457.29"
+ attribute \src "libresoc.v:89082.5-89082.29"
switch \initial
- attribute \src "libresoc.v:90457.9-90457.17"
+ attribute \src "libresoc.v:89082.9-89082.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:90475.3-90493.6"
- process $proc$libresoc.v:90475$3881
+ attribute \src "libresoc.v:89100.3-89118.6"
+ process $proc$libresoc.v:89100$3825
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:90476.5-90476.29"
+ attribute \src "libresoc.v:89101.5-89101.29"
switch \initial
- attribute \src "libresoc.v:90476.9-90476.17"
+ attribute \src "libresoc.v:89101.9-89101.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0]
end
- attribute \src "libresoc.v:90494.3-90512.6"
- process $proc$libresoc.v:90494$3882
+ attribute \src "libresoc.v:89119.3-89137.6"
+ process $proc$libresoc.v:89119$3826
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:90495.5-90495.29"
+ attribute \src "libresoc.v:89120.5-89120.29"
switch \initial
- attribute \src "libresoc.v:90495.9-90495.17"
+ attribute \src "libresoc.v:89120.9-89120.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0]
end
- attribute \src "libresoc.v:90513.3-90531.6"
- process $proc$libresoc.v:90513$3883
+ attribute \src "libresoc.v:89138.3-89156.6"
+ process $proc$libresoc.v:89138$3827
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:90514.5-90514.29"
+ attribute \src "libresoc.v:89139.5-89139.29"
switch \initial
- attribute \src "libresoc.v:90514.9-90514.17"
+ attribute \src "libresoc.v:89139.9-89139.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0]
end
- attribute \src "libresoc.v:90532.3-90550.6"
- process $proc$libresoc.v:90532$3884
+ attribute \src "libresoc.v:89157.3-89175.6"
+ process $proc$libresoc.v:89157$3828
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:90533.5-90533.29"
+ attribute \src "libresoc.v:89158.5-89158.29"
switch \initial
- attribute \src "libresoc.v:90533.9-90533.17"
+ attribute \src "libresoc.v:89158.9-89158.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:90556.1-92077.10"
+attribute \src "libresoc.v:89181.1-90702.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10"
attribute \generator "nMigen"
module \dec31_dec_sub10
- attribute \src "libresoc.v:91854.3-91890.6"
+ attribute \src "libresoc.v:90479.3-90515.6"
wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:91891.3-91927.6"
+ attribute \src "libresoc.v:90516.3-90552.6"
wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:91410.3-91446.6"
+ attribute \src "libresoc.v:90035.3-90071.6"
wire width 8 $0\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:91558.3-91594.6"
+ attribute \src "libresoc.v:90183.3-90219.6"
wire $0\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:90929.3-90965.6"
+ attribute \src "libresoc.v:89554.3-89590.6"
wire width 3 $0\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:90966.3-91002.6"
+ attribute \src "libresoc.v:89591.3-89627.6"
wire width 3 $0\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:91373.3-91409.6"
+ attribute \src "libresoc.v:89998.3-90034.6"
wire width 2 $0\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:91521.3-91557.6"
+ attribute \src "libresoc.v:90146.3-90182.6"
wire $0\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:91706.3-91742.6"
+ attribute \src "libresoc.v:90331.3-90367.6"
wire width 5 $0\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:90892.3-90928.6"
+ attribute \src "libresoc.v:89517.3-89553.6"
wire width 13 $0\dec31_dec_sub10_function_unit[12:0]
- attribute \src "libresoc.v:91928.3-91964.6"
+ attribute \src "libresoc.v:90553.3-90589.6"
wire width 3 $0\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:91965.3-92001.6"
+ attribute \src "libresoc.v:90590.3-90626.6"
wire width 4 $0\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:92002.3-92038.6"
+ attribute \src "libresoc.v:90627.3-90663.6"
wire width 2 $0\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:91299.3-91335.6"
+ attribute \src "libresoc.v:89924.3-89960.6"
wire width 7 $0\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:91447.3-91483.6"
+ attribute \src "libresoc.v:90072.3-90108.6"
wire $0\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:91484.3-91520.6"
+ attribute \src "libresoc.v:90109.3-90145.6"
wire $0\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:91669.3-91705.6"
+ attribute \src "libresoc.v:90294.3-90330.6"
wire $0\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:91225.3-91261.6"
+ attribute \src "libresoc.v:89850.3-89886.6"
wire width 4 $0\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:91780.3-91816.6"
+ attribute \src "libresoc.v:90405.3-90441.6"
wire $0\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:92039.3-92075.6"
+ attribute \src "libresoc.v:90664.3-90700.6"
wire width 2 $0\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:91336.3-91372.6"
+ attribute \src "libresoc.v:89961.3-89997.6"
wire width 2 $0\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:91632.3-91668.6"
+ attribute \src "libresoc.v:90257.3-90293.6"
wire $0\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:91817.3-91853.6"
+ attribute \src "libresoc.v:90442.3-90478.6"
wire $0\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:91743.3-91779.6"
+ attribute \src "libresoc.v:90368.3-90404.6"
wire $0\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:91595.3-91631.6"
+ attribute \src "libresoc.v:90220.3-90256.6"
wire $0\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:91151.3-91187.6"
+ attribute \src "libresoc.v:89776.3-89812.6"
wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:91188.3-91224.6"
+ attribute \src "libresoc.v:89813.3-89849.6"
wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:91003.3-91039.6"
+ attribute \src "libresoc.v:89628.3-89664.6"
wire width 3 $0\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:91040.3-91076.6"
+ attribute \src "libresoc.v:89665.3-89701.6"
wire width 3 $0\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:91077.3-91113.6"
+ attribute \src "libresoc.v:89702.3-89738.6"
wire width 3 $0\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:91114.3-91150.6"
+ attribute \src "libresoc.v:89739.3-89775.6"
wire width 3 $0\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:91262.3-91298.6"
+ attribute \src "libresoc.v:89887.3-89923.6"
wire width 2 $0\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:90557.7-90557.20"
+ attribute \src "libresoc.v:89182.7-89182.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:91854.3-91890.6"
+ attribute \src "libresoc.v:90479.3-90515.6"
wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:91891.3-91927.6"
+ attribute \src "libresoc.v:90516.3-90552.6"
wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:91410.3-91446.6"
+ attribute \src "libresoc.v:90035.3-90071.6"
wire width 8 $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:91558.3-91594.6"
+ attribute \src "libresoc.v:90183.3-90219.6"
wire $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:90929.3-90965.6"
+ attribute \src "libresoc.v:89554.3-89590.6"
wire width 3 $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:90966.3-91002.6"
+ attribute \src "libresoc.v:89591.3-89627.6"
wire width 3 $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:91373.3-91409.6"
+ attribute \src "libresoc.v:89998.3-90034.6"
wire width 2 $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:91521.3-91557.6"
+ attribute \src "libresoc.v:90146.3-90182.6"
wire $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:91706.3-91742.6"
+ attribute \src "libresoc.v:90331.3-90367.6"
wire width 5 $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:90892.3-90928.6"
+ attribute \src "libresoc.v:89517.3-89553.6"
wire width 13 $1\dec31_dec_sub10_function_unit[12:0]
- attribute \src "libresoc.v:91928.3-91964.6"
+ attribute \src "libresoc.v:90553.3-90589.6"
wire width 3 $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:91965.3-92001.6"
+ attribute \src "libresoc.v:90590.3-90626.6"
wire width 4 $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:92002.3-92038.6"
+ attribute \src "libresoc.v:90627.3-90663.6"
wire width 2 $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:91299.3-91335.6"
+ attribute \src "libresoc.v:89924.3-89960.6"
wire width 7 $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:91447.3-91483.6"
+ attribute \src "libresoc.v:90072.3-90108.6"
wire $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:91484.3-91520.6"
+ attribute \src "libresoc.v:90109.3-90145.6"
wire $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:91669.3-91705.6"
+ attribute \src "libresoc.v:90294.3-90330.6"
wire $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:91225.3-91261.6"
+ attribute \src "libresoc.v:89850.3-89886.6"
wire width 4 $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:91780.3-91816.6"
+ attribute \src "libresoc.v:90405.3-90441.6"
wire $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:92039.3-92075.6"
+ attribute \src "libresoc.v:90664.3-90700.6"
wire width 2 $1\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:91336.3-91372.6"
+ attribute \src "libresoc.v:89961.3-89997.6"
wire width 2 $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:91632.3-91668.6"
+ attribute \src "libresoc.v:90257.3-90293.6"
wire $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:91817.3-91853.6"
+ attribute \src "libresoc.v:90442.3-90478.6"
wire $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:91743.3-91779.6"
+ attribute \src "libresoc.v:90368.3-90404.6"
wire $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:91595.3-91631.6"
+ attribute \src "libresoc.v:90220.3-90256.6"
wire $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:91151.3-91187.6"
+ attribute \src "libresoc.v:89776.3-89812.6"
wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:91188.3-91224.6"
+ attribute \src "libresoc.v:89813.3-89849.6"
wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:91003.3-91039.6"
+ attribute \src "libresoc.v:89628.3-89664.6"
wire width 3 $1\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:91040.3-91076.6"
+ attribute \src "libresoc.v:89665.3-89701.6"
wire width 3 $1\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:91077.3-91113.6"
+ attribute \src "libresoc.v:89702.3-89738.6"
wire width 3 $1\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:91114.3-91150.6"
+ attribute \src "libresoc.v:89739.3-89775.6"
wire width 3 $1\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:91262.3-91298.6"
+ attribute \src "libresoc.v:89887.3-89923.6"
wire width 2 $1\dec31_dec_sub10_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub10_upd
- attribute \src "libresoc.v:90557.7-90557.15"
+ attribute \src "libresoc.v:89182.7-89182.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:90557.7-90557.20"
- process $proc$libresoc.v:90557$3918
+ attribute \src "libresoc.v:89182.7-89182.20"
+ process $proc$libresoc.v:89182$3862
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:90892.3-90928.6"
- process $proc$libresoc.v:90892$3886
+ attribute \src "libresoc.v:89517.3-89553.6"
+ process $proc$libresoc.v:89517$3830
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_function_unit[12:0] $1\dec31_dec_sub10_function_unit[12:0]
- attribute \src "libresoc.v:90893.5-90893.29"
+ attribute \src "libresoc.v:89518.5-89518.29"
switch \initial
- attribute \src "libresoc.v:90893.9-90893.17"
+ attribute \src "libresoc.v:89518.9-89518.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[12:0]
end
- attribute \src "libresoc.v:90929.3-90965.6"
- process $proc$libresoc.v:90929$3887
+ attribute \src "libresoc.v:89554.3-89590.6"
+ process $proc$libresoc.v:89554$3831
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:90930.5-90930.29"
+ attribute \src "libresoc.v:89555.5-89555.29"
switch \initial
- attribute \src "libresoc.v:90930.9-90930.17"
+ attribute \src "libresoc.v:89555.9-89555.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0]
end
- attribute \src "libresoc.v:90966.3-91002.6"
- process $proc$libresoc.v:90966$3888
+ attribute \src "libresoc.v:89591.3-89627.6"
+ process $proc$libresoc.v:89591$3832
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:90967.5-90967.29"
+ attribute \src "libresoc.v:89592.5-89592.29"
switch \initial
- attribute \src "libresoc.v:90967.9-90967.17"
+ attribute \src "libresoc.v:89592.9-89592.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0]
end
- attribute \src "libresoc.v:91003.3-91039.6"
- process $proc$libresoc.v:91003$3889
+ attribute \src "libresoc.v:89628.3-89664.6"
+ process $proc$libresoc.v:89628$3833
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0]
- attribute \src "libresoc.v:91004.5-91004.29"
+ attribute \src "libresoc.v:89629.5-89629.29"
switch \initial
- attribute \src "libresoc.v:91004.9-91004.17"
+ attribute \src "libresoc.v:89629.9-89629.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0]
end
- attribute \src "libresoc.v:91040.3-91076.6"
- process $proc$libresoc.v:91040$3890
+ attribute \src "libresoc.v:89665.3-89701.6"
+ process $proc$libresoc.v:89665$3834
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0]
- attribute \src "libresoc.v:91041.5-91041.29"
+ attribute \src "libresoc.v:89666.5-89666.29"
switch \initial
- attribute \src "libresoc.v:91041.9-91041.17"
+ attribute \src "libresoc.v:89666.9-89666.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0]
end
- attribute \src "libresoc.v:91077.3-91113.6"
- process $proc$libresoc.v:91077$3891
+ attribute \src "libresoc.v:89702.3-89738.6"
+ process $proc$libresoc.v:89702$3835
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0]
- attribute \src "libresoc.v:91078.5-91078.29"
+ attribute \src "libresoc.v:89703.5-89703.29"
switch \initial
- attribute \src "libresoc.v:91078.9-91078.17"
+ attribute \src "libresoc.v:89703.9-89703.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0]
end
- attribute \src "libresoc.v:91114.3-91150.6"
- process $proc$libresoc.v:91114$3892
+ attribute \src "libresoc.v:89739.3-89775.6"
+ process $proc$libresoc.v:89739$3836
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0]
- attribute \src "libresoc.v:91115.5-91115.29"
+ attribute \src "libresoc.v:89740.5-89740.29"
switch \initial
- attribute \src "libresoc.v:91115.9-91115.17"
+ attribute \src "libresoc.v:89740.9-89740.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0]
end
- attribute \src "libresoc.v:91151.3-91187.6"
- process $proc$libresoc.v:91151$3893
+ attribute \src "libresoc.v:89776.3-89812.6"
+ process $proc$libresoc.v:89776$3837
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0]
- attribute \src "libresoc.v:91152.5-91152.29"
+ attribute \src "libresoc.v:89777.5-89777.29"
switch \initial
- attribute \src "libresoc.v:91152.9-91152.17"
+ attribute \src "libresoc.v:89777.9-89777.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:91188.3-91224.6"
- process $proc$libresoc.v:91188$3894
+ attribute \src "libresoc.v:89813.3-89849.6"
+ process $proc$libresoc.v:89813$3838
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0]
- attribute \src "libresoc.v:91189.5-91189.29"
+ attribute \src "libresoc.v:89814.5-89814.29"
switch \initial
- attribute \src "libresoc.v:91189.9-91189.17"
+ attribute \src "libresoc.v:89814.9-89814.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:91225.3-91261.6"
- process $proc$libresoc.v:91225$3895
+ attribute \src "libresoc.v:89850.3-89886.6"
+ process $proc$libresoc.v:89850$3839
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:91226.5-91226.29"
+ attribute \src "libresoc.v:89851.5-89851.29"
switch \initial
- attribute \src "libresoc.v:91226.9-91226.17"
+ attribute \src "libresoc.v:89851.9-89851.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0]
end
- attribute \src "libresoc.v:91262.3-91298.6"
- process $proc$libresoc.v:91262$3896
+ attribute \src "libresoc.v:89887.3-89923.6"
+ process $proc$libresoc.v:89887$3840
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:91263.5-91263.29"
+ attribute \src "libresoc.v:89888.5-89888.29"
switch \initial
- attribute \src "libresoc.v:91263.9-91263.17"
+ attribute \src "libresoc.v:89888.9-89888.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0]
end
- attribute \src "libresoc.v:91299.3-91335.6"
- process $proc$libresoc.v:91299$3897
+ attribute \src "libresoc.v:89924.3-89960.6"
+ process $proc$libresoc.v:89924$3841
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:91300.5-91300.29"
+ attribute \src "libresoc.v:89925.5-89925.29"
switch \initial
- attribute \src "libresoc.v:91300.9-91300.17"
+ attribute \src "libresoc.v:89925.9-89925.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0]
end
- attribute \src "libresoc.v:91336.3-91372.6"
- process $proc$libresoc.v:91336$3898
+ attribute \src "libresoc.v:89961.3-89997.6"
+ process $proc$libresoc.v:89961$3842
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:91337.5-91337.29"
+ attribute \src "libresoc.v:89962.5-89962.29"
switch \initial
- attribute \src "libresoc.v:91337.9-91337.17"
+ attribute \src "libresoc.v:89962.9-89962.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0]
end
- attribute \src "libresoc.v:91373.3-91409.6"
- process $proc$libresoc.v:91373$3899
+ attribute \src "libresoc.v:89998.3-90034.6"
+ process $proc$libresoc.v:89998$3843
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:91374.5-91374.29"
+ attribute \src "libresoc.v:89999.5-89999.29"
switch \initial
- attribute \src "libresoc.v:91374.9-91374.17"
+ attribute \src "libresoc.v:89999.9-89999.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0]
end
- attribute \src "libresoc.v:91410.3-91446.6"
- process $proc$libresoc.v:91410$3900
+ attribute \src "libresoc.v:90035.3-90071.6"
+ process $proc$libresoc.v:90035$3844
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:91411.5-91411.29"
+ attribute \src "libresoc.v:90036.5-90036.29"
switch \initial
- attribute \src "libresoc.v:91411.9-91411.17"
+ attribute \src "libresoc.v:90036.9-90036.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0]
end
- attribute \src "libresoc.v:91447.3-91483.6"
- process $proc$libresoc.v:91447$3901
+ attribute \src "libresoc.v:90072.3-90108.6"
+ process $proc$libresoc.v:90072$3845
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:91448.5-91448.29"
+ attribute \src "libresoc.v:90073.5-90073.29"
switch \initial
- attribute \src "libresoc.v:91448.9-91448.17"
+ attribute \src "libresoc.v:90073.9-90073.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0]
end
- attribute \src "libresoc.v:91484.3-91520.6"
- process $proc$libresoc.v:91484$3902
+ attribute \src "libresoc.v:90109.3-90145.6"
+ process $proc$libresoc.v:90109$3846
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:91485.5-91485.29"
+ attribute \src "libresoc.v:90110.5-90110.29"
switch \initial
- attribute \src "libresoc.v:91485.9-91485.17"
+ attribute \src "libresoc.v:90110.9-90110.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0]
end
- attribute \src "libresoc.v:91521.3-91557.6"
- process $proc$libresoc.v:91521$3903
+ attribute \src "libresoc.v:90146.3-90182.6"
+ process $proc$libresoc.v:90146$3847
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:91522.5-91522.29"
+ attribute \src "libresoc.v:90147.5-90147.29"
switch \initial
- attribute \src "libresoc.v:91522.9-91522.17"
+ attribute \src "libresoc.v:90147.9-90147.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0]
end
- attribute \src "libresoc.v:91558.3-91594.6"
- process $proc$libresoc.v:91558$3904
+ attribute \src "libresoc.v:90183.3-90219.6"
+ process $proc$libresoc.v:90183$3848
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:91559.5-91559.29"
+ attribute \src "libresoc.v:90184.5-90184.29"
switch \initial
- attribute \src "libresoc.v:91559.9-91559.17"
+ attribute \src "libresoc.v:90184.9-90184.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0]
end
- attribute \src "libresoc.v:91595.3-91631.6"
- process $proc$libresoc.v:91595$3905
+ attribute \src "libresoc.v:90220.3-90256.6"
+ process $proc$libresoc.v:90220$3849
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:91596.5-91596.29"
+ attribute \src "libresoc.v:90221.5-90221.29"
switch \initial
- attribute \src "libresoc.v:91596.9-91596.17"
+ attribute \src "libresoc.v:90221.9-90221.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0]
end
- attribute \src "libresoc.v:91632.3-91668.6"
- process $proc$libresoc.v:91632$3906
+ attribute \src "libresoc.v:90257.3-90293.6"
+ process $proc$libresoc.v:90257$3850
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:91633.5-91633.29"
+ attribute \src "libresoc.v:90258.5-90258.29"
switch \initial
- attribute \src "libresoc.v:91633.9-91633.17"
+ attribute \src "libresoc.v:90258.9-90258.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0]
end
- attribute \src "libresoc.v:91669.3-91705.6"
- process $proc$libresoc.v:91669$3907
+ attribute \src "libresoc.v:90294.3-90330.6"
+ process $proc$libresoc.v:90294$3851
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:91670.5-91670.29"
+ attribute \src "libresoc.v:90295.5-90295.29"
switch \initial
- attribute \src "libresoc.v:91670.9-91670.17"
+ attribute \src "libresoc.v:90295.9-90295.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0]
end
- attribute \src "libresoc.v:91706.3-91742.6"
- process $proc$libresoc.v:91706$3908
+ attribute \src "libresoc.v:90331.3-90367.6"
+ process $proc$libresoc.v:90331$3852
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:91707.5-91707.29"
+ attribute \src "libresoc.v:90332.5-90332.29"
switch \initial
- attribute \src "libresoc.v:91707.9-91707.17"
+ attribute \src "libresoc.v:90332.9-90332.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0]
end
- attribute \src "libresoc.v:91743.3-91779.6"
- process $proc$libresoc.v:91743$3909
+ attribute \src "libresoc.v:90368.3-90404.6"
+ process $proc$libresoc.v:90368$3853
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:91744.5-91744.29"
+ attribute \src "libresoc.v:90369.5-90369.29"
switch \initial
- attribute \src "libresoc.v:91744.9-91744.17"
+ attribute \src "libresoc.v:90369.9-90369.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0]
end
- attribute \src "libresoc.v:91780.3-91816.6"
- process $proc$libresoc.v:91780$3910
+ attribute \src "libresoc.v:90405.3-90441.6"
+ process $proc$libresoc.v:90405$3854
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:91781.5-91781.29"
+ attribute \src "libresoc.v:90406.5-90406.29"
switch \initial
- attribute \src "libresoc.v:91781.9-91781.17"
+ attribute \src "libresoc.v:90406.9-90406.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0]
end
- attribute \src "libresoc.v:91817.3-91853.6"
- process $proc$libresoc.v:91817$3911
+ attribute \src "libresoc.v:90442.3-90478.6"
+ process $proc$libresoc.v:90442$3855
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:91818.5-91818.29"
+ attribute \src "libresoc.v:90443.5-90443.29"
switch \initial
- attribute \src "libresoc.v:91818.9-91818.17"
+ attribute \src "libresoc.v:90443.9-90443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:91854.3-91890.6"
- process $proc$libresoc.v:91854$3912
+ attribute \src "libresoc.v:90479.3-90515.6"
+ process $proc$libresoc.v:90479$3856
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0]
- attribute \src "libresoc.v:91855.5-91855.29"
+ attribute \src "libresoc.v:90480.5-90480.29"
switch \initial
- attribute \src "libresoc.v:91855.9-91855.17"
+ attribute \src "libresoc.v:90480.9-90480.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0]
end
- attribute \src "libresoc.v:91891.3-91927.6"
- process $proc$libresoc.v:91891$3913
+ attribute \src "libresoc.v:90516.3-90552.6"
+ process $proc$libresoc.v:90516$3857
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0]
- attribute \src "libresoc.v:91892.5-91892.29"
+ attribute \src "libresoc.v:90517.5-90517.29"
switch \initial
- attribute \src "libresoc.v:91892.9-91892.17"
+ attribute \src "libresoc.v:90517.9-90517.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:91928.3-91964.6"
- process $proc$libresoc.v:91928$3914
+ attribute \src "libresoc.v:90553.3-90589.6"
+ process $proc$libresoc.v:90553$3858
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:91929.5-91929.29"
+ attribute \src "libresoc.v:90554.5-90554.29"
switch \initial
- attribute \src "libresoc.v:91929.9-91929.17"
+ attribute \src "libresoc.v:90554.9-90554.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0]
end
- attribute \src "libresoc.v:91965.3-92001.6"
- process $proc$libresoc.v:91965$3915
+ attribute \src "libresoc.v:90590.3-90626.6"
+ process $proc$libresoc.v:90590$3859
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:91966.5-91966.29"
+ attribute \src "libresoc.v:90591.5-90591.29"
switch \initial
- attribute \src "libresoc.v:91966.9-91966.17"
+ attribute \src "libresoc.v:90591.9-90591.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0]
end
- attribute \src "libresoc.v:92002.3-92038.6"
- process $proc$libresoc.v:92002$3916
+ attribute \src "libresoc.v:90627.3-90663.6"
+ process $proc$libresoc.v:90627$3860
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:92003.5-92003.29"
+ attribute \src "libresoc.v:90628.5-90628.29"
switch \initial
- attribute \src "libresoc.v:92003.9-92003.17"
+ attribute \src "libresoc.v:90628.9-90628.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0]
end
- attribute \src "libresoc.v:92039.3-92075.6"
- process $proc$libresoc.v:92039$3917
+ attribute \src "libresoc.v:90664.3-90700.6"
+ process $proc$libresoc.v:90664$3861
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:92040.5-92040.29"
+ attribute \src "libresoc.v:90665.5-90665.29"
switch \initial
- attribute \src "libresoc.v:92040.9-92040.17"
+ attribute \src "libresoc.v:90665.9-90665.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:92081.1-94178.10"
+attribute \src "libresoc.v:90706.1-92803.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11"
attribute \generator "nMigen"
module \dec31_dec_sub11
- attribute \src "libresoc.v:93847.3-93901.6"
+ attribute \src "libresoc.v:92472.3-92526.6"
wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:93902.3-93956.6"
+ attribute \src "libresoc.v:92527.3-92581.6"
wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:93187.3-93241.6"
+ attribute \src "libresoc.v:91812.3-91866.6"
wire width 8 $0\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:93407.3-93461.6"
+ attribute \src "libresoc.v:92032.3-92086.6"
wire $0\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:92472.3-92526.6"
+ attribute \src "libresoc.v:91097.3-91151.6"
wire width 3 $0\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:92527.3-92581.6"
+ attribute \src "libresoc.v:91152.3-91206.6"
wire width 3 $0\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:93132.3-93186.6"
+ attribute \src "libresoc.v:91757.3-91811.6"
wire width 2 $0\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:93352.3-93406.6"
+ attribute \src "libresoc.v:91977.3-92031.6"
wire $0\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:93627.3-93681.6"
+ attribute \src "libresoc.v:92252.3-92306.6"
wire width 5 $0\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:92417.3-92471.6"
+ attribute \src "libresoc.v:91042.3-91096.6"
wire width 13 $0\dec31_dec_sub11_function_unit[12:0]
- attribute \src "libresoc.v:93957.3-94011.6"
+ attribute \src "libresoc.v:92582.3-92636.6"
wire width 3 $0\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:94012.3-94066.6"
+ attribute \src "libresoc.v:92637.3-92691.6"
wire width 4 $0\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:94067.3-94121.6"
+ attribute \src "libresoc.v:92692.3-92746.6"
wire width 2 $0\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:93022.3-93076.6"
+ attribute \src "libresoc.v:91647.3-91701.6"
wire width 7 $0\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:93242.3-93296.6"
+ attribute \src "libresoc.v:91867.3-91921.6"
wire $0\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:93297.3-93351.6"
+ attribute \src "libresoc.v:91922.3-91976.6"
wire $0\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:93572.3-93626.6"
+ attribute \src "libresoc.v:92197.3-92251.6"
wire $0\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:92912.3-92966.6"
+ attribute \src "libresoc.v:91537.3-91591.6"
wire width 4 $0\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:93737.3-93791.6"
+ attribute \src "libresoc.v:92362.3-92416.6"
wire $0\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:94122.3-94176.6"
+ attribute \src "libresoc.v:92747.3-92801.6"
wire width 2 $0\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:93077.3-93131.6"
+ attribute \src "libresoc.v:91702.3-91756.6"
wire width 2 $0\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:93517.3-93571.6"
+ attribute \src "libresoc.v:92142.3-92196.6"
wire $0\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:93792.3-93846.6"
+ attribute \src "libresoc.v:92417.3-92471.6"
wire $0\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:93682.3-93736.6"
+ attribute \src "libresoc.v:92307.3-92361.6"
wire $0\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:93462.3-93516.6"
+ attribute \src "libresoc.v:92087.3-92141.6"
wire $0\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:92802.3-92856.6"
+ attribute \src "libresoc.v:91427.3-91481.6"
wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:92857.3-92911.6"
+ attribute \src "libresoc.v:91482.3-91536.6"
wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:92582.3-92636.6"
+ attribute \src "libresoc.v:91207.3-91261.6"
wire width 3 $0\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:92637.3-92691.6"
+ attribute \src "libresoc.v:91262.3-91316.6"
wire width 3 $0\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:92692.3-92746.6"
+ attribute \src "libresoc.v:91317.3-91371.6"
wire width 3 $0\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:92747.3-92801.6"
+ attribute \src "libresoc.v:91372.3-91426.6"
wire width 3 $0\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:92967.3-93021.6"
+ attribute \src "libresoc.v:91592.3-91646.6"
wire width 2 $0\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:92082.7-92082.20"
+ attribute \src "libresoc.v:90707.7-90707.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:93847.3-93901.6"
+ attribute \src "libresoc.v:92472.3-92526.6"
wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:93902.3-93956.6"
+ attribute \src "libresoc.v:92527.3-92581.6"
wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:93187.3-93241.6"
+ attribute \src "libresoc.v:91812.3-91866.6"
wire width 8 $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:93407.3-93461.6"
+ attribute \src "libresoc.v:92032.3-92086.6"
wire $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:92472.3-92526.6"
+ attribute \src "libresoc.v:91097.3-91151.6"
wire width 3 $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:92527.3-92581.6"
+ attribute \src "libresoc.v:91152.3-91206.6"
wire width 3 $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:93132.3-93186.6"
+ attribute \src "libresoc.v:91757.3-91811.6"
wire width 2 $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:93352.3-93406.6"
+ attribute \src "libresoc.v:91977.3-92031.6"
wire $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:93627.3-93681.6"
+ attribute \src "libresoc.v:92252.3-92306.6"
wire width 5 $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:92417.3-92471.6"
+ attribute \src "libresoc.v:91042.3-91096.6"
wire width 13 $1\dec31_dec_sub11_function_unit[12:0]
- attribute \src "libresoc.v:93957.3-94011.6"
+ attribute \src "libresoc.v:92582.3-92636.6"
wire width 3 $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:94012.3-94066.6"
+ attribute \src "libresoc.v:92637.3-92691.6"
wire width 4 $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:94067.3-94121.6"
+ attribute \src "libresoc.v:92692.3-92746.6"
wire width 2 $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:93022.3-93076.6"
+ attribute \src "libresoc.v:91647.3-91701.6"
wire width 7 $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:93242.3-93296.6"
+ attribute \src "libresoc.v:91867.3-91921.6"
wire $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:93297.3-93351.6"
+ attribute \src "libresoc.v:91922.3-91976.6"
wire $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:93572.3-93626.6"
+ attribute \src "libresoc.v:92197.3-92251.6"
wire $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:92912.3-92966.6"
+ attribute \src "libresoc.v:91537.3-91591.6"
wire width 4 $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:93737.3-93791.6"
+ attribute \src "libresoc.v:92362.3-92416.6"
wire $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:94122.3-94176.6"
+ attribute \src "libresoc.v:92747.3-92801.6"
wire width 2 $1\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:93077.3-93131.6"
+ attribute \src "libresoc.v:91702.3-91756.6"
wire width 2 $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:93517.3-93571.6"
+ attribute \src "libresoc.v:92142.3-92196.6"
wire $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:93792.3-93846.6"
+ attribute \src "libresoc.v:92417.3-92471.6"
wire $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:93682.3-93736.6"
+ attribute \src "libresoc.v:92307.3-92361.6"
wire $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:93462.3-93516.6"
+ attribute \src "libresoc.v:92087.3-92141.6"
wire $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:92802.3-92856.6"
+ attribute \src "libresoc.v:91427.3-91481.6"
wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:92857.3-92911.6"
+ attribute \src "libresoc.v:91482.3-91536.6"
wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:92582.3-92636.6"
+ attribute \src "libresoc.v:91207.3-91261.6"
wire width 3 $1\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:92637.3-92691.6"
+ attribute \src "libresoc.v:91262.3-91316.6"
wire width 3 $1\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:92692.3-92746.6"
+ attribute \src "libresoc.v:91317.3-91371.6"
wire width 3 $1\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:92747.3-92801.6"
+ attribute \src "libresoc.v:91372.3-91426.6"
wire width 3 $1\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:92967.3-93021.6"
+ attribute \src "libresoc.v:91592.3-91646.6"
wire width 2 $1\dec31_dec_sub11_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub11_upd
- attribute \src "libresoc.v:92082.7-92082.15"
+ attribute \src "libresoc.v:90707.7-90707.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:92082.7-92082.20"
- process $proc$libresoc.v:92082$3951
+ attribute \src "libresoc.v:90707.7-90707.20"
+ process $proc$libresoc.v:90707$3895
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:92417.3-92471.6"
- process $proc$libresoc.v:92417$3919
+ attribute \src "libresoc.v:91042.3-91096.6"
+ process $proc$libresoc.v:91042$3863
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_function_unit[12:0] $1\dec31_dec_sub11_function_unit[12:0]
- attribute \src "libresoc.v:92418.5-92418.29"
+ attribute \src "libresoc.v:91043.5-91043.29"
switch \initial
- attribute \src "libresoc.v:92418.9-92418.17"
+ attribute \src "libresoc.v:91043.9-91043.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[12:0]
end
- attribute \src "libresoc.v:92472.3-92526.6"
- process $proc$libresoc.v:92472$3920
+ attribute \src "libresoc.v:91097.3-91151.6"
+ process $proc$libresoc.v:91097$3864
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:92473.5-92473.29"
+ attribute \src "libresoc.v:91098.5-91098.29"
switch \initial
- attribute \src "libresoc.v:92473.9-92473.17"
+ attribute \src "libresoc.v:91098.9-91098.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0]
end
- attribute \src "libresoc.v:92527.3-92581.6"
- process $proc$libresoc.v:92527$3921
+ attribute \src "libresoc.v:91152.3-91206.6"
+ process $proc$libresoc.v:91152$3865
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:92528.5-92528.29"
+ attribute \src "libresoc.v:91153.5-91153.29"
switch \initial
- attribute \src "libresoc.v:92528.9-92528.17"
+ attribute \src "libresoc.v:91153.9-91153.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0]
end
- attribute \src "libresoc.v:92582.3-92636.6"
- process $proc$libresoc.v:92582$3922
+ attribute \src "libresoc.v:91207.3-91261.6"
+ process $proc$libresoc.v:91207$3866
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0]
- attribute \src "libresoc.v:92583.5-92583.29"
+ attribute \src "libresoc.v:91208.5-91208.29"
switch \initial
- attribute \src "libresoc.v:92583.9-92583.17"
+ attribute \src "libresoc.v:91208.9-91208.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0]
end
- attribute \src "libresoc.v:92637.3-92691.6"
- process $proc$libresoc.v:92637$3923
+ attribute \src "libresoc.v:91262.3-91316.6"
+ process $proc$libresoc.v:91262$3867
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0]
- attribute \src "libresoc.v:92638.5-92638.29"
+ attribute \src "libresoc.v:91263.5-91263.29"
switch \initial
- attribute \src "libresoc.v:92638.9-92638.17"
+ attribute \src "libresoc.v:91263.9-91263.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0]
end
- attribute \src "libresoc.v:92692.3-92746.6"
- process $proc$libresoc.v:92692$3924
+ attribute \src "libresoc.v:91317.3-91371.6"
+ process $proc$libresoc.v:91317$3868
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0]
- attribute \src "libresoc.v:92693.5-92693.29"
+ attribute \src "libresoc.v:91318.5-91318.29"
switch \initial
- attribute \src "libresoc.v:92693.9-92693.17"
+ attribute \src "libresoc.v:91318.9-91318.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0]
end
- attribute \src "libresoc.v:92747.3-92801.6"
- process $proc$libresoc.v:92747$3925
+ attribute \src "libresoc.v:91372.3-91426.6"
+ process $proc$libresoc.v:91372$3869
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0]
- attribute \src "libresoc.v:92748.5-92748.29"
+ attribute \src "libresoc.v:91373.5-91373.29"
switch \initial
- attribute \src "libresoc.v:92748.9-92748.17"
+ attribute \src "libresoc.v:91373.9-91373.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0]
end
- attribute \src "libresoc.v:92802.3-92856.6"
- process $proc$libresoc.v:92802$3926
+ attribute \src "libresoc.v:91427.3-91481.6"
+ process $proc$libresoc.v:91427$3870
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0]
- attribute \src "libresoc.v:92803.5-92803.29"
+ attribute \src "libresoc.v:91428.5-91428.29"
switch \initial
- attribute \src "libresoc.v:92803.9-92803.17"
+ attribute \src "libresoc.v:91428.9-91428.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:92857.3-92911.6"
- process $proc$libresoc.v:92857$3927
+ attribute \src "libresoc.v:91482.3-91536.6"
+ process $proc$libresoc.v:91482$3871
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0]
- attribute \src "libresoc.v:92858.5-92858.29"
+ attribute \src "libresoc.v:91483.5-91483.29"
switch \initial
- attribute \src "libresoc.v:92858.9-92858.17"
+ attribute \src "libresoc.v:91483.9-91483.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:92912.3-92966.6"
- process $proc$libresoc.v:92912$3928
+ attribute \src "libresoc.v:91537.3-91591.6"
+ process $proc$libresoc.v:91537$3872
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:92913.5-92913.29"
+ attribute \src "libresoc.v:91538.5-91538.29"
switch \initial
- attribute \src "libresoc.v:92913.9-92913.17"
+ attribute \src "libresoc.v:91538.9-91538.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0]
end
- attribute \src "libresoc.v:92967.3-93021.6"
- process $proc$libresoc.v:92967$3929
+ attribute \src "libresoc.v:91592.3-91646.6"
+ process $proc$libresoc.v:91592$3873
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:92968.5-92968.29"
+ attribute \src "libresoc.v:91593.5-91593.29"
switch \initial
- attribute \src "libresoc.v:92968.9-92968.17"
+ attribute \src "libresoc.v:91593.9-91593.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0]
end
- attribute \src "libresoc.v:93022.3-93076.6"
- process $proc$libresoc.v:93022$3930
+ attribute \src "libresoc.v:91647.3-91701.6"
+ process $proc$libresoc.v:91647$3874
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:93023.5-93023.29"
+ attribute \src "libresoc.v:91648.5-91648.29"
switch \initial
- attribute \src "libresoc.v:93023.9-93023.17"
+ attribute \src "libresoc.v:91648.9-91648.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0]
end
- attribute \src "libresoc.v:93077.3-93131.6"
- process $proc$libresoc.v:93077$3931
+ attribute \src "libresoc.v:91702.3-91756.6"
+ process $proc$libresoc.v:91702$3875
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:93078.5-93078.29"
+ attribute \src "libresoc.v:91703.5-91703.29"
switch \initial
- attribute \src "libresoc.v:93078.9-93078.17"
+ attribute \src "libresoc.v:91703.9-91703.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0]
end
- attribute \src "libresoc.v:93132.3-93186.6"
- process $proc$libresoc.v:93132$3932
+ attribute \src "libresoc.v:91757.3-91811.6"
+ process $proc$libresoc.v:91757$3876
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:93133.5-93133.29"
+ attribute \src "libresoc.v:91758.5-91758.29"
switch \initial
- attribute \src "libresoc.v:93133.9-93133.17"
+ attribute \src "libresoc.v:91758.9-91758.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0]
end
- attribute \src "libresoc.v:93187.3-93241.6"
- process $proc$libresoc.v:93187$3933
+ attribute \src "libresoc.v:91812.3-91866.6"
+ process $proc$libresoc.v:91812$3877
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:93188.5-93188.29"
+ attribute \src "libresoc.v:91813.5-91813.29"
switch \initial
- attribute \src "libresoc.v:93188.9-93188.17"
+ attribute \src "libresoc.v:91813.9-91813.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0]
end
- attribute \src "libresoc.v:93242.3-93296.6"
- process $proc$libresoc.v:93242$3934
+ attribute \src "libresoc.v:91867.3-91921.6"
+ process $proc$libresoc.v:91867$3878
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:93243.5-93243.29"
+ attribute \src "libresoc.v:91868.5-91868.29"
switch \initial
- attribute \src "libresoc.v:93243.9-93243.17"
+ attribute \src "libresoc.v:91868.9-91868.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0]
end
- attribute \src "libresoc.v:93297.3-93351.6"
- process $proc$libresoc.v:93297$3935
+ attribute \src "libresoc.v:91922.3-91976.6"
+ process $proc$libresoc.v:91922$3879
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:93298.5-93298.29"
+ attribute \src "libresoc.v:91923.5-91923.29"
switch \initial
- attribute \src "libresoc.v:93298.9-93298.17"
+ attribute \src "libresoc.v:91923.9-91923.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0]
end
- attribute \src "libresoc.v:93352.3-93406.6"
- process $proc$libresoc.v:93352$3936
+ attribute \src "libresoc.v:91977.3-92031.6"
+ process $proc$libresoc.v:91977$3880
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:93353.5-93353.29"
+ attribute \src "libresoc.v:91978.5-91978.29"
switch \initial
- attribute \src "libresoc.v:93353.9-93353.17"
+ attribute \src "libresoc.v:91978.9-91978.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0]
end
- attribute \src "libresoc.v:93407.3-93461.6"
- process $proc$libresoc.v:93407$3937
+ attribute \src "libresoc.v:92032.3-92086.6"
+ process $proc$libresoc.v:92032$3881
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:93408.5-93408.29"
+ attribute \src "libresoc.v:92033.5-92033.29"
switch \initial
- attribute \src "libresoc.v:93408.9-93408.17"
+ attribute \src "libresoc.v:92033.9-92033.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0]
end
- attribute \src "libresoc.v:93462.3-93516.6"
- process $proc$libresoc.v:93462$3938
+ attribute \src "libresoc.v:92087.3-92141.6"
+ process $proc$libresoc.v:92087$3882
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:93463.5-93463.29"
+ attribute \src "libresoc.v:92088.5-92088.29"
switch \initial
- attribute \src "libresoc.v:93463.9-93463.17"
+ attribute \src "libresoc.v:92088.9-92088.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0]
end
- attribute \src "libresoc.v:93517.3-93571.6"
- process $proc$libresoc.v:93517$3939
+ attribute \src "libresoc.v:92142.3-92196.6"
+ process $proc$libresoc.v:92142$3883
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:93518.5-93518.29"
+ attribute \src "libresoc.v:92143.5-92143.29"
switch \initial
- attribute \src "libresoc.v:93518.9-93518.17"
+ attribute \src "libresoc.v:92143.9-92143.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0]
end
- attribute \src "libresoc.v:93572.3-93626.6"
- process $proc$libresoc.v:93572$3940
+ attribute \src "libresoc.v:92197.3-92251.6"
+ process $proc$libresoc.v:92197$3884
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:93573.5-93573.29"
+ attribute \src "libresoc.v:92198.5-92198.29"
switch \initial
- attribute \src "libresoc.v:93573.9-93573.17"
+ attribute \src "libresoc.v:92198.9-92198.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0]
end
- attribute \src "libresoc.v:93627.3-93681.6"
- process $proc$libresoc.v:93627$3941
+ attribute \src "libresoc.v:92252.3-92306.6"
+ process $proc$libresoc.v:92252$3885
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:93628.5-93628.29"
+ attribute \src "libresoc.v:92253.5-92253.29"
switch \initial
- attribute \src "libresoc.v:93628.9-93628.17"
+ attribute \src "libresoc.v:92253.9-92253.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0]
end
- attribute \src "libresoc.v:93682.3-93736.6"
- process $proc$libresoc.v:93682$3942
+ attribute \src "libresoc.v:92307.3-92361.6"
+ process $proc$libresoc.v:92307$3886
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:93683.5-93683.29"
+ attribute \src "libresoc.v:92308.5-92308.29"
switch \initial
- attribute \src "libresoc.v:93683.9-93683.17"
+ attribute \src "libresoc.v:92308.9-92308.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0]
end
- attribute \src "libresoc.v:93737.3-93791.6"
- process $proc$libresoc.v:93737$3943
+ attribute \src "libresoc.v:92362.3-92416.6"
+ process $proc$libresoc.v:92362$3887
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:93738.5-93738.29"
+ attribute \src "libresoc.v:92363.5-92363.29"
switch \initial
- attribute \src "libresoc.v:93738.9-93738.17"
+ attribute \src "libresoc.v:92363.9-92363.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0]
end
- attribute \src "libresoc.v:93792.3-93846.6"
- process $proc$libresoc.v:93792$3944
+ attribute \src "libresoc.v:92417.3-92471.6"
+ process $proc$libresoc.v:92417$3888
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:93793.5-93793.29"
+ attribute \src "libresoc.v:92418.5-92418.29"
switch \initial
- attribute \src "libresoc.v:93793.9-93793.17"
+ attribute \src "libresoc.v:92418.9-92418.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:93847.3-93901.6"
- process $proc$libresoc.v:93847$3945
+ attribute \src "libresoc.v:92472.3-92526.6"
+ process $proc$libresoc.v:92472$3889
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0]
- attribute \src "libresoc.v:93848.5-93848.29"
+ attribute \src "libresoc.v:92473.5-92473.29"
switch \initial
- attribute \src "libresoc.v:93848.9-93848.17"
+ attribute \src "libresoc.v:92473.9-92473.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0]
end
- attribute \src "libresoc.v:93902.3-93956.6"
- process $proc$libresoc.v:93902$3946
+ attribute \src "libresoc.v:92527.3-92581.6"
+ process $proc$libresoc.v:92527$3890
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0]
- attribute \src "libresoc.v:93903.5-93903.29"
+ attribute \src "libresoc.v:92528.5-92528.29"
switch \initial
- attribute \src "libresoc.v:93903.9-93903.17"
+ attribute \src "libresoc.v:92528.9-92528.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:93957.3-94011.6"
- process $proc$libresoc.v:93957$3947
+ attribute \src "libresoc.v:92582.3-92636.6"
+ process $proc$libresoc.v:92582$3891
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:93958.5-93958.29"
+ attribute \src "libresoc.v:92583.5-92583.29"
switch \initial
- attribute \src "libresoc.v:93958.9-93958.17"
+ attribute \src "libresoc.v:92583.9-92583.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0]
end
- attribute \src "libresoc.v:94012.3-94066.6"
- process $proc$libresoc.v:94012$3948
+ attribute \src "libresoc.v:92637.3-92691.6"
+ process $proc$libresoc.v:92637$3892
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:94013.5-94013.29"
+ attribute \src "libresoc.v:92638.5-92638.29"
switch \initial
- attribute \src "libresoc.v:94013.9-94013.17"
+ attribute \src "libresoc.v:92638.9-92638.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0]
end
- attribute \src "libresoc.v:94067.3-94121.6"
- process $proc$libresoc.v:94067$3949
+ attribute \src "libresoc.v:92692.3-92746.6"
+ process $proc$libresoc.v:92692$3893
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:94068.5-94068.29"
+ attribute \src "libresoc.v:92693.5-92693.29"
switch \initial
- attribute \src "libresoc.v:94068.9-94068.17"
+ attribute \src "libresoc.v:92693.9-92693.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0]
end
- attribute \src "libresoc.v:94122.3-94176.6"
- process $proc$libresoc.v:94122$3950
+ attribute \src "libresoc.v:92747.3-92801.6"
+ process $proc$libresoc.v:92747$3894
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:94123.5-94123.29"
+ attribute \src "libresoc.v:92748.5-92748.29"
switch \initial
- attribute \src "libresoc.v:94123.9-94123.17"
+ attribute \src "libresoc.v:92748.9-92748.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:94182.1-97815.10"
+attribute \src "libresoc.v:92807.1-96440.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15"
attribute \generator "nMigen"
module \dec31_dec_sub15
- attribute \src "libresoc.v:97196.3-97298.6"
+ attribute \src "libresoc.v:95821.3-95923.6"
wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:97299.3-97401.6"
+ attribute \src "libresoc.v:95924.3-96026.6"
wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:95960.3-96062.6"
+ attribute \src "libresoc.v:94585.3-94687.6"
wire width 8 $0\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:96372.3-96474.6"
+ attribute \src "libresoc.v:94997.3-95099.6"
wire $0\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:94621.3-94723.6"
+ attribute \src "libresoc.v:93246.3-93348.6"
wire width 3 $0\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:94724.3-94826.6"
+ attribute \src "libresoc.v:93349.3-93451.6"
wire width 3 $0\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:95857.3-95959.6"
+ attribute \src "libresoc.v:94482.3-94584.6"
wire width 2 $0\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:96269.3-96371.6"
+ attribute \src "libresoc.v:94894.3-94996.6"
wire $0\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:96784.3-96886.6"
+ attribute \src "libresoc.v:95409.3-95511.6"
wire width 5 $0\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:94518.3-94620.6"
+ attribute \src "libresoc.v:93143.3-93245.6"
wire width 13 $0\dec31_dec_sub15_function_unit[12:0]
- attribute \src "libresoc.v:97402.3-97504.6"
+ attribute \src "libresoc.v:96027.3-96129.6"
wire width 3 $0\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:97505.3-97607.6"
+ attribute \src "libresoc.v:96130.3-96232.6"
wire width 4 $0\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:97608.3-97710.6"
+ attribute \src "libresoc.v:96233.3-96335.6"
wire width 2 $0\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:95651.3-95753.6"
+ attribute \src "libresoc.v:94276.3-94378.6"
wire width 7 $0\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:96063.3-96165.6"
+ attribute \src "libresoc.v:94688.3-94790.6"
wire $0\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:96166.3-96268.6"
+ attribute \src "libresoc.v:94791.3-94893.6"
wire $0\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:96681.3-96783.6"
+ attribute \src "libresoc.v:95306.3-95408.6"
wire $0\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:95445.3-95547.6"
+ attribute \src "libresoc.v:94070.3-94172.6"
wire width 4 $0\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:96990.3-97092.6"
+ attribute \src "libresoc.v:95615.3-95717.6"
wire $0\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:97711.3-97813.6"
+ attribute \src "libresoc.v:96336.3-96438.6"
wire width 2 $0\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:95754.3-95856.6"
+ attribute \src "libresoc.v:94379.3-94481.6"
wire width 2 $0\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:96578.3-96680.6"
+ attribute \src "libresoc.v:95203.3-95305.6"
wire $0\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:97093.3-97195.6"
+ attribute \src "libresoc.v:95718.3-95820.6"
wire $0\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:96887.3-96989.6"
+ attribute \src "libresoc.v:95512.3-95614.6"
wire $0\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:96475.3-96577.6"
+ attribute \src "libresoc.v:95100.3-95202.6"
wire $0\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:95239.3-95341.6"
+ attribute \src "libresoc.v:93864.3-93966.6"
wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:95342.3-95444.6"
+ attribute \src "libresoc.v:93967.3-94069.6"
wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:94827.3-94929.6"
+ attribute \src "libresoc.v:93452.3-93554.6"
wire width 3 $0\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:94930.3-95032.6"
+ attribute \src "libresoc.v:93555.3-93657.6"
wire width 3 $0\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:95033.3-95135.6"
+ attribute \src "libresoc.v:93658.3-93760.6"
wire width 3 $0\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:95136.3-95238.6"
+ attribute \src "libresoc.v:93761.3-93863.6"
wire width 3 $0\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:95548.3-95650.6"
+ attribute \src "libresoc.v:94173.3-94275.6"
wire width 2 $0\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:94183.7-94183.20"
+ attribute \src "libresoc.v:92808.7-92808.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:97196.3-97298.6"
+ attribute \src "libresoc.v:95821.3-95923.6"
wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:97299.3-97401.6"
+ attribute \src "libresoc.v:95924.3-96026.6"
wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:95960.3-96062.6"
+ attribute \src "libresoc.v:94585.3-94687.6"
wire width 8 $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:96372.3-96474.6"
+ attribute \src "libresoc.v:94997.3-95099.6"
wire $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:94621.3-94723.6"
+ attribute \src "libresoc.v:93246.3-93348.6"
wire width 3 $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:94724.3-94826.6"
+ attribute \src "libresoc.v:93349.3-93451.6"
wire width 3 $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:95857.3-95959.6"
+ attribute \src "libresoc.v:94482.3-94584.6"
wire width 2 $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:96269.3-96371.6"
+ attribute \src "libresoc.v:94894.3-94996.6"
wire $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:96784.3-96886.6"
+ attribute \src "libresoc.v:95409.3-95511.6"
wire width 5 $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:94518.3-94620.6"
+ attribute \src "libresoc.v:93143.3-93245.6"
wire width 13 $1\dec31_dec_sub15_function_unit[12:0]
- attribute \src "libresoc.v:97402.3-97504.6"
+ attribute \src "libresoc.v:96027.3-96129.6"
wire width 3 $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:97505.3-97607.6"
+ attribute \src "libresoc.v:96130.3-96232.6"
wire width 4 $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:97608.3-97710.6"
+ attribute \src "libresoc.v:96233.3-96335.6"
wire width 2 $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:95651.3-95753.6"
+ attribute \src "libresoc.v:94276.3-94378.6"
wire width 7 $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:96063.3-96165.6"
+ attribute \src "libresoc.v:94688.3-94790.6"
wire $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:96166.3-96268.6"
+ attribute \src "libresoc.v:94791.3-94893.6"
wire $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:96681.3-96783.6"
+ attribute \src "libresoc.v:95306.3-95408.6"
wire $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:95445.3-95547.6"
+ attribute \src "libresoc.v:94070.3-94172.6"
wire width 4 $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:96990.3-97092.6"
+ attribute \src "libresoc.v:95615.3-95717.6"
wire $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:97711.3-97813.6"
+ attribute \src "libresoc.v:96336.3-96438.6"
wire width 2 $1\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:95754.3-95856.6"
+ attribute \src "libresoc.v:94379.3-94481.6"
wire width 2 $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:96578.3-96680.6"
+ attribute \src "libresoc.v:95203.3-95305.6"
wire $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:97093.3-97195.6"
+ attribute \src "libresoc.v:95718.3-95820.6"
wire $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:96887.3-96989.6"
+ attribute \src "libresoc.v:95512.3-95614.6"
wire $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:96475.3-96577.6"
+ attribute \src "libresoc.v:95100.3-95202.6"
wire $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:95239.3-95341.6"
+ attribute \src "libresoc.v:93864.3-93966.6"
wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:95342.3-95444.6"
+ attribute \src "libresoc.v:93967.3-94069.6"
wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:94827.3-94929.6"
+ attribute \src "libresoc.v:93452.3-93554.6"
wire width 3 $1\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:94930.3-95032.6"
+ attribute \src "libresoc.v:93555.3-93657.6"
wire width 3 $1\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:95033.3-95135.6"
+ attribute \src "libresoc.v:93658.3-93760.6"
wire width 3 $1\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:95136.3-95238.6"
+ attribute \src "libresoc.v:93761.3-93863.6"
wire width 3 $1\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:95548.3-95650.6"
+ attribute \src "libresoc.v:94173.3-94275.6"
wire width 2 $1\dec31_dec_sub15_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub15_upd
- attribute \src "libresoc.v:94183.7-94183.15"
+ attribute \src "libresoc.v:92808.7-92808.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:94183.7-94183.20"
- process $proc$libresoc.v:94183$3984
+ attribute \src "libresoc.v:92808.7-92808.20"
+ process $proc$libresoc.v:92808$3928
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:94518.3-94620.6"
- process $proc$libresoc.v:94518$3952
+ attribute \src "libresoc.v:93143.3-93245.6"
+ process $proc$libresoc.v:93143$3896
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_function_unit[12:0] $1\dec31_dec_sub15_function_unit[12:0]
- attribute \src "libresoc.v:94519.5-94519.29"
+ attribute \src "libresoc.v:93144.5-93144.29"
switch \initial
- attribute \src "libresoc.v:94519.9-94519.17"
+ attribute \src "libresoc.v:93144.9-93144.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[12:0]
end
- attribute \src "libresoc.v:94621.3-94723.6"
- process $proc$libresoc.v:94621$3953
+ attribute \src "libresoc.v:93246.3-93348.6"
+ process $proc$libresoc.v:93246$3897
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:94622.5-94622.29"
+ attribute \src "libresoc.v:93247.5-93247.29"
switch \initial
- attribute \src "libresoc.v:94622.9-94622.17"
+ attribute \src "libresoc.v:93247.9-93247.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0]
end
- attribute \src "libresoc.v:94724.3-94826.6"
- process $proc$libresoc.v:94724$3954
+ attribute \src "libresoc.v:93349.3-93451.6"
+ process $proc$libresoc.v:93349$3898
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:94725.5-94725.29"
+ attribute \src "libresoc.v:93350.5-93350.29"
switch \initial
- attribute \src "libresoc.v:94725.9-94725.17"
+ attribute \src "libresoc.v:93350.9-93350.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0]
end
- attribute \src "libresoc.v:94827.3-94929.6"
- process $proc$libresoc.v:94827$3955
+ attribute \src "libresoc.v:93452.3-93554.6"
+ process $proc$libresoc.v:93452$3899
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0]
- attribute \src "libresoc.v:94828.5-94828.29"
+ attribute \src "libresoc.v:93453.5-93453.29"
switch \initial
- attribute \src "libresoc.v:94828.9-94828.17"
+ attribute \src "libresoc.v:93453.9-93453.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0]
end
- attribute \src "libresoc.v:94930.3-95032.6"
- process $proc$libresoc.v:94930$3956
+ attribute \src "libresoc.v:93555.3-93657.6"
+ process $proc$libresoc.v:93555$3900
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0]
- attribute \src "libresoc.v:94931.5-94931.29"
+ attribute \src "libresoc.v:93556.5-93556.29"
switch \initial
- attribute \src "libresoc.v:94931.9-94931.17"
+ attribute \src "libresoc.v:93556.9-93556.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0]
end
- attribute \src "libresoc.v:95033.3-95135.6"
- process $proc$libresoc.v:95033$3957
+ attribute \src "libresoc.v:93658.3-93760.6"
+ process $proc$libresoc.v:93658$3901
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0]
- attribute \src "libresoc.v:95034.5-95034.29"
+ attribute \src "libresoc.v:93659.5-93659.29"
switch \initial
- attribute \src "libresoc.v:95034.9-95034.17"
+ attribute \src "libresoc.v:93659.9-93659.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0]
end
- attribute \src "libresoc.v:95136.3-95238.6"
- process $proc$libresoc.v:95136$3958
+ attribute \src "libresoc.v:93761.3-93863.6"
+ process $proc$libresoc.v:93761$3902
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0]
- attribute \src "libresoc.v:95137.5-95137.29"
+ attribute \src "libresoc.v:93762.5-93762.29"
switch \initial
- attribute \src "libresoc.v:95137.9-95137.17"
+ attribute \src "libresoc.v:93762.9-93762.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0]
end
- attribute \src "libresoc.v:95239.3-95341.6"
- process $proc$libresoc.v:95239$3959
+ attribute \src "libresoc.v:93864.3-93966.6"
+ process $proc$libresoc.v:93864$3903
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0]
- attribute \src "libresoc.v:95240.5-95240.29"
+ attribute \src "libresoc.v:93865.5-93865.29"
switch \initial
- attribute \src "libresoc.v:95240.9-95240.17"
+ attribute \src "libresoc.v:93865.9-93865.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:95342.3-95444.6"
- process $proc$libresoc.v:95342$3960
+ attribute \src "libresoc.v:93967.3-94069.6"
+ process $proc$libresoc.v:93967$3904
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0]
- attribute \src "libresoc.v:95343.5-95343.29"
+ attribute \src "libresoc.v:93968.5-93968.29"
switch \initial
- attribute \src "libresoc.v:95343.9-95343.17"
+ attribute \src "libresoc.v:93968.9-93968.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:95445.3-95547.6"
- process $proc$libresoc.v:95445$3961
+ attribute \src "libresoc.v:94070.3-94172.6"
+ process $proc$libresoc.v:94070$3905
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:95446.5-95446.29"
+ attribute \src "libresoc.v:94071.5-94071.29"
switch \initial
- attribute \src "libresoc.v:95446.9-95446.17"
+ attribute \src "libresoc.v:94071.9-94071.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0]
end
- attribute \src "libresoc.v:95548.3-95650.6"
- process $proc$libresoc.v:95548$3962
+ attribute \src "libresoc.v:94173.3-94275.6"
+ process $proc$libresoc.v:94173$3906
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:95549.5-95549.29"
+ attribute \src "libresoc.v:94174.5-94174.29"
switch \initial
- attribute \src "libresoc.v:95549.9-95549.17"
+ attribute \src "libresoc.v:94174.9-94174.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0]
end
- attribute \src "libresoc.v:95651.3-95753.6"
- process $proc$libresoc.v:95651$3963
+ attribute \src "libresoc.v:94276.3-94378.6"
+ process $proc$libresoc.v:94276$3907
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:95652.5-95652.29"
+ attribute \src "libresoc.v:94277.5-94277.29"
switch \initial
- attribute \src "libresoc.v:95652.9-95652.17"
+ attribute \src "libresoc.v:94277.9-94277.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0]
end
- attribute \src "libresoc.v:95754.3-95856.6"
- process $proc$libresoc.v:95754$3964
+ attribute \src "libresoc.v:94379.3-94481.6"
+ process $proc$libresoc.v:94379$3908
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:95755.5-95755.29"
+ attribute \src "libresoc.v:94380.5-94380.29"
switch \initial
- attribute \src "libresoc.v:95755.9-95755.17"
+ attribute \src "libresoc.v:94380.9-94380.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0]
end
- attribute \src "libresoc.v:95857.3-95959.6"
- process $proc$libresoc.v:95857$3965
+ attribute \src "libresoc.v:94482.3-94584.6"
+ process $proc$libresoc.v:94482$3909
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:95858.5-95858.29"
+ attribute \src "libresoc.v:94483.5-94483.29"
switch \initial
- attribute \src "libresoc.v:95858.9-95858.17"
+ attribute \src "libresoc.v:94483.9-94483.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0]
end
- attribute \src "libresoc.v:95960.3-96062.6"
- process $proc$libresoc.v:95960$3966
+ attribute \src "libresoc.v:94585.3-94687.6"
+ process $proc$libresoc.v:94585$3910
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:95961.5-95961.29"
+ attribute \src "libresoc.v:94586.5-94586.29"
switch \initial
- attribute \src "libresoc.v:95961.9-95961.17"
+ attribute \src "libresoc.v:94586.9-94586.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0]
end
- attribute \src "libresoc.v:96063.3-96165.6"
- process $proc$libresoc.v:96063$3967
+ attribute \src "libresoc.v:94688.3-94790.6"
+ process $proc$libresoc.v:94688$3911
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:96064.5-96064.29"
+ attribute \src "libresoc.v:94689.5-94689.29"
switch \initial
- attribute \src "libresoc.v:96064.9-96064.17"
+ attribute \src "libresoc.v:94689.9-94689.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0]
end
- attribute \src "libresoc.v:96166.3-96268.6"
- process $proc$libresoc.v:96166$3968
+ attribute \src "libresoc.v:94791.3-94893.6"
+ process $proc$libresoc.v:94791$3912
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:96167.5-96167.29"
+ attribute \src "libresoc.v:94792.5-94792.29"
switch \initial
- attribute \src "libresoc.v:96167.9-96167.17"
+ attribute \src "libresoc.v:94792.9-94792.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0]
end
- attribute \src "libresoc.v:96269.3-96371.6"
- process $proc$libresoc.v:96269$3969
+ attribute \src "libresoc.v:94894.3-94996.6"
+ process $proc$libresoc.v:94894$3913
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:96270.5-96270.29"
+ attribute \src "libresoc.v:94895.5-94895.29"
switch \initial
- attribute \src "libresoc.v:96270.9-96270.17"
+ attribute \src "libresoc.v:94895.9-94895.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0]
end
- attribute \src "libresoc.v:96372.3-96474.6"
- process $proc$libresoc.v:96372$3970
+ attribute \src "libresoc.v:94997.3-95099.6"
+ process $proc$libresoc.v:94997$3914
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:96373.5-96373.29"
+ attribute \src "libresoc.v:94998.5-94998.29"
switch \initial
- attribute \src "libresoc.v:96373.9-96373.17"
+ attribute \src "libresoc.v:94998.9-94998.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0]
end
- attribute \src "libresoc.v:96475.3-96577.6"
- process $proc$libresoc.v:96475$3971
+ attribute \src "libresoc.v:95100.3-95202.6"
+ process $proc$libresoc.v:95100$3915
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:96476.5-96476.29"
+ attribute \src "libresoc.v:95101.5-95101.29"
switch \initial
- attribute \src "libresoc.v:96476.9-96476.17"
+ attribute \src "libresoc.v:95101.9-95101.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0]
end
- attribute \src "libresoc.v:96578.3-96680.6"
- process $proc$libresoc.v:96578$3972
+ attribute \src "libresoc.v:95203.3-95305.6"
+ process $proc$libresoc.v:95203$3916
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:96579.5-96579.29"
+ attribute \src "libresoc.v:95204.5-95204.29"
switch \initial
- attribute \src "libresoc.v:96579.9-96579.17"
+ attribute \src "libresoc.v:95204.9-95204.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0]
end
- attribute \src "libresoc.v:96681.3-96783.6"
- process $proc$libresoc.v:96681$3973
+ attribute \src "libresoc.v:95306.3-95408.6"
+ process $proc$libresoc.v:95306$3917
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:96682.5-96682.29"
+ attribute \src "libresoc.v:95307.5-95307.29"
switch \initial
- attribute \src "libresoc.v:96682.9-96682.17"
+ attribute \src "libresoc.v:95307.9-95307.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0]
end
- attribute \src "libresoc.v:96784.3-96886.6"
- process $proc$libresoc.v:96784$3974
+ attribute \src "libresoc.v:95409.3-95511.6"
+ process $proc$libresoc.v:95409$3918
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:96785.5-96785.29"
+ attribute \src "libresoc.v:95410.5-95410.29"
switch \initial
- attribute \src "libresoc.v:96785.9-96785.17"
+ attribute \src "libresoc.v:95410.9-95410.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0]
end
- attribute \src "libresoc.v:96887.3-96989.6"
- process $proc$libresoc.v:96887$3975
+ attribute \src "libresoc.v:95512.3-95614.6"
+ process $proc$libresoc.v:95512$3919
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:96888.5-96888.29"
+ attribute \src "libresoc.v:95513.5-95513.29"
switch \initial
- attribute \src "libresoc.v:96888.9-96888.17"
+ attribute \src "libresoc.v:95513.9-95513.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0]
end
- attribute \src "libresoc.v:96990.3-97092.6"
- process $proc$libresoc.v:96990$3976
+ attribute \src "libresoc.v:95615.3-95717.6"
+ process $proc$libresoc.v:95615$3920
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:96991.5-96991.29"
+ attribute \src "libresoc.v:95616.5-95616.29"
switch \initial
- attribute \src "libresoc.v:96991.9-96991.17"
+ attribute \src "libresoc.v:95616.9-95616.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0]
end
- attribute \src "libresoc.v:97093.3-97195.6"
- process $proc$libresoc.v:97093$3977
+ attribute \src "libresoc.v:95718.3-95820.6"
+ process $proc$libresoc.v:95718$3921
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:97094.5-97094.29"
+ attribute \src "libresoc.v:95719.5-95719.29"
switch \initial
- attribute \src "libresoc.v:97094.9-97094.17"
+ attribute \src "libresoc.v:95719.9-95719.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:97196.3-97298.6"
- process $proc$libresoc.v:97196$3978
+ attribute \src "libresoc.v:95821.3-95923.6"
+ process $proc$libresoc.v:95821$3922
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0]
- attribute \src "libresoc.v:97197.5-97197.29"
+ attribute \src "libresoc.v:95822.5-95822.29"
switch \initial
- attribute \src "libresoc.v:97197.9-97197.17"
+ attribute \src "libresoc.v:95822.9-95822.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0]
end
- attribute \src "libresoc.v:97299.3-97401.6"
- process $proc$libresoc.v:97299$3979
+ attribute \src "libresoc.v:95924.3-96026.6"
+ process $proc$libresoc.v:95924$3923
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0]
- attribute \src "libresoc.v:97300.5-97300.29"
+ attribute \src "libresoc.v:95925.5-95925.29"
switch \initial
- attribute \src "libresoc.v:97300.9-97300.17"
+ attribute \src "libresoc.v:95925.9-95925.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:97402.3-97504.6"
- process $proc$libresoc.v:97402$3980
+ attribute \src "libresoc.v:96027.3-96129.6"
+ process $proc$libresoc.v:96027$3924
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:97403.5-97403.29"
+ attribute \src "libresoc.v:96028.5-96028.29"
switch \initial
- attribute \src "libresoc.v:97403.9-97403.17"
+ attribute \src "libresoc.v:96028.9-96028.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0]
end
- attribute \src "libresoc.v:97505.3-97607.6"
- process $proc$libresoc.v:97505$3981
+ attribute \src "libresoc.v:96130.3-96232.6"
+ process $proc$libresoc.v:96130$3925
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:97506.5-97506.29"
+ attribute \src "libresoc.v:96131.5-96131.29"
switch \initial
- attribute \src "libresoc.v:97506.9-97506.17"
+ attribute \src "libresoc.v:96131.9-96131.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0]
end
- attribute \src "libresoc.v:97608.3-97710.6"
- process $proc$libresoc.v:97608$3982
+ attribute \src "libresoc.v:96233.3-96335.6"
+ process $proc$libresoc.v:96233$3926
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:97609.5-97609.29"
+ attribute \src "libresoc.v:96234.5-96234.29"
switch \initial
- attribute \src "libresoc.v:97609.9-97609.17"
+ attribute \src "libresoc.v:96234.9-96234.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0]
end
- attribute \src "libresoc.v:97711.3-97813.6"
- process $proc$libresoc.v:97711$3983
+ attribute \src "libresoc.v:96336.3-96438.6"
+ process $proc$libresoc.v:96336$3927
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:97712.5-97712.29"
+ attribute \src "libresoc.v:96337.5-96337.29"
switch \initial
- attribute \src "libresoc.v:97712.9-97712.17"
+ attribute \src "libresoc.v:96337.9-96337.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:97819.1-98476.10"
+attribute \src "libresoc.v:96444.1-97101.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16"
attribute \generator "nMigen"
module \dec31_dec_sub16
- attribute \src "libresoc.v:98415.3-98424.6"
+ attribute \src "libresoc.v:97040.3-97049.6"
wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:98425.3-98434.6"
+ attribute \src "libresoc.v:97050.3-97059.6"
wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:98295.3-98304.6"
+ attribute \src "libresoc.v:96920.3-96929.6"
wire width 8 $0\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:98335.3-98344.6"
+ attribute \src "libresoc.v:96960.3-96969.6"
wire $0\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:98165.3-98174.6"
+ attribute \src "libresoc.v:96790.3-96799.6"
wire width 3 $0\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:98175.3-98184.6"
+ attribute \src "libresoc.v:96800.3-96809.6"
wire width 3 $0\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:98285.3-98294.6"
+ attribute \src "libresoc.v:96910.3-96919.6"
wire width 2 $0\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:98325.3-98334.6"
+ attribute \src "libresoc.v:96950.3-96959.6"
wire $0\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:98375.3-98384.6"
+ attribute \src "libresoc.v:97000.3-97009.6"
wire width 5 $0\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:98155.3-98164.6"
+ attribute \src "libresoc.v:96780.3-96789.6"
wire width 13 $0\dec31_dec_sub16_function_unit[12:0]
- attribute \src "libresoc.v:98435.3-98444.6"
+ attribute \src "libresoc.v:97060.3-97069.6"
wire width 3 $0\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:98445.3-98454.6"
+ attribute \src "libresoc.v:97070.3-97079.6"
wire width 4 $0\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:98455.3-98464.6"
+ attribute \src "libresoc.v:97080.3-97089.6"
wire width 2 $0\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:98265.3-98274.6"
+ attribute \src "libresoc.v:96890.3-96899.6"
wire width 7 $0\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:98305.3-98314.6"
+ attribute \src "libresoc.v:96930.3-96939.6"
wire $0\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:98315.3-98324.6"
+ attribute \src "libresoc.v:96940.3-96949.6"
wire $0\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:98365.3-98374.6"
+ attribute \src "libresoc.v:96990.3-96999.6"
wire $0\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:98245.3-98254.6"
+ attribute \src "libresoc.v:96870.3-96879.6"
wire width 4 $0\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:98395.3-98404.6"
+ attribute \src "libresoc.v:97020.3-97029.6"
wire $0\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:98465.3-98474.6"
+ attribute \src "libresoc.v:97090.3-97099.6"
wire width 2 $0\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:98275.3-98284.6"
+ attribute \src "libresoc.v:96900.3-96909.6"
wire width 2 $0\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:98355.3-98364.6"
+ attribute \src "libresoc.v:96980.3-96989.6"
wire $0\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:98405.3-98414.6"
+ attribute \src "libresoc.v:97030.3-97039.6"
wire $0\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:98385.3-98394.6"
+ attribute \src "libresoc.v:97010.3-97019.6"
wire $0\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:98345.3-98354.6"
+ attribute \src "libresoc.v:96970.3-96979.6"
wire $0\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:98225.3-98234.6"
+ attribute \src "libresoc.v:96850.3-96859.6"
wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:98235.3-98244.6"
+ attribute \src "libresoc.v:96860.3-96869.6"
wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:98185.3-98194.6"
+ attribute \src "libresoc.v:96810.3-96819.6"
wire width 3 $0\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:98195.3-98204.6"
+ attribute \src "libresoc.v:96820.3-96829.6"
wire width 3 $0\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:98205.3-98214.6"
+ attribute \src "libresoc.v:96830.3-96839.6"
wire width 3 $0\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:98215.3-98224.6"
+ attribute \src "libresoc.v:96840.3-96849.6"
wire width 3 $0\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:98255.3-98264.6"
+ attribute \src "libresoc.v:96880.3-96889.6"
wire width 2 $0\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:97820.7-97820.20"
+ attribute \src "libresoc.v:96445.7-96445.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:98415.3-98424.6"
+ attribute \src "libresoc.v:97040.3-97049.6"
wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:98425.3-98434.6"
+ attribute \src "libresoc.v:97050.3-97059.6"
wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:98295.3-98304.6"
+ attribute \src "libresoc.v:96920.3-96929.6"
wire width 8 $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:98335.3-98344.6"
+ attribute \src "libresoc.v:96960.3-96969.6"
wire $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:98165.3-98174.6"
+ attribute \src "libresoc.v:96790.3-96799.6"
wire width 3 $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:98175.3-98184.6"
+ attribute \src "libresoc.v:96800.3-96809.6"
wire width 3 $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:98285.3-98294.6"
+ attribute \src "libresoc.v:96910.3-96919.6"
wire width 2 $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:98325.3-98334.6"
+ attribute \src "libresoc.v:96950.3-96959.6"
wire $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:98375.3-98384.6"
+ attribute \src "libresoc.v:97000.3-97009.6"
wire width 5 $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:98155.3-98164.6"
+ attribute \src "libresoc.v:96780.3-96789.6"
wire width 13 $1\dec31_dec_sub16_function_unit[12:0]
- attribute \src "libresoc.v:98435.3-98444.6"
+ attribute \src "libresoc.v:97060.3-97069.6"
wire width 3 $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:98445.3-98454.6"
+ attribute \src "libresoc.v:97070.3-97079.6"
wire width 4 $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:98455.3-98464.6"
+ attribute \src "libresoc.v:97080.3-97089.6"
wire width 2 $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:98265.3-98274.6"
+ attribute \src "libresoc.v:96890.3-96899.6"
wire width 7 $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:98305.3-98314.6"
+ attribute \src "libresoc.v:96930.3-96939.6"
wire $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:98315.3-98324.6"
+ attribute \src "libresoc.v:96940.3-96949.6"
wire $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:98365.3-98374.6"
+ attribute \src "libresoc.v:96990.3-96999.6"
wire $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:98245.3-98254.6"
+ attribute \src "libresoc.v:96870.3-96879.6"
wire width 4 $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:98395.3-98404.6"
+ attribute \src "libresoc.v:97020.3-97029.6"
wire $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:98465.3-98474.6"
+ attribute \src "libresoc.v:97090.3-97099.6"
wire width 2 $1\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:98275.3-98284.6"
+ attribute \src "libresoc.v:96900.3-96909.6"
wire width 2 $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:98355.3-98364.6"
+ attribute \src "libresoc.v:96980.3-96989.6"
wire $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:98405.3-98414.6"
+ attribute \src "libresoc.v:97030.3-97039.6"
wire $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:98385.3-98394.6"
+ attribute \src "libresoc.v:97010.3-97019.6"
wire $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:98345.3-98354.6"
+ attribute \src "libresoc.v:96970.3-96979.6"
wire $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:98225.3-98234.6"
+ attribute \src "libresoc.v:96850.3-96859.6"
wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:98235.3-98244.6"
+ attribute \src "libresoc.v:96860.3-96869.6"
wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:98185.3-98194.6"
+ attribute \src "libresoc.v:96810.3-96819.6"
wire width 3 $1\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:98195.3-98204.6"
+ attribute \src "libresoc.v:96820.3-96829.6"
wire width 3 $1\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:98205.3-98214.6"
+ attribute \src "libresoc.v:96830.3-96839.6"
wire width 3 $1\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:98215.3-98224.6"
+ attribute \src "libresoc.v:96840.3-96849.6"
wire width 3 $1\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:98255.3-98264.6"
+ attribute \src "libresoc.v:96880.3-96889.6"
wire width 2 $1\dec31_dec_sub16_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub16_upd
- attribute \src "libresoc.v:97820.7-97820.15"
+ attribute \src "libresoc.v:96445.7-96445.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:97820.7-97820.20"
- process $proc$libresoc.v:97820$4017
+ attribute \src "libresoc.v:96445.7-96445.20"
+ process $proc$libresoc.v:96445$3961
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:98155.3-98164.6"
- process $proc$libresoc.v:98155$3985
+ attribute \src "libresoc.v:96780.3-96789.6"
+ process $proc$libresoc.v:96780$3929
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_function_unit[12:0] $1\dec31_dec_sub16_function_unit[12:0]
- attribute \src "libresoc.v:98156.5-98156.29"
+ attribute \src "libresoc.v:96781.5-96781.29"
switch \initial
- attribute \src "libresoc.v:98156.9-98156.17"
+ attribute \src "libresoc.v:96781.9-96781.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[12:0]
end
- attribute \src "libresoc.v:98165.3-98174.6"
- process $proc$libresoc.v:98165$3986
+ attribute \src "libresoc.v:96790.3-96799.6"
+ process $proc$libresoc.v:96790$3930
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:98166.5-98166.29"
+ attribute \src "libresoc.v:96791.5-96791.29"
switch \initial
- attribute \src "libresoc.v:98166.9-98166.17"
+ attribute \src "libresoc.v:96791.9-96791.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0]
end
- attribute \src "libresoc.v:98175.3-98184.6"
- process $proc$libresoc.v:98175$3987
+ attribute \src "libresoc.v:96800.3-96809.6"
+ process $proc$libresoc.v:96800$3931
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:98176.5-98176.29"
+ attribute \src "libresoc.v:96801.5-96801.29"
switch \initial
- attribute \src "libresoc.v:98176.9-98176.17"
+ attribute \src "libresoc.v:96801.9-96801.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0]
end
- attribute \src "libresoc.v:98185.3-98194.6"
- process $proc$libresoc.v:98185$3988
+ attribute \src "libresoc.v:96810.3-96819.6"
+ process $proc$libresoc.v:96810$3932
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0]
- attribute \src "libresoc.v:98186.5-98186.29"
+ attribute \src "libresoc.v:96811.5-96811.29"
switch \initial
- attribute \src "libresoc.v:98186.9-98186.17"
+ attribute \src "libresoc.v:96811.9-96811.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0]
end
- attribute \src "libresoc.v:98195.3-98204.6"
- process $proc$libresoc.v:98195$3989
+ attribute \src "libresoc.v:96820.3-96829.6"
+ process $proc$libresoc.v:96820$3933
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0]
- attribute \src "libresoc.v:98196.5-98196.29"
+ attribute \src "libresoc.v:96821.5-96821.29"
switch \initial
- attribute \src "libresoc.v:98196.9-98196.17"
+ attribute \src "libresoc.v:96821.9-96821.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0]
end
- attribute \src "libresoc.v:98205.3-98214.6"
- process $proc$libresoc.v:98205$3990
+ attribute \src "libresoc.v:96830.3-96839.6"
+ process $proc$libresoc.v:96830$3934
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0]
- attribute \src "libresoc.v:98206.5-98206.29"
+ attribute \src "libresoc.v:96831.5-96831.29"
switch \initial
- attribute \src "libresoc.v:98206.9-98206.17"
+ attribute \src "libresoc.v:96831.9-96831.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0]
end
- attribute \src "libresoc.v:98215.3-98224.6"
- process $proc$libresoc.v:98215$3991
+ attribute \src "libresoc.v:96840.3-96849.6"
+ process $proc$libresoc.v:96840$3935
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0]
- attribute \src "libresoc.v:98216.5-98216.29"
+ attribute \src "libresoc.v:96841.5-96841.29"
switch \initial
- attribute \src "libresoc.v:98216.9-98216.17"
+ attribute \src "libresoc.v:96841.9-96841.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0]
end
- attribute \src "libresoc.v:98225.3-98234.6"
- process $proc$libresoc.v:98225$3992
+ attribute \src "libresoc.v:96850.3-96859.6"
+ process $proc$libresoc.v:96850$3936
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0]
- attribute \src "libresoc.v:98226.5-98226.29"
+ attribute \src "libresoc.v:96851.5-96851.29"
switch \initial
- attribute \src "libresoc.v:98226.9-98226.17"
+ attribute \src "libresoc.v:96851.9-96851.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:98235.3-98244.6"
- process $proc$libresoc.v:98235$3993
+ attribute \src "libresoc.v:96860.3-96869.6"
+ process $proc$libresoc.v:96860$3937
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0]
- attribute \src "libresoc.v:98236.5-98236.29"
+ attribute \src "libresoc.v:96861.5-96861.29"
switch \initial
- attribute \src "libresoc.v:98236.9-98236.17"
+ attribute \src "libresoc.v:96861.9-96861.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:98245.3-98254.6"
- process $proc$libresoc.v:98245$3994
+ attribute \src "libresoc.v:96870.3-96879.6"
+ process $proc$libresoc.v:96870$3938
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:98246.5-98246.29"
+ attribute \src "libresoc.v:96871.5-96871.29"
switch \initial
- attribute \src "libresoc.v:98246.9-98246.17"
+ attribute \src "libresoc.v:96871.9-96871.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0]
end
- attribute \src "libresoc.v:98255.3-98264.6"
- process $proc$libresoc.v:98255$3995
+ attribute \src "libresoc.v:96880.3-96889.6"
+ process $proc$libresoc.v:96880$3939
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:98256.5-98256.29"
+ attribute \src "libresoc.v:96881.5-96881.29"
switch \initial
- attribute \src "libresoc.v:98256.9-98256.17"
+ attribute \src "libresoc.v:96881.9-96881.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0]
end
- attribute \src "libresoc.v:98265.3-98274.6"
- process $proc$libresoc.v:98265$3996
+ attribute \src "libresoc.v:96890.3-96899.6"
+ process $proc$libresoc.v:96890$3940
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:98266.5-98266.29"
+ attribute \src "libresoc.v:96891.5-96891.29"
switch \initial
- attribute \src "libresoc.v:98266.9-98266.17"
+ attribute \src "libresoc.v:96891.9-96891.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0]
end
- attribute \src "libresoc.v:98275.3-98284.6"
- process $proc$libresoc.v:98275$3997
+ attribute \src "libresoc.v:96900.3-96909.6"
+ process $proc$libresoc.v:96900$3941
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:98276.5-98276.29"
+ attribute \src "libresoc.v:96901.5-96901.29"
switch \initial
- attribute \src "libresoc.v:98276.9-98276.17"
+ attribute \src "libresoc.v:96901.9-96901.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0]
end
- attribute \src "libresoc.v:98285.3-98294.6"
- process $proc$libresoc.v:98285$3998
+ attribute \src "libresoc.v:96910.3-96919.6"
+ process $proc$libresoc.v:96910$3942
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:98286.5-98286.29"
+ attribute \src "libresoc.v:96911.5-96911.29"
switch \initial
- attribute \src "libresoc.v:98286.9-98286.17"
+ attribute \src "libresoc.v:96911.9-96911.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0]
end
- attribute \src "libresoc.v:98295.3-98304.6"
- process $proc$libresoc.v:98295$3999
+ attribute \src "libresoc.v:96920.3-96929.6"
+ process $proc$libresoc.v:96920$3943
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:98296.5-98296.29"
+ attribute \src "libresoc.v:96921.5-96921.29"
switch \initial
- attribute \src "libresoc.v:98296.9-98296.17"
+ attribute \src "libresoc.v:96921.9-96921.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0]
end
- attribute \src "libresoc.v:98305.3-98314.6"
- process $proc$libresoc.v:98305$4000
+ attribute \src "libresoc.v:96930.3-96939.6"
+ process $proc$libresoc.v:96930$3944
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:98306.5-98306.29"
+ attribute \src "libresoc.v:96931.5-96931.29"
switch \initial
- attribute \src "libresoc.v:98306.9-98306.17"
+ attribute \src "libresoc.v:96931.9-96931.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0]
end
- attribute \src "libresoc.v:98315.3-98324.6"
- process $proc$libresoc.v:98315$4001
+ attribute \src "libresoc.v:96940.3-96949.6"
+ process $proc$libresoc.v:96940$3945
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:98316.5-98316.29"
+ attribute \src "libresoc.v:96941.5-96941.29"
switch \initial
- attribute \src "libresoc.v:98316.9-98316.17"
+ attribute \src "libresoc.v:96941.9-96941.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0]
end
- attribute \src "libresoc.v:98325.3-98334.6"
- process $proc$libresoc.v:98325$4002
+ attribute \src "libresoc.v:96950.3-96959.6"
+ process $proc$libresoc.v:96950$3946
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:98326.5-98326.29"
+ attribute \src "libresoc.v:96951.5-96951.29"
switch \initial
- attribute \src "libresoc.v:98326.9-98326.17"
+ attribute \src "libresoc.v:96951.9-96951.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0]
end
- attribute \src "libresoc.v:98335.3-98344.6"
- process $proc$libresoc.v:98335$4003
+ attribute \src "libresoc.v:96960.3-96969.6"
+ process $proc$libresoc.v:96960$3947
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:98336.5-98336.29"
+ attribute \src "libresoc.v:96961.5-96961.29"
switch \initial
- attribute \src "libresoc.v:98336.9-98336.17"
+ attribute \src "libresoc.v:96961.9-96961.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0]
end
- attribute \src "libresoc.v:98345.3-98354.6"
- process $proc$libresoc.v:98345$4004
+ attribute \src "libresoc.v:96970.3-96979.6"
+ process $proc$libresoc.v:96970$3948
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:98346.5-98346.29"
+ attribute \src "libresoc.v:96971.5-96971.29"
switch \initial
- attribute \src "libresoc.v:98346.9-98346.17"
+ attribute \src "libresoc.v:96971.9-96971.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0]
end
- attribute \src "libresoc.v:98355.3-98364.6"
- process $proc$libresoc.v:98355$4005
+ attribute \src "libresoc.v:96980.3-96989.6"
+ process $proc$libresoc.v:96980$3949
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:98356.5-98356.29"
+ attribute \src "libresoc.v:96981.5-96981.29"
switch \initial
- attribute \src "libresoc.v:98356.9-98356.17"
+ attribute \src "libresoc.v:96981.9-96981.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0]
end
- attribute \src "libresoc.v:98365.3-98374.6"
- process $proc$libresoc.v:98365$4006
+ attribute \src "libresoc.v:96990.3-96999.6"
+ process $proc$libresoc.v:96990$3950
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:98366.5-98366.29"
+ attribute \src "libresoc.v:96991.5-96991.29"
switch \initial
- attribute \src "libresoc.v:98366.9-98366.17"
+ attribute \src "libresoc.v:96991.9-96991.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0]
end
- attribute \src "libresoc.v:98375.3-98384.6"
- process $proc$libresoc.v:98375$4007
+ attribute \src "libresoc.v:97000.3-97009.6"
+ process $proc$libresoc.v:97000$3951
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:98376.5-98376.29"
+ attribute \src "libresoc.v:97001.5-97001.29"
switch \initial
- attribute \src "libresoc.v:98376.9-98376.17"
+ attribute \src "libresoc.v:97001.9-97001.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0]
end
- attribute \src "libresoc.v:98385.3-98394.6"
- process $proc$libresoc.v:98385$4008
+ attribute \src "libresoc.v:97010.3-97019.6"
+ process $proc$libresoc.v:97010$3952
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:98386.5-98386.29"
+ attribute \src "libresoc.v:97011.5-97011.29"
switch \initial
- attribute \src "libresoc.v:98386.9-98386.17"
+ attribute \src "libresoc.v:97011.9-97011.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0]
end
- attribute \src "libresoc.v:98395.3-98404.6"
- process $proc$libresoc.v:98395$4009
+ attribute \src "libresoc.v:97020.3-97029.6"
+ process $proc$libresoc.v:97020$3953
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:98396.5-98396.29"
+ attribute \src "libresoc.v:97021.5-97021.29"
switch \initial
- attribute \src "libresoc.v:98396.9-98396.17"
+ attribute \src "libresoc.v:97021.9-97021.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0]
end
- attribute \src "libresoc.v:98405.3-98414.6"
- process $proc$libresoc.v:98405$4010
+ attribute \src "libresoc.v:97030.3-97039.6"
+ process $proc$libresoc.v:97030$3954
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:98406.5-98406.29"
+ attribute \src "libresoc.v:97031.5-97031.29"
switch \initial
- attribute \src "libresoc.v:98406.9-98406.17"
+ attribute \src "libresoc.v:97031.9-97031.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:98415.3-98424.6"
- process $proc$libresoc.v:98415$4011
+ attribute \src "libresoc.v:97040.3-97049.6"
+ process $proc$libresoc.v:97040$3955
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0]
- attribute \src "libresoc.v:98416.5-98416.29"
+ attribute \src "libresoc.v:97041.5-97041.29"
switch \initial
- attribute \src "libresoc.v:98416.9-98416.17"
+ attribute \src "libresoc.v:97041.9-97041.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0]
end
- attribute \src "libresoc.v:98425.3-98434.6"
- process $proc$libresoc.v:98425$4012
+ attribute \src "libresoc.v:97050.3-97059.6"
+ process $proc$libresoc.v:97050$3956
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0]
- attribute \src "libresoc.v:98426.5-98426.29"
+ attribute \src "libresoc.v:97051.5-97051.29"
switch \initial
- attribute \src "libresoc.v:98426.9-98426.17"
+ attribute \src "libresoc.v:97051.9-97051.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:98435.3-98444.6"
- process $proc$libresoc.v:98435$4013
+ attribute \src "libresoc.v:97060.3-97069.6"
+ process $proc$libresoc.v:97060$3957
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:98436.5-98436.29"
+ attribute \src "libresoc.v:97061.5-97061.29"
switch \initial
- attribute \src "libresoc.v:98436.9-98436.17"
+ attribute \src "libresoc.v:97061.9-97061.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0]
end
- attribute \src "libresoc.v:98445.3-98454.6"
- process $proc$libresoc.v:98445$4014
+ attribute \src "libresoc.v:97070.3-97079.6"
+ process $proc$libresoc.v:97070$3958
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:98446.5-98446.29"
+ attribute \src "libresoc.v:97071.5-97071.29"
switch \initial
- attribute \src "libresoc.v:98446.9-98446.17"
+ attribute \src "libresoc.v:97071.9-97071.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0]
end
- attribute \src "libresoc.v:98455.3-98464.6"
- process $proc$libresoc.v:98455$4015
+ attribute \src "libresoc.v:97080.3-97089.6"
+ process $proc$libresoc.v:97080$3959
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:98456.5-98456.29"
+ attribute \src "libresoc.v:97081.5-97081.29"
switch \initial
- attribute \src "libresoc.v:98456.9-98456.17"
+ attribute \src "libresoc.v:97081.9-97081.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0]
end
- attribute \src "libresoc.v:98465.3-98474.6"
- process $proc$libresoc.v:98465$4016
+ attribute \src "libresoc.v:97090.3-97099.6"
+ process $proc$libresoc.v:97090$3960
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:98466.5-98466.29"
+ attribute \src "libresoc.v:97091.5-97091.29"
switch \initial
- attribute \src "libresoc.v:98466.9-98466.17"
+ attribute \src "libresoc.v:97091.9-97091.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:98480.1-99521.10"
+attribute \src "libresoc.v:97105.1-98146.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18"
attribute \generator "nMigen"
module \dec31_dec_sub18
- attribute \src "libresoc.v:99388.3-99409.6"
+ attribute \src "libresoc.v:98013.3-98034.6"
wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:99410.3-99431.6"
+ attribute \src "libresoc.v:98035.3-98056.6"
wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:99124.3-99145.6"
+ attribute \src "libresoc.v:97749.3-97770.6"
wire width 8 $0\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:99212.3-99233.6"
+ attribute \src "libresoc.v:97837.3-97858.6"
wire $0\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:98838.3-98859.6"
+ attribute \src "libresoc.v:97463.3-97484.6"
wire width 3 $0\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:98860.3-98881.6"
+ attribute \src "libresoc.v:97485.3-97506.6"
wire width 3 $0\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:99102.3-99123.6"
+ attribute \src "libresoc.v:97727.3-97748.6"
wire width 2 $0\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:99190.3-99211.6"
+ attribute \src "libresoc.v:97815.3-97836.6"
wire $0\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:99300.3-99321.6"
+ attribute \src "libresoc.v:97925.3-97946.6"
wire width 5 $0\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:98816.3-98837.6"
+ attribute \src "libresoc.v:97441.3-97462.6"
wire width 13 $0\dec31_dec_sub18_function_unit[12:0]
- attribute \src "libresoc.v:99432.3-99453.6"
+ attribute \src "libresoc.v:98057.3-98078.6"
wire width 3 $0\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:99454.3-99475.6"
+ attribute \src "libresoc.v:98079.3-98100.6"
wire width 4 $0\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:99476.3-99497.6"
+ attribute \src "libresoc.v:98101.3-98122.6"
wire width 2 $0\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:99058.3-99079.6"
+ attribute \src "libresoc.v:97683.3-97704.6"
wire width 7 $0\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:99146.3-99167.6"
+ attribute \src "libresoc.v:97771.3-97792.6"
wire $0\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:99168.3-99189.6"
+ attribute \src "libresoc.v:97793.3-97814.6"
wire $0\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:99278.3-99299.6"
+ attribute \src "libresoc.v:97903.3-97924.6"
wire $0\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:99014.3-99035.6"
+ attribute \src "libresoc.v:97639.3-97660.6"
wire width 4 $0\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:99344.3-99365.6"
+ attribute \src "libresoc.v:97969.3-97990.6"
wire $0\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:99498.3-99519.6"
+ attribute \src "libresoc.v:98123.3-98144.6"
wire width 2 $0\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:99080.3-99101.6"
+ attribute \src "libresoc.v:97705.3-97726.6"
wire width 2 $0\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:99256.3-99277.6"
+ attribute \src "libresoc.v:97881.3-97902.6"
wire $0\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:99366.3-99387.6"
+ attribute \src "libresoc.v:97991.3-98012.6"
wire $0\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:99322.3-99343.6"
+ attribute \src "libresoc.v:97947.3-97968.6"
wire $0\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:99234.3-99255.6"
+ attribute \src "libresoc.v:97859.3-97880.6"
wire $0\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:98970.3-98991.6"
+ attribute \src "libresoc.v:97595.3-97616.6"
wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:98992.3-99013.6"
+ attribute \src "libresoc.v:97617.3-97638.6"
wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:98882.3-98903.6"
+ attribute \src "libresoc.v:97507.3-97528.6"
wire width 3 $0\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:98904.3-98925.6"
+ attribute \src "libresoc.v:97529.3-97550.6"
wire width 3 $0\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:98926.3-98947.6"
+ attribute \src "libresoc.v:97551.3-97572.6"
wire width 3 $0\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:98948.3-98969.6"
+ attribute \src "libresoc.v:97573.3-97594.6"
wire width 3 $0\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:99036.3-99057.6"
+ attribute \src "libresoc.v:97661.3-97682.6"
wire width 2 $0\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:98481.7-98481.20"
+ attribute \src "libresoc.v:97106.7-97106.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:99388.3-99409.6"
+ attribute \src "libresoc.v:98013.3-98034.6"
wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:99410.3-99431.6"
+ attribute \src "libresoc.v:98035.3-98056.6"
wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:99124.3-99145.6"
+ attribute \src "libresoc.v:97749.3-97770.6"
wire width 8 $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:99212.3-99233.6"
+ attribute \src "libresoc.v:97837.3-97858.6"
wire $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:98838.3-98859.6"
+ attribute \src "libresoc.v:97463.3-97484.6"
wire width 3 $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:98860.3-98881.6"
+ attribute \src "libresoc.v:97485.3-97506.6"
wire width 3 $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:99102.3-99123.6"
+ attribute \src "libresoc.v:97727.3-97748.6"
wire width 2 $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:99190.3-99211.6"
+ attribute \src "libresoc.v:97815.3-97836.6"
wire $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:99300.3-99321.6"
+ attribute \src "libresoc.v:97925.3-97946.6"
wire width 5 $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:98816.3-98837.6"
+ attribute \src "libresoc.v:97441.3-97462.6"
wire width 13 $1\dec31_dec_sub18_function_unit[12:0]
- attribute \src "libresoc.v:99432.3-99453.6"
+ attribute \src "libresoc.v:98057.3-98078.6"
wire width 3 $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:99454.3-99475.6"
+ attribute \src "libresoc.v:98079.3-98100.6"
wire width 4 $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:99476.3-99497.6"
+ attribute \src "libresoc.v:98101.3-98122.6"
wire width 2 $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:99058.3-99079.6"
+ attribute \src "libresoc.v:97683.3-97704.6"
wire width 7 $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:99146.3-99167.6"
+ attribute \src "libresoc.v:97771.3-97792.6"
wire $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:99168.3-99189.6"
+ attribute \src "libresoc.v:97793.3-97814.6"
wire $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:99278.3-99299.6"
+ attribute \src "libresoc.v:97903.3-97924.6"
wire $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:99014.3-99035.6"
+ attribute \src "libresoc.v:97639.3-97660.6"
wire width 4 $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:99344.3-99365.6"
+ attribute \src "libresoc.v:97969.3-97990.6"
wire $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:99498.3-99519.6"
+ attribute \src "libresoc.v:98123.3-98144.6"
wire width 2 $1\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:99080.3-99101.6"
+ attribute \src "libresoc.v:97705.3-97726.6"
wire width 2 $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:99256.3-99277.6"
+ attribute \src "libresoc.v:97881.3-97902.6"
wire $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:99366.3-99387.6"
+ attribute \src "libresoc.v:97991.3-98012.6"
wire $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:99322.3-99343.6"
+ attribute \src "libresoc.v:97947.3-97968.6"
wire $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:99234.3-99255.6"
+ attribute \src "libresoc.v:97859.3-97880.6"
wire $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:98970.3-98991.6"
+ attribute \src "libresoc.v:97595.3-97616.6"
wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:98992.3-99013.6"
+ attribute \src "libresoc.v:97617.3-97638.6"
wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:98882.3-98903.6"
+ attribute \src "libresoc.v:97507.3-97528.6"
wire width 3 $1\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:98904.3-98925.6"
+ attribute \src "libresoc.v:97529.3-97550.6"
wire width 3 $1\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:98926.3-98947.6"
+ attribute \src "libresoc.v:97551.3-97572.6"
wire width 3 $1\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:98948.3-98969.6"
+ attribute \src "libresoc.v:97573.3-97594.6"
wire width 3 $1\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:99036.3-99057.6"
+ attribute \src "libresoc.v:97661.3-97682.6"
wire width 2 $1\dec31_dec_sub18_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub18_upd
- attribute \src "libresoc.v:98481.7-98481.15"
+ attribute \src "libresoc.v:97106.7-97106.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:98481.7-98481.20"
- process $proc$libresoc.v:98481$4050
+ attribute \src "libresoc.v:97106.7-97106.20"
+ process $proc$libresoc.v:97106$3994
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:98816.3-98837.6"
- process $proc$libresoc.v:98816$4018
+ attribute \src "libresoc.v:97441.3-97462.6"
+ process $proc$libresoc.v:97441$3962
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_function_unit[12:0] $1\dec31_dec_sub18_function_unit[12:0]
- attribute \src "libresoc.v:98817.5-98817.29"
+ attribute \src "libresoc.v:97442.5-97442.29"
switch \initial
- attribute \src "libresoc.v:98817.9-98817.17"
+ attribute \src "libresoc.v:97442.9-97442.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[12:0]
end
- attribute \src "libresoc.v:98838.3-98859.6"
- process $proc$libresoc.v:98838$4019
+ attribute \src "libresoc.v:97463.3-97484.6"
+ process $proc$libresoc.v:97463$3963
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:98839.5-98839.29"
+ attribute \src "libresoc.v:97464.5-97464.29"
switch \initial
- attribute \src "libresoc.v:98839.9-98839.17"
+ attribute \src "libresoc.v:97464.9-97464.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0]
end
- attribute \src "libresoc.v:98860.3-98881.6"
- process $proc$libresoc.v:98860$4020
+ attribute \src "libresoc.v:97485.3-97506.6"
+ process $proc$libresoc.v:97485$3964
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:98861.5-98861.29"
+ attribute \src "libresoc.v:97486.5-97486.29"
switch \initial
- attribute \src "libresoc.v:98861.9-98861.17"
+ attribute \src "libresoc.v:97486.9-97486.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0]
end
- attribute \src "libresoc.v:98882.3-98903.6"
- process $proc$libresoc.v:98882$4021
+ attribute \src "libresoc.v:97507.3-97528.6"
+ process $proc$libresoc.v:97507$3965
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0]
- attribute \src "libresoc.v:98883.5-98883.29"
+ attribute \src "libresoc.v:97508.5-97508.29"
switch \initial
- attribute \src "libresoc.v:98883.9-98883.17"
+ attribute \src "libresoc.v:97508.9-97508.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0]
end
- attribute \src "libresoc.v:98904.3-98925.6"
- process $proc$libresoc.v:98904$4022
+ attribute \src "libresoc.v:97529.3-97550.6"
+ process $proc$libresoc.v:97529$3966
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0]
- attribute \src "libresoc.v:98905.5-98905.29"
+ attribute \src "libresoc.v:97530.5-97530.29"
switch \initial
- attribute \src "libresoc.v:98905.9-98905.17"
+ attribute \src "libresoc.v:97530.9-97530.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0]
end
- attribute \src "libresoc.v:98926.3-98947.6"
- process $proc$libresoc.v:98926$4023
+ attribute \src "libresoc.v:97551.3-97572.6"
+ process $proc$libresoc.v:97551$3967
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0]
- attribute \src "libresoc.v:98927.5-98927.29"
+ attribute \src "libresoc.v:97552.5-97552.29"
switch \initial
- attribute \src "libresoc.v:98927.9-98927.17"
+ attribute \src "libresoc.v:97552.9-97552.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0]
end
- attribute \src "libresoc.v:98948.3-98969.6"
- process $proc$libresoc.v:98948$4024
+ attribute \src "libresoc.v:97573.3-97594.6"
+ process $proc$libresoc.v:97573$3968
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0]
- attribute \src "libresoc.v:98949.5-98949.29"
+ attribute \src "libresoc.v:97574.5-97574.29"
switch \initial
- attribute \src "libresoc.v:98949.9-98949.17"
+ attribute \src "libresoc.v:97574.9-97574.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0]
end
- attribute \src "libresoc.v:98970.3-98991.6"
- process $proc$libresoc.v:98970$4025
+ attribute \src "libresoc.v:97595.3-97616.6"
+ process $proc$libresoc.v:97595$3969
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0]
- attribute \src "libresoc.v:98971.5-98971.29"
+ attribute \src "libresoc.v:97596.5-97596.29"
switch \initial
- attribute \src "libresoc.v:98971.9-98971.17"
+ attribute \src "libresoc.v:97596.9-97596.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:98992.3-99013.6"
- process $proc$libresoc.v:98992$4026
+ attribute \src "libresoc.v:97617.3-97638.6"
+ process $proc$libresoc.v:97617$3970
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0]
- attribute \src "libresoc.v:98993.5-98993.29"
+ attribute \src "libresoc.v:97618.5-97618.29"
switch \initial
- attribute \src "libresoc.v:98993.9-98993.17"
+ attribute \src "libresoc.v:97618.9-97618.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:99014.3-99035.6"
- process $proc$libresoc.v:99014$4027
+ attribute \src "libresoc.v:97639.3-97660.6"
+ process $proc$libresoc.v:97639$3971
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:99015.5-99015.29"
+ attribute \src "libresoc.v:97640.5-97640.29"
switch \initial
- attribute \src "libresoc.v:99015.9-99015.17"
+ attribute \src "libresoc.v:97640.9-97640.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0]
end
- attribute \src "libresoc.v:99036.3-99057.6"
- process $proc$libresoc.v:99036$4028
+ attribute \src "libresoc.v:97661.3-97682.6"
+ process $proc$libresoc.v:97661$3972
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:99037.5-99037.29"
+ attribute \src "libresoc.v:97662.5-97662.29"
switch \initial
- attribute \src "libresoc.v:99037.9-99037.17"
+ attribute \src "libresoc.v:97662.9-97662.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0]
end
- attribute \src "libresoc.v:99058.3-99079.6"
- process $proc$libresoc.v:99058$4029
+ attribute \src "libresoc.v:97683.3-97704.6"
+ process $proc$libresoc.v:97683$3973
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:99059.5-99059.29"
+ attribute \src "libresoc.v:97684.5-97684.29"
switch \initial
- attribute \src "libresoc.v:99059.9-99059.17"
+ attribute \src "libresoc.v:97684.9-97684.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0]
end
- attribute \src "libresoc.v:99080.3-99101.6"
- process $proc$libresoc.v:99080$4030
+ attribute \src "libresoc.v:97705.3-97726.6"
+ process $proc$libresoc.v:97705$3974
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:99081.5-99081.29"
+ attribute \src "libresoc.v:97706.5-97706.29"
switch \initial
- attribute \src "libresoc.v:99081.9-99081.17"
+ attribute \src "libresoc.v:97706.9-97706.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0]
end
- attribute \src "libresoc.v:99102.3-99123.6"
- process $proc$libresoc.v:99102$4031
+ attribute \src "libresoc.v:97727.3-97748.6"
+ process $proc$libresoc.v:97727$3975
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:99103.5-99103.29"
+ attribute \src "libresoc.v:97728.5-97728.29"
switch \initial
- attribute \src "libresoc.v:99103.9-99103.17"
+ attribute \src "libresoc.v:97728.9-97728.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0]
end
- attribute \src "libresoc.v:99124.3-99145.6"
- process $proc$libresoc.v:99124$4032
+ attribute \src "libresoc.v:97749.3-97770.6"
+ process $proc$libresoc.v:97749$3976
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:99125.5-99125.29"
+ attribute \src "libresoc.v:97750.5-97750.29"
switch \initial
- attribute \src "libresoc.v:99125.9-99125.17"
+ attribute \src "libresoc.v:97750.9-97750.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0]
end
- attribute \src "libresoc.v:99146.3-99167.6"
- process $proc$libresoc.v:99146$4033
+ attribute \src "libresoc.v:97771.3-97792.6"
+ process $proc$libresoc.v:97771$3977
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:99147.5-99147.29"
+ attribute \src "libresoc.v:97772.5-97772.29"
switch \initial
- attribute \src "libresoc.v:99147.9-99147.17"
+ attribute \src "libresoc.v:97772.9-97772.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0]
end
- attribute \src "libresoc.v:99168.3-99189.6"
- process $proc$libresoc.v:99168$4034
+ attribute \src "libresoc.v:97793.3-97814.6"
+ process $proc$libresoc.v:97793$3978
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:99169.5-99169.29"
+ attribute \src "libresoc.v:97794.5-97794.29"
switch \initial
- attribute \src "libresoc.v:99169.9-99169.17"
+ attribute \src "libresoc.v:97794.9-97794.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0]
end
- attribute \src "libresoc.v:99190.3-99211.6"
- process $proc$libresoc.v:99190$4035
+ attribute \src "libresoc.v:97815.3-97836.6"
+ process $proc$libresoc.v:97815$3979
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:99191.5-99191.29"
+ attribute \src "libresoc.v:97816.5-97816.29"
switch \initial
- attribute \src "libresoc.v:99191.9-99191.17"
+ attribute \src "libresoc.v:97816.9-97816.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0]
end
- attribute \src "libresoc.v:99212.3-99233.6"
- process $proc$libresoc.v:99212$4036
+ attribute \src "libresoc.v:97837.3-97858.6"
+ process $proc$libresoc.v:97837$3980
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:99213.5-99213.29"
+ attribute \src "libresoc.v:97838.5-97838.29"
switch \initial
- attribute \src "libresoc.v:99213.9-99213.17"
+ attribute \src "libresoc.v:97838.9-97838.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0]
end
- attribute \src "libresoc.v:99234.3-99255.6"
- process $proc$libresoc.v:99234$4037
+ attribute \src "libresoc.v:97859.3-97880.6"
+ process $proc$libresoc.v:97859$3981
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:99235.5-99235.29"
+ attribute \src "libresoc.v:97860.5-97860.29"
switch \initial
- attribute \src "libresoc.v:99235.9-99235.17"
+ attribute \src "libresoc.v:97860.9-97860.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0]
end
- attribute \src "libresoc.v:99256.3-99277.6"
- process $proc$libresoc.v:99256$4038
+ attribute \src "libresoc.v:97881.3-97902.6"
+ process $proc$libresoc.v:97881$3982
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:99257.5-99257.29"
+ attribute \src "libresoc.v:97882.5-97882.29"
switch \initial
- attribute \src "libresoc.v:99257.9-99257.17"
+ attribute \src "libresoc.v:97882.9-97882.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0]
end
- attribute \src "libresoc.v:99278.3-99299.6"
- process $proc$libresoc.v:99278$4039
+ attribute \src "libresoc.v:97903.3-97924.6"
+ process $proc$libresoc.v:97903$3983
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:99279.5-99279.29"
+ attribute \src "libresoc.v:97904.5-97904.29"
switch \initial
- attribute \src "libresoc.v:99279.9-99279.17"
+ attribute \src "libresoc.v:97904.9-97904.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0]
end
- attribute \src "libresoc.v:99300.3-99321.6"
- process $proc$libresoc.v:99300$4040
+ attribute \src "libresoc.v:97925.3-97946.6"
+ process $proc$libresoc.v:97925$3984
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:99301.5-99301.29"
+ attribute \src "libresoc.v:97926.5-97926.29"
switch \initial
- attribute \src "libresoc.v:99301.9-99301.17"
+ attribute \src "libresoc.v:97926.9-97926.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0]
end
- attribute \src "libresoc.v:99322.3-99343.6"
- process $proc$libresoc.v:99322$4041
+ attribute \src "libresoc.v:97947.3-97968.6"
+ process $proc$libresoc.v:97947$3985
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:99323.5-99323.29"
+ attribute \src "libresoc.v:97948.5-97948.29"
switch \initial
- attribute \src "libresoc.v:99323.9-99323.17"
+ attribute \src "libresoc.v:97948.9-97948.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0]
end
- attribute \src "libresoc.v:99344.3-99365.6"
- process $proc$libresoc.v:99344$4042
+ attribute \src "libresoc.v:97969.3-97990.6"
+ process $proc$libresoc.v:97969$3986
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:99345.5-99345.29"
+ attribute \src "libresoc.v:97970.5-97970.29"
switch \initial
- attribute \src "libresoc.v:99345.9-99345.17"
+ attribute \src "libresoc.v:97970.9-97970.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0]
end
- attribute \src "libresoc.v:99366.3-99387.6"
- process $proc$libresoc.v:99366$4043
+ attribute \src "libresoc.v:97991.3-98012.6"
+ process $proc$libresoc.v:97991$3987
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:99367.5-99367.29"
+ attribute \src "libresoc.v:97992.5-97992.29"
switch \initial
- attribute \src "libresoc.v:99367.9-99367.17"
+ attribute \src "libresoc.v:97992.9-97992.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:99388.3-99409.6"
- process $proc$libresoc.v:99388$4044
+ attribute \src "libresoc.v:98013.3-98034.6"
+ process $proc$libresoc.v:98013$3988
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0]
- attribute \src "libresoc.v:99389.5-99389.29"
+ attribute \src "libresoc.v:98014.5-98014.29"
switch \initial
- attribute \src "libresoc.v:99389.9-99389.17"
+ attribute \src "libresoc.v:98014.9-98014.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0]
end
- attribute \src "libresoc.v:99410.3-99431.6"
- process $proc$libresoc.v:99410$4045
+ attribute \src "libresoc.v:98035.3-98056.6"
+ process $proc$libresoc.v:98035$3989
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0]
- attribute \src "libresoc.v:99411.5-99411.29"
+ attribute \src "libresoc.v:98036.5-98036.29"
switch \initial
- attribute \src "libresoc.v:99411.9-99411.17"
+ attribute \src "libresoc.v:98036.9-98036.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:99432.3-99453.6"
- process $proc$libresoc.v:99432$4046
+ attribute \src "libresoc.v:98057.3-98078.6"
+ process $proc$libresoc.v:98057$3990
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:99433.5-99433.29"
+ attribute \src "libresoc.v:98058.5-98058.29"
switch \initial
- attribute \src "libresoc.v:99433.9-99433.17"
+ attribute \src "libresoc.v:98058.9-98058.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0]
end
- attribute \src "libresoc.v:99454.3-99475.6"
- process $proc$libresoc.v:99454$4047
+ attribute \src "libresoc.v:98079.3-98100.6"
+ process $proc$libresoc.v:98079$3991
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:99455.5-99455.29"
+ attribute \src "libresoc.v:98080.5-98080.29"
switch \initial
- attribute \src "libresoc.v:99455.9-99455.17"
+ attribute \src "libresoc.v:98080.9-98080.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0]
end
- attribute \src "libresoc.v:99476.3-99497.6"
- process $proc$libresoc.v:99476$4048
+ attribute \src "libresoc.v:98101.3-98122.6"
+ process $proc$libresoc.v:98101$3992
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:99477.5-99477.29"
+ attribute \src "libresoc.v:98102.5-98102.29"
switch \initial
- attribute \src "libresoc.v:99477.9-99477.17"
+ attribute \src "libresoc.v:98102.9-98102.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0]
end
- attribute \src "libresoc.v:99498.3-99519.6"
- process $proc$libresoc.v:99498$4049
+ attribute \src "libresoc.v:98123.3-98144.6"
+ process $proc$libresoc.v:98123$3993
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:99499.5-99499.29"
+ attribute \src "libresoc.v:98124.5-98124.29"
switch \initial
- attribute \src "libresoc.v:99499.9-99499.17"
+ attribute \src "libresoc.v:98124.9-98124.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:99525.1-100470.10"
+attribute \src "libresoc.v:98150.1-99095.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19"
attribute \generator "nMigen"
module \dec31_dec_sub19
- attribute \src "libresoc.v:100355.3-100373.6"
+ attribute \src "libresoc.v:98980.3-98998.6"
wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:100374.3-100392.6"
+ attribute \src "libresoc.v:98999.3-99017.6"
wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:100127.3-100145.6"
+ attribute \src "libresoc.v:98752.3-98770.6"
wire width 8 $0\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:100203.3-100221.6"
+ attribute \src "libresoc.v:98828.3-98846.6"
wire $0\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:99880.3-99898.6"
+ attribute \src "libresoc.v:98505.3-98523.6"
wire width 3 $0\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:99899.3-99917.6"
+ attribute \src "libresoc.v:98524.3-98542.6"
wire width 3 $0\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:100108.3-100126.6"
+ attribute \src "libresoc.v:98733.3-98751.6"
wire width 2 $0\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:100184.3-100202.6"
+ attribute \src "libresoc.v:98809.3-98827.6"
wire $0\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:100279.3-100297.6"
+ attribute \src "libresoc.v:98904.3-98922.6"
wire width 5 $0\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:99861.3-99879.6"
+ attribute \src "libresoc.v:98486.3-98504.6"
wire width 13 $0\dec31_dec_sub19_function_unit[12:0]
- attribute \src "libresoc.v:100393.3-100411.6"
+ attribute \src "libresoc.v:99018.3-99036.6"
wire width 3 $0\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:100412.3-100430.6"
+ attribute \src "libresoc.v:99037.3-99055.6"
wire width 4 $0\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:100431.3-100449.6"
+ attribute \src "libresoc.v:99056.3-99074.6"
wire width 2 $0\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:100070.3-100088.6"
+ attribute \src "libresoc.v:98695.3-98713.6"
wire width 7 $0\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:100146.3-100164.6"
+ attribute \src "libresoc.v:98771.3-98789.6"
wire $0\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:100165.3-100183.6"
+ attribute \src "libresoc.v:98790.3-98808.6"
wire $0\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:100260.3-100278.6"
+ attribute \src "libresoc.v:98885.3-98903.6"
wire $0\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:100032.3-100050.6"
+ attribute \src "libresoc.v:98657.3-98675.6"
wire width 4 $0\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:100317.3-100335.6"
+ attribute \src "libresoc.v:98942.3-98960.6"
wire $0\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:100450.3-100468.6"
+ attribute \src "libresoc.v:99075.3-99093.6"
wire width 2 $0\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:100089.3-100107.6"
+ attribute \src "libresoc.v:98714.3-98732.6"
wire width 2 $0\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:100241.3-100259.6"
+ attribute \src "libresoc.v:98866.3-98884.6"
wire $0\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:100336.3-100354.6"
+ attribute \src "libresoc.v:98961.3-98979.6"
wire $0\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:100298.3-100316.6"
+ attribute \src "libresoc.v:98923.3-98941.6"
wire $0\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:100222.3-100240.6"
+ attribute \src "libresoc.v:98847.3-98865.6"
wire $0\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:99994.3-100012.6"
+ attribute \src "libresoc.v:98619.3-98637.6"
wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:100013.3-100031.6"
+ attribute \src "libresoc.v:98638.3-98656.6"
wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:99918.3-99936.6"
+ attribute \src "libresoc.v:98543.3-98561.6"
wire width 3 $0\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:99937.3-99955.6"
+ attribute \src "libresoc.v:98562.3-98580.6"
wire width 3 $0\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:99956.3-99974.6"
+ attribute \src "libresoc.v:98581.3-98599.6"
wire width 3 $0\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:99975.3-99993.6"
+ attribute \src "libresoc.v:98600.3-98618.6"
wire width 3 $0\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:100051.3-100069.6"
+ attribute \src "libresoc.v:98676.3-98694.6"
wire width 2 $0\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:99526.7-99526.20"
+ attribute \src "libresoc.v:98151.7-98151.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:100355.3-100373.6"
+ attribute \src "libresoc.v:98980.3-98998.6"
wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:100374.3-100392.6"
+ attribute \src "libresoc.v:98999.3-99017.6"
wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:100127.3-100145.6"
+ attribute \src "libresoc.v:98752.3-98770.6"
wire width 8 $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:100203.3-100221.6"
+ attribute \src "libresoc.v:98828.3-98846.6"
wire $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:99880.3-99898.6"
+ attribute \src "libresoc.v:98505.3-98523.6"
wire width 3 $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:99899.3-99917.6"
+ attribute \src "libresoc.v:98524.3-98542.6"
wire width 3 $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:100108.3-100126.6"
+ attribute \src "libresoc.v:98733.3-98751.6"
wire width 2 $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:100184.3-100202.6"
+ attribute \src "libresoc.v:98809.3-98827.6"
wire $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:100279.3-100297.6"
+ attribute \src "libresoc.v:98904.3-98922.6"
wire width 5 $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:99861.3-99879.6"
+ attribute \src "libresoc.v:98486.3-98504.6"
wire width 13 $1\dec31_dec_sub19_function_unit[12:0]
- attribute \src "libresoc.v:100393.3-100411.6"
+ attribute \src "libresoc.v:99018.3-99036.6"
wire width 3 $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:100412.3-100430.6"
+ attribute \src "libresoc.v:99037.3-99055.6"
wire width 4 $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:100431.3-100449.6"
+ attribute \src "libresoc.v:99056.3-99074.6"
wire width 2 $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:100070.3-100088.6"
+ attribute \src "libresoc.v:98695.3-98713.6"
wire width 7 $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:100146.3-100164.6"
+ attribute \src "libresoc.v:98771.3-98789.6"
wire $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:100165.3-100183.6"
+ attribute \src "libresoc.v:98790.3-98808.6"
wire $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:100260.3-100278.6"
+ attribute \src "libresoc.v:98885.3-98903.6"
wire $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:100032.3-100050.6"
+ attribute \src "libresoc.v:98657.3-98675.6"
wire width 4 $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:100317.3-100335.6"
+ attribute \src "libresoc.v:98942.3-98960.6"
wire $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:100450.3-100468.6"
+ attribute \src "libresoc.v:99075.3-99093.6"
wire width 2 $1\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:100089.3-100107.6"
+ attribute \src "libresoc.v:98714.3-98732.6"
wire width 2 $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:100241.3-100259.6"
+ attribute \src "libresoc.v:98866.3-98884.6"
wire $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:100336.3-100354.6"
+ attribute \src "libresoc.v:98961.3-98979.6"
wire $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:100298.3-100316.6"
+ attribute \src "libresoc.v:98923.3-98941.6"
wire $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:100222.3-100240.6"
+ attribute \src "libresoc.v:98847.3-98865.6"
wire $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:99994.3-100012.6"
+ attribute \src "libresoc.v:98619.3-98637.6"
wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:100013.3-100031.6"
+ attribute \src "libresoc.v:98638.3-98656.6"
wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:99918.3-99936.6"
+ attribute \src "libresoc.v:98543.3-98561.6"
wire width 3 $1\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:99937.3-99955.6"
+ attribute \src "libresoc.v:98562.3-98580.6"
wire width 3 $1\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:99956.3-99974.6"
+ attribute \src "libresoc.v:98581.3-98599.6"
wire width 3 $1\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:99975.3-99993.6"
+ attribute \src "libresoc.v:98600.3-98618.6"
wire width 3 $1\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:100051.3-100069.6"
+ attribute \src "libresoc.v:98676.3-98694.6"
wire width 2 $1\dec31_dec_sub19_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub19_upd
- attribute \src "libresoc.v:99526.7-99526.15"
+ attribute \src "libresoc.v:98151.7-98151.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:100013.3-100031.6"
- process $proc$libresoc.v:100013$4059
+ attribute \src "libresoc.v:98151.7-98151.20"
+ process $proc$libresoc.v:98151$4027
assign { } { }
+ assign $0\initial[0:0] 1'0
+ sync always
+ update \initial $0\initial[0:0]
+ sync init
+ end
+ attribute \src "libresoc.v:98486.3-98504.6"
+ process $proc$libresoc.v:98486$3995
assign { } { }
- assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0]
- attribute \src "libresoc.v:100014.5-100014.29"
+ assign { } { }
+ assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0]
+ attribute \src "libresoc.v:98487.5-98487.29"
switch \initial
- attribute \src "libresoc.v:100014.9-100014.17"
+ attribute \src "libresoc.v:98487.9-98487.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000
case
- assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000
end
sync always
- update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0]
+ update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0]
end
- attribute \src "libresoc.v:100032.3-100050.6"
- process $proc$libresoc.v:100032$4060
+ attribute \src "libresoc.v:98505.3-98523.6"
+ process $proc$libresoc.v:98505$3996
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:100033.5-100033.29"
+ assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0]
+ attribute \src "libresoc.v:98506.5-98506.29"
switch \initial
- attribute \src "libresoc.v:100033.9-100033.17"
+ attribute \src "libresoc.v:98506.9-98506.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
+ assign $1\dec31_dec_sub19_cr_in[2:0] 3'110
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
+ assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
+ assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
+ assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
case
- assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
+ assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0]
+ update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0]
end
- attribute \src "libresoc.v:100051.3-100069.6"
- process $proc$libresoc.v:100051$4061
+ attribute \src "libresoc.v:98524.3-98542.6"
+ process $proc$libresoc.v:98524$3997
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:100052.5-100052.29"
+ assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0]
+ attribute \src "libresoc.v:98525.5-98525.29"
switch \initial
- attribute \src "libresoc.v:100052.9-100052.17"
+ attribute \src "libresoc.v:98525.9-98525.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_upd[1:0] 2'00
+ assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_upd[1:0] 2'00
+ assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_upd[1:0] 2'00
+ assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_upd[1:0] 2'00
+ assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
case
- assign $1\dec31_dec_sub19_upd[1:0] 2'00
+ assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0]
+ update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0]
end
- attribute \src "libresoc.v:100070.3-100088.6"
- process $proc$libresoc.v:100070$4062
+ attribute \src "libresoc.v:98543.3-98561.6"
+ process $proc$libresoc.v:98543$3998
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:100071.5-100071.29"
+ assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0]
+ attribute \src "libresoc.v:98544.5-98544.29"
switch \initial
- attribute \src "libresoc.v:100071.9-100071.17"
+ attribute \src "libresoc.v:98544.9-98544.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101
+ assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111
+ assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110
+ assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001
+ assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010
case
- assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000
+ assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0]
+ update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0]
end
- attribute \src "libresoc.v:100089.3-100107.6"
- process $proc$libresoc.v:100089$4063
+ attribute \src "libresoc.v:98562.3-98580.6"
+ process $proc$libresoc.v:98562$3999
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:100090.5-100090.29"
+ assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0]
+ attribute \src "libresoc.v:98563.5-98563.29"
switch \initial
- attribute \src "libresoc.v:100090.9-100090.17"
+ attribute \src "libresoc.v:98563.9-98563.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
case
- assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0]
+ update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0]
end
- attribute \src "libresoc.v:100108.3-100126.6"
- process $proc$libresoc.v:100108$4064
+ attribute \src "libresoc.v:98581.3-98599.6"
+ process $proc$libresoc.v:98581$4000
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:100109.5-100109.29"
+ assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0]
+ attribute \src "libresoc.v:98582.5-98582.29"
switch \initial
- attribute \src "libresoc.v:100109.9-100109.17"
+ attribute \src "libresoc.v:98582.9-98582.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
case
- assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
+ assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0]
+ update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0]
end
- attribute \src "libresoc.v:100127.3-100145.6"
- process $proc$libresoc.v:100127$4065
+ attribute \src "libresoc.v:98600.3-98618.6"
+ process $proc$libresoc.v:98600$4001
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:100128.5-100128.29"
+ assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0]
+ attribute \src "libresoc.v:98601.5-98601.29"
switch \initial
- attribute \src "libresoc.v:100128.9-100128.17"
+ attribute \src "libresoc.v:98601.9-98601.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111
+ assign $1\dec31_dec_sub19_sv_out[2:0] 3'001
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000
+ assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001
+ assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001
+ assign $1\dec31_dec_sub19_sv_out[2:0] 3'001
case
- assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000
+ assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0]
+ update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0]
end
- attribute \src "libresoc.v:100146.3-100164.6"
- process $proc$libresoc.v:100146$4066
+ attribute \src "libresoc.v:98619.3-98637.6"
+ process $proc$libresoc.v:98619$4002
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:100147.5-100147.29"
+ assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0]
+ attribute \src "libresoc.v:98620.5-98620.29"
switch \initial
- attribute \src "libresoc.v:100147.9-100147.17"
+ attribute \src "libresoc.v:98620.9-98620.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
case
- assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0]
+ update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:100165.3-100183.6"
- process $proc$libresoc.v:100165$4067
+ attribute \src "libresoc.v:98638.3-98656.6"
+ process $proc$libresoc.v:98638$4003
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:100166.5-100166.29"
+ assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0]
+ attribute \src "libresoc.v:98639.5-98639.29"
switch \initial
- attribute \src "libresoc.v:100166.9-100166.17"
+ attribute \src "libresoc.v:98639.9-98639.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
case
- assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0]
+ update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:100184.3-100202.6"
- process $proc$libresoc.v:100184$4068
+ attribute \src "libresoc.v:98657.3-98675.6"
+ process $proc$libresoc.v:98657$4004
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:100185.5-100185.29"
+ assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0]
+ attribute \src "libresoc.v:98658.5-98658.29"
switch \initial
- attribute \src "libresoc.v:100185.9-100185.17"
+ attribute \src "libresoc.v:98658.9-98658.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
case
- assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
+ assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
end
sync always
- update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0]
+ update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0]
end
- attribute \src "libresoc.v:100203.3-100221.6"
- process $proc$libresoc.v:100203$4069
+ attribute \src "libresoc.v:98676.3-98694.6"
+ process $proc$libresoc.v:98676$4005
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:100204.5-100204.29"
+ assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0]
+ attribute \src "libresoc.v:98677.5-98677.29"
switch \initial
- attribute \src "libresoc.v:100204.9-100204.17"
+ attribute \src "libresoc.v:98677.9-98677.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_br[0:0] 1'0
+ assign $1\dec31_dec_sub19_upd[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_br[0:0] 1'0
+ assign $1\dec31_dec_sub19_upd[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_br[0:0] 1'0
+ assign $1\dec31_dec_sub19_upd[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_br[0:0] 1'0
+ assign $1\dec31_dec_sub19_upd[1:0] 2'00
case
- assign $1\dec31_dec_sub19_br[0:0] 1'0
+ assign $1\dec31_dec_sub19_upd[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0]
+ update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0]
end
- attribute \src "libresoc.v:100222.3-100240.6"
- process $proc$libresoc.v:100222$4070
+ attribute \src "libresoc.v:98695.3-98713.6"
+ process $proc$libresoc.v:98695$4006
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:100223.5-100223.29"
+ assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0]
+ attribute \src "libresoc.v:98696.5-98696.29"
switch \initial
- attribute \src "libresoc.v:100223.9-100223.17"
+ attribute \src "libresoc.v:98696.9-98696.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
+ assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
+ assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
+ assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
+ assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001
case
- assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
+ assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000
end
sync always
- update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0]
+ update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0]
end
- attribute \src "libresoc.v:100241.3-100259.6"
- process $proc$libresoc.v:100241$4071
+ attribute \src "libresoc.v:98714.3-98732.6"
+ process $proc$libresoc.v:98714$4007
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:100242.5-100242.29"
+ assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0]
+ attribute \src "libresoc.v:98715.5-98715.29"
switch \initial
- attribute \src "libresoc.v:100242.9-100242.17"
+ attribute \src "libresoc.v:98715.9-98715.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
+ assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
+ assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
+ assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
+ assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
case
- assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
+ assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0]
+ update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0]
end
- attribute \src "libresoc.v:100260.3-100278.6"
- process $proc$libresoc.v:100260$4072
+ attribute \src "libresoc.v:98733.3-98751.6"
+ process $proc$libresoc.v:98733$4008
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:100261.5-100261.29"
+ assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0]
+ attribute \src "libresoc.v:98734.5-98734.29"
switch \initial
- attribute \src "libresoc.v:100261.9-100261.17"
+ attribute \src "libresoc.v:98734.9-98734.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
case
- assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0]
+ update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0]
end
- attribute \src "libresoc.v:100279.3-100297.6"
- process $proc$libresoc.v:100279$4073
+ attribute \src "libresoc.v:98752.3-98770.6"
+ process $proc$libresoc.v:98752$4009
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:100280.5-100280.29"
+ assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0]
+ attribute \src "libresoc.v:98753.5-98753.29"
switch \initial
- attribute \src "libresoc.v:100280.9-100280.17"
+ attribute \src "libresoc.v:98753.9-98753.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_form[4:0] 5'01010
+ assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_form[4:0] 5'01000
+ assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_form[4:0] 5'01010
+ assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_form[4:0] 5'01010
+ assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001
case
- assign $1\dec31_dec_sub19_form[4:0] 5'00000
+ assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000
end
sync always
- update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0]
+ update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0]
end
- attribute \src "libresoc.v:100298.3-100316.6"
- process $proc$libresoc.v:100298$4074
+ attribute \src "libresoc.v:98771.3-98789.6"
+ process $proc$libresoc.v:98771$4010
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:100299.5-100299.29"
+ assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0]
+ attribute \src "libresoc.v:98772.5-98772.29"
switch \initial
- attribute \src "libresoc.v:100299.9-100299.17"
+ attribute \src "libresoc.v:98772.9-98772.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sgn[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sgn[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sgn[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sgn[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
case
- assign $1\dec31_dec_sub19_sgn[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0]
+ update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0]
end
- attribute \src "libresoc.v:100317.3-100335.6"
- process $proc$libresoc.v:100317$4075
+ attribute \src "libresoc.v:98790.3-98808.6"
+ process $proc$libresoc.v:98790$4011
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:100318.5-100318.29"
+ assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0]
+ attribute \src "libresoc.v:98791.5-98791.29"
switch \initial
- attribute \src "libresoc.v:100318.9-100318.17"
+ attribute \src "libresoc.v:98791.9-98791.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_lk[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_lk[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_lk[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_lk[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
case
- assign $1\dec31_dec_sub19_lk[0:0] 1'0
+ assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0]
+ update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0]
end
- attribute \src "libresoc.v:100336.3-100354.6"
- process $proc$libresoc.v:100336$4076
+ attribute \src "libresoc.v:98809.3-98827.6"
+ process $proc$libresoc.v:98809$4012
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:100337.5-100337.29"
+ assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0]
+ attribute \src "libresoc.v:98810.5-98810.29"
switch \initial
- attribute \src "libresoc.v:100337.9-100337.17"
+ attribute \src "libresoc.v:98810.9-98810.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1
+ assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
case
- assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
+ assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0]
+ update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0]
end
- attribute \src "libresoc.v:100355.3-100373.6"
- process $proc$libresoc.v:100355$4077
+ attribute \src "libresoc.v:98828.3-98846.6"
+ process $proc$libresoc.v:98828$4013
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0]
- attribute \src "libresoc.v:100356.5-100356.29"
+ assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0]
+ attribute \src "libresoc.v:98829.5-98829.29"
switch \initial
- attribute \src "libresoc.v:100356.9-100356.17"
+ attribute \src "libresoc.v:98829.9-98829.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
+ assign $1\dec31_dec_sub19_br[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00
+ assign $1\dec31_dec_sub19_br[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
+ assign $1\dec31_dec_sub19_br[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
+ assign $1\dec31_dec_sub19_br[0:0] 1'0
case
- assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00
+ assign $1\dec31_dec_sub19_br[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0]
+ update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0]
end
- attribute \src "libresoc.v:100374.3-100392.6"
- process $proc$libresoc.v:100374$4078
+ attribute \src "libresoc.v:98847.3-98865.6"
+ process $proc$libresoc.v:98847$4014
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0]
- attribute \src "libresoc.v:100375.5-100375.29"
+ assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0]
+ attribute \src "libresoc.v:98848.5-98848.29"
switch \initial
- attribute \src "libresoc.v:100375.9-100375.17"
+ attribute \src "libresoc.v:98848.9-98848.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
+ assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00
+ assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
+ assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
+ assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
case
- assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00
+ assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0]
+ update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:100393.3-100411.6"
- process $proc$libresoc.v:100393$4079
+ attribute \src "libresoc.v:98866.3-98884.6"
+ process $proc$libresoc.v:98866$4015
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:100394.5-100394.29"
+ assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0]
+ attribute \src "libresoc.v:98867.5-98867.29"
switch \initial
- attribute \src "libresoc.v:100394.9-100394.17"
+ attribute \src "libresoc.v:98867.9-98867.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
+ assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
+ assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011
+ assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100
+ assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
case
- assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
+ assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0]
+ update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0]
end
- attribute \src "libresoc.v:100412.3-100430.6"
- process $proc$libresoc.v:100412$4080
+ attribute \src "libresoc.v:98885.3-98903.6"
+ process $proc$libresoc.v:98885$4016
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:100413.5-100413.29"
+ assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0]
+ attribute \src "libresoc.v:98886.5-98886.29"
switch \initial
- attribute \src "libresoc.v:100413.9-100413.17"
+ attribute \src "libresoc.v:98886.9-98886.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
+ assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
+ assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
+ assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
+ assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
case
- assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
+ assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0]
+ update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0]
end
- attribute \src "libresoc.v:100431.3-100449.6"
- process $proc$libresoc.v:100431$4081
+ attribute \src "libresoc.v:98904.3-98922.6"
+ process $proc$libresoc.v:98904$4017
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:100432.5-100432.29"
+ assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0]
+ attribute \src "libresoc.v:98905.5-98905.29"
switch \initial
- attribute \src "libresoc.v:100432.9-100432.17"
+ attribute \src "libresoc.v:98905.9-98905.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_form[4:0] 5'01010
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_form[4:0] 5'01000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_form[4:0] 5'01010
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_form[4:0] 5'01010
case
- assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_form[4:0] 5'00000
end
sync always
- update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0]
+ update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0]
end
- attribute \src "libresoc.v:100450.3-100468.6"
- process $proc$libresoc.v:100450$4082
+ attribute \src "libresoc.v:98923.3-98941.6"
+ process $proc$libresoc.v:98923$4018
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:100451.5-100451.29"
+ assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0]
+ attribute \src "libresoc.v:98924.5-98924.29"
switch \initial
- attribute \src "libresoc.v:100451.9-100451.17"
+ attribute \src "libresoc.v:98924.9-98924.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
+ assign $1\dec31_dec_sub19_sgn[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
+ assign $1\dec31_dec_sub19_sgn[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
+ assign $1\dec31_dec_sub19_sgn[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_out_sel[1:0] 2'11
+ assign $1\dec31_dec_sub19_sgn[0:0] 1'0
case
- assign $1\dec31_dec_sub19_out_sel[1:0] 2'00
+ assign $1\dec31_dec_sub19_sgn[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0]
- end
- attribute \src "libresoc.v:99526.7-99526.20"
- process $proc$libresoc.v:99526$4083
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
+ update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0]
end
- attribute \src "libresoc.v:99861.3-99879.6"
- process $proc$libresoc.v:99861$4051
+ attribute \src "libresoc.v:98942.3-98960.6"
+ process $proc$libresoc.v:98942$4019
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0]
- attribute \src "libresoc.v:99862.5-99862.29"
+ assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0]
+ attribute \src "libresoc.v:98943.5-98943.29"
switch \initial
- attribute \src "libresoc.v:99862.9-99862.17"
+ attribute \src "libresoc.v:98943.9-98943.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000
+ assign $1\dec31_dec_sub19_lk[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000
+ assign $1\dec31_dec_sub19_lk[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000
+ assign $1\dec31_dec_sub19_lk[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000
+ assign $1\dec31_dec_sub19_lk[0:0] 1'0
case
- assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000
+ assign $1\dec31_dec_sub19_lk[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0]
+ update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0]
end
- attribute \src "libresoc.v:99880.3-99898.6"
- process $proc$libresoc.v:99880$4052
+ attribute \src "libresoc.v:98961.3-98979.6"
+ process $proc$libresoc.v:98961$4020
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:99881.5-99881.29"
+ assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0]
+ attribute \src "libresoc.v:98962.5-98962.29"
switch \initial
- attribute \src "libresoc.v:99881.9-99881.17"
+ attribute \src "libresoc.v:98962.9-98962.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_cr_in[2:0] 3'110
+ assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
case
- assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
end
sync always
- update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0]
+ update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:99899.3-99917.6"
- process $proc$libresoc.v:99899$4053
+ attribute \src "libresoc.v:98980.3-98998.6"
+ process $proc$libresoc.v:98980$4021
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:99900.5-99900.29"
+ assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0]
+ attribute \src "libresoc.v:98981.5-98981.29"
switch \initial
- attribute \src "libresoc.v:99900.9-99900.17"
+ attribute \src "libresoc.v:98981.9-98981.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10
case
- assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0]
+ update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0]
end
- attribute \src "libresoc.v:99918.3-99936.6"
- process $proc$libresoc.v:99918$4054
+ attribute \src "libresoc.v:98999.3-99017.6"
+ process $proc$libresoc.v:98999$4022
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0]
- attribute \src "libresoc.v:99919.5-99919.29"
+ assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0]
+ attribute \src "libresoc.v:99000.5-99000.29"
switch \initial
- attribute \src "libresoc.v:99919.9-99919.17"
+ attribute \src "libresoc.v:99000.9-99000.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010
+ assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010
+ assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10
case
- assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000
+ assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0]
+ update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:99937.3-99955.6"
- process $proc$libresoc.v:99937$4055
+ attribute \src "libresoc.v:99018.3-99036.6"
+ process $proc$libresoc.v:99018$4023
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0]
- attribute \src "libresoc.v:99938.5-99938.29"
+ assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0]
+ attribute \src "libresoc.v:99019.5-99019.29"
switch \initial
- attribute \src "libresoc.v:99938.9-99938.17"
+ attribute \src "libresoc.v:99019.9-99019.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
+ assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
+ assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
+ assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
+ assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100
case
- assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000
+ assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
end
sync always
- update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0]
+ update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0]
end
- attribute \src "libresoc.v:99956.3-99974.6"
- process $proc$libresoc.v:99956$4056
+ attribute \src "libresoc.v:99037.3-99055.6"
+ process $proc$libresoc.v:99037$4024
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0]
- attribute \src "libresoc.v:99957.5-99957.29"
+ assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0]
+ attribute \src "libresoc.v:99038.5-99038.29"
switch \initial
- attribute \src "libresoc.v:99957.9-99957.17"
+ attribute \src "libresoc.v:99038.9-99038.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
+ assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
+ assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
+ assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
+ assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
case
- assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000
+ assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
end
sync always
- update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0]
+ update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0]
end
- attribute \src "libresoc.v:99975.3-99993.6"
- process $proc$libresoc.v:99975$4057
+ attribute \src "libresoc.v:99056.3-99074.6"
+ process $proc$libresoc.v:99056$4025
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0]
- attribute \src "libresoc.v:99976.5-99976.29"
+ assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0]
+ attribute \src "libresoc.v:99057.5-99057.29"
switch \initial
- attribute \src "libresoc.v:99976.9-99976.17"
+ attribute \src "libresoc.v:99057.9-99057.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_out[2:0] 3'001
+ assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_out[2:0] 3'001
+ assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
case
- assign $1\dec31_dec_sub19_sv_out[2:0] 3'000
+ assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0]
+ update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0]
end
- attribute \src "libresoc.v:99994.3-100012.6"
- process $proc$libresoc.v:99994$4058
+ attribute \src "libresoc.v:99075.3-99093.6"
+ process $proc$libresoc.v:99075$4026
assign { } { }
assign { } { }
- assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0]
- attribute \src "libresoc.v:99995.5-99995.29"
+ assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0]
+ attribute \src "libresoc.v:99076.5-99076.29"
switch \initial
- attribute \src "libresoc.v:99995.9-99995.17"
+ attribute \src "libresoc.v:99076.9-99076.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 5'00000
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
attribute \src "libresoc.v:0.0-0.0"
case 5'00010
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
attribute \src "libresoc.v:0.0-0.0"
case 5'01010
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
attribute \src "libresoc.v:0.0-0.0"
case 5'01110
assign { } { }
- assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_out_sel[1:0] 2'11
case
- assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000
+ assign $1\dec31_dec_sub19_out_sel[1:0] 2'00
end
sync always
- update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0]
+ update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0]
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:100474.1-101611.10"
+attribute \src "libresoc.v:99099.1-100236.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20"
attribute \generator "nMigen"
module \dec31_dec_sub20
- attribute \src "libresoc.v:101460.3-101484.6"
+ attribute \src "libresoc.v:100085.3-100109.6"
wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:101485.3-101509.6"
+ attribute \src "libresoc.v:100110.3-100134.6"
wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:101160.3-101184.6"
+ attribute \src "libresoc.v:99785.3-99809.6"
wire width 8 $0\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:101260.3-101284.6"
+ attribute \src "libresoc.v:99885.3-99909.6"
wire $0\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:100835.3-100859.6"
+ attribute \src "libresoc.v:99460.3-99484.6"
wire width 3 $0\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:100860.3-100884.6"
+ attribute \src "libresoc.v:99485.3-99509.6"
wire width 3 $0\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:101135.3-101159.6"
+ attribute \src "libresoc.v:99760.3-99784.6"
wire width 2 $0\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:101235.3-101259.6"
+ attribute \src "libresoc.v:99860.3-99884.6"
wire $0\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:101360.3-101384.6"
+ attribute \src "libresoc.v:99985.3-100009.6"
wire width 5 $0\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:100810.3-100834.6"
+ attribute \src "libresoc.v:99435.3-99459.6"
wire width 13 $0\dec31_dec_sub20_function_unit[12:0]
- attribute \src "libresoc.v:101510.3-101534.6"
+ attribute \src "libresoc.v:100135.3-100159.6"
wire width 3 $0\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:101535.3-101559.6"
+ attribute \src "libresoc.v:100160.3-100184.6"
wire width 4 $0\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:101560.3-101584.6"
+ attribute \src "libresoc.v:100185.3-100209.6"
wire width 2 $0\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:101085.3-101109.6"
+ attribute \src "libresoc.v:99710.3-99734.6"
wire width 7 $0\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:101185.3-101209.6"
+ attribute \src "libresoc.v:99810.3-99834.6"
wire $0\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:101210.3-101234.6"
+ attribute \src "libresoc.v:99835.3-99859.6"
wire $0\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:101335.3-101359.6"
+ attribute \src "libresoc.v:99960.3-99984.6"
wire $0\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:101035.3-101059.6"
+ attribute \src "libresoc.v:99660.3-99684.6"
wire width 4 $0\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:101410.3-101434.6"
+ attribute \src "libresoc.v:100035.3-100059.6"
wire $0\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:101585.3-101609.6"
+ attribute \src "libresoc.v:100210.3-100234.6"
wire width 2 $0\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:101110.3-101134.6"
+ attribute \src "libresoc.v:99735.3-99759.6"
wire width 2 $0\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:101310.3-101334.6"
+ attribute \src "libresoc.v:99935.3-99959.6"
wire $0\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:101435.3-101459.6"
+ attribute \src "libresoc.v:100060.3-100084.6"
wire $0\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:101385.3-101409.6"
+ attribute \src "libresoc.v:100010.3-100034.6"
wire $0\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:101285.3-101309.6"
+ attribute \src "libresoc.v:99910.3-99934.6"
wire $0\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:100985.3-101009.6"
+ attribute \src "libresoc.v:99610.3-99634.6"
wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:101010.3-101034.6"
+ attribute \src "libresoc.v:99635.3-99659.6"
wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:100885.3-100909.6"
+ attribute \src "libresoc.v:99510.3-99534.6"
wire width 3 $0\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:100910.3-100934.6"
+ attribute \src "libresoc.v:99535.3-99559.6"
wire width 3 $0\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:100935.3-100959.6"
+ attribute \src "libresoc.v:99560.3-99584.6"
wire width 3 $0\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:100960.3-100984.6"
+ attribute \src "libresoc.v:99585.3-99609.6"
wire width 3 $0\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:101060.3-101084.6"
+ attribute \src "libresoc.v:99685.3-99709.6"
wire width 2 $0\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:100475.7-100475.20"
+ attribute \src "libresoc.v:99100.7-99100.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:101460.3-101484.6"
+ attribute \src "libresoc.v:100085.3-100109.6"
wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:101485.3-101509.6"
+ attribute \src "libresoc.v:100110.3-100134.6"
wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:101160.3-101184.6"
+ attribute \src "libresoc.v:99785.3-99809.6"
wire width 8 $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:101260.3-101284.6"
+ attribute \src "libresoc.v:99885.3-99909.6"
wire $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:100835.3-100859.6"
+ attribute \src "libresoc.v:99460.3-99484.6"
wire width 3 $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:100860.3-100884.6"
+ attribute \src "libresoc.v:99485.3-99509.6"
wire width 3 $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:101135.3-101159.6"
+ attribute \src "libresoc.v:99760.3-99784.6"
wire width 2 $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:101235.3-101259.6"
+ attribute \src "libresoc.v:99860.3-99884.6"
wire $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:101360.3-101384.6"
+ attribute \src "libresoc.v:99985.3-100009.6"
wire width 5 $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:100810.3-100834.6"
+ attribute \src "libresoc.v:99435.3-99459.6"
wire width 13 $1\dec31_dec_sub20_function_unit[12:0]
- attribute \src "libresoc.v:101510.3-101534.6"
+ attribute \src "libresoc.v:100135.3-100159.6"
wire width 3 $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:101535.3-101559.6"
+ attribute \src "libresoc.v:100160.3-100184.6"
wire width 4 $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:101560.3-101584.6"
+ attribute \src "libresoc.v:100185.3-100209.6"
wire width 2 $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:101085.3-101109.6"
+ attribute \src "libresoc.v:99710.3-99734.6"
wire width 7 $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:101185.3-101209.6"
+ attribute \src "libresoc.v:99810.3-99834.6"
wire $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:101210.3-101234.6"
+ attribute \src "libresoc.v:99835.3-99859.6"
wire $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:101335.3-101359.6"
+ attribute \src "libresoc.v:99960.3-99984.6"
wire $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:101035.3-101059.6"
+ attribute \src "libresoc.v:99660.3-99684.6"
wire width 4 $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:101410.3-101434.6"
+ attribute \src "libresoc.v:100035.3-100059.6"
wire $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:101585.3-101609.6"
+ attribute \src "libresoc.v:100210.3-100234.6"
wire width 2 $1\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:101110.3-101134.6"
+ attribute \src "libresoc.v:99735.3-99759.6"
wire width 2 $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:101310.3-101334.6"
+ attribute \src "libresoc.v:99935.3-99959.6"
wire $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:101435.3-101459.6"
+ attribute \src "libresoc.v:100060.3-100084.6"
wire $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:101385.3-101409.6"
+ attribute \src "libresoc.v:100010.3-100034.6"
wire $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:101285.3-101309.6"
+ attribute \src "libresoc.v:99910.3-99934.6"
wire $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:100985.3-101009.6"
+ attribute \src "libresoc.v:99610.3-99634.6"
wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:101010.3-101034.6"
+ attribute \src "libresoc.v:99635.3-99659.6"
wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:100885.3-100909.6"
+ attribute \src "libresoc.v:99510.3-99534.6"
wire width 3 $1\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:100910.3-100934.6"
+ attribute \src "libresoc.v:99535.3-99559.6"
wire width 3 $1\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:100935.3-100959.6"
+ attribute \src "libresoc.v:99560.3-99584.6"
wire width 3 $1\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:100960.3-100984.6"
+ attribute \src "libresoc.v:99585.3-99609.6"
wire width 3 $1\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:101060.3-101084.6"
+ attribute \src "libresoc.v:99685.3-99709.6"
wire width 2 $1\dec31_dec_sub20_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub20_upd
- attribute \src "libresoc.v:100475.7-100475.15"
+ attribute \src "libresoc.v:99100.7-99100.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:100475.7-100475.20"
- process $proc$libresoc.v:100475$4116
+ attribute \src "libresoc.v:100010.3-100034.6"
+ process $proc$libresoc.v:100010$4051
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0]
+ attribute \src "libresoc.v:100011.5-100011.29"
+ switch \initial
+ attribute \src "libresoc.v:100011.9-100011.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ case
+ assign $1\dec31_dec_sub20_sgn[0:0] 1'0
+ end
+ sync always
+ update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0]
+ end
+ attribute \src "libresoc.v:100035.3-100059.6"
+ process $proc$libresoc.v:100035$4052
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0]
+ attribute \src "libresoc.v:100036.5-100036.29"
+ switch \initial
+ attribute \src "libresoc.v:100036.9-100036.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ case
+ assign $1\dec31_dec_sub20_lk[0:0] 1'0
+ end
+ sync always
+ update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0]
+ end
+ attribute \src "libresoc.v:100060.3-100084.6"
+ process $proc$libresoc.v:100060$4053
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0]
+ attribute \src "libresoc.v:100061.5-100061.29"
+ switch \initial
+ attribute \src "libresoc.v:100061.9-100061.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
+ case
+ assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0
+ end
+ sync always
+ update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0]
+ end
+ attribute \src "libresoc.v:100085.3-100109.6"
+ process $proc$libresoc.v:100085$4054
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0]
+ attribute \src "libresoc.v:100086.5-100086.29"
+ switch \initial
+ attribute \src "libresoc.v:100086.9-100086.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
+ case
+ assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00
+ end
+ sync always
+ update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0]
+ end
+ attribute \src "libresoc.v:100110.3-100134.6"
+ process $proc$libresoc.v:100110$4055
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0]
+ attribute \src "libresoc.v:100111.5-100111.29"
+ switch \initial
+ attribute \src "libresoc.v:100111.9-100111.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
+ case
+ assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00
+ end
+ sync always
+ update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0]
+ end
+ attribute \src "libresoc.v:100135.3-100159.6"
+ process $proc$libresoc.v:100135$4056
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0]
+ attribute \src "libresoc.v:100136.5-100136.29"
+ switch \initial
+ attribute \src "libresoc.v:100136.9-100136.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
+ case
+ assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000
+ end
+ sync always
+ update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0]
+ end
+ attribute \src "libresoc.v:100160.3-100184.6"
+ process $proc$libresoc.v:100160$4057
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0]
+ attribute \src "libresoc.v:100161.5-100161.29"
+ switch \initial
+ attribute \src "libresoc.v:100161.9-100161.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
+ case
+ assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000
+ end
+ sync always
+ update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0]
+ end
+ attribute \src "libresoc.v:100185.3-100209.6"
+ process $proc$libresoc.v:100185$4058
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0]
+ attribute \src "libresoc.v:100186.5-100186.29"
+ switch \initial
+ attribute \src "libresoc.v:100186.9-100186.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01
+ case
+ assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
+ end
+ sync always
+ update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0]
+ end
+ attribute \src "libresoc.v:100210.3-100234.6"
+ process $proc$libresoc.v:100210$4059
+ assign { } { }
+ assign { } { }
+ assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0]
+ attribute \src "libresoc.v:100211.5-100211.29"
+ switch \initial
+ attribute \src "libresoc.v:100211.9-100211.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
+ switch \opcode_switch
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00001
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00010
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10000
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00011
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'00000
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
+ attribute \src "libresoc.v:0.0-0.0"
+ case 5'10100
+ assign { } { }
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
+ case
+ assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
+ end
+ sync always
+ update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0]
+ end
+ attribute \src "libresoc.v:99100.7-99100.20"
+ process $proc$libresoc.v:99100$4060
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:100810.3-100834.6"
- process $proc$libresoc.v:100810$4084
+ attribute \src "libresoc.v:99435.3-99459.6"
+ process $proc$libresoc.v:99435$4028
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_function_unit[12:0] $1\dec31_dec_sub20_function_unit[12:0]
- attribute \src "libresoc.v:100811.5-100811.29"
+ attribute \src "libresoc.v:99436.5-99436.29"
switch \initial
- attribute \src "libresoc.v:100811.9-100811.17"
+ attribute \src "libresoc.v:99436.9-99436.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[12:0]
end
- attribute \src "libresoc.v:100835.3-100859.6"
- process $proc$libresoc.v:100835$4085
+ attribute \src "libresoc.v:99460.3-99484.6"
+ process $proc$libresoc.v:99460$4029
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:100836.5-100836.29"
+ attribute \src "libresoc.v:99461.5-99461.29"
switch \initial
- attribute \src "libresoc.v:100836.9-100836.17"
+ attribute \src "libresoc.v:99461.9-99461.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0]
end
- attribute \src "libresoc.v:100860.3-100884.6"
- process $proc$libresoc.v:100860$4086
+ attribute \src "libresoc.v:99485.3-99509.6"
+ process $proc$libresoc.v:99485$4030
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:100861.5-100861.29"
+ attribute \src "libresoc.v:99486.5-99486.29"
switch \initial
- attribute \src "libresoc.v:100861.9-100861.17"
+ attribute \src "libresoc.v:99486.9-99486.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0]
end
- attribute \src "libresoc.v:100885.3-100909.6"
- process $proc$libresoc.v:100885$4087
+ attribute \src "libresoc.v:99510.3-99534.6"
+ process $proc$libresoc.v:99510$4031
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0]
- attribute \src "libresoc.v:100886.5-100886.29"
+ attribute \src "libresoc.v:99511.5-99511.29"
switch \initial
- attribute \src "libresoc.v:100886.9-100886.17"
+ attribute \src "libresoc.v:99511.9-99511.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0]
end
- attribute \src "libresoc.v:100910.3-100934.6"
- process $proc$libresoc.v:100910$4088
+ attribute \src "libresoc.v:99535.3-99559.6"
+ process $proc$libresoc.v:99535$4032
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0]
- attribute \src "libresoc.v:100911.5-100911.29"
+ attribute \src "libresoc.v:99536.5-99536.29"
switch \initial
- attribute \src "libresoc.v:100911.9-100911.17"
+ attribute \src "libresoc.v:99536.9-99536.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0]
end
- attribute \src "libresoc.v:100935.3-100959.6"
- process $proc$libresoc.v:100935$4089
+ attribute \src "libresoc.v:99560.3-99584.6"
+ process $proc$libresoc.v:99560$4033
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0]
- attribute \src "libresoc.v:100936.5-100936.29"
+ attribute \src "libresoc.v:99561.5-99561.29"
switch \initial
- attribute \src "libresoc.v:100936.9-100936.17"
+ attribute \src "libresoc.v:99561.9-99561.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0]
end
- attribute \src "libresoc.v:100960.3-100984.6"
- process $proc$libresoc.v:100960$4090
+ attribute \src "libresoc.v:99585.3-99609.6"
+ process $proc$libresoc.v:99585$4034
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0]
- attribute \src "libresoc.v:100961.5-100961.29"
+ attribute \src "libresoc.v:99586.5-99586.29"
switch \initial
- attribute \src "libresoc.v:100961.9-100961.17"
+ attribute \src "libresoc.v:99586.9-99586.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0]
end
- attribute \src "libresoc.v:100985.3-101009.6"
- process $proc$libresoc.v:100985$4091
+ attribute \src "libresoc.v:99610.3-99634.6"
+ process $proc$libresoc.v:99610$4035
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0]
- attribute \src "libresoc.v:100986.5-100986.29"
+ attribute \src "libresoc.v:99611.5-99611.29"
switch \initial
- attribute \src "libresoc.v:100986.9-100986.17"
+ attribute \src "libresoc.v:99611.9-99611.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:101010.3-101034.6"
- process $proc$libresoc.v:101010$4092
+ attribute \src "libresoc.v:99635.3-99659.6"
+ process $proc$libresoc.v:99635$4036
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0]
- attribute \src "libresoc.v:101011.5-101011.29"
+ attribute \src "libresoc.v:99636.5-99636.29"
switch \initial
- attribute \src "libresoc.v:101011.9-101011.17"
+ attribute \src "libresoc.v:99636.9-99636.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:101035.3-101059.6"
- process $proc$libresoc.v:101035$4093
+ attribute \src "libresoc.v:99660.3-99684.6"
+ process $proc$libresoc.v:99660$4037
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:101036.5-101036.29"
+ attribute \src "libresoc.v:99661.5-99661.29"
switch \initial
- attribute \src "libresoc.v:101036.9-101036.17"
+ attribute \src "libresoc.v:99661.9-99661.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0]
end
- attribute \src "libresoc.v:101060.3-101084.6"
- process $proc$libresoc.v:101060$4094
+ attribute \src "libresoc.v:99685.3-99709.6"
+ process $proc$libresoc.v:99685$4038
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:101061.5-101061.29"
+ attribute \src "libresoc.v:99686.5-99686.29"
switch \initial
- attribute \src "libresoc.v:101061.9-101061.17"
+ attribute \src "libresoc.v:99686.9-99686.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0]
end
- attribute \src "libresoc.v:101085.3-101109.6"
- process $proc$libresoc.v:101085$4095
+ attribute \src "libresoc.v:99710.3-99734.6"
+ process $proc$libresoc.v:99710$4039
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:101086.5-101086.29"
+ attribute \src "libresoc.v:99711.5-99711.29"
switch \initial
- attribute \src "libresoc.v:101086.9-101086.17"
+ attribute \src "libresoc.v:99711.9-99711.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0]
end
- attribute \src "libresoc.v:101110.3-101134.6"
- process $proc$libresoc.v:101110$4096
+ attribute \src "libresoc.v:99735.3-99759.6"
+ process $proc$libresoc.v:99735$4040
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:101111.5-101111.29"
+ attribute \src "libresoc.v:99736.5-99736.29"
switch \initial
- attribute \src "libresoc.v:101111.9-101111.17"
+ attribute \src "libresoc.v:99736.9-99736.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0]
end
- attribute \src "libresoc.v:101135.3-101159.6"
- process $proc$libresoc.v:101135$4097
+ attribute \src "libresoc.v:99760.3-99784.6"
+ process $proc$libresoc.v:99760$4041
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:101136.5-101136.29"
+ attribute \src "libresoc.v:99761.5-99761.29"
switch \initial
- attribute \src "libresoc.v:101136.9-101136.17"
+ attribute \src "libresoc.v:99761.9-99761.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0]
end
- attribute \src "libresoc.v:101160.3-101184.6"
- process $proc$libresoc.v:101160$4098
+ attribute \src "libresoc.v:99785.3-99809.6"
+ process $proc$libresoc.v:99785$4042
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:101161.5-101161.29"
+ attribute \src "libresoc.v:99786.5-99786.29"
switch \initial
- attribute \src "libresoc.v:101161.9-101161.17"
+ attribute \src "libresoc.v:99786.9-99786.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0]
end
- attribute \src "libresoc.v:101185.3-101209.6"
- process $proc$libresoc.v:101185$4099
+ attribute \src "libresoc.v:99810.3-99834.6"
+ process $proc$libresoc.v:99810$4043
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:101186.5-101186.29"
+ attribute \src "libresoc.v:99811.5-99811.29"
switch \initial
- attribute \src "libresoc.v:101186.9-101186.17"
+ attribute \src "libresoc.v:99811.9-99811.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0]
end
- attribute \src "libresoc.v:101210.3-101234.6"
- process $proc$libresoc.v:101210$4100
+ attribute \src "libresoc.v:99835.3-99859.6"
+ process $proc$libresoc.v:99835$4044
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:101211.5-101211.29"
+ attribute \src "libresoc.v:99836.5-99836.29"
switch \initial
- attribute \src "libresoc.v:101211.9-101211.17"
+ attribute \src "libresoc.v:99836.9-99836.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0]
end
- attribute \src "libresoc.v:101235.3-101259.6"
- process $proc$libresoc.v:101235$4101
+ attribute \src "libresoc.v:99860.3-99884.6"
+ process $proc$libresoc.v:99860$4045
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:101236.5-101236.29"
+ attribute \src "libresoc.v:99861.5-99861.29"
switch \initial
- attribute \src "libresoc.v:101236.9-101236.17"
+ attribute \src "libresoc.v:99861.9-99861.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0]
end
- attribute \src "libresoc.v:101260.3-101284.6"
- process $proc$libresoc.v:101260$4102
+ attribute \src "libresoc.v:99885.3-99909.6"
+ process $proc$libresoc.v:99885$4046
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:101261.5-101261.29"
+ attribute \src "libresoc.v:99886.5-99886.29"
switch \initial
- attribute \src "libresoc.v:101261.9-101261.17"
+ attribute \src "libresoc.v:99886.9-99886.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0]
end
- attribute \src "libresoc.v:101285.3-101309.6"
- process $proc$libresoc.v:101285$4103
+ attribute \src "libresoc.v:99910.3-99934.6"
+ process $proc$libresoc.v:99910$4047
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:101286.5-101286.29"
+ attribute \src "libresoc.v:99911.5-99911.29"
switch \initial
- attribute \src "libresoc.v:101286.9-101286.17"
+ attribute \src "libresoc.v:99911.9-99911.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0]
end
- attribute \src "libresoc.v:101310.3-101334.6"
- process $proc$libresoc.v:101310$4104
+ attribute \src "libresoc.v:99935.3-99959.6"
+ process $proc$libresoc.v:99935$4048
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:101311.5-101311.29"
+ attribute \src "libresoc.v:99936.5-99936.29"
switch \initial
- attribute \src "libresoc.v:101311.9-101311.17"
+ attribute \src "libresoc.v:99936.9-99936.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0]
end
- attribute \src "libresoc.v:101335.3-101359.6"
- process $proc$libresoc.v:101335$4105
+ attribute \src "libresoc.v:99960.3-99984.6"
+ process $proc$libresoc.v:99960$4049
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:101336.5-101336.29"
+ attribute \src "libresoc.v:99961.5-99961.29"
switch \initial
- attribute \src "libresoc.v:101336.9-101336.17"
+ attribute \src "libresoc.v:99961.9-99961.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0]
end
- attribute \src "libresoc.v:101360.3-101384.6"
- process $proc$libresoc.v:101360$4106
+ attribute \src "libresoc.v:99985.3-100009.6"
+ process $proc$libresoc.v:99985$4050
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:101361.5-101361.29"
+ attribute \src "libresoc.v:99986.5-99986.29"
switch \initial
- attribute \src "libresoc.v:101361.9-101361.17"
+ attribute \src "libresoc.v:99986.9-99986.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0]
end
- attribute \src "libresoc.v:101385.3-101409.6"
- process $proc$libresoc.v:101385$4107
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:101386.5-101386.29"
- switch \initial
- attribute \src "libresoc.v:101386.9-101386.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- case
- assign $1\dec31_dec_sub20_sgn[0:0] 1'0
- end
- sync always
- update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0]
- end
- attribute \src "libresoc.v:101410.3-101434.6"
- process $proc$libresoc.v:101410$4108
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:101411.5-101411.29"
- switch \initial
- attribute \src "libresoc.v:101411.9-101411.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- case
- assign $1\dec31_dec_sub20_lk[0:0] 1'0
- end
- sync always
- update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0]
- end
- attribute \src "libresoc.v:101435.3-101459.6"
- process $proc$libresoc.v:101435$4109
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:101436.5-101436.29"
- switch \initial
- attribute \src "libresoc.v:101436.9-101436.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
- case
- assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0
- end
- sync always
- update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0]
- end
- attribute \src "libresoc.v:101460.3-101484.6"
- process $proc$libresoc.v:101460$4110
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0]
- attribute \src "libresoc.v:101461.5-101461.29"
- switch \initial
- attribute \src "libresoc.v:101461.9-101461.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01
- case
- assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00
- end
- sync always
- update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0]
- end
- attribute \src "libresoc.v:101485.3-101509.6"
- process $proc$libresoc.v:101485$4111
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0]
- attribute \src "libresoc.v:101486.5-101486.29"
- switch \initial
- attribute \src "libresoc.v:101486.9-101486.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10
- case
- assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00
- end
- sync always
- update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0]
- end
- attribute \src "libresoc.v:101510.3-101534.6"
- process $proc$libresoc.v:101510$4112
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:101511.5-101511.29"
- switch \initial
- attribute \src "libresoc.v:101511.9-101511.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
- case
- assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000
- end
- sync always
- update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0]
- end
- attribute \src "libresoc.v:101535.3-101559.6"
- process $proc$libresoc.v:101535$4113
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:101536.5-101536.29"
- switch \initial
- attribute \src "libresoc.v:101536.9-101536.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
- case
- assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000
- end
- sync always
- update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0]
- end
- attribute \src "libresoc.v:101560.3-101584.6"
- process $proc$libresoc.v:101560$4114
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:101561.5-101561.29"
- switch \initial
- attribute \src "libresoc.v:101561.9-101561.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01
- case
- assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
- end
- sync always
- update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0]
- end
- attribute \src "libresoc.v:101585.3-101609.6"
- process $proc$libresoc.v:101585$4115
- assign { } { }
- assign { } { }
- assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:101586.5-101586.29"
- switch \initial
- attribute \src "libresoc.v:101586.9-101586.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441"
- switch \opcode_switch
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00001
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00010
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10000
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00011
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'00000
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
- attribute \src "libresoc.v:0.0-0.0"
- case 5'10100
- assign { } { }
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
- case
- assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
- end
- sync always
- update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0]
- end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:101615.1-103502.10"
+attribute \src "libresoc.v:100240.1-102127.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21"
attribute \generator "nMigen"
module \dec31_dec_sub21
- attribute \src "libresoc.v:103207.3-103255.6"
+ attribute \src "libresoc.v:101832.3-101880.6"
wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:103256.3-103304.6"
+ attribute \src "libresoc.v:101881.3-101929.6"
wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:103176.3-103206.6"
+ attribute \src "libresoc.v:101801.3-101831.6"
wire width 8 $0\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:102784.3-102832.6"
+ attribute \src "libresoc.v:101409.3-101457.6"
wire $0\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:102000.3-102048.6"
+ attribute \src "libresoc.v:100625.3-100673.6"
wire width 3 $0\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:102049.3-102097.6"
+ attribute \src "libresoc.v:100674.3-100722.6"
wire width 3 $0\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:102588.3-102636.6"
+ attribute \src "libresoc.v:101213.3-101261.6"
wire width 2 $0\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:102735.3-102783.6"
+ attribute \src "libresoc.v:101360.3-101408.6"
wire $0\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:103029.3-103077.6"
+ attribute \src "libresoc.v:101654.3-101702.6"
wire width 5 $0\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:101951.3-101999.6"
+ attribute \src "libresoc.v:100576.3-100624.6"
wire width 13 $0\dec31_dec_sub21_function_unit[12:0]
- attribute \src "libresoc.v:103305.3-103353.6"
+ attribute \src "libresoc.v:101930.3-101978.6"
wire width 3 $0\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:103354.3-103402.6"
+ attribute \src "libresoc.v:101979.3-102027.6"
wire width 4 $0\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:103403.3-103451.6"
+ attribute \src "libresoc.v:102028.3-102076.6"
wire width 2 $0\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:102490.3-102538.6"
+ attribute \src "libresoc.v:101115.3-101163.6"
wire width 7 $0\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:102637.3-102685.6"
+ attribute \src "libresoc.v:101262.3-101310.6"
wire $0\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:102686.3-102734.6"
+ attribute \src "libresoc.v:101311.3-101359.6"
wire $0\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:102931.3-102979.6"
+ attribute \src "libresoc.v:101556.3-101604.6"
wire $0\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:102392.3-102440.6"
+ attribute \src "libresoc.v:101017.3-101065.6"
wire width 4 $0\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:103078.3-103126.6"
+ attribute \src "libresoc.v:101703.3-101751.6"
wire $0\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:103452.3-103500.6"
+ attribute \src "libresoc.v:102077.3-102125.6"
wire width 2 $0\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:102539.3-102587.6"
+ attribute \src "libresoc.v:101164.3-101212.6"
wire width 2 $0\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:102882.3-102930.6"
+ attribute \src "libresoc.v:101507.3-101555.6"
wire $0\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:103127.3-103175.6"
+ attribute \src "libresoc.v:101752.3-101800.6"
wire $0\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:102980.3-103028.6"
+ attribute \src "libresoc.v:101605.3-101653.6"
wire $0\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:102833.3-102881.6"
+ attribute \src "libresoc.v:101458.3-101506.6"
wire $0\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:102294.3-102342.6"
+ attribute \src "libresoc.v:100919.3-100967.6"
wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:102343.3-102391.6"
+ attribute \src "libresoc.v:100968.3-101016.6"
wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:102098.3-102146.6"
+ attribute \src "libresoc.v:100723.3-100771.6"
wire width 3 $0\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:102147.3-102195.6"
+ attribute \src "libresoc.v:100772.3-100820.6"
wire width 3 $0\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:102196.3-102244.6"
+ attribute \src "libresoc.v:100821.3-100869.6"
wire width 3 $0\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:102245.3-102293.6"
+ attribute \src "libresoc.v:100870.3-100918.6"
wire width 3 $0\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:102441.3-102489.6"
+ attribute \src "libresoc.v:101066.3-101114.6"
wire width 2 $0\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:101616.7-101616.20"
+ attribute \src "libresoc.v:100241.7-100241.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:103207.3-103255.6"
+ attribute \src "libresoc.v:101832.3-101880.6"
wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:103256.3-103304.6"
+ attribute \src "libresoc.v:101881.3-101929.6"
wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:103176.3-103206.6"
+ attribute \src "libresoc.v:101801.3-101831.6"
wire width 8 $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:102784.3-102832.6"
+ attribute \src "libresoc.v:101409.3-101457.6"
wire $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:102000.3-102048.6"
+ attribute \src "libresoc.v:100625.3-100673.6"
wire width 3 $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:102049.3-102097.6"
+ attribute \src "libresoc.v:100674.3-100722.6"
wire width 3 $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:102588.3-102636.6"
+ attribute \src "libresoc.v:101213.3-101261.6"
wire width 2 $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:102735.3-102783.6"
+ attribute \src "libresoc.v:101360.3-101408.6"
wire $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:103029.3-103077.6"
+ attribute \src "libresoc.v:101654.3-101702.6"
wire width 5 $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:101951.3-101999.6"
+ attribute \src "libresoc.v:100576.3-100624.6"
wire width 13 $1\dec31_dec_sub21_function_unit[12:0]
- attribute \src "libresoc.v:103305.3-103353.6"
+ attribute \src "libresoc.v:101930.3-101978.6"
wire width 3 $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:103354.3-103402.6"
+ attribute \src "libresoc.v:101979.3-102027.6"
wire width 4 $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:103403.3-103451.6"
+ attribute \src "libresoc.v:102028.3-102076.6"
wire width 2 $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:102490.3-102538.6"
+ attribute \src "libresoc.v:101115.3-101163.6"
wire width 7 $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:102637.3-102685.6"
+ attribute \src "libresoc.v:101262.3-101310.6"
wire $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:102686.3-102734.6"
+ attribute \src "libresoc.v:101311.3-101359.6"
wire $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:102931.3-102979.6"
+ attribute \src "libresoc.v:101556.3-101604.6"
wire $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:102392.3-102440.6"
+ attribute \src "libresoc.v:101017.3-101065.6"
wire width 4 $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:103078.3-103126.6"
+ attribute \src "libresoc.v:101703.3-101751.6"
wire $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:103452.3-103500.6"
+ attribute \src "libresoc.v:102077.3-102125.6"
wire width 2 $1\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:102539.3-102587.6"
+ attribute \src "libresoc.v:101164.3-101212.6"
wire width 2 $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:102882.3-102930.6"
+ attribute \src "libresoc.v:101507.3-101555.6"
wire $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:103127.3-103175.6"
+ attribute \src "libresoc.v:101752.3-101800.6"
wire $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:102980.3-103028.6"
+ attribute \src "libresoc.v:101605.3-101653.6"
wire $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:102833.3-102881.6"
+ attribute \src "libresoc.v:101458.3-101506.6"
wire $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:102294.3-102342.6"
+ attribute \src "libresoc.v:100919.3-100967.6"
wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:102343.3-102391.6"
+ attribute \src "libresoc.v:100968.3-101016.6"
wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:102098.3-102146.6"
+ attribute \src "libresoc.v:100723.3-100771.6"
wire width 3 $1\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:102147.3-102195.6"
+ attribute \src "libresoc.v:100772.3-100820.6"
wire width 3 $1\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:102196.3-102244.6"
+ attribute \src "libresoc.v:100821.3-100869.6"
wire width 3 $1\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:102245.3-102293.6"
+ attribute \src "libresoc.v:100870.3-100918.6"
wire width 3 $1\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:102441.3-102489.6"
+ attribute \src "libresoc.v:101066.3-101114.6"
wire width 2 $1\dec31_dec_sub21_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub21_upd
- attribute \src "libresoc.v:101616.7-101616.15"
+ attribute \src "libresoc.v:100241.7-100241.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:101616.7-101616.20"
- process $proc$libresoc.v:101616$4149
+ attribute \src "libresoc.v:100241.7-100241.20"
+ process $proc$libresoc.v:100241$4093
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:101951.3-101999.6"
- process $proc$libresoc.v:101951$4117
+ attribute \src "libresoc.v:100576.3-100624.6"
+ process $proc$libresoc.v:100576$4061
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_function_unit[12:0] $1\dec31_dec_sub21_function_unit[12:0]
- attribute \src "libresoc.v:101952.5-101952.29"
+ attribute \src "libresoc.v:100577.5-100577.29"
switch \initial
- attribute \src "libresoc.v:101952.9-101952.17"
+ attribute \src "libresoc.v:100577.9-100577.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[12:0]
end
- attribute \src "libresoc.v:102000.3-102048.6"
- process $proc$libresoc.v:102000$4118
+ attribute \src "libresoc.v:100625.3-100673.6"
+ process $proc$libresoc.v:100625$4062
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:102001.5-102001.29"
+ attribute \src "libresoc.v:100626.5-100626.29"
switch \initial
- attribute \src "libresoc.v:102001.9-102001.17"
+ attribute \src "libresoc.v:100626.9-100626.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0]
end
- attribute \src "libresoc.v:102049.3-102097.6"
- process $proc$libresoc.v:102049$4119
+ attribute \src "libresoc.v:100674.3-100722.6"
+ process $proc$libresoc.v:100674$4063
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:102050.5-102050.29"
+ attribute \src "libresoc.v:100675.5-100675.29"
switch \initial
- attribute \src "libresoc.v:102050.9-102050.17"
+ attribute \src "libresoc.v:100675.9-100675.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0]
end
- attribute \src "libresoc.v:102098.3-102146.6"
- process $proc$libresoc.v:102098$4120
+ attribute \src "libresoc.v:100723.3-100771.6"
+ process $proc$libresoc.v:100723$4064
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0]
- attribute \src "libresoc.v:102099.5-102099.29"
+ attribute \src "libresoc.v:100724.5-100724.29"
switch \initial
- attribute \src "libresoc.v:102099.9-102099.17"
+ attribute \src "libresoc.v:100724.9-100724.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0]
end
- attribute \src "libresoc.v:102147.3-102195.6"
- process $proc$libresoc.v:102147$4121
+ attribute \src "libresoc.v:100772.3-100820.6"
+ process $proc$libresoc.v:100772$4065
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0]
- attribute \src "libresoc.v:102148.5-102148.29"
+ attribute \src "libresoc.v:100773.5-100773.29"
switch \initial
- attribute \src "libresoc.v:102148.9-102148.17"
+ attribute \src "libresoc.v:100773.9-100773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0]
end
- attribute \src "libresoc.v:102196.3-102244.6"
- process $proc$libresoc.v:102196$4122
+ attribute \src "libresoc.v:100821.3-100869.6"
+ process $proc$libresoc.v:100821$4066
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0]
- attribute \src "libresoc.v:102197.5-102197.29"
+ attribute \src "libresoc.v:100822.5-100822.29"
switch \initial
- attribute \src "libresoc.v:102197.9-102197.17"
+ attribute \src "libresoc.v:100822.9-100822.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0]
end
- attribute \src "libresoc.v:102245.3-102293.6"
- process $proc$libresoc.v:102245$4123
+ attribute \src "libresoc.v:100870.3-100918.6"
+ process $proc$libresoc.v:100870$4067
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0]
- attribute \src "libresoc.v:102246.5-102246.29"
+ attribute \src "libresoc.v:100871.5-100871.29"
switch \initial
- attribute \src "libresoc.v:102246.9-102246.17"
+ attribute \src "libresoc.v:100871.9-100871.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0]
end
- attribute \src "libresoc.v:102294.3-102342.6"
- process $proc$libresoc.v:102294$4124
+ attribute \src "libresoc.v:100919.3-100967.6"
+ process $proc$libresoc.v:100919$4068
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0]
- attribute \src "libresoc.v:102295.5-102295.29"
+ attribute \src "libresoc.v:100920.5-100920.29"
switch \initial
- attribute \src "libresoc.v:102295.9-102295.17"
+ attribute \src "libresoc.v:100920.9-100920.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:102343.3-102391.6"
- process $proc$libresoc.v:102343$4125
+ attribute \src "libresoc.v:100968.3-101016.6"
+ process $proc$libresoc.v:100968$4069
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0]
- attribute \src "libresoc.v:102344.5-102344.29"
+ attribute \src "libresoc.v:100969.5-100969.29"
switch \initial
- attribute \src "libresoc.v:102344.9-102344.17"
+ attribute \src "libresoc.v:100969.9-100969.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:102392.3-102440.6"
- process $proc$libresoc.v:102392$4126
+ attribute \src "libresoc.v:101017.3-101065.6"
+ process $proc$libresoc.v:101017$4070
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:102393.5-102393.29"
+ attribute \src "libresoc.v:101018.5-101018.29"
switch \initial
- attribute \src "libresoc.v:102393.9-102393.17"
+ attribute \src "libresoc.v:101018.9-101018.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0]
end
- attribute \src "libresoc.v:102441.3-102489.6"
- process $proc$libresoc.v:102441$4127
+ attribute \src "libresoc.v:101066.3-101114.6"
+ process $proc$libresoc.v:101066$4071
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:102442.5-102442.29"
+ attribute \src "libresoc.v:101067.5-101067.29"
switch \initial
- attribute \src "libresoc.v:102442.9-102442.17"
+ attribute \src "libresoc.v:101067.9-101067.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0]
end
- attribute \src "libresoc.v:102490.3-102538.6"
- process $proc$libresoc.v:102490$4128
+ attribute \src "libresoc.v:101115.3-101163.6"
+ process $proc$libresoc.v:101115$4072
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:102491.5-102491.29"
+ attribute \src "libresoc.v:101116.5-101116.29"
switch \initial
- attribute \src "libresoc.v:102491.9-102491.17"
+ attribute \src "libresoc.v:101116.9-101116.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0]
end
- attribute \src "libresoc.v:102539.3-102587.6"
- process $proc$libresoc.v:102539$4129
+ attribute \src "libresoc.v:101164.3-101212.6"
+ process $proc$libresoc.v:101164$4073
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:102540.5-102540.29"
+ attribute \src "libresoc.v:101165.5-101165.29"
switch \initial
- attribute \src "libresoc.v:102540.9-102540.17"
+ attribute \src "libresoc.v:101165.9-101165.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0]
end
- attribute \src "libresoc.v:102588.3-102636.6"
- process $proc$libresoc.v:102588$4130
+ attribute \src "libresoc.v:101213.3-101261.6"
+ process $proc$libresoc.v:101213$4074
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:102589.5-102589.29"
+ attribute \src "libresoc.v:101214.5-101214.29"
switch \initial
- attribute \src "libresoc.v:102589.9-102589.17"
+ attribute \src "libresoc.v:101214.9-101214.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0]
end
- attribute \src "libresoc.v:102637.3-102685.6"
- process $proc$libresoc.v:102637$4131
+ attribute \src "libresoc.v:101262.3-101310.6"
+ process $proc$libresoc.v:101262$4075
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:102638.5-102638.29"
+ attribute \src "libresoc.v:101263.5-101263.29"
switch \initial
- attribute \src "libresoc.v:102638.9-102638.17"
+ attribute \src "libresoc.v:101263.9-101263.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0]
end
- attribute \src "libresoc.v:102686.3-102734.6"
- process $proc$libresoc.v:102686$4132
+ attribute \src "libresoc.v:101311.3-101359.6"
+ process $proc$libresoc.v:101311$4076
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:102687.5-102687.29"
+ attribute \src "libresoc.v:101312.5-101312.29"
switch \initial
- attribute \src "libresoc.v:102687.9-102687.17"
+ attribute \src "libresoc.v:101312.9-101312.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0]
end
- attribute \src "libresoc.v:102735.3-102783.6"
- process $proc$libresoc.v:102735$4133
+ attribute \src "libresoc.v:101360.3-101408.6"
+ process $proc$libresoc.v:101360$4077
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:102736.5-102736.29"
+ attribute \src "libresoc.v:101361.5-101361.29"
switch \initial
- attribute \src "libresoc.v:102736.9-102736.17"
+ attribute \src "libresoc.v:101361.9-101361.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0]
end
- attribute \src "libresoc.v:102784.3-102832.6"
- process $proc$libresoc.v:102784$4134
+ attribute \src "libresoc.v:101409.3-101457.6"
+ process $proc$libresoc.v:101409$4078
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:102785.5-102785.29"
+ attribute \src "libresoc.v:101410.5-101410.29"
switch \initial
- attribute \src "libresoc.v:102785.9-102785.17"
+ attribute \src "libresoc.v:101410.9-101410.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0]
end
- attribute \src "libresoc.v:102833.3-102881.6"
- process $proc$libresoc.v:102833$4135
+ attribute \src "libresoc.v:101458.3-101506.6"
+ process $proc$libresoc.v:101458$4079
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:102834.5-102834.29"
+ attribute \src "libresoc.v:101459.5-101459.29"
switch \initial
- attribute \src "libresoc.v:102834.9-102834.17"
+ attribute \src "libresoc.v:101459.9-101459.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0]
end
- attribute \src "libresoc.v:102882.3-102930.6"
- process $proc$libresoc.v:102882$4136
+ attribute \src "libresoc.v:101507.3-101555.6"
+ process $proc$libresoc.v:101507$4080
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:102883.5-102883.29"
+ attribute \src "libresoc.v:101508.5-101508.29"
switch \initial
- attribute \src "libresoc.v:102883.9-102883.17"
+ attribute \src "libresoc.v:101508.9-101508.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0]
end
- attribute \src "libresoc.v:102931.3-102979.6"
- process $proc$libresoc.v:102931$4137
+ attribute \src "libresoc.v:101556.3-101604.6"
+ process $proc$libresoc.v:101556$4081
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:102932.5-102932.29"
+ attribute \src "libresoc.v:101557.5-101557.29"
switch \initial
- attribute \src "libresoc.v:102932.9-102932.17"
+ attribute \src "libresoc.v:101557.9-101557.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0]
end
- attribute \src "libresoc.v:102980.3-103028.6"
- process $proc$libresoc.v:102980$4138
+ attribute \src "libresoc.v:101605.3-101653.6"
+ process $proc$libresoc.v:101605$4082
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:102981.5-102981.29"
+ attribute \src "libresoc.v:101606.5-101606.29"
switch \initial
- attribute \src "libresoc.v:102981.9-102981.17"
+ attribute \src "libresoc.v:101606.9-101606.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0]
end
- attribute \src "libresoc.v:103029.3-103077.6"
- process $proc$libresoc.v:103029$4139
+ attribute \src "libresoc.v:101654.3-101702.6"
+ process $proc$libresoc.v:101654$4083
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:103030.5-103030.29"
+ attribute \src "libresoc.v:101655.5-101655.29"
switch \initial
- attribute \src "libresoc.v:103030.9-103030.17"
+ attribute \src "libresoc.v:101655.9-101655.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0]
end
- attribute \src "libresoc.v:103078.3-103126.6"
- process $proc$libresoc.v:103078$4140
+ attribute \src "libresoc.v:101703.3-101751.6"
+ process $proc$libresoc.v:101703$4084
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:103079.5-103079.29"
+ attribute \src "libresoc.v:101704.5-101704.29"
switch \initial
- attribute \src "libresoc.v:103079.9-103079.17"
+ attribute \src "libresoc.v:101704.9-101704.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0]
end
- attribute \src "libresoc.v:103127.3-103175.6"
- process $proc$libresoc.v:103127$4141
+ attribute \src "libresoc.v:101752.3-101800.6"
+ process $proc$libresoc.v:101752$4085
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:103128.5-103128.29"
+ attribute \src "libresoc.v:101753.5-101753.29"
switch \initial
- attribute \src "libresoc.v:103128.9-103128.17"
+ attribute \src "libresoc.v:101753.9-101753.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:103176.3-103206.6"
- process $proc$libresoc.v:103176$4142
+ attribute \src "libresoc.v:101801.3-101831.6"
+ process $proc$libresoc.v:101801$4086
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:103177.5-103177.29"
+ attribute \src "libresoc.v:101802.5-101802.29"
switch \initial
- attribute \src "libresoc.v:103177.9-103177.17"
+ attribute \src "libresoc.v:101802.9-101802.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0]
end
- attribute \src "libresoc.v:103207.3-103255.6"
- process $proc$libresoc.v:103207$4143
+ attribute \src "libresoc.v:101832.3-101880.6"
+ process $proc$libresoc.v:101832$4087
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0]
- attribute \src "libresoc.v:103208.5-103208.29"
+ attribute \src "libresoc.v:101833.5-101833.29"
switch \initial
- attribute \src "libresoc.v:103208.9-103208.17"
+ attribute \src "libresoc.v:101833.9-101833.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0]
end
- attribute \src "libresoc.v:103256.3-103304.6"
- process $proc$libresoc.v:103256$4144
+ attribute \src "libresoc.v:101881.3-101929.6"
+ process $proc$libresoc.v:101881$4088
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0]
- attribute \src "libresoc.v:103257.5-103257.29"
+ attribute \src "libresoc.v:101882.5-101882.29"
switch \initial
- attribute \src "libresoc.v:103257.9-103257.17"
+ attribute \src "libresoc.v:101882.9-101882.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:103305.3-103353.6"
- process $proc$libresoc.v:103305$4145
+ attribute \src "libresoc.v:101930.3-101978.6"
+ process $proc$libresoc.v:101930$4089
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:103306.5-103306.29"
+ attribute \src "libresoc.v:101931.5-101931.29"
switch \initial
- attribute \src "libresoc.v:103306.9-103306.17"
+ attribute \src "libresoc.v:101931.9-101931.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0]
end
- attribute \src "libresoc.v:103354.3-103402.6"
- process $proc$libresoc.v:103354$4146
+ attribute \src "libresoc.v:101979.3-102027.6"
+ process $proc$libresoc.v:101979$4090
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:103355.5-103355.29"
+ attribute \src "libresoc.v:101980.5-101980.29"
switch \initial
- attribute \src "libresoc.v:103355.9-103355.17"
+ attribute \src "libresoc.v:101980.9-101980.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0]
end
- attribute \src "libresoc.v:103403.3-103451.6"
- process $proc$libresoc.v:103403$4147
+ attribute \src "libresoc.v:102028.3-102076.6"
+ process $proc$libresoc.v:102028$4091
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:103404.5-103404.29"
+ attribute \src "libresoc.v:102029.5-102029.29"
switch \initial
- attribute \src "libresoc.v:103404.9-103404.17"
+ attribute \src "libresoc.v:102029.9-102029.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0]
end
- attribute \src "libresoc.v:103452.3-103500.6"
- process $proc$libresoc.v:103452$4148
+ attribute \src "libresoc.v:102077.3-102125.6"
+ process $proc$libresoc.v:102077$4092
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:103453.5-103453.29"
+ attribute \src "libresoc.v:102078.5-102078.29"
switch \initial
- attribute \src "libresoc.v:103453.9-103453.17"
+ attribute \src "libresoc.v:102078.9-102078.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:103506.1-105603.10"
+attribute \src "libresoc.v:102131.1-104228.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22"
attribute \generator "nMigen"
module \dec31_dec_sub22
- attribute \src "libresoc.v:105272.3-105326.6"
+ attribute \src "libresoc.v:103897.3-103951.6"
wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:105327.3-105381.6"
+ attribute \src "libresoc.v:103952.3-104006.6"
wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:104612.3-104666.6"
+ attribute \src "libresoc.v:103237.3-103291.6"
wire width 8 $0\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:104832.3-104886.6"
+ attribute \src "libresoc.v:103457.3-103511.6"
wire $0\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:103897.3-103951.6"
+ attribute \src "libresoc.v:102522.3-102576.6"
wire width 3 $0\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:103952.3-104006.6"
+ attribute \src "libresoc.v:102577.3-102631.6"
wire width 3 $0\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:104557.3-104611.6"
+ attribute \src "libresoc.v:103182.3-103236.6"
wire width 2 $0\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:104777.3-104831.6"
+ attribute \src "libresoc.v:103402.3-103456.6"
wire $0\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:105052.3-105106.6"
+ attribute \src "libresoc.v:103677.3-103731.6"
wire width 5 $0\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:103842.3-103896.6"
+ attribute \src "libresoc.v:102467.3-102521.6"
wire width 13 $0\dec31_dec_sub22_function_unit[12:0]
- attribute \src "libresoc.v:105382.3-105436.6"
+ attribute \src "libresoc.v:104007.3-104061.6"
wire width 3 $0\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:105437.3-105491.6"
+ attribute \src "libresoc.v:104062.3-104116.6"
wire width 4 $0\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:105492.3-105546.6"
+ attribute \src "libresoc.v:104117.3-104171.6"
wire width 2 $0\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:104447.3-104501.6"
+ attribute \src "libresoc.v:103072.3-103126.6"
wire width 7 $0\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:104667.3-104721.6"
+ attribute \src "libresoc.v:103292.3-103346.6"
wire $0\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:104722.3-104776.6"
+ attribute \src "libresoc.v:103347.3-103401.6"
wire $0\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:104997.3-105051.6"
+ attribute \src "libresoc.v:103622.3-103676.6"
wire $0\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:104337.3-104391.6"
+ attribute \src "libresoc.v:102962.3-103016.6"
wire width 4 $0\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:105162.3-105216.6"
+ attribute \src "libresoc.v:103787.3-103841.6"
wire $0\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:105547.3-105601.6"
+ attribute \src "libresoc.v:104172.3-104226.6"
wire width 2 $0\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:104502.3-104556.6"
+ attribute \src "libresoc.v:103127.3-103181.6"
wire width 2 $0\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:104942.3-104996.6"
+ attribute \src "libresoc.v:103567.3-103621.6"
wire $0\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:105217.3-105271.6"
+ attribute \src "libresoc.v:103842.3-103896.6"
wire $0\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:105107.3-105161.6"
+ attribute \src "libresoc.v:103732.3-103786.6"
wire $0\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:104887.3-104941.6"
+ attribute \src "libresoc.v:103512.3-103566.6"
wire $0\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:104227.3-104281.6"
+ attribute \src "libresoc.v:102852.3-102906.6"
wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:104282.3-104336.6"
+ attribute \src "libresoc.v:102907.3-102961.6"
wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:104007.3-104061.6"
+ attribute \src "libresoc.v:102632.3-102686.6"
wire width 3 $0\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:104062.3-104116.6"
+ attribute \src "libresoc.v:102687.3-102741.6"
wire width 3 $0\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:104117.3-104171.6"
+ attribute \src "libresoc.v:102742.3-102796.6"
wire width 3 $0\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:104172.3-104226.6"
+ attribute \src "libresoc.v:102797.3-102851.6"
wire width 3 $0\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:104392.3-104446.6"
+ attribute \src "libresoc.v:103017.3-103071.6"
wire width 2 $0\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:103507.7-103507.20"
+ attribute \src "libresoc.v:102132.7-102132.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:105272.3-105326.6"
+ attribute \src "libresoc.v:103897.3-103951.6"
wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:105327.3-105381.6"
+ attribute \src "libresoc.v:103952.3-104006.6"
wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:104612.3-104666.6"
+ attribute \src "libresoc.v:103237.3-103291.6"
wire width 8 $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:104832.3-104886.6"
+ attribute \src "libresoc.v:103457.3-103511.6"
wire $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:103897.3-103951.6"
+ attribute \src "libresoc.v:102522.3-102576.6"
wire width 3 $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:103952.3-104006.6"
+ attribute \src "libresoc.v:102577.3-102631.6"
wire width 3 $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:104557.3-104611.6"
+ attribute \src "libresoc.v:103182.3-103236.6"
wire width 2 $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:104777.3-104831.6"
+ attribute \src "libresoc.v:103402.3-103456.6"
wire $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:105052.3-105106.6"
+ attribute \src "libresoc.v:103677.3-103731.6"
wire width 5 $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:103842.3-103896.6"
+ attribute \src "libresoc.v:102467.3-102521.6"
wire width 13 $1\dec31_dec_sub22_function_unit[12:0]
- attribute \src "libresoc.v:105382.3-105436.6"
+ attribute \src "libresoc.v:104007.3-104061.6"
wire width 3 $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:105437.3-105491.6"
+ attribute \src "libresoc.v:104062.3-104116.6"
wire width 4 $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:105492.3-105546.6"
+ attribute \src "libresoc.v:104117.3-104171.6"
wire width 2 $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:104447.3-104501.6"
+ attribute \src "libresoc.v:103072.3-103126.6"
wire width 7 $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:104667.3-104721.6"
+ attribute \src "libresoc.v:103292.3-103346.6"
wire $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:104722.3-104776.6"
+ attribute \src "libresoc.v:103347.3-103401.6"
wire $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:104997.3-105051.6"
+ attribute \src "libresoc.v:103622.3-103676.6"
wire $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:104337.3-104391.6"
+ attribute \src "libresoc.v:102962.3-103016.6"
wire width 4 $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:105162.3-105216.6"
+ attribute \src "libresoc.v:103787.3-103841.6"
wire $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:105547.3-105601.6"
+ attribute \src "libresoc.v:104172.3-104226.6"
wire width 2 $1\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:104502.3-104556.6"
+ attribute \src "libresoc.v:103127.3-103181.6"
wire width 2 $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:104942.3-104996.6"
+ attribute \src "libresoc.v:103567.3-103621.6"
wire $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:105217.3-105271.6"
+ attribute \src "libresoc.v:103842.3-103896.6"
wire $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:105107.3-105161.6"
+ attribute \src "libresoc.v:103732.3-103786.6"
wire $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:104887.3-104941.6"
+ attribute \src "libresoc.v:103512.3-103566.6"
wire $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:104227.3-104281.6"
+ attribute \src "libresoc.v:102852.3-102906.6"
wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:104282.3-104336.6"
+ attribute \src "libresoc.v:102907.3-102961.6"
wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:104007.3-104061.6"
+ attribute \src "libresoc.v:102632.3-102686.6"
wire width 3 $1\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:104062.3-104116.6"
+ attribute \src "libresoc.v:102687.3-102741.6"
wire width 3 $1\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:104117.3-104171.6"
+ attribute \src "libresoc.v:102742.3-102796.6"
wire width 3 $1\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:104172.3-104226.6"
+ attribute \src "libresoc.v:102797.3-102851.6"
wire width 3 $1\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:104392.3-104446.6"
+ attribute \src "libresoc.v:103017.3-103071.6"
wire width 2 $1\dec31_dec_sub22_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub22_upd
- attribute \src "libresoc.v:103507.7-103507.15"
+ attribute \src "libresoc.v:102132.7-102132.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:103507.7-103507.20"
- process $proc$libresoc.v:103507$4182
+ attribute \src "libresoc.v:102132.7-102132.20"
+ process $proc$libresoc.v:102132$4126
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:103842.3-103896.6"
- process $proc$libresoc.v:103842$4150
+ attribute \src "libresoc.v:102467.3-102521.6"
+ process $proc$libresoc.v:102467$4094
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_function_unit[12:0] $1\dec31_dec_sub22_function_unit[12:0]
- attribute \src "libresoc.v:103843.5-103843.29"
+ attribute \src "libresoc.v:102468.5-102468.29"
switch \initial
- attribute \src "libresoc.v:103843.9-103843.17"
+ attribute \src "libresoc.v:102468.9-102468.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[12:0]
end
- attribute \src "libresoc.v:103897.3-103951.6"
- process $proc$libresoc.v:103897$4151
+ attribute \src "libresoc.v:102522.3-102576.6"
+ process $proc$libresoc.v:102522$4095
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:103898.5-103898.29"
+ attribute \src "libresoc.v:102523.5-102523.29"
switch \initial
- attribute \src "libresoc.v:103898.9-103898.17"
+ attribute \src "libresoc.v:102523.9-102523.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0]
end
- attribute \src "libresoc.v:103952.3-104006.6"
- process $proc$libresoc.v:103952$4152
+ attribute \src "libresoc.v:102577.3-102631.6"
+ process $proc$libresoc.v:102577$4096
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:103953.5-103953.29"
+ attribute \src "libresoc.v:102578.5-102578.29"
switch \initial
- attribute \src "libresoc.v:103953.9-103953.17"
+ attribute \src "libresoc.v:102578.9-102578.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0]
end
- attribute \src "libresoc.v:104007.3-104061.6"
- process $proc$libresoc.v:104007$4153
+ attribute \src "libresoc.v:102632.3-102686.6"
+ process $proc$libresoc.v:102632$4097
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0]
- attribute \src "libresoc.v:104008.5-104008.29"
+ attribute \src "libresoc.v:102633.5-102633.29"
switch \initial
- attribute \src "libresoc.v:104008.9-104008.17"
+ attribute \src "libresoc.v:102633.9-102633.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0]
end
- attribute \src "libresoc.v:104062.3-104116.6"
- process $proc$libresoc.v:104062$4154
+ attribute \src "libresoc.v:102687.3-102741.6"
+ process $proc$libresoc.v:102687$4098
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0]
- attribute \src "libresoc.v:104063.5-104063.29"
+ attribute \src "libresoc.v:102688.5-102688.29"
switch \initial
- attribute \src "libresoc.v:104063.9-104063.17"
+ attribute \src "libresoc.v:102688.9-102688.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0]
end
- attribute \src "libresoc.v:104117.3-104171.6"
- process $proc$libresoc.v:104117$4155
+ attribute \src "libresoc.v:102742.3-102796.6"
+ process $proc$libresoc.v:102742$4099
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0]
- attribute \src "libresoc.v:104118.5-104118.29"
+ attribute \src "libresoc.v:102743.5-102743.29"
switch \initial
- attribute \src "libresoc.v:104118.9-104118.17"
+ attribute \src "libresoc.v:102743.9-102743.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0]
end
- attribute \src "libresoc.v:104172.3-104226.6"
- process $proc$libresoc.v:104172$4156
+ attribute \src "libresoc.v:102797.3-102851.6"
+ process $proc$libresoc.v:102797$4100
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0]
- attribute \src "libresoc.v:104173.5-104173.29"
+ attribute \src "libresoc.v:102798.5-102798.29"
switch \initial
- attribute \src "libresoc.v:104173.9-104173.17"
+ attribute \src "libresoc.v:102798.9-102798.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0]
end
- attribute \src "libresoc.v:104227.3-104281.6"
- process $proc$libresoc.v:104227$4157
+ attribute \src "libresoc.v:102852.3-102906.6"
+ process $proc$libresoc.v:102852$4101
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0]
- attribute \src "libresoc.v:104228.5-104228.29"
+ attribute \src "libresoc.v:102853.5-102853.29"
switch \initial
- attribute \src "libresoc.v:104228.9-104228.17"
+ attribute \src "libresoc.v:102853.9-102853.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:104282.3-104336.6"
- process $proc$libresoc.v:104282$4158
+ attribute \src "libresoc.v:102907.3-102961.6"
+ process $proc$libresoc.v:102907$4102
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0]
- attribute \src "libresoc.v:104283.5-104283.29"
+ attribute \src "libresoc.v:102908.5-102908.29"
switch \initial
- attribute \src "libresoc.v:104283.9-104283.17"
+ attribute \src "libresoc.v:102908.9-102908.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:104337.3-104391.6"
- process $proc$libresoc.v:104337$4159
+ attribute \src "libresoc.v:102962.3-103016.6"
+ process $proc$libresoc.v:102962$4103
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:104338.5-104338.29"
+ attribute \src "libresoc.v:102963.5-102963.29"
switch \initial
- attribute \src "libresoc.v:104338.9-104338.17"
+ attribute \src "libresoc.v:102963.9-102963.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0]
end
- attribute \src "libresoc.v:104392.3-104446.6"
- process $proc$libresoc.v:104392$4160
+ attribute \src "libresoc.v:103017.3-103071.6"
+ process $proc$libresoc.v:103017$4104
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:104393.5-104393.29"
+ attribute \src "libresoc.v:103018.5-103018.29"
switch \initial
- attribute \src "libresoc.v:104393.9-104393.17"
+ attribute \src "libresoc.v:103018.9-103018.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0]
end
- attribute \src "libresoc.v:104447.3-104501.6"
- process $proc$libresoc.v:104447$4161
+ attribute \src "libresoc.v:103072.3-103126.6"
+ process $proc$libresoc.v:103072$4105
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:104448.5-104448.29"
+ attribute \src "libresoc.v:103073.5-103073.29"
switch \initial
- attribute \src "libresoc.v:104448.9-104448.17"
+ attribute \src "libresoc.v:103073.9-103073.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0]
end
- attribute \src "libresoc.v:104502.3-104556.6"
- process $proc$libresoc.v:104502$4162
+ attribute \src "libresoc.v:103127.3-103181.6"
+ process $proc$libresoc.v:103127$4106
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:104503.5-104503.29"
+ attribute \src "libresoc.v:103128.5-103128.29"
switch \initial
- attribute \src "libresoc.v:104503.9-104503.17"
+ attribute \src "libresoc.v:103128.9-103128.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0]
end
- attribute \src "libresoc.v:104557.3-104611.6"
- process $proc$libresoc.v:104557$4163
+ attribute \src "libresoc.v:103182.3-103236.6"
+ process $proc$libresoc.v:103182$4107
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:104558.5-104558.29"
+ attribute \src "libresoc.v:103183.5-103183.29"
switch \initial
- attribute \src "libresoc.v:104558.9-104558.17"
+ attribute \src "libresoc.v:103183.9-103183.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0]
end
- attribute \src "libresoc.v:104612.3-104666.6"
- process $proc$libresoc.v:104612$4164
+ attribute \src "libresoc.v:103237.3-103291.6"
+ process $proc$libresoc.v:103237$4108
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:104613.5-104613.29"
+ attribute \src "libresoc.v:103238.5-103238.29"
switch \initial
- attribute \src "libresoc.v:104613.9-104613.17"
+ attribute \src "libresoc.v:103238.9-103238.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0]
end
- attribute \src "libresoc.v:104667.3-104721.6"
- process $proc$libresoc.v:104667$4165
+ attribute \src "libresoc.v:103292.3-103346.6"
+ process $proc$libresoc.v:103292$4109
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:104668.5-104668.29"
+ attribute \src "libresoc.v:103293.5-103293.29"
switch \initial
- attribute \src "libresoc.v:104668.9-104668.17"
+ attribute \src "libresoc.v:103293.9-103293.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0]
end
- attribute \src "libresoc.v:104722.3-104776.6"
- process $proc$libresoc.v:104722$4166
+ attribute \src "libresoc.v:103347.3-103401.6"
+ process $proc$libresoc.v:103347$4110
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:104723.5-104723.29"
+ attribute \src "libresoc.v:103348.5-103348.29"
switch \initial
- attribute \src "libresoc.v:104723.9-104723.17"
+ attribute \src "libresoc.v:103348.9-103348.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0]
end
- attribute \src "libresoc.v:104777.3-104831.6"
- process $proc$libresoc.v:104777$4167
+ attribute \src "libresoc.v:103402.3-103456.6"
+ process $proc$libresoc.v:103402$4111
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:104778.5-104778.29"
+ attribute \src "libresoc.v:103403.5-103403.29"
switch \initial
- attribute \src "libresoc.v:104778.9-104778.17"
+ attribute \src "libresoc.v:103403.9-103403.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0]
end
- attribute \src "libresoc.v:104832.3-104886.6"
- process $proc$libresoc.v:104832$4168
+ attribute \src "libresoc.v:103457.3-103511.6"
+ process $proc$libresoc.v:103457$4112
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:104833.5-104833.29"
+ attribute \src "libresoc.v:103458.5-103458.29"
switch \initial
- attribute \src "libresoc.v:104833.9-104833.17"
+ attribute \src "libresoc.v:103458.9-103458.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0]
end
- attribute \src "libresoc.v:104887.3-104941.6"
- process $proc$libresoc.v:104887$4169
+ attribute \src "libresoc.v:103512.3-103566.6"
+ process $proc$libresoc.v:103512$4113
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:104888.5-104888.29"
+ attribute \src "libresoc.v:103513.5-103513.29"
switch \initial
- attribute \src "libresoc.v:104888.9-104888.17"
+ attribute \src "libresoc.v:103513.9-103513.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0]
end
- attribute \src "libresoc.v:104942.3-104996.6"
- process $proc$libresoc.v:104942$4170
+ attribute \src "libresoc.v:103567.3-103621.6"
+ process $proc$libresoc.v:103567$4114
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:104943.5-104943.29"
+ attribute \src "libresoc.v:103568.5-103568.29"
switch \initial
- attribute \src "libresoc.v:104943.9-104943.17"
+ attribute \src "libresoc.v:103568.9-103568.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0]
end
- attribute \src "libresoc.v:104997.3-105051.6"
- process $proc$libresoc.v:104997$4171
+ attribute \src "libresoc.v:103622.3-103676.6"
+ process $proc$libresoc.v:103622$4115
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:104998.5-104998.29"
+ attribute \src "libresoc.v:103623.5-103623.29"
switch \initial
- attribute \src "libresoc.v:104998.9-104998.17"
+ attribute \src "libresoc.v:103623.9-103623.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0]
end
- attribute \src "libresoc.v:105052.3-105106.6"
- process $proc$libresoc.v:105052$4172
+ attribute \src "libresoc.v:103677.3-103731.6"
+ process $proc$libresoc.v:103677$4116
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:105053.5-105053.29"
+ attribute \src "libresoc.v:103678.5-103678.29"
switch \initial
- attribute \src "libresoc.v:105053.9-105053.17"
+ attribute \src "libresoc.v:103678.9-103678.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0]
end
- attribute \src "libresoc.v:105107.3-105161.6"
- process $proc$libresoc.v:105107$4173
+ attribute \src "libresoc.v:103732.3-103786.6"
+ process $proc$libresoc.v:103732$4117
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:105108.5-105108.29"
+ attribute \src "libresoc.v:103733.5-103733.29"
switch \initial
- attribute \src "libresoc.v:105108.9-105108.17"
+ attribute \src "libresoc.v:103733.9-103733.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0]
end
- attribute \src "libresoc.v:105162.3-105216.6"
- process $proc$libresoc.v:105162$4174
+ attribute \src "libresoc.v:103787.3-103841.6"
+ process $proc$libresoc.v:103787$4118
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:105163.5-105163.29"
+ attribute \src "libresoc.v:103788.5-103788.29"
switch \initial
- attribute \src "libresoc.v:105163.9-105163.17"
+ attribute \src "libresoc.v:103788.9-103788.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0]
end
- attribute \src "libresoc.v:105217.3-105271.6"
- process $proc$libresoc.v:105217$4175
+ attribute \src "libresoc.v:103842.3-103896.6"
+ process $proc$libresoc.v:103842$4119
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:105218.5-105218.29"
+ attribute \src "libresoc.v:103843.5-103843.29"
switch \initial
- attribute \src "libresoc.v:105218.9-105218.17"
+ attribute \src "libresoc.v:103843.9-103843.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:105272.3-105326.6"
- process $proc$libresoc.v:105272$4176
+ attribute \src "libresoc.v:103897.3-103951.6"
+ process $proc$libresoc.v:103897$4120
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0]
- attribute \src "libresoc.v:105273.5-105273.29"
+ attribute \src "libresoc.v:103898.5-103898.29"
switch \initial
- attribute \src "libresoc.v:105273.9-105273.17"
+ attribute \src "libresoc.v:103898.9-103898.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0]
end
- attribute \src "libresoc.v:105327.3-105381.6"
- process $proc$libresoc.v:105327$4177
+ attribute \src "libresoc.v:103952.3-104006.6"
+ process $proc$libresoc.v:103952$4121
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0]
- attribute \src "libresoc.v:105328.5-105328.29"
+ attribute \src "libresoc.v:103953.5-103953.29"
switch \initial
- attribute \src "libresoc.v:105328.9-105328.17"
+ attribute \src "libresoc.v:103953.9-103953.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:105382.3-105436.6"
- process $proc$libresoc.v:105382$4178
+ attribute \src "libresoc.v:104007.3-104061.6"
+ process $proc$libresoc.v:104007$4122
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:105383.5-105383.29"
+ attribute \src "libresoc.v:104008.5-104008.29"
switch \initial
- attribute \src "libresoc.v:105383.9-105383.17"
+ attribute \src "libresoc.v:104008.9-104008.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0]
end
- attribute \src "libresoc.v:105437.3-105491.6"
- process $proc$libresoc.v:105437$4179
+ attribute \src "libresoc.v:104062.3-104116.6"
+ process $proc$libresoc.v:104062$4123
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:105438.5-105438.29"
+ attribute \src "libresoc.v:104063.5-104063.29"
switch \initial
- attribute \src "libresoc.v:105438.9-105438.17"
+ attribute \src "libresoc.v:104063.9-104063.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0]
end
- attribute \src "libresoc.v:105492.3-105546.6"
- process $proc$libresoc.v:105492$4180
+ attribute \src "libresoc.v:104117.3-104171.6"
+ process $proc$libresoc.v:104117$4124
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:105493.5-105493.29"
+ attribute \src "libresoc.v:104118.5-104118.29"
switch \initial
- attribute \src "libresoc.v:105493.9-105493.17"
+ attribute \src "libresoc.v:104118.9-104118.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0]
end
- attribute \src "libresoc.v:105547.3-105601.6"
- process $proc$libresoc.v:105547$4181
+ attribute \src "libresoc.v:104172.3-104226.6"
+ process $proc$libresoc.v:104172$4125
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:105548.5-105548.29"
+ attribute \src "libresoc.v:104173.5-104173.29"
switch \initial
- attribute \src "libresoc.v:105548.9-105548.17"
+ attribute \src "libresoc.v:104173.9-104173.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:105607.1-107512.10"
+attribute \src "libresoc.v:104232.1-106137.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23"
attribute \generator "nMigen"
module \dec31_dec_sub23
- attribute \src "libresoc.v:107217.3-107265.6"
+ attribute \src "libresoc.v:105842.3-105890.6"
wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:107266.3-107314.6"
+ attribute \src "libresoc.v:105891.3-105939.6"
wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:106629.3-106677.6"
+ attribute \src "libresoc.v:105254.3-105302.6"
wire width 8 $0\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:106825.3-106873.6"
+ attribute \src "libresoc.v:105450.3-105498.6"
wire $0\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:105992.3-106040.6"
+ attribute \src "libresoc.v:104617.3-104665.6"
wire width 3 $0\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:106041.3-106089.6"
+ attribute \src "libresoc.v:104666.3-104714.6"
wire width 3 $0\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:106580.3-106628.6"
+ attribute \src "libresoc.v:105205.3-105253.6"
wire width 2 $0\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:106776.3-106824.6"
+ attribute \src "libresoc.v:105401.3-105449.6"
wire $0\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:107021.3-107069.6"
+ attribute \src "libresoc.v:105646.3-105694.6"
wire width 5 $0\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:105943.3-105991.6"
+ attribute \src "libresoc.v:104568.3-104616.6"
wire width 13 $0\dec31_dec_sub23_function_unit[12:0]
- attribute \src "libresoc.v:107315.3-107363.6"
+ attribute \src "libresoc.v:105940.3-105988.6"
wire width 3 $0\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:107364.3-107412.6"
+ attribute \src "libresoc.v:105989.3-106037.6"
wire width 4 $0\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:107413.3-107461.6"
+ attribute \src "libresoc.v:106038.3-106086.6"
wire width 2 $0\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:106482.3-106530.6"
+ attribute \src "libresoc.v:105107.3-105155.6"
wire width 7 $0\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:106678.3-106726.6"
+ attribute \src "libresoc.v:105303.3-105351.6"
wire $0\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:106727.3-106775.6"
+ attribute \src "libresoc.v:105352.3-105400.6"
wire $0\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:106972.3-107020.6"
+ attribute \src "libresoc.v:105597.3-105645.6"
wire $0\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:106384.3-106432.6"
+ attribute \src "libresoc.v:105009.3-105057.6"
wire width 4 $0\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:107119.3-107167.6"
+ attribute \src "libresoc.v:105744.3-105792.6"
wire $0\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:107462.3-107510.6"
+ attribute \src "libresoc.v:106087.3-106135.6"
wire width 2 $0\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:106531.3-106579.6"
+ attribute \src "libresoc.v:105156.3-105204.6"
wire width 2 $0\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:106923.3-106971.6"
+ attribute \src "libresoc.v:105548.3-105596.6"
wire $0\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:107168.3-107216.6"
+ attribute \src "libresoc.v:105793.3-105841.6"
wire $0\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:107070.3-107118.6"
+ attribute \src "libresoc.v:105695.3-105743.6"
wire $0\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:106874.3-106922.6"
+ attribute \src "libresoc.v:105499.3-105547.6"
wire $0\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:106286.3-106334.6"
+ attribute \src "libresoc.v:104911.3-104959.6"
wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:106335.3-106383.6"
+ attribute \src "libresoc.v:104960.3-105008.6"
wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:106090.3-106138.6"
+ attribute \src "libresoc.v:104715.3-104763.6"
wire width 3 $0\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:106139.3-106187.6"
+ attribute \src "libresoc.v:104764.3-104812.6"
wire width 3 $0\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:106188.3-106236.6"
+ attribute \src "libresoc.v:104813.3-104861.6"
wire width 3 $0\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:106237.3-106285.6"
+ attribute \src "libresoc.v:104862.3-104910.6"
wire width 3 $0\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:106433.3-106481.6"
+ attribute \src "libresoc.v:105058.3-105106.6"
wire width 2 $0\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:105608.7-105608.20"
+ attribute \src "libresoc.v:104233.7-104233.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:107217.3-107265.6"
+ attribute \src "libresoc.v:105842.3-105890.6"
wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:107266.3-107314.6"
+ attribute \src "libresoc.v:105891.3-105939.6"
wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:106629.3-106677.6"
+ attribute \src "libresoc.v:105254.3-105302.6"
wire width 8 $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:106825.3-106873.6"
+ attribute \src "libresoc.v:105450.3-105498.6"
wire $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:105992.3-106040.6"
+ attribute \src "libresoc.v:104617.3-104665.6"
wire width 3 $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:106041.3-106089.6"
+ attribute \src "libresoc.v:104666.3-104714.6"
wire width 3 $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:106580.3-106628.6"
+ attribute \src "libresoc.v:105205.3-105253.6"
wire width 2 $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:106776.3-106824.6"
+ attribute \src "libresoc.v:105401.3-105449.6"
wire $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:107021.3-107069.6"
+ attribute \src "libresoc.v:105646.3-105694.6"
wire width 5 $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:105943.3-105991.6"
+ attribute \src "libresoc.v:104568.3-104616.6"
wire width 13 $1\dec31_dec_sub23_function_unit[12:0]
- attribute \src "libresoc.v:107315.3-107363.6"
+ attribute \src "libresoc.v:105940.3-105988.6"
wire width 3 $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:107364.3-107412.6"
+ attribute \src "libresoc.v:105989.3-106037.6"
wire width 4 $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:107413.3-107461.6"
+ attribute \src "libresoc.v:106038.3-106086.6"
wire width 2 $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:106482.3-106530.6"
+ attribute \src "libresoc.v:105107.3-105155.6"
wire width 7 $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:106678.3-106726.6"
+ attribute \src "libresoc.v:105303.3-105351.6"
wire $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:106727.3-106775.6"
+ attribute \src "libresoc.v:105352.3-105400.6"
wire $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:106972.3-107020.6"
+ attribute \src "libresoc.v:105597.3-105645.6"
wire $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:106384.3-106432.6"
+ attribute \src "libresoc.v:105009.3-105057.6"
wire width 4 $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:107119.3-107167.6"
+ attribute \src "libresoc.v:105744.3-105792.6"
wire $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:107462.3-107510.6"
+ attribute \src "libresoc.v:106087.3-106135.6"
wire width 2 $1\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:106531.3-106579.6"
+ attribute \src "libresoc.v:105156.3-105204.6"
wire width 2 $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:106923.3-106971.6"
+ attribute \src "libresoc.v:105548.3-105596.6"
wire $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:107168.3-107216.6"
+ attribute \src "libresoc.v:105793.3-105841.6"
wire $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:107070.3-107118.6"
+ attribute \src "libresoc.v:105695.3-105743.6"
wire $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:106874.3-106922.6"
+ attribute \src "libresoc.v:105499.3-105547.6"
wire $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:106286.3-106334.6"
+ attribute \src "libresoc.v:104911.3-104959.6"
wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:106335.3-106383.6"
+ attribute \src "libresoc.v:104960.3-105008.6"
wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:106090.3-106138.6"
+ attribute \src "libresoc.v:104715.3-104763.6"
wire width 3 $1\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:106139.3-106187.6"
+ attribute \src "libresoc.v:104764.3-104812.6"
wire width 3 $1\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:106188.3-106236.6"
+ attribute \src "libresoc.v:104813.3-104861.6"
wire width 3 $1\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:106237.3-106285.6"
+ attribute \src "libresoc.v:104862.3-104910.6"
wire width 3 $1\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:106433.3-106481.6"
+ attribute \src "libresoc.v:105058.3-105106.6"
wire width 2 $1\dec31_dec_sub23_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub23_upd
- attribute \src "libresoc.v:105608.7-105608.15"
+ attribute \src "libresoc.v:104233.7-104233.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:105608.7-105608.20"
- process $proc$libresoc.v:105608$4215
+ attribute \src "libresoc.v:104233.7-104233.20"
+ process $proc$libresoc.v:104233$4159
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:105943.3-105991.6"
- process $proc$libresoc.v:105943$4183
+ attribute \src "libresoc.v:104568.3-104616.6"
+ process $proc$libresoc.v:104568$4127
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_function_unit[12:0] $1\dec31_dec_sub23_function_unit[12:0]
- attribute \src "libresoc.v:105944.5-105944.29"
+ attribute \src "libresoc.v:104569.5-104569.29"
switch \initial
- attribute \src "libresoc.v:105944.9-105944.17"
+ attribute \src "libresoc.v:104569.9-104569.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[12:0]
end
- attribute \src "libresoc.v:105992.3-106040.6"
- process $proc$libresoc.v:105992$4184
+ attribute \src "libresoc.v:104617.3-104665.6"
+ process $proc$libresoc.v:104617$4128
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:105993.5-105993.29"
+ attribute \src "libresoc.v:104618.5-104618.29"
switch \initial
- attribute \src "libresoc.v:105993.9-105993.17"
+ attribute \src "libresoc.v:104618.9-104618.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0]
end
- attribute \src "libresoc.v:106041.3-106089.6"
- process $proc$libresoc.v:106041$4185
+ attribute \src "libresoc.v:104666.3-104714.6"
+ process $proc$libresoc.v:104666$4129
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:106042.5-106042.29"
+ attribute \src "libresoc.v:104667.5-104667.29"
switch \initial
- attribute \src "libresoc.v:106042.9-106042.17"
+ attribute \src "libresoc.v:104667.9-104667.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0]
end
- attribute \src "libresoc.v:106090.3-106138.6"
- process $proc$libresoc.v:106090$4186
+ attribute \src "libresoc.v:104715.3-104763.6"
+ process $proc$libresoc.v:104715$4130
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0]
- attribute \src "libresoc.v:106091.5-106091.29"
+ attribute \src "libresoc.v:104716.5-104716.29"
switch \initial
- attribute \src "libresoc.v:106091.9-106091.17"
+ attribute \src "libresoc.v:104716.9-104716.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0]
end
- attribute \src "libresoc.v:106139.3-106187.6"
- process $proc$libresoc.v:106139$4187
+ attribute \src "libresoc.v:104764.3-104812.6"
+ process $proc$libresoc.v:104764$4131
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0]
- attribute \src "libresoc.v:106140.5-106140.29"
+ attribute \src "libresoc.v:104765.5-104765.29"
switch \initial
- attribute \src "libresoc.v:106140.9-106140.17"
+ attribute \src "libresoc.v:104765.9-104765.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0]
end
- attribute \src "libresoc.v:106188.3-106236.6"
- process $proc$libresoc.v:106188$4188
+ attribute \src "libresoc.v:104813.3-104861.6"
+ process $proc$libresoc.v:104813$4132
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0]
- attribute \src "libresoc.v:106189.5-106189.29"
+ attribute \src "libresoc.v:104814.5-104814.29"
switch \initial
- attribute \src "libresoc.v:106189.9-106189.17"
+ attribute \src "libresoc.v:104814.9-104814.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0]
end
- attribute \src "libresoc.v:106237.3-106285.6"
- process $proc$libresoc.v:106237$4189
+ attribute \src "libresoc.v:104862.3-104910.6"
+ process $proc$libresoc.v:104862$4133
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0]
- attribute \src "libresoc.v:106238.5-106238.29"
+ attribute \src "libresoc.v:104863.5-104863.29"
switch \initial
- attribute \src "libresoc.v:106238.9-106238.17"
+ attribute \src "libresoc.v:104863.9-104863.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0]
end
- attribute \src "libresoc.v:106286.3-106334.6"
- process $proc$libresoc.v:106286$4190
+ attribute \src "libresoc.v:104911.3-104959.6"
+ process $proc$libresoc.v:104911$4134
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0]
- attribute \src "libresoc.v:106287.5-106287.29"
+ attribute \src "libresoc.v:104912.5-104912.29"
switch \initial
- attribute \src "libresoc.v:106287.9-106287.17"
+ attribute \src "libresoc.v:104912.9-104912.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:106335.3-106383.6"
- process $proc$libresoc.v:106335$4191
+ attribute \src "libresoc.v:104960.3-105008.6"
+ process $proc$libresoc.v:104960$4135
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0]
- attribute \src "libresoc.v:106336.5-106336.29"
+ attribute \src "libresoc.v:104961.5-104961.29"
switch \initial
- attribute \src "libresoc.v:106336.9-106336.17"
+ attribute \src "libresoc.v:104961.9-104961.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:106384.3-106432.6"
- process $proc$libresoc.v:106384$4192
+ attribute \src "libresoc.v:105009.3-105057.6"
+ process $proc$libresoc.v:105009$4136
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:106385.5-106385.29"
+ attribute \src "libresoc.v:105010.5-105010.29"
switch \initial
- attribute \src "libresoc.v:106385.9-106385.17"
+ attribute \src "libresoc.v:105010.9-105010.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0]
end
- attribute \src "libresoc.v:106433.3-106481.6"
- process $proc$libresoc.v:106433$4193
+ attribute \src "libresoc.v:105058.3-105106.6"
+ process $proc$libresoc.v:105058$4137
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:106434.5-106434.29"
+ attribute \src "libresoc.v:105059.5-105059.29"
switch \initial
- attribute \src "libresoc.v:106434.9-106434.17"
+ attribute \src "libresoc.v:105059.9-105059.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0]
end
- attribute \src "libresoc.v:106482.3-106530.6"
- process $proc$libresoc.v:106482$4194
+ attribute \src "libresoc.v:105107.3-105155.6"
+ process $proc$libresoc.v:105107$4138
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:106483.5-106483.29"
+ attribute \src "libresoc.v:105108.5-105108.29"
switch \initial
- attribute \src "libresoc.v:106483.9-106483.17"
+ attribute \src "libresoc.v:105108.9-105108.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0]
end
- attribute \src "libresoc.v:106531.3-106579.6"
- process $proc$libresoc.v:106531$4195
+ attribute \src "libresoc.v:105156.3-105204.6"
+ process $proc$libresoc.v:105156$4139
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:106532.5-106532.29"
+ attribute \src "libresoc.v:105157.5-105157.29"
switch \initial
- attribute \src "libresoc.v:106532.9-106532.17"
+ attribute \src "libresoc.v:105157.9-105157.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0]
end
- attribute \src "libresoc.v:106580.3-106628.6"
- process $proc$libresoc.v:106580$4196
+ attribute \src "libresoc.v:105205.3-105253.6"
+ process $proc$libresoc.v:105205$4140
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:106581.5-106581.29"
+ attribute \src "libresoc.v:105206.5-105206.29"
switch \initial
- attribute \src "libresoc.v:106581.9-106581.17"
+ attribute \src "libresoc.v:105206.9-105206.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0]
end
- attribute \src "libresoc.v:106629.3-106677.6"
- process $proc$libresoc.v:106629$4197
+ attribute \src "libresoc.v:105254.3-105302.6"
+ process $proc$libresoc.v:105254$4141
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:106630.5-106630.29"
+ attribute \src "libresoc.v:105255.5-105255.29"
switch \initial
- attribute \src "libresoc.v:106630.9-106630.17"
+ attribute \src "libresoc.v:105255.9-105255.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0]
end
- attribute \src "libresoc.v:106678.3-106726.6"
- process $proc$libresoc.v:106678$4198
+ attribute \src "libresoc.v:105303.3-105351.6"
+ process $proc$libresoc.v:105303$4142
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:106679.5-106679.29"
+ attribute \src "libresoc.v:105304.5-105304.29"
switch \initial
- attribute \src "libresoc.v:106679.9-106679.17"
+ attribute \src "libresoc.v:105304.9-105304.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0]
end
- attribute \src "libresoc.v:106727.3-106775.6"
- process $proc$libresoc.v:106727$4199
+ attribute \src "libresoc.v:105352.3-105400.6"
+ process $proc$libresoc.v:105352$4143
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:106728.5-106728.29"
+ attribute \src "libresoc.v:105353.5-105353.29"
switch \initial
- attribute \src "libresoc.v:106728.9-106728.17"
+ attribute \src "libresoc.v:105353.9-105353.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0]
end
- attribute \src "libresoc.v:106776.3-106824.6"
- process $proc$libresoc.v:106776$4200
+ attribute \src "libresoc.v:105401.3-105449.6"
+ process $proc$libresoc.v:105401$4144
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:106777.5-106777.29"
+ attribute \src "libresoc.v:105402.5-105402.29"
switch \initial
- attribute \src "libresoc.v:106777.9-106777.17"
+ attribute \src "libresoc.v:105402.9-105402.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0]
end
- attribute \src "libresoc.v:106825.3-106873.6"
- process $proc$libresoc.v:106825$4201
+ attribute \src "libresoc.v:105450.3-105498.6"
+ process $proc$libresoc.v:105450$4145
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:106826.5-106826.29"
+ attribute \src "libresoc.v:105451.5-105451.29"
switch \initial
- attribute \src "libresoc.v:106826.9-106826.17"
+ attribute \src "libresoc.v:105451.9-105451.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0]
end
- attribute \src "libresoc.v:106874.3-106922.6"
- process $proc$libresoc.v:106874$4202
+ attribute \src "libresoc.v:105499.3-105547.6"
+ process $proc$libresoc.v:105499$4146
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:106875.5-106875.29"
+ attribute \src "libresoc.v:105500.5-105500.29"
switch \initial
- attribute \src "libresoc.v:106875.9-106875.17"
+ attribute \src "libresoc.v:105500.9-105500.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0]
end
- attribute \src "libresoc.v:106923.3-106971.6"
- process $proc$libresoc.v:106923$4203
+ attribute \src "libresoc.v:105548.3-105596.6"
+ process $proc$libresoc.v:105548$4147
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:106924.5-106924.29"
+ attribute \src "libresoc.v:105549.5-105549.29"
switch \initial
- attribute \src "libresoc.v:106924.9-106924.17"
+ attribute \src "libresoc.v:105549.9-105549.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0]
end
- attribute \src "libresoc.v:106972.3-107020.6"
- process $proc$libresoc.v:106972$4204
+ attribute \src "libresoc.v:105597.3-105645.6"
+ process $proc$libresoc.v:105597$4148
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:106973.5-106973.29"
+ attribute \src "libresoc.v:105598.5-105598.29"
switch \initial
- attribute \src "libresoc.v:106973.9-106973.17"
+ attribute \src "libresoc.v:105598.9-105598.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0]
end
- attribute \src "libresoc.v:107021.3-107069.6"
- process $proc$libresoc.v:107021$4205
+ attribute \src "libresoc.v:105646.3-105694.6"
+ process $proc$libresoc.v:105646$4149
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:107022.5-107022.29"
+ attribute \src "libresoc.v:105647.5-105647.29"
switch \initial
- attribute \src "libresoc.v:107022.9-107022.17"
+ attribute \src "libresoc.v:105647.9-105647.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0]
end
- attribute \src "libresoc.v:107070.3-107118.6"
- process $proc$libresoc.v:107070$4206
+ attribute \src "libresoc.v:105695.3-105743.6"
+ process $proc$libresoc.v:105695$4150
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:107071.5-107071.29"
+ attribute \src "libresoc.v:105696.5-105696.29"
switch \initial
- attribute \src "libresoc.v:107071.9-107071.17"
+ attribute \src "libresoc.v:105696.9-105696.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0]
end
- attribute \src "libresoc.v:107119.3-107167.6"
- process $proc$libresoc.v:107119$4207
+ attribute \src "libresoc.v:105744.3-105792.6"
+ process $proc$libresoc.v:105744$4151
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:107120.5-107120.29"
+ attribute \src "libresoc.v:105745.5-105745.29"
switch \initial
- attribute \src "libresoc.v:107120.9-107120.17"
+ attribute \src "libresoc.v:105745.9-105745.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0]
end
- attribute \src "libresoc.v:107168.3-107216.6"
- process $proc$libresoc.v:107168$4208
+ attribute \src "libresoc.v:105793.3-105841.6"
+ process $proc$libresoc.v:105793$4152
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:107169.5-107169.29"
+ attribute \src "libresoc.v:105794.5-105794.29"
switch \initial
- attribute \src "libresoc.v:107169.9-107169.17"
+ attribute \src "libresoc.v:105794.9-105794.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:107217.3-107265.6"
- process $proc$libresoc.v:107217$4209
+ attribute \src "libresoc.v:105842.3-105890.6"
+ process $proc$libresoc.v:105842$4153
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0]
- attribute \src "libresoc.v:107218.5-107218.29"
+ attribute \src "libresoc.v:105843.5-105843.29"
switch \initial
- attribute \src "libresoc.v:107218.9-107218.17"
+ attribute \src "libresoc.v:105843.9-105843.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0]
end
- attribute \src "libresoc.v:107266.3-107314.6"
- process $proc$libresoc.v:107266$4210
+ attribute \src "libresoc.v:105891.3-105939.6"
+ process $proc$libresoc.v:105891$4154
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0]
- attribute \src "libresoc.v:107267.5-107267.29"
+ attribute \src "libresoc.v:105892.5-105892.29"
switch \initial
- attribute \src "libresoc.v:107267.9-107267.17"
+ attribute \src "libresoc.v:105892.9-105892.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:107315.3-107363.6"
- process $proc$libresoc.v:107315$4211
+ attribute \src "libresoc.v:105940.3-105988.6"
+ process $proc$libresoc.v:105940$4155
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:107316.5-107316.29"
+ attribute \src "libresoc.v:105941.5-105941.29"
switch \initial
- attribute \src "libresoc.v:107316.9-107316.17"
+ attribute \src "libresoc.v:105941.9-105941.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0]
end
- attribute \src "libresoc.v:107364.3-107412.6"
- process $proc$libresoc.v:107364$4212
+ attribute \src "libresoc.v:105989.3-106037.6"
+ process $proc$libresoc.v:105989$4156
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:107365.5-107365.29"
+ attribute \src "libresoc.v:105990.5-105990.29"
switch \initial
- attribute \src "libresoc.v:107365.9-107365.17"
+ attribute \src "libresoc.v:105990.9-105990.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0]
end
- attribute \src "libresoc.v:107413.3-107461.6"
- process $proc$libresoc.v:107413$4213
+ attribute \src "libresoc.v:106038.3-106086.6"
+ process $proc$libresoc.v:106038$4157
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:107414.5-107414.29"
+ attribute \src "libresoc.v:106039.5-106039.29"
switch \initial
- attribute \src "libresoc.v:107414.9-107414.17"
+ attribute \src "libresoc.v:106039.9-106039.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0]
end
- attribute \src "libresoc.v:107462.3-107510.6"
- process $proc$libresoc.v:107462$4214
+ attribute \src "libresoc.v:106087.3-106135.6"
+ process $proc$libresoc.v:106087$4158
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:107463.5-107463.29"
+ attribute \src "libresoc.v:106088.5-106088.29"
switch \initial
- attribute \src "libresoc.v:107463.9-107463.17"
+ attribute \src "libresoc.v:106088.9-106088.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:107516.1-108461.10"
+attribute \src "libresoc.v:106141.1-107086.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24"
attribute \generator "nMigen"
module \dec31_dec_sub24
- attribute \src "libresoc.v:108346.3-108364.6"
+ attribute \src "libresoc.v:106971.3-106989.6"
wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:108365.3-108383.6"
+ attribute \src "libresoc.v:106990.3-107008.6"
wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:108118.3-108136.6"
+ attribute \src "libresoc.v:106743.3-106761.6"
wire width 8 $0\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:108194.3-108212.6"
+ attribute \src "libresoc.v:106819.3-106837.6"
wire $0\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:107871.3-107889.6"
+ attribute \src "libresoc.v:106496.3-106514.6"
wire width 3 $0\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:107890.3-107908.6"
+ attribute \src "libresoc.v:106515.3-106533.6"
wire width 3 $0\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:108099.3-108117.6"
+ attribute \src "libresoc.v:106724.3-106742.6"
wire width 2 $0\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:108175.3-108193.6"
+ attribute \src "libresoc.v:106800.3-106818.6"
wire $0\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:108270.3-108288.6"
+ attribute \src "libresoc.v:106895.3-106913.6"
wire width 5 $0\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:107852.3-107870.6"
+ attribute \src "libresoc.v:106477.3-106495.6"
wire width 13 $0\dec31_dec_sub24_function_unit[12:0]
- attribute \src "libresoc.v:108384.3-108402.6"
+ attribute \src "libresoc.v:107009.3-107027.6"
wire width 3 $0\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:108403.3-108421.6"
+ attribute \src "libresoc.v:107028.3-107046.6"
wire width 4 $0\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:108422.3-108440.6"
+ attribute \src "libresoc.v:107047.3-107065.6"
wire width 2 $0\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:108061.3-108079.6"
+ attribute \src "libresoc.v:106686.3-106704.6"
wire width 7 $0\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:108137.3-108155.6"
+ attribute \src "libresoc.v:106762.3-106780.6"
wire $0\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:108156.3-108174.6"
+ attribute \src "libresoc.v:106781.3-106799.6"
wire $0\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:108251.3-108269.6"
+ attribute \src "libresoc.v:106876.3-106894.6"
wire $0\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:108023.3-108041.6"
+ attribute \src "libresoc.v:106648.3-106666.6"
wire width 4 $0\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:108308.3-108326.6"
+ attribute \src "libresoc.v:106933.3-106951.6"
wire $0\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:108441.3-108459.6"
+ attribute \src "libresoc.v:107066.3-107084.6"
wire width 2 $0\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:108080.3-108098.6"
+ attribute \src "libresoc.v:106705.3-106723.6"
wire width 2 $0\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:108232.3-108250.6"
+ attribute \src "libresoc.v:106857.3-106875.6"
wire $0\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:108327.3-108345.6"
+ attribute \src "libresoc.v:106952.3-106970.6"
wire $0\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:108289.3-108307.6"
+ attribute \src "libresoc.v:106914.3-106932.6"
wire $0\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:108213.3-108231.6"
+ attribute \src "libresoc.v:106838.3-106856.6"
wire $0\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:107985.3-108003.6"
+ attribute \src "libresoc.v:106610.3-106628.6"
wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:108004.3-108022.6"
+ attribute \src "libresoc.v:106629.3-106647.6"
wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:107909.3-107927.6"
+ attribute \src "libresoc.v:106534.3-106552.6"
wire width 3 $0\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:107928.3-107946.6"
+ attribute \src "libresoc.v:106553.3-106571.6"
wire width 3 $0\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:107947.3-107965.6"
+ attribute \src "libresoc.v:106572.3-106590.6"
wire width 3 $0\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:107966.3-107984.6"
+ attribute \src "libresoc.v:106591.3-106609.6"
wire width 3 $0\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:108042.3-108060.6"
+ attribute \src "libresoc.v:106667.3-106685.6"
wire width 2 $0\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:107517.7-107517.20"
+ attribute \src "libresoc.v:106142.7-106142.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:108346.3-108364.6"
+ attribute \src "libresoc.v:106971.3-106989.6"
wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:108365.3-108383.6"
+ attribute \src "libresoc.v:106990.3-107008.6"
wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:108118.3-108136.6"
+ attribute \src "libresoc.v:106743.3-106761.6"
wire width 8 $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:108194.3-108212.6"
+ attribute \src "libresoc.v:106819.3-106837.6"
wire $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:107871.3-107889.6"
+ attribute \src "libresoc.v:106496.3-106514.6"
wire width 3 $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:107890.3-107908.6"
+ attribute \src "libresoc.v:106515.3-106533.6"
wire width 3 $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:108099.3-108117.6"
+ attribute \src "libresoc.v:106724.3-106742.6"
wire width 2 $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:108175.3-108193.6"
+ attribute \src "libresoc.v:106800.3-106818.6"
wire $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:108270.3-108288.6"
+ attribute \src "libresoc.v:106895.3-106913.6"
wire width 5 $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:107852.3-107870.6"
+ attribute \src "libresoc.v:106477.3-106495.6"
wire width 13 $1\dec31_dec_sub24_function_unit[12:0]
- attribute \src "libresoc.v:108384.3-108402.6"
+ attribute \src "libresoc.v:107009.3-107027.6"
wire width 3 $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:108403.3-108421.6"
+ attribute \src "libresoc.v:107028.3-107046.6"
wire width 4 $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:108422.3-108440.6"
+ attribute \src "libresoc.v:107047.3-107065.6"
wire width 2 $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:108061.3-108079.6"
+ attribute \src "libresoc.v:106686.3-106704.6"
wire width 7 $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:108137.3-108155.6"
+ attribute \src "libresoc.v:106762.3-106780.6"
wire $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:108156.3-108174.6"
+ attribute \src "libresoc.v:106781.3-106799.6"
wire $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:108251.3-108269.6"
+ attribute \src "libresoc.v:106876.3-106894.6"
wire $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:108023.3-108041.6"
+ attribute \src "libresoc.v:106648.3-106666.6"
wire width 4 $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:108308.3-108326.6"
+ attribute \src "libresoc.v:106933.3-106951.6"
wire $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:108441.3-108459.6"
+ attribute \src "libresoc.v:107066.3-107084.6"
wire width 2 $1\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:108080.3-108098.6"
+ attribute \src "libresoc.v:106705.3-106723.6"
wire width 2 $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:108232.3-108250.6"
+ attribute \src "libresoc.v:106857.3-106875.6"
wire $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:108327.3-108345.6"
+ attribute \src "libresoc.v:106952.3-106970.6"
wire $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:108289.3-108307.6"
+ attribute \src "libresoc.v:106914.3-106932.6"
wire $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:108213.3-108231.6"
+ attribute \src "libresoc.v:106838.3-106856.6"
wire $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:107985.3-108003.6"
+ attribute \src "libresoc.v:106610.3-106628.6"
wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:108004.3-108022.6"
+ attribute \src "libresoc.v:106629.3-106647.6"
wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:107909.3-107927.6"
+ attribute \src "libresoc.v:106534.3-106552.6"
wire width 3 $1\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:107928.3-107946.6"
+ attribute \src "libresoc.v:106553.3-106571.6"
wire width 3 $1\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:107947.3-107965.6"
+ attribute \src "libresoc.v:106572.3-106590.6"
wire width 3 $1\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:107966.3-107984.6"
+ attribute \src "libresoc.v:106591.3-106609.6"
wire width 3 $1\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:108042.3-108060.6"
+ attribute \src "libresoc.v:106667.3-106685.6"
wire width 2 $1\dec31_dec_sub24_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub24_upd
- attribute \src "libresoc.v:107517.7-107517.15"
+ attribute \src "libresoc.v:106142.7-106142.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:107517.7-107517.20"
- process $proc$libresoc.v:107517$4248
+ attribute \src "libresoc.v:106142.7-106142.20"
+ process $proc$libresoc.v:106142$4192
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:107852.3-107870.6"
- process $proc$libresoc.v:107852$4216
+ attribute \src "libresoc.v:106477.3-106495.6"
+ process $proc$libresoc.v:106477$4160
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_function_unit[12:0] $1\dec31_dec_sub24_function_unit[12:0]
- attribute \src "libresoc.v:107853.5-107853.29"
+ attribute \src "libresoc.v:106478.5-106478.29"
switch \initial
- attribute \src "libresoc.v:107853.9-107853.17"
+ attribute \src "libresoc.v:106478.9-106478.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[12:0]
end
- attribute \src "libresoc.v:107871.3-107889.6"
- process $proc$libresoc.v:107871$4217
+ attribute \src "libresoc.v:106496.3-106514.6"
+ process $proc$libresoc.v:106496$4161
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:107872.5-107872.29"
+ attribute \src "libresoc.v:106497.5-106497.29"
switch \initial
- attribute \src "libresoc.v:107872.9-107872.17"
+ attribute \src "libresoc.v:106497.9-106497.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0]
end
- attribute \src "libresoc.v:107890.3-107908.6"
- process $proc$libresoc.v:107890$4218
+ attribute \src "libresoc.v:106515.3-106533.6"
+ process $proc$libresoc.v:106515$4162
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:107891.5-107891.29"
+ attribute \src "libresoc.v:106516.5-106516.29"
switch \initial
- attribute \src "libresoc.v:107891.9-107891.17"
+ attribute \src "libresoc.v:106516.9-106516.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0]
end
- attribute \src "libresoc.v:107909.3-107927.6"
- process $proc$libresoc.v:107909$4219
+ attribute \src "libresoc.v:106534.3-106552.6"
+ process $proc$libresoc.v:106534$4163
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0]
- attribute \src "libresoc.v:107910.5-107910.29"
+ attribute \src "libresoc.v:106535.5-106535.29"
switch \initial
- attribute \src "libresoc.v:107910.9-107910.17"
+ attribute \src "libresoc.v:106535.9-106535.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0]
end
- attribute \src "libresoc.v:107928.3-107946.6"
- process $proc$libresoc.v:107928$4220
+ attribute \src "libresoc.v:106553.3-106571.6"
+ process $proc$libresoc.v:106553$4164
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0]
- attribute \src "libresoc.v:107929.5-107929.29"
+ attribute \src "libresoc.v:106554.5-106554.29"
switch \initial
- attribute \src "libresoc.v:107929.9-107929.17"
+ attribute \src "libresoc.v:106554.9-106554.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0]
end
- attribute \src "libresoc.v:107947.3-107965.6"
- process $proc$libresoc.v:107947$4221
+ attribute \src "libresoc.v:106572.3-106590.6"
+ process $proc$libresoc.v:106572$4165
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0]
- attribute \src "libresoc.v:107948.5-107948.29"
+ attribute \src "libresoc.v:106573.5-106573.29"
switch \initial
- attribute \src "libresoc.v:107948.9-107948.17"
+ attribute \src "libresoc.v:106573.9-106573.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0]
end
- attribute \src "libresoc.v:107966.3-107984.6"
- process $proc$libresoc.v:107966$4222
+ attribute \src "libresoc.v:106591.3-106609.6"
+ process $proc$libresoc.v:106591$4166
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0]
- attribute \src "libresoc.v:107967.5-107967.29"
+ attribute \src "libresoc.v:106592.5-106592.29"
switch \initial
- attribute \src "libresoc.v:107967.9-107967.17"
+ attribute \src "libresoc.v:106592.9-106592.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0]
end
- attribute \src "libresoc.v:107985.3-108003.6"
- process $proc$libresoc.v:107985$4223
+ attribute \src "libresoc.v:106610.3-106628.6"
+ process $proc$libresoc.v:106610$4167
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0]
- attribute \src "libresoc.v:107986.5-107986.29"
+ attribute \src "libresoc.v:106611.5-106611.29"
switch \initial
- attribute \src "libresoc.v:107986.9-107986.17"
+ attribute \src "libresoc.v:106611.9-106611.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:108004.3-108022.6"
- process $proc$libresoc.v:108004$4224
+ attribute \src "libresoc.v:106629.3-106647.6"
+ process $proc$libresoc.v:106629$4168
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0]
- attribute \src "libresoc.v:108005.5-108005.29"
+ attribute \src "libresoc.v:106630.5-106630.29"
switch \initial
- attribute \src "libresoc.v:108005.9-108005.17"
+ attribute \src "libresoc.v:106630.9-106630.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:108023.3-108041.6"
- process $proc$libresoc.v:108023$4225
+ attribute \src "libresoc.v:106648.3-106666.6"
+ process $proc$libresoc.v:106648$4169
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:108024.5-108024.29"
+ attribute \src "libresoc.v:106649.5-106649.29"
switch \initial
- attribute \src "libresoc.v:108024.9-108024.17"
+ attribute \src "libresoc.v:106649.9-106649.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0]
end
- attribute \src "libresoc.v:108042.3-108060.6"
- process $proc$libresoc.v:108042$4226
+ attribute \src "libresoc.v:106667.3-106685.6"
+ process $proc$libresoc.v:106667$4170
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:108043.5-108043.29"
+ attribute \src "libresoc.v:106668.5-106668.29"
switch \initial
- attribute \src "libresoc.v:108043.9-108043.17"
+ attribute \src "libresoc.v:106668.9-106668.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0]
end
- attribute \src "libresoc.v:108061.3-108079.6"
- process $proc$libresoc.v:108061$4227
+ attribute \src "libresoc.v:106686.3-106704.6"
+ process $proc$libresoc.v:106686$4171
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:108062.5-108062.29"
+ attribute \src "libresoc.v:106687.5-106687.29"
switch \initial
- attribute \src "libresoc.v:108062.9-108062.17"
+ attribute \src "libresoc.v:106687.9-106687.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0]
end
- attribute \src "libresoc.v:108080.3-108098.6"
- process $proc$libresoc.v:108080$4228
+ attribute \src "libresoc.v:106705.3-106723.6"
+ process $proc$libresoc.v:106705$4172
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:108081.5-108081.29"
+ attribute \src "libresoc.v:106706.5-106706.29"
switch \initial
- attribute \src "libresoc.v:108081.9-108081.17"
+ attribute \src "libresoc.v:106706.9-106706.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0]
end
- attribute \src "libresoc.v:108099.3-108117.6"
- process $proc$libresoc.v:108099$4229
+ attribute \src "libresoc.v:106724.3-106742.6"
+ process $proc$libresoc.v:106724$4173
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:108100.5-108100.29"
+ attribute \src "libresoc.v:106725.5-106725.29"
switch \initial
- attribute \src "libresoc.v:108100.9-108100.17"
+ attribute \src "libresoc.v:106725.9-106725.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0]
end
- attribute \src "libresoc.v:108118.3-108136.6"
- process $proc$libresoc.v:108118$4230
+ attribute \src "libresoc.v:106743.3-106761.6"
+ process $proc$libresoc.v:106743$4174
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:108119.5-108119.29"
+ attribute \src "libresoc.v:106744.5-106744.29"
switch \initial
- attribute \src "libresoc.v:108119.9-108119.17"
+ attribute \src "libresoc.v:106744.9-106744.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0]
end
- attribute \src "libresoc.v:108137.3-108155.6"
- process $proc$libresoc.v:108137$4231
+ attribute \src "libresoc.v:106762.3-106780.6"
+ process $proc$libresoc.v:106762$4175
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:108138.5-108138.29"
+ attribute \src "libresoc.v:106763.5-106763.29"
switch \initial
- attribute \src "libresoc.v:108138.9-108138.17"
+ attribute \src "libresoc.v:106763.9-106763.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0]
end
- attribute \src "libresoc.v:108156.3-108174.6"
- process $proc$libresoc.v:108156$4232
+ attribute \src "libresoc.v:106781.3-106799.6"
+ process $proc$libresoc.v:106781$4176
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:108157.5-108157.29"
+ attribute \src "libresoc.v:106782.5-106782.29"
switch \initial
- attribute \src "libresoc.v:108157.9-108157.17"
+ attribute \src "libresoc.v:106782.9-106782.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0]
end
- attribute \src "libresoc.v:108175.3-108193.6"
- process $proc$libresoc.v:108175$4233
+ attribute \src "libresoc.v:106800.3-106818.6"
+ process $proc$libresoc.v:106800$4177
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:108176.5-108176.29"
+ attribute \src "libresoc.v:106801.5-106801.29"
switch \initial
- attribute \src "libresoc.v:108176.9-108176.17"
+ attribute \src "libresoc.v:106801.9-106801.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0]
end
- attribute \src "libresoc.v:108194.3-108212.6"
- process $proc$libresoc.v:108194$4234
+ attribute \src "libresoc.v:106819.3-106837.6"
+ process $proc$libresoc.v:106819$4178
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:108195.5-108195.29"
+ attribute \src "libresoc.v:106820.5-106820.29"
switch \initial
- attribute \src "libresoc.v:108195.9-108195.17"
+ attribute \src "libresoc.v:106820.9-106820.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0]
end
- attribute \src "libresoc.v:108213.3-108231.6"
- process $proc$libresoc.v:108213$4235
+ attribute \src "libresoc.v:106838.3-106856.6"
+ process $proc$libresoc.v:106838$4179
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:108214.5-108214.29"
+ attribute \src "libresoc.v:106839.5-106839.29"
switch \initial
- attribute \src "libresoc.v:108214.9-108214.17"
+ attribute \src "libresoc.v:106839.9-106839.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0]
end
- attribute \src "libresoc.v:108232.3-108250.6"
- process $proc$libresoc.v:108232$4236
+ attribute \src "libresoc.v:106857.3-106875.6"
+ process $proc$libresoc.v:106857$4180
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:108233.5-108233.29"
+ attribute \src "libresoc.v:106858.5-106858.29"
switch \initial
- attribute \src "libresoc.v:108233.9-108233.17"
+ attribute \src "libresoc.v:106858.9-106858.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0]
end
- attribute \src "libresoc.v:108251.3-108269.6"
- process $proc$libresoc.v:108251$4237
+ attribute \src "libresoc.v:106876.3-106894.6"
+ process $proc$libresoc.v:106876$4181
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:108252.5-108252.29"
+ attribute \src "libresoc.v:106877.5-106877.29"
switch \initial
- attribute \src "libresoc.v:108252.9-108252.17"
+ attribute \src "libresoc.v:106877.9-106877.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0]
end
- attribute \src "libresoc.v:108270.3-108288.6"
- process $proc$libresoc.v:108270$4238
+ attribute \src "libresoc.v:106895.3-106913.6"
+ process $proc$libresoc.v:106895$4182
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:108271.5-108271.29"
+ attribute \src "libresoc.v:106896.5-106896.29"
switch \initial
- attribute \src "libresoc.v:108271.9-108271.17"
+ attribute \src "libresoc.v:106896.9-106896.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0]
end
- attribute \src "libresoc.v:108289.3-108307.6"
- process $proc$libresoc.v:108289$4239
+ attribute \src "libresoc.v:106914.3-106932.6"
+ process $proc$libresoc.v:106914$4183
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:108290.5-108290.29"
+ attribute \src "libresoc.v:106915.5-106915.29"
switch \initial
- attribute \src "libresoc.v:108290.9-108290.17"
+ attribute \src "libresoc.v:106915.9-106915.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0]
end
- attribute \src "libresoc.v:108308.3-108326.6"
- process $proc$libresoc.v:108308$4240
+ attribute \src "libresoc.v:106933.3-106951.6"
+ process $proc$libresoc.v:106933$4184
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:108309.5-108309.29"
+ attribute \src "libresoc.v:106934.5-106934.29"
switch \initial
- attribute \src "libresoc.v:108309.9-108309.17"
+ attribute \src "libresoc.v:106934.9-106934.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0]
end
- attribute \src "libresoc.v:108327.3-108345.6"
- process $proc$libresoc.v:108327$4241
+ attribute \src "libresoc.v:106952.3-106970.6"
+ process $proc$libresoc.v:106952$4185
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:108328.5-108328.29"
+ attribute \src "libresoc.v:106953.5-106953.29"
switch \initial
- attribute \src "libresoc.v:108328.9-108328.17"
+ attribute \src "libresoc.v:106953.9-106953.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:108346.3-108364.6"
- process $proc$libresoc.v:108346$4242
+ attribute \src "libresoc.v:106971.3-106989.6"
+ process $proc$libresoc.v:106971$4186
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0]
- attribute \src "libresoc.v:108347.5-108347.29"
+ attribute \src "libresoc.v:106972.5-106972.29"
switch \initial
- attribute \src "libresoc.v:108347.9-108347.17"
+ attribute \src "libresoc.v:106972.9-106972.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0]
end
- attribute \src "libresoc.v:108365.3-108383.6"
- process $proc$libresoc.v:108365$4243
+ attribute \src "libresoc.v:106990.3-107008.6"
+ process $proc$libresoc.v:106990$4187
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0]
- attribute \src "libresoc.v:108366.5-108366.29"
+ attribute \src "libresoc.v:106991.5-106991.29"
switch \initial
- attribute \src "libresoc.v:108366.9-108366.17"
+ attribute \src "libresoc.v:106991.9-106991.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:108384.3-108402.6"
- process $proc$libresoc.v:108384$4244
+ attribute \src "libresoc.v:107009.3-107027.6"
+ process $proc$libresoc.v:107009$4188
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:108385.5-108385.29"
+ attribute \src "libresoc.v:107010.5-107010.29"
switch \initial
- attribute \src "libresoc.v:108385.9-108385.17"
+ attribute \src "libresoc.v:107010.9-107010.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0]
end
- attribute \src "libresoc.v:108403.3-108421.6"
- process $proc$libresoc.v:108403$4245
+ attribute \src "libresoc.v:107028.3-107046.6"
+ process $proc$libresoc.v:107028$4189
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:108404.5-108404.29"
+ attribute \src "libresoc.v:107029.5-107029.29"
switch \initial
- attribute \src "libresoc.v:108404.9-108404.17"
+ attribute \src "libresoc.v:107029.9-107029.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0]
end
- attribute \src "libresoc.v:108422.3-108440.6"
- process $proc$libresoc.v:108422$4246
+ attribute \src "libresoc.v:107047.3-107065.6"
+ process $proc$libresoc.v:107047$4190
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:108423.5-108423.29"
+ attribute \src "libresoc.v:107048.5-107048.29"
switch \initial
- attribute \src "libresoc.v:108423.9-108423.17"
+ attribute \src "libresoc.v:107048.9-107048.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0]
end
- attribute \src "libresoc.v:108441.3-108459.6"
- process $proc$libresoc.v:108441$4247
+ attribute \src "libresoc.v:107066.3-107084.6"
+ process $proc$libresoc.v:107066$4191
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:108442.5-108442.29"
+ attribute \src "libresoc.v:107067.5-107067.29"
switch \initial
- attribute \src "libresoc.v:108442.9-108442.17"
+ attribute \src "libresoc.v:107067.9-107067.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:108465.1-110466.10"
+attribute \src "libresoc.v:107090.1-109091.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26"
attribute \generator "nMigen"
module \dec31_dec_sub26
- attribute \src "libresoc.v:110153.3-110204.6"
+ attribute \src "libresoc.v:108778.3-108829.6"
wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:110205.3-110256.6"
+ attribute \src "libresoc.v:108830.3-108881.6"
wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:109529.3-109580.6"
+ attribute \src "libresoc.v:108154.3-108205.6"
wire width 8 $0\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:109737.3-109788.6"
+ attribute \src "libresoc.v:108362.3-108413.6"
wire $0\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:108853.3-108904.6"
+ attribute \src "libresoc.v:107478.3-107529.6"
wire width 3 $0\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:108905.3-108956.6"
+ attribute \src "libresoc.v:107530.3-107581.6"
wire width 3 $0\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:109477.3-109528.6"
+ attribute \src "libresoc.v:108102.3-108153.6"
wire width 2 $0\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:109685.3-109736.6"
+ attribute \src "libresoc.v:108310.3-108361.6"
wire $0\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:109945.3-109996.6"
+ attribute \src "libresoc.v:108570.3-108621.6"
wire width 5 $0\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:108801.3-108852.6"
+ attribute \src "libresoc.v:107426.3-107477.6"
wire width 13 $0\dec31_dec_sub26_function_unit[12:0]
- attribute \src "libresoc.v:110257.3-110308.6"
+ attribute \src "libresoc.v:108882.3-108933.6"
wire width 3 $0\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:110309.3-110360.6"
+ attribute \src "libresoc.v:108934.3-108985.6"
wire width 4 $0\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:110361.3-110412.6"
+ attribute \src "libresoc.v:108986.3-109037.6"
wire width 2 $0\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:109373.3-109424.6"
+ attribute \src "libresoc.v:107998.3-108049.6"
wire width 7 $0\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:109581.3-109632.6"
+ attribute \src "libresoc.v:108206.3-108257.6"
wire $0\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:109633.3-109684.6"
+ attribute \src "libresoc.v:108258.3-108309.6"
wire $0\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:109893.3-109944.6"
+ attribute \src "libresoc.v:108518.3-108569.6"
wire $0\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:109269.3-109320.6"
+ attribute \src "libresoc.v:107894.3-107945.6"
wire width 4 $0\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:110049.3-110100.6"
+ attribute \src "libresoc.v:108674.3-108725.6"
wire $0\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:110413.3-110464.6"
+ attribute \src "libresoc.v:109038.3-109089.6"
wire width 2 $0\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:109425.3-109476.6"
+ attribute \src "libresoc.v:108050.3-108101.6"
wire width 2 $0\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:109841.3-109892.6"
+ attribute \src "libresoc.v:108466.3-108517.6"
wire $0\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:110101.3-110152.6"
+ attribute \src "libresoc.v:108726.3-108777.6"
wire $0\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:109997.3-110048.6"
+ attribute \src "libresoc.v:108622.3-108673.6"
wire $0\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:109789.3-109840.6"
+ attribute \src "libresoc.v:108414.3-108465.6"
wire $0\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:109165.3-109216.6"
+ attribute \src "libresoc.v:107790.3-107841.6"
wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:109217.3-109268.6"
+ attribute \src "libresoc.v:107842.3-107893.6"
wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:108957.3-109008.6"
+ attribute \src "libresoc.v:107582.3-107633.6"
wire width 3 $0\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:109009.3-109060.6"
+ attribute \src "libresoc.v:107634.3-107685.6"
wire width 3 $0\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:109061.3-109112.6"
+ attribute \src "libresoc.v:107686.3-107737.6"
wire width 3 $0\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:109113.3-109164.6"
+ attribute \src "libresoc.v:107738.3-107789.6"
wire width 3 $0\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:109321.3-109372.6"
+ attribute \src "libresoc.v:107946.3-107997.6"
wire width 2 $0\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:108466.7-108466.20"
+ attribute \src "libresoc.v:107091.7-107091.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:110153.3-110204.6"
+ attribute \src "libresoc.v:108778.3-108829.6"
wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:110205.3-110256.6"
+ attribute \src "libresoc.v:108830.3-108881.6"
wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:109529.3-109580.6"
+ attribute \src "libresoc.v:108154.3-108205.6"
wire width 8 $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:109737.3-109788.6"
+ attribute \src "libresoc.v:108362.3-108413.6"
wire $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:108853.3-108904.6"
+ attribute \src "libresoc.v:107478.3-107529.6"
wire width 3 $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:108905.3-108956.6"
+ attribute \src "libresoc.v:107530.3-107581.6"
wire width 3 $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:109477.3-109528.6"
+ attribute \src "libresoc.v:108102.3-108153.6"
wire width 2 $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:109685.3-109736.6"
+ attribute \src "libresoc.v:108310.3-108361.6"
wire $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:109945.3-109996.6"
+ attribute \src "libresoc.v:108570.3-108621.6"
wire width 5 $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:108801.3-108852.6"
+ attribute \src "libresoc.v:107426.3-107477.6"
wire width 13 $1\dec31_dec_sub26_function_unit[12:0]
- attribute \src "libresoc.v:110257.3-110308.6"
+ attribute \src "libresoc.v:108882.3-108933.6"
wire width 3 $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:110309.3-110360.6"
+ attribute \src "libresoc.v:108934.3-108985.6"
wire width 4 $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:110361.3-110412.6"
+ attribute \src "libresoc.v:108986.3-109037.6"
wire width 2 $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:109373.3-109424.6"
+ attribute \src "libresoc.v:107998.3-108049.6"
wire width 7 $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:109581.3-109632.6"
+ attribute \src "libresoc.v:108206.3-108257.6"
wire $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:109633.3-109684.6"
+ attribute \src "libresoc.v:108258.3-108309.6"
wire $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:109893.3-109944.6"
+ attribute \src "libresoc.v:108518.3-108569.6"
wire $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:109269.3-109320.6"
+ attribute \src "libresoc.v:107894.3-107945.6"
wire width 4 $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:110049.3-110100.6"
+ attribute \src "libresoc.v:108674.3-108725.6"
wire $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:110413.3-110464.6"
+ attribute \src "libresoc.v:109038.3-109089.6"
wire width 2 $1\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:109425.3-109476.6"
+ attribute \src "libresoc.v:108050.3-108101.6"
wire width 2 $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:109841.3-109892.6"
+ attribute \src "libresoc.v:108466.3-108517.6"
wire $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:110101.3-110152.6"
+ attribute \src "libresoc.v:108726.3-108777.6"
wire $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:109997.3-110048.6"
+ attribute \src "libresoc.v:108622.3-108673.6"
wire $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:109789.3-109840.6"
+ attribute \src "libresoc.v:108414.3-108465.6"
wire $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:109165.3-109216.6"
+ attribute \src "libresoc.v:107790.3-107841.6"
wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:109217.3-109268.6"
+ attribute \src "libresoc.v:107842.3-107893.6"
wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:108957.3-109008.6"
+ attribute \src "libresoc.v:107582.3-107633.6"
wire width 3 $1\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:109009.3-109060.6"
+ attribute \src "libresoc.v:107634.3-107685.6"
wire width 3 $1\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:109061.3-109112.6"
+ attribute \src "libresoc.v:107686.3-107737.6"
wire width 3 $1\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:109113.3-109164.6"
+ attribute \src "libresoc.v:107738.3-107789.6"
wire width 3 $1\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:109321.3-109372.6"
+ attribute \src "libresoc.v:107946.3-107997.6"
wire width 2 $1\dec31_dec_sub26_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub26_upd
- attribute \src "libresoc.v:108466.7-108466.15"
+ attribute \src "libresoc.v:107091.7-107091.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:108466.7-108466.20"
- process $proc$libresoc.v:108466$4281
+ attribute \src "libresoc.v:107091.7-107091.20"
+ process $proc$libresoc.v:107091$4225
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:108801.3-108852.6"
- process $proc$libresoc.v:108801$4249
+ attribute \src "libresoc.v:107426.3-107477.6"
+ process $proc$libresoc.v:107426$4193
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_function_unit[12:0] $1\dec31_dec_sub26_function_unit[12:0]
- attribute \src "libresoc.v:108802.5-108802.29"
+ attribute \src "libresoc.v:107427.5-107427.29"
switch \initial
- attribute \src "libresoc.v:108802.9-108802.17"
+ attribute \src "libresoc.v:107427.9-107427.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[12:0]
end
- attribute \src "libresoc.v:108853.3-108904.6"
- process $proc$libresoc.v:108853$4250
+ attribute \src "libresoc.v:107478.3-107529.6"
+ process $proc$libresoc.v:107478$4194
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:108854.5-108854.29"
+ attribute \src "libresoc.v:107479.5-107479.29"
switch \initial
- attribute \src "libresoc.v:108854.9-108854.17"
+ attribute \src "libresoc.v:107479.9-107479.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0]
end
- attribute \src "libresoc.v:108905.3-108956.6"
- process $proc$libresoc.v:108905$4251
+ attribute \src "libresoc.v:107530.3-107581.6"
+ process $proc$libresoc.v:107530$4195
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:108906.5-108906.29"
+ attribute \src "libresoc.v:107531.5-107531.29"
switch \initial
- attribute \src "libresoc.v:108906.9-108906.17"
+ attribute \src "libresoc.v:107531.9-107531.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0]
end
- attribute \src "libresoc.v:108957.3-109008.6"
- process $proc$libresoc.v:108957$4252
+ attribute \src "libresoc.v:107582.3-107633.6"
+ process $proc$libresoc.v:107582$4196
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0]
- attribute \src "libresoc.v:108958.5-108958.29"
+ attribute \src "libresoc.v:107583.5-107583.29"
switch \initial
- attribute \src "libresoc.v:108958.9-108958.17"
+ attribute \src "libresoc.v:107583.9-107583.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0]
end
- attribute \src "libresoc.v:109009.3-109060.6"
- process $proc$libresoc.v:109009$4253
+ attribute \src "libresoc.v:107634.3-107685.6"
+ process $proc$libresoc.v:107634$4197
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0]
- attribute \src "libresoc.v:109010.5-109010.29"
+ attribute \src "libresoc.v:107635.5-107635.29"
switch \initial
- attribute \src "libresoc.v:109010.9-109010.17"
+ attribute \src "libresoc.v:107635.9-107635.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0]
end
- attribute \src "libresoc.v:109061.3-109112.6"
- process $proc$libresoc.v:109061$4254
+ attribute \src "libresoc.v:107686.3-107737.6"
+ process $proc$libresoc.v:107686$4198
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0]
- attribute \src "libresoc.v:109062.5-109062.29"
+ attribute \src "libresoc.v:107687.5-107687.29"
switch \initial
- attribute \src "libresoc.v:109062.9-109062.17"
+ attribute \src "libresoc.v:107687.9-107687.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0]
end
- attribute \src "libresoc.v:109113.3-109164.6"
- process $proc$libresoc.v:109113$4255
+ attribute \src "libresoc.v:107738.3-107789.6"
+ process $proc$libresoc.v:107738$4199
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0]
- attribute \src "libresoc.v:109114.5-109114.29"
+ attribute \src "libresoc.v:107739.5-107739.29"
switch \initial
- attribute \src "libresoc.v:109114.9-109114.17"
+ attribute \src "libresoc.v:107739.9-107739.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0]
end
- attribute \src "libresoc.v:109165.3-109216.6"
- process $proc$libresoc.v:109165$4256
+ attribute \src "libresoc.v:107790.3-107841.6"
+ process $proc$libresoc.v:107790$4200
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0]
- attribute \src "libresoc.v:109166.5-109166.29"
+ attribute \src "libresoc.v:107791.5-107791.29"
switch \initial
- attribute \src "libresoc.v:109166.9-109166.17"
+ attribute \src "libresoc.v:107791.9-107791.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:109217.3-109268.6"
- process $proc$libresoc.v:109217$4257
+ attribute \src "libresoc.v:107842.3-107893.6"
+ process $proc$libresoc.v:107842$4201
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0]
- attribute \src "libresoc.v:109218.5-109218.29"
+ attribute \src "libresoc.v:107843.5-107843.29"
switch \initial
- attribute \src "libresoc.v:109218.9-109218.17"
+ attribute \src "libresoc.v:107843.9-107843.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:109269.3-109320.6"
- process $proc$libresoc.v:109269$4258
+ attribute \src "libresoc.v:107894.3-107945.6"
+ process $proc$libresoc.v:107894$4202
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:109270.5-109270.29"
+ attribute \src "libresoc.v:107895.5-107895.29"
switch \initial
- attribute \src "libresoc.v:109270.9-109270.17"
+ attribute \src "libresoc.v:107895.9-107895.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0]
end
- attribute \src "libresoc.v:109321.3-109372.6"
- process $proc$libresoc.v:109321$4259
+ attribute \src "libresoc.v:107946.3-107997.6"
+ process $proc$libresoc.v:107946$4203
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:109322.5-109322.29"
+ attribute \src "libresoc.v:107947.5-107947.29"
switch \initial
- attribute \src "libresoc.v:109322.9-109322.17"
+ attribute \src "libresoc.v:107947.9-107947.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0]
end
- attribute \src "libresoc.v:109373.3-109424.6"
- process $proc$libresoc.v:109373$4260
+ attribute \src "libresoc.v:107998.3-108049.6"
+ process $proc$libresoc.v:107998$4204
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:109374.5-109374.29"
+ attribute \src "libresoc.v:107999.5-107999.29"
switch \initial
- attribute \src "libresoc.v:109374.9-109374.17"
+ attribute \src "libresoc.v:107999.9-107999.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0]
end
- attribute \src "libresoc.v:109425.3-109476.6"
- process $proc$libresoc.v:109425$4261
+ attribute \src "libresoc.v:108050.3-108101.6"
+ process $proc$libresoc.v:108050$4205
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:109426.5-109426.29"
+ attribute \src "libresoc.v:108051.5-108051.29"
switch \initial
- attribute \src "libresoc.v:109426.9-109426.17"
+ attribute \src "libresoc.v:108051.9-108051.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0]
end
- attribute \src "libresoc.v:109477.3-109528.6"
- process $proc$libresoc.v:109477$4262
+ attribute \src "libresoc.v:108102.3-108153.6"
+ process $proc$libresoc.v:108102$4206
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:109478.5-109478.29"
+ attribute \src "libresoc.v:108103.5-108103.29"
switch \initial
- attribute \src "libresoc.v:109478.9-109478.17"
+ attribute \src "libresoc.v:108103.9-108103.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0]
end
- attribute \src "libresoc.v:109529.3-109580.6"
- process $proc$libresoc.v:109529$4263
+ attribute \src "libresoc.v:108154.3-108205.6"
+ process $proc$libresoc.v:108154$4207
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:109530.5-109530.29"
+ attribute \src "libresoc.v:108155.5-108155.29"
switch \initial
- attribute \src "libresoc.v:109530.9-109530.17"
+ attribute \src "libresoc.v:108155.9-108155.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0]
end
- attribute \src "libresoc.v:109581.3-109632.6"
- process $proc$libresoc.v:109581$4264
+ attribute \src "libresoc.v:108206.3-108257.6"
+ process $proc$libresoc.v:108206$4208
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:109582.5-109582.29"
+ attribute \src "libresoc.v:108207.5-108207.29"
switch \initial
- attribute \src "libresoc.v:109582.9-109582.17"
+ attribute \src "libresoc.v:108207.9-108207.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0]
end
- attribute \src "libresoc.v:109633.3-109684.6"
- process $proc$libresoc.v:109633$4265
+ attribute \src "libresoc.v:108258.3-108309.6"
+ process $proc$libresoc.v:108258$4209
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:109634.5-109634.29"
+ attribute \src "libresoc.v:108259.5-108259.29"
switch \initial
- attribute \src "libresoc.v:109634.9-109634.17"
+ attribute \src "libresoc.v:108259.9-108259.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0]
end
- attribute \src "libresoc.v:109685.3-109736.6"
- process $proc$libresoc.v:109685$4266
+ attribute \src "libresoc.v:108310.3-108361.6"
+ process $proc$libresoc.v:108310$4210
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:109686.5-109686.29"
+ attribute \src "libresoc.v:108311.5-108311.29"
switch \initial
- attribute \src "libresoc.v:109686.9-109686.17"
+ attribute \src "libresoc.v:108311.9-108311.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0]
end
- attribute \src "libresoc.v:109737.3-109788.6"
- process $proc$libresoc.v:109737$4267
+ attribute \src "libresoc.v:108362.3-108413.6"
+ process $proc$libresoc.v:108362$4211
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:109738.5-109738.29"
+ attribute \src "libresoc.v:108363.5-108363.29"
switch \initial
- attribute \src "libresoc.v:109738.9-109738.17"
+ attribute \src "libresoc.v:108363.9-108363.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0]
end
- attribute \src "libresoc.v:109789.3-109840.6"
- process $proc$libresoc.v:109789$4268
+ attribute \src "libresoc.v:108414.3-108465.6"
+ process $proc$libresoc.v:108414$4212
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:109790.5-109790.29"
+ attribute \src "libresoc.v:108415.5-108415.29"
switch \initial
- attribute \src "libresoc.v:109790.9-109790.17"
+ attribute \src "libresoc.v:108415.9-108415.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0]
end
- attribute \src "libresoc.v:109841.3-109892.6"
- process $proc$libresoc.v:109841$4269
+ attribute \src "libresoc.v:108466.3-108517.6"
+ process $proc$libresoc.v:108466$4213
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:109842.5-109842.29"
+ attribute \src "libresoc.v:108467.5-108467.29"
switch \initial
- attribute \src "libresoc.v:109842.9-109842.17"
+ attribute \src "libresoc.v:108467.9-108467.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0]
end
- attribute \src "libresoc.v:109893.3-109944.6"
- process $proc$libresoc.v:109893$4270
+ attribute \src "libresoc.v:108518.3-108569.6"
+ process $proc$libresoc.v:108518$4214
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:109894.5-109894.29"
+ attribute \src "libresoc.v:108519.5-108519.29"
switch \initial
- attribute \src "libresoc.v:109894.9-109894.17"
+ attribute \src "libresoc.v:108519.9-108519.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0]
end
- attribute \src "libresoc.v:109945.3-109996.6"
- process $proc$libresoc.v:109945$4271
+ attribute \src "libresoc.v:108570.3-108621.6"
+ process $proc$libresoc.v:108570$4215
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:109946.5-109946.29"
+ attribute \src "libresoc.v:108571.5-108571.29"
switch \initial
- attribute \src "libresoc.v:109946.9-109946.17"
+ attribute \src "libresoc.v:108571.9-108571.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0]
end
- attribute \src "libresoc.v:109997.3-110048.6"
- process $proc$libresoc.v:109997$4272
+ attribute \src "libresoc.v:108622.3-108673.6"
+ process $proc$libresoc.v:108622$4216
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:109998.5-109998.29"
+ attribute \src "libresoc.v:108623.5-108623.29"
switch \initial
- attribute \src "libresoc.v:109998.9-109998.17"
+ attribute \src "libresoc.v:108623.9-108623.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0]
end
- attribute \src "libresoc.v:110049.3-110100.6"
- process $proc$libresoc.v:110049$4273
+ attribute \src "libresoc.v:108674.3-108725.6"
+ process $proc$libresoc.v:108674$4217
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:110050.5-110050.29"
+ attribute \src "libresoc.v:108675.5-108675.29"
switch \initial
- attribute \src "libresoc.v:110050.9-110050.17"
+ attribute \src "libresoc.v:108675.9-108675.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0]
end
- attribute \src "libresoc.v:110101.3-110152.6"
- process $proc$libresoc.v:110101$4274
+ attribute \src "libresoc.v:108726.3-108777.6"
+ process $proc$libresoc.v:108726$4218
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:110102.5-110102.29"
+ attribute \src "libresoc.v:108727.5-108727.29"
switch \initial
- attribute \src "libresoc.v:110102.9-110102.17"
+ attribute \src "libresoc.v:108727.9-108727.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:110153.3-110204.6"
- process $proc$libresoc.v:110153$4275
+ attribute \src "libresoc.v:108778.3-108829.6"
+ process $proc$libresoc.v:108778$4219
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0]
- attribute \src "libresoc.v:110154.5-110154.29"
+ attribute \src "libresoc.v:108779.5-108779.29"
switch \initial
- attribute \src "libresoc.v:110154.9-110154.17"
+ attribute \src "libresoc.v:108779.9-108779.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0]
end
- attribute \src "libresoc.v:110205.3-110256.6"
- process $proc$libresoc.v:110205$4276
+ attribute \src "libresoc.v:108830.3-108881.6"
+ process $proc$libresoc.v:108830$4220
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0]
- attribute \src "libresoc.v:110206.5-110206.29"
+ attribute \src "libresoc.v:108831.5-108831.29"
switch \initial
- attribute \src "libresoc.v:110206.9-110206.17"
+ attribute \src "libresoc.v:108831.9-108831.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:110257.3-110308.6"
- process $proc$libresoc.v:110257$4277
+ attribute \src "libresoc.v:108882.3-108933.6"
+ process $proc$libresoc.v:108882$4221
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:110258.5-110258.29"
+ attribute \src "libresoc.v:108883.5-108883.29"
switch \initial
- attribute \src "libresoc.v:110258.9-110258.17"
+ attribute \src "libresoc.v:108883.9-108883.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0]
end
- attribute \src "libresoc.v:110309.3-110360.6"
- process $proc$libresoc.v:110309$4278
+ attribute \src "libresoc.v:108934.3-108985.6"
+ process $proc$libresoc.v:108934$4222
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:110310.5-110310.29"
+ attribute \src "libresoc.v:108935.5-108935.29"
switch \initial
- attribute \src "libresoc.v:110310.9-110310.17"
+ attribute \src "libresoc.v:108935.9-108935.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0]
end
- attribute \src "libresoc.v:110361.3-110412.6"
- process $proc$libresoc.v:110361$4279
+ attribute \src "libresoc.v:108986.3-109037.6"
+ process $proc$libresoc.v:108986$4223
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:110362.5-110362.29"
+ attribute \src "libresoc.v:108987.5-108987.29"
switch \initial
- attribute \src "libresoc.v:110362.9-110362.17"
+ attribute \src "libresoc.v:108987.9-108987.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0]
end
- attribute \src "libresoc.v:110413.3-110464.6"
- process $proc$libresoc.v:110413$4280
+ attribute \src "libresoc.v:109038.3-109089.6"
+ process $proc$libresoc.v:109038$4224
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:110414.5-110414.29"
+ attribute \src "libresoc.v:109039.5-109039.29"
switch \initial
- attribute \src "libresoc.v:110414.9-110414.17"
+ attribute \src "libresoc.v:109039.9-109039.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:110470.1-111415.10"
+attribute \src "libresoc.v:109095.1-110040.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27"
attribute \generator "nMigen"
module \dec31_dec_sub27
- attribute \src "libresoc.v:111300.3-111318.6"
+ attribute \src "libresoc.v:109925.3-109943.6"
wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:111319.3-111337.6"
+ attribute \src "libresoc.v:109944.3-109962.6"
wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:111072.3-111090.6"
+ attribute \src "libresoc.v:109697.3-109715.6"
wire width 8 $0\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:111148.3-111166.6"
+ attribute \src "libresoc.v:109773.3-109791.6"
wire $0\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:110825.3-110843.6"
+ attribute \src "libresoc.v:109450.3-109468.6"
wire width 3 $0\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:110844.3-110862.6"
+ attribute \src "libresoc.v:109469.3-109487.6"
wire width 3 $0\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:111053.3-111071.6"
+ attribute \src "libresoc.v:109678.3-109696.6"
wire width 2 $0\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:111129.3-111147.6"
+ attribute \src "libresoc.v:109754.3-109772.6"
wire $0\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:111224.3-111242.6"
+ attribute \src "libresoc.v:109849.3-109867.6"
wire width 5 $0\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:110806.3-110824.6"
+ attribute \src "libresoc.v:109431.3-109449.6"
wire width 13 $0\dec31_dec_sub27_function_unit[12:0]
- attribute \src "libresoc.v:111338.3-111356.6"
+ attribute \src "libresoc.v:109963.3-109981.6"
wire width 3 $0\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:111357.3-111375.6"
+ attribute \src "libresoc.v:109982.3-110000.6"
wire width 4 $0\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:111376.3-111394.6"
+ attribute \src "libresoc.v:110001.3-110019.6"
wire width 2 $0\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:111015.3-111033.6"
+ attribute \src "libresoc.v:109640.3-109658.6"
wire width 7 $0\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:111091.3-111109.6"
+ attribute \src "libresoc.v:109716.3-109734.6"
wire $0\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:111110.3-111128.6"
+ attribute \src "libresoc.v:109735.3-109753.6"
wire $0\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:111205.3-111223.6"
+ attribute \src "libresoc.v:109830.3-109848.6"
wire $0\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:110977.3-110995.6"
+ attribute \src "libresoc.v:109602.3-109620.6"
wire width 4 $0\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:111262.3-111280.6"
+ attribute \src "libresoc.v:109887.3-109905.6"
wire $0\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:111395.3-111413.6"
+ attribute \src "libresoc.v:110020.3-110038.6"
wire width 2 $0\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:111034.3-111052.6"
+ attribute \src "libresoc.v:109659.3-109677.6"
wire width 2 $0\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:111186.3-111204.6"
+ attribute \src "libresoc.v:109811.3-109829.6"
wire $0\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:111281.3-111299.6"
+ attribute \src "libresoc.v:109906.3-109924.6"
wire $0\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:111243.3-111261.6"
+ attribute \src "libresoc.v:109868.3-109886.6"
wire $0\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:111167.3-111185.6"
+ attribute \src "libresoc.v:109792.3-109810.6"
wire $0\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:110939.3-110957.6"
+ attribute \src "libresoc.v:109564.3-109582.6"
wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:110958.3-110976.6"
+ attribute \src "libresoc.v:109583.3-109601.6"
wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:110863.3-110881.6"
+ attribute \src "libresoc.v:109488.3-109506.6"
wire width 3 $0\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:110882.3-110900.6"
+ attribute \src "libresoc.v:109507.3-109525.6"
wire width 3 $0\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:110901.3-110919.6"
+ attribute \src "libresoc.v:109526.3-109544.6"
wire width 3 $0\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:110920.3-110938.6"
+ attribute \src "libresoc.v:109545.3-109563.6"
wire width 3 $0\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:110996.3-111014.6"
+ attribute \src "libresoc.v:109621.3-109639.6"
wire width 2 $0\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:110471.7-110471.20"
+ attribute \src "libresoc.v:109096.7-109096.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:111300.3-111318.6"
+ attribute \src "libresoc.v:109925.3-109943.6"
wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:111319.3-111337.6"
+ attribute \src "libresoc.v:109944.3-109962.6"
wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:111072.3-111090.6"
+ attribute \src "libresoc.v:109697.3-109715.6"
wire width 8 $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:111148.3-111166.6"
+ attribute \src "libresoc.v:109773.3-109791.6"
wire $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:110825.3-110843.6"
+ attribute \src "libresoc.v:109450.3-109468.6"
wire width 3 $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:110844.3-110862.6"
+ attribute \src "libresoc.v:109469.3-109487.6"
wire width 3 $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:111053.3-111071.6"
+ attribute \src "libresoc.v:109678.3-109696.6"
wire width 2 $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:111129.3-111147.6"
+ attribute \src "libresoc.v:109754.3-109772.6"
wire $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:111224.3-111242.6"
+ attribute \src "libresoc.v:109849.3-109867.6"
wire width 5 $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:110806.3-110824.6"
+ attribute \src "libresoc.v:109431.3-109449.6"
wire width 13 $1\dec31_dec_sub27_function_unit[12:0]
- attribute \src "libresoc.v:111338.3-111356.6"
+ attribute \src "libresoc.v:109963.3-109981.6"
wire width 3 $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:111357.3-111375.6"
+ attribute \src "libresoc.v:109982.3-110000.6"
wire width 4 $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:111376.3-111394.6"
+ attribute \src "libresoc.v:110001.3-110019.6"
wire width 2 $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:111015.3-111033.6"
+ attribute \src "libresoc.v:109640.3-109658.6"
wire width 7 $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:111091.3-111109.6"
+ attribute \src "libresoc.v:109716.3-109734.6"
wire $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:111110.3-111128.6"
+ attribute \src "libresoc.v:109735.3-109753.6"
wire $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:111205.3-111223.6"
+ attribute \src "libresoc.v:109830.3-109848.6"
wire $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:110977.3-110995.6"
+ attribute \src "libresoc.v:109602.3-109620.6"
wire width 4 $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:111262.3-111280.6"
+ attribute \src "libresoc.v:109887.3-109905.6"
wire $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:111395.3-111413.6"
+ attribute \src "libresoc.v:110020.3-110038.6"
wire width 2 $1\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:111034.3-111052.6"
+ attribute \src "libresoc.v:109659.3-109677.6"
wire width 2 $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:111186.3-111204.6"
+ attribute \src "libresoc.v:109811.3-109829.6"
wire $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:111281.3-111299.6"
+ attribute \src "libresoc.v:109906.3-109924.6"
wire $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:111243.3-111261.6"
+ attribute \src "libresoc.v:109868.3-109886.6"
wire $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:111167.3-111185.6"
+ attribute \src "libresoc.v:109792.3-109810.6"
wire $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:110939.3-110957.6"
+ attribute \src "libresoc.v:109564.3-109582.6"
wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:110958.3-110976.6"
+ attribute \src "libresoc.v:109583.3-109601.6"
wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:110863.3-110881.6"
+ attribute \src "libresoc.v:109488.3-109506.6"
wire width 3 $1\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:110882.3-110900.6"
+ attribute \src "libresoc.v:109507.3-109525.6"
wire width 3 $1\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:110901.3-110919.6"
+ attribute \src "libresoc.v:109526.3-109544.6"
wire width 3 $1\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:110920.3-110938.6"
+ attribute \src "libresoc.v:109545.3-109563.6"
wire width 3 $1\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:110996.3-111014.6"
+ attribute \src "libresoc.v:109621.3-109639.6"
wire width 2 $1\dec31_dec_sub27_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub27_upd
- attribute \src "libresoc.v:110471.7-110471.15"
+ attribute \src "libresoc.v:109096.7-109096.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:110471.7-110471.20"
- process $proc$libresoc.v:110471$4314
+ attribute \src "libresoc.v:109096.7-109096.20"
+ process $proc$libresoc.v:109096$4258
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:110806.3-110824.6"
- process $proc$libresoc.v:110806$4282
+ attribute \src "libresoc.v:109431.3-109449.6"
+ process $proc$libresoc.v:109431$4226
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_function_unit[12:0] $1\dec31_dec_sub27_function_unit[12:0]
- attribute \src "libresoc.v:110807.5-110807.29"
+ attribute \src "libresoc.v:109432.5-109432.29"
switch \initial
- attribute \src "libresoc.v:110807.9-110807.17"
+ attribute \src "libresoc.v:109432.9-109432.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[12:0]
end
- attribute \src "libresoc.v:110825.3-110843.6"
- process $proc$libresoc.v:110825$4283
+ attribute \src "libresoc.v:109450.3-109468.6"
+ process $proc$libresoc.v:109450$4227
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:110826.5-110826.29"
+ attribute \src "libresoc.v:109451.5-109451.29"
switch \initial
- attribute \src "libresoc.v:110826.9-110826.17"
+ attribute \src "libresoc.v:109451.9-109451.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0]
end
- attribute \src "libresoc.v:110844.3-110862.6"
- process $proc$libresoc.v:110844$4284
+ attribute \src "libresoc.v:109469.3-109487.6"
+ process $proc$libresoc.v:109469$4228
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:110845.5-110845.29"
+ attribute \src "libresoc.v:109470.5-109470.29"
switch \initial
- attribute \src "libresoc.v:110845.9-110845.17"
+ attribute \src "libresoc.v:109470.9-109470.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0]
end
- attribute \src "libresoc.v:110863.3-110881.6"
- process $proc$libresoc.v:110863$4285
+ attribute \src "libresoc.v:109488.3-109506.6"
+ process $proc$libresoc.v:109488$4229
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0]
- attribute \src "libresoc.v:110864.5-110864.29"
+ attribute \src "libresoc.v:109489.5-109489.29"
switch \initial
- attribute \src "libresoc.v:110864.9-110864.17"
+ attribute \src "libresoc.v:109489.9-109489.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0]
end
- attribute \src "libresoc.v:110882.3-110900.6"
- process $proc$libresoc.v:110882$4286
+ attribute \src "libresoc.v:109507.3-109525.6"
+ process $proc$libresoc.v:109507$4230
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0]
- attribute \src "libresoc.v:110883.5-110883.29"
+ attribute \src "libresoc.v:109508.5-109508.29"
switch \initial
- attribute \src "libresoc.v:110883.9-110883.17"
+ attribute \src "libresoc.v:109508.9-109508.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0]
end
- attribute \src "libresoc.v:110901.3-110919.6"
- process $proc$libresoc.v:110901$4287
+ attribute \src "libresoc.v:109526.3-109544.6"
+ process $proc$libresoc.v:109526$4231
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0]
- attribute \src "libresoc.v:110902.5-110902.29"
+ attribute \src "libresoc.v:109527.5-109527.29"
switch \initial
- attribute \src "libresoc.v:110902.9-110902.17"
+ attribute \src "libresoc.v:109527.9-109527.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0]
end
- attribute \src "libresoc.v:110920.3-110938.6"
- process $proc$libresoc.v:110920$4288
+ attribute \src "libresoc.v:109545.3-109563.6"
+ process $proc$libresoc.v:109545$4232
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0]
- attribute \src "libresoc.v:110921.5-110921.29"
+ attribute \src "libresoc.v:109546.5-109546.29"
switch \initial
- attribute \src "libresoc.v:110921.9-110921.17"
+ attribute \src "libresoc.v:109546.9-109546.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0]
end
- attribute \src "libresoc.v:110939.3-110957.6"
- process $proc$libresoc.v:110939$4289
+ attribute \src "libresoc.v:109564.3-109582.6"
+ process $proc$libresoc.v:109564$4233
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0]
- attribute \src "libresoc.v:110940.5-110940.29"
+ attribute \src "libresoc.v:109565.5-109565.29"
switch \initial
- attribute \src "libresoc.v:110940.9-110940.17"
+ attribute \src "libresoc.v:109565.9-109565.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:110958.3-110976.6"
- process $proc$libresoc.v:110958$4290
+ attribute \src "libresoc.v:109583.3-109601.6"
+ process $proc$libresoc.v:109583$4234
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0]
- attribute \src "libresoc.v:110959.5-110959.29"
+ attribute \src "libresoc.v:109584.5-109584.29"
switch \initial
- attribute \src "libresoc.v:110959.9-110959.17"
+ attribute \src "libresoc.v:109584.9-109584.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:110977.3-110995.6"
- process $proc$libresoc.v:110977$4291
+ attribute \src "libresoc.v:109602.3-109620.6"
+ process $proc$libresoc.v:109602$4235
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:110978.5-110978.29"
+ attribute \src "libresoc.v:109603.5-109603.29"
switch \initial
- attribute \src "libresoc.v:110978.9-110978.17"
+ attribute \src "libresoc.v:109603.9-109603.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0]
end
- attribute \src "libresoc.v:110996.3-111014.6"
- process $proc$libresoc.v:110996$4292
+ attribute \src "libresoc.v:109621.3-109639.6"
+ process $proc$libresoc.v:109621$4236
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:110997.5-110997.29"
+ attribute \src "libresoc.v:109622.5-109622.29"
switch \initial
- attribute \src "libresoc.v:110997.9-110997.17"
+ attribute \src "libresoc.v:109622.9-109622.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0]
end
- attribute \src "libresoc.v:111015.3-111033.6"
- process $proc$libresoc.v:111015$4293
+ attribute \src "libresoc.v:109640.3-109658.6"
+ process $proc$libresoc.v:109640$4237
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:111016.5-111016.29"
+ attribute \src "libresoc.v:109641.5-109641.29"
switch \initial
- attribute \src "libresoc.v:111016.9-111016.17"
+ attribute \src "libresoc.v:109641.9-109641.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0]
end
- attribute \src "libresoc.v:111034.3-111052.6"
- process $proc$libresoc.v:111034$4294
+ attribute \src "libresoc.v:109659.3-109677.6"
+ process $proc$libresoc.v:109659$4238
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:111035.5-111035.29"
+ attribute \src "libresoc.v:109660.5-109660.29"
switch \initial
- attribute \src "libresoc.v:111035.9-111035.17"
+ attribute \src "libresoc.v:109660.9-109660.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0]
end
- attribute \src "libresoc.v:111053.3-111071.6"
- process $proc$libresoc.v:111053$4295
+ attribute \src "libresoc.v:109678.3-109696.6"
+ process $proc$libresoc.v:109678$4239
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:111054.5-111054.29"
+ attribute \src "libresoc.v:109679.5-109679.29"
switch \initial
- attribute \src "libresoc.v:111054.9-111054.17"
+ attribute \src "libresoc.v:109679.9-109679.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0]
end
- attribute \src "libresoc.v:111072.3-111090.6"
- process $proc$libresoc.v:111072$4296
+ attribute \src "libresoc.v:109697.3-109715.6"
+ process $proc$libresoc.v:109697$4240
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:111073.5-111073.29"
+ attribute \src "libresoc.v:109698.5-109698.29"
switch \initial
- attribute \src "libresoc.v:111073.9-111073.17"
+ attribute \src "libresoc.v:109698.9-109698.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0]
end
- attribute \src "libresoc.v:111091.3-111109.6"
- process $proc$libresoc.v:111091$4297
+ attribute \src "libresoc.v:109716.3-109734.6"
+ process $proc$libresoc.v:109716$4241
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:111092.5-111092.29"
+ attribute \src "libresoc.v:109717.5-109717.29"
switch \initial
- attribute \src "libresoc.v:111092.9-111092.17"
+ attribute \src "libresoc.v:109717.9-109717.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0]
end
- attribute \src "libresoc.v:111110.3-111128.6"
- process $proc$libresoc.v:111110$4298
+ attribute \src "libresoc.v:109735.3-109753.6"
+ process $proc$libresoc.v:109735$4242
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:111111.5-111111.29"
+ attribute \src "libresoc.v:109736.5-109736.29"
switch \initial
- attribute \src "libresoc.v:111111.9-111111.17"
+ attribute \src "libresoc.v:109736.9-109736.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0]
end
- attribute \src "libresoc.v:111129.3-111147.6"
- process $proc$libresoc.v:111129$4299
+ attribute \src "libresoc.v:109754.3-109772.6"
+ process $proc$libresoc.v:109754$4243
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:111130.5-111130.29"
+ attribute \src "libresoc.v:109755.5-109755.29"
switch \initial
- attribute \src "libresoc.v:111130.9-111130.17"
+ attribute \src "libresoc.v:109755.9-109755.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0]
end
- attribute \src "libresoc.v:111148.3-111166.6"
- process $proc$libresoc.v:111148$4300
+ attribute \src "libresoc.v:109773.3-109791.6"
+ process $proc$libresoc.v:109773$4244
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:111149.5-111149.29"
+ attribute \src "libresoc.v:109774.5-109774.29"
switch \initial
- attribute \src "libresoc.v:111149.9-111149.17"
+ attribute \src "libresoc.v:109774.9-109774.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0]
end
- attribute \src "libresoc.v:111167.3-111185.6"
- process $proc$libresoc.v:111167$4301
+ attribute \src "libresoc.v:109792.3-109810.6"
+ process $proc$libresoc.v:109792$4245
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:111168.5-111168.29"
+ attribute \src "libresoc.v:109793.5-109793.29"
switch \initial
- attribute \src "libresoc.v:111168.9-111168.17"
+ attribute \src "libresoc.v:109793.9-109793.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0]
end
- attribute \src "libresoc.v:111186.3-111204.6"
- process $proc$libresoc.v:111186$4302
+ attribute \src "libresoc.v:109811.3-109829.6"
+ process $proc$libresoc.v:109811$4246
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:111187.5-111187.29"
+ attribute \src "libresoc.v:109812.5-109812.29"
switch \initial
- attribute \src "libresoc.v:111187.9-111187.17"
+ attribute \src "libresoc.v:109812.9-109812.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0]
end
- attribute \src "libresoc.v:111205.3-111223.6"
- process $proc$libresoc.v:111205$4303
+ attribute \src "libresoc.v:109830.3-109848.6"
+ process $proc$libresoc.v:109830$4247
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:111206.5-111206.29"
+ attribute \src "libresoc.v:109831.5-109831.29"
switch \initial
- attribute \src "libresoc.v:111206.9-111206.17"
+ attribute \src "libresoc.v:109831.9-109831.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0]
end
- attribute \src "libresoc.v:111224.3-111242.6"
- process $proc$libresoc.v:111224$4304
+ attribute \src "libresoc.v:109849.3-109867.6"
+ process $proc$libresoc.v:109849$4248
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:111225.5-111225.29"
+ attribute \src "libresoc.v:109850.5-109850.29"
switch \initial
- attribute \src "libresoc.v:111225.9-111225.17"
+ attribute \src "libresoc.v:109850.9-109850.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0]
end
- attribute \src "libresoc.v:111243.3-111261.6"
- process $proc$libresoc.v:111243$4305
+ attribute \src "libresoc.v:109868.3-109886.6"
+ process $proc$libresoc.v:109868$4249
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:111244.5-111244.29"
+ attribute \src "libresoc.v:109869.5-109869.29"
switch \initial
- attribute \src "libresoc.v:111244.9-111244.17"
+ attribute \src "libresoc.v:109869.9-109869.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0]
end
- attribute \src "libresoc.v:111262.3-111280.6"
- process $proc$libresoc.v:111262$4306
+ attribute \src "libresoc.v:109887.3-109905.6"
+ process $proc$libresoc.v:109887$4250
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:111263.5-111263.29"
+ attribute \src "libresoc.v:109888.5-109888.29"
switch \initial
- attribute \src "libresoc.v:111263.9-111263.17"
+ attribute \src "libresoc.v:109888.9-109888.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0]
end
- attribute \src "libresoc.v:111281.3-111299.6"
- process $proc$libresoc.v:111281$4307
+ attribute \src "libresoc.v:109906.3-109924.6"
+ process $proc$libresoc.v:109906$4251
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:111282.5-111282.29"
+ attribute \src "libresoc.v:109907.5-109907.29"
switch \initial
- attribute \src "libresoc.v:111282.9-111282.17"
+ attribute \src "libresoc.v:109907.9-109907.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:111300.3-111318.6"
- process $proc$libresoc.v:111300$4308
+ attribute \src "libresoc.v:109925.3-109943.6"
+ process $proc$libresoc.v:109925$4252
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0]
- attribute \src "libresoc.v:111301.5-111301.29"
+ attribute \src "libresoc.v:109926.5-109926.29"
switch \initial
- attribute \src "libresoc.v:111301.9-111301.17"
+ attribute \src "libresoc.v:109926.9-109926.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0]
end
- attribute \src "libresoc.v:111319.3-111337.6"
- process $proc$libresoc.v:111319$4309
+ attribute \src "libresoc.v:109944.3-109962.6"
+ process $proc$libresoc.v:109944$4253
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0]
- attribute \src "libresoc.v:111320.5-111320.29"
+ attribute \src "libresoc.v:109945.5-109945.29"
switch \initial
- attribute \src "libresoc.v:111320.9-111320.17"
+ attribute \src "libresoc.v:109945.9-109945.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:111338.3-111356.6"
- process $proc$libresoc.v:111338$4310
+ attribute \src "libresoc.v:109963.3-109981.6"
+ process $proc$libresoc.v:109963$4254
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:111339.5-111339.29"
+ attribute \src "libresoc.v:109964.5-109964.29"
switch \initial
- attribute \src "libresoc.v:111339.9-111339.17"
+ attribute \src "libresoc.v:109964.9-109964.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0]
end
- attribute \src "libresoc.v:111357.3-111375.6"
- process $proc$libresoc.v:111357$4311
+ attribute \src "libresoc.v:109982.3-110000.6"
+ process $proc$libresoc.v:109982$4255
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:111358.5-111358.29"
+ attribute \src "libresoc.v:109983.5-109983.29"
switch \initial
- attribute \src "libresoc.v:111358.9-111358.17"
+ attribute \src "libresoc.v:109983.9-109983.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0]
end
- attribute \src "libresoc.v:111376.3-111394.6"
- process $proc$libresoc.v:111376$4312
+ attribute \src "libresoc.v:110001.3-110019.6"
+ process $proc$libresoc.v:110001$4256
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:111377.5-111377.29"
+ attribute \src "libresoc.v:110002.5-110002.29"
switch \initial
- attribute \src "libresoc.v:111377.9-111377.17"
+ attribute \src "libresoc.v:110002.9-110002.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0]
end
- attribute \src "libresoc.v:111395.3-111413.6"
- process $proc$libresoc.v:111395$4313
+ attribute \src "libresoc.v:110020.3-110038.6"
+ process $proc$libresoc.v:110020$4257
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:111396.5-111396.29"
+ attribute \src "libresoc.v:110021.5-110021.29"
switch \initial
- attribute \src "libresoc.v:111396.9-111396.17"
+ attribute \src "libresoc.v:110021.9-110021.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:111419.1-112940.10"
+attribute \src "libresoc.v:110044.1-111565.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28"
attribute \generator "nMigen"
module \dec31_dec_sub28
- attribute \src "libresoc.v:112717.3-112753.6"
+ attribute \src "libresoc.v:111342.3-111378.6"
wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:112754.3-112790.6"
+ attribute \src "libresoc.v:111379.3-111415.6"
wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:112273.3-112309.6"
+ attribute \src "libresoc.v:110898.3-110934.6"
wire width 8 $0\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:112421.3-112457.6"
+ attribute \src "libresoc.v:111046.3-111082.6"
wire $0\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:111792.3-111828.6"
+ attribute \src "libresoc.v:110417.3-110453.6"
wire width 3 $0\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:111829.3-111865.6"
+ attribute \src "libresoc.v:110454.3-110490.6"
wire width 3 $0\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:112236.3-112272.6"
+ attribute \src "libresoc.v:110861.3-110897.6"
wire width 2 $0\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:112384.3-112420.6"
+ attribute \src "libresoc.v:111009.3-111045.6"
wire $0\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:112569.3-112605.6"
+ attribute \src "libresoc.v:111194.3-111230.6"
wire width 5 $0\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:111755.3-111791.6"
+ attribute \src "libresoc.v:110380.3-110416.6"
wire width 13 $0\dec31_dec_sub28_function_unit[12:0]
- attribute \src "libresoc.v:112791.3-112827.6"
+ attribute \src "libresoc.v:111416.3-111452.6"
wire width 3 $0\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:112828.3-112864.6"
+ attribute \src "libresoc.v:111453.3-111489.6"
wire width 4 $0\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:112865.3-112901.6"
+ attribute \src "libresoc.v:111490.3-111526.6"
wire width 2 $0\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:112162.3-112198.6"
+ attribute \src "libresoc.v:110787.3-110823.6"
wire width 7 $0\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:112310.3-112346.6"
+ attribute \src "libresoc.v:110935.3-110971.6"
wire $0\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:112347.3-112383.6"
+ attribute \src "libresoc.v:110972.3-111008.6"
wire $0\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:112532.3-112568.6"
+ attribute \src "libresoc.v:111157.3-111193.6"
wire $0\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:112088.3-112124.6"
+ attribute \src "libresoc.v:110713.3-110749.6"
wire width 4 $0\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:112643.3-112679.6"
+ attribute \src "libresoc.v:111268.3-111304.6"
wire $0\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:112902.3-112938.6"
+ attribute \src "libresoc.v:111527.3-111563.6"
wire width 2 $0\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:112199.3-112235.6"
+ attribute \src "libresoc.v:110824.3-110860.6"
wire width 2 $0\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:112495.3-112531.6"
+ attribute \src "libresoc.v:111120.3-111156.6"
wire $0\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:112680.3-112716.6"
+ attribute \src "libresoc.v:111305.3-111341.6"
wire $0\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:112606.3-112642.6"
+ attribute \src "libresoc.v:111231.3-111267.6"
wire $0\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:112458.3-112494.6"
+ attribute \src "libresoc.v:111083.3-111119.6"
wire $0\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:112014.3-112050.6"
+ attribute \src "libresoc.v:110639.3-110675.6"
wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:112051.3-112087.6"
+ attribute \src "libresoc.v:110676.3-110712.6"
wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:111866.3-111902.6"
+ attribute \src "libresoc.v:110491.3-110527.6"
wire width 3 $0\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:111903.3-111939.6"
+ attribute \src "libresoc.v:110528.3-110564.6"
wire width 3 $0\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:111940.3-111976.6"
+ attribute \src "libresoc.v:110565.3-110601.6"
wire width 3 $0\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:111977.3-112013.6"
+ attribute \src "libresoc.v:110602.3-110638.6"
wire width 3 $0\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:112125.3-112161.6"
+ attribute \src "libresoc.v:110750.3-110786.6"
wire width 2 $0\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:111420.7-111420.20"
+ attribute \src "libresoc.v:110045.7-110045.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:112717.3-112753.6"
+ attribute \src "libresoc.v:111342.3-111378.6"
wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:112754.3-112790.6"
+ attribute \src "libresoc.v:111379.3-111415.6"
wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:112273.3-112309.6"
+ attribute \src "libresoc.v:110898.3-110934.6"
wire width 8 $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:112421.3-112457.6"
+ attribute \src "libresoc.v:111046.3-111082.6"
wire $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:111792.3-111828.6"
+ attribute \src "libresoc.v:110417.3-110453.6"
wire width 3 $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:111829.3-111865.6"
+ attribute \src "libresoc.v:110454.3-110490.6"
wire width 3 $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:112236.3-112272.6"
+ attribute \src "libresoc.v:110861.3-110897.6"
wire width 2 $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:112384.3-112420.6"
+ attribute \src "libresoc.v:111009.3-111045.6"
wire $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:112569.3-112605.6"
+ attribute \src "libresoc.v:111194.3-111230.6"
wire width 5 $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:111755.3-111791.6"
+ attribute \src "libresoc.v:110380.3-110416.6"
wire width 13 $1\dec31_dec_sub28_function_unit[12:0]
- attribute \src "libresoc.v:112791.3-112827.6"
+ attribute \src "libresoc.v:111416.3-111452.6"
wire width 3 $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:112828.3-112864.6"
+ attribute \src "libresoc.v:111453.3-111489.6"
wire width 4 $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:112865.3-112901.6"
+ attribute \src "libresoc.v:111490.3-111526.6"
wire width 2 $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:112162.3-112198.6"
+ attribute \src "libresoc.v:110787.3-110823.6"
wire width 7 $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:112310.3-112346.6"
+ attribute \src "libresoc.v:110935.3-110971.6"
wire $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:112347.3-112383.6"
+ attribute \src "libresoc.v:110972.3-111008.6"
wire $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:112532.3-112568.6"
+ attribute \src "libresoc.v:111157.3-111193.6"
wire $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:112088.3-112124.6"
+ attribute \src "libresoc.v:110713.3-110749.6"
wire width 4 $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:112643.3-112679.6"
+ attribute \src "libresoc.v:111268.3-111304.6"
wire $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:112902.3-112938.6"
+ attribute \src "libresoc.v:111527.3-111563.6"
wire width 2 $1\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:112199.3-112235.6"
+ attribute \src "libresoc.v:110824.3-110860.6"
wire width 2 $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:112495.3-112531.6"
+ attribute \src "libresoc.v:111120.3-111156.6"
wire $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:112680.3-112716.6"
+ attribute \src "libresoc.v:111305.3-111341.6"
wire $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:112606.3-112642.6"
+ attribute \src "libresoc.v:111231.3-111267.6"
wire $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:112458.3-112494.6"
+ attribute \src "libresoc.v:111083.3-111119.6"
wire $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:112014.3-112050.6"
+ attribute \src "libresoc.v:110639.3-110675.6"
wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:112051.3-112087.6"
+ attribute \src "libresoc.v:110676.3-110712.6"
wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:111866.3-111902.6"
+ attribute \src "libresoc.v:110491.3-110527.6"
wire width 3 $1\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:111903.3-111939.6"
+ attribute \src "libresoc.v:110528.3-110564.6"
wire width 3 $1\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:111940.3-111976.6"
+ attribute \src "libresoc.v:110565.3-110601.6"
wire width 3 $1\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:111977.3-112013.6"
+ attribute \src "libresoc.v:110602.3-110638.6"
wire width 3 $1\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:112125.3-112161.6"
+ attribute \src "libresoc.v:110750.3-110786.6"
wire width 2 $1\dec31_dec_sub28_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub28_upd
- attribute \src "libresoc.v:111420.7-111420.15"
+ attribute \src "libresoc.v:110045.7-110045.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:111420.7-111420.20"
- process $proc$libresoc.v:111420$4347
+ attribute \src "libresoc.v:110045.7-110045.20"
+ process $proc$libresoc.v:110045$4291
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:111755.3-111791.6"
- process $proc$libresoc.v:111755$4315
+ attribute \src "libresoc.v:110380.3-110416.6"
+ process $proc$libresoc.v:110380$4259
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_function_unit[12:0] $1\dec31_dec_sub28_function_unit[12:0]
- attribute \src "libresoc.v:111756.5-111756.29"
+ attribute \src "libresoc.v:110381.5-110381.29"
switch \initial
- attribute \src "libresoc.v:111756.9-111756.17"
+ attribute \src "libresoc.v:110381.9-110381.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[12:0]
end
- attribute \src "libresoc.v:111792.3-111828.6"
- process $proc$libresoc.v:111792$4316
+ attribute \src "libresoc.v:110417.3-110453.6"
+ process $proc$libresoc.v:110417$4260
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:111793.5-111793.29"
+ attribute \src "libresoc.v:110418.5-110418.29"
switch \initial
- attribute \src "libresoc.v:111793.9-111793.17"
+ attribute \src "libresoc.v:110418.9-110418.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0]
end
- attribute \src "libresoc.v:111829.3-111865.6"
- process $proc$libresoc.v:111829$4317
+ attribute \src "libresoc.v:110454.3-110490.6"
+ process $proc$libresoc.v:110454$4261
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:111830.5-111830.29"
+ attribute \src "libresoc.v:110455.5-110455.29"
switch \initial
- attribute \src "libresoc.v:111830.9-111830.17"
+ attribute \src "libresoc.v:110455.9-110455.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0]
end
- attribute \src "libresoc.v:111866.3-111902.6"
- process $proc$libresoc.v:111866$4318
+ attribute \src "libresoc.v:110491.3-110527.6"
+ process $proc$libresoc.v:110491$4262
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0]
- attribute \src "libresoc.v:111867.5-111867.29"
+ attribute \src "libresoc.v:110492.5-110492.29"
switch \initial
- attribute \src "libresoc.v:111867.9-111867.17"
+ attribute \src "libresoc.v:110492.9-110492.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0]
end
- attribute \src "libresoc.v:111903.3-111939.6"
- process $proc$libresoc.v:111903$4319
+ attribute \src "libresoc.v:110528.3-110564.6"
+ process $proc$libresoc.v:110528$4263
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0]
- attribute \src "libresoc.v:111904.5-111904.29"
+ attribute \src "libresoc.v:110529.5-110529.29"
switch \initial
- attribute \src "libresoc.v:111904.9-111904.17"
+ attribute \src "libresoc.v:110529.9-110529.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0]
end
- attribute \src "libresoc.v:111940.3-111976.6"
- process $proc$libresoc.v:111940$4320
+ attribute \src "libresoc.v:110565.3-110601.6"
+ process $proc$libresoc.v:110565$4264
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0]
- attribute \src "libresoc.v:111941.5-111941.29"
+ attribute \src "libresoc.v:110566.5-110566.29"
switch \initial
- attribute \src "libresoc.v:111941.9-111941.17"
+ attribute \src "libresoc.v:110566.9-110566.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0]
end
- attribute \src "libresoc.v:111977.3-112013.6"
- process $proc$libresoc.v:111977$4321
+ attribute \src "libresoc.v:110602.3-110638.6"
+ process $proc$libresoc.v:110602$4265
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0]
- attribute \src "libresoc.v:111978.5-111978.29"
+ attribute \src "libresoc.v:110603.5-110603.29"
switch \initial
- attribute \src "libresoc.v:111978.9-111978.17"
+ attribute \src "libresoc.v:110603.9-110603.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0]
end
- attribute \src "libresoc.v:112014.3-112050.6"
- process $proc$libresoc.v:112014$4322
+ attribute \src "libresoc.v:110639.3-110675.6"
+ process $proc$libresoc.v:110639$4266
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0]
- attribute \src "libresoc.v:112015.5-112015.29"
+ attribute \src "libresoc.v:110640.5-110640.29"
switch \initial
- attribute \src "libresoc.v:112015.9-112015.17"
+ attribute \src "libresoc.v:110640.9-110640.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:112051.3-112087.6"
- process $proc$libresoc.v:112051$4323
+ attribute \src "libresoc.v:110676.3-110712.6"
+ process $proc$libresoc.v:110676$4267
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0]
- attribute \src "libresoc.v:112052.5-112052.29"
+ attribute \src "libresoc.v:110677.5-110677.29"
switch \initial
- attribute \src "libresoc.v:112052.9-112052.17"
+ attribute \src "libresoc.v:110677.9-110677.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:112088.3-112124.6"
- process $proc$libresoc.v:112088$4324
+ attribute \src "libresoc.v:110713.3-110749.6"
+ process $proc$libresoc.v:110713$4268
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:112089.5-112089.29"
+ attribute \src "libresoc.v:110714.5-110714.29"
switch \initial
- attribute \src "libresoc.v:112089.9-112089.17"
+ attribute \src "libresoc.v:110714.9-110714.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0]
end
- attribute \src "libresoc.v:112125.3-112161.6"
- process $proc$libresoc.v:112125$4325
+ attribute \src "libresoc.v:110750.3-110786.6"
+ process $proc$libresoc.v:110750$4269
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:112126.5-112126.29"
+ attribute \src "libresoc.v:110751.5-110751.29"
switch \initial
- attribute \src "libresoc.v:112126.9-112126.17"
+ attribute \src "libresoc.v:110751.9-110751.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0]
end
- attribute \src "libresoc.v:112162.3-112198.6"
- process $proc$libresoc.v:112162$4326
+ attribute \src "libresoc.v:110787.3-110823.6"
+ process $proc$libresoc.v:110787$4270
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:112163.5-112163.29"
+ attribute \src "libresoc.v:110788.5-110788.29"
switch \initial
- attribute \src "libresoc.v:112163.9-112163.17"
+ attribute \src "libresoc.v:110788.9-110788.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0]
end
- attribute \src "libresoc.v:112199.3-112235.6"
- process $proc$libresoc.v:112199$4327
+ attribute \src "libresoc.v:110824.3-110860.6"
+ process $proc$libresoc.v:110824$4271
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:112200.5-112200.29"
+ attribute \src "libresoc.v:110825.5-110825.29"
switch \initial
- attribute \src "libresoc.v:112200.9-112200.17"
+ attribute \src "libresoc.v:110825.9-110825.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0]
end
- attribute \src "libresoc.v:112236.3-112272.6"
- process $proc$libresoc.v:112236$4328
+ attribute \src "libresoc.v:110861.3-110897.6"
+ process $proc$libresoc.v:110861$4272
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:112237.5-112237.29"
+ attribute \src "libresoc.v:110862.5-110862.29"
switch \initial
- attribute \src "libresoc.v:112237.9-112237.17"
+ attribute \src "libresoc.v:110862.9-110862.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0]
end
- attribute \src "libresoc.v:112273.3-112309.6"
- process $proc$libresoc.v:112273$4329
+ attribute \src "libresoc.v:110898.3-110934.6"
+ process $proc$libresoc.v:110898$4273
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:112274.5-112274.29"
+ attribute \src "libresoc.v:110899.5-110899.29"
switch \initial
- attribute \src "libresoc.v:112274.9-112274.17"
+ attribute \src "libresoc.v:110899.9-110899.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0]
end
- attribute \src "libresoc.v:112310.3-112346.6"
- process $proc$libresoc.v:112310$4330
+ attribute \src "libresoc.v:110935.3-110971.6"
+ process $proc$libresoc.v:110935$4274
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:112311.5-112311.29"
+ attribute \src "libresoc.v:110936.5-110936.29"
switch \initial
- attribute \src "libresoc.v:112311.9-112311.17"
+ attribute \src "libresoc.v:110936.9-110936.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0]
end
- attribute \src "libresoc.v:112347.3-112383.6"
- process $proc$libresoc.v:112347$4331
+ attribute \src "libresoc.v:110972.3-111008.6"
+ process $proc$libresoc.v:110972$4275
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:112348.5-112348.29"
+ attribute \src "libresoc.v:110973.5-110973.29"
switch \initial
- attribute \src "libresoc.v:112348.9-112348.17"
+ attribute \src "libresoc.v:110973.9-110973.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0]
end
- attribute \src "libresoc.v:112384.3-112420.6"
- process $proc$libresoc.v:112384$4332
+ attribute \src "libresoc.v:111009.3-111045.6"
+ process $proc$libresoc.v:111009$4276
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:112385.5-112385.29"
+ attribute \src "libresoc.v:111010.5-111010.29"
switch \initial
- attribute \src "libresoc.v:112385.9-112385.17"
+ attribute \src "libresoc.v:111010.9-111010.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0]
end
- attribute \src "libresoc.v:112421.3-112457.6"
- process $proc$libresoc.v:112421$4333
+ attribute \src "libresoc.v:111046.3-111082.6"
+ process $proc$libresoc.v:111046$4277
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:112422.5-112422.29"
+ attribute \src "libresoc.v:111047.5-111047.29"
switch \initial
- attribute \src "libresoc.v:112422.9-112422.17"
+ attribute \src "libresoc.v:111047.9-111047.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0]
end
- attribute \src "libresoc.v:112458.3-112494.6"
- process $proc$libresoc.v:112458$4334
+ attribute \src "libresoc.v:111083.3-111119.6"
+ process $proc$libresoc.v:111083$4278
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:112459.5-112459.29"
+ attribute \src "libresoc.v:111084.5-111084.29"
switch \initial
- attribute \src "libresoc.v:112459.9-112459.17"
+ attribute \src "libresoc.v:111084.9-111084.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0]
end
- attribute \src "libresoc.v:112495.3-112531.6"
- process $proc$libresoc.v:112495$4335
+ attribute \src "libresoc.v:111120.3-111156.6"
+ process $proc$libresoc.v:111120$4279
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:112496.5-112496.29"
+ attribute \src "libresoc.v:111121.5-111121.29"
switch \initial
- attribute \src "libresoc.v:112496.9-112496.17"
+ attribute \src "libresoc.v:111121.9-111121.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0]
end
- attribute \src "libresoc.v:112532.3-112568.6"
- process $proc$libresoc.v:112532$4336
+ attribute \src "libresoc.v:111157.3-111193.6"
+ process $proc$libresoc.v:111157$4280
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:112533.5-112533.29"
+ attribute \src "libresoc.v:111158.5-111158.29"
switch \initial
- attribute \src "libresoc.v:112533.9-112533.17"
+ attribute \src "libresoc.v:111158.9-111158.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0]
end
- attribute \src "libresoc.v:112569.3-112605.6"
- process $proc$libresoc.v:112569$4337
+ attribute \src "libresoc.v:111194.3-111230.6"
+ process $proc$libresoc.v:111194$4281
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:112570.5-112570.29"
+ attribute \src "libresoc.v:111195.5-111195.29"
switch \initial
- attribute \src "libresoc.v:112570.9-112570.17"
+ attribute \src "libresoc.v:111195.9-111195.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0]
end
- attribute \src "libresoc.v:112606.3-112642.6"
- process $proc$libresoc.v:112606$4338
+ attribute \src "libresoc.v:111231.3-111267.6"
+ process $proc$libresoc.v:111231$4282
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:112607.5-112607.29"
+ attribute \src "libresoc.v:111232.5-111232.29"
switch \initial
- attribute \src "libresoc.v:112607.9-112607.17"
+ attribute \src "libresoc.v:111232.9-111232.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0]
end
- attribute \src "libresoc.v:112643.3-112679.6"
- process $proc$libresoc.v:112643$4339
+ attribute \src "libresoc.v:111268.3-111304.6"
+ process $proc$libresoc.v:111268$4283
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:112644.5-112644.29"
+ attribute \src "libresoc.v:111269.5-111269.29"
switch \initial
- attribute \src "libresoc.v:112644.9-112644.17"
+ attribute \src "libresoc.v:111269.9-111269.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0]
end
- attribute \src "libresoc.v:112680.3-112716.6"
- process $proc$libresoc.v:112680$4340
+ attribute \src "libresoc.v:111305.3-111341.6"
+ process $proc$libresoc.v:111305$4284
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:112681.5-112681.29"
+ attribute \src "libresoc.v:111306.5-111306.29"
switch \initial
- attribute \src "libresoc.v:112681.9-112681.17"
+ attribute \src "libresoc.v:111306.9-111306.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:112717.3-112753.6"
- process $proc$libresoc.v:112717$4341
+ attribute \src "libresoc.v:111342.3-111378.6"
+ process $proc$libresoc.v:111342$4285
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0]
- attribute \src "libresoc.v:112718.5-112718.29"
+ attribute \src "libresoc.v:111343.5-111343.29"
switch \initial
- attribute \src "libresoc.v:112718.9-112718.17"
+ attribute \src "libresoc.v:111343.9-111343.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0]
end
- attribute \src "libresoc.v:112754.3-112790.6"
- process $proc$libresoc.v:112754$4342
+ attribute \src "libresoc.v:111379.3-111415.6"
+ process $proc$libresoc.v:111379$4286
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0]
- attribute \src "libresoc.v:112755.5-112755.29"
+ attribute \src "libresoc.v:111380.5-111380.29"
switch \initial
- attribute \src "libresoc.v:112755.9-112755.17"
+ attribute \src "libresoc.v:111380.9-111380.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:112791.3-112827.6"
- process $proc$libresoc.v:112791$4343
+ attribute \src "libresoc.v:111416.3-111452.6"
+ process $proc$libresoc.v:111416$4287
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:112792.5-112792.29"
+ attribute \src "libresoc.v:111417.5-111417.29"
switch \initial
- attribute \src "libresoc.v:112792.9-112792.17"
+ attribute \src "libresoc.v:111417.9-111417.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0]
end
- attribute \src "libresoc.v:112828.3-112864.6"
- process $proc$libresoc.v:112828$4344
+ attribute \src "libresoc.v:111453.3-111489.6"
+ process $proc$libresoc.v:111453$4288
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:112829.5-112829.29"
+ attribute \src "libresoc.v:111454.5-111454.29"
switch \initial
- attribute \src "libresoc.v:112829.9-112829.17"
+ attribute \src "libresoc.v:111454.9-111454.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0]
end
- attribute \src "libresoc.v:112865.3-112901.6"
- process $proc$libresoc.v:112865$4345
+ attribute \src "libresoc.v:111490.3-111526.6"
+ process $proc$libresoc.v:111490$4289
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:112866.5-112866.29"
+ attribute \src "libresoc.v:111491.5-111491.29"
switch \initial
- attribute \src "libresoc.v:112866.9-112866.17"
+ attribute \src "libresoc.v:111491.9-111491.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0]
end
- attribute \src "libresoc.v:112902.3-112938.6"
- process $proc$libresoc.v:112902$4346
+ attribute \src "libresoc.v:111527.3-111563.6"
+ process $proc$libresoc.v:111527$4290
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:112903.5-112903.29"
+ attribute \src "libresoc.v:111528.5-111528.29"
switch \initial
- attribute \src "libresoc.v:112903.9-112903.17"
+ attribute \src "libresoc.v:111528.9-111528.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:112944.1-113697.10"
+attribute \src "libresoc.v:111569.1-112322.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4"
attribute \generator "nMigen"
module \dec31_dec_sub4
- attribute \src "libresoc.v:113618.3-113630.6"
+ attribute \src "libresoc.v:112243.3-112255.6"
wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:113631.3-113643.6"
+ attribute \src "libresoc.v:112256.3-112268.6"
wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:113462.3-113474.6"
+ attribute \src "libresoc.v:112087.3-112099.6"
wire width 8 $0\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:113514.3-113526.6"
+ attribute \src "libresoc.v:112139.3-112151.6"
wire $0\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:113293.3-113305.6"
+ attribute \src "libresoc.v:111918.3-111930.6"
wire width 3 $0\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:113306.3-113318.6"
+ attribute \src "libresoc.v:111931.3-111943.6"
wire width 3 $0\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:113449.3-113461.6"
+ attribute \src "libresoc.v:112074.3-112086.6"
wire width 2 $0\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:113501.3-113513.6"
+ attribute \src "libresoc.v:112126.3-112138.6"
wire $0\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:113566.3-113578.6"
+ attribute \src "libresoc.v:112191.3-112203.6"
wire width 5 $0\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:113280.3-113292.6"
+ attribute \src "libresoc.v:111905.3-111917.6"
wire width 13 $0\dec31_dec_sub4_function_unit[12:0]
- attribute \src "libresoc.v:113644.3-113656.6"
+ attribute \src "libresoc.v:112269.3-112281.6"
wire width 3 $0\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:113657.3-113669.6"
+ attribute \src "libresoc.v:112282.3-112294.6"
wire width 4 $0\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:113670.3-113682.6"
+ attribute \src "libresoc.v:112295.3-112307.6"
wire width 2 $0\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:113423.3-113435.6"
+ attribute \src "libresoc.v:112048.3-112060.6"
wire width 7 $0\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:113475.3-113487.6"
+ attribute \src "libresoc.v:112100.3-112112.6"
wire $0\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:113488.3-113500.6"
+ attribute \src "libresoc.v:112113.3-112125.6"
wire $0\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:113553.3-113565.6"
+ attribute \src "libresoc.v:112178.3-112190.6"
wire $0\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:113397.3-113409.6"
+ attribute \src "libresoc.v:112022.3-112034.6"
wire width 4 $0\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:113592.3-113604.6"
+ attribute \src "libresoc.v:112217.3-112229.6"
wire $0\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:113683.3-113695.6"
+ attribute \src "libresoc.v:112308.3-112320.6"
wire width 2 $0\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:113436.3-113448.6"
+ attribute \src "libresoc.v:112061.3-112073.6"
wire width 2 $0\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:113540.3-113552.6"
+ attribute \src "libresoc.v:112165.3-112177.6"
wire $0\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:113605.3-113617.6"
+ attribute \src "libresoc.v:112230.3-112242.6"
wire $0\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:113579.3-113591.6"
+ attribute \src "libresoc.v:112204.3-112216.6"
wire $0\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:113527.3-113539.6"
+ attribute \src "libresoc.v:112152.3-112164.6"
wire $0\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:113371.3-113383.6"
+ attribute \src "libresoc.v:111996.3-112008.6"
wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:113384.3-113396.6"
+ attribute \src "libresoc.v:112009.3-112021.6"
wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:113319.3-113331.6"
+ attribute \src "libresoc.v:111944.3-111956.6"
wire width 3 $0\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:113332.3-113344.6"
+ attribute \src "libresoc.v:111957.3-111969.6"
wire width 3 $0\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:113345.3-113357.6"
+ attribute \src "libresoc.v:111970.3-111982.6"
wire width 3 $0\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:113358.3-113370.6"
+ attribute \src "libresoc.v:111983.3-111995.6"
wire width 3 $0\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:113410.3-113422.6"
+ attribute \src "libresoc.v:112035.3-112047.6"
wire width 2 $0\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:112945.7-112945.20"
+ attribute \src "libresoc.v:111570.7-111570.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:113618.3-113630.6"
+ attribute \src "libresoc.v:112243.3-112255.6"
wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:113631.3-113643.6"
+ attribute \src "libresoc.v:112256.3-112268.6"
wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:113462.3-113474.6"
+ attribute \src "libresoc.v:112087.3-112099.6"
wire width 8 $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:113514.3-113526.6"
+ attribute \src "libresoc.v:112139.3-112151.6"
wire $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:113293.3-113305.6"
+ attribute \src "libresoc.v:111918.3-111930.6"
wire width 3 $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:113306.3-113318.6"
+ attribute \src "libresoc.v:111931.3-111943.6"
wire width 3 $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:113449.3-113461.6"
+ attribute \src "libresoc.v:112074.3-112086.6"
wire width 2 $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:113501.3-113513.6"
+ attribute \src "libresoc.v:112126.3-112138.6"
wire $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:113566.3-113578.6"
+ attribute \src "libresoc.v:112191.3-112203.6"
wire width 5 $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:113280.3-113292.6"
+ attribute \src "libresoc.v:111905.3-111917.6"
wire width 13 $1\dec31_dec_sub4_function_unit[12:0]
- attribute \src "libresoc.v:113644.3-113656.6"
+ attribute \src "libresoc.v:112269.3-112281.6"
wire width 3 $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:113657.3-113669.6"
+ attribute \src "libresoc.v:112282.3-112294.6"
wire width 4 $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:113670.3-113682.6"
+ attribute \src "libresoc.v:112295.3-112307.6"
wire width 2 $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:113423.3-113435.6"
+ attribute \src "libresoc.v:112048.3-112060.6"
wire width 7 $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:113475.3-113487.6"
+ attribute \src "libresoc.v:112100.3-112112.6"
wire $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:113488.3-113500.6"
+ attribute \src "libresoc.v:112113.3-112125.6"
wire $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:113553.3-113565.6"
+ attribute \src "libresoc.v:112178.3-112190.6"
wire $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:113397.3-113409.6"
+ attribute \src "libresoc.v:112022.3-112034.6"
wire width 4 $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:113592.3-113604.6"
+ attribute \src "libresoc.v:112217.3-112229.6"
wire $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:113683.3-113695.6"
+ attribute \src "libresoc.v:112308.3-112320.6"
wire width 2 $1\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:113436.3-113448.6"
+ attribute \src "libresoc.v:112061.3-112073.6"
wire width 2 $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:113540.3-113552.6"
+ attribute \src "libresoc.v:112165.3-112177.6"
wire $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:113605.3-113617.6"
+ attribute \src "libresoc.v:112230.3-112242.6"
wire $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:113579.3-113591.6"
+ attribute \src "libresoc.v:112204.3-112216.6"
wire $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:113527.3-113539.6"
+ attribute \src "libresoc.v:112152.3-112164.6"
wire $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:113371.3-113383.6"
+ attribute \src "libresoc.v:111996.3-112008.6"
wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:113384.3-113396.6"
+ attribute \src "libresoc.v:112009.3-112021.6"
wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:113319.3-113331.6"
+ attribute \src "libresoc.v:111944.3-111956.6"
wire width 3 $1\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:113332.3-113344.6"
+ attribute \src "libresoc.v:111957.3-111969.6"
wire width 3 $1\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:113345.3-113357.6"
+ attribute \src "libresoc.v:111970.3-111982.6"
wire width 3 $1\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:113358.3-113370.6"
+ attribute \src "libresoc.v:111983.3-111995.6"
wire width 3 $1\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:113410.3-113422.6"
+ attribute \src "libresoc.v:112035.3-112047.6"
wire width 2 $1\dec31_dec_sub4_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub4_upd
- attribute \src "libresoc.v:112945.7-112945.15"
+ attribute \src "libresoc.v:111570.7-111570.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:112945.7-112945.20"
- process $proc$libresoc.v:112945$4380
+ attribute \src "libresoc.v:111570.7-111570.20"
+ process $proc$libresoc.v:111570$4324
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:113280.3-113292.6"
- process $proc$libresoc.v:113280$4348
+ attribute \src "libresoc.v:111905.3-111917.6"
+ process $proc$libresoc.v:111905$4292
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_function_unit[12:0] $1\dec31_dec_sub4_function_unit[12:0]
- attribute \src "libresoc.v:113281.5-113281.29"
+ attribute \src "libresoc.v:111906.5-111906.29"
switch \initial
- attribute \src "libresoc.v:113281.9-113281.17"
+ attribute \src "libresoc.v:111906.9-111906.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[12:0]
end
- attribute \src "libresoc.v:113293.3-113305.6"
- process $proc$libresoc.v:113293$4349
+ attribute \src "libresoc.v:111918.3-111930.6"
+ process $proc$libresoc.v:111918$4293
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:113294.5-113294.29"
+ attribute \src "libresoc.v:111919.5-111919.29"
switch \initial
- attribute \src "libresoc.v:113294.9-113294.17"
+ attribute \src "libresoc.v:111919.9-111919.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0]
end
- attribute \src "libresoc.v:113306.3-113318.6"
- process $proc$libresoc.v:113306$4350
+ attribute \src "libresoc.v:111931.3-111943.6"
+ process $proc$libresoc.v:111931$4294
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:113307.5-113307.29"
+ attribute \src "libresoc.v:111932.5-111932.29"
switch \initial
- attribute \src "libresoc.v:113307.9-113307.17"
+ attribute \src "libresoc.v:111932.9-111932.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0]
end
- attribute \src "libresoc.v:113319.3-113331.6"
- process $proc$libresoc.v:113319$4351
+ attribute \src "libresoc.v:111944.3-111956.6"
+ process $proc$libresoc.v:111944$4295
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0]
- attribute \src "libresoc.v:113320.5-113320.29"
+ attribute \src "libresoc.v:111945.5-111945.29"
switch \initial
- attribute \src "libresoc.v:113320.9-113320.17"
+ attribute \src "libresoc.v:111945.9-111945.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0]
end
- attribute \src "libresoc.v:113332.3-113344.6"
- process $proc$libresoc.v:113332$4352
+ attribute \src "libresoc.v:111957.3-111969.6"
+ process $proc$libresoc.v:111957$4296
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0]
- attribute \src "libresoc.v:113333.5-113333.29"
+ attribute \src "libresoc.v:111958.5-111958.29"
switch \initial
- attribute \src "libresoc.v:113333.9-113333.17"
+ attribute \src "libresoc.v:111958.9-111958.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0]
end
- attribute \src "libresoc.v:113345.3-113357.6"
- process $proc$libresoc.v:113345$4353
+ attribute \src "libresoc.v:111970.3-111982.6"
+ process $proc$libresoc.v:111970$4297
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0]
- attribute \src "libresoc.v:113346.5-113346.29"
+ attribute \src "libresoc.v:111971.5-111971.29"
switch \initial
- attribute \src "libresoc.v:113346.9-113346.17"
+ attribute \src "libresoc.v:111971.9-111971.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0]
end
- attribute \src "libresoc.v:113358.3-113370.6"
- process $proc$libresoc.v:113358$4354
+ attribute \src "libresoc.v:111983.3-111995.6"
+ process $proc$libresoc.v:111983$4298
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0]
- attribute \src "libresoc.v:113359.5-113359.29"
+ attribute \src "libresoc.v:111984.5-111984.29"
switch \initial
- attribute \src "libresoc.v:113359.9-113359.17"
+ attribute \src "libresoc.v:111984.9-111984.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0]
end
- attribute \src "libresoc.v:113371.3-113383.6"
- process $proc$libresoc.v:113371$4355
+ attribute \src "libresoc.v:111996.3-112008.6"
+ process $proc$libresoc.v:111996$4299
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0]
- attribute \src "libresoc.v:113372.5-113372.29"
+ attribute \src "libresoc.v:111997.5-111997.29"
switch \initial
- attribute \src "libresoc.v:113372.9-113372.17"
+ attribute \src "libresoc.v:111997.9-111997.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:113384.3-113396.6"
- process $proc$libresoc.v:113384$4356
+ attribute \src "libresoc.v:112009.3-112021.6"
+ process $proc$libresoc.v:112009$4300
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0]
- attribute \src "libresoc.v:113385.5-113385.29"
+ attribute \src "libresoc.v:112010.5-112010.29"
switch \initial
- attribute \src "libresoc.v:113385.9-113385.17"
+ attribute \src "libresoc.v:112010.9-112010.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:113397.3-113409.6"
- process $proc$libresoc.v:113397$4357
+ attribute \src "libresoc.v:112022.3-112034.6"
+ process $proc$libresoc.v:112022$4301
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:113398.5-113398.29"
+ attribute \src "libresoc.v:112023.5-112023.29"
switch \initial
- attribute \src "libresoc.v:113398.9-113398.17"
+ attribute \src "libresoc.v:112023.9-112023.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0]
end
- attribute \src "libresoc.v:113410.3-113422.6"
- process $proc$libresoc.v:113410$4358
+ attribute \src "libresoc.v:112035.3-112047.6"
+ process $proc$libresoc.v:112035$4302
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:113411.5-113411.29"
+ attribute \src "libresoc.v:112036.5-112036.29"
switch \initial
- attribute \src "libresoc.v:113411.9-113411.17"
+ attribute \src "libresoc.v:112036.9-112036.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0]
end
- attribute \src "libresoc.v:113423.3-113435.6"
- process $proc$libresoc.v:113423$4359
+ attribute \src "libresoc.v:112048.3-112060.6"
+ process $proc$libresoc.v:112048$4303
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:113424.5-113424.29"
+ attribute \src "libresoc.v:112049.5-112049.29"
switch \initial
- attribute \src "libresoc.v:113424.9-113424.17"
+ attribute \src "libresoc.v:112049.9-112049.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0]
end
- attribute \src "libresoc.v:113436.3-113448.6"
- process $proc$libresoc.v:113436$4360
+ attribute \src "libresoc.v:112061.3-112073.6"
+ process $proc$libresoc.v:112061$4304
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:113437.5-113437.29"
+ attribute \src "libresoc.v:112062.5-112062.29"
switch \initial
- attribute \src "libresoc.v:113437.9-113437.17"
+ attribute \src "libresoc.v:112062.9-112062.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0]
end
- attribute \src "libresoc.v:113449.3-113461.6"
- process $proc$libresoc.v:113449$4361
+ attribute \src "libresoc.v:112074.3-112086.6"
+ process $proc$libresoc.v:112074$4305
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:113450.5-113450.29"
+ attribute \src "libresoc.v:112075.5-112075.29"
switch \initial
- attribute \src "libresoc.v:113450.9-113450.17"
+ attribute \src "libresoc.v:112075.9-112075.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0]
end
- attribute \src "libresoc.v:113462.3-113474.6"
- process $proc$libresoc.v:113462$4362
+ attribute \src "libresoc.v:112087.3-112099.6"
+ process $proc$libresoc.v:112087$4306
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:113463.5-113463.29"
+ attribute \src "libresoc.v:112088.5-112088.29"
switch \initial
- attribute \src "libresoc.v:113463.9-113463.17"
+ attribute \src "libresoc.v:112088.9-112088.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0]
end
- attribute \src "libresoc.v:113475.3-113487.6"
- process $proc$libresoc.v:113475$4363
+ attribute \src "libresoc.v:112100.3-112112.6"
+ process $proc$libresoc.v:112100$4307
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:113476.5-113476.29"
+ attribute \src "libresoc.v:112101.5-112101.29"
switch \initial
- attribute \src "libresoc.v:113476.9-113476.17"
+ attribute \src "libresoc.v:112101.9-112101.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0]
end
- attribute \src "libresoc.v:113488.3-113500.6"
- process $proc$libresoc.v:113488$4364
+ attribute \src "libresoc.v:112113.3-112125.6"
+ process $proc$libresoc.v:112113$4308
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:113489.5-113489.29"
+ attribute \src "libresoc.v:112114.5-112114.29"
switch \initial
- attribute \src "libresoc.v:113489.9-113489.17"
+ attribute \src "libresoc.v:112114.9-112114.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0]
end
- attribute \src "libresoc.v:113501.3-113513.6"
- process $proc$libresoc.v:113501$4365
+ attribute \src "libresoc.v:112126.3-112138.6"
+ process $proc$libresoc.v:112126$4309
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:113502.5-113502.29"
+ attribute \src "libresoc.v:112127.5-112127.29"
switch \initial
- attribute \src "libresoc.v:113502.9-113502.17"
+ attribute \src "libresoc.v:112127.9-112127.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0]
end
- attribute \src "libresoc.v:113514.3-113526.6"
- process $proc$libresoc.v:113514$4366
+ attribute \src "libresoc.v:112139.3-112151.6"
+ process $proc$libresoc.v:112139$4310
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:113515.5-113515.29"
+ attribute \src "libresoc.v:112140.5-112140.29"
switch \initial
- attribute \src "libresoc.v:113515.9-113515.17"
+ attribute \src "libresoc.v:112140.9-112140.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0]
end
- attribute \src "libresoc.v:113527.3-113539.6"
- process $proc$libresoc.v:113527$4367
+ attribute \src "libresoc.v:112152.3-112164.6"
+ process $proc$libresoc.v:112152$4311
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:113528.5-113528.29"
+ attribute \src "libresoc.v:112153.5-112153.29"
switch \initial
- attribute \src "libresoc.v:113528.9-113528.17"
+ attribute \src "libresoc.v:112153.9-112153.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0]
end
- attribute \src "libresoc.v:113540.3-113552.6"
- process $proc$libresoc.v:113540$4368
+ attribute \src "libresoc.v:112165.3-112177.6"
+ process $proc$libresoc.v:112165$4312
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:113541.5-113541.29"
+ attribute \src "libresoc.v:112166.5-112166.29"
switch \initial
- attribute \src "libresoc.v:113541.9-113541.17"
+ attribute \src "libresoc.v:112166.9-112166.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0]
end
- attribute \src "libresoc.v:113553.3-113565.6"
- process $proc$libresoc.v:113553$4369
+ attribute \src "libresoc.v:112178.3-112190.6"
+ process $proc$libresoc.v:112178$4313
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:113554.5-113554.29"
+ attribute \src "libresoc.v:112179.5-112179.29"
switch \initial
- attribute \src "libresoc.v:113554.9-113554.17"
+ attribute \src "libresoc.v:112179.9-112179.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0]
end
- attribute \src "libresoc.v:113566.3-113578.6"
- process $proc$libresoc.v:113566$4370
+ attribute \src "libresoc.v:112191.3-112203.6"
+ process $proc$libresoc.v:112191$4314
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:113567.5-113567.29"
+ attribute \src "libresoc.v:112192.5-112192.29"
switch \initial
- attribute \src "libresoc.v:113567.9-113567.17"
+ attribute \src "libresoc.v:112192.9-112192.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0]
end
- attribute \src "libresoc.v:113579.3-113591.6"
- process $proc$libresoc.v:113579$4371
+ attribute \src "libresoc.v:112204.3-112216.6"
+ process $proc$libresoc.v:112204$4315
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:113580.5-113580.29"
+ attribute \src "libresoc.v:112205.5-112205.29"
switch \initial
- attribute \src "libresoc.v:113580.9-113580.17"
+ attribute \src "libresoc.v:112205.9-112205.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0]
end
- attribute \src "libresoc.v:113592.3-113604.6"
- process $proc$libresoc.v:113592$4372
+ attribute \src "libresoc.v:112217.3-112229.6"
+ process $proc$libresoc.v:112217$4316
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:113593.5-113593.29"
+ attribute \src "libresoc.v:112218.5-112218.29"
switch \initial
- attribute \src "libresoc.v:113593.9-113593.17"
+ attribute \src "libresoc.v:112218.9-112218.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0]
end
- attribute \src "libresoc.v:113605.3-113617.6"
- process $proc$libresoc.v:113605$4373
+ attribute \src "libresoc.v:112230.3-112242.6"
+ process $proc$libresoc.v:112230$4317
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:113606.5-113606.29"
+ attribute \src "libresoc.v:112231.5-112231.29"
switch \initial
- attribute \src "libresoc.v:113606.9-113606.17"
+ attribute \src "libresoc.v:112231.9-112231.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:113618.3-113630.6"
- process $proc$libresoc.v:113618$4374
+ attribute \src "libresoc.v:112243.3-112255.6"
+ process $proc$libresoc.v:112243$4318
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0]
- attribute \src "libresoc.v:113619.5-113619.29"
+ attribute \src "libresoc.v:112244.5-112244.29"
switch \initial
- attribute \src "libresoc.v:113619.9-113619.17"
+ attribute \src "libresoc.v:112244.9-112244.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0]
end
- attribute \src "libresoc.v:113631.3-113643.6"
- process $proc$libresoc.v:113631$4375
+ attribute \src "libresoc.v:112256.3-112268.6"
+ process $proc$libresoc.v:112256$4319
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0]
- attribute \src "libresoc.v:113632.5-113632.29"
+ attribute \src "libresoc.v:112257.5-112257.29"
switch \initial
- attribute \src "libresoc.v:113632.9-113632.17"
+ attribute \src "libresoc.v:112257.9-112257.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:113644.3-113656.6"
- process $proc$libresoc.v:113644$4376
+ attribute \src "libresoc.v:112269.3-112281.6"
+ process $proc$libresoc.v:112269$4320
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:113645.5-113645.29"
+ attribute \src "libresoc.v:112270.5-112270.29"
switch \initial
- attribute \src "libresoc.v:113645.9-113645.17"
+ attribute \src "libresoc.v:112270.9-112270.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0]
end
- attribute \src "libresoc.v:113657.3-113669.6"
- process $proc$libresoc.v:113657$4377
+ attribute \src "libresoc.v:112282.3-112294.6"
+ process $proc$libresoc.v:112282$4321
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:113658.5-113658.29"
+ attribute \src "libresoc.v:112283.5-112283.29"
switch \initial
- attribute \src "libresoc.v:113658.9-113658.17"
+ attribute \src "libresoc.v:112283.9-112283.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0]
end
- attribute \src "libresoc.v:113670.3-113682.6"
- process $proc$libresoc.v:113670$4378
+ attribute \src "libresoc.v:112295.3-112307.6"
+ process $proc$libresoc.v:112295$4322
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:113671.5-113671.29"
+ attribute \src "libresoc.v:112296.5-112296.29"
switch \initial
- attribute \src "libresoc.v:113671.9-113671.17"
+ attribute \src "libresoc.v:112296.9-112296.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0]
end
- attribute \src "libresoc.v:113683.3-113695.6"
- process $proc$libresoc.v:113683$4379
+ attribute \src "libresoc.v:112308.3-112320.6"
+ process $proc$libresoc.v:112308$4323
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:113684.5-113684.29"
+ attribute \src "libresoc.v:112309.5-112309.29"
switch \initial
- attribute \src "libresoc.v:113684.9-113684.17"
+ attribute \src "libresoc.v:112309.9-112309.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:113701.1-115414.10"
+attribute \src "libresoc.v:112326.1-114039.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8"
attribute \generator "nMigen"
module \dec31_dec_sub8
- attribute \src "libresoc.v:115155.3-115197.6"
+ attribute \src "libresoc.v:113780.3-113822.6"
wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:115198.3-115240.6"
+ attribute \src "libresoc.v:113823.3-113865.6"
wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:114639.3-114681.6"
+ attribute \src "libresoc.v:113264.3-113306.6"
wire width 8 $0\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:114811.3-114853.6"
+ attribute \src "libresoc.v:113436.3-113478.6"
wire $0\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:114080.3-114122.6"
+ attribute \src "libresoc.v:112705.3-112747.6"
wire width 3 $0\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:114123.3-114165.6"
+ attribute \src "libresoc.v:112748.3-112790.6"
wire width 3 $0\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:114596.3-114638.6"
+ attribute \src "libresoc.v:113221.3-113263.6"
wire width 2 $0\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:114768.3-114810.6"
+ attribute \src "libresoc.v:113393.3-113435.6"
wire $0\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:114983.3-115025.6"
+ attribute \src "libresoc.v:113608.3-113650.6"
wire width 5 $0\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:114037.3-114079.6"
+ attribute \src "libresoc.v:112662.3-112704.6"
wire width 13 $0\dec31_dec_sub8_function_unit[12:0]
- attribute \src "libresoc.v:115241.3-115283.6"
+ attribute \src "libresoc.v:113866.3-113908.6"
wire width 3 $0\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:115284.3-115326.6"
+ attribute \src "libresoc.v:113909.3-113951.6"
wire width 4 $0\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:115327.3-115369.6"
+ attribute \src "libresoc.v:113952.3-113994.6"
wire width 2 $0\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:114510.3-114552.6"
+ attribute \src "libresoc.v:113135.3-113177.6"
wire width 7 $0\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:114682.3-114724.6"
+ attribute \src "libresoc.v:113307.3-113349.6"
wire $0\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:114725.3-114767.6"
+ attribute \src "libresoc.v:113350.3-113392.6"
wire $0\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:114940.3-114982.6"
+ attribute \src "libresoc.v:113565.3-113607.6"
wire $0\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:114424.3-114466.6"
+ attribute \src "libresoc.v:113049.3-113091.6"
wire width 4 $0\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:115069.3-115111.6"
+ attribute \src "libresoc.v:113694.3-113736.6"
wire $0\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:115370.3-115412.6"
+ attribute \src "libresoc.v:113995.3-114037.6"
wire width 2 $0\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:114553.3-114595.6"
+ attribute \src "libresoc.v:113178.3-113220.6"
wire width 2 $0\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:114897.3-114939.6"
+ attribute \src "libresoc.v:113522.3-113564.6"
wire $0\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:115112.3-115154.6"
+ attribute \src "libresoc.v:113737.3-113779.6"
wire $0\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:115026.3-115068.6"
+ attribute \src "libresoc.v:113651.3-113693.6"
wire $0\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:114854.3-114896.6"
+ attribute \src "libresoc.v:113479.3-113521.6"
wire $0\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:114338.3-114380.6"
+ attribute \src "libresoc.v:112963.3-113005.6"
wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:114381.3-114423.6"
+ attribute \src "libresoc.v:113006.3-113048.6"
wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:114166.3-114208.6"
+ attribute \src "libresoc.v:112791.3-112833.6"
wire width 3 $0\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:114209.3-114251.6"
+ attribute \src "libresoc.v:112834.3-112876.6"
wire width 3 $0\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:114252.3-114294.6"
+ attribute \src "libresoc.v:112877.3-112919.6"
wire width 3 $0\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:114295.3-114337.6"
+ attribute \src "libresoc.v:112920.3-112962.6"
wire width 3 $0\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:114467.3-114509.6"
+ attribute \src "libresoc.v:113092.3-113134.6"
wire width 2 $0\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:113702.7-113702.20"
+ attribute \src "libresoc.v:112327.7-112327.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:115155.3-115197.6"
+ attribute \src "libresoc.v:113780.3-113822.6"
wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:115198.3-115240.6"
+ attribute \src "libresoc.v:113823.3-113865.6"
wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:114639.3-114681.6"
+ attribute \src "libresoc.v:113264.3-113306.6"
wire width 8 $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:114811.3-114853.6"
+ attribute \src "libresoc.v:113436.3-113478.6"
wire $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:114080.3-114122.6"
+ attribute \src "libresoc.v:112705.3-112747.6"
wire width 3 $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:114123.3-114165.6"
+ attribute \src "libresoc.v:112748.3-112790.6"
wire width 3 $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:114596.3-114638.6"
+ attribute \src "libresoc.v:113221.3-113263.6"
wire width 2 $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:114768.3-114810.6"
+ attribute \src "libresoc.v:113393.3-113435.6"
wire $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:114983.3-115025.6"
+ attribute \src "libresoc.v:113608.3-113650.6"
wire width 5 $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:114037.3-114079.6"
+ attribute \src "libresoc.v:112662.3-112704.6"
wire width 13 $1\dec31_dec_sub8_function_unit[12:0]
- attribute \src "libresoc.v:115241.3-115283.6"
+ attribute \src "libresoc.v:113866.3-113908.6"
wire width 3 $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:115284.3-115326.6"
+ attribute \src "libresoc.v:113909.3-113951.6"
wire width 4 $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:115327.3-115369.6"
+ attribute \src "libresoc.v:113952.3-113994.6"
wire width 2 $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:114510.3-114552.6"
+ attribute \src "libresoc.v:113135.3-113177.6"
wire width 7 $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:114682.3-114724.6"
+ attribute \src "libresoc.v:113307.3-113349.6"
wire $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:114725.3-114767.6"
+ attribute \src "libresoc.v:113350.3-113392.6"
wire $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:114940.3-114982.6"
+ attribute \src "libresoc.v:113565.3-113607.6"
wire $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:114424.3-114466.6"
+ attribute \src "libresoc.v:113049.3-113091.6"
wire width 4 $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:115069.3-115111.6"
+ attribute \src "libresoc.v:113694.3-113736.6"
wire $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:115370.3-115412.6"
+ attribute \src "libresoc.v:113995.3-114037.6"
wire width 2 $1\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:114553.3-114595.6"
+ attribute \src "libresoc.v:113178.3-113220.6"
wire width 2 $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:114897.3-114939.6"
+ attribute \src "libresoc.v:113522.3-113564.6"
wire $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:115112.3-115154.6"
+ attribute \src "libresoc.v:113737.3-113779.6"
wire $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:115026.3-115068.6"
+ attribute \src "libresoc.v:113651.3-113693.6"
wire $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:114854.3-114896.6"
+ attribute \src "libresoc.v:113479.3-113521.6"
wire $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:114338.3-114380.6"
+ attribute \src "libresoc.v:112963.3-113005.6"
wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:114381.3-114423.6"
+ attribute \src "libresoc.v:113006.3-113048.6"
wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:114166.3-114208.6"
+ attribute \src "libresoc.v:112791.3-112833.6"
wire width 3 $1\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:114209.3-114251.6"
+ attribute \src "libresoc.v:112834.3-112876.6"
wire width 3 $1\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:114252.3-114294.6"
+ attribute \src "libresoc.v:112877.3-112919.6"
wire width 3 $1\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:114295.3-114337.6"
+ attribute \src "libresoc.v:112920.3-112962.6"
wire width 3 $1\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:114467.3-114509.6"
+ attribute \src "libresoc.v:113092.3-113134.6"
wire width 2 $1\dec31_dec_sub8_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub8_upd
- attribute \src "libresoc.v:113702.7-113702.15"
+ attribute \src "libresoc.v:112327.7-112327.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:113702.7-113702.20"
- process $proc$libresoc.v:113702$4413
+ attribute \src "libresoc.v:112327.7-112327.20"
+ process $proc$libresoc.v:112327$4357
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:114037.3-114079.6"
- process $proc$libresoc.v:114037$4381
+ attribute \src "libresoc.v:112662.3-112704.6"
+ process $proc$libresoc.v:112662$4325
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_function_unit[12:0] $1\dec31_dec_sub8_function_unit[12:0]
- attribute \src "libresoc.v:114038.5-114038.29"
+ attribute \src "libresoc.v:112663.5-112663.29"
switch \initial
- attribute \src "libresoc.v:114038.9-114038.17"
+ attribute \src "libresoc.v:112663.9-112663.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[12:0]
end
- attribute \src "libresoc.v:114080.3-114122.6"
- process $proc$libresoc.v:114080$4382
+ attribute \src "libresoc.v:112705.3-112747.6"
+ process $proc$libresoc.v:112705$4326
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:114081.5-114081.29"
+ attribute \src "libresoc.v:112706.5-112706.29"
switch \initial
- attribute \src "libresoc.v:114081.9-114081.17"
+ attribute \src "libresoc.v:112706.9-112706.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0]
end
- attribute \src "libresoc.v:114123.3-114165.6"
- process $proc$libresoc.v:114123$4383
+ attribute \src "libresoc.v:112748.3-112790.6"
+ process $proc$libresoc.v:112748$4327
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:114124.5-114124.29"
+ attribute \src "libresoc.v:112749.5-112749.29"
switch \initial
- attribute \src "libresoc.v:114124.9-114124.17"
+ attribute \src "libresoc.v:112749.9-112749.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0]
end
- attribute \src "libresoc.v:114166.3-114208.6"
- process $proc$libresoc.v:114166$4384
+ attribute \src "libresoc.v:112791.3-112833.6"
+ process $proc$libresoc.v:112791$4328
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0]
- attribute \src "libresoc.v:114167.5-114167.29"
+ attribute \src "libresoc.v:112792.5-112792.29"
switch \initial
- attribute \src "libresoc.v:114167.9-114167.17"
+ attribute \src "libresoc.v:112792.9-112792.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0]
end
- attribute \src "libresoc.v:114209.3-114251.6"
- process $proc$libresoc.v:114209$4385
+ attribute \src "libresoc.v:112834.3-112876.6"
+ process $proc$libresoc.v:112834$4329
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0]
- attribute \src "libresoc.v:114210.5-114210.29"
+ attribute \src "libresoc.v:112835.5-112835.29"
switch \initial
- attribute \src "libresoc.v:114210.9-114210.17"
+ attribute \src "libresoc.v:112835.9-112835.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0]
end
- attribute \src "libresoc.v:114252.3-114294.6"
- process $proc$libresoc.v:114252$4386
+ attribute \src "libresoc.v:112877.3-112919.6"
+ process $proc$libresoc.v:112877$4330
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0]
- attribute \src "libresoc.v:114253.5-114253.29"
+ attribute \src "libresoc.v:112878.5-112878.29"
switch \initial
- attribute \src "libresoc.v:114253.9-114253.17"
+ attribute \src "libresoc.v:112878.9-112878.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0]
end
- attribute \src "libresoc.v:114295.3-114337.6"
- process $proc$libresoc.v:114295$4387
+ attribute \src "libresoc.v:112920.3-112962.6"
+ process $proc$libresoc.v:112920$4331
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0]
- attribute \src "libresoc.v:114296.5-114296.29"
+ attribute \src "libresoc.v:112921.5-112921.29"
switch \initial
- attribute \src "libresoc.v:114296.9-114296.17"
+ attribute \src "libresoc.v:112921.9-112921.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0]
end
- attribute \src "libresoc.v:114338.3-114380.6"
- process $proc$libresoc.v:114338$4388
+ attribute \src "libresoc.v:112963.3-113005.6"
+ process $proc$libresoc.v:112963$4332
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0]
- attribute \src "libresoc.v:114339.5-114339.29"
+ attribute \src "libresoc.v:112964.5-112964.29"
switch \initial
- attribute \src "libresoc.v:114339.9-114339.17"
+ attribute \src "libresoc.v:112964.9-112964.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:114381.3-114423.6"
- process $proc$libresoc.v:114381$4389
+ attribute \src "libresoc.v:113006.3-113048.6"
+ process $proc$libresoc.v:113006$4333
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0]
- attribute \src "libresoc.v:114382.5-114382.29"
+ attribute \src "libresoc.v:113007.5-113007.29"
switch \initial
- attribute \src "libresoc.v:114382.9-114382.17"
+ attribute \src "libresoc.v:113007.9-113007.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:114424.3-114466.6"
- process $proc$libresoc.v:114424$4390
+ attribute \src "libresoc.v:113049.3-113091.6"
+ process $proc$libresoc.v:113049$4334
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:114425.5-114425.29"
+ attribute \src "libresoc.v:113050.5-113050.29"
switch \initial
- attribute \src "libresoc.v:114425.9-114425.17"
+ attribute \src "libresoc.v:113050.9-113050.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0]
end
- attribute \src "libresoc.v:114467.3-114509.6"
- process $proc$libresoc.v:114467$4391
+ attribute \src "libresoc.v:113092.3-113134.6"
+ process $proc$libresoc.v:113092$4335
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:114468.5-114468.29"
+ attribute \src "libresoc.v:113093.5-113093.29"
switch \initial
- attribute \src "libresoc.v:114468.9-114468.17"
+ attribute \src "libresoc.v:113093.9-113093.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0]
end
- attribute \src "libresoc.v:114510.3-114552.6"
- process $proc$libresoc.v:114510$4392
+ attribute \src "libresoc.v:113135.3-113177.6"
+ process $proc$libresoc.v:113135$4336
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:114511.5-114511.29"
+ attribute \src "libresoc.v:113136.5-113136.29"
switch \initial
- attribute \src "libresoc.v:114511.9-114511.17"
+ attribute \src "libresoc.v:113136.9-113136.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0]
end
- attribute \src "libresoc.v:114553.3-114595.6"
- process $proc$libresoc.v:114553$4393
+ attribute \src "libresoc.v:113178.3-113220.6"
+ process $proc$libresoc.v:113178$4337
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:114554.5-114554.29"
+ attribute \src "libresoc.v:113179.5-113179.29"
switch \initial
- attribute \src "libresoc.v:114554.9-114554.17"
+ attribute \src "libresoc.v:113179.9-113179.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0]
end
- attribute \src "libresoc.v:114596.3-114638.6"
- process $proc$libresoc.v:114596$4394
+ attribute \src "libresoc.v:113221.3-113263.6"
+ process $proc$libresoc.v:113221$4338
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:114597.5-114597.29"
+ attribute \src "libresoc.v:113222.5-113222.29"
switch \initial
- attribute \src "libresoc.v:114597.9-114597.17"
+ attribute \src "libresoc.v:113222.9-113222.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0]
end
- attribute \src "libresoc.v:114639.3-114681.6"
- process $proc$libresoc.v:114639$4395
+ attribute \src "libresoc.v:113264.3-113306.6"
+ process $proc$libresoc.v:113264$4339
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:114640.5-114640.29"
+ attribute \src "libresoc.v:113265.5-113265.29"
switch \initial
- attribute \src "libresoc.v:114640.9-114640.17"
+ attribute \src "libresoc.v:113265.9-113265.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0]
end
- attribute \src "libresoc.v:114682.3-114724.6"
- process $proc$libresoc.v:114682$4396
+ attribute \src "libresoc.v:113307.3-113349.6"
+ process $proc$libresoc.v:113307$4340
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:114683.5-114683.29"
+ attribute \src "libresoc.v:113308.5-113308.29"
switch \initial
- attribute \src "libresoc.v:114683.9-114683.17"
+ attribute \src "libresoc.v:113308.9-113308.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0]
end
- attribute \src "libresoc.v:114725.3-114767.6"
- process $proc$libresoc.v:114725$4397
+ attribute \src "libresoc.v:113350.3-113392.6"
+ process $proc$libresoc.v:113350$4341
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:114726.5-114726.29"
+ attribute \src "libresoc.v:113351.5-113351.29"
switch \initial
- attribute \src "libresoc.v:114726.9-114726.17"
+ attribute \src "libresoc.v:113351.9-113351.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0]
end
- attribute \src "libresoc.v:114768.3-114810.6"
- process $proc$libresoc.v:114768$4398
+ attribute \src "libresoc.v:113393.3-113435.6"
+ process $proc$libresoc.v:113393$4342
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:114769.5-114769.29"
+ attribute \src "libresoc.v:113394.5-113394.29"
switch \initial
- attribute \src "libresoc.v:114769.9-114769.17"
+ attribute \src "libresoc.v:113394.9-113394.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0]
end
- attribute \src "libresoc.v:114811.3-114853.6"
- process $proc$libresoc.v:114811$4399
+ attribute \src "libresoc.v:113436.3-113478.6"
+ process $proc$libresoc.v:113436$4343
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:114812.5-114812.29"
+ attribute \src "libresoc.v:113437.5-113437.29"
switch \initial
- attribute \src "libresoc.v:114812.9-114812.17"
+ attribute \src "libresoc.v:113437.9-113437.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0]
end
- attribute \src "libresoc.v:114854.3-114896.6"
- process $proc$libresoc.v:114854$4400
+ attribute \src "libresoc.v:113479.3-113521.6"
+ process $proc$libresoc.v:113479$4344
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:114855.5-114855.29"
+ attribute \src "libresoc.v:113480.5-113480.29"
switch \initial
- attribute \src "libresoc.v:114855.9-114855.17"
+ attribute \src "libresoc.v:113480.9-113480.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0]
end
- attribute \src "libresoc.v:114897.3-114939.6"
- process $proc$libresoc.v:114897$4401
+ attribute \src "libresoc.v:113522.3-113564.6"
+ process $proc$libresoc.v:113522$4345
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:114898.5-114898.29"
+ attribute \src "libresoc.v:113523.5-113523.29"
switch \initial
- attribute \src "libresoc.v:114898.9-114898.17"
+ attribute \src "libresoc.v:113523.9-113523.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0]
end
- attribute \src "libresoc.v:114940.3-114982.6"
- process $proc$libresoc.v:114940$4402
+ attribute \src "libresoc.v:113565.3-113607.6"
+ process $proc$libresoc.v:113565$4346
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:114941.5-114941.29"
+ attribute \src "libresoc.v:113566.5-113566.29"
switch \initial
- attribute \src "libresoc.v:114941.9-114941.17"
+ attribute \src "libresoc.v:113566.9-113566.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0]
end
- attribute \src "libresoc.v:114983.3-115025.6"
- process $proc$libresoc.v:114983$4403
+ attribute \src "libresoc.v:113608.3-113650.6"
+ process $proc$libresoc.v:113608$4347
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:114984.5-114984.29"
+ attribute \src "libresoc.v:113609.5-113609.29"
switch \initial
- attribute \src "libresoc.v:114984.9-114984.17"
+ attribute \src "libresoc.v:113609.9-113609.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0]
end
- attribute \src "libresoc.v:115026.3-115068.6"
- process $proc$libresoc.v:115026$4404
+ attribute \src "libresoc.v:113651.3-113693.6"
+ process $proc$libresoc.v:113651$4348
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:115027.5-115027.29"
+ attribute \src "libresoc.v:113652.5-113652.29"
switch \initial
- attribute \src "libresoc.v:115027.9-115027.17"
+ attribute \src "libresoc.v:113652.9-113652.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0]
end
- attribute \src "libresoc.v:115069.3-115111.6"
- process $proc$libresoc.v:115069$4405
+ attribute \src "libresoc.v:113694.3-113736.6"
+ process $proc$libresoc.v:113694$4349
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:115070.5-115070.29"
+ attribute \src "libresoc.v:113695.5-113695.29"
switch \initial
- attribute \src "libresoc.v:115070.9-115070.17"
+ attribute \src "libresoc.v:113695.9-113695.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0]
end
- attribute \src "libresoc.v:115112.3-115154.6"
- process $proc$libresoc.v:115112$4406
+ attribute \src "libresoc.v:113737.3-113779.6"
+ process $proc$libresoc.v:113737$4350
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:115113.5-115113.29"
+ attribute \src "libresoc.v:113738.5-113738.29"
switch \initial
- attribute \src "libresoc.v:115113.9-115113.17"
+ attribute \src "libresoc.v:113738.9-113738.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:115155.3-115197.6"
- process $proc$libresoc.v:115155$4407
+ attribute \src "libresoc.v:113780.3-113822.6"
+ process $proc$libresoc.v:113780$4351
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0]
- attribute \src "libresoc.v:115156.5-115156.29"
+ attribute \src "libresoc.v:113781.5-113781.29"
switch \initial
- attribute \src "libresoc.v:115156.9-115156.17"
+ attribute \src "libresoc.v:113781.9-113781.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0]
end
- attribute \src "libresoc.v:115198.3-115240.6"
- process $proc$libresoc.v:115198$4408
+ attribute \src "libresoc.v:113823.3-113865.6"
+ process $proc$libresoc.v:113823$4352
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0]
- attribute \src "libresoc.v:115199.5-115199.29"
+ attribute \src "libresoc.v:113824.5-113824.29"
switch \initial
- attribute \src "libresoc.v:115199.9-115199.17"
+ attribute \src "libresoc.v:113824.9-113824.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:115241.3-115283.6"
- process $proc$libresoc.v:115241$4409
+ attribute \src "libresoc.v:113866.3-113908.6"
+ process $proc$libresoc.v:113866$4353
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:115242.5-115242.29"
+ attribute \src "libresoc.v:113867.5-113867.29"
switch \initial
- attribute \src "libresoc.v:115242.9-115242.17"
+ attribute \src "libresoc.v:113867.9-113867.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0]
end
- attribute \src "libresoc.v:115284.3-115326.6"
- process $proc$libresoc.v:115284$4410
+ attribute \src "libresoc.v:113909.3-113951.6"
+ process $proc$libresoc.v:113909$4354
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:115285.5-115285.29"
+ attribute \src "libresoc.v:113910.5-113910.29"
switch \initial
- attribute \src "libresoc.v:115285.9-115285.17"
+ attribute \src "libresoc.v:113910.9-113910.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0]
end
- attribute \src "libresoc.v:115327.3-115369.6"
- process $proc$libresoc.v:115327$4411
+ attribute \src "libresoc.v:113952.3-113994.6"
+ process $proc$libresoc.v:113952$4355
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:115328.5-115328.29"
+ attribute \src "libresoc.v:113953.5-113953.29"
switch \initial
- attribute \src "libresoc.v:115328.9-115328.17"
+ attribute \src "libresoc.v:113953.9-113953.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0]
end
- attribute \src "libresoc.v:115370.3-115412.6"
- process $proc$libresoc.v:115370$4412
+ attribute \src "libresoc.v:113995.3-114037.6"
+ process $proc$libresoc.v:113995$4356
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:115371.5-115371.29"
+ attribute \src "libresoc.v:113996.5-113996.29"
switch \initial
- attribute \src "libresoc.v:115371.9-115371.17"
+ attribute \src "libresoc.v:113996.9-113996.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:115418.1-117515.10"
+attribute \src "libresoc.v:114043.1-116140.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9"
attribute \generator "nMigen"
module \dec31_dec_sub9
- attribute \src "libresoc.v:117184.3-117238.6"
+ attribute \src "libresoc.v:115809.3-115863.6"
wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:117239.3-117293.6"
+ attribute \src "libresoc.v:115864.3-115918.6"
wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:116524.3-116578.6"
+ attribute \src "libresoc.v:115149.3-115203.6"
wire width 8 $0\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:116744.3-116798.6"
+ attribute \src "libresoc.v:115369.3-115423.6"
wire $0\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:115809.3-115863.6"
+ attribute \src "libresoc.v:114434.3-114488.6"
wire width 3 $0\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:115864.3-115918.6"
+ attribute \src "libresoc.v:114489.3-114543.6"
wire width 3 $0\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:116469.3-116523.6"
+ attribute \src "libresoc.v:115094.3-115148.6"
wire width 2 $0\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:116689.3-116743.6"
+ attribute \src "libresoc.v:115314.3-115368.6"
wire $0\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:116964.3-117018.6"
+ attribute \src "libresoc.v:115589.3-115643.6"
wire width 5 $0\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:115754.3-115808.6"
+ attribute \src "libresoc.v:114379.3-114433.6"
wire width 13 $0\dec31_dec_sub9_function_unit[12:0]
- attribute \src "libresoc.v:117294.3-117348.6"
+ attribute \src "libresoc.v:115919.3-115973.6"
wire width 3 $0\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:117349.3-117403.6"
+ attribute \src "libresoc.v:115974.3-116028.6"
wire width 4 $0\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:117404.3-117458.6"
+ attribute \src "libresoc.v:116029.3-116083.6"
wire width 2 $0\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:116359.3-116413.6"
+ attribute \src "libresoc.v:114984.3-115038.6"
wire width 7 $0\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:116579.3-116633.6"
+ attribute \src "libresoc.v:115204.3-115258.6"
wire $0\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:116634.3-116688.6"
+ attribute \src "libresoc.v:115259.3-115313.6"
wire $0\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:116909.3-116963.6"
+ attribute \src "libresoc.v:115534.3-115588.6"
wire $0\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:116249.3-116303.6"
+ attribute \src "libresoc.v:114874.3-114928.6"
wire width 4 $0\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:117074.3-117128.6"
+ attribute \src "libresoc.v:115699.3-115753.6"
wire $0\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:117459.3-117513.6"
+ attribute \src "libresoc.v:116084.3-116138.6"
wire width 2 $0\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:116414.3-116468.6"
+ attribute \src "libresoc.v:115039.3-115093.6"
wire width 2 $0\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:116854.3-116908.6"
+ attribute \src "libresoc.v:115479.3-115533.6"
wire $0\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:117129.3-117183.6"
+ attribute \src "libresoc.v:115754.3-115808.6"
wire $0\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:117019.3-117073.6"
+ attribute \src "libresoc.v:115644.3-115698.6"
wire $0\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:116799.3-116853.6"
+ attribute \src "libresoc.v:115424.3-115478.6"
wire $0\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:116139.3-116193.6"
+ attribute \src "libresoc.v:114764.3-114818.6"
wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:116194.3-116248.6"
+ attribute \src "libresoc.v:114819.3-114873.6"
wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:115919.3-115973.6"
+ attribute \src "libresoc.v:114544.3-114598.6"
wire width 3 $0\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:115974.3-116028.6"
+ attribute \src "libresoc.v:114599.3-114653.6"
wire width 3 $0\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:116029.3-116083.6"
+ attribute \src "libresoc.v:114654.3-114708.6"
wire width 3 $0\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:116084.3-116138.6"
+ attribute \src "libresoc.v:114709.3-114763.6"
wire width 3 $0\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:116304.3-116358.6"
+ attribute \src "libresoc.v:114929.3-114983.6"
wire width 2 $0\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:115419.7-115419.20"
+ attribute \src "libresoc.v:114044.7-114044.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:117184.3-117238.6"
+ attribute \src "libresoc.v:115809.3-115863.6"
wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:117239.3-117293.6"
+ attribute \src "libresoc.v:115864.3-115918.6"
wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:116524.3-116578.6"
+ attribute \src "libresoc.v:115149.3-115203.6"
wire width 8 $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:116744.3-116798.6"
+ attribute \src "libresoc.v:115369.3-115423.6"
wire $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:115809.3-115863.6"
+ attribute \src "libresoc.v:114434.3-114488.6"
wire width 3 $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:115864.3-115918.6"
+ attribute \src "libresoc.v:114489.3-114543.6"
wire width 3 $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:116469.3-116523.6"
+ attribute \src "libresoc.v:115094.3-115148.6"
wire width 2 $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:116689.3-116743.6"
+ attribute \src "libresoc.v:115314.3-115368.6"
wire $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:116964.3-117018.6"
+ attribute \src "libresoc.v:115589.3-115643.6"
wire width 5 $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:115754.3-115808.6"
+ attribute \src "libresoc.v:114379.3-114433.6"
wire width 13 $1\dec31_dec_sub9_function_unit[12:0]
- attribute \src "libresoc.v:117294.3-117348.6"
+ attribute \src "libresoc.v:115919.3-115973.6"
wire width 3 $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:117349.3-117403.6"
+ attribute \src "libresoc.v:115974.3-116028.6"
wire width 4 $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:117404.3-117458.6"
+ attribute \src "libresoc.v:116029.3-116083.6"
wire width 2 $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:116359.3-116413.6"
+ attribute \src "libresoc.v:114984.3-115038.6"
wire width 7 $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:116579.3-116633.6"
+ attribute \src "libresoc.v:115204.3-115258.6"
wire $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:116634.3-116688.6"
+ attribute \src "libresoc.v:115259.3-115313.6"
wire $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:116909.3-116963.6"
+ attribute \src "libresoc.v:115534.3-115588.6"
wire $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:116249.3-116303.6"
+ attribute \src "libresoc.v:114874.3-114928.6"
wire width 4 $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:117074.3-117128.6"
+ attribute \src "libresoc.v:115699.3-115753.6"
wire $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:117459.3-117513.6"
+ attribute \src "libresoc.v:116084.3-116138.6"
wire width 2 $1\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:116414.3-116468.6"
+ attribute \src "libresoc.v:115039.3-115093.6"
wire width 2 $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:116854.3-116908.6"
+ attribute \src "libresoc.v:115479.3-115533.6"
wire $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:117129.3-117183.6"
+ attribute \src "libresoc.v:115754.3-115808.6"
wire $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:117019.3-117073.6"
+ attribute \src "libresoc.v:115644.3-115698.6"
wire $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:116799.3-116853.6"
+ attribute \src "libresoc.v:115424.3-115478.6"
wire $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:116139.3-116193.6"
+ attribute \src "libresoc.v:114764.3-114818.6"
wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:116194.3-116248.6"
+ attribute \src "libresoc.v:114819.3-114873.6"
wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:115919.3-115973.6"
+ attribute \src "libresoc.v:114544.3-114598.6"
wire width 3 $1\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:115974.3-116028.6"
+ attribute \src "libresoc.v:114599.3-114653.6"
wire width 3 $1\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:116029.3-116083.6"
+ attribute \src "libresoc.v:114654.3-114708.6"
wire width 3 $1\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:116084.3-116138.6"
+ attribute \src "libresoc.v:114709.3-114763.6"
wire width 3 $1\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:116304.3-116358.6"
+ attribute \src "libresoc.v:114929.3-114983.6"
wire width 2 $1\dec31_dec_sub9_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec31_dec_sub9_upd
- attribute \src "libresoc.v:115419.7-115419.15"
+ attribute \src "libresoc.v:114044.7-114044.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:115419.7-115419.20"
- process $proc$libresoc.v:115419$4446
+ attribute \src "libresoc.v:114044.7-114044.20"
+ process $proc$libresoc.v:114044$4390
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:115754.3-115808.6"
- process $proc$libresoc.v:115754$4414
+ attribute \src "libresoc.v:114379.3-114433.6"
+ process $proc$libresoc.v:114379$4358
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_function_unit[12:0] $1\dec31_dec_sub9_function_unit[12:0]
- attribute \src "libresoc.v:115755.5-115755.29"
+ attribute \src "libresoc.v:114380.5-114380.29"
switch \initial
- attribute \src "libresoc.v:115755.9-115755.17"
+ attribute \src "libresoc.v:114380.9-114380.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[12:0]
end
- attribute \src "libresoc.v:115809.3-115863.6"
- process $proc$libresoc.v:115809$4415
+ attribute \src "libresoc.v:114434.3-114488.6"
+ process $proc$libresoc.v:114434$4359
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:115810.5-115810.29"
+ attribute \src "libresoc.v:114435.5-114435.29"
switch \initial
- attribute \src "libresoc.v:115810.9-115810.17"
+ attribute \src "libresoc.v:114435.9-114435.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0]
end
- attribute \src "libresoc.v:115864.3-115918.6"
- process $proc$libresoc.v:115864$4416
+ attribute \src "libresoc.v:114489.3-114543.6"
+ process $proc$libresoc.v:114489$4360
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:115865.5-115865.29"
+ attribute \src "libresoc.v:114490.5-114490.29"
switch \initial
- attribute \src "libresoc.v:115865.9-115865.17"
+ attribute \src "libresoc.v:114490.9-114490.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0]
end
- attribute \src "libresoc.v:115919.3-115973.6"
- process $proc$libresoc.v:115919$4417
+ attribute \src "libresoc.v:114544.3-114598.6"
+ process $proc$libresoc.v:114544$4361
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0]
- attribute \src "libresoc.v:115920.5-115920.29"
+ attribute \src "libresoc.v:114545.5-114545.29"
switch \initial
- attribute \src "libresoc.v:115920.9-115920.17"
+ attribute \src "libresoc.v:114545.9-114545.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0]
end
- attribute \src "libresoc.v:115974.3-116028.6"
- process $proc$libresoc.v:115974$4418
+ attribute \src "libresoc.v:114599.3-114653.6"
+ process $proc$libresoc.v:114599$4362
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0]
- attribute \src "libresoc.v:115975.5-115975.29"
+ attribute \src "libresoc.v:114600.5-114600.29"
switch \initial
- attribute \src "libresoc.v:115975.9-115975.17"
+ attribute \src "libresoc.v:114600.9-114600.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0]
end
- attribute \src "libresoc.v:116029.3-116083.6"
- process $proc$libresoc.v:116029$4419
+ attribute \src "libresoc.v:114654.3-114708.6"
+ process $proc$libresoc.v:114654$4363
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0]
- attribute \src "libresoc.v:116030.5-116030.29"
+ attribute \src "libresoc.v:114655.5-114655.29"
switch \initial
- attribute \src "libresoc.v:116030.9-116030.17"
+ attribute \src "libresoc.v:114655.9-114655.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0]
end
- attribute \src "libresoc.v:116084.3-116138.6"
- process $proc$libresoc.v:116084$4420
+ attribute \src "libresoc.v:114709.3-114763.6"
+ process $proc$libresoc.v:114709$4364
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0]
- attribute \src "libresoc.v:116085.5-116085.29"
+ attribute \src "libresoc.v:114710.5-114710.29"
switch \initial
- attribute \src "libresoc.v:116085.9-116085.17"
+ attribute \src "libresoc.v:114710.9-114710.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0]
end
- attribute \src "libresoc.v:116139.3-116193.6"
- process $proc$libresoc.v:116139$4421
+ attribute \src "libresoc.v:114764.3-114818.6"
+ process $proc$libresoc.v:114764$4365
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0]
- attribute \src "libresoc.v:116140.5-116140.29"
+ attribute \src "libresoc.v:114765.5-114765.29"
switch \initial
- attribute \src "libresoc.v:116140.9-116140.17"
+ attribute \src "libresoc.v:114765.9-114765.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:116194.3-116248.6"
- process $proc$libresoc.v:116194$4422
+ attribute \src "libresoc.v:114819.3-114873.6"
+ process $proc$libresoc.v:114819$4366
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0]
- attribute \src "libresoc.v:116195.5-116195.29"
+ attribute \src "libresoc.v:114820.5-114820.29"
switch \initial
- attribute \src "libresoc.v:116195.9-116195.17"
+ attribute \src "libresoc.v:114820.9-114820.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:116249.3-116303.6"
- process $proc$libresoc.v:116249$4423
+ attribute \src "libresoc.v:114874.3-114928.6"
+ process $proc$libresoc.v:114874$4367
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:116250.5-116250.29"
+ attribute \src "libresoc.v:114875.5-114875.29"
switch \initial
- attribute \src "libresoc.v:116250.9-116250.17"
+ attribute \src "libresoc.v:114875.9-114875.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0]
end
- attribute \src "libresoc.v:116304.3-116358.6"
- process $proc$libresoc.v:116304$4424
+ attribute \src "libresoc.v:114929.3-114983.6"
+ process $proc$libresoc.v:114929$4368
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:116305.5-116305.29"
+ attribute \src "libresoc.v:114930.5-114930.29"
switch \initial
- attribute \src "libresoc.v:116305.9-116305.17"
+ attribute \src "libresoc.v:114930.9-114930.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0]
end
- attribute \src "libresoc.v:116359.3-116413.6"
- process $proc$libresoc.v:116359$4425
+ attribute \src "libresoc.v:114984.3-115038.6"
+ process $proc$libresoc.v:114984$4369
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:116360.5-116360.29"
+ attribute \src "libresoc.v:114985.5-114985.29"
switch \initial
- attribute \src "libresoc.v:116360.9-116360.17"
+ attribute \src "libresoc.v:114985.9-114985.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0]
end
- attribute \src "libresoc.v:116414.3-116468.6"
- process $proc$libresoc.v:116414$4426
+ attribute \src "libresoc.v:115039.3-115093.6"
+ process $proc$libresoc.v:115039$4370
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:116415.5-116415.29"
+ attribute \src "libresoc.v:115040.5-115040.29"
switch \initial
- attribute \src "libresoc.v:116415.9-116415.17"
+ attribute \src "libresoc.v:115040.9-115040.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0]
end
- attribute \src "libresoc.v:116469.3-116523.6"
- process $proc$libresoc.v:116469$4427
+ attribute \src "libresoc.v:115094.3-115148.6"
+ process $proc$libresoc.v:115094$4371
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:116470.5-116470.29"
+ attribute \src "libresoc.v:115095.5-115095.29"
switch \initial
- attribute \src "libresoc.v:116470.9-116470.17"
+ attribute \src "libresoc.v:115095.9-115095.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0]
end
- attribute \src "libresoc.v:116524.3-116578.6"
- process $proc$libresoc.v:116524$4428
+ attribute \src "libresoc.v:115149.3-115203.6"
+ process $proc$libresoc.v:115149$4372
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:116525.5-116525.29"
+ attribute \src "libresoc.v:115150.5-115150.29"
switch \initial
- attribute \src "libresoc.v:116525.9-116525.17"
+ attribute \src "libresoc.v:115150.9-115150.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0]
end
- attribute \src "libresoc.v:116579.3-116633.6"
- process $proc$libresoc.v:116579$4429
+ attribute \src "libresoc.v:115204.3-115258.6"
+ process $proc$libresoc.v:115204$4373
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:116580.5-116580.29"
+ attribute \src "libresoc.v:115205.5-115205.29"
switch \initial
- attribute \src "libresoc.v:116580.9-116580.17"
+ attribute \src "libresoc.v:115205.9-115205.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0]
end
- attribute \src "libresoc.v:116634.3-116688.6"
- process $proc$libresoc.v:116634$4430
+ attribute \src "libresoc.v:115259.3-115313.6"
+ process $proc$libresoc.v:115259$4374
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:116635.5-116635.29"
+ attribute \src "libresoc.v:115260.5-115260.29"
switch \initial
- attribute \src "libresoc.v:116635.9-116635.17"
+ attribute \src "libresoc.v:115260.9-115260.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0]
end
- attribute \src "libresoc.v:116689.3-116743.6"
- process $proc$libresoc.v:116689$4431
+ attribute \src "libresoc.v:115314.3-115368.6"
+ process $proc$libresoc.v:115314$4375
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:116690.5-116690.29"
+ attribute \src "libresoc.v:115315.5-115315.29"
switch \initial
- attribute \src "libresoc.v:116690.9-116690.17"
+ attribute \src "libresoc.v:115315.9-115315.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0]
end
- attribute \src "libresoc.v:116744.3-116798.6"
- process $proc$libresoc.v:116744$4432
+ attribute \src "libresoc.v:115369.3-115423.6"
+ process $proc$libresoc.v:115369$4376
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:116745.5-116745.29"
+ attribute \src "libresoc.v:115370.5-115370.29"
switch \initial
- attribute \src "libresoc.v:116745.9-116745.17"
+ attribute \src "libresoc.v:115370.9-115370.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0]
end
- attribute \src "libresoc.v:116799.3-116853.6"
- process $proc$libresoc.v:116799$4433
+ attribute \src "libresoc.v:115424.3-115478.6"
+ process $proc$libresoc.v:115424$4377
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:116800.5-116800.29"
+ attribute \src "libresoc.v:115425.5-115425.29"
switch \initial
- attribute \src "libresoc.v:116800.9-116800.17"
+ attribute \src "libresoc.v:115425.9-115425.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0]
end
- attribute \src "libresoc.v:116854.3-116908.6"
- process $proc$libresoc.v:116854$4434
+ attribute \src "libresoc.v:115479.3-115533.6"
+ process $proc$libresoc.v:115479$4378
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:116855.5-116855.29"
+ attribute \src "libresoc.v:115480.5-115480.29"
switch \initial
- attribute \src "libresoc.v:116855.9-116855.17"
+ attribute \src "libresoc.v:115480.9-115480.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0]
end
- attribute \src "libresoc.v:116909.3-116963.6"
- process $proc$libresoc.v:116909$4435
+ attribute \src "libresoc.v:115534.3-115588.6"
+ process $proc$libresoc.v:115534$4379
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:116910.5-116910.29"
+ attribute \src "libresoc.v:115535.5-115535.29"
switch \initial
- attribute \src "libresoc.v:116910.9-116910.17"
+ attribute \src "libresoc.v:115535.9-115535.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0]
end
- attribute \src "libresoc.v:116964.3-117018.6"
- process $proc$libresoc.v:116964$4436
+ attribute \src "libresoc.v:115589.3-115643.6"
+ process $proc$libresoc.v:115589$4380
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:116965.5-116965.29"
+ attribute \src "libresoc.v:115590.5-115590.29"
switch \initial
- attribute \src "libresoc.v:116965.9-116965.17"
+ attribute \src "libresoc.v:115590.9-115590.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0]
end
- attribute \src "libresoc.v:117019.3-117073.6"
- process $proc$libresoc.v:117019$4437
+ attribute \src "libresoc.v:115644.3-115698.6"
+ process $proc$libresoc.v:115644$4381
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:117020.5-117020.29"
+ attribute \src "libresoc.v:115645.5-115645.29"
switch \initial
- attribute \src "libresoc.v:117020.9-117020.17"
+ attribute \src "libresoc.v:115645.9-115645.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0]
end
- attribute \src "libresoc.v:117074.3-117128.6"
- process $proc$libresoc.v:117074$4438
+ attribute \src "libresoc.v:115699.3-115753.6"
+ process $proc$libresoc.v:115699$4382
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:117075.5-117075.29"
+ attribute \src "libresoc.v:115700.5-115700.29"
switch \initial
- attribute \src "libresoc.v:117075.9-117075.17"
+ attribute \src "libresoc.v:115700.9-115700.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0]
end
- attribute \src "libresoc.v:117129.3-117183.6"
- process $proc$libresoc.v:117129$4439
+ attribute \src "libresoc.v:115754.3-115808.6"
+ process $proc$libresoc.v:115754$4383
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:117130.5-117130.29"
+ attribute \src "libresoc.v:115755.5-115755.29"
switch \initial
- attribute \src "libresoc.v:117130.9-117130.17"
+ attribute \src "libresoc.v:115755.9-115755.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:117184.3-117238.6"
- process $proc$libresoc.v:117184$4440
+ attribute \src "libresoc.v:115809.3-115863.6"
+ process $proc$libresoc.v:115809$4384
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0]
- attribute \src "libresoc.v:117185.5-117185.29"
+ attribute \src "libresoc.v:115810.5-115810.29"
switch \initial
- attribute \src "libresoc.v:117185.9-117185.17"
+ attribute \src "libresoc.v:115810.9-115810.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0]
end
- attribute \src "libresoc.v:117239.3-117293.6"
- process $proc$libresoc.v:117239$4441
+ attribute \src "libresoc.v:115864.3-115918.6"
+ process $proc$libresoc.v:115864$4385
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0]
- attribute \src "libresoc.v:117240.5-117240.29"
+ attribute \src "libresoc.v:115865.5-115865.29"
switch \initial
- attribute \src "libresoc.v:117240.9-117240.17"
+ attribute \src "libresoc.v:115865.9-115865.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:117294.3-117348.6"
- process $proc$libresoc.v:117294$4442
+ attribute \src "libresoc.v:115919.3-115973.6"
+ process $proc$libresoc.v:115919$4386
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:117295.5-117295.29"
+ attribute \src "libresoc.v:115920.5-115920.29"
switch \initial
- attribute \src "libresoc.v:117295.9-117295.17"
+ attribute \src "libresoc.v:115920.9-115920.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0]
end
- attribute \src "libresoc.v:117349.3-117403.6"
- process $proc$libresoc.v:117349$4443
+ attribute \src "libresoc.v:115974.3-116028.6"
+ process $proc$libresoc.v:115974$4387
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:117350.5-117350.29"
+ attribute \src "libresoc.v:115975.5-115975.29"
switch \initial
- attribute \src "libresoc.v:117350.9-117350.17"
+ attribute \src "libresoc.v:115975.9-115975.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0]
end
- attribute \src "libresoc.v:117404.3-117458.6"
- process $proc$libresoc.v:117404$4444
+ attribute \src "libresoc.v:116029.3-116083.6"
+ process $proc$libresoc.v:116029$4388
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:117405.5-117405.29"
+ attribute \src "libresoc.v:116030.5-116030.29"
switch \initial
- attribute \src "libresoc.v:117405.9-117405.17"
+ attribute \src "libresoc.v:116030.9-116030.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0]
end
- attribute \src "libresoc.v:117459.3-117513.6"
- process $proc$libresoc.v:117459$4445
+ attribute \src "libresoc.v:116084.3-116138.6"
+ process $proc$libresoc.v:116084$4389
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:117460.5-117460.29"
+ attribute \src "libresoc.v:116085.5-116085.29"
switch \initial
- attribute \src "libresoc.v:117460.9-117460.17"
+ attribute \src "libresoc.v:116085.9-116085.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:117519.1-118368.10"
+attribute \src "libresoc.v:116144.1-116993.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58"
attribute \generator "nMigen"
module \dec58
- attribute \src "libresoc.v:118271.3-118286.6"
+ attribute \src "libresoc.v:116896.3-116911.6"
wire width 2 $0\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:118287.3-118302.6"
+ attribute \src "libresoc.v:116912.3-116927.6"
wire width 2 $0\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:118079.3-118094.6"
+ attribute \src "libresoc.v:116704.3-116719.6"
wire width 8 $0\dec58_asmcode[7:0]
- attribute \src "libresoc.v:118143.3-118158.6"
+ attribute \src "libresoc.v:116768.3-116783.6"
wire $0\dec58_br[0:0]
- attribute \src "libresoc.v:117871.3-117886.6"
+ attribute \src "libresoc.v:116496.3-116511.6"
wire width 3 $0\dec58_cr_in[2:0]
- attribute \src "libresoc.v:117887.3-117902.6"
+ attribute \src "libresoc.v:116512.3-116527.6"
wire width 3 $0\dec58_cr_out[2:0]
- attribute \src "libresoc.v:118063.3-118078.6"
+ attribute \src "libresoc.v:116688.3-116703.6"
wire width 2 $0\dec58_cry_in[1:0]
- attribute \src "libresoc.v:118127.3-118142.6"
+ attribute \src "libresoc.v:116752.3-116767.6"
wire $0\dec58_cry_out[0:0]
- attribute \src "libresoc.v:118207.3-118222.6"
+ attribute \src "libresoc.v:116832.3-116847.6"
wire width 5 $0\dec58_form[4:0]
- attribute \src "libresoc.v:117855.3-117870.6"
+ attribute \src "libresoc.v:116480.3-116495.6"
wire width 13 $0\dec58_function_unit[12:0]
- attribute \src "libresoc.v:118303.3-118318.6"
+ attribute \src "libresoc.v:116928.3-116943.6"
wire width 3 $0\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:118319.3-118334.6"
+ attribute \src "libresoc.v:116944.3-116959.6"
wire width 4 $0\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:118335.3-118350.6"
+ attribute \src "libresoc.v:116960.3-116975.6"
wire width 2 $0\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:118031.3-118046.6"
+ attribute \src "libresoc.v:116656.3-116671.6"
wire width 7 $0\dec58_internal_op[6:0]
- attribute \src "libresoc.v:118095.3-118110.6"
+ attribute \src "libresoc.v:116720.3-116735.6"
wire $0\dec58_inv_a[0:0]
- attribute \src "libresoc.v:118111.3-118126.6"
+ attribute \src "libresoc.v:116736.3-116751.6"
wire $0\dec58_inv_out[0:0]
- attribute \src "libresoc.v:118191.3-118206.6"
+ attribute \src "libresoc.v:116816.3-116831.6"
wire $0\dec58_is_32b[0:0]
- attribute \src "libresoc.v:117999.3-118014.6"
+ attribute \src "libresoc.v:116624.3-116639.6"
wire width 4 $0\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:118239.3-118254.6"
+ attribute \src "libresoc.v:116864.3-116879.6"
wire $0\dec58_lk[0:0]
- attribute \src "libresoc.v:118351.3-118366.6"
+ attribute \src "libresoc.v:116976.3-116991.6"
wire width 2 $0\dec58_out_sel[1:0]
- attribute \src "libresoc.v:118047.3-118062.6"
+ attribute \src "libresoc.v:116672.3-116687.6"
wire width 2 $0\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:118175.3-118190.6"
+ attribute \src "libresoc.v:116800.3-116815.6"
wire $0\dec58_rsrv[0:0]
- attribute \src "libresoc.v:118255.3-118270.6"
+ attribute \src "libresoc.v:116880.3-116895.6"
wire $0\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:118223.3-118238.6"
+ attribute \src "libresoc.v:116848.3-116863.6"
wire $0\dec58_sgn[0:0]
- attribute \src "libresoc.v:118159.3-118174.6"
+ attribute \src "libresoc.v:116784.3-116799.6"
wire $0\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:117967.3-117982.6"
+ attribute \src "libresoc.v:116592.3-116607.6"
wire width 3 $0\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:117983.3-117998.6"
+ attribute \src "libresoc.v:116608.3-116623.6"
wire width 3 $0\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:117903.3-117918.6"
+ attribute \src "libresoc.v:116528.3-116543.6"
wire width 3 $0\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:117919.3-117934.6"
+ attribute \src "libresoc.v:116544.3-116559.6"
wire width 3 $0\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:117935.3-117950.6"
+ attribute \src "libresoc.v:116560.3-116575.6"
wire width 3 $0\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:117951.3-117966.6"
+ attribute \src "libresoc.v:116576.3-116591.6"
wire width 3 $0\dec58_sv_out[2:0]
- attribute \src "libresoc.v:118015.3-118030.6"
+ attribute \src "libresoc.v:116640.3-116655.6"
wire width 2 $0\dec58_upd[1:0]
- attribute \src "libresoc.v:117520.7-117520.20"
+ attribute \src "libresoc.v:116145.7-116145.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:118271.3-118286.6"
+ attribute \src "libresoc.v:116896.3-116911.6"
wire width 2 $1\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:118287.3-118302.6"
+ attribute \src "libresoc.v:116912.3-116927.6"
wire width 2 $1\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:118079.3-118094.6"
+ attribute \src "libresoc.v:116704.3-116719.6"
wire width 8 $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:118143.3-118158.6"
+ attribute \src "libresoc.v:116768.3-116783.6"
wire $1\dec58_br[0:0]
- attribute \src "libresoc.v:117871.3-117886.6"
+ attribute \src "libresoc.v:116496.3-116511.6"
wire width 3 $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:117887.3-117902.6"
+ attribute \src "libresoc.v:116512.3-116527.6"
wire width 3 $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:118063.3-118078.6"
+ attribute \src "libresoc.v:116688.3-116703.6"
wire width 2 $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:118127.3-118142.6"
+ attribute \src "libresoc.v:116752.3-116767.6"
wire $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:118207.3-118222.6"
+ attribute \src "libresoc.v:116832.3-116847.6"
wire width 5 $1\dec58_form[4:0]
- attribute \src "libresoc.v:117855.3-117870.6"
+ attribute \src "libresoc.v:116480.3-116495.6"
wire width 13 $1\dec58_function_unit[12:0]
- attribute \src "libresoc.v:118303.3-118318.6"
+ attribute \src "libresoc.v:116928.3-116943.6"
wire width 3 $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:118319.3-118334.6"
+ attribute \src "libresoc.v:116944.3-116959.6"
wire width 4 $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:118335.3-118350.6"
+ attribute \src "libresoc.v:116960.3-116975.6"
wire width 2 $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:118031.3-118046.6"
+ attribute \src "libresoc.v:116656.3-116671.6"
wire width 7 $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:118095.3-118110.6"
+ attribute \src "libresoc.v:116720.3-116735.6"
wire $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:118111.3-118126.6"
+ attribute \src "libresoc.v:116736.3-116751.6"
wire $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:118191.3-118206.6"
+ attribute \src "libresoc.v:116816.3-116831.6"
wire $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:117999.3-118014.6"
+ attribute \src "libresoc.v:116624.3-116639.6"
wire width 4 $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:118239.3-118254.6"
+ attribute \src "libresoc.v:116864.3-116879.6"
wire $1\dec58_lk[0:0]
- attribute \src "libresoc.v:118351.3-118366.6"
+ attribute \src "libresoc.v:116976.3-116991.6"
wire width 2 $1\dec58_out_sel[1:0]
- attribute \src "libresoc.v:118047.3-118062.6"
+ attribute \src "libresoc.v:116672.3-116687.6"
wire width 2 $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:118175.3-118190.6"
+ attribute \src "libresoc.v:116800.3-116815.6"
wire $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:118255.3-118270.6"
+ attribute \src "libresoc.v:116880.3-116895.6"
wire $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:118223.3-118238.6"
+ attribute \src "libresoc.v:116848.3-116863.6"
wire $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:118159.3-118174.6"
+ attribute \src "libresoc.v:116784.3-116799.6"
wire $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:117967.3-117982.6"
+ attribute \src "libresoc.v:116592.3-116607.6"
wire width 3 $1\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:117983.3-117998.6"
+ attribute \src "libresoc.v:116608.3-116623.6"
wire width 3 $1\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:117903.3-117918.6"
+ attribute \src "libresoc.v:116528.3-116543.6"
wire width 3 $1\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:117919.3-117934.6"
+ attribute \src "libresoc.v:116544.3-116559.6"
wire width 3 $1\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:117935.3-117950.6"
+ attribute \src "libresoc.v:116560.3-116575.6"
wire width 3 $1\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:117951.3-117966.6"
+ attribute \src "libresoc.v:116576.3-116591.6"
wire width 3 $1\dec58_sv_out[2:0]
- attribute \src "libresoc.v:118015.3-118030.6"
+ attribute \src "libresoc.v:116640.3-116655.6"
wire width 2 $1\dec58_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec58_upd
- attribute \src "libresoc.v:117520.7-117520.15"
+ attribute \src "libresoc.v:116145.7-116145.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:117520.7-117520.20"
- process $proc$libresoc.v:117520$4479
+ attribute \src "libresoc.v:116145.7-116145.20"
+ process $proc$libresoc.v:116145$4423
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:117855.3-117870.6"
- process $proc$libresoc.v:117855$4447
+ attribute \src "libresoc.v:116480.3-116495.6"
+ process $proc$libresoc.v:116480$4391
assign { } { }
assign { } { }
assign $0\dec58_function_unit[12:0] $1\dec58_function_unit[12:0]
- attribute \src "libresoc.v:117856.5-117856.29"
+ attribute \src "libresoc.v:116481.5-116481.29"
switch \initial
- attribute \src "libresoc.v:117856.9-117856.17"
+ attribute \src "libresoc.v:116481.9-116481.17"
case 1'1
case
end
sync always
update \dec58_function_unit $0\dec58_function_unit[12:0]
end
- attribute \src "libresoc.v:117871.3-117886.6"
- process $proc$libresoc.v:117871$4448
+ attribute \src "libresoc.v:116496.3-116511.6"
+ process $proc$libresoc.v:116496$4392
assign { } { }
assign { } { }
assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:117872.5-117872.29"
+ attribute \src "libresoc.v:116497.5-116497.29"
switch \initial
- attribute \src "libresoc.v:117872.9-117872.17"
+ attribute \src "libresoc.v:116497.9-116497.17"
case 1'1
case
end
sync always
update \dec58_cr_in $0\dec58_cr_in[2:0]
end
- attribute \src "libresoc.v:117887.3-117902.6"
- process $proc$libresoc.v:117887$4449
+ attribute \src "libresoc.v:116512.3-116527.6"
+ process $proc$libresoc.v:116512$4393
assign { } { }
assign { } { }
assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:117888.5-117888.29"
+ attribute \src "libresoc.v:116513.5-116513.29"
switch \initial
- attribute \src "libresoc.v:117888.9-117888.17"
+ attribute \src "libresoc.v:116513.9-116513.17"
case 1'1
case
end
sync always
update \dec58_cr_out $0\dec58_cr_out[2:0]
end
- attribute \src "libresoc.v:117903.3-117918.6"
- process $proc$libresoc.v:117903$4450
+ attribute \src "libresoc.v:116528.3-116543.6"
+ process $proc$libresoc.v:116528$4394
assign { } { }
assign { } { }
assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0]
- attribute \src "libresoc.v:117904.5-117904.29"
+ attribute \src "libresoc.v:116529.5-116529.29"
switch \initial
- attribute \src "libresoc.v:117904.9-117904.17"
+ attribute \src "libresoc.v:116529.9-116529.17"
case 1'1
case
end
sync always
update \dec58_sv_in1 $0\dec58_sv_in1[2:0]
end
- attribute \src "libresoc.v:117919.3-117934.6"
- process $proc$libresoc.v:117919$4451
+ attribute \src "libresoc.v:116544.3-116559.6"
+ process $proc$libresoc.v:116544$4395
assign { } { }
assign { } { }
assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0]
- attribute \src "libresoc.v:117920.5-117920.29"
+ attribute \src "libresoc.v:116545.5-116545.29"
switch \initial
- attribute \src "libresoc.v:117920.9-117920.17"
+ attribute \src "libresoc.v:116545.9-116545.17"
case 1'1
case
end
sync always
update \dec58_sv_in2 $0\dec58_sv_in2[2:0]
end
- attribute \src "libresoc.v:117935.3-117950.6"
- process $proc$libresoc.v:117935$4452
+ attribute \src "libresoc.v:116560.3-116575.6"
+ process $proc$libresoc.v:116560$4396
assign { } { }
assign { } { }
assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0]
- attribute \src "libresoc.v:117936.5-117936.29"
+ attribute \src "libresoc.v:116561.5-116561.29"
switch \initial
- attribute \src "libresoc.v:117936.9-117936.17"
+ attribute \src "libresoc.v:116561.9-116561.17"
case 1'1
case
end
sync always
update \dec58_sv_in3 $0\dec58_sv_in3[2:0]
end
- attribute \src "libresoc.v:117951.3-117966.6"
- process $proc$libresoc.v:117951$4453
+ attribute \src "libresoc.v:116576.3-116591.6"
+ process $proc$libresoc.v:116576$4397
assign { } { }
assign { } { }
assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0]
- attribute \src "libresoc.v:117952.5-117952.29"
+ attribute \src "libresoc.v:116577.5-116577.29"
switch \initial
- attribute \src "libresoc.v:117952.9-117952.17"
+ attribute \src "libresoc.v:116577.9-116577.17"
case 1'1
case
end
sync always
update \dec58_sv_out $0\dec58_sv_out[2:0]
end
- attribute \src "libresoc.v:117967.3-117982.6"
- process $proc$libresoc.v:117967$4454
+ attribute \src "libresoc.v:116592.3-116607.6"
+ process $proc$libresoc.v:116592$4398
assign { } { }
assign { } { }
assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0]
- attribute \src "libresoc.v:117968.5-117968.29"
+ attribute \src "libresoc.v:116593.5-116593.29"
switch \initial
- attribute \src "libresoc.v:117968.9-117968.17"
+ attribute \src "libresoc.v:116593.9-116593.17"
case 1'1
case
end
sync always
update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:117983.3-117998.6"
- process $proc$libresoc.v:117983$4455
+ attribute \src "libresoc.v:116608.3-116623.6"
+ process $proc$libresoc.v:116608$4399
assign { } { }
assign { } { }
assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0]
- attribute \src "libresoc.v:117984.5-117984.29"
+ attribute \src "libresoc.v:116609.5-116609.29"
switch \initial
- attribute \src "libresoc.v:117984.9-117984.17"
+ attribute \src "libresoc.v:116609.9-116609.17"
case 1'1
case
end
sync always
update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:117999.3-118014.6"
- process $proc$libresoc.v:117999$4456
+ attribute \src "libresoc.v:116624.3-116639.6"
+ process $proc$libresoc.v:116624$4400
assign { } { }
assign { } { }
assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:118000.5-118000.29"
+ attribute \src "libresoc.v:116625.5-116625.29"
switch \initial
- attribute \src "libresoc.v:118000.9-118000.17"
+ attribute \src "libresoc.v:116625.9-116625.17"
case 1'1
case
end
sync always
update \dec58_ldst_len $0\dec58_ldst_len[3:0]
end
- attribute \src "libresoc.v:118015.3-118030.6"
- process $proc$libresoc.v:118015$4457
+ attribute \src "libresoc.v:116640.3-116655.6"
+ process $proc$libresoc.v:116640$4401
assign { } { }
assign { } { }
assign $0\dec58_upd[1:0] $1\dec58_upd[1:0]
- attribute \src "libresoc.v:118016.5-118016.29"
+ attribute \src "libresoc.v:116641.5-116641.29"
switch \initial
- attribute \src "libresoc.v:118016.9-118016.17"
+ attribute \src "libresoc.v:116641.9-116641.17"
case 1'1
case
end
sync always
update \dec58_upd $0\dec58_upd[1:0]
end
- attribute \src "libresoc.v:118031.3-118046.6"
- process $proc$libresoc.v:118031$4458
+ attribute \src "libresoc.v:116656.3-116671.6"
+ process $proc$libresoc.v:116656$4402
assign { } { }
assign { } { }
assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:118032.5-118032.29"
+ attribute \src "libresoc.v:116657.5-116657.29"
switch \initial
- attribute \src "libresoc.v:118032.9-118032.17"
+ attribute \src "libresoc.v:116657.9-116657.17"
case 1'1
case
end
sync always
update \dec58_internal_op $0\dec58_internal_op[6:0]
end
- attribute \src "libresoc.v:118047.3-118062.6"
- process $proc$libresoc.v:118047$4459
+ attribute \src "libresoc.v:116672.3-116687.6"
+ process $proc$libresoc.v:116672$4403
assign { } { }
assign { } { }
assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:118048.5-118048.29"
+ attribute \src "libresoc.v:116673.5-116673.29"
switch \initial
- attribute \src "libresoc.v:118048.9-118048.17"
+ attribute \src "libresoc.v:116673.9-116673.17"
case 1'1
case
end
sync always
update \dec58_rc_sel $0\dec58_rc_sel[1:0]
end
- attribute \src "libresoc.v:118063.3-118078.6"
- process $proc$libresoc.v:118063$4460
+ attribute \src "libresoc.v:116688.3-116703.6"
+ process $proc$libresoc.v:116688$4404
assign { } { }
assign { } { }
assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:118064.5-118064.29"
+ attribute \src "libresoc.v:116689.5-116689.29"
switch \initial
- attribute \src "libresoc.v:118064.9-118064.17"
+ attribute \src "libresoc.v:116689.9-116689.17"
case 1'1
case
end
sync always
update \dec58_cry_in $0\dec58_cry_in[1:0]
end
- attribute \src "libresoc.v:118079.3-118094.6"
- process $proc$libresoc.v:118079$4461
+ attribute \src "libresoc.v:116704.3-116719.6"
+ process $proc$libresoc.v:116704$4405
assign { } { }
assign { } { }
assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:118080.5-118080.29"
+ attribute \src "libresoc.v:116705.5-116705.29"
switch \initial
- attribute \src "libresoc.v:118080.9-118080.17"
+ attribute \src "libresoc.v:116705.9-116705.17"
case 1'1
case
end
sync always
update \dec58_asmcode $0\dec58_asmcode[7:0]
end
- attribute \src "libresoc.v:118095.3-118110.6"
- process $proc$libresoc.v:118095$4462
+ attribute \src "libresoc.v:116720.3-116735.6"
+ process $proc$libresoc.v:116720$4406
assign { } { }
assign { } { }
assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:118096.5-118096.29"
+ attribute \src "libresoc.v:116721.5-116721.29"
switch \initial
- attribute \src "libresoc.v:118096.9-118096.17"
+ attribute \src "libresoc.v:116721.9-116721.17"
case 1'1
case
end
sync always
update \dec58_inv_a $0\dec58_inv_a[0:0]
end
- attribute \src "libresoc.v:118111.3-118126.6"
- process $proc$libresoc.v:118111$4463
+ attribute \src "libresoc.v:116736.3-116751.6"
+ process $proc$libresoc.v:116736$4407
assign { } { }
assign { } { }
assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:118112.5-118112.29"
+ attribute \src "libresoc.v:116737.5-116737.29"
switch \initial
- attribute \src "libresoc.v:118112.9-118112.17"
+ attribute \src "libresoc.v:116737.9-116737.17"
case 1'1
case
end
sync always
update \dec58_inv_out $0\dec58_inv_out[0:0]
end
- attribute \src "libresoc.v:118127.3-118142.6"
- process $proc$libresoc.v:118127$4464
+ attribute \src "libresoc.v:116752.3-116767.6"
+ process $proc$libresoc.v:116752$4408
assign { } { }
assign { } { }
assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:118128.5-118128.29"
+ attribute \src "libresoc.v:116753.5-116753.29"
switch \initial
- attribute \src "libresoc.v:118128.9-118128.17"
+ attribute \src "libresoc.v:116753.9-116753.17"
case 1'1
case
end
sync always
update \dec58_cry_out $0\dec58_cry_out[0:0]
end
- attribute \src "libresoc.v:118143.3-118158.6"
- process $proc$libresoc.v:118143$4465
+ attribute \src "libresoc.v:116768.3-116783.6"
+ process $proc$libresoc.v:116768$4409
assign { } { }
assign { } { }
assign $0\dec58_br[0:0] $1\dec58_br[0:0]
- attribute \src "libresoc.v:118144.5-118144.29"
+ attribute \src "libresoc.v:116769.5-116769.29"
switch \initial
- attribute \src "libresoc.v:118144.9-118144.17"
+ attribute \src "libresoc.v:116769.9-116769.17"
case 1'1
case
end
sync always
update \dec58_br $0\dec58_br[0:0]
end
- attribute \src "libresoc.v:118159.3-118174.6"
- process $proc$libresoc.v:118159$4466
+ attribute \src "libresoc.v:116784.3-116799.6"
+ process $proc$libresoc.v:116784$4410
assign { } { }
assign { } { }
assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:118160.5-118160.29"
+ attribute \src "libresoc.v:116785.5-116785.29"
switch \initial
- attribute \src "libresoc.v:118160.9-118160.17"
+ attribute \src "libresoc.v:116785.9-116785.17"
case 1'1
case
end
sync always
update \dec58_sgn_ext $0\dec58_sgn_ext[0:0]
end
- attribute \src "libresoc.v:118175.3-118190.6"
- process $proc$libresoc.v:118175$4467
+ attribute \src "libresoc.v:116800.3-116815.6"
+ process $proc$libresoc.v:116800$4411
assign { } { }
assign { } { }
assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:118176.5-118176.29"
+ attribute \src "libresoc.v:116801.5-116801.29"
switch \initial
- attribute \src "libresoc.v:118176.9-118176.17"
+ attribute \src "libresoc.v:116801.9-116801.17"
case 1'1
case
end
sync always
update \dec58_rsrv $0\dec58_rsrv[0:0]
end
- attribute \src "libresoc.v:118191.3-118206.6"
- process $proc$libresoc.v:118191$4468
+ attribute \src "libresoc.v:116816.3-116831.6"
+ process $proc$libresoc.v:116816$4412
assign { } { }
assign { } { }
assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:118192.5-118192.29"
+ attribute \src "libresoc.v:116817.5-116817.29"
switch \initial
- attribute \src "libresoc.v:118192.9-118192.17"
+ attribute \src "libresoc.v:116817.9-116817.17"
case 1'1
case
end
sync always
update \dec58_is_32b $0\dec58_is_32b[0:0]
end
- attribute \src "libresoc.v:118207.3-118222.6"
- process $proc$libresoc.v:118207$4469
+ attribute \src "libresoc.v:116832.3-116847.6"
+ process $proc$libresoc.v:116832$4413
assign { } { }
assign { } { }
assign $0\dec58_form[4:0] $1\dec58_form[4:0]
- attribute \src "libresoc.v:118208.5-118208.29"
+ attribute \src "libresoc.v:116833.5-116833.29"
switch \initial
- attribute \src "libresoc.v:118208.9-118208.17"
+ attribute \src "libresoc.v:116833.9-116833.17"
case 1'1
case
end
sync always
update \dec58_form $0\dec58_form[4:0]
end
- attribute \src "libresoc.v:118223.3-118238.6"
- process $proc$libresoc.v:118223$4470
+ attribute \src "libresoc.v:116848.3-116863.6"
+ process $proc$libresoc.v:116848$4414
assign { } { }
assign { } { }
assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:118224.5-118224.29"
+ attribute \src "libresoc.v:116849.5-116849.29"
switch \initial
- attribute \src "libresoc.v:118224.9-118224.17"
+ attribute \src "libresoc.v:116849.9-116849.17"
case 1'1
case
end
sync always
update \dec58_sgn $0\dec58_sgn[0:0]
end
- attribute \src "libresoc.v:118239.3-118254.6"
- process $proc$libresoc.v:118239$4471
+ attribute \src "libresoc.v:116864.3-116879.6"
+ process $proc$libresoc.v:116864$4415
assign { } { }
assign { } { }
assign $0\dec58_lk[0:0] $1\dec58_lk[0:0]
- attribute \src "libresoc.v:118240.5-118240.29"
+ attribute \src "libresoc.v:116865.5-116865.29"
switch \initial
- attribute \src "libresoc.v:118240.9-118240.17"
+ attribute \src "libresoc.v:116865.9-116865.17"
case 1'1
case
end
sync always
update \dec58_lk $0\dec58_lk[0:0]
end
- attribute \src "libresoc.v:118255.3-118270.6"
- process $proc$libresoc.v:118255$4472
+ attribute \src "libresoc.v:116880.3-116895.6"
+ process $proc$libresoc.v:116880$4416
assign { } { }
assign { } { }
assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:118256.5-118256.29"
+ attribute \src "libresoc.v:116881.5-116881.29"
switch \initial
- attribute \src "libresoc.v:118256.9-118256.17"
+ attribute \src "libresoc.v:116881.9-116881.17"
case 1'1
case
end
sync always
update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:118271.3-118286.6"
- process $proc$libresoc.v:118271$4473
+ attribute \src "libresoc.v:116896.3-116911.6"
+ process $proc$libresoc.v:116896$4417
assign { } { }
assign { } { }
assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0]
- attribute \src "libresoc.v:118272.5-118272.29"
+ attribute \src "libresoc.v:116897.5-116897.29"
switch \initial
- attribute \src "libresoc.v:118272.9-118272.17"
+ attribute \src "libresoc.v:116897.9-116897.17"
case 1'1
case
end
sync always
update \dec58_SV_Etype $0\dec58_SV_Etype[1:0]
end
- attribute \src "libresoc.v:118287.3-118302.6"
- process $proc$libresoc.v:118287$4474
+ attribute \src "libresoc.v:116912.3-116927.6"
+ process $proc$libresoc.v:116912$4418
assign { } { }
assign { } { }
assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0]
- attribute \src "libresoc.v:118288.5-118288.29"
+ attribute \src "libresoc.v:116913.5-116913.29"
switch \initial
- attribute \src "libresoc.v:118288.9-118288.17"
+ attribute \src "libresoc.v:116913.9-116913.17"
case 1'1
case
end
sync always
update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:118303.3-118318.6"
- process $proc$libresoc.v:118303$4475
+ attribute \src "libresoc.v:116928.3-116943.6"
+ process $proc$libresoc.v:116928$4419
assign { } { }
assign { } { }
assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:118304.5-118304.29"
+ attribute \src "libresoc.v:116929.5-116929.29"
switch \initial
- attribute \src "libresoc.v:118304.9-118304.17"
+ attribute \src "libresoc.v:116929.9-116929.17"
case 1'1
case
end
sync always
update \dec58_in1_sel $0\dec58_in1_sel[2:0]
end
- attribute \src "libresoc.v:118319.3-118334.6"
- process $proc$libresoc.v:118319$4476
+ attribute \src "libresoc.v:116944.3-116959.6"
+ process $proc$libresoc.v:116944$4420
assign { } { }
assign { } { }
assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:118320.5-118320.29"
+ attribute \src "libresoc.v:116945.5-116945.29"
switch \initial
- attribute \src "libresoc.v:118320.9-118320.17"
+ attribute \src "libresoc.v:116945.9-116945.17"
case 1'1
case
end
sync always
update \dec58_in2_sel $0\dec58_in2_sel[3:0]
end
- attribute \src "libresoc.v:118335.3-118350.6"
- process $proc$libresoc.v:118335$4477
+ attribute \src "libresoc.v:116960.3-116975.6"
+ process $proc$libresoc.v:116960$4421
assign { } { }
assign { } { }
assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:118336.5-118336.29"
+ attribute \src "libresoc.v:116961.5-116961.29"
switch \initial
- attribute \src "libresoc.v:118336.9-118336.17"
+ attribute \src "libresoc.v:116961.9-116961.17"
case 1'1
case
end
sync always
update \dec58_in3_sel $0\dec58_in3_sel[1:0]
end
- attribute \src "libresoc.v:118351.3-118366.6"
- process $proc$libresoc.v:118351$4478
+ attribute \src "libresoc.v:116976.3-116991.6"
+ process $proc$libresoc.v:116976$4422
assign { } { }
assign { } { }
assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0]
- attribute \src "libresoc.v:118352.5-118352.29"
+ attribute \src "libresoc.v:116977.5-116977.29"
switch \initial
- attribute \src "libresoc.v:118352.9-118352.17"
+ attribute \src "libresoc.v:116977.9-116977.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:118372.1-119125.10"
+attribute \src "libresoc.v:116997.1-117750.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62"
attribute \generator "nMigen"
module \dec62
- attribute \src "libresoc.v:119046.3-119058.6"
+ attribute \src "libresoc.v:117671.3-117683.6"
wire width 2 $0\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:119059.3-119071.6"
+ attribute \src "libresoc.v:117684.3-117696.6"
wire width 2 $0\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:118890.3-118902.6"
+ attribute \src "libresoc.v:117515.3-117527.6"
wire width 8 $0\dec62_asmcode[7:0]
- attribute \src "libresoc.v:118942.3-118954.6"
+ attribute \src "libresoc.v:117567.3-117579.6"
wire $0\dec62_br[0:0]
- attribute \src "libresoc.v:118721.3-118733.6"
+ attribute \src "libresoc.v:117346.3-117358.6"
wire width 3 $0\dec62_cr_in[2:0]
- attribute \src "libresoc.v:118734.3-118746.6"
+ attribute \src "libresoc.v:117359.3-117371.6"
wire width 3 $0\dec62_cr_out[2:0]
- attribute \src "libresoc.v:118877.3-118889.6"
+ attribute \src "libresoc.v:117502.3-117514.6"
wire width 2 $0\dec62_cry_in[1:0]
- attribute \src "libresoc.v:118929.3-118941.6"
+ attribute \src "libresoc.v:117554.3-117566.6"
wire $0\dec62_cry_out[0:0]
- attribute \src "libresoc.v:118994.3-119006.6"
+ attribute \src "libresoc.v:117619.3-117631.6"
wire width 5 $0\dec62_form[4:0]
- attribute \src "libresoc.v:118708.3-118720.6"
+ attribute \src "libresoc.v:117333.3-117345.6"
wire width 13 $0\dec62_function_unit[12:0]
- attribute \src "libresoc.v:119072.3-119084.6"
+ attribute \src "libresoc.v:117697.3-117709.6"
wire width 3 $0\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:119085.3-119097.6"
+ attribute \src "libresoc.v:117710.3-117722.6"
wire width 4 $0\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:119098.3-119110.6"
+ attribute \src "libresoc.v:117723.3-117735.6"
wire width 2 $0\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:118851.3-118863.6"
+ attribute \src "libresoc.v:117476.3-117488.6"
wire width 7 $0\dec62_internal_op[6:0]
- attribute \src "libresoc.v:118903.3-118915.6"
+ attribute \src "libresoc.v:117528.3-117540.6"
wire $0\dec62_inv_a[0:0]
- attribute \src "libresoc.v:118916.3-118928.6"
+ attribute \src "libresoc.v:117541.3-117553.6"
wire $0\dec62_inv_out[0:0]
- attribute \src "libresoc.v:118981.3-118993.6"
+ attribute \src "libresoc.v:117606.3-117618.6"
wire $0\dec62_is_32b[0:0]
- attribute \src "libresoc.v:118825.3-118837.6"
+ attribute \src "libresoc.v:117450.3-117462.6"
wire width 4 $0\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:119020.3-119032.6"
+ attribute \src "libresoc.v:117645.3-117657.6"
wire $0\dec62_lk[0:0]
- attribute \src "libresoc.v:119111.3-119123.6"
+ attribute \src "libresoc.v:117736.3-117748.6"
wire width 2 $0\dec62_out_sel[1:0]
- attribute \src "libresoc.v:118864.3-118876.6"
+ attribute \src "libresoc.v:117489.3-117501.6"
wire width 2 $0\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:118968.3-118980.6"
+ attribute \src "libresoc.v:117593.3-117605.6"
wire $0\dec62_rsrv[0:0]
- attribute \src "libresoc.v:119033.3-119045.6"
+ attribute \src "libresoc.v:117658.3-117670.6"
wire $0\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:119007.3-119019.6"
+ attribute \src "libresoc.v:117632.3-117644.6"
wire $0\dec62_sgn[0:0]
- attribute \src "libresoc.v:118955.3-118967.6"
+ attribute \src "libresoc.v:117580.3-117592.6"
wire $0\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:118799.3-118811.6"
+ attribute \src "libresoc.v:117424.3-117436.6"
wire width 3 $0\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:118812.3-118824.6"
+ attribute \src "libresoc.v:117437.3-117449.6"
wire width 3 $0\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:118747.3-118759.6"
+ attribute \src "libresoc.v:117372.3-117384.6"
wire width 3 $0\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:118760.3-118772.6"
+ attribute \src "libresoc.v:117385.3-117397.6"
wire width 3 $0\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:118773.3-118785.6"
+ attribute \src "libresoc.v:117398.3-117410.6"
wire width 3 $0\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:118786.3-118798.6"
+ attribute \src "libresoc.v:117411.3-117423.6"
wire width 3 $0\dec62_sv_out[2:0]
- attribute \src "libresoc.v:118838.3-118850.6"
+ attribute \src "libresoc.v:117463.3-117475.6"
wire width 2 $0\dec62_upd[1:0]
- attribute \src "libresoc.v:118373.7-118373.20"
+ attribute \src "libresoc.v:116998.7-116998.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:119046.3-119058.6"
+ attribute \src "libresoc.v:117671.3-117683.6"
wire width 2 $1\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:119059.3-119071.6"
+ attribute \src "libresoc.v:117684.3-117696.6"
wire width 2 $1\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:118890.3-118902.6"
+ attribute \src "libresoc.v:117515.3-117527.6"
wire width 8 $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:118942.3-118954.6"
+ attribute \src "libresoc.v:117567.3-117579.6"
wire $1\dec62_br[0:0]
- attribute \src "libresoc.v:118721.3-118733.6"
+ attribute \src "libresoc.v:117346.3-117358.6"
wire width 3 $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:118734.3-118746.6"
+ attribute \src "libresoc.v:117359.3-117371.6"
wire width 3 $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:118877.3-118889.6"
+ attribute \src "libresoc.v:117502.3-117514.6"
wire width 2 $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:118929.3-118941.6"
+ attribute \src "libresoc.v:117554.3-117566.6"
wire $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:118994.3-119006.6"
+ attribute \src "libresoc.v:117619.3-117631.6"
wire width 5 $1\dec62_form[4:0]
- attribute \src "libresoc.v:118708.3-118720.6"
+ attribute \src "libresoc.v:117333.3-117345.6"
wire width 13 $1\dec62_function_unit[12:0]
- attribute \src "libresoc.v:119072.3-119084.6"
+ attribute \src "libresoc.v:117697.3-117709.6"
wire width 3 $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:119085.3-119097.6"
+ attribute \src "libresoc.v:117710.3-117722.6"
wire width 4 $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:119098.3-119110.6"
+ attribute \src "libresoc.v:117723.3-117735.6"
wire width 2 $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:118851.3-118863.6"
+ attribute \src "libresoc.v:117476.3-117488.6"
wire width 7 $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:118903.3-118915.6"
+ attribute \src "libresoc.v:117528.3-117540.6"
wire $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:118916.3-118928.6"
+ attribute \src "libresoc.v:117541.3-117553.6"
wire $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:118981.3-118993.6"
+ attribute \src "libresoc.v:117606.3-117618.6"
wire $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:118825.3-118837.6"
+ attribute \src "libresoc.v:117450.3-117462.6"
wire width 4 $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:119020.3-119032.6"
+ attribute \src "libresoc.v:117645.3-117657.6"
wire $1\dec62_lk[0:0]
- attribute \src "libresoc.v:119111.3-119123.6"
+ attribute \src "libresoc.v:117736.3-117748.6"
wire width 2 $1\dec62_out_sel[1:0]
- attribute \src "libresoc.v:118864.3-118876.6"
+ attribute \src "libresoc.v:117489.3-117501.6"
wire width 2 $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:118968.3-118980.6"
+ attribute \src "libresoc.v:117593.3-117605.6"
wire $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:119033.3-119045.6"
+ attribute \src "libresoc.v:117658.3-117670.6"
wire $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:119007.3-119019.6"
+ attribute \src "libresoc.v:117632.3-117644.6"
wire $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:118955.3-118967.6"
+ attribute \src "libresoc.v:117580.3-117592.6"
wire $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:118799.3-118811.6"
+ attribute \src "libresoc.v:117424.3-117436.6"
wire width 3 $1\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:118812.3-118824.6"
+ attribute \src "libresoc.v:117437.3-117449.6"
wire width 3 $1\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:118747.3-118759.6"
+ attribute \src "libresoc.v:117372.3-117384.6"
wire width 3 $1\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:118760.3-118772.6"
+ attribute \src "libresoc.v:117385.3-117397.6"
wire width 3 $1\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:118773.3-118785.6"
+ attribute \src "libresoc.v:117398.3-117410.6"
wire width 3 $1\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:118786.3-118798.6"
+ attribute \src "libresoc.v:117411.3-117423.6"
wire width 3 $1\dec62_sv_out[2:0]
- attribute \src "libresoc.v:118838.3-118850.6"
+ attribute \src "libresoc.v:117463.3-117475.6"
wire width 2 $1\dec62_upd[1:0]
attribute \enum_base_type "SVEtype"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 output 20 \dec62_upd
- attribute \src "libresoc.v:118373.7-118373.15"
+ attribute \src "libresoc.v:116998.7-116998.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303"
wire width 32 input 33 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:118373.7-118373.20"
- process $proc$libresoc.v:118373$4512
+ attribute \src "libresoc.v:116998.7-116998.20"
+ process $proc$libresoc.v:116998$4456
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:118708.3-118720.6"
- process $proc$libresoc.v:118708$4480
+ attribute \src "libresoc.v:117333.3-117345.6"
+ process $proc$libresoc.v:117333$4424
assign { } { }
assign { } { }
assign $0\dec62_function_unit[12:0] $1\dec62_function_unit[12:0]
- attribute \src "libresoc.v:118709.5-118709.29"
+ attribute \src "libresoc.v:117334.5-117334.29"
switch \initial
- attribute \src "libresoc.v:118709.9-118709.17"
+ attribute \src "libresoc.v:117334.9-117334.17"
case 1'1
case
end
sync always
update \dec62_function_unit $0\dec62_function_unit[12:0]
end
- attribute \src "libresoc.v:118721.3-118733.6"
- process $proc$libresoc.v:118721$4481
+ attribute \src "libresoc.v:117346.3-117358.6"
+ process $proc$libresoc.v:117346$4425
assign { } { }
assign { } { }
assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:118722.5-118722.29"
+ attribute \src "libresoc.v:117347.5-117347.29"
switch \initial
- attribute \src "libresoc.v:118722.9-118722.17"
+ attribute \src "libresoc.v:117347.9-117347.17"
case 1'1
case
end
sync always
update \dec62_cr_in $0\dec62_cr_in[2:0]
end
- attribute \src "libresoc.v:118734.3-118746.6"
- process $proc$libresoc.v:118734$4482
+ attribute \src "libresoc.v:117359.3-117371.6"
+ process $proc$libresoc.v:117359$4426
assign { } { }
assign { } { }
assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:118735.5-118735.29"
+ attribute \src "libresoc.v:117360.5-117360.29"
switch \initial
- attribute \src "libresoc.v:118735.9-118735.17"
+ attribute \src "libresoc.v:117360.9-117360.17"
case 1'1
case
end
sync always
update \dec62_cr_out $0\dec62_cr_out[2:0]
end
- attribute \src "libresoc.v:118747.3-118759.6"
- process $proc$libresoc.v:118747$4483
+ attribute \src "libresoc.v:117372.3-117384.6"
+ process $proc$libresoc.v:117372$4427
assign { } { }
assign { } { }
assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0]
- attribute \src "libresoc.v:118748.5-118748.29"
+ attribute \src "libresoc.v:117373.5-117373.29"
switch \initial
- attribute \src "libresoc.v:118748.9-118748.17"
+ attribute \src "libresoc.v:117373.9-117373.17"
case 1'1
case
end
sync always
update \dec62_sv_in1 $0\dec62_sv_in1[2:0]
end
- attribute \src "libresoc.v:118760.3-118772.6"
- process $proc$libresoc.v:118760$4484
+ attribute \src "libresoc.v:117385.3-117397.6"
+ process $proc$libresoc.v:117385$4428
assign { } { }
assign { } { }
assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0]
- attribute \src "libresoc.v:118761.5-118761.29"
+ attribute \src "libresoc.v:117386.5-117386.29"
switch \initial
- attribute \src "libresoc.v:118761.9-118761.17"
+ attribute \src "libresoc.v:117386.9-117386.17"
case 1'1
case
end
sync always
update \dec62_sv_in2 $0\dec62_sv_in2[2:0]
end
- attribute \src "libresoc.v:118773.3-118785.6"
- process $proc$libresoc.v:118773$4485
+ attribute \src "libresoc.v:117398.3-117410.6"
+ process $proc$libresoc.v:117398$4429
assign { } { }
assign { } { }
assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0]
- attribute \src "libresoc.v:118774.5-118774.29"
+ attribute \src "libresoc.v:117399.5-117399.29"
switch \initial
- attribute \src "libresoc.v:118774.9-118774.17"
+ attribute \src "libresoc.v:117399.9-117399.17"
case 1'1
case
end
sync always
update \dec62_sv_in3 $0\dec62_sv_in3[2:0]
end
- attribute \src "libresoc.v:118786.3-118798.6"
- process $proc$libresoc.v:118786$4486
+ attribute \src "libresoc.v:117411.3-117423.6"
+ process $proc$libresoc.v:117411$4430
assign { } { }
assign { } { }
assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0]
- attribute \src "libresoc.v:118787.5-118787.29"
+ attribute \src "libresoc.v:117412.5-117412.29"
switch \initial
- attribute \src "libresoc.v:118787.9-118787.17"
+ attribute \src "libresoc.v:117412.9-117412.17"
case 1'1
case
end
sync always
update \dec62_sv_out $0\dec62_sv_out[2:0]
end
- attribute \src "libresoc.v:118799.3-118811.6"
- process $proc$libresoc.v:118799$4487
+ attribute \src "libresoc.v:117424.3-117436.6"
+ process $proc$libresoc.v:117424$4431
assign { } { }
assign { } { }
assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0]
- attribute \src "libresoc.v:118800.5-118800.29"
+ attribute \src "libresoc.v:117425.5-117425.29"
switch \initial
- attribute \src "libresoc.v:118800.9-118800.17"
+ attribute \src "libresoc.v:117425.9-117425.17"
case 1'1
case
end
sync always
update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0]
end
- attribute \src "libresoc.v:118812.3-118824.6"
- process $proc$libresoc.v:118812$4488
+ attribute \src "libresoc.v:117437.3-117449.6"
+ process $proc$libresoc.v:117437$4432
assign { } { }
assign { } { }
assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0]
- attribute \src "libresoc.v:118813.5-118813.29"
+ attribute \src "libresoc.v:117438.5-117438.29"
switch \initial
- attribute \src "libresoc.v:118813.9-118813.17"
+ attribute \src "libresoc.v:117438.9-117438.17"
case 1'1
case
end
sync always
update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0]
end
- attribute \src "libresoc.v:118825.3-118837.6"
- process $proc$libresoc.v:118825$4489
+ attribute \src "libresoc.v:117450.3-117462.6"
+ process $proc$libresoc.v:117450$4433
assign { } { }
assign { } { }
assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:118826.5-118826.29"
+ attribute \src "libresoc.v:117451.5-117451.29"
switch \initial
- attribute \src "libresoc.v:118826.9-118826.17"
+ attribute \src "libresoc.v:117451.9-117451.17"
case 1'1
case
end
sync always
update \dec62_ldst_len $0\dec62_ldst_len[3:0]
end
- attribute \src "libresoc.v:118838.3-118850.6"
- process $proc$libresoc.v:118838$4490
+ attribute \src "libresoc.v:117463.3-117475.6"
+ process $proc$libresoc.v:117463$4434
assign { } { }
assign { } { }
assign $0\dec62_upd[1:0] $1\dec62_upd[1:0]
- attribute \src "libresoc.v:118839.5-118839.29"
+ attribute \src "libresoc.v:117464.5-117464.29"
switch \initial
- attribute \src "libresoc.v:118839.9-118839.17"
+ attribute \src "libresoc.v:117464.9-117464.17"
case 1'1
case
end
sync always
update \dec62_upd $0\dec62_upd[1:0]
end
- attribute \src "libresoc.v:118851.3-118863.6"
- process $proc$libresoc.v:118851$4491
+ attribute \src "libresoc.v:117476.3-117488.6"
+ process $proc$libresoc.v:117476$4435
assign { } { }
assign { } { }
assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:118852.5-118852.29"
+ attribute \src "libresoc.v:117477.5-117477.29"
switch \initial
- attribute \src "libresoc.v:118852.9-118852.17"
+ attribute \src "libresoc.v:117477.9-117477.17"
case 1'1
case
end
sync always
update \dec62_internal_op $0\dec62_internal_op[6:0]
end
- attribute \src "libresoc.v:118864.3-118876.6"
- process $proc$libresoc.v:118864$4492
+ attribute \src "libresoc.v:117489.3-117501.6"
+ process $proc$libresoc.v:117489$4436
assign { } { }
assign { } { }
assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:118865.5-118865.29"
+ attribute \src "libresoc.v:117490.5-117490.29"
switch \initial
- attribute \src "libresoc.v:118865.9-118865.17"
+ attribute \src "libresoc.v:117490.9-117490.17"
case 1'1
case
end
sync always
update \dec62_rc_sel $0\dec62_rc_sel[1:0]
end
- attribute \src "libresoc.v:118877.3-118889.6"
- process $proc$libresoc.v:118877$4493
+ attribute \src "libresoc.v:117502.3-117514.6"
+ process $proc$libresoc.v:117502$4437
assign { } { }
assign { } { }
assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:118878.5-118878.29"
+ attribute \src "libresoc.v:117503.5-117503.29"
switch \initial
- attribute \src "libresoc.v:118878.9-118878.17"
+ attribute \src "libresoc.v:117503.9-117503.17"
case 1'1
case
end
sync always
update \dec62_cry_in $0\dec62_cry_in[1:0]
end
- attribute \src "libresoc.v:118890.3-118902.6"
- process $proc$libresoc.v:118890$4494
+ attribute \src "libresoc.v:117515.3-117527.6"
+ process $proc$libresoc.v:117515$4438
assign { } { }
assign { } { }
assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:118891.5-118891.29"
+ attribute \src "libresoc.v:117516.5-117516.29"
switch \initial
- attribute \src "libresoc.v:118891.9-118891.17"
+ attribute \src "libresoc.v:117516.9-117516.17"
case 1'1
case
end
sync always
update \dec62_asmcode $0\dec62_asmcode[7:0]
end
- attribute \src "libresoc.v:118903.3-118915.6"
- process $proc$libresoc.v:118903$4495
+ attribute \src "libresoc.v:117528.3-117540.6"
+ process $proc$libresoc.v:117528$4439
assign { } { }
assign { } { }
assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:118904.5-118904.29"
+ attribute \src "libresoc.v:117529.5-117529.29"
switch \initial
- attribute \src "libresoc.v:118904.9-118904.17"
+ attribute \src "libresoc.v:117529.9-117529.17"
case 1'1
case
end
sync always
update \dec62_inv_a $0\dec62_inv_a[0:0]
end
- attribute \src "libresoc.v:118916.3-118928.6"
- process $proc$libresoc.v:118916$4496
+ attribute \src "libresoc.v:117541.3-117553.6"
+ process $proc$libresoc.v:117541$4440
assign { } { }
assign { } { }
assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:118917.5-118917.29"
+ attribute \src "libresoc.v:117542.5-117542.29"
switch \initial
- attribute \src "libresoc.v:118917.9-118917.17"
+ attribute \src "libresoc.v:117542.9-117542.17"
case 1'1
case
end
sync always
update \dec62_inv_out $0\dec62_inv_out[0:0]
end
- attribute \src "libresoc.v:118929.3-118941.6"
- process $proc$libresoc.v:118929$4497
+ attribute \src "libresoc.v:117554.3-117566.6"
+ process $proc$libresoc.v:117554$4441
assign { } { }
assign { } { }
assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:118930.5-118930.29"
+ attribute \src "libresoc.v:117555.5-117555.29"
switch \initial
- attribute \src "libresoc.v:118930.9-118930.17"
+ attribute \src "libresoc.v:117555.9-117555.17"
case 1'1
case
end
sync always
update \dec62_cry_out $0\dec62_cry_out[0:0]
end
- attribute \src "libresoc.v:118942.3-118954.6"
- process $proc$libresoc.v:118942$4498
+ attribute \src "libresoc.v:117567.3-117579.6"
+ process $proc$libresoc.v:117567$4442
assign { } { }
assign { } { }
assign $0\dec62_br[0:0] $1\dec62_br[0:0]
- attribute \src "libresoc.v:118943.5-118943.29"
+ attribute \src "libresoc.v:117568.5-117568.29"
switch \initial
- attribute \src "libresoc.v:118943.9-118943.17"
+ attribute \src "libresoc.v:117568.9-117568.17"
case 1'1
case
end
sync always
update \dec62_br $0\dec62_br[0:0]
end
- attribute \src "libresoc.v:118955.3-118967.6"
- process $proc$libresoc.v:118955$4499
+ attribute \src "libresoc.v:117580.3-117592.6"
+ process $proc$libresoc.v:117580$4443
assign { } { }
assign { } { }
assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:118956.5-118956.29"
+ attribute \src "libresoc.v:117581.5-117581.29"
switch \initial
- attribute \src "libresoc.v:118956.9-118956.17"
+ attribute \src "libresoc.v:117581.9-117581.17"
case 1'1
case
end
sync always
update \dec62_sgn_ext $0\dec62_sgn_ext[0:0]
end
- attribute \src "libresoc.v:118968.3-118980.6"
- process $proc$libresoc.v:118968$4500
+ attribute \src "libresoc.v:117593.3-117605.6"
+ process $proc$libresoc.v:117593$4444
assign { } { }
assign { } { }
assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:118969.5-118969.29"
+ attribute \src "libresoc.v:117594.5-117594.29"
switch \initial
- attribute \src "libresoc.v:118969.9-118969.17"
+ attribute \src "libresoc.v:117594.9-117594.17"
case 1'1
case
end
sync always
update \dec62_rsrv $0\dec62_rsrv[0:0]
end
- attribute \src "libresoc.v:118981.3-118993.6"
- process $proc$libresoc.v:118981$4501
+ attribute \src "libresoc.v:117606.3-117618.6"
+ process $proc$libresoc.v:117606$4445
assign { } { }
assign { } { }
assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:118982.5-118982.29"
+ attribute \src "libresoc.v:117607.5-117607.29"
switch \initial
- attribute \src "libresoc.v:118982.9-118982.17"
+ attribute \src "libresoc.v:117607.9-117607.17"
case 1'1
case
end
sync always
update \dec62_is_32b $0\dec62_is_32b[0:0]
end
- attribute \src "libresoc.v:118994.3-119006.6"
- process $proc$libresoc.v:118994$4502
+ attribute \src "libresoc.v:117619.3-117631.6"
+ process $proc$libresoc.v:117619$4446
assign { } { }
assign { } { }
assign $0\dec62_form[4:0] $1\dec62_form[4:0]
- attribute \src "libresoc.v:118995.5-118995.29"
+ attribute \src "libresoc.v:117620.5-117620.29"
switch \initial
- attribute \src "libresoc.v:118995.9-118995.17"
+ attribute \src "libresoc.v:117620.9-117620.17"
case 1'1
case
end
sync always
update \dec62_form $0\dec62_form[4:0]
end
- attribute \src "libresoc.v:119007.3-119019.6"
- process $proc$libresoc.v:119007$4503
+ attribute \src "libresoc.v:117632.3-117644.6"
+ process $proc$libresoc.v:117632$4447
assign { } { }
assign { } { }
assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:119008.5-119008.29"
+ attribute \src "libresoc.v:117633.5-117633.29"
switch \initial
- attribute \src "libresoc.v:119008.9-119008.17"
+ attribute \src "libresoc.v:117633.9-117633.17"
case 1'1
case
end
sync always
update \dec62_sgn $0\dec62_sgn[0:0]
end
- attribute \src "libresoc.v:119020.3-119032.6"
- process $proc$libresoc.v:119020$4504
+ attribute \src "libresoc.v:117645.3-117657.6"
+ process $proc$libresoc.v:117645$4448
assign { } { }
assign { } { }
assign $0\dec62_lk[0:0] $1\dec62_lk[0:0]
- attribute \src "libresoc.v:119021.5-119021.29"
+ attribute \src "libresoc.v:117646.5-117646.29"
switch \initial
- attribute \src "libresoc.v:119021.9-119021.17"
+ attribute \src "libresoc.v:117646.9-117646.17"
case 1'1
case
end
sync always
update \dec62_lk $0\dec62_lk[0:0]
end
- attribute \src "libresoc.v:119033.3-119045.6"
- process $proc$libresoc.v:119033$4505
+ attribute \src "libresoc.v:117658.3-117670.6"
+ process $proc$libresoc.v:117658$4449
assign { } { }
assign { } { }
assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:119034.5-119034.29"
+ attribute \src "libresoc.v:117659.5-117659.29"
switch \initial
- attribute \src "libresoc.v:119034.9-119034.17"
+ attribute \src "libresoc.v:117659.9-117659.17"
case 1'1
case
end
sync always
update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:119046.3-119058.6"
- process $proc$libresoc.v:119046$4506
+ attribute \src "libresoc.v:117671.3-117683.6"
+ process $proc$libresoc.v:117671$4450
assign { } { }
assign { } { }
assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0]
- attribute \src "libresoc.v:119047.5-119047.29"
+ attribute \src "libresoc.v:117672.5-117672.29"
switch \initial
- attribute \src "libresoc.v:119047.9-119047.17"
+ attribute \src "libresoc.v:117672.9-117672.17"
case 1'1
case
end
sync always
update \dec62_SV_Etype $0\dec62_SV_Etype[1:0]
end
- attribute \src "libresoc.v:119059.3-119071.6"
- process $proc$libresoc.v:119059$4507
+ attribute \src "libresoc.v:117684.3-117696.6"
+ process $proc$libresoc.v:117684$4451
assign { } { }
assign { } { }
assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0]
- attribute \src "libresoc.v:119060.5-119060.29"
+ attribute \src "libresoc.v:117685.5-117685.29"
switch \initial
- attribute \src "libresoc.v:119060.9-119060.17"
+ attribute \src "libresoc.v:117685.9-117685.17"
case 1'1
case
end
sync always
update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0]
end
- attribute \src "libresoc.v:119072.3-119084.6"
- process $proc$libresoc.v:119072$4508
+ attribute \src "libresoc.v:117697.3-117709.6"
+ process $proc$libresoc.v:117697$4452
assign { } { }
assign { } { }
assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:119073.5-119073.29"
+ attribute \src "libresoc.v:117698.5-117698.29"
switch \initial
- attribute \src "libresoc.v:119073.9-119073.17"
+ attribute \src "libresoc.v:117698.9-117698.17"
case 1'1
case
end
sync always
update \dec62_in1_sel $0\dec62_in1_sel[2:0]
end
- attribute \src "libresoc.v:119085.3-119097.6"
- process $proc$libresoc.v:119085$4509
+ attribute \src "libresoc.v:117710.3-117722.6"
+ process $proc$libresoc.v:117710$4453
assign { } { }
assign { } { }
assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:119086.5-119086.29"
+ attribute \src "libresoc.v:117711.5-117711.29"
switch \initial
- attribute \src "libresoc.v:119086.9-119086.17"
+ attribute \src "libresoc.v:117711.9-117711.17"
case 1'1
case
end
sync always
update \dec62_in2_sel $0\dec62_in2_sel[3:0]
end
- attribute \src "libresoc.v:119098.3-119110.6"
- process $proc$libresoc.v:119098$4510
+ attribute \src "libresoc.v:117723.3-117735.6"
+ process $proc$libresoc.v:117723$4454
assign { } { }
assign { } { }
assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:119099.5-119099.29"
+ attribute \src "libresoc.v:117724.5-117724.29"
switch \initial
- attribute \src "libresoc.v:119099.9-119099.17"
+ attribute \src "libresoc.v:117724.9-117724.17"
case 1'1
case
end
sync always
update \dec62_in3_sel $0\dec62_in3_sel[1:0]
end
- attribute \src "libresoc.v:119111.3-119123.6"
- process $proc$libresoc.v:119111$4511
+ attribute \src "libresoc.v:117736.3-117748.6"
+ process $proc$libresoc.v:117736$4455
assign { } { }
assign { } { }
assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0]
- attribute \src "libresoc.v:119112.5-119112.29"
+ attribute \src "libresoc.v:117737.5-117737.29"
switch \initial
- attribute \src "libresoc.v:119112.9-119112.17"
+ attribute \src "libresoc.v:117737.9-117737.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:119129.1-119702.10"
+attribute \src "libresoc.v:117754.1-118327.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU"
attribute \generator "nMigen"
module \dec_ALU
- attribute \src "libresoc.v:119666.3-119680.6"
+ attribute \src "libresoc.v:118291.3-118305.6"
wire width 13 $0\ALU__fn_unit[12:0]
- attribute \src "libresoc.v:119653.3-119665.6"
+ attribute \src "libresoc.v:118278.3-118290.6"
wire width 7 $0\ALU__insn_type[6:0]
- attribute \src "libresoc.v:119638.3-119652.6"
+ attribute \src "libresoc.v:118263.3-118277.6"
wire $0\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:119130.7-119130.20"
+ attribute \src "libresoc.v:117755.7-117755.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:119666.3-119680.6"
+ attribute \src "libresoc.v:118291.3-118305.6"
wire width 13 $1\ALU__fn_unit[12:0]
- attribute \src "libresoc.v:119653.3-119665.6"
+ attribute \src "libresoc.v:118278.3-118290.6"
wire width 7 $1\ALU__insn_type[6:0]
- attribute \src "libresoc.v:119638.3-119652.6"
+ attribute \src "libresoc.v:118263.3-118277.6"
wire $1\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:119555.18-119555.113"
- wire $and$libresoc.v:119555$4513_Y
- attribute \src "libresoc.v:119557.18-119557.110"
- wire $and$libresoc.v:119557$4515_Y
- attribute \src "libresoc.v:119570.18-119570.114"
- wire $and$libresoc.v:119570$4528_Y
- attribute \src "libresoc.v:119571.18-119571.116"
- wire $and$libresoc.v:119571$4529_Y
- attribute \src "libresoc.v:119573.18-119573.114"
- wire $and$libresoc.v:119573$4531_Y
- attribute \src "libresoc.v:119575.18-119575.110"
- wire $and$libresoc.v:119575$4533_Y
- attribute \src "libresoc.v:119576.17-119576.112"
- wire $and$libresoc.v:119576$4534_Y
- attribute \src "libresoc.v:119577.17-119577.114"
- wire $and$libresoc.v:119577$4535_Y
- attribute \src "libresoc.v:119558.18-119558.126"
- wire $eq$libresoc.v:119558$4516_Y
- attribute \src "libresoc.v:119559.18-119559.126"
- wire $eq$libresoc.v:119559$4517_Y
- attribute \src "libresoc.v:119561.18-119561.110"
- wire $eq$libresoc.v:119561$4519_Y
- attribute \src "libresoc.v:119562.18-119562.110"
- wire $eq$libresoc.v:119562$4520_Y
- attribute \src "libresoc.v:119564.18-119564.112"
- wire $eq$libresoc.v:119564$4522_Y
- attribute \src "libresoc.v:119565.17-119565.130"
- wire $eq$libresoc.v:119565$4523_Y
- attribute \src "libresoc.v:119567.18-119567.110"
- wire $eq$libresoc.v:119567$4525_Y
- attribute \src "libresoc.v:119569.18-119569.131"
- wire $eq$libresoc.v:119569$4527_Y
- attribute \src "libresoc.v:119572.18-119572.131"
- wire $eq$libresoc.v:119572$4530_Y
- attribute \src "libresoc.v:119578.17-119578.130"
- wire $eq$libresoc.v:119578$4536_Y
- attribute \src "libresoc.v:119556.18-119556.110"
- wire $not$libresoc.v:119556$4514_Y
- attribute \src "libresoc.v:119574.18-119574.110"
- wire $not$libresoc.v:119574$4532_Y
- attribute \src "libresoc.v:119560.18-119560.110"
- wire $or$libresoc.v:119560$4518_Y
- attribute \src "libresoc.v:119563.18-119563.110"
- wire $or$libresoc.v:119563$4521_Y
- attribute \src "libresoc.v:119566.18-119566.110"
- wire $or$libresoc.v:119566$4524_Y
- attribute \src "libresoc.v:119568.18-119568.110"
- wire $or$libresoc.v:119568$4526_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:118180.18-118180.113"
+ wire $and$libresoc.v:118180$4457_Y
+ attribute \src "libresoc.v:118182.18-118182.110"
+ wire $and$libresoc.v:118182$4459_Y
+ attribute \src "libresoc.v:118195.18-118195.114"
+ wire $and$libresoc.v:118195$4472_Y
+ attribute \src "libresoc.v:118196.18-118196.116"
+ wire $and$libresoc.v:118196$4473_Y
+ attribute \src "libresoc.v:118198.18-118198.114"
+ wire $and$libresoc.v:118198$4475_Y
+ attribute \src "libresoc.v:118200.18-118200.110"
+ wire $and$libresoc.v:118200$4477_Y
+ attribute \src "libresoc.v:118201.17-118201.112"
+ wire $and$libresoc.v:118201$4478_Y
+ attribute \src "libresoc.v:118202.17-118202.114"
+ wire $and$libresoc.v:118202$4479_Y
+ attribute \src "libresoc.v:118183.18-118183.126"
+ wire $eq$libresoc.v:118183$4460_Y
+ attribute \src "libresoc.v:118184.18-118184.126"
+ wire $eq$libresoc.v:118184$4461_Y
+ attribute \src "libresoc.v:118186.18-118186.110"
+ wire $eq$libresoc.v:118186$4463_Y
+ attribute \src "libresoc.v:118187.18-118187.110"
+ wire $eq$libresoc.v:118187$4464_Y
+ attribute \src "libresoc.v:118189.18-118189.112"
+ wire $eq$libresoc.v:118189$4466_Y
+ attribute \src "libresoc.v:118190.17-118190.130"
+ wire $eq$libresoc.v:118190$4467_Y
+ attribute \src "libresoc.v:118192.18-118192.110"
+ wire $eq$libresoc.v:118192$4469_Y
+ attribute \src "libresoc.v:118194.18-118194.131"
+ wire $eq$libresoc.v:118194$4471_Y
+ attribute \src "libresoc.v:118197.18-118197.131"
+ wire $eq$libresoc.v:118197$4474_Y
+ attribute \src "libresoc.v:118203.17-118203.130"
+ wire $eq$libresoc.v:118203$4480_Y
+ attribute \src "libresoc.v:118181.18-118181.110"
+ wire $not$libresoc.v:118181$4458_Y
+ attribute \src "libresoc.v:118199.18-118199.110"
+ wire $not$libresoc.v:118199$4476_Y
+ attribute \src "libresoc.v:118185.18-118185.110"
+ wire $or$libresoc.v:118185$4462_Y
+ attribute \src "libresoc.v:118188.18-118188.110"
+ wire $or$libresoc.v:118188$4465_Y
+ attribute \src "libresoc.v:118191.18-118191.110"
+ wire $or$libresoc.v:118191$4468_Y
+ attribute \src "libresoc.v:118193.18-118193.110"
+ wire $or$libresoc.v:118193$4470_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 18 \ALU__data_len
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:119130.7-119130.15"
+ attribute \src "libresoc.v:117755.7-117755.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 20 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:119555$4513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118180$4457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:119555$4513_Y
+ connect \Y $and$libresoc.v:118180$4457_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:119557$4515
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118182$4459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:119557$4515_Y
+ connect \Y $and$libresoc.v:118182$4459_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:119570$4528
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118195$4472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:119570$4528_Y
+ connect \Y $and$libresoc.v:118195$4472_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:119571$4529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118196$4473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:119571$4529_Y
+ connect \Y $and$libresoc.v:118196$4473_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118198$4475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:119573$4531_Y
+ connect \Y $and$libresoc.v:118198$4475_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118200$4477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:119575$4533_Y
+ connect \Y $and$libresoc.v:118200$4477_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:119576$4534_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:119577$4535_Y
+ connect \Y $and$libresoc.v:118202$4479_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:119558$4516_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:119559$4517_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
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parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:119561$4519_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
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parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:119562$4520_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:118189$4466
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:119565$4523_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
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parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:119569$4527_Y
+ connect \Y $eq$libresoc.v:118194$4471_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
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parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:119572$4530_Y
+ connect \Y $eq$libresoc.v:118197$4474_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
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parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_ALU_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:119578$4536_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
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+ connect \Y $not$libresoc.v:118199$4476_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
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+ connect \Y $or$libresoc.v:118185$4462_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:119568$4526_Y
+ connect \Y $or$libresoc.v:118193$4470_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:119579.7-119607.4"
+ attribute \src "libresoc.v:118204.7-118232.4"
cell \dec \dec
connect \ALU_BD \dec_ALU_BD
connect \ALU_DS \dec_ALU_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:119608.10-119612.4"
+ attribute \src "libresoc.v:118233.10-118237.4"
cell \dec_ai \dec_ai
connect \ALU_RA \dec_ALU_RA
connect \immz_out \dec_ai_immz_out
connect \sel_in \dec_ai_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:119613.10-119624.4"
+ attribute \src "libresoc.v:118238.10-118249.4"
cell \dec_bi \dec_bi
connect \ALU_BD \dec_ALU_BD
connect \ALU_DS \dec_ALU_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:119625.10-119631.4"
+ attribute \src "libresoc.v:118250.10-118256.4"
cell \dec_oe \dec_oe
connect \ALU_OE \dec_ALU_OE
connect \ALU_internal_op \dec_ALU_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:119632.10-119637.4"
+ attribute \src "libresoc.v:118257.10-118262.4"
cell \dec_rc \dec_rc
connect \ALU_Rc \dec_ALU_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:119130.7-119130.20"
- process $proc$libresoc.v:119130$4540
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assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:119638.3-119652.6"
- process $proc$libresoc.v:119638$4537
+ attribute \src "libresoc.v:118263.3-118277.6"
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assign { } { }
assign { } { }
assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0]
- attribute \src "libresoc.v:119639.5-119639.29"
+ attribute \src "libresoc.v:118264.5-118264.29"
switch \initial
- attribute \src "libresoc.v:119639.9-119639.17"
+ attribute \src "libresoc.v:118264.9-118264.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
switch \dec_ALU_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
sync always
update \ALU__write_cr0 $0\ALU__write_cr0[0:0]
end
- attribute \src "libresoc.v:119653.3-119665.6"
- process $proc$libresoc.v:119653$4538
+ attribute \src "libresoc.v:118278.3-118290.6"
+ process $proc$libresoc.v:118278$4482
assign { } { }
assign { } { }
assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0]
- attribute \src "libresoc.v:119654.5-119654.29"
+ attribute \src "libresoc.v:118279.5-118279.29"
switch \initial
- attribute \src "libresoc.v:119654.9-119654.17"
+ attribute \src "libresoc.v:118279.9-118279.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \ALU__insn_type $0\ALU__insn_type[6:0]
end
- attribute \src "libresoc.v:119666.3-119680.6"
- process $proc$libresoc.v:119666$4539
+ attribute \src "libresoc.v:118291.3-118305.6"
+ process $proc$libresoc.v:118291$4483
assign { } { }
assign $0\ALU__fn_unit[12:0] $1\ALU__fn_unit[12:0]
- attribute \src "libresoc.v:119667.5-119667.29"
+ attribute \src "libresoc.v:118292.5-118292.29"
switch \initial
- attribute \src "libresoc.v:119667.9-119667.17"
+ attribute \src "libresoc.v:118292.9-118292.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \ALU__fn_unit $0\ALU__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:119555$4513_Y
- connect \$12 $not$libresoc.v:119556$4514_Y
- connect \$14 $and$libresoc.v:119557$4515_Y
- connect \$16 $eq$libresoc.v:119558$4516_Y
- connect \$18 $eq$libresoc.v:119559$4517_Y
- connect \$20 $or$libresoc.v:119560$4518_Y
- connect \$22 $eq$libresoc.v:119561$4519_Y
- connect \$24 $eq$libresoc.v:119562$4520_Y
- connect \$26 $or$libresoc.v:119563$4521_Y
- connect \$28 $eq$libresoc.v:119564$4522_Y
- connect \$2 $eq$libresoc.v:119565$4523_Y
- connect \$30 $or$libresoc.v:119566$4524_Y
- connect \$32 $eq$libresoc.v:119567$4525_Y
- connect \$34 $or$libresoc.v:119568$4526_Y
- connect \$36 $eq$libresoc.v:119569$4527_Y
- connect \$38 $and$libresoc.v:119570$4528_Y
- connect \$40 $and$libresoc.v:119571$4529_Y
- connect \$42 $eq$libresoc.v:119572$4530_Y
- connect \$44 $and$libresoc.v:119573$4531_Y
- connect \$46 $not$libresoc.v:119574$4532_Y
- connect \$48 $and$libresoc.v:119575$4533_Y
- connect \$4 $and$libresoc.v:119576$4534_Y
- connect \$6 $and$libresoc.v:119577$4535_Y
- connect \$8 $eq$libresoc.v:119578$4536_Y
+ connect \$10 $and$libresoc.v:118180$4457_Y
+ connect \$12 $not$libresoc.v:118181$4458_Y
+ connect \$14 $and$libresoc.v:118182$4459_Y
+ connect \$16 $eq$libresoc.v:118183$4460_Y
+ connect \$18 $eq$libresoc.v:118184$4461_Y
+ connect \$20 $or$libresoc.v:118185$4462_Y
+ connect \$22 $eq$libresoc.v:118186$4463_Y
+ connect \$24 $eq$libresoc.v:118187$4464_Y
+ connect \$26 $or$libresoc.v:118188$4465_Y
+ connect \$28 $eq$libresoc.v:118189$4466_Y
+ connect \$2 $eq$libresoc.v:118190$4467_Y
+ connect \$30 $or$libresoc.v:118191$4468_Y
+ connect \$32 $eq$libresoc.v:118192$4469_Y
+ connect \$34 $or$libresoc.v:118193$4470_Y
+ connect \$36 $eq$libresoc.v:118194$4471_Y
+ connect \$38 $and$libresoc.v:118195$4472_Y
+ connect \$40 $and$libresoc.v:118196$4473_Y
+ connect \$42 $eq$libresoc.v:118197$4474_Y
+ connect \$44 $and$libresoc.v:118198$4475_Y
+ connect \$46 $not$libresoc.v:118199$4476_Y
+ connect \$48 $and$libresoc.v:118200$4477_Y
+ connect \$4 $and$libresoc.v:118201$4478_Y
+ connect \$6 $and$libresoc.v:118202$4479_Y
+ connect \$8 $eq$libresoc.v:118203$4480_Y
connect \ALU__is_signed \dec_ALU_sgn
connect \ALU__is_32bit \dec_ALU_is_32b
connect \ALU__output_carry \dec_ALU_cry_out
connect \insn_in \dec_opcode_in
connect \ALU__insn \dec_opcode_in
end
-attribute \src "libresoc.v:119706.1-120182.10"
+attribute \src "libresoc.v:118331.1-118807.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH"
attribute \generator "nMigen"
module \dec_BRANCH
- attribute \src "libresoc.v:120132.3-120146.6"
+ attribute \src "libresoc.v:118757.3-118771.6"
wire width 13 $0\BRANCH__fn_unit[12:0]
- attribute \src "libresoc.v:120157.3-120169.6"
+ attribute \src "libresoc.v:118782.3-118794.6"
wire width 7 $0\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:120147.3-120156.6"
+ attribute \src "libresoc.v:118772.3-118781.6"
wire $0\BRANCH__lk[0:0]
- attribute \src "libresoc.v:119707.7-119707.20"
+ attribute \src "libresoc.v:118332.7-118332.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:120132.3-120146.6"
+ attribute \src "libresoc.v:118757.3-118771.6"
wire width 13 $1\BRANCH__fn_unit[12:0]
- attribute \src "libresoc.v:120157.3-120169.6"
+ attribute \src "libresoc.v:118782.3-118794.6"
wire width 7 $1\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:120147.3-120156.6"
+ attribute \src "libresoc.v:118772.3-118781.6"
wire $1\BRANCH__lk[0:0]
- attribute \src "libresoc.v:120064.18-120064.113"
- wire $and$libresoc.v:120064$4541_Y
- attribute \src "libresoc.v:120066.18-120066.110"
- wire $and$libresoc.v:120066$4543_Y
- attribute \src "libresoc.v:120079.18-120079.114"
- wire $and$libresoc.v:120079$4556_Y
- attribute \src "libresoc.v:120080.18-120080.116"
- wire $and$libresoc.v:120080$4557_Y
- attribute \src "libresoc.v:120082.18-120082.114"
- wire $and$libresoc.v:120082$4559_Y
- attribute \src "libresoc.v:120084.18-120084.110"
- wire $and$libresoc.v:120084$4561_Y
- attribute \src "libresoc.v:120085.17-120085.112"
- wire $and$libresoc.v:120085$4562_Y
- attribute \src "libresoc.v:120086.17-120086.114"
- wire $and$libresoc.v:120086$4563_Y
- attribute \src "libresoc.v:120067.18-120067.129"
- wire $eq$libresoc.v:120067$4544_Y
- attribute \src "libresoc.v:120068.18-120068.129"
- wire $eq$libresoc.v:120068$4545_Y
- attribute \src "libresoc.v:120070.18-120070.110"
- wire $eq$libresoc.v:120070$4547_Y
- attribute \src "libresoc.v:120071.18-120071.110"
- wire $eq$libresoc.v:120071$4548_Y
- attribute \src "libresoc.v:120073.18-120073.112"
- wire $eq$libresoc.v:120073$4550_Y
- attribute \src "libresoc.v:120074.17-120074.133"
- wire $eq$libresoc.v:120074$4551_Y
- attribute \src "libresoc.v:120076.18-120076.110"
- wire $eq$libresoc.v:120076$4553_Y
- attribute \src "libresoc.v:120078.18-120078.134"
- wire $eq$libresoc.v:120078$4555_Y
- attribute \src "libresoc.v:120081.18-120081.134"
- wire $eq$libresoc.v:120081$4558_Y
- attribute \src "libresoc.v:120087.17-120087.133"
- wire $eq$libresoc.v:120087$4564_Y
- attribute \src "libresoc.v:120065.18-120065.110"
- wire $not$libresoc.v:120065$4542_Y
- attribute \src "libresoc.v:120083.18-120083.110"
- wire $not$libresoc.v:120083$4560_Y
- attribute \src "libresoc.v:120069.18-120069.110"
- wire $or$libresoc.v:120069$4546_Y
- attribute \src "libresoc.v:120072.18-120072.110"
- wire $or$libresoc.v:120072$4549_Y
- attribute \src "libresoc.v:120075.18-120075.110"
- wire $or$libresoc.v:120075$4552_Y
- attribute \src "libresoc.v:120077.18-120077.110"
- wire $or$libresoc.v:120077$4554_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:118689.18-118689.113"
+ wire $and$libresoc.v:118689$4485_Y
+ attribute \src "libresoc.v:118691.18-118691.110"
+ wire $and$libresoc.v:118691$4487_Y
+ attribute \src "libresoc.v:118704.18-118704.114"
+ wire $and$libresoc.v:118704$4500_Y
+ attribute \src "libresoc.v:118705.18-118705.116"
+ wire $and$libresoc.v:118705$4501_Y
+ attribute \src "libresoc.v:118707.18-118707.114"
+ wire $and$libresoc.v:118707$4503_Y
+ attribute \src "libresoc.v:118709.18-118709.110"
+ wire $and$libresoc.v:118709$4505_Y
+ attribute \src "libresoc.v:118710.17-118710.112"
+ wire $and$libresoc.v:118710$4506_Y
+ attribute \src "libresoc.v:118711.17-118711.114"
+ wire $and$libresoc.v:118711$4507_Y
+ attribute \src "libresoc.v:118692.18-118692.129"
+ wire $eq$libresoc.v:118692$4488_Y
+ attribute \src "libresoc.v:118693.18-118693.129"
+ wire $eq$libresoc.v:118693$4489_Y
+ attribute \src "libresoc.v:118695.18-118695.110"
+ wire $eq$libresoc.v:118695$4491_Y
+ attribute \src "libresoc.v:118696.18-118696.110"
+ wire $eq$libresoc.v:118696$4492_Y
+ attribute \src "libresoc.v:118698.18-118698.112"
+ wire $eq$libresoc.v:118698$4494_Y
+ attribute \src "libresoc.v:118699.17-118699.133"
+ wire $eq$libresoc.v:118699$4495_Y
+ attribute \src "libresoc.v:118701.18-118701.110"
+ wire $eq$libresoc.v:118701$4497_Y
+ attribute \src "libresoc.v:118703.18-118703.134"
+ wire $eq$libresoc.v:118703$4499_Y
+ attribute \src "libresoc.v:118706.18-118706.134"
+ wire $eq$libresoc.v:118706$4502_Y
+ attribute \src "libresoc.v:118712.17-118712.133"
+ wire $eq$libresoc.v:118712$4508_Y
+ attribute \src "libresoc.v:118690.18-118690.110"
+ wire $not$libresoc.v:118690$4486_Y
+ attribute \src "libresoc.v:118708.18-118708.110"
+ wire $not$libresoc.v:118708$4504_Y
+ attribute \src "libresoc.v:118694.18-118694.110"
+ wire $or$libresoc.v:118694$4490_Y
+ attribute \src "libresoc.v:118697.18-118697.110"
+ wire $or$libresoc.v:118697$4493_Y
+ attribute \src "libresoc.v:118700.18-118700.110"
+ wire $or$libresoc.v:118700$4496_Y
+ attribute \src "libresoc.v:118702.18-118702.110"
+ wire $or$libresoc.v:118702$4498_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 64 output 3 \BRANCH__cia
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:119707.7-119707.15"
+ attribute \src "libresoc.v:118332.7-118332.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 1 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120064$4541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118689$4485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:120064$4541_Y
+ connect \Y $and$libresoc.v:118689$4485_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120066$4543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118691$4487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:120066$4543_Y
+ connect \Y $and$libresoc.v:118691$4487_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120079$4556
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118704$4500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:120079$4556_Y
+ connect \Y $and$libresoc.v:118704$4500_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120080$4557
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118705$4501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:120080$4557_Y
+ connect \Y $and$libresoc.v:118705$4501_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120082$4559
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118707$4503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:120082$4559_Y
+ connect \Y $and$libresoc.v:118707$4503_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120084$4561
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:118709$4505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:120084$4561_Y
+ connect \Y $and$libresoc.v:118709$4505_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120085$4562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118710$4506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:120085$4562_Y
+ connect \Y $and$libresoc.v:118710$4506_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120086$4563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:118711$4507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:120086$4563_Y
+ connect \Y $and$libresoc.v:118711$4507_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:120067$4544
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:118692$4488
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:120067$4544_Y
+ connect \Y $eq$libresoc.v:118692$4488_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:120068$4545
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:118693$4489
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:120068$4545_Y
+ connect \Y $eq$libresoc.v:118693$4489_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120070$4547
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:118695$4491
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:120070$4547_Y
+ connect \Y $eq$libresoc.v:118695$4491_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120071$4548
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:118696$4492
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:120071$4548_Y
+ connect \Y $eq$libresoc.v:118696$4492_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120073$4550
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:118698$4494
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:120073$4550_Y
+ connect \Y $eq$libresoc.v:118698$4494_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120074$4551
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:118699$4495
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120074$4551_Y
+ connect \Y $eq$libresoc.v:118699$4495_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:120076$4553
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:118701$4497
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:120076$4553_Y
+ connect \Y $eq$libresoc.v:118701$4497_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120078$4555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:118703$4499
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120078$4555_Y
+ connect \Y $eq$libresoc.v:118703$4499_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:120081$4558
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:118706$4502
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:120081$4558_Y
+ connect \Y $eq$libresoc.v:118706$4502_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:120087$4564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:118712$4508
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_BRANCH_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:120087$4564_Y
+ connect \Y $eq$libresoc.v:118712$4508_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:120065$4542
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:118690$4486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:120065$4542_Y
+ connect \Y $not$libresoc.v:118690$4486_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:120083$4560
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:118708$4504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:120083$4560_Y
+ connect \Y $not$libresoc.v:118708$4504_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:120069$4546
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:118694$4490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:120069$4546_Y
+ connect \Y $or$libresoc.v:118694$4490_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120072$4549
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:118697$4493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:120072$4549_Y
+ connect \Y $or$libresoc.v:118697$4493_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120075$4552
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:118700$4496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:120075$4552_Y
+ connect \Y $or$libresoc.v:118700$4496_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:120077$4554
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:118702$4498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:120077$4554_Y
+ connect \Y $or$libresoc.v:118702$4498_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120088.13-120110.4"
+ attribute \src "libresoc.v:118713.13-118735.4"
cell \dec$141 \dec
connect \BRANCH_BD \dec_BRANCH_BD
connect \BRANCH_DS \dec_BRANCH_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120111.16-120122.4"
+ attribute \src "libresoc.v:118736.16-118747.4"
cell \dec_bi$144 \dec_bi
connect \BRANCH_BD \dec_BRANCH_BD
connect \BRANCH_DS \dec_BRANCH_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120123.16-120127.4"
+ attribute \src "libresoc.v:118748.16-118752.4"
cell \dec_oe$143 \dec_oe
connect \BRANCH_OE \dec_BRANCH_OE
connect \BRANCH_internal_op \dec_BRANCH_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120128.16-120131.4"
+ attribute \src "libresoc.v:118753.16-118756.4"
cell \dec_rc$142 \dec_rc
connect \BRANCH_Rc \dec_BRANCH_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:119707.7-119707.20"
- process $proc$libresoc.v:119707$4568
+ attribute \src "libresoc.v:118332.7-118332.20"
+ process $proc$libresoc.v:118332$4512
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:120132.3-120146.6"
- process $proc$libresoc.v:120132$4565
+ attribute \src "libresoc.v:118757.3-118771.6"
+ process $proc$libresoc.v:118757$4509
assign { } { }
assign $0\BRANCH__fn_unit[12:0] $1\BRANCH__fn_unit[12:0]
- attribute \src "libresoc.v:120133.5-120133.29"
+ attribute \src "libresoc.v:118758.5-118758.29"
switch \initial
- attribute \src "libresoc.v:120133.9-120133.17"
+ attribute \src "libresoc.v:118758.9-118758.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \BRANCH__fn_unit $0\BRANCH__fn_unit[12:0]
end
- attribute \src "libresoc.v:120147.3-120156.6"
- process $proc$libresoc.v:120147$4566
+ attribute \src "libresoc.v:118772.3-118781.6"
+ process $proc$libresoc.v:118772$4510
assign { } { }
assign { } { }
assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0]
- attribute \src "libresoc.v:120148.5-120148.29"
+ attribute \src "libresoc.v:118773.5-118773.29"
switch \initial
- attribute \src "libresoc.v:120148.9-120148.17"
+ attribute \src "libresoc.v:118773.9-118773.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:857"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863"
switch \dec_BRANCH_lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \BRANCH__lk $0\BRANCH__lk[0:0]
end
- attribute \src "libresoc.v:120157.3-120169.6"
- process $proc$libresoc.v:120157$4567
+ attribute \src "libresoc.v:118782.3-118794.6"
+ process $proc$libresoc.v:118782$4511
assign { } { }
assign { } { }
assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0]
- attribute \src "libresoc.v:120158.5-120158.29"
+ attribute \src "libresoc.v:118783.5-118783.29"
switch \initial
- attribute \src "libresoc.v:120158.9-120158.17"
+ attribute \src "libresoc.v:118783.9-118783.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \BRANCH__insn_type $0\BRANCH__insn_type[6:0]
end
- connect \$10 $and$libresoc.v:120064$4541_Y
- connect \$12 $not$libresoc.v:120065$4542_Y
- connect \$14 $and$libresoc.v:120066$4543_Y
- connect \$16 $eq$libresoc.v:120067$4544_Y
- connect \$18 $eq$libresoc.v:120068$4545_Y
- connect \$20 $or$libresoc.v:120069$4546_Y
- connect \$22 $eq$libresoc.v:120070$4547_Y
- connect \$24 $eq$libresoc.v:120071$4548_Y
- connect \$26 $or$libresoc.v:120072$4549_Y
- connect \$28 $eq$libresoc.v:120073$4550_Y
- connect \$2 $eq$libresoc.v:120074$4551_Y
- connect \$30 $or$libresoc.v:120075$4552_Y
- connect \$32 $eq$libresoc.v:120076$4553_Y
- connect \$34 $or$libresoc.v:120077$4554_Y
- connect \$36 $eq$libresoc.v:120078$4555_Y
- connect \$38 $and$libresoc.v:120079$4556_Y
- connect \$40 $and$libresoc.v:120080$4557_Y
- connect \$42 $eq$libresoc.v:120081$4558_Y
- connect \$44 $and$libresoc.v:120082$4559_Y
- connect \$46 $not$libresoc.v:120083$4560_Y
- connect \$48 $and$libresoc.v:120084$4561_Y
- connect \$4 $and$libresoc.v:120085$4562_Y
- connect \$6 $and$libresoc.v:120086$4563_Y
- connect \$8 $eq$libresoc.v:120087$4564_Y
+ connect \$10 $and$libresoc.v:118689$4485_Y
+ connect \$12 $not$libresoc.v:118690$4486_Y
+ connect \$14 $and$libresoc.v:118691$4487_Y
+ connect \$16 $eq$libresoc.v:118692$4488_Y
+ connect \$18 $eq$libresoc.v:118693$4489_Y
+ connect \$20 $or$libresoc.v:118694$4490_Y
+ connect \$22 $eq$libresoc.v:118695$4491_Y
+ connect \$24 $eq$libresoc.v:118696$4492_Y
+ connect \$26 $or$libresoc.v:118697$4493_Y
+ connect \$28 $eq$libresoc.v:118698$4494_Y
+ connect \$2 $eq$libresoc.v:118699$4495_Y
+ connect \$30 $or$libresoc.v:118700$4496_Y
+ connect \$32 $eq$libresoc.v:118701$4497_Y
+ connect \$34 $or$libresoc.v:118702$4498_Y
+ connect \$36 $eq$libresoc.v:118703$4499_Y
+ connect \$38 $and$libresoc.v:118704$4500_Y
+ connect \$40 $and$libresoc.v:118705$4501_Y
+ connect \$42 $eq$libresoc.v:118706$4502_Y
+ connect \$44 $and$libresoc.v:118707$4503_Y
+ connect \$46 $not$libresoc.v:118708$4504_Y
+ connect \$48 $and$libresoc.v:118709$4505_Y
+ connect \$4 $and$libresoc.v:118710$4506_Y
+ connect \$6 $and$libresoc.v:118711$4507_Y
+ connect \$8 $eq$libresoc.v:118712$4508_Y
connect \BRANCH__is_32bit \dec_BRANCH_is_32b
connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b }
connect \dec_bi_sel_in \dec_BRANCH_in2_sel
connect \insn_in \dec_opcode_in
connect \BRANCH__insn \dec_opcode_in
end
-attribute \src "libresoc.v:120186.1-120554.10"
+attribute \src "libresoc.v:118811.1-119179.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR"
attribute \generator "nMigen"
module \dec_CR
- attribute \src "libresoc.v:120531.3-120545.6"
+ attribute \src "libresoc.v:119156.3-119170.6"
wire width 13 $0\CR__fn_unit[12:0]
- attribute \src "libresoc.v:120518.3-120530.6"
+ attribute \src "libresoc.v:119143.3-119155.6"
wire width 7 $0\CR__insn_type[6:0]
- attribute \src "libresoc.v:120187.7-120187.20"
+ attribute \src "libresoc.v:118812.7-118812.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:120531.3-120545.6"
+ attribute \src "libresoc.v:119156.3-119170.6"
wire width 13 $1\CR__fn_unit[12:0]
- attribute \src "libresoc.v:120518.3-120530.6"
+ attribute \src "libresoc.v:119143.3-119155.6"
wire width 7 $1\CR__insn_type[6:0]
- attribute \src "libresoc.v:120473.18-120473.113"
- wire $and$libresoc.v:120473$4569_Y
- attribute \src "libresoc.v:120475.18-120475.110"
- wire $and$libresoc.v:120475$4571_Y
- attribute \src "libresoc.v:120488.18-120488.114"
- wire $and$libresoc.v:120488$4584_Y
- attribute \src "libresoc.v:120489.18-120489.116"
- wire $and$libresoc.v:120489$4585_Y
- attribute \src "libresoc.v:120491.18-120491.114"
- wire $and$libresoc.v:120491$4587_Y
- attribute \src "libresoc.v:120493.18-120493.110"
- wire $and$libresoc.v:120493$4589_Y
- attribute \src "libresoc.v:120494.17-120494.112"
- wire $and$libresoc.v:120494$4590_Y
- attribute \src "libresoc.v:120495.17-120495.114"
- wire $and$libresoc.v:120495$4591_Y
- attribute \src "libresoc.v:120476.18-120476.125"
- wire $eq$libresoc.v:120476$4572_Y
- attribute \src "libresoc.v:120477.18-120477.125"
- wire $eq$libresoc.v:120477$4573_Y
- attribute \src "libresoc.v:120479.18-120479.110"
- wire $eq$libresoc.v:120479$4575_Y
- attribute \src "libresoc.v:120480.18-120480.110"
- wire $eq$libresoc.v:120480$4576_Y
- attribute \src "libresoc.v:120482.18-120482.112"
- wire $eq$libresoc.v:120482$4578_Y
- attribute \src "libresoc.v:120483.17-120483.129"
- wire $eq$libresoc.v:120483$4579_Y
- attribute \src "libresoc.v:120485.18-120485.110"
- wire $eq$libresoc.v:120485$4581_Y
- attribute \src "libresoc.v:120487.18-120487.130"
- wire $eq$libresoc.v:120487$4583_Y
- attribute \src "libresoc.v:120490.18-120490.130"
- wire $eq$libresoc.v:120490$4586_Y
- attribute \src "libresoc.v:120496.17-120496.129"
- wire $eq$libresoc.v:120496$4592_Y
- attribute \src "libresoc.v:120474.18-120474.110"
- wire $not$libresoc.v:120474$4570_Y
- attribute \src "libresoc.v:120492.18-120492.110"
- wire $not$libresoc.v:120492$4588_Y
- attribute \src "libresoc.v:120478.18-120478.110"
- wire $or$libresoc.v:120478$4574_Y
- attribute \src "libresoc.v:120481.18-120481.110"
- wire $or$libresoc.v:120481$4577_Y
- attribute \src "libresoc.v:120484.18-120484.110"
- wire $or$libresoc.v:120484$4580_Y
- attribute \src "libresoc.v:120486.18-120486.110"
- wire $or$libresoc.v:120486$4582_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:119098.18-119098.113"
+ wire $and$libresoc.v:119098$4513_Y
+ attribute \src "libresoc.v:119100.18-119100.110"
+ wire $and$libresoc.v:119100$4515_Y
+ attribute \src "libresoc.v:119113.18-119113.114"
+ wire $and$libresoc.v:119113$4528_Y
+ attribute \src "libresoc.v:119114.18-119114.116"
+ wire $and$libresoc.v:119114$4529_Y
+ attribute \src "libresoc.v:119116.18-119116.114"
+ wire $and$libresoc.v:119116$4531_Y
+ attribute \src "libresoc.v:119118.18-119118.110"
+ wire $and$libresoc.v:119118$4533_Y
+ attribute \src "libresoc.v:119119.17-119119.112"
+ wire $and$libresoc.v:119119$4534_Y
+ attribute \src "libresoc.v:119120.17-119120.114"
+ wire $and$libresoc.v:119120$4535_Y
+ attribute \src "libresoc.v:119101.18-119101.125"
+ wire $eq$libresoc.v:119101$4516_Y
+ attribute \src "libresoc.v:119102.18-119102.125"
+ wire $eq$libresoc.v:119102$4517_Y
+ attribute \src "libresoc.v:119104.18-119104.110"
+ wire $eq$libresoc.v:119104$4519_Y
+ attribute \src "libresoc.v:119105.18-119105.110"
+ wire $eq$libresoc.v:119105$4520_Y
+ attribute \src "libresoc.v:119107.18-119107.112"
+ wire $eq$libresoc.v:119107$4522_Y
+ attribute \src "libresoc.v:119108.17-119108.129"
+ wire $eq$libresoc.v:119108$4523_Y
+ attribute \src "libresoc.v:119110.18-119110.110"
+ wire $eq$libresoc.v:119110$4525_Y
+ attribute \src "libresoc.v:119112.18-119112.130"
+ wire $eq$libresoc.v:119112$4527_Y
+ attribute \src "libresoc.v:119115.18-119115.130"
+ wire $eq$libresoc.v:119115$4530_Y
+ attribute \src "libresoc.v:119121.17-119121.129"
+ wire $eq$libresoc.v:119121$4536_Y
+ attribute \src "libresoc.v:119099.18-119099.110"
+ wire $not$libresoc.v:119099$4514_Y
+ attribute \src "libresoc.v:119117.18-119117.110"
+ wire $not$libresoc.v:119117$4532_Y
+ attribute \src "libresoc.v:119103.18-119103.110"
+ wire $or$libresoc.v:119103$4518_Y
+ attribute \src "libresoc.v:119106.18-119106.110"
+ wire $or$libresoc.v:119106$4521_Y
+ attribute \src "libresoc.v:119109.18-119109.110"
+ wire $or$libresoc.v:119109$4524_Y
+ attribute \src "libresoc.v:119111.18-119111.110"
+ wire $or$libresoc.v:119111$4526_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:120187.7-120187.15"
+ attribute \src "libresoc.v:118812.7-118812.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 5 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120473$4569
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119098$4513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:120473$4569_Y
+ connect \Y $and$libresoc.v:119098$4513_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120475$4571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119100$4515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:120475$4571_Y
+ connect \Y $and$libresoc.v:119100$4515_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120488$4584
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119113$4528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:120488$4584_Y
+ connect \Y $and$libresoc.v:119113$4528_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120489$4585
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119114$4529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:120489$4585_Y
+ connect \Y $and$libresoc.v:119114$4529_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120491$4587
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119116$4531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:120491$4587_Y
+ connect \Y $and$libresoc.v:119116$4531_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120493$4589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119118$4533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:120493$4589_Y
+ connect \Y $and$libresoc.v:119118$4533_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120494$4590
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119119$4534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:120494$4590_Y
+ connect \Y $and$libresoc.v:119119$4534_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120495$4591
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119120$4535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:120495$4591_Y
+ connect \Y $and$libresoc.v:119120$4535_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:120476$4572
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:119101$4516
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:120476$4572_Y
+ connect \Y $eq$libresoc.v:119101$4516_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:120477$4573
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:119102$4517
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:120477$4573_Y
+ connect \Y $eq$libresoc.v:119102$4517_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120479$4575
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119104$4519
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:120479$4575_Y
+ connect \Y $eq$libresoc.v:119104$4519_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120480$4576
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119105$4520
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:120480$4576_Y
+ connect \Y $eq$libresoc.v:119105$4520_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120482$4578
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119107$4522
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:120482$4578_Y
+ connect \Y $eq$libresoc.v:119107$4522_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120483$4579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:119108$4523
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120483$4579_Y
+ connect \Y $eq$libresoc.v:119108$4523_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:120485$4581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:119110$4525
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:120485$4581_Y
+ connect \Y $eq$libresoc.v:119110$4525_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120487$4583
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:119112$4527
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120487$4583_Y
+ connect \Y $eq$libresoc.v:119112$4527_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:120490$4586
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:119115$4530
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:120490$4586_Y
+ connect \Y $eq$libresoc.v:119115$4530_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:120496$4592
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:119121$4536
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_CR_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:120496$4592_Y
+ connect \Y $eq$libresoc.v:119121$4536_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:120474$4570
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:119099$4514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:120474$4570_Y
+ connect \Y $not$libresoc.v:119099$4514_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:120492$4588
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:119117$4532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:120492$4588_Y
+ connect \Y $not$libresoc.v:119117$4532_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:120478$4574
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:119103$4518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:120478$4574_Y
+ connect \Y $or$libresoc.v:119103$4518_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120481$4577
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:119106$4521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:120481$4577_Y
+ connect \Y $or$libresoc.v:119106$4521_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120484$4580
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:119109$4524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:120484$4580_Y
+ connect \Y $or$libresoc.v:119109$4524_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:120486$4582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:119111$4526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:120486$4582_Y
+ connect \Y $or$libresoc.v:119111$4526_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120497.13-120508.4"
+ attribute \src "libresoc.v:119122.13-119133.4"
cell \dec$138 \dec
connect \CR_OE \dec_CR_OE
connect \CR_Rc \dec_CR_Rc
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120509.16-120513.4"
+ attribute \src "libresoc.v:119134.16-119138.4"
cell \dec_oe$140 \dec_oe
connect \CR_OE \dec_CR_OE
connect \CR_internal_op \dec_CR_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:120514.16-120517.4"
+ attribute \src "libresoc.v:119139.16-119142.4"
cell \dec_rc$139 \dec_rc
connect \CR_Rc \dec_CR_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:120187.7-120187.20"
- process $proc$libresoc.v:120187$4595
+ attribute \src "libresoc.v:118812.7-118812.20"
+ process $proc$libresoc.v:118812$4539
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:120518.3-120530.6"
- process $proc$libresoc.v:120518$4593
+ attribute \src "libresoc.v:119143.3-119155.6"
+ process $proc$libresoc.v:119143$4537
assign { } { }
assign { } { }
assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0]
- attribute \src "libresoc.v:120519.5-120519.29"
+ attribute \src "libresoc.v:119144.5-119144.29"
switch \initial
- attribute \src "libresoc.v:120519.9-120519.17"
+ attribute \src "libresoc.v:119144.9-119144.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \CR__insn_type $0\CR__insn_type[6:0]
end
- attribute \src "libresoc.v:120531.3-120545.6"
- process $proc$libresoc.v:120531$4594
+ attribute \src "libresoc.v:119156.3-119170.6"
+ process $proc$libresoc.v:119156$4538
assign { } { }
assign $0\CR__fn_unit[12:0] $1\CR__fn_unit[12:0]
- attribute \src "libresoc.v:120532.5-120532.29"
+ attribute \src "libresoc.v:119157.5-119157.29"
switch \initial
- attribute \src "libresoc.v:120532.9-120532.17"
+ attribute \src "libresoc.v:119157.9-119157.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \CR__fn_unit $0\CR__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:120473$4569_Y
- connect \$12 $not$libresoc.v:120474$4570_Y
- connect \$14 $and$libresoc.v:120475$4571_Y
- connect \$16 $eq$libresoc.v:120476$4572_Y
- connect \$18 $eq$libresoc.v:120477$4573_Y
- connect \$20 $or$libresoc.v:120478$4574_Y
- connect \$22 $eq$libresoc.v:120479$4575_Y
- connect \$24 $eq$libresoc.v:120480$4576_Y
- connect \$26 $or$libresoc.v:120481$4577_Y
- connect \$28 $eq$libresoc.v:120482$4578_Y
- connect \$2 $eq$libresoc.v:120483$4579_Y
- connect \$30 $or$libresoc.v:120484$4580_Y
- connect \$32 $eq$libresoc.v:120485$4581_Y
- connect \$34 $or$libresoc.v:120486$4582_Y
- connect \$36 $eq$libresoc.v:120487$4583_Y
- connect \$38 $and$libresoc.v:120488$4584_Y
- connect \$40 $and$libresoc.v:120489$4585_Y
- connect \$42 $eq$libresoc.v:120490$4586_Y
- connect \$44 $and$libresoc.v:120491$4587_Y
- connect \$46 $not$libresoc.v:120492$4588_Y
- connect \$48 $and$libresoc.v:120493$4589_Y
- connect \$4 $and$libresoc.v:120494$4590_Y
- connect \$6 $and$libresoc.v:120495$4591_Y
- connect \$8 $eq$libresoc.v:120496$4592_Y
+ connect \$10 $and$libresoc.v:119098$4513_Y
+ connect \$12 $not$libresoc.v:119099$4514_Y
+ connect \$14 $and$libresoc.v:119100$4515_Y
+ connect \$16 $eq$libresoc.v:119101$4516_Y
+ connect \$18 $eq$libresoc.v:119102$4517_Y
+ connect \$20 $or$libresoc.v:119103$4518_Y
+ connect \$22 $eq$libresoc.v:119104$4519_Y
+ connect \$24 $eq$libresoc.v:119105$4520_Y
+ connect \$26 $or$libresoc.v:119106$4521_Y
+ connect \$28 $eq$libresoc.v:119107$4522_Y
+ connect \$2 $eq$libresoc.v:119108$4523_Y
+ connect \$30 $or$libresoc.v:119109$4524_Y
+ connect \$32 $eq$libresoc.v:119110$4525_Y
+ connect \$34 $or$libresoc.v:119111$4526_Y
+ connect \$36 $eq$libresoc.v:119112$4527_Y
+ connect \$38 $and$libresoc.v:119113$4528_Y
+ connect \$40 $and$libresoc.v:119114$4529_Y
+ connect \$42 $eq$libresoc.v:119115$4530_Y
+ connect \$44 $and$libresoc.v:119116$4531_Y
+ connect \$46 $not$libresoc.v:119117$4532_Y
+ connect \$48 $and$libresoc.v:119118$4533_Y
+ connect \$4 $and$libresoc.v:119119$4534_Y
+ connect \$6 $and$libresoc.v:119120$4535_Y
+ connect \$8 $eq$libresoc.v:119121$4536_Y
connect \is_mmu_spr \$34
connect \is_spr_mv \$20
connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] }
connect \insn_in \dec_opcode_in
connect \CR__insn \dec_opcode_in
end
-attribute \src "libresoc.v:120558.1-121131.10"
+attribute \src "libresoc.v:119183.1-119756.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV"
attribute \generator "nMigen"
module \dec_DIV
- attribute \src "libresoc.v:121095.3-121109.6"
+ attribute \src "libresoc.v:119720.3-119734.6"
wire width 13 $0\DIV__fn_unit[12:0]
- attribute \src "libresoc.v:121082.3-121094.6"
+ attribute \src "libresoc.v:119707.3-119719.6"
wire width 7 $0\DIV__insn_type[6:0]
- attribute \src "libresoc.v:121067.3-121081.6"
+ attribute \src "libresoc.v:119692.3-119706.6"
wire $0\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:120559.7-120559.20"
+ attribute \src "libresoc.v:119184.7-119184.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:121095.3-121109.6"
+ attribute \src "libresoc.v:119720.3-119734.6"
wire width 13 $1\DIV__fn_unit[12:0]
- attribute \src "libresoc.v:121082.3-121094.6"
+ attribute \src "libresoc.v:119707.3-119719.6"
wire width 7 $1\DIV__insn_type[6:0]
- attribute \src "libresoc.v:121067.3-121081.6"
+ attribute \src "libresoc.v:119692.3-119706.6"
wire $1\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:120984.18-120984.113"
- wire $and$libresoc.v:120984$4596_Y
- attribute \src "libresoc.v:120986.18-120986.110"
- wire $and$libresoc.v:120986$4598_Y
- attribute \src "libresoc.v:120999.18-120999.114"
- wire $and$libresoc.v:120999$4611_Y
- attribute \src "libresoc.v:121000.18-121000.116"
- wire $and$libresoc.v:121000$4612_Y
- attribute \src "libresoc.v:121002.18-121002.114"
- wire $and$libresoc.v:121002$4614_Y
- attribute \src "libresoc.v:121004.18-121004.110"
- wire $and$libresoc.v:121004$4616_Y
- attribute \src "libresoc.v:121005.17-121005.112"
- wire $and$libresoc.v:121005$4617_Y
- attribute \src "libresoc.v:121006.17-121006.114"
- wire $and$libresoc.v:121006$4618_Y
- attribute \src "libresoc.v:120987.18-120987.126"
- wire $eq$libresoc.v:120987$4599_Y
- attribute \src "libresoc.v:120988.18-120988.126"
- wire $eq$libresoc.v:120988$4600_Y
- attribute \src "libresoc.v:120990.18-120990.110"
- wire $eq$libresoc.v:120990$4602_Y
- attribute \src "libresoc.v:120991.18-120991.110"
- wire $eq$libresoc.v:120991$4603_Y
- attribute \src "libresoc.v:120993.18-120993.112"
- wire $eq$libresoc.v:120993$4605_Y
- attribute \src "libresoc.v:120994.17-120994.130"
- wire $eq$libresoc.v:120994$4606_Y
- attribute \src "libresoc.v:120996.18-120996.110"
- wire $eq$libresoc.v:120996$4608_Y
- attribute \src "libresoc.v:120998.18-120998.131"
- wire $eq$libresoc.v:120998$4610_Y
- attribute \src "libresoc.v:121001.18-121001.131"
- wire $eq$libresoc.v:121001$4613_Y
- attribute \src "libresoc.v:121007.17-121007.130"
- wire $eq$libresoc.v:121007$4619_Y
- attribute \src "libresoc.v:120985.18-120985.110"
- wire $not$libresoc.v:120985$4597_Y
- attribute \src "libresoc.v:121003.18-121003.110"
- wire $not$libresoc.v:121003$4615_Y
- attribute \src "libresoc.v:120989.18-120989.110"
- wire $or$libresoc.v:120989$4601_Y
- attribute \src "libresoc.v:120992.18-120992.110"
- wire $or$libresoc.v:120992$4604_Y
- attribute \src "libresoc.v:120995.18-120995.110"
- wire $or$libresoc.v:120995$4607_Y
- attribute \src "libresoc.v:120997.18-120997.110"
- wire $or$libresoc.v:120997$4609_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:119609.18-119609.113"
+ wire $and$libresoc.v:119609$4540_Y
+ attribute \src "libresoc.v:119611.18-119611.110"
+ wire $and$libresoc.v:119611$4542_Y
+ attribute \src "libresoc.v:119624.18-119624.114"
+ wire $and$libresoc.v:119624$4555_Y
+ attribute \src "libresoc.v:119625.18-119625.116"
+ wire $and$libresoc.v:119625$4556_Y
+ attribute \src "libresoc.v:119627.18-119627.114"
+ wire $and$libresoc.v:119627$4558_Y
+ attribute \src "libresoc.v:119629.18-119629.110"
+ wire $and$libresoc.v:119629$4560_Y
+ attribute \src "libresoc.v:119630.17-119630.112"
+ wire $and$libresoc.v:119630$4561_Y
+ attribute \src "libresoc.v:119631.17-119631.114"
+ wire $and$libresoc.v:119631$4562_Y
+ attribute \src "libresoc.v:119612.18-119612.126"
+ wire $eq$libresoc.v:119612$4543_Y
+ attribute \src "libresoc.v:119613.18-119613.126"
+ wire $eq$libresoc.v:119613$4544_Y
+ attribute \src "libresoc.v:119615.18-119615.110"
+ wire $eq$libresoc.v:119615$4546_Y
+ attribute \src "libresoc.v:119616.18-119616.110"
+ wire $eq$libresoc.v:119616$4547_Y
+ attribute \src "libresoc.v:119618.18-119618.112"
+ wire $eq$libresoc.v:119618$4549_Y
+ attribute \src "libresoc.v:119619.17-119619.130"
+ wire $eq$libresoc.v:119619$4550_Y
+ attribute \src "libresoc.v:119621.18-119621.110"
+ wire $eq$libresoc.v:119621$4552_Y
+ attribute \src "libresoc.v:119623.18-119623.131"
+ wire $eq$libresoc.v:119623$4554_Y
+ attribute \src "libresoc.v:119626.18-119626.131"
+ wire $eq$libresoc.v:119626$4557_Y
+ attribute \src "libresoc.v:119632.17-119632.130"
+ wire $eq$libresoc.v:119632$4563_Y
+ attribute \src "libresoc.v:119610.18-119610.110"
+ wire $not$libresoc.v:119610$4541_Y
+ attribute \src "libresoc.v:119628.18-119628.110"
+ wire $not$libresoc.v:119628$4559_Y
+ attribute \src "libresoc.v:119614.18-119614.110"
+ wire $or$libresoc.v:119614$4545_Y
+ attribute \src "libresoc.v:119617.18-119617.110"
+ wire $or$libresoc.v:119617$4548_Y
+ attribute \src "libresoc.v:119620.18-119620.110"
+ wire $or$libresoc.v:119620$4551_Y
+ attribute \src "libresoc.v:119622.18-119622.110"
+ wire $or$libresoc.v:119622$4553_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 18 \DIV__data_len
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:120559.7-120559.15"
+ attribute \src "libresoc.v:119184.7-119184.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 20 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120984$4596
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119609$4540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:120984$4596_Y
+ connect \Y $and$libresoc.v:119609$4540_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:120986$4598
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119611$4542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:120986$4598_Y
+ connect \Y $and$libresoc.v:119611$4542_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:120999$4611
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119624$4555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:120999$4611_Y
+ connect \Y $and$libresoc.v:119624$4555_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121000$4612
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119625$4556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121000$4612_Y
+ connect \Y $and$libresoc.v:119625$4556_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121002$4614
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119627$4558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:121002$4614_Y
+ connect \Y $and$libresoc.v:119627$4558_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121004$4616
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:119629$4560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:121004$4616_Y
+ connect \Y $and$libresoc.v:119629$4560_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121005$4617
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119630$4561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:121005$4617_Y
+ connect \Y $and$libresoc.v:119630$4561_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121006$4618
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:119631$4562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121006$4618_Y
+ connect \Y $and$libresoc.v:119631$4562_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:120987$4599
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:119612$4543
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:120987$4599_Y
+ connect \Y $eq$libresoc.v:119612$4543_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:120988$4600
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:119613$4544
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:120988$4600_Y
+ connect \Y $eq$libresoc.v:119613$4544_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120990$4602
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119615$4546
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:120990$4602_Y
+ connect \Y $eq$libresoc.v:119615$4546_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120991$4603
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119616$4547
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:120991$4603_Y
+ connect \Y $eq$libresoc.v:119616$4547_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:120993$4605
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:119618$4549
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:120993$4605_Y
+ connect \Y $eq$libresoc.v:119618$4549_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120994$4606
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:119619$4550
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120994$4606_Y
+ connect \Y $eq$libresoc.v:119619$4550_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:120996$4608
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:119621$4552
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:120996$4608_Y
+ connect \Y $eq$libresoc.v:119621$4552_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:120998$4610
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:119623$4554
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:120998$4610_Y
+ connect \Y $eq$libresoc.v:119623$4554_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:121001$4613
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:119626$4557
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:121001$4613_Y
+ connect \Y $eq$libresoc.v:119626$4557_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:121007$4619
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:119632$4563
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_DIV_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:121007$4619_Y
+ connect \Y $eq$libresoc.v:119632$4563_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:120985$4597
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:119610$4541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:120985$4597_Y
+ connect \Y $not$libresoc.v:119610$4541_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:121003$4615
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:119628$4559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121003$4615_Y
+ connect \Y $not$libresoc.v:119628$4559_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:120989$4601
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:119614$4545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:120989$4601_Y
+ connect \Y $or$libresoc.v:119614$4545_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120992$4604
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:119617$4548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:120992$4604_Y
+ connect \Y $or$libresoc.v:119617$4548_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:120995$4607
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:119620$4551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:120995$4607_Y
+ connect \Y $or$libresoc.v:119620$4551_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:120997$4609
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:119622$4553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:120997$4609_Y
+ connect \Y $or$libresoc.v:119622$4553_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121008.13-121036.4"
+ attribute \src "libresoc.v:119633.13-119661.4"
cell \dec$153 \dec
connect \DIV_BD \dec_DIV_BD
connect \DIV_DS \dec_DIV_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121037.16-121041.4"
+ attribute \src "libresoc.v:119662.16-119666.4"
cell \dec_ai$156 \dec_ai
connect \DIV_RA \dec_DIV_RA
connect \immz_out \dec_ai_immz_out
connect \sel_in \dec_ai_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121042.16-121053.4"
+ attribute \src "libresoc.v:119667.16-119678.4"
cell \dec_bi$157 \dec_bi
connect \DIV_BD \dec_DIV_BD
connect \DIV_DS \dec_DIV_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121054.16-121060.4"
+ attribute \src "libresoc.v:119679.16-119685.4"
cell \dec_oe$155 \dec_oe
connect \DIV_OE \dec_DIV_OE
connect \DIV_internal_op \dec_DIV_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121061.16-121066.4"
+ attribute \src "libresoc.v:119686.16-119691.4"
cell \dec_rc$154 \dec_rc
connect \DIV_Rc \dec_DIV_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:120559.7-120559.20"
- process $proc$libresoc.v:120559$4623
+ attribute \src "libresoc.v:119184.7-119184.20"
+ process $proc$libresoc.v:119184$4567
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:121067.3-121081.6"
- process $proc$libresoc.v:121067$4620
+ attribute \src "libresoc.v:119692.3-119706.6"
+ process $proc$libresoc.v:119692$4564
assign { } { }
assign { } { }
assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0]
- attribute \src "libresoc.v:121068.5-121068.29"
+ attribute \src "libresoc.v:119693.5-119693.29"
switch \initial
- attribute \src "libresoc.v:121068.9-121068.17"
+ attribute \src "libresoc.v:119693.9-119693.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
switch \dec_DIV_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
sync always
update \DIV__write_cr0 $0\DIV__write_cr0[0:0]
end
- attribute \src "libresoc.v:121082.3-121094.6"
- process $proc$libresoc.v:121082$4621
+ attribute \src "libresoc.v:119707.3-119719.6"
+ process $proc$libresoc.v:119707$4565
assign { } { }
assign { } { }
assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0]
- attribute \src "libresoc.v:121083.5-121083.29"
+ attribute \src "libresoc.v:119708.5-119708.29"
switch \initial
- attribute \src "libresoc.v:121083.9-121083.17"
+ attribute \src "libresoc.v:119708.9-119708.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \DIV__insn_type $0\DIV__insn_type[6:0]
end
- attribute \src "libresoc.v:121095.3-121109.6"
- process $proc$libresoc.v:121095$4622
+ attribute \src "libresoc.v:119720.3-119734.6"
+ process $proc$libresoc.v:119720$4566
assign { } { }
assign $0\DIV__fn_unit[12:0] $1\DIV__fn_unit[12:0]
- attribute \src "libresoc.v:121096.5-121096.29"
+ attribute \src "libresoc.v:119721.5-119721.29"
switch \initial
- attribute \src "libresoc.v:121096.9-121096.17"
+ attribute \src "libresoc.v:119721.9-119721.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \DIV__fn_unit $0\DIV__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:120984$4596_Y
- connect \$12 $not$libresoc.v:120985$4597_Y
- connect \$14 $and$libresoc.v:120986$4598_Y
- connect \$16 $eq$libresoc.v:120987$4599_Y
- connect \$18 $eq$libresoc.v:120988$4600_Y
- connect \$20 $or$libresoc.v:120989$4601_Y
- connect \$22 $eq$libresoc.v:120990$4602_Y
- connect \$24 $eq$libresoc.v:120991$4603_Y
- connect \$26 $or$libresoc.v:120992$4604_Y
- connect \$28 $eq$libresoc.v:120993$4605_Y
- connect \$2 $eq$libresoc.v:120994$4606_Y
- connect \$30 $or$libresoc.v:120995$4607_Y
- connect \$32 $eq$libresoc.v:120996$4608_Y
- connect \$34 $or$libresoc.v:120997$4609_Y
- connect \$36 $eq$libresoc.v:120998$4610_Y
- connect \$38 $and$libresoc.v:120999$4611_Y
- connect \$40 $and$libresoc.v:121000$4612_Y
- connect \$42 $eq$libresoc.v:121001$4613_Y
- connect \$44 $and$libresoc.v:121002$4614_Y
- connect \$46 $not$libresoc.v:121003$4615_Y
- connect \$48 $and$libresoc.v:121004$4616_Y
- connect \$4 $and$libresoc.v:121005$4617_Y
- connect \$6 $and$libresoc.v:121006$4618_Y
- connect \$8 $eq$libresoc.v:121007$4619_Y
+ connect \$10 $and$libresoc.v:119609$4540_Y
+ connect \$12 $not$libresoc.v:119610$4541_Y
+ connect \$14 $and$libresoc.v:119611$4542_Y
+ connect \$16 $eq$libresoc.v:119612$4543_Y
+ connect \$18 $eq$libresoc.v:119613$4544_Y
+ connect \$20 $or$libresoc.v:119614$4545_Y
+ connect \$22 $eq$libresoc.v:119615$4546_Y
+ connect \$24 $eq$libresoc.v:119616$4547_Y
+ connect \$26 $or$libresoc.v:119617$4548_Y
+ connect \$28 $eq$libresoc.v:119618$4549_Y
+ connect \$2 $eq$libresoc.v:119619$4550_Y
+ connect \$30 $or$libresoc.v:119620$4551_Y
+ connect \$32 $eq$libresoc.v:119621$4552_Y
+ connect \$34 $or$libresoc.v:119622$4553_Y
+ connect \$36 $eq$libresoc.v:119623$4554_Y
+ connect \$38 $and$libresoc.v:119624$4555_Y
+ connect \$40 $and$libresoc.v:119625$4556_Y
+ connect \$42 $eq$libresoc.v:119626$4557_Y
+ connect \$44 $and$libresoc.v:119627$4558_Y
+ connect \$46 $not$libresoc.v:119628$4559_Y
+ connect \$48 $and$libresoc.v:119629$4560_Y
+ connect \$4 $and$libresoc.v:119630$4561_Y
+ connect \$6 $and$libresoc.v:119631$4562_Y
+ connect \$8 $eq$libresoc.v:119632$4563_Y
connect \DIV__is_signed \dec_DIV_sgn
connect \DIV__is_32bit \dec_DIV_is_32b
connect \DIV__output_carry \dec_DIV_cry_out
connect \insn_in \dec_opcode_in
connect \DIV__insn \dec_opcode_in
end
-attribute \src "libresoc.v:121135.1-121686.10"
+attribute \src "libresoc.v:119760.1-120311.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST"
attribute \generator "nMigen"
module \dec_LDST
- attribute \src "libresoc.v:121651.3-121665.6"
+ attribute \src "libresoc.v:120276.3-120290.6"
wire width 13 $0\LDST__fn_unit[12:0]
- attribute \src "libresoc.v:121638.3-121650.6"
+ attribute \src "libresoc.v:120263.3-120275.6"
wire width 7 $0\LDST__insn_type[6:0]
- attribute \src "libresoc.v:121136.7-121136.20"
+ attribute \src "libresoc.v:119761.7-119761.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:121651.3-121665.6"
+ attribute \src "libresoc.v:120276.3-120290.6"
wire width 13 $1\LDST__fn_unit[12:0]
- attribute \src "libresoc.v:121638.3-121650.6"
+ attribute \src "libresoc.v:120263.3-120275.6"
wire width 7 $1\LDST__insn_type[6:0]
- attribute \src "libresoc.v:121556.18-121556.113"
- wire $and$libresoc.v:121556$4624_Y
- attribute \src "libresoc.v:121558.18-121558.110"
- wire $and$libresoc.v:121558$4626_Y
- attribute \src "libresoc.v:121571.18-121571.114"
- wire $and$libresoc.v:121571$4639_Y
- attribute \src "libresoc.v:121572.18-121572.116"
- wire $and$libresoc.v:121572$4640_Y
- attribute \src "libresoc.v:121574.18-121574.114"
- wire $and$libresoc.v:121574$4642_Y
- attribute \src "libresoc.v:121576.18-121576.110"
- wire $and$libresoc.v:121576$4644_Y
- attribute \src "libresoc.v:121577.17-121577.112"
- wire $and$libresoc.v:121577$4645_Y
- attribute \src "libresoc.v:121578.17-121578.114"
- wire $and$libresoc.v:121578$4646_Y
- attribute \src "libresoc.v:121559.18-121559.127"
- wire $eq$libresoc.v:121559$4627_Y
- attribute \src "libresoc.v:121560.18-121560.127"
- wire $eq$libresoc.v:121560$4628_Y
- attribute \src "libresoc.v:121562.18-121562.110"
- wire $eq$libresoc.v:121562$4630_Y
- attribute \src "libresoc.v:121563.18-121563.110"
- wire $eq$libresoc.v:121563$4631_Y
- attribute \src "libresoc.v:121565.18-121565.112"
- wire $eq$libresoc.v:121565$4633_Y
- attribute \src "libresoc.v:121566.17-121566.131"
- wire $eq$libresoc.v:121566$4634_Y
- attribute \src "libresoc.v:121568.18-121568.110"
- wire $eq$libresoc.v:121568$4636_Y
- attribute \src "libresoc.v:121570.18-121570.132"
- wire $eq$libresoc.v:121570$4638_Y
- attribute \src "libresoc.v:121573.18-121573.132"
- wire $eq$libresoc.v:121573$4641_Y
- attribute \src "libresoc.v:121579.17-121579.131"
- wire $eq$libresoc.v:121579$4647_Y
- attribute \src "libresoc.v:121557.18-121557.110"
- wire $not$libresoc.v:121557$4625_Y
- attribute \src "libresoc.v:121575.18-121575.110"
- wire $not$libresoc.v:121575$4643_Y
- attribute \src "libresoc.v:121561.18-121561.110"
- wire $or$libresoc.v:121561$4629_Y
- attribute \src "libresoc.v:121564.18-121564.110"
- wire $or$libresoc.v:121564$4632_Y
- attribute \src "libresoc.v:121567.18-121567.110"
- wire $or$libresoc.v:121567$4635_Y
- attribute \src "libresoc.v:121569.18-121569.110"
- wire $or$libresoc.v:121569$4637_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:120181.18-120181.113"
+ wire $and$libresoc.v:120181$4568_Y
+ attribute \src "libresoc.v:120183.18-120183.110"
+ wire $and$libresoc.v:120183$4570_Y
+ attribute \src "libresoc.v:120196.18-120196.114"
+ wire $and$libresoc.v:120196$4583_Y
+ attribute \src "libresoc.v:120197.18-120197.116"
+ wire $and$libresoc.v:120197$4584_Y
+ attribute \src "libresoc.v:120199.18-120199.114"
+ wire $and$libresoc.v:120199$4586_Y
+ attribute \src "libresoc.v:120201.18-120201.110"
+ wire $and$libresoc.v:120201$4588_Y
+ attribute \src "libresoc.v:120202.17-120202.112"
+ wire $and$libresoc.v:120202$4589_Y
+ attribute \src "libresoc.v:120203.17-120203.114"
+ wire $and$libresoc.v:120203$4590_Y
+ attribute \src "libresoc.v:120184.18-120184.127"
+ wire $eq$libresoc.v:120184$4571_Y
+ attribute \src "libresoc.v:120185.18-120185.127"
+ wire $eq$libresoc.v:120185$4572_Y
+ attribute \src "libresoc.v:120187.18-120187.110"
+ wire $eq$libresoc.v:120187$4574_Y
+ attribute \src "libresoc.v:120188.18-120188.110"
+ wire $eq$libresoc.v:120188$4575_Y
+ attribute \src "libresoc.v:120190.18-120190.112"
+ wire $eq$libresoc.v:120190$4577_Y
+ attribute \src "libresoc.v:120191.17-120191.131"
+ wire $eq$libresoc.v:120191$4578_Y
+ attribute \src "libresoc.v:120193.18-120193.110"
+ wire $eq$libresoc.v:120193$4580_Y
+ attribute \src "libresoc.v:120195.18-120195.132"
+ wire $eq$libresoc.v:120195$4582_Y
+ attribute \src "libresoc.v:120198.18-120198.132"
+ wire $eq$libresoc.v:120198$4585_Y
+ attribute \src "libresoc.v:120204.17-120204.131"
+ wire $eq$libresoc.v:120204$4591_Y
+ attribute \src "libresoc.v:120182.18-120182.110"
+ wire $not$libresoc.v:120182$4569_Y
+ attribute \src "libresoc.v:120200.18-120200.110"
+ wire $not$libresoc.v:120200$4587_Y
+ attribute \src "libresoc.v:120186.18-120186.110"
+ wire $or$libresoc.v:120186$4573_Y
+ attribute \src "libresoc.v:120189.18-120189.110"
+ wire $or$libresoc.v:120189$4576_Y
+ attribute \src "libresoc.v:120192.18-120192.110"
+ wire $or$libresoc.v:120192$4579_Y
+ attribute \src "libresoc.v:120194.18-120194.110"
+ wire $or$libresoc.v:120194$4581_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire output 14 \LDST__byte_reverse
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:121136.7-121136.15"
+ attribute \src "libresoc.v:119761.7-119761.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 18 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121556$4624
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120181$4568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:121556$4624_Y
+ connect \Y $and$libresoc.v:120181$4568_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121558$4626
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120183$4570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:121558$4626_Y
+ connect \Y $and$libresoc.v:120183$4570_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121571$4639
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120196$4583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:121571$4639_Y
+ connect \Y $and$libresoc.v:120196$4583_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121572$4640
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120197$4584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121572$4640_Y
+ connect \Y $and$libresoc.v:120197$4584_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121574$4642
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120199$4586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:121574$4642_Y
+ connect \Y $and$libresoc.v:120199$4586_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:121576$4644
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120201$4588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:121576$4644_Y
+ connect \Y $and$libresoc.v:120201$4588_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121577$4645
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120202$4589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:121577$4645_Y
+ connect \Y $and$libresoc.v:120202$4589_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:121578$4646
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120203$4590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:121578$4646_Y
+ connect \Y $and$libresoc.v:120203$4590_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:121559$4627
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:120184$4571
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:121559$4627_Y
+ connect \Y $eq$libresoc.v:120184$4571_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:121560$4628
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:120185$4572
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:121560$4628_Y
+ connect \Y $eq$libresoc.v:120185$4572_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:121562$4630
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120187$4574
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:121562$4630_Y
+ connect \Y $eq$libresoc.v:120187$4574_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:121563$4631
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120188$4575
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:121563$4631_Y
+ connect \Y $eq$libresoc.v:120188$4575_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:121565$4633
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120190$4577
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:121565$4633_Y
+ connect \Y $eq$libresoc.v:120190$4577_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:121566$4634
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:120191$4578
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:121566$4634_Y
+ connect \Y $eq$libresoc.v:120191$4578_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:121568$4636
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:120193$4580
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:121568$4636_Y
+ connect \Y $eq$libresoc.v:120193$4580_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:121570$4638
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:120195$4582
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:121570$4638_Y
+ connect \Y $eq$libresoc.v:120195$4582_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:121573$4641
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:120198$4585
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:121573$4641_Y
+ connect \Y $eq$libresoc.v:120198$4585_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:121579$4647
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:120204$4591
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LDST_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:121579$4647_Y
+ connect \Y $eq$libresoc.v:120204$4591_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:121557$4625
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:120182$4569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121557$4625_Y
+ connect \Y $not$libresoc.v:120182$4569_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:121575$4643
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:120200$4587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:121575$4643_Y
+ connect \Y $not$libresoc.v:120200$4587_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:121561$4629
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:120186$4573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:121561$4629_Y
+ connect \Y $or$libresoc.v:120186$4573_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:121564$4632
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:120189$4576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:121564$4632_Y
+ connect \Y $or$libresoc.v:120189$4576_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:121567$4635
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:120192$4579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:121567$4635_Y
+ connect \Y $or$libresoc.v:120192$4579_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:121569$4637
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:120194$4581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:121569$4637_Y
+ connect \Y $or$libresoc.v:120194$4581_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121580.13-121607.4"
+ attribute \src "libresoc.v:120205.13-120232.4"
cell \dec$166 \dec
connect \LDST_BD \dec_LDST_BD
connect \LDST_DS \dec_LDST_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121608.16-121612.4"
+ attribute \src "libresoc.v:120233.16-120237.4"
cell \dec_ai$169 \dec_ai
connect \LDST_RA \dec_LDST_RA
connect \immz_out \dec_ai_immz_out
connect \sel_in \dec_ai_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121613.16-121624.4"
+ attribute \src "libresoc.v:120238.16-120249.4"
cell \dec_bi$170 \dec_bi
connect \LDST_BD \dec_LDST_BD
connect \LDST_DS \dec_LDST_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121625.16-121631.4"
+ attribute \src "libresoc.v:120250.16-120256.4"
cell \dec_oe$168 \dec_oe
connect \LDST_OE \dec_LDST_OE
connect \LDST_internal_op \dec_LDST_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:121632.16-121637.4"
+ attribute \src "libresoc.v:120257.16-120262.4"
cell \dec_rc$167 \dec_rc
connect \LDST_Rc \dec_LDST_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:121136.7-121136.20"
- process $proc$libresoc.v:121136$4650
+ attribute \src "libresoc.v:119761.7-119761.20"
+ process $proc$libresoc.v:119761$4594
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:121638.3-121650.6"
- process $proc$libresoc.v:121638$4648
+ attribute \src "libresoc.v:120263.3-120275.6"
+ process $proc$libresoc.v:120263$4592
assign { } { }
assign { } { }
assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0]
- attribute \src "libresoc.v:121639.5-121639.29"
+ attribute \src "libresoc.v:120264.5-120264.29"
switch \initial
- attribute \src "libresoc.v:121639.9-121639.17"
+ attribute \src "libresoc.v:120264.9-120264.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \LDST__insn_type $0\LDST__insn_type[6:0]
end
- attribute \src "libresoc.v:121651.3-121665.6"
- process $proc$libresoc.v:121651$4649
+ attribute \src "libresoc.v:120276.3-120290.6"
+ process $proc$libresoc.v:120276$4593
assign { } { }
assign $0\LDST__fn_unit[12:0] $1\LDST__fn_unit[12:0]
- attribute \src "libresoc.v:121652.5-121652.29"
+ attribute \src "libresoc.v:120277.5-120277.29"
switch \initial
- attribute \src "libresoc.v:121652.9-121652.17"
+ attribute \src "libresoc.v:120277.9-120277.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \LDST__fn_unit $0\LDST__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:121556$4624_Y
- connect \$12 $not$libresoc.v:121557$4625_Y
- connect \$14 $and$libresoc.v:121558$4626_Y
- connect \$16 $eq$libresoc.v:121559$4627_Y
- connect \$18 $eq$libresoc.v:121560$4628_Y
- connect \$20 $or$libresoc.v:121561$4629_Y
- connect \$22 $eq$libresoc.v:121562$4630_Y
- connect \$24 $eq$libresoc.v:121563$4631_Y
- connect \$26 $or$libresoc.v:121564$4632_Y
- connect \$28 $eq$libresoc.v:121565$4633_Y
- connect \$2 $eq$libresoc.v:121566$4634_Y
- connect \$30 $or$libresoc.v:121567$4635_Y
- connect \$32 $eq$libresoc.v:121568$4636_Y
- connect \$34 $or$libresoc.v:121569$4637_Y
- connect \$36 $eq$libresoc.v:121570$4638_Y
- connect \$38 $and$libresoc.v:121571$4639_Y
- connect \$40 $and$libresoc.v:121572$4640_Y
- connect \$42 $eq$libresoc.v:121573$4641_Y
- connect \$44 $and$libresoc.v:121574$4642_Y
- connect \$46 $not$libresoc.v:121575$4643_Y
- connect \$48 $and$libresoc.v:121576$4644_Y
- connect \$4 $and$libresoc.v:121577$4645_Y
- connect \$6 $and$libresoc.v:121578$4646_Y
- connect \$8 $eq$libresoc.v:121579$4647_Y
+ connect \$10 $and$libresoc.v:120181$4568_Y
+ connect \$12 $not$libresoc.v:120182$4569_Y
+ connect \$14 $and$libresoc.v:120183$4570_Y
+ connect \$16 $eq$libresoc.v:120184$4571_Y
+ connect \$18 $eq$libresoc.v:120185$4572_Y
+ connect \$20 $or$libresoc.v:120186$4573_Y
+ connect \$22 $eq$libresoc.v:120187$4574_Y
+ connect \$24 $eq$libresoc.v:120188$4575_Y
+ connect \$26 $or$libresoc.v:120189$4576_Y
+ connect \$28 $eq$libresoc.v:120190$4577_Y
+ connect \$2 $eq$libresoc.v:120191$4578_Y
+ connect \$30 $or$libresoc.v:120192$4579_Y
+ connect \$32 $eq$libresoc.v:120193$4580_Y
+ connect \$34 $or$libresoc.v:120194$4581_Y
+ connect \$36 $eq$libresoc.v:120195$4582_Y
+ connect \$38 $and$libresoc.v:120196$4583_Y
+ connect \$40 $and$libresoc.v:120197$4584_Y
+ connect \$42 $eq$libresoc.v:120198$4585_Y
+ connect \$44 $and$libresoc.v:120199$4586_Y
+ connect \$46 $not$libresoc.v:120200$4587_Y
+ connect \$48 $and$libresoc.v:120201$4588_Y
+ connect \$4 $and$libresoc.v:120202$4589_Y
+ connect \$6 $and$libresoc.v:120203$4590_Y
+ connect \$8 $eq$libresoc.v:120204$4591_Y
connect \LDST__ldst_mode \dec_LDST_upd
connect \LDST__sign_extend \dec_LDST_sgn_ext
connect \LDST__byte_reverse \dec_LDST_br
connect \insn_in \dec_opcode_in
connect \LDST__insn \dec_opcode_in
end
-attribute \src "libresoc.v:121690.1-122263.10"
+attribute \src "libresoc.v:120315.1-120888.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL"
attribute \generator "nMigen"
module \dec_LOGICAL
- attribute \src "libresoc.v:122227.3-122241.6"
+ attribute \src "libresoc.v:120852.3-120866.6"
wire width 13 $0\LOGICAL__fn_unit[12:0]
- attribute \src "libresoc.v:122214.3-122226.6"
+ attribute \src "libresoc.v:120839.3-120851.6"
wire width 7 $0\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:122199.3-122213.6"
+ attribute \src "libresoc.v:120824.3-120838.6"
wire $0\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:121691.7-121691.20"
+ attribute \src "libresoc.v:120316.7-120316.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:122227.3-122241.6"
+ attribute \src "libresoc.v:120852.3-120866.6"
wire width 13 $1\LOGICAL__fn_unit[12:0]
- attribute \src "libresoc.v:122214.3-122226.6"
+ attribute \src "libresoc.v:120839.3-120851.6"
wire width 7 $1\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:122199.3-122213.6"
+ attribute \src "libresoc.v:120824.3-120838.6"
wire $1\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:122116.18-122116.113"
- wire $and$libresoc.v:122116$4651_Y
- attribute \src "libresoc.v:122118.18-122118.110"
- wire $and$libresoc.v:122118$4653_Y
- attribute \src "libresoc.v:122131.18-122131.114"
- wire $and$libresoc.v:122131$4666_Y
- attribute \src "libresoc.v:122132.18-122132.116"
- wire $and$libresoc.v:122132$4667_Y
- attribute \src "libresoc.v:122134.18-122134.114"
- wire $and$libresoc.v:122134$4669_Y
- attribute \src "libresoc.v:122136.18-122136.110"
- wire $and$libresoc.v:122136$4671_Y
- attribute \src "libresoc.v:122137.17-122137.112"
- wire $and$libresoc.v:122137$4672_Y
- attribute \src "libresoc.v:122138.17-122138.114"
- wire $and$libresoc.v:122138$4673_Y
- attribute \src "libresoc.v:122119.18-122119.130"
- wire $eq$libresoc.v:122119$4654_Y
- attribute \src "libresoc.v:122120.18-122120.130"
- wire $eq$libresoc.v:122120$4655_Y
- attribute \src "libresoc.v:122122.18-122122.110"
- wire $eq$libresoc.v:122122$4657_Y
- attribute \src "libresoc.v:122123.18-122123.110"
- wire $eq$libresoc.v:122123$4658_Y
- attribute \src "libresoc.v:122125.18-122125.112"
- wire $eq$libresoc.v:122125$4660_Y
- attribute \src "libresoc.v:122126.17-122126.134"
- wire $eq$libresoc.v:122126$4661_Y
- attribute \src "libresoc.v:122128.18-122128.110"
- wire $eq$libresoc.v:122128$4663_Y
- attribute \src "libresoc.v:122130.18-122130.135"
- wire $eq$libresoc.v:122130$4665_Y
- attribute \src "libresoc.v:122133.18-122133.135"
- wire $eq$libresoc.v:122133$4668_Y
- attribute \src "libresoc.v:122139.17-122139.134"
- wire $eq$libresoc.v:122139$4674_Y
- attribute \src "libresoc.v:122117.18-122117.110"
- wire $not$libresoc.v:122117$4652_Y
- attribute \src "libresoc.v:122135.18-122135.110"
- wire $not$libresoc.v:122135$4670_Y
- attribute \src "libresoc.v:122121.18-122121.110"
- wire $or$libresoc.v:122121$4656_Y
- attribute \src "libresoc.v:122124.18-122124.110"
- wire $or$libresoc.v:122124$4659_Y
- attribute \src "libresoc.v:122127.18-122127.110"
- wire $or$libresoc.v:122127$4662_Y
- attribute \src "libresoc.v:122129.18-122129.110"
- wire $or$libresoc.v:122129$4664_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:120741.18-120741.113"
+ wire $and$libresoc.v:120741$4595_Y
+ attribute \src "libresoc.v:120743.18-120743.110"
+ wire $and$libresoc.v:120743$4597_Y
+ attribute \src "libresoc.v:120756.18-120756.114"
+ wire $and$libresoc.v:120756$4610_Y
+ attribute \src "libresoc.v:120757.18-120757.116"
+ wire $and$libresoc.v:120757$4611_Y
+ attribute \src "libresoc.v:120759.18-120759.114"
+ wire $and$libresoc.v:120759$4613_Y
+ attribute \src "libresoc.v:120761.18-120761.110"
+ wire $and$libresoc.v:120761$4615_Y
+ attribute \src "libresoc.v:120762.17-120762.112"
+ wire $and$libresoc.v:120762$4616_Y
+ attribute \src "libresoc.v:120763.17-120763.114"
+ wire $and$libresoc.v:120763$4617_Y
+ attribute \src "libresoc.v:120744.18-120744.130"
+ wire $eq$libresoc.v:120744$4598_Y
+ attribute \src "libresoc.v:120745.18-120745.130"
+ wire $eq$libresoc.v:120745$4599_Y
+ attribute \src "libresoc.v:120747.18-120747.110"
+ wire $eq$libresoc.v:120747$4601_Y
+ attribute \src "libresoc.v:120748.18-120748.110"
+ wire $eq$libresoc.v:120748$4602_Y
+ attribute \src "libresoc.v:120750.18-120750.112"
+ wire $eq$libresoc.v:120750$4604_Y
+ attribute \src "libresoc.v:120751.17-120751.134"
+ wire $eq$libresoc.v:120751$4605_Y
+ attribute \src "libresoc.v:120753.18-120753.110"
+ wire $eq$libresoc.v:120753$4607_Y
+ attribute \src "libresoc.v:120755.18-120755.135"
+ wire $eq$libresoc.v:120755$4609_Y
+ attribute \src "libresoc.v:120758.18-120758.135"
+ wire $eq$libresoc.v:120758$4612_Y
+ attribute \src "libresoc.v:120764.17-120764.134"
+ wire $eq$libresoc.v:120764$4618_Y
+ attribute \src "libresoc.v:120742.18-120742.110"
+ wire $not$libresoc.v:120742$4596_Y
+ attribute \src "libresoc.v:120760.18-120760.110"
+ wire $not$libresoc.v:120760$4614_Y
+ attribute \src "libresoc.v:120746.18-120746.110"
+ wire $or$libresoc.v:120746$4600_Y
+ attribute \src "libresoc.v:120749.18-120749.110"
+ wire $or$libresoc.v:120749$4603_Y
+ attribute \src "libresoc.v:120752.18-120752.110"
+ wire $or$libresoc.v:120752$4606_Y
+ attribute \src "libresoc.v:120754.18-120754.110"
+ wire $or$libresoc.v:120754$4608_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 18 \LOGICAL__data_len
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:121691.7-121691.15"
+ attribute \src "libresoc.v:120316.7-120316.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 20 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122116$4651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120741$4595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:122116$4651_Y
+ connect \Y $and$libresoc.v:120741$4595_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122118$4653
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120743$4597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:122118$4653_Y
+ connect \Y $and$libresoc.v:120743$4597_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120756$4610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:122131$4666_Y
+ connect \Y $and$libresoc.v:120756$4610_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120757$4611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122132$4667_Y
+ connect \Y $and$libresoc.v:120757$4611_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:120759$4613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:122134$4669_Y
+ connect \Y $and$libresoc.v:120759$4613_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:122136$4671_Y
+ connect \Y $and$libresoc.v:120761$4615_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:122137$4672_Y
+ connect \Y $and$libresoc.v:120762$4616_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:122138$4673
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:120763$4617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122138$4673_Y
+ connect \Y $and$libresoc.v:120763$4617_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:122119$4654
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:120744$4598
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:122119$4654_Y
+ connect \Y $eq$libresoc.v:120744$4598_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:122120$4655
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:120745$4599
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:122120$4655_Y
+ connect \Y $eq$libresoc.v:120745$4599_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122122$4657
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120747$4601
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:122122$4657_Y
+ connect \Y $eq$libresoc.v:120747$4601_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122123$4658
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120748$4602
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:122123$4658_Y
+ connect \Y $eq$libresoc.v:120748$4602_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122125$4660
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:120750$4604
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:122125$4660_Y
+ connect \Y $eq$libresoc.v:120750$4604_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:122126$4661
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:120751$4605
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:122126$4661_Y
+ connect \Y $eq$libresoc.v:120751$4605_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:122128$4663
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:120753$4607
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:122128$4663_Y
+ connect \Y $eq$libresoc.v:120753$4607_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:122130$4665
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:120755$4609
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:122130$4665_Y
+ connect \Y $eq$libresoc.v:120755$4609_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:122133$4668
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:120758$4612
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:122133$4668_Y
+ connect \Y $eq$libresoc.v:120758$4612_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:122139$4674
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:120764$4618
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_LOGICAL_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:122139$4674_Y
+ connect \Y $eq$libresoc.v:120764$4618_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:122117$4652
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:120742$4596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122117$4652_Y
+ connect \Y $not$libresoc.v:120742$4596_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:122135$4670
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:120760$4614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122135$4670_Y
+ connect \Y $not$libresoc.v:120760$4614_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:122121$4656
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:120746$4600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:122121$4656_Y
+ connect \Y $or$libresoc.v:120746$4600_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:122124$4659
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:120749$4603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:122124$4659_Y
+ connect \Y $or$libresoc.v:120749$4603_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:122127$4662
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:120752$4606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:122127$4662_Y
+ connect \Y $or$libresoc.v:120752$4606_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:122129$4664
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:120754$4608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:122129$4664_Y
+ connect \Y $or$libresoc.v:120754$4608_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122140.13-122168.4"
+ attribute \src "libresoc.v:120765.13-120793.4"
cell \dec$145 \dec
connect \LOGICAL_BD \dec_LOGICAL_BD
connect \LOGICAL_DS \dec_LOGICAL_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122169.16-122173.4"
+ attribute \src "libresoc.v:120794.16-120798.4"
cell \dec_ai$148 \dec_ai
connect \LOGICAL_RA \dec_LOGICAL_RA
connect \immz_out \dec_ai_immz_out
connect \sel_in \dec_ai_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122174.16-122185.4"
+ attribute \src "libresoc.v:120799.16-120810.4"
cell \dec_bi$149 \dec_bi
connect \LOGICAL_BD \dec_LOGICAL_BD
connect \LOGICAL_DS \dec_LOGICAL_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122186.16-122192.4"
+ attribute \src "libresoc.v:120811.16-120817.4"
cell \dec_oe$147 \dec_oe
connect \LOGICAL_OE \dec_LOGICAL_OE
connect \LOGICAL_internal_op \dec_LOGICAL_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122193.16-122198.4"
+ attribute \src "libresoc.v:120818.16-120823.4"
cell \dec_rc$146 \dec_rc
connect \LOGICAL_Rc \dec_LOGICAL_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:121691.7-121691.20"
- process $proc$libresoc.v:121691$4678
+ attribute \src "libresoc.v:120316.7-120316.20"
+ process $proc$libresoc.v:120316$4622
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:122199.3-122213.6"
- process $proc$libresoc.v:122199$4675
+ attribute \src "libresoc.v:120824.3-120838.6"
+ process $proc$libresoc.v:120824$4619
assign { } { }
assign { } { }
assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0]
- attribute \src "libresoc.v:122200.5-122200.29"
+ attribute \src "libresoc.v:120825.5-120825.29"
switch \initial
- attribute \src "libresoc.v:122200.9-122200.17"
+ attribute \src "libresoc.v:120825.9-120825.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
switch \dec_LOGICAL_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
sync always
update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0]
end
- attribute \src "libresoc.v:122214.3-122226.6"
- process $proc$libresoc.v:122214$4676
+ attribute \src "libresoc.v:120839.3-120851.6"
+ process $proc$libresoc.v:120839$4620
assign { } { }
assign { } { }
assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0]
- attribute \src "libresoc.v:122215.5-122215.29"
+ attribute \src "libresoc.v:120840.5-120840.29"
switch \initial
- attribute \src "libresoc.v:122215.9-122215.17"
+ attribute \src "libresoc.v:120840.9-120840.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0]
end
- attribute \src "libresoc.v:122227.3-122241.6"
- process $proc$libresoc.v:122227$4677
+ attribute \src "libresoc.v:120852.3-120866.6"
+ process $proc$libresoc.v:120852$4621
assign { } { }
assign $0\LOGICAL__fn_unit[12:0] $1\LOGICAL__fn_unit[12:0]
- attribute \src "libresoc.v:122228.5-122228.29"
+ attribute \src "libresoc.v:120853.5-120853.29"
switch \initial
- attribute \src "libresoc.v:122228.9-122228.17"
+ attribute \src "libresoc.v:120853.9-120853.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:122116$4651_Y
- connect \$12 $not$libresoc.v:122117$4652_Y
- connect \$14 $and$libresoc.v:122118$4653_Y
- connect \$16 $eq$libresoc.v:122119$4654_Y
- connect \$18 $eq$libresoc.v:122120$4655_Y
- connect \$20 $or$libresoc.v:122121$4656_Y
- connect \$22 $eq$libresoc.v:122122$4657_Y
- connect \$24 $eq$libresoc.v:122123$4658_Y
- connect \$26 $or$libresoc.v:122124$4659_Y
- connect \$28 $eq$libresoc.v:122125$4660_Y
- connect \$2 $eq$libresoc.v:122126$4661_Y
- connect \$30 $or$libresoc.v:122127$4662_Y
- connect \$32 $eq$libresoc.v:122128$4663_Y
- connect \$34 $or$libresoc.v:122129$4664_Y
- connect \$36 $eq$libresoc.v:122130$4665_Y
- connect \$38 $and$libresoc.v:122131$4666_Y
- connect \$40 $and$libresoc.v:122132$4667_Y
- connect \$42 $eq$libresoc.v:122133$4668_Y
- connect \$44 $and$libresoc.v:122134$4669_Y
- connect \$46 $not$libresoc.v:122135$4670_Y
- connect \$48 $and$libresoc.v:122136$4671_Y
- connect \$4 $and$libresoc.v:122137$4672_Y
- connect \$6 $and$libresoc.v:122138$4673_Y
- connect \$8 $eq$libresoc.v:122139$4674_Y
+ connect \$10 $and$libresoc.v:120741$4595_Y
+ connect \$12 $not$libresoc.v:120742$4596_Y
+ connect \$14 $and$libresoc.v:120743$4597_Y
+ connect \$16 $eq$libresoc.v:120744$4598_Y
+ connect \$18 $eq$libresoc.v:120745$4599_Y
+ connect \$20 $or$libresoc.v:120746$4600_Y
+ connect \$22 $eq$libresoc.v:120747$4601_Y
+ connect \$24 $eq$libresoc.v:120748$4602_Y
+ connect \$26 $or$libresoc.v:120749$4603_Y
+ connect \$28 $eq$libresoc.v:120750$4604_Y
+ connect \$2 $eq$libresoc.v:120751$4605_Y
+ connect \$30 $or$libresoc.v:120752$4606_Y
+ connect \$32 $eq$libresoc.v:120753$4607_Y
+ connect \$34 $or$libresoc.v:120754$4608_Y
+ connect \$36 $eq$libresoc.v:120755$4609_Y
+ connect \$38 $and$libresoc.v:120756$4610_Y
+ connect \$40 $and$libresoc.v:120757$4611_Y
+ connect \$42 $eq$libresoc.v:120758$4612_Y
+ connect \$44 $and$libresoc.v:120759$4613_Y
+ connect \$46 $not$libresoc.v:120760$4614_Y
+ connect \$48 $and$libresoc.v:120761$4615_Y
+ connect \$4 $and$libresoc.v:120762$4616_Y
+ connect \$6 $and$libresoc.v:120763$4617_Y
+ connect \$8 $eq$libresoc.v:120764$4618_Y
connect \LOGICAL__is_signed \dec_LOGICAL_sgn
connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b
connect \LOGICAL__output_carry \dec_LOGICAL_cry_out
connect \insn_in \dec_opcode_in
connect \LOGICAL__insn \dec_opcode_in
end
-attribute \src "libresoc.v:122267.1-122765.10"
+attribute \src "libresoc.v:120892.1-121390.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL"
attribute \generator "nMigen"
module \dec_MUL
- attribute \src "libresoc.v:122736.3-122750.6"
+ attribute \src "libresoc.v:121361.3-121375.6"
wire width 13 $0\MUL__fn_unit[12:0]
- attribute \src "libresoc.v:122723.3-122735.6"
+ attribute \src "libresoc.v:121348.3-121360.6"
wire width 7 $0\MUL__insn_type[6:0]
- attribute \src "libresoc.v:122708.3-122722.6"
+ attribute \src "libresoc.v:121333.3-121347.6"
wire $0\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:122268.7-122268.20"
+ attribute \src "libresoc.v:120893.7-120893.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:122736.3-122750.6"
+ attribute \src "libresoc.v:121361.3-121375.6"
wire width 13 $1\MUL__fn_unit[12:0]
- attribute \src "libresoc.v:122723.3-122735.6"
+ attribute \src "libresoc.v:121348.3-121360.6"
wire width 7 $1\MUL__insn_type[6:0]
- attribute \src "libresoc.v:122708.3-122722.6"
+ attribute \src "libresoc.v:121333.3-121347.6"
wire $1\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:122637.18-122637.113"
- wire $and$libresoc.v:122637$4679_Y
- attribute \src "libresoc.v:122639.18-122639.110"
- wire $and$libresoc.v:122639$4681_Y
- attribute \src "libresoc.v:122652.18-122652.114"
- wire $and$libresoc.v:122652$4694_Y
- attribute \src "libresoc.v:122653.18-122653.116"
- wire $and$libresoc.v:122653$4695_Y
- attribute \src "libresoc.v:122655.18-122655.114"
- wire $and$libresoc.v:122655$4697_Y
- attribute \src "libresoc.v:122657.18-122657.110"
- wire $and$libresoc.v:122657$4699_Y
- attribute \src "libresoc.v:122658.17-122658.112"
- wire $and$libresoc.v:122658$4700_Y
- attribute \src "libresoc.v:122659.17-122659.114"
- wire $and$libresoc.v:122659$4701_Y
- attribute \src "libresoc.v:122640.18-122640.126"
- wire $eq$libresoc.v:122640$4682_Y
- attribute \src "libresoc.v:122641.18-122641.126"
- wire $eq$libresoc.v:122641$4683_Y
- attribute \src "libresoc.v:122643.18-122643.110"
- wire $eq$libresoc.v:122643$4685_Y
- attribute \src "libresoc.v:122644.18-122644.110"
- wire $eq$libresoc.v:122644$4686_Y
- attribute \src "libresoc.v:122646.18-122646.112"
- wire $eq$libresoc.v:122646$4688_Y
- attribute \src "libresoc.v:122647.17-122647.130"
- wire $eq$libresoc.v:122647$4689_Y
- attribute \src "libresoc.v:122649.18-122649.110"
- wire $eq$libresoc.v:122649$4691_Y
- attribute \src "libresoc.v:122651.18-122651.131"
- wire $eq$libresoc.v:122651$4693_Y
- attribute \src "libresoc.v:122654.18-122654.131"
- wire $eq$libresoc.v:122654$4696_Y
- attribute \src "libresoc.v:122660.17-122660.130"
- wire $eq$libresoc.v:122660$4702_Y
- attribute \src "libresoc.v:122638.18-122638.110"
- wire $not$libresoc.v:122638$4680_Y
- attribute \src "libresoc.v:122656.18-122656.110"
- wire $not$libresoc.v:122656$4698_Y
- attribute \src "libresoc.v:122642.18-122642.110"
- wire $or$libresoc.v:122642$4684_Y
- attribute \src "libresoc.v:122645.18-122645.110"
- wire $or$libresoc.v:122645$4687_Y
- attribute \src "libresoc.v:122648.18-122648.110"
- wire $or$libresoc.v:122648$4690_Y
- attribute \src "libresoc.v:122650.18-122650.110"
- wire $or$libresoc.v:122650$4692_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:121262.18-121262.113"
+ wire $and$libresoc.v:121262$4623_Y
+ attribute \src "libresoc.v:121264.18-121264.110"
+ wire $and$libresoc.v:121264$4625_Y
+ attribute \src "libresoc.v:121277.18-121277.114"
+ wire $and$libresoc.v:121277$4638_Y
+ attribute \src "libresoc.v:121278.18-121278.116"
+ wire $and$libresoc.v:121278$4639_Y
+ attribute \src "libresoc.v:121280.18-121280.114"
+ wire $and$libresoc.v:121280$4641_Y
+ attribute \src "libresoc.v:121282.18-121282.110"
+ wire $and$libresoc.v:121282$4643_Y
+ attribute \src "libresoc.v:121283.17-121283.112"
+ wire $and$libresoc.v:121283$4644_Y
+ attribute \src "libresoc.v:121284.17-121284.114"
+ wire $and$libresoc.v:121284$4645_Y
+ attribute \src "libresoc.v:121265.18-121265.126"
+ wire $eq$libresoc.v:121265$4626_Y
+ attribute \src "libresoc.v:121266.18-121266.126"
+ wire $eq$libresoc.v:121266$4627_Y
+ attribute \src "libresoc.v:121268.18-121268.110"
+ wire $eq$libresoc.v:121268$4629_Y
+ attribute \src "libresoc.v:121269.18-121269.110"
+ wire $eq$libresoc.v:121269$4630_Y
+ attribute \src "libresoc.v:121271.18-121271.112"
+ wire $eq$libresoc.v:121271$4632_Y
+ attribute \src "libresoc.v:121272.17-121272.130"
+ wire $eq$libresoc.v:121272$4633_Y
+ attribute \src "libresoc.v:121274.18-121274.110"
+ wire $eq$libresoc.v:121274$4635_Y
+ attribute \src "libresoc.v:121276.18-121276.131"
+ wire $eq$libresoc.v:121276$4637_Y
+ attribute \src "libresoc.v:121279.18-121279.131"
+ wire $eq$libresoc.v:121279$4640_Y
+ attribute \src "libresoc.v:121285.17-121285.130"
+ wire $eq$libresoc.v:121285$4646_Y
+ attribute \src "libresoc.v:121263.18-121263.110"
+ wire $not$libresoc.v:121263$4624_Y
+ attribute \src "libresoc.v:121281.18-121281.110"
+ wire $not$libresoc.v:121281$4642_Y
+ attribute \src "libresoc.v:121267.18-121267.110"
+ wire $or$libresoc.v:121267$4628_Y
+ attribute \src "libresoc.v:121270.18-121270.110"
+ wire $or$libresoc.v:121270$4631_Y
+ attribute \src "libresoc.v:121273.18-121273.110"
+ wire $or$libresoc.v:121273$4634_Y
+ attribute \src "libresoc.v:121275.18-121275.110"
+ wire $or$libresoc.v:121275$4636_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:122268.7-122268.15"
+ attribute \src "libresoc.v:120893.7-120893.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 14 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122637$4679
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121262$4623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:122637$4679_Y
+ connect \Y $and$libresoc.v:121262$4623_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122639$4681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121264$4625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:122639$4681_Y
+ connect \Y $and$libresoc.v:121264$4625_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:122652$4694
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121277$4638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:122652$4694_Y
+ connect \Y $and$libresoc.v:121277$4638_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:122653$4695
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121278$4639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122653$4695_Y
+ connect \Y $and$libresoc.v:121278$4639_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122655$4697
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121280$4641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:122655$4697_Y
+ connect \Y $and$libresoc.v:121280$4641_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:122657$4699
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121282$4643
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:122657$4699_Y
+ connect \Y $and$libresoc.v:121282$4643_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:122658$4700
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121283$4644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:122658$4700_Y
+ connect \Y $and$libresoc.v:121283$4644_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:122659$4701
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121284$4645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:122659$4701_Y
+ connect \Y $and$libresoc.v:121284$4645_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:122640$4682
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:121265$4626
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:122640$4682_Y
+ connect \Y $eq$libresoc.v:121265$4626_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:122641$4683
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:121266$4627
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:122641$4683_Y
+ connect \Y $eq$libresoc.v:121266$4627_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122643$4685
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121268$4629
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:122643$4685_Y
+ connect \Y $eq$libresoc.v:121268$4629_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122644$4686
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121269$4630
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:122644$4686_Y
+ connect \Y $eq$libresoc.v:121269$4630_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:122646$4688
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121271$4632
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:122646$4688_Y
+ connect \Y $eq$libresoc.v:121271$4632_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:122647$4689
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:121272$4633
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:122647$4689_Y
+ connect \Y $eq$libresoc.v:121272$4633_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:122649$4691
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:121274$4635
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:122649$4691_Y
+ connect \Y $eq$libresoc.v:121274$4635_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:122651$4693
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:121276$4637
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:122651$4693_Y
+ connect \Y $eq$libresoc.v:121276$4637_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:122654$4696
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:121279$4640
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:122654$4696_Y
+ connect \Y $eq$libresoc.v:121279$4640_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:122660$4702
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:121285$4646
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_MUL_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:122660$4702_Y
+ connect \Y $eq$libresoc.v:121285$4646_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:122638$4680
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:121263$4624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122638$4680_Y
+ connect \Y $not$libresoc.v:121263$4624_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:122656$4698
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:121281$4642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:122656$4698_Y
+ connect \Y $not$libresoc.v:121281$4642_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:122642$4684
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:121267$4628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:122642$4684_Y
+ connect \Y $or$libresoc.v:121267$4628_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:122645$4687
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:121270$4631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:122645$4687_Y
+ connect \Y $or$libresoc.v:121270$4631_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:122648$4690
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:121273$4634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:122648$4690_Y
+ connect \Y $or$libresoc.v:121273$4634_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:122650$4692
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:121275$4636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:122650$4692_Y
+ connect \Y $or$libresoc.v:121275$4636_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122661.13-122682.4"
+ attribute \src "libresoc.v:121286.13-121307.4"
cell \dec$158 \dec
connect \MUL_BD \dec_MUL_BD
connect \MUL_DS \dec_MUL_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122683.16-122694.4"
+ attribute \src "libresoc.v:121308.16-121319.4"
cell \dec_bi$161 \dec_bi
connect \MUL_BD \dec_MUL_BD
connect \MUL_DS \dec_MUL_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122695.16-122701.4"
+ attribute \src "libresoc.v:121320.16-121326.4"
cell \dec_oe$160 \dec_oe
connect \MUL_OE \dec_MUL_OE
connect \MUL_internal_op \dec_MUL_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:122702.16-122707.4"
+ attribute \src "libresoc.v:121327.16-121332.4"
cell \dec_rc$159 \dec_rc
connect \MUL_Rc \dec_MUL_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:122268.7-122268.20"
- process $proc$libresoc.v:122268$4706
+ attribute \src "libresoc.v:120893.7-120893.20"
+ process $proc$libresoc.v:120893$4650
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:122708.3-122722.6"
- process $proc$libresoc.v:122708$4703
+ attribute \src "libresoc.v:121333.3-121347.6"
+ process $proc$libresoc.v:121333$4647
assign { } { }
assign { } { }
assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0]
- attribute \src "libresoc.v:122709.5-122709.29"
+ attribute \src "libresoc.v:121334.5-121334.29"
switch \initial
- attribute \src "libresoc.v:122709.9-122709.17"
+ attribute \src "libresoc.v:121334.9-121334.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
switch \dec_MUL_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
sync always
update \MUL__write_cr0 $0\MUL__write_cr0[0:0]
end
- attribute \src "libresoc.v:122723.3-122735.6"
- process $proc$libresoc.v:122723$4704
+ attribute \src "libresoc.v:121348.3-121360.6"
+ process $proc$libresoc.v:121348$4648
assign { } { }
assign { } { }
assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0]
- attribute \src "libresoc.v:122724.5-122724.29"
+ attribute \src "libresoc.v:121349.5-121349.29"
switch \initial
- attribute \src "libresoc.v:122724.9-122724.17"
+ attribute \src "libresoc.v:121349.9-121349.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \MUL__insn_type $0\MUL__insn_type[6:0]
end
- attribute \src "libresoc.v:122736.3-122750.6"
- process $proc$libresoc.v:122736$4705
+ attribute \src "libresoc.v:121361.3-121375.6"
+ process $proc$libresoc.v:121361$4649
assign { } { }
assign $0\MUL__fn_unit[12:0] $1\MUL__fn_unit[12:0]
- attribute \src "libresoc.v:122737.5-122737.29"
+ attribute \src "libresoc.v:121362.5-121362.29"
switch \initial
- attribute \src "libresoc.v:122737.9-122737.17"
+ attribute \src "libresoc.v:121362.9-121362.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \MUL__fn_unit $0\MUL__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:122637$4679_Y
- connect \$12 $not$libresoc.v:122638$4680_Y
- connect \$14 $and$libresoc.v:122639$4681_Y
- connect \$16 $eq$libresoc.v:122640$4682_Y
- connect \$18 $eq$libresoc.v:122641$4683_Y
- connect \$20 $or$libresoc.v:122642$4684_Y
- connect \$22 $eq$libresoc.v:122643$4685_Y
- connect \$24 $eq$libresoc.v:122644$4686_Y
- connect \$26 $or$libresoc.v:122645$4687_Y
- connect \$28 $eq$libresoc.v:122646$4688_Y
- connect \$2 $eq$libresoc.v:122647$4689_Y
- connect \$30 $or$libresoc.v:122648$4690_Y
- connect \$32 $eq$libresoc.v:122649$4691_Y
- connect \$34 $or$libresoc.v:122650$4692_Y
- connect \$36 $eq$libresoc.v:122651$4693_Y
- connect \$38 $and$libresoc.v:122652$4694_Y
- connect \$40 $and$libresoc.v:122653$4695_Y
- connect \$42 $eq$libresoc.v:122654$4696_Y
- connect \$44 $and$libresoc.v:122655$4697_Y
- connect \$46 $not$libresoc.v:122656$4698_Y
- connect \$48 $and$libresoc.v:122657$4699_Y
- connect \$4 $and$libresoc.v:122658$4700_Y
- connect \$6 $and$libresoc.v:122659$4701_Y
- connect \$8 $eq$libresoc.v:122660$4702_Y
+ connect \$10 $and$libresoc.v:121262$4623_Y
+ connect \$12 $not$libresoc.v:121263$4624_Y
+ connect \$14 $and$libresoc.v:121264$4625_Y
+ connect \$16 $eq$libresoc.v:121265$4626_Y
+ connect \$18 $eq$libresoc.v:121266$4627_Y
+ connect \$20 $or$libresoc.v:121267$4628_Y
+ connect \$22 $eq$libresoc.v:121268$4629_Y
+ connect \$24 $eq$libresoc.v:121269$4630_Y
+ connect \$26 $or$libresoc.v:121270$4631_Y
+ connect \$28 $eq$libresoc.v:121271$4632_Y
+ connect \$2 $eq$libresoc.v:121272$4633_Y
+ connect \$30 $or$libresoc.v:121273$4634_Y
+ connect \$32 $eq$libresoc.v:121274$4635_Y
+ connect \$34 $or$libresoc.v:121275$4636_Y
+ connect \$36 $eq$libresoc.v:121276$4637_Y
+ connect \$38 $and$libresoc.v:121277$4638_Y
+ connect \$40 $and$libresoc.v:121278$4639_Y
+ connect \$42 $eq$libresoc.v:121279$4640_Y
+ connect \$44 $and$libresoc.v:121280$4641_Y
+ connect \$46 $not$libresoc.v:121281$4642_Y
+ connect \$48 $and$libresoc.v:121282$4643_Y
+ connect \$4 $and$libresoc.v:121283$4644_Y
+ connect \$6 $and$libresoc.v:121284$4645_Y
+ connect \$8 $eq$libresoc.v:121285$4646_Y
connect \MUL__is_signed \dec_MUL_sgn
connect \MUL__is_32bit \dec_MUL_is_32b
connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe }
connect \insn_in \dec_opcode_in
connect \MUL__insn \dec_opcode_in
end
-attribute \src "libresoc.v:122769.1-123311.10"
+attribute \src "libresoc.v:121394.1-121936.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT"
attribute \generator "nMigen"
module \dec_SHIFT_ROT
- attribute \src "libresoc.v:123277.3-123291.6"
+ attribute \src "libresoc.v:121902.3-121916.6"
wire width 13 $0\SHIFT_ROT__fn_unit[12:0]
- attribute \src "libresoc.v:123264.3-123276.6"
+ attribute \src "libresoc.v:121889.3-121901.6"
wire width 7 $0\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:123249.3-123263.6"
+ attribute \src "libresoc.v:121874.3-121888.6"
wire $0\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:122770.7-122770.20"
+ attribute \src "libresoc.v:121395.7-121395.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:123277.3-123291.6"
+ attribute \src "libresoc.v:121902.3-121916.6"
wire width 13 $1\SHIFT_ROT__fn_unit[12:0]
- attribute \src "libresoc.v:123264.3-123276.6"
+ attribute \src "libresoc.v:121889.3-121901.6"
wire width 7 $1\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:123249.3-123263.6"
+ attribute \src "libresoc.v:121874.3-121888.6"
wire $1\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:123174.18-123174.113"
- wire $and$libresoc.v:123174$4707_Y
- attribute \src "libresoc.v:123176.18-123176.110"
- wire $and$libresoc.v:123176$4709_Y
- attribute \src "libresoc.v:123189.18-123189.114"
- wire $and$libresoc.v:123189$4722_Y
- attribute \src "libresoc.v:123190.18-123190.116"
- wire $and$libresoc.v:123190$4723_Y
- attribute \src "libresoc.v:123192.18-123192.114"
- wire $and$libresoc.v:123192$4725_Y
- attribute \src "libresoc.v:123194.18-123194.110"
- wire $and$libresoc.v:123194$4727_Y
- attribute \src "libresoc.v:123195.17-123195.112"
- wire $and$libresoc.v:123195$4728_Y
- attribute \src "libresoc.v:123196.17-123196.114"
- wire $and$libresoc.v:123196$4729_Y
- attribute \src "libresoc.v:123177.18-123177.132"
- wire $eq$libresoc.v:123177$4710_Y
- attribute \src "libresoc.v:123178.18-123178.132"
- wire $eq$libresoc.v:123178$4711_Y
- attribute \src "libresoc.v:123180.18-123180.110"
- wire $eq$libresoc.v:123180$4713_Y
- attribute \src "libresoc.v:123181.18-123181.110"
- wire $eq$libresoc.v:123181$4714_Y
- attribute \src "libresoc.v:123183.18-123183.112"
- wire $eq$libresoc.v:123183$4716_Y
- attribute \src "libresoc.v:123184.17-123184.136"
- wire $eq$libresoc.v:123184$4717_Y
- attribute \src "libresoc.v:123186.18-123186.110"
- wire $eq$libresoc.v:123186$4719_Y
- attribute \src "libresoc.v:123188.18-123188.137"
- wire $eq$libresoc.v:123188$4721_Y
- attribute \src "libresoc.v:123191.18-123191.137"
- wire $eq$libresoc.v:123191$4724_Y
- attribute \src "libresoc.v:123197.17-123197.136"
- wire $eq$libresoc.v:123197$4730_Y
- attribute \src "libresoc.v:123175.18-123175.110"
- wire $not$libresoc.v:123175$4708_Y
- attribute \src "libresoc.v:123193.18-123193.110"
- wire $not$libresoc.v:123193$4726_Y
- attribute \src "libresoc.v:123179.18-123179.110"
- wire $or$libresoc.v:123179$4712_Y
- attribute \src "libresoc.v:123182.18-123182.110"
- wire $or$libresoc.v:123182$4715_Y
- attribute \src "libresoc.v:123185.18-123185.110"
- wire $or$libresoc.v:123185$4718_Y
- attribute \src "libresoc.v:123187.18-123187.110"
- wire $or$libresoc.v:123187$4720_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:121799.18-121799.113"
+ wire $and$libresoc.v:121799$4651_Y
+ attribute \src "libresoc.v:121801.18-121801.110"
+ wire $and$libresoc.v:121801$4653_Y
+ attribute \src "libresoc.v:121814.18-121814.114"
+ wire $and$libresoc.v:121814$4666_Y
+ attribute \src "libresoc.v:121815.18-121815.116"
+ wire $and$libresoc.v:121815$4667_Y
+ attribute \src "libresoc.v:121817.18-121817.114"
+ wire $and$libresoc.v:121817$4669_Y
+ attribute \src "libresoc.v:121819.18-121819.110"
+ wire $and$libresoc.v:121819$4671_Y
+ attribute \src "libresoc.v:121820.17-121820.112"
+ wire $and$libresoc.v:121820$4672_Y
+ attribute \src "libresoc.v:121821.17-121821.114"
+ wire $and$libresoc.v:121821$4673_Y
+ attribute \src "libresoc.v:121802.18-121802.132"
+ wire $eq$libresoc.v:121802$4654_Y
+ attribute \src "libresoc.v:121803.18-121803.132"
+ wire $eq$libresoc.v:121803$4655_Y
+ attribute \src "libresoc.v:121805.18-121805.110"
+ wire $eq$libresoc.v:121805$4657_Y
+ attribute \src "libresoc.v:121806.18-121806.110"
+ wire $eq$libresoc.v:121806$4658_Y
+ attribute \src "libresoc.v:121808.18-121808.112"
+ wire $eq$libresoc.v:121808$4660_Y
+ attribute \src "libresoc.v:121809.17-121809.136"
+ wire $eq$libresoc.v:121809$4661_Y
+ attribute \src "libresoc.v:121811.18-121811.110"
+ wire $eq$libresoc.v:121811$4663_Y
+ attribute \src "libresoc.v:121813.18-121813.137"
+ wire $eq$libresoc.v:121813$4665_Y
+ attribute \src "libresoc.v:121816.18-121816.137"
+ wire $eq$libresoc.v:121816$4668_Y
+ attribute \src "libresoc.v:121822.17-121822.136"
+ wire $eq$libresoc.v:121822$4674_Y
+ attribute \src "libresoc.v:121800.18-121800.110"
+ wire $not$libresoc.v:121800$4652_Y
+ attribute \src "libresoc.v:121818.18-121818.110"
+ wire $not$libresoc.v:121818$4670_Y
+ attribute \src "libresoc.v:121804.18-121804.110"
+ wire $or$libresoc.v:121804$4656_Y
+ attribute \src "libresoc.v:121807.18-121807.110"
+ wire $or$libresoc.v:121807$4659_Y
+ attribute \src "libresoc.v:121810.18-121810.110"
+ wire $or$libresoc.v:121810$4662_Y
+ attribute \src "libresoc.v:121812.18-121812.110"
+ wire $or$libresoc.v:121812$4664_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:122770.7-122770.15"
+ attribute \src "libresoc.v:121395.7-121395.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 19 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123174$4707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121799$4651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:123174$4707_Y
+ connect \Y $and$libresoc.v:121799$4651_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123176$4709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121801$4653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:123176$4709_Y
+ connect \Y $and$libresoc.v:121801$4653_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123189$4722
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121814$4666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:123189$4722_Y
+ connect \Y $and$libresoc.v:121814$4666_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123190$4723
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121815$4667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123190$4723_Y
+ connect \Y $and$libresoc.v:121815$4667_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123192$4725
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121817$4669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:123192$4725_Y
+ connect \Y $and$libresoc.v:121817$4669_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123194$4727
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:121819$4671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:123194$4727_Y
+ connect \Y $and$libresoc.v:121819$4671_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123195$4728
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121820$4672
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:123195$4728_Y
+ connect \Y $and$libresoc.v:121820$4672_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123196$4729
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:121821$4673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123196$4729_Y
+ connect \Y $and$libresoc.v:121821$4673_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:123177$4710
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:121802$4654
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:123177$4710_Y
+ connect \Y $eq$libresoc.v:121802$4654_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:123178$4711
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:121803$4655
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:123178$4711_Y
+ connect \Y $eq$libresoc.v:121803$4655_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123180$4713
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121805$4657
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:123180$4713_Y
+ connect \Y $eq$libresoc.v:121805$4657_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123181$4714
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121806$4658
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:123181$4714_Y
+ connect \Y $eq$libresoc.v:121806$4658_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123183$4716
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:121808$4660
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:123183$4716_Y
+ connect \Y $eq$libresoc.v:121808$4660_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:123184$4717
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:121809$4661
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:123184$4717_Y
+ connect \Y $eq$libresoc.v:121809$4661_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:123186$4719
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:121811$4663
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:123186$4719_Y
+ connect \Y $eq$libresoc.v:121811$4663_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:123188$4721
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:121813$4665
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:123188$4721_Y
+ connect \Y $eq$libresoc.v:121813$4665_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:123191$4724
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:121816$4668
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:123191$4724_Y
+ connect \Y $eq$libresoc.v:121816$4668_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:123197$4730
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:121822$4674
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SHIFT_ROT_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:123197$4730_Y
+ connect \Y $eq$libresoc.v:121822$4674_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:123175$4708
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:121800$4652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123175$4708_Y
+ connect \Y $not$libresoc.v:121800$4652_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:123193$4726
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:121818$4670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123193$4726_Y
+ connect \Y $not$libresoc.v:121818$4670_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:123179$4712
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:121804$4656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:123179$4712_Y
+ connect \Y $or$libresoc.v:121804$4656_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:123182$4715
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:121807$4659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:123182$4715_Y
+ connect \Y $or$libresoc.v:121807$4659_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:123185$4718
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:121810$4662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:123185$4718_Y
+ connect \Y $or$libresoc.v:121810$4662_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:123187$4720
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:121812$4664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:123187$4720_Y
+ connect \Y $or$libresoc.v:121812$4664_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123198.13-123223.4"
+ attribute \src "libresoc.v:121823.13-121848.4"
cell \dec$162 \dec
connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD
connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123224.16-123235.4"
+ attribute \src "libresoc.v:121849.16-121860.4"
cell \dec_bi$165 \dec_bi
connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD
connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS
connect \sel_in \dec_bi_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123236.16-123242.4"
+ attribute \src "libresoc.v:121861.16-121867.4"
cell \dec_oe$164 \dec_oe
connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE
connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123243.16-123248.4"
+ attribute \src "libresoc.v:121868.16-121873.4"
cell \dec_rc$163 \dec_rc
connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:122770.7-122770.20"
- process $proc$libresoc.v:122770$4734
+ attribute \src "libresoc.v:121395.7-121395.20"
+ process $proc$libresoc.v:121395$4678
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:123249.3-123263.6"
- process $proc$libresoc.v:123249$4731
+ attribute \src "libresoc.v:121874.3-121888.6"
+ process $proc$libresoc.v:121874$4675
assign { } { }
assign { } { }
assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0]
- attribute \src "libresoc.v:123250.5-123250.29"
+ attribute \src "libresoc.v:121875.5-121875.29"
switch \initial
- attribute \src "libresoc.v:123250.9-123250.17"
+ attribute \src "libresoc.v:121875.9-121875.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
switch \dec_SHIFT_ROT_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
sync always
update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0]
end
- attribute \src "libresoc.v:123264.3-123276.6"
- process $proc$libresoc.v:123264$4732
+ attribute \src "libresoc.v:121889.3-121901.6"
+ process $proc$libresoc.v:121889$4676
assign { } { }
assign { } { }
assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0]
- attribute \src "libresoc.v:123265.5-123265.29"
+ attribute \src "libresoc.v:121890.5-121890.29"
switch \initial
- attribute \src "libresoc.v:123265.9-123265.17"
+ attribute \src "libresoc.v:121890.9-121890.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0]
end
- attribute \src "libresoc.v:123277.3-123291.6"
- process $proc$libresoc.v:123277$4733
+ attribute \src "libresoc.v:121902.3-121916.6"
+ process $proc$libresoc.v:121902$4677
assign { } { }
assign $0\SHIFT_ROT__fn_unit[12:0] $1\SHIFT_ROT__fn_unit[12:0]
- attribute \src "libresoc.v:123278.5-123278.29"
+ attribute \src "libresoc.v:121903.5-121903.29"
switch \initial
- attribute \src "libresoc.v:123278.9-123278.17"
+ attribute \src "libresoc.v:121903.9-121903.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:123174$4707_Y
- connect \$12 $not$libresoc.v:123175$4708_Y
- connect \$14 $and$libresoc.v:123176$4709_Y
- connect \$16 $eq$libresoc.v:123177$4710_Y
- connect \$18 $eq$libresoc.v:123178$4711_Y
- connect \$20 $or$libresoc.v:123179$4712_Y
- connect \$22 $eq$libresoc.v:123180$4713_Y
- connect \$24 $eq$libresoc.v:123181$4714_Y
- connect \$26 $or$libresoc.v:123182$4715_Y
- connect \$28 $eq$libresoc.v:123183$4716_Y
- connect \$2 $eq$libresoc.v:123184$4717_Y
- connect \$30 $or$libresoc.v:123185$4718_Y
- connect \$32 $eq$libresoc.v:123186$4719_Y
- connect \$34 $or$libresoc.v:123187$4720_Y
- connect \$36 $eq$libresoc.v:123188$4721_Y
- connect \$38 $and$libresoc.v:123189$4722_Y
- connect \$40 $and$libresoc.v:123190$4723_Y
- connect \$42 $eq$libresoc.v:123191$4724_Y
- connect \$44 $and$libresoc.v:123192$4725_Y
- connect \$46 $not$libresoc.v:123193$4726_Y
- connect \$48 $and$libresoc.v:123194$4727_Y
- connect \$4 $and$libresoc.v:123195$4728_Y
- connect \$6 $and$libresoc.v:123196$4729_Y
- connect \$8 $eq$libresoc.v:123197$4730_Y
+ connect \$10 $and$libresoc.v:121799$4651_Y
+ connect \$12 $not$libresoc.v:121800$4652_Y
+ connect \$14 $and$libresoc.v:121801$4653_Y
+ connect \$16 $eq$libresoc.v:121802$4654_Y
+ connect \$18 $eq$libresoc.v:121803$4655_Y
+ connect \$20 $or$libresoc.v:121804$4656_Y
+ connect \$22 $eq$libresoc.v:121805$4657_Y
+ connect \$24 $eq$libresoc.v:121806$4658_Y
+ connect \$26 $or$libresoc.v:121807$4659_Y
+ connect \$28 $eq$libresoc.v:121808$4660_Y
+ connect \$2 $eq$libresoc.v:121809$4661_Y
+ connect \$30 $or$libresoc.v:121810$4662_Y
+ connect \$32 $eq$libresoc.v:121811$4663_Y
+ connect \$34 $or$libresoc.v:121812$4664_Y
+ connect \$36 $eq$libresoc.v:121813$4665_Y
+ connect \$38 $and$libresoc.v:121814$4666_Y
+ connect \$40 $and$libresoc.v:121815$4667_Y
+ connect \$42 $eq$libresoc.v:121816$4668_Y
+ connect \$44 $and$libresoc.v:121817$4669_Y
+ connect \$46 $not$libresoc.v:121818$4670_Y
+ connect \$48 $and$libresoc.v:121819$4671_Y
+ connect \$4 $and$libresoc.v:121820$4672_Y
+ connect \$6 $and$libresoc.v:121821$4673_Y
+ connect \$8 $eq$libresoc.v:121822$4674_Y
connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn
connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b
connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out
connect \insn_in \dec_opcode_in
connect \SHIFT_ROT__insn \dec_opcode_in
end
-attribute \src "libresoc.v:123315.1-123689.10"
+attribute \src "libresoc.v:121940.1-122314.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR"
attribute \generator "nMigen"
module \dec_SPR
- attribute \src "libresoc.v:123665.3-123679.6"
+ attribute \src "libresoc.v:122290.3-122304.6"
wire width 13 $0\SPR__fn_unit[12:0]
- attribute \src "libresoc.v:123652.3-123664.6"
+ attribute \src "libresoc.v:122277.3-122289.6"
wire width 7 $0\SPR__insn_type[6:0]
- attribute \src "libresoc.v:123316.7-123316.20"
+ attribute \src "libresoc.v:121941.7-121941.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:123665.3-123679.6"
+ attribute \src "libresoc.v:122290.3-122304.6"
wire width 13 $1\SPR__fn_unit[12:0]
- attribute \src "libresoc.v:123652.3-123664.6"
+ attribute \src "libresoc.v:122277.3-122289.6"
wire width 7 $1\SPR__insn_type[6:0]
- attribute \src "libresoc.v:123606.18-123606.113"
- wire $and$libresoc.v:123606$4735_Y
- attribute \src "libresoc.v:123608.18-123608.110"
- wire $and$libresoc.v:123608$4737_Y
- attribute \src "libresoc.v:123621.18-123621.114"
- wire $and$libresoc.v:123621$4750_Y
- attribute \src "libresoc.v:123622.18-123622.116"
- wire $and$libresoc.v:123622$4751_Y
- attribute \src "libresoc.v:123624.18-123624.114"
- wire $and$libresoc.v:123624$4753_Y
- attribute \src "libresoc.v:123626.18-123626.110"
- wire $and$libresoc.v:123626$4755_Y
- attribute \src "libresoc.v:123627.17-123627.112"
- wire $and$libresoc.v:123627$4756_Y
- attribute \src "libresoc.v:123628.17-123628.114"
- wire $and$libresoc.v:123628$4757_Y
- attribute \src "libresoc.v:123609.18-123609.126"
- wire $eq$libresoc.v:123609$4738_Y
- attribute \src "libresoc.v:123610.18-123610.126"
- wire $eq$libresoc.v:123610$4739_Y
- attribute \src "libresoc.v:123612.18-123612.110"
- wire $eq$libresoc.v:123612$4741_Y
- attribute \src "libresoc.v:123613.18-123613.110"
- wire $eq$libresoc.v:123613$4742_Y
- attribute \src "libresoc.v:123615.18-123615.112"
- wire $eq$libresoc.v:123615$4744_Y
- attribute \src "libresoc.v:123616.17-123616.130"
- wire $eq$libresoc.v:123616$4745_Y
- attribute \src "libresoc.v:123618.18-123618.110"
- wire $eq$libresoc.v:123618$4747_Y
- attribute \src "libresoc.v:123620.18-123620.131"
- wire $eq$libresoc.v:123620$4749_Y
- attribute \src "libresoc.v:123623.18-123623.131"
- wire $eq$libresoc.v:123623$4752_Y
- attribute \src "libresoc.v:123629.17-123629.130"
- wire $eq$libresoc.v:123629$4758_Y
- attribute \src "libresoc.v:123607.18-123607.110"
- wire $not$libresoc.v:123607$4736_Y
- attribute \src "libresoc.v:123625.18-123625.110"
- wire $not$libresoc.v:123625$4754_Y
- attribute \src "libresoc.v:123611.18-123611.110"
- wire $or$libresoc.v:123611$4740_Y
- attribute \src "libresoc.v:123614.18-123614.110"
- wire $or$libresoc.v:123614$4743_Y
- attribute \src "libresoc.v:123617.18-123617.110"
- wire $or$libresoc.v:123617$4746_Y
- attribute \src "libresoc.v:123619.18-123619.110"
- wire $or$libresoc.v:123619$4748_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "libresoc.v:122231.18-122231.113"
+ wire $and$libresoc.v:122231$4679_Y
+ attribute \src "libresoc.v:122233.18-122233.110"
+ wire $and$libresoc.v:122233$4681_Y
+ attribute \src "libresoc.v:122246.18-122246.114"
+ wire $and$libresoc.v:122246$4694_Y
+ attribute \src "libresoc.v:122247.18-122247.116"
+ wire $and$libresoc.v:122247$4695_Y
+ attribute \src "libresoc.v:122249.18-122249.114"
+ wire $and$libresoc.v:122249$4697_Y
+ attribute \src "libresoc.v:122251.18-122251.110"
+ wire $and$libresoc.v:122251$4699_Y
+ attribute \src "libresoc.v:122252.17-122252.112"
+ wire $and$libresoc.v:122252$4700_Y
+ attribute \src "libresoc.v:122253.17-122253.114"
+ wire $and$libresoc.v:122253$4701_Y
+ attribute \src "libresoc.v:122234.18-122234.126"
+ wire $eq$libresoc.v:122234$4682_Y
+ attribute \src "libresoc.v:122235.18-122235.126"
+ wire $eq$libresoc.v:122235$4683_Y
+ attribute \src "libresoc.v:122237.18-122237.110"
+ wire $eq$libresoc.v:122237$4685_Y
+ attribute \src "libresoc.v:122238.18-122238.110"
+ wire $eq$libresoc.v:122238$4686_Y
+ attribute \src "libresoc.v:122240.18-122240.112"
+ wire $eq$libresoc.v:122240$4688_Y
+ attribute \src "libresoc.v:122241.17-122241.130"
+ wire $eq$libresoc.v:122241$4689_Y
+ attribute \src "libresoc.v:122243.18-122243.110"
+ wire $eq$libresoc.v:122243$4691_Y
+ attribute \src "libresoc.v:122245.18-122245.131"
+ wire $eq$libresoc.v:122245$4693_Y
+ attribute \src "libresoc.v:122248.18-122248.131"
+ wire $eq$libresoc.v:122248$4696_Y
+ attribute \src "libresoc.v:122254.17-122254.130"
+ wire $eq$libresoc.v:122254$4702_Y
+ attribute \src "libresoc.v:122232.18-122232.110"
+ wire $not$libresoc.v:122232$4680_Y
+ attribute \src "libresoc.v:122250.18-122250.110"
+ wire $not$libresoc.v:122250$4698_Y
+ attribute \src "libresoc.v:122236.18-122236.110"
+ wire $or$libresoc.v:122236$4684_Y
+ attribute \src "libresoc.v:122239.18-122239.110"
+ wire $or$libresoc.v:122239$4687_Y
+ attribute \src "libresoc.v:122242.18-122242.110"
+ wire $or$libresoc.v:122242$4690_Y
+ attribute \src "libresoc.v:122244.18-122244.110"
+ wire $or$libresoc.v:122244$4692_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- wire \$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ wire \$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 \dec_rc_sel_in
- attribute \src "libresoc.v:123316.7-123316.15"
+ attribute \src "libresoc.v:121941.7-121941.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437"
wire width 32 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
wire width 32 input 6 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123606$4735
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:122231$4679
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$8
- connect \Y $and$libresoc.v:123606$4735_Y
+ connect \Y $and$libresoc.v:122231$4679_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123608$4737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:122233$4681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$10
connect \B \$12
- connect \Y $and$libresoc.v:123608$4737_Y
+ connect \Y $and$libresoc.v:122233$4681_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123621$4750
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:122246$4694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$36
- connect \Y $and$libresoc.v:123621$4750_Y
+ connect \Y $and$libresoc.v:122246$4694_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123622$4751
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:122247$4695
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123622$4751_Y
+ connect \Y $and$libresoc.v:122247$4695_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123624$4753
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:122249$4697
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$42
- connect \Y $and$libresoc.v:123624$4753_Y
+ connect \Y $and$libresoc.v:122249$4697_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $and $and$libresoc.v:123626$4755
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $and $and$libresoc.v:122251$4699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:123626$4755_Y
+ connect \Y $and$libresoc.v:122251$4699_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123627$4756
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:122252$4700
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_spr_mv
connect \B \$2
- connect \Y $and$libresoc.v:123627$4756_Y
+ connect \Y $and$libresoc.v:122252$4700_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $and $and$libresoc.v:123628$4757
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $and $and$libresoc.v:122253$4701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$4
connect \B \is_mmu_spr
- connect \Y $and$libresoc.v:123628$4757_Y
+ connect \Y $and$libresoc.v:122253$4701_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803"
- cell $eq $eq$libresoc.v:123609$4738
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809"
+ cell $eq $eq$libresoc.v:122234$4682
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:123609$4738_Y
+ connect \Y $eq$libresoc.v:122234$4682_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $eq $eq$libresoc.v:123610$4739
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $eq $eq$libresoc.v:122235$4683
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:123610$4739_Y
+ connect \Y $eq$libresoc.v:122235$4683_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123612$4741
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:122237$4685
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10010
- connect \Y $eq$libresoc.v:123612$4741_Y
+ connect \Y $eq$libresoc.v:122237$4685_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123613$4742
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:122238$4686
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 5'10011
- connect \Y $eq$libresoc.v:123613$4742_Y
+ connect \Y $eq$libresoc.v:122238$4686_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $eq $eq$libresoc.v:123615$4744
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $eq $eq$libresoc.v:122240$4688
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'1011010000
- connect \Y $eq$libresoc.v:123615$4744_Y
+ connect \Y $eq$libresoc.v:122240$4688_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:123616$4745
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:122241$4689
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:123616$4745_Y
+ connect \Y $eq$libresoc.v:122241$4689_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $eq $eq$libresoc.v:123618$4747
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $eq $eq$libresoc.v:122243$4691
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 6'110000
- connect \Y $eq$libresoc.v:123618$4747_Y
+ connect \Y $eq$libresoc.v:122243$4691_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
- cell $eq $eq$libresoc.v:123620$4749
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ cell $eq $eq$libresoc.v:122245$4693
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 13'0010000000000
- connect \Y $eq$libresoc.v:123620$4749_Y
+ connect \Y $eq$libresoc.v:122245$4693_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:123623$4752
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:122248$4696
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:123623$4752_Y
+ connect \Y $eq$libresoc.v:122248$4696_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $eq $eq$libresoc.v:123629$4758
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $eq $eq$libresoc.v:122254$4702
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_SPR_function_unit
connect \B 13'0100000000000
- connect \Y $eq$libresoc.v:123629$4758_Y
+ connect \Y $eq$libresoc.v:122254$4702_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:123607$4736
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:122232$4680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123607$4736_Y
+ connect \Y $not$libresoc.v:122232$4680_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
- cell $not $not$libresoc.v:123625$4754
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ cell $not $not$libresoc.v:122250$4698
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_mmu_spr
- connect \Y $not$libresoc.v:123625$4754_Y
+ connect \Y $not$libresoc.v:122250$4698_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804"
- cell $or $or$libresoc.v:123611$4740
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ cell $or $or$libresoc.v:122236$4684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$16
connect \B \$18
- connect \Y $or$libresoc.v:123611$4740_Y
+ connect \Y $or$libresoc.v:122236$4684_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:123614$4743
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:122239$4687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$22
connect \B \$24
- connect \Y $or$libresoc.v:123614$4743_Y
+ connect \Y $or$libresoc.v:122239$4687_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807"
- cell $or $or$libresoc.v:123617$4746
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ cell $or $or$libresoc.v:122242$4690
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$26
connect \B \$28
- connect \Y $or$libresoc.v:123617$4746_Y
+ connect \Y $or$libresoc.v:122242$4690_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
- cell $or $or$libresoc.v:123619$4748
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ cell $or $or$libresoc.v:122244$4692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:123619$4748_Y
+ connect \Y $or$libresoc.v:122244$4692_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123630.13-123642.4"
+ attribute \src "libresoc.v:122255.13-122267.4"
cell \dec$150 \dec
connect \SPR_OE \dec_SPR_OE
connect \SPR_Rc \dec_SPR_Rc
connect \raw_opcode_in \raw_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123643.16-123647.4"
+ attribute \src "libresoc.v:122268.16-122272.4"
cell \dec_oe$152 \dec_oe
connect \SPR_OE \dec_SPR_OE
connect \SPR_internal_op \dec_SPR_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:123648.16-123651.4"
+ attribute \src "libresoc.v:122273.16-122276.4"
cell \dec_rc$151 \dec_rc
connect \SPR_Rc \dec_SPR_Rc
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:123316.7-123316.20"
- process $proc$libresoc.v:123316$4761
+ attribute \src "libresoc.v:121941.7-121941.20"
+ process $proc$libresoc.v:121941$4705
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:123652.3-123664.6"
- process $proc$libresoc.v:123652$4759
+ attribute \src "libresoc.v:122277.3-122289.6"
+ process $proc$libresoc.v:122277$4703
assign { } { }
assign { } { }
assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0]
- attribute \src "libresoc.v:123653.5-123653.29"
+ attribute \src "libresoc.v:122278.5-122278.29"
switch \initial
- attribute \src "libresoc.v:123653.9-123653.17"
+ attribute \src "libresoc.v:122278.9-122278.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \SPR__insn_type $0\SPR__insn_type[6:0]
end
- attribute \src "libresoc.v:123665.3-123679.6"
- process $proc$libresoc.v:123665$4760
+ attribute \src "libresoc.v:122290.3-122304.6"
+ process $proc$libresoc.v:122290$4704
assign { } { }
assign $0\SPR__fn_unit[12:0] $1\SPR__fn_unit[12:0]
- attribute \src "libresoc.v:123666.5-123666.29"
+ attribute \src "libresoc.v:122291.5-122291.29"
switch \initial
- attribute \src "libresoc.v:123666.9-123666.17"
+ attribute \src "libresoc.v:122291.9-122291.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
sync always
update \SPR__fn_unit $0\SPR__fn_unit[12:0]
end
- connect \$10 $and$libresoc.v:123606$4735_Y
- connect \$12 $not$libresoc.v:123607$4736_Y
- connect \$14 $and$libresoc.v:123608$4737_Y
- connect \$16 $eq$libresoc.v:123609$4738_Y
- connect \$18 $eq$libresoc.v:123610$4739_Y
- connect \$20 $or$libresoc.v:123611$4740_Y
- connect \$22 $eq$libresoc.v:123612$4741_Y
- connect \$24 $eq$libresoc.v:123613$4742_Y
- connect \$26 $or$libresoc.v:123614$4743_Y
- connect \$28 $eq$libresoc.v:123615$4744_Y
- connect \$2 $eq$libresoc.v:123616$4745_Y
- connect \$30 $or$libresoc.v:123617$4746_Y
- connect \$32 $eq$libresoc.v:123618$4747_Y
- connect \$34 $or$libresoc.v:123619$4748_Y
- connect \$36 $eq$libresoc.v:123620$4749_Y
- connect \$38 $and$libresoc.v:123621$4750_Y
- connect \$40 $and$libresoc.v:123622$4751_Y
- connect \$42 $eq$libresoc.v:123623$4752_Y
- connect \$44 $and$libresoc.v:123624$4753_Y
- connect \$46 $not$libresoc.v:123625$4754_Y
- connect \$48 $and$libresoc.v:123626$4755_Y
- connect \$4 $and$libresoc.v:123627$4756_Y
- connect \$6 $and$libresoc.v:123628$4757_Y
- connect \$8 $eq$libresoc.v:123629$4758_Y
+ connect \$10 $and$libresoc.v:122231$4679_Y
+ connect \$12 $not$libresoc.v:122232$4680_Y
+ connect \$14 $and$libresoc.v:122233$4681_Y
+ connect \$16 $eq$libresoc.v:122234$4682_Y
+ connect \$18 $eq$libresoc.v:122235$4683_Y
+ connect \$20 $or$libresoc.v:122236$4684_Y
+ connect \$22 $eq$libresoc.v:122237$4685_Y
+ connect \$24 $eq$libresoc.v:122238$4686_Y
+ connect \$26 $or$libresoc.v:122239$4687_Y
+ connect \$28 $eq$libresoc.v:122240$4688_Y
+ connect \$2 $eq$libresoc.v:122241$4689_Y
+ connect \$30 $or$libresoc.v:122242$4690_Y
+ connect \$32 $eq$libresoc.v:122243$4691_Y
+ connect \$34 $or$libresoc.v:122244$4692_Y
+ connect \$36 $eq$libresoc.v:122245$4693_Y
+ connect \$38 $and$libresoc.v:122246$4694_Y
+ connect \$40 $and$libresoc.v:122247$4695_Y
+ connect \$42 $eq$libresoc.v:122248$4696_Y
+ connect \$44 $and$libresoc.v:122249$4697_Y
+ connect \$46 $not$libresoc.v:122250$4698_Y
+ connect \$48 $and$libresoc.v:122251$4699_Y
+ connect \$4 $and$libresoc.v:122252$4700_Y
+ connect \$6 $and$libresoc.v:122253$4701_Y
+ connect \$8 $eq$libresoc.v:122254$4702_Y
connect \SPR__is_32bit \dec_SPR_is_32b
connect \is_mmu_spr \$34
connect \is_spr_mv \$20
connect \insn_in \dec_opcode_in
connect \SPR__insn \dec_opcode_in
end
-attribute \src "libresoc.v:123693.1-124207.10"
+attribute \src "libresoc.v:122318.1-122832.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a"
attribute \generator "nMigen"
module \dec_a
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire width 3 $0\fast_a[2:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire $0\fast_a_ok[0:0]
- attribute \src "libresoc.v:123694.7-123694.20"
+ attribute \src "libresoc.v:122319.7-122319.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124103.3-124118.6"
+ attribute \src "libresoc.v:122728.3-122743.6"
wire width 5 $0\reg_a[4:0]
- attribute \src "libresoc.v:124119.3-124134.6"
+ attribute \src "libresoc.v:122744.3-122759.6"
wire $0\reg_a_ok[0:0]
- attribute \src "libresoc.v:124171.3-124181.6"
+ attribute \src "libresoc.v:122796.3-122806.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:124193.3-124204.6"
+ attribute \src "libresoc.v:122818.3-122829.6"
wire width 10 $0\spr_a[9:0]
- attribute \src "libresoc.v:124193.3-124204.6"
+ attribute \src "libresoc.v:122818.3-122829.6"
wire $0\spr_a_ok[0:0]
- attribute \src "libresoc.v:124182.3-124192.6"
+ attribute \src "libresoc.v:122807.3-122817.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire width 3 $1\fast_a[2:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:124103.3-124118.6"
+ attribute \src "libresoc.v:122728.3-122743.6"
wire width 5 $1\reg_a[4:0]
- attribute \src "libresoc.v:124119.3-124134.6"
+ attribute \src "libresoc.v:122744.3-122759.6"
wire $1\reg_a_ok[0:0]
- attribute \src "libresoc.v:124171.3-124181.6"
+ attribute \src "libresoc.v:122796.3-122806.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:124193.3-124204.6"
+ attribute \src "libresoc.v:122818.3-122829.6"
wire width 10 $1\spr_a[9:0]
- attribute \src "libresoc.v:124193.3-124204.6"
+ attribute \src "libresoc.v:122818.3-122829.6"
wire $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:124182.3-124192.6"
+ attribute \src "libresoc.v:122807.3-122817.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire width 3 $2\fast_a[2:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire $2\fast_a_ok[0:0]
- attribute \src "libresoc.v:124103.3-124118.6"
+ attribute \src "libresoc.v:122728.3-122743.6"
wire width 5 $2\reg_a[4:0]
- attribute \src "libresoc.v:124119.3-124134.6"
+ attribute \src "libresoc.v:122744.3-122759.6"
wire $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire width 3 $3\fast_a[2:0]
- attribute \src "libresoc.v:124135.3-124170.6"
+ attribute \src "libresoc.v:122760.3-122795.6"
wire $3\fast_a_ok[0:0]
- attribute \src "libresoc.v:124087.18-124087.110"
- wire $and$libresoc.v:124087$4768_Y
- attribute \src "libresoc.v:124092.18-124092.113"
- wire $and$libresoc.v:124092$4773_Y
- attribute \src "libresoc.v:124095.17-124095.107"
- wire $and$libresoc.v:124095$4776_Y
- attribute \src "libresoc.v:124082.18-124082.112"
- wire $eq$libresoc.v:124082$4763_Y
- attribute \src "libresoc.v:124083.18-124083.112"
- wire $eq$libresoc.v:124083$4764_Y
- attribute \src "libresoc.v:124084.18-124084.112"
- wire $eq$libresoc.v:124084$4765_Y
- attribute \src "libresoc.v:124086.17-124086.111"
- wire $eq$libresoc.v:124086$4767_Y
- attribute \src "libresoc.v:124089.18-124089.112"
- wire $eq$libresoc.v:124089$4770_Y
- attribute \src "libresoc.v:124093.17-124093.111"
- wire $eq$libresoc.v:124093$4774_Y
- attribute \src "libresoc.v:124085.18-124085.109"
- wire $ne$libresoc.v:124085$4766_Y
- attribute \src "libresoc.v:124094.17-124094.108"
- wire $ne$libresoc.v:124094$4775_Y
- attribute \src "libresoc.v:124090.18-124090.105"
- wire $not$libresoc.v:124090$4771_Y
- attribute \src "libresoc.v:124091.18-124091.108"
- wire $not$libresoc.v:124091$4772_Y
- attribute \src "libresoc.v:124081.17-124081.107"
- wire $or$libresoc.v:124081$4762_Y
- attribute \src "libresoc.v:124088.18-124088.110"
- wire $or$libresoc.v:124088$4769_Y
+ attribute \src "libresoc.v:122712.18-122712.110"
+ wire $and$libresoc.v:122712$4712_Y
+ attribute \src "libresoc.v:122717.18-122717.113"
+ wire $and$libresoc.v:122717$4717_Y
+ attribute \src "libresoc.v:122720.17-122720.107"
+ wire $and$libresoc.v:122720$4720_Y
+ attribute \src "libresoc.v:122707.18-122707.112"
+ wire $eq$libresoc.v:122707$4707_Y
+ attribute \src "libresoc.v:122708.18-122708.112"
+ wire $eq$libresoc.v:122708$4708_Y
+ attribute \src "libresoc.v:122709.18-122709.112"
+ wire $eq$libresoc.v:122709$4709_Y
+ attribute \src "libresoc.v:122711.17-122711.111"
+ wire $eq$libresoc.v:122711$4711_Y
+ attribute \src "libresoc.v:122714.18-122714.112"
+ wire $eq$libresoc.v:122714$4714_Y
+ attribute \src "libresoc.v:122718.17-122718.111"
+ wire $eq$libresoc.v:122718$4718_Y
+ attribute \src "libresoc.v:122710.18-122710.109"
+ wire $ne$libresoc.v:122710$4710_Y
+ attribute \src "libresoc.v:122719.17-122719.108"
+ wire $ne$libresoc.v:122719$4719_Y
+ attribute \src "libresoc.v:122715.18-122715.105"
+ wire $not$libresoc.v:122715$4715_Y
+ attribute \src "libresoc.v:122716.18-122716.108"
+ wire $not$libresoc.v:122716$4716_Y
+ attribute \src "libresoc.v:122706.17-122706.107"
+ wire $or$libresoc.v:122706$4706_Y
+ attribute \src "libresoc.v:122713.18-122713.110"
+ wire $or$libresoc.v:122713$4713_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
wire width 3 output 7 \fast_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 8 \fast_a_ok
- attribute \src "libresoc.v:123694.7-123694.15"
+ attribute \src "libresoc.v:122319.7-122319.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \sprmap_spr_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $and $and$libresoc.v:124087$4768
+ cell $and $and$libresoc.v:122712$4712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \$17
- connect \Y $and$libresoc.v:124087$4768_Y
+ connect \Y $and$libresoc.v:122712$4712_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
- cell $and $and$libresoc.v:124092$4773
+ cell $and $and$libresoc.v:122717$4717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
connect \B \$27
- connect \Y $and$libresoc.v:124092$4773_Y
+ connect \Y $and$libresoc.v:122717$4717_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $and $and$libresoc.v:124095$4776
+ cell $and $and$libresoc.v:122720$4720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:124095$4776_Y
+ connect \Y $and$libresoc.v:122720$4720_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
- cell $eq $eq$libresoc.v:124082$4763
+ cell $eq $eq$libresoc.v:122707$4707
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:124082$4763_Y
+ connect \Y $eq$libresoc.v:122707$4707_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
- cell $eq $eq$libresoc.v:124083$4764
+ cell $eq $eq$libresoc.v:122708$4708
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:124083$4764_Y
+ connect \Y $eq$libresoc.v:122708$4708_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
- cell $eq $eq$libresoc.v:124084$4765
+ cell $eq $eq$libresoc.v:122709$4709
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124084$4765_Y
+ connect \Y $eq$libresoc.v:122709$4709_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
- cell $eq $eq$libresoc.v:124086$4767
+ cell $eq $eq$libresoc.v:122711$4711
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:124086$4767_Y
+ connect \Y $eq$libresoc.v:122711$4711_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
- cell $eq $eq$libresoc.v:124089$4770
+ cell $eq $eq$libresoc.v:122714$4714
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:124089$4770_Y
+ connect \Y $eq$libresoc.v:122714$4714_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
- cell $eq $eq$libresoc.v:124093$4774
+ cell $eq $eq$libresoc.v:122718$4718
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124093$4774_Y
+ connect \Y $eq$libresoc.v:122718$4718_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $ne $ne$libresoc.v:124085$4766
+ cell $ne $ne$libresoc.v:122710$4710
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:124085$4766_Y
+ connect \Y $ne$libresoc.v:122710$4710_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $ne $ne$libresoc.v:124094$4775
+ cell $ne $ne$libresoc.v:122719$4719
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:124094$4775_Y
+ connect \Y $ne$libresoc.v:122719$4719_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
- cell $not $not$libresoc.v:124090$4771
+ cell $not $not$libresoc.v:122715$4715
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:124090$4771_Y
+ connect \Y $not$libresoc.v:122715$4715_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
- cell $not $not$libresoc.v:124091$4772
+ cell $not $not$libresoc.v:122716$4716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [5]
- connect \Y $not$libresoc.v:124091$4772_Y
+ connect \Y $not$libresoc.v:122716$4716_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $or $or$libresoc.v:124081$4762
+ cell $or $or$libresoc.v:122706$4706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$7
- connect \Y $or$libresoc.v:124081$4762_Y
+ connect \Y $or$libresoc.v:122706$4706_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
- cell $or $or$libresoc.v:124088$4769
+ cell $or $or$libresoc.v:122713$4713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$13
connect \B \$19
- connect \Y $or$libresoc.v:124088$4769_Y
+ connect \Y $or$libresoc.v:122713$4713_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:124096.10-124102.4"
+ attribute \src "libresoc.v:122721.10-122727.4"
cell \sprmap \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:123694.7-123694.20"
- process $proc$libresoc.v:123694$4783
+ attribute \src "libresoc.v:122319.7-122319.20"
+ process $proc$libresoc.v:122319$4727
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124103.3-124118.6"
- process $proc$libresoc.v:124103$4777
+ attribute \src "libresoc.v:122728.3-122743.6"
+ process $proc$libresoc.v:122728$4721
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a[4:0] $2\reg_a[4:0]
- attribute \src "libresoc.v:124104.5-124104.29"
+ attribute \src "libresoc.v:122729.5-122729.29"
switch \initial
- attribute \src "libresoc.v:124104.9-124104.17"
+ attribute \src "libresoc.v:122729.9-122729.17"
case 1'1
case
end
sync always
update \reg_a $0\reg_a[4:0]
end
- attribute \src "libresoc.v:124119.3-124134.6"
- process $proc$libresoc.v:124119$4778
+ attribute \src "libresoc.v:122744.3-122759.6"
+ process $proc$libresoc.v:122744$4722
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:124120.5-124120.29"
+ attribute \src "libresoc.v:122745.5-122745.29"
switch \initial
- attribute \src "libresoc.v:124120.9-124120.17"
+ attribute \src "libresoc.v:122745.9-122745.17"
case 1'1
case
end
sync always
update \reg_a_ok $0\reg_a_ok[0:0]
end
- attribute \src "libresoc.v:124135.3-124170.6"
- process $proc$libresoc.v:124135$4779
+ attribute \src "libresoc.v:122760.3-122795.6"
+ process $proc$libresoc.v:122760$4723
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_a[2:0] $1\fast_a[2:0]
assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:124136.5-124136.29"
+ attribute \src "libresoc.v:122761.5-122761.29"
switch \initial
- attribute \src "libresoc.v:124136.9-124136.17"
+ attribute \src "libresoc.v:122761.9-122761.17"
case 1'1
case
end
update \fast_a $0\fast_a[2:0]
update \fast_a_ok $0\fast_a_ok[0:0]
end
- attribute \src "libresoc.v:124171.3-124181.6"
- process $proc$libresoc.v:124171$4780
+ attribute \src "libresoc.v:122796.3-122806.6"
+ process $proc$libresoc.v:122796$4724
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:124172.5-124172.29"
+ attribute \src "libresoc.v:122797.5-122797.29"
switch \initial
- attribute \src "libresoc.v:124172.9-124172.17"
+ attribute \src "libresoc.v:122797.9-122797.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:124182.3-124192.6"
- process $proc$libresoc.v:124182$4781
+ attribute \src "libresoc.v:122807.3-122817.6"
+ process $proc$libresoc.v:122807$4725
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:124183.5-124183.29"
+ attribute \src "libresoc.v:122808.5-122808.29"
switch \initial
- attribute \src "libresoc.v:124183.9-124183.17"
+ attribute \src "libresoc.v:122808.9-122808.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:124193.3-124204.6"
- process $proc$libresoc.v:124193$4782
+ attribute \src "libresoc.v:122818.3-122829.6"
+ process $proc$libresoc.v:122818$4726
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_a[9:0] $1\spr_a[9:0]
assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:124194.5-124194.29"
+ attribute \src "libresoc.v:122819.5-122819.29"
switch \initial
- attribute \src "libresoc.v:124194.9-124194.17"
+ attribute \src "libresoc.v:122819.9-122819.17"
case 1'1
case
end
update \spr_a $0\spr_a[9:0]
update \spr_a_ok $0\spr_a_ok[0:0]
end
- connect \$9 $or$libresoc.v:124081$4762_Y
- connect \$11 $eq$libresoc.v:124082$4763_Y
- connect \$13 $eq$libresoc.v:124083$4764_Y
- connect \$15 $eq$libresoc.v:124084$4765_Y
- connect \$17 $ne$libresoc.v:124085$4766_Y
- connect \$1 $eq$libresoc.v:124086$4767_Y
- connect \$19 $and$libresoc.v:124087$4768_Y
- connect \$21 $or$libresoc.v:124088$4769_Y
- connect \$23 $eq$libresoc.v:124089$4770_Y
- connect \$25 $not$libresoc.v:124090$4771_Y
- connect \$27 $not$libresoc.v:124091$4772_Y
- connect \$29 $and$libresoc.v:124092$4773_Y
- connect \$3 $eq$libresoc.v:124093$4774_Y
- connect \$5 $ne$libresoc.v:124094$4775_Y
- connect \$7 $and$libresoc.v:124095$4776_Y
+ connect \$9 $or$libresoc.v:122706$4706_Y
+ connect \$11 $eq$libresoc.v:122707$4707_Y
+ connect \$13 $eq$libresoc.v:122708$4708_Y
+ connect \$15 $eq$libresoc.v:122709$4709_Y
+ connect \$17 $ne$libresoc.v:122710$4710_Y
+ connect \$1 $eq$libresoc.v:122711$4711_Y
+ connect \$19 $and$libresoc.v:122712$4712_Y
+ connect \$21 $or$libresoc.v:122713$4713_Y
+ connect \$23 $eq$libresoc.v:122714$4714_Y
+ connect \$25 $not$libresoc.v:122715$4715_Y
+ connect \$27 $not$libresoc.v:122716$4716_Y
+ connect \$29 $and$libresoc.v:122717$4717_Y
+ connect \$3 $eq$libresoc.v:122718$4718_Y
+ connect \$5 $ne$libresoc.v:122719$4719_Y
+ connect \$7 $and$libresoc.v:122720$4720_Y
connect \rs \RS
connect \ra \RA
end
-attribute \src "libresoc.v:124211.1-124248.10"
+attribute \src "libresoc.v:122836.1-122873.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai"
attribute \generator "nMigen"
module \dec_ai
- attribute \src "libresoc.v:124237.3-124246.6"
+ attribute \src "libresoc.v:122862.3-122871.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:124212.7-124212.20"
+ attribute \src "libresoc.v:122837.7-122837.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124237.3-124246.6"
+ attribute \src "libresoc.v:122862.3-122871.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:124236.17-124236.107"
- wire $and$libresoc.v:124236$4786_Y
- attribute \src "libresoc.v:124234.17-124234.111"
- wire $eq$libresoc.v:124234$4784_Y
- attribute \src "libresoc.v:124235.17-124235.108"
- wire $eq$libresoc.v:124235$4785_Y
+ attribute \src "libresoc.v:122861.17-122861.107"
+ wire $and$libresoc.v:122861$4730_Y
+ attribute \src "libresoc.v:122859.17-122859.111"
+ wire $eq$libresoc.v:122859$4728_Y
+ attribute \src "libresoc.v:122860.17-122860.108"
+ wire $eq$libresoc.v:122860$4729_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire width 5 input 2 \ALU_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162"
wire output 1 \immz_out
- attribute \src "libresoc.v:124212.7-124212.15"
+ attribute \src "libresoc.v:122837.7-122837.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 3 input 3 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $and $and$libresoc.v:124236$4786
+ cell $and $and$libresoc.v:122861$4730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:124236$4786_Y
+ connect \Y $and$libresoc.v:122861$4730_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124234$4784
+ cell $eq $eq$libresoc.v:122859$4728
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124234$4784_Y
+ connect \Y $eq$libresoc.v:122859$4728_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124235$4785
+ cell $eq $eq$libresoc.v:122860$4729
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:124235$4785_Y
+ connect \Y $eq$libresoc.v:122860$4729_Y
end
- attribute \src "libresoc.v:124212.7-124212.20"
- process $proc$libresoc.v:124212$4788
+ attribute \src "libresoc.v:122837.7-122837.20"
+ process $proc$libresoc.v:122837$4732
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124237.3-124246.6"
- process $proc$libresoc.v:124237$4787
+ attribute \src "libresoc.v:122862.3-122871.6"
+ process $proc$libresoc.v:122862$4731
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:124238.5-124238.29"
+ attribute \src "libresoc.v:122863.5-122863.29"
switch \initial
- attribute \src "libresoc.v:124238.9-124238.17"
+ attribute \src "libresoc.v:122863.9-122863.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$1 $eq$libresoc.v:124234$4784_Y
- connect \$3 $eq$libresoc.v:124235$4785_Y
- connect \$5 $and$libresoc.v:124236$4786_Y
+ connect \$1 $eq$libresoc.v:122859$4728_Y
+ connect \$3 $eq$libresoc.v:122860$4729_Y
+ connect \$5 $and$libresoc.v:122861$4730_Y
connect \ra \ALU_RA
end
-attribute \src "libresoc.v:124252.1-124289.10"
+attribute \src "libresoc.v:122877.1-122914.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai"
attribute \generator "nMigen"
module \dec_ai$148
- attribute \src "libresoc.v:124278.3-124287.6"
+ attribute \src "libresoc.v:122903.3-122912.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:124253.7-124253.20"
+ attribute \src "libresoc.v:122878.7-122878.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124278.3-124287.6"
+ attribute \src "libresoc.v:122903.3-122912.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:124277.17-124277.107"
- wire $and$libresoc.v:124277$4791_Y
- attribute \src "libresoc.v:124275.17-124275.111"
- wire $eq$libresoc.v:124275$4789_Y
- attribute \src "libresoc.v:124276.17-124276.108"
- wire $eq$libresoc.v:124276$4790_Y
+ attribute \src "libresoc.v:122902.17-122902.107"
+ wire $and$libresoc.v:122902$4735_Y
+ attribute \src "libresoc.v:122900.17-122900.111"
+ wire $eq$libresoc.v:122900$4733_Y
+ attribute \src "libresoc.v:122901.17-122901.108"
+ wire $eq$libresoc.v:122901$4734_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire width 5 input 2 \LOGICAL_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162"
wire output 1 \immz_out
- attribute \src "libresoc.v:124253.7-124253.15"
+ attribute \src "libresoc.v:122878.7-122878.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 3 input 3 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $and $and$libresoc.v:124277$4791
+ cell $and $and$libresoc.v:122902$4735
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:124277$4791_Y
+ connect \Y $and$libresoc.v:122902$4735_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124275$4789
+ cell $eq $eq$libresoc.v:122900$4733
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124275$4789_Y
+ connect \Y $eq$libresoc.v:122900$4733_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124276$4790
+ cell $eq $eq$libresoc.v:122901$4734
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:124276$4790_Y
+ connect \Y $eq$libresoc.v:122901$4734_Y
end
- attribute \src "libresoc.v:124253.7-124253.20"
- process $proc$libresoc.v:124253$4793
+ attribute \src "libresoc.v:122878.7-122878.20"
+ process $proc$libresoc.v:122878$4737
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124278.3-124287.6"
- process $proc$libresoc.v:124278$4792
+ attribute \src "libresoc.v:122903.3-122912.6"
+ process $proc$libresoc.v:122903$4736
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:124279.5-124279.29"
+ attribute \src "libresoc.v:122904.5-122904.29"
switch \initial
- attribute \src "libresoc.v:124279.9-124279.17"
+ attribute \src "libresoc.v:122904.9-122904.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$1 $eq$libresoc.v:124275$4789_Y
- connect \$3 $eq$libresoc.v:124276$4790_Y
- connect \$5 $and$libresoc.v:124277$4791_Y
+ connect \$1 $eq$libresoc.v:122900$4733_Y
+ connect \$3 $eq$libresoc.v:122901$4734_Y
+ connect \$5 $and$libresoc.v:122902$4735_Y
connect \ra \LOGICAL_RA
end
-attribute \src "libresoc.v:124293.1-124330.10"
+attribute \src "libresoc.v:122918.1-122955.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai"
attribute \generator "nMigen"
module \dec_ai$156
- attribute \src "libresoc.v:124319.3-124328.6"
+ attribute \src "libresoc.v:122944.3-122953.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:124294.7-124294.20"
+ attribute \src "libresoc.v:122919.7-122919.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124319.3-124328.6"
+ attribute \src "libresoc.v:122944.3-122953.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:124318.17-124318.107"
- wire $and$libresoc.v:124318$4796_Y
- attribute \src "libresoc.v:124316.17-124316.111"
- wire $eq$libresoc.v:124316$4794_Y
- attribute \src "libresoc.v:124317.17-124317.108"
- wire $eq$libresoc.v:124317$4795_Y
+ attribute \src "libresoc.v:122943.17-122943.107"
+ wire $and$libresoc.v:122943$4740_Y
+ attribute \src "libresoc.v:122941.17-122941.111"
+ wire $eq$libresoc.v:122941$4738_Y
+ attribute \src "libresoc.v:122942.17-122942.108"
+ wire $eq$libresoc.v:122942$4739_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire width 5 input 2 \DIV_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162"
wire output 1 \immz_out
- attribute \src "libresoc.v:124294.7-124294.15"
+ attribute \src "libresoc.v:122919.7-122919.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 3 input 3 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $and $and$libresoc.v:124318$4796
+ cell $and $and$libresoc.v:122943$4740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:124318$4796_Y
+ connect \Y $and$libresoc.v:122943$4740_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124316$4794
+ cell $eq $eq$libresoc.v:122941$4738
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124316$4794_Y
+ connect \Y $eq$libresoc.v:122941$4738_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124317$4795
+ cell $eq $eq$libresoc.v:122942$4739
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:124317$4795_Y
+ connect \Y $eq$libresoc.v:122942$4739_Y
end
- attribute \src "libresoc.v:124294.7-124294.20"
- process $proc$libresoc.v:124294$4798
+ attribute \src "libresoc.v:122919.7-122919.20"
+ process $proc$libresoc.v:122919$4742
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124319.3-124328.6"
- process $proc$libresoc.v:124319$4797
+ attribute \src "libresoc.v:122944.3-122953.6"
+ process $proc$libresoc.v:122944$4741
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:124320.5-124320.29"
+ attribute \src "libresoc.v:122945.5-122945.29"
switch \initial
- attribute \src "libresoc.v:124320.9-124320.17"
+ attribute \src "libresoc.v:122945.9-122945.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$1 $eq$libresoc.v:124316$4794_Y
- connect \$3 $eq$libresoc.v:124317$4795_Y
- connect \$5 $and$libresoc.v:124318$4796_Y
+ connect \$1 $eq$libresoc.v:122941$4738_Y
+ connect \$3 $eq$libresoc.v:122942$4739_Y
+ connect \$5 $and$libresoc.v:122943$4740_Y
connect \ra \DIV_RA
end
-attribute \src "libresoc.v:124334.1-124371.10"
+attribute \src "libresoc.v:122959.1-122996.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai"
attribute \generator "nMigen"
module \dec_ai$169
- attribute \src "libresoc.v:124360.3-124369.6"
+ attribute \src "libresoc.v:122985.3-122994.6"
wire $0\immz_out[0:0]
- attribute \src "libresoc.v:124335.7-124335.20"
+ attribute \src "libresoc.v:122960.7-122960.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124360.3-124369.6"
+ attribute \src "libresoc.v:122985.3-122994.6"
wire $1\immz_out[0:0]
- attribute \src "libresoc.v:124359.17-124359.107"
- wire $and$libresoc.v:124359$4801_Y
- attribute \src "libresoc.v:124357.17-124357.111"
- wire $eq$libresoc.v:124357$4799_Y
- attribute \src "libresoc.v:124358.17-124358.108"
- wire $eq$libresoc.v:124358$4800_Y
+ attribute \src "libresoc.v:122984.17-122984.107"
+ wire $and$libresoc.v:122984$4745_Y
+ attribute \src "libresoc.v:122982.17-122982.111"
+ wire $eq$libresoc.v:122982$4743_Y
+ attribute \src "libresoc.v:122983.17-122983.108"
+ wire $eq$libresoc.v:122983$4744_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
wire width 5 input 2 \LDST_RA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162"
wire output 1 \immz_out
- attribute \src "libresoc.v:124335.7-124335.15"
+ attribute \src "libresoc.v:122960.7-122960.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
wire width 5 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 3 input 3 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $and $and$libresoc.v:124359$4801
+ cell $and $and$libresoc.v:122984$4745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:124359$4801_Y
+ connect \Y $and$libresoc.v:122984$4745_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124357$4799
+ cell $eq $eq$libresoc.v:122982$4743
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:124357$4799_Y
+ connect \Y $eq$libresoc.v:122982$4743_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- cell $eq $eq$libresoc.v:124358$4800
+ cell $eq $eq$libresoc.v:122983$4744
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $eq$libresoc.v:124358$4800_Y
+ connect \Y $eq$libresoc.v:122983$4744_Y
end
- attribute \src "libresoc.v:124335.7-124335.20"
- process $proc$libresoc.v:124335$4803
+ attribute \src "libresoc.v:122960.7-122960.20"
+ process $proc$libresoc.v:122960$4747
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124360.3-124369.6"
- process $proc$libresoc.v:124360$4802
+ attribute \src "libresoc.v:122985.3-122994.6"
+ process $proc$libresoc.v:122985$4746
assign { } { }
assign { } { }
assign $0\immz_out[0:0] $1\immz_out[0:0]
- attribute \src "libresoc.v:124361.5-124361.29"
+ attribute \src "libresoc.v:122986.5-122986.29"
switch \initial
- attribute \src "libresoc.v:124361.9-124361.17"
+ attribute \src "libresoc.v:122986.9-122986.17"
case 1'1
case
end
sync always
update \immz_out $0\immz_out[0:0]
end
- connect \$1 $eq$libresoc.v:124357$4799_Y
- connect \$3 $eq$libresoc.v:124358$4800_Y
- connect \$5 $and$libresoc.v:124359$4801_Y
+ connect \$1 $eq$libresoc.v:122982$4743_Y
+ connect \$3 $eq$libresoc.v:122983$4744_Y
+ connect \$5 $and$libresoc.v:122984$4745_Y
connect \ra \LDST_RA
end
-attribute \src "libresoc.v:124375.1-124572.10"
+attribute \src "libresoc.v:123000.1-123197.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b"
attribute \generator "nMigen"
module \dec_b
- attribute \src "libresoc.v:124536.3-124553.6"
+ attribute \src "libresoc.v:123161.3-123178.6"
wire width 3 $0\fast_b[2:0]
- attribute \src "libresoc.v:124554.3-124571.6"
+ attribute \src "libresoc.v:123179.3-123196.6"
wire $0\fast_b_ok[0:0]
- attribute \src "libresoc.v:124376.7-124376.20"
+ attribute \src "libresoc.v:123001.7-123001.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124506.3-124520.6"
+ attribute \src "libresoc.v:123131.3-123145.6"
wire width 7 $0\reg_b[6:0]
- attribute \src "libresoc.v:124521.3-124535.6"
+ attribute \src "libresoc.v:123146.3-123160.6"
wire $0\reg_b_ok[0:0]
- attribute \src "libresoc.v:124536.3-124553.6"
+ attribute \src "libresoc.v:123161.3-123178.6"
wire width 3 $1\fast_b[2:0]
- attribute \src "libresoc.v:124554.3-124571.6"
+ attribute \src "libresoc.v:123179.3-123196.6"
wire $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:124506.3-124520.6"
+ attribute \src "libresoc.v:123131.3-123145.6"
wire width 7 $1\reg_b[6:0]
- attribute \src "libresoc.v:124521.3-124535.6"
+ attribute \src "libresoc.v:123146.3-123160.6"
wire $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:124536.3-124553.6"
+ attribute \src "libresoc.v:123161.3-123178.6"
wire width 3 $2\fast_b[2:0]
- attribute \src "libresoc.v:124554.3-124571.6"
+ attribute \src "libresoc.v:123179.3-123196.6"
wire $2\fast_b_ok[0:0]
- attribute \src "libresoc.v:124500.17-124500.117"
- wire $eq$libresoc.v:124500$4804_Y
- attribute \src "libresoc.v:124504.17-124504.117"
- wire $eq$libresoc.v:124504$4810_Y
- attribute \src "libresoc.v:124502.17-124502.100"
- wire width 7 $extend$libresoc.v:124502$4806_Y
- attribute \src "libresoc.v:124503.17-124503.100"
- wire width 7 $extend$libresoc.v:124503$4808_Y
- attribute \src "libresoc.v:124501.18-124501.108"
- wire $not$libresoc.v:124501$4805_Y
- attribute \src "libresoc.v:124505.17-124505.107"
- wire $not$libresoc.v:124505$4811_Y
- attribute \src "libresoc.v:124502.17-124502.100"
- wire width 7 $pos$libresoc.v:124502$4807_Y
- attribute \src "libresoc.v:124503.17-124503.100"
- wire width 7 $pos$libresoc.v:124503$4809_Y
+ attribute \src "libresoc.v:123125.17-123125.117"
+ wire $eq$libresoc.v:123125$4748_Y
+ attribute \src "libresoc.v:123129.17-123129.117"
+ wire $eq$libresoc.v:123129$4754_Y
+ attribute \src "libresoc.v:123127.17-123127.100"
+ wire width 7 $extend$libresoc.v:123127$4750_Y
+ attribute \src "libresoc.v:123128.17-123128.100"
+ wire width 7 $extend$libresoc.v:123128$4752_Y
+ attribute \src "libresoc.v:123126.18-123126.108"
+ wire $not$libresoc.v:123126$4749_Y
+ attribute \src "libresoc.v:123130.17-123130.107"
+ wire $not$libresoc.v:123130$4755_Y
+ attribute \src "libresoc.v:123127.17-123127.100"
+ wire width 7 $pos$libresoc.v:123127$4751_Y
+ attribute \src "libresoc.v:123128.17-123128.100"
+ wire width 7 $pos$libresoc.v:123128$4753_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 7 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216"
wire width 3 output 4 \fast_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \fast_b_ok
- attribute \src "libresoc.v:124376.7-124376.15"
+ attribute \src "libresoc.v:123001.7-123001.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
wire width 4 input 1 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
- cell $eq $eq$libresoc.v:124500$4804
+ cell $eq $eq$libresoc.v:123125$4748
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:124500$4804_Y
+ connect \Y $eq$libresoc.v:123125$4748_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
- cell $eq $eq$libresoc.v:124504$4810
+ cell $eq $eq$libresoc.v:123129$4754
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:124504$4810_Y
+ connect \Y $eq$libresoc.v:123129$4754_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124502$4806
+ cell $pos $extend$libresoc.v:123127$4750
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \RB
- connect \Y $extend$libresoc.v:124502$4806_Y
+ connect \Y $extend$libresoc.v:123127$4750_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124503$4808
+ cell $pos $extend$libresoc.v:123128$4752
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \RS
- connect \Y $extend$libresoc.v:124503$4808_Y
+ connect \Y $extend$libresoc.v:123128$4752_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216"
- cell $not $not$libresoc.v:124501$4805
+ cell $not $not$libresoc.v:123126$4749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:124501$4805_Y
+ connect \Y $not$libresoc.v:123126$4749_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216"
- cell $not $not$libresoc.v:124505$4811
+ cell $not $not$libresoc.v:123130$4755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:124505$4811_Y
+ connect \Y $not$libresoc.v:123130$4755_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124502$4807
+ cell $pos $pos$libresoc.v:123127$4751
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:124502$4806_Y
- connect \Y $pos$libresoc.v:124502$4807_Y
+ connect \A $extend$libresoc.v:123127$4750_Y
+ connect \Y $pos$libresoc.v:123127$4751_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124503$4809
+ cell $pos $pos$libresoc.v:123128$4753
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:124503$4808_Y
- connect \Y $pos$libresoc.v:124503$4809_Y
+ connect \A $extend$libresoc.v:123128$4752_Y
+ connect \Y $pos$libresoc.v:123128$4753_Y
end
- attribute \src "libresoc.v:124376.7-124376.20"
- process $proc$libresoc.v:124376$4816
+ attribute \src "libresoc.v:123001.7-123001.20"
+ process $proc$libresoc.v:123001$4760
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124506.3-124520.6"
- process $proc$libresoc.v:124506$4812
+ attribute \src "libresoc.v:123131.3-123145.6"
+ process $proc$libresoc.v:123131$4756
assign { } { }
assign { } { }
assign $0\reg_b[6:0] $1\reg_b[6:0]
- attribute \src "libresoc.v:124507.5-124507.29"
+ attribute \src "libresoc.v:123132.5-123132.29"
switch \initial
- attribute \src "libresoc.v:124507.9-124507.17"
+ attribute \src "libresoc.v:123132.9-123132.17"
case 1'1
case
end
sync always
update \reg_b $0\reg_b[6:0]
end
- attribute \src "libresoc.v:124521.3-124535.6"
- process $proc$libresoc.v:124521$4813
+ attribute \src "libresoc.v:123146.3-123160.6"
+ process $proc$libresoc.v:123146$4757
assign { } { }
assign { } { }
assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:124522.5-124522.29"
+ attribute \src "libresoc.v:123147.5-123147.29"
switch \initial
- attribute \src "libresoc.v:124522.9-124522.17"
+ attribute \src "libresoc.v:123147.9-123147.17"
case 1'1
case
end
sync always
update \reg_b_ok $0\reg_b_ok[0:0]
end
- attribute \src "libresoc.v:124536.3-124553.6"
- process $proc$libresoc.v:124536$4814
+ attribute \src "libresoc.v:123161.3-123178.6"
+ process $proc$libresoc.v:123161$4758
assign { } { }
assign { } { }
assign $0\fast_b[2:0] $1\fast_b[2:0]
- attribute \src "libresoc.v:124537.5-124537.29"
+ attribute \src "libresoc.v:123162.5-123162.29"
switch \initial
- attribute \src "libresoc.v:124537.9-124537.17"
+ attribute \src "libresoc.v:123162.9-123162.17"
case 1'1
case
end
sync always
update \fast_b $0\fast_b[2:0]
end
- attribute \src "libresoc.v:124554.3-124571.6"
- process $proc$libresoc.v:124554$4815
+ attribute \src "libresoc.v:123179.3-123196.6"
+ process $proc$libresoc.v:123179$4759
assign { } { }
assign { } { }
assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:124555.5-124555.29"
+ attribute \src "libresoc.v:123180.5-123180.29"
switch \initial
- attribute \src "libresoc.v:124555.9-124555.17"
+ attribute \src "libresoc.v:123180.9-123180.17"
case 1'1
case
end
sync always
update \fast_b_ok $0\fast_b_ok[0:0]
end
- connect \$9 $eq$libresoc.v:124500$4804_Y
- connect \$11 $not$libresoc.v:124501$4805_Y
- connect \$1 $pos$libresoc.v:124502$4807_Y
- connect \$3 $pos$libresoc.v:124503$4809_Y
- connect \$5 $eq$libresoc.v:124504$4810_Y
- connect \$7 $not$libresoc.v:124505$4811_Y
+ connect \$9 $eq$libresoc.v:123125$4748_Y
+ connect \$11 $not$libresoc.v:123126$4749_Y
+ connect \$1 $pos$libresoc.v:123127$4751_Y
+ connect \$3 $pos$libresoc.v:123128$4753_Y
+ connect \$5 $eq$libresoc.v:123129$4754_Y
+ connect \$7 $not$libresoc.v:123130$4755_Y
end
-attribute \src "libresoc.v:124576.1-124829.10"
+attribute \src "libresoc.v:123201.1-123454.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi"
attribute \generator "nMigen"
module \dec_bi
- attribute \src "libresoc.v:124803.3-124813.6"
+ attribute \src "libresoc.v:123428.3-123438.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:124814.3-124824.6"
+ attribute \src "libresoc.v:123439.3-123449.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:124665.3-124711.6"
+ attribute \src "libresoc.v:123290.3-123336.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:124712.3-124758.6"
+ attribute \src "libresoc.v:123337.3-123383.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:124577.7-124577.20"
+ attribute \src "libresoc.v:123202.7-123202.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:124792.3-124802.6"
+ attribute \src "libresoc.v:123417.3-123427.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:124759.3-124769.6"
+ attribute \src "libresoc.v:123384.3-123394.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:124770.3-124780.6"
+ attribute \src "libresoc.v:123395.3-123405.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:124781.3-124791.6"
+ attribute \src "libresoc.v:123406.3-123416.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:124803.3-124813.6"
+ attribute \src "libresoc.v:123428.3-123438.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:124814.3-124824.6"
+ attribute \src "libresoc.v:123439.3-123449.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:124665.3-124711.6"
+ attribute \src "libresoc.v:123290.3-123336.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:124712.3-124758.6"
+ attribute \src "libresoc.v:123337.3-123383.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:124792.3-124802.6"
+ attribute \src "libresoc.v:123417.3-123427.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:124759.3-124769.6"
+ attribute \src "libresoc.v:123384.3-123394.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:124770.3-124780.6"
+ attribute \src "libresoc.v:123395.3-123405.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:124781.3-124791.6"
+ attribute \src "libresoc.v:123406.3-123416.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:124655.17-124655.104"
- wire width 64 $extend$libresoc.v:124655$4817_Y
- attribute \src "libresoc.v:124656.18-124656.107"
- wire width 64 $extend$libresoc.v:124656$4819_Y
- attribute \src "libresoc.v:124659.17-124659.104"
- wire width 64 $extend$libresoc.v:124659$4823_Y
- attribute \src "libresoc.v:124663.17-124663.102"
- wire width 64 $extend$libresoc.v:124663$4828_Y
- attribute \src "libresoc.v:124655.17-124655.104"
- wire width 64 $pos$libresoc.v:124655$4818_Y
- attribute \src "libresoc.v:124656.18-124656.107"
- wire width 64 $pos$libresoc.v:124656$4820_Y
- attribute \src "libresoc.v:124659.17-124659.104"
- wire width 64 $pos$libresoc.v:124659$4824_Y
- attribute \src "libresoc.v:124663.17-124663.102"
- wire width 64 $pos$libresoc.v:124663$4829_Y
- attribute \src "libresoc.v:124657.18-124657.114"
- wire width 47 $sshl$libresoc.v:124657$4821_Y
- attribute \src "libresoc.v:124658.18-124658.113"
- wire width 27 $sshl$libresoc.v:124658$4822_Y
- attribute \src "libresoc.v:124660.18-124660.113"
- wire width 17 $sshl$libresoc.v:124660$4825_Y
- attribute \src "libresoc.v:124661.18-124661.113"
- wire width 17 $sshl$libresoc.v:124661$4826_Y
- attribute \src "libresoc.v:124662.17-124662.109"
- wire width 47 $sshl$libresoc.v:124662$4827_Y
+ attribute \src "libresoc.v:123280.17-123280.104"
+ wire width 64 $extend$libresoc.v:123280$4761_Y
+ attribute \src "libresoc.v:123281.18-123281.107"
+ wire width 64 $extend$libresoc.v:123281$4763_Y
+ attribute \src "libresoc.v:123284.17-123284.104"
+ wire width 64 $extend$libresoc.v:123284$4767_Y
+ attribute \src "libresoc.v:123288.17-123288.102"
+ wire width 64 $extend$libresoc.v:123288$4772_Y
+ attribute \src "libresoc.v:123280.17-123280.104"
+ wire width 64 $pos$libresoc.v:123280$4762_Y
+ attribute \src "libresoc.v:123281.18-123281.107"
+ wire width 64 $pos$libresoc.v:123281$4764_Y
+ attribute \src "libresoc.v:123284.17-123284.104"
+ wire width 64 $pos$libresoc.v:123284$4768_Y
+ attribute \src "libresoc.v:123288.17-123288.102"
+ wire width 64 $pos$libresoc.v:123288$4773_Y
+ attribute \src "libresoc.v:123282.18-123282.114"
+ wire width 47 $sshl$libresoc.v:123282$4765_Y
+ attribute \src "libresoc.v:123283.18-123283.113"
+ wire width 27 $sshl$libresoc.v:123283$4766_Y
+ attribute \src "libresoc.v:123285.18-123285.113"
+ wire width 17 $sshl$libresoc.v:123285$4769_Y
+ attribute \src "libresoc.v:123286.18-123286.113"
+ wire width 17 $sshl$libresoc.v:123286$4770_Y
+ attribute \src "libresoc.v:123287.17-123287.109"
+ wire width 47 $sshl$libresoc.v:123287$4771_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:124577.7-124577.15"
+ attribute \src "libresoc.v:123202.7-123202.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124655$4817
+ cell $pos $extend$libresoc.v:123280$4761
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \ALU_sh
- connect \Y $extend$libresoc.v:124655$4817_Y
+ connect \Y $extend$libresoc.v:123280$4761_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124656$4819
+ cell $pos $extend$libresoc.v:123281$4763
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \ALU_SH32
- connect \Y $extend$libresoc.v:124656$4819_Y
+ connect \Y $extend$libresoc.v:123281$4763_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124659$4823
+ cell $pos $extend$libresoc.v:123284$4767
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \ALU_UI
- connect \Y $extend$libresoc.v:124659$4823_Y
+ connect \Y $extend$libresoc.v:123284$4767_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:124663$4828
+ cell $pos $extend$libresoc.v:123288$4772
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:124663$4828_Y
+ connect \Y $extend$libresoc.v:123288$4772_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124655$4818
+ cell $pos $pos$libresoc.v:123280$4762
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124655$4817_Y
- connect \Y $pos$libresoc.v:124655$4818_Y
+ connect \A $extend$libresoc.v:123280$4761_Y
+ connect \Y $pos$libresoc.v:123280$4762_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124656$4820
+ cell $pos $pos$libresoc.v:123281$4764
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124656$4819_Y
- connect \Y $pos$libresoc.v:124656$4820_Y
+ connect \A $extend$libresoc.v:123281$4763_Y
+ connect \Y $pos$libresoc.v:123281$4764_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124659$4824
+ cell $pos $pos$libresoc.v:123284$4768
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124659$4823_Y
- connect \Y $pos$libresoc.v:124659$4824_Y
+ connect \A $extend$libresoc.v:123284$4767_Y
+ connect \Y $pos$libresoc.v:123284$4768_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:124663$4829
+ cell $pos $pos$libresoc.v:123288$4773
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124663$4828_Y
- connect \Y $pos$libresoc.v:124663$4829_Y
+ connect \A $extend$libresoc.v:123288$4772_Y
+ connect \Y $pos$libresoc.v:123288$4773_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:124657$4821
+ cell $sshl $sshl$libresoc.v:123282$4765
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ALU_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:124657$4821_Y
+ connect \Y $sshl$libresoc.v:123282$4765_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:124658$4822
+ cell $sshl $sshl$libresoc.v:123283$4766
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \ALU_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:124658$4822_Y
+ connect \Y $sshl$libresoc.v:123283$4766_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:124660$4825
+ cell $sshl $sshl$libresoc.v:123285$4769
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \ALU_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:124660$4825_Y
+ connect \Y $sshl$libresoc.v:123285$4769_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:124661$4826
+ cell $sshl $sshl$libresoc.v:123286$4770
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \ALU_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:124661$4826_Y
+ connect \Y $sshl$libresoc.v:123286$4770_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:124662$4827
+ cell $sshl $sshl$libresoc.v:123287$4771
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:124662$4827_Y
+ connect \Y $sshl$libresoc.v:123287$4771_Y
end
- attribute \src "libresoc.v:124577.7-124577.20"
- process $proc$libresoc.v:124577$4838
+ attribute \src "libresoc.v:123202.7-123202.20"
+ process $proc$libresoc.v:123202$4782
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124665.3-124711.6"
- process $proc$libresoc.v:124665$4830
+ attribute \src "libresoc.v:123290.3-123336.6"
+ process $proc$libresoc.v:123290$4774
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:124666.5-124666.29"
+ attribute \src "libresoc.v:123291.5-123291.29"
switch \initial
- attribute \src "libresoc.v:124666.9-124666.17"
+ attribute \src "libresoc.v:123291.9-123291.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:124712.3-124758.6"
- process $proc$libresoc.v:124712$4831
+ attribute \src "libresoc.v:123337.3-123383.6"
+ process $proc$libresoc.v:123337$4775
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:124713.5-124713.29"
+ attribute \src "libresoc.v:123338.5-123338.29"
switch \initial
- attribute \src "libresoc.v:124713.9-124713.17"
+ attribute \src "libresoc.v:123338.9-123338.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:124759.3-124769.6"
- process $proc$libresoc.v:124759$4832
+ attribute \src "libresoc.v:123384.3-123394.6"
+ process $proc$libresoc.v:123384$4776
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:124760.5-124760.29"
+ attribute \src "libresoc.v:123385.5-123385.29"
switch \initial
- attribute \src "libresoc.v:124760.9-124760.17"
+ attribute \src "libresoc.v:123385.9-123385.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:124770.3-124780.6"
- process $proc$libresoc.v:124770$4833
+ attribute \src "libresoc.v:123395.3-123405.6"
+ process $proc$libresoc.v:123395$4777
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:124771.5-124771.29"
+ attribute \src "libresoc.v:123396.5-123396.29"
switch \initial
- attribute \src "libresoc.v:124771.9-124771.17"
+ attribute \src "libresoc.v:123396.9-123396.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:124781.3-124791.6"
- process $proc$libresoc.v:124781$4834
+ attribute \src "libresoc.v:123406.3-123416.6"
+ process $proc$libresoc.v:123406$4778
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:124782.5-124782.29"
+ attribute \src "libresoc.v:123407.5-123407.29"
switch \initial
- attribute \src "libresoc.v:124782.9-124782.17"
+ attribute \src "libresoc.v:123407.9-123407.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:124792.3-124802.6"
- process $proc$libresoc.v:124792$4835
+ attribute \src "libresoc.v:123417.3-123427.6"
+ process $proc$libresoc.v:123417$4779
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:124793.5-124793.29"
+ attribute \src "libresoc.v:123418.5-123418.29"
switch \initial
- attribute \src "libresoc.v:124793.9-124793.17"
+ attribute \src "libresoc.v:123418.9-123418.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:124803.3-124813.6"
- process $proc$libresoc.v:124803$4836
+ attribute \src "libresoc.v:123428.3-123438.6"
+ process $proc$libresoc.v:123428$4780
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:124804.5-124804.29"
+ attribute \src "libresoc.v:123429.5-123429.29"
switch \initial
- attribute \src "libresoc.v:124804.9-124804.17"
+ attribute \src "libresoc.v:123429.9-123429.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:124814.3-124824.6"
- process $proc$libresoc.v:124814$4837
+ attribute \src "libresoc.v:123439.3-123449.6"
+ process $proc$libresoc.v:123439$4781
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:124815.5-124815.29"
+ attribute \src "libresoc.v:123440.5-123440.29"
switch \initial
- attribute \src "libresoc.v:124815.9-124815.17"
+ attribute \src "libresoc.v:123440.9-123440.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:124655$4818_Y
- connect \$11 $pos$libresoc.v:124656$4820_Y
- connect \$14 $sshl$libresoc.v:124657$4821_Y
- connect \$17 $sshl$libresoc.v:124658$4822_Y
- connect \$1 $pos$libresoc.v:124659$4824_Y
- connect \$20 $sshl$libresoc.v:124660$4825_Y
- connect \$23 $sshl$libresoc.v:124661$4826_Y
- connect \$4 $sshl$libresoc.v:124662$4827_Y
- connect \$3 $pos$libresoc.v:124663$4829_Y
+ connect \$9 $pos$libresoc.v:123280$4762_Y
+ connect \$11 $pos$libresoc.v:123281$4764_Y
+ connect \$14 $sshl$libresoc.v:123282$4765_Y
+ connect \$17 $sshl$libresoc.v:123283$4766_Y
+ connect \$1 $pos$libresoc.v:123284$4768_Y
+ connect \$20 $sshl$libresoc.v:123285$4769_Y
+ connect \$23 $sshl$libresoc.v:123286$4770_Y
+ connect \$4 $sshl$libresoc.v:123287$4771_Y
+ connect \$3 $pos$libresoc.v:123288$4773_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:124833.1-125086.10"
+attribute \src "libresoc.v:123458.1-123711.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi"
attribute \generator "nMigen"
module \dec_bi$144
- attribute \src "libresoc.v:125060.3-125070.6"
+ attribute \src "libresoc.v:123685.3-123695.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:125071.3-125081.6"
+ attribute \src "libresoc.v:123696.3-123706.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:124922.3-124968.6"
+ attribute \src "libresoc.v:123547.3-123593.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:124969.3-125015.6"
+ attribute \src "libresoc.v:123594.3-123640.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:124834.7-124834.20"
+ attribute \src "libresoc.v:123459.7-123459.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125049.3-125059.6"
+ attribute \src "libresoc.v:123674.3-123684.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:125016.3-125026.6"
+ attribute \src "libresoc.v:123641.3-123651.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:125027.3-125037.6"
+ attribute \src "libresoc.v:123652.3-123662.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:125038.3-125048.6"
+ attribute \src "libresoc.v:123663.3-123673.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:125060.3-125070.6"
+ attribute \src "libresoc.v:123685.3-123695.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:125071.3-125081.6"
+ attribute \src "libresoc.v:123696.3-123706.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:124922.3-124968.6"
+ attribute \src "libresoc.v:123547.3-123593.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:124969.3-125015.6"
+ attribute \src "libresoc.v:123594.3-123640.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125049.3-125059.6"
+ attribute \src "libresoc.v:123674.3-123684.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:125016.3-125026.6"
+ attribute \src "libresoc.v:123641.3-123651.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:125027.3-125037.6"
+ attribute \src "libresoc.v:123652.3-123662.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:125038.3-125048.6"
+ attribute \src "libresoc.v:123663.3-123673.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:124912.17-124912.107"
- wire width 64 $extend$libresoc.v:124912$4839_Y
- attribute \src "libresoc.v:124913.18-124913.110"
- wire width 64 $extend$libresoc.v:124913$4841_Y
- attribute \src "libresoc.v:124916.17-124916.107"
- wire width 64 $extend$libresoc.v:124916$4845_Y
- attribute \src "libresoc.v:124920.17-124920.102"
- wire width 64 $extend$libresoc.v:124920$4850_Y
- attribute \src "libresoc.v:124912.17-124912.107"
- wire width 64 $pos$libresoc.v:124912$4840_Y
- attribute \src "libresoc.v:124913.18-124913.110"
- wire width 64 $pos$libresoc.v:124913$4842_Y
- attribute \src "libresoc.v:124916.17-124916.107"
- wire width 64 $pos$libresoc.v:124916$4846_Y
- attribute \src "libresoc.v:124920.17-124920.102"
- wire width 64 $pos$libresoc.v:124920$4851_Y
- attribute \src "libresoc.v:124914.18-124914.117"
- wire width 47 $sshl$libresoc.v:124914$4843_Y
- attribute \src "libresoc.v:124915.18-124915.116"
- wire width 27 $sshl$libresoc.v:124915$4844_Y
- attribute \src "libresoc.v:124917.18-124917.116"
- wire width 17 $sshl$libresoc.v:124917$4847_Y
- attribute \src "libresoc.v:124918.18-124918.116"
- wire width 17 $sshl$libresoc.v:124918$4848_Y
- attribute \src "libresoc.v:124919.17-124919.109"
- wire width 47 $sshl$libresoc.v:124919$4849_Y
+ attribute \src "libresoc.v:123537.17-123537.107"
+ wire width 64 $extend$libresoc.v:123537$4783_Y
+ attribute \src "libresoc.v:123538.18-123538.110"
+ wire width 64 $extend$libresoc.v:123538$4785_Y
+ attribute \src "libresoc.v:123541.17-123541.107"
+ wire width 64 $extend$libresoc.v:123541$4789_Y
+ attribute \src "libresoc.v:123545.17-123545.102"
+ wire width 64 $extend$libresoc.v:123545$4794_Y
+ attribute \src "libresoc.v:123537.17-123537.107"
+ wire width 64 $pos$libresoc.v:123537$4784_Y
+ attribute \src "libresoc.v:123538.18-123538.110"
+ wire width 64 $pos$libresoc.v:123538$4786_Y
+ attribute \src "libresoc.v:123541.17-123541.107"
+ wire width 64 $pos$libresoc.v:123541$4790_Y
+ attribute \src "libresoc.v:123545.17-123545.102"
+ wire width 64 $pos$libresoc.v:123545$4795_Y
+ attribute \src "libresoc.v:123539.18-123539.117"
+ wire width 47 $sshl$libresoc.v:123539$4787_Y
+ attribute \src "libresoc.v:123540.18-123540.116"
+ wire width 27 $sshl$libresoc.v:123540$4788_Y
+ attribute \src "libresoc.v:123542.18-123542.116"
+ wire width 17 $sshl$libresoc.v:123542$4791_Y
+ attribute \src "libresoc.v:123543.18-123543.116"
+ wire width 17 $sshl$libresoc.v:123543$4792_Y
+ attribute \src "libresoc.v:123544.17-123544.109"
+ wire width 47 $sshl$libresoc.v:123544$4793_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:124834.7-124834.15"
+ attribute \src "libresoc.v:123459.7-123459.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124912$4839
+ cell $pos $extend$libresoc.v:123537$4783
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \BRANCH_sh
- connect \Y $extend$libresoc.v:124912$4839_Y
+ connect \Y $extend$libresoc.v:123537$4783_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124913$4841
+ cell $pos $extend$libresoc.v:123538$4785
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \BRANCH_SH32
- connect \Y $extend$libresoc.v:124913$4841_Y
+ connect \Y $extend$libresoc.v:123538$4785_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:124916$4845
+ cell $pos $extend$libresoc.v:123541$4789
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \BRANCH_UI
- connect \Y $extend$libresoc.v:124916$4845_Y
+ connect \Y $extend$libresoc.v:123541$4789_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:124920$4850
+ cell $pos $extend$libresoc.v:123545$4794
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:124920$4850_Y
+ connect \Y $extend$libresoc.v:123545$4794_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124912$4840
+ cell $pos $pos$libresoc.v:123537$4784
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124912$4839_Y
- connect \Y $pos$libresoc.v:124912$4840_Y
+ connect \A $extend$libresoc.v:123537$4783_Y
+ connect \Y $pos$libresoc.v:123537$4784_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124913$4842
+ cell $pos $pos$libresoc.v:123538$4786
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124913$4841_Y
- connect \Y $pos$libresoc.v:124913$4842_Y
+ connect \A $extend$libresoc.v:123538$4785_Y
+ connect \Y $pos$libresoc.v:123538$4786_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:124916$4846
+ cell $pos $pos$libresoc.v:123541$4790
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124916$4845_Y
- connect \Y $pos$libresoc.v:124916$4846_Y
+ connect \A $extend$libresoc.v:123541$4789_Y
+ connect \Y $pos$libresoc.v:123541$4790_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:124920$4851
+ cell $pos $pos$libresoc.v:123545$4795
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:124920$4850_Y
- connect \Y $pos$libresoc.v:124920$4851_Y
+ connect \A $extend$libresoc.v:123545$4794_Y
+ connect \Y $pos$libresoc.v:123545$4795_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:124914$4843
+ cell $sshl $sshl$libresoc.v:123539$4787
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \BRANCH_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:124914$4843_Y
+ connect \Y $sshl$libresoc.v:123539$4787_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:124915$4844
+ cell $sshl $sshl$libresoc.v:123540$4788
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \BRANCH_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:124915$4844_Y
+ connect \Y $sshl$libresoc.v:123540$4788_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:124917$4847
+ cell $sshl $sshl$libresoc.v:123542$4791
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \BRANCH_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:124917$4847_Y
+ connect \Y $sshl$libresoc.v:123542$4791_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:124918$4848
+ cell $sshl $sshl$libresoc.v:123543$4792
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \BRANCH_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:124918$4848_Y
+ connect \Y $sshl$libresoc.v:123543$4792_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:124919$4849
+ cell $sshl $sshl$libresoc.v:123544$4793
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:124919$4849_Y
+ connect \Y $sshl$libresoc.v:123544$4793_Y
end
- attribute \src "libresoc.v:124834.7-124834.20"
- process $proc$libresoc.v:124834$4860
+ attribute \src "libresoc.v:123459.7-123459.20"
+ process $proc$libresoc.v:123459$4804
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:124922.3-124968.6"
- process $proc$libresoc.v:124922$4852
+ attribute \src "libresoc.v:123547.3-123593.6"
+ process $proc$libresoc.v:123547$4796
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:124923.5-124923.29"
+ attribute \src "libresoc.v:123548.5-123548.29"
switch \initial
- attribute \src "libresoc.v:124923.9-124923.17"
+ attribute \src "libresoc.v:123548.9-123548.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:124969.3-125015.6"
- process $proc$libresoc.v:124969$4853
+ attribute \src "libresoc.v:123594.3-123640.6"
+ process $proc$libresoc.v:123594$4797
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:124970.5-124970.29"
+ attribute \src "libresoc.v:123595.5-123595.29"
switch \initial
- attribute \src "libresoc.v:124970.9-124970.17"
+ attribute \src "libresoc.v:123595.9-123595.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:125016.3-125026.6"
- process $proc$libresoc.v:125016$4854
+ attribute \src "libresoc.v:123641.3-123651.6"
+ process $proc$libresoc.v:123641$4798
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:125017.5-125017.29"
+ attribute \src "libresoc.v:123642.5-123642.29"
switch \initial
- attribute \src "libresoc.v:125017.9-125017.17"
+ attribute \src "libresoc.v:123642.9-123642.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:125027.3-125037.6"
- process $proc$libresoc.v:125027$4855
+ attribute \src "libresoc.v:123652.3-123662.6"
+ process $proc$libresoc.v:123652$4799
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:125028.5-125028.29"
+ attribute \src "libresoc.v:123653.5-123653.29"
switch \initial
- attribute \src "libresoc.v:125028.9-125028.17"
+ attribute \src "libresoc.v:123653.9-123653.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:125038.3-125048.6"
- process $proc$libresoc.v:125038$4856
+ attribute \src "libresoc.v:123663.3-123673.6"
+ process $proc$libresoc.v:123663$4800
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:125039.5-125039.29"
+ attribute \src "libresoc.v:123664.5-123664.29"
switch \initial
- attribute \src "libresoc.v:125039.9-125039.17"
+ attribute \src "libresoc.v:123664.9-123664.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:125049.3-125059.6"
- process $proc$libresoc.v:125049$4857
+ attribute \src "libresoc.v:123674.3-123684.6"
+ process $proc$libresoc.v:123674$4801
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:125050.5-125050.29"
+ attribute \src "libresoc.v:123675.5-123675.29"
switch \initial
- attribute \src "libresoc.v:125050.9-125050.17"
+ attribute \src "libresoc.v:123675.9-123675.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:125060.3-125070.6"
- process $proc$libresoc.v:125060$4858
+ attribute \src "libresoc.v:123685.3-123695.6"
+ process $proc$libresoc.v:123685$4802
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:125061.5-125061.29"
+ attribute \src "libresoc.v:123686.5-123686.29"
switch \initial
- attribute \src "libresoc.v:125061.9-125061.17"
+ attribute \src "libresoc.v:123686.9-123686.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:125071.3-125081.6"
- process $proc$libresoc.v:125071$4859
+ attribute \src "libresoc.v:123696.3-123706.6"
+ process $proc$libresoc.v:123696$4803
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:125072.5-125072.29"
+ attribute \src "libresoc.v:123697.5-123697.29"
switch \initial
- attribute \src "libresoc.v:125072.9-125072.17"
+ attribute \src "libresoc.v:123697.9-123697.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:124912$4840_Y
- connect \$11 $pos$libresoc.v:124913$4842_Y
- connect \$14 $sshl$libresoc.v:124914$4843_Y
- connect \$17 $sshl$libresoc.v:124915$4844_Y
- connect \$1 $pos$libresoc.v:124916$4846_Y
- connect \$20 $sshl$libresoc.v:124917$4847_Y
- connect \$23 $sshl$libresoc.v:124918$4848_Y
- connect \$4 $sshl$libresoc.v:124919$4849_Y
- connect \$3 $pos$libresoc.v:124920$4851_Y
+ connect \$9 $pos$libresoc.v:123537$4784_Y
+ connect \$11 $pos$libresoc.v:123538$4786_Y
+ connect \$14 $sshl$libresoc.v:123539$4787_Y
+ connect \$17 $sshl$libresoc.v:123540$4788_Y
+ connect \$1 $pos$libresoc.v:123541$4790_Y
+ connect \$20 $sshl$libresoc.v:123542$4791_Y
+ connect \$23 $sshl$libresoc.v:123543$4792_Y
+ connect \$4 $sshl$libresoc.v:123544$4793_Y
+ connect \$3 $pos$libresoc.v:123545$4795_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:125090.1-125343.10"
+attribute \src "libresoc.v:123715.1-123968.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi"
attribute \generator "nMigen"
module \dec_bi$149
- attribute \src "libresoc.v:125317.3-125327.6"
+ attribute \src "libresoc.v:123942.3-123952.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:125328.3-125338.6"
+ attribute \src "libresoc.v:123953.3-123963.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:125179.3-125225.6"
+ attribute \src "libresoc.v:123804.3-123850.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:125226.3-125272.6"
+ attribute \src "libresoc.v:123851.3-123897.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:125091.7-125091.20"
+ attribute \src "libresoc.v:123716.7-123716.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125306.3-125316.6"
+ attribute \src "libresoc.v:123931.3-123941.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:125273.3-125283.6"
+ attribute \src "libresoc.v:123898.3-123908.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:125284.3-125294.6"
+ attribute \src "libresoc.v:123909.3-123919.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:125295.3-125305.6"
+ attribute \src "libresoc.v:123920.3-123930.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:125317.3-125327.6"
+ attribute \src "libresoc.v:123942.3-123952.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:125328.3-125338.6"
+ attribute \src "libresoc.v:123953.3-123963.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:125179.3-125225.6"
+ attribute \src "libresoc.v:123804.3-123850.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:125226.3-125272.6"
+ attribute \src "libresoc.v:123851.3-123897.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125306.3-125316.6"
+ attribute \src "libresoc.v:123931.3-123941.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:125273.3-125283.6"
+ attribute \src "libresoc.v:123898.3-123908.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:125284.3-125294.6"
+ attribute \src "libresoc.v:123909.3-123919.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:125295.3-125305.6"
+ attribute \src "libresoc.v:123920.3-123930.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:125169.17-125169.108"
- wire width 64 $extend$libresoc.v:125169$4861_Y
- attribute \src "libresoc.v:125170.18-125170.111"
- wire width 64 $extend$libresoc.v:125170$4863_Y
- attribute \src "libresoc.v:125173.17-125173.108"
- wire width 64 $extend$libresoc.v:125173$4867_Y
- attribute \src "libresoc.v:125177.17-125177.102"
- wire width 64 $extend$libresoc.v:125177$4872_Y
- attribute \src "libresoc.v:125169.17-125169.108"
- wire width 64 $pos$libresoc.v:125169$4862_Y
- attribute \src "libresoc.v:125170.18-125170.111"
- wire width 64 $pos$libresoc.v:125170$4864_Y
- attribute \src "libresoc.v:125173.17-125173.108"
- wire width 64 $pos$libresoc.v:125173$4868_Y
- attribute \src "libresoc.v:125177.17-125177.102"
- wire width 64 $pos$libresoc.v:125177$4873_Y
- attribute \src "libresoc.v:125171.18-125171.118"
- wire width 47 $sshl$libresoc.v:125171$4865_Y
- attribute \src "libresoc.v:125172.18-125172.117"
- wire width 27 $sshl$libresoc.v:125172$4866_Y
- attribute \src "libresoc.v:125174.18-125174.117"
- wire width 17 $sshl$libresoc.v:125174$4869_Y
- attribute \src "libresoc.v:125175.18-125175.117"
- wire width 17 $sshl$libresoc.v:125175$4870_Y
- attribute \src "libresoc.v:125176.17-125176.109"
- wire width 47 $sshl$libresoc.v:125176$4871_Y
+ attribute \src "libresoc.v:123794.17-123794.108"
+ wire width 64 $extend$libresoc.v:123794$4805_Y
+ attribute \src "libresoc.v:123795.18-123795.111"
+ wire width 64 $extend$libresoc.v:123795$4807_Y
+ attribute \src "libresoc.v:123798.17-123798.108"
+ wire width 64 $extend$libresoc.v:123798$4811_Y
+ attribute \src "libresoc.v:123802.17-123802.102"
+ wire width 64 $extend$libresoc.v:123802$4816_Y
+ attribute \src "libresoc.v:123794.17-123794.108"
+ wire width 64 $pos$libresoc.v:123794$4806_Y
+ attribute \src "libresoc.v:123795.18-123795.111"
+ wire width 64 $pos$libresoc.v:123795$4808_Y
+ attribute \src "libresoc.v:123798.17-123798.108"
+ wire width 64 $pos$libresoc.v:123798$4812_Y
+ attribute \src "libresoc.v:123802.17-123802.102"
+ wire width 64 $pos$libresoc.v:123802$4817_Y
+ attribute \src "libresoc.v:123796.18-123796.118"
+ wire width 47 $sshl$libresoc.v:123796$4809_Y
+ attribute \src "libresoc.v:123797.18-123797.117"
+ wire width 27 $sshl$libresoc.v:123797$4810_Y
+ attribute \src "libresoc.v:123799.18-123799.117"
+ wire width 17 $sshl$libresoc.v:123799$4813_Y
+ attribute \src "libresoc.v:123800.18-123800.117"
+ wire width 17 $sshl$libresoc.v:123800$4814_Y
+ attribute \src "libresoc.v:123801.17-123801.109"
+ wire width 47 $sshl$libresoc.v:123801$4815_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:125091.7-125091.15"
+ attribute \src "libresoc.v:123716.7-123716.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125169$4861
+ cell $pos $extend$libresoc.v:123794$4805
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \LOGICAL_sh
- connect \Y $extend$libresoc.v:125169$4861_Y
+ connect \Y $extend$libresoc.v:123794$4805_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125170$4863
+ cell $pos $extend$libresoc.v:123795$4807
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \LOGICAL_SH32
- connect \Y $extend$libresoc.v:125170$4863_Y
+ connect \Y $extend$libresoc.v:123795$4807_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125173$4867
+ cell $pos $extend$libresoc.v:123798$4811
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \LOGICAL_UI
- connect \Y $extend$libresoc.v:125173$4867_Y
+ connect \Y $extend$libresoc.v:123798$4811_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:125177$4872
+ cell $pos $extend$libresoc.v:123802$4816
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:125177$4872_Y
+ connect \Y $extend$libresoc.v:123802$4816_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125169$4862
+ cell $pos $pos$libresoc.v:123794$4806
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125169$4861_Y
- connect \Y $pos$libresoc.v:125169$4862_Y
+ connect \A $extend$libresoc.v:123794$4805_Y
+ connect \Y $pos$libresoc.v:123794$4806_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125170$4864
+ cell $pos $pos$libresoc.v:123795$4808
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125170$4863_Y
- connect \Y $pos$libresoc.v:125170$4864_Y
+ connect \A $extend$libresoc.v:123795$4807_Y
+ connect \Y $pos$libresoc.v:123795$4808_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125173$4868
+ cell $pos $pos$libresoc.v:123798$4812
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125173$4867_Y
- connect \Y $pos$libresoc.v:125173$4868_Y
+ connect \A $extend$libresoc.v:123798$4811_Y
+ connect \Y $pos$libresoc.v:123798$4812_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:125177$4873
+ cell $pos $pos$libresoc.v:123802$4817
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125177$4872_Y
- connect \Y $pos$libresoc.v:125177$4873_Y
+ connect \A $extend$libresoc.v:123802$4816_Y
+ connect \Y $pos$libresoc.v:123802$4817_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:125171$4865
+ cell $sshl $sshl$libresoc.v:123796$4809
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \LOGICAL_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125171$4865_Y
+ connect \Y $sshl$libresoc.v:123796$4809_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:125172$4866
+ cell $sshl $sshl$libresoc.v:123797$4810
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \LOGICAL_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:125172$4866_Y
+ connect \Y $sshl$libresoc.v:123797$4810_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:125174$4869
+ cell $sshl $sshl$libresoc.v:123799$4813
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LOGICAL_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:125174$4869_Y
+ connect \Y $sshl$libresoc.v:123799$4813_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:125175$4870
+ cell $sshl $sshl$libresoc.v:123800$4814
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LOGICAL_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:125175$4870_Y
+ connect \Y $sshl$libresoc.v:123800$4814_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:125176$4871
+ cell $sshl $sshl$libresoc.v:123801$4815
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125176$4871_Y
+ connect \Y $sshl$libresoc.v:123801$4815_Y
end
- attribute \src "libresoc.v:125091.7-125091.20"
- process $proc$libresoc.v:125091$4882
+ attribute \src "libresoc.v:123716.7-123716.20"
+ process $proc$libresoc.v:123716$4826
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125179.3-125225.6"
- process $proc$libresoc.v:125179$4874
+ attribute \src "libresoc.v:123804.3-123850.6"
+ process $proc$libresoc.v:123804$4818
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:125180.5-125180.29"
+ attribute \src "libresoc.v:123805.5-123805.29"
switch \initial
- attribute \src "libresoc.v:125180.9-125180.17"
+ attribute \src "libresoc.v:123805.9-123805.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:125226.3-125272.6"
- process $proc$libresoc.v:125226$4875
+ attribute \src "libresoc.v:123851.3-123897.6"
+ process $proc$libresoc.v:123851$4819
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125227.5-125227.29"
+ attribute \src "libresoc.v:123852.5-123852.29"
switch \initial
- attribute \src "libresoc.v:125227.9-125227.17"
+ attribute \src "libresoc.v:123852.9-123852.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:125273.3-125283.6"
- process $proc$libresoc.v:125273$4876
+ attribute \src "libresoc.v:123898.3-123908.6"
+ process $proc$libresoc.v:123898$4820
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:125274.5-125274.29"
+ attribute \src "libresoc.v:123899.5-123899.29"
switch \initial
- attribute \src "libresoc.v:125274.9-125274.17"
+ attribute \src "libresoc.v:123899.9-123899.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:125284.3-125294.6"
- process $proc$libresoc.v:125284$4877
+ attribute \src "libresoc.v:123909.3-123919.6"
+ process $proc$libresoc.v:123909$4821
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:125285.5-125285.29"
+ attribute \src "libresoc.v:123910.5-123910.29"
switch \initial
- attribute \src "libresoc.v:125285.9-125285.17"
+ attribute \src "libresoc.v:123910.9-123910.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:125295.3-125305.6"
- process $proc$libresoc.v:125295$4878
+ attribute \src "libresoc.v:123920.3-123930.6"
+ process $proc$libresoc.v:123920$4822
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:125296.5-125296.29"
+ attribute \src "libresoc.v:123921.5-123921.29"
switch \initial
- attribute \src "libresoc.v:125296.9-125296.17"
+ attribute \src "libresoc.v:123921.9-123921.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:125306.3-125316.6"
- process $proc$libresoc.v:125306$4879
+ attribute \src "libresoc.v:123931.3-123941.6"
+ process $proc$libresoc.v:123931$4823
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:125307.5-125307.29"
+ attribute \src "libresoc.v:123932.5-123932.29"
switch \initial
- attribute \src "libresoc.v:125307.9-125307.17"
+ attribute \src "libresoc.v:123932.9-123932.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:125317.3-125327.6"
- process $proc$libresoc.v:125317$4880
+ attribute \src "libresoc.v:123942.3-123952.6"
+ process $proc$libresoc.v:123942$4824
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:125318.5-125318.29"
+ attribute \src "libresoc.v:123943.5-123943.29"
switch \initial
- attribute \src "libresoc.v:125318.9-125318.17"
+ attribute \src "libresoc.v:123943.9-123943.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:125328.3-125338.6"
- process $proc$libresoc.v:125328$4881
+ attribute \src "libresoc.v:123953.3-123963.6"
+ process $proc$libresoc.v:123953$4825
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:125329.5-125329.29"
+ attribute \src "libresoc.v:123954.5-123954.29"
switch \initial
- attribute \src "libresoc.v:125329.9-125329.17"
+ attribute \src "libresoc.v:123954.9-123954.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:125169$4862_Y
- connect \$11 $pos$libresoc.v:125170$4864_Y
- connect \$14 $sshl$libresoc.v:125171$4865_Y
- connect \$17 $sshl$libresoc.v:125172$4866_Y
- connect \$1 $pos$libresoc.v:125173$4868_Y
- connect \$20 $sshl$libresoc.v:125174$4869_Y
- connect \$23 $sshl$libresoc.v:125175$4870_Y
- connect \$4 $sshl$libresoc.v:125176$4871_Y
- connect \$3 $pos$libresoc.v:125177$4873_Y
+ connect \$9 $pos$libresoc.v:123794$4806_Y
+ connect \$11 $pos$libresoc.v:123795$4808_Y
+ connect \$14 $sshl$libresoc.v:123796$4809_Y
+ connect \$17 $sshl$libresoc.v:123797$4810_Y
+ connect \$1 $pos$libresoc.v:123798$4812_Y
+ connect \$20 $sshl$libresoc.v:123799$4813_Y
+ connect \$23 $sshl$libresoc.v:123800$4814_Y
+ connect \$4 $sshl$libresoc.v:123801$4815_Y
+ connect \$3 $pos$libresoc.v:123802$4817_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:125347.1-125600.10"
+attribute \src "libresoc.v:123972.1-124225.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi"
attribute \generator "nMigen"
module \dec_bi$157
- attribute \src "libresoc.v:125574.3-125584.6"
+ attribute \src "libresoc.v:124199.3-124209.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:125585.3-125595.6"
+ attribute \src "libresoc.v:124210.3-124220.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:125436.3-125482.6"
+ attribute \src "libresoc.v:124061.3-124107.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:125483.3-125529.6"
+ attribute \src "libresoc.v:124108.3-124154.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:125348.7-125348.20"
+ attribute \src "libresoc.v:123973.7-123973.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125563.3-125573.6"
+ attribute \src "libresoc.v:124188.3-124198.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:125530.3-125540.6"
+ attribute \src "libresoc.v:124155.3-124165.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:125541.3-125551.6"
+ attribute \src "libresoc.v:124166.3-124176.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:125552.3-125562.6"
+ attribute \src "libresoc.v:124177.3-124187.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:125574.3-125584.6"
+ attribute \src "libresoc.v:124199.3-124209.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:125585.3-125595.6"
+ attribute \src "libresoc.v:124210.3-124220.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:125436.3-125482.6"
+ attribute \src "libresoc.v:124061.3-124107.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:125483.3-125529.6"
+ attribute \src "libresoc.v:124108.3-124154.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125563.3-125573.6"
+ attribute \src "libresoc.v:124188.3-124198.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:125530.3-125540.6"
+ attribute \src "libresoc.v:124155.3-124165.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:125541.3-125551.6"
+ attribute \src "libresoc.v:124166.3-124176.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:125552.3-125562.6"
+ attribute \src "libresoc.v:124177.3-124187.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:125426.17-125426.104"
- wire width 64 $extend$libresoc.v:125426$4883_Y
- attribute \src "libresoc.v:125427.18-125427.107"
- wire width 64 $extend$libresoc.v:125427$4885_Y
- attribute \src "libresoc.v:125430.17-125430.104"
- wire width 64 $extend$libresoc.v:125430$4889_Y
- attribute \src "libresoc.v:125434.17-125434.102"
- wire width 64 $extend$libresoc.v:125434$4894_Y
- attribute \src "libresoc.v:125426.17-125426.104"
- wire width 64 $pos$libresoc.v:125426$4884_Y
- attribute \src "libresoc.v:125427.18-125427.107"
- wire width 64 $pos$libresoc.v:125427$4886_Y
- attribute \src "libresoc.v:125430.17-125430.104"
- wire width 64 $pos$libresoc.v:125430$4890_Y
- attribute \src "libresoc.v:125434.17-125434.102"
- wire width 64 $pos$libresoc.v:125434$4895_Y
- attribute \src "libresoc.v:125428.18-125428.114"
- wire width 47 $sshl$libresoc.v:125428$4887_Y
- attribute \src "libresoc.v:125429.18-125429.113"
- wire width 27 $sshl$libresoc.v:125429$4888_Y
- attribute \src "libresoc.v:125431.18-125431.113"
- wire width 17 $sshl$libresoc.v:125431$4891_Y
- attribute \src "libresoc.v:125432.18-125432.113"
- wire width 17 $sshl$libresoc.v:125432$4892_Y
- attribute \src "libresoc.v:125433.17-125433.109"
- wire width 47 $sshl$libresoc.v:125433$4893_Y
+ attribute \src "libresoc.v:124051.17-124051.104"
+ wire width 64 $extend$libresoc.v:124051$4827_Y
+ attribute \src "libresoc.v:124052.18-124052.107"
+ wire width 64 $extend$libresoc.v:124052$4829_Y
+ attribute \src "libresoc.v:124055.17-124055.104"
+ wire width 64 $extend$libresoc.v:124055$4833_Y
+ attribute \src "libresoc.v:124059.17-124059.102"
+ wire width 64 $extend$libresoc.v:124059$4838_Y
+ attribute \src "libresoc.v:124051.17-124051.104"
+ wire width 64 $pos$libresoc.v:124051$4828_Y
+ attribute \src "libresoc.v:124052.18-124052.107"
+ wire width 64 $pos$libresoc.v:124052$4830_Y
+ attribute \src "libresoc.v:124055.17-124055.104"
+ wire width 64 $pos$libresoc.v:124055$4834_Y
+ attribute \src "libresoc.v:124059.17-124059.102"
+ wire width 64 $pos$libresoc.v:124059$4839_Y
+ attribute \src "libresoc.v:124053.18-124053.114"
+ wire width 47 $sshl$libresoc.v:124053$4831_Y
+ attribute \src "libresoc.v:124054.18-124054.113"
+ wire width 27 $sshl$libresoc.v:124054$4832_Y
+ attribute \src "libresoc.v:124056.18-124056.113"
+ wire width 17 $sshl$libresoc.v:124056$4835_Y
+ attribute \src "libresoc.v:124057.18-124057.113"
+ wire width 17 $sshl$libresoc.v:124057$4836_Y
+ attribute \src "libresoc.v:124058.17-124058.109"
+ wire width 47 $sshl$libresoc.v:124058$4837_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:125348.7-125348.15"
+ attribute \src "libresoc.v:123973.7-123973.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125426$4883
+ cell $pos $extend$libresoc.v:124051$4827
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \DIV_sh
- connect \Y $extend$libresoc.v:125426$4883_Y
+ connect \Y $extend$libresoc.v:124051$4827_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125427$4885
+ cell $pos $extend$libresoc.v:124052$4829
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \DIV_SH32
- connect \Y $extend$libresoc.v:125427$4885_Y
+ connect \Y $extend$libresoc.v:124052$4829_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125430$4889
+ cell $pos $extend$libresoc.v:124055$4833
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \DIV_UI
- connect \Y $extend$libresoc.v:125430$4889_Y
+ connect \Y $extend$libresoc.v:124055$4833_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:125434$4894
+ cell $pos $extend$libresoc.v:124059$4838
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:125434$4894_Y
+ connect \Y $extend$libresoc.v:124059$4838_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125426$4884
+ cell $pos $pos$libresoc.v:124051$4828
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125426$4883_Y
- connect \Y $pos$libresoc.v:125426$4884_Y
+ connect \A $extend$libresoc.v:124051$4827_Y
+ connect \Y $pos$libresoc.v:124051$4828_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125427$4886
+ cell $pos $pos$libresoc.v:124052$4830
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125427$4885_Y
- connect \Y $pos$libresoc.v:125427$4886_Y
+ connect \A $extend$libresoc.v:124052$4829_Y
+ connect \Y $pos$libresoc.v:124052$4830_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125430$4890
+ cell $pos $pos$libresoc.v:124055$4834
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125430$4889_Y
- connect \Y $pos$libresoc.v:125430$4890_Y
+ connect \A $extend$libresoc.v:124055$4833_Y
+ connect \Y $pos$libresoc.v:124055$4834_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:125434$4895
+ cell $pos $pos$libresoc.v:124059$4839
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125434$4894_Y
- connect \Y $pos$libresoc.v:125434$4895_Y
+ connect \A $extend$libresoc.v:124059$4838_Y
+ connect \Y $pos$libresoc.v:124059$4839_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:125428$4887
+ cell $sshl $sshl$libresoc.v:124053$4831
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \DIV_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125428$4887_Y
+ connect \Y $sshl$libresoc.v:124053$4831_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:125429$4888
+ cell $sshl $sshl$libresoc.v:124054$4832
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \DIV_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:125429$4888_Y
+ connect \Y $sshl$libresoc.v:124054$4832_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:125431$4891
+ cell $sshl $sshl$libresoc.v:124056$4835
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \DIV_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:125431$4891_Y
+ connect \Y $sshl$libresoc.v:124056$4835_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:125432$4892
+ cell $sshl $sshl$libresoc.v:124057$4836
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \DIV_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:125432$4892_Y
+ connect \Y $sshl$libresoc.v:124057$4836_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:125433$4893
+ cell $sshl $sshl$libresoc.v:124058$4837
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125433$4893_Y
+ connect \Y $sshl$libresoc.v:124058$4837_Y
end
- attribute \src "libresoc.v:125348.7-125348.20"
- process $proc$libresoc.v:125348$4904
+ attribute \src "libresoc.v:123973.7-123973.20"
+ process $proc$libresoc.v:123973$4848
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125436.3-125482.6"
- process $proc$libresoc.v:125436$4896
+ attribute \src "libresoc.v:124061.3-124107.6"
+ process $proc$libresoc.v:124061$4840
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:125437.5-125437.29"
+ attribute \src "libresoc.v:124062.5-124062.29"
switch \initial
- attribute \src "libresoc.v:125437.9-125437.17"
+ attribute \src "libresoc.v:124062.9-124062.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:125483.3-125529.6"
- process $proc$libresoc.v:125483$4897
+ attribute \src "libresoc.v:124108.3-124154.6"
+ process $proc$libresoc.v:124108$4841
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125484.5-125484.29"
+ attribute \src "libresoc.v:124109.5-124109.29"
switch \initial
- attribute \src "libresoc.v:125484.9-125484.17"
+ attribute \src "libresoc.v:124109.9-124109.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:125530.3-125540.6"
- process $proc$libresoc.v:125530$4898
+ attribute \src "libresoc.v:124155.3-124165.6"
+ process $proc$libresoc.v:124155$4842
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:125531.5-125531.29"
+ attribute \src "libresoc.v:124156.5-124156.29"
switch \initial
- attribute \src "libresoc.v:125531.9-125531.17"
+ attribute \src "libresoc.v:124156.9-124156.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:125541.3-125551.6"
- process $proc$libresoc.v:125541$4899
+ attribute \src "libresoc.v:124166.3-124176.6"
+ process $proc$libresoc.v:124166$4843
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:125542.5-125542.29"
+ attribute \src "libresoc.v:124167.5-124167.29"
switch \initial
- attribute \src "libresoc.v:125542.9-125542.17"
+ attribute \src "libresoc.v:124167.9-124167.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:125552.3-125562.6"
- process $proc$libresoc.v:125552$4900
+ attribute \src "libresoc.v:124177.3-124187.6"
+ process $proc$libresoc.v:124177$4844
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:125553.5-125553.29"
+ attribute \src "libresoc.v:124178.5-124178.29"
switch \initial
- attribute \src "libresoc.v:125553.9-125553.17"
+ attribute \src "libresoc.v:124178.9-124178.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:125563.3-125573.6"
- process $proc$libresoc.v:125563$4901
+ attribute \src "libresoc.v:124188.3-124198.6"
+ process $proc$libresoc.v:124188$4845
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:125564.5-125564.29"
+ attribute \src "libresoc.v:124189.5-124189.29"
switch \initial
- attribute \src "libresoc.v:125564.9-125564.17"
+ attribute \src "libresoc.v:124189.9-124189.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:125574.3-125584.6"
- process $proc$libresoc.v:125574$4902
+ attribute \src "libresoc.v:124199.3-124209.6"
+ process $proc$libresoc.v:124199$4846
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:125575.5-125575.29"
+ attribute \src "libresoc.v:124200.5-124200.29"
switch \initial
- attribute \src "libresoc.v:125575.9-125575.17"
+ attribute \src "libresoc.v:124200.9-124200.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:125585.3-125595.6"
- process $proc$libresoc.v:125585$4903
+ attribute \src "libresoc.v:124210.3-124220.6"
+ process $proc$libresoc.v:124210$4847
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:125586.5-125586.29"
+ attribute \src "libresoc.v:124211.5-124211.29"
switch \initial
- attribute \src "libresoc.v:125586.9-125586.17"
+ attribute \src "libresoc.v:124211.9-124211.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:125426$4884_Y
- connect \$11 $pos$libresoc.v:125427$4886_Y
- connect \$14 $sshl$libresoc.v:125428$4887_Y
- connect \$17 $sshl$libresoc.v:125429$4888_Y
- connect \$1 $pos$libresoc.v:125430$4890_Y
- connect \$20 $sshl$libresoc.v:125431$4891_Y
- connect \$23 $sshl$libresoc.v:125432$4892_Y
- connect \$4 $sshl$libresoc.v:125433$4893_Y
- connect \$3 $pos$libresoc.v:125434$4895_Y
+ connect \$9 $pos$libresoc.v:124051$4828_Y
+ connect \$11 $pos$libresoc.v:124052$4830_Y
+ connect \$14 $sshl$libresoc.v:124053$4831_Y
+ connect \$17 $sshl$libresoc.v:124054$4832_Y
+ connect \$1 $pos$libresoc.v:124055$4834_Y
+ connect \$20 $sshl$libresoc.v:124056$4835_Y
+ connect \$23 $sshl$libresoc.v:124057$4836_Y
+ connect \$4 $sshl$libresoc.v:124058$4837_Y
+ connect \$3 $pos$libresoc.v:124059$4839_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:125604.1-125857.10"
+attribute \src "libresoc.v:124229.1-124482.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi"
attribute \generator "nMigen"
module \dec_bi$161
- attribute \src "libresoc.v:125831.3-125841.6"
+ attribute \src "libresoc.v:124456.3-124466.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:125842.3-125852.6"
+ attribute \src "libresoc.v:124467.3-124477.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:125693.3-125739.6"
+ attribute \src "libresoc.v:124318.3-124364.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:125740.3-125786.6"
+ attribute \src "libresoc.v:124365.3-124411.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:125605.7-125605.20"
+ attribute \src "libresoc.v:124230.7-124230.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:125820.3-125830.6"
+ attribute \src "libresoc.v:124445.3-124455.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:125787.3-125797.6"
+ attribute \src "libresoc.v:124412.3-124422.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:125798.3-125808.6"
+ attribute \src "libresoc.v:124423.3-124433.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:125809.3-125819.6"
+ attribute \src "libresoc.v:124434.3-124444.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:125831.3-125841.6"
+ attribute \src "libresoc.v:124456.3-124466.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:125842.3-125852.6"
+ attribute \src "libresoc.v:124467.3-124477.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:125693.3-125739.6"
+ attribute \src "libresoc.v:124318.3-124364.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:125740.3-125786.6"
+ attribute \src "libresoc.v:124365.3-124411.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125820.3-125830.6"
+ attribute \src "libresoc.v:124445.3-124455.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:125787.3-125797.6"
+ attribute \src "libresoc.v:124412.3-124422.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:125798.3-125808.6"
+ attribute \src "libresoc.v:124423.3-124433.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:125809.3-125819.6"
+ attribute \src "libresoc.v:124434.3-124444.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:125683.17-125683.104"
- wire width 64 $extend$libresoc.v:125683$4905_Y
- attribute \src "libresoc.v:125684.18-125684.107"
- wire width 64 $extend$libresoc.v:125684$4907_Y
- attribute \src "libresoc.v:125687.17-125687.104"
- wire width 64 $extend$libresoc.v:125687$4911_Y
- attribute \src "libresoc.v:125691.17-125691.102"
- wire width 64 $extend$libresoc.v:125691$4916_Y
- attribute \src "libresoc.v:125683.17-125683.104"
- wire width 64 $pos$libresoc.v:125683$4906_Y
- attribute \src "libresoc.v:125684.18-125684.107"
- wire width 64 $pos$libresoc.v:125684$4908_Y
- attribute \src "libresoc.v:125687.17-125687.104"
- wire width 64 $pos$libresoc.v:125687$4912_Y
- attribute \src "libresoc.v:125691.17-125691.102"
- wire width 64 $pos$libresoc.v:125691$4917_Y
- attribute \src "libresoc.v:125685.18-125685.114"
- wire width 47 $sshl$libresoc.v:125685$4909_Y
- attribute \src "libresoc.v:125686.18-125686.113"
- wire width 27 $sshl$libresoc.v:125686$4910_Y
- attribute \src "libresoc.v:125688.18-125688.113"
- wire width 17 $sshl$libresoc.v:125688$4913_Y
- attribute \src "libresoc.v:125689.18-125689.113"
- wire width 17 $sshl$libresoc.v:125689$4914_Y
- attribute \src "libresoc.v:125690.17-125690.109"
- wire width 47 $sshl$libresoc.v:125690$4915_Y
+ attribute \src "libresoc.v:124308.17-124308.104"
+ wire width 64 $extend$libresoc.v:124308$4849_Y
+ attribute \src "libresoc.v:124309.18-124309.107"
+ wire width 64 $extend$libresoc.v:124309$4851_Y
+ attribute \src "libresoc.v:124312.17-124312.104"
+ wire width 64 $extend$libresoc.v:124312$4855_Y
+ attribute \src "libresoc.v:124316.17-124316.102"
+ wire width 64 $extend$libresoc.v:124316$4860_Y
+ attribute \src "libresoc.v:124308.17-124308.104"
+ wire width 64 $pos$libresoc.v:124308$4850_Y
+ attribute \src "libresoc.v:124309.18-124309.107"
+ wire width 64 $pos$libresoc.v:124309$4852_Y
+ attribute \src "libresoc.v:124312.17-124312.104"
+ wire width 64 $pos$libresoc.v:124312$4856_Y
+ attribute \src "libresoc.v:124316.17-124316.102"
+ wire width 64 $pos$libresoc.v:124316$4861_Y
+ attribute \src "libresoc.v:124310.18-124310.114"
+ wire width 47 $sshl$libresoc.v:124310$4853_Y
+ attribute \src "libresoc.v:124311.18-124311.113"
+ wire width 27 $sshl$libresoc.v:124311$4854_Y
+ attribute \src "libresoc.v:124313.18-124313.113"
+ wire width 17 $sshl$libresoc.v:124313$4857_Y
+ attribute \src "libresoc.v:124314.18-124314.113"
+ wire width 17 $sshl$libresoc.v:124314$4858_Y
+ attribute \src "libresoc.v:124315.17-124315.109"
+ wire width 47 $sshl$libresoc.v:124315$4859_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:125605.7-125605.15"
+ attribute \src "libresoc.v:124230.7-124230.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125683$4905
+ cell $pos $extend$libresoc.v:124308$4849
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \MUL_sh
- connect \Y $extend$libresoc.v:125683$4905_Y
+ connect \Y $extend$libresoc.v:124308$4849_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125684$4907
+ cell $pos $extend$libresoc.v:124309$4851
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \MUL_SH32
- connect \Y $extend$libresoc.v:125684$4907_Y
+ connect \Y $extend$libresoc.v:124309$4851_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125687$4911
+ cell $pos $extend$libresoc.v:124312$4855
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \MUL_UI
- connect \Y $extend$libresoc.v:125687$4911_Y
+ connect \Y $extend$libresoc.v:124312$4855_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:125691$4916
+ cell $pos $extend$libresoc.v:124316$4860
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:125691$4916_Y
+ connect \Y $extend$libresoc.v:124316$4860_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125683$4906
+ cell $pos $pos$libresoc.v:124308$4850
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125683$4905_Y
- connect \Y $pos$libresoc.v:125683$4906_Y
+ connect \A $extend$libresoc.v:124308$4849_Y
+ connect \Y $pos$libresoc.v:124308$4850_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125684$4908
+ cell $pos $pos$libresoc.v:124309$4852
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125684$4907_Y
- connect \Y $pos$libresoc.v:125684$4908_Y
+ connect \A $extend$libresoc.v:124309$4851_Y
+ connect \Y $pos$libresoc.v:124309$4852_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125687$4912
+ cell $pos $pos$libresoc.v:124312$4856
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125687$4911_Y
- connect \Y $pos$libresoc.v:125687$4912_Y
+ connect \A $extend$libresoc.v:124312$4855_Y
+ connect \Y $pos$libresoc.v:124312$4856_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:125691$4917
+ cell $pos $pos$libresoc.v:124316$4861
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125691$4916_Y
- connect \Y $pos$libresoc.v:125691$4917_Y
+ connect \A $extend$libresoc.v:124316$4860_Y
+ connect \Y $pos$libresoc.v:124316$4861_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:125685$4909
+ cell $sshl $sshl$libresoc.v:124310$4853
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \MUL_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125685$4909_Y
+ connect \Y $sshl$libresoc.v:124310$4853_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:125686$4910
+ cell $sshl $sshl$libresoc.v:124311$4854
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \MUL_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:125686$4910_Y
+ connect \Y $sshl$libresoc.v:124311$4854_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:125688$4913
+ cell $sshl $sshl$libresoc.v:124313$4857
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \MUL_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:125688$4913_Y
+ connect \Y $sshl$libresoc.v:124313$4857_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:125689$4914
+ cell $sshl $sshl$libresoc.v:124314$4858
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \MUL_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:125689$4914_Y
+ connect \Y $sshl$libresoc.v:124314$4858_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:125690$4915
+ cell $sshl $sshl$libresoc.v:124315$4859
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125690$4915_Y
+ connect \Y $sshl$libresoc.v:124315$4859_Y
end
- attribute \src "libresoc.v:125605.7-125605.20"
- process $proc$libresoc.v:125605$4926
+ attribute \src "libresoc.v:124230.7-124230.20"
+ process $proc$libresoc.v:124230$4870
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125693.3-125739.6"
- process $proc$libresoc.v:125693$4918
+ attribute \src "libresoc.v:124318.3-124364.6"
+ process $proc$libresoc.v:124318$4862
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:125694.5-125694.29"
+ attribute \src "libresoc.v:124319.5-124319.29"
switch \initial
- attribute \src "libresoc.v:125694.9-125694.17"
+ attribute \src "libresoc.v:124319.9-124319.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:125740.3-125786.6"
- process $proc$libresoc.v:125740$4919
+ attribute \src "libresoc.v:124365.3-124411.6"
+ process $proc$libresoc.v:124365$4863
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125741.5-125741.29"
+ attribute \src "libresoc.v:124366.5-124366.29"
switch \initial
- attribute \src "libresoc.v:125741.9-125741.17"
+ attribute \src "libresoc.v:124366.9-124366.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:125787.3-125797.6"
- process $proc$libresoc.v:125787$4920
+ attribute \src "libresoc.v:124412.3-124422.6"
+ process $proc$libresoc.v:124412$4864
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:125788.5-125788.29"
+ attribute \src "libresoc.v:124413.5-124413.29"
switch \initial
- attribute \src "libresoc.v:125788.9-125788.17"
+ attribute \src "libresoc.v:124413.9-124413.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:125798.3-125808.6"
- process $proc$libresoc.v:125798$4921
+ attribute \src "libresoc.v:124423.3-124433.6"
+ process $proc$libresoc.v:124423$4865
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:125799.5-125799.29"
+ attribute \src "libresoc.v:124424.5-124424.29"
switch \initial
- attribute \src "libresoc.v:125799.9-125799.17"
+ attribute \src "libresoc.v:124424.9-124424.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:125809.3-125819.6"
- process $proc$libresoc.v:125809$4922
+ attribute \src "libresoc.v:124434.3-124444.6"
+ process $proc$libresoc.v:124434$4866
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:125810.5-125810.29"
+ attribute \src "libresoc.v:124435.5-124435.29"
switch \initial
- attribute \src "libresoc.v:125810.9-125810.17"
+ attribute \src "libresoc.v:124435.9-124435.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:125820.3-125830.6"
- process $proc$libresoc.v:125820$4923
+ attribute \src "libresoc.v:124445.3-124455.6"
+ process $proc$libresoc.v:124445$4867
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:125821.5-125821.29"
+ attribute \src "libresoc.v:124446.5-124446.29"
switch \initial
- attribute \src "libresoc.v:125821.9-125821.17"
+ attribute \src "libresoc.v:124446.9-124446.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:125831.3-125841.6"
- process $proc$libresoc.v:125831$4924
+ attribute \src "libresoc.v:124456.3-124466.6"
+ process $proc$libresoc.v:124456$4868
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:125832.5-125832.29"
+ attribute \src "libresoc.v:124457.5-124457.29"
switch \initial
- attribute \src "libresoc.v:125832.9-125832.17"
+ attribute \src "libresoc.v:124457.9-124457.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:125842.3-125852.6"
- process $proc$libresoc.v:125842$4925
+ attribute \src "libresoc.v:124467.3-124477.6"
+ process $proc$libresoc.v:124467$4869
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:125843.5-125843.29"
+ attribute \src "libresoc.v:124468.5-124468.29"
switch \initial
- attribute \src "libresoc.v:125843.9-125843.17"
+ attribute \src "libresoc.v:124468.9-124468.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:125683$4906_Y
- connect \$11 $pos$libresoc.v:125684$4908_Y
- connect \$14 $sshl$libresoc.v:125685$4909_Y
- connect \$17 $sshl$libresoc.v:125686$4910_Y
- connect \$1 $pos$libresoc.v:125687$4912_Y
- connect \$20 $sshl$libresoc.v:125688$4913_Y
- connect \$23 $sshl$libresoc.v:125689$4914_Y
- connect \$4 $sshl$libresoc.v:125690$4915_Y
- connect \$3 $pos$libresoc.v:125691$4917_Y
+ connect \$9 $pos$libresoc.v:124308$4850_Y
+ connect \$11 $pos$libresoc.v:124309$4852_Y
+ connect \$14 $sshl$libresoc.v:124310$4853_Y
+ connect \$17 $sshl$libresoc.v:124311$4854_Y
+ connect \$1 $pos$libresoc.v:124312$4856_Y
+ connect \$20 $sshl$libresoc.v:124313$4857_Y
+ connect \$23 $sshl$libresoc.v:124314$4858_Y
+ connect \$4 $sshl$libresoc.v:124315$4859_Y
+ connect \$3 $pos$libresoc.v:124316$4861_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:125861.1-126114.10"
+attribute \src "libresoc.v:124486.1-124739.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi"
attribute \generator "nMigen"
module \dec_bi$165
- attribute \src "libresoc.v:126088.3-126098.6"
+ attribute \src "libresoc.v:124713.3-124723.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:126099.3-126109.6"
+ attribute \src "libresoc.v:124724.3-124734.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:125950.3-125996.6"
+ attribute \src "libresoc.v:124575.3-124621.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:125997.3-126043.6"
+ attribute \src "libresoc.v:124622.3-124668.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:125862.7-125862.20"
+ attribute \src "libresoc.v:124487.7-124487.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126077.3-126087.6"
+ attribute \src "libresoc.v:124702.3-124712.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:126044.3-126054.6"
+ attribute \src "libresoc.v:124669.3-124679.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:126055.3-126065.6"
+ attribute \src "libresoc.v:124680.3-124690.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:126066.3-126076.6"
+ attribute \src "libresoc.v:124691.3-124701.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:126088.3-126098.6"
+ attribute \src "libresoc.v:124713.3-124723.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:126099.3-126109.6"
+ attribute \src "libresoc.v:124724.3-124734.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:125950.3-125996.6"
+ attribute \src "libresoc.v:124575.3-124621.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:125997.3-126043.6"
+ attribute \src "libresoc.v:124622.3-124668.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:126077.3-126087.6"
+ attribute \src "libresoc.v:124702.3-124712.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:126044.3-126054.6"
+ attribute \src "libresoc.v:124669.3-124679.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:126055.3-126065.6"
+ attribute \src "libresoc.v:124680.3-124690.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:126066.3-126076.6"
+ attribute \src "libresoc.v:124691.3-124701.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:125940.17-125940.110"
- wire width 64 $extend$libresoc.v:125940$4927_Y
- attribute \src "libresoc.v:125941.18-125941.113"
- wire width 64 $extend$libresoc.v:125941$4929_Y
- attribute \src "libresoc.v:125944.17-125944.110"
- wire width 64 $extend$libresoc.v:125944$4933_Y
- attribute \src "libresoc.v:125948.17-125948.102"
- wire width 64 $extend$libresoc.v:125948$4938_Y
- attribute \src "libresoc.v:125940.17-125940.110"
- wire width 64 $pos$libresoc.v:125940$4928_Y
- attribute \src "libresoc.v:125941.18-125941.113"
- wire width 64 $pos$libresoc.v:125941$4930_Y
- attribute \src "libresoc.v:125944.17-125944.110"
- wire width 64 $pos$libresoc.v:125944$4934_Y
- attribute \src "libresoc.v:125948.17-125948.102"
- wire width 64 $pos$libresoc.v:125948$4939_Y
- attribute \src "libresoc.v:125942.18-125942.120"
- wire width 47 $sshl$libresoc.v:125942$4931_Y
- attribute \src "libresoc.v:125943.18-125943.119"
- wire width 27 $sshl$libresoc.v:125943$4932_Y
- attribute \src "libresoc.v:125945.18-125945.119"
- wire width 17 $sshl$libresoc.v:125945$4935_Y
- attribute \src "libresoc.v:125946.18-125946.119"
- wire width 17 $sshl$libresoc.v:125946$4936_Y
- attribute \src "libresoc.v:125947.17-125947.109"
- wire width 47 $sshl$libresoc.v:125947$4937_Y
+ attribute \src "libresoc.v:124565.17-124565.110"
+ wire width 64 $extend$libresoc.v:124565$4871_Y
+ attribute \src "libresoc.v:124566.18-124566.113"
+ wire width 64 $extend$libresoc.v:124566$4873_Y
+ attribute \src "libresoc.v:124569.17-124569.110"
+ wire width 64 $extend$libresoc.v:124569$4877_Y
+ attribute \src "libresoc.v:124573.17-124573.102"
+ wire width 64 $extend$libresoc.v:124573$4882_Y
+ attribute \src "libresoc.v:124565.17-124565.110"
+ wire width 64 $pos$libresoc.v:124565$4872_Y
+ attribute \src "libresoc.v:124566.18-124566.113"
+ wire width 64 $pos$libresoc.v:124566$4874_Y
+ attribute \src "libresoc.v:124569.17-124569.110"
+ wire width 64 $pos$libresoc.v:124569$4878_Y
+ attribute \src "libresoc.v:124573.17-124573.102"
+ wire width 64 $pos$libresoc.v:124573$4883_Y
+ attribute \src "libresoc.v:124567.18-124567.120"
+ wire width 47 $sshl$libresoc.v:124567$4875_Y
+ attribute \src "libresoc.v:124568.18-124568.119"
+ wire width 27 $sshl$libresoc.v:124568$4876_Y
+ attribute \src "libresoc.v:124570.18-124570.119"
+ wire width 17 $sshl$libresoc.v:124570$4879_Y
+ attribute \src "libresoc.v:124571.18-124571.119"
+ wire width 17 $sshl$libresoc.v:124571$4880_Y
+ attribute \src "libresoc.v:124572.17-124572.109"
+ wire width 47 $sshl$libresoc.v:124572$4881_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:125862.7-125862.15"
+ attribute \src "libresoc.v:124487.7-124487.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125940$4927
+ cell $pos $extend$libresoc.v:124565$4871
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_sh
- connect \Y $extend$libresoc.v:125940$4927_Y
+ connect \Y $extend$libresoc.v:124565$4871_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125941$4929
+ cell $pos $extend$libresoc.v:124566$4873
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_SH32
- connect \Y $extend$libresoc.v:125941$4929_Y
+ connect \Y $extend$libresoc.v:124566$4873_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:125944$4933
+ cell $pos $extend$libresoc.v:124569$4877
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \SHIFT_ROT_UI
- connect \Y $extend$libresoc.v:125944$4933_Y
+ connect \Y $extend$libresoc.v:124569$4877_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:125948$4938
+ cell $pos $extend$libresoc.v:124573$4882
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:125948$4938_Y
+ connect \Y $extend$libresoc.v:124573$4882_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125940$4928
+ cell $pos $pos$libresoc.v:124565$4872
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125940$4927_Y
- connect \Y $pos$libresoc.v:125940$4928_Y
+ connect \A $extend$libresoc.v:124565$4871_Y
+ connect \Y $pos$libresoc.v:124565$4872_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125941$4930
+ cell $pos $pos$libresoc.v:124566$4874
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125941$4929_Y
- connect \Y $pos$libresoc.v:125941$4930_Y
+ connect \A $extend$libresoc.v:124566$4873_Y
+ connect \Y $pos$libresoc.v:124566$4874_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:125944$4934
+ cell $pos $pos$libresoc.v:124569$4878
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125944$4933_Y
- connect \Y $pos$libresoc.v:125944$4934_Y
+ connect \A $extend$libresoc.v:124569$4877_Y
+ connect \Y $pos$libresoc.v:124569$4878_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:125948$4939
+ cell $pos $pos$libresoc.v:124573$4883
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:125948$4938_Y
- connect \Y $pos$libresoc.v:125948$4939_Y
+ connect \A $extend$libresoc.v:124573$4882_Y
+ connect \Y $pos$libresoc.v:124573$4883_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:125942$4931
+ cell $sshl $sshl$libresoc.v:124567$4875
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \SHIFT_ROT_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125942$4931_Y
+ connect \Y $sshl$libresoc.v:124567$4875_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:125943$4932
+ cell $sshl $sshl$libresoc.v:124568$4876
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \SHIFT_ROT_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:125943$4932_Y
+ connect \Y $sshl$libresoc.v:124568$4876_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:125945$4935
+ cell $sshl $sshl$libresoc.v:124570$4879
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \SHIFT_ROT_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:125945$4935_Y
+ connect \Y $sshl$libresoc.v:124570$4879_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:125946$4936
+ cell $sshl $sshl$libresoc.v:124571$4880
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \SHIFT_ROT_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:125946$4936_Y
+ connect \Y $sshl$libresoc.v:124571$4880_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:125947$4937
+ cell $sshl $sshl$libresoc.v:124572$4881
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:125947$4937_Y
+ connect \Y $sshl$libresoc.v:124572$4881_Y
end
- attribute \src "libresoc.v:125862.7-125862.20"
- process $proc$libresoc.v:125862$4948
+ attribute \src "libresoc.v:124487.7-124487.20"
+ process $proc$libresoc.v:124487$4892
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:125950.3-125996.6"
- process $proc$libresoc.v:125950$4940
+ attribute \src "libresoc.v:124575.3-124621.6"
+ process $proc$libresoc.v:124575$4884
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:125951.5-125951.29"
+ attribute \src "libresoc.v:124576.5-124576.29"
switch \initial
- attribute \src "libresoc.v:125951.9-125951.17"
+ attribute \src "libresoc.v:124576.9-124576.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:125997.3-126043.6"
- process $proc$libresoc.v:125997$4941
+ attribute \src "libresoc.v:124622.3-124668.6"
+ process $proc$libresoc.v:124622$4885
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:125998.5-125998.29"
+ attribute \src "libresoc.v:124623.5-124623.29"
switch \initial
- attribute \src "libresoc.v:125998.9-125998.17"
+ attribute \src "libresoc.v:124623.9-124623.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:126044.3-126054.6"
- process $proc$libresoc.v:126044$4942
+ attribute \src "libresoc.v:124669.3-124679.6"
+ process $proc$libresoc.v:124669$4886
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:126045.5-126045.29"
+ attribute \src "libresoc.v:124670.5-124670.29"
switch \initial
- attribute \src "libresoc.v:126045.9-126045.17"
+ attribute \src "libresoc.v:124670.9-124670.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:126055.3-126065.6"
- process $proc$libresoc.v:126055$4943
+ attribute \src "libresoc.v:124680.3-124690.6"
+ process $proc$libresoc.v:124680$4887
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:126056.5-126056.29"
+ attribute \src "libresoc.v:124681.5-124681.29"
switch \initial
- attribute \src "libresoc.v:126056.9-126056.17"
+ attribute \src "libresoc.v:124681.9-124681.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:126066.3-126076.6"
- process $proc$libresoc.v:126066$4944
+ attribute \src "libresoc.v:124691.3-124701.6"
+ process $proc$libresoc.v:124691$4888
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:126067.5-126067.29"
+ attribute \src "libresoc.v:124692.5-124692.29"
switch \initial
- attribute \src "libresoc.v:126067.9-126067.17"
+ attribute \src "libresoc.v:124692.9-124692.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:126077.3-126087.6"
- process $proc$libresoc.v:126077$4945
+ attribute \src "libresoc.v:124702.3-124712.6"
+ process $proc$libresoc.v:124702$4889
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:126078.5-126078.29"
+ attribute \src "libresoc.v:124703.5-124703.29"
switch \initial
- attribute \src "libresoc.v:126078.9-126078.17"
+ attribute \src "libresoc.v:124703.9-124703.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:126088.3-126098.6"
- process $proc$libresoc.v:126088$4946
+ attribute \src "libresoc.v:124713.3-124723.6"
+ process $proc$libresoc.v:124713$4890
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:126089.5-126089.29"
+ attribute \src "libresoc.v:124714.5-124714.29"
switch \initial
- attribute \src "libresoc.v:126089.9-126089.17"
+ attribute \src "libresoc.v:124714.9-124714.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:126099.3-126109.6"
- process $proc$libresoc.v:126099$4947
+ attribute \src "libresoc.v:124724.3-124734.6"
+ process $proc$libresoc.v:124724$4891
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:126100.5-126100.29"
+ attribute \src "libresoc.v:124725.5-124725.29"
switch \initial
- attribute \src "libresoc.v:126100.9-126100.17"
+ attribute \src "libresoc.v:124725.9-124725.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:125940$4928_Y
- connect \$11 $pos$libresoc.v:125941$4930_Y
- connect \$14 $sshl$libresoc.v:125942$4931_Y
- connect \$17 $sshl$libresoc.v:125943$4932_Y
- connect \$1 $pos$libresoc.v:125944$4934_Y
- connect \$20 $sshl$libresoc.v:125945$4935_Y
- connect \$23 $sshl$libresoc.v:125946$4936_Y
- connect \$4 $sshl$libresoc.v:125947$4937_Y
- connect \$3 $pos$libresoc.v:125948$4939_Y
+ connect \$9 $pos$libresoc.v:124565$4872_Y
+ connect \$11 $pos$libresoc.v:124566$4874_Y
+ connect \$14 $sshl$libresoc.v:124567$4875_Y
+ connect \$17 $sshl$libresoc.v:124568$4876_Y
+ connect \$1 $pos$libresoc.v:124569$4878_Y
+ connect \$20 $sshl$libresoc.v:124570$4879_Y
+ connect \$23 $sshl$libresoc.v:124571$4880_Y
+ connect \$4 $sshl$libresoc.v:124572$4881_Y
+ connect \$3 $pos$libresoc.v:124573$4883_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:126118.1-126371.10"
+attribute \src "libresoc.v:124743.1-124996.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi"
attribute \generator "nMigen"
module \dec_bi$170
- attribute \src "libresoc.v:126345.3-126355.6"
+ attribute \src "libresoc.v:124970.3-124980.6"
wire width 16 $0\bd[15:0]
- attribute \src "libresoc.v:126356.3-126366.6"
+ attribute \src "libresoc.v:124981.3-124991.6"
wire width 16 $0\ds[15:0]
- attribute \src "libresoc.v:126207.3-126253.6"
+ attribute \src "libresoc.v:124832.3-124878.6"
wire width 64 $0\imm_b[63:0]
- attribute \src "libresoc.v:126254.3-126300.6"
+ attribute \src "libresoc.v:124879.3-124925.6"
wire $0\imm_b_ok[0:0]
- attribute \src "libresoc.v:126119.7-126119.20"
+ attribute \src "libresoc.v:124744.7-124744.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126334.3-126344.6"
+ attribute \src "libresoc.v:124959.3-124969.6"
wire width 26 $0\li[25:0]
- attribute \src "libresoc.v:126301.3-126311.6"
+ attribute \src "libresoc.v:124926.3-124936.6"
wire width 16 $0\si[15:0]
- attribute \src "libresoc.v:126312.3-126322.6"
+ attribute \src "libresoc.v:124937.3-124947.6"
wire width 32 $0\si_hi[31:0]
- attribute \src "libresoc.v:126323.3-126333.6"
+ attribute \src "libresoc.v:124948.3-124958.6"
wire width 16 $0\ui[15:0]
- attribute \src "libresoc.v:126345.3-126355.6"
+ attribute \src "libresoc.v:124970.3-124980.6"
wire width 16 $1\bd[15:0]
- attribute \src "libresoc.v:126356.3-126366.6"
+ attribute \src "libresoc.v:124981.3-124991.6"
wire width 16 $1\ds[15:0]
- attribute \src "libresoc.v:126207.3-126253.6"
+ attribute \src "libresoc.v:124832.3-124878.6"
wire width 64 $1\imm_b[63:0]
- attribute \src "libresoc.v:126254.3-126300.6"
+ attribute \src "libresoc.v:124879.3-124925.6"
wire $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:126334.3-126344.6"
+ attribute \src "libresoc.v:124959.3-124969.6"
wire width 26 $1\li[25:0]
- attribute \src "libresoc.v:126301.3-126311.6"
+ attribute \src "libresoc.v:124926.3-124936.6"
wire width 16 $1\si[15:0]
- attribute \src "libresoc.v:126312.3-126322.6"
+ attribute \src "libresoc.v:124937.3-124947.6"
wire width 32 $1\si_hi[31:0]
- attribute \src "libresoc.v:126323.3-126333.6"
+ attribute \src "libresoc.v:124948.3-124958.6"
wire width 16 $1\ui[15:0]
- attribute \src "libresoc.v:126197.17-126197.105"
- wire width 64 $extend$libresoc.v:126197$4949_Y
- attribute \src "libresoc.v:126198.18-126198.108"
- wire width 64 $extend$libresoc.v:126198$4951_Y
- attribute \src "libresoc.v:126201.17-126201.105"
- wire width 64 $extend$libresoc.v:126201$4955_Y
- attribute \src "libresoc.v:126205.17-126205.102"
- wire width 64 $extend$libresoc.v:126205$4960_Y
- attribute \src "libresoc.v:126197.17-126197.105"
- wire width 64 $pos$libresoc.v:126197$4950_Y
- attribute \src "libresoc.v:126198.18-126198.108"
- wire width 64 $pos$libresoc.v:126198$4952_Y
- attribute \src "libresoc.v:126201.17-126201.105"
- wire width 64 $pos$libresoc.v:126201$4956_Y
- attribute \src "libresoc.v:126205.17-126205.102"
- wire width 64 $pos$libresoc.v:126205$4961_Y
- attribute \src "libresoc.v:126199.18-126199.115"
- wire width 47 $sshl$libresoc.v:126199$4953_Y
- attribute \src "libresoc.v:126200.18-126200.114"
- wire width 27 $sshl$libresoc.v:126200$4954_Y
- attribute \src "libresoc.v:126202.18-126202.114"
- wire width 17 $sshl$libresoc.v:126202$4957_Y
- attribute \src "libresoc.v:126203.18-126203.114"
- wire width 17 $sshl$libresoc.v:126203$4958_Y
- attribute \src "libresoc.v:126204.17-126204.109"
- wire width 47 $sshl$libresoc.v:126204$4959_Y
+ attribute \src "libresoc.v:124822.17-124822.105"
+ wire width 64 $extend$libresoc.v:124822$4893_Y
+ attribute \src "libresoc.v:124823.18-124823.108"
+ wire width 64 $extend$libresoc.v:124823$4895_Y
+ attribute \src "libresoc.v:124826.17-124826.105"
+ wire width 64 $extend$libresoc.v:124826$4899_Y
+ attribute \src "libresoc.v:124830.17-124830.102"
+ wire width 64 $extend$libresoc.v:124830$4904_Y
+ attribute \src "libresoc.v:124822.17-124822.105"
+ wire width 64 $pos$libresoc.v:124822$4894_Y
+ attribute \src "libresoc.v:124823.18-124823.108"
+ wire width 64 $pos$libresoc.v:124823$4896_Y
+ attribute \src "libresoc.v:124826.17-124826.105"
+ wire width 64 $pos$libresoc.v:124826$4900_Y
+ attribute \src "libresoc.v:124830.17-124830.102"
+ wire width 64 $pos$libresoc.v:124830$4905_Y
+ attribute \src "libresoc.v:124824.18-124824.115"
+ wire width 47 $sshl$libresoc.v:124824$4897_Y
+ attribute \src "libresoc.v:124825.18-124825.114"
+ wire width 27 $sshl$libresoc.v:124825$4898_Y
+ attribute \src "libresoc.v:124827.18-124827.114"
+ wire width 17 $sshl$libresoc.v:124827$4901_Y
+ attribute \src "libresoc.v:124828.18-124828.114"
+ wire width 17 $sshl$libresoc.v:124828$4902_Y
+ attribute \src "libresoc.v:124829.17-124829.109"
+ wire width 47 $sshl$libresoc.v:124829$4903_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 64 output 1 \imm_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \imm_b_ok
- attribute \src "libresoc.v:126119.7-126119.15"
+ attribute \src "libresoc.v:124744.7-124744.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
wire width 26 \li
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:126197$4949
+ cell $pos $extend$libresoc.v:124822$4893
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \LDST_sh
- connect \Y $extend$libresoc.v:126197$4949_Y
+ connect \Y $extend$libresoc.v:124822$4893_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:126198$4951
+ cell $pos $extend$libresoc.v:124823$4895
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 64
connect \A \LDST_SH32
- connect \Y $extend$libresoc.v:126198$4951_Y
+ connect \Y $extend$libresoc.v:124823$4895_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $extend$libresoc.v:126201$4955
+ cell $pos $extend$libresoc.v:124826$4899
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 64
connect \A \LDST_UI
- connect \Y $extend$libresoc.v:126201$4955_Y
+ connect \Y $extend$libresoc.v:124826$4899_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $extend$libresoc.v:126205$4960
+ cell $pos $extend$libresoc.v:124830$4904
parameter \A_SIGNED 0
parameter \A_WIDTH 47
parameter \Y_WIDTH 64
connect \A \$4
- connect \Y $extend$libresoc.v:126205$4960_Y
+ connect \Y $extend$libresoc.v:124830$4904_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:126197$4950
+ cell $pos $pos$libresoc.v:124822$4894
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126197$4949_Y
- connect \Y $pos$libresoc.v:126197$4950_Y
+ connect \A $extend$libresoc.v:124822$4893_Y
+ connect \Y $pos$libresoc.v:124822$4894_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:126198$4952
+ cell $pos $pos$libresoc.v:124823$4896
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126198$4951_Y
- connect \Y $pos$libresoc.v:126198$4952_Y
+ connect \A $extend$libresoc.v:124823$4895_Y
+ connect \Y $pos$libresoc.v:124823$4896_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- cell $pos $pos$libresoc.v:126201$4956
+ cell $pos $pos$libresoc.v:124826$4900
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126201$4955_Y
- connect \Y $pos$libresoc.v:126201$4956_Y
+ connect \A $extend$libresoc.v:124826$4899_Y
+ connect \Y $pos$libresoc.v:124826$4900_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $pos $pos$libresoc.v:126205$4961
+ cell $pos $pos$libresoc.v:124830$4905
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:126205$4960_Y
- connect \Y $pos$libresoc.v:126205$4961_Y
+ connect \A $extend$libresoc.v:124830$4904_Y
+ connect \Y $pos$libresoc.v:124830$4905_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250"
- cell $sshl $sshl$libresoc.v:126199$4953
+ cell $sshl $sshl$libresoc.v:124824$4897
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \LDST_SI
connect \B 5'10000
- connect \Y $sshl$libresoc.v:126199$4953_Y
+ connect \Y $sshl$libresoc.v:124824$4897_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
- cell $sshl $sshl$libresoc.v:126200$4954
+ cell $sshl $sshl$libresoc.v:124825$4898
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 27
connect \A \LDST_LI
connect \B 2'10
- connect \Y $sshl$libresoc.v:126200$4954_Y
+ connect \Y $sshl$libresoc.v:124825$4898_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
- cell $sshl $sshl$libresoc.v:126202$4957
+ cell $sshl $sshl$libresoc.v:124827$4901
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LDST_BD
connect \B 2'10
- connect \Y $sshl$libresoc.v:126202$4957_Y
+ connect \Y $sshl$libresoc.v:124827$4901_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
- cell $sshl $sshl$libresoc.v:126203$4958
+ cell $sshl $sshl$libresoc.v:124828$4902
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \B_SIGNED 0
parameter \Y_WIDTH 17
connect \A \LDST_DS
connect \B 2'10
- connect \Y $sshl$libresoc.v:126203$4958_Y
+ connect \Y $sshl$libresoc.v:124828$4902_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
- cell $sshl $sshl$libresoc.v:126204$4959
+ cell $sshl $sshl$libresoc.v:124829$4903
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 47
connect \A \ui
connect \B 5'10000
- connect \Y $sshl$libresoc.v:126204$4959_Y
+ connect \Y $sshl$libresoc.v:124829$4903_Y
end
- attribute \src "libresoc.v:126119.7-126119.20"
- process $proc$libresoc.v:126119$4970
+ attribute \src "libresoc.v:124744.7-124744.20"
+ process $proc$libresoc.v:124744$4914
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126207.3-126253.6"
- process $proc$libresoc.v:126207$4962
+ attribute \src "libresoc.v:124832.3-124878.6"
+ process $proc$libresoc.v:124832$4906
assign { } { }
assign { } { }
assign $0\imm_b[63:0] $1\imm_b[63:0]
- attribute \src "libresoc.v:126208.5-126208.29"
+ attribute \src "libresoc.v:124833.5-124833.29"
switch \initial
- attribute \src "libresoc.v:126208.9-126208.17"
+ attribute \src "libresoc.v:124833.9-124833.17"
case 1'1
case
end
sync always
update \imm_b $0\imm_b[63:0]
end
- attribute \src "libresoc.v:126254.3-126300.6"
- process $proc$libresoc.v:126254$4963
+ attribute \src "libresoc.v:124879.3-124925.6"
+ process $proc$libresoc.v:124879$4907
assign { } { }
assign { } { }
assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0]
- attribute \src "libresoc.v:126255.5-126255.29"
+ attribute \src "libresoc.v:124880.5-124880.29"
switch \initial
- attribute \src "libresoc.v:126255.9-126255.17"
+ attribute \src "libresoc.v:124880.9-124880.17"
case 1'1
case
end
sync always
update \imm_b_ok $0\imm_b_ok[0:0]
end
- attribute \src "libresoc.v:126301.3-126311.6"
- process $proc$libresoc.v:126301$4964
+ attribute \src "libresoc.v:124926.3-124936.6"
+ process $proc$libresoc.v:124926$4908
assign { } { }
assign { } { }
assign $0\si[15:0] $1\si[15:0]
- attribute \src "libresoc.v:126302.5-126302.29"
+ attribute \src "libresoc.v:124927.5-124927.29"
switch \initial
- attribute \src "libresoc.v:126302.9-126302.17"
+ attribute \src "libresoc.v:124927.9-124927.17"
case 1'1
case
end
sync always
update \si $0\si[15:0]
end
- attribute \src "libresoc.v:126312.3-126322.6"
- process $proc$libresoc.v:126312$4965
+ attribute \src "libresoc.v:124937.3-124947.6"
+ process $proc$libresoc.v:124937$4909
assign { } { }
assign { } { }
assign $0\si_hi[31:0] $1\si_hi[31:0]
- attribute \src "libresoc.v:126313.5-126313.29"
+ attribute \src "libresoc.v:124938.5-124938.29"
switch \initial
- attribute \src "libresoc.v:126313.9-126313.17"
+ attribute \src "libresoc.v:124938.9-124938.17"
case 1'1
case
end
sync always
update \si_hi $0\si_hi[31:0]
end
- attribute \src "libresoc.v:126323.3-126333.6"
- process $proc$libresoc.v:126323$4966
+ attribute \src "libresoc.v:124948.3-124958.6"
+ process $proc$libresoc.v:124948$4910
assign { } { }
assign { } { }
assign $0\ui[15:0] $1\ui[15:0]
- attribute \src "libresoc.v:126324.5-126324.29"
+ attribute \src "libresoc.v:124949.5-124949.29"
switch \initial
- attribute \src "libresoc.v:126324.9-126324.17"
+ attribute \src "libresoc.v:124949.9-124949.17"
case 1'1
case
end
sync always
update \ui $0\ui[15:0]
end
- attribute \src "libresoc.v:126334.3-126344.6"
- process $proc$libresoc.v:126334$4967
+ attribute \src "libresoc.v:124959.3-124969.6"
+ process $proc$libresoc.v:124959$4911
assign { } { }
assign { } { }
assign $0\li[25:0] $1\li[25:0]
- attribute \src "libresoc.v:126335.5-126335.29"
+ attribute \src "libresoc.v:124960.5-124960.29"
switch \initial
- attribute \src "libresoc.v:126335.9-126335.17"
+ attribute \src "libresoc.v:124960.9-124960.17"
case 1'1
case
end
sync always
update \li $0\li[25:0]
end
- attribute \src "libresoc.v:126345.3-126355.6"
- process $proc$libresoc.v:126345$4968
+ attribute \src "libresoc.v:124970.3-124980.6"
+ process $proc$libresoc.v:124970$4912
assign { } { }
assign { } { }
assign $0\bd[15:0] $1\bd[15:0]
- attribute \src "libresoc.v:126346.5-126346.29"
+ attribute \src "libresoc.v:124971.5-124971.29"
switch \initial
- attribute \src "libresoc.v:126346.9-126346.17"
+ attribute \src "libresoc.v:124971.9-124971.17"
case 1'1
case
end
sync always
update \bd $0\bd[15:0]
end
- attribute \src "libresoc.v:126356.3-126366.6"
- process $proc$libresoc.v:126356$4969
+ attribute \src "libresoc.v:124981.3-124991.6"
+ process $proc$libresoc.v:124981$4913
assign { } { }
assign { } { }
assign $0\ds[15:0] $1\ds[15:0]
- attribute \src "libresoc.v:126357.5-126357.29"
+ attribute \src "libresoc.v:124982.5-124982.29"
switch \initial
- attribute \src "libresoc.v:126357.9-126357.17"
+ attribute \src "libresoc.v:124982.9-124982.17"
case 1'1
case
end
sync always
update \ds $0\ds[15:0]
end
- connect \$9 $pos$libresoc.v:126197$4950_Y
- connect \$11 $pos$libresoc.v:126198$4952_Y
- connect \$14 $sshl$libresoc.v:126199$4953_Y
- connect \$17 $sshl$libresoc.v:126200$4954_Y
- connect \$1 $pos$libresoc.v:126201$4956_Y
- connect \$20 $sshl$libresoc.v:126202$4957_Y
- connect \$23 $sshl$libresoc.v:126203$4958_Y
- connect \$4 $sshl$libresoc.v:126204$4959_Y
- connect \$3 $pos$libresoc.v:126205$4961_Y
+ connect \$9 $pos$libresoc.v:124822$4894_Y
+ connect \$11 $pos$libresoc.v:124823$4896_Y
+ connect \$14 $sshl$libresoc.v:124824$4897_Y
+ connect \$17 $sshl$libresoc.v:124825$4898_Y
+ connect \$1 $pos$libresoc.v:124826$4900_Y
+ connect \$20 $sshl$libresoc.v:124827$4901_Y
+ connect \$23 $sshl$libresoc.v:124828$4902_Y
+ connect \$4 $sshl$libresoc.v:124829$4903_Y
+ connect \$3 $pos$libresoc.v:124830$4905_Y
connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111
connect \$13 \$14
connect \$16 \$17
connect \$19 \$20
connect \$22 \$23
end
-attribute \src "libresoc.v:126375.1-126423.10"
+attribute \src "libresoc.v:125000.1-125048.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c"
attribute \generator "nMigen"
module \dec_c
- attribute \src "libresoc.v:126376.7-126376.20"
+ attribute \src "libresoc.v:125001.7-125001.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126393.3-126407.6"
+ attribute \src "libresoc.v:125018.3-125032.6"
wire width 5 $0\reg_c[4:0]
- attribute \src "libresoc.v:126408.3-126422.6"
+ attribute \src "libresoc.v:125033.3-125047.6"
wire $0\reg_c_ok[0:0]
- attribute \src "libresoc.v:126393.3-126407.6"
+ attribute \src "libresoc.v:125018.3-125032.6"
wire width 5 $1\reg_c[4:0]
- attribute \src "libresoc.v:126408.3-126422.6"
+ attribute \src "libresoc.v:125033.3-125047.6"
wire $1\reg_c_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 5 input 4 \RB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire width 5 input 3 \RS
- attribute \src "libresoc.v:126376.7-126376.15"
+ attribute \src "libresoc.v:125001.7-125001.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 5 output 1 \reg_c
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:126376.7-126376.20"
- process $proc$libresoc.v:126376$4973
+ attribute \src "libresoc.v:125001.7-125001.20"
+ process $proc$libresoc.v:125001$4917
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126393.3-126407.6"
- process $proc$libresoc.v:126393$4971
+ attribute \src "libresoc.v:125018.3-125032.6"
+ process $proc$libresoc.v:125018$4915
assign { } { }
assign { } { }
assign $0\reg_c[4:0] $1\reg_c[4:0]
- attribute \src "libresoc.v:126394.5-126394.29"
+ attribute \src "libresoc.v:125019.5-125019.29"
switch \initial
- attribute \src "libresoc.v:126394.9-126394.17"
+ attribute \src "libresoc.v:125019.9-125019.17"
case 1'1
case
end
sync always
update \reg_c $0\reg_c[4:0]
end
- attribute \src "libresoc.v:126408.3-126422.6"
- process $proc$libresoc.v:126408$4972
+ attribute \src "libresoc.v:125033.3-125047.6"
+ process $proc$libresoc.v:125033$4916
assign { } { }
assign { } { }
assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0]
- attribute \src "libresoc.v:126409.5-126409.29"
+ attribute \src "libresoc.v:125034.5-125034.29"
switch \initial
- attribute \src "libresoc.v:126409.9-126409.17"
+ attribute \src "libresoc.v:125034.9-125034.17"
case 1'1
case
end
update \reg_c_ok $0\reg_c_ok[0:0]
end
end
-attribute \src "libresoc.v:126427.1-126759.10"
+attribute \src "libresoc.v:125052.1-125383.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in"
attribute \generator "nMigen"
module \dec_cr_in
- attribute \src "libresoc.v:126679.3-126709.6"
+ attribute \src "libresoc.v:125303.3-125333.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:126710.3-126720.6"
+ attribute \src "libresoc.v:125334.3-125344.6"
wire width 3 $0\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:126612.3-126622.6"
+ attribute \src "libresoc.v:125236.3-125246.6"
wire $0\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:126721.3-126731.6"
+ attribute \src "libresoc.v:125345.3-125355.6"
wire width 3 $0\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:126642.3-126652.6"
+ attribute \src "libresoc.v:125266.3-125276.6"
wire $0\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:126581.3-126611.6"
+ attribute \src "libresoc.v:125205.3-125235.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126623.3-126641.6"
+ attribute \src "libresoc.v:125247.3-125265.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:126653.3-126663.6"
+ attribute \src "libresoc.v:125277.3-125287.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126428.7-126428.20"
+ attribute \src "libresoc.v:125053.7-125053.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126732.3-126742.6"
+ attribute \src "libresoc.v:125356.3-125366.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:126743.3-126758.6"
+ attribute \src "libresoc.v:125367.3-125382.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:126664.3-126678.6"
+ attribute \src "libresoc.v:125288.3-125302.6"
wire width 2 $0\sv_override[1:0]
- attribute \src "libresoc.v:126679.3-126709.6"
+ attribute \src "libresoc.v:125303.3-125333.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:126710.3-126720.6"
+ attribute \src "libresoc.v:125334.3-125344.6"
wire width 3 $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:126612.3-126622.6"
+ attribute \src "libresoc.v:125236.3-125246.6"
wire $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:126721.3-126731.6"
+ attribute \src "libresoc.v:125345.3-125355.6"
wire width 3 $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:126642.3-126652.6"
+ attribute \src "libresoc.v:125266.3-125276.6"
wire $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:126581.3-126611.6"
+ attribute \src "libresoc.v:125205.3-125235.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126623.3-126641.6"
+ attribute \src "libresoc.v:125247.3-125265.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:126653.3-126663.6"
+ attribute \src "libresoc.v:125277.3-125287.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126732.3-126742.6"
+ attribute \src "libresoc.v:125356.3-125366.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:126743.3-126758.6"
+ attribute \src "libresoc.v:125367.3-125382.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:126664.3-126678.6"
+ attribute \src "libresoc.v:125288.3-125302.6"
wire width 2 $1\sv_override[1:0]
- attribute \src "libresoc.v:126623.3-126641.6"
+ attribute \src "libresoc.v:125247.3-125265.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:126743.3-126758.6"
+ attribute \src "libresoc.v:125367.3-125382.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:126574.17-126574.112"
- wire $and$libresoc.v:126574$4975_Y
- attribute \src "libresoc.v:126576.17-126576.112"
- wire $and$libresoc.v:126576$4977_Y
- attribute \src "libresoc.v:126573.17-126573.117"
- wire $eq$libresoc.v:126573$4974_Y
- attribute \src "libresoc.v:126575.17-126575.117"
- wire $eq$libresoc.v:126575$4976_Y
+ attribute \src "libresoc.v:125198.17-125198.112"
+ wire $and$libresoc.v:125198$4919_Y
+ attribute \src "libresoc.v:125200.17-125200.112"
+ wire $and$libresoc.v:125200$4921_Y
+ attribute \src "libresoc.v:125197.17-125197.117"
+ wire $eq$libresoc.v:125197$4918_Y
+ attribute \src "libresoc.v:125199.17-125199.117"
+ wire $eq$libresoc.v:125199$4920_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
wire \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 input 13 \BA
+ wire width 5 input 12 \BA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 input 12 \BB
+ wire width 5 input 11 \BB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 input 17 \BC
+ wire width 5 input 16 \BC
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 input 16 \BI
+ wire width 5 input 15 \BI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 5 input 14 \BT
+ wire width 5 input 13 \BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 8 input 15 \FXM
+ wire width 8 input 14 \FXM
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 3 input 18 \X_BFA
+ wire width 3 input 17 \X_BFA
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 5 \cr_bitfield
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 8 \cr_bitfield_b
+ wire width 3 output 7 \cr_bitfield_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 9 \cr_bitfield_b_ok
+ wire output 8 \cr_bitfield_b_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 3 output 10 \cr_bitfield_o
+ wire width 3 output 9 \cr_bitfield_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 11 \cr_bitfield_o_ok
+ wire output 10 \cr_bitfield_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 7 \cr_bitfield_ok
+ wire output 6 \cr_bitfield_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 8 output 3 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \cr_fxm_ok
- attribute \src "libresoc.v:126428.7-126428.15"
+ attribute \src "libresoc.v:125053.7-125053.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517"
wire width 32 input 1 \insn_in
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 7 input 19 \internal_op
+ wire width 7 input 18 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568"
wire \move_one
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516"
wire width 3 input 2 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522"
- wire width 2 output 6 \sv_override
+ wire width 2 \sv_override
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
- cell $and $and$libresoc.v:126574$4975
+ cell $and $and$libresoc.v:125198$4919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \move_one
- connect \Y $and$libresoc.v:126574$4975_Y
+ connect \Y $and$libresoc.v:125198$4919_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
- cell $and $and$libresoc.v:126576$4977
+ cell $and $and$libresoc.v:125200$4921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \move_one
- connect \Y $and$libresoc.v:126576$4977_Y
+ connect \Y $and$libresoc.v:125200$4921_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
- cell $eq $eq$libresoc.v:126573$4974
+ cell $eq $eq$libresoc.v:125197$4918
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:126573$4974_Y
+ connect \Y $eq$libresoc.v:125197$4918_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570"
- cell $eq $eq$libresoc.v:126575$4976
+ cell $eq $eq$libresoc.v:125199$4920
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:126575$4976_Y
+ connect \Y $eq$libresoc.v:125199$4920_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:126577.9-126580.4"
+ attribute \src "libresoc.v:125201.9-125204.4"
cell \ppick \ppick
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:126428.7-126428.20"
- process $proc$libresoc.v:126428$4989
+ attribute \src "libresoc.v:125053.7-125053.20"
+ process $proc$libresoc.v:125053$4933
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126581.3-126611.6"
- process $proc$libresoc.v:126581$4978
+ attribute \src "libresoc.v:125205.3-125235.6"
+ process $proc$libresoc.v:125205$4922
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126582.5-126582.29"
+ attribute \src "libresoc.v:125206.5-125206.29"
switch \initial
- attribute \src "libresoc.v:126582.9-126582.17"
+ attribute \src "libresoc.v:125206.9-125206.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:126612.3-126622.6"
- process $proc$libresoc.v:126612$4979
+ attribute \src "libresoc.v:125236.3-125246.6"
+ process $proc$libresoc.v:125236$4923
assign { } { }
assign { } { }
assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:126613.5-126613.29"
+ attribute \src "libresoc.v:125237.5-125237.29"
switch \initial
- attribute \src "libresoc.v:126613.9-126613.17"
+ attribute \src "libresoc.v:125237.9-125237.17"
case 1'1
case
end
sync always
update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0]
end
- attribute \src "libresoc.v:126623.3-126641.6"
- process $proc$libresoc.v:126623$4980
+ attribute \src "libresoc.v:125247.3-125265.6"
+ process $proc$libresoc.v:125247$4924
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:126624.5-126624.29"
+ attribute \src "libresoc.v:125248.5-125248.29"
switch \initial
- attribute \src "libresoc.v:126624.9-126624.17"
+ attribute \src "libresoc.v:125248.9-125248.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- attribute \src "libresoc.v:126642.3-126652.6"
- process $proc$libresoc.v:126642$4981
+ attribute \src "libresoc.v:125266.3-125276.6"
+ process $proc$libresoc.v:125266$4925
assign { } { }
assign { } { }
assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:126643.5-126643.29"
+ attribute \src "libresoc.v:125267.5-125267.29"
switch \initial
- attribute \src "libresoc.v:126643.9-126643.17"
+ attribute \src "libresoc.v:125267.9-125267.17"
case 1'1
case
end
sync always
update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0]
end
- attribute \src "libresoc.v:126653.3-126663.6"
- process $proc$libresoc.v:126653$4982
+ attribute \src "libresoc.v:125277.3-125287.6"
+ process $proc$libresoc.v:125277$4926
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126654.5-126654.29"
+ attribute \src "libresoc.v:125278.5-125278.29"
switch \initial
- attribute \src "libresoc.v:126654.9-126654.17"
+ attribute \src "libresoc.v:125278.9-125278.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:126664.3-126678.6"
- process $proc$libresoc.v:126664$4983
+ attribute \src "libresoc.v:125288.3-125302.6"
+ process $proc$libresoc.v:125288$4927
assign { } { }
assign { } { }
assign $0\sv_override[1:0] $1\sv_override[1:0]
- attribute \src "libresoc.v:126665.5-126665.29"
+ attribute \src "libresoc.v:125289.5-125289.29"
switch \initial
- attribute \src "libresoc.v:126665.9-126665.17"
+ attribute \src "libresoc.v:125289.9-125289.17"
case 1'1
case
end
sync always
update \sv_override $0\sv_override[1:0]
end
- attribute \src "libresoc.v:126679.3-126709.6"
- process $proc$libresoc.v:126679$4984
+ attribute \src "libresoc.v:125303.3-125333.6"
+ process $proc$libresoc.v:125303$4928
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:126680.5-126680.29"
+ attribute \src "libresoc.v:125304.5-125304.29"
switch \initial
- attribute \src "libresoc.v:126680.9-126680.17"
+ attribute \src "libresoc.v:125304.9-125304.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:126710.3-126720.6"
- process $proc$libresoc.v:126710$4985
+ attribute \src "libresoc.v:125334.3-125344.6"
+ process $proc$libresoc.v:125334$4929
assign { } { }
assign { } { }
assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:126711.5-126711.29"
+ attribute \src "libresoc.v:125335.5-125335.29"
switch \initial
- attribute \src "libresoc.v:126711.9-126711.17"
+ attribute \src "libresoc.v:125335.9-125335.17"
case 1'1
case
end
sync always
update \cr_bitfield_b $0\cr_bitfield_b[2:0]
end
- attribute \src "libresoc.v:126721.3-126731.6"
- process $proc$libresoc.v:126721$4986
+ attribute \src "libresoc.v:125345.3-125355.6"
+ process $proc$libresoc.v:125345$4930
assign { } { }
assign { } { }
assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:126722.5-126722.29"
+ attribute \src "libresoc.v:125346.5-125346.29"
switch \initial
- attribute \src "libresoc.v:126722.9-126722.17"
+ attribute \src "libresoc.v:125346.9-125346.17"
case 1'1
case
end
sync always
update \cr_bitfield_o $0\cr_bitfield_o[2:0]
end
- attribute \src "libresoc.v:126732.3-126742.6"
- process $proc$libresoc.v:126732$4987
+ attribute \src "libresoc.v:125356.3-125366.6"
+ process $proc$libresoc.v:125356$4931
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:126733.5-126733.29"
+ attribute \src "libresoc.v:125357.5-125357.29"
switch \initial
- attribute \src "libresoc.v:126733.9-126733.17"
+ attribute \src "libresoc.v:125357.9-125357.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:126743.3-126758.6"
- process $proc$libresoc.v:126743$4988
+ attribute \src "libresoc.v:125367.3-125382.6"
+ process $proc$libresoc.v:125367$4932
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:126744.5-126744.29"
+ attribute \src "libresoc.v:125368.5-125368.29"
switch \initial
- attribute \src "libresoc.v:126744.9-126744.17"
+ attribute \src "libresoc.v:125368.9-125368.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- connect \$1 $eq$libresoc.v:126573$4974_Y
- connect \$3 $and$libresoc.v:126574$4975_Y
- connect \$5 $eq$libresoc.v:126575$4976_Y
- connect \$7 $and$libresoc.v:126576$4977_Y
+ connect \$1 $eq$libresoc.v:125197$4918_Y
+ connect \$3 $and$libresoc.v:125198$4919_Y
+ connect \$5 $eq$libresoc.v:125199$4920_Y
+ connect \$7 $and$libresoc.v:125200$4921_Y
end
-attribute \src "libresoc.v:126763.1-127033.10"
+attribute \src "libresoc.v:125387.1-125656.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out"
attribute \generator "nMigen"
module \dec_cr_out
- attribute \src "libresoc.v:126943.3-126965.6"
+ attribute \src "libresoc.v:125566.3-125588.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:126894.3-126916.6"
+ attribute \src "libresoc.v:125517.3-125539.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126998.3-127032.6"
+ attribute \src "libresoc.v:125621.3-125655.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:126917.3-126927.6"
+ attribute \src "libresoc.v:125540.3-125550.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126764.7-126764.20"
+ attribute \src "libresoc.v:125388.7-125388.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:126966.3-126976.6"
+ attribute \src "libresoc.v:125589.3-125599.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:126977.3-126997.6"
+ attribute \src "libresoc.v:125600.3-125620.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:126928.3-126942.6"
+ attribute \src "libresoc.v:125551.3-125565.6"
wire width 2 $0\sv_override[1:0]
- attribute \src "libresoc.v:126943.3-126965.6"
+ attribute \src "libresoc.v:125566.3-125588.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:126894.3-126916.6"
+ attribute \src "libresoc.v:125517.3-125539.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126998.3-127032.6"
+ attribute \src "libresoc.v:125621.3-125655.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:126917.3-126927.6"
+ attribute \src "libresoc.v:125540.3-125550.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126966.3-126976.6"
+ attribute \src "libresoc.v:125589.3-125599.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:126977.3-126997.6"
+ attribute \src "libresoc.v:125600.3-125620.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:126928.3-126942.6"
+ attribute \src "libresoc.v:125551.3-125565.6"
wire width 2 $1\sv_override[1:0]
- attribute \src "libresoc.v:126998.3-127032.6"
+ attribute \src "libresoc.v:125621.3-125655.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:126977.3-126997.6"
+ attribute \src "libresoc.v:125600.3-125620.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:126998.3-127032.6"
+ attribute \src "libresoc.v:125621.3-125655.6"
wire width 8 $3\cr_fxm[7:0]
- attribute \src "libresoc.v:126977.3-126997.6"
+ attribute \src "libresoc.v:125600.3-125620.6"
wire width 8 $3\ppick_i[7:0]
- attribute \src "libresoc.v:126998.3-127032.6"
+ attribute \src "libresoc.v:125621.3-125655.6"
wire width 8 $4\cr_fxm[7:0]
- attribute \src "libresoc.v:126887.17-126887.117"
- wire $eq$libresoc.v:126887$4990_Y
- attribute \src "libresoc.v:126888.17-126888.117"
- wire $eq$libresoc.v:126888$4991_Y
+ attribute \src "libresoc.v:125510.17-125510.117"
+ wire $eq$libresoc.v:125510$4934_Y
+ attribute \src "libresoc.v:125511.17-125511.117"
+ wire $eq$libresoc.v:125511$4935_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
- wire width 8 input 9 \FXM
+ wire width 8 input 8 \FXM
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 5 input 11 \XL_BT
+ wire width 5 input 10 \XL_BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481"
- wire width 3 input 10 \X_BF
+ wire width 3 input 9 \X_BF
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 6 \cr_bitfield
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire output 8 \cr_bitfield_ok
+ wire output 7 \cr_bitfield_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 8 output 4 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \cr_fxm_ok
- attribute \src "libresoc.v:126764.7-126764.15"
+ attribute \src "libresoc.v:125388.7-125388.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592"
wire width 32 input 1 \insn_in
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
- wire width 7 input 12 \internal_op
+ wire width 7 input 11 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633"
wire \move_one
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591"
wire width 3 input 2 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595"
- wire width 2 output 7 \sv_override
+ wire width 2 \sv_override
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635"
- cell $eq $eq$libresoc.v:126887$4990
+ cell $eq $eq$libresoc.v:125510$4934
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:126887$4990_Y
+ connect \Y $eq$libresoc.v:125510$4934_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635"
- cell $eq $eq$libresoc.v:126888$4991
+ cell $eq $eq$libresoc.v:125511$4935
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:126888$4991_Y
+ connect \Y $eq$libresoc.v:125511$4935_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:126889.15-126893.4"
+ attribute \src "libresoc.v:125512.15-125516.4"
cell \ppick$175 \ppick
connect \en_o \ppick_en_o
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:126764.7-126764.20"
- process $proc$libresoc.v:126764$4999
+ attribute \src "libresoc.v:125388.7-125388.20"
+ process $proc$libresoc.v:125388$4943
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:126894.3-126916.6"
- process $proc$libresoc.v:126894$4992
+ attribute \src "libresoc.v:125517.3-125539.6"
+ process $proc$libresoc.v:125517$4936
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:126895.5-126895.29"
+ attribute \src "libresoc.v:125518.5-125518.29"
switch \initial
- attribute \src "libresoc.v:126895.9-126895.17"
+ attribute \src "libresoc.v:125518.9-125518.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:126917.3-126927.6"
- process $proc$libresoc.v:126917$4993
+ attribute \src "libresoc.v:125540.3-125550.6"
+ process $proc$libresoc.v:125540$4937
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:126918.5-126918.29"
+ attribute \src "libresoc.v:125541.5-125541.29"
switch \initial
- attribute \src "libresoc.v:126918.9-126918.17"
+ attribute \src "libresoc.v:125541.9-125541.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:126928.3-126942.6"
- process $proc$libresoc.v:126928$4994
+ attribute \src "libresoc.v:125551.3-125565.6"
+ process $proc$libresoc.v:125551$4938
assign { } { }
assign { } { }
assign $0\sv_override[1:0] $1\sv_override[1:0]
- attribute \src "libresoc.v:126929.5-126929.29"
+ attribute \src "libresoc.v:125552.5-125552.29"
switch \initial
- attribute \src "libresoc.v:126929.9-126929.17"
+ attribute \src "libresoc.v:125552.9-125552.17"
case 1'1
case
end
sync always
update \sv_override $0\sv_override[1:0]
end
- attribute \src "libresoc.v:126943.3-126965.6"
- process $proc$libresoc.v:126943$4995
+ attribute \src "libresoc.v:125566.3-125588.6"
+ process $proc$libresoc.v:125566$4939
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:126944.5-126944.29"
+ attribute \src "libresoc.v:125567.5-125567.29"
switch \initial
- attribute \src "libresoc.v:126944.9-126944.17"
+ attribute \src "libresoc.v:125567.9-125567.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:126966.3-126976.6"
- process $proc$libresoc.v:126966$4996
+ attribute \src "libresoc.v:125589.3-125599.6"
+ process $proc$libresoc.v:125589$4940
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:126967.5-126967.29"
+ attribute \src "libresoc.v:125590.5-125590.29"
switch \initial
- attribute \src "libresoc.v:126967.9-126967.17"
+ attribute \src "libresoc.v:125590.9-125590.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:126977.3-126997.6"
- process $proc$libresoc.v:126977$4997
+ attribute \src "libresoc.v:125600.3-125620.6"
+ process $proc$libresoc.v:125600$4941
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:126978.5-126978.29"
+ attribute \src "libresoc.v:125601.5-125601.29"
switch \initial
- attribute \src "libresoc.v:126978.9-126978.17"
+ attribute \src "libresoc.v:125601.9-125601.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- attribute \src "libresoc.v:126998.3-127032.6"
- process $proc$libresoc.v:126998$4998
+ attribute \src "libresoc.v:125621.3-125655.6"
+ process $proc$libresoc.v:125621$4942
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:126999.5-126999.29"
+ attribute \src "libresoc.v:125622.5-125622.29"
switch \initial
- attribute \src "libresoc.v:126999.9-126999.17"
+ attribute \src "libresoc.v:125622.9-125622.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- connect \$1 $eq$libresoc.v:126887$4990_Y
- connect \$3 $eq$libresoc.v:126888$4991_Y
+ connect \$1 $eq$libresoc.v:125510$4934_Y
+ connect \$3 $eq$libresoc.v:125511$4935_Y
end
-attribute \src "libresoc.v:127037.1-127520.10"
+attribute \src "libresoc.v:125660.1-126143.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o"
attribute \generator "nMigen"
module \dec_o
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:127038.7-127038.20"
+ attribute \src "libresoc.v:125661.7-125661.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127407.3-127421.6"
+ attribute \src "libresoc.v:126030.3-126044.6"
wire width 5 $0\reg_o[4:0]
- attribute \src "libresoc.v:127422.3-127436.6"
+ attribute \src "libresoc.v:126045.3-126059.6"
wire $0\reg_o_ok[0:0]
- attribute \src "libresoc.v:127437.3-127447.6"
+ attribute \src "libresoc.v:126060.3-126070.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:127448.3-127463.6"
+ attribute \src "libresoc.v:126071.3-126086.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:127407.3-127421.6"
+ attribute \src "libresoc.v:126030.3-126044.6"
wire width 5 $1\reg_o[4:0]
- attribute \src "libresoc.v:127422.3-127436.6"
+ attribute \src "libresoc.v:126045.3-126059.6"
wire $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:127437.3-127447.6"
+ attribute \src "libresoc.v:126060.3-126070.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:127448.3-127463.6"
+ attribute \src "libresoc.v:126071.3-126086.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire width 3 $2\fast_o[2:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire $2\fast_o_ok[0:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire width 10 $2\spr_o[9:0]
- attribute \src "libresoc.v:127464.3-127480.6"
+ attribute \src "libresoc.v:126087.3-126103.6"
wire $2\spr_o_ok[0:0]
- attribute \src "libresoc.v:127448.3-127463.6"
+ attribute \src "libresoc.v:126071.3-126086.6"
wire width 10 $2\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire width 3 $3\fast_o[2:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire width 3 $4\fast_o[2:0]
- attribute \src "libresoc.v:127481.3-127519.6"
+ attribute \src "libresoc.v:126104.3-126142.6"
wire $4\fast_o_ok[0:0]
- attribute \src "libresoc.v:127396.17-127396.117"
- wire $eq$libresoc.v:127396$5000_Y
- attribute \src "libresoc.v:127397.17-127397.117"
- wire $eq$libresoc.v:127397$5001_Y
- attribute \src "libresoc.v:127398.17-127398.117"
- wire $eq$libresoc.v:127398$5002_Y
- attribute \src "libresoc.v:127399.17-127399.104"
- wire $not$libresoc.v:127399$5003_Y
+ attribute \src "libresoc.v:126019.17-126019.117"
+ wire $eq$libresoc.v:126019$4944_Y
+ attribute \src "libresoc.v:126020.17-126020.117"
+ wire $eq$libresoc.v:126020$4945_Y
+ attribute \src "libresoc.v:126021.17-126021.117"
+ wire $eq$libresoc.v:126021$4946_Y
+ attribute \src "libresoc.v:126022.17-126022.104"
+ wire $not$libresoc.v:126022$4947_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
wire width 3 output 7 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 8 \fast_o_ok
- attribute \src "libresoc.v:127038.7-127038.15"
+ attribute \src "libresoc.v:125661.7-125661.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \sprmap_spr_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
- cell $eq $eq$libresoc.v:127396$5000
+ cell $eq $eq$libresoc.v:126019$4944
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:127396$5000_Y
+ connect \Y $eq$libresoc.v:126019$4944_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
- cell $eq $eq$libresoc.v:127397$5001
+ cell $eq $eq$libresoc.v:126020$4945
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:127397$5001_Y
+ connect \Y $eq$libresoc.v:126020$4945_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
- cell $eq $eq$libresoc.v:127398$5002
+ cell $eq $eq$libresoc.v:126021$4946
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:127398$5002_Y
+ connect \Y $eq$libresoc.v:126021$4946_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360"
- cell $not $not$libresoc.v:127399$5003
+ cell $not $not$libresoc.v:126022$4947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:127399$5003_Y
+ connect \Y $not$libresoc.v:126022$4947_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:127400.16-127406.4"
+ attribute \src "libresoc.v:126023.16-126029.4"
cell \sprmap$174 \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:127038.7-127038.20"
- process $proc$libresoc.v:127038$5010
+ attribute \src "libresoc.v:125661.7-125661.20"
+ process $proc$libresoc.v:125661$4954
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127407.3-127421.6"
- process $proc$libresoc.v:127407$5004
+ attribute \src "libresoc.v:126030.3-126044.6"
+ process $proc$libresoc.v:126030$4948
assign { } { }
assign { } { }
assign $0\reg_o[4:0] $1\reg_o[4:0]
- attribute \src "libresoc.v:127408.5-127408.29"
+ attribute \src "libresoc.v:126031.5-126031.29"
switch \initial
- attribute \src "libresoc.v:127408.9-127408.17"
+ attribute \src "libresoc.v:126031.9-126031.17"
case 1'1
case
end
sync always
update \reg_o $0\reg_o[4:0]
end
- attribute \src "libresoc.v:127422.3-127436.6"
- process $proc$libresoc.v:127422$5005
+ attribute \src "libresoc.v:126045.3-126059.6"
+ process $proc$libresoc.v:126045$4949
assign { } { }
assign { } { }
assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:127423.5-127423.29"
+ attribute \src "libresoc.v:126046.5-126046.29"
switch \initial
- attribute \src "libresoc.v:127423.9-127423.17"
+ attribute \src "libresoc.v:126046.9-126046.17"
case 1'1
case
end
sync always
update \reg_o_ok $0\reg_o_ok[0:0]
end
- attribute \src "libresoc.v:127437.3-127447.6"
- process $proc$libresoc.v:127437$5006
+ attribute \src "libresoc.v:126060.3-126070.6"
+ process $proc$libresoc.v:126060$4950
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:127438.5-127438.29"
+ attribute \src "libresoc.v:126061.5-126061.29"
switch \initial
- attribute \src "libresoc.v:127438.9-127438.17"
+ attribute \src "libresoc.v:126061.9-126061.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:127448.3-127463.6"
- process $proc$libresoc.v:127448$5007
+ attribute \src "libresoc.v:126071.3-126086.6"
+ process $proc$libresoc.v:126071$4951
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:127449.5-127449.29"
+ attribute \src "libresoc.v:126072.5-126072.29"
switch \initial
- attribute \src "libresoc.v:127449.9-127449.17"
+ attribute \src "libresoc.v:126072.9-126072.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:127464.3-127480.6"
- process $proc$libresoc.v:127464$5008
+ attribute \src "libresoc.v:126087.3-126103.6"
+ process $proc$libresoc.v:126087$4952
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:127465.5-127465.29"
+ attribute \src "libresoc.v:126088.5-126088.29"
switch \initial
- attribute \src "libresoc.v:127465.9-127465.17"
+ attribute \src "libresoc.v:126088.9-126088.17"
case 1'1
case
end
update \spr_o $0\spr_o[9:0]
update \spr_o_ok $0\spr_o_ok[0:0]
end
- attribute \src "libresoc.v:127481.3-127519.6"
- process $proc$libresoc.v:127481$5009
+ attribute \src "libresoc.v:126104.3-126142.6"
+ process $proc$libresoc.v:126104$4953
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $3\fast_o[2:0]
assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:127482.5-127482.29"
+ attribute \src "libresoc.v:126105.5-126105.29"
switch \initial
- attribute \src "libresoc.v:127482.9-127482.17"
+ attribute \src "libresoc.v:126105.9-126105.17"
case 1'1
case
end
update \fast_o $0\fast_o[2:0]
update \fast_o_ok $0\fast_o_ok[0:0]
end
- connect \$1 $eq$libresoc.v:127396$5000_Y
- connect \$3 $eq$libresoc.v:127397$5001_Y
- connect \$5 $eq$libresoc.v:127398$5002_Y
- connect \$7 $not$libresoc.v:127399$5003_Y
+ connect \$1 $eq$libresoc.v:126019$4944_Y
+ connect \$3 $eq$libresoc.v:126020$4945_Y
+ connect \$5 $eq$libresoc.v:126021$4946_Y
+ connect \$7 $not$libresoc.v:126022$4947_Y
end
-attribute \src "libresoc.v:127524.1-127691.10"
+attribute \src "libresoc.v:126147.1-126314.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2"
attribute \generator "nMigen"
module \dec_o2
- attribute \src "libresoc.v:127651.3-127670.6"
+ attribute \src "libresoc.v:126274.3-126293.6"
wire width 3 $0\fast_o2[2:0]
- attribute \src "libresoc.v:127671.3-127690.6"
+ attribute \src "libresoc.v:126294.3-126313.6"
wire $0\fast_o2_ok[0:0]
- attribute \src "libresoc.v:127525.7-127525.20"
+ attribute \src "libresoc.v:126148.7-126148.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127631.3-127640.6"
+ attribute \src "libresoc.v:126254.3-126263.6"
wire width 5 $0\reg_o2[4:0]
- attribute \src "libresoc.v:127641.3-127650.6"
+ attribute \src "libresoc.v:126264.3-126273.6"
wire $0\reg_o2_ok[0:0]
- attribute \src "libresoc.v:127651.3-127670.6"
+ attribute \src "libresoc.v:126274.3-126293.6"
wire width 3 $1\fast_o2[2:0]
- attribute \src "libresoc.v:127671.3-127690.6"
+ attribute \src "libresoc.v:126294.3-126313.6"
wire $1\fast_o2_ok[0:0]
- attribute \src "libresoc.v:127631.3-127640.6"
+ attribute \src "libresoc.v:126254.3-126263.6"
wire width 5 $1\reg_o2[4:0]
- attribute \src "libresoc.v:127641.3-127650.6"
+ attribute \src "libresoc.v:126264.3-126273.6"
wire $1\reg_o2_ok[0:0]
- attribute \src "libresoc.v:127651.3-127670.6"
+ attribute \src "libresoc.v:126274.3-126293.6"
wire width 3 $2\fast_o2[2:0]
- attribute \src "libresoc.v:127671.3-127690.6"
+ attribute \src "libresoc.v:126294.3-126313.6"
wire $2\fast_o2_ok[0:0]
- attribute \src "libresoc.v:127629.17-127629.108"
- wire $eq$libresoc.v:127629$5011_Y
- attribute \src "libresoc.v:127630.17-127630.108"
- wire $eq$libresoc.v:127630$5012_Y
+ attribute \src "libresoc.v:126252.17-126252.108"
+ wire $eq$libresoc.v:126252$4955_Y
+ attribute \src "libresoc.v:126253.17-126253.108"
+ wire $eq$libresoc.v:126253$4956_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406"
wire width 3 output 4 \fast_o2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 5 \fast_o2_ok
- attribute \src "libresoc.v:127525.7-127525.15"
+ attribute \src "libresoc.v:126148.7-126148.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 2 input 6 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406"
- cell $eq $eq$libresoc.v:127629$5011
+ cell $eq $eq$libresoc.v:126252$4955
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd
connect \B 2'01
- connect \Y $eq$libresoc.v:127629$5011_Y
+ connect \Y $eq$libresoc.v:126252$4955_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406"
- cell $eq $eq$libresoc.v:127630$5012
+ cell $eq $eq$libresoc.v:126253$4956
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd
connect \B 2'01
- connect \Y $eq$libresoc.v:127630$5012_Y
+ connect \Y $eq$libresoc.v:126253$4956_Y
end
- attribute \src "libresoc.v:127525.7-127525.20"
- process $proc$libresoc.v:127525$5017
+ attribute \src "libresoc.v:126148.7-126148.20"
+ process $proc$libresoc.v:126148$4961
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127631.3-127640.6"
- process $proc$libresoc.v:127631$5013
+ attribute \src "libresoc.v:126254.3-126263.6"
+ process $proc$libresoc.v:126254$4957
assign { } { }
assign { } { }
assign $0\reg_o2[4:0] $1\reg_o2[4:0]
- attribute \src "libresoc.v:127632.5-127632.29"
+ attribute \src "libresoc.v:126255.5-126255.29"
switch \initial
- attribute \src "libresoc.v:127632.9-127632.17"
+ attribute \src "libresoc.v:126255.9-126255.17"
case 1'1
case
end
sync always
update \reg_o2 $0\reg_o2[4:0]
end
- attribute \src "libresoc.v:127641.3-127650.6"
- process $proc$libresoc.v:127641$5014
+ attribute \src "libresoc.v:126264.3-126273.6"
+ process $proc$libresoc.v:126264$4958
assign { } { }
assign { } { }
assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0]
- attribute \src "libresoc.v:127642.5-127642.29"
+ attribute \src "libresoc.v:126265.5-126265.29"
switch \initial
- attribute \src "libresoc.v:127642.9-127642.17"
+ attribute \src "libresoc.v:126265.9-126265.17"
case 1'1
case
end
sync always
update \reg_o2_ok $0\reg_o2_ok[0:0]
end
- attribute \src "libresoc.v:127651.3-127670.6"
- process $proc$libresoc.v:127651$5015
+ attribute \src "libresoc.v:126274.3-126293.6"
+ process $proc$libresoc.v:126274$4959
assign { } { }
assign { } { }
assign $0\fast_o2[2:0] $1\fast_o2[2:0]
- attribute \src "libresoc.v:127652.5-127652.29"
+ attribute \src "libresoc.v:126275.5-126275.29"
switch \initial
- attribute \src "libresoc.v:127652.9-127652.17"
+ attribute \src "libresoc.v:126275.9-126275.17"
case 1'1
case
end
sync always
update \fast_o2 $0\fast_o2[2:0]
end
- attribute \src "libresoc.v:127671.3-127690.6"
- process $proc$libresoc.v:127671$5016
+ attribute \src "libresoc.v:126294.3-126313.6"
+ process $proc$libresoc.v:126294$4960
assign { } { }
assign { } { }
assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0]
- attribute \src "libresoc.v:127672.5-127672.29"
+ attribute \src "libresoc.v:126295.5-126295.29"
switch \initial
- attribute \src "libresoc.v:127672.9-127672.17"
+ attribute \src "libresoc.v:126295.9-126295.17"
case 1'1
case
end
sync always
update \fast_o2_ok $0\fast_o2_ok[0:0]
end
- connect \$1 $eq$libresoc.v:127629$5011_Y
- connect \$3 $eq$libresoc.v:127630$5012_Y
+ connect \$1 $eq$libresoc.v:126252$4955_Y
+ connect \$3 $eq$libresoc.v:126253$4956_Y
end
-attribute \src "libresoc.v:127695.1-127829.10"
+attribute \src "libresoc.v:126318.1-126452.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe"
attribute \generator "nMigen"
module \dec_oe
- attribute \src "libresoc.v:127696.7-127696.20"
+ attribute \src "libresoc.v:126319.7-126319.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127787.3-127807.6"
+ attribute \src "libresoc.v:126410.3-126430.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:127808.3-127828.6"
+ attribute \src "libresoc.v:126431.3-126451.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:127787.3-127807.6"
+ attribute \src "libresoc.v:126410.3-126430.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:127808.3-127828.6"
+ attribute \src "libresoc.v:126431.3-126451.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:127787.3-127807.6"
+ attribute \src "libresoc.v:126410.3-126430.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:127808.3-127828.6"
+ attribute \src "libresoc.v:126431.3-126451.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \ALU_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \ALU_internal_op
- attribute \src "libresoc.v:127696.7-127696.15"
+ attribute \src "libresoc.v:126319.7-126319.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:127696.7-127696.20"
- process $proc$libresoc.v:127696$5020
+ attribute \src "libresoc.v:126319.7-126319.20"
+ process $proc$libresoc.v:126319$4964
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127787.3-127807.6"
- process $proc$libresoc.v:127787$5018
+ attribute \src "libresoc.v:126410.3-126430.6"
+ process $proc$libresoc.v:126410$4962
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:127788.5-127788.29"
+ attribute \src "libresoc.v:126411.5-126411.29"
switch \initial
- attribute \src "libresoc.v:127788.9-127788.17"
+ attribute \src "libresoc.v:126411.9-126411.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:127808.3-127828.6"
- process $proc$libresoc.v:127808$5019
+ attribute \src "libresoc.v:126431.3-126451.6"
+ process $proc$libresoc.v:126431$4963
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:127809.5-127809.29"
+ attribute \src "libresoc.v:126432.5-126432.29"
switch \initial
- attribute \src "libresoc.v:127809.9-127809.17"
+ attribute \src "libresoc.v:126432.9-126432.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:127833.1-127965.10"
+attribute \src "libresoc.v:126456.1-126588.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe"
attribute \generator "nMigen"
module \dec_oe$140
- attribute \src "libresoc.v:127834.7-127834.20"
+ attribute \src "libresoc.v:126457.7-126457.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:127923.3-127943.6"
+ attribute \src "libresoc.v:126546.3-126566.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:127944.3-127964.6"
+ attribute \src "libresoc.v:126567.3-126587.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:127923.3-127943.6"
+ attribute \src "libresoc.v:126546.3-126566.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:127944.3-127964.6"
+ attribute \src "libresoc.v:126567.3-126587.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:127923.3-127943.6"
+ attribute \src "libresoc.v:126546.3-126566.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:127944.3-127964.6"
+ attribute \src "libresoc.v:126567.3-126587.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 2 \CR_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \CR_internal_op
- attribute \src "libresoc.v:127834.7-127834.15"
+ attribute \src "libresoc.v:126457.7-126457.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:127834.7-127834.20"
- process $proc$libresoc.v:127834$5023
+ attribute \src "libresoc.v:126457.7-126457.20"
+ process $proc$libresoc.v:126457$4967
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:127923.3-127943.6"
- process $proc$libresoc.v:127923$5021
+ attribute \src "libresoc.v:126546.3-126566.6"
+ process $proc$libresoc.v:126546$4965
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:127924.5-127924.29"
+ attribute \src "libresoc.v:126547.5-126547.29"
switch \initial
- attribute \src "libresoc.v:127924.9-127924.17"
+ attribute \src "libresoc.v:126547.9-126547.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:127944.3-127964.6"
- process $proc$libresoc.v:127944$5022
+ attribute \src "libresoc.v:126567.3-126587.6"
+ process $proc$libresoc.v:126567$4966
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:127945.5-127945.29"
+ attribute \src "libresoc.v:126568.5-126568.29"
switch \initial
- attribute \src "libresoc.v:127945.9-127945.17"
+ attribute \src "libresoc.v:126568.9-126568.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:127969.1-128101.10"
+attribute \src "libresoc.v:126592.1-126724.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe"
attribute \generator "nMigen"
module \dec_oe$143
- attribute \src "libresoc.v:127970.7-127970.20"
+ attribute \src "libresoc.v:126593.7-126593.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128059.3-128079.6"
+ attribute \src "libresoc.v:126682.3-126702.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128080.3-128100.6"
+ attribute \src "libresoc.v:126703.3-126723.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128059.3-128079.6"
+ attribute \src "libresoc.v:126682.3-126702.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128080.3-128100.6"
+ attribute \src "libresoc.v:126703.3-126723.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128059.3-128079.6"
+ attribute \src "libresoc.v:126682.3-126702.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128080.3-128100.6"
+ attribute \src "libresoc.v:126703.3-126723.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 2 \BRANCH_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \BRANCH_internal_op
- attribute \src "libresoc.v:127970.7-127970.15"
+ attribute \src "libresoc.v:126593.7-126593.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:127970.7-127970.20"
- process $proc$libresoc.v:127970$5026
+ attribute \src "libresoc.v:126593.7-126593.20"
+ process $proc$libresoc.v:126593$4970
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128059.3-128079.6"
- process $proc$libresoc.v:128059$5024
+ attribute \src "libresoc.v:126682.3-126702.6"
+ process $proc$libresoc.v:126682$4968
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128060.5-128060.29"
+ attribute \src "libresoc.v:126683.5-126683.29"
switch \initial
- attribute \src "libresoc.v:128060.9-128060.17"
+ attribute \src "libresoc.v:126683.9-126683.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128080.3-128100.6"
- process $proc$libresoc.v:128080$5025
+ attribute \src "libresoc.v:126703.3-126723.6"
+ process $proc$libresoc.v:126703$4969
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128081.5-128081.29"
+ attribute \src "libresoc.v:126704.5-126704.29"
switch \initial
- attribute \src "libresoc.v:128081.9-128081.17"
+ attribute \src "libresoc.v:126704.9-126704.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128105.1-128239.10"
+attribute \src "libresoc.v:126728.1-126862.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe"
attribute \generator "nMigen"
module \dec_oe$147
- attribute \src "libresoc.v:128106.7-128106.20"
+ attribute \src "libresoc.v:126729.7-126729.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128197.3-128217.6"
+ attribute \src "libresoc.v:126820.3-126840.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128218.3-128238.6"
+ attribute \src "libresoc.v:126841.3-126861.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128197.3-128217.6"
+ attribute \src "libresoc.v:126820.3-126840.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128218.3-128238.6"
+ attribute \src "libresoc.v:126841.3-126861.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128197.3-128217.6"
+ attribute \src "libresoc.v:126820.3-126840.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128218.3-128238.6"
+ attribute \src "libresoc.v:126841.3-126861.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \LOGICAL_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \LOGICAL_internal_op
- attribute \src "libresoc.v:128106.7-128106.15"
+ attribute \src "libresoc.v:126729.7-126729.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128106.7-128106.20"
- process $proc$libresoc.v:128106$5029
+ attribute \src "libresoc.v:126729.7-126729.20"
+ process $proc$libresoc.v:126729$4973
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128197.3-128217.6"
- process $proc$libresoc.v:128197$5027
+ attribute \src "libresoc.v:126820.3-126840.6"
+ process $proc$libresoc.v:126820$4971
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128198.5-128198.29"
+ attribute \src "libresoc.v:126821.5-126821.29"
switch \initial
- attribute \src "libresoc.v:128198.9-128198.17"
+ attribute \src "libresoc.v:126821.9-126821.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128218.3-128238.6"
- process $proc$libresoc.v:128218$5028
+ attribute \src "libresoc.v:126841.3-126861.6"
+ process $proc$libresoc.v:126841$4972
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128219.5-128219.29"
+ attribute \src "libresoc.v:126842.5-126842.29"
switch \initial
- attribute \src "libresoc.v:128219.9-128219.17"
+ attribute \src "libresoc.v:126842.9-126842.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128243.1-128375.10"
+attribute \src "libresoc.v:126866.1-126998.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe"
attribute \generator "nMigen"
module \dec_oe$152
- attribute \src "libresoc.v:128244.7-128244.20"
+ attribute \src "libresoc.v:126867.7-126867.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128333.3-128353.6"
+ attribute \src "libresoc.v:126956.3-126976.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128354.3-128374.6"
+ attribute \src "libresoc.v:126977.3-126997.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128333.3-128353.6"
+ attribute \src "libresoc.v:126956.3-126976.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128354.3-128374.6"
+ attribute \src "libresoc.v:126977.3-126997.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128333.3-128353.6"
+ attribute \src "libresoc.v:126956.3-126976.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128354.3-128374.6"
+ attribute \src "libresoc.v:126977.3-126997.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 2 \SPR_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \SPR_internal_op
- attribute \src "libresoc.v:128244.7-128244.15"
+ attribute \src "libresoc.v:126867.7-126867.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 3 \sel_in
- attribute \src "libresoc.v:128244.7-128244.20"
- process $proc$libresoc.v:128244$5032
+ attribute \src "libresoc.v:126867.7-126867.20"
+ process $proc$libresoc.v:126867$4976
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128333.3-128353.6"
- process $proc$libresoc.v:128333$5030
+ attribute \src "libresoc.v:126956.3-126976.6"
+ process $proc$libresoc.v:126956$4974
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128334.5-128334.29"
+ attribute \src "libresoc.v:126957.5-126957.29"
switch \initial
- attribute \src "libresoc.v:128334.9-128334.17"
+ attribute \src "libresoc.v:126957.9-126957.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128354.3-128374.6"
- process $proc$libresoc.v:128354$5031
+ attribute \src "libresoc.v:126977.3-126997.6"
+ process $proc$libresoc.v:126977$4975
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128355.5-128355.29"
+ attribute \src "libresoc.v:126978.5-126978.29"
switch \initial
- attribute \src "libresoc.v:128355.9-128355.17"
+ attribute \src "libresoc.v:126978.9-126978.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128379.1-128513.10"
+attribute \src "libresoc.v:127002.1-127136.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe"
attribute \generator "nMigen"
module \dec_oe$155
- attribute \src "libresoc.v:128380.7-128380.20"
+ attribute \src "libresoc.v:127003.7-127003.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128471.3-128491.6"
+ attribute \src "libresoc.v:127094.3-127114.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128492.3-128512.6"
+ attribute \src "libresoc.v:127115.3-127135.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128471.3-128491.6"
+ attribute \src "libresoc.v:127094.3-127114.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128492.3-128512.6"
+ attribute \src "libresoc.v:127115.3-127135.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128471.3-128491.6"
+ attribute \src "libresoc.v:127094.3-127114.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128492.3-128512.6"
+ attribute \src "libresoc.v:127115.3-127135.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \DIV_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \DIV_internal_op
- attribute \src "libresoc.v:128380.7-128380.15"
+ attribute \src "libresoc.v:127003.7-127003.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128380.7-128380.20"
- process $proc$libresoc.v:128380$5035
+ attribute \src "libresoc.v:127003.7-127003.20"
+ process $proc$libresoc.v:127003$4979
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128471.3-128491.6"
- process $proc$libresoc.v:128471$5033
+ attribute \src "libresoc.v:127094.3-127114.6"
+ process $proc$libresoc.v:127094$4977
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128472.5-128472.29"
+ attribute \src "libresoc.v:127095.5-127095.29"
switch \initial
- attribute \src "libresoc.v:128472.9-128472.17"
+ attribute \src "libresoc.v:127095.9-127095.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128492.3-128512.6"
- process $proc$libresoc.v:128492$5034
+ attribute \src "libresoc.v:127115.3-127135.6"
+ process $proc$libresoc.v:127115$4978
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128493.5-128493.29"
+ attribute \src "libresoc.v:127116.5-127116.29"
switch \initial
- attribute \src "libresoc.v:128493.9-128493.17"
+ attribute \src "libresoc.v:127116.9-127116.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128517.1-128651.10"
+attribute \src "libresoc.v:127140.1-127274.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe"
attribute \generator "nMigen"
module \dec_oe$160
- attribute \src "libresoc.v:128518.7-128518.20"
+ attribute \src "libresoc.v:127141.7-127141.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128609.3-128629.6"
+ attribute \src "libresoc.v:127232.3-127252.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128630.3-128650.6"
+ attribute \src "libresoc.v:127253.3-127273.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128609.3-128629.6"
+ attribute \src "libresoc.v:127232.3-127252.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128630.3-128650.6"
+ attribute \src "libresoc.v:127253.3-127273.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128609.3-128629.6"
+ attribute \src "libresoc.v:127232.3-127252.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128630.3-128650.6"
+ attribute \src "libresoc.v:127253.3-127273.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \MUL_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \MUL_internal_op
- attribute \src "libresoc.v:128518.7-128518.15"
+ attribute \src "libresoc.v:127141.7-127141.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128518.7-128518.20"
- process $proc$libresoc.v:128518$5038
+ attribute \src "libresoc.v:127141.7-127141.20"
+ process $proc$libresoc.v:127141$4982
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128609.3-128629.6"
- process $proc$libresoc.v:128609$5036
+ attribute \src "libresoc.v:127232.3-127252.6"
+ process $proc$libresoc.v:127232$4980
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128610.5-128610.29"
+ attribute \src "libresoc.v:127233.5-127233.29"
switch \initial
- attribute \src "libresoc.v:128610.9-128610.17"
+ attribute \src "libresoc.v:127233.9-127233.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128630.3-128650.6"
- process $proc$libresoc.v:128630$5037
+ attribute \src "libresoc.v:127253.3-127273.6"
+ process $proc$libresoc.v:127253$4981
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128631.5-128631.29"
+ attribute \src "libresoc.v:127254.5-127254.29"
switch \initial
- attribute \src "libresoc.v:128631.9-128631.17"
+ attribute \src "libresoc.v:127254.9-127254.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128655.1-128789.10"
+attribute \src "libresoc.v:127278.1-127412.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe"
attribute \generator "nMigen"
module \dec_oe$164
- attribute \src "libresoc.v:128656.7-128656.20"
+ attribute \src "libresoc.v:127279.7-127279.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128747.3-128767.6"
+ attribute \src "libresoc.v:127370.3-127390.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128768.3-128788.6"
+ attribute \src "libresoc.v:127391.3-127411.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128747.3-128767.6"
+ attribute \src "libresoc.v:127370.3-127390.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128768.3-128788.6"
+ attribute \src "libresoc.v:127391.3-127411.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128747.3-128767.6"
+ attribute \src "libresoc.v:127370.3-127390.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128768.3-128788.6"
+ attribute \src "libresoc.v:127391.3-127411.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \SHIFT_ROT_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \SHIFT_ROT_internal_op
- attribute \src "libresoc.v:128656.7-128656.15"
+ attribute \src "libresoc.v:127279.7-127279.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128656.7-128656.20"
- process $proc$libresoc.v:128656$5041
+ attribute \src "libresoc.v:127279.7-127279.20"
+ process $proc$libresoc.v:127279$4985
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128747.3-128767.6"
- process $proc$libresoc.v:128747$5039
+ attribute \src "libresoc.v:127370.3-127390.6"
+ process $proc$libresoc.v:127370$4983
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128748.5-128748.29"
+ attribute \src "libresoc.v:127371.5-127371.29"
switch \initial
- attribute \src "libresoc.v:128748.9-128748.17"
+ attribute \src "libresoc.v:127371.9-127371.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128768.3-128788.6"
- process $proc$libresoc.v:128768$5040
+ attribute \src "libresoc.v:127391.3-127411.6"
+ process $proc$libresoc.v:127391$4984
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128769.5-128769.29"
+ attribute \src "libresoc.v:127392.5-127392.29"
switch \initial
- attribute \src "libresoc.v:128769.9-128769.17"
+ attribute \src "libresoc.v:127392.9-127392.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128793.1-128927.10"
+attribute \src "libresoc.v:127416.1-127550.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe"
attribute \generator "nMigen"
module \dec_oe$168
- attribute \src "libresoc.v:128794.7-128794.20"
+ attribute \src "libresoc.v:127417.7-127417.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:128885.3-128905.6"
+ attribute \src "libresoc.v:127508.3-127528.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:128906.3-128926.6"
+ attribute \src "libresoc.v:127529.3-127549.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:128885.3-128905.6"
+ attribute \src "libresoc.v:127508.3-127528.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:128906.3-128926.6"
+ attribute \src "libresoc.v:127529.3-127549.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:128885.3-128905.6"
+ attribute \src "libresoc.v:127508.3-127528.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:128906.3-128926.6"
+ attribute \src "libresoc.v:127529.3-127549.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \LDST_OE
attribute \enum_value_1001011 "OP_TLBIE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187"
wire width 7 input 1 \LDST_internal_op
- attribute \src "libresoc.v:128794.7-128794.15"
+ attribute \src "libresoc.v:127417.7-127417.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \oe
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128794.7-128794.20"
- process $proc$libresoc.v:128794$5044
+ attribute \src "libresoc.v:127417.7-127417.20"
+ process $proc$libresoc.v:127417$4988
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:128885.3-128905.6"
- process $proc$libresoc.v:128885$5042
+ attribute \src "libresoc.v:127508.3-127528.6"
+ process $proc$libresoc.v:127508$4986
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:128886.5-128886.29"
+ attribute \src "libresoc.v:127509.5-127509.29"
switch \initial
- attribute \src "libresoc.v:128886.9-128886.17"
+ attribute \src "libresoc.v:127509.9-127509.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:128906.3-128926.6"
- process $proc$libresoc.v:128906$5043
+ attribute \src "libresoc.v:127529.3-127549.6"
+ process $proc$libresoc.v:127529$4987
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:128907.5-128907.29"
+ attribute \src "libresoc.v:127530.5-127530.29"
switch \initial
- attribute \src "libresoc.v:128907.9-128907.17"
+ attribute \src "libresoc.v:127530.9-127530.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:128931.1-129065.10"
+attribute \src "libresoc.v:127554.1-127688.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe"
attribute \generator "nMigen"
module \dec_oe$173
- attribute \src "libresoc.v:128932.7-128932.20"
+ attribute \src "libresoc.v:127555.7-127555.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129023.3-129043.6"
+ attribute \src "libresoc.v:127646.3-127666.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:129044.3-129064.6"
+ attribute \src "libresoc.v:127667.3-127687.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:129023.3-129043.6"
+ attribute \src "libresoc.v:127646.3-127666.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:129044.3-129064.6"
+ attribute \src "libresoc.v:127667.3-127687.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:129023.3-129043.6"
+ attribute \src "libresoc.v:127646.3-127666.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:129044.3-129064.6"
+ attribute \src "libresoc.v:127667.3-127687.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 4 \OE
- attribute \src "libresoc.v:128932.7-128932.15"
+ attribute \src "libresoc.v:127555.7-127555.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:128932.7-128932.20"
- process $proc$libresoc.v:128932$5047
+ attribute \src "libresoc.v:127555.7-127555.20"
+ process $proc$libresoc.v:127555$4991
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129023.3-129043.6"
- process $proc$libresoc.v:129023$5045
+ attribute \src "libresoc.v:127646.3-127666.6"
+ process $proc$libresoc.v:127646$4989
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:129024.5-129024.29"
+ attribute \src "libresoc.v:127647.5-127647.29"
switch \initial
- attribute \src "libresoc.v:129024.9-129024.17"
+ attribute \src "libresoc.v:127647.9-127647.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:129044.3-129064.6"
- process $proc$libresoc.v:129044$5046
+ attribute \src "libresoc.v:127667.3-127687.6"
+ process $proc$libresoc.v:127667$4990
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:129045.5-129045.29"
+ attribute \src "libresoc.v:127668.5-127668.29"
switch \initial
- attribute \src "libresoc.v:129045.9-129045.17"
+ attribute \src "libresoc.v:127668.9-127668.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:129069.1-129123.10"
+attribute \src "libresoc.v:127692.1-127746.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc"
attribute \generator "nMigen"
module \dec_rc
- attribute \src "libresoc.v:129070.7-129070.20"
+ attribute \src "libresoc.v:127693.7-127693.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129085.3-129103.6"
+ attribute \src "libresoc.v:127708.3-127726.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129104.3-129122.6"
+ attribute \src "libresoc.v:127727.3-127745.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129085.3-129103.6"
+ attribute \src "libresoc.v:127708.3-127726.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129104.3-129122.6"
+ attribute \src "libresoc.v:127727.3-127745.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \ALU_Rc
- attribute \src "libresoc.v:129070.7-129070.15"
+ attribute \src "libresoc.v:127693.7-127693.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129070.7-129070.20"
- process $proc$libresoc.v:129070$5050
+ attribute \src "libresoc.v:127693.7-127693.20"
+ process $proc$libresoc.v:127693$4994
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129085.3-129103.6"
- process $proc$libresoc.v:129085$5048
+ attribute \src "libresoc.v:127708.3-127726.6"
+ process $proc$libresoc.v:127708$4992
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129086.5-129086.29"
+ attribute \src "libresoc.v:127709.5-127709.29"
switch \initial
- attribute \src "libresoc.v:129086.9-129086.17"
+ attribute \src "libresoc.v:127709.9-127709.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129104.3-129122.6"
- process $proc$libresoc.v:129104$5049
+ attribute \src "libresoc.v:127727.3-127745.6"
+ process $proc$libresoc.v:127727$4993
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129105.5-129105.29"
+ attribute \src "libresoc.v:127728.5-127728.29"
switch \initial
- attribute \src "libresoc.v:129105.9-129105.17"
+ attribute \src "libresoc.v:127728.9-127728.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129127.1-129179.10"
+attribute \src "libresoc.v:127750.1-127802.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc"
attribute \generator "nMigen"
module \dec_rc$139
- attribute \src "libresoc.v:129128.7-129128.20"
+ attribute \src "libresoc.v:127751.7-127751.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129141.3-129159.6"
+ attribute \src "libresoc.v:127764.3-127782.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129160.3-129178.6"
+ attribute \src "libresoc.v:127783.3-127801.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129141.3-129159.6"
+ attribute \src "libresoc.v:127764.3-127782.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129160.3-129178.6"
+ attribute \src "libresoc.v:127783.3-127801.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 1 \CR_Rc
- attribute \src "libresoc.v:129128.7-129128.15"
+ attribute \src "libresoc.v:127751.7-127751.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:129128.7-129128.20"
- process $proc$libresoc.v:129128$5053
+ attribute \src "libresoc.v:127751.7-127751.20"
+ process $proc$libresoc.v:127751$4997
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129141.3-129159.6"
- process $proc$libresoc.v:129141$5051
+ attribute \src "libresoc.v:127764.3-127782.6"
+ process $proc$libresoc.v:127764$4995
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129142.5-129142.29"
+ attribute \src "libresoc.v:127765.5-127765.29"
switch \initial
- attribute \src "libresoc.v:129142.9-129142.17"
+ attribute \src "libresoc.v:127765.9-127765.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129160.3-129178.6"
- process $proc$libresoc.v:129160$5052
+ attribute \src "libresoc.v:127783.3-127801.6"
+ process $proc$libresoc.v:127783$4996
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129161.5-129161.29"
+ attribute \src "libresoc.v:127784.5-127784.29"
switch \initial
- attribute \src "libresoc.v:129161.9-129161.17"
+ attribute \src "libresoc.v:127784.9-127784.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129183.1-129235.10"
+attribute \src "libresoc.v:127806.1-127858.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc"
attribute \generator "nMigen"
module \dec_rc$142
- attribute \src "libresoc.v:129184.7-129184.20"
+ attribute \src "libresoc.v:127807.7-127807.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129197.3-129215.6"
+ attribute \src "libresoc.v:127820.3-127838.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129216.3-129234.6"
+ attribute \src "libresoc.v:127839.3-127857.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129197.3-129215.6"
+ attribute \src "libresoc.v:127820.3-127838.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129216.3-129234.6"
+ attribute \src "libresoc.v:127839.3-127857.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 1 \BRANCH_Rc
- attribute \src "libresoc.v:129184.7-129184.15"
+ attribute \src "libresoc.v:127807.7-127807.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:129184.7-129184.20"
- process $proc$libresoc.v:129184$5056
+ attribute \src "libresoc.v:127807.7-127807.20"
+ process $proc$libresoc.v:127807$5000
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129197.3-129215.6"
- process $proc$libresoc.v:129197$5054
+ attribute \src "libresoc.v:127820.3-127838.6"
+ process $proc$libresoc.v:127820$4998
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129198.5-129198.29"
+ attribute \src "libresoc.v:127821.5-127821.29"
switch \initial
- attribute \src "libresoc.v:129198.9-129198.17"
+ attribute \src "libresoc.v:127821.9-127821.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129216.3-129234.6"
- process $proc$libresoc.v:129216$5055
+ attribute \src "libresoc.v:127839.3-127857.6"
+ process $proc$libresoc.v:127839$4999
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129217.5-129217.29"
+ attribute \src "libresoc.v:127840.5-127840.29"
switch \initial
- attribute \src "libresoc.v:129217.9-129217.17"
+ attribute \src "libresoc.v:127840.9-127840.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129239.1-129293.10"
+attribute \src "libresoc.v:127862.1-127916.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc"
attribute \generator "nMigen"
module \dec_rc$146
- attribute \src "libresoc.v:129240.7-129240.20"
+ attribute \src "libresoc.v:127863.7-127863.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129255.3-129273.6"
+ attribute \src "libresoc.v:127878.3-127896.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129274.3-129292.6"
+ attribute \src "libresoc.v:127897.3-127915.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129255.3-129273.6"
+ attribute \src "libresoc.v:127878.3-127896.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129274.3-129292.6"
+ attribute \src "libresoc.v:127897.3-127915.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \LOGICAL_Rc
- attribute \src "libresoc.v:129240.7-129240.15"
+ attribute \src "libresoc.v:127863.7-127863.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129240.7-129240.20"
- process $proc$libresoc.v:129240$5059
+ attribute \src "libresoc.v:127863.7-127863.20"
+ process $proc$libresoc.v:127863$5003
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129255.3-129273.6"
- process $proc$libresoc.v:129255$5057
+ attribute \src "libresoc.v:127878.3-127896.6"
+ process $proc$libresoc.v:127878$5001
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129256.5-129256.29"
+ attribute \src "libresoc.v:127879.5-127879.29"
switch \initial
- attribute \src "libresoc.v:129256.9-129256.17"
+ attribute \src "libresoc.v:127879.9-127879.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129274.3-129292.6"
- process $proc$libresoc.v:129274$5058
+ attribute \src "libresoc.v:127897.3-127915.6"
+ process $proc$libresoc.v:127897$5002
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129275.5-129275.29"
+ attribute \src "libresoc.v:127898.5-127898.29"
switch \initial
- attribute \src "libresoc.v:129275.9-129275.17"
+ attribute \src "libresoc.v:127898.9-127898.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129297.1-129349.10"
+attribute \src "libresoc.v:127920.1-127972.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc"
attribute \generator "nMigen"
module \dec_rc$151
- attribute \src "libresoc.v:129298.7-129298.20"
+ attribute \src "libresoc.v:127921.7-127921.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129311.3-129329.6"
+ attribute \src "libresoc.v:127934.3-127952.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129330.3-129348.6"
+ attribute \src "libresoc.v:127953.3-127971.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129311.3-129329.6"
+ attribute \src "libresoc.v:127934.3-127952.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129330.3-129348.6"
+ attribute \src "libresoc.v:127953.3-127971.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 1 \SPR_Rc
- attribute \src "libresoc.v:129298.7-129298.15"
+ attribute \src "libresoc.v:127921.7-127921.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 2 \sel_in
- attribute \src "libresoc.v:129298.7-129298.20"
- process $proc$libresoc.v:129298$5062
+ attribute \src "libresoc.v:127921.7-127921.20"
+ process $proc$libresoc.v:127921$5006
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129311.3-129329.6"
- process $proc$libresoc.v:129311$5060
+ attribute \src "libresoc.v:127934.3-127952.6"
+ process $proc$libresoc.v:127934$5004
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129312.5-129312.29"
+ attribute \src "libresoc.v:127935.5-127935.29"
switch \initial
- attribute \src "libresoc.v:129312.9-129312.17"
+ attribute \src "libresoc.v:127935.9-127935.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129330.3-129348.6"
- process $proc$libresoc.v:129330$5061
+ attribute \src "libresoc.v:127953.3-127971.6"
+ process $proc$libresoc.v:127953$5005
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129331.5-129331.29"
+ attribute \src "libresoc.v:127954.5-127954.29"
switch \initial
- attribute \src "libresoc.v:129331.9-129331.17"
+ attribute \src "libresoc.v:127954.9-127954.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129353.1-129407.10"
+attribute \src "libresoc.v:127976.1-128030.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc"
attribute \generator "nMigen"
module \dec_rc$154
- attribute \src "libresoc.v:129354.7-129354.20"
+ attribute \src "libresoc.v:127977.7-127977.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129369.3-129387.6"
+ attribute \src "libresoc.v:127992.3-128010.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129388.3-129406.6"
+ attribute \src "libresoc.v:128011.3-128029.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129369.3-129387.6"
+ attribute \src "libresoc.v:127992.3-128010.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129388.3-129406.6"
+ attribute \src "libresoc.v:128011.3-128029.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \DIV_Rc
- attribute \src "libresoc.v:129354.7-129354.15"
+ attribute \src "libresoc.v:127977.7-127977.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129354.7-129354.20"
- process $proc$libresoc.v:129354$5065
+ attribute \src "libresoc.v:127977.7-127977.20"
+ process $proc$libresoc.v:127977$5009
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129369.3-129387.6"
- process $proc$libresoc.v:129369$5063
+ attribute \src "libresoc.v:127992.3-128010.6"
+ process $proc$libresoc.v:127992$5007
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129370.5-129370.29"
+ attribute \src "libresoc.v:127993.5-127993.29"
switch \initial
- attribute \src "libresoc.v:129370.9-129370.17"
+ attribute \src "libresoc.v:127993.9-127993.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129388.3-129406.6"
- process $proc$libresoc.v:129388$5064
+ attribute \src "libresoc.v:128011.3-128029.6"
+ process $proc$libresoc.v:128011$5008
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129389.5-129389.29"
+ attribute \src "libresoc.v:128012.5-128012.29"
switch \initial
- attribute \src "libresoc.v:129389.9-129389.17"
+ attribute \src "libresoc.v:128012.9-128012.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129411.1-129465.10"
+attribute \src "libresoc.v:128034.1-128088.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc"
attribute \generator "nMigen"
module \dec_rc$159
- attribute \src "libresoc.v:129412.7-129412.20"
+ attribute \src "libresoc.v:128035.7-128035.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129427.3-129445.6"
+ attribute \src "libresoc.v:128050.3-128068.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129446.3-129464.6"
+ attribute \src "libresoc.v:128069.3-128087.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129427.3-129445.6"
+ attribute \src "libresoc.v:128050.3-128068.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129446.3-129464.6"
+ attribute \src "libresoc.v:128069.3-128087.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \MUL_Rc
- attribute \src "libresoc.v:129412.7-129412.15"
+ attribute \src "libresoc.v:128035.7-128035.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129412.7-129412.20"
- process $proc$libresoc.v:129412$5068
+ attribute \src "libresoc.v:128035.7-128035.20"
+ process $proc$libresoc.v:128035$5012
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129427.3-129445.6"
- process $proc$libresoc.v:129427$5066
+ attribute \src "libresoc.v:128050.3-128068.6"
+ process $proc$libresoc.v:128050$5010
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129428.5-129428.29"
+ attribute \src "libresoc.v:128051.5-128051.29"
switch \initial
- attribute \src "libresoc.v:129428.9-129428.17"
+ attribute \src "libresoc.v:128051.9-128051.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129446.3-129464.6"
- process $proc$libresoc.v:129446$5067
+ attribute \src "libresoc.v:128069.3-128087.6"
+ process $proc$libresoc.v:128069$5011
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129447.5-129447.29"
+ attribute \src "libresoc.v:128070.5-128070.29"
switch \initial
- attribute \src "libresoc.v:129447.9-129447.17"
+ attribute \src "libresoc.v:128070.9-128070.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129469.1-129523.10"
+attribute \src "libresoc.v:128092.1-128146.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc"
attribute \generator "nMigen"
module \dec_rc$163
- attribute \src "libresoc.v:129470.7-129470.20"
+ attribute \src "libresoc.v:128093.7-128093.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129485.3-129503.6"
+ attribute \src "libresoc.v:128108.3-128126.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129504.3-129522.6"
+ attribute \src "libresoc.v:128127.3-128145.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129485.3-129503.6"
+ attribute \src "libresoc.v:128108.3-128126.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129504.3-129522.6"
+ attribute \src "libresoc.v:128127.3-128145.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \SHIFT_ROT_Rc
- attribute \src "libresoc.v:129470.7-129470.15"
+ attribute \src "libresoc.v:128093.7-128093.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129470.7-129470.20"
- process $proc$libresoc.v:129470$5071
+ attribute \src "libresoc.v:128093.7-128093.20"
+ process $proc$libresoc.v:128093$5015
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129485.3-129503.6"
- process $proc$libresoc.v:129485$5069
+ attribute \src "libresoc.v:128108.3-128126.6"
+ process $proc$libresoc.v:128108$5013
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129486.5-129486.29"
+ attribute \src "libresoc.v:128109.5-128109.29"
switch \initial
- attribute \src "libresoc.v:129486.9-129486.17"
+ attribute \src "libresoc.v:128109.9-128109.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129504.3-129522.6"
- process $proc$libresoc.v:129504$5070
+ attribute \src "libresoc.v:128127.3-128145.6"
+ process $proc$libresoc.v:128127$5014
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129505.5-129505.29"
+ attribute \src "libresoc.v:128128.5-128128.29"
switch \initial
- attribute \src "libresoc.v:129505.9-129505.17"
+ attribute \src "libresoc.v:128128.9-128128.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129527.1-129581.10"
+attribute \src "libresoc.v:128150.1-128204.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc"
attribute \generator "nMigen"
module \dec_rc$167
- attribute \src "libresoc.v:129528.7-129528.20"
+ attribute \src "libresoc.v:128151.7-128151.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129543.3-129561.6"
+ attribute \src "libresoc.v:128166.3-128184.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129562.3-129580.6"
+ attribute \src "libresoc.v:128185.3-128203.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129543.3-129561.6"
+ attribute \src "libresoc.v:128166.3-128184.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129562.3-129580.6"
+ attribute \src "libresoc.v:128185.3-128203.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \LDST_Rc
- attribute \src "libresoc.v:129528.7-129528.15"
+ attribute \src "libresoc.v:128151.7-128151.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129528.7-129528.20"
- process $proc$libresoc.v:129528$5074
+ attribute \src "libresoc.v:128151.7-128151.20"
+ process $proc$libresoc.v:128151$5018
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129543.3-129561.6"
- process $proc$libresoc.v:129543$5072
+ attribute \src "libresoc.v:128166.3-128184.6"
+ process $proc$libresoc.v:128166$5016
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129544.5-129544.29"
+ attribute \src "libresoc.v:128167.5-128167.29"
switch \initial
- attribute \src "libresoc.v:129544.9-129544.17"
+ attribute \src "libresoc.v:128167.9-128167.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129562.3-129580.6"
- process $proc$libresoc.v:129562$5073
+ attribute \src "libresoc.v:128185.3-128203.6"
+ process $proc$libresoc.v:128185$5017
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129563.5-129563.29"
+ attribute \src "libresoc.v:128186.5-128186.29"
switch \initial
- attribute \src "libresoc.v:129563.9-129563.17"
+ attribute \src "libresoc.v:128186.9-128186.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129585.1-129639.10"
+attribute \src "libresoc.v:128208.1-128262.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc"
attribute \generator "nMigen"
module \dec_rc$172
- attribute \src "libresoc.v:129586.7-129586.20"
+ attribute \src "libresoc.v:128209.7-128209.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:129601.3-129619.6"
+ attribute \src "libresoc.v:128224.3-128242.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:129620.3-129638.6"
+ attribute \src "libresoc.v:128243.3-128261.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:129601.3-129619.6"
+ attribute \src "libresoc.v:128224.3-128242.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:129620.3-129638.6"
+ attribute \src "libresoc.v:128243.3-128261.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468"
wire input 3 \Rc
- attribute \src "libresoc.v:129586.7-129586.15"
+ attribute \src "libresoc.v:128209.7-128209.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:129586.7-129586.20"
- process $proc$libresoc.v:129586$5077
+ attribute \src "libresoc.v:128209.7-128209.20"
+ process $proc$libresoc.v:128209$5021
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129601.3-129619.6"
- process $proc$libresoc.v:129601$5075
+ attribute \src "libresoc.v:128224.3-128242.6"
+ process $proc$libresoc.v:128224$5019
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:129602.5-129602.29"
+ attribute \src "libresoc.v:128225.5-128225.29"
switch \initial
- attribute \src "libresoc.v:129602.9-129602.17"
+ attribute \src "libresoc.v:128225.9-128225.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:129620.3-129638.6"
- process $proc$libresoc.v:129620$5076
+ attribute \src "libresoc.v:128243.3-128261.6"
+ process $proc$libresoc.v:128243$5020
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:129621.5-129621.29"
+ attribute \src "libresoc.v:128244.5-128244.29"
switch \initial
- attribute \src "libresoc.v:129621.9-129621.17"
+ attribute \src "libresoc.v:128244.9-128244.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:129643.1-130883.10"
+attribute \src "libresoc.v:128266.1-129506.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0"
attribute \generator "nMigen"
module \div0
- attribute \src "libresoc.v:130440.3-130441.25"
+ attribute \src "libresoc.v:129063.3-129064.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5217
- attribute \src "libresoc.v:130412.3-130413.75"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5161
+ attribute \src "libresoc.v:129035.3-129036.75"
wire width 4 $0\alu_div0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5218
- attribute \src "libresoc.v:130382.3-130383.73"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5162
+ attribute \src "libresoc.v:129005.3-129006.73"
wire width 13 $0\alu_div0_logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219
- attribute \src "libresoc.v:130384.3-130385.87"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163
+ attribute \src "libresoc.v:129007.3-129008.87"
wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220
- attribute \src "libresoc.v:130386.3-130387.83"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164
+ attribute \src "libresoc.v:129009.3-129010.83"
wire $0\alu_div0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5221
- attribute \src "libresoc.v:130400.3-130401.81"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5165
+ attribute \src "libresoc.v:129023.3-129024.81"
wire width 2 $0\alu_div0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5222
- attribute \src "libresoc.v:130414.3-130415.67"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5166
+ attribute \src "libresoc.v:129037.3-129038.67"
wire width 32 $0\alu_div0_logical_op__insn[31:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5223
- attribute \src "libresoc.v:130380.3-130381.77"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5167
+ attribute \src "libresoc.v:129003.3-129004.77"
wire width 7 $0\alu_div0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__invert_in$next[0:0]$5224
- attribute \src "libresoc.v:130396.3-130397.77"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__invert_in$next[0:0]$5168
+ attribute \src "libresoc.v:129019.3-129020.77"
wire $0\alu_div0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__invert_out$next[0:0]$5225
- attribute \src "libresoc.v:130402.3-130403.79"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__invert_out$next[0:0]$5169
+ attribute \src "libresoc.v:129025.3-129026.79"
wire $0\alu_div0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5226
- attribute \src "libresoc.v:130408.3-130409.75"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5170
+ attribute \src "libresoc.v:129031.3-129032.75"
wire $0\alu_div0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__is_signed$next[0:0]$5227
- attribute \src "libresoc.v:130410.3-130411.77"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__is_signed$next[0:0]$5171
+ attribute \src "libresoc.v:129033.3-129034.77"
wire $0\alu_div0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5228
- attribute \src "libresoc.v:130392.3-130393.71"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5172
+ attribute \src "libresoc.v:129015.3-129016.71"
wire $0\alu_div0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5229
- attribute \src "libresoc.v:130394.3-130395.71"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5173
+ attribute \src "libresoc.v:129017.3-129018.71"
wire $0\alu_div0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__output_carry$next[0:0]$5230
- attribute \src "libresoc.v:130406.3-130407.83"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__output_carry$next[0:0]$5174
+ attribute \src "libresoc.v:129029.3-129030.83"
wire $0\alu_div0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5231
- attribute \src "libresoc.v:130390.3-130391.71"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5175
+ attribute \src "libresoc.v:129013.3-129014.71"
wire $0\alu_div0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5232
- attribute \src "libresoc.v:130388.3-130389.71"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5176
+ attribute \src "libresoc.v:129011.3-129012.71"
wire $0\alu_div0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5233
- attribute \src "libresoc.v:130404.3-130405.77"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5177
+ attribute \src "libresoc.v:129027.3-129028.77"
wire $0\alu_div0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $0\alu_div0_logical_op__zero_a$next[0:0]$5234
- attribute \src "libresoc.v:130398.3-130399.71"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $0\alu_div0_logical_op__zero_a$next[0:0]$5178
+ attribute \src "libresoc.v:129021.3-129022.71"
wire $0\alu_div0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:130438.3-130439.40"
+ attribute \src "libresoc.v:129061.3-129062.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:130793.3-130801.6"
- wire $0\alu_l_r_alu$next[0:0]$5304
- attribute \src "libresoc.v:130354.3-130355.39"
+ attribute \src "libresoc.v:129416.3-129424.6"
+ wire $0\alu_l_r_alu$next[0:0]$5248
+ attribute \src "libresoc.v:128977.3-128978.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:130784.3-130792.6"
- wire $0\alui_l_r_alui$next[0:0]$5301
- attribute \src "libresoc.v:130356.3-130357.43"
+ attribute \src "libresoc.v:129407.3-129415.6"
+ wire $0\alui_l_r_alui$next[0:0]$5245
+ attribute \src "libresoc.v:128979.3-128980.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:130666.3-130687.6"
- wire width 64 $0\data_r0__o$next[63:0]$5260
- attribute \src "libresoc.v:130376.3-130377.37"
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire width 64 $0\data_r0__o$next[63:0]$5204
+ attribute \src "libresoc.v:128999.3-129000.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:130666.3-130687.6"
- wire $0\data_r0__o_ok$next[0:0]$5261
- attribute \src "libresoc.v:130378.3-130379.43"
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire $0\data_r0__o_ok$next[0:0]$5205
+ attribute \src "libresoc.v:129001.3-129002.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:130688.3-130709.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$5268
- attribute \src "libresoc.v:130372.3-130373.43"
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$5212
+ attribute \src "libresoc.v:128995.3-128996.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:130688.3-130709.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$5269
- attribute \src "libresoc.v:130374.3-130375.49"
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$5213
+ attribute \src "libresoc.v:128997.3-128998.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:130710.3-130731.6"
- wire width 2 $0\data_r2__xer_ov$next[1:0]$5276
- attribute \src "libresoc.v:130368.3-130369.47"
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire width 2 $0\data_r2__xer_ov$next[1:0]$5220
+ attribute \src "libresoc.v:128991.3-128992.47"
wire width 2 $0\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:130710.3-130731.6"
- wire $0\data_r2__xer_ov_ok$next[0:0]$5277
- attribute \src "libresoc.v:130370.3-130371.53"
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire $0\data_r2__xer_ov_ok$next[0:0]$5221
+ attribute \src "libresoc.v:128993.3-128994.53"
wire $0\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $0\data_r3__xer_so$next[0:0]$5284
- attribute \src "libresoc.v:130364.3-130365.47"
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $0\data_r3__xer_so$next[0:0]$5228
+ attribute \src "libresoc.v:128987.3-128988.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$5285
- attribute \src "libresoc.v:130366.3-130367.53"
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$5229
+ attribute \src "libresoc.v:128989.3-128990.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:130802.3-130811.6"
+ attribute \src "libresoc.v:129425.3-129434.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:130812.3-130821.6"
+ attribute \src "libresoc.v:129435.3-129444.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:130822.3-130831.6"
+ attribute \src "libresoc.v:129445.3-129454.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:130832.3-130841.6"
+ attribute \src "libresoc.v:129455.3-129464.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:129644.7-129644.20"
+ attribute \src "libresoc.v:128267.7-128267.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130582.3-130590.6"
- wire $0\opc_l_r_opc$next[0:0]$5202
- attribute \src "libresoc.v:130424.3-130425.39"
+ attribute \src "libresoc.v:129205.3-129213.6"
+ wire $0\opc_l_r_opc$next[0:0]$5146
+ attribute \src "libresoc.v:129047.3-129048.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:130573.3-130581.6"
- wire $0\opc_l_s_opc$next[0:0]$5199
- attribute \src "libresoc.v:130426.3-130427.39"
+ attribute \src "libresoc.v:129196.3-129204.6"
+ wire $0\opc_l_s_opc$next[0:0]$5143
+ attribute \src "libresoc.v:129049.3-129050.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:130842.3-130850.6"
- wire width 4 $0\prev_wr_go$next[3:0]$5311
- attribute \src "libresoc.v:130436.3-130437.37"
+ attribute \src "libresoc.v:129465.3-129473.6"
+ wire width 4 $0\prev_wr_go$next[3:0]$5255
+ attribute \src "libresoc.v:129059.3-129060.37"
wire width 4 $0\prev_wr_go[3:0]
- attribute \src "libresoc.v:130527.3-130536.6"
+ attribute \src "libresoc.v:129150.3-129159.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:130618.3-130626.6"
- wire width 4 $0\req_l_r_req$next[3:0]$5214
- attribute \src "libresoc.v:130416.3-130417.39"
+ attribute \src "libresoc.v:129241.3-129249.6"
+ wire width 4 $0\req_l_r_req$next[3:0]$5158
+ attribute \src "libresoc.v:129039.3-129040.39"
wire width 4 $0\req_l_r_req[3:0]
- attribute \src "libresoc.v:130609.3-130617.6"
- wire width 4 $0\req_l_s_req$next[3:0]$5211
- attribute \src "libresoc.v:130418.3-130419.39"
+ attribute \src "libresoc.v:129232.3-129240.6"
+ wire width 4 $0\req_l_s_req$next[3:0]$5155
+ attribute \src "libresoc.v:129041.3-129042.39"
wire width 4 $0\req_l_s_req[3:0]
- attribute \src "libresoc.v:130546.3-130554.6"
- wire $0\rok_l_r_rdok$next[0:0]$5190
- attribute \src "libresoc.v:130432.3-130433.41"
+ attribute \src "libresoc.v:129169.3-129177.6"
+ wire $0\rok_l_r_rdok$next[0:0]$5134
+ attribute \src "libresoc.v:129055.3-129056.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:130537.3-130545.6"
- wire $0\rok_l_s_rdok$next[0:0]$5187
- attribute \src "libresoc.v:130434.3-130435.41"
+ attribute \src "libresoc.v:129160.3-129168.6"
+ wire $0\rok_l_s_rdok$next[0:0]$5131
+ attribute \src "libresoc.v:129057.3-129058.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:130564.3-130572.6"
- wire $0\rst_l_r_rst$next[0:0]$5196
- attribute \src "libresoc.v:130428.3-130429.39"
+ attribute \src "libresoc.v:129187.3-129195.6"
+ wire $0\rst_l_r_rst$next[0:0]$5140
+ attribute \src "libresoc.v:129051.3-129052.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:130555.3-130563.6"
- wire $0\rst_l_s_rst$next[0:0]$5193
- attribute \src "libresoc.v:130430.3-130431.39"
+ attribute \src "libresoc.v:129178.3-129186.6"
+ wire $0\rst_l_s_rst$next[0:0]$5137
+ attribute \src "libresoc.v:129053.3-129054.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:130600.3-130608.6"
- wire width 3 $0\src_l_r_src$next[2:0]$5208
- attribute \src "libresoc.v:130420.3-130421.39"
+ attribute \src "libresoc.v:129223.3-129231.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$5152
+ attribute \src "libresoc.v:129043.3-129044.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:130591.3-130599.6"
- wire width 3 $0\src_l_s_src$next[2:0]$5205
- attribute \src "libresoc.v:130422.3-130423.39"
+ attribute \src "libresoc.v:129214.3-129222.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$5149
+ attribute \src "libresoc.v:129045.3-129046.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:130754.3-130763.6"
- wire width 64 $0\src_r0$next[63:0]$5292
- attribute \src "libresoc.v:130362.3-130363.29"
+ attribute \src "libresoc.v:129377.3-129386.6"
+ wire width 64 $0\src_r0$next[63:0]$5236
+ attribute \src "libresoc.v:128985.3-128986.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:130764.3-130773.6"
- wire width 64 $0\src_r1$next[63:0]$5295
- attribute \src "libresoc.v:130360.3-130361.29"
+ attribute \src "libresoc.v:129387.3-129396.6"
+ wire width 64 $0\src_r1$next[63:0]$5239
+ attribute \src "libresoc.v:128983.3-128984.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:130774.3-130783.6"
- wire $0\src_r2$next[0:0]$5298
- attribute \src "libresoc.v:130358.3-130359.29"
+ attribute \src "libresoc.v:129397.3-129406.6"
+ wire $0\src_r2$next[0:0]$5242
+ attribute \src "libresoc.v:128981.3-128982.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:129774.7-129774.24"
+ attribute \src "libresoc.v:128397.7-128397.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5235
- attribute \src "libresoc.v:129784.13-129784.49"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5179
+ attribute \src "libresoc.v:128407.13-128407.49"
wire width 4 $1\alu_div0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236
- attribute \src "libresoc.v:129802.14-129802.53"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180
+ attribute \src "libresoc.v:128425.14-128425.53"
wire width 13 $1\alu_div0_logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237
- attribute \src "libresoc.v:129806.14-129806.72"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181
+ attribute \src "libresoc.v:128429.14-128429.72"
wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238
- attribute \src "libresoc.v:129810.7-129810.47"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182
+ attribute \src "libresoc.v:128433.7-128433.47"
wire $1\alu_div0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5239
- attribute \src "libresoc.v:129818.13-129818.52"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5183
+ attribute \src "libresoc.v:128441.13-128441.52"
wire width 2 $1\alu_div0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5240
- attribute \src "libresoc.v:129822.14-129822.47"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5184
+ attribute \src "libresoc.v:128445.14-128445.47"
wire width 32 $1\alu_div0_logical_op__insn[31:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5241
- attribute \src "libresoc.v:129900.13-129900.51"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5185
+ attribute \src "libresoc.v:128523.13-128523.51"
wire width 7 $1\alu_div0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__invert_in$next[0:0]$5242
- attribute \src "libresoc.v:129904.7-129904.44"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__invert_in$next[0:0]$5186
+ attribute \src "libresoc.v:128527.7-128527.44"
wire $1\alu_div0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__invert_out$next[0:0]$5243
- attribute \src "libresoc.v:129908.7-129908.45"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__invert_out$next[0:0]$5187
+ attribute \src "libresoc.v:128531.7-128531.45"
wire $1\alu_div0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5244
- attribute \src "libresoc.v:129912.7-129912.43"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5188
+ attribute \src "libresoc.v:128535.7-128535.43"
wire $1\alu_div0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__is_signed$next[0:0]$5245
- attribute \src "libresoc.v:129916.7-129916.44"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__is_signed$next[0:0]$5189
+ attribute \src "libresoc.v:128539.7-128539.44"
wire $1\alu_div0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5246
- attribute \src "libresoc.v:129920.7-129920.41"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5190
+ attribute \src "libresoc.v:128543.7-128543.41"
wire $1\alu_div0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5247
- attribute \src "libresoc.v:129924.7-129924.41"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5191
+ attribute \src "libresoc.v:128547.7-128547.41"
wire $1\alu_div0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__output_carry$next[0:0]$5248
- attribute \src "libresoc.v:129928.7-129928.47"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__output_carry$next[0:0]$5192
+ attribute \src "libresoc.v:128551.7-128551.47"
wire $1\alu_div0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5249
- attribute \src "libresoc.v:129932.7-129932.41"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5193
+ attribute \src "libresoc.v:128555.7-128555.41"
wire $1\alu_div0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5250
- attribute \src "libresoc.v:129936.7-129936.41"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5194
+ attribute \src "libresoc.v:128559.7-128559.41"
wire $1\alu_div0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5251
- attribute \src "libresoc.v:129940.7-129940.44"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5195
+ attribute \src "libresoc.v:128563.7-128563.44"
wire $1\alu_div0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $1\alu_div0_logical_op__zero_a$next[0:0]$5252
- attribute \src "libresoc.v:129944.7-129944.41"
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $1\alu_div0_logical_op__zero_a$next[0:0]$5196
+ attribute \src "libresoc.v:128567.7-128567.41"
wire $1\alu_div0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:129970.7-129970.26"
+ attribute \src "libresoc.v:128593.7-128593.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:130793.3-130801.6"
- wire $1\alu_l_r_alu$next[0:0]$5305
- attribute \src "libresoc.v:129978.7-129978.25"
+ attribute \src "libresoc.v:129416.3-129424.6"
+ wire $1\alu_l_r_alu$next[0:0]$5249
+ attribute \src "libresoc.v:128601.7-128601.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:130784.3-130792.6"
- wire $1\alui_l_r_alui$next[0:0]$5302
- attribute \src "libresoc.v:129990.7-129990.27"
+ attribute \src "libresoc.v:129407.3-129415.6"
+ wire $1\alui_l_r_alui$next[0:0]$5246
+ attribute \src "libresoc.v:128613.7-128613.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:130666.3-130687.6"
- wire width 64 $1\data_r0__o$next[63:0]$5262
- attribute \src "libresoc.v:130024.14-130024.47"
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire width 64 $1\data_r0__o$next[63:0]$5206
+ attribute \src "libresoc.v:128647.14-128647.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:130666.3-130687.6"
- wire $1\data_r0__o_ok$next[0:0]$5263
- attribute \src "libresoc.v:130028.7-130028.27"
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire $1\data_r0__o_ok$next[0:0]$5207
+ attribute \src "libresoc.v:128651.7-128651.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:130688.3-130709.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$5270
- attribute \src "libresoc.v:130032.13-130032.33"
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$5214
+ attribute \src "libresoc.v:128655.13-128655.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:130688.3-130709.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$5271
- attribute \src "libresoc.v:130036.7-130036.30"
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$5215
+ attribute \src "libresoc.v:128659.7-128659.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:130710.3-130731.6"
- wire width 2 $1\data_r2__xer_ov$next[1:0]$5278
- attribute \src "libresoc.v:130040.13-130040.35"
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire width 2 $1\data_r2__xer_ov$next[1:0]$5222
+ attribute \src "libresoc.v:128663.13-128663.35"
wire width 2 $1\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:130710.3-130731.6"
- wire $1\data_r2__xer_ov_ok$next[0:0]$5279
- attribute \src "libresoc.v:130044.7-130044.32"
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire $1\data_r2__xer_ov_ok$next[0:0]$5223
+ attribute \src "libresoc.v:128667.7-128667.32"
wire $1\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $1\data_r3__xer_so$next[0:0]$5286
- attribute \src "libresoc.v:130048.7-130048.29"
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $1\data_r3__xer_so$next[0:0]$5230
+ attribute \src "libresoc.v:128671.7-128671.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$5287
- attribute \src "libresoc.v:130052.7-130052.32"
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$5231
+ attribute \src "libresoc.v:128675.7-128675.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:130802.3-130811.6"
+ attribute \src "libresoc.v:129425.3-129434.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:130812.3-130821.6"
+ attribute \src "libresoc.v:129435.3-129444.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:130822.3-130831.6"
+ attribute \src "libresoc.v:129445.3-129454.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:130832.3-130841.6"
+ attribute \src "libresoc.v:129455.3-129464.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:130582.3-130590.6"
- wire $1\opc_l_r_opc$next[0:0]$5203
- attribute \src "libresoc.v:130072.7-130072.25"
+ attribute \src "libresoc.v:129205.3-129213.6"
+ wire $1\opc_l_r_opc$next[0:0]$5147
+ attribute \src "libresoc.v:128695.7-128695.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:130573.3-130581.6"
- wire $1\opc_l_s_opc$next[0:0]$5200
- attribute \src "libresoc.v:130076.7-130076.25"
+ attribute \src "libresoc.v:129196.3-129204.6"
+ wire $1\opc_l_s_opc$next[0:0]$5144
+ attribute \src "libresoc.v:128699.7-128699.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:130842.3-130850.6"
- wire width 4 $1\prev_wr_go$next[3:0]$5312
- attribute \src "libresoc.v:130208.13-130208.30"
+ attribute \src "libresoc.v:129465.3-129473.6"
+ wire width 4 $1\prev_wr_go$next[3:0]$5256
+ attribute \src "libresoc.v:128831.13-128831.30"
wire width 4 $1\prev_wr_go[3:0]
- attribute \src "libresoc.v:130527.3-130536.6"
+ attribute \src "libresoc.v:129150.3-129159.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:130618.3-130626.6"
- wire width 4 $1\req_l_r_req$next[3:0]$5215
- attribute \src "libresoc.v:130216.13-130216.31"
+ attribute \src "libresoc.v:129241.3-129249.6"
+ wire width 4 $1\req_l_r_req$next[3:0]$5159
+ attribute \src "libresoc.v:128839.13-128839.31"
wire width 4 $1\req_l_r_req[3:0]
- attribute \src "libresoc.v:130609.3-130617.6"
- wire width 4 $1\req_l_s_req$next[3:0]$5212
- attribute \src "libresoc.v:130220.13-130220.31"
+ attribute \src "libresoc.v:129232.3-129240.6"
+ wire width 4 $1\req_l_s_req$next[3:0]$5156
+ attribute \src "libresoc.v:128843.13-128843.31"
wire width 4 $1\req_l_s_req[3:0]
- attribute \src "libresoc.v:130546.3-130554.6"
- wire $1\rok_l_r_rdok$next[0:0]$5191
- attribute \src "libresoc.v:130232.7-130232.26"
+ attribute \src "libresoc.v:129169.3-129177.6"
+ wire $1\rok_l_r_rdok$next[0:0]$5135
+ attribute \src "libresoc.v:128855.7-128855.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:130537.3-130545.6"
- wire $1\rok_l_s_rdok$next[0:0]$5188
- attribute \src "libresoc.v:130236.7-130236.26"
+ attribute \src "libresoc.v:129160.3-129168.6"
+ wire $1\rok_l_s_rdok$next[0:0]$5132
+ attribute \src "libresoc.v:128859.7-128859.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:130564.3-130572.6"
- wire $1\rst_l_r_rst$next[0:0]$5197
- attribute \src "libresoc.v:130240.7-130240.25"
+ attribute \src "libresoc.v:129187.3-129195.6"
+ wire $1\rst_l_r_rst$next[0:0]$5141
+ attribute \src "libresoc.v:128863.7-128863.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:130555.3-130563.6"
- wire $1\rst_l_s_rst$next[0:0]$5194
- attribute \src "libresoc.v:130244.7-130244.25"
+ attribute \src "libresoc.v:129178.3-129186.6"
+ wire $1\rst_l_s_rst$next[0:0]$5138
+ attribute \src "libresoc.v:128867.7-128867.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:130600.3-130608.6"
- wire width 3 $1\src_l_r_src$next[2:0]$5209
- attribute \src "libresoc.v:130258.13-130258.31"
+ attribute \src "libresoc.v:129223.3-129231.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$5153
+ attribute \src "libresoc.v:128881.13-128881.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:130591.3-130599.6"
- wire width 3 $1\src_l_s_src$next[2:0]$5206
- attribute \src "libresoc.v:130262.13-130262.31"
+ attribute \src "libresoc.v:129214.3-129222.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$5150
+ attribute \src "libresoc.v:128885.13-128885.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:130754.3-130763.6"
- wire width 64 $1\src_r0$next[63:0]$5293
- attribute \src "libresoc.v:130270.14-130270.43"
+ attribute \src "libresoc.v:129377.3-129386.6"
+ wire width 64 $1\src_r0$next[63:0]$5237
+ attribute \src "libresoc.v:128893.14-128893.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:130764.3-130773.6"
- wire width 64 $1\src_r1$next[63:0]$5296
- attribute \src "libresoc.v:130274.14-130274.43"
+ attribute \src "libresoc.v:129387.3-129396.6"
+ wire width 64 $1\src_r1$next[63:0]$5240
+ attribute \src "libresoc.v:128897.14-128897.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:130774.3-130783.6"
- wire $1\src_r2$next[0:0]$5299
- attribute \src "libresoc.v:130278.7-130278.20"
+ attribute \src "libresoc.v:129397.3-129406.6"
+ wire $1\src_r2$next[0:0]$5243
+ attribute \src "libresoc.v:128901.7-128901.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:130627.3-130665.6"
- wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5255
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5256
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5257
- attribute \src "libresoc.v:130627.3-130665.6"
- wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5258
- attribute \src "libresoc.v:130666.3-130687.6"
- wire width 64 $2\data_r0__o$next[63:0]$5264
- attribute \src "libresoc.v:130666.3-130687.6"
- wire $2\data_r0__o_ok$next[0:0]$5265
- attribute \src "libresoc.v:130688.3-130709.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$5272
- attribute \src "libresoc.v:130688.3-130709.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$5273
- attribute \src "libresoc.v:130710.3-130731.6"
- wire width 2 $2\data_r2__xer_ov$next[1:0]$5280
- attribute \src "libresoc.v:130710.3-130731.6"
- wire $2\data_r2__xer_ov_ok$next[0:0]$5281
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $2\data_r3__xer_so$next[0:0]$5288
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$5289
- attribute \src "libresoc.v:130666.3-130687.6"
- wire $3\data_r0__o_ok$next[0:0]$5266
- attribute \src "libresoc.v:130688.3-130709.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$5274
- attribute \src "libresoc.v:130710.3-130731.6"
- wire $3\data_r2__xer_ov_ok$next[0:0]$5282
- attribute \src "libresoc.v:130732.3-130753.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$5290
- attribute \src "libresoc.v:130293.19-130293.133"
- wire width 3 $and$libresoc.v:130293$5080_Y
- attribute \src "libresoc.v:130295.19-130295.115"
- wire width 3 $and$libresoc.v:130295$5082_Y
- attribute \src "libresoc.v:130296.18-130296.110"
- wire $and$libresoc.v:130296$5083_Y
- attribute \src "libresoc.v:130297.19-130297.125"
- wire $and$libresoc.v:130297$5084_Y
- attribute \src "libresoc.v:130298.19-130298.125"
- wire $and$libresoc.v:130298$5085_Y
- attribute \src "libresoc.v:130299.19-130299.125"
- wire $and$libresoc.v:130299$5086_Y
- attribute \src "libresoc.v:130300.19-130300.125"
- wire $and$libresoc.v:130300$5087_Y
- attribute \src "libresoc.v:130301.19-130301.149"
- wire width 4 $and$libresoc.v:130301$5088_Y
- attribute \src "libresoc.v:130302.19-130302.121"
- wire width 4 $and$libresoc.v:130302$5089_Y
- attribute \src "libresoc.v:130303.19-130303.127"
- wire $and$libresoc.v:130303$5090_Y
- attribute \src "libresoc.v:130304.19-130304.127"
- wire $and$libresoc.v:130304$5091_Y
- attribute \src "libresoc.v:130305.19-130305.127"
- wire $and$libresoc.v:130305$5092_Y
- attribute \src "libresoc.v:130306.19-130306.127"
- wire $and$libresoc.v:130306$5093_Y
- attribute \src "libresoc.v:130308.18-130308.98"
- wire $and$libresoc.v:130308$5095_Y
- attribute \src "libresoc.v:130310.18-130310.100"
- wire $and$libresoc.v:130310$5097_Y
- attribute \src "libresoc.v:130311.18-130311.160"
- wire width 4 $and$libresoc.v:130311$5098_Y
- attribute \src "libresoc.v:130313.18-130313.119"
- wire width 4 $and$libresoc.v:130313$5100_Y
- attribute \src "libresoc.v:130316.17-130316.123"
- wire $and$libresoc.v:130316$5103_Y
- attribute \src "libresoc.v:130317.18-130317.116"
- wire $and$libresoc.v:130317$5104_Y
- attribute \src "libresoc.v:130322.18-130322.113"
- wire $and$libresoc.v:130322$5109_Y
- attribute \src "libresoc.v:130323.18-130323.125"
- wire width 4 $and$libresoc.v:130323$5110_Y
- attribute \src "libresoc.v:130325.18-130325.112"
- wire $and$libresoc.v:130325$5112_Y
- attribute \src "libresoc.v:130327.18-130327.126"
- wire $and$libresoc.v:130327$5114_Y
- attribute \src "libresoc.v:130328.18-130328.126"
- wire $and$libresoc.v:130328$5115_Y
- attribute \src "libresoc.v:130329.18-130329.117"
- wire $and$libresoc.v:130329$5116_Y
- attribute \src "libresoc.v:130335.18-130335.130"
- wire $and$libresoc.v:130335$5122_Y
- attribute \src "libresoc.v:130336.18-130336.124"
- wire width 4 $and$libresoc.v:130336$5123_Y
- attribute \src "libresoc.v:130338.18-130338.116"
- wire $and$libresoc.v:130338$5125_Y
- attribute \src "libresoc.v:130339.18-130339.119"
- wire $and$libresoc.v:130339$5126_Y
- attribute \src "libresoc.v:130340.18-130340.121"
- wire $and$libresoc.v:130340$5127_Y
- attribute \src "libresoc.v:130341.18-130341.121"
- wire $and$libresoc.v:130341$5128_Y
- attribute \src "libresoc.v:130351.18-130351.134"
- wire $and$libresoc.v:130351$5138_Y
- attribute \src "libresoc.v:130352.18-130352.132"
- wire $and$libresoc.v:130352$5139_Y
- attribute \src "libresoc.v:130353.18-130353.149"
- wire width 3 $and$libresoc.v:130353$5140_Y
- attribute \src "libresoc.v:130324.18-130324.113"
- wire $eq$libresoc.v:130324$5111_Y
- attribute \src "libresoc.v:130326.18-130326.119"
- wire $eq$libresoc.v:130326$5113_Y
- attribute \src "libresoc.v:130291.19-130291.130"
- wire $not$libresoc.v:130291$5078_Y
- attribute \src "libresoc.v:130292.19-130292.136"
- wire $not$libresoc.v:130292$5079_Y
- attribute \src "libresoc.v:130294.19-130294.115"
- wire width 3 $not$libresoc.v:130294$5081_Y
- attribute \src "libresoc.v:130307.18-130307.97"
- wire $not$libresoc.v:130307$5094_Y
- attribute \src "libresoc.v:130309.18-130309.99"
- wire $not$libresoc.v:130309$5096_Y
- attribute \src "libresoc.v:130312.18-130312.113"
- wire width 4 $not$libresoc.v:130312$5099_Y
- attribute \src "libresoc.v:130315.18-130315.106"
- wire $not$libresoc.v:130315$5102_Y
- attribute \src "libresoc.v:130321.18-130321.120"
- wire $not$libresoc.v:130321$5108_Y
- attribute \src "libresoc.v:130332.17-130332.113"
- wire width 3 $not$libresoc.v:130332$5119_Y
- attribute \src "libresoc.v:130320.18-130320.112"
- wire $or$libresoc.v:130320$5107_Y
- attribute \src "libresoc.v:130330.18-130330.122"
- wire $or$libresoc.v:130330$5117_Y
- attribute \src "libresoc.v:130331.18-130331.124"
- wire $or$libresoc.v:130331$5118_Y
- attribute \src "libresoc.v:130333.18-130333.168"
- wire width 4 $or$libresoc.v:130333$5120_Y
- attribute \src "libresoc.v:130334.18-130334.155"
- wire width 3 $or$libresoc.v:130334$5121_Y
- attribute \src "libresoc.v:130337.18-130337.120"
- wire width 4 $or$libresoc.v:130337$5124_Y
- attribute \src "libresoc.v:130343.17-130343.117"
- wire width 3 $or$libresoc.v:130343$5130_Y
- attribute \src "libresoc.v:130348.17-130348.104"
- wire $reduce_and$libresoc.v:130348$5135_Y
- attribute \src "libresoc.v:130314.18-130314.106"
- wire $reduce_or$libresoc.v:130314$5101_Y
- attribute \src "libresoc.v:130318.18-130318.113"
- wire $reduce_or$libresoc.v:130318$5105_Y
- attribute \src "libresoc.v:130319.18-130319.112"
- wire $reduce_or$libresoc.v:130319$5106_Y
- attribute \src "libresoc.v:130342.18-130342.158"
- wire $ternary$libresoc.v:130342$5129_Y
- attribute \src "libresoc.v:130344.18-130344.159"
- wire width 64 $ternary$libresoc.v:130344$5131_Y
- attribute \src "libresoc.v:130345.18-130345.164"
- wire $ternary$libresoc.v:130345$5132_Y
- attribute \src "libresoc.v:130346.18-130346.180"
- wire width 64 $ternary$libresoc.v:130346$5133_Y
- attribute \src "libresoc.v:130347.18-130347.115"
- wire width 64 $ternary$libresoc.v:130347$5134_Y
- attribute \src "libresoc.v:130349.18-130349.125"
- wire width 64 $ternary$libresoc.v:130349$5136_Y
- attribute \src "libresoc.v:130350.18-130350.118"
- wire $ternary$libresoc.v:130350$5137_Y
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5199
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5200
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5201
+ attribute \src "libresoc.v:129250.3-129288.6"
+ wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5202
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire width 64 $2\data_r0__o$next[63:0]$5208
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire $2\data_r0__o_ok$next[0:0]$5209
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$5216
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$5217
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire width 2 $2\data_r2__xer_ov$next[1:0]$5224
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire $2\data_r2__xer_ov_ok$next[0:0]$5225
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $2\data_r3__xer_so$next[0:0]$5232
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$5233
+ attribute \src "libresoc.v:129289.3-129310.6"
+ wire $3\data_r0__o_ok$next[0:0]$5210
+ attribute \src "libresoc.v:129311.3-129332.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$5218
+ attribute \src "libresoc.v:129333.3-129354.6"
+ wire $3\data_r2__xer_ov_ok$next[0:0]$5226
+ attribute \src "libresoc.v:129355.3-129376.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$5234
+ attribute \src "libresoc.v:128916.19-128916.133"
+ wire width 3 $and$libresoc.v:128916$5024_Y
+ attribute \src "libresoc.v:128918.19-128918.115"
+ wire width 3 $and$libresoc.v:128918$5026_Y
+ attribute \src "libresoc.v:128919.18-128919.110"
+ wire $and$libresoc.v:128919$5027_Y
+ attribute \src "libresoc.v:128920.19-128920.125"
+ wire $and$libresoc.v:128920$5028_Y
+ attribute \src "libresoc.v:128921.19-128921.125"
+ wire $and$libresoc.v:128921$5029_Y
+ attribute \src "libresoc.v:128922.19-128922.125"
+ wire $and$libresoc.v:128922$5030_Y
+ attribute \src "libresoc.v:128923.19-128923.125"
+ wire $and$libresoc.v:128923$5031_Y
+ attribute \src "libresoc.v:128924.19-128924.149"
+ wire width 4 $and$libresoc.v:128924$5032_Y
+ attribute \src "libresoc.v:128925.19-128925.121"
+ wire width 4 $and$libresoc.v:128925$5033_Y
+ attribute \src "libresoc.v:128926.19-128926.127"
+ wire $and$libresoc.v:128926$5034_Y
+ attribute \src "libresoc.v:128927.19-128927.127"
+ wire $and$libresoc.v:128927$5035_Y
+ attribute \src "libresoc.v:128928.19-128928.127"
+ wire $and$libresoc.v:128928$5036_Y
+ attribute \src "libresoc.v:128929.19-128929.127"
+ wire $and$libresoc.v:128929$5037_Y
+ attribute \src "libresoc.v:128931.18-128931.98"
+ wire $and$libresoc.v:128931$5039_Y
+ attribute \src "libresoc.v:128933.18-128933.100"
+ wire $and$libresoc.v:128933$5041_Y
+ attribute \src "libresoc.v:128934.18-128934.160"
+ wire width 4 $and$libresoc.v:128934$5042_Y
+ attribute \src "libresoc.v:128936.18-128936.119"
+ wire width 4 $and$libresoc.v:128936$5044_Y
+ attribute \src "libresoc.v:128939.17-128939.123"
+ wire $and$libresoc.v:128939$5047_Y
+ attribute \src "libresoc.v:128940.18-128940.116"
+ wire $and$libresoc.v:128940$5048_Y
+ attribute \src "libresoc.v:128945.18-128945.113"
+ wire $and$libresoc.v:128945$5053_Y
+ attribute \src "libresoc.v:128946.18-128946.125"
+ wire width 4 $and$libresoc.v:128946$5054_Y
+ attribute \src "libresoc.v:128948.18-128948.112"
+ wire $and$libresoc.v:128948$5056_Y
+ attribute \src "libresoc.v:128950.18-128950.126"
+ wire $and$libresoc.v:128950$5058_Y
+ attribute \src "libresoc.v:128951.18-128951.126"
+ wire $and$libresoc.v:128951$5059_Y
+ attribute \src "libresoc.v:128952.18-128952.117"
+ wire $and$libresoc.v:128952$5060_Y
+ attribute \src "libresoc.v:128958.18-128958.130"
+ wire $and$libresoc.v:128958$5066_Y
+ attribute \src "libresoc.v:128959.18-128959.124"
+ wire width 4 $and$libresoc.v:128959$5067_Y
+ attribute \src "libresoc.v:128961.18-128961.116"
+ wire $and$libresoc.v:128961$5069_Y
+ attribute \src "libresoc.v:128962.18-128962.119"
+ wire $and$libresoc.v:128962$5070_Y
+ attribute \src "libresoc.v:128963.18-128963.121"
+ wire $and$libresoc.v:128963$5071_Y
+ attribute \src "libresoc.v:128964.18-128964.121"
+ wire $and$libresoc.v:128964$5072_Y
+ attribute \src "libresoc.v:128974.18-128974.134"
+ wire $and$libresoc.v:128974$5082_Y
+ attribute \src "libresoc.v:128975.18-128975.132"
+ wire $and$libresoc.v:128975$5083_Y
+ attribute \src "libresoc.v:128976.18-128976.149"
+ wire width 3 $and$libresoc.v:128976$5084_Y
+ attribute \src "libresoc.v:128947.18-128947.113"
+ wire $eq$libresoc.v:128947$5055_Y
+ attribute \src "libresoc.v:128949.18-128949.119"
+ wire $eq$libresoc.v:128949$5057_Y
+ attribute \src "libresoc.v:128914.19-128914.130"
+ wire $not$libresoc.v:128914$5022_Y
+ attribute \src "libresoc.v:128915.19-128915.136"
+ wire $not$libresoc.v:128915$5023_Y
+ attribute \src "libresoc.v:128917.19-128917.115"
+ wire width 3 $not$libresoc.v:128917$5025_Y
+ attribute \src "libresoc.v:128930.18-128930.97"
+ wire $not$libresoc.v:128930$5038_Y
+ attribute \src "libresoc.v:128932.18-128932.99"
+ wire $not$libresoc.v:128932$5040_Y
+ attribute \src "libresoc.v:128935.18-128935.113"
+ wire width 4 $not$libresoc.v:128935$5043_Y
+ attribute \src "libresoc.v:128938.18-128938.106"
+ wire $not$libresoc.v:128938$5046_Y
+ attribute \src "libresoc.v:128944.18-128944.120"
+ wire $not$libresoc.v:128944$5052_Y
+ attribute \src "libresoc.v:128955.17-128955.113"
+ wire width 3 $not$libresoc.v:128955$5063_Y
+ attribute \src "libresoc.v:128943.18-128943.112"
+ wire $or$libresoc.v:128943$5051_Y
+ attribute \src "libresoc.v:128953.18-128953.122"
+ wire $or$libresoc.v:128953$5061_Y
+ attribute \src "libresoc.v:128954.18-128954.124"
+ wire $or$libresoc.v:128954$5062_Y
+ attribute \src "libresoc.v:128956.18-128956.168"
+ wire width 4 $or$libresoc.v:128956$5064_Y
+ attribute \src "libresoc.v:128957.18-128957.155"
+ wire width 3 $or$libresoc.v:128957$5065_Y
+ attribute \src "libresoc.v:128960.18-128960.120"
+ wire width 4 $or$libresoc.v:128960$5068_Y
+ attribute \src "libresoc.v:128966.17-128966.117"
+ wire width 3 $or$libresoc.v:128966$5074_Y
+ attribute \src "libresoc.v:128971.17-128971.104"
+ wire $reduce_and$libresoc.v:128971$5079_Y
+ attribute \src "libresoc.v:128937.18-128937.106"
+ wire $reduce_or$libresoc.v:128937$5045_Y
+ attribute \src "libresoc.v:128941.18-128941.113"
+ wire $reduce_or$libresoc.v:128941$5049_Y
+ attribute \src "libresoc.v:128942.18-128942.112"
+ wire $reduce_or$libresoc.v:128942$5050_Y
+ attribute \src "libresoc.v:128965.18-128965.158"
+ wire $ternary$libresoc.v:128965$5073_Y
+ attribute \src "libresoc.v:128967.18-128967.159"
+ wire width 64 $ternary$libresoc.v:128967$5075_Y
+ attribute \src "libresoc.v:128968.18-128968.164"
+ wire $ternary$libresoc.v:128968$5076_Y
+ attribute \src "libresoc.v:128969.18-128969.180"
+ wire width 64 $ternary$libresoc.v:128969$5077_Y
+ attribute \src "libresoc.v:128970.18-128970.115"
+ wire width 64 $ternary$libresoc.v:128970$5078_Y
+ attribute \src "libresoc.v:128972.18-128972.125"
+ wire width 64 $ternary$libresoc.v:128972$5080_Y
+ attribute \src "libresoc.v:128973.18-128973.118"
+ wire $ternary$libresoc.v:128973$5081_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 32 \cr_a_ok
wire width 2 output 35 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire output 37 \dest4_o
- attribute \src "libresoc.v:129644.7-129644.15"
+ attribute \src "libresoc.v:128267.7-128267.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 36 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:130293$5080
+ cell $and $and$libresoc.v:128916$5024
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$98
connect \B { 1'1 \$102 \$100 }
- connect \Y $and$libresoc.v:130293$5080_Y
+ connect \Y $and$libresoc.v:128916$5024_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:130295$5082
+ cell $and $and$libresoc.v:128918$5026
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$104
connect \B \$106
- connect \Y $and$libresoc.v:130295$5082_Y
+ connect \Y $and$libresoc.v:128918$5026_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:130296$5083
+ cell $and $and$libresoc.v:128919$5027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:130296$5083_Y
+ connect \Y $and$libresoc.v:128919$5027_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:130297$5084
+ cell $and $and$libresoc.v:128920$5028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:130297$5084_Y
+ connect \Y $and$libresoc.v:128920$5028_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:130298$5085
+ cell $and $and$libresoc.v:128921$5029
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:130298$5085_Y
+ connect \Y $and$libresoc.v:128921$5029_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:130299$5086
+ cell $and $and$libresoc.v:128922$5030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:130299$5086_Y
+ connect \Y $and$libresoc.v:128922$5030_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:130300$5087
+ cell $and $and$libresoc.v:128923$5031
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:130300$5087_Y
+ connect \Y $and$libresoc.v:128923$5031_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:130301$5088
+ cell $and $and$libresoc.v:128924$5032
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B { \$110 \$112 \$114 \$116 }
- connect \Y $and$libresoc.v:130301$5088_Y
+ connect \Y $and$libresoc.v:128924$5032_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:130302$5089
+ cell $and $and$libresoc.v:128925$5033
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$118
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:130302$5089_Y
+ connect \Y $and$libresoc.v:128925$5033_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:130303$5090
+ cell $and $and$libresoc.v:128926$5034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130303$5090_Y
+ connect \Y $and$libresoc.v:128926$5034_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:130304$5091
+ cell $and $and$libresoc.v:128927$5035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130304$5091_Y
+ connect \Y $and$libresoc.v:128927$5035_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:130305$5092
+ cell $and $and$libresoc.v:128928$5036
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130305$5092_Y
+ connect \Y $and$libresoc.v:128928$5036_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:130306$5093
+ cell $and $and$libresoc.v:128929$5037
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130306$5093_Y
+ connect \Y $and$libresoc.v:128929$5037_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:130308$5095
+ cell $and $and$libresoc.v:128931$5039
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:130308$5095_Y
+ connect \Y $and$libresoc.v:128931$5039_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:130310$5097
+ cell $and $and$libresoc.v:128933$5041
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:130310$5097_Y
+ connect \Y $and$libresoc.v:128933$5041_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:130311$5098
+ cell $and $and$libresoc.v:128934$5042
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:130311$5098_Y
+ connect \Y $and$libresoc.v:128934$5042_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:130313$5100
+ cell $and $and$libresoc.v:128936$5044
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:130313$5100_Y
+ connect \Y $and$libresoc.v:128936$5044_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:130316$5103
+ cell $and $and$libresoc.v:128939$5047
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:130316$5103_Y
+ connect \Y $and$libresoc.v:128939$5047_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:130317$5104
+ cell $and $and$libresoc.v:128940$5048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:130317$5104_Y
+ connect \Y $and$libresoc.v:128940$5048_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:130322$5109
+ cell $and $and$libresoc.v:128945$5053
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:130322$5109_Y
+ connect \Y $and$libresoc.v:128945$5053_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:130323$5110
+ cell $and $and$libresoc.v:128946$5054
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:130323$5110_Y
+ connect \Y $and$libresoc.v:128946$5054_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:130325$5112
+ cell $and $and$libresoc.v:128948$5056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:130325$5112_Y
+ connect \Y $and$libresoc.v:128948$5056_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:130327$5114
+ cell $and $and$libresoc.v:128950$5058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_div0_n_ready_i
- connect \Y $and$libresoc.v:130327$5114_Y
+ connect \Y $and$libresoc.v:128950$5058_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:130328$5115
+ cell $and $and$libresoc.v:128951$5059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_div0_n_valid_o
- connect \Y $and$libresoc.v:130328$5115_Y
+ connect \Y $and$libresoc.v:128951$5059_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:130329$5116
+ cell $and $and$libresoc.v:128952$5060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130329$5116_Y
+ connect \Y $and$libresoc.v:128952$5060_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:130335$5122
+ cell $and $and$libresoc.v:128958$5066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130335$5122_Y
+ connect \Y $and$libresoc.v:128958$5066_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:130336$5123
+ cell $and $and$libresoc.v:128959$5067
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:130336$5123_Y
+ connect \Y $and$libresoc.v:128959$5067_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:130338$5125
+ cell $and $and$libresoc.v:128961$5069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130338$5125_Y
+ connect \Y $and$libresoc.v:128961$5069_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:130339$5126
+ cell $and $and$libresoc.v:128962$5070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130339$5126_Y
+ connect \Y $and$libresoc.v:128962$5070_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:130340$5127
+ cell $and $and$libresoc.v:128963$5071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130340$5127_Y
+ connect \Y $and$libresoc.v:128963$5071_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:130341$5128
+ cell $and $and$libresoc.v:128964$5072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:130341$5128_Y
+ connect \Y $and$libresoc.v:128964$5072_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:130351$5138
+ cell $and $and$libresoc.v:128974$5082
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:130351$5138_Y
+ connect \Y $and$libresoc.v:128974$5082_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:130352$5139
+ cell $and $and$libresoc.v:128975$5083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_div0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:130352$5139_Y
+ connect \Y $and$libresoc.v:128975$5083_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:130353$5140
+ cell $and $and$libresoc.v:128976$5084
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:130353$5140_Y
+ connect \Y $and$libresoc.v:128976$5084_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:130324$5111
+ cell $eq $eq$libresoc.v:128947$5055
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:130324$5111_Y
+ connect \Y $eq$libresoc.v:128947$5055_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:130326$5113
+ cell $eq $eq$libresoc.v:128949$5057
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:130326$5113_Y
+ connect \Y $eq$libresoc.v:128949$5057_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:130291$5078
+ cell $not $not$libresoc.v:128914$5022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_logical_op__zero_a
- connect \Y $not$libresoc.v:130291$5078_Y
+ connect \Y $not$libresoc.v:128914$5022_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:130292$5079
+ cell $not $not$libresoc.v:128915$5023
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_logical_op__imm_data__ok
- connect \Y $not$libresoc.v:130292$5079_Y
+ connect \Y $not$libresoc.v:128915$5023_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:130294$5081
+ cell $not $not$libresoc.v:128917$5025
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:130294$5081_Y
+ connect \Y $not$libresoc.v:128917$5025_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:130307$5094
+ cell $not $not$libresoc.v:128930$5038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:130307$5094_Y
+ connect \Y $not$libresoc.v:128930$5038_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:130309$5096
+ cell $not $not$libresoc.v:128932$5040
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:130309$5096_Y
+ connect \Y $not$libresoc.v:128932$5040_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:130312$5099
+ cell $not $not$libresoc.v:128935$5043
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:130312$5099_Y
+ connect \Y $not$libresoc.v:128935$5043_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:130315$5102
+ cell $not $not$libresoc.v:128938$5046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:130315$5102_Y
+ connect \Y $not$libresoc.v:128938$5046_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:130321$5108
+ cell $not $not$libresoc.v:128944$5052
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_div0_n_ready_i
- connect \Y $not$libresoc.v:130321$5108_Y
+ connect \Y $not$libresoc.v:128944$5052_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:130332$5119
+ cell $not $not$libresoc.v:128955$5063
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:130332$5119_Y
+ connect \Y $not$libresoc.v:128955$5063_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:130320$5107
+ cell $or $or$libresoc.v:128943$5051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:130320$5107_Y
+ connect \Y $or$libresoc.v:128943$5051_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:130330$5117
+ cell $or $or$libresoc.v:128953$5061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:130330$5117_Y
+ connect \Y $or$libresoc.v:128953$5061_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:130331$5118
+ cell $or $or$libresoc.v:128954$5062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:130331$5118_Y
+ connect \Y $or$libresoc.v:128954$5062_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:130333$5120
+ cell $or $or$libresoc.v:128956$5064
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:130333$5120_Y
+ connect \Y $or$libresoc.v:128956$5064_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:130334$5121
+ cell $or $or$libresoc.v:128957$5065
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:130334$5121_Y
+ connect \Y $or$libresoc.v:128957$5065_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:130337$5124
+ cell $or $or$libresoc.v:128960$5068
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:130337$5124_Y
+ connect \Y $or$libresoc.v:128960$5068_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:130343$5130
+ cell $or $or$libresoc.v:128966$5074
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:130343$5130_Y
+ connect \Y $or$libresoc.v:128966$5074_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:130348$5135
+ cell $reduce_and $reduce_and$libresoc.v:128971$5079
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:130348$5135_Y
+ connect \Y $reduce_and$libresoc.v:128971$5079_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:130314$5101
+ cell $reduce_or $reduce_or$libresoc.v:128937$5045
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:130314$5101_Y
+ connect \Y $reduce_or$libresoc.v:128937$5045_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:130318$5105
+ cell $reduce_or $reduce_or$libresoc.v:128941$5049
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:130318$5105_Y
+ connect \Y $reduce_or$libresoc.v:128941$5049_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:130319$5106
+ cell $reduce_or $reduce_or$libresoc.v:128942$5050
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:130319$5106_Y
+ connect \Y $reduce_or$libresoc.v:128942$5050_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:130342$5129
+ cell $mux $ternary$libresoc.v:128965$5073
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \alu_div0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:130342$5129_Y
+ connect \Y $ternary$libresoc.v:128965$5073_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:130344$5131
+ cell $mux $ternary$libresoc.v:128967$5075
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \alu_div0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:130344$5131_Y
+ connect \Y $ternary$libresoc.v:128967$5075_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:130345$5132
+ cell $mux $ternary$libresoc.v:128968$5076
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_div0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:130345$5132_Y
+ connect \Y $ternary$libresoc.v:128968$5076_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:130346$5133
+ cell $mux $ternary$libresoc.v:128969$5077
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_div0_logical_op__imm_data__data
connect \S \alu_div0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:130346$5133_Y
+ connect \Y $ternary$libresoc.v:128969$5077_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:130347$5134
+ cell $mux $ternary$libresoc.v:128970$5078
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:130347$5134_Y
+ connect \Y $ternary$libresoc.v:128970$5078_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:130349$5136
+ cell $mux $ternary$libresoc.v:128972$5080
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm$85
connect \S \src_sel$82
- connect \Y $ternary$libresoc.v:130349$5136_Y
+ connect \Y $ternary$libresoc.v:128972$5080_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:130350$5137
+ cell $mux $ternary$libresoc.v:128973$5081
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:130350$5137_Y
+ connect \Y $ternary$libresoc.v:128973$5081_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130442.12-130478.4"
+ attribute \src "libresoc.v:129065.12-129101.4"
cell \alu_div0 \alu_div0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130479.14-130485.4"
+ attribute \src "libresoc.v:129102.14-129108.4"
cell \alu_l$90 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130486.15-130492.4"
+ attribute \src "libresoc.v:129109.15-129115.4"
cell \alui_l$89 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130493.14-130499.4"
+ attribute \src "libresoc.v:129116.14-129122.4"
cell \opc_l$85 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130500.14-130506.4"
+ attribute \src "libresoc.v:129123.14-129129.4"
cell \req_l$86 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130507.14-130513.4"
+ attribute \src "libresoc.v:129130.14-129136.4"
cell \rok_l$88 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130514.14-130519.4"
+ attribute \src "libresoc.v:129137.14-129142.4"
cell \rst_l$87 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:130520.14-130526.4"
+ attribute \src "libresoc.v:129143.14-129149.4"
cell \src_l$84 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:129644.7-129644.20"
- process $proc$libresoc.v:129644$5313
+ attribute \src "libresoc.v:128267.7-128267.20"
+ process $proc$libresoc.v:128267$5257
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:129774.7-129774.24"
- process $proc$libresoc.v:129774$5314
+ attribute \src "libresoc.v:128397.7-128397.24"
+ process $proc$libresoc.v:128397$5258
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:129784.13-129784.49"
- process $proc$libresoc.v:129784$5315
+ attribute \src "libresoc.v:128407.13-128407.49"
+ process $proc$libresoc.v:128407$5259
assign { } { }
assign $1\alu_div0_logical_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:129802.14-129802.53"
- process $proc$libresoc.v:129802$5316
+ attribute \src "libresoc.v:128425.14-128425.53"
+ process $proc$libresoc.v:128425$5260
assign { } { }
assign $1\alu_div0_logical_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:129806.14-129806.72"
- process $proc$libresoc.v:129806$5317
+ attribute \src "libresoc.v:128429.14-128429.72"
+ process $proc$libresoc.v:128429$5261
assign { } { }
assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:129810.7-129810.47"
- process $proc$libresoc.v:129810$5318
+ attribute \src "libresoc.v:128433.7-128433.47"
+ process $proc$libresoc.v:128433$5262
assign { } { }
assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:129818.13-129818.52"
- process $proc$libresoc.v:129818$5319
+ attribute \src "libresoc.v:128441.13-128441.52"
+ process $proc$libresoc.v:128441$5263
assign { } { }
assign $1\alu_div0_logical_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:129822.14-129822.47"
- process $proc$libresoc.v:129822$5320
+ attribute \src "libresoc.v:128445.14-128445.47"
+ process $proc$libresoc.v:128445$5264
assign { } { }
assign $1\alu_div0_logical_op__insn[31:0] 0
sync always
sync init
update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:129900.13-129900.51"
- process $proc$libresoc.v:129900$5321
+ attribute \src "libresoc.v:128523.13-128523.51"
+ process $proc$libresoc.v:128523$5265
assign { } { }
assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:129904.7-129904.44"
- process $proc$libresoc.v:129904$5322
+ attribute \src "libresoc.v:128527.7-128527.44"
+ process $proc$libresoc.v:128527$5266
assign { } { }
assign $1\alu_div0_logical_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:129908.7-129908.45"
- process $proc$libresoc.v:129908$5323
+ attribute \src "libresoc.v:128531.7-128531.45"
+ process $proc$libresoc.v:128531$5267
assign { } { }
assign $1\alu_div0_logical_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:129912.7-129912.43"
- process $proc$libresoc.v:129912$5324
+ attribute \src "libresoc.v:128535.7-128535.43"
+ process $proc$libresoc.v:128535$5268
assign { } { }
assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:129916.7-129916.44"
- process $proc$libresoc.v:129916$5325
+ attribute \src "libresoc.v:128539.7-128539.44"
+ process $proc$libresoc.v:128539$5269
assign { } { }
assign $1\alu_div0_logical_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:129920.7-129920.41"
- process $proc$libresoc.v:129920$5326
+ attribute \src "libresoc.v:128543.7-128543.41"
+ process $proc$libresoc.v:128543$5270
assign { } { }
assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:129924.7-129924.41"
- process $proc$libresoc.v:129924$5327
+ attribute \src "libresoc.v:128547.7-128547.41"
+ process $proc$libresoc.v:128547$5271
assign { } { }
assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:129928.7-129928.47"
- process $proc$libresoc.v:129928$5328
+ attribute \src "libresoc.v:128551.7-128551.47"
+ process $proc$libresoc.v:128551$5272
assign { } { }
assign $1\alu_div0_logical_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:129932.7-129932.41"
- process $proc$libresoc.v:129932$5329
+ attribute \src "libresoc.v:128555.7-128555.41"
+ process $proc$libresoc.v:128555$5273
assign { } { }
assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:129936.7-129936.41"
- process $proc$libresoc.v:129936$5330
+ attribute \src "libresoc.v:128559.7-128559.41"
+ process $proc$libresoc.v:128559$5274
assign { } { }
assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:129940.7-129940.44"
- process $proc$libresoc.v:129940$5331
+ attribute \src "libresoc.v:128563.7-128563.44"
+ process $proc$libresoc.v:128563$5275
assign { } { }
assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:129944.7-129944.41"
- process $proc$libresoc.v:129944$5332
+ attribute \src "libresoc.v:128567.7-128567.41"
+ process $proc$libresoc.v:128567$5276
assign { } { }
assign $1\alu_div0_logical_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:129970.7-129970.26"
- process $proc$libresoc.v:129970$5333
+ attribute \src "libresoc.v:128593.7-128593.26"
+ process $proc$libresoc.v:128593$5277
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:129978.7-129978.25"
- process $proc$libresoc.v:129978$5334
+ attribute \src "libresoc.v:128601.7-128601.25"
+ process $proc$libresoc.v:128601$5278
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:129990.7-129990.27"
- process $proc$libresoc.v:129990$5335
+ attribute \src "libresoc.v:128613.7-128613.27"
+ process $proc$libresoc.v:128613$5279
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:130024.14-130024.47"
- process $proc$libresoc.v:130024$5336
+ attribute \src "libresoc.v:128647.14-128647.47"
+ process $proc$libresoc.v:128647$5280
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:130028.7-130028.27"
- process $proc$libresoc.v:130028$5337
+ attribute \src "libresoc.v:128651.7-128651.27"
+ process $proc$libresoc.v:128651$5281
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:130032.13-130032.33"
- process $proc$libresoc.v:130032$5338
+ attribute \src "libresoc.v:128655.13-128655.33"
+ process $proc$libresoc.v:128655$5282
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:130036.7-130036.30"
- process $proc$libresoc.v:130036$5339
+ attribute \src "libresoc.v:128659.7-128659.30"
+ process $proc$libresoc.v:128659$5283
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:130040.13-130040.35"
- process $proc$libresoc.v:130040$5340
+ attribute \src "libresoc.v:128663.13-128663.35"
+ process $proc$libresoc.v:128663$5284
assign { } { }
assign $1\data_r2__xer_ov[1:0] 2'00
sync always
sync init
update \data_r2__xer_ov $1\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:130044.7-130044.32"
- process $proc$libresoc.v:130044$5341
+ attribute \src "libresoc.v:128667.7-128667.32"
+ process $proc$libresoc.v:128667$5285
assign { } { }
assign $1\data_r2__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:130048.7-130048.29"
- process $proc$libresoc.v:130048$5342
+ attribute \src "libresoc.v:128671.7-128671.29"
+ process $proc$libresoc.v:128671$5286
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:130052.7-130052.32"
- process $proc$libresoc.v:130052$5343
+ attribute \src "libresoc.v:128675.7-128675.32"
+ process $proc$libresoc.v:128675$5287
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:130072.7-130072.25"
- process $proc$libresoc.v:130072$5344
+ attribute \src "libresoc.v:128695.7-128695.25"
+ process $proc$libresoc.v:128695$5288
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:130076.7-130076.25"
- process $proc$libresoc.v:130076$5345
+ attribute \src "libresoc.v:128699.7-128699.25"
+ process $proc$libresoc.v:128699$5289
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:130208.13-130208.30"
- process $proc$libresoc.v:130208$5346
+ attribute \src "libresoc.v:128831.13-128831.30"
+ process $proc$libresoc.v:128831$5290
assign { } { }
assign $1\prev_wr_go[3:0] 4'0000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:130216.13-130216.31"
- process $proc$libresoc.v:130216$5347
+ attribute \src "libresoc.v:128839.13-128839.31"
+ process $proc$libresoc.v:128839$5291
assign { } { }
assign $1\req_l_r_req[3:0] 4'1111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:130220.13-130220.31"
- process $proc$libresoc.v:130220$5348
+ attribute \src "libresoc.v:128843.13-128843.31"
+ process $proc$libresoc.v:128843$5292
assign { } { }
assign $1\req_l_s_req[3:0] 4'0000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:130232.7-130232.26"
- process $proc$libresoc.v:130232$5349
+ attribute \src "libresoc.v:128855.7-128855.26"
+ process $proc$libresoc.v:128855$5293
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:130236.7-130236.26"
- process $proc$libresoc.v:130236$5350
+ attribute \src "libresoc.v:128859.7-128859.26"
+ process $proc$libresoc.v:128859$5294
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:130240.7-130240.25"
- process $proc$libresoc.v:130240$5351
+ attribute \src "libresoc.v:128863.7-128863.25"
+ process $proc$libresoc.v:128863$5295
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:130244.7-130244.25"
- process $proc$libresoc.v:130244$5352
+ attribute \src "libresoc.v:128867.7-128867.25"
+ process $proc$libresoc.v:128867$5296
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:130258.13-130258.31"
- process $proc$libresoc.v:130258$5353
+ attribute \src "libresoc.v:128881.13-128881.31"
+ process $proc$libresoc.v:128881$5297
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:130262.13-130262.31"
- process $proc$libresoc.v:130262$5354
+ attribute \src "libresoc.v:128885.13-128885.31"
+ process $proc$libresoc.v:128885$5298
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:130270.14-130270.43"
- process $proc$libresoc.v:130270$5355
+ attribute \src "libresoc.v:128893.14-128893.43"
+ process $proc$libresoc.v:128893$5299
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:130274.14-130274.43"
- process $proc$libresoc.v:130274$5356
+ attribute \src "libresoc.v:128897.14-128897.43"
+ process $proc$libresoc.v:128897$5300
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:130278.7-130278.20"
- process $proc$libresoc.v:130278$5357
+ attribute \src "libresoc.v:128901.7-128901.20"
+ process $proc$libresoc.v:128901$5301
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:130354.3-130355.39"
- process $proc$libresoc.v:130354$5141
+ attribute \src "libresoc.v:128977.3-128978.39"
+ process $proc$libresoc.v:128977$5085
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:130356.3-130357.43"
- process $proc$libresoc.v:130356$5142
+ attribute \src "libresoc.v:128979.3-128980.43"
+ process $proc$libresoc.v:128979$5086
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:130358.3-130359.29"
- process $proc$libresoc.v:130358$5143
+ attribute \src "libresoc.v:128981.3-128982.29"
+ process $proc$libresoc.v:128981$5087
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:130360.3-130361.29"
- process $proc$libresoc.v:130360$5144
+ attribute \src "libresoc.v:128983.3-128984.29"
+ process $proc$libresoc.v:128983$5088
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:130362.3-130363.29"
- process $proc$libresoc.v:130362$5145
+ attribute \src "libresoc.v:128985.3-128986.29"
+ process $proc$libresoc.v:128985$5089
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:130364.3-130365.47"
- process $proc$libresoc.v:130364$5146
+ attribute \src "libresoc.v:128987.3-128988.47"
+ process $proc$libresoc.v:128987$5090
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:130366.3-130367.53"
- process $proc$libresoc.v:130366$5147
+ attribute \src "libresoc.v:128989.3-128990.53"
+ process $proc$libresoc.v:128989$5091
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:130368.3-130369.47"
- process $proc$libresoc.v:130368$5148
+ attribute \src "libresoc.v:128991.3-128992.47"
+ process $proc$libresoc.v:128991$5092
assign { } { }
assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next
sync posedge \coresync_clk
update \data_r2__xer_ov $0\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:130370.3-130371.53"
- process $proc$libresoc.v:130370$5149
+ attribute \src "libresoc.v:128993.3-128994.53"
+ process $proc$libresoc.v:128993$5093
assign { } { }
assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:130372.3-130373.43"
- process $proc$libresoc.v:130372$5150
+ attribute \src "libresoc.v:128995.3-128996.43"
+ process $proc$libresoc.v:128995$5094
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:130374.3-130375.49"
- process $proc$libresoc.v:130374$5151
+ attribute \src "libresoc.v:128997.3-128998.49"
+ process $proc$libresoc.v:128997$5095
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:130376.3-130377.37"
- process $proc$libresoc.v:130376$5152
+ attribute \src "libresoc.v:128999.3-129000.37"
+ process $proc$libresoc.v:128999$5096
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:130378.3-130379.43"
- process $proc$libresoc.v:130378$5153
+ attribute \src "libresoc.v:129001.3-129002.43"
+ process $proc$libresoc.v:129001$5097
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:130380.3-130381.77"
- process $proc$libresoc.v:130380$5154
+ attribute \src "libresoc.v:129003.3-129004.77"
+ process $proc$libresoc.v:129003$5098
assign { } { }
assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next
sync posedge \coresync_clk
update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:130382.3-130383.73"
- process $proc$libresoc.v:130382$5155
+ attribute \src "libresoc.v:129005.3-129006.73"
+ process $proc$libresoc.v:129005$5099
assign { } { }
assign $0\alu_div0_logical_op__fn_unit[12:0] \alu_div0_logical_op__fn_unit$next
sync posedge \coresync_clk
update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:130384.3-130385.87"
- process $proc$libresoc.v:130384$5156
+ attribute \src "libresoc.v:129007.3-129008.87"
+ process $proc$libresoc.v:129007$5100
assign { } { }
assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:130386.3-130387.83"
- process $proc$libresoc.v:130386$5157
+ attribute \src "libresoc.v:129009.3-129010.83"
+ process $proc$libresoc.v:129009$5101
assign { } { }
assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:130388.3-130389.71"
- process $proc$libresoc.v:130388$5158
+ attribute \src "libresoc.v:129011.3-129012.71"
+ process $proc$libresoc.v:129011$5102
assign { } { }
assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next
sync posedge \coresync_clk
update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:130390.3-130391.71"
- process $proc$libresoc.v:130390$5159
+ attribute \src "libresoc.v:129013.3-129014.71"
+ process $proc$libresoc.v:129013$5103
assign { } { }
assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:130392.3-130393.71"
- process $proc$libresoc.v:130392$5160
+ attribute \src "libresoc.v:129015.3-129016.71"
+ process $proc$libresoc.v:129015$5104
assign { } { }
assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next
sync posedge \coresync_clk
update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:130394.3-130395.71"
- process $proc$libresoc.v:130394$5161
+ attribute \src "libresoc.v:129017.3-129018.71"
+ process $proc$libresoc.v:129017$5105
assign { } { }
assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next
sync posedge \coresync_clk
update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:130396.3-130397.77"
- process $proc$libresoc.v:130396$5162
+ attribute \src "libresoc.v:129019.3-129020.77"
+ process $proc$libresoc.v:129019$5106
assign { } { }
assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next
sync posedge \coresync_clk
update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:130398.3-130399.71"
- process $proc$libresoc.v:130398$5163
+ attribute \src "libresoc.v:129021.3-129022.71"
+ process $proc$libresoc.v:129021$5107
assign { } { }
assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next
sync posedge \coresync_clk
update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:130400.3-130401.81"
- process $proc$libresoc.v:130400$5164
+ attribute \src "libresoc.v:129023.3-129024.81"
+ process $proc$libresoc.v:129023$5108
assign { } { }
assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next
sync posedge \coresync_clk
update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:130402.3-130403.79"
- process $proc$libresoc.v:130402$5165
+ attribute \src "libresoc.v:129025.3-129026.79"
+ process $proc$libresoc.v:129025$5109
assign { } { }
assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next
sync posedge \coresync_clk
update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:130404.3-130405.77"
- process $proc$libresoc.v:130404$5166
+ attribute \src "libresoc.v:129027.3-129028.77"
+ process $proc$libresoc.v:129027$5110
assign { } { }
assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next
sync posedge \coresync_clk
update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:130406.3-130407.83"
- process $proc$libresoc.v:130406$5167
+ attribute \src "libresoc.v:129029.3-129030.83"
+ process $proc$libresoc.v:129029$5111
assign { } { }
assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next
sync posedge \coresync_clk
update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:130408.3-130409.75"
- process $proc$libresoc.v:130408$5168
+ attribute \src "libresoc.v:129031.3-129032.75"
+ process $proc$libresoc.v:129031$5112
assign { } { }
assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next
sync posedge \coresync_clk
update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:130410.3-130411.77"
- process $proc$libresoc.v:130410$5169
+ attribute \src "libresoc.v:129033.3-129034.77"
+ process $proc$libresoc.v:129033$5113
assign { } { }
assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next
sync posedge \coresync_clk
update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:130412.3-130413.75"
- process $proc$libresoc.v:130412$5170
+ attribute \src "libresoc.v:129035.3-129036.75"
+ process $proc$libresoc.v:129035$5114
assign { } { }
assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next
sync posedge \coresync_clk
update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:130414.3-130415.67"
- process $proc$libresoc.v:130414$5171
+ attribute \src "libresoc.v:129037.3-129038.67"
+ process $proc$libresoc.v:129037$5115
assign { } { }
assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next
sync posedge \coresync_clk
update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:130416.3-130417.39"
- process $proc$libresoc.v:130416$5172
+ attribute \src "libresoc.v:129039.3-129040.39"
+ process $proc$libresoc.v:129039$5116
assign { } { }
assign $0\req_l_r_req[3:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:130418.3-130419.39"
- process $proc$libresoc.v:130418$5173
+ attribute \src "libresoc.v:129041.3-129042.39"
+ process $proc$libresoc.v:129041$5117
assign { } { }
assign $0\req_l_s_req[3:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:130420.3-130421.39"
- process $proc$libresoc.v:130420$5174
+ attribute \src "libresoc.v:129043.3-129044.39"
+ process $proc$libresoc.v:129043$5118
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:130422.3-130423.39"
- process $proc$libresoc.v:130422$5175
+ attribute \src "libresoc.v:129045.3-129046.39"
+ process $proc$libresoc.v:129045$5119
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:130424.3-130425.39"
- process $proc$libresoc.v:130424$5176
+ attribute \src "libresoc.v:129047.3-129048.39"
+ process $proc$libresoc.v:129047$5120
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:130426.3-130427.39"
- process $proc$libresoc.v:130426$5177
+ attribute \src "libresoc.v:129049.3-129050.39"
+ process $proc$libresoc.v:129049$5121
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:130428.3-130429.39"
- process $proc$libresoc.v:130428$5178
+ attribute \src "libresoc.v:129051.3-129052.39"
+ process $proc$libresoc.v:129051$5122
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:130430.3-130431.39"
- process $proc$libresoc.v:130430$5179
+ attribute \src "libresoc.v:129053.3-129054.39"
+ process $proc$libresoc.v:129053$5123
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:130432.3-130433.41"
- process $proc$libresoc.v:130432$5180
+ attribute \src "libresoc.v:129055.3-129056.41"
+ process $proc$libresoc.v:129055$5124
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:130434.3-130435.41"
- process $proc$libresoc.v:130434$5181
+ attribute \src "libresoc.v:129057.3-129058.41"
+ process $proc$libresoc.v:129057$5125
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:130436.3-130437.37"
- process $proc$libresoc.v:130436$5182
+ attribute \src "libresoc.v:129059.3-129060.37"
+ process $proc$libresoc.v:129059$5126
assign { } { }
assign $0\prev_wr_go[3:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:130438.3-130439.40"
- process $proc$libresoc.v:130438$5183
+ attribute \src "libresoc.v:129061.3-129062.40"
+ process $proc$libresoc.v:129061$5127
assign { } { }
assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:130440.3-130441.25"
- process $proc$libresoc.v:130440$5184
+ attribute \src "libresoc.v:129063.3-129064.25"
+ process $proc$libresoc.v:129063$5128
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:130527.3-130536.6"
- process $proc$libresoc.v:130527$5185
+ attribute \src "libresoc.v:129150.3-129159.6"
+ process $proc$libresoc.v:129150$5129
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:130528.5-130528.29"
+ attribute \src "libresoc.v:129151.5-129151.29"
switch \initial
- attribute \src "libresoc.v:130528.9-130528.17"
+ attribute \src "libresoc.v:129151.9-129151.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:130537.3-130545.6"
- process $proc$libresoc.v:130537$5186
+ attribute \src "libresoc.v:129160.3-129168.6"
+ process $proc$libresoc.v:129160$5130
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$5187 $1\rok_l_s_rdok$next[0:0]$5188
- attribute \src "libresoc.v:130538.5-130538.29"
+ assign $0\rok_l_s_rdok$next[0:0]$5131 $1\rok_l_s_rdok$next[0:0]$5132
+ attribute \src "libresoc.v:129161.5-129161.29"
switch \initial
- attribute \src "libresoc.v:130538.9-130538.17"
+ attribute \src "libresoc.v:129161.9-129161.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$5188 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$5132 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$5188 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$5132 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5187
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5131
end
- attribute \src "libresoc.v:130546.3-130554.6"
- process $proc$libresoc.v:130546$5189
+ attribute \src "libresoc.v:129169.3-129177.6"
+ process $proc$libresoc.v:129169$5133
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$5190 $1\rok_l_r_rdok$next[0:0]$5191
- attribute \src "libresoc.v:130547.5-130547.29"
+ assign $0\rok_l_r_rdok$next[0:0]$5134 $1\rok_l_r_rdok$next[0:0]$5135
+ attribute \src "libresoc.v:129170.5-129170.29"
switch \initial
- attribute \src "libresoc.v:130547.9-130547.17"
+ attribute \src "libresoc.v:129170.9-129170.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$5191 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$5135 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$5191 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$5135 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5190
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5134
end
- attribute \src "libresoc.v:130555.3-130563.6"
- process $proc$libresoc.v:130555$5192
+ attribute \src "libresoc.v:129178.3-129186.6"
+ process $proc$libresoc.v:129178$5136
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$5193 $1\rst_l_s_rst$next[0:0]$5194
- attribute \src "libresoc.v:130556.5-130556.29"
+ assign $0\rst_l_s_rst$next[0:0]$5137 $1\rst_l_s_rst$next[0:0]$5138
+ attribute \src "libresoc.v:129179.5-129179.29"
switch \initial
- attribute \src "libresoc.v:130556.9-130556.17"
+ attribute \src "libresoc.v:129179.9-129179.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$5194 1'0
+ assign $1\rst_l_s_rst$next[0:0]$5138 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$5194 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$5138 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5193
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5137
end
- attribute \src "libresoc.v:130564.3-130572.6"
- process $proc$libresoc.v:130564$5195
+ attribute \src "libresoc.v:129187.3-129195.6"
+ process $proc$libresoc.v:129187$5139
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$5196 $1\rst_l_r_rst$next[0:0]$5197
- attribute \src "libresoc.v:130565.5-130565.29"
+ assign $0\rst_l_r_rst$next[0:0]$5140 $1\rst_l_r_rst$next[0:0]$5141
+ attribute \src "libresoc.v:129188.5-129188.29"
switch \initial
- attribute \src "libresoc.v:130565.9-130565.17"
+ attribute \src "libresoc.v:129188.9-129188.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$5197 1'1
+ assign $1\rst_l_r_rst$next[0:0]$5141 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$5197 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$5141 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5196
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5140
end
- attribute \src "libresoc.v:130573.3-130581.6"
- process $proc$libresoc.v:130573$5198
+ attribute \src "libresoc.v:129196.3-129204.6"
+ process $proc$libresoc.v:129196$5142
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$5199 $1\opc_l_s_opc$next[0:0]$5200
- attribute \src "libresoc.v:130574.5-130574.29"
+ assign $0\opc_l_s_opc$next[0:0]$5143 $1\opc_l_s_opc$next[0:0]$5144
+ attribute \src "libresoc.v:129197.5-129197.29"
switch \initial
- attribute \src "libresoc.v:130574.9-130574.17"
+ attribute \src "libresoc.v:129197.9-129197.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$5200 1'0
+ assign $1\opc_l_s_opc$next[0:0]$5144 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$5200 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$5144 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5199
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5143
end
- attribute \src "libresoc.v:130582.3-130590.6"
- process $proc$libresoc.v:130582$5201
+ attribute \src "libresoc.v:129205.3-129213.6"
+ process $proc$libresoc.v:129205$5145
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$5202 $1\opc_l_r_opc$next[0:0]$5203
- attribute \src "libresoc.v:130583.5-130583.29"
+ assign $0\opc_l_r_opc$next[0:0]$5146 $1\opc_l_r_opc$next[0:0]$5147
+ attribute \src "libresoc.v:129206.5-129206.29"
switch \initial
- attribute \src "libresoc.v:130583.9-130583.17"
+ attribute \src "libresoc.v:129206.9-129206.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$5203 1'1
+ assign $1\opc_l_r_opc$next[0:0]$5147 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$5203 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$5147 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5202
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5146
end
- attribute \src "libresoc.v:130591.3-130599.6"
- process $proc$libresoc.v:130591$5204
+ attribute \src "libresoc.v:129214.3-129222.6"
+ process $proc$libresoc.v:129214$5148
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$5205 $1\src_l_s_src$next[2:0]$5206
- attribute \src "libresoc.v:130592.5-130592.29"
+ assign $0\src_l_s_src$next[2:0]$5149 $1\src_l_s_src$next[2:0]$5150
+ attribute \src "libresoc.v:129215.5-129215.29"
switch \initial
- attribute \src "libresoc.v:130592.9-130592.17"
+ attribute \src "libresoc.v:129215.9-129215.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$5206 3'000
+ assign $1\src_l_s_src$next[2:0]$5150 3'000
case
- assign $1\src_l_s_src$next[2:0]$5206 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$5150 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5205
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5149
end
- attribute \src "libresoc.v:130600.3-130608.6"
- process $proc$libresoc.v:130600$5207
+ attribute \src "libresoc.v:129223.3-129231.6"
+ process $proc$libresoc.v:129223$5151
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$5208 $1\src_l_r_src$next[2:0]$5209
- attribute \src "libresoc.v:130601.5-130601.29"
+ assign $0\src_l_r_src$next[2:0]$5152 $1\src_l_r_src$next[2:0]$5153
+ attribute \src "libresoc.v:129224.5-129224.29"
switch \initial
- attribute \src "libresoc.v:130601.9-130601.17"
+ attribute \src "libresoc.v:129224.9-129224.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$5209 3'111
+ assign $1\src_l_r_src$next[2:0]$5153 3'111
case
- assign $1\src_l_r_src$next[2:0]$5209 \reset_r
+ assign $1\src_l_r_src$next[2:0]$5153 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5208
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5152
end
- attribute \src "libresoc.v:130609.3-130617.6"
- process $proc$libresoc.v:130609$5210
+ attribute \src "libresoc.v:129232.3-129240.6"
+ process $proc$libresoc.v:129232$5154
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[3:0]$5211 $1\req_l_s_req$next[3:0]$5212
- attribute \src "libresoc.v:130610.5-130610.29"
+ assign $0\req_l_s_req$next[3:0]$5155 $1\req_l_s_req$next[3:0]$5156
+ attribute \src "libresoc.v:129233.5-129233.29"
switch \initial
- attribute \src "libresoc.v:130610.9-130610.17"
+ attribute \src "libresoc.v:129233.9-129233.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[3:0]$5212 4'0000
+ assign $1\req_l_s_req$next[3:0]$5156 4'0000
case
- assign $1\req_l_s_req$next[3:0]$5212 \$66
+ assign $1\req_l_s_req$next[3:0]$5156 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5211
+ update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5155
end
- attribute \src "libresoc.v:130618.3-130626.6"
- process $proc$libresoc.v:130618$5213
+ attribute \src "libresoc.v:129241.3-129249.6"
+ process $proc$libresoc.v:129241$5157
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[3:0]$5214 $1\req_l_r_req$next[3:0]$5215
- attribute \src "libresoc.v:130619.5-130619.29"
+ assign $0\req_l_r_req$next[3:0]$5158 $1\req_l_r_req$next[3:0]$5159
+ attribute \src "libresoc.v:129242.5-129242.29"
switch \initial
- attribute \src "libresoc.v:130619.9-130619.17"
+ attribute \src "libresoc.v:129242.9-129242.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[3:0]$5215 4'1111
+ assign $1\req_l_r_req$next[3:0]$5159 4'1111
case
- assign $1\req_l_r_req$next[3:0]$5215 \$68
+ assign $1\req_l_r_req$next[3:0]$5159 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5214
+ update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5158
end
- attribute \src "libresoc.v:130627.3-130665.6"
- process $proc$libresoc.v:130627$5216
+ attribute \src "libresoc.v:129250.3-129288.6"
+ process $proc$libresoc.v:129250$5160
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__data_len$next[3:0]$5217 $1\alu_div0_logical_op__data_len$next[3:0]$5235
- assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5218 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236
+ assign $0\alu_div0_logical_op__data_len$next[3:0]$5161 $1\alu_div0_logical_op__data_len$next[3:0]$5179
+ assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5162 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__input_carry$next[1:0]$5221 $1\alu_div0_logical_op__input_carry$next[1:0]$5239
- assign $0\alu_div0_logical_op__insn$next[31:0]$5222 $1\alu_div0_logical_op__insn$next[31:0]$5240
- assign $0\alu_div0_logical_op__insn_type$next[6:0]$5223 $1\alu_div0_logical_op__insn_type$next[6:0]$5241
- assign $0\alu_div0_logical_op__invert_in$next[0:0]$5224 $1\alu_div0_logical_op__invert_in$next[0:0]$5242
- assign $0\alu_div0_logical_op__invert_out$next[0:0]$5225 $1\alu_div0_logical_op__invert_out$next[0:0]$5243
- assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5226 $1\alu_div0_logical_op__is_32bit$next[0:0]$5244
- assign $0\alu_div0_logical_op__is_signed$next[0:0]$5227 $1\alu_div0_logical_op__is_signed$next[0:0]$5245
+ assign $0\alu_div0_logical_op__input_carry$next[1:0]$5165 $1\alu_div0_logical_op__input_carry$next[1:0]$5183
+ assign $0\alu_div0_logical_op__insn$next[31:0]$5166 $1\alu_div0_logical_op__insn$next[31:0]$5184
+ assign $0\alu_div0_logical_op__insn_type$next[6:0]$5167 $1\alu_div0_logical_op__insn_type$next[6:0]$5185
+ assign $0\alu_div0_logical_op__invert_in$next[0:0]$5168 $1\alu_div0_logical_op__invert_in$next[0:0]$5186
+ assign $0\alu_div0_logical_op__invert_out$next[0:0]$5169 $1\alu_div0_logical_op__invert_out$next[0:0]$5187
+ assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5170 $1\alu_div0_logical_op__is_32bit$next[0:0]$5188
+ assign $0\alu_div0_logical_op__is_signed$next[0:0]$5171 $1\alu_div0_logical_op__is_signed$next[0:0]$5189
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__output_carry$next[0:0]$5230 $1\alu_div0_logical_op__output_carry$next[0:0]$5248
+ assign $0\alu_div0_logical_op__output_carry$next[0:0]$5174 $1\alu_div0_logical_op__output_carry$next[0:0]$5192
assign { } { }
assign { } { }
- assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5233 $1\alu_div0_logical_op__write_cr0$next[0:0]$5251
- assign $0\alu_div0_logical_op__zero_a$next[0:0]$5234 $1\alu_div0_logical_op__zero_a$next[0:0]$5252
- assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253
- assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254
- assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5228 $2\alu_div0_logical_op__oe__oe$next[0:0]$5255
- assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5229 $2\alu_div0_logical_op__oe__ok$next[0:0]$5256
- assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5231 $2\alu_div0_logical_op__rc__ok$next[0:0]$5257
- assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5232 $2\alu_div0_logical_op__rc__rc$next[0:0]$5258
- attribute \src "libresoc.v:130628.5-130628.29"
+ assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5177 $1\alu_div0_logical_op__write_cr0$next[0:0]$5195
+ assign $0\alu_div0_logical_op__zero_a$next[0:0]$5178 $1\alu_div0_logical_op__zero_a$next[0:0]$5196
+ assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197
+ assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198
+ assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5172 $2\alu_div0_logical_op__oe__oe$next[0:0]$5199
+ assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5173 $2\alu_div0_logical_op__oe__ok$next[0:0]$5200
+ assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5175 $2\alu_div0_logical_op__rc__ok$next[0:0]$5201
+ assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5176 $2\alu_div0_logical_op__rc__rc$next[0:0]$5202
+ attribute \src "libresoc.v:129251.5-129251.29"
switch \initial
- attribute \src "libresoc.v:130628.9-130628.17"
+ attribute \src "libresoc.v:129251.9-129251.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_div0_logical_op__insn$next[31:0]$5240 $1\alu_div0_logical_op__data_len$next[3:0]$5235 $1\alu_div0_logical_op__is_signed$next[0:0]$5245 $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 $1\alu_div0_logical_op__output_carry$next[0:0]$5248 $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 $1\alu_div0_logical_op__invert_out$next[0:0]$5243 $1\alu_div0_logical_op__input_carry$next[1:0]$5239 $1\alu_div0_logical_op__zero_a$next[0:0]$5252 $1\alu_div0_logical_op__invert_in$next[0:0]$5242 $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 $1\alu_div0_logical_op__insn_type$next[6:0]$5241 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
+ assign { $1\alu_div0_logical_op__insn$next[31:0]$5184 $1\alu_div0_logical_op__data_len$next[3:0]$5179 $1\alu_div0_logical_op__is_signed$next[0:0]$5189 $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 $1\alu_div0_logical_op__output_carry$next[0:0]$5192 $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 $1\alu_div0_logical_op__invert_out$next[0:0]$5187 $1\alu_div0_logical_op__input_carry$next[1:0]$5183 $1\alu_div0_logical_op__zero_a$next[0:0]$5196 $1\alu_div0_logical_op__invert_in$next[0:0]$5186 $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 $1\alu_div0_logical_op__insn_type$next[6:0]$5185 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
case
- assign $1\alu_div0_logical_op__data_len$next[3:0]$5235 \alu_div0_logical_op__data_len
- assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 \alu_div0_logical_op__fn_unit
- assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 \alu_div0_logical_op__imm_data__data
- assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 \alu_div0_logical_op__imm_data__ok
- assign $1\alu_div0_logical_op__input_carry$next[1:0]$5239 \alu_div0_logical_op__input_carry
- assign $1\alu_div0_logical_op__insn$next[31:0]$5240 \alu_div0_logical_op__insn
- assign $1\alu_div0_logical_op__insn_type$next[6:0]$5241 \alu_div0_logical_op__insn_type
- assign $1\alu_div0_logical_op__invert_in$next[0:0]$5242 \alu_div0_logical_op__invert_in
- assign $1\alu_div0_logical_op__invert_out$next[0:0]$5243 \alu_div0_logical_op__invert_out
- assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 \alu_div0_logical_op__is_32bit
- assign $1\alu_div0_logical_op__is_signed$next[0:0]$5245 \alu_div0_logical_op__is_signed
- assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 \alu_div0_logical_op__oe__oe
- assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 \alu_div0_logical_op__oe__ok
- assign $1\alu_div0_logical_op__output_carry$next[0:0]$5248 \alu_div0_logical_op__output_carry
- assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 \alu_div0_logical_op__rc__ok
- assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 \alu_div0_logical_op__rc__rc
- assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 \alu_div0_logical_op__write_cr0
- assign $1\alu_div0_logical_op__zero_a$next[0:0]$5252 \alu_div0_logical_op__zero_a
+ assign $1\alu_div0_logical_op__data_len$next[3:0]$5179 \alu_div0_logical_op__data_len
+ assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 \alu_div0_logical_op__fn_unit
+ assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 \alu_div0_logical_op__imm_data__data
+ assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 \alu_div0_logical_op__imm_data__ok
+ assign $1\alu_div0_logical_op__input_carry$next[1:0]$5183 \alu_div0_logical_op__input_carry
+ assign $1\alu_div0_logical_op__insn$next[31:0]$5184 \alu_div0_logical_op__insn
+ assign $1\alu_div0_logical_op__insn_type$next[6:0]$5185 \alu_div0_logical_op__insn_type
+ assign $1\alu_div0_logical_op__invert_in$next[0:0]$5186 \alu_div0_logical_op__invert_in
+ assign $1\alu_div0_logical_op__invert_out$next[0:0]$5187 \alu_div0_logical_op__invert_out
+ assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 \alu_div0_logical_op__is_32bit
+ assign $1\alu_div0_logical_op__is_signed$next[0:0]$5189 \alu_div0_logical_op__is_signed
+ assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 \alu_div0_logical_op__oe__oe
+ assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 \alu_div0_logical_op__oe__ok
+ assign $1\alu_div0_logical_op__output_carry$next[0:0]$5192 \alu_div0_logical_op__output_carry
+ assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 \alu_div0_logical_op__rc__ok
+ assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 \alu_div0_logical_op__rc__rc
+ assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 \alu_div0_logical_op__write_cr0
+ assign $1\alu_div0_logical_op__zero_a$next[0:0]$5196 \alu_div0_logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254 1'0
- assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5258 1'0
- assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5257 1'0
- assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5255 1'0
- assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5256 1'0
+ assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 1'0
+ assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 1'0
+ assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 1'0
+ assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 1'0
+ assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 1'0
case
- assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237
- assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238
- assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5255 $1\alu_div0_logical_op__oe__oe$next[0:0]$5246
- assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5256 $1\alu_div0_logical_op__oe__ok$next[0:0]$5247
- assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5257 $1\alu_div0_logical_op__rc__ok$next[0:0]$5249
- assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5258 $1\alu_div0_logical_op__rc__rc$next[0:0]$5250
+ assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181
+ assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182
+ assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 $1\alu_div0_logical_op__oe__oe$next[0:0]$5190
+ assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 $1\alu_div0_logical_op__oe__ok$next[0:0]$5191
+ assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 $1\alu_div0_logical_op__rc__ok$next[0:0]$5193
+ assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 $1\alu_div0_logical_op__rc__rc$next[0:0]$5194
end
sync always
- update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5217
- update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5218
- update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219
- update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220
- update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5221
- update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5222
- update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5223
- update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5224
- update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5225
- update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5226
- update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5227
- update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5228
- update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5229
- update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5230
- update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5231
- update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5232
- update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5233
- update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5234
+ update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5161
+ update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5162
+ update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163
+ update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164
+ update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5165
+ update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5166
+ update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5167
+ update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5168
+ update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5169
+ update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5170
+ update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5171
+ update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5172
+ update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5173
+ update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5174
+ update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5175
+ update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5176
+ update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5177
+ update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5178
end
- attribute \src "libresoc.v:130666.3-130687.6"
- process $proc$libresoc.v:130666$5259
+ attribute \src "libresoc.v:129289.3-129310.6"
+ process $proc$libresoc.v:129289$5203
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$5260 $2\data_r0__o$next[63:0]$5264
+ assign $0\data_r0__o$next[63:0]$5204 $2\data_r0__o$next[63:0]$5208
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$5261 $3\data_r0__o_ok$next[0:0]$5266
- attribute \src "libresoc.v:130667.5-130667.29"
+ assign $0\data_r0__o_ok$next[0:0]$5205 $3\data_r0__o_ok$next[0:0]$5210
+ attribute \src "libresoc.v:129290.5-129290.29"
switch \initial
- attribute \src "libresoc.v:130667.9-130667.17"
+ attribute \src "libresoc.v:129290.9-129290.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$5263 $1\data_r0__o$next[63:0]$5262 } { \o_ok \alu_div0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$5207 $1\data_r0__o$next[63:0]$5206 } { \o_ok \alu_div0_o }
case
- assign $1\data_r0__o$next[63:0]$5262 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$5263 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$5206 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$5207 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$5265 $2\data_r0__o$next[63:0]$5264 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$5209 $2\data_r0__o$next[63:0]$5208 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$5264 $1\data_r0__o$next[63:0]$5262
- assign $2\data_r0__o_ok$next[0:0]$5265 $1\data_r0__o_ok$next[0:0]$5263
+ assign $2\data_r0__o$next[63:0]$5208 $1\data_r0__o$next[63:0]$5206
+ assign $2\data_r0__o_ok$next[0:0]$5209 $1\data_r0__o_ok$next[0:0]$5207
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$5266 1'0
+ assign $3\data_r0__o_ok$next[0:0]$5210 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$5266 $2\data_r0__o_ok$next[0:0]$5265
+ assign $3\data_r0__o_ok$next[0:0]$5210 $2\data_r0__o_ok$next[0:0]$5209
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$5260
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5261
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$5204
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5205
end
- attribute \src "libresoc.v:130688.3-130709.6"
- process $proc$libresoc.v:130688$5267
+ attribute \src "libresoc.v:129311.3-129332.6"
+ process $proc$libresoc.v:129311$5211
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$5268 $2\data_r1__cr_a$next[3:0]$5272
+ assign $0\data_r1__cr_a$next[3:0]$5212 $2\data_r1__cr_a$next[3:0]$5216
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$5269 $3\data_r1__cr_a_ok$next[0:0]$5274
- attribute \src "libresoc.v:130689.5-130689.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$5213 $3\data_r1__cr_a_ok$next[0:0]$5218
+ attribute \src "libresoc.v:129312.5-129312.29"
switch \initial
- attribute \src "libresoc.v:130689.9-130689.17"
+ attribute \src "libresoc.v:129312.9-129312.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$5271 $1\data_r1__cr_a$next[3:0]$5270 } { \cr_a_ok \alu_div0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$5215 $1\data_r1__cr_a$next[3:0]$5214 } { \cr_a_ok \alu_div0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$5270 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$5271 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$5214 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$5215 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$5273 $2\data_r1__cr_a$next[3:0]$5272 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$5217 $2\data_r1__cr_a$next[3:0]$5216 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$5272 $1\data_r1__cr_a$next[3:0]$5270
- assign $2\data_r1__cr_a_ok$next[0:0]$5273 $1\data_r1__cr_a_ok$next[0:0]$5271
+ assign $2\data_r1__cr_a$next[3:0]$5216 $1\data_r1__cr_a$next[3:0]$5214
+ assign $2\data_r1__cr_a_ok$next[0:0]$5217 $1\data_r1__cr_a_ok$next[0:0]$5215
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$5274 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$5218 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$5274 $2\data_r1__cr_a_ok$next[0:0]$5273
+ assign $3\data_r1__cr_a_ok$next[0:0]$5218 $2\data_r1__cr_a_ok$next[0:0]$5217
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5268
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5269
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5212
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5213
end
- attribute \src "libresoc.v:130710.3-130731.6"
- process $proc$libresoc.v:130710$5275
+ attribute \src "libresoc.v:129333.3-129354.6"
+ process $proc$libresoc.v:129333$5219
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ov$next[1:0]$5276 $2\data_r2__xer_ov$next[1:0]$5280
+ assign $0\data_r2__xer_ov$next[1:0]$5220 $2\data_r2__xer_ov$next[1:0]$5224
assign { } { }
- assign $0\data_r2__xer_ov_ok$next[0:0]$5277 $3\data_r2__xer_ov_ok$next[0:0]$5282
- attribute \src "libresoc.v:130711.5-130711.29"
+ assign $0\data_r2__xer_ov_ok$next[0:0]$5221 $3\data_r2__xer_ov_ok$next[0:0]$5226
+ attribute \src "libresoc.v:129334.5-129334.29"
switch \initial
- attribute \src "libresoc.v:130711.9-130711.17"
+ attribute \src "libresoc.v:129334.9-129334.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ov_ok$next[0:0]$5279 $1\data_r2__xer_ov$next[1:0]$5278 } { \xer_ov_ok \alu_div0_xer_ov }
+ assign { $1\data_r2__xer_ov_ok$next[0:0]$5223 $1\data_r2__xer_ov$next[1:0]$5222 } { \xer_ov_ok \alu_div0_xer_ov }
case
- assign $1\data_r2__xer_ov$next[1:0]$5278 \data_r2__xer_ov
- assign $1\data_r2__xer_ov_ok$next[0:0]$5279 \data_r2__xer_ov_ok
+ assign $1\data_r2__xer_ov$next[1:0]$5222 \data_r2__xer_ov
+ assign $1\data_r2__xer_ov_ok$next[0:0]$5223 \data_r2__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ov_ok$next[0:0]$5281 $2\data_r2__xer_ov$next[1:0]$5280 } 3'000
+ assign { $2\data_r2__xer_ov_ok$next[0:0]$5225 $2\data_r2__xer_ov$next[1:0]$5224 } 3'000
case
- assign $2\data_r2__xer_ov$next[1:0]$5280 $1\data_r2__xer_ov$next[1:0]$5278
- assign $2\data_r2__xer_ov_ok$next[0:0]$5281 $1\data_r2__xer_ov_ok$next[0:0]$5279
+ assign $2\data_r2__xer_ov$next[1:0]$5224 $1\data_r2__xer_ov$next[1:0]$5222
+ assign $2\data_r2__xer_ov_ok$next[0:0]$5225 $1\data_r2__xer_ov_ok$next[0:0]$5223
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ov_ok$next[0:0]$5282 1'0
+ assign $3\data_r2__xer_ov_ok$next[0:0]$5226 1'0
case
- assign $3\data_r2__xer_ov_ok$next[0:0]$5282 $2\data_r2__xer_ov_ok$next[0:0]$5281
+ assign $3\data_r2__xer_ov_ok$next[0:0]$5226 $2\data_r2__xer_ov_ok$next[0:0]$5225
end
sync always
- update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5276
- update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5277
+ update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5220
+ update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5221
end
- attribute \src "libresoc.v:130732.3-130753.6"
- process $proc$libresoc.v:130732$5283
+ attribute \src "libresoc.v:129355.3-129376.6"
+ process $proc$libresoc.v:129355$5227
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$5284 $2\data_r3__xer_so$next[0:0]$5288
+ assign $0\data_r3__xer_so$next[0:0]$5228 $2\data_r3__xer_so$next[0:0]$5232
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$5285 $3\data_r3__xer_so_ok$next[0:0]$5290
- attribute \src "libresoc.v:130733.5-130733.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$5229 $3\data_r3__xer_so_ok$next[0:0]$5234
+ attribute \src "libresoc.v:129356.5-129356.29"
switch \initial
- attribute \src "libresoc.v:130733.9-130733.17"
+ attribute \src "libresoc.v:129356.9-129356.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$5287 $1\data_r3__xer_so$next[0:0]$5286 } { \xer_so_ok \alu_div0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$5231 $1\data_r3__xer_so$next[0:0]$5230 } { \xer_so_ok \alu_div0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$5286 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$5287 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$5230 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$5231 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$5289 $2\data_r3__xer_so$next[0:0]$5288 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$5233 $2\data_r3__xer_so$next[0:0]$5232 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$5288 $1\data_r3__xer_so$next[0:0]$5286
- assign $2\data_r3__xer_so_ok$next[0:0]$5289 $1\data_r3__xer_so_ok$next[0:0]$5287
+ assign $2\data_r3__xer_so$next[0:0]$5232 $1\data_r3__xer_so$next[0:0]$5230
+ assign $2\data_r3__xer_so_ok$next[0:0]$5233 $1\data_r3__xer_so_ok$next[0:0]$5231
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$5290 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$5234 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$5290 $2\data_r3__xer_so_ok$next[0:0]$5289
+ assign $3\data_r3__xer_so_ok$next[0:0]$5234 $2\data_r3__xer_so_ok$next[0:0]$5233
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5284
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5285
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5228
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5229
end
- attribute \src "libresoc.v:130754.3-130763.6"
- process $proc$libresoc.v:130754$5291
+ attribute \src "libresoc.v:129377.3-129386.6"
+ process $proc$libresoc.v:129377$5235
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$5292 $1\src_r0$next[63:0]$5293
- attribute \src "libresoc.v:130755.5-130755.29"
+ assign $0\src_r0$next[63:0]$5236 $1\src_r0$next[63:0]$5237
+ attribute \src "libresoc.v:129378.5-129378.29"
switch \initial
- attribute \src "libresoc.v:130755.9-130755.17"
+ attribute \src "libresoc.v:129378.9-129378.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$5293 \src_or_imm
+ assign $1\src_r0$next[63:0]$5237 \src_or_imm
case
- assign $1\src_r0$next[63:0]$5293 \src_r0
+ assign $1\src_r0$next[63:0]$5237 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$5292
+ update \src_r0$next $0\src_r0$next[63:0]$5236
end
- attribute \src "libresoc.v:130764.3-130773.6"
- process $proc$libresoc.v:130764$5294
+ attribute \src "libresoc.v:129387.3-129396.6"
+ process $proc$libresoc.v:129387$5238
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$5295 $1\src_r1$next[63:0]$5296
- attribute \src "libresoc.v:130765.5-130765.29"
+ assign $0\src_r1$next[63:0]$5239 $1\src_r1$next[63:0]$5240
+ attribute \src "libresoc.v:129388.5-129388.29"
switch \initial
- attribute \src "libresoc.v:130765.9-130765.17"
+ attribute \src "libresoc.v:129388.9-129388.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$5296 \src_or_imm$85
+ assign $1\src_r1$next[63:0]$5240 \src_or_imm$85
case
- assign $1\src_r1$next[63:0]$5296 \src_r1
+ assign $1\src_r1$next[63:0]$5240 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$5295
+ update \src_r1$next $0\src_r1$next[63:0]$5239
end
- attribute \src "libresoc.v:130774.3-130783.6"
- process $proc$libresoc.v:130774$5297
+ attribute \src "libresoc.v:129397.3-129406.6"
+ process $proc$libresoc.v:129397$5241
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$5298 $1\src_r2$next[0:0]$5299
- attribute \src "libresoc.v:130775.5-130775.29"
+ assign $0\src_r2$next[0:0]$5242 $1\src_r2$next[0:0]$5243
+ attribute \src "libresoc.v:129398.5-129398.29"
switch \initial
- attribute \src "libresoc.v:130775.9-130775.17"
+ attribute \src "libresoc.v:129398.9-129398.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$5299 \src3_i
+ assign $1\src_r2$next[0:0]$5243 \src3_i
case
- assign $1\src_r2$next[0:0]$5299 \src_r2
+ assign $1\src_r2$next[0:0]$5243 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$5298
+ update \src_r2$next $0\src_r2$next[0:0]$5242
end
- attribute \src "libresoc.v:130784.3-130792.6"
- process $proc$libresoc.v:130784$5300
+ attribute \src "libresoc.v:129407.3-129415.6"
+ process $proc$libresoc.v:129407$5244
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$5301 $1\alui_l_r_alui$next[0:0]$5302
- attribute \src "libresoc.v:130785.5-130785.29"
+ assign $0\alui_l_r_alui$next[0:0]$5245 $1\alui_l_r_alui$next[0:0]$5246
+ attribute \src "libresoc.v:129408.5-129408.29"
switch \initial
- attribute \src "libresoc.v:130785.9-130785.17"
+ attribute \src "libresoc.v:129408.9-129408.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$5302 1'1
+ assign $1\alui_l_r_alui$next[0:0]$5246 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$5302 \$94
+ assign $1\alui_l_r_alui$next[0:0]$5246 \$94
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5301
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5245
end
- attribute \src "libresoc.v:130793.3-130801.6"
- process $proc$libresoc.v:130793$5303
+ attribute \src "libresoc.v:129416.3-129424.6"
+ process $proc$libresoc.v:129416$5247
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$5304 $1\alu_l_r_alu$next[0:0]$5305
- attribute \src "libresoc.v:130794.5-130794.29"
+ assign $0\alu_l_r_alu$next[0:0]$5248 $1\alu_l_r_alu$next[0:0]$5249
+ attribute \src "libresoc.v:129417.5-129417.29"
switch \initial
- attribute \src "libresoc.v:130794.9-130794.17"
+ attribute \src "libresoc.v:129417.9-129417.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$5305 1'1
+ assign $1\alu_l_r_alu$next[0:0]$5249 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$5305 \$96
+ assign $1\alu_l_r_alu$next[0:0]$5249 \$96
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5304
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5248
end
- attribute \src "libresoc.v:130802.3-130811.6"
- process $proc$libresoc.v:130802$5306
+ attribute \src "libresoc.v:129425.3-129434.6"
+ process $proc$libresoc.v:129425$5250
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:130803.5-130803.29"
+ attribute \src "libresoc.v:129426.5-129426.29"
switch \initial
- attribute \src "libresoc.v:130803.9-130803.17"
+ attribute \src "libresoc.v:129426.9-129426.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:130812.3-130821.6"
- process $proc$libresoc.v:130812$5307
+ attribute \src "libresoc.v:129435.3-129444.6"
+ process $proc$libresoc.v:129435$5251
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:130813.5-130813.29"
+ attribute \src "libresoc.v:129436.5-129436.29"
switch \initial
- attribute \src "libresoc.v:130813.9-130813.17"
+ attribute \src "libresoc.v:129436.9-129436.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:130822.3-130831.6"
- process $proc$libresoc.v:130822$5308
+ attribute \src "libresoc.v:129445.3-129454.6"
+ process $proc$libresoc.v:129445$5252
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:130823.5-130823.29"
+ attribute \src "libresoc.v:129446.5-129446.29"
switch \initial
- attribute \src "libresoc.v:130823.9-130823.17"
+ attribute \src "libresoc.v:129446.9-129446.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:130832.3-130841.6"
- process $proc$libresoc.v:130832$5309
+ attribute \src "libresoc.v:129455.3-129464.6"
+ process $proc$libresoc.v:129455$5253
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:130833.5-130833.29"
+ attribute \src "libresoc.v:129456.5-129456.29"
switch \initial
- attribute \src "libresoc.v:130833.9-130833.17"
+ attribute \src "libresoc.v:129456.9-129456.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:130842.3-130850.6"
- process $proc$libresoc.v:130842$5310
+ attribute \src "libresoc.v:129465.3-129473.6"
+ process $proc$libresoc.v:129465$5254
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[3:0]$5311 $1\prev_wr_go$next[3:0]$5312
- attribute \src "libresoc.v:130843.5-130843.29"
+ assign $0\prev_wr_go$next[3:0]$5255 $1\prev_wr_go$next[3:0]$5256
+ attribute \src "libresoc.v:129466.5-129466.29"
switch \initial
- attribute \src "libresoc.v:130843.9-130843.17"
+ attribute \src "libresoc.v:129466.9-129466.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[3:0]$5312 4'0000
- case
- assign $1\prev_wr_go$next[3:0]$5312 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5311
- end
- connect \$100 $not$libresoc.v:130291$5078_Y
- connect \$102 $not$libresoc.v:130292$5079_Y
- connect \$104 $and$libresoc.v:130293$5080_Y
- connect \$106 $not$libresoc.v:130294$5081_Y
- connect \$108 $and$libresoc.v:130295$5082_Y
- connect \$10 $and$libresoc.v:130296$5083_Y
- connect \$110 $and$libresoc.v:130297$5084_Y
- connect \$112 $and$libresoc.v:130298$5085_Y
- connect \$114 $and$libresoc.v:130299$5086_Y
- connect \$116 $and$libresoc.v:130300$5087_Y
- connect \$118 $and$libresoc.v:130301$5088_Y
- connect \$120 $and$libresoc.v:130302$5089_Y
- connect \$122 $and$libresoc.v:130303$5090_Y
- connect \$124 $and$libresoc.v:130304$5091_Y
- connect \$126 $and$libresoc.v:130305$5092_Y
- connect \$128 $and$libresoc.v:130306$5093_Y
- connect \$12 $not$libresoc.v:130307$5094_Y
- connect \$14 $and$libresoc.v:130308$5095_Y
- connect \$16 $not$libresoc.v:130309$5096_Y
- connect \$18 $and$libresoc.v:130310$5097_Y
- connect \$20 $and$libresoc.v:130311$5098_Y
- connect \$24 $not$libresoc.v:130312$5099_Y
- connect \$26 $and$libresoc.v:130313$5100_Y
- connect \$23 $reduce_or$libresoc.v:130314$5101_Y
- connect \$22 $not$libresoc.v:130315$5102_Y
- connect \$2 $and$libresoc.v:130316$5103_Y
- connect \$30 $and$libresoc.v:130317$5104_Y
- connect \$32 $reduce_or$libresoc.v:130318$5105_Y
- connect \$34 $reduce_or$libresoc.v:130319$5106_Y
- connect \$36 $or$libresoc.v:130320$5107_Y
- connect \$38 $not$libresoc.v:130321$5108_Y
- connect \$40 $and$libresoc.v:130322$5109_Y
- connect \$42 $and$libresoc.v:130323$5110_Y
- connect \$44 $eq$libresoc.v:130324$5111_Y
- connect \$46 $and$libresoc.v:130325$5112_Y
- connect \$48 $eq$libresoc.v:130326$5113_Y
- connect \$50 $and$libresoc.v:130327$5114_Y
- connect \$52 $and$libresoc.v:130328$5115_Y
- connect \$54 $and$libresoc.v:130329$5116_Y
- connect \$56 $or$libresoc.v:130330$5117_Y
- connect \$58 $or$libresoc.v:130331$5118_Y
- connect \$5 $not$libresoc.v:130332$5119_Y
- connect \$60 $or$libresoc.v:130333$5120_Y
- connect \$62 $or$libresoc.v:130334$5121_Y
- connect \$64 $and$libresoc.v:130335$5122_Y
- connect \$66 $and$libresoc.v:130336$5123_Y
- connect \$68 $or$libresoc.v:130337$5124_Y
- connect \$70 $and$libresoc.v:130338$5125_Y
- connect \$72 $and$libresoc.v:130339$5126_Y
- connect \$74 $and$libresoc.v:130340$5127_Y
- connect \$76 $and$libresoc.v:130341$5128_Y
- connect \$78 $ternary$libresoc.v:130342$5129_Y
- connect \$7 $or$libresoc.v:130343$5130_Y
- connect \$80 $ternary$libresoc.v:130344$5131_Y
- connect \$83 $ternary$libresoc.v:130345$5132_Y
- connect \$86 $ternary$libresoc.v:130346$5133_Y
- connect \$88 $ternary$libresoc.v:130347$5134_Y
- connect \$4 $reduce_and$libresoc.v:130348$5135_Y
- connect \$90 $ternary$libresoc.v:130349$5136_Y
- connect \$92 $ternary$libresoc.v:130350$5137_Y
- connect \$94 $and$libresoc.v:130351$5138_Y
- connect \$96 $and$libresoc.v:130352$5139_Y
- connect \$98 $and$libresoc.v:130353$5140_Y
+ assign $1\prev_wr_go$next[3:0]$5256 4'0000
+ case
+ assign $1\prev_wr_go$next[3:0]$5256 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5255
+ end
+ connect \$100 $not$libresoc.v:128914$5022_Y
+ connect \$102 $not$libresoc.v:128915$5023_Y
+ connect \$104 $and$libresoc.v:128916$5024_Y
+ connect \$106 $not$libresoc.v:128917$5025_Y
+ connect \$108 $and$libresoc.v:128918$5026_Y
+ connect \$10 $and$libresoc.v:128919$5027_Y
+ connect \$110 $and$libresoc.v:128920$5028_Y
+ connect \$112 $and$libresoc.v:128921$5029_Y
+ connect \$114 $and$libresoc.v:128922$5030_Y
+ connect \$116 $and$libresoc.v:128923$5031_Y
+ connect \$118 $and$libresoc.v:128924$5032_Y
+ connect \$120 $and$libresoc.v:128925$5033_Y
+ connect \$122 $and$libresoc.v:128926$5034_Y
+ connect \$124 $and$libresoc.v:128927$5035_Y
+ connect \$126 $and$libresoc.v:128928$5036_Y
+ connect \$128 $and$libresoc.v:128929$5037_Y
+ connect \$12 $not$libresoc.v:128930$5038_Y
+ connect \$14 $and$libresoc.v:128931$5039_Y
+ connect \$16 $not$libresoc.v:128932$5040_Y
+ connect \$18 $and$libresoc.v:128933$5041_Y
+ connect \$20 $and$libresoc.v:128934$5042_Y
+ connect \$24 $not$libresoc.v:128935$5043_Y
+ connect \$26 $and$libresoc.v:128936$5044_Y
+ connect \$23 $reduce_or$libresoc.v:128937$5045_Y
+ connect \$22 $not$libresoc.v:128938$5046_Y
+ connect \$2 $and$libresoc.v:128939$5047_Y
+ connect \$30 $and$libresoc.v:128940$5048_Y
+ connect \$32 $reduce_or$libresoc.v:128941$5049_Y
+ connect \$34 $reduce_or$libresoc.v:128942$5050_Y
+ connect \$36 $or$libresoc.v:128943$5051_Y
+ connect \$38 $not$libresoc.v:128944$5052_Y
+ connect \$40 $and$libresoc.v:128945$5053_Y
+ connect \$42 $and$libresoc.v:128946$5054_Y
+ connect \$44 $eq$libresoc.v:128947$5055_Y
+ connect \$46 $and$libresoc.v:128948$5056_Y
+ connect \$48 $eq$libresoc.v:128949$5057_Y
+ connect \$50 $and$libresoc.v:128950$5058_Y
+ connect \$52 $and$libresoc.v:128951$5059_Y
+ connect \$54 $and$libresoc.v:128952$5060_Y
+ connect \$56 $or$libresoc.v:128953$5061_Y
+ connect \$58 $or$libresoc.v:128954$5062_Y
+ connect \$5 $not$libresoc.v:128955$5063_Y
+ connect \$60 $or$libresoc.v:128956$5064_Y
+ connect \$62 $or$libresoc.v:128957$5065_Y
+ connect \$64 $and$libresoc.v:128958$5066_Y
+ connect \$66 $and$libresoc.v:128959$5067_Y
+ connect \$68 $or$libresoc.v:128960$5068_Y
+ connect \$70 $and$libresoc.v:128961$5069_Y
+ connect \$72 $and$libresoc.v:128962$5070_Y
+ connect \$74 $and$libresoc.v:128963$5071_Y
+ connect \$76 $and$libresoc.v:128964$5072_Y
+ connect \$78 $ternary$libresoc.v:128965$5073_Y
+ connect \$7 $or$libresoc.v:128966$5074_Y
+ connect \$80 $ternary$libresoc.v:128967$5075_Y
+ connect \$83 $ternary$libresoc.v:128968$5076_Y
+ connect \$86 $ternary$libresoc.v:128969$5077_Y
+ connect \$88 $ternary$libresoc.v:128970$5078_Y
+ connect \$4 $reduce_and$libresoc.v:128971$5079_Y
+ connect \$90 $ternary$libresoc.v:128972$5080_Y
+ connect \$92 $ternary$libresoc.v:128973$5081_Y
+ connect \$94 $and$libresoc.v:128974$5082_Y
+ connect \$96 $and$libresoc.v:128975$5083_Y
+ connect \$98 $and$libresoc.v:128976$5084_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$120
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:130887.1-130896.10"
+attribute \src "libresoc.v:129510.1-129519.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init"
attribute \generator "nMigen"
connect \o_dividend_quotient \dividend
connect \o_q_bits_known 7'0000000
end
-attribute \src "libresoc.v:130900.1-130982.10"
+attribute \src "libresoc.v:129523.1-129605.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next"
attribute \generator "nMigen"
module \div_state_next
- attribute \src "libresoc.v:130901.7-130901.20"
+ attribute \src "libresoc.v:129524.7-129524.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:130966.3-130977.6"
+ attribute \src "libresoc.v:129589.3-129600.6"
wire width 128 $0\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:130954.3-130965.6"
+ attribute \src "libresoc.v:129577.3-129588.6"
wire width 7 $0\o_q_bits_known[6:0]
- attribute \src "libresoc.v:130942.3-130953.6"
+ attribute \src "libresoc.v:129565.3-129576.6"
wire width 128 $0\value[127:0]
- attribute \src "libresoc.v:130966.3-130977.6"
+ attribute \src "libresoc.v:129589.3-129600.6"
wire width 128 $1\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:130954.3-130965.6"
+ attribute \src "libresoc.v:129577.3-129588.6"
wire width 7 $1\o_q_bits_known[6:0]
- attribute \src "libresoc.v:130942.3-130953.6"
+ attribute \src "libresoc.v:129565.3-129576.6"
wire width 128 $1\value[127:0]
- attribute \src "libresoc.v:130936.18-130936.106"
- wire width 8 $add$libresoc.v:130936$5358_Y
- attribute \src "libresoc.v:130937.18-130937.109"
- wire $ge$libresoc.v:130937$5359_Y
- attribute \src "libresoc.v:130941.17-130941.108"
- wire $ge$libresoc.v:130941$5363_Y
- attribute \src "libresoc.v:130940.17-130940.101"
- wire $not$libresoc.v:130940$5362_Y
- attribute \src "libresoc.v:130938.17-130938.101"
- wire width 127 $sshl$libresoc.v:130938$5360_Y
- attribute \src "libresoc.v:130939.17-130939.109"
- wire width 129 $sub$libresoc.v:130939$5361_Y
+ attribute \src "libresoc.v:129559.18-129559.106"
+ wire width 8 $add$libresoc.v:129559$5302_Y
+ attribute \src "libresoc.v:129560.18-129560.109"
+ wire $ge$libresoc.v:129560$5303_Y
+ attribute \src "libresoc.v:129564.17-129564.108"
+ wire $ge$libresoc.v:129564$5307_Y
+ attribute \src "libresoc.v:129563.17-129563.101"
+ wire $not$libresoc.v:129563$5306_Y
+ attribute \src "libresoc.v:129561.17-129561.101"
+ wire width 127 $sshl$libresoc.v:129561$5304_Y
+ attribute \src "libresoc.v:129562.17-129562.109"
+ wire width 129 $sub$libresoc.v:129562$5305_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
wire width 129 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81"
wire width 128 input 3 \i_dividend_quotient
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103"
wire width 7 input 2 \i_q_bits_known
- attribute \src "libresoc.v:130901.7-130901.15"
+ attribute \src "libresoc.v:129524.7-129524.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68"
wire \next_quotient_bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71"
wire width 128 \value
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81"
- cell $add $add$libresoc.v:130936$5358
+ cell $add $add$libresoc.v:129559$5302
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \i_q_bits_known
connect \B 1'1
- connect \Y $add$libresoc.v:130936$5358_Y
+ connect \Y $add$libresoc.v:129559$5302_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:130937$5359
+ cell $ge $ge$libresoc.v:129560$5303
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i_q_bits_known
connect \B 7'1000000
- connect \Y $ge$libresoc.v:130937$5359_Y
+ connect \Y $ge$libresoc.v:129560$5303_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:130941$5363
+ cell $ge $ge$libresoc.v:129564$5307
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i_q_bits_known
connect \B 7'1000000
- connect \Y $ge$libresoc.v:130941$5363_Y
+ connect \Y $ge$libresoc.v:129564$5307_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70"
- cell $not $not$libresoc.v:130940$5362
+ cell $not $not$libresoc.v:129563$5306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \difference [127]
- connect \Y $not$libresoc.v:130940$5362_Y
+ connect \Y $not$libresoc.v:129563$5306_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
- cell $sshl $sshl$libresoc.v:130938$5360
+ cell $sshl $sshl$libresoc.v:129561$5304
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 127
connect \A \divisor
connect \B 6'111111
- connect \Y $sshl$libresoc.v:130938$5360_Y
+ connect \Y $sshl$libresoc.v:129561$5304_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67"
- cell $sub $sub$libresoc.v:130939$5361
+ cell $sub $sub$libresoc.v:129562$5305
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \B_SIGNED 0
parameter \Y_WIDTH 129
connect \A \i_dividend_quotient
connect \B \$2
- connect \Y $sub$libresoc.v:130939$5361_Y
+ connect \Y $sub$libresoc.v:129562$5305_Y
end
- attribute \src "libresoc.v:130901.7-130901.20"
- process $proc$libresoc.v:130901$5367
+ attribute \src "libresoc.v:129524.7-129524.20"
+ process $proc$libresoc.v:129524$5311
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:130942.3-130953.6"
- process $proc$libresoc.v:130942$5364
+ attribute \src "libresoc.v:129565.3-129576.6"
+ process $proc$libresoc.v:129565$5308
assign { } { }
assign $0\value[127:0] $1\value[127:0]
- attribute \src "libresoc.v:130943.5-130943.29"
+ attribute \src "libresoc.v:129566.5-129566.29"
switch \initial
- attribute \src "libresoc.v:130943.9-130943.17"
+ attribute \src "libresoc.v:129566.9-129566.17"
case 1'1
case
end
sync always
update \value $0\value[127:0]
end
- attribute \src "libresoc.v:130954.3-130965.6"
- process $proc$libresoc.v:130954$5365
+ attribute \src "libresoc.v:129577.3-129588.6"
+ process $proc$libresoc.v:129577$5309
assign { } { }
assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0]
- attribute \src "libresoc.v:130955.5-130955.29"
+ attribute \src "libresoc.v:129578.5-129578.29"
switch \initial
- attribute \src "libresoc.v:130955.9-130955.17"
+ attribute \src "libresoc.v:129578.9-129578.17"
case 1'1
case
end
sync always
update \o_q_bits_known $0\o_q_bits_known[6:0]
end
- attribute \src "libresoc.v:130966.3-130977.6"
- process $proc$libresoc.v:130966$5366
+ attribute \src "libresoc.v:129589.3-129600.6"
+ process $proc$libresoc.v:129589$5310
assign { } { }
assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0]
- attribute \src "libresoc.v:130967.5-130967.29"
+ attribute \src "libresoc.v:129590.5-129590.29"
switch \initial
- attribute \src "libresoc.v:130967.9-130967.17"
+ attribute \src "libresoc.v:129590.9-129590.17"
case 1'1
case
end
sync always
update \o_dividend_quotient $0\o_dividend_quotient[127:0]
end
- connect \$11 $add$libresoc.v:130936$5358_Y
- connect \$13 $ge$libresoc.v:130937$5359_Y
- connect \$2 $sshl$libresoc.v:130938$5360_Y
- connect \$4 $sub$libresoc.v:130939$5361_Y
- connect \$6 $not$libresoc.v:130940$5362_Y
- connect \$8 $ge$libresoc.v:130941$5363_Y
+ connect \$11 $add$libresoc.v:129559$5302_Y
+ connect \$13 $ge$libresoc.v:129560$5303_Y
+ connect \$2 $sshl$libresoc.v:129561$5304_Y
+ connect \$4 $sub$libresoc.v:129562$5305_Y
+ connect \$6 $not$libresoc.v:129563$5306_Y
+ connect \$8 $ge$libresoc.v:129564$5307_Y
connect \$1 \$4
connect \$10 \$11
connect \next_quotient_bit \$6
connect \difference \$4 [127:0]
end
-attribute \src "libresoc.v:130986.1-131225.10"
+attribute \src "libresoc.v:129609.1-129848.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy"
attribute \generator "nMigen"
connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \muxid$1 \muxid
end
-attribute \src "libresoc.v:131229.1-131400.10"
+attribute \src "libresoc.v:129852.1-130023.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fast"
attribute \generator "nMigen"
module \fast
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 3 $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 64 $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 64 $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 3 $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 64 $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388
- attribute \src "libresoc.v:131324.3-131330.6"
- wire width 64 $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389
- attribute \src "libresoc.v:131324.3-131330.6"
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 3 $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 3 $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332
+ attribute \src "libresoc.v:129947.3-129953.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333
+ attribute \src "libresoc.v:129947.3-129953.6"
wire width 3 $0\_0_[2:0]
- attribute \src "libresoc.v:131324.3-131330.6"
+ attribute \src "libresoc.v:129947.3-129953.6"
wire width 3 $0\_1_[2:0]
- attribute \src "libresoc.v:131324.3-131330.6"
+ attribute \src "libresoc.v:129947.3-129953.6"
wire width 3 $0\_2_[2:0]
- attribute \src "libresoc.v:131230.7-131230.20"
+ attribute \src "libresoc.v:129853.7-129853.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:131381.3-131390.6"
+ attribute \src "libresoc.v:130004.3-130013.6"
wire width 64 $0\issue__data_o[63:0]
- attribute \src "libresoc.v:131353.3-131361.6"
- wire $0\ren_delay$10$next[0:0]$5398
- attribute \src "libresoc.v:131306.3-131307.43"
- wire $0\ren_delay$10[0:0]$5381
- attribute \src "libresoc.v:131281.7-131281.28"
- wire $0\ren_delay$10[0:0]$5418
- attribute \src "libresoc.v:131372.3-131380.6"
- wire $0\ren_delay$11$next[0:0]$5402
- attribute \src "libresoc.v:131304.3-131305.43"
- wire $0\ren_delay$11[0:0]$5379
- attribute \src "libresoc.v:131285.7-131285.28"
- wire $0\ren_delay$11[0:0]$5420
- attribute \src "libresoc.v:131334.3-131342.6"
- wire $0\ren_delay$next[0:0]$5394
- attribute \src "libresoc.v:131308.3-131309.35"
+ attribute \src "libresoc.v:129976.3-129984.6"
+ wire $0\ren_delay$10$next[0:0]$5342
+ attribute \src "libresoc.v:129929.3-129930.43"
+ wire $0\ren_delay$10[0:0]$5325
+ attribute \src "libresoc.v:129904.7-129904.28"
+ wire $0\ren_delay$10[0:0]$5362
+ attribute \src "libresoc.v:129995.3-130003.6"
+ wire $0\ren_delay$11$next[0:0]$5346
+ attribute \src "libresoc.v:129927.3-129928.43"
+ wire $0\ren_delay$11[0:0]$5323
+ attribute \src "libresoc.v:129908.7-129908.28"
+ wire $0\ren_delay$11[0:0]$5364
+ attribute \src "libresoc.v:129957.3-129965.6"
+ wire $0\ren_delay$next[0:0]$5338
+ attribute \src "libresoc.v:129931.3-129932.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:131343.3-131352.6"
+ attribute \src "libresoc.v:129966.3-129975.6"
wire width 64 $0\src1__data_o[63:0]
- attribute \src "libresoc.v:131362.3-131371.6"
+ attribute \src "libresoc.v:129985.3-129994.6"
wire width 64 $0\src2__data_o[63:0]
- attribute \src "libresoc.v:131381.3-131390.6"
+ attribute \src "libresoc.v:130004.3-130013.6"
wire width 64 $1\issue__data_o[63:0]
- attribute \src "libresoc.v:131353.3-131361.6"
- wire $1\ren_delay$10$next[0:0]$5399
- attribute \src "libresoc.v:131372.3-131380.6"
- wire $1\ren_delay$11$next[0:0]$5403
- attribute \src "libresoc.v:131334.3-131342.6"
- wire $1\ren_delay$next[0:0]$5395
- attribute \src "libresoc.v:131279.7-131279.23"
+ attribute \src "libresoc.v:129976.3-129984.6"
+ wire $1\ren_delay$10$next[0:0]$5343
+ attribute \src "libresoc.v:129995.3-130003.6"
+ wire $1\ren_delay$11$next[0:0]$5347
+ attribute \src "libresoc.v:129957.3-129965.6"
+ wire $1\ren_delay$next[0:0]$5339
+ attribute \src "libresoc.v:129902.7-129902.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:131343.3-131352.6"
+ attribute \src "libresoc.v:129966.3-129975.6"
wire width 64 $1\src1__data_o[63:0]
- attribute \src "libresoc.v:131362.3-131371.6"
+ attribute \src "libresoc.v:129985.3-129994.6"
wire width 64 $1\src2__data_o[63:0]
- attribute \src "libresoc.v:131331.26-131331.32"
- wire width 64 $memrd$\memory$libresoc.v:131331$5390_DATA
- attribute \src "libresoc.v:131332.30-131332.36"
- wire width 64 $memrd$\memory$libresoc.v:131332$5391_DATA
- attribute \src "libresoc.v:131333.30-131333.36"
- wire width 64 $memrd$\memory$libresoc.v:131333$5392_DATA
+ attribute \src "libresoc.v:129954.26-129954.32"
+ wire width 64 $memrd$\memory$libresoc.v:129954$5334_DATA
+ attribute \src "libresoc.v:129955.30-129955.36"
+ wire width 64 $memrd$\memory$libresoc.v:129955$5335_DATA
+ attribute \src "libresoc.v:129956.30-129956.36"
+ wire width 64 $memrd$\memory$libresoc.v:129956$5336_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 3 $memwr$\memory$libresoc.v:131328$5376_ADDR
+ wire width 3 $memwr$\memory$libresoc.v:129951$5320_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:131328$5376_DATA
+ wire width 64 $memwr$\memory$libresoc.v:129951$5320_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:131328$5376_EN
+ wire width 64 $memwr$\memory$libresoc.v:129951$5320_EN
attribute \src "libresoc.v:0.0-0.0"
- wire width 3 $memwr$\memory$libresoc.v:131329$5377_ADDR
+ wire width 3 $memwr$\memory$libresoc.v:129952$5321_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:131329$5377_DATA
+ wire width 64 $memwr$\memory$libresoc.v:129952$5321_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:131329$5377_EN
- attribute \src "libresoc.v:131321.13-131321.16"
+ wire width 64 $memwr$\memory$libresoc.v:129952$5321_EN
+ attribute \src "libresoc.v:129944.13-129944.16"
wire width 3 \_0_
- attribute \src "libresoc.v:131322.13-131322.16"
+ attribute \src "libresoc.v:129945.13-129945.16"
wire width 3 \_1_
- attribute \src "libresoc.v:131323.13-131323.16"
+ attribute \src "libresoc.v:129946.13-129946.16"
wire width 3 \_2_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 17 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \dest1__addr
wire width 64 input 14 \dest1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 16 \dest1__wen
- attribute \src "libresoc.v:131230.7-131230.15"
+ attribute \src "libresoc.v:129853.7-129853.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 2 \issue__addr
wire width 64 output 11 \src2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 13 \src2__ren
- attribute \src "libresoc.v:131310.14-131310.20"
+ attribute \src "libresoc.v:129933.14-129933.20"
memory width 64 size 8 \memory
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5405
+ cell $meminit $meminit$\memory$libresoc.v:0$5349
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5405
+ parameter \PRIORITY 5349
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5406
+ cell $meminit $meminit$\memory$libresoc.v:0$5350
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5406
+ parameter \PRIORITY 5350
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5407
+ cell $meminit $meminit$\memory$libresoc.v:0$5351
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5407
+ parameter \PRIORITY 5351
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5408
+ cell $meminit $meminit$\memory$libresoc.v:0$5352
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5408
+ parameter \PRIORITY 5352
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5409
+ cell $meminit $meminit$\memory$libresoc.v:0$5353
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5409
+ parameter \PRIORITY 5353
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5410
+ cell $meminit $meminit$\memory$libresoc.v:0$5354
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5410
+ parameter \PRIORITY 5354
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5411
+ cell $meminit $meminit$\memory$libresoc.v:0$5355
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5411
+ parameter \PRIORITY 5355
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5412
+ cell $meminit $meminit$\memory$libresoc.v:0$5356
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5412
+ parameter \PRIORITY 5356
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:131331.26-131331.32"
- cell $memrd $memrd$\memory$libresoc.v:131331$5390
+ attribute \src "libresoc.v:129954.26-129954.32"
+ cell $memrd $memrd$\memory$libresoc.v:129954$5334
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:131331$5390_DATA
+ connect \DATA $memrd$\memory$libresoc.v:129954$5334_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:131332.30-131332.36"
- cell $memrd $memrd$\memory$libresoc.v:131332$5391
+ attribute \src "libresoc.v:129955.30-129955.36"
+ cell $memrd $memrd$\memory$libresoc.v:129955$5335
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_1_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:131332$5391_DATA
+ connect \DATA $memrd$\memory$libresoc.v:129955$5335_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:131333.30-131333.36"
- cell $memrd $memrd$\memory$libresoc.v:131333$5392
+ attribute \src "libresoc.v:129956.30-129956.36"
+ cell $memrd $memrd$\memory$libresoc.v:129956$5336
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_2_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:131333$5392_DATA
+ connect \DATA $memrd$\memory$libresoc.v:129956$5336_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- cell $memwr $memwr$\memory$libresoc.v:0$5413
+ cell $memwr $memwr$\memory$libresoc.v:0$5357
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\memory"
- parameter \PRIORITY 5413
+ parameter \PRIORITY 5357
parameter \WIDTH 64
- connect \ADDR $memwr$\memory$libresoc.v:131328$5376_ADDR
+ connect \ADDR $memwr$\memory$libresoc.v:129951$5320_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\memory$libresoc.v:131328$5376_DATA
- connect \EN $memwr$\memory$libresoc.v:131328$5376_EN
+ connect \DATA $memwr$\memory$libresoc.v:129951$5320_DATA
+ connect \EN $memwr$\memory$libresoc.v:129951$5320_EN
end
attribute \src "libresoc.v:0.0-0.0"
- cell $memwr $memwr$\memory$libresoc.v:0$5414
+ cell $memwr $memwr$\memory$libresoc.v:0$5358
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\memory"
- parameter \PRIORITY 5414
+ parameter \PRIORITY 5358
parameter \WIDTH 64
- connect \ADDR $memwr$\memory$libresoc.v:131329$5377_ADDR
+ connect \ADDR $memwr$\memory$libresoc.v:129952$5321_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\memory$libresoc.v:131329$5377_DATA
- connect \EN $memwr$\memory$libresoc.v:131329$5377_EN
+ connect \DATA $memwr$\memory$libresoc.v:129952$5321_DATA
+ connect \EN $memwr$\memory$libresoc.v:129952$5321_EN
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$5421
+ process $proc$libresoc.v:0$5365
sync always
sync init
end
- attribute \src "libresoc.v:131230.7-131230.20"
- process $proc$libresoc.v:131230$5415
+ attribute \src "libresoc.v:129853.7-129853.20"
+ process $proc$libresoc.v:129853$5359
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:131279.7-131279.23"
- process $proc$libresoc.v:131279$5416
+ attribute \src "libresoc.v:129902.7-129902.23"
+ process $proc$libresoc.v:129902$5360
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:131281.7-131281.28"
- process $proc$libresoc.v:131281$5417
+ attribute \src "libresoc.v:129904.7-129904.28"
+ process $proc$libresoc.v:129904$5361
assign { } { }
- assign $0\ren_delay$10[0:0]$5418 1'0
+ assign $0\ren_delay$10[0:0]$5362 1'0
sync always
sync init
- update \ren_delay$10 $0\ren_delay$10[0:0]$5418
+ update \ren_delay$10 $0\ren_delay$10[0:0]$5362
end
- attribute \src "libresoc.v:131285.7-131285.28"
- process $proc$libresoc.v:131285$5419
+ attribute \src "libresoc.v:129908.7-129908.28"
+ process $proc$libresoc.v:129908$5363
assign { } { }
- assign $0\ren_delay$11[0:0]$5420 1'0
+ assign $0\ren_delay$11[0:0]$5364 1'0
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[0:0]$5420
+ update \ren_delay$11 $0\ren_delay$11[0:0]$5364
end
- attribute \src "libresoc.v:131304.3-131305.43"
- process $proc$libresoc.v:131304$5378
+ attribute \src "libresoc.v:129927.3-129928.43"
+ process $proc$libresoc.v:129927$5322
assign { } { }
- assign $0\ren_delay$11[0:0]$5379 \ren_delay$11$next
+ assign $0\ren_delay$11[0:0]$5323 \ren_delay$11$next
sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[0:0]$5379
+ update \ren_delay$11 $0\ren_delay$11[0:0]$5323
end
- attribute \src "libresoc.v:131306.3-131307.43"
- process $proc$libresoc.v:131306$5380
+ attribute \src "libresoc.v:129929.3-129930.43"
+ process $proc$libresoc.v:129929$5324
assign { } { }
- assign $0\ren_delay$10[0:0]$5381 \ren_delay$10$next
+ assign $0\ren_delay$10[0:0]$5325 \ren_delay$10$next
sync posedge \coresync_clk
- update \ren_delay$10 $0\ren_delay$10[0:0]$5381
+ update \ren_delay$10 $0\ren_delay$10[0:0]$5325
end
- attribute \src "libresoc.v:131308.3-131309.35"
- process $proc$libresoc.v:131308$5382
+ attribute \src "libresoc.v:129931.3-129932.35"
+ process $proc$libresoc.v:129931$5326
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:131324.3-131330.6"
- process $proc$libresoc.v:131324$5383
+ attribute \src "libresoc.v:129947.3-129953.6"
+ process $proc$libresoc.v:129947$5327
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 3'xxx
- assign $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 3'xxx
- assign $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 3'xxx
+ assign $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 3'xxx
+ assign $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 64'0000000000000000000000000000000000000000000000000000000000000000
assign $0\_0_[2:0] \src1__addr
assign $0\_1_[2:0] \src2__addr
assign $0\_2_[2:0] \issue__addr
- attribute \src "libresoc.v:131328.5-131328.62"
+ attribute \src "libresoc.v:129951.5-129951.62"
switch \issue__wen
- attribute \src "libresoc.v:131328.9-131328.19"
+ attribute \src "libresoc.v:129951.9-129951.19"
case 1'1
- assign $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 \issue__addr$1
- assign $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 \issue__data_i
- assign $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 \issue__addr$1
+ assign $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 \issue__data_i
+ assign $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 64'1111111111111111111111111111111111111111111111111111111111111111
case
end
- attribute \src "libresoc.v:131329.5-131329.58"
+ attribute \src "libresoc.v:129952.5-129952.58"
switch \dest1__wen
- attribute \src "libresoc.v:131329.9-131329.19"
+ attribute \src "libresoc.v:129952.9-129952.19"
case 1'1
- assign $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 \dest1__addr
- assign $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 \dest1__data_i
- assign $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 \dest1__addr
+ assign $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 \dest1__data_i
+ assign $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 64'1111111111111111111111111111111111111111111111111111111111111111
case
end
sync posedge \coresync_clk
update \_0_ $0\_0_[2:0]
update \_1_ $0\_1_[2:0]
update \_2_ $0\_2_[2:0]
- update $memwr$\memory$libresoc.v:131328$5376_ADDR $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384
- update $memwr$\memory$libresoc.v:131328$5376_DATA $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385
- update $memwr$\memory$libresoc.v:131328$5376_EN $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386
- update $memwr$\memory$libresoc.v:131329$5377_ADDR $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387
- update $memwr$\memory$libresoc.v:131329$5377_DATA $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388
- update $memwr$\memory$libresoc.v:131329$5377_EN $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389
+ update $memwr$\memory$libresoc.v:129951$5320_ADDR $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328
+ update $memwr$\memory$libresoc.v:129951$5320_DATA $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329
+ update $memwr$\memory$libresoc.v:129951$5320_EN $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330
+ update $memwr$\memory$libresoc.v:129952$5321_ADDR $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331
+ update $memwr$\memory$libresoc.v:129952$5321_DATA $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332
+ update $memwr$\memory$libresoc.v:129952$5321_EN $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333
end
- attribute \src "libresoc.v:131334.3-131342.6"
- process $proc$libresoc.v:131334$5393
+ attribute \src "libresoc.v:129957.3-129965.6"
+ process $proc$libresoc.v:129957$5337
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$5394 $1\ren_delay$next[0:0]$5395
- attribute \src "libresoc.v:131335.5-131335.29"
+ assign $0\ren_delay$next[0:0]$5338 $1\ren_delay$next[0:0]$5339
+ attribute \src "libresoc.v:129958.5-129958.29"
switch \initial
- attribute \src "libresoc.v:131335.9-131335.17"
+ attribute \src "libresoc.v:129958.9-129958.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$5395 1'0
+ assign $1\ren_delay$next[0:0]$5339 1'0
case
- assign $1\ren_delay$next[0:0]$5395 \src1__ren
+ assign $1\ren_delay$next[0:0]$5339 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$5394
+ update \ren_delay$next $0\ren_delay$next[0:0]$5338
end
- attribute \src "libresoc.v:131343.3-131352.6"
- process $proc$libresoc.v:131343$5396
+ attribute \src "libresoc.v:129966.3-129975.6"
+ process $proc$libresoc.v:129966$5340
assign { } { }
assign { } { }
assign $0\src1__data_o[63:0] $1\src1__data_o[63:0]
- attribute \src "libresoc.v:131344.5-131344.29"
+ attribute \src "libresoc.v:129967.5-129967.29"
switch \initial
- attribute \src "libresoc.v:131344.9-131344.17"
+ attribute \src "libresoc.v:129967.9-129967.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[63:0]
end
- attribute \src "libresoc.v:131353.3-131361.6"
- process $proc$libresoc.v:131353$5397
+ attribute \src "libresoc.v:129976.3-129984.6"
+ process $proc$libresoc.v:129976$5341
assign { } { }
assign { } { }
- assign $0\ren_delay$10$next[0:0]$5398 $1\ren_delay$10$next[0:0]$5399
- attribute \src "libresoc.v:131354.5-131354.29"
+ assign $0\ren_delay$10$next[0:0]$5342 $1\ren_delay$10$next[0:0]$5343
+ attribute \src "libresoc.v:129977.5-129977.29"
switch \initial
- attribute \src "libresoc.v:131354.9-131354.17"
+ attribute \src "libresoc.v:129977.9-129977.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$10$next[0:0]$5399 1'0
+ assign $1\ren_delay$10$next[0:0]$5343 1'0
case
- assign $1\ren_delay$10$next[0:0]$5399 \src2__ren
+ assign $1\ren_delay$10$next[0:0]$5343 \src2__ren
end
sync always
- update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5398
+ update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5342
end
- attribute \src "libresoc.v:131362.3-131371.6"
- process $proc$libresoc.v:131362$5400
+ attribute \src "libresoc.v:129985.3-129994.6"
+ process $proc$libresoc.v:129985$5344
assign { } { }
assign { } { }
assign $0\src2__data_o[63:0] $1\src2__data_o[63:0]
- attribute \src "libresoc.v:131363.5-131363.29"
+ attribute \src "libresoc.v:129986.5-129986.29"
switch \initial
- attribute \src "libresoc.v:131363.9-131363.17"
+ attribute \src "libresoc.v:129986.9-129986.17"
case 1'1
case
end
sync always
update \src2__data_o $0\src2__data_o[63:0]
end
- attribute \src "libresoc.v:131372.3-131380.6"
- process $proc$libresoc.v:131372$5401
+ attribute \src "libresoc.v:129995.3-130003.6"
+ process $proc$libresoc.v:129995$5345
assign { } { }
assign { } { }
- assign $0\ren_delay$11$next[0:0]$5402 $1\ren_delay$11$next[0:0]$5403
- attribute \src "libresoc.v:131373.5-131373.29"
+ assign $0\ren_delay$11$next[0:0]$5346 $1\ren_delay$11$next[0:0]$5347
+ attribute \src "libresoc.v:129996.5-129996.29"
switch \initial
- attribute \src "libresoc.v:131373.9-131373.17"
+ attribute \src "libresoc.v:129996.9-129996.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$11$next[0:0]$5403 1'0
+ assign $1\ren_delay$11$next[0:0]$5347 1'0
case
- assign $1\ren_delay$11$next[0:0]$5403 \issue__ren
+ assign $1\ren_delay$11$next[0:0]$5347 \issue__ren
end
sync always
- update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5402
+ update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5346
end
- attribute \src "libresoc.v:131381.3-131390.6"
- process $proc$libresoc.v:131381$5404
+ attribute \src "libresoc.v:130004.3-130013.6"
+ process $proc$libresoc.v:130004$5348
assign { } { }
assign { } { }
assign $0\issue__data_o[63:0] $1\issue__data_o[63:0]
- attribute \src "libresoc.v:131382.5-131382.29"
+ attribute \src "libresoc.v:130005.5-130005.29"
switch \initial
- attribute \src "libresoc.v:131382.9-131382.17"
+ attribute \src "libresoc.v:130005.9-130005.17"
case 1'1
case
end
sync always
update \issue__data_o $0\issue__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:131331$5390_DATA
- connect \memory_r_data$4 $memrd$\memory$libresoc.v:131332$5391_DATA
- connect \memory_r_data$6 $memrd$\memory$libresoc.v:131333$5392_DATA
+ connect \memory_r_data $memrd$\memory$libresoc.v:129954$5334_DATA
+ connect \memory_r_data$4 $memrd$\memory$libresoc.v:129955$5335_DATA
+ connect \memory_r_data$6 $memrd$\memory$libresoc.v:129956$5336_DATA
connect \memory_w_data$9 \issue__data_i
connect \memory_w_en$7 \issue__wen
connect \memory_w_addr$8 \issue__addr$1
connect \memory_r_addr$3 \src2__addr
connect \memory_r_addr \src1__addr
end
-attribute \src "libresoc.v:131404.1-133334.10"
+attribute \src "libresoc.v:130027.1-131957.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus"
attribute \generator "nMigen"
module \fus
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 330 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 257 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 286 \xer_so_ok$131
attribute \module_not_derived 1
- attribute \src "libresoc.v:132966.8-133008.4"
+ attribute \src "libresoc.v:131589.8-131631.4"
cell \alu0 \alu0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133009.11-133036.4"
+ attribute \src "libresoc.v:131632.11-131659.4"
cell \branch0 \branch0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src3_i \src3_i$71
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133037.7-133062.4"
+ attribute \src "libresoc.v:131660.7-131685.4"
cell \cr0 \cr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src6_i \src6_i$73
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133063.8-133102.4"
+ attribute \src "libresoc.v:131686.8-131725.4"
cell \div0 \div0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok$130
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133103.9-133157.4"
+ attribute \src "libresoc.v:131726.9-131780.4"
cell \ldst0 \ldst0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src3_i \src3_i$59
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133158.12-133193.4"
+ attribute \src "libresoc.v:131781.12-131816.4"
cell \logical0 \logical0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src3_i \src3_i$61
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133194.8-133227.4"
+ attribute \src "libresoc.v:131817.8-131850.4"
cell \mul0 \mul0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok$131
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133228.13-133266.4"
+ attribute \src "libresoc.v:131851.13-131889.4"
cell \shiftrot0 \shiftrot0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_ca_ok \xer_ca_ok$121
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133267.8-133299.4"
+ attribute \src "libresoc.v:131890.8-131922.4"
cell \spr0 \spr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok$129
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:133300.9-133333.4"
+ attribute \src "libresoc.v:131923.9-131956.4"
cell \trap0 \trap0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \src4_i \src4_i$78
end
end
-attribute \src "libresoc.v:133338.1-133396.10"
+attribute \src "libresoc.v:131961.1-132019.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l"
attribute \generator "nMigen"
module \idx_l
- attribute \src "libresoc.v:133339.7-133339.20"
+ attribute \src "libresoc.v:131962.7-131962.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:133384.3-133392.6"
- wire $0\q_int$next[0:0]$5432
- attribute \src "libresoc.v:133382.3-133383.27"
+ attribute \src "libresoc.v:132007.3-132015.6"
+ wire $0\q_int$next[0:0]$5376
+ attribute \src "libresoc.v:132005.3-132006.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:133384.3-133392.6"
- wire $1\q_int$next[0:0]$5433
- attribute \src "libresoc.v:133363.7-133363.19"
+ attribute \src "libresoc.v:132007.3-132015.6"
+ wire $1\q_int$next[0:0]$5377
+ attribute \src "libresoc.v:131986.7-131986.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:133374.17-133374.96"
- wire $and$libresoc.v:133374$5422_Y
- attribute \src "libresoc.v:133379.17-133379.96"
- wire $and$libresoc.v:133379$5427_Y
- attribute \src "libresoc.v:133376.18-133376.95"
- wire $not$libresoc.v:133376$5424_Y
- attribute \src "libresoc.v:133378.17-133378.94"
- wire $not$libresoc.v:133378$5426_Y
- attribute \src "libresoc.v:133381.17-133381.94"
- wire $not$libresoc.v:133381$5429_Y
- attribute \src "libresoc.v:133375.18-133375.100"
- wire $or$libresoc.v:133375$5423_Y
- attribute \src "libresoc.v:133377.18-133377.101"
- wire $or$libresoc.v:133377$5425_Y
- attribute \src "libresoc.v:133380.17-133380.99"
- wire $or$libresoc.v:133380$5428_Y
+ attribute \src "libresoc.v:131997.17-131997.96"
+ wire $and$libresoc.v:131997$5366_Y
+ attribute \src "libresoc.v:132002.17-132002.96"
+ wire $and$libresoc.v:132002$5371_Y
+ attribute \src "libresoc.v:131999.18-131999.95"
+ wire $not$libresoc.v:131999$5368_Y
+ attribute \src "libresoc.v:132001.17-132001.94"
+ wire $not$libresoc.v:132001$5370_Y
+ attribute \src "libresoc.v:132004.17-132004.94"
+ wire $not$libresoc.v:132004$5373_Y
+ attribute \src "libresoc.v:131998.18-131998.100"
+ wire $or$libresoc.v:131998$5367_Y
+ attribute \src "libresoc.v:132000.18-132000.101"
+ wire $or$libresoc.v:132000$5369_Y
+ attribute \src "libresoc.v:132003.17-132003.99"
+ wire $or$libresoc.v:132003$5372_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:133339.7-133339.15"
+ attribute \src "libresoc.v:131962.7-131962.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire output 2 \q_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:133374$5422
+ cell $and $and$libresoc.v:131997$5366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:133374$5422_Y
+ connect \Y $and$libresoc.v:131997$5366_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:133379$5427
+ cell $and $and$libresoc.v:132002$5371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:133379$5427_Y
+ connect \Y $and$libresoc.v:132002$5371_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:133376$5424
+ cell $not $not$libresoc.v:131999$5368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_idx_l
- connect \Y $not$libresoc.v:133376$5424_Y
+ connect \Y $not$libresoc.v:131999$5368_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:133378$5426
+ cell $not $not$libresoc.v:132001$5370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_idx_l
- connect \Y $not$libresoc.v:133378$5426_Y
+ connect \Y $not$libresoc.v:132001$5370_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:133381$5429
+ cell $not $not$libresoc.v:132004$5373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_idx_l
- connect \Y $not$libresoc.v:133381$5429_Y
+ connect \Y $not$libresoc.v:132004$5373_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:133375$5423
+ cell $or $or$libresoc.v:131998$5367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_idx_l
- connect \Y $or$libresoc.v:133375$5423_Y
+ connect \Y $or$libresoc.v:131998$5367_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:133377$5425
+ cell $or $or$libresoc.v:132000$5369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_idx_l
connect \B \q_int
- connect \Y $or$libresoc.v:133377$5425_Y
+ connect \Y $or$libresoc.v:132000$5369_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:133380$5428
+ cell $or $or$libresoc.v:132003$5372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_idx_l
- connect \Y $or$libresoc.v:133380$5428_Y
+ connect \Y $or$libresoc.v:132003$5372_Y
end
- attribute \src "libresoc.v:133339.7-133339.20"
- process $proc$libresoc.v:133339$5434
+ attribute \src "libresoc.v:131962.7-131962.20"
+ process $proc$libresoc.v:131962$5378
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:133363.7-133363.19"
- process $proc$libresoc.v:133363$5435
+ attribute \src "libresoc.v:131986.7-131986.19"
+ process $proc$libresoc.v:131986$5379
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:133382.3-133383.27"
- process $proc$libresoc.v:133382$5430
+ attribute \src "libresoc.v:132005.3-132006.27"
+ process $proc$libresoc.v:132005$5374
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:133384.3-133392.6"
- process $proc$libresoc.v:133384$5431
+ attribute \src "libresoc.v:132007.3-132015.6"
+ process $proc$libresoc.v:132007$5375
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$5432 $1\q_int$next[0:0]$5433
- attribute \src "libresoc.v:133385.5-133385.29"
+ assign $0\q_int$next[0:0]$5376 $1\q_int$next[0:0]$5377
+ attribute \src "libresoc.v:132008.5-132008.29"
switch \initial
- attribute \src "libresoc.v:133385.9-133385.17"
+ attribute \src "libresoc.v:132008.9-132008.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$5433 1'0
+ assign $1\q_int$next[0:0]$5377 1'0
case
- assign $1\q_int$next[0:0]$5433 \$5
+ assign $1\q_int$next[0:0]$5377 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$5432
+ update \q_int$next $0\q_int$next[0:0]$5376
end
- connect \$9 $and$libresoc.v:133374$5422_Y
- connect \$11 $or$libresoc.v:133375$5423_Y
- connect \$13 $not$libresoc.v:133376$5424_Y
- connect \$15 $or$libresoc.v:133377$5425_Y
- connect \$1 $not$libresoc.v:133378$5426_Y
- connect \$3 $and$libresoc.v:133379$5427_Y
- connect \$5 $or$libresoc.v:133380$5428_Y
- connect \$7 $not$libresoc.v:133381$5429_Y
+ connect \$9 $and$libresoc.v:131997$5366_Y
+ connect \$11 $or$libresoc.v:131998$5367_Y
+ connect \$13 $not$libresoc.v:131999$5368_Y
+ connect \$15 $or$libresoc.v:132000$5369_Y
+ connect \$1 $not$libresoc.v:132001$5370_Y
+ connect \$3 $and$libresoc.v:132002$5371_Y
+ connect \$5 $or$libresoc.v:132003$5372_Y
+ connect \$7 $not$libresoc.v:132004$5373_Y
connect \qlq_idx_l \$15
connect \qn_idx_l \$13
connect \q_idx_l \$11
end
-attribute \src "libresoc.v:133400.1-133779.10"
+attribute \src "libresoc.v:132023.1-132402.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.imem"
attribute \generator "nMigen"
module \imem
- attribute \src "libresoc.v:133731.3-133740.6"
+ attribute \src "libresoc.v:132354.3-132363.6"
wire $0\a_busy_o[0:0]
- attribute \src "libresoc.v:133711.3-133730.6"
- wire width 45 $0\f_badaddr_o$next[44:0]$5504
- attribute \src "libresoc.v:133542.3-133543.39"
+ attribute \src "libresoc.v:132334.3-132353.6"
+ wire width 45 $0\f_badaddr_o$next[44:0]$5448
+ attribute \src "libresoc.v:132165.3-132166.39"
wire width 45 $0\f_badaddr_o[44:0]
- attribute \src "libresoc.v:133741.3-133758.6"
+ attribute \src "libresoc.v:132364.3-132381.6"
wire $0\f_busy_o[0:0]
- attribute \src "libresoc.v:133688.3-133710.6"
- wire $0\f_fetch_err_o$next[0:0]$5499
- attribute \src "libresoc.v:133544.3-133545.43"
+ attribute \src "libresoc.v:132311.3-132333.6"
+ wire $0\f_fetch_err_o$next[0:0]$5443
+ attribute \src "libresoc.v:132167.3-132168.43"
wire $0\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:133759.3-133776.6"
+ attribute \src "libresoc.v:132382.3-132399.6"
wire width 64 $0\f_instr_o[63:0]
- attribute \src "libresoc.v:133665.3-133687.6"
- wire width 45 $0\ibus__adr$next[44:0]$5494
- attribute \src "libresoc.v:133546.3-133547.35"
+ attribute \src "libresoc.v:132288.3-132310.6"
+ wire width 45 $0\ibus__adr$next[44:0]$5438
+ attribute \src "libresoc.v:132169.3-132170.35"
wire width 45 $0\ibus__adr[44:0]
- attribute \src "libresoc.v:133556.3-133583.6"
- wire $0\ibus__cyc$next[0:0]$5470
- attribute \src "libresoc.v:133554.3-133555.35"
+ attribute \src "libresoc.v:132179.3-132206.6"
+ wire $0\ibus__cyc$next[0:0]$5414
+ attribute \src "libresoc.v:132177.3-132178.35"
wire $0\ibus__cyc[0:0]
- attribute \src "libresoc.v:133612.3-133639.6"
- wire width 8 $0\ibus__sel$next[7:0]$5482
- attribute \src "libresoc.v:133550.3-133551.35"
+ attribute \src "libresoc.v:132235.3-132262.6"
+ wire width 8 $0\ibus__sel$next[7:0]$5426
+ attribute \src "libresoc.v:132173.3-132174.35"
wire width 8 $0\ibus__sel[7:0]
- attribute \src "libresoc.v:133584.3-133611.6"
- wire $0\ibus__stb$next[0:0]$5476
- attribute \src "libresoc.v:133552.3-133553.35"
+ attribute \src "libresoc.v:132207.3-132234.6"
+ wire $0\ibus__stb$next[0:0]$5420
+ attribute \src "libresoc.v:132175.3-132176.35"
wire $0\ibus__stb[0:0]
- attribute \src "libresoc.v:133640.3-133664.6"
- wire width 64 $0\ibus_rdata$next[63:0]$5488
- attribute \src "libresoc.v:133548.3-133549.37"
+ attribute \src "libresoc.v:132263.3-132287.6"
+ wire width 64 $0\ibus_rdata$next[63:0]$5432
+ attribute \src "libresoc.v:132171.3-132172.37"
wire width 64 $0\ibus_rdata[63:0]
- attribute \src "libresoc.v:133401.7-133401.20"
+ attribute \src "libresoc.v:132024.7-132024.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:133731.3-133740.6"
+ attribute \src "libresoc.v:132354.3-132363.6"
wire $1\a_busy_o[0:0]
- attribute \src "libresoc.v:133711.3-133730.6"
- wire width 45 $1\f_badaddr_o$next[44:0]$5505
- attribute \src "libresoc.v:133465.14-133465.44"
+ attribute \src "libresoc.v:132334.3-132353.6"
+ wire width 45 $1\f_badaddr_o$next[44:0]$5449
+ attribute \src "libresoc.v:132088.14-132088.44"
wire width 45 $1\f_badaddr_o[44:0]
- attribute \src "libresoc.v:133741.3-133758.6"
+ attribute \src "libresoc.v:132364.3-132381.6"
wire $1\f_busy_o[0:0]
- attribute \src "libresoc.v:133688.3-133710.6"
- wire $1\f_fetch_err_o$next[0:0]$5500
- attribute \src "libresoc.v:133472.7-133472.27"
+ attribute \src "libresoc.v:132311.3-132333.6"
+ wire $1\f_fetch_err_o$next[0:0]$5444
+ attribute \src "libresoc.v:132095.7-132095.27"
wire $1\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:133759.3-133776.6"
+ attribute \src "libresoc.v:132382.3-132399.6"
wire width 64 $1\f_instr_o[63:0]
- attribute \src "libresoc.v:133665.3-133687.6"
- wire width 45 $1\ibus__adr$next[44:0]$5495
- attribute \src "libresoc.v:133486.14-133486.42"
+ attribute \src "libresoc.v:132288.3-132310.6"
+ wire width 45 $1\ibus__adr$next[44:0]$5439
+ attribute \src "libresoc.v:132109.14-132109.42"
wire width 45 $1\ibus__adr[44:0]
- attribute \src "libresoc.v:133556.3-133583.6"
- wire $1\ibus__cyc$next[0:0]$5471
- attribute \src "libresoc.v:133491.7-133491.23"
+ attribute \src "libresoc.v:132179.3-132206.6"
+ wire $1\ibus__cyc$next[0:0]$5415
+ attribute \src "libresoc.v:132114.7-132114.23"
wire $1\ibus__cyc[0:0]
- attribute \src "libresoc.v:133612.3-133639.6"
- wire width 8 $1\ibus__sel$next[7:0]$5483
- attribute \src "libresoc.v:133500.13-133500.30"
+ attribute \src "libresoc.v:132235.3-132262.6"
+ wire width 8 $1\ibus__sel$next[7:0]$5427
+ attribute \src "libresoc.v:132123.13-132123.30"
wire width 8 $1\ibus__sel[7:0]
- attribute \src "libresoc.v:133584.3-133611.6"
- wire $1\ibus__stb$next[0:0]$5477
- attribute \src "libresoc.v:133505.7-133505.23"
+ attribute \src "libresoc.v:132207.3-132234.6"
+ wire $1\ibus__stb$next[0:0]$5421
+ attribute \src "libresoc.v:132128.7-132128.23"
wire $1\ibus__stb[0:0]
- attribute \src "libresoc.v:133640.3-133664.6"
- wire width 64 $1\ibus_rdata$next[63:0]$5489
- attribute \src "libresoc.v:133509.14-133509.47"
+ attribute \src "libresoc.v:132263.3-132287.6"
+ wire width 64 $1\ibus_rdata$next[63:0]$5433
+ attribute \src "libresoc.v:132132.14-132132.47"
wire width 64 $1\ibus_rdata[63:0]
- attribute \src "libresoc.v:133711.3-133730.6"
- wire width 45 $2\f_badaddr_o$next[44:0]$5506
- attribute \src "libresoc.v:133741.3-133758.6"
+ attribute \src "libresoc.v:132334.3-132353.6"
+ wire width 45 $2\f_badaddr_o$next[44:0]$5450
+ attribute \src "libresoc.v:132364.3-132381.6"
wire $2\f_busy_o[0:0]
- attribute \src "libresoc.v:133688.3-133710.6"
- wire $2\f_fetch_err_o$next[0:0]$5501
- attribute \src "libresoc.v:133759.3-133776.6"
+ attribute \src "libresoc.v:132311.3-132333.6"
+ wire $2\f_fetch_err_o$next[0:0]$5445
+ attribute \src "libresoc.v:132382.3-132399.6"
wire width 64 $2\f_instr_o[63:0]
- attribute \src "libresoc.v:133665.3-133687.6"
- wire width 45 $2\ibus__adr$next[44:0]$5496
- attribute \src "libresoc.v:133556.3-133583.6"
- wire $2\ibus__cyc$next[0:0]$5472
- attribute \src "libresoc.v:133612.3-133639.6"
- wire width 8 $2\ibus__sel$next[7:0]$5484
- attribute \src "libresoc.v:133584.3-133611.6"
- wire $2\ibus__stb$next[0:0]$5478
- attribute \src "libresoc.v:133640.3-133664.6"
- wire width 64 $2\ibus_rdata$next[63:0]$5490
- attribute \src "libresoc.v:133711.3-133730.6"
- wire width 45 $3\f_badaddr_o$next[44:0]$5507
- attribute \src "libresoc.v:133688.3-133710.6"
- wire $3\f_fetch_err_o$next[0:0]$5502
- attribute \src "libresoc.v:133665.3-133687.6"
- wire width 45 $3\ibus__adr$next[44:0]$5497
- attribute \src "libresoc.v:133556.3-133583.6"
- wire $3\ibus__cyc$next[0:0]$5473
- attribute \src "libresoc.v:133612.3-133639.6"
- wire width 8 $3\ibus__sel$next[7:0]$5485
- attribute \src "libresoc.v:133584.3-133611.6"
- wire $3\ibus__stb$next[0:0]$5479
- attribute \src "libresoc.v:133640.3-133664.6"
- wire width 64 $3\ibus_rdata$next[63:0]$5491
- attribute \src "libresoc.v:133556.3-133583.6"
- wire $4\ibus__cyc$next[0:0]$5474
- attribute \src "libresoc.v:133612.3-133639.6"
- wire width 8 $4\ibus__sel$next[7:0]$5486
- attribute \src "libresoc.v:133584.3-133611.6"
- wire $4\ibus__stb$next[0:0]$5480
- attribute \src "libresoc.v:133640.3-133664.6"
- wire width 64 $4\ibus_rdata$next[63:0]$5492
- attribute \src "libresoc.v:133518.18-133518.110"
- wire $and$libresoc.v:133518$5438_Y
- attribute \src "libresoc.v:133524.18-133524.110"
- wire $and$libresoc.v:133524$5444_Y
- attribute \src "libresoc.v:133529.18-133529.110"
- wire $and$libresoc.v:133529$5449_Y
- attribute \src "libresoc.v:133532.17-133532.108"
- wire $and$libresoc.v:133532$5452_Y
- attribute \src "libresoc.v:133535.18-133535.110"
- wire $and$libresoc.v:133535$5455_Y
- attribute \src "libresoc.v:133536.18-133536.115"
- wire $and$libresoc.v:133536$5456_Y
- attribute \src "libresoc.v:133538.18-133538.115"
- wire $and$libresoc.v:133538$5458_Y
- attribute \src "libresoc.v:133517.18-133517.105"
- wire $not$libresoc.v:133517$5437_Y
- attribute \src "libresoc.v:133520.18-133520.105"
- wire $not$libresoc.v:133520$5440_Y
- attribute \src "libresoc.v:133521.17-133521.104"
- wire $not$libresoc.v:133521$5441_Y
- attribute \src "libresoc.v:133523.18-133523.105"
- wire $not$libresoc.v:133523$5443_Y
- attribute \src "libresoc.v:133526.18-133526.105"
- wire $not$libresoc.v:133526$5446_Y
- attribute \src "libresoc.v:133528.18-133528.105"
- wire $not$libresoc.v:133528$5448_Y
- attribute \src "libresoc.v:133531.18-133531.105"
- wire $not$libresoc.v:133531$5451_Y
- attribute \src "libresoc.v:133534.18-133534.105"
- wire $not$libresoc.v:133534$5454_Y
- attribute \src "libresoc.v:133537.18-133537.105"
- wire $not$libresoc.v:133537$5457_Y
- attribute \src "libresoc.v:133539.18-133539.105"
- wire $not$libresoc.v:133539$5459_Y
- attribute \src "libresoc.v:133541.17-133541.104"
- wire $not$libresoc.v:133541$5461_Y
- attribute \src "libresoc.v:133516.17-133516.103"
- wire $or$libresoc.v:133516$5436_Y
- attribute \src "libresoc.v:133519.18-133519.115"
- wire $or$libresoc.v:133519$5439_Y
- attribute \src "libresoc.v:133522.18-133522.106"
- wire $or$libresoc.v:133522$5442_Y
- attribute \src "libresoc.v:133525.18-133525.115"
- wire $or$libresoc.v:133525$5445_Y
- attribute \src "libresoc.v:133527.18-133527.106"
- wire $or$libresoc.v:133527$5447_Y
- attribute \src "libresoc.v:133530.18-133530.115"
- wire $or$libresoc.v:133530$5450_Y
- attribute \src "libresoc.v:133533.18-133533.106"
- wire $or$libresoc.v:133533$5453_Y
- attribute \src "libresoc.v:133540.17-133540.114"
- wire $or$libresoc.v:133540$5460_Y
+ attribute \src "libresoc.v:132288.3-132310.6"
+ wire width 45 $2\ibus__adr$next[44:0]$5440
+ attribute \src "libresoc.v:132179.3-132206.6"
+ wire $2\ibus__cyc$next[0:0]$5416
+ attribute \src "libresoc.v:132235.3-132262.6"
+ wire width 8 $2\ibus__sel$next[7:0]$5428
+ attribute \src "libresoc.v:132207.3-132234.6"
+ wire $2\ibus__stb$next[0:0]$5422
+ attribute \src "libresoc.v:132263.3-132287.6"
+ wire width 64 $2\ibus_rdata$next[63:0]$5434
+ attribute \src "libresoc.v:132334.3-132353.6"
+ wire width 45 $3\f_badaddr_o$next[44:0]$5451
+ attribute \src "libresoc.v:132311.3-132333.6"
+ wire $3\f_fetch_err_o$next[0:0]$5446
+ attribute \src "libresoc.v:132288.3-132310.6"
+ wire width 45 $3\ibus__adr$next[44:0]$5441
+ attribute \src "libresoc.v:132179.3-132206.6"
+ wire $3\ibus__cyc$next[0:0]$5417
+ attribute \src "libresoc.v:132235.3-132262.6"
+ wire width 8 $3\ibus__sel$next[7:0]$5429
+ attribute \src "libresoc.v:132207.3-132234.6"
+ wire $3\ibus__stb$next[0:0]$5423
+ attribute \src "libresoc.v:132263.3-132287.6"
+ wire width 64 $3\ibus_rdata$next[63:0]$5435
+ attribute \src "libresoc.v:132179.3-132206.6"
+ wire $4\ibus__cyc$next[0:0]$5418
+ attribute \src "libresoc.v:132235.3-132262.6"
+ wire width 8 $4\ibus__sel$next[7:0]$5430
+ attribute \src "libresoc.v:132207.3-132234.6"
+ wire $4\ibus__stb$next[0:0]$5424
+ attribute \src "libresoc.v:132263.3-132287.6"
+ wire width 64 $4\ibus_rdata$next[63:0]$5436
+ attribute \src "libresoc.v:132141.18-132141.110"
+ wire $and$libresoc.v:132141$5382_Y
+ attribute \src "libresoc.v:132147.18-132147.110"
+ wire $and$libresoc.v:132147$5388_Y
+ attribute \src "libresoc.v:132152.18-132152.110"
+ wire $and$libresoc.v:132152$5393_Y
+ attribute \src "libresoc.v:132155.17-132155.108"
+ wire $and$libresoc.v:132155$5396_Y
+ attribute \src "libresoc.v:132158.18-132158.110"
+ wire $and$libresoc.v:132158$5399_Y
+ attribute \src "libresoc.v:132159.18-132159.115"
+ wire $and$libresoc.v:132159$5400_Y
+ attribute \src "libresoc.v:132161.18-132161.115"
+ wire $and$libresoc.v:132161$5402_Y
+ attribute \src "libresoc.v:132140.18-132140.105"
+ wire $not$libresoc.v:132140$5381_Y
+ attribute \src "libresoc.v:132143.18-132143.105"
+ wire $not$libresoc.v:132143$5384_Y
+ attribute \src "libresoc.v:132144.17-132144.104"
+ wire $not$libresoc.v:132144$5385_Y
+ attribute \src "libresoc.v:132146.18-132146.105"
+ wire $not$libresoc.v:132146$5387_Y
+ attribute \src "libresoc.v:132149.18-132149.105"
+ wire $not$libresoc.v:132149$5390_Y
+ attribute \src "libresoc.v:132151.18-132151.105"
+ wire $not$libresoc.v:132151$5392_Y
+ attribute \src "libresoc.v:132154.18-132154.105"
+ wire $not$libresoc.v:132154$5395_Y
+ attribute \src "libresoc.v:132157.18-132157.105"
+ wire $not$libresoc.v:132157$5398_Y
+ attribute \src "libresoc.v:132160.18-132160.105"
+ wire $not$libresoc.v:132160$5401_Y
+ attribute \src "libresoc.v:132162.18-132162.105"
+ wire $not$libresoc.v:132162$5403_Y
+ attribute \src "libresoc.v:132164.17-132164.104"
+ wire $not$libresoc.v:132164$5405_Y
+ attribute \src "libresoc.v:132139.17-132139.103"
+ wire $or$libresoc.v:132139$5380_Y
+ attribute \src "libresoc.v:132142.18-132142.115"
+ wire $or$libresoc.v:132142$5383_Y
+ attribute \src "libresoc.v:132145.18-132145.106"
+ wire $or$libresoc.v:132145$5386_Y
+ attribute \src "libresoc.v:132148.18-132148.115"
+ wire $or$libresoc.v:132148$5389_Y
+ attribute \src "libresoc.v:132150.18-132150.106"
+ wire $or$libresoc.v:132150$5391_Y
+ attribute \src "libresoc.v:132153.18-132153.115"
+ wire $or$libresoc.v:132153$5394_Y
+ attribute \src "libresoc.v:132156.18-132156.106"
+ wire $or$libresoc.v:132156$5397_Y
+ attribute \src "libresoc.v:132163.17-132163.114"
+ wire $or$libresoc.v:132163$5404_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
wire \a_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
wire input 3 \a_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
wire input 15 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
wire width 45 \f_badaddr_o
wire width 64 \ibus_rdata
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69"
wire width 64 \ibus_rdata$next
- attribute \src "libresoc.v:133401.7-133401.15"
+ attribute \src "libresoc.v:132024.7-132024.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire input 7 \wb_icache_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:133518$5438
+ cell $and $and$libresoc.v:132141$5382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$11
- connect \Y $and$libresoc.v:133518$5438_Y
+ connect \Y $and$libresoc.v:132141$5382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:133524$5444
+ cell $and $and$libresoc.v:132147$5388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$21
- connect \Y $and$libresoc.v:133524$5444_Y
+ connect \Y $and$libresoc.v:132147$5388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:133529$5449
+ cell $and $and$libresoc.v:132152$5393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$31
- connect \Y $and$libresoc.v:133529$5449_Y
+ connect \Y $and$libresoc.v:132152$5393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:133532$5452
+ cell $and $and$libresoc.v:132155$5396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$1
- connect \Y $and$libresoc.v:133532$5452_Y
+ connect \Y $and$libresoc.v:132155$5396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $and $and$libresoc.v:133535$5455
+ cell $and $and$libresoc.v:132158$5399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$41
- connect \Y $and$libresoc.v:133535$5455_Y
+ connect \Y $and$libresoc.v:132158$5399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
- cell $and $and$libresoc.v:133536$5456
+ cell $and $and$libresoc.v:132159$5400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:133536$5456_Y
+ connect \Y $and$libresoc.v:132159$5400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
- cell $and $and$libresoc.v:133538$5458
+ cell $and $and$libresoc.v:132161$5402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:133538$5458_Y
+ connect \Y $and$libresoc.v:132161$5402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:133517$5437
+ cell $not $not$libresoc.v:132140$5381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:133517$5437_Y
+ connect \Y $not$libresoc.v:132140$5381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:133520$5440
+ cell $not $not$libresoc.v:132143$5384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:133520$5440_Y
+ connect \Y $not$libresoc.v:132143$5384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:133521$5441
+ cell $not $not$libresoc.v:132144$5385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:133521$5441_Y
+ connect \Y $not$libresoc.v:132144$5385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:133523$5443
+ cell $not $not$libresoc.v:132146$5387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:133523$5443_Y
+ connect \Y $not$libresoc.v:132146$5387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:133526$5446
+ cell $not $not$libresoc.v:132149$5390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:133526$5446_Y
+ connect \Y $not$libresoc.v:132149$5390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:133528$5448
+ cell $not $not$libresoc.v:132151$5392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:133528$5448_Y
+ connect \Y $not$libresoc.v:132151$5392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:133531$5451
+ cell $not $not$libresoc.v:132154$5395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:133531$5451_Y
+ connect \Y $not$libresoc.v:132154$5395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
- cell $not $not$libresoc.v:133534$5454
+ cell $not $not$libresoc.v:132157$5398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:133534$5454_Y
+ connect \Y $not$libresoc.v:132157$5398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
- cell $not $not$libresoc.v:133537$5457
+ cell $not $not$libresoc.v:132160$5401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:133537$5457_Y
+ connect \Y $not$libresoc.v:132160$5401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
- cell $not $not$libresoc.v:133539$5459
+ cell $not $not$libresoc.v:132162$5403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:133539$5459_Y
+ connect \Y $not$libresoc.v:132162$5403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $not $not$libresoc.v:133541$5461
+ cell $not $not$libresoc.v:132164$5405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:133541$5461_Y
+ connect \Y $not$libresoc.v:132164$5405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133516$5436
+ cell $or $or$libresoc.v:132139$5380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $or$libresoc.v:133516$5436_Y
+ connect \Y $or$libresoc.v:132139$5380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133519$5439
+ cell $or $or$libresoc.v:132142$5383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:133519$5439_Y
+ connect \Y $or$libresoc.v:132142$5383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133522$5442
+ cell $or $or$libresoc.v:132145$5386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \$17
- connect \Y $or$libresoc.v:133522$5442_Y
+ connect \Y $or$libresoc.v:132145$5386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133525$5445
+ cell $or $or$libresoc.v:132148$5389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:133525$5445_Y
+ connect \Y $or$libresoc.v:132148$5389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133527$5447
+ cell $or $or$libresoc.v:132150$5391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$25
connect \B \$27
- connect \Y $or$libresoc.v:133527$5447_Y
+ connect \Y $or$libresoc.v:132150$5391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133530$5450
+ cell $or $or$libresoc.v:132153$5394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:133530$5450_Y
+ connect \Y $or$libresoc.v:132153$5394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133533$5453
+ cell $or $or$libresoc.v:132156$5397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$35
connect \B \$37
- connect \Y $or$libresoc.v:133533$5453_Y
+ connect \Y $or$libresoc.v:132156$5397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
- cell $or $or$libresoc.v:133540$5460
+ cell $or $or$libresoc.v:132163$5404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:133540$5460_Y
+ connect \Y $or$libresoc.v:132163$5404_Y
end
- attribute \src "libresoc.v:133401.7-133401.20"
- process $proc$libresoc.v:133401$5511
+ attribute \src "libresoc.v:132024.7-132024.20"
+ process $proc$libresoc.v:132024$5455
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:133465.14-133465.44"
- process $proc$libresoc.v:133465$5512
+ attribute \src "libresoc.v:132088.14-132088.44"
+ process $proc$libresoc.v:132088$5456
assign { } { }
assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \f_badaddr_o $1\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:133472.7-133472.27"
- process $proc$libresoc.v:133472$5513
+ attribute \src "libresoc.v:132095.7-132095.27"
+ process $proc$libresoc.v:132095$5457
assign { } { }
assign $1\f_fetch_err_o[0:0] 1'0
sync always
sync init
update \f_fetch_err_o $1\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:133486.14-133486.42"
- process $proc$libresoc.v:133486$5514
+ attribute \src "libresoc.v:132109.14-132109.42"
+ process $proc$libresoc.v:132109$5458
assign { } { }
assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \ibus__adr $1\ibus__adr[44:0]
end
- attribute \src "libresoc.v:133491.7-133491.23"
- process $proc$libresoc.v:133491$5515
+ attribute \src "libresoc.v:132114.7-132114.23"
+ process $proc$libresoc.v:132114$5459
assign { } { }
assign $1\ibus__cyc[0:0] 1'0
sync always
sync init
update \ibus__cyc $1\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:133500.13-133500.30"
- process $proc$libresoc.v:133500$5516
+ attribute \src "libresoc.v:132123.13-132123.30"
+ process $proc$libresoc.v:132123$5460
assign { } { }
assign $1\ibus__sel[7:0] 8'00000000
sync always
sync init
update \ibus__sel $1\ibus__sel[7:0]
end
- attribute \src "libresoc.v:133505.7-133505.23"
- process $proc$libresoc.v:133505$5517
+ attribute \src "libresoc.v:132128.7-132128.23"
+ process $proc$libresoc.v:132128$5461
assign { } { }
assign $1\ibus__stb[0:0] 1'0
sync always
sync init
update \ibus__stb $1\ibus__stb[0:0]
end
- attribute \src "libresoc.v:133509.14-133509.47"
- process $proc$libresoc.v:133509$5518
+ attribute \src "libresoc.v:132132.14-132132.47"
+ process $proc$libresoc.v:132132$5462
assign { } { }
assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ibus_rdata $1\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:133542.3-133543.39"
- process $proc$libresoc.v:133542$5462
+ attribute \src "libresoc.v:132165.3-132166.39"
+ process $proc$libresoc.v:132165$5406
assign { } { }
assign $0\f_badaddr_o[44:0] \f_badaddr_o$next
sync posedge \clk
update \f_badaddr_o $0\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:133544.3-133545.43"
- process $proc$libresoc.v:133544$5463
+ attribute \src "libresoc.v:132167.3-132168.43"
+ process $proc$libresoc.v:132167$5407
assign { } { }
assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next
sync posedge \clk
update \f_fetch_err_o $0\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:133546.3-133547.35"
- process $proc$libresoc.v:133546$5464
+ attribute \src "libresoc.v:132169.3-132170.35"
+ process $proc$libresoc.v:132169$5408
assign { } { }
assign $0\ibus__adr[44:0] \ibus__adr$next
sync posedge \clk
update \ibus__adr $0\ibus__adr[44:0]
end
- attribute \src "libresoc.v:133548.3-133549.37"
- process $proc$libresoc.v:133548$5465
+ attribute \src "libresoc.v:132171.3-132172.37"
+ process $proc$libresoc.v:132171$5409
assign { } { }
assign $0\ibus_rdata[63:0] \ibus_rdata$next
sync posedge \clk
update \ibus_rdata $0\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:133550.3-133551.35"
- process $proc$libresoc.v:133550$5466
+ attribute \src "libresoc.v:132173.3-132174.35"
+ process $proc$libresoc.v:132173$5410
assign { } { }
assign $0\ibus__sel[7:0] \ibus__sel$next
sync posedge \clk
update \ibus__sel $0\ibus__sel[7:0]
end
- attribute \src "libresoc.v:133552.3-133553.35"
- process $proc$libresoc.v:133552$5467
+ attribute \src "libresoc.v:132175.3-132176.35"
+ process $proc$libresoc.v:132175$5411
assign { } { }
assign $0\ibus__stb[0:0] \ibus__stb$next
sync posedge \clk
update \ibus__stb $0\ibus__stb[0:0]
end
- attribute \src "libresoc.v:133554.3-133555.35"
- process $proc$libresoc.v:133554$5468
+ attribute \src "libresoc.v:132177.3-132178.35"
+ process $proc$libresoc.v:132177$5412
assign { } { }
assign $0\ibus__cyc[0:0] \ibus__cyc$next
sync posedge \clk
update \ibus__cyc $0\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:133556.3-133583.6"
- process $proc$libresoc.v:133556$5469
+ attribute \src "libresoc.v:132179.3-132206.6"
+ process $proc$libresoc.v:132179$5413
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__cyc$next[0:0]$5470 $4\ibus__cyc$next[0:0]$5474
- attribute \src "libresoc.v:133557.5-133557.29"
+ assign $0\ibus__cyc$next[0:0]$5414 $4\ibus__cyc$next[0:0]$5418
+ attribute \src "libresoc.v:132180.5-132180.29"
switch \initial
- attribute \src "libresoc.v:133557.9-133557.17"
+ attribute \src "libresoc.v:132180.9-132180.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__cyc$next[0:0]$5471 $2\ibus__cyc$next[0:0]$5472
+ assign $1\ibus__cyc$next[0:0]$5415 $2\ibus__cyc$next[0:0]$5416
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$3 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__cyc$next[0:0]$5472 $3\ibus__cyc$next[0:0]$5473
+ assign $2\ibus__cyc$next[0:0]$5416 $3\ibus__cyc$next[0:0]$5417
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__cyc$next[0:0]$5473 1'0
+ assign $3\ibus__cyc$next[0:0]$5417 1'0
case
- assign $3\ibus__cyc$next[0:0]$5473 \ibus__cyc
+ assign $3\ibus__cyc$next[0:0]$5417 \ibus__cyc
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__cyc$next[0:0]$5472 1'1
+ assign $2\ibus__cyc$next[0:0]$5416 1'1
case
- assign $2\ibus__cyc$next[0:0]$5472 \ibus__cyc
+ assign $2\ibus__cyc$next[0:0]$5416 \ibus__cyc
end
case
- assign $1\ibus__cyc$next[0:0]$5471 \ibus__cyc
+ assign $1\ibus__cyc$next[0:0]$5415 \ibus__cyc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__cyc$next[0:0]$5474 1'0
+ assign $4\ibus__cyc$next[0:0]$5418 1'0
case
- assign $4\ibus__cyc$next[0:0]$5474 $1\ibus__cyc$next[0:0]$5471
+ assign $4\ibus__cyc$next[0:0]$5418 $1\ibus__cyc$next[0:0]$5415
end
sync always
- update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5470
+ update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5414
end
- attribute \src "libresoc.v:133584.3-133611.6"
- process $proc$libresoc.v:133584$5475
+ attribute \src "libresoc.v:132207.3-132234.6"
+ process $proc$libresoc.v:132207$5419
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__stb$next[0:0]$5476 $4\ibus__stb$next[0:0]$5480
- attribute \src "libresoc.v:133585.5-133585.29"
+ assign $0\ibus__stb$next[0:0]$5420 $4\ibus__stb$next[0:0]$5424
+ attribute \src "libresoc.v:132208.5-132208.29"
switch \initial
- attribute \src "libresoc.v:133585.9-133585.17"
+ attribute \src "libresoc.v:132208.9-132208.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__stb$next[0:0]$5477 $2\ibus__stb$next[0:0]$5478
+ assign $1\ibus__stb$next[0:0]$5421 $2\ibus__stb$next[0:0]$5422
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$13 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__stb$next[0:0]$5478 $3\ibus__stb$next[0:0]$5479
+ assign $2\ibus__stb$next[0:0]$5422 $3\ibus__stb$next[0:0]$5423
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__stb$next[0:0]$5479 1'0
+ assign $3\ibus__stb$next[0:0]$5423 1'0
case
- assign $3\ibus__stb$next[0:0]$5479 \ibus__stb
+ assign $3\ibus__stb$next[0:0]$5423 \ibus__stb
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__stb$next[0:0]$5478 1'1
+ assign $2\ibus__stb$next[0:0]$5422 1'1
case
- assign $2\ibus__stb$next[0:0]$5478 \ibus__stb
+ assign $2\ibus__stb$next[0:0]$5422 \ibus__stb
end
case
- assign $1\ibus__stb$next[0:0]$5477 \ibus__stb
+ assign $1\ibus__stb$next[0:0]$5421 \ibus__stb
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__stb$next[0:0]$5480 1'0
+ assign $4\ibus__stb$next[0:0]$5424 1'0
case
- assign $4\ibus__stb$next[0:0]$5480 $1\ibus__stb$next[0:0]$5477
+ assign $4\ibus__stb$next[0:0]$5424 $1\ibus__stb$next[0:0]$5421
end
sync always
- update \ibus__stb$next $0\ibus__stb$next[0:0]$5476
+ update \ibus__stb$next $0\ibus__stb$next[0:0]$5420
end
- attribute \src "libresoc.v:133612.3-133639.6"
- process $proc$libresoc.v:133612$5481
+ attribute \src "libresoc.v:132235.3-132262.6"
+ process $proc$libresoc.v:132235$5425
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__sel$next[7:0]$5482 $4\ibus__sel$next[7:0]$5486
- attribute \src "libresoc.v:133613.5-133613.29"
+ assign $0\ibus__sel$next[7:0]$5426 $4\ibus__sel$next[7:0]$5430
+ attribute \src "libresoc.v:132236.5-132236.29"
switch \initial
- attribute \src "libresoc.v:133613.9-133613.17"
+ attribute \src "libresoc.v:132236.9-132236.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__sel$next[7:0]$5483 $2\ibus__sel$next[7:0]$5484
+ assign $1\ibus__sel$next[7:0]$5427 $2\ibus__sel$next[7:0]$5428
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$23 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus__sel$next[7:0]$5484 $3\ibus__sel$next[7:0]$5485
+ assign $2\ibus__sel$next[7:0]$5428 $3\ibus__sel$next[7:0]$5429
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$29
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__sel$next[7:0]$5485 8'00000000
+ assign $3\ibus__sel$next[7:0]$5429 8'00000000
case
- assign $3\ibus__sel$next[7:0]$5485 \ibus__sel
+ assign $3\ibus__sel$next[7:0]$5429 \ibus__sel
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__sel$next[7:0]$5484 8'11111111
+ assign $2\ibus__sel$next[7:0]$5428 8'11111111
case
- assign $2\ibus__sel$next[7:0]$5484 \ibus__sel
+ assign $2\ibus__sel$next[7:0]$5428 \ibus__sel
end
case
- assign $1\ibus__sel$next[7:0]$5483 \ibus__sel
+ assign $1\ibus__sel$next[7:0]$5427 \ibus__sel
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus__sel$next[7:0]$5486 8'00000000
+ assign $4\ibus__sel$next[7:0]$5430 8'00000000
case
- assign $4\ibus__sel$next[7:0]$5486 $1\ibus__sel$next[7:0]$5483
+ assign $4\ibus__sel$next[7:0]$5430 $1\ibus__sel$next[7:0]$5427
end
sync always
- update \ibus__sel$next $0\ibus__sel$next[7:0]$5482
+ update \ibus__sel$next $0\ibus__sel$next[7:0]$5426
end
- attribute \src "libresoc.v:133640.3-133664.6"
- process $proc$libresoc.v:133640$5487
+ attribute \src "libresoc.v:132263.3-132287.6"
+ process $proc$libresoc.v:132263$5431
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus_rdata$next[63:0]$5488 $4\ibus_rdata$next[63:0]$5492
- attribute \src "libresoc.v:133641.5-133641.29"
+ assign $0\ibus_rdata$next[63:0]$5432 $4\ibus_rdata$next[63:0]$5436
+ attribute \src "libresoc.v:132264.5-132264.29"
switch \initial
- attribute \src "libresoc.v:133641.9-133641.17"
+ attribute \src "libresoc.v:132264.9-132264.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus_rdata$next[63:0]$5489 $2\ibus_rdata$next[63:0]$5490
+ assign $1\ibus_rdata$next[63:0]$5433 $2\ibus_rdata$next[63:0]$5434
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$33 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\ibus_rdata$next[63:0]$5490 $3\ibus_rdata$next[63:0]$5491
+ assign $2\ibus_rdata$next[63:0]$5434 $3\ibus_rdata$next[63:0]$5435
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
switch \$39
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus_rdata$next[63:0]$5491 \ibus__dat_r
+ assign $3\ibus_rdata$next[63:0]$5435 \ibus__dat_r
case
- assign $3\ibus_rdata$next[63:0]$5491 \ibus_rdata
+ assign $3\ibus_rdata$next[63:0]$5435 \ibus_rdata
end
case
- assign $2\ibus_rdata$next[63:0]$5490 \ibus_rdata
+ assign $2\ibus_rdata$next[63:0]$5434 \ibus_rdata
end
case
- assign $1\ibus_rdata$next[63:0]$5489 \ibus_rdata
+ assign $1\ibus_rdata$next[63:0]$5433 \ibus_rdata
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\ibus_rdata$next[63:0]$5492 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $4\ibus_rdata$next[63:0]$5436 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $4\ibus_rdata$next[63:0]$5492 $1\ibus_rdata$next[63:0]$5489
+ assign $4\ibus_rdata$next[63:0]$5436 $1\ibus_rdata$next[63:0]$5433
end
sync always
- update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5488
+ update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5432
end
- attribute \src "libresoc.v:133665.3-133687.6"
- process $proc$libresoc.v:133665$5493
+ attribute \src "libresoc.v:132288.3-132310.6"
+ process $proc$libresoc.v:132288$5437
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__adr$next[44:0]$5494 $3\ibus__adr$next[44:0]$5497
- attribute \src "libresoc.v:133666.5-133666.29"
+ assign $0\ibus__adr$next[44:0]$5438 $3\ibus__adr$next[44:0]$5441
+ attribute \src "libresoc.v:132289.5-132289.29"
switch \initial
- attribute \src "libresoc.v:133666.9-133666.17"
+ attribute \src "libresoc.v:132289.9-132289.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ibus__adr$next[44:0]$5495 $2\ibus__adr$next[44:0]$5496
+ assign $1\ibus__adr$next[44:0]$5439 $2\ibus__adr$next[44:0]$5440
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
switch { \$43 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\ibus__adr$next[44:0]$5496 \ibus__adr
+ assign $2\ibus__adr$next[44:0]$5440 \ibus__adr
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\ibus__adr$next[44:0]$5496 \a_pc_i [47:3]
+ assign $2\ibus__adr$next[44:0]$5440 \a_pc_i [47:3]
case
- assign $2\ibus__adr$next[44:0]$5496 \ibus__adr
+ assign $2\ibus__adr$next[44:0]$5440 \ibus__adr
end
case
- assign $1\ibus__adr$next[44:0]$5495 \ibus__adr
+ assign $1\ibus__adr$next[44:0]$5439 \ibus__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__adr$next[44:0]$5497 45'000000000000000000000000000000000000000000000
+ assign $3\ibus__adr$next[44:0]$5441 45'000000000000000000000000000000000000000000000
case
- assign $3\ibus__adr$next[44:0]$5497 $1\ibus__adr$next[44:0]$5495
+ assign $3\ibus__adr$next[44:0]$5441 $1\ibus__adr$next[44:0]$5439
end
sync always
- update \ibus__adr$next $0\ibus__adr$next[44:0]$5494
+ update \ibus__adr$next $0\ibus__adr$next[44:0]$5438
end
- attribute \src "libresoc.v:133688.3-133710.6"
- process $proc$libresoc.v:133688$5498
+ attribute \src "libresoc.v:132311.3-132333.6"
+ process $proc$libresoc.v:132311$5442
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_fetch_err_o$next[0:0]$5499 $3\f_fetch_err_o$next[0:0]$5502
- attribute \src "libresoc.v:133689.5-133689.29"
+ assign $0\f_fetch_err_o$next[0:0]$5443 $3\f_fetch_err_o$next[0:0]$5446
+ attribute \src "libresoc.v:132312.5-132312.29"
switch \initial
- attribute \src "libresoc.v:133689.9-133689.17"
+ attribute \src "libresoc.v:132312.9-132312.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\f_fetch_err_o$next[0:0]$5500 $2\f_fetch_err_o$next[0:0]$5501
+ assign $1\f_fetch_err_o$next[0:0]$5444 $2\f_fetch_err_o$next[0:0]$5445
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
switch { \$47 \$45 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\f_fetch_err_o$next[0:0]$5501 1'1
+ assign $2\f_fetch_err_o$next[0:0]$5445 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\f_fetch_err_o$next[0:0]$5501 1'0
+ assign $2\f_fetch_err_o$next[0:0]$5445 1'0
case
- assign $2\f_fetch_err_o$next[0:0]$5501 \f_fetch_err_o
+ assign $2\f_fetch_err_o$next[0:0]$5445 \f_fetch_err_o
end
case
- assign $1\f_fetch_err_o$next[0:0]$5500 \f_fetch_err_o
+ assign $1\f_fetch_err_o$next[0:0]$5444 \f_fetch_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\f_fetch_err_o$next[0:0]$5502 1'0
+ assign $3\f_fetch_err_o$next[0:0]$5446 1'0
case
- assign $3\f_fetch_err_o$next[0:0]$5502 $1\f_fetch_err_o$next[0:0]$5500
+ assign $3\f_fetch_err_o$next[0:0]$5446 $1\f_fetch_err_o$next[0:0]$5444
end
sync always
- update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5499
+ update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5443
end
- attribute \src "libresoc.v:133711.3-133730.6"
- process $proc$libresoc.v:133711$5503
+ attribute \src "libresoc.v:132334.3-132353.6"
+ process $proc$libresoc.v:132334$5447
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_badaddr_o$next[44:0]$5504 $3\f_badaddr_o$next[44:0]$5507
- attribute \src "libresoc.v:133712.5-133712.29"
+ assign $0\f_badaddr_o$next[44:0]$5448 $3\f_badaddr_o$next[44:0]$5451
+ attribute \src "libresoc.v:132335.5-132335.29"
switch \initial
- attribute \src "libresoc.v:133712.9-133712.17"
+ attribute \src "libresoc.v:132335.9-132335.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\f_badaddr_o$next[44:0]$5505 $2\f_badaddr_o$next[44:0]$5506
+ assign $1\f_badaddr_o$next[44:0]$5449 $2\f_badaddr_o$next[44:0]$5450
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
switch { \$51 \$49 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\f_badaddr_o$next[44:0]$5506 \ibus__adr
+ assign $2\f_badaddr_o$next[44:0]$5450 \ibus__adr
case
- assign $2\f_badaddr_o$next[44:0]$5506 \f_badaddr_o
+ assign $2\f_badaddr_o$next[44:0]$5450 \f_badaddr_o
end
case
- assign $1\f_badaddr_o$next[44:0]$5505 \f_badaddr_o
+ assign $1\f_badaddr_o$next[44:0]$5449 \f_badaddr_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\f_badaddr_o$next[44:0]$5507 45'000000000000000000000000000000000000000000000
+ assign $3\f_badaddr_o$next[44:0]$5451 45'000000000000000000000000000000000000000000000
case
- assign $3\f_badaddr_o$next[44:0]$5507 $1\f_badaddr_o$next[44:0]$5505
+ assign $3\f_badaddr_o$next[44:0]$5451 $1\f_badaddr_o$next[44:0]$5449
end
sync always
- update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5504
+ update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5448
end
- attribute \src "libresoc.v:133731.3-133740.6"
- process $proc$libresoc.v:133731$5508
+ attribute \src "libresoc.v:132354.3-132363.6"
+ process $proc$libresoc.v:132354$5452
assign { } { }
assign { } { }
assign $0\a_busy_o[0:0] $1\a_busy_o[0:0]
- attribute \src "libresoc.v:133732.5-133732.29"
+ attribute \src "libresoc.v:132355.5-132355.29"
switch \initial
- attribute \src "libresoc.v:133732.9-133732.17"
+ attribute \src "libresoc.v:132355.9-132355.17"
case 1'1
case
end
sync always
update \a_busy_o $0\a_busy_o[0:0]
end
- attribute \src "libresoc.v:133741.3-133758.6"
- process $proc$libresoc.v:133741$5509
+ attribute \src "libresoc.v:132364.3-132381.6"
+ process $proc$libresoc.v:132364$5453
assign { } { }
assign { } { }
assign $0\f_busy_o[0:0] $1\f_busy_o[0:0]
- attribute \src "libresoc.v:133742.5-133742.29"
+ attribute \src "libresoc.v:132365.5-132365.29"
switch \initial
- attribute \src "libresoc.v:133742.9-133742.17"
+ attribute \src "libresoc.v:132365.9-132365.17"
case 1'1
case
end
sync always
update \f_busy_o $0\f_busy_o[0:0]
end
- attribute \src "libresoc.v:133759.3-133776.6"
- process $proc$libresoc.v:133759$5510
+ attribute \src "libresoc.v:132382.3-132399.6"
+ process $proc$libresoc.v:132382$5454
assign { } { }
assign { } { }
assign $0\f_instr_o[63:0] $1\f_instr_o[63:0]
- attribute \src "libresoc.v:133760.5-133760.29"
+ attribute \src "libresoc.v:132383.5-132383.29"
switch \initial
- attribute \src "libresoc.v:133760.9-133760.17"
+ attribute \src "libresoc.v:132383.9-132383.17"
case 1'1
case
end
sync always
update \f_instr_o $0\f_instr_o[63:0]
end
- connect \$9 $or$libresoc.v:133516$5436_Y
- connect \$11 $not$libresoc.v:133517$5437_Y
- connect \$13 $and$libresoc.v:133518$5438_Y
- connect \$15 $or$libresoc.v:133519$5439_Y
- connect \$17 $not$libresoc.v:133520$5440_Y
- connect \$1 $not$libresoc.v:133521$5441_Y
- connect \$19 $or$libresoc.v:133522$5442_Y
- connect \$21 $not$libresoc.v:133523$5443_Y
- connect \$23 $and$libresoc.v:133524$5444_Y
- connect \$25 $or$libresoc.v:133525$5445_Y
- connect \$27 $not$libresoc.v:133526$5446_Y
- connect \$29 $or$libresoc.v:133527$5447_Y
- connect \$31 $not$libresoc.v:133528$5448_Y
- connect \$33 $and$libresoc.v:133529$5449_Y
- connect \$35 $or$libresoc.v:133530$5450_Y
- connect \$37 $not$libresoc.v:133531$5451_Y
- connect \$3 $and$libresoc.v:133532$5452_Y
- connect \$39 $or$libresoc.v:133533$5453_Y
- connect \$41 $not$libresoc.v:133534$5454_Y
- connect \$43 $and$libresoc.v:133535$5455_Y
- connect \$45 $and$libresoc.v:133536$5456_Y
- connect \$47 $not$libresoc.v:133537$5457_Y
- connect \$49 $and$libresoc.v:133538$5458_Y
- connect \$51 $not$libresoc.v:133539$5459_Y
- connect \$5 $or$libresoc.v:133540$5460_Y
- connect \$7 $not$libresoc.v:133541$5461_Y
+ connect \$9 $or$libresoc.v:132139$5380_Y
+ connect \$11 $not$libresoc.v:132140$5381_Y
+ connect \$13 $and$libresoc.v:132141$5382_Y
+ connect \$15 $or$libresoc.v:132142$5383_Y
+ connect \$17 $not$libresoc.v:132143$5384_Y
+ connect \$1 $not$libresoc.v:132144$5385_Y
+ connect \$19 $or$libresoc.v:132145$5386_Y
+ connect \$21 $not$libresoc.v:132146$5387_Y
+ connect \$23 $and$libresoc.v:132147$5388_Y
+ connect \$25 $or$libresoc.v:132148$5389_Y
+ connect \$27 $not$libresoc.v:132149$5390_Y
+ connect \$29 $or$libresoc.v:132150$5391_Y
+ connect \$31 $not$libresoc.v:132151$5392_Y
+ connect \$33 $and$libresoc.v:132152$5393_Y
+ connect \$35 $or$libresoc.v:132153$5394_Y
+ connect \$37 $not$libresoc.v:132154$5395_Y
+ connect \$3 $and$libresoc.v:132155$5396_Y
+ connect \$39 $or$libresoc.v:132156$5397_Y
+ connect \$41 $not$libresoc.v:132157$5398_Y
+ connect \$43 $and$libresoc.v:132158$5399_Y
+ connect \$45 $and$libresoc.v:132159$5400_Y
+ connect \$47 $not$libresoc.v:132160$5401_Y
+ connect \$49 $and$libresoc.v:132161$5402_Y
+ connect \$51 $not$libresoc.v:132162$5403_Y
+ connect \$5 $or$libresoc.v:132163$5404_Y
+ connect \$7 $not$libresoc.v:132164$5405_Y
connect \a_stall_i 1'0
connect \f_stall_i 1'0
end
-attribute \src "libresoc.v:133783.1-133943.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.in1_svdec"
-attribute \generator "nMigen"
-module \in1_svdec
- attribute \src "libresoc.v:133878.3-133894.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:133895.3-133911.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:133912.3-133928.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:133784.7-133784.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:133929.3-133940.6"
- wire width 7 $0\reg_out[6:0]
- attribute \src "libresoc.v:133819.3-133877.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:133878.3-133894.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:133895.3-133911.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:133912.3-133928.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:133929.3-133940.6"
- wire width 7 $1\reg_out[6:0]
- attribute \src "libresoc.v:133819.3-133877.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:133878.3-133894.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:133895.3-133911.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:133912.3-133928.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:133819.3-133877.6"
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- wire width 2 input 1 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 6 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
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- attribute \enum_value_100 "Idx3"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 5 \idx
- attribute \src "libresoc.v:133784.7-133784.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire output 3 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 input 2 \reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 output 4 \reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101"
- wire width 2 \spec_aug
- attribute \src "libresoc.v:133784.7-133784.20"
- process $proc$libresoc.v:133784$5524
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:133819.3-133877.6"
- process $proc$libresoc.v:133819$5519
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:133820.5-133820.29"
- switch \initial
- attribute \src "libresoc.v:133820.9-133820.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:133878.3-133894.6"
- process $proc$libresoc.v:133878$5520
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:133879.5-133879.29"
- switch \initial
- attribute \src "libresoc.v:133879.9-133879.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:133895.3-133911.6"
- process $proc$libresoc.v:133895$5521
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:133896.5-133896.29"
- switch \initial
- attribute \src "libresoc.v:133896.9-133896.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:133912.3-133928.6"
- process $proc$libresoc.v:133912$5522
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:133913.5-133913.29"
- switch \initial
- attribute \src "libresoc.v:133913.9-133913.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:133929.3-133940.6"
- process $proc$libresoc.v:133929$5523
- assign { } { }
- assign $0\reg_out[6:0] $1\reg_out[6:0]
- attribute \src "libresoc.v:133930.5-133930.29"
- switch \initial
- attribute \src "libresoc.v:133930.9-133930.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg_out[6:0] { \reg_in \spec_aug }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\reg_out[6:0] { \spec_aug \reg_in }
- end
- sync always
- update \reg_out $0\reg_out[6:0]
- end
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:133947.1-134107.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.in2_svdec"
-attribute \generator "nMigen"
-module \in2_svdec
- attribute \src "libresoc.v:134042.3-134058.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:134059.3-134075.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:134076.3-134092.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:133948.7-133948.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:134093.3-134104.6"
- wire width 7 $0\reg_out[6:0]
- attribute \src "libresoc.v:133983.3-134041.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:134042.3-134058.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:134059.3-134075.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:134076.3-134092.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:134093.3-134104.6"
- wire width 7 $1\reg_out[6:0]
- attribute \src "libresoc.v:133983.3-134041.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:134042.3-134058.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:134059.3-134075.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:134076.3-134092.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:133983.3-134041.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:133983.3-134041.6"
- wire width 3 $3\spec[2:0]
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 1 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 6 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 5 \idx
- attribute \src "libresoc.v:133948.7-133948.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire output 3 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 input 2 \reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 output 4 \reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101"
- wire width 2 \spec_aug
- attribute \src "libresoc.v:133948.7-133948.20"
- process $proc$libresoc.v:133948$5530
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:133983.3-134041.6"
- process $proc$libresoc.v:133983$5525
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:133984.5-133984.29"
- switch \initial
- attribute \src "libresoc.v:133984.9-133984.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:134042.3-134058.6"
- process $proc$libresoc.v:134042$5526
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:134043.5-134043.29"
- switch \initial
- attribute \src "libresoc.v:134043.9-134043.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:134059.3-134075.6"
- process $proc$libresoc.v:134059$5527
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:134060.5-134060.29"
- switch \initial
- attribute \src "libresoc.v:134060.9-134060.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:134076.3-134092.6"
- process $proc$libresoc.v:134076$5528
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:134077.5-134077.29"
- switch \initial
- attribute \src "libresoc.v:134077.9-134077.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:134093.3-134104.6"
- process $proc$libresoc.v:134093$5529
- assign { } { }
- assign $0\reg_out[6:0] $1\reg_out[6:0]
- attribute \src "libresoc.v:134094.5-134094.29"
- switch \initial
- attribute \src "libresoc.v:134094.9-134094.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg_out[6:0] { \reg_in \spec_aug }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\reg_out[6:0] { \spec_aug \reg_in }
- end
- sync always
- update \reg_out $0\reg_out[6:0]
- end
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:134111.1-134271.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.in3_svdec"
-attribute \generator "nMigen"
-module \in3_svdec
- attribute \src "libresoc.v:134206.3-134222.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:134223.3-134239.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:134240.3-134256.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:134112.7-134112.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:134257.3-134268.6"
- wire width 7 $0\reg_out[6:0]
- attribute \src "libresoc.v:134147.3-134205.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:134206.3-134222.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:134223.3-134239.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:134240.3-134256.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:134257.3-134268.6"
- wire width 7 $1\reg_out[6:0]
- attribute \src "libresoc.v:134147.3-134205.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:134206.3-134222.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:134223.3-134239.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:134240.3-134256.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:134147.3-134205.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:134147.3-134205.6"
- wire width 3 $3\spec[2:0]
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 1 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 6 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 5 \idx
- attribute \src "libresoc.v:134112.7-134112.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire output 3 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 input 2 \reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 output 4 \reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101"
- wire width 2 \spec_aug
- attribute \src "libresoc.v:134112.7-134112.20"
- process $proc$libresoc.v:134112$5536
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:134147.3-134205.6"
- process $proc$libresoc.v:134147$5531
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:134148.5-134148.29"
- switch \initial
- attribute \src "libresoc.v:134148.9-134148.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:134206.3-134222.6"
- process $proc$libresoc.v:134206$5532
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:134207.5-134207.29"
- switch \initial
- attribute \src "libresoc.v:134207.9-134207.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:134223.3-134239.6"
- process $proc$libresoc.v:134223$5533
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:134224.5-134224.29"
- switch \initial
- attribute \src "libresoc.v:134224.9-134224.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:134240.3-134256.6"
- process $proc$libresoc.v:134240$5534
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:134241.5-134241.29"
- switch \initial
- attribute \src "libresoc.v:134241.9-134241.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:134257.3-134268.6"
- process $proc$libresoc.v:134257$5535
- assign { } { }
- assign $0\reg_out[6:0] $1\reg_out[6:0]
- attribute \src "libresoc.v:134258.5-134258.29"
- switch \initial
- attribute \src "libresoc.v:134258.9-134258.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg_out[6:0] { \reg_in \spec_aug }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\reg_out[6:0] { \spec_aug \reg_in }
- end
- sync always
- update \reg_out $0\reg_out[6:0]
- end
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:134275.1-134598.10"
+attribute \src "libresoc.v:132406.1-132729.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input"
attribute \generator "nMigen"
module \input
- attribute \src "libresoc.v:134561.3-134572.6"
+ attribute \src "libresoc.v:132692.3-132703.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:134276.7-134276.20"
+ attribute \src "libresoc.v:132407.7-132407.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:134573.3-134591.6"
- wire width 2 $0\xer_ca$23[1:0]$5540
- attribute \src "libresoc.v:134561.3-134572.6"
+ attribute \src "libresoc.v:132704.3-132722.6"
+ wire width 2 $0\xer_ca$23[1:0]$5466
+ attribute \src "libresoc.v:132692.3-132703.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:134573.3-134591.6"
- wire width 2 $1\xer_ca$23[1:0]$5541
- attribute \src "libresoc.v:134560.18-134560.100"
- wire width 64 $not$libresoc.v:134560$5537_Y
+ attribute \src "libresoc.v:132704.3-132722.6"
+ wire width 2 $1\xer_ca$23[1:0]$5467
+ attribute \src "libresoc.v:132691.18-132691.100"
+ wire width 64 $not$libresoc.v:132691$5463_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire output 33 \alu_op__zero_a$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:134276.7-134276.15"
+ attribute \src "libresoc.v:132407.7-132407.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 46 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 44 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:134560$5537
+ cell $not $not$libresoc.v:132691$5463
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:134560$5537_Y
+ connect \Y $not$libresoc.v:132691$5463_Y
end
- attribute \src "libresoc.v:134276.7-134276.20"
- process $proc$libresoc.v:134276$5542
+ attribute \src "libresoc.v:132407.7-132407.20"
+ process $proc$libresoc.v:132407$5468
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:134561.3-134572.6"
- process $proc$libresoc.v:134561$5538
+ attribute \src "libresoc.v:132692.3-132703.6"
+ process $proc$libresoc.v:132692$5464
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:134562.5-134562.29"
+ attribute \src "libresoc.v:132693.5-132693.29"
switch \initial
- attribute \src "libresoc.v:134562.9-134562.17"
+ attribute \src "libresoc.v:132693.9-132693.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:134573.3-134591.6"
- process $proc$libresoc.v:134573$5539
+ attribute \src "libresoc.v:132704.3-132722.6"
+ process $proc$libresoc.v:132704$5465
assign { } { }
assign { } { }
- assign $0\xer_ca$23[1:0]$5540 $1\xer_ca$23[1:0]$5541
- attribute \src "libresoc.v:134574.5-134574.29"
+ assign $0\xer_ca$23[1:0]$5466 $1\xer_ca$23[1:0]$5467
+ attribute \src "libresoc.v:132705.5-132705.29"
switch \initial
- attribute \src "libresoc.v:134574.9-134574.17"
+ attribute \src "libresoc.v:132705.9-132705.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\xer_ca$23[1:0]$5541 2'00
+ assign $1\xer_ca$23[1:0]$5467 2'00
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\xer_ca$23[1:0]$5541 2'11
+ assign $1\xer_ca$23[1:0]$5467 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\xer_ca$23[1:0]$5541 \xer_ca
+ assign $1\xer_ca$23[1:0]$5467 \xer_ca
case
- assign $1\xer_ca$23[1:0]$5541 2'00
+ assign $1\xer_ca$23[1:0]$5467 2'00
end
sync always
- update \xer_ca$23 $0\xer_ca$23[1:0]$5540
+ update \xer_ca$23 $0\xer_ca$23[1:0]$5466
end
- connect \$24 $not$libresoc.v:134560$5537_Y
+ connect \$24 $not$libresoc.v:132691$5463_Y
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \b \rb
connect \ra$20 \a
end
-attribute \src "libresoc.v:134602.1-134926.10"
+attribute \src "libresoc.v:132733.1-133057.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input"
attribute \generator "nMigen"
module \input$113
- attribute \src "libresoc.v:134888.3-134899.6"
+ attribute \src "libresoc.v:133019.3-133030.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:134603.7-134603.20"
+ attribute \src "libresoc.v:132734.7-132734.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:134900.3-134918.6"
- wire width 2 $0\xer_ca$23[1:0]$5546
- attribute \src "libresoc.v:134888.3-134899.6"
+ attribute \src "libresoc.v:133031.3-133049.6"
+ wire width 2 $0\xer_ca$23[1:0]$5472
+ attribute \src "libresoc.v:133019.3-133030.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:134900.3-134918.6"
- wire width 2 $1\xer_ca$23[1:0]$5547
- attribute \src "libresoc.v:134887.18-134887.100"
- wire width 64 $not$libresoc.v:134887$5543_Y
+ attribute \src "libresoc.v:133031.3-133049.6"
+ wire width 2 $1\xer_ca$23[1:0]$5473
+ attribute \src "libresoc.v:133018.18-133018.100"
+ wire width 64 $not$libresoc.v:133018$5469_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:134603.7-134603.15"
+ attribute \src "libresoc.v:132734.7-132734.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 46 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 44 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:134887$5543
+ cell $not $not$libresoc.v:133018$5469
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:134887$5543_Y
+ connect \Y $not$libresoc.v:133018$5469_Y
end
- attribute \src "libresoc.v:134603.7-134603.20"
- process $proc$libresoc.v:134603$5548
+ attribute \src "libresoc.v:132734.7-132734.20"
+ process $proc$libresoc.v:132734$5474
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:134888.3-134899.6"
- process $proc$libresoc.v:134888$5544
+ attribute \src "libresoc.v:133019.3-133030.6"
+ process $proc$libresoc.v:133019$5470
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:134889.5-134889.29"
+ attribute \src "libresoc.v:133020.5-133020.29"
switch \initial
- attribute \src "libresoc.v:134889.9-134889.17"
+ attribute \src "libresoc.v:133020.9-133020.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:134900.3-134918.6"
- process $proc$libresoc.v:134900$5545
+ attribute \src "libresoc.v:133031.3-133049.6"
+ process $proc$libresoc.v:133031$5471
assign { } { }
assign { } { }
- assign $0\xer_ca$23[1:0]$5546 $1\xer_ca$23[1:0]$5547
- attribute \src "libresoc.v:134901.5-134901.29"
+ assign $0\xer_ca$23[1:0]$5472 $1\xer_ca$23[1:0]$5473
+ attribute \src "libresoc.v:133032.5-133032.29"
switch \initial
- attribute \src "libresoc.v:134901.9-134901.17"
+ attribute \src "libresoc.v:133032.9-133032.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\xer_ca$23[1:0]$5547 2'00
+ assign $1\xer_ca$23[1:0]$5473 2'00
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\xer_ca$23[1:0]$5547 2'11
+ assign $1\xer_ca$23[1:0]$5473 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\xer_ca$23[1:0]$5547 \xer_ca
+ assign $1\xer_ca$23[1:0]$5473 \xer_ca
case
- assign $1\xer_ca$23[1:0]$5547 2'00
+ assign $1\xer_ca$23[1:0]$5473 2'00
end
sync always
- update \xer_ca$23 $0\xer_ca$23[1:0]$5546
+ update \xer_ca$23 $0\xer_ca$23[1:0]$5472
end
- connect \$24 $not$libresoc.v:134887$5543_Y
+ connect \$24 $not$libresoc.v:133018$5469_Y
connect \rc$21 \rc
connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \muxid$1 \muxid
connect \b \rb
connect \ra$19 \a
end
-attribute \src "libresoc.v:134930.1-135229.10"
+attribute \src "libresoc.v:133061.1-133360.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input"
attribute \generator "nMigen"
module \input$50
- attribute \src "libresoc.v:135211.3-135222.6"
+ attribute \src "libresoc.v:133342.3-133353.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:134931.7-134931.20"
+ attribute \src "libresoc.v:133062.7-133062.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:135211.3-135222.6"
+ attribute \src "libresoc.v:133342.3-133353.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:135210.18-135210.100"
- wire width 64 $not$libresoc.v:135210$5549_Y
+ attribute \src "libresoc.v:133341.18-133341.100"
+ wire width 64 $not$libresoc.v:133341$5475_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43"
wire width 64 \$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:134931.7-134931.15"
+ attribute \src "libresoc.v:133062.7-133062.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 43 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43"
- cell $not $not$libresoc.v:135210$5549
+ cell $not $not$libresoc.v:133341$5475
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \rb
- connect \Y $not$libresoc.v:135210$5549_Y
+ connect \Y $not$libresoc.v:133341$5475_Y
end
- attribute \src "libresoc.v:134931.7-134931.20"
- process $proc$libresoc.v:134931$5551
+ attribute \src "libresoc.v:133062.7-133062.20"
+ process $proc$libresoc.v:133062$5477
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:135211.3-135222.6"
- process $proc$libresoc.v:135211$5550
+ attribute \src "libresoc.v:133342.3-133353.6"
+ process $proc$libresoc.v:133342$5476
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:135212.5-135212.29"
+ attribute \src "libresoc.v:133343.5-133343.29"
switch \initial
- attribute \src "libresoc.v:135212.9-135212.17"
+ attribute \src "libresoc.v:133343.9-133343.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- connect \$23 $not$libresoc.v:135210$5549_Y
+ connect \$23 $not$libresoc.v:133341$5475_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \ra$20 \a
connect \a \ra
end
-attribute \src "libresoc.v:135233.1-135532.10"
+attribute \src "libresoc.v:133364.1-133663.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input"
attribute \generator "nMigen"
module \input$78
- attribute \src "libresoc.v:135514.3-135525.6"
+ attribute \src "libresoc.v:133645.3-133656.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:135234.7-135234.20"
+ attribute \src "libresoc.v:133365.7-133365.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:135514.3-135525.6"
+ attribute \src "libresoc.v:133645.3-133656.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:135513.18-135513.100"
- wire width 64 $not$libresoc.v:135513$5552_Y
+ attribute \src "libresoc.v:133644.18-133644.100"
+ wire width 64 $not$libresoc.v:133644$5478_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
wire width 64 \$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
wire width 64 \b
- attribute \src "libresoc.v:135234.7-135234.15"
+ attribute \src "libresoc.v:133365.7-133365.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 43 \xer_so$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28"
- cell $not $not$libresoc.v:135513$5552
+ cell $not $not$libresoc.v:133644$5478
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:135513$5552_Y
+ connect \Y $not$libresoc.v:133644$5478_Y
end
- attribute \src "libresoc.v:135234.7-135234.20"
- process $proc$libresoc.v:135234$5554
+ attribute \src "libresoc.v:133365.7-133365.20"
+ process $proc$libresoc.v:133365$5480
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:135514.3-135525.6"
- process $proc$libresoc.v:135514$5553
+ attribute \src "libresoc.v:133645.3-133656.6"
+ process $proc$libresoc.v:133645$5479
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:135515.5-135515.29"
+ attribute \src "libresoc.v:133646.5-133646.29"
switch \initial
- attribute \src "libresoc.v:135515.9-135515.17"
+ attribute \src "libresoc.v:133646.9-133646.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- connect \$23 $not$libresoc.v:135513$5552_Y
+ connect \$23 $not$libresoc.v:133644$5478_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$22 \xer_so
connect \b \rb
connect \ra$20 \a
end
-attribute \src "libresoc.v:135536.1-135788.10"
+attribute \src "libresoc.v:133667.1-133919.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input"
attribute \generator "nMigen"
connect \ra$14 \a
connect \a \ra
end
-attribute \src "libresoc.v:135792.1-136011.10"
+attribute \src "libresoc.v:133923.1-134142.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.int"
attribute \generator "nMigen"
module \int
- attribute \src "libresoc.v:135917.3-135923.6"
- wire width 5 $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596
- attribute \src "libresoc.v:135917.3-135923.6"
- wire width 64 $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597
- attribute \src "libresoc.v:135917.3-135923.6"
- wire width 64 $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598
- attribute \src "libresoc.v:135917.3-135923.6"
+ attribute \src "libresoc.v:134048.3-134054.6"
+ wire width 5 $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522
+ attribute \src "libresoc.v:134048.3-134054.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523
+ attribute \src "libresoc.v:134048.3-134054.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524
+ attribute \src "libresoc.v:134048.3-134054.6"
wire width 5 $0\_0_[4:0]
- attribute \src "libresoc.v:135917.3-135923.6"
+ attribute \src "libresoc.v:134048.3-134054.6"
wire width 5 $0\_1_[4:0]
- attribute \src "libresoc.v:135917.3-135923.6"
+ attribute \src "libresoc.v:134048.3-134054.6"
wire width 5 $0\_2_[4:0]
- attribute \src "libresoc.v:135917.3-135923.6"
+ attribute \src "libresoc.v:134048.3-134054.6"
wire width 5 $0\_3_[4:0]
- attribute \src "libresoc.v:135946.3-135955.6"
+ attribute \src "libresoc.v:134077.3-134086.6"
wire width 64 $0\dmi__data_o[63:0]
- attribute \src "libresoc.v:135793.7-135793.20"
+ attribute \src "libresoc.v:133924.7-133924.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:135937.3-135945.6"
- wire $0\ren_delay$10$next[0:0]$5607
- attribute \src "libresoc.v:135870.3-135871.43"
- wire $0\ren_delay$10[0:0]$5589
- attribute \src "libresoc.v:135836.7-135836.28"
- wire $0\ren_delay$10[0:0]$5655
- attribute \src "libresoc.v:135966.3-135974.6"
- wire $0\ren_delay$8$next[0:0]$5612
- attribute \src "libresoc.v:135874.3-135875.41"
- wire $0\ren_delay$8[0:0]$5593
- attribute \src "libresoc.v:135840.7-135840.27"
- wire $0\ren_delay$8[0:0]$5657
- attribute \src "libresoc.v:135985.3-135993.6"
- wire $0\ren_delay$9$next[0:0]$5616
- attribute \src "libresoc.v:135872.3-135873.41"
- wire $0\ren_delay$9[0:0]$5591
- attribute \src "libresoc.v:135844.7-135844.27"
- wire $0\ren_delay$9[0:0]$5659
- attribute \src "libresoc.v:135928.3-135936.6"
- wire $0\ren_delay$next[0:0]$5604
- attribute \src "libresoc.v:135876.3-135877.35"
+ attribute \src "libresoc.v:134068.3-134076.6"
+ wire $0\ren_delay$10$next[0:0]$5533
+ attribute \src "libresoc.v:134001.3-134002.43"
+ wire $0\ren_delay$10[0:0]$5515
+ attribute \src "libresoc.v:133967.7-133967.28"
+ wire $0\ren_delay$10[0:0]$5581
+ attribute \src "libresoc.v:134097.3-134105.6"
+ wire $0\ren_delay$8$next[0:0]$5538
+ attribute \src "libresoc.v:134005.3-134006.41"
+ wire $0\ren_delay$8[0:0]$5519
+ attribute \src "libresoc.v:133971.7-133971.27"
+ wire $0\ren_delay$8[0:0]$5583
+ attribute \src "libresoc.v:134116.3-134124.6"
+ wire $0\ren_delay$9$next[0:0]$5542
+ attribute \src "libresoc.v:134003.3-134004.41"
+ wire $0\ren_delay$9[0:0]$5517
+ attribute \src "libresoc.v:133975.7-133975.27"
+ wire $0\ren_delay$9[0:0]$5585
+ attribute \src "libresoc.v:134059.3-134067.6"
+ wire $0\ren_delay$next[0:0]$5530
+ attribute \src "libresoc.v:134007.3-134008.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:135956.3-135965.6"
+ attribute \src "libresoc.v:134087.3-134096.6"
wire width 64 $0\src1__data_o[63:0]
- attribute \src "libresoc.v:135975.3-135984.6"
+ attribute \src "libresoc.v:134106.3-134115.6"
wire width 64 $0\src2__data_o[63:0]
- attribute \src "libresoc.v:135994.3-136003.6"
+ attribute \src "libresoc.v:134125.3-134134.6"
wire width 64 $0\src3__data_o[63:0]
- attribute \src "libresoc.v:135946.3-135955.6"
+ attribute \src "libresoc.v:134077.3-134086.6"
wire width 64 $1\dmi__data_o[63:0]
- attribute \src "libresoc.v:135937.3-135945.6"
- wire $1\ren_delay$10$next[0:0]$5608
- attribute \src "libresoc.v:135966.3-135974.6"
- wire $1\ren_delay$8$next[0:0]$5613
- attribute \src "libresoc.v:135985.3-135993.6"
- wire $1\ren_delay$9$next[0:0]$5617
- attribute \src "libresoc.v:135928.3-135936.6"
- wire $1\ren_delay$next[0:0]$5605
- attribute \src "libresoc.v:135834.7-135834.23"
+ attribute \src "libresoc.v:134068.3-134076.6"
+ wire $1\ren_delay$10$next[0:0]$5534
+ attribute \src "libresoc.v:134097.3-134105.6"
+ wire $1\ren_delay$8$next[0:0]$5539
+ attribute \src "libresoc.v:134116.3-134124.6"
+ wire $1\ren_delay$9$next[0:0]$5543
+ attribute \src "libresoc.v:134059.3-134067.6"
+ wire $1\ren_delay$next[0:0]$5531
+ attribute \src "libresoc.v:133965.7-133965.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:135956.3-135965.6"
+ attribute \src "libresoc.v:134087.3-134096.6"
wire width 64 $1\src1__data_o[63:0]
- attribute \src "libresoc.v:135975.3-135984.6"
+ attribute \src "libresoc.v:134106.3-134115.6"
wire width 64 $1\src2__data_o[63:0]
- attribute \src "libresoc.v:135994.3-136003.6"
+ attribute \src "libresoc.v:134125.3-134134.6"
wire width 64 $1\src3__data_o[63:0]
- attribute \src "libresoc.v:135924.26-135924.32"
- wire width 64 $memrd$\memory$libresoc.v:135924$5599_DATA
- attribute \src "libresoc.v:135925.30-135925.36"
- wire width 64 $memrd$\memory$libresoc.v:135925$5600_DATA
- attribute \src "libresoc.v:135926.30-135926.36"
- wire width 64 $memrd$\memory$libresoc.v:135926$5601_DATA
- attribute \src "libresoc.v:135927.30-135927.36"
- wire width 64 $memrd$\memory$libresoc.v:135927$5602_DATA
+ attribute \src "libresoc.v:134055.26-134055.32"
+ wire width 64 $memrd$\memory$libresoc.v:134055$5525_DATA
+ attribute \src "libresoc.v:134056.30-134056.36"
+ wire width 64 $memrd$\memory$libresoc.v:134056$5526_DATA
+ attribute \src "libresoc.v:134057.30-134057.36"
+ wire width 64 $memrd$\memory$libresoc.v:134057$5527_DATA
+ attribute \src "libresoc.v:134058.30-134058.36"
+ wire width 64 $memrd$\memory$libresoc.v:134058$5528_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 5 $memwr$\memory$libresoc.v:135922$5587_ADDR
+ wire width 5 $memwr$\memory$libresoc.v:134053$5513_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:135922$5587_DATA
+ wire width 64 $memwr$\memory$libresoc.v:134053$5513_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:135922$5587_EN
- attribute \src "libresoc.v:135913.13-135913.16"
+ wire width 64 $memwr$\memory$libresoc.v:134053$5513_EN
+ attribute \src "libresoc.v:134044.13-134044.16"
wire width 5 \_0_
- attribute \src "libresoc.v:135914.13-135914.16"
+ attribute \src "libresoc.v:134045.13-134045.16"
wire width 5 \_1_
- attribute \src "libresoc.v:135915.13-135915.16"
+ attribute \src "libresoc.v:134046.13-134046.16"
wire width 5 \_2_
- attribute \src "libresoc.v:135916.13-135916.16"
+ attribute \src "libresoc.v:134047.13-134047.16"
wire width 5 \_3_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 17 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 5 input 15 \dest1__addr
wire width 64 output 4 \dmi__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 3 \dmi__ren
- attribute \src "libresoc.v:135793.7-135793.15"
+ attribute \src "libresoc.v:133924.7-133924.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 5 \memory_r_addr
wire width 64 output 11 \src3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 13 \src3__ren
- attribute \src "libresoc.v:135878.14-135878.20"
+ attribute \src "libresoc.v:134009.14-134009.20"
memory width 64 size 32 \memory
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5619
+ cell $meminit $meminit$\memory$libresoc.v:0$5545
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5619
+ parameter \PRIORITY 5545
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5620
+ cell $meminit $meminit$\memory$libresoc.v:0$5546
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5620
+ parameter \PRIORITY 5546
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5621
+ cell $meminit $meminit$\memory$libresoc.v:0$5547
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5621
+ parameter \PRIORITY 5547
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5622
+ cell $meminit $meminit$\memory$libresoc.v:0$5548
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5622
+ parameter \PRIORITY 5548
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5623
+ cell $meminit $meminit$\memory$libresoc.v:0$5549
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5623
+ parameter \PRIORITY 5549
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5624
+ cell $meminit $meminit$\memory$libresoc.v:0$5550
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5624
+ parameter \PRIORITY 5550
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5625
+ cell $meminit $meminit$\memory$libresoc.v:0$5551
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5625
+ parameter \PRIORITY 5551
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5626
+ cell $meminit $meminit$\memory$libresoc.v:0$5552
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5626
+ parameter \PRIORITY 5552
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5627
+ cell $meminit $meminit$\memory$libresoc.v:0$5553
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5627
+ parameter \PRIORITY 5553
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 8
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5628
+ cell $meminit $meminit$\memory$libresoc.v:0$5554
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5628
+ parameter \PRIORITY 5554
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 9
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5629
+ cell $meminit $meminit$\memory$libresoc.v:0$5555
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5629
+ parameter \PRIORITY 5555
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 10
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5630
+ cell $meminit $meminit$\memory$libresoc.v:0$5556
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5630
+ parameter \PRIORITY 5556
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 11
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5631
+ cell $meminit $meminit$\memory$libresoc.v:0$5557
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5631
+ parameter \PRIORITY 5557
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 12
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5632
+ cell $meminit $meminit$\memory$libresoc.v:0$5558
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5632
+ parameter \PRIORITY 5558
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 13
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5633
+ cell $meminit $meminit$\memory$libresoc.v:0$5559
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5633
+ parameter \PRIORITY 5559
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 14
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5634
+ cell $meminit $meminit$\memory$libresoc.v:0$5560
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5634
+ parameter \PRIORITY 5560
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 15
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5635
+ cell $meminit $meminit$\memory$libresoc.v:0$5561
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5635
+ parameter \PRIORITY 5561
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 16
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5636
+ cell $meminit $meminit$\memory$libresoc.v:0$5562
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5636
+ parameter \PRIORITY 5562
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 17
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5637
+ cell $meminit $meminit$\memory$libresoc.v:0$5563
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5637
+ parameter \PRIORITY 5563
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 18
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5638
+ cell $meminit $meminit$\memory$libresoc.v:0$5564
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5638
+ parameter \PRIORITY 5564
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 19
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5639
+ cell $meminit $meminit$\memory$libresoc.v:0$5565
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5639
+ parameter \PRIORITY 5565
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 20
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5640
+ cell $meminit $meminit$\memory$libresoc.v:0$5566
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5640
+ parameter \PRIORITY 5566
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 21
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5641
+ cell $meminit $meminit$\memory$libresoc.v:0$5567
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5641
+ parameter \PRIORITY 5567
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 22
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5642
+ cell $meminit $meminit$\memory$libresoc.v:0$5568
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5642
+ parameter \PRIORITY 5568
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 23
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5643
+ cell $meminit $meminit$\memory$libresoc.v:0$5569
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5643
+ parameter \PRIORITY 5569
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 24
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5644
+ cell $meminit $meminit$\memory$libresoc.v:0$5570
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5644
+ parameter \PRIORITY 5570
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 25
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5645
+ cell $meminit $meminit$\memory$libresoc.v:0$5571
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5645
+ parameter \PRIORITY 5571
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 26
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5646
+ cell $meminit $meminit$\memory$libresoc.v:0$5572
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5646
+ parameter \PRIORITY 5572
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 27
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5647
+ cell $meminit $meminit$\memory$libresoc.v:0$5573
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5647
+ parameter \PRIORITY 5573
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 28
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5648
+ cell $meminit $meminit$\memory$libresoc.v:0$5574
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5648
+ parameter \PRIORITY 5574
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 29
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5649
+ cell $meminit $meminit$\memory$libresoc.v:0$5575
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5649
+ parameter \PRIORITY 5575
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 30
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$5650
+ cell $meminit $meminit$\memory$libresoc.v:0$5576
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 5650
+ parameter \PRIORITY 5576
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 31
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:135924.26-135924.32"
- cell $memrd $memrd$\memory$libresoc.v:135924$5599
+ attribute \src "libresoc.v:134055.26-134055.32"
+ cell $memrd $memrd$\memory$libresoc.v:134055$5525
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:135924$5599_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134055$5525_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:135925.30-135925.36"
- cell $memrd $memrd$\memory$libresoc.v:135925$5600
+ attribute \src "libresoc.v:134056.30-134056.36"
+ cell $memrd $memrd$\memory$libresoc.v:134056$5526
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_1_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:135925$5600_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134056$5526_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:135926.30-135926.36"
- cell $memrd $memrd$\memory$libresoc.v:135926$5601
+ attribute \src "libresoc.v:134057.30-134057.36"
+ cell $memrd $memrd$\memory$libresoc.v:134057$5527
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_2_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:135926$5601_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134057$5527_DATA
connect \EN 1'x
end
- attribute \src "libresoc.v:135927.30-135927.36"
- cell $memrd $memrd$\memory$libresoc.v:135927$5602
+ attribute \src "libresoc.v:134058.30-134058.36"
+ cell $memrd $memrd$\memory$libresoc.v:134058$5528
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_3_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:135927$5602_DATA
+ connect \DATA $memrd$\memory$libresoc.v:134058$5528_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- cell $memwr $memwr$\memory$libresoc.v:0$5651
+ cell $memwr $memwr$\memory$libresoc.v:0$5577
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\memory"
- parameter \PRIORITY 5651
+ parameter \PRIORITY 5577
parameter \WIDTH 64
- connect \ADDR $memwr$\memory$libresoc.v:135922$5587_ADDR
+ connect \ADDR $memwr$\memory$libresoc.v:134053$5513_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\memory$libresoc.v:135922$5587_DATA
- connect \EN $memwr$\memory$libresoc.v:135922$5587_EN
+ connect \DATA $memwr$\memory$libresoc.v:134053$5513_DATA
+ connect \EN $memwr$\memory$libresoc.v:134053$5513_EN
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$5660
+ process $proc$libresoc.v:0$5586
sync always
sync init
end
- attribute \src "libresoc.v:135793.7-135793.20"
- process $proc$libresoc.v:135793$5652
+ attribute \src "libresoc.v:133924.7-133924.20"
+ process $proc$libresoc.v:133924$5578
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:135834.7-135834.23"
- process $proc$libresoc.v:135834$5653
+ attribute \src "libresoc.v:133965.7-133965.23"
+ process $proc$libresoc.v:133965$5579
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:135836.7-135836.28"
- process $proc$libresoc.v:135836$5654
+ attribute \src "libresoc.v:133967.7-133967.28"
+ process $proc$libresoc.v:133967$5580
assign { } { }
- assign $0\ren_delay$10[0:0]$5655 1'0
+ assign $0\ren_delay$10[0:0]$5581 1'0
sync always
sync init
- update \ren_delay$10 $0\ren_delay$10[0:0]$5655
+ update \ren_delay$10 $0\ren_delay$10[0:0]$5581
end
- attribute \src "libresoc.v:135840.7-135840.27"
- process $proc$libresoc.v:135840$5656
+ attribute \src "libresoc.v:133971.7-133971.27"
+ process $proc$libresoc.v:133971$5582
assign { } { }
- assign $0\ren_delay$8[0:0]$5657 1'0
+ assign $0\ren_delay$8[0:0]$5583 1'0
sync always
sync init
- update \ren_delay$8 $0\ren_delay$8[0:0]$5657
+ update \ren_delay$8 $0\ren_delay$8[0:0]$5583
end
- attribute \src "libresoc.v:135844.7-135844.27"
- process $proc$libresoc.v:135844$5658
+ attribute \src "libresoc.v:133975.7-133975.27"
+ process $proc$libresoc.v:133975$5584
assign { } { }
- assign $0\ren_delay$9[0:0]$5659 1'0
+ assign $0\ren_delay$9[0:0]$5585 1'0
sync always
sync init
- update \ren_delay$9 $0\ren_delay$9[0:0]$5659
+ update \ren_delay$9 $0\ren_delay$9[0:0]$5585
end
- attribute \src "libresoc.v:135870.3-135871.43"
- process $proc$libresoc.v:135870$5588
+ attribute \src "libresoc.v:134001.3-134002.43"
+ process $proc$libresoc.v:134001$5514
assign { } { }
- assign $0\ren_delay$10[0:0]$5589 \ren_delay$10$next
+ assign $0\ren_delay$10[0:0]$5515 \ren_delay$10$next
sync posedge \coresync_clk
- update \ren_delay$10 $0\ren_delay$10[0:0]$5589
+ update \ren_delay$10 $0\ren_delay$10[0:0]$5515
end
- attribute \src "libresoc.v:135872.3-135873.41"
- process $proc$libresoc.v:135872$5590
+ attribute \src "libresoc.v:134003.3-134004.41"
+ process $proc$libresoc.v:134003$5516
assign { } { }
- assign $0\ren_delay$9[0:0]$5591 \ren_delay$9$next
+ assign $0\ren_delay$9[0:0]$5517 \ren_delay$9$next
sync posedge \coresync_clk
- update \ren_delay$9 $0\ren_delay$9[0:0]$5591
+ update \ren_delay$9 $0\ren_delay$9[0:0]$5517
end
- attribute \src "libresoc.v:135874.3-135875.41"
- process $proc$libresoc.v:135874$5592
+ attribute \src "libresoc.v:134005.3-134006.41"
+ process $proc$libresoc.v:134005$5518
assign { } { }
- assign $0\ren_delay$8[0:0]$5593 \ren_delay$8$next
+ assign $0\ren_delay$8[0:0]$5519 \ren_delay$8$next
sync posedge \coresync_clk
- update \ren_delay$8 $0\ren_delay$8[0:0]$5593
+ update \ren_delay$8 $0\ren_delay$8[0:0]$5519
end
- attribute \src "libresoc.v:135876.3-135877.35"
- process $proc$libresoc.v:135876$5594
+ attribute \src "libresoc.v:134007.3-134008.35"
+ process $proc$libresoc.v:134007$5520
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:135917.3-135923.6"
- process $proc$libresoc.v:135917$5595
+ attribute \src "libresoc.v:134048.3-134054.6"
+ process $proc$libresoc.v:134048$5521
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 5'xxxxx
- assign $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 5'xxxxx
+ assign $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 64'0000000000000000000000000000000000000000000000000000000000000000
assign $0\_0_[4:0] \src1__addr
assign $0\_1_[4:0] \src2__addr
assign $0\_2_[4:0] \src3__addr
assign $0\_3_[4:0] \dmi__addr
- attribute \src "libresoc.v:135922.5-135922.58"
+ attribute \src "libresoc.v:134053.5-134053.58"
switch \dest1__wen
- attribute \src "libresoc.v:135922.9-135922.19"
+ attribute \src "libresoc.v:134053.9-134053.19"
case 1'1
- assign $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 \dest1__addr
- assign $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 \dest1__data_i
- assign $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 \dest1__addr
+ assign $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 \dest1__data_i
+ assign $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 64'1111111111111111111111111111111111111111111111111111111111111111
case
end
sync posedge \coresync_clk
update \_1_ $0\_1_[4:0]
update \_2_ $0\_2_[4:0]
update \_3_ $0\_3_[4:0]
- update $memwr$\memory$libresoc.v:135922$5587_ADDR $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596
- update $memwr$\memory$libresoc.v:135922$5587_DATA $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597
- update $memwr$\memory$libresoc.v:135922$5587_EN $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598
+ update $memwr$\memory$libresoc.v:134053$5513_ADDR $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522
+ update $memwr$\memory$libresoc.v:134053$5513_DATA $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523
+ update $memwr$\memory$libresoc.v:134053$5513_EN $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524
end
- attribute \src "libresoc.v:135928.3-135936.6"
- process $proc$libresoc.v:135928$5603
+ attribute \src "libresoc.v:134059.3-134067.6"
+ process $proc$libresoc.v:134059$5529
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$5604 $1\ren_delay$next[0:0]$5605
- attribute \src "libresoc.v:135929.5-135929.29"
+ assign $0\ren_delay$next[0:0]$5530 $1\ren_delay$next[0:0]$5531
+ attribute \src "libresoc.v:134060.5-134060.29"
switch \initial
- attribute \src "libresoc.v:135929.9-135929.17"
+ attribute \src "libresoc.v:134060.9-134060.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$5605 1'0
+ assign $1\ren_delay$next[0:0]$5531 1'0
case
- assign $1\ren_delay$next[0:0]$5605 \src1__ren
+ assign $1\ren_delay$next[0:0]$5531 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$5604
+ update \ren_delay$next $0\ren_delay$next[0:0]$5530
end
- attribute \src "libresoc.v:135937.3-135945.6"
- process $proc$libresoc.v:135937$5606
+ attribute \src "libresoc.v:134068.3-134076.6"
+ process $proc$libresoc.v:134068$5532
assign { } { }
assign { } { }
- assign $0\ren_delay$10$next[0:0]$5607 $1\ren_delay$10$next[0:0]$5608
- attribute \src "libresoc.v:135938.5-135938.29"
+ assign $0\ren_delay$10$next[0:0]$5533 $1\ren_delay$10$next[0:0]$5534
+ attribute \src "libresoc.v:134069.5-134069.29"
switch \initial
- attribute \src "libresoc.v:135938.9-135938.17"
+ attribute \src "libresoc.v:134069.9-134069.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$10$next[0:0]$5608 1'0
+ assign $1\ren_delay$10$next[0:0]$5534 1'0
case
- assign $1\ren_delay$10$next[0:0]$5608 \dmi__ren
+ assign $1\ren_delay$10$next[0:0]$5534 \dmi__ren
end
sync always
- update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5607
+ update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5533
end
- attribute \src "libresoc.v:135946.3-135955.6"
- process $proc$libresoc.v:135946$5609
+ attribute \src "libresoc.v:134077.3-134086.6"
+ process $proc$libresoc.v:134077$5535
assign { } { }
assign { } { }
assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0]
- attribute \src "libresoc.v:135947.5-135947.29"
+ attribute \src "libresoc.v:134078.5-134078.29"
switch \initial
- attribute \src "libresoc.v:135947.9-135947.17"
+ attribute \src "libresoc.v:134078.9-134078.17"
case 1'1
case
end
sync always
update \dmi__data_o $0\dmi__data_o[63:0]
end
- attribute \src "libresoc.v:135956.3-135965.6"
- process $proc$libresoc.v:135956$5610
+ attribute \src "libresoc.v:134087.3-134096.6"
+ process $proc$libresoc.v:134087$5536
assign { } { }
assign { } { }
assign $0\src1__data_o[63:0] $1\src1__data_o[63:0]
- attribute \src "libresoc.v:135957.5-135957.29"
+ attribute \src "libresoc.v:134088.5-134088.29"
switch \initial
- attribute \src "libresoc.v:135957.9-135957.17"
+ attribute \src "libresoc.v:134088.9-134088.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[63:0]
end
- attribute \src "libresoc.v:135966.3-135974.6"
- process $proc$libresoc.v:135966$5611
+ attribute \src "libresoc.v:134097.3-134105.6"
+ process $proc$libresoc.v:134097$5537
assign { } { }
assign { } { }
- assign $0\ren_delay$8$next[0:0]$5612 $1\ren_delay$8$next[0:0]$5613
- attribute \src "libresoc.v:135967.5-135967.29"
+ assign $0\ren_delay$8$next[0:0]$5538 $1\ren_delay$8$next[0:0]$5539
+ attribute \src "libresoc.v:134098.5-134098.29"
switch \initial
- attribute \src "libresoc.v:135967.9-135967.17"
+ attribute \src "libresoc.v:134098.9-134098.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$8$next[0:0]$5613 1'0
+ assign $1\ren_delay$8$next[0:0]$5539 1'0
case
- assign $1\ren_delay$8$next[0:0]$5613 \src2__ren
+ assign $1\ren_delay$8$next[0:0]$5539 \src2__ren
end
sync always
- update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5612
+ update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5538
end
- attribute \src "libresoc.v:135975.3-135984.6"
- process $proc$libresoc.v:135975$5614
+ attribute \src "libresoc.v:134106.3-134115.6"
+ process $proc$libresoc.v:134106$5540
assign { } { }
assign { } { }
assign $0\src2__data_o[63:0] $1\src2__data_o[63:0]
- attribute \src "libresoc.v:135976.5-135976.29"
+ attribute \src "libresoc.v:134107.5-134107.29"
switch \initial
- attribute \src "libresoc.v:135976.9-135976.17"
+ attribute \src "libresoc.v:134107.9-134107.17"
case 1'1
case
end
sync always
update \src2__data_o $0\src2__data_o[63:0]
end
- attribute \src "libresoc.v:135985.3-135993.6"
- process $proc$libresoc.v:135985$5615
+ attribute \src "libresoc.v:134116.3-134124.6"
+ process $proc$libresoc.v:134116$5541
assign { } { }
assign { } { }
- assign $0\ren_delay$9$next[0:0]$5616 $1\ren_delay$9$next[0:0]$5617
- attribute \src "libresoc.v:135986.5-135986.29"
+ assign $0\ren_delay$9$next[0:0]$5542 $1\ren_delay$9$next[0:0]$5543
+ attribute \src "libresoc.v:134117.5-134117.29"
switch \initial
- attribute \src "libresoc.v:135986.9-135986.17"
+ attribute \src "libresoc.v:134117.9-134117.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$9$next[0:0]$5617 1'0
+ assign $1\ren_delay$9$next[0:0]$5543 1'0
case
- assign $1\ren_delay$9$next[0:0]$5617 \src3__ren
+ assign $1\ren_delay$9$next[0:0]$5543 \src3__ren
end
sync always
- update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5616
+ update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5542
end
- attribute \src "libresoc.v:135994.3-136003.6"
- process $proc$libresoc.v:135994$5618
+ attribute \src "libresoc.v:134125.3-134134.6"
+ process $proc$libresoc.v:134125$5544
assign { } { }
assign { } { }
assign $0\src3__data_o[63:0] $1\src3__data_o[63:0]
- attribute \src "libresoc.v:135995.5-135995.29"
+ attribute \src "libresoc.v:134126.5-134126.29"
switch \initial
- attribute \src "libresoc.v:135995.9-135995.17"
+ attribute \src "libresoc.v:134126.9-134126.17"
case 1'1
case
end
sync always
update \src3__data_o $0\src3__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:135924$5599_DATA
- connect \memory_r_data$3 $memrd$\memory$libresoc.v:135925$5600_DATA
- connect \memory_r_data$5 $memrd$\memory$libresoc.v:135926$5601_DATA
- connect \memory_r_data$7 $memrd$\memory$libresoc.v:135927$5602_DATA
+ connect \memory_r_data $memrd$\memory$libresoc.v:134055$5525_DATA
+ connect \memory_r_data$3 $memrd$\memory$libresoc.v:134056$5526_DATA
+ connect \memory_r_data$5 $memrd$\memory$libresoc.v:134057$5527_DATA
+ connect \memory_r_data$7 $memrd$\memory$libresoc.v:134058$5528_DATA
connect \memory_w_data \dest1__data_i
connect \memory_w_en \dest1__wen
connect \memory_w_addr \dest1__addr
connect \memory_r_addr$2 \src2__addr
connect \memory_r_addr \src1__addr
end
-attribute \src "libresoc.v:136015.1-138738.10"
+attribute \src "libresoc.v:134146.1-136868.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.jtag"
attribute \generator "nMigen"
module \jtag
- attribute \src "libresoc.v:138168.3-138194.6"
+ attribute \src "libresoc.v:136298.3-136324.6"
wire $0\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:137816.3-137831.6"
+ attribute \src "libresoc.v:135946.3-135961.6"
wire $0\TAP_tdo[0:0]
- attribute \src "libresoc.v:138329.3-138361.6"
- wire width 4 $0\dmi0__addr_i$next[3:0]$6072
- attribute \src "libresoc.v:137719.3-137720.41"
+ attribute \src "libresoc.v:136459.3-136491.6"
+ wire width 4 $0\dmi0__addr_i$next[3:0]$5998
+ attribute \src "libresoc.v:135849.3-135850.41"
wire width 4 $0\dmi0__addr_i[3:0]
- attribute \src "libresoc.v:138415.3-138441.6"
- wire width 64 $0\dmi0__din$next[63:0]$6085
- attribute \src "libresoc.v:137715.3-137716.35"
+ attribute \src "libresoc.v:136545.3-136571.6"
+ wire width 64 $0\dmi0__din$next[63:0]$6011
+ attribute \src "libresoc.v:135845.3-135846.35"
wire width 64 $0\dmi0__din[63:0]
- attribute \src "libresoc.v:138018.3-138034.6"
- wire $0\dmi0_addrsr__oe$next[0:0]$6009
- attribute \src "libresoc.v:137747.3-137748.47"
+ attribute \src "libresoc.v:136148.3-136164.6"
+ wire $0\dmi0_addrsr__oe$next[0:0]$5935
+ attribute \src "libresoc.v:135877.3-135878.47"
wire $0\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:138035.3-138055.6"
- wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6013
- attribute \src "libresoc.v:137745.3-137746.47"
+ attribute \src "libresoc.v:136165.3-136185.6"
+ wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5939
+ attribute \src "libresoc.v:135875.3-135876.47"
wire width 8 $0\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:138000.3-138008.6"
- wire $0\dmi0_addrsr_update_core$next[0:0]$6003
- attribute \src "libresoc.v:137751.3-137752.63"
+ attribute \src "libresoc.v:136130.3-136138.6"
+ wire $0\dmi0_addrsr_update_core$next[0:0]$5929
+ attribute \src "libresoc.v:135881.3-135882.63"
wire $0\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:138009.3-138017.6"
- wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6006
- attribute \src "libresoc.v:137749.3-137750.73"
+ attribute \src "libresoc.v:136139.3-136147.6"
+ wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5932
+ attribute \src "libresoc.v:135879.3-135880.73"
wire $0\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:138442.3-138462.6"
- wire width 64 $0\dmi0_datasr__i$next[63:0]$6090
- attribute \src "libresoc.v:137713.3-137714.45"
+ attribute \src "libresoc.v:136572.3-136592.6"
+ wire width 64 $0\dmi0_datasr__i$next[63:0]$6016
+ attribute \src "libresoc.v:135843.3-135844.45"
wire width 64 $0\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:138074.3-138090.6"
- wire width 2 $0\dmi0_datasr__oe$next[1:0]$6024
- attribute \src "libresoc.v:137739.3-137740.47"
+ attribute \src "libresoc.v:136204.3-136220.6"
+ wire width 2 $0\dmi0_datasr__oe$next[1:0]$5950
+ attribute \src "libresoc.v:135869.3-135870.47"
wire width 2 $0\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:138091.3-138111.6"
- wire width 64 $0\dmi0_datasr_reg$next[63:0]$6028
- attribute \src "libresoc.v:137737.3-137738.47"
+ attribute \src "libresoc.v:136221.3-136241.6"
+ wire width 64 $0\dmi0_datasr_reg$next[63:0]$5954
+ attribute \src "libresoc.v:135867.3-135868.47"
wire width 64 $0\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:138056.3-138064.6"
- wire $0\dmi0_datasr_update_core$next[0:0]$6018
- attribute \src "libresoc.v:137743.3-137744.63"
+ attribute \src "libresoc.v:136186.3-136194.6"
+ wire $0\dmi0_datasr_update_core$next[0:0]$5944
+ attribute \src "libresoc.v:135873.3-135874.63"
wire $0\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:138065.3-138073.6"
- wire $0\dmi0_datasr_update_core_prev$next[0:0]$6021
- attribute \src "libresoc.v:137741.3-137742.73"
+ attribute \src "libresoc.v:136195.3-136203.6"
+ wire $0\dmi0_datasr_update_core_prev$next[0:0]$5947
+ attribute \src "libresoc.v:135871.3-135872.73"
wire $0\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $0\fsm_state$503$next[2:0]$6078
- attribute \src "libresoc.v:137717.3-137718.45"
- wire width 3 $0\fsm_state$503[2:0]$5924
- attribute \src "libresoc.v:136661.13-136661.35"
- wire width 3 $0\fsm_state$503[2:0]$6127
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $0\fsm_state$next[2:0]$6055
- attribute \src "libresoc.v:137725.3-137726.35"
+ attribute \src "libresoc.v:136492.3-136544.6"
+ wire width 3 $0\fsm_state$503$next[2:0]$6004
+ attribute \src "libresoc.v:135847.3-135848.45"
+ wire width 3 $0\fsm_state$503[2:0]$5850
+ attribute \src "libresoc.v:134792.13-134792.35"
+ wire width 3 $0\fsm_state$503[2:0]$6053
+ attribute \src "libresoc.v:136358.3-136410.6"
+ wire width 3 $0\fsm_state$next[2:0]$5981
+ attribute \src "libresoc.v:135855.3-135856.35"
wire width 3 $0\fsm_state[2:0]
- attribute \src "libresoc.v:136016.7-136016.20"
+ attribute \src "libresoc.v:134147.7-134147.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:138512.3-138532.6"
- wire width 154 $0\io_bd$next[153:0]$6110
- attribute \src "libresoc.v:137777.3-137778.27"
+ attribute \src "libresoc.v:136642.3-136662.6"
+ wire width 154 $0\io_bd$next[153:0]$6036
+ attribute \src "libresoc.v:135907.3-135908.27"
wire width 154 $0\io_bd[153:0]
- attribute \src "libresoc.v:138494.3-138511.6"
- wire width 154 $0\io_sr$next[153:0]$6106
- attribute \src "libresoc.v:137779.3-137780.27"
+ attribute \src "libresoc.v:136624.3-136641.6"
+ wire width 154 $0\io_sr$next[153:0]$6032
+ attribute \src "libresoc.v:135909.3-135910.27"
wire width 154 $0\io_sr[153:0]
- attribute \src "libresoc.v:138195.3-138227.6"
- wire width 29 $0\jtag_wb__adr$next[28:0]$6049
- attribute \src "libresoc.v:137727.3-137728.41"
+ attribute \src "libresoc.v:136325.3-136357.6"
+ wire width 29 $0\jtag_wb__adr$next[28:0]$5975
+ attribute \src "libresoc.v:135857.3-135858.41"
wire width 29 $0\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:138281.3-138307.6"
- wire width 64 $0\jtag_wb__dat_w$next[63:0]$6062
- attribute \src "libresoc.v:137723.3-137724.45"
+ attribute \src "libresoc.v:136411.3-136437.6"
+ wire width 64 $0\jtag_wb__dat_w$next[63:0]$5988
+ attribute \src "libresoc.v:135853.3-135854.45"
wire width 64 $0\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:137906.3-137922.6"
- wire $0\jtag_wb_addrsr__oe$next[0:0]$5979
- attribute \src "libresoc.v:137763.3-137764.53"
+ attribute \src "libresoc.v:136036.3-136052.6"
+ wire $0\jtag_wb_addrsr__oe$next[0:0]$5905
+ attribute \src "libresoc.v:135893.3-135894.53"
wire $0\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:137923.3-137943.6"
- wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5983
- attribute \src "libresoc.v:137761.3-137762.53"
+ attribute \src "libresoc.v:136053.3-136073.6"
+ wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5909
+ attribute \src "libresoc.v:135891.3-135892.53"
wire width 29 $0\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:137888.3-137896.6"
- wire $0\jtag_wb_addrsr_update_core$next[0:0]$5973
- attribute \src "libresoc.v:137767.3-137768.69"
+ attribute \src "libresoc.v:136018.3-136026.6"
+ wire $0\jtag_wb_addrsr_update_core$next[0:0]$5899
+ attribute \src "libresoc.v:135897.3-135898.69"
wire $0\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:137897.3-137905.6"
- wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976
- attribute \src "libresoc.v:137765.3-137766.79"
+ attribute \src "libresoc.v:136027.3-136035.6"
+ wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902
+ attribute \src "libresoc.v:135895.3-135896.79"
wire $0\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:138308.3-138328.6"
- wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6067
- attribute \src "libresoc.v:137721.3-137722.51"
+ attribute \src "libresoc.v:136438.3-136458.6"
+ wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5993
+ attribute \src "libresoc.v:135851.3-135852.51"
wire width 64 $0\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:137962.3-137978.6"
- wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5994
- attribute \src "libresoc.v:137755.3-137756.53"
+ attribute \src "libresoc.v:136092.3-136108.6"
+ wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5920
+ attribute \src "libresoc.v:135885.3-135886.53"
wire width 2 $0\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:137979.3-137999.6"
- wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5998
- attribute \src "libresoc.v:137753.3-137754.53"
+ attribute \src "libresoc.v:136109.3-136129.6"
+ wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5924
+ attribute \src "libresoc.v:135883.3-135884.53"
wire width 64 $0\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:137944.3-137952.6"
- wire $0\jtag_wb_datasr_update_core$next[0:0]$5988
- attribute \src "libresoc.v:137759.3-137760.69"
+ attribute \src "libresoc.v:136074.3-136082.6"
+ wire $0\jtag_wb_datasr_update_core$next[0:0]$5914
+ attribute \src "libresoc.v:135889.3-135890.69"
wire $0\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:137953.3-137961.6"
- wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991
- attribute \src "libresoc.v:137757.3-137758.79"
+ attribute \src "libresoc.v:136083.3-136091.6"
+ wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917
+ attribute \src "libresoc.v:135887.3-135888.79"
wire $0\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:137850.3-137866.6"
- wire $0\sr0__oe$next[0:0]$5964
- attribute \src "libresoc.v:137771.3-137772.31"
+ attribute \src "libresoc.v:135980.3-135996.6"
+ wire $0\sr0__oe$next[0:0]$5890
+ attribute \src "libresoc.v:135901.3-135902.31"
wire $0\sr0__oe[0:0]
- attribute \src "libresoc.v:137867.3-137887.6"
- wire width 3 $0\sr0_reg$next[2:0]$5968
- attribute \src "libresoc.v:137769.3-137770.31"
+ attribute \src "libresoc.v:135997.3-136017.6"
+ wire width 3 $0\sr0_reg$next[2:0]$5894
+ attribute \src "libresoc.v:135899.3-135900.31"
wire width 3 $0\sr0_reg[2:0]
- attribute \src "libresoc.v:137832.3-137840.6"
- wire $0\sr0_update_core$next[0:0]$5958
- attribute \src "libresoc.v:137775.3-137776.47"
+ attribute \src "libresoc.v:135962.3-135970.6"
+ wire $0\sr0_update_core$next[0:0]$5884
+ attribute \src "libresoc.v:135905.3-135906.47"
wire $0\sr0_update_core[0:0]
- attribute \src "libresoc.v:137841.3-137849.6"
- wire $0\sr0_update_core_prev$next[0:0]$5961
- attribute \src "libresoc.v:137773.3-137774.57"
+ attribute \src "libresoc.v:135971.3-135979.6"
+ wire $0\sr0_update_core_prev$next[0:0]$5887
+ attribute \src "libresoc.v:135903.3-135904.57"
wire $0\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:138484.3-138493.6"
+ attribute \src "libresoc.v:136614.3-136623.6"
wire width 3 $0\sr5__i[2:0]
- attribute \src "libresoc.v:138130.3-138146.6"
- wire $0\sr5__oe$next[0:0]$6039
- attribute \src "libresoc.v:137731.3-137732.31"
+ attribute \src "libresoc.v:136260.3-136276.6"
+ wire $0\sr5__oe$next[0:0]$5965
+ attribute \src "libresoc.v:135861.3-135862.31"
wire $0\sr5__oe[0:0]
- attribute \src "libresoc.v:138147.3-138167.6"
- wire width 3 $0\sr5_reg$next[2:0]$6043
- attribute \src "libresoc.v:137729.3-137730.31"
+ attribute \src "libresoc.v:136277.3-136297.6"
+ wire width 3 $0\sr5_reg$next[2:0]$5969
+ attribute \src "libresoc.v:135859.3-135860.31"
wire width 3 $0\sr5_reg[2:0]
- attribute \src "libresoc.v:138112.3-138120.6"
- wire $0\sr5_update_core$next[0:0]$6033
- attribute \src "libresoc.v:137735.3-137736.47"
+ attribute \src "libresoc.v:136242.3-136250.6"
+ wire $0\sr5_update_core$next[0:0]$5959
+ attribute \src "libresoc.v:135865.3-135866.47"
wire $0\sr5_update_core[0:0]
- attribute \src "libresoc.v:138121.3-138129.6"
- wire $0\sr5_update_core_prev$next[0:0]$6036
- attribute \src "libresoc.v:137733.3-137734.57"
+ attribute \src "libresoc.v:136251.3-136259.6"
+ wire $0\sr5_update_core_prev$next[0:0]$5962
+ attribute \src "libresoc.v:135863.3-135864.57"
wire $0\sr5_update_core_prev[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $0\wb_dcache_en$next[0:0]$6095
- attribute \src "libresoc.v:137709.3-137710.41"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $0\wb_dcache_en$next[0:0]$6021
+ attribute \src "libresoc.v:135839.3-135840.41"
wire $0\wb_dcache_en[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $0\wb_icache_en$next[0:0]$6096
- attribute \src "libresoc.v:137707.3-137708.41"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $0\wb_icache_en$next[0:0]$6022
+ attribute \src "libresoc.v:135837.3-135838.41"
wire $0\wb_icache_en[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $0\wb_sram_en$next[0:0]$6097
- attribute \src "libresoc.v:137711.3-137712.37"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $0\wb_sram_en$next[0:0]$6023
+ attribute \src "libresoc.v:135841.3-135842.37"
wire $0\wb_sram_en[0:0]
- attribute \src "libresoc.v:138168.3-138194.6"
+ attribute \src "libresoc.v:136298.3-136324.6"
wire $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:137816.3-137831.6"
+ attribute \src "libresoc.v:135946.3-135961.6"
wire $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:138329.3-138361.6"
- wire width 4 $1\dmi0__addr_i$next[3:0]$6073
- attribute \src "libresoc.v:136574.13-136574.32"
+ attribute \src "libresoc.v:136459.3-136491.6"
+ wire width 4 $1\dmi0__addr_i$next[3:0]$5999
+ attribute \src "libresoc.v:134705.13-134705.32"
wire width 4 $1\dmi0__addr_i[3:0]
- attribute \src "libresoc.v:138415.3-138441.6"
- wire width 64 $1\dmi0__din$next[63:0]$6086
- attribute \src "libresoc.v:136579.14-136579.46"
+ attribute \src "libresoc.v:136545.3-136571.6"
+ wire width 64 $1\dmi0__din$next[63:0]$6012
+ attribute \src "libresoc.v:134710.14-134710.46"
wire width 64 $1\dmi0__din[63:0]
- attribute \src "libresoc.v:138018.3-138034.6"
- wire $1\dmi0_addrsr__oe$next[0:0]$6010
- attribute \src "libresoc.v:136593.7-136593.29"
+ attribute \src "libresoc.v:136148.3-136164.6"
+ wire $1\dmi0_addrsr__oe$next[0:0]$5936
+ attribute \src "libresoc.v:134724.7-134724.29"
wire $1\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:138035.3-138055.6"
- wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6014
- attribute \src "libresoc.v:136601.13-136601.36"
+ attribute \src "libresoc.v:136165.3-136185.6"
+ wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5940
+ attribute \src "libresoc.v:134732.13-134732.36"
wire width 8 $1\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:138000.3-138008.6"
- wire $1\dmi0_addrsr_update_core$next[0:0]$6004
- attribute \src "libresoc.v:136609.7-136609.37"
+ attribute \src "libresoc.v:136130.3-136138.6"
+ wire $1\dmi0_addrsr_update_core$next[0:0]$5930
+ attribute \src "libresoc.v:134740.7-134740.37"
wire $1\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:138009.3-138017.6"
- wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6007
- attribute \src "libresoc.v:136613.7-136613.42"
+ attribute \src "libresoc.v:136139.3-136147.6"
+ wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5933
+ attribute \src "libresoc.v:134744.7-134744.42"
wire $1\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:138442.3-138462.6"
- wire width 64 $1\dmi0_datasr__i$next[63:0]$6091
- attribute \src "libresoc.v:136617.14-136617.51"
+ attribute \src "libresoc.v:136572.3-136592.6"
+ wire width 64 $1\dmi0_datasr__i$next[63:0]$6017
+ attribute \src "libresoc.v:134748.14-134748.51"
wire width 64 $1\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:138074.3-138090.6"
- wire width 2 $1\dmi0_datasr__oe$next[1:0]$6025
- attribute \src "libresoc.v:136623.13-136623.35"
+ attribute \src "libresoc.v:136204.3-136220.6"
+ wire width 2 $1\dmi0_datasr__oe$next[1:0]$5951
+ attribute \src "libresoc.v:134754.13-134754.35"
wire width 2 $1\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:138091.3-138111.6"
- wire width 64 $1\dmi0_datasr_reg$next[63:0]$6029
- attribute \src "libresoc.v:136631.14-136631.52"
+ attribute \src "libresoc.v:136221.3-136241.6"
+ wire width 64 $1\dmi0_datasr_reg$next[63:0]$5955
+ attribute \src "libresoc.v:134762.14-134762.52"
wire width 64 $1\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:138056.3-138064.6"
- wire $1\dmi0_datasr_update_core$next[0:0]$6019
- attribute \src "libresoc.v:136639.7-136639.37"
+ attribute \src "libresoc.v:136186.3-136194.6"
+ wire $1\dmi0_datasr_update_core$next[0:0]$5945
+ attribute \src "libresoc.v:134770.7-134770.37"
wire $1\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:138065.3-138073.6"
- wire $1\dmi0_datasr_update_core_prev$next[0:0]$6022
- attribute \src "libresoc.v:136643.7-136643.42"
+ attribute \src "libresoc.v:136195.3-136203.6"
+ wire $1\dmi0_datasr_update_core_prev$next[0:0]$5948
+ attribute \src "libresoc.v:134774.7-134774.42"
wire $1\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $1\fsm_state$503$next[2:0]$6079
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $1\fsm_state$next[2:0]$6056
- attribute \src "libresoc.v:136659.13-136659.29"
+ attribute \src "libresoc.v:136492.3-136544.6"
+ wire width 3 $1\fsm_state$503$next[2:0]$6005
+ attribute \src "libresoc.v:136358.3-136410.6"
+ wire width 3 $1\fsm_state$next[2:0]$5982
+ attribute \src "libresoc.v:134790.13-134790.29"
wire width 3 $1\fsm_state[2:0]
- attribute \src "libresoc.v:138512.3-138532.6"
- wire width 154 $1\io_bd$next[153:0]$6111
- attribute \src "libresoc.v:136859.15-136859.67"
+ attribute \src "libresoc.v:136642.3-136662.6"
+ wire width 154 $1\io_bd$next[153:0]$6037
+ attribute \src "libresoc.v:134990.15-134990.67"
wire width 154 $1\io_bd[153:0]
- attribute \src "libresoc.v:138494.3-138511.6"
- wire width 154 $1\io_sr$next[153:0]$6107
- attribute \src "libresoc.v:136871.15-136871.67"
+ attribute \src "libresoc.v:136624.3-136641.6"
+ wire width 154 $1\io_sr$next[153:0]$6033
+ attribute \src "libresoc.v:135002.15-135002.67"
wire width 154 $1\io_sr[153:0]
- attribute \src "libresoc.v:138195.3-138227.6"
- wire width 29 $1\jtag_wb__adr$next[28:0]$6050
- attribute \src "libresoc.v:136880.14-136880.41"
+ attribute \src "libresoc.v:136325.3-136357.6"
+ wire width 29 $1\jtag_wb__adr$next[28:0]$5976
+ attribute \src "libresoc.v:135011.14-135011.41"
wire width 29 $1\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:138281.3-138307.6"
- wire width 64 $1\jtag_wb__dat_w$next[63:0]$6063
- attribute \src "libresoc.v:136889.14-136889.51"
+ attribute \src "libresoc.v:136411.3-136437.6"
+ wire width 64 $1\jtag_wb__dat_w$next[63:0]$5989
+ attribute \src "libresoc.v:135020.14-135020.51"
wire width 64 $1\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:137906.3-137922.6"
- wire $1\jtag_wb_addrsr__oe$next[0:0]$5980
- attribute \src "libresoc.v:136903.7-136903.32"
+ attribute \src "libresoc.v:136036.3-136052.6"
+ wire $1\jtag_wb_addrsr__oe$next[0:0]$5906
+ attribute \src "libresoc.v:135034.7-135034.32"
wire $1\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:137923.3-137943.6"
- wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5984
- attribute \src "libresoc.v:136911.14-136911.47"
+ attribute \src "libresoc.v:136053.3-136073.6"
+ wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5910
+ attribute \src "libresoc.v:135042.14-135042.47"
wire width 29 $1\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:137888.3-137896.6"
- wire $1\jtag_wb_addrsr_update_core$next[0:0]$5974
- attribute \src "libresoc.v:136919.7-136919.40"
+ attribute \src "libresoc.v:136018.3-136026.6"
+ wire $1\jtag_wb_addrsr_update_core$next[0:0]$5900
+ attribute \src "libresoc.v:135050.7-135050.40"
wire $1\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:137897.3-137905.6"
- wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977
- attribute \src "libresoc.v:136923.7-136923.45"
+ attribute \src "libresoc.v:136027.3-136035.6"
+ wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903
+ attribute \src "libresoc.v:135054.7-135054.45"
wire $1\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:138308.3-138328.6"
- wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6068
- attribute \src "libresoc.v:136927.14-136927.54"
+ attribute \src "libresoc.v:136438.3-136458.6"
+ wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5994
+ attribute \src "libresoc.v:135058.14-135058.54"
wire width 64 $1\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:137962.3-137978.6"
- wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5995
- attribute \src "libresoc.v:136933.13-136933.38"
+ attribute \src "libresoc.v:136092.3-136108.6"
+ wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5921
+ attribute \src "libresoc.v:135064.13-135064.38"
wire width 2 $1\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:137979.3-137999.6"
- wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5999
- attribute \src "libresoc.v:136941.14-136941.55"
+ attribute \src "libresoc.v:136109.3-136129.6"
+ wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5925
+ attribute \src "libresoc.v:135072.14-135072.55"
wire width 64 $1\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:137944.3-137952.6"
- wire $1\jtag_wb_datasr_update_core$next[0:0]$5989
- attribute \src "libresoc.v:136949.7-136949.40"
+ attribute \src "libresoc.v:136074.3-136082.6"
+ wire $1\jtag_wb_datasr_update_core$next[0:0]$5915
+ attribute \src "libresoc.v:135080.7-135080.40"
wire $1\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:137953.3-137961.6"
- wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992
- attribute \src "libresoc.v:136953.7-136953.45"
+ attribute \src "libresoc.v:136083.3-136091.6"
+ wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918
+ attribute \src "libresoc.v:135084.7-135084.45"
wire $1\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:137850.3-137866.6"
- wire $1\sr0__oe$next[0:0]$5965
- attribute \src "libresoc.v:137383.7-137383.21"
+ attribute \src "libresoc.v:135980.3-135996.6"
+ wire $1\sr0__oe$next[0:0]$5891
+ attribute \src "libresoc.v:135514.7-135514.21"
wire $1\sr0__oe[0:0]
- attribute \src "libresoc.v:137867.3-137887.6"
- wire width 3 $1\sr0_reg$next[2:0]$5969
- attribute \src "libresoc.v:137391.13-137391.27"
+ attribute \src "libresoc.v:135997.3-136017.6"
+ wire width 3 $1\sr0_reg$next[2:0]$5895
+ attribute \src "libresoc.v:135522.13-135522.27"
wire width 3 $1\sr0_reg[2:0]
- attribute \src "libresoc.v:137832.3-137840.6"
- wire $1\sr0_update_core$next[0:0]$5959
- attribute \src "libresoc.v:137399.7-137399.29"
+ attribute \src "libresoc.v:135962.3-135970.6"
+ wire $1\sr0_update_core$next[0:0]$5885
+ attribute \src "libresoc.v:135530.7-135530.29"
wire $1\sr0_update_core[0:0]
- attribute \src "libresoc.v:137841.3-137849.6"
- wire $1\sr0_update_core_prev$next[0:0]$5962
- attribute \src "libresoc.v:137403.7-137403.34"
+ attribute \src "libresoc.v:135971.3-135979.6"
+ wire $1\sr0_update_core_prev$next[0:0]$5888
+ attribute \src "libresoc.v:135534.7-135534.34"
wire $1\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:138484.3-138493.6"
+ attribute \src "libresoc.v:136614.3-136623.6"
wire width 3 $1\sr5__i[2:0]
- attribute \src "libresoc.v:138130.3-138146.6"
- wire $1\sr5__oe$next[0:0]$6040
- attribute \src "libresoc.v:137413.7-137413.21"
+ attribute \src "libresoc.v:136260.3-136276.6"
+ wire $1\sr5__oe$next[0:0]$5966
+ attribute \src "libresoc.v:135544.7-135544.21"
wire $1\sr5__oe[0:0]
- attribute \src "libresoc.v:138147.3-138167.6"
- wire width 3 $1\sr5_reg$next[2:0]$6044
- attribute \src "libresoc.v:137421.13-137421.27"
+ attribute \src "libresoc.v:136277.3-136297.6"
+ wire width 3 $1\sr5_reg$next[2:0]$5970
+ attribute \src "libresoc.v:135552.13-135552.27"
wire width 3 $1\sr5_reg[2:0]
- attribute \src "libresoc.v:138112.3-138120.6"
- wire $1\sr5_update_core$next[0:0]$6034
- attribute \src "libresoc.v:137429.7-137429.29"
+ attribute \src "libresoc.v:136242.3-136250.6"
+ wire $1\sr5_update_core$next[0:0]$5960
+ attribute \src "libresoc.v:135560.7-135560.29"
wire $1\sr5_update_core[0:0]
- attribute \src "libresoc.v:138121.3-138129.6"
- wire $1\sr5_update_core_prev$next[0:0]$6037
- attribute \src "libresoc.v:137433.7-137433.34"
+ attribute \src "libresoc.v:136251.3-136259.6"
+ wire $1\sr5_update_core_prev$next[0:0]$5963
+ attribute \src "libresoc.v:135564.7-135564.34"
wire $1\sr5_update_core_prev[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $1\wb_dcache_en$next[0:0]$6098
- attribute \src "libresoc.v:137438.7-137438.26"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $1\wb_dcache_en$next[0:0]$6024
+ attribute \src "libresoc.v:135569.7-135569.26"
wire $1\wb_dcache_en[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $1\wb_icache_en$next[0:0]$6099
- attribute \src "libresoc.v:137443.7-137443.26"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $1\wb_icache_en$next[0:0]$6025
+ attribute \src "libresoc.v:135574.7-135574.26"
wire $1\wb_icache_en[0:0]
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $1\wb_sram_en$next[0:0]$6100
- attribute \src "libresoc.v:137448.7-137448.24"
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $1\wb_sram_en$next[0:0]$6026
+ attribute \src "libresoc.v:135578.7-135578.24"
wire $1\wb_sram_en[0:0]
- attribute \src "libresoc.v:138329.3-138361.6"
- wire width 4 $2\dmi0__addr_i$next[3:0]$6074
- attribute \src "libresoc.v:138415.3-138441.6"
- wire width 64 $2\dmi0__din$next[63:0]$6087
- attribute \src "libresoc.v:138018.3-138034.6"
- wire $2\dmi0_addrsr__oe$next[0:0]$6011
- attribute \src "libresoc.v:138035.3-138055.6"
- wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6015
- attribute \src "libresoc.v:138442.3-138462.6"
- wire width 64 $2\dmi0_datasr__i$next[63:0]$6092
- attribute \src "libresoc.v:138074.3-138090.6"
- wire width 2 $2\dmi0_datasr__oe$next[1:0]$6026
- attribute \src "libresoc.v:138091.3-138111.6"
- wire width 64 $2\dmi0_datasr_reg$next[63:0]$6030
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $2\fsm_state$503$next[2:0]$6080
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $2\fsm_state$next[2:0]$6057
- attribute \src "libresoc.v:138512.3-138532.6"
- wire width 154 $2\io_bd$next[153:0]$6112
- attribute \src "libresoc.v:138494.3-138511.6"
- wire width 154 $2\io_sr$next[153:0]$6108
- attribute \src "libresoc.v:138195.3-138227.6"
- wire width 29 $2\jtag_wb__adr$next[28:0]$6051
- attribute \src "libresoc.v:138281.3-138307.6"
- wire width 64 $2\jtag_wb__dat_w$next[63:0]$6064
- attribute \src "libresoc.v:137906.3-137922.6"
- wire $2\jtag_wb_addrsr__oe$next[0:0]$5981
- attribute \src "libresoc.v:137923.3-137943.6"
- wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5985
- attribute \src "libresoc.v:138308.3-138328.6"
- wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6069
- attribute \src "libresoc.v:137962.3-137978.6"
- wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5996
- attribute \src "libresoc.v:137979.3-137999.6"
- wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6000
- attribute \src "libresoc.v:137850.3-137866.6"
- wire $2\sr0__oe$next[0:0]$5966
- attribute \src "libresoc.v:137867.3-137887.6"
- wire width 3 $2\sr0_reg$next[2:0]$5970
- attribute \src "libresoc.v:138130.3-138146.6"
- wire $2\sr5__oe$next[0:0]$6041
- attribute \src "libresoc.v:138147.3-138167.6"
- wire width 3 $2\sr5_reg$next[2:0]$6045
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $2\wb_dcache_en$next[0:0]$6101
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $2\wb_icache_en$next[0:0]$6102
- attribute \src "libresoc.v:138463.3-138483.6"
- wire $2\wb_sram_en$next[0:0]$6103
- attribute \src "libresoc.v:138329.3-138361.6"
- wire width 4 $3\dmi0__addr_i$next[3:0]$6075
- attribute \src "libresoc.v:138415.3-138441.6"
- wire width 64 $3\dmi0__din$next[63:0]$6088
- attribute \src "libresoc.v:138035.3-138055.6"
- wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6016
- attribute \src "libresoc.v:138442.3-138462.6"
- wire width 64 $3\dmi0_datasr__i$next[63:0]$6093
- attribute \src "libresoc.v:138091.3-138111.6"
- wire width 64 $3\dmi0_datasr_reg$next[63:0]$6031
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $3\fsm_state$503$next[2:0]$6081
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $3\fsm_state$next[2:0]$6058
- attribute \src "libresoc.v:138195.3-138227.6"
- wire width 29 $3\jtag_wb__adr$next[28:0]$6052
- attribute \src "libresoc.v:138281.3-138307.6"
- wire width 64 $3\jtag_wb__dat_w$next[63:0]$6065
- attribute \src "libresoc.v:137923.3-137943.6"
- wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5986
- attribute \src "libresoc.v:138308.3-138328.6"
- wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6070
- attribute \src "libresoc.v:137979.3-137999.6"
- wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6001
- attribute \src "libresoc.v:137867.3-137887.6"
- wire width 3 $3\sr0_reg$next[2:0]$5971
- attribute \src "libresoc.v:138147.3-138167.6"
- wire width 3 $3\sr5_reg$next[2:0]$6046
- attribute \src "libresoc.v:138329.3-138361.6"
- wire width 4 $4\dmi0__addr_i$next[3:0]$6076
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $4\fsm_state$503$next[2:0]$6082
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $4\fsm_state$next[2:0]$6059
- attribute \src "libresoc.v:138195.3-138227.6"
- wire width 29 $4\jtag_wb__adr$next[28:0]$6053
- attribute \src "libresoc.v:138362.3-138414.6"
- wire width 3 $5\fsm_state$503$next[2:0]$6083
- attribute \src "libresoc.v:138228.3-138280.6"
- wire width 3 $5\fsm_state$next[2:0]$6060
- attribute \src "libresoc.v:137671.19-137671.112"
- wire width 30 $add$libresoc.v:137671$5881_Y
- attribute \src "libresoc.v:137673.19-137673.112"
- wire width 30 $add$libresoc.v:137673$5883_Y
- attribute \src "libresoc.v:137679.19-137679.112"
- wire width 5 $add$libresoc.v:137679$5890_Y
- attribute \src "libresoc.v:137680.19-137680.112"
- wire width 5 $add$libresoc.v:137680$5891_Y
- attribute \src "libresoc.v:137495.18-137495.112"
- wire $and$libresoc.v:137495$5705_Y
- attribute \src "libresoc.v:137562.18-137562.108"
- wire $and$libresoc.v:137562$5772_Y
- attribute \src "libresoc.v:137573.18-137573.110"
- wire $and$libresoc.v:137573$5783_Y
- attribute \src "libresoc.v:137601.19-137601.110"
- wire $and$libresoc.v:137601$5811_Y
- attribute \src "libresoc.v:137604.19-137604.114"
- wire $and$libresoc.v:137604$5814_Y
- attribute \src "libresoc.v:137607.19-137607.112"
- wire $and$libresoc.v:137607$5817_Y
- attribute \src "libresoc.v:137609.19-137609.113"
- wire $and$libresoc.v:137609$5819_Y
- attribute \src "libresoc.v:137611.19-137611.121"
- wire $and$libresoc.v:137611$5821_Y
- attribute \src "libresoc.v:137614.19-137614.114"
- wire $and$libresoc.v:137614$5824_Y
- attribute \src "libresoc.v:137616.19-137616.112"
- wire $and$libresoc.v:137616$5826_Y
- attribute \src "libresoc.v:137620.19-137620.113"
- wire $and$libresoc.v:137620$5830_Y
- attribute \src "libresoc.v:137622.19-137622.132"
- wire $and$libresoc.v:137622$5832_Y
- attribute \src "libresoc.v:137626.19-137626.114"
- wire $and$libresoc.v:137626$5836_Y
- attribute \src "libresoc.v:137628.19-137628.112"
- wire $and$libresoc.v:137628$5838_Y
- attribute \src "libresoc.v:137631.19-137631.113"
- wire $and$libresoc.v:137631$5841_Y
- attribute \src "libresoc.v:137633.19-137633.132"
- wire $and$libresoc.v:137633$5843_Y
- attribute \src "libresoc.v:137636.19-137636.114"
- wire $and$libresoc.v:137636$5846_Y
- attribute \src "libresoc.v:137638.19-137638.112"
- wire $and$libresoc.v:137638$5848_Y
- attribute \src "libresoc.v:137640.18-137640.108"
- wire $and$libresoc.v:137640$5850_Y
- attribute \src "libresoc.v:137641.19-137641.113"
- wire $and$libresoc.v:137641$5851_Y
- attribute \src "libresoc.v:137643.19-137643.129"
- wire $and$libresoc.v:137643$5853_Y
- attribute \src "libresoc.v:137647.19-137647.114"
- wire $and$libresoc.v:137647$5857_Y
- attribute \src "libresoc.v:137649.19-137649.112"
- wire $and$libresoc.v:137649$5859_Y
- attribute \src "libresoc.v:137651.18-137651.111"
- wire $and$libresoc.v:137651$5861_Y
- attribute \src "libresoc.v:137652.19-137652.113"
- wire $and$libresoc.v:137652$5862_Y
- attribute \src "libresoc.v:137654.19-137654.129"
- wire $and$libresoc.v:137654$5864_Y
- attribute \src "libresoc.v:137657.19-137657.114"
- wire $and$libresoc.v:137657$5867_Y
- attribute \src "libresoc.v:137659.19-137659.112"
- wire $and$libresoc.v:137659$5869_Y
- attribute \src "libresoc.v:137661.19-137661.113"
- wire $and$libresoc.v:137661$5871_Y
- attribute \src "libresoc.v:137664.19-137664.121"
- wire $and$libresoc.v:137664$5874_Y
- attribute \src "libresoc.v:137696.17-137696.106"
- wire $and$libresoc.v:137696$5907_Y
- attribute \src "libresoc.v:137451.17-137451.110"
- wire $eq$libresoc.v:137451$5661_Y
- attribute \src "libresoc.v:137462.18-137462.111"
- wire $eq$libresoc.v:137462$5672_Y
- attribute \src "libresoc.v:137473.18-137473.111"
- wire $eq$libresoc.v:137473$5683_Y
- attribute \src "libresoc.v:137506.17-137506.110"
- wire $eq$libresoc.v:137506$5716_Y
- attribute \src "libresoc.v:137507.18-137507.111"
- wire $eq$libresoc.v:137507$5717_Y
- attribute \src "libresoc.v:137518.18-137518.111"
- wire $eq$libresoc.v:137518$5728_Y
- attribute \src "libresoc.v:137540.18-137540.111"
- wire $eq$libresoc.v:137540$5750_Y
- attribute \src "libresoc.v:137584.18-137584.111"
- wire $eq$libresoc.v:137584$5794_Y
- attribute \src "libresoc.v:137595.18-137595.111"
- wire $eq$libresoc.v:137595$5805_Y
- attribute \src "libresoc.v:137596.19-137596.112"
- wire $eq$libresoc.v:137596$5806_Y
- attribute \src "libresoc.v:137597.19-137597.112"
- wire $eq$libresoc.v:137597$5807_Y
- attribute \src "libresoc.v:137599.19-137599.112"
- wire $eq$libresoc.v:137599$5809_Y
- attribute \src "libresoc.v:137602.19-137602.112"
- wire $eq$libresoc.v:137602$5812_Y
- attribute \src "libresoc.v:137612.19-137612.112"
- wire $eq$libresoc.v:137612$5822_Y
- attribute \src "libresoc.v:137617.17-137617.110"
- wire $eq$libresoc.v:137617$5827_Y
- attribute \src "libresoc.v:137618.18-137618.111"
- wire $eq$libresoc.v:137618$5828_Y
- attribute \src "libresoc.v:137623.19-137623.112"
- wire $eq$libresoc.v:137623$5833_Y
- attribute \src "libresoc.v:137624.19-137624.112"
- wire $eq$libresoc.v:137624$5834_Y
- attribute \src "libresoc.v:137634.19-137634.112"
- wire $eq$libresoc.v:137634$5844_Y
- attribute \src "libresoc.v:137644.19-137644.112"
- wire $eq$libresoc.v:137644$5854_Y
- attribute \src "libresoc.v:137645.19-137645.112"
- wire $eq$libresoc.v:137645$5855_Y
- attribute \src "libresoc.v:137655.19-137655.112"
- wire $eq$libresoc.v:137655$5865_Y
- attribute \src "libresoc.v:137662.18-137662.111"
- wire $eq$libresoc.v:137662$5872_Y
- attribute \src "libresoc.v:137665.19-137665.110"
- wire $eq$libresoc.v:137665$5875_Y
- attribute \src "libresoc.v:137667.19-137667.110"
- wire $eq$libresoc.v:137667$5877_Y
- attribute \src "libresoc.v:137668.19-137668.110"
- wire $eq$libresoc.v:137668$5878_Y
- attribute \src "libresoc.v:137670.19-137670.110"
- wire $eq$libresoc.v:137670$5880_Y
- attribute \src "libresoc.v:137672.18-137672.111"
- wire $eq$libresoc.v:137672$5882_Y
- attribute \src "libresoc.v:137675.19-137675.116"
- wire $eq$libresoc.v:137675$5886_Y
- attribute \src "libresoc.v:137676.19-137676.116"
- wire $eq$libresoc.v:137676$5887_Y
- attribute \src "libresoc.v:137678.19-137678.116"
- wire $eq$libresoc.v:137678$5889_Y
- attribute \src "libresoc.v:137674.19-137674.106"
- wire width 8 $extend$libresoc.v:137674$5884_Y
- attribute \src "libresoc.v:137603.19-137603.109"
- wire $ne$libresoc.v:137603$5813_Y
- attribute \src "libresoc.v:137605.19-137605.109"
- wire $ne$libresoc.v:137605$5815_Y
- attribute \src "libresoc.v:137608.19-137608.109"
- wire $ne$libresoc.v:137608$5818_Y
- attribute \src "libresoc.v:137613.19-137613.120"
- wire $ne$libresoc.v:137613$5823_Y
- attribute \src "libresoc.v:137615.19-137615.120"
- wire $ne$libresoc.v:137615$5825_Y
- attribute \src "libresoc.v:137619.19-137619.120"
- wire $ne$libresoc.v:137619$5829_Y
- attribute \src "libresoc.v:137625.19-137625.120"
- wire $ne$libresoc.v:137625$5835_Y
- attribute \src "libresoc.v:137627.19-137627.120"
- wire $ne$libresoc.v:137627$5837_Y
- attribute \src "libresoc.v:137630.19-137630.120"
- wire $ne$libresoc.v:137630$5840_Y
- attribute \src "libresoc.v:137635.19-137635.117"
- wire $ne$libresoc.v:137635$5845_Y
- attribute \src "libresoc.v:137637.19-137637.117"
- wire $ne$libresoc.v:137637$5847_Y
- attribute \src "libresoc.v:137639.19-137639.117"
- wire $ne$libresoc.v:137639$5849_Y
- attribute \src "libresoc.v:137646.19-137646.117"
- wire $ne$libresoc.v:137646$5856_Y
- attribute \src "libresoc.v:137648.19-137648.117"
- wire $ne$libresoc.v:137648$5858_Y
- attribute \src "libresoc.v:137650.19-137650.117"
- wire $ne$libresoc.v:137650$5860_Y
- attribute \src "libresoc.v:137656.19-137656.109"
- wire $ne$libresoc.v:137656$5866_Y
- attribute \src "libresoc.v:137658.19-137658.109"
- wire $ne$libresoc.v:137658$5868_Y
- attribute \src "libresoc.v:137660.19-137660.109"
- wire $ne$libresoc.v:137660$5870_Y
- attribute \src "libresoc.v:137610.19-137610.110"
- wire $not$libresoc.v:137610$5820_Y
- attribute \src "libresoc.v:137621.19-137621.121"
- wire $not$libresoc.v:137621$5831_Y
- attribute \src "libresoc.v:137632.19-137632.121"
- wire $not$libresoc.v:137632$5842_Y
- attribute \src "libresoc.v:137642.19-137642.118"
- wire $not$libresoc.v:137642$5852_Y
- attribute \src "libresoc.v:137653.19-137653.118"
- wire $not$libresoc.v:137653$5863_Y
- attribute \src "libresoc.v:137663.19-137663.110"
- wire $not$libresoc.v:137663$5873_Y
- attribute \src "libresoc.v:137666.19-137666.100"
- wire $not$libresoc.v:137666$5876_Y
- attribute \src "libresoc.v:137484.18-137484.104"
- wire $or$libresoc.v:137484$5694_Y
- attribute \src "libresoc.v:137529.18-137529.104"
- wire $or$libresoc.v:137529$5739_Y
- attribute \src "libresoc.v:137551.18-137551.104"
- wire $or$libresoc.v:137551$5761_Y
- attribute \src "libresoc.v:137598.19-137598.107"
- wire $or$libresoc.v:137598$5808_Y
- attribute \src "libresoc.v:137600.19-137600.107"
- wire $or$libresoc.v:137600$5810_Y
- attribute \src "libresoc.v:137606.18-137606.104"
- wire $or$libresoc.v:137606$5816_Y
- attribute \src "libresoc.v:137629.18-137629.104"
- wire $or$libresoc.v:137629$5839_Y
- attribute \src "libresoc.v:137669.19-137669.107"
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+ wire $2\sr0__oe$next[0:0]$5892
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+ wire width 3 $2\sr0_reg$next[2:0]$5896
+ attribute \src "libresoc.v:136260.3-136276.6"
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+ attribute \src "libresoc.v:136277.3-136297.6"
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+ attribute \src "libresoc.v:136593.3-136613.6"
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+ wire $2\wb_icache_en$next[0:0]$6028
+ attribute \src "libresoc.v:136593.3-136613.6"
+ wire $2\wb_sram_en$next[0:0]$6029
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+ wire width 64 $3\dmi0__din$next[63:0]$6014
+ attribute \src "libresoc.v:136165.3-136185.6"
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+ wire $eq$libresoc.v:135592$5598_Y
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+ wire $eq$libresoc.v:135603$5609_Y
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+ wire $eq$libresoc.v:135637$5643_Y
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+ wire $eq$libresoc.v:135670$5676_Y
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+ wire $eq$libresoc.v:135714$5720_Y
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+ wire $eq$libresoc.v:135725$5731_Y
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+ wire $eq$libresoc.v:135726$5732_Y
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+ wire $eq$libresoc.v:135727$5733_Y
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+ wire $eq$libresoc.v:135732$5738_Y
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+ wire $eq$libresoc.v:135742$5748_Y
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+ wire $eq$libresoc.v:135747$5753_Y
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+ wire $eq$libresoc.v:135748$5754_Y
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+ wire $eq$libresoc.v:135753$5759_Y
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+ wire $eq$libresoc.v:135754$5760_Y
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+ wire $eq$libresoc.v:135764$5770_Y
+ attribute \src "libresoc.v:135774.19-135774.112"
+ wire $eq$libresoc.v:135774$5780_Y
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+ wire $eq$libresoc.v:135775$5781_Y
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+ wire $eq$libresoc.v:135785$5791_Y
+ attribute \src "libresoc.v:135792.18-135792.111"
+ wire $eq$libresoc.v:135792$5798_Y
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+ wire $eq$libresoc.v:135795$5801_Y
+ attribute \src "libresoc.v:135797.19-135797.110"
+ wire $eq$libresoc.v:135797$5803_Y
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+ wire $eq$libresoc.v:135798$5804_Y
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+ wire $eq$libresoc.v:135800$5806_Y
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+ wire $eq$libresoc.v:135802$5808_Y
+ attribute \src "libresoc.v:135805.19-135805.116"
+ wire $eq$libresoc.v:135805$5812_Y
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+ wire $eq$libresoc.v:135806$5813_Y
+ attribute \src "libresoc.v:135808.19-135808.116"
+ wire $eq$libresoc.v:135808$5815_Y
+ attribute \src "libresoc.v:135804.19-135804.106"
+ wire width 8 $extend$libresoc.v:135804$5810_Y
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+ wire $ne$libresoc.v:135733$5739_Y
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+ wire $ne$libresoc.v:135735$5741_Y
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+ wire $ne$libresoc.v:135738$5744_Y
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+ wire $ne$libresoc.v:135743$5749_Y
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+ wire $ne$libresoc.v:135745$5751_Y
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+ wire $ne$libresoc.v:135749$5755_Y
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+ wire $ne$libresoc.v:135755$5761_Y
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+ wire $ne$libresoc.v:135757$5763_Y
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+ wire $ne$libresoc.v:135760$5766_Y
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+ wire $ne$libresoc.v:135765$5771_Y
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+ wire $ne$libresoc.v:135767$5773_Y
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+ wire $ne$libresoc.v:135769$5775_Y
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+ wire $ne$libresoc.v:135776$5782_Y
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+ wire $ne$libresoc.v:135778$5784_Y
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+ wire $ne$libresoc.v:135780$5786_Y
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+ wire $ne$libresoc.v:135786$5792_Y
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+ wire $ne$libresoc.v:135788$5794_Y
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+ wire $ne$libresoc.v:135790$5796_Y
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+ wire $not$libresoc.v:135740$5746_Y
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+ wire $not$libresoc.v:135751$5757_Y
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+ wire $not$libresoc.v:135762$5768_Y
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+ wire $not$libresoc.v:135772$5778_Y
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+ wire $not$libresoc.v:135783$5789_Y
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+ wire $not$libresoc.v:135793$5799_Y
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+ wire $not$libresoc.v:135796$5802_Y
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+ wire $or$libresoc.v:135614$5620_Y
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+ wire $or$libresoc.v:135659$5665_Y
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+ wire $or$libresoc.v:135681$5687_Y
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+ wire $or$libresoc.v:135728$5734_Y
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+ wire $or$libresoc.v:135730$5736_Y
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+ wire $or$libresoc.v:135736$5742_Y
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+ wire $or$libresoc.v:135799$5805_Y
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+ wire width 8 $pos$libresoc.v:135804$5811_Y
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+ wire $ternary$libresoc.v:135583$5589_Y
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+ wire $ternary$libresoc.v:135584$5590_Y
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+ wire $ternary$libresoc.v:135585$5591_Y
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+ wire $ternary$libresoc.v:135586$5592_Y
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+ wire $ternary$libresoc.v:135587$5593_Y
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+ wire $ternary$libresoc.v:135588$5594_Y
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+ wire $ternary$libresoc.v:135590$5596_Y
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+ wire $ternary$libresoc.v:135594$5600_Y
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+ wire $ternary$libresoc.v:135601$5607_Y
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+ attribute \src "libresoc.v:135633.19-135633.135"
+ wire $ternary$libresoc.v:135633$5639_Y
+ attribute \src "libresoc.v:135634.19-135634.135"
+ wire $ternary$libresoc.v:135634$5640_Y
+ attribute \src "libresoc.v:135635.19-135635.134"
+ wire $ternary$libresoc.v:135635$5641_Y
+ attribute \src "libresoc.v:135638.19-135638.135"
+ wire $ternary$libresoc.v:135638$5644_Y
+ attribute \src "libresoc.v:135639.19-135639.135"
+ wire $ternary$libresoc.v:135639$5645_Y
+ attribute \src "libresoc.v:135640.19-135640.134"
+ wire $ternary$libresoc.v:135640$5646_Y
+ attribute \src "libresoc.v:135641.19-135641.135"
+ wire $ternary$libresoc.v:135641$5647_Y
+ attribute \src "libresoc.v:135642.19-135642.135"
+ wire $ternary$libresoc.v:135642$5648_Y
+ attribute \src "libresoc.v:135643.19-135643.134"
+ wire $ternary$libresoc.v:135643$5649_Y
+ attribute \src "libresoc.v:135644.19-135644.135"
+ wire $ternary$libresoc.v:135644$5650_Y
+ attribute \src "libresoc.v:135645.19-135645.133"
+ wire $ternary$libresoc.v:135645$5651_Y
+ attribute \src "libresoc.v:135646.19-135646.134"
+ wire $ternary$libresoc.v:135646$5652_Y
+ attribute \src "libresoc.v:135647.19-135647.133"
+ wire $ternary$libresoc.v:135647$5653_Y
+ attribute \src "libresoc.v:135649.19-135649.134"
+ wire $ternary$libresoc.v:135649$5655_Y
+ attribute \src "libresoc.v:135650.19-135650.134"
+ wire $ternary$libresoc.v:135650$5656_Y
+ attribute \src "libresoc.v:135651.19-135651.133"
+ wire $ternary$libresoc.v:135651$5657_Y
+ attribute \src "libresoc.v:135652.19-135652.134"
+ wire $ternary$libresoc.v:135652$5658_Y
+ attribute \src "libresoc.v:135653.19-135653.134"
+ wire $ternary$libresoc.v:135653$5659_Y
+ attribute \src "libresoc.v:135654.19-135654.133"
+ wire $ternary$libresoc.v:135654$5660_Y
+ attribute \src "libresoc.v:135655.19-135655.134"
+ wire $ternary$libresoc.v:135655$5661_Y
+ attribute \src "libresoc.v:135656.19-135656.134"
+ wire $ternary$libresoc.v:135656$5662_Y
+ attribute \src "libresoc.v:135657.19-135657.133"
+ wire $ternary$libresoc.v:135657$5663_Y
+ attribute \src "libresoc.v:135658.19-135658.134"
+ wire $ternary$libresoc.v:135658$5664_Y
+ attribute \src "libresoc.v:135660.19-135660.134"
+ wire $ternary$libresoc.v:135660$5666_Y
+ attribute \src "libresoc.v:135661.19-135661.133"
+ wire $ternary$libresoc.v:135661$5667_Y
+ attribute \src "libresoc.v:135662.19-135662.134"
+ wire $ternary$libresoc.v:135662$5668_Y
+ attribute \src "libresoc.v:135663.19-135663.134"
+ wire $ternary$libresoc.v:135663$5669_Y
+ attribute \src "libresoc.v:135664.19-135664.133"
+ wire $ternary$libresoc.v:135664$5670_Y
+ attribute \src "libresoc.v:135665.19-135665.134"
+ wire $ternary$libresoc.v:135665$5671_Y
+ attribute \src "libresoc.v:135666.19-135666.135"
+ wire $ternary$libresoc.v:135666$5672_Y
+ attribute \src "libresoc.v:135667.19-135667.134"
+ wire $ternary$libresoc.v:135667$5673_Y
+ attribute \src "libresoc.v:135668.19-135668.135"
+ wire $ternary$libresoc.v:135668$5674_Y
+ attribute \src "libresoc.v:135669.19-135669.135"
+ wire $ternary$libresoc.v:135669$5675_Y
+ attribute \src "libresoc.v:135671.19-135671.134"
+ wire $ternary$libresoc.v:135671$5677_Y
+ attribute \src "libresoc.v:135672.19-135672.135"
+ wire $ternary$libresoc.v:135672$5678_Y
+ attribute \src "libresoc.v:135673.19-135673.133"
+ wire $ternary$libresoc.v:135673$5679_Y
+ attribute \src "libresoc.v:135674.19-135674.133"
+ wire $ternary$libresoc.v:135674$5680_Y
+ attribute \src "libresoc.v:135675.19-135675.133"
+ wire $ternary$libresoc.v:135675$5681_Y
+ attribute \src "libresoc.v:135676.19-135676.133"
+ wire $ternary$libresoc.v:135676$5682_Y
+ attribute \src "libresoc.v:135677.19-135677.133"
+ wire $ternary$libresoc.v:135677$5683_Y
+ attribute \src "libresoc.v:135678.19-135678.133"
+ wire $ternary$libresoc.v:135678$5684_Y
+ attribute \src "libresoc.v:135679.19-135679.133"
+ wire $ternary$libresoc.v:135679$5685_Y
+ attribute \src "libresoc.v:135680.19-135680.133"
+ wire $ternary$libresoc.v:135680$5686_Y
+ attribute \src "libresoc.v:135682.19-135682.133"
+ wire $ternary$libresoc.v:135682$5688_Y
+ attribute \src "libresoc.v:135683.19-135683.133"
+ wire $ternary$libresoc.v:135683$5689_Y
+ attribute \src "libresoc.v:135684.19-135684.134"
+ wire $ternary$libresoc.v:135684$5690_Y
+ attribute \src "libresoc.v:135685.19-135685.134"
+ wire $ternary$libresoc.v:135685$5691_Y
+ attribute \src "libresoc.v:135686.19-135686.135"
+ wire $ternary$libresoc.v:135686$5692_Y
+ attribute \src "libresoc.v:135687.19-135687.133"
+ wire $ternary$libresoc.v:135687$5693_Y
+ attribute \src "libresoc.v:135688.19-135688.135"
+ wire $ternary$libresoc.v:135688$5694_Y
+ attribute \src "libresoc.v:135689.19-135689.135"
+ wire $ternary$libresoc.v:135689$5695_Y
+ attribute \src "libresoc.v:135690.19-135690.134"
+ wire $ternary$libresoc.v:135690$5696_Y
+ attribute \src "libresoc.v:135691.19-135691.134"
+ wire $ternary$libresoc.v:135691$5697_Y
+ attribute \src "libresoc.v:135693.19-135693.134"
+ wire $ternary$libresoc.v:135693$5699_Y
+ attribute \src "libresoc.v:135694.19-135694.134"
+ wire $ternary$libresoc.v:135694$5700_Y
+ attribute \src "libresoc.v:135695.19-135695.134"
+ wire $ternary$libresoc.v:135695$5701_Y
+ attribute \src "libresoc.v:135696.19-135696.135"
+ wire $ternary$libresoc.v:135696$5702_Y
+ attribute \src "libresoc.v:135697.19-135697.134"
+ wire $ternary$libresoc.v:135697$5703_Y
+ attribute \src "libresoc.v:135698.19-135698.135"
+ wire $ternary$libresoc.v:135698$5704_Y
+ attribute \src "libresoc.v:135699.19-135699.135"
+ wire $ternary$libresoc.v:135699$5705_Y
+ attribute \src "libresoc.v:135700.19-135700.134"
+ wire $ternary$libresoc.v:135700$5706_Y
+ attribute \src "libresoc.v:135701.19-135701.135"
+ wire $ternary$libresoc.v:135701$5707_Y
+ attribute \src "libresoc.v:135702.19-135702.135"
+ wire $ternary$libresoc.v:135702$5708_Y
+ attribute \src "libresoc.v:135704.19-135704.134"
+ wire $ternary$libresoc.v:135704$5710_Y
+ attribute \src "libresoc.v:135705.19-135705.135"
+ wire $ternary$libresoc.v:135705$5711_Y
+ attribute \src "libresoc.v:135706.19-135706.136"
+ wire $ternary$libresoc.v:135706$5712_Y
+ attribute \src "libresoc.v:135707.19-135707.135"
+ wire $ternary$libresoc.v:135707$5713_Y
+ attribute \src "libresoc.v:135708.19-135708.136"
+ wire $ternary$libresoc.v:135708$5714_Y
+ attribute \src "libresoc.v:135709.19-135709.136"
+ wire $ternary$libresoc.v:135709$5715_Y
+ attribute \src "libresoc.v:135710.19-135710.135"
+ wire $ternary$libresoc.v:135710$5716_Y
+ attribute \src "libresoc.v:135711.19-135711.136"
+ wire $ternary$libresoc.v:135711$5717_Y
+ attribute \src "libresoc.v:135712.19-135712.136"
+ wire $ternary$libresoc.v:135712$5718_Y
+ attribute \src "libresoc.v:135713.19-135713.135"
+ wire $ternary$libresoc.v:135713$5719_Y
+ attribute \src "libresoc.v:135715.19-135715.136"
+ wire $ternary$libresoc.v:135715$5721_Y
+ attribute \src "libresoc.v:135716.19-135716.136"
+ wire $ternary$libresoc.v:135716$5722_Y
+ attribute \src "libresoc.v:135717.19-135717.135"
+ wire $ternary$libresoc.v:135717$5723_Y
+ attribute \src "libresoc.v:135718.19-135718.136"
+ wire $ternary$libresoc.v:135718$5724_Y
+ attribute \src "libresoc.v:135719.19-135719.136"
+ wire $ternary$libresoc.v:135719$5725_Y
+ attribute \src "libresoc.v:135720.19-135720.135"
+ wire $ternary$libresoc.v:135720$5726_Y
+ attribute \src "libresoc.v:135721.19-135721.136"
+ wire $ternary$libresoc.v:135721$5727_Y
+ attribute \src "libresoc.v:135722.19-135722.136"
+ wire $ternary$libresoc.v:135722$5728_Y
+ attribute \src "libresoc.v:135723.19-135723.135"
+ wire $ternary$libresoc.v:135723$5729_Y
+ attribute \src "libresoc.v:135724.19-135724.136"
+ wire $ternary$libresoc.v:135724$5730_Y
+ attribute \src "libresoc.v:135811.18-135811.130"
+ wire $ternary$libresoc.v:135811$5818_Y
+ attribute \src "libresoc.v:135812.18-135812.130"
+ wire $ternary$libresoc.v:135812$5819_Y
+ attribute \src "libresoc.v:135813.18-135813.130"
+ wire $ternary$libresoc.v:135813$5820_Y
+ attribute \src "libresoc.v:135814.18-135814.131"
+ wire $ternary$libresoc.v:135814$5821_Y
+ attribute \src "libresoc.v:135816.18-135816.130"
+ wire $ternary$libresoc.v:135816$5823_Y
+ attribute \src "libresoc.v:135817.18-135817.131"
+ wire $ternary$libresoc.v:135817$5824_Y
+ attribute \src "libresoc.v:135818.18-135818.131"
+ wire $ternary$libresoc.v:135818$5825_Y
+ attribute \src "libresoc.v:135819.18-135819.130"
+ wire $ternary$libresoc.v:135819$5826_Y
+ attribute \src "libresoc.v:135820.18-135820.131"
+ wire $ternary$libresoc.v:135820$5827_Y
+ attribute \src "libresoc.v:135821.18-135821.132"
+ wire $ternary$libresoc.v:135821$5828_Y
+ attribute \src "libresoc.v:135822.18-135822.132"
+ wire $ternary$libresoc.v:135822$5829_Y
+ attribute \src "libresoc.v:135823.18-135823.133"
+ wire $ternary$libresoc.v:135823$5830_Y
+ attribute \src "libresoc.v:135824.18-135824.133"
+ wire $ternary$libresoc.v:135824$5831_Y
+ attribute \src "libresoc.v:135825.18-135825.132"
+ wire $ternary$libresoc.v:135825$5832_Y
+ attribute \src "libresoc.v:135827.18-135827.133"
+ wire $ternary$libresoc.v:135827$5834_Y
+ attribute \src "libresoc.v:135828.18-135828.133"
+ wire $ternary$libresoc.v:135828$5835_Y
+ attribute \src "libresoc.v:135829.18-135829.132"
+ wire $ternary$libresoc.v:135829$5836_Y
+ attribute \src "libresoc.v:135830.18-135830.133"
+ wire $ternary$libresoc.v:135830$5837_Y
+ attribute \src "libresoc.v:135831.18-135831.133"
+ wire $ternary$libresoc.v:135831$5838_Y
+ attribute \src "libresoc.v:135832.18-135832.132"
+ wire $ternary$libresoc.v:135832$5839_Y
+ attribute \src "libresoc.v:135833.18-135833.133"
+ wire $ternary$libresoc.v:135833$5840_Y
+ attribute \src "libresoc.v:135834.18-135834.133"
+ wire $ternary$libresoc.v:135834$5841_Y
+ attribute \src "libresoc.v:135835.18-135835.132"
+ wire $ternary$libresoc.v:135835$5842_Y
+ attribute \src "libresoc.v:135836.18-135836.133"
+ wire $ternary$libresoc.v:135836$5843_Y
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
wire \$1
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
wire \$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
- wire input 329 \TAP_bus__tck
+ wire input 328 \TAP_bus__tck
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
- wire input 165 \TAP_bus__tdi
+ wire input 164 \TAP_bus__tdi
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
- wire output 320 \TAP_bus__tdo
+ wire output 319 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
- wire input 330 \TAP_bus__tms
+ wire input 329 \TAP_bus__tms
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414"
wire \TAP_tdo
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
wire width 4 \_irblock_ir
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
wire \_irblock_tdo
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 331 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 330 \clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire input 6 \dmi0__ack_o
+ wire input 5 \dmi0__ack_o
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire width 4 output 2 \dmi0__addr_i
+ wire width 4 output 1 \dmi0__addr_i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire width 4 \dmi0__addr_i$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire width 64 output 5 \dmi0__din
+ wire width 64 output 4 \dmi0__din
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire width 64 \dmi0__din$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire width 64 input 7 \dmi0__dout
+ wire width 64 input 6 \dmi0__dout
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire output 3 \dmi0__req_i
+ wire output 2 \dmi0__req_i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- wire output 4 \dmi0__we_i
+ wire output 3 \dmi0__we_i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
wire width 8 \dmi0_addrsr__i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
wire \dmi0_datasr_update_core_prev$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 166 \eint_0__core__i
+ wire output 165 \eint_0__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 11 \eint_0__pad__i
+ wire input 10 \eint_0__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 167 \eint_1__core__i
+ wire output 166 \eint_1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 12 \eint_1__pad__i
+ wire input 11 \eint_1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 168 \eint_2__core__i
+ wire output 167 \eint_2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 13 \eint_2__pad__i
+ wire input 12 \eint_2__pad__i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
wire width 3 \fsm_state
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
wire width 3 \fsm_state$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 175 \gpio_e10__core__i
+ wire output 174 \gpio_e10__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 21 \gpio_e10__core__o
+ wire input 20 \gpio_e10__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 22 \gpio_e10__core__oe
+ wire input 21 \gpio_e10__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 20 \gpio_e10__pad__i
+ wire input 19 \gpio_e10__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 176 \gpio_e10__pad__o
+ wire output 175 \gpio_e10__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 177 \gpio_e10__pad__oe
+ wire output 176 \gpio_e10__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 178 \gpio_e11__core__i
+ wire output 177 \gpio_e11__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 24 \gpio_e11__core__o
+ wire input 23 \gpio_e11__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 25 \gpio_e11__core__oe
+ wire input 24 \gpio_e11__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 23 \gpio_e11__pad__i
+ wire input 22 \gpio_e11__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 179 \gpio_e11__pad__o
+ wire output 178 \gpio_e11__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 180 \gpio_e11__pad__oe
+ wire output 179 \gpio_e11__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 181 \gpio_e12__core__i
+ wire output 180 \gpio_e12__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 27 \gpio_e12__core__o
+ wire input 26 \gpio_e12__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 28 \gpio_e12__core__oe
+ wire input 27 \gpio_e12__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 26 \gpio_e12__pad__i
+ wire input 25 \gpio_e12__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 182 \gpio_e12__pad__o
+ wire output 181 \gpio_e12__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 183 \gpio_e12__pad__oe
+ wire output 182 \gpio_e12__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 184 \gpio_e13__core__i
+ wire output 183 \gpio_e13__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 30 \gpio_e13__core__o
+ wire input 29 \gpio_e13__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 31 \gpio_e13__core__oe
+ wire input 30 \gpio_e13__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 29 \gpio_e13__pad__i
+ wire input 28 \gpio_e13__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 185 \gpio_e13__pad__o
+ wire output 184 \gpio_e13__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 186 \gpio_e13__pad__oe
+ wire output 185 \gpio_e13__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 187 \gpio_e14__core__i
+ wire output 186 \gpio_e14__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 33 \gpio_e14__core__o
+ wire input 32 \gpio_e14__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 34 \gpio_e14__core__oe
+ wire input 33 \gpio_e14__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 32 \gpio_e14__pad__i
+ wire input 31 \gpio_e14__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 188 \gpio_e14__pad__o
+ wire output 187 \gpio_e14__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 189 \gpio_e14__pad__oe
+ wire output 188 \gpio_e14__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 190 \gpio_e15__core__i
+ wire output 189 \gpio_e15__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 36 \gpio_e15__core__o
+ wire input 35 \gpio_e15__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 37 \gpio_e15__core__oe
+ wire input 36 \gpio_e15__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 35 \gpio_e15__pad__i
+ wire input 34 \gpio_e15__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 191 \gpio_e15__pad__o
+ wire output 190 \gpio_e15__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 192 \gpio_e15__pad__oe
+ wire output 191 \gpio_e15__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 169 \gpio_e8__core__i
+ wire output 168 \gpio_e8__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 15 \gpio_e8__core__o
+ wire input 14 \gpio_e8__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 16 \gpio_e8__core__oe
+ wire input 15 \gpio_e8__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 14 \gpio_e8__pad__i
+ wire input 13 \gpio_e8__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 170 \gpio_e8__pad__o
+ wire output 169 \gpio_e8__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 171 \gpio_e8__pad__oe
+ wire output 170 \gpio_e8__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 172 \gpio_e9__core__i
+ wire output 171 \gpio_e9__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 18 \gpio_e9__core__o
+ wire input 17 \gpio_e9__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 19 \gpio_e9__core__oe
+ wire input 18 \gpio_e9__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 17 \gpio_e9__pad__i
+ wire input 16 \gpio_e9__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 173 \gpio_e9__pad__o
+ wire output 172 \gpio_e9__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 174 \gpio_e9__pad__oe
+ wire output 173 \gpio_e9__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 193 \gpio_s0__core__i
+ wire output 192 \gpio_s0__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 39 \gpio_s0__core__o
+ wire input 38 \gpio_s0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 40 \gpio_s0__core__oe
+ wire input 39 \gpio_s0__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 38 \gpio_s0__pad__i
+ wire input 37 \gpio_s0__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 194 \gpio_s0__pad__o
+ wire output 193 \gpio_s0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 195 \gpio_s0__pad__oe
+ wire output 194 \gpio_s0__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 196 \gpio_s1__core__i
+ wire output 195 \gpio_s1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 42 \gpio_s1__core__o
+ wire input 41 \gpio_s1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 43 \gpio_s1__core__oe
+ wire input 42 \gpio_s1__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 41 \gpio_s1__pad__i
+ wire input 40 \gpio_s1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 197 \gpio_s1__pad__o
+ wire output 196 \gpio_s1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 198 \gpio_s1__pad__oe
+ wire output 197 \gpio_s1__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 199 \gpio_s2__core__i
+ wire output 198 \gpio_s2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 45 \gpio_s2__core__o
+ wire input 44 \gpio_s2__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 46 \gpio_s2__core__oe
+ wire input 45 \gpio_s2__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 44 \gpio_s2__pad__i
+ wire input 43 \gpio_s2__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 200 \gpio_s2__pad__o
+ wire output 199 \gpio_s2__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 201 \gpio_s2__pad__oe
+ wire output 200 \gpio_s2__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 202 \gpio_s3__core__i
+ wire output 201 \gpio_s3__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 48 \gpio_s3__core__o
+ wire input 47 \gpio_s3__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 49 \gpio_s3__core__oe
+ wire input 48 \gpio_s3__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 47 \gpio_s3__pad__i
+ wire input 46 \gpio_s3__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 203 \gpio_s3__pad__o
+ wire output 202 \gpio_s3__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 204 \gpio_s3__pad__oe
+ wire output 203 \gpio_s3__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 205 \gpio_s4__core__i
+ wire output 204 \gpio_s4__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 51 \gpio_s4__core__o
+ wire input 50 \gpio_s4__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 52 \gpio_s4__core__oe
+ wire input 51 \gpio_s4__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 50 \gpio_s4__pad__i
+ wire input 49 \gpio_s4__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 206 \gpio_s4__pad__o
+ wire output 205 \gpio_s4__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 207 \gpio_s4__pad__oe
+ wire output 206 \gpio_s4__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 208 \gpio_s5__core__i
+ wire output 207 \gpio_s5__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 54 \gpio_s5__core__o
+ wire input 53 \gpio_s5__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 55 \gpio_s5__core__oe
+ wire input 54 \gpio_s5__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 53 \gpio_s5__pad__i
+ wire input 52 \gpio_s5__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 209 \gpio_s5__pad__o
+ wire output 208 \gpio_s5__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 210 \gpio_s5__pad__oe
+ wire output 209 \gpio_s5__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 211 \gpio_s6__core__i
+ wire output 210 \gpio_s6__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 57 \gpio_s6__core__o
+ wire input 56 \gpio_s6__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 58 \gpio_s6__core__oe
+ wire input 57 \gpio_s6__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 56 \gpio_s6__pad__i
+ wire input 55 \gpio_s6__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 212 \gpio_s6__pad__o
+ wire output 211 \gpio_s6__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 213 \gpio_s6__pad__oe
+ wire output 212 \gpio_s6__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 214 \gpio_s7__core__i
+ wire output 213 \gpio_s7__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 60 \gpio_s7__core__o
+ wire input 59 \gpio_s7__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 61 \gpio_s7__core__oe
+ wire input 60 \gpio_s7__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 59 \gpio_s7__pad__i
+ wire input 58 \gpio_s7__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 215 \gpio_s7__pad__o
+ wire output 214 \gpio_s7__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 216 \gpio_s7__pad__oe
- attribute \src "libresoc.v:136016.7-136016.15"
+ wire output 215 \gpio_s7__pad__oe
+ attribute \src "libresoc.v:134147.7-134147.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549"
wire width 154 \io_bd
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
wire \io_update
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire input 327 \jtag_wb__ack
+ wire input 326 \jtag_wb__ack
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire width 29 output 321 \jtag_wb__adr
+ wire width 29 output 320 \jtag_wb__adr
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire width 29 \jtag_wb__adr$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire output 323 \jtag_wb__cyc
+ wire output 322 \jtag_wb__cyc
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire width 64 input 328 \jtag_wb__dat_r
+ wire width 64 input 327 \jtag_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire width 64 output 326 \jtag_wb__dat_w
+ wire width 64 output 325 \jtag_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire width 64 \jtag_wb__dat_w$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire output 322 \jtag_wb__sel
+ wire output 321 \jtag_wb__sel
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire output 324 \jtag_wb__stb
+ wire output 323 \jtag_wb__stb
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
- wire output 325 \jtag_wb__we
+ wire output 324 \jtag_wb__we
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
wire width 29 \jtag_wb_addrsr__i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
wire \jtag_wb_datasr_update_core_prev$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 62 \mspi0_clk__core__o
+ wire input 61 \mspi0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 217 \mspi0_clk__pad__o
+ wire output 216 \mspi0_clk__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 63 \mspi0_cs_n__core__o
+ wire input 62 \mspi0_cs_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 218 \mspi0_cs_n__pad__o
+ wire output 217 \mspi0_cs_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 220 \mspi0_miso__core__i
+ wire output 219 \mspi0_miso__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 65 \mspi0_miso__pad__i
+ wire input 64 \mspi0_miso__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 64 \mspi0_mosi__core__o
+ wire input 63 \mspi0_mosi__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 219 \mspi0_mosi__pad__o
+ wire output 218 \mspi0_mosi__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 66 \mspi1_clk__core__o
+ wire input 65 \mspi1_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 221 \mspi1_clk__pad__o
+ wire output 220 \mspi1_clk__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 67 \mspi1_cs_n__core__o
+ wire input 66 \mspi1_cs_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 222 \mspi1_cs_n__pad__o
+ wire output 221 \mspi1_cs_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 224 \mspi1_miso__core__i
+ wire output 223 \mspi1_miso__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 69 \mspi1_miso__pad__i
+ wire input 68 \mspi1_miso__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 68 \mspi1_mosi__core__o
+ wire input 67 \mspi1_mosi__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 223 \mspi1_mosi__pad__o
+ wire output 222 \mspi1_mosi__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 73 \mtwi_scl__core__o
+ wire input 72 \mtwi_scl__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 228 \mtwi_scl__pad__o
+ wire output 227 \mtwi_scl__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 225 \mtwi_sda__core__i
+ wire output 224 \mtwi_sda__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 71 \mtwi_sda__core__o
+ wire input 70 \mtwi_sda__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 72 \mtwi_sda__core__oe
+ wire input 71 \mtwi_sda__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 70 \mtwi_sda__pad__i
+ wire input 69 \mtwi_sda__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 226 \mtwi_sda__pad__o
+ wire output 225 \mtwi_sda__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 227 \mtwi_sda__pad__oe
+ wire output 226 \mtwi_sda__pad__oe
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
wire \negjtag_clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
wire \posjtag_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 74 \pwm_0__core__o
+ wire input 73 \pwm_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 229 \pwm_0__pad__o
+ wire output 228 \pwm_0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 75 \pwm_1__core__o
+ wire input 74 \pwm_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 230 \pwm_1__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
+ wire output 229 \pwm_1__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 7 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 79 \sd0_clk__core__o
+ wire input 78 \sd0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 234 \sd0_clk__pad__o
+ wire output 233 \sd0_clk__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 231 \sd0_cmd__core__i
+ wire output 230 \sd0_cmd__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 77 \sd0_cmd__core__o
+ wire input 76 \sd0_cmd__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 78 \sd0_cmd__core__oe
+ wire input 77 \sd0_cmd__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 76 \sd0_cmd__pad__i
+ wire input 75 \sd0_cmd__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 232 \sd0_cmd__pad__o
+ wire output 231 \sd0_cmd__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 233 \sd0_cmd__pad__oe
+ wire output 232 \sd0_cmd__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 235 \sd0_data0__core__i
+ wire output 234 \sd0_data0__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 81 \sd0_data0__core__o
+ wire input 80 \sd0_data0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 82 \sd0_data0__core__oe
+ wire input 81 \sd0_data0__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 80 \sd0_data0__pad__i
+ wire input 79 \sd0_data0__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 236 \sd0_data0__pad__o
+ wire output 235 \sd0_data0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 237 \sd0_data0__pad__oe
+ wire output 236 \sd0_data0__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 238 \sd0_data1__core__i
+ wire output 237 \sd0_data1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 84 \sd0_data1__core__o
+ wire input 83 \sd0_data1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 85 \sd0_data1__core__oe
+ wire input 84 \sd0_data1__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 83 \sd0_data1__pad__i
+ wire input 82 \sd0_data1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 239 \sd0_data1__pad__o
+ wire output 238 \sd0_data1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 240 \sd0_data1__pad__oe
+ wire output 239 \sd0_data1__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 241 \sd0_data2__core__i
+ wire output 240 \sd0_data2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 87 \sd0_data2__core__o
+ wire input 86 \sd0_data2__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 88 \sd0_data2__core__oe
+ wire input 87 \sd0_data2__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 86 \sd0_data2__pad__i
+ wire input 85 \sd0_data2__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 242 \sd0_data2__pad__o
+ wire output 241 \sd0_data2__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 243 \sd0_data2__pad__oe
+ wire output 242 \sd0_data2__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 244 \sd0_data3__core__i
+ wire output 243 \sd0_data3__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 90 \sd0_data3__core__o
+ wire input 89 \sd0_data3__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 91 \sd0_data3__core__oe
+ wire input 90 \sd0_data3__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 89 \sd0_data3__pad__i
+ wire input 88 \sd0_data3__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 245 \sd0_data3__pad__o
+ wire output 244 \sd0_data3__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 246 \sd0_data3__pad__oe
+ wire output 245 \sd0_data3__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 117 \sdr_a_0__core__o
+ wire input 116 \sdr_a_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 272 \sdr_a_0__pad__o
+ wire output 271 \sdr_a_0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 135 \sdr_a_10__core__o
+ wire input 134 \sdr_a_10__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 290 \sdr_a_10__pad__o
+ wire output 289 \sdr_a_10__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 136 \sdr_a_11__core__o
+ wire input 135 \sdr_a_11__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 291 \sdr_a_11__pad__o
+ wire output 290 \sdr_a_11__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 137 \sdr_a_12__core__o
+ wire input 136 \sdr_a_12__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 292 \sdr_a_12__pad__o
+ wire output 291 \sdr_a_12__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 118 \sdr_a_1__core__o
+ wire input 117 \sdr_a_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 273 \sdr_a_1__pad__o
+ wire output 272 \sdr_a_1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 119 \sdr_a_2__core__o
+ wire input 118 \sdr_a_2__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 274 \sdr_a_2__pad__o
+ wire output 273 \sdr_a_2__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 120 \sdr_a_3__core__o
+ wire input 119 \sdr_a_3__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 275 \sdr_a_3__pad__o
+ wire output 274 \sdr_a_3__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 121 \sdr_a_4__core__o
+ wire input 120 \sdr_a_4__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 276 \sdr_a_4__pad__o
+ wire output 275 \sdr_a_4__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 122 \sdr_a_5__core__o
+ wire input 121 \sdr_a_5__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 277 \sdr_a_5__pad__o
+ wire output 276 \sdr_a_5__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 123 \sdr_a_6__core__o
+ wire input 122 \sdr_a_6__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 278 \sdr_a_6__pad__o
+ wire output 277 \sdr_a_6__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 124 \sdr_a_7__core__o
+ wire input 123 \sdr_a_7__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 279 \sdr_a_7__pad__o
+ wire output 278 \sdr_a_7__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 125 \sdr_a_8__core__o
+ wire input 124 \sdr_a_8__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 280 \sdr_a_8__pad__o
+ wire output 279 \sdr_a_8__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 126 \sdr_a_9__core__o
+ wire input 125 \sdr_a_9__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 281 \sdr_a_9__pad__o
+ wire output 280 \sdr_a_9__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 127 \sdr_ba_0__core__o
+ wire input 126 \sdr_ba_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 282 \sdr_ba_0__pad__o
+ wire output 281 \sdr_ba_0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 128 \sdr_ba_1__core__o
+ wire input 127 \sdr_ba_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 283 \sdr_ba_1__pad__o
+ wire output 282 \sdr_ba_1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 132 \sdr_cas_n__core__o
+ wire input 131 \sdr_cas_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 287 \sdr_cas_n__pad__o
+ wire output 286 \sdr_cas_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 130 \sdr_cke__core__o
+ wire input 129 \sdr_cke__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 285 \sdr_cke__pad__o
+ wire output 284 \sdr_cke__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 129 \sdr_clock__core__o
+ wire input 128 \sdr_clock__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 284 \sdr_clock__pad__o
+ wire output 283 \sdr_clock__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 134 \sdr_cs_n__core__o
+ wire input 133 \sdr_cs_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 289 \sdr_cs_n__pad__o
+ wire output 288 \sdr_cs_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 92 \sdr_dm_0__core__o
+ wire input 91 \sdr_dm_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 247 \sdr_dm_0__pad__o
+ wire output 246 \sdr_dm_0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 293 \sdr_dm_1__core__i
+ wire output 292 \sdr_dm_1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 139 \sdr_dm_1__core__o
+ wire input 138 \sdr_dm_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 140 \sdr_dm_1__core__oe
+ wire input 139 \sdr_dm_1__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 138 \sdr_dm_1__pad__i
+ wire input 137 \sdr_dm_1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 294 \sdr_dm_1__pad__o
+ wire output 293 \sdr_dm_1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 295 \sdr_dm_1__pad__oe
+ wire output 294 \sdr_dm_1__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 248 \sdr_dq_0__core__i
+ wire output 247 \sdr_dq_0__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 94 \sdr_dq_0__core__o
+ wire input 93 \sdr_dq_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 95 \sdr_dq_0__core__oe
+ wire input 94 \sdr_dq_0__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 93 \sdr_dq_0__pad__i
+ wire input 92 \sdr_dq_0__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 249 \sdr_dq_0__pad__o
+ wire output 248 \sdr_dq_0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 250 \sdr_dq_0__pad__oe
+ wire output 249 \sdr_dq_0__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 302 \sdr_dq_10__core__i
+ wire output 301 \sdr_dq_10__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 148 \sdr_dq_10__core__o
+ wire input 147 \sdr_dq_10__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 149 \sdr_dq_10__core__oe
+ wire input 148 \sdr_dq_10__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 147 \sdr_dq_10__pad__i
+ wire input 146 \sdr_dq_10__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 303 \sdr_dq_10__pad__o
+ wire output 302 \sdr_dq_10__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 304 \sdr_dq_10__pad__oe
+ wire output 303 \sdr_dq_10__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 305 \sdr_dq_11__core__i
+ wire output 304 \sdr_dq_11__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 151 \sdr_dq_11__core__o
+ wire input 150 \sdr_dq_11__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 152 \sdr_dq_11__core__oe
+ wire input 151 \sdr_dq_11__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 150 \sdr_dq_11__pad__i
+ wire input 149 \sdr_dq_11__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 306 \sdr_dq_11__pad__o
+ wire output 305 \sdr_dq_11__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 307 \sdr_dq_11__pad__oe
+ wire output 306 \sdr_dq_11__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 308 \sdr_dq_12__core__i
+ wire output 307 \sdr_dq_12__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 154 \sdr_dq_12__core__o
+ wire input 153 \sdr_dq_12__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 155 \sdr_dq_12__core__oe
+ wire input 154 \sdr_dq_12__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 153 \sdr_dq_12__pad__i
+ wire input 152 \sdr_dq_12__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 309 \sdr_dq_12__pad__o
+ wire output 308 \sdr_dq_12__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 310 \sdr_dq_12__pad__oe
+ wire output 309 \sdr_dq_12__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 311 \sdr_dq_13__core__i
+ wire output 310 \sdr_dq_13__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 157 \sdr_dq_13__core__o
+ wire input 156 \sdr_dq_13__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 158 \sdr_dq_13__core__oe
+ wire input 157 \sdr_dq_13__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 156 \sdr_dq_13__pad__i
+ wire input 155 \sdr_dq_13__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 312 \sdr_dq_13__pad__o
+ wire output 311 \sdr_dq_13__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 313 \sdr_dq_13__pad__oe
+ wire output 312 \sdr_dq_13__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 314 \sdr_dq_14__core__i
+ wire output 313 \sdr_dq_14__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 160 \sdr_dq_14__core__o
+ wire input 159 \sdr_dq_14__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 161 \sdr_dq_14__core__oe
+ wire input 160 \sdr_dq_14__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 159 \sdr_dq_14__pad__i
+ wire input 158 \sdr_dq_14__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 315 \sdr_dq_14__pad__o
+ wire output 314 \sdr_dq_14__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 316 \sdr_dq_14__pad__oe
+ wire output 315 \sdr_dq_14__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 317 \sdr_dq_15__core__i
+ wire output 316 \sdr_dq_15__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 163 \sdr_dq_15__core__o
+ wire input 162 \sdr_dq_15__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 164 \sdr_dq_15__core__oe
+ wire input 163 \sdr_dq_15__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 162 \sdr_dq_15__pad__i
+ wire input 161 \sdr_dq_15__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 318 \sdr_dq_15__pad__o
+ wire output 317 \sdr_dq_15__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 319 \sdr_dq_15__pad__oe
+ wire output 318 \sdr_dq_15__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 251 \sdr_dq_1__core__i
+ wire output 250 \sdr_dq_1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 97 \sdr_dq_1__core__o
+ wire input 96 \sdr_dq_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 98 \sdr_dq_1__core__oe
+ wire input 97 \sdr_dq_1__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 96 \sdr_dq_1__pad__i
+ wire input 95 \sdr_dq_1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 252 \sdr_dq_1__pad__o
+ wire output 251 \sdr_dq_1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 253 \sdr_dq_1__pad__oe
+ wire output 252 \sdr_dq_1__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 254 \sdr_dq_2__core__i
+ wire output 253 \sdr_dq_2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 100 \sdr_dq_2__core__o
+ wire input 99 \sdr_dq_2__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 101 \sdr_dq_2__core__oe
+ wire input 100 \sdr_dq_2__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 99 \sdr_dq_2__pad__i
+ wire input 98 \sdr_dq_2__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 255 \sdr_dq_2__pad__o
+ wire output 254 \sdr_dq_2__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 256 \sdr_dq_2__pad__oe
+ wire output 255 \sdr_dq_2__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 257 \sdr_dq_3__core__i
+ wire output 256 \sdr_dq_3__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 103 \sdr_dq_3__core__o
+ wire input 102 \sdr_dq_3__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 104 \sdr_dq_3__core__oe
+ wire input 103 \sdr_dq_3__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 102 \sdr_dq_3__pad__i
+ wire input 101 \sdr_dq_3__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 258 \sdr_dq_3__pad__o
+ wire output 257 \sdr_dq_3__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 259 \sdr_dq_3__pad__oe
+ wire output 258 \sdr_dq_3__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 260 \sdr_dq_4__core__i
+ wire output 259 \sdr_dq_4__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 106 \sdr_dq_4__core__o
+ wire input 105 \sdr_dq_4__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 107 \sdr_dq_4__core__oe
+ wire input 106 \sdr_dq_4__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 105 \sdr_dq_4__pad__i
+ wire input 104 \sdr_dq_4__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 261 \sdr_dq_4__pad__o
+ wire output 260 \sdr_dq_4__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 262 \sdr_dq_4__pad__oe
+ wire output 261 \sdr_dq_4__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 263 \sdr_dq_5__core__i
+ wire output 262 \sdr_dq_5__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 109 \sdr_dq_5__core__o
+ wire input 108 \sdr_dq_5__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 110 \sdr_dq_5__core__oe
+ wire input 109 \sdr_dq_5__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 108 \sdr_dq_5__pad__i
+ wire input 107 \sdr_dq_5__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 264 \sdr_dq_5__pad__o
+ wire output 263 \sdr_dq_5__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 265 \sdr_dq_5__pad__oe
+ wire output 264 \sdr_dq_5__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 266 \sdr_dq_6__core__i
+ wire output 265 \sdr_dq_6__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 112 \sdr_dq_6__core__o
+ wire input 111 \sdr_dq_6__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 113 \sdr_dq_6__core__oe
+ wire input 112 \sdr_dq_6__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 111 \sdr_dq_6__pad__i
+ wire input 110 \sdr_dq_6__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 267 \sdr_dq_6__pad__o
+ wire output 266 \sdr_dq_6__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 268 \sdr_dq_6__pad__oe
+ wire output 267 \sdr_dq_6__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 269 \sdr_dq_7__core__i
+ wire output 268 \sdr_dq_7__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 115 \sdr_dq_7__core__o
+ wire input 114 \sdr_dq_7__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 116 \sdr_dq_7__core__oe
+ wire input 115 \sdr_dq_7__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 114 \sdr_dq_7__pad__i
+ wire input 113 \sdr_dq_7__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 270 \sdr_dq_7__pad__o
+ wire output 269 \sdr_dq_7__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 271 \sdr_dq_7__pad__oe
+ wire output 270 \sdr_dq_7__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 296 \sdr_dq_8__core__i
+ wire output 295 \sdr_dq_8__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 142 \sdr_dq_8__core__o
+ wire input 141 \sdr_dq_8__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 143 \sdr_dq_8__core__oe
+ wire input 142 \sdr_dq_8__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 141 \sdr_dq_8__pad__i
+ wire input 140 \sdr_dq_8__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 297 \sdr_dq_8__pad__o
+ wire output 296 \sdr_dq_8__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 298 \sdr_dq_8__pad__oe
+ wire output 297 \sdr_dq_8__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 299 \sdr_dq_9__core__i
+ wire output 298 \sdr_dq_9__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 145 \sdr_dq_9__core__o
+ wire input 144 \sdr_dq_9__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 146 \sdr_dq_9__core__oe
+ wire input 145 \sdr_dq_9__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 144 \sdr_dq_9__pad__i
+ wire input 143 \sdr_dq_9__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 300 \sdr_dq_9__pad__o
+ wire output 299 \sdr_dq_9__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 301 \sdr_dq_9__pad__oe
+ wire output 300 \sdr_dq_9__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 131 \sdr_ras_n__core__o
+ wire input 130 \sdr_ras_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 286 \sdr_ras_n__pad__o
+ wire output 285 \sdr_ras_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire input 133 \sdr_we_n__core__o
+ wire input 132 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
- wire output 288 \sdr_we_n__pad__o
+ wire output 287 \sdr_we_n__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
wire width 3 \sr0__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
wire \sr5_update_core_prev$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
- wire output 9 \wb_dcache_en
+ wire output 8 \wb_dcache_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
wire \wb_dcache_en$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
- wire output 10 \wb_icache_en
+ wire output 9 \wb_icache_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire \wb_icache_en$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95"
- wire output 8 \wb_sram_en
+ wire \wb_sram_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95"
wire \wb_sram_en$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761"
- cell $add $add$libresoc.v:137671$5881
+ cell $add $add$libresoc.v:135801$5807
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:137671$5881_Y
+ connect \Y $add$libresoc.v:135801$5807_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786"
- cell $add $add$libresoc.v:137673$5883
+ cell $add $add$libresoc.v:135803$5809
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:137673$5883_Y
+ connect \Y $add$libresoc.v:135803$5809_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494"
- cell $add $add$libresoc.v:137679$5890
+ cell $add $add$libresoc.v:135809$5816
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0__addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:137679$5890_Y
+ connect \Y $add$libresoc.v:135809$5816_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518"
- cell $add $add$libresoc.v:137680$5891
+ cell $add $add$libresoc.v:135810$5817
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0__addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:137680$5891_Y
+ connect \Y $add$libresoc.v:135810$5817_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
- cell $and $and$libresoc.v:137495$5705
+ cell $and $and$libresoc.v:135625$5631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137495$5705_Y
+ connect \Y $and$libresoc.v:135625$5631_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:137562$5772
+ cell $and $and$libresoc.v:135692$5698
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$27
- connect \Y $and$libresoc.v:137562$5772_Y
+ connect \Y $and$libresoc.v:135692$5698_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402"
- cell $and $and$libresoc.v:137573$5783
+ cell $and $and$libresoc.v:135703$5709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137573$5783_Y
+ connect \Y $and$libresoc.v:135703$5709_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:137601$5811
+ cell $and $and$libresoc.v:135731$5737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$367
- connect \Y $and$libresoc.v:137601$5811_Y
+ connect \Y $and$libresoc.v:135731$5737_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137604$5814
+ cell $and $and$libresoc.v:135734$5740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$373
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137604$5814_Y
+ connect \Y $and$libresoc.v:135734$5740_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137607$5817
+ cell $and $and$libresoc.v:135737$5743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$377
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137607$5817_Y
+ connect \Y $and$libresoc.v:135737$5743_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137609$5819
+ cell $and $and$libresoc.v:135739$5745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$381
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137609$5819_Y
+ connect \Y $and$libresoc.v:135739$5745_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137611$5821
+ cell $and $and$libresoc.v:135741$5747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_update_core_prev
connect \B \$385
- connect \Y $and$libresoc.v:137611$5821_Y
+ connect \Y $and$libresoc.v:135741$5747_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137614$5824
+ cell $and $and$libresoc.v:135744$5750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$391
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137614$5824_Y
+ connect \Y $and$libresoc.v:135744$5750_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137616$5826
+ cell $and $and$libresoc.v:135746$5752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$395
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137616$5826_Y
+ connect \Y $and$libresoc.v:135746$5752_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137620$5830
+ cell $and $and$libresoc.v:135750$5756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$399
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137620$5830_Y
+ connect \Y $and$libresoc.v:135750$5756_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137622$5832
+ cell $and $and$libresoc.v:135752$5758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core_prev
connect \B \$403
- connect \Y $and$libresoc.v:137622$5832_Y
+ connect \Y $and$libresoc.v:135752$5758_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137626$5836
+ cell $and $and$libresoc.v:135756$5762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$411
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137626$5836_Y
+ connect \Y $and$libresoc.v:135756$5762_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137628$5838
+ cell $and $and$libresoc.v:135758$5764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$415
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137628$5838_Y
+ connect \Y $and$libresoc.v:135758$5764_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137631$5841
+ cell $and $and$libresoc.v:135761$5767
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$419
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137631$5841_Y
+ connect \Y $and$libresoc.v:135761$5767_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137633$5843
+ cell $and $and$libresoc.v:135763$5769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core_prev
connect \B \$423
- connect \Y $and$libresoc.v:137633$5843_Y
+ connect \Y $and$libresoc.v:135763$5769_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137636$5846
+ cell $and $and$libresoc.v:135766$5772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$429
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137636$5846_Y
+ connect \Y $and$libresoc.v:135766$5772_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137638$5848
+ cell $and $and$libresoc.v:135768$5774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$433
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137638$5848_Y
+ connect \Y $and$libresoc.v:135768$5774_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $and $and$libresoc.v:137640$5850
+ cell $and $and$libresoc.v:135770$5776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$41
- connect \Y $and$libresoc.v:137640$5850_Y
+ connect \Y $and$libresoc.v:135770$5776_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137641$5851
+ cell $and $and$libresoc.v:135771$5777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$437
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137641$5851_Y
+ connect \Y $and$libresoc.v:135771$5777_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137643$5853
+ cell $and $and$libresoc.v:135773$5779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core_prev
connect \B \$441
- connect \Y $and$libresoc.v:137643$5853_Y
+ connect \Y $and$libresoc.v:135773$5779_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137647$5857
+ cell $and $and$libresoc.v:135777$5783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$449
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137647$5857_Y
+ connect \Y $and$libresoc.v:135777$5783_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137649$5859
+ cell $and $and$libresoc.v:135779$5785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$453
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137649$5859_Y
+ connect \Y $and$libresoc.v:135779$5785_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403"
- cell $and $and$libresoc.v:137651$5861
+ cell $and $and$libresoc.v:135781$5787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137651$5861_Y
+ connect \Y $and$libresoc.v:135781$5787_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137652$5862
+ cell $and $and$libresoc.v:135782$5788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$457
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137652$5862_Y
+ connect \Y $and$libresoc.v:135782$5788_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137654$5864
+ cell $and $and$libresoc.v:135784$5790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core_prev
connect \B \$461
- connect \Y $and$libresoc.v:137654$5864_Y
+ connect \Y $and$libresoc.v:135784$5790_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $and $and$libresoc.v:137657$5867
+ cell $and $and$libresoc.v:135787$5793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$467
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:137657$5867_Y
+ connect \Y $and$libresoc.v:135787$5793_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $and $and$libresoc.v:137659$5869
+ cell $and $and$libresoc.v:135789$5795
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$471
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:137659$5869_Y
+ connect \Y $and$libresoc.v:135789$5795_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $and $and$libresoc.v:137661$5871
+ cell $and $and$libresoc.v:135791$5797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$475
connect \B \_fsm_update
- connect \Y $and$libresoc.v:137661$5871_Y
+ connect \Y $and$libresoc.v:135791$5797_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $and $and$libresoc.v:137664$5874
+ cell $and $and$libresoc.v:135794$5800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_update_core_prev
connect \B \$479
- connect \Y $and$libresoc.v:137664$5874_Y
+ connect \Y $and$libresoc.v:135794$5800_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $and $and$libresoc.v:137696$5907
+ cell $and $and$libresoc.v:135826$5833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$5
- connect \Y $and$libresoc.v:137696$5907_Y
+ connect \Y $and$libresoc.v:135826$5833_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:137451$5661
+ cell $eq $eq$libresoc.v:135581$5587
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1111
- connect \Y $eq$libresoc.v:137451$5661_Y
+ connect \Y $eq$libresoc.v:135581$5587_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137462$5672
+ cell $eq $eq$libresoc.v:135592$5598
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137462$5672_Y
+ connect \Y $eq$libresoc.v:135592$5598_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137473$5683
+ cell $eq $eq$libresoc.v:135603$5609
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137473$5683_Y
+ connect \Y $eq$libresoc.v:135603$5609_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $eq $eq$libresoc.v:137506$5716
+ cell $eq $eq$libresoc.v:135636$5642
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'1
- connect \Y $eq$libresoc.v:137506$5716_Y
+ connect \Y $eq$libresoc.v:135636$5642_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137507$5717
+ cell $eq $eq$libresoc.v:135637$5643
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137507$5717_Y
+ connect \Y $eq$libresoc.v:135637$5643_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137518$5728
+ cell $eq $eq$libresoc.v:135648$5654
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137518$5728_Y
+ connect \Y $eq$libresoc.v:135648$5654_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:137540$5750
+ cell $eq $eq$libresoc.v:135670$5676
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137540$5750_Y
+ connect \Y $eq$libresoc.v:135670$5676_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137584$5794
+ cell $eq $eq$libresoc.v:135714$5720
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137584$5794_Y
+ connect \Y $eq$libresoc.v:135714$5720_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137595$5805
+ cell $eq $eq$libresoc.v:135725$5731
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137595$5805_Y
+ connect \Y $eq$libresoc.v:135725$5731_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137596$5806
+ cell $eq $eq$libresoc.v:135726$5732
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137596$5806_Y
+ connect \Y $eq$libresoc.v:135726$5732_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $eq $eq$libresoc.v:137597$5807
+ cell $eq $eq$libresoc.v:135727$5733
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137597$5807_Y
+ connect \Y $eq$libresoc.v:135727$5733_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:137599$5809
+ cell $eq $eq$libresoc.v:135729$5735
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137599$5809_Y
+ connect \Y $eq$libresoc.v:135729$5735_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137602$5812
+ cell $eq $eq$libresoc.v:135732$5738
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'100
- connect \Y $eq$libresoc.v:137602$5812_Y
+ connect \Y $eq$libresoc.v:135732$5738_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137612$5822
+ cell $eq $eq$libresoc.v:135742$5748
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'101
- connect \Y $eq$libresoc.v:137612$5822_Y
+ connect \Y $eq$libresoc.v:135742$5748_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $eq $eq$libresoc.v:137617$5827
+ cell $eq $eq$libresoc.v:135747$5753
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1111
- connect \Y $eq$libresoc.v:137617$5827_Y
+ connect \Y $eq$libresoc.v:135747$5753_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
- cell $eq $eq$libresoc.v:137618$5828
+ cell $eq $eq$libresoc.v:135748$5754
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:137618$5828_Y
+ connect \Y $eq$libresoc.v:135748$5754_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137623$5833
+ cell $eq $eq$libresoc.v:135753$5759
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'110
- connect \Y $eq$libresoc.v:137623$5833_Y
+ connect \Y $eq$libresoc.v:135753$5759_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137624$5834
+ cell $eq $eq$libresoc.v:135754$5760
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'111
- connect \Y $eq$libresoc.v:137624$5834_Y
+ connect \Y $eq$libresoc.v:135754$5760_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137634$5844
+ cell $eq $eq$libresoc.v:135764$5770
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1000
- connect \Y $eq$libresoc.v:137634$5844_Y
+ connect \Y $eq$libresoc.v:135764$5770_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137644$5854
+ cell $eq $eq$libresoc.v:135774$5780
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1001
- connect \Y $eq$libresoc.v:137644$5854_Y
+ connect \Y $eq$libresoc.v:135774$5780_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137645$5855
+ cell $eq $eq$libresoc.v:135775$5781
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1010
- connect \Y $eq$libresoc.v:137645$5855_Y
+ connect \Y $eq$libresoc.v:135775$5781_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
- cell $eq $eq$libresoc.v:137655$5865
+ cell $eq $eq$libresoc.v:135785$5791
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1011
- connect \Y $eq$libresoc.v:137655$5865_Y
+ connect \Y $eq$libresoc.v:135785$5791_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404"
- cell $eq $eq$libresoc.v:137662$5872
+ cell $eq $eq$libresoc.v:135792$5798
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137662$5872_Y
+ connect \Y $eq$libresoc.v:135792$5798_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
- cell $eq $eq$libresoc.v:137665$5875
+ cell $eq $eq$libresoc.v:135795$5801
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'0
- connect \Y $eq$libresoc.v:137665$5875_Y
+ connect \Y $eq$libresoc.v:135795$5801_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $eq $eq$libresoc.v:137667$5877
+ cell $eq $eq$libresoc.v:135797$5803
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'1
- connect \Y $eq$libresoc.v:137667$5877_Y
+ connect \Y $eq$libresoc.v:135797$5803_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $eq $eq$libresoc.v:137668$5878
+ cell $eq $eq$libresoc.v:135798$5804
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:137668$5878_Y
+ connect \Y $eq$libresoc.v:135798$5804_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792"
- cell $eq $eq$libresoc.v:137670$5880
+ cell $eq $eq$libresoc.v:135800$5806
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:137670$5880_Y
+ connect \Y $eq$libresoc.v:135800$5806_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405"
- cell $eq $eq$libresoc.v:137672$5882
+ cell $eq $eq$libresoc.v:135802$5808
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:137672$5882_Y
+ connect \Y $eq$libresoc.v:135802$5808_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $eq $eq$libresoc.v:137675$5886
+ cell $eq $eq$libresoc.v:135805$5812
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$503
connect \B 1'1
- connect \Y $eq$libresoc.v:137675$5886_Y
+ connect \Y $eq$libresoc.v:135805$5812_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $eq $eq$libresoc.v:137676$5887
+ cell $eq $eq$libresoc.v:135806$5813
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$503
connect \B 2'10
- connect \Y $eq$libresoc.v:137676$5887_Y
+ connect \Y $eq$libresoc.v:135806$5813_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524"
- cell $eq $eq$libresoc.v:137678$5889
+ cell $eq $eq$libresoc.v:135808$5815
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$503
connect \B 2'10
- connect \Y $eq$libresoc.v:137678$5889_Y
+ connect \Y $eq$libresoc.v:135808$5815_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- cell $pos $extend$libresoc.v:137674$5884
+ cell $pos $extend$libresoc.v:135804$5810
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \dmi0__addr_i
- connect \Y $extend$libresoc.v:137674$5884_Y
+ connect \Y $extend$libresoc.v:135804$5810_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137603$5813
+ cell $ne $ne$libresoc.v:135733$5739
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137603$5813_Y
+ connect \Y $ne$libresoc.v:135733$5739_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137605$5815
+ cell $ne $ne$libresoc.v:135735$5741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137605$5815_Y
+ connect \Y $ne$libresoc.v:135735$5741_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137608$5818
+ cell $ne $ne$libresoc.v:135738$5744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137608$5818_Y
+ connect \Y $ne$libresoc.v:135738$5744_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137613$5823
+ cell $ne $ne$libresoc.v:135743$5749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137613$5823_Y
+ connect \Y $ne$libresoc.v:135743$5749_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137615$5825
+ cell $ne $ne$libresoc.v:135745$5751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137615$5825_Y
+ connect \Y $ne$libresoc.v:135745$5751_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137619$5829
+ cell $ne $ne$libresoc.v:135749$5755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137619$5829_Y
+ connect \Y $ne$libresoc.v:135749$5755_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137625$5835
+ cell $ne $ne$libresoc.v:135755$5761
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137625$5835_Y
+ connect \Y $ne$libresoc.v:135755$5761_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137627$5837
+ cell $ne $ne$libresoc.v:135757$5763
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137627$5837_Y
+ connect \Y $ne$libresoc.v:135757$5763_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137630$5840
+ cell $ne $ne$libresoc.v:135760$5766
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137630$5840_Y
+ connect \Y $ne$libresoc.v:135760$5766_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137635$5845
+ cell $ne $ne$libresoc.v:135765$5771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137635$5845_Y
+ connect \Y $ne$libresoc.v:135765$5771_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137637$5847
+ cell $ne $ne$libresoc.v:135767$5773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137637$5847_Y
+ connect \Y $ne$libresoc.v:135767$5773_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137639$5849
+ cell $ne $ne$libresoc.v:135769$5775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137639$5849_Y
+ connect \Y $ne$libresoc.v:135769$5775_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137646$5856
+ cell $ne $ne$libresoc.v:135776$5782
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137646$5856_Y
+ connect \Y $ne$libresoc.v:135776$5782_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137648$5858
+ cell $ne $ne$libresoc.v:135778$5784
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137648$5858_Y
+ connect \Y $ne$libresoc.v:135778$5784_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137650$5860
+ cell $ne $ne$libresoc.v:135780$5786
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137650$5860_Y
+ connect \Y $ne$libresoc.v:135780$5786_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
- cell $ne $ne$libresoc.v:137656$5866
+ cell $ne $ne$libresoc.v:135786$5792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137656$5866_Y
+ connect \Y $ne$libresoc.v:135786$5792_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
- cell $ne $ne$libresoc.v:137658$5868
+ cell $ne $ne$libresoc.v:135788$5794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137658$5868_Y
+ connect \Y $ne$libresoc.v:135788$5794_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
- cell $ne $ne$libresoc.v:137660$5870
+ cell $ne $ne$libresoc.v:135790$5796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr5_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:137660$5870_Y
+ connect \Y $ne$libresoc.v:135790$5796_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137610$5820
+ cell $not $not$libresoc.v:135740$5746
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sr0_update_core
- connect \Y $not$libresoc.v:137610$5820_Y
+ connect \Y $not$libresoc.v:135740$5746_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137621$5831
+ cell $not $not$libresoc.v:135751$5757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core
- connect \Y $not$libresoc.v:137621$5831_Y
+ connect \Y $not$libresoc.v:135751$5757_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137632$5842
+ cell $not $not$libresoc.v:135762$5768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core
- connect \Y $not$libresoc.v:137632$5842_Y
+ connect \Y $not$libresoc.v:135762$5768_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137642$5852
+ cell $not $not$libresoc.v:135772$5778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core
- connect \Y $not$libresoc.v:137642$5852_Y
+ connect \Y $not$libresoc.v:135772$5778_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137653$5863
+ cell $not $not$libresoc.v:135783$5789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core
- connect \Y $not$libresoc.v:137653$5863_Y
+ connect \Y $not$libresoc.v:135783$5789_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
- cell $not $not$libresoc.v:137663$5873
+ cell $not $not$libresoc.v:135793$5799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sr5_update_core
- connect \Y $not$libresoc.v:137663$5873_Y
+ connect \Y $not$libresoc.v:135793$5799_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
- cell $not $not$libresoc.v:137666$5876
+ cell $not $not$libresoc.v:135796$5802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$484
- connect \Y $not$libresoc.v:137666$5876_Y
+ connect \Y $not$libresoc.v:135796$5802_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:137484$5694
+ cell $or $or$libresoc.v:135614$5620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$11
connect \B \$13
- connect \Y $or$libresoc.v:137484$5694_Y
+ connect \Y $or$libresoc.v:135614$5620_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:137529$5739
+ cell $or $or$libresoc.v:135659$5665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \$21
- connect \Y $or$libresoc.v:137529$5739_Y
+ connect \Y $or$libresoc.v:135659$5665_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:137551$5761
+ cell $or $or$libresoc.v:135681$5687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $or$libresoc.v:137551$5761_Y
+ connect \Y $or$libresoc.v:135681$5687_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:137598$5808
+ cell $or $or$libresoc.v:135728$5734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$359
connect \B \$361
- connect \Y $or$libresoc.v:137598$5808_Y
+ connect \Y $or$libresoc.v:135728$5734_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:137600$5810
+ cell $or $or$libresoc.v:135730$5736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$363
connect \B \$365
- connect \Y $or$libresoc.v:137600$5810_Y
+ connect \Y $or$libresoc.v:135730$5736_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
- cell $or $or$libresoc.v:137606$5816
+ cell $or $or$libresoc.v:135736$5742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:137606$5816_Y
+ connect \Y $or$libresoc.v:135736$5742_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
- cell $or $or$libresoc.v:137629$5839
+ cell $or $or$libresoc.v:135759$5765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$37
connect \B \$39
- connect \Y $or$libresoc.v:137629$5839_Y
+ connect \Y $or$libresoc.v:135759$5765_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
- cell $or $or$libresoc.v:137669$5879
+ cell $or $or$libresoc.v:135799$5805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$487
connect \B \$489
- connect \Y $or$libresoc.v:137669$5879_Y
+ connect \Y $or$libresoc.v:135799$5805_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
- cell $or $or$libresoc.v:137677$5888
+ cell $or $or$libresoc.v:135807$5814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$504
connect \B \$506
- connect \Y $or$libresoc.v:137677$5888_Y
+ connect \Y $or$libresoc.v:135807$5814_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
- cell $or $or$libresoc.v:137685$5896
+ cell $or $or$libresoc.v:135815$5822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $or$libresoc.v:137685$5896_Y
+ connect \Y $or$libresoc.v:135815$5822_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
- cell $pos $pos$libresoc.v:137674$5885
+ cell $pos $pos$libresoc.v:135804$5811
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:137674$5884_Y
- connect \Y $pos$libresoc.v:137674$5885_Y
+ connect \A $extend$libresoc.v:135804$5810_Y
+ connect \Y $pos$libresoc.v:135804$5811_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137452$5662
+ cell $mux $ternary$libresoc.v:135582$5588
parameter \WIDTH 1
connect \A \gpio_e15__pad__i
connect \B \io_bd [24]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137452$5662_Y
+ connect \Y $ternary$libresoc.v:135582$5588_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137453$5663
+ cell $mux $ternary$libresoc.v:135583$5589
parameter \WIDTH 1
connect \A \gpio_e15__core__o
connect \B \io_bd [25]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137453$5663_Y
+ connect \Y $ternary$libresoc.v:135583$5589_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137454$5664
+ cell $mux $ternary$libresoc.v:135584$5590
parameter \WIDTH 1
connect \A \gpio_e15__core__oe
connect \B \io_bd [26]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137454$5664_Y
+ connect \Y $ternary$libresoc.v:135584$5590_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137455$5665
+ cell $mux $ternary$libresoc.v:135585$5591
parameter \WIDTH 1
connect \A \gpio_s0__pad__i
connect \B \io_bd [27]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137455$5665_Y
+ connect \Y $ternary$libresoc.v:135585$5591_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137456$5666
+ cell $mux $ternary$libresoc.v:135586$5592
parameter \WIDTH 1
connect \A \gpio_s0__core__o
connect \B \io_bd [28]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137456$5666_Y
+ connect \Y $ternary$libresoc.v:135586$5592_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137457$5667
+ cell $mux $ternary$libresoc.v:135587$5593
parameter \WIDTH 1
connect \A \gpio_s0__core__oe
connect \B \io_bd [29]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137457$5667_Y
+ connect \Y $ternary$libresoc.v:135587$5593_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137458$5668
+ cell $mux $ternary$libresoc.v:135588$5594
parameter \WIDTH 1
connect \A \gpio_s1__pad__i
connect \B \io_bd [30]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137458$5668_Y
+ connect \Y $ternary$libresoc.v:135588$5594_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137459$5669
+ cell $mux $ternary$libresoc.v:135589$5595
parameter \WIDTH 1
connect \A \gpio_s1__core__o
connect \B \io_bd [31]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137459$5669_Y
+ connect \Y $ternary$libresoc.v:135589$5595_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137460$5670
+ cell $mux $ternary$libresoc.v:135590$5596
parameter \WIDTH 1
connect \A \gpio_s1__core__oe
connect \B \io_bd [32]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137460$5670_Y
+ connect \Y $ternary$libresoc.v:135590$5596_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137461$5671
+ cell $mux $ternary$libresoc.v:135591$5597
parameter \WIDTH 1
connect \A \gpio_s2__pad__i
connect \B \io_bd [33]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137461$5671_Y
+ connect \Y $ternary$libresoc.v:135591$5597_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137463$5673
+ cell $mux $ternary$libresoc.v:135593$5599
parameter \WIDTH 1
connect \A \gpio_s2__core__o
connect \B \io_bd [34]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137463$5673_Y
+ connect \Y $ternary$libresoc.v:135593$5599_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137464$5674
+ cell $mux $ternary$libresoc.v:135594$5600
parameter \WIDTH 1
connect \A \gpio_s2__core__oe
connect \B \io_bd [35]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137464$5674_Y
+ connect \Y $ternary$libresoc.v:135594$5600_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137465$5675
+ cell $mux $ternary$libresoc.v:135595$5601
parameter \WIDTH 1
connect \A \gpio_s3__pad__i
connect \B \io_bd [36]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137465$5675_Y
+ connect \Y $ternary$libresoc.v:135595$5601_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137466$5676
+ cell $mux $ternary$libresoc.v:135596$5602
parameter \WIDTH 1
connect \A \gpio_s3__core__o
connect \B \io_bd [37]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137466$5676_Y
+ connect \Y $ternary$libresoc.v:135596$5602_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137467$5677
+ cell $mux $ternary$libresoc.v:135597$5603
parameter \WIDTH 1
connect \A \gpio_s3__core__oe
connect \B \io_bd [38]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137467$5677_Y
+ connect \Y $ternary$libresoc.v:135597$5603_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137468$5678
+ cell $mux $ternary$libresoc.v:135598$5604
parameter \WIDTH 1
connect \A \gpio_s4__pad__i
connect \B \io_bd [39]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137468$5678_Y
+ connect \Y $ternary$libresoc.v:135598$5604_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137469$5679
+ cell $mux $ternary$libresoc.v:135599$5605
parameter \WIDTH 1
connect \A \gpio_s4__core__o
connect \B \io_bd [40]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137469$5679_Y
+ connect \Y $ternary$libresoc.v:135599$5605_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137470$5680
+ cell $mux $ternary$libresoc.v:135600$5606
parameter \WIDTH 1
connect \A \gpio_s4__core__oe
connect \B \io_bd [41]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137470$5680_Y
+ connect \Y $ternary$libresoc.v:135600$5606_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137471$5681
+ cell $mux $ternary$libresoc.v:135601$5607
parameter \WIDTH 1
connect \A \gpio_s5__pad__i
connect \B \io_bd [42]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137471$5681_Y
+ connect \Y $ternary$libresoc.v:135601$5607_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137472$5682
+ cell $mux $ternary$libresoc.v:135602$5608
parameter \WIDTH 1
connect \A \gpio_s5__core__o
connect \B \io_bd [43]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137472$5682_Y
+ connect \Y $ternary$libresoc.v:135602$5608_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137474$5684
+ cell $mux $ternary$libresoc.v:135604$5610
parameter \WIDTH 1
connect \A \gpio_s5__core__oe
connect \B \io_bd [44]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137474$5684_Y
+ connect \Y $ternary$libresoc.v:135604$5610_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137475$5685
+ cell $mux $ternary$libresoc.v:135605$5611
parameter \WIDTH 1
connect \A \gpio_s6__pad__i
connect \B \io_bd [45]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137475$5685_Y
+ connect \Y $ternary$libresoc.v:135605$5611_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137476$5686
+ cell $mux $ternary$libresoc.v:135606$5612
parameter \WIDTH 1
connect \A \gpio_s6__core__o
connect \B \io_bd [46]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137476$5686_Y
+ connect \Y $ternary$libresoc.v:135606$5612_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137477$5687
+ cell $mux $ternary$libresoc.v:135607$5613
parameter \WIDTH 1
connect \A \gpio_s6__core__oe
connect \B \io_bd [47]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137477$5687_Y
+ connect \Y $ternary$libresoc.v:135607$5613_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137478$5688
+ cell $mux $ternary$libresoc.v:135608$5614
parameter \WIDTH 1
connect \A \gpio_s7__pad__i
connect \B \io_bd [48]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137478$5688_Y
+ connect \Y $ternary$libresoc.v:135608$5614_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137479$5689
+ cell $mux $ternary$libresoc.v:135609$5615
parameter \WIDTH 1
connect \A \gpio_s7__core__o
connect \B \io_bd [49]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137479$5689_Y
+ connect \Y $ternary$libresoc.v:135609$5615_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137480$5690
+ cell $mux $ternary$libresoc.v:135610$5616
parameter \WIDTH 1
connect \A \gpio_s7__core__oe
connect \B \io_bd [50]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137480$5690_Y
+ connect \Y $ternary$libresoc.v:135610$5616_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137481$5691
+ cell $mux $ternary$libresoc.v:135611$5617
parameter \WIDTH 1
connect \A \mspi0_clk__core__o
connect \B \io_bd [51]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137481$5691_Y
+ connect \Y $ternary$libresoc.v:135611$5617_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137482$5692
+ cell $mux $ternary$libresoc.v:135612$5618
parameter \WIDTH 1
connect \A \mspi0_cs_n__core__o
connect \B \io_bd [52]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137482$5692_Y
+ connect \Y $ternary$libresoc.v:135612$5618_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137483$5693
+ cell $mux $ternary$libresoc.v:135613$5619
parameter \WIDTH 1
connect \A \mspi0_mosi__core__o
connect \B \io_bd [53]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137483$5693_Y
+ connect \Y $ternary$libresoc.v:135613$5619_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:137485$5695
+ cell $mux $ternary$libresoc.v:135615$5621
parameter \WIDTH 1
connect \A \mspi0_miso__pad__i
connect \B \io_bd [54]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137485$5695_Y
+ connect \Y $ternary$libresoc.v:135615$5621_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137486$5696
+ cell $mux $ternary$libresoc.v:135616$5622
parameter \WIDTH 1
connect \A \mspi1_clk__core__o
connect \B \io_bd [55]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137486$5696_Y
+ connect \Y $ternary$libresoc.v:135616$5622_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137487$5697
+ cell $mux $ternary$libresoc.v:135617$5623
parameter \WIDTH 1
connect \A \mspi1_cs_n__core__o
connect \B \io_bd [56]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137487$5697_Y
+ connect \Y $ternary$libresoc.v:135617$5623_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137488$5698
+ cell $mux $ternary$libresoc.v:135618$5624
parameter \WIDTH 1
connect \A \mspi1_mosi__core__o
connect \B \io_bd [57]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137488$5698_Y
+ connect \Y $ternary$libresoc.v:135618$5624_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:137489$5699
+ cell $mux $ternary$libresoc.v:135619$5625
parameter \WIDTH 1
connect \A \mspi1_miso__pad__i
connect \B \io_bd [58]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137489$5699_Y
+ connect \Y $ternary$libresoc.v:135619$5625_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137490$5700
+ cell $mux $ternary$libresoc.v:135620$5626
parameter \WIDTH 1
connect \A \mtwi_sda__pad__i
connect \B \io_bd [59]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137490$5700_Y
+ connect \Y $ternary$libresoc.v:135620$5626_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137491$5701
+ cell $mux $ternary$libresoc.v:135621$5627
parameter \WIDTH 1
connect \A \mtwi_sda__core__o
connect \B \io_bd [60]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137491$5701_Y
+ connect \Y $ternary$libresoc.v:135621$5627_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137492$5702
+ cell $mux $ternary$libresoc.v:135622$5628
parameter \WIDTH 1
connect \A \mtwi_sda__core__oe
connect \B \io_bd [61]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137492$5702_Y
+ connect \Y $ternary$libresoc.v:135622$5628_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137493$5703
+ cell $mux $ternary$libresoc.v:135623$5629
parameter \WIDTH 1
connect \A \mtwi_scl__core__o
connect \B \io_bd [62]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137493$5703_Y
+ connect \Y $ternary$libresoc.v:135623$5629_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137494$5704
+ cell $mux $ternary$libresoc.v:135624$5630
parameter \WIDTH 1
connect \A \pwm_0__core__o
connect \B \io_bd [63]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137494$5704_Y
+ connect \Y $ternary$libresoc.v:135624$5630_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137496$5706
+ cell $mux $ternary$libresoc.v:135626$5632
parameter \WIDTH 1
connect \A \pwm_1__core__o
connect \B \io_bd [64]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137496$5706_Y
+ connect \Y $ternary$libresoc.v:135626$5632_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137497$5707
+ cell $mux $ternary$libresoc.v:135627$5633
parameter \WIDTH 1
connect \A \sd0_cmd__pad__i
connect \B \io_bd [65]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137497$5707_Y
+ connect \Y $ternary$libresoc.v:135627$5633_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137498$5708
+ cell $mux $ternary$libresoc.v:135628$5634
parameter \WIDTH 1
connect \A \sd0_cmd__core__o
connect \B \io_bd [66]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137498$5708_Y
+ connect \Y $ternary$libresoc.v:135628$5634_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137499$5709
+ cell $mux $ternary$libresoc.v:135629$5635
parameter \WIDTH 1
connect \A \sd0_cmd__core__oe
connect \B \io_bd [67]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137499$5709_Y
+ connect \Y $ternary$libresoc.v:135629$5635_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137500$5710
+ cell $mux $ternary$libresoc.v:135630$5636
parameter \WIDTH 1
connect \A \sd0_clk__core__o
connect \B \io_bd [68]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137500$5710_Y
+ connect \Y $ternary$libresoc.v:135630$5636_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137501$5711
+ cell $mux $ternary$libresoc.v:135631$5637
parameter \WIDTH 1
connect \A \sd0_data0__pad__i
connect \B \io_bd [69]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137501$5711_Y
+ connect \Y $ternary$libresoc.v:135631$5637_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137502$5712
+ cell $mux $ternary$libresoc.v:135632$5638
parameter \WIDTH 1
connect \A \sd0_data0__core__o
connect \B \io_bd [70]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137502$5712_Y
+ connect \Y $ternary$libresoc.v:135632$5638_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137503$5713
+ cell $mux $ternary$libresoc.v:135633$5639
parameter \WIDTH 1
connect \A \sd0_data0__core__oe
connect \B \io_bd [71]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137503$5713_Y
+ connect \Y $ternary$libresoc.v:135633$5639_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137504$5714
+ cell $mux $ternary$libresoc.v:135634$5640
parameter \WIDTH 1
connect \A \sd0_data1__pad__i
connect \B \io_bd [72]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137504$5714_Y
+ connect \Y $ternary$libresoc.v:135634$5640_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137505$5715
+ cell $mux $ternary$libresoc.v:135635$5641
parameter \WIDTH 1
connect \A \sd0_data1__core__o
connect \B \io_bd [73]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137505$5715_Y
+ connect \Y $ternary$libresoc.v:135635$5641_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137508$5718
+ cell $mux $ternary$libresoc.v:135638$5644
parameter \WIDTH 1
connect \A \sd0_data1__core__oe
connect \B \io_bd [74]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137508$5718_Y
+ connect \Y $ternary$libresoc.v:135638$5644_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137509$5719
+ cell $mux $ternary$libresoc.v:135639$5645
parameter \WIDTH 1
connect \A \sd0_data2__pad__i
connect \B \io_bd [75]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137509$5719_Y
+ connect \Y $ternary$libresoc.v:135639$5645_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137510$5720
+ cell $mux $ternary$libresoc.v:135640$5646
parameter \WIDTH 1
connect \A \sd0_data2__core__o
connect \B \io_bd [76]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137510$5720_Y
+ connect \Y $ternary$libresoc.v:135640$5646_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137511$5721
+ cell $mux $ternary$libresoc.v:135641$5647
parameter \WIDTH 1
connect \A \sd0_data2__core__oe
connect \B \io_bd [77]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137511$5721_Y
+ connect \Y $ternary$libresoc.v:135641$5647_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137512$5722
+ cell $mux $ternary$libresoc.v:135642$5648
parameter \WIDTH 1
connect \A \sd0_data3__pad__i
connect \B \io_bd [78]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137512$5722_Y
+ connect \Y $ternary$libresoc.v:135642$5648_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137513$5723
+ cell $mux $ternary$libresoc.v:135643$5649
parameter \WIDTH 1
connect \A \sd0_data3__core__o
connect \B \io_bd [79]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137513$5723_Y
+ connect \Y $ternary$libresoc.v:135643$5649_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137514$5724
+ cell $mux $ternary$libresoc.v:135644$5650
parameter \WIDTH 1
connect \A \sd0_data3__core__oe
connect \B \io_bd [80]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137514$5724_Y
+ connect \Y $ternary$libresoc.v:135644$5650_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137515$5725
+ cell $mux $ternary$libresoc.v:135645$5651
parameter \WIDTH 1
connect \A \sdr_dm_0__core__o
connect \B \io_bd [81]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137515$5725_Y
+ connect \Y $ternary$libresoc.v:135645$5651_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137516$5726
+ cell $mux $ternary$libresoc.v:135646$5652
parameter \WIDTH 1
connect \A \sdr_dq_0__pad__i
connect \B \io_bd [82]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137516$5726_Y
+ connect \Y $ternary$libresoc.v:135646$5652_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137517$5727
+ cell $mux $ternary$libresoc.v:135647$5653
parameter \WIDTH 1
connect \A \sdr_dq_0__core__o
connect \B \io_bd [83]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137517$5727_Y
+ connect \Y $ternary$libresoc.v:135647$5653_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137519$5729
+ cell $mux $ternary$libresoc.v:135649$5655
parameter \WIDTH 1
connect \A \sdr_dq_0__core__oe
connect \B \io_bd [84]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137519$5729_Y
+ connect \Y $ternary$libresoc.v:135649$5655_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137520$5730
+ cell $mux $ternary$libresoc.v:135650$5656
parameter \WIDTH 1
connect \A \sdr_dq_1__pad__i
connect \B \io_bd [85]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137520$5730_Y
+ connect \Y $ternary$libresoc.v:135650$5656_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137521$5731
+ cell $mux $ternary$libresoc.v:135651$5657
parameter \WIDTH 1
connect \A \sdr_dq_1__core__o
connect \B \io_bd [86]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137521$5731_Y
+ connect \Y $ternary$libresoc.v:135651$5657_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137522$5732
+ cell $mux $ternary$libresoc.v:135652$5658
parameter \WIDTH 1
connect \A \sdr_dq_1__core__oe
connect \B \io_bd [87]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137522$5732_Y
+ connect \Y $ternary$libresoc.v:135652$5658_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137523$5733
+ cell $mux $ternary$libresoc.v:135653$5659
parameter \WIDTH 1
connect \A \sdr_dq_2__pad__i
connect \B \io_bd [88]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137523$5733_Y
+ connect \Y $ternary$libresoc.v:135653$5659_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137524$5734
+ cell $mux $ternary$libresoc.v:135654$5660
parameter \WIDTH 1
connect \A \sdr_dq_2__core__o
connect \B \io_bd [89]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137524$5734_Y
+ connect \Y $ternary$libresoc.v:135654$5660_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137525$5735
+ cell $mux $ternary$libresoc.v:135655$5661
parameter \WIDTH 1
connect \A \sdr_dq_2__core__oe
connect \B \io_bd [90]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137525$5735_Y
+ connect \Y $ternary$libresoc.v:135655$5661_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137526$5736
+ cell $mux $ternary$libresoc.v:135656$5662
parameter \WIDTH 1
connect \A \sdr_dq_3__pad__i
connect \B \io_bd [91]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137526$5736_Y
+ connect \Y $ternary$libresoc.v:135656$5662_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137527$5737
+ cell $mux $ternary$libresoc.v:135657$5663
parameter \WIDTH 1
connect \A \sdr_dq_3__core__o
connect \B \io_bd [92]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137527$5737_Y
+ connect \Y $ternary$libresoc.v:135657$5663_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137528$5738
+ cell $mux $ternary$libresoc.v:135658$5664
parameter \WIDTH 1
connect \A \sdr_dq_3__core__oe
connect \B \io_bd [93]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137528$5738_Y
+ connect \Y $ternary$libresoc.v:135658$5664_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137530$5740
+ cell $mux $ternary$libresoc.v:135660$5666
parameter \WIDTH 1
connect \A \sdr_dq_4__pad__i
connect \B \io_bd [94]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137530$5740_Y
+ connect \Y $ternary$libresoc.v:135660$5666_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137531$5741
+ cell $mux $ternary$libresoc.v:135661$5667
parameter \WIDTH 1
connect \A \sdr_dq_4__core__o
connect \B \io_bd [95]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137531$5741_Y
+ connect \Y $ternary$libresoc.v:135661$5667_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137532$5742
+ cell $mux $ternary$libresoc.v:135662$5668
parameter \WIDTH 1
connect \A \sdr_dq_4__core__oe
connect \B \io_bd [96]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137532$5742_Y
+ connect \Y $ternary$libresoc.v:135662$5668_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137533$5743
+ cell $mux $ternary$libresoc.v:135663$5669
parameter \WIDTH 1
connect \A \sdr_dq_5__pad__i
connect \B \io_bd [97]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137533$5743_Y
+ connect \Y $ternary$libresoc.v:135663$5669_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137534$5744
+ cell $mux $ternary$libresoc.v:135664$5670
parameter \WIDTH 1
connect \A \sdr_dq_5__core__o
connect \B \io_bd [98]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137534$5744_Y
+ connect \Y $ternary$libresoc.v:135664$5670_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137535$5745
+ cell $mux $ternary$libresoc.v:135665$5671
parameter \WIDTH 1
connect \A \sdr_dq_5__core__oe
connect \B \io_bd [99]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137535$5745_Y
+ connect \Y $ternary$libresoc.v:135665$5671_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137536$5746
+ cell $mux $ternary$libresoc.v:135666$5672
parameter \WIDTH 1
connect \A \sdr_dq_6__pad__i
connect \B \io_bd [100]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137536$5746_Y
+ connect \Y $ternary$libresoc.v:135666$5672_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137537$5747
+ cell $mux $ternary$libresoc.v:135667$5673
parameter \WIDTH 1
connect \A \sdr_dq_6__core__o
connect \B \io_bd [101]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137537$5747_Y
+ connect \Y $ternary$libresoc.v:135667$5673_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137538$5748
+ cell $mux $ternary$libresoc.v:135668$5674
parameter \WIDTH 1
connect \A \sdr_dq_6__core__oe
connect \B \io_bd [102]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137538$5748_Y
+ connect \Y $ternary$libresoc.v:135668$5674_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137539$5749
+ cell $mux $ternary$libresoc.v:135669$5675
parameter \WIDTH 1
connect \A \sdr_dq_7__pad__i
connect \B \io_bd [103]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137539$5749_Y
+ connect \Y $ternary$libresoc.v:135669$5675_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137541$5751
+ cell $mux $ternary$libresoc.v:135671$5677
parameter \WIDTH 1
connect \A \sdr_dq_7__core__o
connect \B \io_bd [104]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137541$5751_Y
+ connect \Y $ternary$libresoc.v:135671$5677_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137542$5752
+ cell $mux $ternary$libresoc.v:135672$5678
parameter \WIDTH 1
connect \A \sdr_dq_7__core__oe
connect \B \io_bd [105]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137542$5752_Y
+ connect \Y $ternary$libresoc.v:135672$5678_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137543$5753
+ cell $mux $ternary$libresoc.v:135673$5679
parameter \WIDTH 1
connect \A \sdr_a_0__core__o
connect \B \io_bd [106]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137543$5753_Y
+ connect \Y $ternary$libresoc.v:135673$5679_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137544$5754
+ cell $mux $ternary$libresoc.v:135674$5680
parameter \WIDTH 1
connect \A \sdr_a_1__core__o
connect \B \io_bd [107]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137544$5754_Y
+ connect \Y $ternary$libresoc.v:135674$5680_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137545$5755
+ cell $mux $ternary$libresoc.v:135675$5681
parameter \WIDTH 1
connect \A \sdr_a_2__core__o
connect \B \io_bd [108]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137545$5755_Y
+ connect \Y $ternary$libresoc.v:135675$5681_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137546$5756
+ cell $mux $ternary$libresoc.v:135676$5682
parameter \WIDTH 1
connect \A \sdr_a_3__core__o
connect \B \io_bd [109]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137546$5756_Y
+ connect \Y $ternary$libresoc.v:135676$5682_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137547$5757
+ cell $mux $ternary$libresoc.v:135677$5683
parameter \WIDTH 1
connect \A \sdr_a_4__core__o
connect \B \io_bd [110]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137547$5757_Y
+ connect \Y $ternary$libresoc.v:135677$5683_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137548$5758
+ cell $mux $ternary$libresoc.v:135678$5684
parameter \WIDTH 1
connect \A \sdr_a_5__core__o
connect \B \io_bd [111]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137548$5758_Y
+ connect \Y $ternary$libresoc.v:135678$5684_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137549$5759
+ cell $mux $ternary$libresoc.v:135679$5685
parameter \WIDTH 1
connect \A \sdr_a_6__core__o
connect \B \io_bd [112]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137549$5759_Y
+ connect \Y $ternary$libresoc.v:135679$5685_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137550$5760
+ cell $mux $ternary$libresoc.v:135680$5686
parameter \WIDTH 1
connect \A \sdr_a_7__core__o
connect \B \io_bd [113]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137550$5760_Y
+ connect \Y $ternary$libresoc.v:135680$5686_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137552$5762
+ cell $mux $ternary$libresoc.v:135682$5688
parameter \WIDTH 1
connect \A \sdr_a_8__core__o
connect \B \io_bd [114]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137552$5762_Y
+ connect \Y $ternary$libresoc.v:135682$5688_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137553$5763
+ cell $mux $ternary$libresoc.v:135683$5689
parameter \WIDTH 1
connect \A \sdr_a_9__core__o
connect \B \io_bd [115]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137553$5763_Y
+ connect \Y $ternary$libresoc.v:135683$5689_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137554$5764
+ cell $mux $ternary$libresoc.v:135684$5690
parameter \WIDTH 1
connect \A \sdr_ba_0__core__o
connect \B \io_bd [116]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137554$5764_Y
+ connect \Y $ternary$libresoc.v:135684$5690_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137555$5765
+ cell $mux $ternary$libresoc.v:135685$5691
parameter \WIDTH 1
connect \A \sdr_ba_1__core__o
connect \B \io_bd [117]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137555$5765_Y
+ connect \Y $ternary$libresoc.v:135685$5691_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137556$5766
+ cell $mux $ternary$libresoc.v:135686$5692
parameter \WIDTH 1
connect \A \sdr_clock__core__o
connect \B \io_bd [118]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137556$5766_Y
+ connect \Y $ternary$libresoc.v:135686$5692_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137557$5767
+ cell $mux $ternary$libresoc.v:135687$5693
parameter \WIDTH 1
connect \A \sdr_cke__core__o
connect \B \io_bd [119]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137557$5767_Y
+ connect \Y $ternary$libresoc.v:135687$5693_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137558$5768
+ cell $mux $ternary$libresoc.v:135688$5694
parameter \WIDTH 1
connect \A \sdr_ras_n__core__o
connect \B \io_bd [120]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137558$5768_Y
+ connect \Y $ternary$libresoc.v:135688$5694_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137559$5769
+ cell $mux $ternary$libresoc.v:135689$5695
parameter \WIDTH 1
connect \A \sdr_cas_n__core__o
connect \B \io_bd [121]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137559$5769_Y
+ connect \Y $ternary$libresoc.v:135689$5695_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137560$5770
+ cell $mux $ternary$libresoc.v:135690$5696
parameter \WIDTH 1
connect \A \sdr_we_n__core__o
connect \B \io_bd [122]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137560$5770_Y
+ connect \Y $ternary$libresoc.v:135690$5696_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137561$5771
+ cell $mux $ternary$libresoc.v:135691$5697
parameter \WIDTH 1
connect \A \sdr_cs_n__core__o
connect \B \io_bd [123]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137561$5771_Y
+ connect \Y $ternary$libresoc.v:135691$5697_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137563$5773
+ cell $mux $ternary$libresoc.v:135693$5699
parameter \WIDTH 1
connect \A \sdr_a_10__core__o
connect \B \io_bd [124]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137563$5773_Y
+ connect \Y $ternary$libresoc.v:135693$5699_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137564$5774
+ cell $mux $ternary$libresoc.v:135694$5700
parameter \WIDTH 1
connect \A \sdr_a_11__core__o
connect \B \io_bd [125]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137564$5774_Y
+ connect \Y $ternary$libresoc.v:135694$5700_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
- cell $mux $ternary$libresoc.v:137565$5775
+ cell $mux $ternary$libresoc.v:135695$5701
parameter \WIDTH 1
connect \A \sdr_a_12__core__o
connect \B \io_bd [126]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137565$5775_Y
+ connect \Y $ternary$libresoc.v:135695$5701_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137566$5776
+ cell $mux $ternary$libresoc.v:135696$5702
parameter \WIDTH 1
connect \A \sdr_dm_1__pad__i
connect \B \io_bd [127]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137566$5776_Y
+ connect \Y $ternary$libresoc.v:135696$5702_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137567$5777
+ cell $mux $ternary$libresoc.v:135697$5703
parameter \WIDTH 1
connect \A \sdr_dm_1__core__o
connect \B \io_bd [128]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137567$5777_Y
+ connect \Y $ternary$libresoc.v:135697$5703_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137568$5778
+ cell $mux $ternary$libresoc.v:135698$5704
parameter \WIDTH 1
connect \A \sdr_dm_1__core__oe
connect \B \io_bd [129]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137568$5778_Y
+ connect \Y $ternary$libresoc.v:135698$5704_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137569$5779
+ cell $mux $ternary$libresoc.v:135699$5705
parameter \WIDTH 1
connect \A \sdr_dq_8__pad__i
connect \B \io_bd [130]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137569$5779_Y
+ connect \Y $ternary$libresoc.v:135699$5705_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137570$5780
+ cell $mux $ternary$libresoc.v:135700$5706
parameter \WIDTH 1
connect \A \sdr_dq_8__core__o
connect \B \io_bd [131]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137570$5780_Y
+ connect \Y $ternary$libresoc.v:135700$5706_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137571$5781
+ cell $mux $ternary$libresoc.v:135701$5707
parameter \WIDTH 1
connect \A \sdr_dq_8__core__oe
connect \B \io_bd [132]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137571$5781_Y
+ connect \Y $ternary$libresoc.v:135701$5707_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137572$5782
+ cell $mux $ternary$libresoc.v:135702$5708
parameter \WIDTH 1
connect \A \sdr_dq_9__pad__i
connect \B \io_bd [133]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137572$5782_Y
+ connect \Y $ternary$libresoc.v:135702$5708_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137574$5784
+ cell $mux $ternary$libresoc.v:135704$5710
parameter \WIDTH 1
connect \A \sdr_dq_9__core__o
connect \B \io_bd [134]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137574$5784_Y
+ connect \Y $ternary$libresoc.v:135704$5710_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137575$5785
+ cell $mux $ternary$libresoc.v:135705$5711
parameter \WIDTH 1
connect \A \sdr_dq_9__core__oe
connect \B \io_bd [135]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137575$5785_Y
+ connect \Y $ternary$libresoc.v:135705$5711_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137576$5786
+ cell $mux $ternary$libresoc.v:135706$5712
parameter \WIDTH 1
connect \A \sdr_dq_10__pad__i
connect \B \io_bd [136]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137576$5786_Y
+ connect \Y $ternary$libresoc.v:135706$5712_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137577$5787
+ cell $mux $ternary$libresoc.v:135707$5713
parameter \WIDTH 1
connect \A \sdr_dq_10__core__o
connect \B \io_bd [137]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137577$5787_Y
+ connect \Y $ternary$libresoc.v:135707$5713_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137578$5788
+ cell $mux $ternary$libresoc.v:135708$5714
parameter \WIDTH 1
connect \A \sdr_dq_10__core__oe
connect \B \io_bd [138]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137578$5788_Y
+ connect \Y $ternary$libresoc.v:135708$5714_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137579$5789
+ cell $mux $ternary$libresoc.v:135709$5715
parameter \WIDTH 1
connect \A \sdr_dq_11__pad__i
connect \B \io_bd [139]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137579$5789_Y
+ connect \Y $ternary$libresoc.v:135709$5715_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137580$5790
+ cell $mux $ternary$libresoc.v:135710$5716
parameter \WIDTH 1
connect \A \sdr_dq_11__core__o
connect \B \io_bd [140]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137580$5790_Y
+ connect \Y $ternary$libresoc.v:135710$5716_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137581$5791
+ cell $mux $ternary$libresoc.v:135711$5717
parameter \WIDTH 1
connect \A \sdr_dq_11__core__oe
connect \B \io_bd [141]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137581$5791_Y
+ connect \Y $ternary$libresoc.v:135711$5717_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137582$5792
+ cell $mux $ternary$libresoc.v:135712$5718
parameter \WIDTH 1
connect \A \sdr_dq_12__pad__i
connect \B \io_bd [142]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137582$5792_Y
+ connect \Y $ternary$libresoc.v:135712$5718_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137583$5793
+ cell $mux $ternary$libresoc.v:135713$5719
parameter \WIDTH 1
connect \A \sdr_dq_12__core__o
connect \B \io_bd [143]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137583$5793_Y
+ connect \Y $ternary$libresoc.v:135713$5719_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137585$5795
+ cell $mux $ternary$libresoc.v:135715$5721
parameter \WIDTH 1
connect \A \sdr_dq_12__core__oe
connect \B \io_bd [144]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137585$5795_Y
+ connect \Y $ternary$libresoc.v:135715$5721_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137586$5796
+ cell $mux $ternary$libresoc.v:135716$5722
parameter \WIDTH 1
connect \A \sdr_dq_13__pad__i
connect \B \io_bd [145]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137586$5796_Y
+ connect \Y $ternary$libresoc.v:135716$5722_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137587$5797
+ cell $mux $ternary$libresoc.v:135717$5723
parameter \WIDTH 1
connect \A \sdr_dq_13__core__o
connect \B \io_bd [146]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137587$5797_Y
+ connect \Y $ternary$libresoc.v:135717$5723_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137588$5798
+ cell $mux $ternary$libresoc.v:135718$5724
parameter \WIDTH 1
connect \A \sdr_dq_13__core__oe
connect \B \io_bd [147]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137588$5798_Y
+ connect \Y $ternary$libresoc.v:135718$5724_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137589$5799
+ cell $mux $ternary$libresoc.v:135719$5725
parameter \WIDTH 1
connect \A \sdr_dq_14__pad__i
connect \B \io_bd [148]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137589$5799_Y
+ connect \Y $ternary$libresoc.v:135719$5725_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137590$5800
+ cell $mux $ternary$libresoc.v:135720$5726
parameter \WIDTH 1
connect \A \sdr_dq_14__core__o
connect \B \io_bd [149]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137590$5800_Y
+ connect \Y $ternary$libresoc.v:135720$5726_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137591$5801
+ cell $mux $ternary$libresoc.v:135721$5727
parameter \WIDTH 1
connect \A \sdr_dq_14__core__oe
connect \B \io_bd [150]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137591$5801_Y
+ connect \Y $ternary$libresoc.v:135721$5727_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137592$5802
+ cell $mux $ternary$libresoc.v:135722$5728
parameter \WIDTH 1
connect \A \sdr_dq_15__pad__i
connect \B \io_bd [151]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137592$5802_Y
+ connect \Y $ternary$libresoc.v:135722$5728_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137593$5803
+ cell $mux $ternary$libresoc.v:135723$5729
parameter \WIDTH 1
connect \A \sdr_dq_15__core__o
connect \B \io_bd [152]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137593$5803_Y
+ connect \Y $ternary$libresoc.v:135723$5729_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137594$5804
+ cell $mux $ternary$libresoc.v:135724$5730
parameter \WIDTH 1
connect \A \sdr_dq_15__core__oe
connect \B \io_bd [153]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137594$5804_Y
+ connect \Y $ternary$libresoc.v:135724$5730_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:137681$5892
+ cell $mux $ternary$libresoc.v:135811$5818
parameter \WIDTH 1
connect \A \eint_0__pad__i
connect \B \io_bd [0]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137681$5892_Y
+ connect \Y $ternary$libresoc.v:135811$5818_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:137682$5893
+ cell $mux $ternary$libresoc.v:135812$5819
parameter \WIDTH 1
connect \A \eint_1__pad__i
connect \B \io_bd [1]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137682$5893_Y
+ connect \Y $ternary$libresoc.v:135812$5819_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
- cell $mux $ternary$libresoc.v:137683$5894
+ cell $mux $ternary$libresoc.v:135813$5820
parameter \WIDTH 1
connect \A \eint_2__pad__i
connect \B \io_bd [2]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137683$5894_Y
+ connect \Y $ternary$libresoc.v:135813$5820_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137684$5895
+ cell $mux $ternary$libresoc.v:135814$5821
parameter \WIDTH 1
connect \A \gpio_e8__pad__i
connect \B \io_bd [3]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137684$5895_Y
+ connect \Y $ternary$libresoc.v:135814$5821_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137686$5897
+ cell $mux $ternary$libresoc.v:135816$5823
parameter \WIDTH 1
connect \A \gpio_e8__core__o
connect \B \io_bd [4]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137686$5897_Y
+ connect \Y $ternary$libresoc.v:135816$5823_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137687$5898
+ cell $mux $ternary$libresoc.v:135817$5824
parameter \WIDTH 1
connect \A \gpio_e8__core__oe
connect \B \io_bd [5]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137687$5898_Y
+ connect \Y $ternary$libresoc.v:135817$5824_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137688$5899
+ cell $mux $ternary$libresoc.v:135818$5825
parameter \WIDTH 1
connect \A \gpio_e9__pad__i
connect \B \io_bd [6]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137688$5899_Y
+ connect \Y $ternary$libresoc.v:135818$5825_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137689$5900
+ cell $mux $ternary$libresoc.v:135819$5826
parameter \WIDTH 1
connect \A \gpio_e9__core__o
connect \B \io_bd [7]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137689$5900_Y
+ connect \Y $ternary$libresoc.v:135819$5826_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137690$5901
+ cell $mux $ternary$libresoc.v:135820$5827
parameter \WIDTH 1
connect \A \gpio_e9__core__oe
connect \B \io_bd [8]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137690$5901_Y
+ connect \Y $ternary$libresoc.v:135820$5827_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137691$5902
+ cell $mux $ternary$libresoc.v:135821$5828
parameter \WIDTH 1
connect \A \gpio_e10__pad__i
connect \B \io_bd [9]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137691$5902_Y
+ connect \Y $ternary$libresoc.v:135821$5828_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137692$5903
+ cell $mux $ternary$libresoc.v:135822$5829
parameter \WIDTH 1
connect \A \gpio_e10__core__o
connect \B \io_bd [10]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137692$5903_Y
+ connect \Y $ternary$libresoc.v:135822$5829_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137693$5904
+ cell $mux $ternary$libresoc.v:135823$5830
parameter \WIDTH 1
connect \A \gpio_e10__core__oe
connect \B \io_bd [11]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137693$5904_Y
+ connect \Y $ternary$libresoc.v:135823$5830_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137694$5905
+ cell $mux $ternary$libresoc.v:135824$5831
parameter \WIDTH 1
connect \A \gpio_e11__pad__i
connect \B \io_bd [12]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137694$5905_Y
+ connect \Y $ternary$libresoc.v:135824$5831_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137695$5906
+ cell $mux $ternary$libresoc.v:135825$5832
parameter \WIDTH 1
connect \A \gpio_e11__core__o
connect \B \io_bd [13]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137695$5906_Y
+ connect \Y $ternary$libresoc.v:135825$5832_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137697$5908
+ cell $mux $ternary$libresoc.v:135827$5834
parameter \WIDTH 1
connect \A \gpio_e11__core__oe
connect \B \io_bd [14]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137697$5908_Y
+ connect \Y $ternary$libresoc.v:135827$5834_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137698$5909
+ cell $mux $ternary$libresoc.v:135828$5835
parameter \WIDTH 1
connect \A \gpio_e12__pad__i
connect \B \io_bd [15]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137698$5909_Y
+ connect \Y $ternary$libresoc.v:135828$5835_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137699$5910
+ cell $mux $ternary$libresoc.v:135829$5836
parameter \WIDTH 1
connect \A \gpio_e12__core__o
connect \B \io_bd [16]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137699$5910_Y
+ connect \Y $ternary$libresoc.v:135829$5836_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137700$5911
+ cell $mux $ternary$libresoc.v:135830$5837
parameter \WIDTH 1
connect \A \gpio_e12__core__oe
connect \B \io_bd [17]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137700$5911_Y
+ connect \Y $ternary$libresoc.v:135830$5837_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137701$5912
+ cell $mux $ternary$libresoc.v:135831$5838
parameter \WIDTH 1
connect \A \gpio_e13__pad__i
connect \B \io_bd [18]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137701$5912_Y
+ connect \Y $ternary$libresoc.v:135831$5838_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137702$5913
+ cell $mux $ternary$libresoc.v:135832$5839
parameter \WIDTH 1
connect \A \gpio_e13__core__o
connect \B \io_bd [19]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137702$5913_Y
+ connect \Y $ternary$libresoc.v:135832$5839_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137703$5914
+ cell $mux $ternary$libresoc.v:135833$5840
parameter \WIDTH 1
connect \A \gpio_e13__core__oe
connect \B \io_bd [20]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137703$5914_Y
+ connect \Y $ternary$libresoc.v:135833$5840_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
- cell $mux $ternary$libresoc.v:137704$5915
+ cell $mux $ternary$libresoc.v:135834$5841
parameter \WIDTH 1
connect \A \gpio_e14__pad__i
connect \B \io_bd [21]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:137704$5915_Y
+ connect \Y $ternary$libresoc.v:135834$5841_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
- cell $mux $ternary$libresoc.v:137705$5916
+ cell $mux $ternary$libresoc.v:135835$5842
parameter \WIDTH 1
connect \A \gpio_e14__core__o
connect \B \io_bd [22]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137705$5916_Y
+ connect \Y $ternary$libresoc.v:135835$5842_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
- cell $mux $ternary$libresoc.v:137706$5917
+ cell $mux $ternary$libresoc.v:135836$5843
parameter \WIDTH 1
connect \A \gpio_e14__core__oe
connect \B \io_bd [23]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:137706$5917_Y
+ connect \Y $ternary$libresoc.v:135836$5843_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:137781.8-137793.4"
+ attribute \src "libresoc.v:135911.8-135923.4"
cell \_fsm \_fsm
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tms \TAP_bus__tms
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:137794.12-137804.4"
+ attribute \src "libresoc.v:135924.12-135934.4"
cell \_idblock \_idblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \TAP_id_tdo \_idblock_TAP_id_tdo
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:137805.12-137815.4"
+ attribute \src "libresoc.v:135935.12-135945.4"
cell \_irblock \_irblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \capture \_fsm_capture
connect \tdo \_irblock_tdo
connect \update \_fsm_update
end
- attribute \src "libresoc.v:136016.7-136016.20"
- process $proc$libresoc.v:136016$6113
+ attribute \src "libresoc.v:134147.7-134147.20"
+ process $proc$libresoc.v:134147$6039
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:136574.13-136574.32"
- process $proc$libresoc.v:136574$6114
+ attribute \src "libresoc.v:134705.13-134705.32"
+ process $proc$libresoc.v:134705$6040
assign { } { }
assign $1\dmi0__addr_i[3:0] 4'0000
sync always
sync init
update \dmi0__addr_i $1\dmi0__addr_i[3:0]
end
- attribute \src "libresoc.v:136579.14-136579.46"
- process $proc$libresoc.v:136579$6115
+ attribute \src "libresoc.v:134710.14-134710.46"
+ process $proc$libresoc.v:134710$6041
assign { } { }
assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0__din $1\dmi0__din[63:0]
end
- attribute \src "libresoc.v:136593.7-136593.29"
- process $proc$libresoc.v:136593$6116
+ attribute \src "libresoc.v:134724.7-134724.29"
+ process $proc$libresoc.v:134724$6042
assign { } { }
assign $1\dmi0_addrsr__oe[0:0] 1'0
sync always
sync init
update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:136601.13-136601.36"
- process $proc$libresoc.v:136601$6117
+ attribute \src "libresoc.v:134732.13-134732.36"
+ process $proc$libresoc.v:134732$6043
assign { } { }
assign $1\dmi0_addrsr_reg[7:0] 8'00000000
sync always
sync init
update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:136609.7-136609.37"
- process $proc$libresoc.v:136609$6118
+ attribute \src "libresoc.v:134740.7-134740.37"
+ process $proc$libresoc.v:134740$6044
assign { } { }
assign $1\dmi0_addrsr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:136613.7-136613.42"
- process $proc$libresoc.v:136613$6119
+ attribute \src "libresoc.v:134744.7-134744.42"
+ process $proc$libresoc.v:134744$6045
assign { } { }
assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:136617.14-136617.51"
- process $proc$libresoc.v:136617$6120
+ attribute \src "libresoc.v:134748.14-134748.51"
+ process $proc$libresoc.v:134748$6046
assign { } { }
assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr__i $1\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:136623.13-136623.35"
- process $proc$libresoc.v:136623$6121
+ attribute \src "libresoc.v:134754.13-134754.35"
+ process $proc$libresoc.v:134754$6047
assign { } { }
assign $1\dmi0_datasr__oe[1:0] 2'00
sync always
sync init
update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:136631.14-136631.52"
- process $proc$libresoc.v:136631$6122
+ attribute \src "libresoc.v:134762.14-134762.52"
+ process $proc$libresoc.v:134762$6048
assign { } { }
assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:136639.7-136639.37"
- process $proc$libresoc.v:136639$6123
+ attribute \src "libresoc.v:134770.7-134770.37"
+ process $proc$libresoc.v:134770$6049
assign { } { }
assign $1\dmi0_datasr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:136643.7-136643.42"
- process $proc$libresoc.v:136643$6124
+ attribute \src "libresoc.v:134774.7-134774.42"
+ process $proc$libresoc.v:134774$6050
assign { } { }
assign $1\dmi0_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:136659.13-136659.29"
- process $proc$libresoc.v:136659$6125
+ attribute \src "libresoc.v:134790.13-134790.29"
+ process $proc$libresoc.v:134790$6051
assign { } { }
assign $1\fsm_state[2:0] 3'000
sync always
sync init
update \fsm_state $1\fsm_state[2:0]
end
- attribute \src "libresoc.v:136661.13-136661.35"
- process $proc$libresoc.v:136661$6126
+ attribute \src "libresoc.v:134792.13-134792.35"
+ process $proc$libresoc.v:134792$6052
assign { } { }
- assign $0\fsm_state$503[2:0]$6127 3'000
+ assign $0\fsm_state$503[2:0]$6053 3'000
sync always
sync init
- update \fsm_state$503 $0\fsm_state$503[2:0]$6127
+ update \fsm_state$503 $0\fsm_state$503[2:0]$6053
end
- attribute \src "libresoc.v:136859.15-136859.67"
- process $proc$libresoc.v:136859$6128
+ attribute \src "libresoc.v:134990.15-134990.67"
+ process $proc$libresoc.v:134990$6054
assign { } { }
assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \io_bd $1\io_bd[153:0]
end
- attribute \src "libresoc.v:136871.15-136871.67"
- process $proc$libresoc.v:136871$6129
+ attribute \src "libresoc.v:135002.15-135002.67"
+ process $proc$libresoc.v:135002$6055
assign { } { }
assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \io_sr $1\io_sr[153:0]
end
- attribute \src "libresoc.v:136880.14-136880.41"
- process $proc$libresoc.v:136880$6130
+ attribute \src "libresoc.v:135011.14-135011.41"
+ process $proc$libresoc.v:135011$6056
assign { } { }
assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb__adr $1\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:136889.14-136889.51"
- process $proc$libresoc.v:136889$6131
+ attribute \src "libresoc.v:135020.14-135020.51"
+ process $proc$libresoc.v:135020$6057
assign { } { }
assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:136903.7-136903.32"
- process $proc$libresoc.v:136903$6132
+ attribute \src "libresoc.v:135034.7-135034.32"
+ process $proc$libresoc.v:135034$6058
assign { } { }
assign $1\jtag_wb_addrsr__oe[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:136911.14-136911.47"
- process $proc$libresoc.v:136911$6133
+ attribute \src "libresoc.v:135042.14-135042.47"
+ process $proc$libresoc.v:135042$6059
assign { } { }
assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:136919.7-136919.40"
- process $proc$libresoc.v:136919$6134
+ attribute \src "libresoc.v:135050.7-135050.40"
+ process $proc$libresoc.v:135050$6060
assign { } { }
assign $1\jtag_wb_addrsr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:136923.7-136923.45"
- process $proc$libresoc.v:136923$6135
+ attribute \src "libresoc.v:135054.7-135054.45"
+ process $proc$libresoc.v:135054$6061
assign { } { }
assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:136927.14-136927.54"
- process $proc$libresoc.v:136927$6136
+ attribute \src "libresoc.v:135058.14-135058.54"
+ process $proc$libresoc.v:135058$6062
assign { } { }
assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:136933.13-136933.38"
- process $proc$libresoc.v:136933$6137
+ attribute \src "libresoc.v:135064.13-135064.38"
+ process $proc$libresoc.v:135064$6063
assign { } { }
assign $1\jtag_wb_datasr__oe[1:0] 2'00
sync always
sync init
update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:136941.14-136941.55"
- process $proc$libresoc.v:136941$6138
+ attribute \src "libresoc.v:135072.14-135072.55"
+ process $proc$libresoc.v:135072$6064
assign { } { }
assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:136949.7-136949.40"
- process $proc$libresoc.v:136949$6139
+ attribute \src "libresoc.v:135080.7-135080.40"
+ process $proc$libresoc.v:135080$6065
assign { } { }
assign $1\jtag_wb_datasr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:136953.7-136953.45"
- process $proc$libresoc.v:136953$6140
+ attribute \src "libresoc.v:135084.7-135084.45"
+ process $proc$libresoc.v:135084$6066
assign { } { }
assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137383.7-137383.21"
- process $proc$libresoc.v:137383$6141
+ attribute \src "libresoc.v:135514.7-135514.21"
+ process $proc$libresoc.v:135514$6067
assign { } { }
assign $1\sr0__oe[0:0] 1'0
sync always
sync init
update \sr0__oe $1\sr0__oe[0:0]
end
- attribute \src "libresoc.v:137391.13-137391.27"
- process $proc$libresoc.v:137391$6142
+ attribute \src "libresoc.v:135522.13-135522.27"
+ process $proc$libresoc.v:135522$6068
assign { } { }
assign $1\sr0_reg[2:0] 3'000
sync always
sync init
update \sr0_reg $1\sr0_reg[2:0]
end
- attribute \src "libresoc.v:137399.7-137399.29"
- process $proc$libresoc.v:137399$6143
+ attribute \src "libresoc.v:135530.7-135530.29"
+ process $proc$libresoc.v:135530$6069
assign { } { }
assign $1\sr0_update_core[0:0] 1'0
sync always
sync init
update \sr0_update_core $1\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:137403.7-137403.34"
- process $proc$libresoc.v:137403$6144
+ attribute \src "libresoc.v:135534.7-135534.34"
+ process $proc$libresoc.v:135534$6070
assign { } { }
assign $1\sr0_update_core_prev[0:0] 1'0
sync always
sync init
update \sr0_update_core_prev $1\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137413.7-137413.21"
- process $proc$libresoc.v:137413$6145
+ attribute \src "libresoc.v:135544.7-135544.21"
+ process $proc$libresoc.v:135544$6071
assign { } { }
assign $1\sr5__oe[0:0] 1'0
sync always
sync init
update \sr5__oe $1\sr5__oe[0:0]
end
- attribute \src "libresoc.v:137421.13-137421.27"
- process $proc$libresoc.v:137421$6146
+ attribute \src "libresoc.v:135552.13-135552.27"
+ process $proc$libresoc.v:135552$6072
assign { } { }
assign $1\sr5_reg[2:0] 3'000
sync always
sync init
update \sr5_reg $1\sr5_reg[2:0]
end
- attribute \src "libresoc.v:137429.7-137429.29"
- process $proc$libresoc.v:137429$6147
+ attribute \src "libresoc.v:135560.7-135560.29"
+ process $proc$libresoc.v:135560$6073
assign { } { }
assign $1\sr5_update_core[0:0] 1'0
sync always
sync init
update \sr5_update_core $1\sr5_update_core[0:0]
end
- attribute \src "libresoc.v:137433.7-137433.34"
- process $proc$libresoc.v:137433$6148
+ attribute \src "libresoc.v:135564.7-135564.34"
+ process $proc$libresoc.v:135564$6074
assign { } { }
assign $1\sr5_update_core_prev[0:0] 1'0
sync always
sync init
update \sr5_update_core_prev $1\sr5_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137438.7-137438.26"
- process $proc$libresoc.v:137438$6149
+ attribute \src "libresoc.v:135569.7-135569.26"
+ process $proc$libresoc.v:135569$6075
assign { } { }
assign $1\wb_dcache_en[0:0] 1'1
sync always
sync init
update \wb_dcache_en $1\wb_dcache_en[0:0]
end
- attribute \src "libresoc.v:137443.7-137443.26"
- process $proc$libresoc.v:137443$6150
+ attribute \src "libresoc.v:135574.7-135574.26"
+ process $proc$libresoc.v:135574$6076
assign { } { }
assign $1\wb_icache_en[0:0] 1'1
sync always
sync init
update \wb_icache_en $1\wb_icache_en[0:0]
end
- attribute \src "libresoc.v:137448.7-137448.24"
- process $proc$libresoc.v:137448$6151
+ attribute \src "libresoc.v:135578.7-135578.24"
+ process $proc$libresoc.v:135578$6077
assign { } { }
assign $1\wb_sram_en[0:0] 1'1
sync always
sync init
update \wb_sram_en $1\wb_sram_en[0:0]
end
- attribute \src "libresoc.v:137707.3-137708.41"
- process $proc$libresoc.v:137707$5918
+ attribute \src "libresoc.v:135837.3-135838.41"
+ process $proc$libresoc.v:135837$5844
assign { } { }
assign $0\wb_icache_en[0:0] \wb_icache_en$next
sync posedge \clk
update \wb_icache_en $0\wb_icache_en[0:0]
end
- attribute \src "libresoc.v:137709.3-137710.41"
- process $proc$libresoc.v:137709$5919
+ attribute \src "libresoc.v:135839.3-135840.41"
+ process $proc$libresoc.v:135839$5845
assign { } { }
assign $0\wb_dcache_en[0:0] \wb_dcache_en$next
sync posedge \clk
update \wb_dcache_en $0\wb_dcache_en[0:0]
end
- attribute \src "libresoc.v:137711.3-137712.37"
- process $proc$libresoc.v:137711$5920
+ attribute \src "libresoc.v:135841.3-135842.37"
+ process $proc$libresoc.v:135841$5846
assign { } { }
assign $0\wb_sram_en[0:0] \wb_sram_en$next
sync posedge \clk
update \wb_sram_en $0\wb_sram_en[0:0]
end
- attribute \src "libresoc.v:137713.3-137714.45"
- process $proc$libresoc.v:137713$5921
+ attribute \src "libresoc.v:135843.3-135844.45"
+ process $proc$libresoc.v:135843$5847
assign { } { }
assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next
sync posedge \clk
update \dmi0_datasr__i $0\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:137715.3-137716.35"
- process $proc$libresoc.v:137715$5922
+ attribute \src "libresoc.v:135845.3-135846.35"
+ process $proc$libresoc.v:135845$5848
assign { } { }
assign $0\dmi0__din[63:0] \dmi0__din$next
sync posedge \clk
update \dmi0__din $0\dmi0__din[63:0]
end
- attribute \src "libresoc.v:137717.3-137718.45"
- process $proc$libresoc.v:137717$5923
+ attribute \src "libresoc.v:135847.3-135848.45"
+ process $proc$libresoc.v:135847$5849
assign { } { }
- assign $0\fsm_state$503[2:0]$5924 \fsm_state$503$next
+ assign $0\fsm_state$503[2:0]$5850 \fsm_state$503$next
sync posedge \clk
- update \fsm_state$503 $0\fsm_state$503[2:0]$5924
+ update \fsm_state$503 $0\fsm_state$503[2:0]$5850
end
- attribute \src "libresoc.v:137719.3-137720.41"
- process $proc$libresoc.v:137719$5925
+ attribute \src "libresoc.v:135849.3-135850.41"
+ process $proc$libresoc.v:135849$5851
assign { } { }
assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next
sync posedge \clk
update \dmi0__addr_i $0\dmi0__addr_i[3:0]
end
- attribute \src "libresoc.v:137721.3-137722.51"
- process $proc$libresoc.v:137721$5926
+ attribute \src "libresoc.v:135851.3-135852.51"
+ process $proc$libresoc.v:135851$5852
assign { } { }
assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next
sync posedge \clk
update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:137723.3-137724.45"
- process $proc$libresoc.v:137723$5927
+ attribute \src "libresoc.v:135853.3-135854.45"
+ process $proc$libresoc.v:135853$5853
assign { } { }
assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next
sync posedge \clk
update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:137725.3-137726.35"
- process $proc$libresoc.v:137725$5928
+ attribute \src "libresoc.v:135855.3-135856.35"
+ process $proc$libresoc.v:135855$5854
assign { } { }
assign $0\fsm_state[2:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[2:0]
end
- attribute \src "libresoc.v:137727.3-137728.41"
- process $proc$libresoc.v:137727$5929
+ attribute \src "libresoc.v:135857.3-135858.41"
+ process $proc$libresoc.v:135857$5855
assign { } { }
assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next
sync posedge \clk
update \jtag_wb__adr $0\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:137729.3-137730.31"
- process $proc$libresoc.v:137729$5930
+ attribute \src "libresoc.v:135859.3-135860.31"
+ process $proc$libresoc.v:135859$5856
assign { } { }
assign $0\sr5_reg[2:0] \sr5_reg$next
sync posedge \posjtag_clk
update \sr5_reg $0\sr5_reg[2:0]
end
- attribute \src "libresoc.v:137731.3-137732.31"
- process $proc$libresoc.v:137731$5931
+ attribute \src "libresoc.v:135861.3-135862.31"
+ process $proc$libresoc.v:135861$5857
assign { } { }
assign $0\sr5__oe[0:0] \sr5__oe$next
sync posedge \clk
update \sr5__oe $0\sr5__oe[0:0]
end
- attribute \src "libresoc.v:137733.3-137734.57"
- process $proc$libresoc.v:137733$5932
+ attribute \src "libresoc.v:135863.3-135864.57"
+ process $proc$libresoc.v:135863$5858
assign { } { }
assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next
sync posedge \clk
update \sr5_update_core_prev $0\sr5_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137735.3-137736.47"
- process $proc$libresoc.v:137735$5933
+ attribute \src "libresoc.v:135865.3-135866.47"
+ process $proc$libresoc.v:135865$5859
assign { } { }
assign $0\sr5_update_core[0:0] \sr5_update_core$next
sync posedge \clk
update \sr5_update_core $0\sr5_update_core[0:0]
end
- attribute \src "libresoc.v:137737.3-137738.47"
- process $proc$libresoc.v:137737$5934
+ attribute \src "libresoc.v:135867.3-135868.47"
+ process $proc$libresoc.v:135867$5860
assign { } { }
assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next
sync posedge \posjtag_clk
update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:137739.3-137740.47"
- process $proc$libresoc.v:137739$5935
+ attribute \src "libresoc.v:135869.3-135870.47"
+ process $proc$libresoc.v:135869$5861
assign { } { }
assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next
sync posedge \clk
update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:137741.3-137742.73"
- process $proc$libresoc.v:137741$5936
+ attribute \src "libresoc.v:135871.3-135872.73"
+ process $proc$libresoc.v:135871$5862
assign { } { }
assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next
sync posedge \clk
update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137743.3-137744.63"
- process $proc$libresoc.v:137743$5937
+ attribute \src "libresoc.v:135873.3-135874.63"
+ process $proc$libresoc.v:135873$5863
assign { } { }
assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next
sync posedge \clk
update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:137745.3-137746.47"
- process $proc$libresoc.v:137745$5938
+ attribute \src "libresoc.v:135875.3-135876.47"
+ process $proc$libresoc.v:135875$5864
assign { } { }
assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next
sync posedge \posjtag_clk
update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:137747.3-137748.47"
- process $proc$libresoc.v:137747$5939
+ attribute \src "libresoc.v:135877.3-135878.47"
+ process $proc$libresoc.v:135877$5865
assign { } { }
assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next
sync posedge \clk
update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:137749.3-137750.73"
- process $proc$libresoc.v:137749$5940
+ attribute \src "libresoc.v:135879.3-135880.73"
+ process $proc$libresoc.v:135879$5866
assign { } { }
assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next
sync posedge \clk
update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137751.3-137752.63"
- process $proc$libresoc.v:137751$5941
+ attribute \src "libresoc.v:135881.3-135882.63"
+ process $proc$libresoc.v:135881$5867
assign { } { }
assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next
sync posedge \clk
update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:137753.3-137754.53"
- process $proc$libresoc.v:137753$5942
+ attribute \src "libresoc.v:135883.3-135884.53"
+ process $proc$libresoc.v:135883$5868
assign { } { }
assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:137755.3-137756.53"
- process $proc$libresoc.v:137755$5943
+ attribute \src "libresoc.v:135885.3-135886.53"
+ process $proc$libresoc.v:135885$5869
assign { } { }
assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next
sync posedge \clk
update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:137757.3-137758.79"
- process $proc$libresoc.v:137757$5944
+ attribute \src "libresoc.v:135887.3-135888.79"
+ process $proc$libresoc.v:135887$5870
assign { } { }
assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next
sync posedge \clk
update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137759.3-137760.69"
- process $proc$libresoc.v:137759$5945
+ attribute \src "libresoc.v:135889.3-135890.69"
+ process $proc$libresoc.v:135889$5871
assign { } { }
assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next
sync posedge \clk
update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:137761.3-137762.53"
- process $proc$libresoc.v:137761$5946
+ attribute \src "libresoc.v:135891.3-135892.53"
+ process $proc$libresoc.v:135891$5872
assign { } { }
assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:137763.3-137764.53"
- process $proc$libresoc.v:137763$5947
+ attribute \src "libresoc.v:135893.3-135894.53"
+ process $proc$libresoc.v:135893$5873
assign { } { }
assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next
sync posedge \clk
update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:137765.3-137766.79"
- process $proc$libresoc.v:137765$5948
+ attribute \src "libresoc.v:135895.3-135896.79"
+ process $proc$libresoc.v:135895$5874
assign { } { }
assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next
sync posedge \clk
update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137767.3-137768.69"
- process $proc$libresoc.v:137767$5949
+ attribute \src "libresoc.v:135897.3-135898.69"
+ process $proc$libresoc.v:135897$5875
assign { } { }
assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next
sync posedge \clk
update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:137769.3-137770.31"
- process $proc$libresoc.v:137769$5950
+ attribute \src "libresoc.v:135899.3-135900.31"
+ process $proc$libresoc.v:135899$5876
assign { } { }
assign $0\sr0_reg[2:0] \sr0_reg$next
sync posedge \posjtag_clk
update \sr0_reg $0\sr0_reg[2:0]
end
- attribute \src "libresoc.v:137771.3-137772.31"
- process $proc$libresoc.v:137771$5951
+ attribute \src "libresoc.v:135901.3-135902.31"
+ process $proc$libresoc.v:135901$5877
assign { } { }
assign $0\sr0__oe[0:0] \sr0__oe$next
sync posedge \clk
update \sr0__oe $0\sr0__oe[0:0]
end
- attribute \src "libresoc.v:137773.3-137774.57"
- process $proc$libresoc.v:137773$5952
+ attribute \src "libresoc.v:135903.3-135904.57"
+ process $proc$libresoc.v:135903$5878
assign { } { }
assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next
sync posedge \clk
update \sr0_update_core_prev $0\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:137775.3-137776.47"
- process $proc$libresoc.v:137775$5953
+ attribute \src "libresoc.v:135905.3-135906.47"
+ process $proc$libresoc.v:135905$5879
assign { } { }
assign $0\sr0_update_core[0:0] \sr0_update_core$next
sync posedge \clk
update \sr0_update_core $0\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:137777.3-137778.27"
- process $proc$libresoc.v:137777$5954
+ attribute \src "libresoc.v:135907.3-135908.27"
+ process $proc$libresoc.v:135907$5880
assign { } { }
assign $0\io_bd[153:0] \io_bd$next
sync negedge \negjtag_clk
update \io_bd $0\io_bd[153:0]
end
- attribute \src "libresoc.v:137779.3-137780.27"
- process $proc$libresoc.v:137779$5955
+ attribute \src "libresoc.v:135909.3-135910.27"
+ process $proc$libresoc.v:135909$5881
assign { } { }
assign $0\io_sr[153:0] \io_sr$next
sync posedge \posjtag_clk
update \io_sr $0\io_sr[153:0]
end
- attribute \src "libresoc.v:137816.3-137831.6"
- process $proc$libresoc.v:137816$5956
+ attribute \src "libresoc.v:135946.3-135961.6"
+ process $proc$libresoc.v:135946$5882
assign { } { }
assign { } { }
assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:137817.5-137817.29"
+ attribute \src "libresoc.v:135947.5-135947.29"
switch \initial
- attribute \src "libresoc.v:137817.9-137817.17"
+ attribute \src "libresoc.v:135947.9-135947.17"
case 1'1
case
end
sync always
update \TAP_tdo $0\TAP_tdo[0:0]
end
- attribute \src "libresoc.v:137832.3-137840.6"
- process $proc$libresoc.v:137832$5957
+ attribute \src "libresoc.v:135962.3-135970.6"
+ process $proc$libresoc.v:135962$5883
assign { } { }
assign { } { }
- assign $0\sr0_update_core$next[0:0]$5958 $1\sr0_update_core$next[0:0]$5959
- attribute \src "libresoc.v:137833.5-137833.29"
+ assign $0\sr0_update_core$next[0:0]$5884 $1\sr0_update_core$next[0:0]$5885
+ attribute \src "libresoc.v:135963.5-135963.29"
switch \initial
- attribute \src "libresoc.v:137833.9-137833.17"
+ attribute \src "libresoc.v:135963.9-135963.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core$next[0:0]$5959 1'0
+ assign $1\sr0_update_core$next[0:0]$5885 1'0
case
- assign $1\sr0_update_core$next[0:0]$5959 \sr0_update
+ assign $1\sr0_update_core$next[0:0]$5885 \sr0_update
end
sync always
- update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5958
+ update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5884
end
- attribute \src "libresoc.v:137841.3-137849.6"
- process $proc$libresoc.v:137841$5960
+ attribute \src "libresoc.v:135971.3-135979.6"
+ process $proc$libresoc.v:135971$5886
assign { } { }
assign { } { }
- assign $0\sr0_update_core_prev$next[0:0]$5961 $1\sr0_update_core_prev$next[0:0]$5962
- attribute \src "libresoc.v:137842.5-137842.29"
+ assign $0\sr0_update_core_prev$next[0:0]$5887 $1\sr0_update_core_prev$next[0:0]$5888
+ attribute \src "libresoc.v:135972.5-135972.29"
switch \initial
- attribute \src "libresoc.v:137842.9-137842.17"
+ attribute \src "libresoc.v:135972.9-135972.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core_prev$next[0:0]$5962 1'0
+ assign $1\sr0_update_core_prev$next[0:0]$5888 1'0
case
- assign $1\sr0_update_core_prev$next[0:0]$5962 \sr0_update_core
+ assign $1\sr0_update_core_prev$next[0:0]$5888 \sr0_update_core
end
sync always
- update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5961
+ update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5887
end
- attribute \src "libresoc.v:137850.3-137866.6"
- process $proc$libresoc.v:137850$5963
+ attribute \src "libresoc.v:135980.3-135996.6"
+ process $proc$libresoc.v:135980$5889
assign { } { }
assign { } { }
- assign $0\sr0__oe$next[0:0]$5964 $2\sr0__oe$next[0:0]$5966
- attribute \src "libresoc.v:137851.5-137851.29"
+ assign $0\sr0__oe$next[0:0]$5890 $2\sr0__oe$next[0:0]$5892
+ attribute \src "libresoc.v:135981.5-135981.29"
switch \initial
- attribute \src "libresoc.v:137851.9-137851.17"
+ attribute \src "libresoc.v:135981.9-135981.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0__oe$next[0:0]$5965 \sr0_isir
+ assign $1\sr0__oe$next[0:0]$5891 \sr0_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\sr0__oe$next[0:0]$5965 1'0
+ assign $1\sr0__oe$next[0:0]$5891 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0__oe$next[0:0]$5966 1'0
+ assign $2\sr0__oe$next[0:0]$5892 1'0
case
- assign $2\sr0__oe$next[0:0]$5966 $1\sr0__oe$next[0:0]$5965
+ assign $2\sr0__oe$next[0:0]$5892 $1\sr0__oe$next[0:0]$5891
end
sync always
- update \sr0__oe$next $0\sr0__oe$next[0:0]$5964
+ update \sr0__oe$next $0\sr0__oe$next[0:0]$5890
end
- attribute \src "libresoc.v:137867.3-137887.6"
- process $proc$libresoc.v:137867$5967
+ attribute \src "libresoc.v:135997.3-136017.6"
+ process $proc$libresoc.v:135997$5893
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr0_reg$next[2:0]$5968 $3\sr0_reg$next[2:0]$5971
- attribute \src "libresoc.v:137868.5-137868.29"
+ assign $0\sr0_reg$next[2:0]$5894 $3\sr0_reg$next[2:0]$5897
+ attribute \src "libresoc.v:135998.5-135998.29"
switch \initial
- attribute \src "libresoc.v:137868.9-137868.17"
+ attribute \src "libresoc.v:135998.9-135998.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_reg$next[2:0]$5969 { \TAP_bus__tdi \sr0_reg [2:1] }
+ assign $1\sr0_reg$next[2:0]$5895 { \TAP_bus__tdi \sr0_reg [2:1] }
case
- assign $1\sr0_reg$next[2:0]$5969 \sr0_reg
+ assign $1\sr0_reg$next[2:0]$5895 \sr0_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \sr0_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0_reg$next[2:0]$5970 \sr0__i
+ assign $2\sr0_reg$next[2:0]$5896 \sr0__i
case
- assign $2\sr0_reg$next[2:0]$5970 $1\sr0_reg$next[2:0]$5969
+ assign $2\sr0_reg$next[2:0]$5896 $1\sr0_reg$next[2:0]$5895
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sr0_reg$next[2:0]$5971 3'000
+ assign $3\sr0_reg$next[2:0]$5897 3'000
case
- assign $3\sr0_reg$next[2:0]$5971 $2\sr0_reg$next[2:0]$5970
+ assign $3\sr0_reg$next[2:0]$5897 $2\sr0_reg$next[2:0]$5896
end
sync always
- update \sr0_reg$next $0\sr0_reg$next[2:0]$5968
+ update \sr0_reg$next $0\sr0_reg$next[2:0]$5894
end
- attribute \src "libresoc.v:137888.3-137896.6"
- process $proc$libresoc.v:137888$5972
+ attribute \src "libresoc.v:136018.3-136026.6"
+ process $proc$libresoc.v:136018$5898
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core$next[0:0]$5973 $1\jtag_wb_addrsr_update_core$next[0:0]$5974
- attribute \src "libresoc.v:137889.5-137889.29"
+ assign $0\jtag_wb_addrsr_update_core$next[0:0]$5899 $1\jtag_wb_addrsr_update_core$next[0:0]$5900
+ attribute \src "libresoc.v:136019.5-136019.29"
switch \initial
- attribute \src "libresoc.v:137889.9-137889.17"
+ attribute \src "libresoc.v:136019.9-136019.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$5974 1'0
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$5900 1'0
case
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$5974 \jtag_wb_addrsr_update
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$5900 \jtag_wb_addrsr_update
end
sync always
- update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5973
+ update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5899
end
- attribute \src "libresoc.v:137897.3-137905.6"
- process $proc$libresoc.v:137897$5975
+ attribute \src "libresoc.v:136027.3-136035.6"
+ process $proc$libresoc.v:136027$5901
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977
- attribute \src "libresoc.v:137898.5-137898.29"
+ assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903
+ attribute \src "libresoc.v:136028.5-136028.29"
switch \initial
- attribute \src "libresoc.v:137898.9-137898.17"
+ attribute \src "libresoc.v:136028.9-136028.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 1'0
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 1'0
case
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 \jtag_wb_addrsr_update_core
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 \jtag_wb_addrsr_update_core
end
sync always
- update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976
+ update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902
end
- attribute \src "libresoc.v:137906.3-137922.6"
- process $proc$libresoc.v:137906$5978
+ attribute \src "libresoc.v:136036.3-136052.6"
+ process $proc$libresoc.v:136036$5904
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr__oe$next[0:0]$5979 $2\jtag_wb_addrsr__oe$next[0:0]$5981
- attribute \src "libresoc.v:137907.5-137907.29"
+ assign $0\jtag_wb_addrsr__oe$next[0:0]$5905 $2\jtag_wb_addrsr__oe$next[0:0]$5907
+ attribute \src "libresoc.v:136037.5-136037.29"
switch \initial
- attribute \src "libresoc.v:137907.9-137907.17"
+ attribute \src "libresoc.v:136037.9-136037.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$5980 \jtag_wb_addrsr_isir
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$5906 \jtag_wb_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$5980 1'0
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$5906 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr__oe$next[0:0]$5981 1'0
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$5907 1'0
case
- assign $2\jtag_wb_addrsr__oe$next[0:0]$5981 $1\jtag_wb_addrsr__oe$next[0:0]$5980
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$5907 $1\jtag_wb_addrsr__oe$next[0:0]$5906
end
sync always
- update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5979
+ update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5905
end
- attribute \src "libresoc.v:137923.3-137943.6"
- process $proc$libresoc.v:137923$5982
+ attribute \src "libresoc.v:136053.3-136073.6"
+ process $proc$libresoc.v:136053$5908
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_reg$next[28:0]$5983 $3\jtag_wb_addrsr_reg$next[28:0]$5986
- attribute \src "libresoc.v:137924.5-137924.29"
+ assign $0\jtag_wb_addrsr_reg$next[28:0]$5909 $3\jtag_wb_addrsr_reg$next[28:0]$5912
+ attribute \src "libresoc.v:136054.5-136054.29"
switch \initial
- attribute \src "libresoc.v:137924.9-137924.17"
+ attribute \src "libresoc.v:136054.9-136054.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_reg$next[28:0]$5984 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$5910 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
case
- assign $1\jtag_wb_addrsr_reg$next[28:0]$5984 \jtag_wb_addrsr_reg
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$5910 \jtag_wb_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \jtag_wb_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr_reg$next[28:0]$5985 \jtag_wb_addrsr__i
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$5911 \jtag_wb_addrsr__i
case
- assign $2\jtag_wb_addrsr_reg$next[28:0]$5985 $1\jtag_wb_addrsr_reg$next[28:0]$5984
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$5911 $1\jtag_wb_addrsr_reg$next[28:0]$5910
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_addrsr_reg$next[28:0]$5986 29'00000000000000000000000000000
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$5912 29'00000000000000000000000000000
case
- assign $3\jtag_wb_addrsr_reg$next[28:0]$5986 $2\jtag_wb_addrsr_reg$next[28:0]$5985
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$5912 $2\jtag_wb_addrsr_reg$next[28:0]$5911
end
sync always
- update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5983
+ update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5909
end
- attribute \src "libresoc.v:137944.3-137952.6"
- process $proc$libresoc.v:137944$5987
+ attribute \src "libresoc.v:136074.3-136082.6"
+ process $proc$libresoc.v:136074$5913
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core$next[0:0]$5988 $1\jtag_wb_datasr_update_core$next[0:0]$5989
- attribute \src "libresoc.v:137945.5-137945.29"
+ assign $0\jtag_wb_datasr_update_core$next[0:0]$5914 $1\jtag_wb_datasr_update_core$next[0:0]$5915
+ attribute \src "libresoc.v:136075.5-136075.29"
switch \initial
- attribute \src "libresoc.v:137945.9-137945.17"
+ attribute \src "libresoc.v:136075.9-136075.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core$next[0:0]$5989 1'0
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$5915 1'0
case
- assign $1\jtag_wb_datasr_update_core$next[0:0]$5989 \jtag_wb_datasr_update
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$5915 \jtag_wb_datasr_update
end
sync always
- update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5988
+ update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5914
end
- attribute \src "libresoc.v:137953.3-137961.6"
- process $proc$libresoc.v:137953$5990
+ attribute \src "libresoc.v:136083.3-136091.6"
+ process $proc$libresoc.v:136083$5916
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992
- attribute \src "libresoc.v:137954.5-137954.29"
+ assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918
+ attribute \src "libresoc.v:136084.5-136084.29"
switch \initial
- attribute \src "libresoc.v:137954.9-137954.17"
+ attribute \src "libresoc.v:136084.9-136084.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 1'0
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 1'0
case
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 \jtag_wb_datasr_update_core
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 \jtag_wb_datasr_update_core
end
sync always
- update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991
+ update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917
end
- attribute \src "libresoc.v:137962.3-137978.6"
- process $proc$libresoc.v:137962$5993
+ attribute \src "libresoc.v:136092.3-136108.6"
+ process $proc$libresoc.v:136092$5919
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__oe$next[1:0]$5994 $2\jtag_wb_datasr__oe$next[1:0]$5996
- attribute \src "libresoc.v:137963.5-137963.29"
+ assign $0\jtag_wb_datasr__oe$next[1:0]$5920 $2\jtag_wb_datasr__oe$next[1:0]$5922
+ attribute \src "libresoc.v:136093.5-136093.29"
switch \initial
- attribute \src "libresoc.v:137963.9-137963.17"
+ attribute \src "libresoc.v:136093.9-136093.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$5995 \jtag_wb_datasr_isir
+ assign $1\jtag_wb_datasr__oe$next[1:0]$5921 \jtag_wb_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$5995 2'00
+ assign $1\jtag_wb_datasr__oe$next[1:0]$5921 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__oe$next[1:0]$5996 2'00
+ assign $2\jtag_wb_datasr__oe$next[1:0]$5922 2'00
case
- assign $2\jtag_wb_datasr__oe$next[1:0]$5996 $1\jtag_wb_datasr__oe$next[1:0]$5995
+ assign $2\jtag_wb_datasr__oe$next[1:0]$5922 $1\jtag_wb_datasr__oe$next[1:0]$5921
end
sync always
- update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5994
+ update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5920
end
- attribute \src "libresoc.v:137979.3-137999.6"
- process $proc$libresoc.v:137979$5997
+ attribute \src "libresoc.v:136109.3-136129.6"
+ process $proc$libresoc.v:136109$5923
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_reg$next[63:0]$5998 $3\jtag_wb_datasr_reg$next[63:0]$6001
- attribute \src "libresoc.v:137980.5-137980.29"
+ assign $0\jtag_wb_datasr_reg$next[63:0]$5924 $3\jtag_wb_datasr_reg$next[63:0]$5927
+ attribute \src "libresoc.v:136110.5-136110.29"
switch \initial
- attribute \src "libresoc.v:137980.9-137980.17"
+ attribute \src "libresoc.v:136110.9-136110.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_reg$next[63:0]$5999 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
+ assign $1\jtag_wb_datasr_reg$next[63:0]$5925 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
case
- assign $1\jtag_wb_datasr_reg$next[63:0]$5999 \jtag_wb_datasr_reg
+ assign $1\jtag_wb_datasr_reg$next[63:0]$5925 \jtag_wb_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \jtag_wb_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr_reg$next[63:0]$6000 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr_reg$next[63:0]$5926 \jtag_wb_datasr__i
case
- assign $2\jtag_wb_datasr_reg$next[63:0]$6000 $1\jtag_wb_datasr_reg$next[63:0]$5999
+ assign $2\jtag_wb_datasr_reg$next[63:0]$5926 $1\jtag_wb_datasr_reg$next[63:0]$5925
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr_reg$next[63:0]$6001 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr_reg$next[63:0]$5927 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr_reg$next[63:0]$6001 $2\jtag_wb_datasr_reg$next[63:0]$6000
+ assign $3\jtag_wb_datasr_reg$next[63:0]$5927 $2\jtag_wb_datasr_reg$next[63:0]$5926
end
sync always
- update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5998
+ update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5924
end
- attribute \src "libresoc.v:138000.3-138008.6"
- process $proc$libresoc.v:138000$6002
+ attribute \src "libresoc.v:136130.3-136138.6"
+ process $proc$libresoc.v:136130$5928
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core$next[0:0]$6003 $1\dmi0_addrsr_update_core$next[0:0]$6004
- attribute \src "libresoc.v:138001.5-138001.29"
+ assign $0\dmi0_addrsr_update_core$next[0:0]$5929 $1\dmi0_addrsr_update_core$next[0:0]$5930
+ attribute \src "libresoc.v:136131.5-136131.29"
switch \initial
- attribute \src "libresoc.v:138001.9-138001.17"
+ attribute \src "libresoc.v:136131.9-136131.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core$next[0:0]$6004 1'0
+ assign $1\dmi0_addrsr_update_core$next[0:0]$5930 1'0
case
- assign $1\dmi0_addrsr_update_core$next[0:0]$6004 \dmi0_addrsr_update
+ assign $1\dmi0_addrsr_update_core$next[0:0]$5930 \dmi0_addrsr_update
end
sync always
- update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6003
+ update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5929
end
- attribute \src "libresoc.v:138009.3-138017.6"
- process $proc$libresoc.v:138009$6005
+ attribute \src "libresoc.v:136139.3-136147.6"
+ process $proc$libresoc.v:136139$5931
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6006 $1\dmi0_addrsr_update_core_prev$next[0:0]$6007
- attribute \src "libresoc.v:138010.5-138010.29"
+ assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5932 $1\dmi0_addrsr_update_core_prev$next[0:0]$5933
+ attribute \src "libresoc.v:136140.5-136140.29"
switch \initial
- attribute \src "libresoc.v:138010.9-138010.17"
+ attribute \src "libresoc.v:136140.9-136140.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 1'0
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 1'0
case
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 \dmi0_addrsr_update_core
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 \dmi0_addrsr_update_core
end
sync always
- update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6006
+ update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5932
end
- attribute \src "libresoc.v:138018.3-138034.6"
- process $proc$libresoc.v:138018$6008
+ attribute \src "libresoc.v:136148.3-136164.6"
+ process $proc$libresoc.v:136148$5934
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr__oe$next[0:0]$6009 $2\dmi0_addrsr__oe$next[0:0]$6011
- attribute \src "libresoc.v:138019.5-138019.29"
+ assign $0\dmi0_addrsr__oe$next[0:0]$5935 $2\dmi0_addrsr__oe$next[0:0]$5937
+ attribute \src "libresoc.v:136149.5-136149.29"
switch \initial
- attribute \src "libresoc.v:138019.9-138019.17"
+ attribute \src "libresoc.v:136149.9-136149.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$6010 \dmi0_addrsr_isir
+ assign $1\dmi0_addrsr__oe$next[0:0]$5936 \dmi0_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$6010 1'0
+ assign $1\dmi0_addrsr__oe$next[0:0]$5936 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr__oe$next[0:0]$6011 1'0
+ assign $2\dmi0_addrsr__oe$next[0:0]$5937 1'0
case
- assign $2\dmi0_addrsr__oe$next[0:0]$6011 $1\dmi0_addrsr__oe$next[0:0]$6010
+ assign $2\dmi0_addrsr__oe$next[0:0]$5937 $1\dmi0_addrsr__oe$next[0:0]$5936
end
sync always
- update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6009
+ update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5935
end
- attribute \src "libresoc.v:138035.3-138055.6"
- process $proc$libresoc.v:138035$6012
+ attribute \src "libresoc.v:136165.3-136185.6"
+ process $proc$libresoc.v:136165$5938
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_reg$next[7:0]$6013 $3\dmi0_addrsr_reg$next[7:0]$6016
- attribute \src "libresoc.v:138036.5-138036.29"
+ assign $0\dmi0_addrsr_reg$next[7:0]$5939 $3\dmi0_addrsr_reg$next[7:0]$5942
+ attribute \src "libresoc.v:136166.5-136166.29"
switch \initial
- attribute \src "libresoc.v:138036.9-138036.17"
+ attribute \src "libresoc.v:136166.9-136166.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_reg$next[7:0]$6014 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
+ assign $1\dmi0_addrsr_reg$next[7:0]$5940 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
case
- assign $1\dmi0_addrsr_reg$next[7:0]$6014 \dmi0_addrsr_reg
+ assign $1\dmi0_addrsr_reg$next[7:0]$5940 \dmi0_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \dmi0_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr_reg$next[7:0]$6015 \dmi0_addrsr__i
+ assign $2\dmi0_addrsr_reg$next[7:0]$5941 \dmi0_addrsr__i
case
- assign $2\dmi0_addrsr_reg$next[7:0]$6015 $1\dmi0_addrsr_reg$next[7:0]$6014
+ assign $2\dmi0_addrsr_reg$next[7:0]$5941 $1\dmi0_addrsr_reg$next[7:0]$5940
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_addrsr_reg$next[7:0]$6016 8'00000000
+ assign $3\dmi0_addrsr_reg$next[7:0]$5942 8'00000000
case
- assign $3\dmi0_addrsr_reg$next[7:0]$6016 $2\dmi0_addrsr_reg$next[7:0]$6015
+ assign $3\dmi0_addrsr_reg$next[7:0]$5942 $2\dmi0_addrsr_reg$next[7:0]$5941
end
sync always
- update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6013
+ update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5939
end
- attribute \src "libresoc.v:138056.3-138064.6"
- process $proc$libresoc.v:138056$6017
+ attribute \src "libresoc.v:136186.3-136194.6"
+ process $proc$libresoc.v:136186$5943
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core$next[0:0]$6018 $1\dmi0_datasr_update_core$next[0:0]$6019
- attribute \src "libresoc.v:138057.5-138057.29"
+ assign $0\dmi0_datasr_update_core$next[0:0]$5944 $1\dmi0_datasr_update_core$next[0:0]$5945
+ attribute \src "libresoc.v:136187.5-136187.29"
switch \initial
- attribute \src "libresoc.v:138057.9-138057.17"
+ attribute \src "libresoc.v:136187.9-136187.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_update_core$next[0:0]$6019 1'0
+ assign $1\dmi0_datasr_update_core$next[0:0]$5945 1'0
case
- assign $1\dmi0_datasr_update_core$next[0:0]$6019 \dmi0_datasr_update
+ assign $1\dmi0_datasr_update_core$next[0:0]$5945 \dmi0_datasr_update
end
sync always
- update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6018
+ update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5944
end
- attribute \src "libresoc.v:138065.3-138073.6"
- process $proc$libresoc.v:138065$6020
+ attribute \src "libresoc.v:136195.3-136203.6"
+ process $proc$libresoc.v:136195$5946
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core_prev$next[0:0]$6021 $1\dmi0_datasr_update_core_prev$next[0:0]$6022
- attribute \src "libresoc.v:138066.5-138066.29"
+ assign $0\dmi0_datasr_update_core_prev$next[0:0]$5947 $1\dmi0_datasr_update_core_prev$next[0:0]$5948
+ attribute \src "libresoc.v:136196.5-136196.29"
switch \initial
- attribute \src "libresoc.v:138066.9-138066.17"
+ attribute \src "libresoc.v:136196.9-136196.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$6022 1'0
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$5948 1'0
case
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$6022 \dmi0_datasr_update_core
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$5948 \dmi0_datasr_update_core
end
sync always
- update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6021
+ update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5947
end
- attribute \src "libresoc.v:138074.3-138090.6"
- process $proc$libresoc.v:138074$6023
+ attribute \src "libresoc.v:136204.3-136220.6"
+ process $proc$libresoc.v:136204$5949
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__oe$next[1:0]$6024 $2\dmi0_datasr__oe$next[1:0]$6026
- attribute \src "libresoc.v:138075.5-138075.29"
+ assign $0\dmi0_datasr__oe$next[1:0]$5950 $2\dmi0_datasr__oe$next[1:0]$5952
+ attribute \src "libresoc.v:136205.5-136205.29"
switch \initial
- attribute \src "libresoc.v:138075.9-138075.17"
+ attribute \src "libresoc.v:136205.9-136205.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$6025 \dmi0_datasr_isir
+ assign $1\dmi0_datasr__oe$next[1:0]$5951 \dmi0_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$6025 2'00
+ assign $1\dmi0_datasr__oe$next[1:0]$5951 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__oe$next[1:0]$6026 2'00
+ assign $2\dmi0_datasr__oe$next[1:0]$5952 2'00
case
- assign $2\dmi0_datasr__oe$next[1:0]$6026 $1\dmi0_datasr__oe$next[1:0]$6025
+ assign $2\dmi0_datasr__oe$next[1:0]$5952 $1\dmi0_datasr__oe$next[1:0]$5951
end
sync always
- update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6024
+ update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5950
end
- attribute \src "libresoc.v:138091.3-138111.6"
- process $proc$libresoc.v:138091$6027
+ attribute \src "libresoc.v:136221.3-136241.6"
+ process $proc$libresoc.v:136221$5953
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_reg$next[63:0]$6028 $3\dmi0_datasr_reg$next[63:0]$6031
- attribute \src "libresoc.v:138092.5-138092.29"
+ assign $0\dmi0_datasr_reg$next[63:0]$5954 $3\dmi0_datasr_reg$next[63:0]$5957
+ attribute \src "libresoc.v:136222.5-136222.29"
switch \initial
- attribute \src "libresoc.v:138092.9-138092.17"
+ attribute \src "libresoc.v:136222.9-136222.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_reg$next[63:0]$6029 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
+ assign $1\dmi0_datasr_reg$next[63:0]$5955 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
case
- assign $1\dmi0_datasr_reg$next[63:0]$6029 \dmi0_datasr_reg
+ assign $1\dmi0_datasr_reg$next[63:0]$5955 \dmi0_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \dmi0_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr_reg$next[63:0]$6030 \dmi0_datasr__i
+ assign $2\dmi0_datasr_reg$next[63:0]$5956 \dmi0_datasr__i
case
- assign $2\dmi0_datasr_reg$next[63:0]$6030 $1\dmi0_datasr_reg$next[63:0]$6029
+ assign $2\dmi0_datasr_reg$next[63:0]$5956 $1\dmi0_datasr_reg$next[63:0]$5955
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr_reg$next[63:0]$6031 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr_reg$next[63:0]$5957 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr_reg$next[63:0]$6031 $2\dmi0_datasr_reg$next[63:0]$6030
+ assign $3\dmi0_datasr_reg$next[63:0]$5957 $2\dmi0_datasr_reg$next[63:0]$5956
end
sync always
- update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6028
+ update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5954
end
- attribute \src "libresoc.v:138112.3-138120.6"
- process $proc$libresoc.v:138112$6032
+ attribute \src "libresoc.v:136242.3-136250.6"
+ process $proc$libresoc.v:136242$5958
assign { } { }
assign { } { }
- assign $0\sr5_update_core$next[0:0]$6033 $1\sr5_update_core$next[0:0]$6034
- attribute \src "libresoc.v:138113.5-138113.29"
+ assign $0\sr5_update_core$next[0:0]$5959 $1\sr5_update_core$next[0:0]$5960
+ attribute \src "libresoc.v:136243.5-136243.29"
switch \initial
- attribute \src "libresoc.v:138113.9-138113.17"
+ attribute \src "libresoc.v:136243.9-136243.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_update_core$next[0:0]$6034 1'0
+ assign $1\sr5_update_core$next[0:0]$5960 1'0
case
- assign $1\sr5_update_core$next[0:0]$6034 \sr5_update
+ assign $1\sr5_update_core$next[0:0]$5960 \sr5_update
end
sync always
- update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6033
+ update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5959
end
- attribute \src "libresoc.v:138121.3-138129.6"
- process $proc$libresoc.v:138121$6035
+ attribute \src "libresoc.v:136251.3-136259.6"
+ process $proc$libresoc.v:136251$5961
assign { } { }
assign { } { }
- assign $0\sr5_update_core_prev$next[0:0]$6036 $1\sr5_update_core_prev$next[0:0]$6037
- attribute \src "libresoc.v:138122.5-138122.29"
+ assign $0\sr5_update_core_prev$next[0:0]$5962 $1\sr5_update_core_prev$next[0:0]$5963
+ attribute \src "libresoc.v:136252.5-136252.29"
switch \initial
- attribute \src "libresoc.v:138122.9-138122.17"
+ attribute \src "libresoc.v:136252.9-136252.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_update_core_prev$next[0:0]$6037 1'0
+ assign $1\sr5_update_core_prev$next[0:0]$5963 1'0
case
- assign $1\sr5_update_core_prev$next[0:0]$6037 \sr5_update_core
+ assign $1\sr5_update_core_prev$next[0:0]$5963 \sr5_update_core
end
sync always
- update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6036
+ update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5962
end
- attribute \src "libresoc.v:138130.3-138146.6"
- process $proc$libresoc.v:138130$6038
+ attribute \src "libresoc.v:136260.3-136276.6"
+ process $proc$libresoc.v:136260$5964
assign { } { }
assign { } { }
- assign $0\sr5__oe$next[0:0]$6039 $2\sr5__oe$next[0:0]$6041
- attribute \src "libresoc.v:138131.5-138131.29"
+ assign $0\sr5__oe$next[0:0]$5965 $2\sr5__oe$next[0:0]$5967
+ attribute \src "libresoc.v:136261.5-136261.29"
switch \initial
- attribute \src "libresoc.v:138131.9-138131.17"
+ attribute \src "libresoc.v:136261.9-136261.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5__oe$next[0:0]$6040 \sr5_isir
+ assign $1\sr5__oe$next[0:0]$5966 \sr5_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\sr5__oe$next[0:0]$6040 1'0
+ assign $1\sr5__oe$next[0:0]$5966 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr5__oe$next[0:0]$6041 1'0
+ assign $2\sr5__oe$next[0:0]$5967 1'0
case
- assign $2\sr5__oe$next[0:0]$6041 $1\sr5__oe$next[0:0]$6040
+ assign $2\sr5__oe$next[0:0]$5967 $1\sr5__oe$next[0:0]$5966
end
sync always
- update \sr5__oe$next $0\sr5__oe$next[0:0]$6039
+ update \sr5__oe$next $0\sr5__oe$next[0:0]$5965
end
- attribute \src "libresoc.v:138147.3-138167.6"
- process $proc$libresoc.v:138147$6042
+ attribute \src "libresoc.v:136277.3-136297.6"
+ process $proc$libresoc.v:136277$5968
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr5_reg$next[2:0]$6043 $3\sr5_reg$next[2:0]$6046
- attribute \src "libresoc.v:138148.5-138148.29"
+ assign $0\sr5_reg$next[2:0]$5969 $3\sr5_reg$next[2:0]$5972
+ attribute \src "libresoc.v:136278.5-136278.29"
switch \initial
- attribute \src "libresoc.v:138148.9-138148.17"
+ attribute \src "libresoc.v:136278.9-136278.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr5_reg$next[2:0]$6044 { \TAP_bus__tdi \sr5_reg [2:1] }
+ assign $1\sr5_reg$next[2:0]$5970 { \TAP_bus__tdi \sr5_reg [2:1] }
case
- assign $1\sr5_reg$next[2:0]$6044 \sr5_reg
+ assign $1\sr5_reg$next[2:0]$5970 \sr5_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
switch \sr5_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr5_reg$next[2:0]$6045 \sr5__i
+ assign $2\sr5_reg$next[2:0]$5971 \sr5__i
case
- assign $2\sr5_reg$next[2:0]$6045 $1\sr5_reg$next[2:0]$6044
+ assign $2\sr5_reg$next[2:0]$5971 $1\sr5_reg$next[2:0]$5970
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sr5_reg$next[2:0]$6046 3'000
+ assign $3\sr5_reg$next[2:0]$5972 3'000
case
- assign $3\sr5_reg$next[2:0]$6046 $2\sr5_reg$next[2:0]$6045
+ assign $3\sr5_reg$next[2:0]$5972 $2\sr5_reg$next[2:0]$5971
end
sync always
- update \sr5_reg$next $0\sr5_reg$next[2:0]$6043
+ update \sr5_reg$next $0\sr5_reg$next[2:0]$5969
end
- attribute \src "libresoc.v:138168.3-138194.6"
- process $proc$libresoc.v:138168$6047
+ attribute \src "libresoc.v:136298.3-136324.6"
+ process $proc$libresoc.v:136298$5973
assign { } { }
assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:138169.5-138169.29"
+ attribute \src "libresoc.v:136299.5-136299.29"
switch \initial
- attribute \src "libresoc.v:138169.9-138169.17"
+ attribute \src "libresoc.v:136299.9-136299.17"
case 1'1
case
end
sync always
update \TAP_bus__tdo $0\TAP_bus__tdo[0:0]
end
- attribute \src "libresoc.v:138195.3-138227.6"
- process $proc$libresoc.v:138195$6048
+ attribute \src "libresoc.v:136325.3-136357.6"
+ process $proc$libresoc.v:136325$5974
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__adr$next[28:0]$6049 $4\jtag_wb__adr$next[28:0]$6053
- attribute \src "libresoc.v:138196.5-138196.29"
+ assign $0\jtag_wb__adr$next[28:0]$5975 $4\jtag_wb__adr$next[28:0]$5979
+ attribute \src "libresoc.v:136326.5-136326.29"
switch \initial
- attribute \src "libresoc.v:138196.9-138196.17"
+ attribute \src "libresoc.v:136326.9-136326.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$6050 $2\jtag_wb__adr$next[28:0]$6051
+ assign $1\jtag_wb__adr$next[28:0]$5976 $2\jtag_wb__adr$next[28:0]$5977
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$6051 \jtag_wb_addrsr__o
+ assign $2\jtag_wb__adr$next[28:0]$5977 \jtag_wb_addrsr__o
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$6051 \$495 [28:0]
+ assign $2\jtag_wb__adr$next[28:0]$5977 \$495 [28:0]
case
- assign $2\jtag_wb__adr$next[28:0]$6051 \jtag_wb__adr
+ assign $2\jtag_wb__adr$next[28:0]$5977 \jtag_wb__adr
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$6050 $3\jtag_wb__adr$next[28:0]$6052
+ assign $1\jtag_wb__adr$next[28:0]$5976 $3\jtag_wb__adr$next[28:0]$5978
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__adr$next[28:0]$6052 \$498 [28:0]
+ assign $3\jtag_wb__adr$next[28:0]$5978 \$498 [28:0]
case
- assign $3\jtag_wb__adr$next[28:0]$6052 \jtag_wb__adr
+ assign $3\jtag_wb__adr$next[28:0]$5978 \jtag_wb__adr
end
case
- assign $1\jtag_wb__adr$next[28:0]$6050 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$5976 \jtag_wb__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\jtag_wb__adr$next[28:0]$6053 29'00000000000000000000000000000
+ assign $4\jtag_wb__adr$next[28:0]$5979 29'00000000000000000000000000000
case
- assign $4\jtag_wb__adr$next[28:0]$6053 $1\jtag_wb__adr$next[28:0]$6050
+ assign $4\jtag_wb__adr$next[28:0]$5979 $1\jtag_wb__adr$next[28:0]$5976
end
sync always
- update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6049
+ update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5975
end
- attribute \src "libresoc.v:138228.3-138280.6"
- process $proc$libresoc.v:138228$6054
+ attribute \src "libresoc.v:136358.3-136410.6"
+ process $proc$libresoc.v:136358$5980
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[2:0]$6055 $5\fsm_state$next[2:0]$6060
- attribute \src "libresoc.v:138229.5-138229.29"
+ assign $0\fsm_state$next[2:0]$5981 $5\fsm_state$next[2:0]$5986
+ attribute \src "libresoc.v:136359.5-136359.29"
switch \initial
- attribute \src "libresoc.v:138229.9-138229.17"
+ attribute \src "libresoc.v:136359.9-136359.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$next[2:0]$6056 $2\fsm_state$next[2:0]$6057
+ assign $1\fsm_state$next[2:0]$5982 $2\fsm_state$next[2:0]$5983
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$next[2:0]$6057 3'001
+ assign $2\fsm_state$next[2:0]$5983 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$next[2:0]$6057 3'001
+ assign $2\fsm_state$next[2:0]$5983 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$next[2:0]$6057 3'010
+ assign $2\fsm_state$next[2:0]$5983 3'010
case
- assign $2\fsm_state$next[2:0]$6057 \fsm_state
+ assign $2\fsm_state$next[2:0]$5983 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$next[2:0]$6056 3'011
+ assign $1\fsm_state$next[2:0]$5982 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$next[2:0]$6056 $3\fsm_state$next[2:0]$6058
+ assign $1\fsm_state$next[2:0]$5982 $3\fsm_state$next[2:0]$5984
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$next[2:0]$6058 3'000
+ assign $3\fsm_state$next[2:0]$5984 3'000
case
- assign $3\fsm_state$next[2:0]$6058 \fsm_state
+ assign $3\fsm_state$next[2:0]$5984 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$next[2:0]$6056 3'100
+ assign $1\fsm_state$next[2:0]$5982 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$next[2:0]$6056 $4\fsm_state$next[2:0]$6059
+ assign $1\fsm_state$next[2:0]$5982 $4\fsm_state$next[2:0]$5985
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[2:0]$6059 3'001
+ assign $4\fsm_state$next[2:0]$5985 3'001
case
- assign $4\fsm_state$next[2:0]$6059 \fsm_state
+ assign $4\fsm_state$next[2:0]$5985 \fsm_state
end
case
- assign $1\fsm_state$next[2:0]$6056 \fsm_state
+ assign $1\fsm_state$next[2:0]$5982 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[2:0]$6060 3'000
+ assign $5\fsm_state$next[2:0]$5986 3'000
case
- assign $5\fsm_state$next[2:0]$6060 $1\fsm_state$next[2:0]$6056
+ assign $5\fsm_state$next[2:0]$5986 $1\fsm_state$next[2:0]$5982
end
sync always
- update \fsm_state$next $0\fsm_state$next[2:0]$6055
+ update \fsm_state$next $0\fsm_state$next[2:0]$5981
end
- attribute \src "libresoc.v:138281.3-138307.6"
- process $proc$libresoc.v:138281$6061
+ attribute \src "libresoc.v:136411.3-136437.6"
+ process $proc$libresoc.v:136411$5987
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__dat_w$next[63:0]$6062 $3\jtag_wb__dat_w$next[63:0]$6065
- attribute \src "libresoc.v:138282.5-138282.29"
+ assign $0\jtag_wb__dat_w$next[63:0]$5988 $3\jtag_wb__dat_w$next[63:0]$5991
+ attribute \src "libresoc.v:136412.5-136412.29"
switch \initial
- attribute \src "libresoc.v:138282.9-138282.17"
+ attribute \src "libresoc.v:136412.9-136412.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__dat_w$next[63:0]$6063 $2\jtag_wb__dat_w$next[63:0]$6064
+ assign $1\jtag_wb__dat_w$next[63:0]$5989 $2\jtag_wb__dat_w$next[63:0]$5990
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb_datasr__o
+ assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb_datasr__o
case
- assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w
end
case
- assign $1\jtag_wb__dat_w$next[63:0]$6063 \jtag_wb__dat_w
+ assign $1\jtag_wb__dat_w$next[63:0]$5989 \jtag_wb__dat_w
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__dat_w$next[63:0]$6065 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb__dat_w$next[63:0]$5991 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb__dat_w$next[63:0]$6065 $1\jtag_wb__dat_w$next[63:0]$6063
+ assign $3\jtag_wb__dat_w$next[63:0]$5991 $1\jtag_wb__dat_w$next[63:0]$5989
end
sync always
- update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6062
+ update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5988
end
- attribute \src "libresoc.v:138308.3-138328.6"
- process $proc$libresoc.v:138308$6066
+ attribute \src "libresoc.v:136438.3-136458.6"
+ process $proc$libresoc.v:136438$5992
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__i$next[63:0]$6067 $3\jtag_wb_datasr__i$next[63:0]$6070
- attribute \src "libresoc.v:138309.5-138309.29"
+ assign $0\jtag_wb_datasr__i$next[63:0]$5993 $3\jtag_wb_datasr__i$next[63:0]$5996
+ attribute \src "libresoc.v:136439.5-136439.29"
switch \initial
- attribute \src "libresoc.v:138309.9-138309.17"
+ attribute \src "libresoc.v:136439.9-136439.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\jtag_wb_datasr__i$next[63:0]$6068 $2\jtag_wb_datasr__i$next[63:0]$6069
+ assign $1\jtag_wb_datasr__i$next[63:0]$5994 $2\jtag_wb_datasr__i$next[63:0]$5995
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__i$next[63:0]$6069 \jtag_wb__dat_r
+ assign $2\jtag_wb_datasr__i$next[63:0]$5995 \jtag_wb__dat_r
case
- assign $2\jtag_wb_datasr__i$next[63:0]$6069 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr__i$next[63:0]$5995 \jtag_wb_datasr__i
end
case
- assign $1\jtag_wb_datasr__i$next[63:0]$6068 \jtag_wb_datasr__i
+ assign $1\jtag_wb_datasr__i$next[63:0]$5994 \jtag_wb_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr__i$next[63:0]$6070 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr__i$next[63:0]$5996 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr__i$next[63:0]$6070 $1\jtag_wb_datasr__i$next[63:0]$6068
+ assign $3\jtag_wb_datasr__i$next[63:0]$5996 $1\jtag_wb_datasr__i$next[63:0]$5994
end
sync always
- update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6067
+ update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5993
end
- attribute \src "libresoc.v:138329.3-138361.6"
- process $proc$libresoc.v:138329$6071
+ attribute \src "libresoc.v:136459.3-136491.6"
+ process $proc$libresoc.v:136459$5997
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0__addr_i$next[3:0]$6072 $4\dmi0__addr_i$next[3:0]$6076
- attribute \src "libresoc.v:138330.5-138330.29"
+ assign $0\dmi0__addr_i$next[3:0]$5998 $4\dmi0__addr_i$next[3:0]$6002
+ attribute \src "libresoc.v:136460.5-136460.29"
switch \initial
- attribute \src "libresoc.v:138330.9-138330.17"
+ attribute \src "libresoc.v:136460.9-136460.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0__addr_i$next[3:0]$6073 $2\dmi0__addr_i$next[3:0]$6074
+ assign $1\dmi0__addr_i$next[3:0]$5999 $2\dmi0__addr_i$next[3:0]$6000
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\dmi0__addr_i$next[3:0]$6074 \dmi0_addrsr__o [3:0]
+ assign $2\dmi0__addr_i$next[3:0]$6000 \dmi0_addrsr__o [3:0]
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\dmi0__addr_i$next[3:0]$6074 \$512 [3:0]
+ assign $2\dmi0__addr_i$next[3:0]$6000 \$512 [3:0]
case
- assign $2\dmi0__addr_i$next[3:0]$6074 \dmi0__addr_i
+ assign $2\dmi0__addr_i$next[3:0]$6000 \dmi0__addr_i
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\dmi0__addr_i$next[3:0]$6073 $3\dmi0__addr_i$next[3:0]$6075
+ assign $1\dmi0__addr_i$next[3:0]$5999 $3\dmi0__addr_i$next[3:0]$6001
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0__addr_i$next[3:0]$6075 \$515 [3:0]
+ assign $3\dmi0__addr_i$next[3:0]$6001 \$515 [3:0]
case
- assign $3\dmi0__addr_i$next[3:0]$6075 \dmi0__addr_i
+ assign $3\dmi0__addr_i$next[3:0]$6001 \dmi0__addr_i
end
case
- assign $1\dmi0__addr_i$next[3:0]$6073 \dmi0__addr_i
+ assign $1\dmi0__addr_i$next[3:0]$5999 \dmi0__addr_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dmi0__addr_i$next[3:0]$6076 4'0000
+ assign $4\dmi0__addr_i$next[3:0]$6002 4'0000
case
- assign $4\dmi0__addr_i$next[3:0]$6076 $1\dmi0__addr_i$next[3:0]$6073
+ assign $4\dmi0__addr_i$next[3:0]$6002 $1\dmi0__addr_i$next[3:0]$5999
end
sync always
- update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6072
+ update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5998
end
- attribute \src "libresoc.v:138362.3-138414.6"
- process $proc$libresoc.v:138362$6077
+ attribute \src "libresoc.v:136492.3-136544.6"
+ process $proc$libresoc.v:136492$6003
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$503$next[2:0]$6078 $5\fsm_state$503$next[2:0]$6083
- attribute \src "libresoc.v:138363.5-138363.29"
+ assign $0\fsm_state$503$next[2:0]$6004 $5\fsm_state$503$next[2:0]$6009
+ attribute \src "libresoc.v:136493.5-136493.29"
switch \initial
- attribute \src "libresoc.v:138363.9-138363.17"
+ attribute \src "libresoc.v:136493.9-136493.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$503$next[2:0]$6079 $2\fsm_state$503$next[2:0]$6080
+ assign $1\fsm_state$503$next[2:0]$6005 $2\fsm_state$503$next[2:0]$6006
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$503$next[2:0]$6080 3'001
+ assign $2\fsm_state$503$next[2:0]$6006 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$503$next[2:0]$6080 3'001
+ assign $2\fsm_state$503$next[2:0]$6006 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$503$next[2:0]$6080 3'010
+ assign $2\fsm_state$503$next[2:0]$6006 3'010
case
- assign $2\fsm_state$503$next[2:0]$6080 \fsm_state$503
+ assign $2\fsm_state$503$next[2:0]$6006 \fsm_state$503
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$503$next[2:0]$6079 3'011
+ assign $1\fsm_state$503$next[2:0]$6005 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$503$next[2:0]$6079 $3\fsm_state$503$next[2:0]$6081
+ assign $1\fsm_state$503$next[2:0]$6005 $3\fsm_state$503$next[2:0]$6007
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$503$next[2:0]$6081 3'000
+ assign $3\fsm_state$503$next[2:0]$6007 3'000
case
- assign $3\fsm_state$503$next[2:0]$6081 \fsm_state$503
+ assign $3\fsm_state$503$next[2:0]$6007 \fsm_state$503
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$503$next[2:0]$6079 3'100
+ assign $1\fsm_state$503$next[2:0]$6005 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$503$next[2:0]$6079 $4\fsm_state$503$next[2:0]$6082
+ assign $1\fsm_state$503$next[2:0]$6005 $4\fsm_state$503$next[2:0]$6008
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$503$next[2:0]$6082 3'001
+ assign $4\fsm_state$503$next[2:0]$6008 3'001
case
- assign $4\fsm_state$503$next[2:0]$6082 \fsm_state$503
+ assign $4\fsm_state$503$next[2:0]$6008 \fsm_state$503
end
case
- assign $1\fsm_state$503$next[2:0]$6079 \fsm_state$503
+ assign $1\fsm_state$503$next[2:0]$6005 \fsm_state$503
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$503$next[2:0]$6083 3'000
+ assign $5\fsm_state$503$next[2:0]$6009 3'000
case
- assign $5\fsm_state$503$next[2:0]$6083 $1\fsm_state$503$next[2:0]$6079
+ assign $5\fsm_state$503$next[2:0]$6009 $1\fsm_state$503$next[2:0]$6005
end
sync always
- update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6078
+ update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6004
end
- attribute \src "libresoc.v:138415.3-138441.6"
- process $proc$libresoc.v:138415$6084
+ attribute \src "libresoc.v:136545.3-136571.6"
+ process $proc$libresoc.v:136545$6010
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0__din$next[63:0]$6085 $3\dmi0__din$next[63:0]$6088
- attribute \src "libresoc.v:138416.5-138416.29"
+ assign $0\dmi0__din$next[63:0]$6011 $3\dmi0__din$next[63:0]$6014
+ attribute \src "libresoc.v:136546.5-136546.29"
switch \initial
- attribute \src "libresoc.v:138416.9-138416.17"
+ attribute \src "libresoc.v:136546.9-136546.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0__din$next[63:0]$6086 $2\dmi0__din$next[63:0]$6087
+ assign $1\dmi0__din$next[63:0]$6012 $2\dmi0__din$next[63:0]$6013
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\dmi0__din$next[63:0]$6087 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6013 \dmi0__din
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\dmi0__din$next[63:0]$6087 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6013 \dmi0__din
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\dmi0__din$next[63:0]$6087 \dmi0_datasr__o
+ assign $2\dmi0__din$next[63:0]$6013 \dmi0_datasr__o
case
- assign $2\dmi0__din$next[63:0]$6087 \dmi0__din
+ assign $2\dmi0__din$next[63:0]$6013 \dmi0__din
end
case
- assign $1\dmi0__din$next[63:0]$6086 \dmi0__din
+ assign $1\dmi0__din$next[63:0]$6012 \dmi0__din
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0__din$next[63:0]$6088 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0__din$next[63:0]$6014 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0__din$next[63:0]$6088 $1\dmi0__din$next[63:0]$6086
+ assign $3\dmi0__din$next[63:0]$6014 $1\dmi0__din$next[63:0]$6012
end
sync always
- update \dmi0__din$next $0\dmi0__din$next[63:0]$6085
+ update \dmi0__din$next $0\dmi0__din$next[63:0]$6011
end
- attribute \src "libresoc.v:138442.3-138462.6"
- process $proc$libresoc.v:138442$6089
+ attribute \src "libresoc.v:136572.3-136592.6"
+ process $proc$libresoc.v:136572$6015
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__i$next[63:0]$6090 $3\dmi0_datasr__i$next[63:0]$6093
- attribute \src "libresoc.v:138443.5-138443.29"
+ assign $0\dmi0_datasr__i$next[63:0]$6016 $3\dmi0_datasr__i$next[63:0]$6019
+ attribute \src "libresoc.v:136573.5-136573.29"
switch \initial
- attribute \src "libresoc.v:138443.9-138443.17"
+ attribute \src "libresoc.v:136573.9-136573.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\dmi0_datasr__i$next[63:0]$6091 $2\dmi0_datasr__i$next[63:0]$6092
+ assign $1\dmi0_datasr__i$next[63:0]$6017 $2\dmi0_datasr__i$next[63:0]$6018
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
switch \dmi0__ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__i$next[63:0]$6092 \dmi0__dout
+ assign $2\dmi0_datasr__i$next[63:0]$6018 \dmi0__dout
case
- assign $2\dmi0_datasr__i$next[63:0]$6092 \dmi0_datasr__i
+ assign $2\dmi0_datasr__i$next[63:0]$6018 \dmi0_datasr__i
end
case
- assign $1\dmi0_datasr__i$next[63:0]$6091 \dmi0_datasr__i
+ assign $1\dmi0_datasr__i$next[63:0]$6017 \dmi0_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr__i$next[63:0]$6093 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr__i$next[63:0]$6019 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr__i$next[63:0]$6093 $1\dmi0_datasr__i$next[63:0]$6091
+ assign $3\dmi0_datasr__i$next[63:0]$6019 $1\dmi0_datasr__i$next[63:0]$6017
end
sync always
- update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6090
+ update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6016
end
- attribute \src "libresoc.v:138463.3-138483.6"
- process $proc$libresoc.v:138463$6094
+ attribute \src "libresoc.v:136593.3-136613.6"
+ process $proc$libresoc.v:136593$6020
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\wb_dcache_en$next[0:0]$6095 $2\wb_dcache_en$next[0:0]$6101
- assign $0\wb_icache_en$next[0:0]$6096 $2\wb_icache_en$next[0:0]$6102
- assign $0\wb_sram_en$next[0:0]$6097 $2\wb_sram_en$next[0:0]$6103
- attribute \src "libresoc.v:138464.5-138464.29"
+ assign $0\wb_dcache_en$next[0:0]$6021 $2\wb_dcache_en$next[0:0]$6027
+ assign $0\wb_icache_en$next[0:0]$6022 $2\wb_icache_en$next[0:0]$6028
+ assign $0\wb_sram_en$next[0:0]$6023 $2\wb_sram_en$next[0:0]$6029
+ attribute \src "libresoc.v:136594.5-136594.29"
switch \initial
- attribute \src "libresoc.v:138464.9-138464.17"
+ attribute \src "libresoc.v:136594.9-136594.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\wb_sram_en$next[0:0]$6100 $1\wb_dcache_en$next[0:0]$6098 $1\wb_icache_en$next[0:0]$6099 } \sr5__o
+ assign { $1\wb_sram_en$next[0:0]$6026 $1\wb_dcache_en$next[0:0]$6024 $1\wb_icache_en$next[0:0]$6025 } \sr5__o
case
- assign $1\wb_dcache_en$next[0:0]$6098 \wb_dcache_en
- assign $1\wb_icache_en$next[0:0]$6099 \wb_icache_en
- assign $1\wb_sram_en$next[0:0]$6100 \wb_sram_en
+ assign $1\wb_dcache_en$next[0:0]$6024 \wb_dcache_en
+ assign $1\wb_icache_en$next[0:0]$6025 \wb_icache_en
+ assign $1\wb_sram_en$next[0:0]$6026 \wb_sram_en
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\wb_icache_en$next[0:0]$6102 1'1
- assign $2\wb_dcache_en$next[0:0]$6101 1'1
- assign $2\wb_sram_en$next[0:0]$6103 1'1
+ assign $2\wb_icache_en$next[0:0]$6028 1'1
+ assign $2\wb_dcache_en$next[0:0]$6027 1'1
+ assign $2\wb_sram_en$next[0:0]$6029 1'1
case
- assign $2\wb_dcache_en$next[0:0]$6101 $1\wb_dcache_en$next[0:0]$6098
- assign $2\wb_icache_en$next[0:0]$6102 $1\wb_icache_en$next[0:0]$6099
- assign $2\wb_sram_en$next[0:0]$6103 $1\wb_sram_en$next[0:0]$6100
+ assign $2\wb_dcache_en$next[0:0]$6027 $1\wb_dcache_en$next[0:0]$6024
+ assign $2\wb_icache_en$next[0:0]$6028 $1\wb_icache_en$next[0:0]$6025
+ assign $2\wb_sram_en$next[0:0]$6029 $1\wb_sram_en$next[0:0]$6026
end
sync always
- update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6095
- update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6096
- update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6097
+ update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6021
+ update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6022
+ update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6023
end
- attribute \src "libresoc.v:138484.3-138493.6"
- process $proc$libresoc.v:138484$6104
+ attribute \src "libresoc.v:136614.3-136623.6"
+ process $proc$libresoc.v:136614$6030
assign { } { }
assign { } { }
assign $0\sr5__i[2:0] $1\sr5__i[2:0]
- attribute \src "libresoc.v:138485.5-138485.29"
+ attribute \src "libresoc.v:136615.5-136615.29"
switch \initial
- attribute \src "libresoc.v:138485.9-138485.17"
+ attribute \src "libresoc.v:136615.9-136615.17"
case 1'1
case
end
sync always
update \sr5__i $0\sr5__i[2:0]
end
- attribute \src "libresoc.v:138494.3-138511.6"
- process $proc$libresoc.v:138494$6105
+ attribute \src "libresoc.v:136624.3-136641.6"
+ process $proc$libresoc.v:136624$6031
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_sr$next[153:0]$6106 $2\io_sr$next[153:0]$6108
- attribute \src "libresoc.v:138495.5-138495.29"
+ assign $0\io_sr$next[153:0]$6032 $2\io_sr$next[153:0]$6034
+ attribute \src "libresoc.v:136625.5-136625.29"
switch \initial
- attribute \src "libresoc.v:138495.9-138495.17"
+ attribute \src "libresoc.v:136625.9-136625.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $1\io_sr$next[153:0]$6107 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i }
+ assign $1\io_sr$next[153:0]$6033 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i }
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $1\io_sr$next[153:0]$6107 { \io_sr [152:0] \TAP_bus__tdi }
+ assign $1\io_sr$next[153:0]$6033 { \io_sr [152:0] \TAP_bus__tdi }
case
- assign $1\io_sr$next[153:0]$6107 \io_sr
+ assign $1\io_sr$next[153:0]$6033 \io_sr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_sr$next[153:0]$6108 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $2\io_sr$next[153:0]$6034 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\io_sr$next[153:0]$6108 $1\io_sr$next[153:0]$6107
+ assign $2\io_sr$next[153:0]$6034 $1\io_sr$next[153:0]$6033
end
sync always
- update \io_sr$next $0\io_sr$next[153:0]$6106
+ update \io_sr$next $0\io_sr$next[153:0]$6032
end
- attribute \src "libresoc.v:138512.3-138532.6"
- process $proc$libresoc.v:138512$6109
+ attribute \src "libresoc.v:136642.3-136662.6"
+ process $proc$libresoc.v:136642$6035
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_bd$next[153:0]$6110 $2\io_bd$next[153:0]$6112
- attribute \src "libresoc.v:138513.5-138513.29"
+ assign $0\io_bd$next[153:0]$6036 $2\io_bd$next[153:0]$6038
+ attribute \src "libresoc.v:136643.5-136643.29"
switch \initial
- attribute \src "libresoc.v:138513.9-138513.17"
+ attribute \src "libresoc.v:136643.9-136643.17"
case 1'1
case
end
switch { \io_update \io_shift \io_capture }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $1\io_bd$next[153:0]$6111 \io_bd
+ assign $1\io_bd$next[153:0]$6037 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $1\io_bd$next[153:0]$6111 \io_bd
+ assign $1\io_bd$next[153:0]$6037 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $1\io_bd$next[153:0]$6111 \io_sr
+ assign $1\io_bd$next[153:0]$6037 \io_sr
case
- assign $1\io_bd$next[153:0]$6111 \io_bd
+ assign $1\io_bd$next[153:0]$6037 \io_bd
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \negjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_bd$next[153:0]$6112 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- case
- assign $2\io_bd$next[153:0]$6112 $1\io_bd$next[153:0]$6111
- end
- sync always
- update \io_bd$next $0\io_bd$next[153:0]$6110
- end
- connect \$9 $eq$libresoc.v:137451$5661_Y
- connect \$99 $ternary$libresoc.v:137452$5662_Y
- connect \$101 $ternary$libresoc.v:137453$5663_Y
- connect \$103 $ternary$libresoc.v:137454$5664_Y
- connect \$105 $ternary$libresoc.v:137455$5665_Y
- connect \$107 $ternary$libresoc.v:137456$5666_Y
- connect \$109 $ternary$libresoc.v:137457$5667_Y
- connect \$111 $ternary$libresoc.v:137458$5668_Y
- connect \$113 $ternary$libresoc.v:137459$5669_Y
- connect \$115 $ternary$libresoc.v:137460$5670_Y
- connect \$117 $ternary$libresoc.v:137461$5671_Y
- connect \$11 $eq$libresoc.v:137462$5672_Y
- connect \$119 $ternary$libresoc.v:137463$5673_Y
- connect \$121 $ternary$libresoc.v:137464$5674_Y
- connect \$123 $ternary$libresoc.v:137465$5675_Y
- connect \$125 $ternary$libresoc.v:137466$5676_Y
- connect \$127 $ternary$libresoc.v:137467$5677_Y
- connect \$129 $ternary$libresoc.v:137468$5678_Y
- connect \$131 $ternary$libresoc.v:137469$5679_Y
- connect \$133 $ternary$libresoc.v:137470$5680_Y
- connect \$135 $ternary$libresoc.v:137471$5681_Y
- connect \$137 $ternary$libresoc.v:137472$5682_Y
- connect \$13 $eq$libresoc.v:137473$5683_Y
- connect \$139 $ternary$libresoc.v:137474$5684_Y
- connect \$141 $ternary$libresoc.v:137475$5685_Y
- connect \$143 $ternary$libresoc.v:137476$5686_Y
- connect \$145 $ternary$libresoc.v:137477$5687_Y
- connect \$147 $ternary$libresoc.v:137478$5688_Y
- connect \$149 $ternary$libresoc.v:137479$5689_Y
- connect \$151 $ternary$libresoc.v:137480$5690_Y
- connect \$153 $ternary$libresoc.v:137481$5691_Y
- connect \$155 $ternary$libresoc.v:137482$5692_Y
- connect \$157 $ternary$libresoc.v:137483$5693_Y
- connect \$15 $or$libresoc.v:137484$5694_Y
- connect \$159 $ternary$libresoc.v:137485$5695_Y
- connect \$161 $ternary$libresoc.v:137486$5696_Y
- connect \$163 $ternary$libresoc.v:137487$5697_Y
- connect \$165 $ternary$libresoc.v:137488$5698_Y
- connect \$167 $ternary$libresoc.v:137489$5699_Y
- connect \$169 $ternary$libresoc.v:137490$5700_Y
- connect \$171 $ternary$libresoc.v:137491$5701_Y
- connect \$173 $ternary$libresoc.v:137492$5702_Y
- connect \$175 $ternary$libresoc.v:137493$5703_Y
- connect \$177 $ternary$libresoc.v:137494$5704_Y
- connect \$17 $and$libresoc.v:137495$5705_Y
- connect \$179 $ternary$libresoc.v:137496$5706_Y
- connect \$181 $ternary$libresoc.v:137497$5707_Y
- connect \$183 $ternary$libresoc.v:137498$5708_Y
- connect \$185 $ternary$libresoc.v:137499$5709_Y
- connect \$187 $ternary$libresoc.v:137500$5710_Y
- connect \$189 $ternary$libresoc.v:137501$5711_Y
- connect \$191 $ternary$libresoc.v:137502$5712_Y
- connect \$193 $ternary$libresoc.v:137503$5713_Y
- connect \$195 $ternary$libresoc.v:137504$5714_Y
- connect \$197 $ternary$libresoc.v:137505$5715_Y
- connect \$1 $eq$libresoc.v:137506$5716_Y
- connect \$19 $eq$libresoc.v:137507$5717_Y
- connect \$199 $ternary$libresoc.v:137508$5718_Y
- connect \$201 $ternary$libresoc.v:137509$5719_Y
- connect \$203 $ternary$libresoc.v:137510$5720_Y
- connect \$205 $ternary$libresoc.v:137511$5721_Y
- connect \$207 $ternary$libresoc.v:137512$5722_Y
- connect \$209 $ternary$libresoc.v:137513$5723_Y
- connect \$211 $ternary$libresoc.v:137514$5724_Y
- connect \$213 $ternary$libresoc.v:137515$5725_Y
- connect \$215 $ternary$libresoc.v:137516$5726_Y
- connect \$217 $ternary$libresoc.v:137517$5727_Y
- connect \$21 $eq$libresoc.v:137518$5728_Y
- connect \$219 $ternary$libresoc.v:137519$5729_Y
- connect \$221 $ternary$libresoc.v:137520$5730_Y
- connect \$223 $ternary$libresoc.v:137521$5731_Y
- connect \$225 $ternary$libresoc.v:137522$5732_Y
- connect \$227 $ternary$libresoc.v:137523$5733_Y
- connect \$229 $ternary$libresoc.v:137524$5734_Y
- connect \$231 $ternary$libresoc.v:137525$5735_Y
- connect \$233 $ternary$libresoc.v:137526$5736_Y
- connect \$235 $ternary$libresoc.v:137527$5737_Y
- connect \$237 $ternary$libresoc.v:137528$5738_Y
- connect \$23 $or$libresoc.v:137529$5739_Y
- connect \$239 $ternary$libresoc.v:137530$5740_Y
- connect \$241 $ternary$libresoc.v:137531$5741_Y
- connect \$243 $ternary$libresoc.v:137532$5742_Y
- connect \$245 $ternary$libresoc.v:137533$5743_Y
- connect \$247 $ternary$libresoc.v:137534$5744_Y
- connect \$249 $ternary$libresoc.v:137535$5745_Y
- connect \$251 $ternary$libresoc.v:137536$5746_Y
- connect \$253 $ternary$libresoc.v:137537$5747_Y
- connect \$255 $ternary$libresoc.v:137538$5748_Y
- connect \$257 $ternary$libresoc.v:137539$5749_Y
- connect \$25 $eq$libresoc.v:137540$5750_Y
- connect \$259 $ternary$libresoc.v:137541$5751_Y
- connect \$261 $ternary$libresoc.v:137542$5752_Y
- connect \$263 $ternary$libresoc.v:137543$5753_Y
- connect \$265 $ternary$libresoc.v:137544$5754_Y
- connect \$267 $ternary$libresoc.v:137545$5755_Y
- connect \$269 $ternary$libresoc.v:137546$5756_Y
- connect \$271 $ternary$libresoc.v:137547$5757_Y
- connect \$273 $ternary$libresoc.v:137548$5758_Y
- connect \$275 $ternary$libresoc.v:137549$5759_Y
- connect \$277 $ternary$libresoc.v:137550$5760_Y
- connect \$27 $or$libresoc.v:137551$5761_Y
- connect \$279 $ternary$libresoc.v:137552$5762_Y
- connect \$281 $ternary$libresoc.v:137553$5763_Y
- connect \$283 $ternary$libresoc.v:137554$5764_Y
- connect \$285 $ternary$libresoc.v:137555$5765_Y
- connect \$287 $ternary$libresoc.v:137556$5766_Y
- connect \$289 $ternary$libresoc.v:137557$5767_Y
- connect \$291 $ternary$libresoc.v:137558$5768_Y
- connect \$293 $ternary$libresoc.v:137559$5769_Y
- connect \$295 $ternary$libresoc.v:137560$5770_Y
- connect \$297 $ternary$libresoc.v:137561$5771_Y
- connect \$29 $and$libresoc.v:137562$5772_Y
- connect \$299 $ternary$libresoc.v:137563$5773_Y
- connect \$301 $ternary$libresoc.v:137564$5774_Y
- connect \$303 $ternary$libresoc.v:137565$5775_Y
- connect \$305 $ternary$libresoc.v:137566$5776_Y
- connect \$307 $ternary$libresoc.v:137567$5777_Y
- connect \$309 $ternary$libresoc.v:137568$5778_Y
- connect \$311 $ternary$libresoc.v:137569$5779_Y
- connect \$313 $ternary$libresoc.v:137570$5780_Y
- connect \$315 $ternary$libresoc.v:137571$5781_Y
- connect \$317 $ternary$libresoc.v:137572$5782_Y
- connect \$31 $and$libresoc.v:137573$5783_Y
- connect \$319 $ternary$libresoc.v:137574$5784_Y
- connect \$321 $ternary$libresoc.v:137575$5785_Y
- connect \$323 $ternary$libresoc.v:137576$5786_Y
- connect \$325 $ternary$libresoc.v:137577$5787_Y
- connect \$327 $ternary$libresoc.v:137578$5788_Y
- connect \$329 $ternary$libresoc.v:137579$5789_Y
- connect \$331 $ternary$libresoc.v:137580$5790_Y
- connect \$333 $ternary$libresoc.v:137581$5791_Y
- connect \$335 $ternary$libresoc.v:137582$5792_Y
- connect \$337 $ternary$libresoc.v:137583$5793_Y
- connect \$33 $eq$libresoc.v:137584$5794_Y
- connect \$339 $ternary$libresoc.v:137585$5795_Y
- connect \$341 $ternary$libresoc.v:137586$5796_Y
- connect \$343 $ternary$libresoc.v:137587$5797_Y
- connect \$345 $ternary$libresoc.v:137588$5798_Y
- connect \$347 $ternary$libresoc.v:137589$5799_Y
- connect \$349 $ternary$libresoc.v:137590$5800_Y
- connect \$351 $ternary$libresoc.v:137591$5801_Y
- connect \$353 $ternary$libresoc.v:137592$5802_Y
- connect \$355 $ternary$libresoc.v:137593$5803_Y
- connect \$357 $ternary$libresoc.v:137594$5804_Y
- connect \$35 $eq$libresoc.v:137595$5805_Y
- connect \$359 $eq$libresoc.v:137596$5806_Y
- connect \$361 $eq$libresoc.v:137597$5807_Y
- connect \$363 $or$libresoc.v:137598$5808_Y
- connect \$365 $eq$libresoc.v:137599$5809_Y
- connect \$367 $or$libresoc.v:137600$5810_Y
- connect \$369 $and$libresoc.v:137601$5811_Y
- connect \$371 $eq$libresoc.v:137602$5812_Y
- connect \$373 $ne$libresoc.v:137603$5813_Y
- connect \$375 $and$libresoc.v:137604$5814_Y
- connect \$377 $ne$libresoc.v:137605$5815_Y
- connect \$37 $or$libresoc.v:137606$5816_Y
- connect \$379 $and$libresoc.v:137607$5817_Y
- connect \$381 $ne$libresoc.v:137608$5818_Y
- connect \$383 $and$libresoc.v:137609$5819_Y
- connect \$385 $not$libresoc.v:137610$5820_Y
- connect \$387 $and$libresoc.v:137611$5821_Y
- connect \$389 $eq$libresoc.v:137612$5822_Y
- connect \$391 $ne$libresoc.v:137613$5823_Y
- connect \$393 $and$libresoc.v:137614$5824_Y
- connect \$395 $ne$libresoc.v:137615$5825_Y
- connect \$397 $and$libresoc.v:137616$5826_Y
- connect \$3 $eq$libresoc.v:137617$5827_Y
- connect \$39 $eq$libresoc.v:137618$5828_Y
- connect \$399 $ne$libresoc.v:137619$5829_Y
- connect \$401 $and$libresoc.v:137620$5830_Y
- connect \$403 $not$libresoc.v:137621$5831_Y
- connect \$405 $and$libresoc.v:137622$5832_Y
- connect \$407 $eq$libresoc.v:137623$5833_Y
- connect \$409 $eq$libresoc.v:137624$5834_Y
- connect \$411 $ne$libresoc.v:137625$5835_Y
- connect \$413 $and$libresoc.v:137626$5836_Y
- connect \$415 $ne$libresoc.v:137627$5837_Y
- connect \$417 $and$libresoc.v:137628$5838_Y
- connect \$41 $or$libresoc.v:137629$5839_Y
- connect \$419 $ne$libresoc.v:137630$5840_Y
- connect \$421 $and$libresoc.v:137631$5841_Y
- connect \$423 $not$libresoc.v:137632$5842_Y
- connect \$425 $and$libresoc.v:137633$5843_Y
- connect \$427 $eq$libresoc.v:137634$5844_Y
- connect \$429 $ne$libresoc.v:137635$5845_Y
- connect \$431 $and$libresoc.v:137636$5846_Y
- connect \$433 $ne$libresoc.v:137637$5847_Y
- connect \$435 $and$libresoc.v:137638$5848_Y
- connect \$437 $ne$libresoc.v:137639$5849_Y
- connect \$43 $and$libresoc.v:137640$5850_Y
- connect \$439 $and$libresoc.v:137641$5851_Y
- connect \$441 $not$libresoc.v:137642$5852_Y
- connect \$443 $and$libresoc.v:137643$5853_Y
- connect \$445 $eq$libresoc.v:137644$5854_Y
- connect \$447 $eq$libresoc.v:137645$5855_Y
- connect \$449 $ne$libresoc.v:137646$5856_Y
- connect \$451 $and$libresoc.v:137647$5857_Y
- connect \$453 $ne$libresoc.v:137648$5858_Y
- connect \$455 $and$libresoc.v:137649$5859_Y
- connect \$457 $ne$libresoc.v:137650$5860_Y
- connect \$45 $and$libresoc.v:137651$5861_Y
- connect \$459 $and$libresoc.v:137652$5862_Y
- connect \$461 $not$libresoc.v:137653$5863_Y
- connect \$463 $and$libresoc.v:137654$5864_Y
- connect \$465 $eq$libresoc.v:137655$5865_Y
- connect \$467 $ne$libresoc.v:137656$5866_Y
- connect \$469 $and$libresoc.v:137657$5867_Y
- connect \$471 $ne$libresoc.v:137658$5868_Y
- connect \$473 $and$libresoc.v:137659$5869_Y
- connect \$475 $ne$libresoc.v:137660$5870_Y
- connect \$477 $and$libresoc.v:137661$5871_Y
- connect \$47 $eq$libresoc.v:137662$5872_Y
- connect \$479 $not$libresoc.v:137663$5873_Y
- connect \$481 $and$libresoc.v:137664$5874_Y
- connect \$484 $eq$libresoc.v:137665$5875_Y
- connect \$483 $not$libresoc.v:137666$5876_Y
- connect \$487 $eq$libresoc.v:137667$5877_Y
- connect \$489 $eq$libresoc.v:137668$5878_Y
- connect \$491 $or$libresoc.v:137669$5879_Y
- connect \$493 $eq$libresoc.v:137670$5880_Y
- connect \$496 $add$libresoc.v:137671$5881_Y
- connect \$49 $eq$libresoc.v:137672$5882_Y
- connect \$499 $add$libresoc.v:137673$5883_Y
- connect \$501 $pos$libresoc.v:137674$5885_Y
- connect \$504 $eq$libresoc.v:137675$5886_Y
- connect \$506 $eq$libresoc.v:137676$5887_Y
- connect \$508 $or$libresoc.v:137677$5888_Y
- connect \$510 $eq$libresoc.v:137678$5889_Y
- connect \$513 $add$libresoc.v:137679$5890_Y
- connect \$516 $add$libresoc.v:137680$5891_Y
- connect \$51 $ternary$libresoc.v:137681$5892_Y
- connect \$53 $ternary$libresoc.v:137682$5893_Y
- connect \$55 $ternary$libresoc.v:137683$5894_Y
- connect \$57 $ternary$libresoc.v:137684$5895_Y
- connect \$5 $or$libresoc.v:137685$5896_Y
- connect \$59 $ternary$libresoc.v:137686$5897_Y
- connect \$61 $ternary$libresoc.v:137687$5898_Y
- connect \$63 $ternary$libresoc.v:137688$5899_Y
- connect \$65 $ternary$libresoc.v:137689$5900_Y
- connect \$67 $ternary$libresoc.v:137690$5901_Y
- connect \$69 $ternary$libresoc.v:137691$5902_Y
- connect \$71 $ternary$libresoc.v:137692$5903_Y
- connect \$73 $ternary$libresoc.v:137693$5904_Y
- connect \$75 $ternary$libresoc.v:137694$5905_Y
- connect \$77 $ternary$libresoc.v:137695$5906_Y
- connect \$7 $and$libresoc.v:137696$5907_Y
- connect \$79 $ternary$libresoc.v:137697$5908_Y
- connect \$81 $ternary$libresoc.v:137698$5909_Y
- connect \$83 $ternary$libresoc.v:137699$5910_Y
- connect \$85 $ternary$libresoc.v:137700$5911_Y
- connect \$87 $ternary$libresoc.v:137701$5912_Y
- connect \$89 $ternary$libresoc.v:137702$5913_Y
- connect \$91 $ternary$libresoc.v:137703$5914_Y
- connect \$93 $ternary$libresoc.v:137704$5915_Y
- connect \$95 $ternary$libresoc.v:137705$5916_Y
- connect \$97 $ternary$libresoc.v:137706$5917_Y
+ assign $2\io_bd$next[153:0]$6038 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ case
+ assign $2\io_bd$next[153:0]$6038 $1\io_bd$next[153:0]$6037
+ end
+ sync always
+ update \io_bd$next $0\io_bd$next[153:0]$6036
+ end
+ connect \$9 $eq$libresoc.v:135581$5587_Y
+ connect \$99 $ternary$libresoc.v:135582$5588_Y
+ connect \$101 $ternary$libresoc.v:135583$5589_Y
+ connect \$103 $ternary$libresoc.v:135584$5590_Y
+ connect \$105 $ternary$libresoc.v:135585$5591_Y
+ connect \$107 $ternary$libresoc.v:135586$5592_Y
+ connect \$109 $ternary$libresoc.v:135587$5593_Y
+ connect \$111 $ternary$libresoc.v:135588$5594_Y
+ connect \$113 $ternary$libresoc.v:135589$5595_Y
+ connect \$115 $ternary$libresoc.v:135590$5596_Y
+ connect \$117 $ternary$libresoc.v:135591$5597_Y
+ connect \$11 $eq$libresoc.v:135592$5598_Y
+ connect \$119 $ternary$libresoc.v:135593$5599_Y
+ connect \$121 $ternary$libresoc.v:135594$5600_Y
+ connect \$123 $ternary$libresoc.v:135595$5601_Y
+ connect \$125 $ternary$libresoc.v:135596$5602_Y
+ connect \$127 $ternary$libresoc.v:135597$5603_Y
+ connect \$129 $ternary$libresoc.v:135598$5604_Y
+ connect \$131 $ternary$libresoc.v:135599$5605_Y
+ connect \$133 $ternary$libresoc.v:135600$5606_Y
+ connect \$135 $ternary$libresoc.v:135601$5607_Y
+ connect \$137 $ternary$libresoc.v:135602$5608_Y
+ connect \$13 $eq$libresoc.v:135603$5609_Y
+ connect \$139 $ternary$libresoc.v:135604$5610_Y
+ connect \$141 $ternary$libresoc.v:135605$5611_Y
+ connect \$143 $ternary$libresoc.v:135606$5612_Y
+ connect \$145 $ternary$libresoc.v:135607$5613_Y
+ connect \$147 $ternary$libresoc.v:135608$5614_Y
+ connect \$149 $ternary$libresoc.v:135609$5615_Y
+ connect \$151 $ternary$libresoc.v:135610$5616_Y
+ connect \$153 $ternary$libresoc.v:135611$5617_Y
+ connect \$155 $ternary$libresoc.v:135612$5618_Y
+ connect \$157 $ternary$libresoc.v:135613$5619_Y
+ connect \$15 $or$libresoc.v:135614$5620_Y
+ connect \$159 $ternary$libresoc.v:135615$5621_Y
+ connect \$161 $ternary$libresoc.v:135616$5622_Y
+ connect \$163 $ternary$libresoc.v:135617$5623_Y
+ connect \$165 $ternary$libresoc.v:135618$5624_Y
+ connect \$167 $ternary$libresoc.v:135619$5625_Y
+ connect \$169 $ternary$libresoc.v:135620$5626_Y
+ connect \$171 $ternary$libresoc.v:135621$5627_Y
+ connect \$173 $ternary$libresoc.v:135622$5628_Y
+ connect \$175 $ternary$libresoc.v:135623$5629_Y
+ connect \$177 $ternary$libresoc.v:135624$5630_Y
+ connect \$17 $and$libresoc.v:135625$5631_Y
+ connect \$179 $ternary$libresoc.v:135626$5632_Y
+ connect \$181 $ternary$libresoc.v:135627$5633_Y
+ connect \$183 $ternary$libresoc.v:135628$5634_Y
+ connect \$185 $ternary$libresoc.v:135629$5635_Y
+ connect \$187 $ternary$libresoc.v:135630$5636_Y
+ connect \$189 $ternary$libresoc.v:135631$5637_Y
+ connect \$191 $ternary$libresoc.v:135632$5638_Y
+ connect \$193 $ternary$libresoc.v:135633$5639_Y
+ connect \$195 $ternary$libresoc.v:135634$5640_Y
+ connect \$197 $ternary$libresoc.v:135635$5641_Y
+ connect \$1 $eq$libresoc.v:135636$5642_Y
+ connect \$19 $eq$libresoc.v:135637$5643_Y
+ connect \$199 $ternary$libresoc.v:135638$5644_Y
+ connect \$201 $ternary$libresoc.v:135639$5645_Y
+ connect \$203 $ternary$libresoc.v:135640$5646_Y
+ connect \$205 $ternary$libresoc.v:135641$5647_Y
+ connect \$207 $ternary$libresoc.v:135642$5648_Y
+ connect \$209 $ternary$libresoc.v:135643$5649_Y
+ connect \$211 $ternary$libresoc.v:135644$5650_Y
+ connect \$213 $ternary$libresoc.v:135645$5651_Y
+ connect \$215 $ternary$libresoc.v:135646$5652_Y
+ connect \$217 $ternary$libresoc.v:135647$5653_Y
+ connect \$21 $eq$libresoc.v:135648$5654_Y
+ connect \$219 $ternary$libresoc.v:135649$5655_Y
+ connect \$221 $ternary$libresoc.v:135650$5656_Y
+ connect \$223 $ternary$libresoc.v:135651$5657_Y
+ connect \$225 $ternary$libresoc.v:135652$5658_Y
+ connect \$227 $ternary$libresoc.v:135653$5659_Y
+ connect \$229 $ternary$libresoc.v:135654$5660_Y
+ connect \$231 $ternary$libresoc.v:135655$5661_Y
+ connect \$233 $ternary$libresoc.v:135656$5662_Y
+ connect \$235 $ternary$libresoc.v:135657$5663_Y
+ connect \$237 $ternary$libresoc.v:135658$5664_Y
+ connect \$23 $or$libresoc.v:135659$5665_Y
+ connect \$239 $ternary$libresoc.v:135660$5666_Y
+ connect \$241 $ternary$libresoc.v:135661$5667_Y
+ connect \$243 $ternary$libresoc.v:135662$5668_Y
+ connect \$245 $ternary$libresoc.v:135663$5669_Y
+ connect \$247 $ternary$libresoc.v:135664$5670_Y
+ connect \$249 $ternary$libresoc.v:135665$5671_Y
+ connect \$251 $ternary$libresoc.v:135666$5672_Y
+ connect \$253 $ternary$libresoc.v:135667$5673_Y
+ connect \$255 $ternary$libresoc.v:135668$5674_Y
+ connect \$257 $ternary$libresoc.v:135669$5675_Y
+ connect \$25 $eq$libresoc.v:135670$5676_Y
+ connect \$259 $ternary$libresoc.v:135671$5677_Y
+ connect \$261 $ternary$libresoc.v:135672$5678_Y
+ connect \$263 $ternary$libresoc.v:135673$5679_Y
+ connect \$265 $ternary$libresoc.v:135674$5680_Y
+ connect \$267 $ternary$libresoc.v:135675$5681_Y
+ connect \$269 $ternary$libresoc.v:135676$5682_Y
+ connect \$271 $ternary$libresoc.v:135677$5683_Y
+ connect \$273 $ternary$libresoc.v:135678$5684_Y
+ connect \$275 $ternary$libresoc.v:135679$5685_Y
+ connect \$277 $ternary$libresoc.v:135680$5686_Y
+ connect \$27 $or$libresoc.v:135681$5687_Y
+ connect \$279 $ternary$libresoc.v:135682$5688_Y
+ connect \$281 $ternary$libresoc.v:135683$5689_Y
+ connect \$283 $ternary$libresoc.v:135684$5690_Y
+ connect \$285 $ternary$libresoc.v:135685$5691_Y
+ connect \$287 $ternary$libresoc.v:135686$5692_Y
+ connect \$289 $ternary$libresoc.v:135687$5693_Y
+ connect \$291 $ternary$libresoc.v:135688$5694_Y
+ connect \$293 $ternary$libresoc.v:135689$5695_Y
+ connect \$295 $ternary$libresoc.v:135690$5696_Y
+ connect \$297 $ternary$libresoc.v:135691$5697_Y
+ connect \$29 $and$libresoc.v:135692$5698_Y
+ connect \$299 $ternary$libresoc.v:135693$5699_Y
+ connect \$301 $ternary$libresoc.v:135694$5700_Y
+ connect \$303 $ternary$libresoc.v:135695$5701_Y
+ connect \$305 $ternary$libresoc.v:135696$5702_Y
+ connect \$307 $ternary$libresoc.v:135697$5703_Y
+ connect \$309 $ternary$libresoc.v:135698$5704_Y
+ connect \$311 $ternary$libresoc.v:135699$5705_Y
+ connect \$313 $ternary$libresoc.v:135700$5706_Y
+ connect \$315 $ternary$libresoc.v:135701$5707_Y
+ connect \$317 $ternary$libresoc.v:135702$5708_Y
+ connect \$31 $and$libresoc.v:135703$5709_Y
+ connect \$319 $ternary$libresoc.v:135704$5710_Y
+ connect \$321 $ternary$libresoc.v:135705$5711_Y
+ connect \$323 $ternary$libresoc.v:135706$5712_Y
+ connect \$325 $ternary$libresoc.v:135707$5713_Y
+ connect \$327 $ternary$libresoc.v:135708$5714_Y
+ connect \$329 $ternary$libresoc.v:135709$5715_Y
+ connect \$331 $ternary$libresoc.v:135710$5716_Y
+ connect \$333 $ternary$libresoc.v:135711$5717_Y
+ connect \$335 $ternary$libresoc.v:135712$5718_Y
+ connect \$337 $ternary$libresoc.v:135713$5719_Y
+ connect \$33 $eq$libresoc.v:135714$5720_Y
+ connect \$339 $ternary$libresoc.v:135715$5721_Y
+ connect \$341 $ternary$libresoc.v:135716$5722_Y
+ connect \$343 $ternary$libresoc.v:135717$5723_Y
+ connect \$345 $ternary$libresoc.v:135718$5724_Y
+ connect \$347 $ternary$libresoc.v:135719$5725_Y
+ connect \$349 $ternary$libresoc.v:135720$5726_Y
+ connect \$351 $ternary$libresoc.v:135721$5727_Y
+ connect \$353 $ternary$libresoc.v:135722$5728_Y
+ connect \$355 $ternary$libresoc.v:135723$5729_Y
+ connect \$357 $ternary$libresoc.v:135724$5730_Y
+ connect \$35 $eq$libresoc.v:135725$5731_Y
+ connect \$359 $eq$libresoc.v:135726$5732_Y
+ connect \$361 $eq$libresoc.v:135727$5733_Y
+ connect \$363 $or$libresoc.v:135728$5734_Y
+ connect \$365 $eq$libresoc.v:135729$5735_Y
+ connect \$367 $or$libresoc.v:135730$5736_Y
+ connect \$369 $and$libresoc.v:135731$5737_Y
+ connect \$371 $eq$libresoc.v:135732$5738_Y
+ connect \$373 $ne$libresoc.v:135733$5739_Y
+ connect \$375 $and$libresoc.v:135734$5740_Y
+ connect \$377 $ne$libresoc.v:135735$5741_Y
+ connect \$37 $or$libresoc.v:135736$5742_Y
+ connect \$379 $and$libresoc.v:135737$5743_Y
+ connect \$381 $ne$libresoc.v:135738$5744_Y
+ connect \$383 $and$libresoc.v:135739$5745_Y
+ connect \$385 $not$libresoc.v:135740$5746_Y
+ connect \$387 $and$libresoc.v:135741$5747_Y
+ connect \$389 $eq$libresoc.v:135742$5748_Y
+ connect \$391 $ne$libresoc.v:135743$5749_Y
+ connect \$393 $and$libresoc.v:135744$5750_Y
+ connect \$395 $ne$libresoc.v:135745$5751_Y
+ connect \$397 $and$libresoc.v:135746$5752_Y
+ connect \$3 $eq$libresoc.v:135747$5753_Y
+ connect \$39 $eq$libresoc.v:135748$5754_Y
+ connect \$399 $ne$libresoc.v:135749$5755_Y
+ connect \$401 $and$libresoc.v:135750$5756_Y
+ connect \$403 $not$libresoc.v:135751$5757_Y
+ connect \$405 $and$libresoc.v:135752$5758_Y
+ connect \$407 $eq$libresoc.v:135753$5759_Y
+ connect \$409 $eq$libresoc.v:135754$5760_Y
+ connect \$411 $ne$libresoc.v:135755$5761_Y
+ connect \$413 $and$libresoc.v:135756$5762_Y
+ connect \$415 $ne$libresoc.v:135757$5763_Y
+ connect \$417 $and$libresoc.v:135758$5764_Y
+ connect \$41 $or$libresoc.v:135759$5765_Y
+ connect \$419 $ne$libresoc.v:135760$5766_Y
+ connect \$421 $and$libresoc.v:135761$5767_Y
+ connect \$423 $not$libresoc.v:135762$5768_Y
+ connect \$425 $and$libresoc.v:135763$5769_Y
+ connect \$427 $eq$libresoc.v:135764$5770_Y
+ connect \$429 $ne$libresoc.v:135765$5771_Y
+ connect \$431 $and$libresoc.v:135766$5772_Y
+ connect \$433 $ne$libresoc.v:135767$5773_Y
+ connect \$435 $and$libresoc.v:135768$5774_Y
+ connect \$437 $ne$libresoc.v:135769$5775_Y
+ connect \$43 $and$libresoc.v:135770$5776_Y
+ connect \$439 $and$libresoc.v:135771$5777_Y
+ connect \$441 $not$libresoc.v:135772$5778_Y
+ connect \$443 $and$libresoc.v:135773$5779_Y
+ connect \$445 $eq$libresoc.v:135774$5780_Y
+ connect \$447 $eq$libresoc.v:135775$5781_Y
+ connect \$449 $ne$libresoc.v:135776$5782_Y
+ connect \$451 $and$libresoc.v:135777$5783_Y
+ connect \$453 $ne$libresoc.v:135778$5784_Y
+ connect \$455 $and$libresoc.v:135779$5785_Y
+ connect \$457 $ne$libresoc.v:135780$5786_Y
+ connect \$45 $and$libresoc.v:135781$5787_Y
+ connect \$459 $and$libresoc.v:135782$5788_Y
+ connect \$461 $not$libresoc.v:135783$5789_Y
+ connect \$463 $and$libresoc.v:135784$5790_Y
+ connect \$465 $eq$libresoc.v:135785$5791_Y
+ connect \$467 $ne$libresoc.v:135786$5792_Y
+ connect \$469 $and$libresoc.v:135787$5793_Y
+ connect \$471 $ne$libresoc.v:135788$5794_Y
+ connect \$473 $and$libresoc.v:135789$5795_Y
+ connect \$475 $ne$libresoc.v:135790$5796_Y
+ connect \$477 $and$libresoc.v:135791$5797_Y
+ connect \$47 $eq$libresoc.v:135792$5798_Y
+ connect \$479 $not$libresoc.v:135793$5799_Y
+ connect \$481 $and$libresoc.v:135794$5800_Y
+ connect \$484 $eq$libresoc.v:135795$5801_Y
+ connect \$483 $not$libresoc.v:135796$5802_Y
+ connect \$487 $eq$libresoc.v:135797$5803_Y
+ connect \$489 $eq$libresoc.v:135798$5804_Y
+ connect \$491 $or$libresoc.v:135799$5805_Y
+ connect \$493 $eq$libresoc.v:135800$5806_Y
+ connect \$496 $add$libresoc.v:135801$5807_Y
+ connect \$49 $eq$libresoc.v:135802$5808_Y
+ connect \$499 $add$libresoc.v:135803$5809_Y
+ connect \$501 $pos$libresoc.v:135804$5811_Y
+ connect \$504 $eq$libresoc.v:135805$5812_Y
+ connect \$506 $eq$libresoc.v:135806$5813_Y
+ connect \$508 $or$libresoc.v:135807$5814_Y
+ connect \$510 $eq$libresoc.v:135808$5815_Y
+ connect \$513 $add$libresoc.v:135809$5816_Y
+ connect \$516 $add$libresoc.v:135810$5817_Y
+ connect \$51 $ternary$libresoc.v:135811$5818_Y
+ connect \$53 $ternary$libresoc.v:135812$5819_Y
+ connect \$55 $ternary$libresoc.v:135813$5820_Y
+ connect \$57 $ternary$libresoc.v:135814$5821_Y
+ connect \$5 $or$libresoc.v:135815$5822_Y
+ connect \$59 $ternary$libresoc.v:135816$5823_Y
+ connect \$61 $ternary$libresoc.v:135817$5824_Y
+ connect \$63 $ternary$libresoc.v:135818$5825_Y
+ connect \$65 $ternary$libresoc.v:135819$5826_Y
+ connect \$67 $ternary$libresoc.v:135820$5827_Y
+ connect \$69 $ternary$libresoc.v:135821$5828_Y
+ connect \$71 $ternary$libresoc.v:135822$5829_Y
+ connect \$73 $ternary$libresoc.v:135823$5830_Y
+ connect \$75 $ternary$libresoc.v:135824$5831_Y
+ connect \$77 $ternary$libresoc.v:135825$5832_Y
+ connect \$7 $and$libresoc.v:135826$5833_Y
+ connect \$79 $ternary$libresoc.v:135827$5834_Y
+ connect \$81 $ternary$libresoc.v:135828$5835_Y
+ connect \$83 $ternary$libresoc.v:135829$5836_Y
+ connect \$85 $ternary$libresoc.v:135830$5837_Y
+ connect \$87 $ternary$libresoc.v:135831$5838_Y
+ connect \$89 $ternary$libresoc.v:135832$5839_Y
+ connect \$91 $ternary$libresoc.v:135833$5840_Y
+ connect \$93 $ternary$libresoc.v:135834$5841_Y
+ connect \$95 $ternary$libresoc.v:135835$5842_Y
+ connect \$97 $ternary$libresoc.v:135836$5843_Y
connect \$495 \$496
connect \$498 \$499
connect \$512 \$513
connect \_idblock_id_bypass \$9
connect \_idblock_select_id \$7
end
-attribute \src "libresoc.v:138742.1-138931.10"
+attribute \src "libresoc.v:136872.1-137061.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0"
attribute \generator "nMigen"
module \l0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 23 \dbus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
wire input 21 \wb_dcache_en
attribute \module_not_derived 1
- attribute \src "libresoc.v:138847.12-138881.4"
+ attribute \src "libresoc.v:136977.12-137011.4"
cell \l0$130 \l0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:138882.9-138904.4"
+ attribute \src "libresoc.v:137012.9-137034.4"
cell \lsmem \lsmem
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \x_valid_i \pimem_x_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:138905.9-138929.4"
+ attribute \src "libresoc.v:137035.9-137059.4"
cell \pimem \pimem
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
end
connect \pimem_ldst_port0_exc_$signal 1'0
end
-attribute \src "libresoc.v:138935.1-139343.10"
+attribute \src "libresoc.v:137065.1-137473.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0"
attribute \generator "nMigen"
module \l0$130
- attribute \src "libresoc.v:139198.3-139212.6"
- wire $0\idx_l$23$next[0:0]$6191
- attribute \src "libresoc.v:139098.3-139099.35"
- wire $0\idx_l$23[0:0]$6158
- attribute \src "libresoc.v:138956.7-138956.24"
- wire $0\idx_l$23[0:0]$6213
- attribute \src "libresoc.v:139253.3-139262.6"
+ attribute \src "libresoc.v:137328.3-137342.6"
+ wire $0\idx_l$23$next[0:0]$6117
+ attribute \src "libresoc.v:137228.3-137229.35"
+ wire $0\idx_l$23[0:0]$6084
+ attribute \src "libresoc.v:137086.7-137086.24"
+ wire $0\idx_l$23[0:0]$6139
+ attribute \src "libresoc.v:137383.3-137392.6"
wire $0\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:139243.3-139252.6"
+ attribute \src "libresoc.v:137373.3-137382.6"
wire $0\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:138936.7-138936.20"
+ attribute \src "libresoc.v:137066.7-137066.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:139119.3-139128.6"
- wire width 48 $0\ldst_port0_addr_i$12[47:0]$6160
- attribute \src "libresoc.v:139129.3-139138.6"
- wire $0\ldst_port0_addr_i_ok$13[0:0]$6163
- attribute \src "libresoc.v:139171.3-139180.6"
+ attribute \src "libresoc.v:137249.3-137258.6"
+ wire width 48 $0\ldst_port0_addr_i$12[47:0]$6086
+ attribute \src "libresoc.v:137259.3-137268.6"
+ wire $0\ldst_port0_addr_i_ok$13[0:0]$6089
+ attribute \src "libresoc.v:137301.3-137310.6"
wire $0\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:139161.3-139170.6"
+ attribute \src "libresoc.v:137291.3-137300.6"
wire $0\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:139233.3-139242.6"
+ attribute \src "libresoc.v:137363.3-137372.6"
wire $0\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:139308.3-139317.6"
- wire width 4 $0\ldst_port0_data_len$11[3:0]$6208
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$1[0:0]$6175
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$2[0:0]$6176
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$3[0:0]$6177
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$4[0:0]$6178
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$5[0:0]$6179
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$6[0:0]$6180
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal$7[0:0]$6181
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $0\ldst_port0_exc_$signal[0:0]$6174
- attribute \src "libresoc.v:139318.3-139327.6"
+ attribute \src "libresoc.v:137438.3-137447.6"
+ wire width 4 $0\ldst_port0_data_len$11[3:0]$6134
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$1[0:0]$6101
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$2[0:0]$6102
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$3[0:0]$6103
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$4[0:0]$6104
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$5[0:0]$6105
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$6[0:0]$6106
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal$7[0:0]$6107
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $0\ldst_port0_exc_$signal[0:0]$6100
+ attribute \src "libresoc.v:137448.3-137457.6"
wire $0\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:139288.3-139297.6"
- wire $0\ldst_port0_is_ld_i$8[0:0]$6202
- attribute \src "libresoc.v:139298.3-139307.6"
- wire $0\ldst_port0_is_st_i$9[0:0]$6205
- attribute \src "libresoc.v:139150.3-139160.6"
+ attribute \src "libresoc.v:137418.3-137427.6"
+ wire $0\ldst_port0_is_ld_i$8[0:0]$6128
+ attribute \src "libresoc.v:137428.3-137437.6"
+ wire $0\ldst_port0_is_st_i$9[0:0]$6131
+ attribute \src "libresoc.v:137280.3-137290.6"
wire width 64 $0\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:139150.3-139160.6"
+ attribute \src "libresoc.v:137280.3-137290.6"
wire $0\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:139223.3-139232.6"
+ attribute \src "libresoc.v:137353.3-137362.6"
wire $0\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:139213.3-139222.6"
+ attribute \src "libresoc.v:137343.3-137352.6"
wire $0\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:139139.3-139149.6"
- wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6166
- attribute \src "libresoc.v:139139.3-139149.6"
- wire $0\ldst_port0_st_data_i_ok$17[0:0]$6167
- attribute \src "libresoc.v:139096.3-139097.36"
+ attribute \src "libresoc.v:137269.3-137279.6"
+ wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6092
+ attribute \src "libresoc.v:137269.3-137279.6"
+ wire $0\ldst_port0_st_data_i_ok$17[0:0]$6093
+ attribute \src "libresoc.v:137226.3-137227.36"
wire $0\reset_delay[0:0]
- attribute \src "libresoc.v:139278.3-139287.6"
+ attribute \src "libresoc.v:137408.3-137417.6"
wire $0\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:139263.3-139277.6"
+ attribute \src "libresoc.v:137393.3-137407.6"
wire $0\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:139198.3-139212.6"
- wire $1\idx_l$23$next[0:0]$6192
- attribute \src "libresoc.v:139253.3-139262.6"
+ attribute \src "libresoc.v:137328.3-137342.6"
+ wire $1\idx_l$23$next[0:0]$6118
+ attribute \src "libresoc.v:137383.3-137392.6"
wire $1\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:139243.3-139252.6"
+ attribute \src "libresoc.v:137373.3-137382.6"
wire $1\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:139119.3-139128.6"
- wire width 48 $1\ldst_port0_addr_i$12[47:0]$6161
- attribute \src "libresoc.v:139129.3-139138.6"
- wire $1\ldst_port0_addr_i_ok$13[0:0]$6164
- attribute \src "libresoc.v:139171.3-139180.6"
+ attribute \src "libresoc.v:137249.3-137258.6"
+ wire width 48 $1\ldst_port0_addr_i$12[47:0]$6087
+ attribute \src "libresoc.v:137259.3-137268.6"
+ wire $1\ldst_port0_addr_i_ok$13[0:0]$6090
+ attribute \src "libresoc.v:137301.3-137310.6"
wire $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:139161.3-139170.6"
+ attribute \src "libresoc.v:137291.3-137300.6"
wire $1\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:139233.3-139242.6"
+ attribute \src "libresoc.v:137363.3-137372.6"
wire $1\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:139308.3-139317.6"
- wire width 4 $1\ldst_port0_data_len$11[3:0]$6209
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$1[0:0]$6183
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$2[0:0]$6184
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$3[0:0]$6185
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$4[0:0]$6186
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$5[0:0]$6187
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$6[0:0]$6188
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal$7[0:0]$6189
- attribute \src "libresoc.v:139181.3-139197.6"
- wire $1\ldst_port0_exc_$signal[0:0]$6182
- attribute \src "libresoc.v:139318.3-139327.6"
+ attribute \src "libresoc.v:137438.3-137447.6"
+ wire width 4 $1\ldst_port0_data_len$11[3:0]$6135
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$1[0:0]$6109
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$2[0:0]$6110
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$3[0:0]$6111
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$4[0:0]$6112
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$5[0:0]$6113
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$6[0:0]$6114
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal$7[0:0]$6115
+ attribute \src "libresoc.v:137311.3-137327.6"
+ wire $1\ldst_port0_exc_$signal[0:0]$6108
+ attribute \src "libresoc.v:137448.3-137457.6"
wire $1\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:139288.3-139297.6"
- wire $1\ldst_port0_is_ld_i$8[0:0]$6203
- attribute \src "libresoc.v:139298.3-139307.6"
- wire $1\ldst_port0_is_st_i$9[0:0]$6206
- attribute \src "libresoc.v:139150.3-139160.6"
+ attribute \src "libresoc.v:137418.3-137427.6"
+ wire $1\ldst_port0_is_ld_i$8[0:0]$6129
+ attribute \src "libresoc.v:137428.3-137437.6"
+ wire $1\ldst_port0_is_st_i$9[0:0]$6132
+ attribute \src "libresoc.v:137280.3-137290.6"
wire width 64 $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:139150.3-139160.6"
+ attribute \src "libresoc.v:137280.3-137290.6"
wire $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:139223.3-139232.6"
+ attribute \src "libresoc.v:137353.3-137362.6"
wire $1\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:139213.3-139222.6"
+ attribute \src "libresoc.v:137343.3-137352.6"
wire $1\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:139139.3-139149.6"
- wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6168
- attribute \src "libresoc.v:139139.3-139149.6"
- wire $1\ldst_port0_st_data_i_ok$17[0:0]$6169
- attribute \src "libresoc.v:139083.7-139083.25"
+ attribute \src "libresoc.v:137269.3-137279.6"
+ wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6094
+ attribute \src "libresoc.v:137269.3-137279.6"
+ wire $1\ldst_port0_st_data_i_ok$17[0:0]$6095
+ attribute \src "libresoc.v:137213.7-137213.25"
wire $1\reset_delay[0:0]
- attribute \src "libresoc.v:139278.3-139287.6"
+ attribute \src "libresoc.v:137408.3-137417.6"
wire $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:139263.3-139277.6"
+ attribute \src "libresoc.v:137393.3-137407.6"
wire $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:139198.3-139212.6"
- wire $2\idx_l$23$next[0:0]$6193
- attribute \src "libresoc.v:139263.3-139277.6"
+ attribute \src "libresoc.v:137328.3-137342.6"
+ wire $2\idx_l$23$next[0:0]$6119
+ attribute \src "libresoc.v:137393.3-137407.6"
wire $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:139094.18-139094.103"
- wire $not$libresoc.v:139094$6154_Y
- attribute \src "libresoc.v:139095.18-139095.118"
- wire $not$libresoc.v:139095$6155_Y
- attribute \src "libresoc.v:139092.18-139092.134"
- wire $or$libresoc.v:139092$6152_Y
- attribute \src "libresoc.v:139093.18-139093.120"
- wire $ternary$libresoc.v:139093$6153_Y
+ attribute \src "libresoc.v:137224.18-137224.103"
+ wire $not$libresoc.v:137224$6080_Y
+ attribute \src "libresoc.v:137225.18-137225.118"
+ wire $not$libresoc.v:137225$6081_Y
+ attribute \src "libresoc.v:137222.18-137222.134"
+ wire $or$libresoc.v:137222$6078_Y
+ attribute \src "libresoc.v:137223.18-137223.120"
+ wire $ternary$libresoc.v:137223$6079_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262"
wire \$20
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
wire width 96 \$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136"
wire width 96 \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
wire \idx_l$23
wire \idx_l_r_idx_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \idx_l_s_idx_l
- attribute \src "libresoc.v:138936.7-138936.15"
+ attribute \src "libresoc.v:137066.7-137066.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 96 input 6 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \reset_l_s_reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278"
- cell $not $not$libresoc.v:139094$6154
+ cell $not $not$libresoc.v:137224$6080
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pick_n
- connect \Y $not$libresoc.v:139094$6154_Y
+ connect \Y $not$libresoc.v:137224$6080_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288"
- cell $not $not$libresoc.v:139095$6155
+ cell $not $not$libresoc.v:137225$6081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o$10
- connect \Y $not$libresoc.v:139095$6155_Y
+ connect \Y $not$libresoc.v:137225$6081_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262"
- cell $or $or$libresoc.v:139092$6152
+ cell $or $or$libresoc.v:137222$6078
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:139092$6152_Y
+ connect \Y $or$libresoc.v:137222$6078_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:139093$6153
+ cell $mux $ternary$libresoc.v:137223$6079
parameter \WIDTH 1
connect \A \idx_l$23
connect \B \pick_o
connect \S \idx_l_q_idx_l
- connect \Y $ternary$libresoc.v:139093$6153_Y
+ connect \Y $ternary$libresoc.v:137223$6079_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:139100.9-139106.4"
+ attribute \src "libresoc.v:137230.9-137236.4"
cell \idx_l \idx_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_idx_l \idx_l_s_idx_l
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:139107.8-139111.4"
+ attribute \src "libresoc.v:137237.8-137241.4"
cell \pick \pick
connect \i \pick_i
connect \n \pick_n
connect \o \pick_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:139112.17-139118.4"
+ attribute \src "libresoc.v:137242.17-137248.4"
cell \reset_l$131 \reset_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_reset \reset_l_r_reset
connect \s_reset \reset_l_s_reset
end
- attribute \src "libresoc.v:138936.7-138936.20"
- process $proc$libresoc.v:138936$6211
+ attribute \src "libresoc.v:137066.7-137066.20"
+ process $proc$libresoc.v:137066$6137
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:138956.7-138956.24"
- process $proc$libresoc.v:138956$6212
+ attribute \src "libresoc.v:137086.7-137086.24"
+ process $proc$libresoc.v:137086$6138
assign { } { }
- assign $0\idx_l$23[0:0]$6213 1'0
+ assign $0\idx_l$23[0:0]$6139 1'0
sync always
sync init
- update \idx_l$23 $0\idx_l$23[0:0]$6213
+ update \idx_l$23 $0\idx_l$23[0:0]$6139
end
- attribute \src "libresoc.v:139083.7-139083.25"
- process $proc$libresoc.v:139083$6214
+ attribute \src "libresoc.v:137213.7-137213.25"
+ process $proc$libresoc.v:137213$6140
assign { } { }
assign $1\reset_delay[0:0] 1'0
sync always
sync init
update \reset_delay $1\reset_delay[0:0]
end
- attribute \src "libresoc.v:139096.3-139097.36"
- process $proc$libresoc.v:139096$6156
+ attribute \src "libresoc.v:137226.3-137227.36"
+ process $proc$libresoc.v:137226$6082
assign { } { }
assign $0\reset_delay[0:0] \reset_l_q_reset
sync posedge \coresync_clk
update \reset_delay $0\reset_delay[0:0]
end
- attribute \src "libresoc.v:139098.3-139099.35"
- process $proc$libresoc.v:139098$6157
+ attribute \src "libresoc.v:137228.3-137229.35"
+ process $proc$libresoc.v:137228$6083
assign { } { }
- assign $0\idx_l$23[0:0]$6158 \idx_l$23$next
+ assign $0\idx_l$23[0:0]$6084 \idx_l$23$next
sync posedge \coresync_clk
- update \idx_l$23 $0\idx_l$23[0:0]$6158
+ update \idx_l$23 $0\idx_l$23[0:0]$6084
end
- attribute \src "libresoc.v:139119.3-139128.6"
- process $proc$libresoc.v:139119$6159
+ attribute \src "libresoc.v:137249.3-137258.6"
+ process $proc$libresoc.v:137249$6085
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i$12[47:0]$6160 $1\ldst_port0_addr_i$12[47:0]$6161
- attribute \src "libresoc.v:139120.5-139120.29"
+ assign $0\ldst_port0_addr_i$12[47:0]$6086 $1\ldst_port0_addr_i$12[47:0]$6087
+ attribute \src "libresoc.v:137250.5-137250.29"
switch \initial
- attribute \src "libresoc.v:139120.9-139120.17"
+ attribute \src "libresoc.v:137250.9-137250.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i$12[47:0]$6161 \$32 [47:0]
+ assign $1\ldst_port0_addr_i$12[47:0]$6087 \$32 [47:0]
case
- assign $1\ldst_port0_addr_i$12[47:0]$6161 48'000000000000000000000000000000000000000000000000
+ assign $1\ldst_port0_addr_i$12[47:0]$6087 48'000000000000000000000000000000000000000000000000
end
sync always
- update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6160
+ update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6086
end
- attribute \src "libresoc.v:139129.3-139138.6"
- process $proc$libresoc.v:139129$6162
+ attribute \src "libresoc.v:137259.3-137268.6"
+ process $proc$libresoc.v:137259$6088
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i_ok$13[0:0]$6163 $1\ldst_port0_addr_i_ok$13[0:0]$6164
- attribute \src "libresoc.v:139130.5-139130.29"
+ assign $0\ldst_port0_addr_i_ok$13[0:0]$6089 $1\ldst_port0_addr_i_ok$13[0:0]$6090
+ attribute \src "libresoc.v:137260.5-137260.29"
switch \initial
- attribute \src "libresoc.v:139130.9-139130.17"
+ attribute \src "libresoc.v:137260.9-137260.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i_ok$13[0:0]$6164 \ldst_port0_addr_i_ok
+ assign $1\ldst_port0_addr_i_ok$13[0:0]$6090 \ldst_port0_addr_i_ok
case
- assign $1\ldst_port0_addr_i_ok$13[0:0]$6164 1'0
+ assign $1\ldst_port0_addr_i_ok$13[0:0]$6090 1'0
end
sync always
- update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6163
+ update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6089
end
- attribute \src "libresoc.v:139139.3-139149.6"
- process $proc$libresoc.v:139139$6165
+ attribute \src "libresoc.v:137269.3-137279.6"
+ process $proc$libresoc.v:137269$6091
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\ldst_port0_st_data_i$18[63:0]$6166 $1\ldst_port0_st_data_i$18[63:0]$6168
- assign $0\ldst_port0_st_data_i_ok$17[0:0]$6167 $1\ldst_port0_st_data_i_ok$17[0:0]$6169
- attribute \src "libresoc.v:139140.5-139140.29"
+ assign $0\ldst_port0_st_data_i$18[63:0]$6092 $1\ldst_port0_st_data_i$18[63:0]$6094
+ assign $0\ldst_port0_st_data_i_ok$17[0:0]$6093 $1\ldst_port0_st_data_i_ok$17[0:0]$6095
+ attribute \src "libresoc.v:137270.5-137270.29"
switch \initial
- attribute \src "libresoc.v:139140.9-139140.17"
+ attribute \src "libresoc.v:137270.9-137270.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6169 $1\ldst_port0_st_data_i$18[63:0]$6168 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
+ assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6095 $1\ldst_port0_st_data_i$18[63:0]$6094 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
case
- assign $1\ldst_port0_st_data_i$18[63:0]$6168 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $1\ldst_port0_st_data_i_ok$17[0:0]$6169 1'0
+ assign $1\ldst_port0_st_data_i$18[63:0]$6094 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\ldst_port0_st_data_i_ok$17[0:0]$6095 1'0
end
sync always
- update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6166
- update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6167
+ update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6092
+ update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6093
end
- attribute \src "libresoc.v:139150.3-139160.6"
- process $proc$libresoc.v:139150$6170
+ attribute \src "libresoc.v:137280.3-137290.6"
+ process $proc$libresoc.v:137280$6096
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0]
assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:139151.5-139151.29"
+ attribute \src "libresoc.v:137281.5-137281.29"
switch \initial
- attribute \src "libresoc.v:139151.9-139151.17"
+ attribute \src "libresoc.v:137281.9-137281.17"
case 1'1
case
end
update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0]
update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0]
end
- attribute \src "libresoc.v:139161.3-139170.6"
- process $proc$libresoc.v:139161$6171
+ attribute \src "libresoc.v:137291.3-137300.6"
+ process $proc$libresoc.v:137291$6097
assign { } { }
assign { } { }
assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0]
- attribute \src "libresoc.v:139162.5-139162.29"
+ attribute \src "libresoc.v:137292.5-137292.29"
switch \initial
- attribute \src "libresoc.v:139162.9-139162.17"
+ attribute \src "libresoc.v:137292.9-137292.17"
case 1'1
case
end
sync always
update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0]
end
- attribute \src "libresoc.v:139171.3-139180.6"
- process $proc$libresoc.v:139171$6172
+ attribute \src "libresoc.v:137301.3-137310.6"
+ process $proc$libresoc.v:137301$6098
assign { } { }
assign { } { }
assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:139172.5-139172.29"
+ attribute \src "libresoc.v:137302.5-137302.29"
switch \initial
- attribute \src "libresoc.v:139172.9-139172.17"
+ attribute \src "libresoc.v:137302.9-137302.17"
case 1'1
case
end
sync always
update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0]
end
- attribute \src "libresoc.v:139181.3-139197.6"
- process $proc$libresoc.v:139181$6173
+ attribute \src "libresoc.v:137311.3-137327.6"
+ process $proc$libresoc.v:137311$6099
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\ldst_port0_exc_$signal[0:0]$6174 $1\ldst_port0_exc_$signal[0:0]$6182
- assign $0\ldst_port0_exc_$signal$1[0:0]$6175 $1\ldst_port0_exc_$signal$1[0:0]$6183
- assign $0\ldst_port0_exc_$signal$2[0:0]$6176 $1\ldst_port0_exc_$signal$2[0:0]$6184
- assign $0\ldst_port0_exc_$signal$3[0:0]$6177 $1\ldst_port0_exc_$signal$3[0:0]$6185
- assign $0\ldst_port0_exc_$signal$4[0:0]$6178 $1\ldst_port0_exc_$signal$4[0:0]$6186
- assign $0\ldst_port0_exc_$signal$5[0:0]$6179 $1\ldst_port0_exc_$signal$5[0:0]$6187
- assign $0\ldst_port0_exc_$signal$6[0:0]$6180 $1\ldst_port0_exc_$signal$6[0:0]$6188
- assign $0\ldst_port0_exc_$signal$7[0:0]$6181 $1\ldst_port0_exc_$signal$7[0:0]$6189
- attribute \src "libresoc.v:139182.5-139182.29"
+ assign $0\ldst_port0_exc_$signal[0:0]$6100 $1\ldst_port0_exc_$signal[0:0]$6108
+ assign $0\ldst_port0_exc_$signal$1[0:0]$6101 $1\ldst_port0_exc_$signal$1[0:0]$6109
+ assign $0\ldst_port0_exc_$signal$2[0:0]$6102 $1\ldst_port0_exc_$signal$2[0:0]$6110
+ assign $0\ldst_port0_exc_$signal$3[0:0]$6103 $1\ldst_port0_exc_$signal$3[0:0]$6111
+ assign $0\ldst_port0_exc_$signal$4[0:0]$6104 $1\ldst_port0_exc_$signal$4[0:0]$6112
+ assign $0\ldst_port0_exc_$signal$5[0:0]$6105 $1\ldst_port0_exc_$signal$5[0:0]$6113
+ assign $0\ldst_port0_exc_$signal$6[0:0]$6106 $1\ldst_port0_exc_$signal$6[0:0]$6114
+ assign $0\ldst_port0_exc_$signal$7[0:0]$6107 $1\ldst_port0_exc_$signal$7[0:0]$6115
+ attribute \src "libresoc.v:137312.5-137312.29"
switch \initial
- attribute \src "libresoc.v:139182.9-139182.17"
+ attribute \src "libresoc.v:137312.9-137312.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\ldst_port0_exc_$signal$7[0:0]$6189 $1\ldst_port0_exc_$signal$6[0:0]$6188 $1\ldst_port0_exc_$signal$5[0:0]$6187 $1\ldst_port0_exc_$signal$4[0:0]$6186 $1\ldst_port0_exc_$signal$3[0:0]$6185 $1\ldst_port0_exc_$signal$2[0:0]$6184 $1\ldst_port0_exc_$signal$1[0:0]$6183 $1\ldst_port0_exc_$signal[0:0]$6182 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 }
+ assign { $1\ldst_port0_exc_$signal$7[0:0]$6115 $1\ldst_port0_exc_$signal$6[0:0]$6114 $1\ldst_port0_exc_$signal$5[0:0]$6113 $1\ldst_port0_exc_$signal$4[0:0]$6112 $1\ldst_port0_exc_$signal$3[0:0]$6111 $1\ldst_port0_exc_$signal$2[0:0]$6110 $1\ldst_port0_exc_$signal$1[0:0]$6109 $1\ldst_port0_exc_$signal[0:0]$6108 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 }
case
- assign $1\ldst_port0_exc_$signal[0:0]$6182 1'0
- assign $1\ldst_port0_exc_$signal$1[0:0]$6183 1'0
- assign $1\ldst_port0_exc_$signal$2[0:0]$6184 1'0
- assign $1\ldst_port0_exc_$signal$3[0:0]$6185 1'0
- assign $1\ldst_port0_exc_$signal$4[0:0]$6186 1'0
- assign $1\ldst_port0_exc_$signal$5[0:0]$6187 1'0
- assign $1\ldst_port0_exc_$signal$6[0:0]$6188 1'0
- assign $1\ldst_port0_exc_$signal$7[0:0]$6189 1'0
+ assign $1\ldst_port0_exc_$signal[0:0]$6108 1'0
+ assign $1\ldst_port0_exc_$signal$1[0:0]$6109 1'0
+ assign $1\ldst_port0_exc_$signal$2[0:0]$6110 1'0
+ assign $1\ldst_port0_exc_$signal$3[0:0]$6111 1'0
+ assign $1\ldst_port0_exc_$signal$4[0:0]$6112 1'0
+ assign $1\ldst_port0_exc_$signal$5[0:0]$6113 1'0
+ assign $1\ldst_port0_exc_$signal$6[0:0]$6114 1'0
+ assign $1\ldst_port0_exc_$signal$7[0:0]$6115 1'0
end
sync always
- update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6174
- update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6175
- update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6176
- update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6177
- update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6178
- update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6179
- update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6180
- update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6181
+ update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6100
+ update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6101
+ update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6102
+ update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6103
+ update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6104
+ update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6105
+ update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6106
+ update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6107
end
- attribute \src "libresoc.v:139198.3-139212.6"
- process $proc$libresoc.v:139198$6190
+ attribute \src "libresoc.v:137328.3-137342.6"
+ process $proc$libresoc.v:137328$6116
assign { } { }
assign { } { }
assign { } { }
- assign $0\idx_l$23$next[0:0]$6191 $2\idx_l$23$next[0:0]$6193
- attribute \src "libresoc.v:139199.5-139199.29"
+ assign $0\idx_l$23$next[0:0]$6117 $2\idx_l$23$next[0:0]$6119
+ attribute \src "libresoc.v:137329.5-137329.29"
switch \initial
- attribute \src "libresoc.v:139199.9-139199.17"
+ attribute \src "libresoc.v:137329.9-137329.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\idx_l$23$next[0:0]$6192 \pick_o
+ assign $1\idx_l$23$next[0:0]$6118 \pick_o
case
- assign $1\idx_l$23$next[0:0]$6192 \idx_l$23
+ assign $1\idx_l$23$next[0:0]$6118 \idx_l$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\idx_l$23$next[0:0]$6193 1'0
+ assign $2\idx_l$23$next[0:0]$6119 1'0
case
- assign $2\idx_l$23$next[0:0]$6193 $1\idx_l$23$next[0:0]$6192
+ assign $2\idx_l$23$next[0:0]$6119 $1\idx_l$23$next[0:0]$6118
end
sync always
- update \idx_l$23$next $0\idx_l$23$next[0:0]$6191
+ update \idx_l$23$next $0\idx_l$23$next[0:0]$6117
end
- attribute \src "libresoc.v:139213.3-139222.6"
- process $proc$libresoc.v:139213$6194
+ attribute \src "libresoc.v:137343.3-137352.6"
+ process $proc$libresoc.v:137343$6120
assign { } { }
assign { } { }
assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0]
- attribute \src "libresoc.v:139214.5-139214.29"
+ attribute \src "libresoc.v:137344.5-137344.29"
switch \initial
- attribute \src "libresoc.v:139214.9-139214.17"
+ attribute \src "libresoc.v:137344.9-137344.17"
case 1'1
case
end
sync always
update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0]
end
- attribute \src "libresoc.v:139223.3-139232.6"
- process $proc$libresoc.v:139223$6195
+ attribute \src "libresoc.v:137353.3-137362.6"
+ process $proc$libresoc.v:137353$6121
assign { } { }
assign { } { }
assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0]
- attribute \src "libresoc.v:139224.5-139224.29"
+ attribute \src "libresoc.v:137354.5-137354.29"
switch \initial
- attribute \src "libresoc.v:139224.9-139224.17"
+ attribute \src "libresoc.v:137354.9-137354.17"
case 1'1
case
end
sync always
update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0]
end
- attribute \src "libresoc.v:139233.3-139242.6"
- process $proc$libresoc.v:139233$6196
+ attribute \src "libresoc.v:137363.3-137372.6"
+ process $proc$libresoc.v:137363$6122
assign { } { }
assign { } { }
assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0]
- attribute \src "libresoc.v:139234.5-139234.29"
+ attribute \src "libresoc.v:137364.5-137364.29"
switch \initial
- attribute \src "libresoc.v:139234.9-139234.17"
+ attribute \src "libresoc.v:137364.9-137364.17"
case 1'1
case
end
sync always
update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0]
end
- attribute \src "libresoc.v:139243.3-139252.6"
- process $proc$libresoc.v:139243$6197
+ attribute \src "libresoc.v:137373.3-137382.6"
+ process $proc$libresoc.v:137373$6123
assign { } { }
assign { } { }
assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0]
- attribute \src "libresoc.v:139244.5-139244.29"
+ attribute \src "libresoc.v:137374.5-137374.29"
switch \initial
- attribute \src "libresoc.v:139244.9-139244.17"
+ attribute \src "libresoc.v:137374.9-137374.17"
case 1'1
case
end
sync always
update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0]
end
- attribute \src "libresoc.v:139253.3-139262.6"
- process $proc$libresoc.v:139253$6198
+ attribute \src "libresoc.v:137383.3-137392.6"
+ process $proc$libresoc.v:137383$6124
assign { } { }
assign { } { }
assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0]
- attribute \src "libresoc.v:139254.5-139254.29"
+ attribute \src "libresoc.v:137384.5-137384.29"
switch \initial
- attribute \src "libresoc.v:139254.9-139254.17"
+ attribute \src "libresoc.v:137384.9-137384.17"
case 1'1
case
end
sync always
update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0]
end
- attribute \src "libresoc.v:139263.3-139277.6"
- process $proc$libresoc.v:139263$6199
+ attribute \src "libresoc.v:137393.3-137407.6"
+ process $proc$libresoc.v:137393$6125
assign { } { }
assign { } { }
assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:139264.5-139264.29"
+ attribute \src "libresoc.v:137394.5-137394.29"
switch \initial
- attribute \src "libresoc.v:139264.9-139264.17"
+ attribute \src "libresoc.v:137394.9-137394.17"
case 1'1
case
end
sync always
update \reset_l_s_reset $0\reset_l_s_reset[0:0]
end
- attribute \src "libresoc.v:139278.3-139287.6"
- process $proc$libresoc.v:139278$6200
+ attribute \src "libresoc.v:137408.3-137417.6"
+ process $proc$libresoc.v:137408$6126
assign { } { }
assign { } { }
assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:139279.5-139279.29"
+ attribute \src "libresoc.v:137409.5-137409.29"
switch \initial
- attribute \src "libresoc.v:139279.9-139279.17"
+ attribute \src "libresoc.v:137409.9-137409.17"
case 1'1
case
end
sync always
update \reset_l_r_reset $0\reset_l_r_reset[0:0]
end
- attribute \src "libresoc.v:139288.3-139297.6"
- process $proc$libresoc.v:139288$6201
+ attribute \src "libresoc.v:137418.3-137427.6"
+ process $proc$libresoc.v:137418$6127
assign { } { }
assign { } { }
- assign $0\ldst_port0_is_ld_i$8[0:0]$6202 $1\ldst_port0_is_ld_i$8[0:0]$6203
- attribute \src "libresoc.v:139289.5-139289.29"
+ assign $0\ldst_port0_is_ld_i$8[0:0]$6128 $1\ldst_port0_is_ld_i$8[0:0]$6129
+ attribute \src "libresoc.v:137419.5-137419.29"
switch \initial
- attribute \src "libresoc.v:139289.9-139289.17"
+ attribute \src "libresoc.v:137419.9-137419.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_is_ld_i$8[0:0]$6203 \ldst_port0_is_ld_i
+ assign $1\ldst_port0_is_ld_i$8[0:0]$6129 \ldst_port0_is_ld_i
case
- assign $1\ldst_port0_is_ld_i$8[0:0]$6203 1'0
+ assign $1\ldst_port0_is_ld_i$8[0:0]$6129 1'0
end
sync always
- update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6202
+ update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6128
end
- attribute \src "libresoc.v:139298.3-139307.6"
- process $proc$libresoc.v:139298$6204
+ attribute \src "libresoc.v:137428.3-137437.6"
+ process $proc$libresoc.v:137428$6130
assign { } { }
assign { } { }
- assign $0\ldst_port0_is_st_i$9[0:0]$6205 $1\ldst_port0_is_st_i$9[0:0]$6206
- attribute \src "libresoc.v:139299.5-139299.29"
+ assign $0\ldst_port0_is_st_i$9[0:0]$6131 $1\ldst_port0_is_st_i$9[0:0]$6132
+ attribute \src "libresoc.v:137429.5-137429.29"
switch \initial
- attribute \src "libresoc.v:139299.9-139299.17"
+ attribute \src "libresoc.v:137429.9-137429.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_is_st_i$9[0:0]$6206 \ldst_port0_is_st_i
+ assign $1\ldst_port0_is_st_i$9[0:0]$6132 \ldst_port0_is_st_i
case
- assign $1\ldst_port0_is_st_i$9[0:0]$6206 1'0
+ assign $1\ldst_port0_is_st_i$9[0:0]$6132 1'0
end
sync always
- update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6205
+ update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6131
end
- attribute \src "libresoc.v:139308.3-139317.6"
- process $proc$libresoc.v:139308$6207
+ attribute \src "libresoc.v:137438.3-137447.6"
+ process $proc$libresoc.v:137438$6133
assign { } { }
assign { } { }
- assign $0\ldst_port0_data_len$11[3:0]$6208 $1\ldst_port0_data_len$11[3:0]$6209
- attribute \src "libresoc.v:139309.5-139309.29"
+ assign $0\ldst_port0_data_len$11[3:0]$6134 $1\ldst_port0_data_len$11[3:0]$6135
+ attribute \src "libresoc.v:137439.5-137439.29"
switch \initial
- attribute \src "libresoc.v:139309.9-139309.17"
+ attribute \src "libresoc.v:137439.9-137439.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_data_len$11[3:0]$6209 \ldst_port0_data_len
+ assign $1\ldst_port0_data_len$11[3:0]$6135 \ldst_port0_data_len
case
- assign $1\ldst_port0_data_len$11[3:0]$6209 4'0000
+ assign $1\ldst_port0_data_len$11[3:0]$6135 4'0000
end
sync always
- update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6208
+ update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6134
end
- attribute \src "libresoc.v:139318.3-139327.6"
- process $proc$libresoc.v:139318$6210
+ attribute \src "libresoc.v:137448.3-137457.6"
+ process $proc$libresoc.v:137448$6136
assign { } { }
assign { } { }
assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0]
- attribute \src "libresoc.v:139319.5-139319.29"
+ attribute \src "libresoc.v:137449.5-137449.29"
switch \initial
- attribute \src "libresoc.v:139319.9-139319.17"
+ attribute \src "libresoc.v:137449.9-137449.17"
case 1'1
case
end
sync always
update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0]
end
- connect \$20 $or$libresoc.v:139092$6152_Y
- connect \$24 $ternary$libresoc.v:139093$6153_Y
- connect \$26 $not$libresoc.v:139094$6154_Y
- connect \$28 $not$libresoc.v:139095$6155_Y
+ connect \$20 $or$libresoc.v:137222$6078_Y
+ connect \$24 $ternary$libresoc.v:137223$6079_Y
+ connect \$26 $not$libresoc.v:137224$6080_Y
+ connect \$28 $not$libresoc.v:137225$6081_Y
connect \$22 \$24
connect \$32 \ldst_port0_addr_i
connect \ldst_port0_go_die_i$30 1'0
connect \reset_delay$next \reset_l_q_reset
connect \pick_i \$20
end
-attribute \src "libresoc.v:139347.1-139405.10"
+attribute \src "libresoc.v:137477.1-137535.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active"
attribute \generator "nMigen"
module \ld_active
- attribute \src "libresoc.v:139348.7-139348.20"
+ attribute \src "libresoc.v:137478.7-137478.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:139393.3-139401.6"
- wire $0\q_int$next[0:0]$6225
- attribute \src "libresoc.v:139391.3-139392.27"
+ attribute \src "libresoc.v:137523.3-137531.6"
+ wire $0\q_int$next[0:0]$6151
+ attribute \src "libresoc.v:137521.3-137522.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:139393.3-139401.6"
- wire $1\q_int$next[0:0]$6226
- attribute \src "libresoc.v:139370.7-139370.19"
+ attribute \src "libresoc.v:137523.3-137531.6"
+ wire $1\q_int$next[0:0]$6152
+ attribute \src "libresoc.v:137500.7-137500.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:139383.17-139383.96"
- wire $and$libresoc.v:139383$6215_Y
- attribute \src "libresoc.v:139388.17-139388.96"
- wire $and$libresoc.v:139388$6220_Y
- attribute \src "libresoc.v:139385.18-139385.99"
- wire $not$libresoc.v:139385$6217_Y
- attribute \src "libresoc.v:139387.17-139387.98"
- wire $not$libresoc.v:139387$6219_Y
- attribute \src "libresoc.v:139390.17-139390.98"
- wire $not$libresoc.v:139390$6222_Y
- attribute \src "libresoc.v:139384.18-139384.104"
- wire $or$libresoc.v:139384$6216_Y
- attribute \src "libresoc.v:139386.18-139386.105"
- wire $or$libresoc.v:139386$6218_Y
- attribute \src "libresoc.v:139389.17-139389.103"
- wire $or$libresoc.v:139389$6221_Y
+ attribute \src "libresoc.v:137513.17-137513.96"
+ wire $and$libresoc.v:137513$6141_Y
+ attribute \src "libresoc.v:137518.17-137518.96"
+ wire $and$libresoc.v:137518$6146_Y
+ attribute \src "libresoc.v:137515.18-137515.99"
+ wire $not$libresoc.v:137515$6143_Y
+ attribute \src "libresoc.v:137517.17-137517.98"
+ wire $not$libresoc.v:137517$6145_Y
+ attribute \src "libresoc.v:137520.17-137520.98"
+ wire $not$libresoc.v:137520$6148_Y
+ attribute \src "libresoc.v:137514.18-137514.104"
+ wire $or$libresoc.v:137514$6142_Y
+ attribute \src "libresoc.v:137516.18-137516.105"
+ wire $or$libresoc.v:137516$6144_Y
+ attribute \src "libresoc.v:137519.17-137519.103"
+ wire $or$libresoc.v:137519$6147_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:139348.7-139348.15"
+ attribute \src "libresoc.v:137478.7-137478.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_ld_active
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:139383$6215
+ cell $and $and$libresoc.v:137513$6141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:139383$6215_Y
+ connect \Y $and$libresoc.v:137513$6141_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:139388$6220
+ cell $and $and$libresoc.v:137518$6146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:139388$6220_Y
+ connect \Y $and$libresoc.v:137518$6146_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:139385$6217
+ cell $not $not$libresoc.v:137515$6143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_ld_active
- connect \Y $not$libresoc.v:139385$6217_Y
+ connect \Y $not$libresoc.v:137515$6143_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:139387$6219
+ cell $not $not$libresoc.v:137517$6145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_ld_active
- connect \Y $not$libresoc.v:139387$6219_Y
+ connect \Y $not$libresoc.v:137517$6145_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:139390$6222
+ cell $not $not$libresoc.v:137520$6148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_ld_active
- connect \Y $not$libresoc.v:139390$6222_Y
+ connect \Y $not$libresoc.v:137520$6148_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:139384$6216
+ cell $or $or$libresoc.v:137514$6142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_ld_active
- connect \Y $or$libresoc.v:139384$6216_Y
+ connect \Y $or$libresoc.v:137514$6142_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:139386$6218
+ cell $or $or$libresoc.v:137516$6144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_ld_active
connect \B \q_int
- connect \Y $or$libresoc.v:139386$6218_Y
+ connect \Y $or$libresoc.v:137516$6144_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:139389$6221
+ cell $or $or$libresoc.v:137519$6147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_ld_active
- connect \Y $or$libresoc.v:139389$6221_Y
+ connect \Y $or$libresoc.v:137519$6147_Y
end
- attribute \src "libresoc.v:139348.7-139348.20"
- process $proc$libresoc.v:139348$6227
+ attribute \src "libresoc.v:137478.7-137478.20"
+ process $proc$libresoc.v:137478$6153
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:139370.7-139370.19"
- process $proc$libresoc.v:139370$6228
+ attribute \src "libresoc.v:137500.7-137500.19"
+ process $proc$libresoc.v:137500$6154
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:139391.3-139392.27"
- process $proc$libresoc.v:139391$6223
+ attribute \src "libresoc.v:137521.3-137522.27"
+ process $proc$libresoc.v:137521$6149
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:139393.3-139401.6"
- process $proc$libresoc.v:139393$6224
+ attribute \src "libresoc.v:137523.3-137531.6"
+ process $proc$libresoc.v:137523$6150
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$6225 $1\q_int$next[0:0]$6226
- attribute \src "libresoc.v:139394.5-139394.29"
+ assign $0\q_int$next[0:0]$6151 $1\q_int$next[0:0]$6152
+ attribute \src "libresoc.v:137524.5-137524.29"
switch \initial
- attribute \src "libresoc.v:139394.9-139394.17"
+ attribute \src "libresoc.v:137524.9-137524.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$6226 1'0
+ assign $1\q_int$next[0:0]$6152 1'0
case
- assign $1\q_int$next[0:0]$6226 \$5
+ assign $1\q_int$next[0:0]$6152 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$6225
+ update \q_int$next $0\q_int$next[0:0]$6151
end
- connect \$9 $and$libresoc.v:139383$6215_Y
- connect \$11 $or$libresoc.v:139384$6216_Y
- connect \$13 $not$libresoc.v:139385$6217_Y
- connect \$15 $or$libresoc.v:139386$6218_Y
- connect \$1 $not$libresoc.v:139387$6219_Y
- connect \$3 $and$libresoc.v:139388$6220_Y
- connect \$5 $or$libresoc.v:139389$6221_Y
- connect \$7 $not$libresoc.v:139390$6222_Y
+ connect \$9 $and$libresoc.v:137513$6141_Y
+ connect \$11 $or$libresoc.v:137514$6142_Y
+ connect \$13 $not$libresoc.v:137515$6143_Y
+ connect \$15 $or$libresoc.v:137516$6144_Y
+ connect \$1 $not$libresoc.v:137517$6145_Y
+ connect \$3 $and$libresoc.v:137518$6146_Y
+ connect \$5 $or$libresoc.v:137519$6147_Y
+ connect \$7 $not$libresoc.v:137520$6148_Y
connect \qlq_ld_active \$15
connect \qn_ld_active \$13
connect \q_ld_active \$11
end
-attribute \src "libresoc.v:139409.1-140768.10"
+attribute \src "libresoc.v:137539.1-138898.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0"
attribute \generator "nMigen"
module \ldst0
- attribute \src "libresoc.v:140423.3-140431.6"
- wire $0\adr_l_r_adr$next[0:0]$6371
- attribute \src "libresoc.v:140305.3-140306.39"
+ attribute \src "libresoc.v:138553.3-138561.6"
+ wire $0\adr_l_r_adr$next[0:0]$6297
+ attribute \src "libresoc.v:138435.3-138436.39"
wire $0\adr_l_r_adr[0:0]
- attribute \src "libresoc.v:140251.3-140252.21"
+ attribute \src "libresoc.v:138381.3-138382.21"
wire $0\alu_ok[0:0]
- attribute \src "libresoc.v:140588.3-140597.6"
+ attribute \src "libresoc.v:138718.3-138727.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:140598.3-140607.6"
+ attribute \src "libresoc.v:138728.3-138737.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:140578.3-140587.6"
- wire width 64 $0\ea_r$next[63:0]$6459
- attribute \src "libresoc.v:140253.3-140254.25"
+ attribute \src "libresoc.v:138708.3-138717.6"
+ wire width 64 $0\ea_r$next[63:0]$6385
+ attribute \src "libresoc.v:138383.3-138384.25"
wire width 64 $0\ea_r[63:0]
- attribute \src "libresoc.v:139410.7-139410.20"
+ attribute \src "libresoc.v:137540.7-137540.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:140653.3-140672.6"
+ attribute \src "libresoc.v:138783.3-138802.6"
wire width 64 $0\ldd_o[63:0]
- attribute \src "libresoc.v:140617.3-140640.6"
+ attribute \src "libresoc.v:138747.3-138770.6"
wire width 64 $0\lddata_r[63:0]
- attribute \src "libresoc.v:140520.3-140529.6"
- wire width 64 $0\ldo_r$next[63:0]$6444
- attribute \src "libresoc.v:140261.3-140262.27"
+ attribute \src "libresoc.v:138650.3-138659.6"
+ wire width 64 $0\ldo_r$next[63:0]$6370
+ attribute \src "libresoc.v:138391.3-138392.27"
wire width 64 $0\ldo_r[63:0]
- attribute \src "libresoc.v:140249.3-140250.33"
+ attribute \src "libresoc.v:138379.3-138380.33"
wire width 96 $0\ldst_port0_addr_i[95:0]
- attribute \src "libresoc.v:140608.3-140616.6"
- wire $0\ldst_port0_addr_i_ok$next[0:0]$6464
- attribute \src "libresoc.v:140247.3-140248.57"
+ attribute \src "libresoc.v:138738.3-138746.6"
+ wire $0\ldst_port0_addr_i_ok$next[0:0]$6390
+ attribute \src "libresoc.v:138377.3-138378.57"
wire $0\ldst_port0_addr_i_ok[0:0]
- attribute \src "libresoc.v:140697.3-140708.6"
+ attribute \src "libresoc.v:138827.3-138838.6"
wire width 64 $0\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:140468.3-140476.6"
- wire $0\lsd_l_r_lsd$next[0:0]$6386
- attribute \src "libresoc.v:140295.3-140296.39"
+ attribute \src "libresoc.v:138598.3-138606.6"
+ wire $0\lsd_l_r_lsd$next[0:0]$6312
+ attribute \src "libresoc.v:138425.3-138426.39"
wire $0\lsd_l_r_lsd[0:0]
- attribute \src "libresoc.v:140396.3-140404.6"
- wire $0\opc_l_r_opc$next[0:0]$6362
- attribute \src "libresoc.v:140311.3-140312.39"
+ attribute \src "libresoc.v:138526.3-138534.6"
+ wire $0\opc_l_r_opc$next[0:0]$6288
+ attribute \src "libresoc.v:138441.3-138442.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:140387.3-140395.6"
- wire $0\opc_l_s_opc$next[0:0]$6359
- attribute \src "libresoc.v:140313.3-140314.39"
+ attribute \src "libresoc.v:138517.3-138525.6"
+ wire $0\opc_l_s_opc$next[0:0]$6285
+ attribute \src "libresoc.v:138443.3-138444.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__byte_reverse$next[0:0]$6389
- attribute \src "libresoc.v:140287.3-140288.57"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__byte_reverse$next[0:0]$6315
+ attribute \src "libresoc.v:138417.3-138418.57"
wire $0\oper_r__byte_reverse[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 4 $0\oper_r__data_len$next[3:0]$6390
- attribute \src "libresoc.v:140285.3-140286.49"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 4 $0\oper_r__data_len$next[3:0]$6316
+ attribute \src "libresoc.v:138415.3-138416.49"
wire width 4 $0\oper_r__data_len[3:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 13 $0\oper_r__fn_unit$next[12:0]$6391
- attribute \src "libresoc.v:140265.3-140266.47"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 13 $0\oper_r__fn_unit$next[12:0]$6317
+ attribute \src "libresoc.v:138395.3-138396.47"
wire width 13 $0\oper_r__fn_unit[12:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 64 $0\oper_r__imm_data__data$next[63:0]$6392
- attribute \src "libresoc.v:140267.3-140268.61"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 64 $0\oper_r__imm_data__data$next[63:0]$6318
+ attribute \src "libresoc.v:138397.3-138398.61"
wire width 64 $0\oper_r__imm_data__data[63:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__imm_data__ok$next[0:0]$6393
- attribute \src "libresoc.v:140269.3-140270.57"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__imm_data__ok$next[0:0]$6319
+ attribute \src "libresoc.v:138399.3-138400.57"
wire $0\oper_r__imm_data__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 32 $0\oper_r__insn$next[31:0]$6394
- attribute \src "libresoc.v:140293.3-140294.41"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 32 $0\oper_r__insn$next[31:0]$6320
+ attribute \src "libresoc.v:138423.3-138424.41"
wire width 32 $0\oper_r__insn[31:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 7 $0\oper_r__insn_type$next[6:0]$6395
- attribute \src "libresoc.v:140263.3-140264.51"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 7 $0\oper_r__insn_type$next[6:0]$6321
+ attribute \src "libresoc.v:138393.3-138394.51"
wire width 7 $0\oper_r__insn_type[6:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__is_32bit$next[0:0]$6396
- attribute \src "libresoc.v:140281.3-140282.49"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__is_32bit$next[0:0]$6322
+ attribute \src "libresoc.v:138411.3-138412.49"
wire $0\oper_r__is_32bit[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__is_signed$next[0:0]$6397
- attribute \src "libresoc.v:140283.3-140284.51"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__is_signed$next[0:0]$6323
+ attribute \src "libresoc.v:138413.3-138414.51"
wire $0\oper_r__is_signed[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 2 $0\oper_r__ldst_mode$next[1:0]$6398
- attribute \src "libresoc.v:140291.3-140292.51"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 2 $0\oper_r__ldst_mode$next[1:0]$6324
+ attribute \src "libresoc.v:138421.3-138422.51"
wire width 2 $0\oper_r__ldst_mode[1:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__oe__oe$next[0:0]$6399
- attribute \src "libresoc.v:140277.3-140278.45"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__oe__oe$next[0:0]$6325
+ attribute \src "libresoc.v:138407.3-138408.45"
wire $0\oper_r__oe__oe[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__oe__ok$next[0:0]$6400
- attribute \src "libresoc.v:140279.3-140280.45"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__oe__ok$next[0:0]$6326
+ attribute \src "libresoc.v:138409.3-138410.45"
wire $0\oper_r__oe__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__rc__ok$next[0:0]$6401
- attribute \src "libresoc.v:140275.3-140276.45"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__rc__ok$next[0:0]$6327
+ attribute \src "libresoc.v:138405.3-138406.45"
wire $0\oper_r__rc__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__rc__rc$next[0:0]$6402
- attribute \src "libresoc.v:140273.3-140274.45"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__rc__rc$next[0:0]$6328
+ attribute \src "libresoc.v:138403.3-138404.45"
wire $0\oper_r__rc__rc[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__sign_extend$next[0:0]$6403
- attribute \src "libresoc.v:140289.3-140290.55"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__sign_extend$next[0:0]$6329
+ attribute \src "libresoc.v:138419.3-138420.55"
wire $0\oper_r__sign_extend[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $0\oper_r__zero_a$next[0:0]$6404
- attribute \src "libresoc.v:140271.3-140272.45"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $0\oper_r__zero_a$next[0:0]$6330
+ attribute \src "libresoc.v:138401.3-138402.45"
wire $0\oper_r__zero_a[0:0]
- attribute \src "libresoc.v:140315.3-140316.28"
+ attribute \src "libresoc.v:138445.3-138446.28"
wire $0\p_st_go[0:0]
- attribute \src "libresoc.v:140641.3-140652.6"
+ attribute \src "libresoc.v:138771.3-138782.6"
wire width 64 $0\revnorev[63:0]
- attribute \src "libresoc.v:140414.3-140422.6"
- wire width 3 $0\src_l_r_src$next[2:0]$6368
- attribute \src "libresoc.v:140307.3-140308.39"
+ attribute \src "libresoc.v:138544.3-138552.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$6294
+ attribute \src "libresoc.v:138437.3-138438.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:140405.3-140413.6"
- wire width 3 $0\src_l_s_src$next[2:0]$6365
- attribute \src "libresoc.v:140309.3-140310.39"
+ attribute \src "libresoc.v:138535.3-138543.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$6291
+ attribute \src "libresoc.v:138439.3-138440.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:140530.3-140545.6"
- wire width 64 $0\src_r0$next[63:0]$6447
- attribute \src "libresoc.v:140259.3-140260.29"
+ attribute \src "libresoc.v:138660.3-138675.6"
+ wire width 64 $0\src_r0$next[63:0]$6373
+ attribute \src "libresoc.v:138389.3-138390.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:140546.3-140561.6"
- wire width 64 $0\src_r1$next[63:0]$6451
- attribute \src "libresoc.v:140257.3-140258.29"
+ attribute \src "libresoc.v:138676.3-138691.6"
+ wire width 64 $0\src_r1$next[63:0]$6377
+ attribute \src "libresoc.v:138387.3-138388.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:140562.3-140577.6"
- wire width 64 $0\src_r2$next[63:0]$6455
- attribute \src "libresoc.v:140255.3-140256.29"
+ attribute \src "libresoc.v:138692.3-138707.6"
+ wire width 64 $0\src_r2$next[63:0]$6381
+ attribute \src "libresoc.v:138385.3-138386.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:140673.3-140696.6"
+ attribute \src "libresoc.v:138803.3-138826.6"
wire width 64 $0\stdata_r[63:0]
- attribute \src "libresoc.v:140459.3-140467.6"
- wire $0\sto_l_r_sto$next[0:0]$6383
- attribute \src "libresoc.v:140297.3-140298.39"
+ attribute \src "libresoc.v:138589.3-138597.6"
+ wire $0\sto_l_r_sto$next[0:0]$6309
+ attribute \src "libresoc.v:138427.3-138428.39"
wire $0\sto_l_r_sto[0:0]
- attribute \src "libresoc.v:140450.3-140458.6"
- wire $0\upd_l_r_upd$next[0:0]$6380
- attribute \src "libresoc.v:140299.3-140300.39"
+ attribute \src "libresoc.v:138580.3-138588.6"
+ wire $0\upd_l_r_upd$next[0:0]$6306
+ attribute \src "libresoc.v:138429.3-138430.39"
wire $0\upd_l_r_upd[0:0]
- attribute \src "libresoc.v:140441.3-140449.6"
- wire $0\upd_l_s_upd$next[0:0]$6377
- attribute \src "libresoc.v:140301.3-140302.39"
+ attribute \src "libresoc.v:138571.3-138579.6"
+ wire $0\upd_l_s_upd$next[0:0]$6303
+ attribute \src "libresoc.v:138431.3-138432.39"
wire $0\upd_l_s_upd[0:0]
- attribute \src "libresoc.v:140432.3-140440.6"
- wire $0\wri_l_r_wri$next[0:0]$6374
- attribute \src "libresoc.v:140303.3-140304.39"
+ attribute \src "libresoc.v:138562.3-138570.6"
+ wire $0\wri_l_r_wri$next[0:0]$6300
+ attribute \src "libresoc.v:138433.3-138434.39"
wire $0\wri_l_r_wri[0:0]
- attribute \src "libresoc.v:140423.3-140431.6"
- wire $1\adr_l_r_adr$next[0:0]$6372
- attribute \src "libresoc.v:139606.7-139606.25"
+ attribute \src "libresoc.v:138553.3-138561.6"
+ wire $1\adr_l_r_adr$next[0:0]$6298
+ attribute \src "libresoc.v:137736.7-137736.25"
wire $1\adr_l_r_adr[0:0]
- attribute \src "libresoc.v:139620.7-139620.20"
+ attribute \src "libresoc.v:137750.7-137750.20"
wire $1\alu_ok[0:0]
- attribute \src "libresoc.v:140588.3-140597.6"
+ attribute \src "libresoc.v:138718.3-138727.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:140598.3-140607.6"
+ attribute \src "libresoc.v:138728.3-138737.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:140578.3-140587.6"
- wire width 64 $1\ea_r$next[63:0]$6460
- attribute \src "libresoc.v:139666.14-139666.41"
+ attribute \src "libresoc.v:138708.3-138717.6"
+ wire width 64 $1\ea_r$next[63:0]$6386
+ attribute \src "libresoc.v:137796.14-137796.41"
wire width 64 $1\ea_r[63:0]
- attribute \src "libresoc.v:140653.3-140672.6"
+ attribute \src "libresoc.v:138783.3-138802.6"
wire width 64 $1\ldd_o[63:0]
- attribute \src "libresoc.v:140617.3-140640.6"
+ attribute \src "libresoc.v:138747.3-138770.6"
wire width 64 $1\lddata_r[63:0]
- attribute \src "libresoc.v:140520.3-140529.6"
- wire width 64 $1\ldo_r$next[63:0]$6445
- attribute \src "libresoc.v:139696.14-139696.42"
+ attribute \src "libresoc.v:138650.3-138659.6"
+ wire width 64 $1\ldo_r$next[63:0]$6371
+ attribute \src "libresoc.v:137826.14-137826.42"
wire width 64 $1\ldo_r[63:0]
- attribute \src "libresoc.v:139701.14-139701.62"
+ attribute \src "libresoc.v:137831.14-137831.62"
wire width 96 $1\ldst_port0_addr_i[95:0]
- attribute \src "libresoc.v:140608.3-140616.6"
- wire $1\ldst_port0_addr_i_ok$next[0:0]$6465
- attribute \src "libresoc.v:139706.7-139706.34"
+ attribute \src "libresoc.v:138738.3-138746.6"
+ wire $1\ldst_port0_addr_i_ok$next[0:0]$6391
+ attribute \src "libresoc.v:137836.7-137836.34"
wire $1\ldst_port0_addr_i_ok[0:0]
- attribute \src "libresoc.v:140697.3-140708.6"
+ attribute \src "libresoc.v:138827.3-138838.6"
wire width 64 $1\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:140468.3-140476.6"
- wire $1\lsd_l_r_lsd$next[0:0]$6387
- attribute \src "libresoc.v:139755.7-139755.25"
+ attribute \src "libresoc.v:138598.3-138606.6"
+ wire $1\lsd_l_r_lsd$next[0:0]$6313
+ attribute \src "libresoc.v:137885.7-137885.25"
wire $1\lsd_l_r_lsd[0:0]
- attribute \src "libresoc.v:140396.3-140404.6"
- wire $1\opc_l_r_opc$next[0:0]$6363
- attribute \src "libresoc.v:139769.7-139769.25"
+ attribute \src "libresoc.v:138526.3-138534.6"
+ wire $1\opc_l_r_opc$next[0:0]$6289
+ attribute \src "libresoc.v:137899.7-137899.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:140387.3-140395.6"
- wire $1\opc_l_s_opc$next[0:0]$6360
- attribute \src "libresoc.v:139773.7-139773.25"
+ attribute \src "libresoc.v:138517.3-138525.6"
+ wire $1\opc_l_s_opc$next[0:0]$6286
+ attribute \src "libresoc.v:137903.7-137903.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__byte_reverse$next[0:0]$6405
- attribute \src "libresoc.v:139902.7-139902.34"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__byte_reverse$next[0:0]$6331
+ attribute \src "libresoc.v:138032.7-138032.34"
wire $1\oper_r__byte_reverse[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 4 $1\oper_r__data_len$next[3:0]$6406
- attribute \src "libresoc.v:139906.13-139906.36"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 4 $1\oper_r__data_len$next[3:0]$6332
+ attribute \src "libresoc.v:138036.13-138036.36"
wire width 4 $1\oper_r__data_len[3:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 13 $1\oper_r__fn_unit$next[12:0]$6407
- attribute \src "libresoc.v:139924.14-139924.40"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 13 $1\oper_r__fn_unit$next[12:0]$6333
+ attribute \src "libresoc.v:138054.14-138054.40"
wire width 13 $1\oper_r__fn_unit[12:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 64 $1\oper_r__imm_data__data$next[63:0]$6408
- attribute \src "libresoc.v:139928.14-139928.59"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 64 $1\oper_r__imm_data__data$next[63:0]$6334
+ attribute \src "libresoc.v:138058.14-138058.59"
wire width 64 $1\oper_r__imm_data__data[63:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__imm_data__ok$next[0:0]$6409
- attribute \src "libresoc.v:139932.7-139932.34"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__imm_data__ok$next[0:0]$6335
+ attribute \src "libresoc.v:138062.7-138062.34"
wire $1\oper_r__imm_data__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 32 $1\oper_r__insn$next[31:0]$6410
- attribute \src "libresoc.v:139936.14-139936.34"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 32 $1\oper_r__insn$next[31:0]$6336
+ attribute \src "libresoc.v:138066.14-138066.34"
wire width 32 $1\oper_r__insn[31:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 7 $1\oper_r__insn_type$next[6:0]$6411
- attribute \src "libresoc.v:140014.13-140014.38"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 7 $1\oper_r__insn_type$next[6:0]$6337
+ attribute \src "libresoc.v:138144.13-138144.38"
wire width 7 $1\oper_r__insn_type[6:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__is_32bit$next[0:0]$6412
- attribute \src "libresoc.v:140018.7-140018.30"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__is_32bit$next[0:0]$6338
+ attribute \src "libresoc.v:138148.7-138148.30"
wire $1\oper_r__is_32bit[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__is_signed$next[0:0]$6413
- attribute \src "libresoc.v:140022.7-140022.31"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__is_signed$next[0:0]$6339
+ attribute \src "libresoc.v:138152.7-138152.31"
wire $1\oper_r__is_signed[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 2 $1\oper_r__ldst_mode$next[1:0]$6414
- attribute \src "libresoc.v:140031.13-140031.37"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 2 $1\oper_r__ldst_mode$next[1:0]$6340
+ attribute \src "libresoc.v:138161.13-138161.37"
wire width 2 $1\oper_r__ldst_mode[1:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__oe__oe$next[0:0]$6415
- attribute \src "libresoc.v:140035.7-140035.28"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__oe__oe$next[0:0]$6341
+ attribute \src "libresoc.v:138165.7-138165.28"
wire $1\oper_r__oe__oe[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__oe__ok$next[0:0]$6416
- attribute \src "libresoc.v:140039.7-140039.28"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__oe__ok$next[0:0]$6342
+ attribute \src "libresoc.v:138169.7-138169.28"
wire $1\oper_r__oe__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__rc__ok$next[0:0]$6417
- attribute \src "libresoc.v:140043.7-140043.28"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__rc__ok$next[0:0]$6343
+ attribute \src "libresoc.v:138173.7-138173.28"
wire $1\oper_r__rc__ok[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__rc__rc$next[0:0]$6418
- attribute \src "libresoc.v:140047.7-140047.28"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__rc__rc$next[0:0]$6344
+ attribute \src "libresoc.v:138177.7-138177.28"
wire $1\oper_r__rc__rc[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__sign_extend$next[0:0]$6419
- attribute \src "libresoc.v:140051.7-140051.33"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__sign_extend$next[0:0]$6345
+ attribute \src "libresoc.v:138181.7-138181.33"
wire $1\oper_r__sign_extend[0:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $1\oper_r__zero_a$next[0:0]$6420
- attribute \src "libresoc.v:140055.7-140055.28"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $1\oper_r__zero_a$next[0:0]$6346
+ attribute \src "libresoc.v:138185.7-138185.28"
wire $1\oper_r__zero_a[0:0]
- attribute \src "libresoc.v:140059.7-140059.21"
+ attribute \src "libresoc.v:138189.7-138189.21"
wire $1\p_st_go[0:0]
- attribute \src "libresoc.v:140641.3-140652.6"
+ attribute \src "libresoc.v:138771.3-138782.6"
wire width 64 $1\revnorev[63:0]
- attribute \src "libresoc.v:140414.3-140422.6"
- wire width 3 $1\src_l_r_src$next[2:0]$6369
- attribute \src "libresoc.v:140101.13-140101.31"
+ attribute \src "libresoc.v:138544.3-138552.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$6295
+ attribute \src "libresoc.v:138231.13-138231.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:140405.3-140413.6"
- wire width 3 $1\src_l_s_src$next[2:0]$6366
- attribute \src "libresoc.v:140105.13-140105.31"
+ attribute \src "libresoc.v:138535.3-138543.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$6292
+ attribute \src "libresoc.v:138235.13-138235.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:140530.3-140545.6"
- wire width 64 $1\src_r0$next[63:0]$6448
- attribute \src "libresoc.v:140109.14-140109.43"
+ attribute \src "libresoc.v:138660.3-138675.6"
+ wire width 64 $1\src_r0$next[63:0]$6374
+ attribute \src "libresoc.v:138239.14-138239.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:140546.3-140561.6"
- wire width 64 $1\src_r1$next[63:0]$6452
- attribute \src "libresoc.v:140113.14-140113.43"
+ attribute \src "libresoc.v:138676.3-138691.6"
+ wire width 64 $1\src_r1$next[63:0]$6378
+ attribute \src "libresoc.v:138243.14-138243.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:140562.3-140577.6"
- wire width 64 $1\src_r2$next[63:0]$6456
- attribute \src "libresoc.v:140117.14-140117.43"
+ attribute \src "libresoc.v:138692.3-138707.6"
+ wire width 64 $1\src_r2$next[63:0]$6382
+ attribute \src "libresoc.v:138247.14-138247.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:140673.3-140696.6"
+ attribute \src "libresoc.v:138803.3-138826.6"
wire width 64 $1\stdata_r[63:0]
- attribute \src "libresoc.v:140459.3-140467.6"
- wire $1\sto_l_r_sto$next[0:0]$6384
- attribute \src "libresoc.v:140127.7-140127.25"
+ attribute \src "libresoc.v:138589.3-138597.6"
+ wire $1\sto_l_r_sto$next[0:0]$6310
+ attribute \src "libresoc.v:138257.7-138257.25"
wire $1\sto_l_r_sto[0:0]
- attribute \src "libresoc.v:140450.3-140458.6"
- wire $1\upd_l_r_upd$next[0:0]$6381
- attribute \src "libresoc.v:140137.7-140137.25"
+ attribute \src "libresoc.v:138580.3-138588.6"
+ wire $1\upd_l_r_upd$next[0:0]$6307
+ attribute \src "libresoc.v:138267.7-138267.25"
wire $1\upd_l_r_upd[0:0]
- attribute \src "libresoc.v:140441.3-140449.6"
- wire $1\upd_l_s_upd$next[0:0]$6378
- attribute \src "libresoc.v:140141.7-140141.25"
+ attribute \src "libresoc.v:138571.3-138579.6"
+ wire $1\upd_l_s_upd$next[0:0]$6304
+ attribute \src "libresoc.v:138271.7-138271.25"
wire $1\upd_l_s_upd[0:0]
- attribute \src "libresoc.v:140432.3-140440.6"
- wire $1\wri_l_r_wri$next[0:0]$6375
- attribute \src "libresoc.v:140151.7-140151.25"
+ attribute \src "libresoc.v:138562.3-138570.6"
+ wire $1\wri_l_r_wri$next[0:0]$6301
+ attribute \src "libresoc.v:138281.7-138281.25"
wire $1\wri_l_r_wri[0:0]
- attribute \src "libresoc.v:140653.3-140672.6"
+ attribute \src "libresoc.v:138783.3-138802.6"
wire width 64 $2\ldd_o[63:0]
- attribute \src "libresoc.v:140617.3-140640.6"
+ attribute \src "libresoc.v:138747.3-138770.6"
wire width 64 $2\lddata_r[63:0]
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__byte_reverse$next[0:0]$6421
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 4 $2\oper_r__data_len$next[3:0]$6422
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 13 $2\oper_r__fn_unit$next[12:0]$6423
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 64 $2\oper_r__imm_data__data$next[63:0]$6424
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__imm_data__ok$next[0:0]$6425
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 32 $2\oper_r__insn$next[31:0]$6426
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 7 $2\oper_r__insn_type$next[6:0]$6427
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__is_32bit$next[0:0]$6428
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__is_signed$next[0:0]$6429
- attribute \src "libresoc.v:140477.3-140519.6"
- wire width 2 $2\oper_r__ldst_mode$next[1:0]$6430
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__oe__oe$next[0:0]$6431
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__oe__ok$next[0:0]$6432
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__rc__ok$next[0:0]$6433
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__rc__rc$next[0:0]$6434
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__sign_extend$next[0:0]$6435
- attribute \src "libresoc.v:140477.3-140519.6"
- wire $2\oper_r__zero_a$next[0:0]$6436
- attribute \src "libresoc.v:140530.3-140545.6"
- wire width 64 $2\src_r0$next[63:0]$6449
- attribute \src "libresoc.v:140546.3-140561.6"
- wire width 64 $2\src_r1$next[63:0]$6453
- attribute \src "libresoc.v:140562.3-140577.6"
- wire width 64 $2\src_r2$next[63:0]$6457
- attribute \src "libresoc.v:140673.3-140696.6"
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__byte_reverse$next[0:0]$6347
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 4 $2\oper_r__data_len$next[3:0]$6348
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 13 $2\oper_r__fn_unit$next[12:0]$6349
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 64 $2\oper_r__imm_data__data$next[63:0]$6350
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__imm_data__ok$next[0:0]$6351
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 32 $2\oper_r__insn$next[31:0]$6352
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 7 $2\oper_r__insn_type$next[6:0]$6353
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__is_32bit$next[0:0]$6354
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__is_signed$next[0:0]$6355
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire width 2 $2\oper_r__ldst_mode$next[1:0]$6356
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__oe__oe$next[0:0]$6357
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__oe__ok$next[0:0]$6358
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__rc__ok$next[0:0]$6359
+ attribute \src "libresoc.v:138607.3-138649.6"
+ wire $2\oper_r__rc__rc$next[0:0]$6360
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wire width 64 $2\stdata_r[63:0]
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+ attribute \src "libresoc.v:138311.19-138311.126"
+ wire $or$libresoc.v:138311$6180_Y
+ attribute \src "libresoc.v:138313.18-138313.129"
+ wire $or$libresoc.v:138313$6182_Y
+ attribute \src "libresoc.v:138315.19-138315.125"
+ wire $or$libresoc.v:138315$6184_Y
+ attribute \src "libresoc.v:138318.19-138318.119"
+ wire $or$libresoc.v:138318$6187_Y
+ attribute \src "libresoc.v:138323.18-138323.126"
+ wire $or$libresoc.v:138323$6192_Y
+ attribute \src "libresoc.v:138331.18-138331.156"
+ wire width 3 $or$libresoc.v:138331$6202_Y
+ attribute \src "libresoc.v:138337.18-138337.126"
+ wire $or$libresoc.v:138337$6209_Y
+ attribute \src "libresoc.v:138349.18-138349.116"
+ wire $or$libresoc.v:138349$6221_Y
+ attribute \src "libresoc.v:138353.18-138353.116"
+ wire $or$libresoc.v:138353$6225_Y
+ attribute \src "libresoc.v:138354.18-138354.127"
+ wire width 2 $or$libresoc.v:138354$6226_Y
+ attribute \src "libresoc.v:138356.18-138356.118"
+ wire $or$libresoc.v:138356$6228_Y
+ attribute \src "libresoc.v:138357.18-138357.118"
+ wire $or$libresoc.v:138357$6229_Y
+ attribute \src "libresoc.v:138358.18-138358.114"
+ wire $or$libresoc.v:138358$6230_Y
+ attribute \src "libresoc.v:138371.17-138371.124"
+ wire $or$libresoc.v:138371$6243_Y
+ attribute \src "libresoc.v:138372.18-138372.132"
+ wire $or$libresoc.v:138372$6244_Y
+ attribute \src "libresoc.v:138373.18-138373.134"
+ wire $or$libresoc.v:138373$6245_Y
+ attribute \src "libresoc.v:138327.19-138327.110"
+ wire width 96 $pos$libresoc.v:138327$6197_Y
+ attribute \src "libresoc.v:138329.19-138329.116"
+ wire width 64 $pos$libresoc.v:138329$6200_Y
+ attribute \src "libresoc.v:138330.19-138330.148"
+ wire width 64 $pos$libresoc.v:138330$6201_Y
+ attribute \src "libresoc.v:138332.19-138332.206"
+ wire width 64 $pos$libresoc.v:138332$6203_Y
+ attribute \src "libresoc.v:138334.19-138334.102"
+ wire width 64 $pos$libresoc.v:138334$6206_Y
+ attribute \src "libresoc.v:138335.19-138335.120"
+ wire width 64 $pos$libresoc.v:138335$6207_Y
+ attribute \src "libresoc.v:138336.19-138336.150"
+ wire width 64 $pos$libresoc.v:138336$6208_Y
+ attribute \src "libresoc.v:138359.18-138359.107"
+ wire width 64 $ternary$libresoc.v:138359$6231_Y
+ attribute \src "libresoc.v:138360.18-138360.112"
+ wire width 64 $ternary$libresoc.v:138360$6232_Y
+ attribute \src "libresoc.v:138361.18-138361.147"
+ wire width 64 $ternary$libresoc.v:138361$6233_Y
+ attribute \src "libresoc.v:138362.18-138362.155"
+ wire width 64 $ternary$libresoc.v:138362$6234_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
wire \alu_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
wire \alu_valid
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire input 3 \cu_ad__go_i
wire \exc_$signal$184
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \exc_$signal$185
- attribute \src "libresoc.v:139410.7-139410.15"
+ attribute \src "libresoc.v:137540.7-137540.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110"
wire \ld_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \wri_l_s_wri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
- cell $add $add$libresoc.v:140233$6309
+ cell $add $add$libresoc.v:138363$6235
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \src1_or_z
connect \B \src2_or_imm
- connect \Y $add$libresoc.v:140233$6309_Y
+ connect \Y $add$libresoc.v:138363$6235_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $and $and$libresoc.v:140156$6229
+ cell $and $and$libresoc.v:138286$6155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_valid
connect \B \$98
- connect \Y $and$libresoc.v:140156$6229_Y
+ connect \Y $and$libresoc.v:138286$6155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $and $and$libresoc.v:140157$6230
+ cell $and $and$libresoc.v:138287$6156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_valid
connect \B \adr_l_q_adr
- connect \Y $and$libresoc.v:140157$6230_Y
+ connect \Y $and$libresoc.v:138287$6156_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $and $and$libresoc.v:140158$6231
+ cell $and $and$libresoc.v:138288$6157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$102
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140158$6231_Y
+ connect \Y $and$libresoc.v:138288$6157_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:140159$6232
+ cell $and $and$libresoc.v:138289$6158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sto_l_q_sto
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140159$6232_Y
+ connect \Y $and$libresoc.v:138289$6158_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:140160$6233
+ cell $and $and$libresoc.v:138290$6159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$106
connect \B \rd_done
- connect \Y $and$libresoc.v:140160$6233_Y
+ connect \Y $and$libresoc.v:138290$6159_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446"
- cell $and $and$libresoc.v:140162$6235
+ cell $and $and$libresoc.v:138292$6161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$108
connect \B \op_is_st
- connect \Y $and$libresoc.v:140162$6235_Y
+ connect \Y $and$libresoc.v:138292$6161_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
- cell $and $and$libresoc.v:140163$6236
+ cell $and $and$libresoc.v:138293$6162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$110
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:140163$6236_Y
+ connect \Y $and$libresoc.v:138293$6162_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:140164$6237
+ cell $and $and$libresoc.v:138294$6163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd_done
connect \B \wri_l_q_wri
- connect \Y $and$libresoc.v:140164$6237_Y
+ connect \Y $and$libresoc.v:138294$6163_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:140165$6238
+ cell $and $and$libresoc.v:138295$6164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$114
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140165$6238_Y
+ connect \Y $and$libresoc.v:138295$6164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:140166$6239
+ cell $and $and$libresoc.v:138296$6165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$116
connect \B \lod_l_qn_lod
- connect \Y $and$libresoc.v:140166$6239_Y
+ connect \Y $and$libresoc.v:138296$6165_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:140167$6240
+ cell $and $and$libresoc.v:138297$6166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$118
connect \B \op_is_ld
- connect \Y $and$libresoc.v:140167$6240_Y
+ connect \Y $and$libresoc.v:138297$6166_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
- cell $and $and$libresoc.v:140168$6241
+ cell $and $and$libresoc.v:138298$6167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$120
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:140168$6241_Y
+ connect \Y $and$libresoc.v:138298$6167_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:140169$6242
+ cell $and $and$libresoc.v:138299$6168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd_l_q_upd
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140169$6242_Y
+ connect \Y $and$libresoc.v:138299$6168_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:140171$6244
+ cell $and $and$libresoc.v:138301$6170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$124
connect \B \$126
- connect \Y $and$libresoc.v:140171$6244_Y
+ connect \Y $and$libresoc.v:138301$6170_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:140173$6246
+ cell $and $and$libresoc.v:138303$6172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$128
connect \B \alu_valid
- connect \Y $and$libresoc.v:140173$6246_Y
+ connect \Y $and$libresoc.v:138303$6172_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455"
- cell $and $and$libresoc.v:140174$6247
+ cell $and $and$libresoc.v:138304$6173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$130
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:140174$6247_Y
+ connect \Y $and$libresoc.v:138304$6173_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:140178$6251
+ cell $and $and$libresoc.v:138308$6177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rst_l_q_rst
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140178$6251_Y
+ connect \Y $and$libresoc.v:138308$6177_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:140179$6252
+ cell $and $and$libresoc.v:138309$6178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$140
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:140179$6252_Y
+ connect \Y $and$libresoc.v:138309$6178_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $and $and$libresoc.v:140184$6257
+ cell $and $and$libresoc.v:138314$6183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$142
connect \B \$144
- connect \Y $and$libresoc.v:140184$6257_Y
+ connect \Y $and$libresoc.v:138314$6183_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463"
- cell $and $and$libresoc.v:140186$6259
+ cell $and $and$libresoc.v:138316$6185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$150
connect \B \$152
- connect \Y $and$libresoc.v:140186$6259_Y
+ connect \Y $and$libresoc.v:138316$6185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $and $and$libresoc.v:140189$6262
+ cell $and $and$libresoc.v:138319$6188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$158
- connect \Y $and$libresoc.v:140189$6262_Y
+ connect \Y $and$libresoc.v:138319$6188_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
- cell $and $and$libresoc.v:140191$6264
+ cell $and $and$libresoc.v:138321$6190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$162
connect \B \cu_wr__go_i [1]
- connect \Y $and$libresoc.v:140191$6264_Y
+ connect \Y $and$libresoc.v:138321$6190_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482"
- cell $and $and$libresoc.v:140194$6267
+ cell $and $and$libresoc.v:138324$6193
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { \cu_busy_o \cu_busy_o \cu_busy_o }
connect \B { 1'0 \$167 \op_is_ld }
- connect \Y $and$libresoc.v:140194$6267_Y
+ connect \Y $and$libresoc.v:138324$6193_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
- cell $and $and$libresoc.v:140195$6268
+ cell $and $and$libresoc.v:138325$6194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_ld
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140195$6268_Y
+ connect \Y $and$libresoc.v:138325$6194_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
- cell $and $and$libresoc.v:140196$6269
+ cell $and $and$libresoc.v:138326$6195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_st
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140196$6269_Y
+ connect \Y $and$libresoc.v:138326$6195_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494"
- cell $and $and$libresoc.v:140198$6272
+ cell $and $and$libresoc.v:138328$6198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_ok
connect \B \lsd_l_q_lsd
- connect \Y $and$libresoc.v:140198$6272_Y
+ connect \Y $and$libresoc.v:138328$6198_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312"
- cell $and $and$libresoc.v:140210$6286
+ cell $and $and$libresoc.v:138340$6212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_ld
connect \B \cu_ad__go_i
- connect \Y $and$libresoc.v:140210$6286_Y
+ connect \Y $and$libresoc.v:138340$6212_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313"
- cell $and $and$libresoc.v:140211$6287
+ cell $and $and$libresoc.v:138341$6213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_st
connect \B \cu_st__go_i
- connect \Y $and$libresoc.v:140211$6287_Y
+ connect \Y $and$libresoc.v:138341$6213_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $and $and$libresoc.v:140213$6289
+ cell $and $and$libresoc.v:138343$6215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_ok
connect \B \$30
- connect \Y $and$libresoc.v:140213$6289_Y
+ connect \Y $and$libresoc.v:138343$6215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $and $and$libresoc.v:140215$6291
+ cell $and $and$libresoc.v:138345$6217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $and$libresoc.v:140215$6291_Y
+ connect \Y $and$libresoc.v:138345$6217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $and $and$libresoc.v:140218$6294
+ cell $and $and$libresoc.v:138348$6220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \$41
- connect \Y $and$libresoc.v:140218$6294_Y
+ connect \Y $and$libresoc.v:138348$6220_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $and $and$libresoc.v:140222$6298
+ cell $and $and$libresoc.v:138352$6224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$47
connect \B \$49
- connect \Y $and$libresoc.v:140222$6298_Y
+ connect \Y $and$libresoc.v:138352$6224_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367"
- cell $and $and$libresoc.v:140225$6301
+ cell $and $and$libresoc.v:138355$6227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \addr_ok
connect \B \op_is_st
- connect \Y $and$libresoc.v:140225$6301_Y
+ connect \Y $and$libresoc.v:138355$6227_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:140234$6310
+ cell $and $and$libresoc.v:138364$6236
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:140234$6310_Y
+ connect \Y $and$libresoc.v:138364$6236_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:140236$6312
+ cell $and $and$libresoc.v:138366$6238
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$76
connect \B \$78
- connect \Y $and$libresoc.v:140236$6312_Y
+ connect \Y $and$libresoc.v:138366$6238_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $and $and$libresoc.v:140238$6314
+ cell $and $and$libresoc.v:138368$6240
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$80
connect \B \$82
- connect \Y $and$libresoc.v:140238$6314_Y
+ connect \Y $and$libresoc.v:138368$6240_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
- cell $and $and$libresoc.v:140239$6315
+ cell $and $and$libresoc.v:138369$6241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src_l_q_src [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:140239$6315_Y
+ connect \Y $and$libresoc.v:138369$6241_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
- cell $and $and$libresoc.v:140240$6316
+ cell $and $and$libresoc.v:138370$6242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$86
connect \B \op_is_st
- connect \Y $and$libresoc.v:140240$6316_Y
+ connect \Y $and$libresoc.v:138370$6242_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $and $and$libresoc.v:140245$6321
+ cell $and $and$libresoc.v:138375$6247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$92
- connect \Y $and$libresoc.v:140245$6321_Y
+ connect \Y $and$libresoc.v:138375$6247_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:140170$6243
+ cell $eq $eq$libresoc.v:138300$6169
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:140170$6243_Y
+ connect \Y $eq$libresoc.v:138300$6169_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:140190$6263
+ cell $eq $eq$libresoc.v:138320$6189
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:140190$6263_Y
+ connect \Y $eq$libresoc.v:138320$6189_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:140192$6265
+ cell $eq $eq$libresoc.v:138322$6191
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:140192$6265_Y
+ connect \Y $eq$libresoc.v:138322$6191_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511"
- cell $eq $eq$libresoc.v:140203$6278
+ cell $eq $eq$libresoc.v:138333$6204
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__data_len
connect \B 2'10
- connect \Y $eq$libresoc.v:140203$6278_Y
+ connect \Y $eq$libresoc.v:138333$6204_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308"
- cell $eq $eq$libresoc.v:140208$6284
+ cell $eq $eq$libresoc.v:138338$6210
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__insn_type
connect \B 7'0100110
- connect \Y $eq$libresoc.v:140208$6284_Y
+ connect \Y $eq$libresoc.v:138338$6210_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309"
- cell $eq $eq$libresoc.v:140209$6285
+ cell $eq $eq$libresoc.v:138339$6211
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__insn_type
connect \B 7'0100101
- connect \Y $eq$libresoc.v:140209$6285_Y
+ connect \Y $eq$libresoc.v:138339$6211_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:140217$6293
+ cell $eq $eq$libresoc.v:138347$6219
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:140217$6293_Y
+ connect \Y $eq$libresoc.v:138347$6219_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310"
- cell $eq $eq$libresoc.v:140221$6297
+ cell $eq $eq$libresoc.v:138351$6223
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oper_r__ldst_mode
connect \B 2'01
- connect \Y $eq$libresoc.v:140221$6297_Y
+ connect \Y $eq$libresoc.v:138351$6223_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
- cell $pos $extend$libresoc.v:140197$6270
+ cell $pos $extend$libresoc.v:138327$6196
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 96
connect \A \addr_r
- connect \Y $extend$libresoc.v:140197$6270_Y
+ connect \Y $extend$libresoc.v:138327$6196_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $extend$libresoc.v:140199$6273
+ cell $pos $extend$libresoc.v:138329$6199
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \ldst_port0_ld_data_o [7:0]
- connect \Y $extend$libresoc.v:140199$6273_Y
+ connect \Y $extend$libresoc.v:138329$6199_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $extend$libresoc.v:140204$6279
+ cell $pos $extend$libresoc.v:138334$6205
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \src_r2 [7:0]
- connect \Y $extend$libresoc.v:140204$6279_Y
+ connect \Y $extend$libresoc.v:138334$6205_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $not $not$libresoc.v:140182$6255
+ cell $not $not$libresoc.v:138312$6181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$147
- connect \Y $not$libresoc.v:140182$6255_Y
+ connect \Y $not$libresoc.v:138312$6181_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $not $not$libresoc.v:140187$6260
+ cell $not $not$libresoc.v:138317$6186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:140187$6260_Y
+ connect \Y $not$libresoc.v:138317$6186_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $not $not$libresoc.v:140212$6288
+ cell $not $not$libresoc.v:138342$6214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_valid
- connect \Y $not$libresoc.v:140212$6288_Y
+ connect \Y $not$libresoc.v:138342$6214_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344"
- cell $not $not$libresoc.v:140214$6290
+ cell $not $not$libresoc.v:138344$6216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rda_any
- connect \Y $not$libresoc.v:140214$6290_Y
+ connect \Y $not$libresoc.v:138344$6216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $not $not$libresoc.v:140216$6292
+ cell $not $not$libresoc.v:138346$6218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:140216$6292_Y
+ connect \Y $not$libresoc.v:138346$6218_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $not $not$libresoc.v:140220$6296
+ cell $not $not$libresoc.v:138350$6222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:140220$6296_Y
+ connect \Y $not$libresoc.v:138350$6222_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $not $not$libresoc.v:140235$6311
+ cell $not $not$libresoc.v:138365$6237
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A { \oper_r__imm_data__ok \oper_r__zero_a }
- connect \Y $not$libresoc.v:140235$6311_Y
+ connect \Y $not$libresoc.v:138365$6237_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
- cell $not $not$libresoc.v:140237$6313
+ cell $not $not$libresoc.v:138367$6239
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:140237$6313_Y
+ connect \Y $not$libresoc.v:138367$6239_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $not $not$libresoc.v:140244$6320
+ cell $not $not$libresoc.v:138374$6246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$93
- connect \Y $not$libresoc.v:140244$6320_Y
+ connect \Y $not$libresoc.v:138374$6246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $not $not$libresoc.v:140246$6322
+ cell $not $not$libresoc.v:138376$6248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_rd__rel_o [2]
- connect \Y $not$libresoc.v:140246$6322_Y
+ connect \Y $not$libresoc.v:138376$6248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
- cell $or $or$libresoc.v:140161$6234
+ cell $or $or$libresoc.v:138291$6160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_done_o
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140161$6234_Y
+ connect \Y $or$libresoc.v:138291$6160_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
- cell $or $or$libresoc.v:140172$6245
+ cell $or $or$libresoc.v:138302$6171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140172$6245_Y
+ connect \Y $or$libresoc.v:138302$6171_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:140175$6248
+ cell $or $or$libresoc.v:138305$6174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__go_i
connect \B \p_st_go
- connect \Y $or$libresoc.v:140175$6248_Y
+ connect \Y $or$libresoc.v:138305$6174_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:140176$6249
+ cell $or $or$libresoc.v:138306$6175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$134
connect \B \cu_wr__go_i [0]
- connect \Y $or$libresoc.v:140176$6249_Y
+ connect \Y $or$libresoc.v:138306$6175_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
- cell $or $or$libresoc.v:140177$6250
+ cell $or $or$libresoc.v:138307$6176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$136
connect \B \cu_wr__go_i [1]
- connect \Y $or$libresoc.v:140177$6250_Y
+ connect \Y $or$libresoc.v:138307$6176_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $or $or$libresoc.v:140180$6253
+ cell $or $or$libresoc.v:138310$6179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o
connect \B \cu_wr__rel_o [0]
- connect \Y $or$libresoc.v:140180$6253_Y
+ connect \Y $or$libresoc.v:138310$6179_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
- cell $or $or$libresoc.v:140181$6254
+ cell $or $or$libresoc.v:138311$6180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$145
connect \B \cu_wr__rel_o [1]
- connect \Y $or$libresoc.v:140181$6254_Y
+ connect \Y $or$libresoc.v:138311$6180_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
- cell $or $or$libresoc.v:140183$6256
+ cell $or $or$libresoc.v:138313$6182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140183$6256_Y
+ connect \Y $or$libresoc.v:138313$6182_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463"
- cell $or $or$libresoc.v:140185$6258
+ cell $or $or$libresoc.v:138315$6184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lod_l_qn_lod
connect \B \op_is_st
- connect \Y $or$libresoc.v:140185$6258_Y
+ connect \Y $or$libresoc.v:138315$6184_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465"
- cell $or $or$libresoc.v:140188$6261
+ cell $or $or$libresoc.v:138318$6187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$156
connect \B \op_is_ld
- connect \Y $or$libresoc.v:140188$6261_Y
+ connect \Y $or$libresoc.v:138318$6187_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
- cell $or $or$libresoc.v:140193$6266
+ cell $or $or$libresoc.v:138323$6192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__go_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140193$6266_Y
+ connect \Y $or$libresoc.v:138323$6192_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
- cell $or $or$libresoc.v:140201$6276
+ cell $or $or$libresoc.v:138331$6202
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:140201$6276_Y
+ connect \Y $or$libresoc.v:138331$6202_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
- cell $or $or$libresoc.v:140207$6283
+ cell $or $or$libresoc.v:138337$6209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_ad__go_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140207$6283_Y
+ connect \Y $or$libresoc.v:138337$6209_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $or $or$libresoc.v:140219$6295
+ cell $or $or$libresoc.v:138349$6221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$43
- connect \Y $or$libresoc.v:140219$6295_Y
+ connect \Y $or$libresoc.v:138349$6221_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357"
- cell $or $or$libresoc.v:140223$6299
+ cell $or $or$libresoc.v:138353$6225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_reset
connect \B \$51
- connect \Y $or$libresoc.v:140223$6299_Y
+ connect \Y $or$libresoc.v:138353$6225_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360"
- cell $or $or$libresoc.v:140224$6300
+ cell $or $or$libresoc.v:138354$6226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reset_w
connect \B { \$45 \$53 }
- connect \Y $or$libresoc.v:140224$6300_Y
+ connect \Y $or$libresoc.v:138354$6226_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
- cell $or $or$libresoc.v:140226$6302
+ cell $or $or$libresoc.v:138356$6228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \reset_s
connect \B \p_st_go
- connect \Y $or$libresoc.v:140226$6302_Y
+ connect \Y $or$libresoc.v:138356$6228_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372"
- cell $or $or$libresoc.v:140227$6303
+ cell $or $or$libresoc.v:138357$6229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \reset_s
connect \B \p_st_go
- connect \Y $or$libresoc.v:140227$6303_Y
+ connect \Y $or$libresoc.v:138357$6229_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372"
- cell $or $or$libresoc.v:140228$6304
+ cell $or $or$libresoc.v:138358$6230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$61
connect \B \ld_ok
- connect \Y $or$libresoc.v:140228$6304_Y
+ connect \Y $or$libresoc.v:138358$6230_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
- cell $or $or$libresoc.v:140241$6317
+ cell $or $or$libresoc.v:138371$6243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:140241$6317_Y
+ connect \Y $or$libresoc.v:138371$6243_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
- cell $or $or$libresoc.v:140242$6318
+ cell $or $or$libresoc.v:138372$6244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_rd__go_i [0]
connect \B \cu_rd__go_i [1]
- connect \Y $or$libresoc.v:140242$6318_Y
+ connect \Y $or$libresoc.v:138372$6244_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
- cell $or $or$libresoc.v:140243$6319
+ cell $or $or$libresoc.v:138373$6245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_rd__rel_o [0]
connect \B \cu_rd__rel_o [1]
- connect \Y $or$libresoc.v:140243$6319_Y
+ connect \Y $or$libresoc.v:138373$6245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
- cell $pos $pos$libresoc.v:140197$6271
+ cell $pos $pos$libresoc.v:138327$6197
parameter \A_SIGNED 0
parameter \A_WIDTH 96
parameter \Y_WIDTH 96
- connect \A $extend$libresoc.v:140197$6270_Y
- connect \Y $pos$libresoc.v:140197$6271_Y
+ connect \A $extend$libresoc.v:138327$6196_Y
+ connect \Y $pos$libresoc.v:138327$6197_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140199$6274
+ cell $pos $pos$libresoc.v:138329$6200
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:140199$6273_Y
- connect \Y $pos$libresoc.v:140199$6274_Y
+ connect \A $extend$libresoc.v:138329$6199_Y
+ connect \Y $pos$libresoc.v:138329$6200_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140200$6275
+ cell $pos $pos$libresoc.v:138330$6201
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] }
- connect \Y $pos$libresoc.v:140200$6275_Y
+ connect \Y $pos$libresoc.v:138330$6201_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140202$6277
+ cell $pos $pos$libresoc.v:138332$6203
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] }
- connect \Y $pos$libresoc.v:140202$6277_Y
+ connect \Y $pos$libresoc.v:138332$6203_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140204$6280
+ cell $pos $pos$libresoc.v:138334$6206
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:140204$6279_Y
- connect \Y $pos$libresoc.v:140204$6280_Y
+ connect \A $extend$libresoc.v:138334$6205_Y
+ connect \Y $pos$libresoc.v:138334$6206_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140205$6281
+ cell $pos $pos$libresoc.v:138335$6207
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] }
- connect \Y $pos$libresoc.v:140205$6281_Y
+ connect \Y $pos$libresoc.v:138335$6207_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36"
- cell $pos $pos$libresoc.v:140206$6282
+ cell $pos $pos$libresoc.v:138336$6208
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] }
- connect \Y $pos$libresoc.v:140206$6282_Y
+ connect \Y $pos$libresoc.v:138336$6208_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:140229$6305
+ cell $mux $ternary$libresoc.v:138359$6231
parameter \WIDTH 64
connect \A \ldo_r
connect \B \ldd_o
connect \S \ld_ok
- connect \Y $ternary$libresoc.v:140229$6305_Y
+ connect \Y $ternary$libresoc.v:138359$6231_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:140230$6306
+ cell $mux $ternary$libresoc.v:138360$6232
parameter \WIDTH 64
connect \A \ea_r
connect \B \alu_o
connect \S \alu_l_q_alu
- connect \Y $ternary$libresoc.v:140230$6306_Y
+ connect \Y $ternary$libresoc.v:138360$6232_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406"
- cell $mux $ternary$libresoc.v:140231$6307
+ cell $mux $ternary$libresoc.v:138361$6233
parameter \WIDTH 64
connect \A \src_r0
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \oper_r__zero_a
- connect \Y $ternary$libresoc.v:140231$6307_Y
+ connect \Y $ternary$libresoc.v:138361$6233_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
- cell $mux $ternary$libresoc.v:140232$6308
+ cell $mux $ternary$libresoc.v:138362$6234
parameter \WIDTH 64
connect \A \src_r1
connect \B \oper_r__imm_data__data
connect \S \oper_r__imm_data__ok
- connect \Y $ternary$libresoc.v:140232$6308_Y
+ connect \Y $ternary$libresoc.v:138362$6234_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140317.9-140323.4"
+ attribute \src "libresoc.v:138447.9-138453.4"
cell \adr_l \adr_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_adr \adr_l_s_adr
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140324.15-140330.4"
+ attribute \src "libresoc.v:138454.15-138460.4"
cell \alu_l$128 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140331.9-140337.4"
+ attribute \src "libresoc.v:138461.9-138467.4"
cell \lod_l \lod_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_lod \lod_l_s_lod
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140338.9-140344.4"
+ attribute \src "libresoc.v:138468.9-138474.4"
cell \lsd_l \lsd_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_lsd \lsd_l_s_lsd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140345.15-140351.4"
+ attribute \src "libresoc.v:138475.15-138481.4"
cell \opc_l$126 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140352.15-140358.4"
+ attribute \src "libresoc.v:138482.15-138488.4"
cell \rst_l$129 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140359.15-140365.4"
+ attribute \src "libresoc.v:138489.15-138495.4"
cell \src_l$127 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_src \src_l_s_src
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140366.9-140372.4"
+ attribute \src "libresoc.v:138496.9-138502.4"
cell \sto_l \sto_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_sto \sto_l_s_sto
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140373.9-140379.4"
+ attribute \src "libresoc.v:138503.9-138509.4"
cell \upd_l \upd_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_upd \upd_l_s_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:140380.9-140386.4"
+ attribute \src "libresoc.v:138510.9-138516.4"
cell \wri_l \wri_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_wri \wri_l_r_wri
connect \s_wri \wri_l_s_wri
end
- attribute \src "libresoc.v:139410.7-139410.20"
- process $proc$libresoc.v:139410$6471
+ attribute \src "libresoc.v:137540.7-137540.20"
+ process $proc$libresoc.v:137540$6397
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:139606.7-139606.25"
- process $proc$libresoc.v:139606$6472
+ attribute \src "libresoc.v:137736.7-137736.25"
+ process $proc$libresoc.v:137736$6398
assign { } { }
assign $1\adr_l_r_adr[0:0] 1'1
sync always
sync init
update \adr_l_r_adr $1\adr_l_r_adr[0:0]
end
- attribute \src "libresoc.v:139620.7-139620.20"
- process $proc$libresoc.v:139620$6473
+ attribute \src "libresoc.v:137750.7-137750.20"
+ process $proc$libresoc.v:137750$6399
assign { } { }
assign $1\alu_ok[0:0] 1'0
sync always
sync init
update \alu_ok $1\alu_ok[0:0]
end
- attribute \src "libresoc.v:139666.14-139666.41"
- process $proc$libresoc.v:139666$6474
+ attribute \src "libresoc.v:137796.14-137796.41"
+ process $proc$libresoc.v:137796$6400
assign { } { }
assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ea_r $1\ea_r[63:0]
end
- attribute \src "libresoc.v:139696.14-139696.42"
- process $proc$libresoc.v:139696$6475
+ attribute \src "libresoc.v:137826.14-137826.42"
+ process $proc$libresoc.v:137826$6401
assign { } { }
assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ldo_r $1\ldo_r[63:0]
end
- attribute \src "libresoc.v:139701.14-139701.62"
- process $proc$libresoc.v:139701$6476
+ attribute \src "libresoc.v:137831.14-137831.62"
+ process $proc$libresoc.v:137831$6402
assign { } { }
assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0]
end
- attribute \src "libresoc.v:139706.7-139706.34"
- process $proc$libresoc.v:139706$6477
+ attribute \src "libresoc.v:137836.7-137836.34"
+ process $proc$libresoc.v:137836$6403
assign { } { }
assign $1\ldst_port0_addr_i_ok[0:0] 1'0
sync always
sync init
update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0]
end
- attribute \src "libresoc.v:139755.7-139755.25"
- process $proc$libresoc.v:139755$6478
+ attribute \src "libresoc.v:137885.7-137885.25"
+ process $proc$libresoc.v:137885$6404
assign { } { }
assign $1\lsd_l_r_lsd[0:0] 1'1
sync always
sync init
update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0]
end
- attribute \src "libresoc.v:139769.7-139769.25"
- process $proc$libresoc.v:139769$6479
+ attribute \src "libresoc.v:137899.7-137899.25"
+ process $proc$libresoc.v:137899$6405
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:139773.7-139773.25"
- process $proc$libresoc.v:139773$6480
+ attribute \src "libresoc.v:137903.7-137903.25"
+ process $proc$libresoc.v:137903$6406
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:139902.7-139902.34"
- process $proc$libresoc.v:139902$6481
+ attribute \src "libresoc.v:138032.7-138032.34"
+ process $proc$libresoc.v:138032$6407
assign { } { }
assign $1\oper_r__byte_reverse[0:0] 1'0
sync always
sync init
update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0]
end
- attribute \src "libresoc.v:139906.13-139906.36"
- process $proc$libresoc.v:139906$6482
+ attribute \src "libresoc.v:138036.13-138036.36"
+ process $proc$libresoc.v:138036$6408
assign { } { }
assign $1\oper_r__data_len[3:0] 4'0000
sync always
sync init
update \oper_r__data_len $1\oper_r__data_len[3:0]
end
- attribute \src "libresoc.v:139924.14-139924.40"
- process $proc$libresoc.v:139924$6483
+ attribute \src "libresoc.v:138054.14-138054.40"
+ process $proc$libresoc.v:138054$6409
assign { } { }
assign $1\oper_r__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \oper_r__fn_unit $1\oper_r__fn_unit[12:0]
end
- attribute \src "libresoc.v:139928.14-139928.59"
- process $proc$libresoc.v:139928$6484
+ attribute \src "libresoc.v:138058.14-138058.59"
+ process $proc$libresoc.v:138058$6410
assign { } { }
assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0]
end
- attribute \src "libresoc.v:139932.7-139932.34"
- process $proc$libresoc.v:139932$6485
+ attribute \src "libresoc.v:138062.7-138062.34"
+ process $proc$libresoc.v:138062$6411
assign { } { }
assign $1\oper_r__imm_data__ok[0:0] 1'0
sync always
sync init
update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:139936.14-139936.34"
- process $proc$libresoc.v:139936$6486
+ attribute \src "libresoc.v:138066.14-138066.34"
+ process $proc$libresoc.v:138066$6412
assign { } { }
assign $1\oper_r__insn[31:0] 0
sync always
sync init
update \oper_r__insn $1\oper_r__insn[31:0]
end
- attribute \src "libresoc.v:140014.13-140014.38"
- process $proc$libresoc.v:140014$6487
+ attribute \src "libresoc.v:138144.13-138144.38"
+ process $proc$libresoc.v:138144$6413
assign { } { }
assign $1\oper_r__insn_type[6:0] 7'0000000
sync always
sync init
update \oper_r__insn_type $1\oper_r__insn_type[6:0]
end
- attribute \src "libresoc.v:140018.7-140018.30"
- process $proc$libresoc.v:140018$6488
+ attribute \src "libresoc.v:138148.7-138148.30"
+ process $proc$libresoc.v:138148$6414
assign { } { }
assign $1\oper_r__is_32bit[0:0] 1'0
sync always
sync init
update \oper_r__is_32bit $1\oper_r__is_32bit[0:0]
end
- attribute \src "libresoc.v:140022.7-140022.31"
- process $proc$libresoc.v:140022$6489
+ attribute \src "libresoc.v:138152.7-138152.31"
+ process $proc$libresoc.v:138152$6415
assign { } { }
assign $1\oper_r__is_signed[0:0] 1'0
sync always
sync init
update \oper_r__is_signed $1\oper_r__is_signed[0:0]
end
- attribute \src "libresoc.v:140031.13-140031.37"
- process $proc$libresoc.v:140031$6490
+ attribute \src "libresoc.v:138161.13-138161.37"
+ process $proc$libresoc.v:138161$6416
assign { } { }
assign $1\oper_r__ldst_mode[1:0] 2'00
sync always
sync init
update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0]
end
- attribute \src "libresoc.v:140035.7-140035.28"
- process $proc$libresoc.v:140035$6491
+ attribute \src "libresoc.v:138165.7-138165.28"
+ process $proc$libresoc.v:138165$6417
assign { } { }
assign $1\oper_r__oe__oe[0:0] 1'0
sync always
sync init
update \oper_r__oe__oe $1\oper_r__oe__oe[0:0]
end
- attribute \src "libresoc.v:140039.7-140039.28"
- process $proc$libresoc.v:140039$6492
+ attribute \src "libresoc.v:138169.7-138169.28"
+ process $proc$libresoc.v:138169$6418
assign { } { }
assign $1\oper_r__oe__ok[0:0] 1'0
sync always
sync init
update \oper_r__oe__ok $1\oper_r__oe__ok[0:0]
end
- attribute \src "libresoc.v:140043.7-140043.28"
- process $proc$libresoc.v:140043$6493
+ attribute \src "libresoc.v:138173.7-138173.28"
+ process $proc$libresoc.v:138173$6419
assign { } { }
assign $1\oper_r__rc__ok[0:0] 1'0
sync always
sync init
update \oper_r__rc__ok $1\oper_r__rc__ok[0:0]
end
- attribute \src "libresoc.v:140047.7-140047.28"
- process $proc$libresoc.v:140047$6494
+ attribute \src "libresoc.v:138177.7-138177.28"
+ process $proc$libresoc.v:138177$6420
assign { } { }
assign $1\oper_r__rc__rc[0:0] 1'0
sync always
sync init
update \oper_r__rc__rc $1\oper_r__rc__rc[0:0]
end
- attribute \src "libresoc.v:140051.7-140051.33"
- process $proc$libresoc.v:140051$6495
+ attribute \src "libresoc.v:138181.7-138181.33"
+ process $proc$libresoc.v:138181$6421
assign { } { }
assign $1\oper_r__sign_extend[0:0] 1'0
sync always
sync init
update \oper_r__sign_extend $1\oper_r__sign_extend[0:0]
end
- attribute \src "libresoc.v:140055.7-140055.28"
- process $proc$libresoc.v:140055$6496
+ attribute \src "libresoc.v:138185.7-138185.28"
+ process $proc$libresoc.v:138185$6422
assign { } { }
assign $1\oper_r__zero_a[0:0] 1'0
sync always
sync init
update \oper_r__zero_a $1\oper_r__zero_a[0:0]
end
- attribute \src "libresoc.v:140059.7-140059.21"
- process $proc$libresoc.v:140059$6497
+ attribute \src "libresoc.v:138189.7-138189.21"
+ process $proc$libresoc.v:138189$6423
assign { } { }
assign $1\p_st_go[0:0] 1'0
sync always
sync init
update \p_st_go $1\p_st_go[0:0]
end
- attribute \src "libresoc.v:140101.13-140101.31"
- process $proc$libresoc.v:140101$6498
+ attribute \src "libresoc.v:138231.13-138231.31"
+ process $proc$libresoc.v:138231$6424
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:140105.13-140105.31"
- process $proc$libresoc.v:140105$6499
+ attribute \src "libresoc.v:138235.13-138235.31"
+ process $proc$libresoc.v:138235$6425
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:140109.14-140109.43"
- process $proc$libresoc.v:140109$6500
+ attribute \src "libresoc.v:138239.14-138239.43"
+ process $proc$libresoc.v:138239$6426
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:140113.14-140113.43"
- process $proc$libresoc.v:140113$6501
+ attribute \src "libresoc.v:138243.14-138243.43"
+ process $proc$libresoc.v:138243$6427
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:140117.14-140117.43"
- process $proc$libresoc.v:140117$6502
+ attribute \src "libresoc.v:138247.14-138247.43"
+ process $proc$libresoc.v:138247$6428
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:140127.7-140127.25"
- process $proc$libresoc.v:140127$6503
+ attribute \src "libresoc.v:138257.7-138257.25"
+ process $proc$libresoc.v:138257$6429
assign { } { }
assign $1\sto_l_r_sto[0:0] 1'1
sync always
sync init
update \sto_l_r_sto $1\sto_l_r_sto[0:0]
end
- attribute \src "libresoc.v:140137.7-140137.25"
- process $proc$libresoc.v:140137$6504
+ attribute \src "libresoc.v:138267.7-138267.25"
+ process $proc$libresoc.v:138267$6430
assign { } { }
assign $1\upd_l_r_upd[0:0] 1'1
sync always
sync init
update \upd_l_r_upd $1\upd_l_r_upd[0:0]
end
- attribute \src "libresoc.v:140141.7-140141.25"
- process $proc$libresoc.v:140141$6505
+ attribute \src "libresoc.v:138271.7-138271.25"
+ process $proc$libresoc.v:138271$6431
assign { } { }
assign $1\upd_l_s_upd[0:0] 1'0
sync always
sync init
update \upd_l_s_upd $1\upd_l_s_upd[0:0]
end
- attribute \src "libresoc.v:140151.7-140151.25"
- process $proc$libresoc.v:140151$6506
+ attribute \src "libresoc.v:138281.7-138281.25"
+ process $proc$libresoc.v:138281$6432
assign { } { }
assign $1\wri_l_r_wri[0:0] 1'1
sync always
sync init
update \wri_l_r_wri $1\wri_l_r_wri[0:0]
end
- attribute \src "libresoc.v:140247.3-140248.57"
- process $proc$libresoc.v:140247$6323
+ attribute \src "libresoc.v:138377.3-138378.57"
+ process $proc$libresoc.v:138377$6249
assign { } { }
assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next
sync posedge \coresync_clk
update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0]
end
- attribute \src "libresoc.v:140249.3-140250.33"
- process $proc$libresoc.v:140249$6324
+ attribute \src "libresoc.v:138379.3-138380.33"
+ process $proc$libresoc.v:138379$6250
assign { } { }
assign $0\ldst_port0_addr_i[95:0] \$175
sync posedge \coresync_clk
update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0]
end
- attribute \src "libresoc.v:140251.3-140252.21"
- process $proc$libresoc.v:140251$6325
+ attribute \src "libresoc.v:138381.3-138382.21"
+ process $proc$libresoc.v:138381$6251
assign { } { }
assign $0\alu_ok[0:0] \$96
sync posedge \coresync_clk
update \alu_ok $0\alu_ok[0:0]
end
- attribute \src "libresoc.v:140253.3-140254.25"
- process $proc$libresoc.v:140253$6326
+ attribute \src "libresoc.v:138383.3-138384.25"
+ process $proc$libresoc.v:138383$6252
assign { } { }
assign $0\ea_r[63:0] \ea_r$next
sync posedge \coresync_clk
update \ea_r $0\ea_r[63:0]
end
- attribute \src "libresoc.v:140255.3-140256.29"
- process $proc$libresoc.v:140255$6327
+ attribute \src "libresoc.v:138385.3-138386.29"
+ process $proc$libresoc.v:138385$6253
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:140257.3-140258.29"
- process $proc$libresoc.v:140257$6328
+ attribute \src "libresoc.v:138387.3-138388.29"
+ process $proc$libresoc.v:138387$6254
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:140259.3-140260.29"
- process $proc$libresoc.v:140259$6329
+ attribute \src "libresoc.v:138389.3-138390.29"
+ process $proc$libresoc.v:138389$6255
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:140261.3-140262.27"
- process $proc$libresoc.v:140261$6330
+ attribute \src "libresoc.v:138391.3-138392.27"
+ process $proc$libresoc.v:138391$6256
assign { } { }
assign $0\ldo_r[63:0] \ldo_r$next
sync posedge \coresync_clk
update \ldo_r $0\ldo_r[63:0]
end
- attribute \src "libresoc.v:140263.3-140264.51"
- process $proc$libresoc.v:140263$6331
+ attribute \src "libresoc.v:138393.3-138394.51"
+ process $proc$libresoc.v:138393$6257
assign { } { }
assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next
sync posedge \coresync_clk
update \oper_r__insn_type $0\oper_r__insn_type[6:0]
end
- attribute \src "libresoc.v:140265.3-140266.47"
- process $proc$libresoc.v:140265$6332
+ attribute \src "libresoc.v:138395.3-138396.47"
+ process $proc$libresoc.v:138395$6258
assign { } { }
assign $0\oper_r__fn_unit[12:0] \oper_r__fn_unit$next
sync posedge \coresync_clk
update \oper_r__fn_unit $0\oper_r__fn_unit[12:0]
end
- attribute \src "libresoc.v:140267.3-140268.61"
- process $proc$libresoc.v:140267$6333
+ attribute \src "libresoc.v:138397.3-138398.61"
+ process $proc$libresoc.v:138397$6259
assign { } { }
assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next
sync posedge \coresync_clk
update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0]
end
- attribute \src "libresoc.v:140269.3-140270.57"
- process $proc$libresoc.v:140269$6334
+ attribute \src "libresoc.v:138399.3-138400.57"
+ process $proc$libresoc.v:138399$6260
assign { } { }
assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next
sync posedge \coresync_clk
update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:140271.3-140272.45"
- process $proc$libresoc.v:140271$6335
+ attribute \src "libresoc.v:138401.3-138402.45"
+ process $proc$libresoc.v:138401$6261
assign { } { }
assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next
sync posedge \coresync_clk
update \oper_r__zero_a $0\oper_r__zero_a[0:0]
end
- attribute \src "libresoc.v:140273.3-140274.45"
- process $proc$libresoc.v:140273$6336
+ attribute \src "libresoc.v:138403.3-138404.45"
+ process $proc$libresoc.v:138403$6262
assign { } { }
assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next
sync posedge \coresync_clk
update \oper_r__rc__rc $0\oper_r__rc__rc[0:0]
end
- attribute \src "libresoc.v:140275.3-140276.45"
- process $proc$libresoc.v:140275$6337
+ attribute \src "libresoc.v:138405.3-138406.45"
+ process $proc$libresoc.v:138405$6263
assign { } { }
assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next
sync posedge \coresync_clk
update \oper_r__rc__ok $0\oper_r__rc__ok[0:0]
end
- attribute \src "libresoc.v:140277.3-140278.45"
- process $proc$libresoc.v:140277$6338
+ attribute \src "libresoc.v:138407.3-138408.45"
+ process $proc$libresoc.v:138407$6264
assign { } { }
assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next
sync posedge \coresync_clk
update \oper_r__oe__oe $0\oper_r__oe__oe[0:0]
end
- attribute \src "libresoc.v:140279.3-140280.45"
- process $proc$libresoc.v:140279$6339
+ attribute \src "libresoc.v:138409.3-138410.45"
+ process $proc$libresoc.v:138409$6265
assign { } { }
assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next
sync posedge \coresync_clk
update \oper_r__oe__ok $0\oper_r__oe__ok[0:0]
end
- attribute \src "libresoc.v:140281.3-140282.49"
- process $proc$libresoc.v:140281$6340
+ attribute \src "libresoc.v:138411.3-138412.49"
+ process $proc$libresoc.v:138411$6266
assign { } { }
assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next
sync posedge \coresync_clk
update \oper_r__is_32bit $0\oper_r__is_32bit[0:0]
end
- attribute \src "libresoc.v:140283.3-140284.51"
- process $proc$libresoc.v:140283$6341
+ attribute \src "libresoc.v:138413.3-138414.51"
+ process $proc$libresoc.v:138413$6267
assign { } { }
assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next
sync posedge \coresync_clk
update \oper_r__is_signed $0\oper_r__is_signed[0:0]
end
- attribute \src "libresoc.v:140285.3-140286.49"
- process $proc$libresoc.v:140285$6342
+ attribute \src "libresoc.v:138415.3-138416.49"
+ process $proc$libresoc.v:138415$6268
assign { } { }
assign $0\oper_r__data_len[3:0] \oper_r__data_len$next
sync posedge \coresync_clk
update \oper_r__data_len $0\oper_r__data_len[3:0]
end
- attribute \src "libresoc.v:140287.3-140288.57"
- process $proc$libresoc.v:140287$6343
+ attribute \src "libresoc.v:138417.3-138418.57"
+ process $proc$libresoc.v:138417$6269
assign { } { }
assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next
sync posedge \coresync_clk
update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0]
end
- attribute \src "libresoc.v:140289.3-140290.55"
- process $proc$libresoc.v:140289$6344
+ attribute \src "libresoc.v:138419.3-138420.55"
+ process $proc$libresoc.v:138419$6270
assign { } { }
assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next
sync posedge \coresync_clk
update \oper_r__sign_extend $0\oper_r__sign_extend[0:0]
end
- attribute \src "libresoc.v:140291.3-140292.51"
- process $proc$libresoc.v:140291$6345
+ attribute \src "libresoc.v:138421.3-138422.51"
+ process $proc$libresoc.v:138421$6271
assign { } { }
assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next
sync posedge \coresync_clk
update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0]
end
- attribute \src "libresoc.v:140293.3-140294.41"
- process $proc$libresoc.v:140293$6346
+ attribute \src "libresoc.v:138423.3-138424.41"
+ process $proc$libresoc.v:138423$6272
assign { } { }
assign $0\oper_r__insn[31:0] \oper_r__insn$next
sync posedge \coresync_clk
update \oper_r__insn $0\oper_r__insn[31:0]
end
- attribute \src "libresoc.v:140295.3-140296.39"
- process $proc$libresoc.v:140295$6347
+ attribute \src "libresoc.v:138425.3-138426.39"
+ process $proc$libresoc.v:138425$6273
assign { } { }
assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next
sync posedge \coresync_clk
update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0]
end
- attribute \src "libresoc.v:140297.3-140298.39"
- process $proc$libresoc.v:140297$6348
+ attribute \src "libresoc.v:138427.3-138428.39"
+ process $proc$libresoc.v:138427$6274
assign { } { }
assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next
sync posedge \coresync_clk
update \sto_l_r_sto $0\sto_l_r_sto[0:0]
end
- attribute \src "libresoc.v:140299.3-140300.39"
- process $proc$libresoc.v:140299$6349
+ attribute \src "libresoc.v:138429.3-138430.39"
+ process $proc$libresoc.v:138429$6275
assign { } { }
assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next
sync posedge \coresync_clk
update \upd_l_r_upd $0\upd_l_r_upd[0:0]
end
- attribute \src "libresoc.v:140301.3-140302.39"
- process $proc$libresoc.v:140301$6350
+ attribute \src "libresoc.v:138431.3-138432.39"
+ process $proc$libresoc.v:138431$6276
assign { } { }
assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next
sync posedge \coresync_clk
update \upd_l_s_upd $0\upd_l_s_upd[0:0]
end
- attribute \src "libresoc.v:140303.3-140304.39"
- process $proc$libresoc.v:140303$6351
+ attribute \src "libresoc.v:138433.3-138434.39"
+ process $proc$libresoc.v:138433$6277
assign { } { }
assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next
sync posedge \coresync_clk
update \wri_l_r_wri $0\wri_l_r_wri[0:0]
end
- attribute \src "libresoc.v:140305.3-140306.39"
- process $proc$libresoc.v:140305$6352
+ attribute \src "libresoc.v:138435.3-138436.39"
+ process $proc$libresoc.v:138435$6278
assign { } { }
assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next
sync posedge \coresync_clk
update \adr_l_r_adr $0\adr_l_r_adr[0:0]
end
- attribute \src "libresoc.v:140307.3-140308.39"
- process $proc$libresoc.v:140307$6353
+ attribute \src "libresoc.v:138437.3-138438.39"
+ process $proc$libresoc.v:138437$6279
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:140309.3-140310.39"
- process $proc$libresoc.v:140309$6354
+ attribute \src "libresoc.v:138439.3-138440.39"
+ process $proc$libresoc.v:138439$6280
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:140311.3-140312.39"
- process $proc$libresoc.v:140311$6355
+ attribute \src "libresoc.v:138441.3-138442.39"
+ process $proc$libresoc.v:138441$6281
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:140313.3-140314.39"
- process $proc$libresoc.v:140313$6356
+ attribute \src "libresoc.v:138443.3-138444.39"
+ process $proc$libresoc.v:138443$6282
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:140315.3-140316.28"
- process $proc$libresoc.v:140315$6357
+ attribute \src "libresoc.v:138445.3-138446.28"
+ process $proc$libresoc.v:138445$6283
assign { } { }
assign $0\p_st_go[0:0] \cu_st__go_i
sync posedge \coresync_clk
update \p_st_go $0\p_st_go[0:0]
end
- attribute \src "libresoc.v:140387.3-140395.6"
- process $proc$libresoc.v:140387$6358
+ attribute \src "libresoc.v:138517.3-138525.6"
+ process $proc$libresoc.v:138517$6284
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$6359 $1\opc_l_s_opc$next[0:0]$6360
- attribute \src "libresoc.v:140388.5-140388.29"
+ assign $0\opc_l_s_opc$next[0:0]$6285 $1\opc_l_s_opc$next[0:0]$6286
+ attribute \src "libresoc.v:138518.5-138518.29"
switch \initial
- attribute \src "libresoc.v:140388.9-140388.17"
+ attribute \src "libresoc.v:138518.9-138518.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$6360 1'0
+ assign $1\opc_l_s_opc$next[0:0]$6286 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$6360 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$6286 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6359
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6285
end
- attribute \src "libresoc.v:140396.3-140404.6"
- process $proc$libresoc.v:140396$6361
+ attribute \src "libresoc.v:138526.3-138534.6"
+ process $proc$libresoc.v:138526$6287
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$6362 $1\opc_l_r_opc$next[0:0]$6363
- attribute \src "libresoc.v:140397.5-140397.29"
+ assign $0\opc_l_r_opc$next[0:0]$6288 $1\opc_l_r_opc$next[0:0]$6289
+ attribute \src "libresoc.v:138527.5-138527.29"
switch \initial
- attribute \src "libresoc.v:140397.9-140397.17"
+ attribute \src "libresoc.v:138527.9-138527.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$6363 1'1
+ assign $1\opc_l_r_opc$next[0:0]$6289 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$6363 \reset_o
+ assign $1\opc_l_r_opc$next[0:0]$6289 \reset_o
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6362
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6288
end
- attribute \src "libresoc.v:140405.3-140413.6"
- process $proc$libresoc.v:140405$6364
+ attribute \src "libresoc.v:138535.3-138543.6"
+ process $proc$libresoc.v:138535$6290
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$6365 $1\src_l_s_src$next[2:0]$6366
- attribute \src "libresoc.v:140406.5-140406.29"
+ assign $0\src_l_s_src$next[2:0]$6291 $1\src_l_s_src$next[2:0]$6292
+ attribute \src "libresoc.v:138536.5-138536.29"
switch \initial
- attribute \src "libresoc.v:140406.9-140406.17"
+ attribute \src "libresoc.v:138536.9-138536.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$6366 3'000
+ assign $1\src_l_s_src$next[2:0]$6292 3'000
case
- assign $1\src_l_s_src$next[2:0]$6366 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$6292 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6365
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6291
end
- attribute \src "libresoc.v:140414.3-140422.6"
- process $proc$libresoc.v:140414$6367
+ attribute \src "libresoc.v:138544.3-138552.6"
+ process $proc$libresoc.v:138544$6293
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$6368 $1\src_l_r_src$next[2:0]$6369
- attribute \src "libresoc.v:140415.5-140415.29"
+ assign $0\src_l_r_src$next[2:0]$6294 $1\src_l_r_src$next[2:0]$6295
+ attribute \src "libresoc.v:138545.5-138545.29"
switch \initial
- attribute \src "libresoc.v:140415.9-140415.17"
+ attribute \src "libresoc.v:138545.9-138545.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$6369 3'111
+ assign $1\src_l_r_src$next[2:0]$6295 3'111
case
- assign $1\src_l_r_src$next[2:0]$6369 \reset_r
+ assign $1\src_l_r_src$next[2:0]$6295 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6368
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6294
end
- attribute \src "libresoc.v:140423.3-140431.6"
- process $proc$libresoc.v:140423$6370
+ attribute \src "libresoc.v:138553.3-138561.6"
+ process $proc$libresoc.v:138553$6296
assign { } { }
assign { } { }
- assign $0\adr_l_r_adr$next[0:0]$6371 $1\adr_l_r_adr$next[0:0]$6372
- attribute \src "libresoc.v:140424.5-140424.29"
+ assign $0\adr_l_r_adr$next[0:0]$6297 $1\adr_l_r_adr$next[0:0]$6298
+ attribute \src "libresoc.v:138554.5-138554.29"
switch \initial
- attribute \src "libresoc.v:140424.9-140424.17"
+ attribute \src "libresoc.v:138554.9-138554.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\adr_l_r_adr$next[0:0]$6372 1'1
+ assign $1\adr_l_r_adr$next[0:0]$6298 1'1
case
- assign $1\adr_l_r_adr$next[0:0]$6372 \reset_a
+ assign $1\adr_l_r_adr$next[0:0]$6298 \reset_a
end
sync always
- update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6371
+ update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6297
end
- attribute \src "libresoc.v:140432.3-140440.6"
- process $proc$libresoc.v:140432$6373
+ attribute \src "libresoc.v:138562.3-138570.6"
+ process $proc$libresoc.v:138562$6299
assign { } { }
assign { } { }
- assign $0\wri_l_r_wri$next[0:0]$6374 $1\wri_l_r_wri$next[0:0]$6375
- attribute \src "libresoc.v:140433.5-140433.29"
+ assign $0\wri_l_r_wri$next[0:0]$6300 $1\wri_l_r_wri$next[0:0]$6301
+ attribute \src "libresoc.v:138563.5-138563.29"
switch \initial
- attribute \src "libresoc.v:140433.9-140433.17"
+ attribute \src "libresoc.v:138563.9-138563.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\wri_l_r_wri$next[0:0]$6375 1'1
+ assign $1\wri_l_r_wri$next[0:0]$6301 1'1
case
- assign $1\wri_l_r_wri$next[0:0]$6375 \$38 [0]
+ assign $1\wri_l_r_wri$next[0:0]$6301 \$38 [0]
end
sync always
- update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6374
+ update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6300
end
- attribute \src "libresoc.v:140441.3-140449.6"
- process $proc$libresoc.v:140441$6376
+ attribute \src "libresoc.v:138571.3-138579.6"
+ process $proc$libresoc.v:138571$6302
assign { } { }
assign { } { }
- assign $0\upd_l_s_upd$next[0:0]$6377 $1\upd_l_s_upd$next[0:0]$6378
- attribute \src "libresoc.v:140442.5-140442.29"
+ assign $0\upd_l_s_upd$next[0:0]$6303 $1\upd_l_s_upd$next[0:0]$6304
+ attribute \src "libresoc.v:138572.5-138572.29"
switch \initial
- attribute \src "libresoc.v:140442.9-140442.17"
+ attribute \src "libresoc.v:138572.9-138572.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\upd_l_s_upd$next[0:0]$6378 1'0
+ assign $1\upd_l_s_upd$next[0:0]$6304 1'0
case
- assign $1\upd_l_s_upd$next[0:0]$6378 \reset_i
+ assign $1\upd_l_s_upd$next[0:0]$6304 \reset_i
end
sync always
- update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6377
+ update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6303
end
- attribute \src "libresoc.v:140450.3-140458.6"
- process $proc$libresoc.v:140450$6379
+ attribute \src "libresoc.v:138580.3-138588.6"
+ process $proc$libresoc.v:138580$6305
assign { } { }
assign { } { }
- assign $0\upd_l_r_upd$next[0:0]$6380 $1\upd_l_r_upd$next[0:0]$6381
- attribute \src "libresoc.v:140451.5-140451.29"
+ assign $0\upd_l_r_upd$next[0:0]$6306 $1\upd_l_r_upd$next[0:0]$6307
+ attribute \src "libresoc.v:138581.5-138581.29"
switch \initial
- attribute \src "libresoc.v:140451.9-140451.17"
+ attribute \src "libresoc.v:138581.9-138581.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\upd_l_r_upd$next[0:0]$6381 1'1
+ assign $1\upd_l_r_upd$next[0:0]$6307 1'1
case
- assign $1\upd_l_r_upd$next[0:0]$6381 \reset_u
+ assign $1\upd_l_r_upd$next[0:0]$6307 \reset_u
end
sync always
- update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6380
+ update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6306
end
- attribute \src "libresoc.v:140459.3-140467.6"
- process $proc$libresoc.v:140459$6382
+ attribute \src "libresoc.v:138589.3-138597.6"
+ process $proc$libresoc.v:138589$6308
assign { } { }
assign { } { }
- assign $0\sto_l_r_sto$next[0:0]$6383 $1\sto_l_r_sto$next[0:0]$6384
- attribute \src "libresoc.v:140460.5-140460.29"
+ assign $0\sto_l_r_sto$next[0:0]$6309 $1\sto_l_r_sto$next[0:0]$6310
+ attribute \src "libresoc.v:138590.5-138590.29"
switch \initial
- attribute \src "libresoc.v:140460.9-140460.17"
+ attribute \src "libresoc.v:138590.9-138590.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sto_l_r_sto$next[0:0]$6384 1'1
+ assign $1\sto_l_r_sto$next[0:0]$6310 1'1
case
- assign $1\sto_l_r_sto$next[0:0]$6384 \$59
+ assign $1\sto_l_r_sto$next[0:0]$6310 \$59
end
sync always
- update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6383
+ update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6309
end
- attribute \src "libresoc.v:140468.3-140476.6"
- process $proc$libresoc.v:140468$6385
+ attribute \src "libresoc.v:138598.3-138606.6"
+ process $proc$libresoc.v:138598$6311
assign { } { }
assign { } { }
- assign $0\lsd_l_r_lsd$next[0:0]$6386 $1\lsd_l_r_lsd$next[0:0]$6387
- attribute \src "libresoc.v:140469.5-140469.29"
+ assign $0\lsd_l_r_lsd$next[0:0]$6312 $1\lsd_l_r_lsd$next[0:0]$6313
+ attribute \src "libresoc.v:138599.5-138599.29"
switch \initial
- attribute \src "libresoc.v:140469.9-140469.17"
+ attribute \src "libresoc.v:138599.9-138599.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\lsd_l_r_lsd$next[0:0]$6387 1'1
+ assign $1\lsd_l_r_lsd$next[0:0]$6313 1'1
case
- assign $1\lsd_l_r_lsd$next[0:0]$6387 \$63
+ assign $1\lsd_l_r_lsd$next[0:0]$6313 \$63
end
sync always
- update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6386
+ update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6312
end
- attribute \src "libresoc.v:140477.3-140519.6"
- process $proc$libresoc.v:140477$6388
+ attribute \src "libresoc.v:138607.3-138649.6"
+ process $proc$libresoc.v:138607$6314
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\oper_r__byte_reverse$next[0:0]$6389 $2\oper_r__byte_reverse$next[0:0]$6421
- assign $0\oper_r__data_len$next[3:0]$6390 $2\oper_r__data_len$next[3:0]$6422
- assign $0\oper_r__fn_unit$next[12:0]$6391 $2\oper_r__fn_unit$next[12:0]$6423
+ assign $0\oper_r__byte_reverse$next[0:0]$6315 $2\oper_r__byte_reverse$next[0:0]$6347
+ assign $0\oper_r__data_len$next[3:0]$6316 $2\oper_r__data_len$next[3:0]$6348
+ assign $0\oper_r__fn_unit$next[12:0]$6317 $2\oper_r__fn_unit$next[12:0]$6349
assign { } { }
assign { } { }
- assign $0\oper_r__insn$next[31:0]$6394 $2\oper_r__insn$next[31:0]$6426
- assign $0\oper_r__insn_type$next[6:0]$6395 $2\oper_r__insn_type$next[6:0]$6427
- assign $0\oper_r__is_32bit$next[0:0]$6396 $2\oper_r__is_32bit$next[0:0]$6428
- assign $0\oper_r__is_signed$next[0:0]$6397 $2\oper_r__is_signed$next[0:0]$6429
- assign $0\oper_r__ldst_mode$next[1:0]$6398 $2\oper_r__ldst_mode$next[1:0]$6430
+ assign $0\oper_r__insn$next[31:0]$6320 $2\oper_r__insn$next[31:0]$6352
+ assign $0\oper_r__insn_type$next[6:0]$6321 $2\oper_r__insn_type$next[6:0]$6353
+ assign $0\oper_r__is_32bit$next[0:0]$6322 $2\oper_r__is_32bit$next[0:0]$6354
+ assign $0\oper_r__is_signed$next[0:0]$6323 $2\oper_r__is_signed$next[0:0]$6355
+ assign $0\oper_r__ldst_mode$next[1:0]$6324 $2\oper_r__ldst_mode$next[1:0]$6356
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\oper_r__sign_extend$next[0:0]$6403 $2\oper_r__sign_extend$next[0:0]$6435
- assign $0\oper_r__zero_a$next[0:0]$6404 $2\oper_r__zero_a$next[0:0]$6436
- assign $0\oper_r__imm_data__data$next[63:0]$6392 $3\oper_r__imm_data__data$next[63:0]$6437
- assign $0\oper_r__imm_data__ok$next[0:0]$6393 $3\oper_r__imm_data__ok$next[0:0]$6438
- assign $0\oper_r__oe__oe$next[0:0]$6399 $3\oper_r__oe__oe$next[0:0]$6439
- assign $0\oper_r__oe__ok$next[0:0]$6400 $3\oper_r__oe__ok$next[0:0]$6440
- assign $0\oper_r__rc__ok$next[0:0]$6401 $3\oper_r__rc__ok$next[0:0]$6441
- assign $0\oper_r__rc__rc$next[0:0]$6402 $3\oper_r__rc__rc$next[0:0]$6442
- attribute \src "libresoc.v:140478.5-140478.29"
+ assign $0\oper_r__sign_extend$next[0:0]$6329 $2\oper_r__sign_extend$next[0:0]$6361
+ assign $0\oper_r__zero_a$next[0:0]$6330 $2\oper_r__zero_a$next[0:0]$6362
+ assign $0\oper_r__imm_data__data$next[63:0]$6318 $3\oper_r__imm_data__data$next[63:0]$6363
+ assign $0\oper_r__imm_data__ok$next[0:0]$6319 $3\oper_r__imm_data__ok$next[0:0]$6364
+ assign $0\oper_r__oe__oe$next[0:0]$6325 $3\oper_r__oe__oe$next[0:0]$6365
+ assign $0\oper_r__oe__ok$next[0:0]$6326 $3\oper_r__oe__ok$next[0:0]$6366
+ assign $0\oper_r__rc__ok$next[0:0]$6327 $3\oper_r__rc__ok$next[0:0]$6367
+ assign $0\oper_r__rc__rc$next[0:0]$6328 $3\oper_r__rc__rc$next[0:0]$6368
+ attribute \src "libresoc.v:138608.5-138608.29"
switch \initial
- attribute \src "libresoc.v:140478.9-140478.17"
+ attribute \src "libresoc.v:138608.9-138608.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\oper_r__insn$next[31:0]$6410 $1\oper_r__ldst_mode$next[1:0]$6414 $1\oper_r__sign_extend$next[0:0]$6419 $1\oper_r__byte_reverse$next[0:0]$6405 $1\oper_r__data_len$next[3:0]$6406 $1\oper_r__is_signed$next[0:0]$6413 $1\oper_r__is_32bit$next[0:0]$6412 $1\oper_r__oe__ok$next[0:0]$6416 $1\oper_r__oe__oe$next[0:0]$6415 $1\oper_r__rc__ok$next[0:0]$6417 $1\oper_r__rc__rc$next[0:0]$6418 $1\oper_r__zero_a$next[0:0]$6420 $1\oper_r__imm_data__ok$next[0:0]$6409 $1\oper_r__imm_data__data$next[63:0]$6408 $1\oper_r__fn_unit$next[12:0]$6407 $1\oper_r__insn_type$next[6:0]$6411 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type }
+ assign { $1\oper_r__insn$next[31:0]$6336 $1\oper_r__ldst_mode$next[1:0]$6340 $1\oper_r__sign_extend$next[0:0]$6345 $1\oper_r__byte_reverse$next[0:0]$6331 $1\oper_r__data_len$next[3:0]$6332 $1\oper_r__is_signed$next[0:0]$6339 $1\oper_r__is_32bit$next[0:0]$6338 $1\oper_r__oe__ok$next[0:0]$6342 $1\oper_r__oe__oe$next[0:0]$6341 $1\oper_r__rc__ok$next[0:0]$6343 $1\oper_r__rc__rc$next[0:0]$6344 $1\oper_r__zero_a$next[0:0]$6346 $1\oper_r__imm_data__ok$next[0:0]$6335 $1\oper_r__imm_data__data$next[63:0]$6334 $1\oper_r__fn_unit$next[12:0]$6333 $1\oper_r__insn_type$next[6:0]$6337 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type }
case
- assign $1\oper_r__byte_reverse$next[0:0]$6405 \oper_r__byte_reverse
- assign $1\oper_r__data_len$next[3:0]$6406 \oper_r__data_len
- assign $1\oper_r__fn_unit$next[12:0]$6407 \oper_r__fn_unit
- assign $1\oper_r__imm_data__data$next[63:0]$6408 \oper_r__imm_data__data
- assign $1\oper_r__imm_data__ok$next[0:0]$6409 \oper_r__imm_data__ok
- assign $1\oper_r__insn$next[31:0]$6410 \oper_r__insn
- assign $1\oper_r__insn_type$next[6:0]$6411 \oper_r__insn_type
- assign $1\oper_r__is_32bit$next[0:0]$6412 \oper_r__is_32bit
- assign $1\oper_r__is_signed$next[0:0]$6413 \oper_r__is_signed
- assign $1\oper_r__ldst_mode$next[1:0]$6414 \oper_r__ldst_mode
- assign $1\oper_r__oe__oe$next[0:0]$6415 \oper_r__oe__oe
- assign $1\oper_r__oe__ok$next[0:0]$6416 \oper_r__oe__ok
- assign $1\oper_r__rc__ok$next[0:0]$6417 \oper_r__rc__ok
- assign $1\oper_r__rc__rc$next[0:0]$6418 \oper_r__rc__rc
- assign $1\oper_r__sign_extend$next[0:0]$6419 \oper_r__sign_extend
- assign $1\oper_r__zero_a$next[0:0]$6420 \oper_r__zero_a
+ assign $1\oper_r__byte_reverse$next[0:0]$6331 \oper_r__byte_reverse
+ assign $1\oper_r__data_len$next[3:0]$6332 \oper_r__data_len
+ assign $1\oper_r__fn_unit$next[12:0]$6333 \oper_r__fn_unit
+ assign $1\oper_r__imm_data__data$next[63:0]$6334 \oper_r__imm_data__data
+ assign $1\oper_r__imm_data__ok$next[0:0]$6335 \oper_r__imm_data__ok
+ assign $1\oper_r__insn$next[31:0]$6336 \oper_r__insn
+ assign $1\oper_r__insn_type$next[6:0]$6337 \oper_r__insn_type
+ assign $1\oper_r__is_32bit$next[0:0]$6338 \oper_r__is_32bit
+ assign $1\oper_r__is_signed$next[0:0]$6339 \oper_r__is_signed
+ assign $1\oper_r__ldst_mode$next[1:0]$6340 \oper_r__ldst_mode
+ assign $1\oper_r__oe__oe$next[0:0]$6341 \oper_r__oe__oe
+ assign $1\oper_r__oe__ok$next[0:0]$6342 \oper_r__oe__ok
+ assign $1\oper_r__rc__ok$next[0:0]$6343 \oper_r__rc__ok
+ assign $1\oper_r__rc__rc$next[0:0]$6344 \oper_r__rc__rc
+ assign $1\oper_r__sign_extend$next[0:0]$6345 \oper_r__sign_extend
+ assign $1\oper_r__zero_a$next[0:0]$6346 \oper_r__zero_a
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381"
switch \cu_done_o
assign { } { }
assign { } { }
assign { } { }
- assign { $2\oper_r__insn$next[31:0]$6426 $2\oper_r__ldst_mode$next[1:0]$6430 $2\oper_r__sign_extend$next[0:0]$6435 $2\oper_r__byte_reverse$next[0:0]$6421 $2\oper_r__data_len$next[3:0]$6422 $2\oper_r__is_signed$next[0:0]$6429 $2\oper_r__is_32bit$next[0:0]$6428 $2\oper_r__oe__ok$next[0:0]$6432 $2\oper_r__oe__oe$next[0:0]$6431 $2\oper_r__rc__ok$next[0:0]$6433 $2\oper_r__rc__rc$next[0:0]$6434 $2\oper_r__zero_a$next[0:0]$6436 $2\oper_r__imm_data__ok$next[0:0]$6425 $2\oper_r__imm_data__data$next[63:0]$6424 $2\oper_r__fn_unit$next[12:0]$6423 $2\oper_r__insn_type$next[6:0]$6427 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\oper_r__insn$next[31:0]$6352 $2\oper_r__ldst_mode$next[1:0]$6356 $2\oper_r__sign_extend$next[0:0]$6361 $2\oper_r__byte_reverse$next[0:0]$6347 $2\oper_r__data_len$next[3:0]$6348 $2\oper_r__is_signed$next[0:0]$6355 $2\oper_r__is_32bit$next[0:0]$6354 $2\oper_r__oe__ok$next[0:0]$6358 $2\oper_r__oe__oe$next[0:0]$6357 $2\oper_r__rc__ok$next[0:0]$6359 $2\oper_r__rc__rc$next[0:0]$6360 $2\oper_r__zero_a$next[0:0]$6362 $2\oper_r__imm_data__ok$next[0:0]$6351 $2\oper_r__imm_data__data$next[63:0]$6350 $2\oper_r__fn_unit$next[12:0]$6349 $2\oper_r__insn_type$next[6:0]$6353 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\oper_r__byte_reverse$next[0:0]$6421 $1\oper_r__byte_reverse$next[0:0]$6405
- assign $2\oper_r__data_len$next[3:0]$6422 $1\oper_r__data_len$next[3:0]$6406
- assign $2\oper_r__fn_unit$next[12:0]$6423 $1\oper_r__fn_unit$next[12:0]$6407
- assign $2\oper_r__imm_data__data$next[63:0]$6424 $1\oper_r__imm_data__data$next[63:0]$6408
- assign $2\oper_r__imm_data__ok$next[0:0]$6425 $1\oper_r__imm_data__ok$next[0:0]$6409
- assign $2\oper_r__insn$next[31:0]$6426 $1\oper_r__insn$next[31:0]$6410
- assign $2\oper_r__insn_type$next[6:0]$6427 $1\oper_r__insn_type$next[6:0]$6411
- assign $2\oper_r__is_32bit$next[0:0]$6428 $1\oper_r__is_32bit$next[0:0]$6412
- assign $2\oper_r__is_signed$next[0:0]$6429 $1\oper_r__is_signed$next[0:0]$6413
- assign $2\oper_r__ldst_mode$next[1:0]$6430 $1\oper_r__ldst_mode$next[1:0]$6414
- assign $2\oper_r__oe__oe$next[0:0]$6431 $1\oper_r__oe__oe$next[0:0]$6415
- assign $2\oper_r__oe__ok$next[0:0]$6432 $1\oper_r__oe__ok$next[0:0]$6416
- assign $2\oper_r__rc__ok$next[0:0]$6433 $1\oper_r__rc__ok$next[0:0]$6417
- assign $2\oper_r__rc__rc$next[0:0]$6434 $1\oper_r__rc__rc$next[0:0]$6418
- assign $2\oper_r__sign_extend$next[0:0]$6435 $1\oper_r__sign_extend$next[0:0]$6419
- assign $2\oper_r__zero_a$next[0:0]$6436 $1\oper_r__zero_a$next[0:0]$6420
+ assign $2\oper_r__byte_reverse$next[0:0]$6347 $1\oper_r__byte_reverse$next[0:0]$6331
+ assign $2\oper_r__data_len$next[3:0]$6348 $1\oper_r__data_len$next[3:0]$6332
+ assign $2\oper_r__fn_unit$next[12:0]$6349 $1\oper_r__fn_unit$next[12:0]$6333
+ assign $2\oper_r__imm_data__data$next[63:0]$6350 $1\oper_r__imm_data__data$next[63:0]$6334
+ assign $2\oper_r__imm_data__ok$next[0:0]$6351 $1\oper_r__imm_data__ok$next[0:0]$6335
+ assign $2\oper_r__insn$next[31:0]$6352 $1\oper_r__insn$next[31:0]$6336
+ assign $2\oper_r__insn_type$next[6:0]$6353 $1\oper_r__insn_type$next[6:0]$6337
+ assign $2\oper_r__is_32bit$next[0:0]$6354 $1\oper_r__is_32bit$next[0:0]$6338
+ assign $2\oper_r__is_signed$next[0:0]$6355 $1\oper_r__is_signed$next[0:0]$6339
+ assign $2\oper_r__ldst_mode$next[1:0]$6356 $1\oper_r__ldst_mode$next[1:0]$6340
+ assign $2\oper_r__oe__oe$next[0:0]$6357 $1\oper_r__oe__oe$next[0:0]$6341
+ assign $2\oper_r__oe__ok$next[0:0]$6358 $1\oper_r__oe__ok$next[0:0]$6342
+ assign $2\oper_r__rc__ok$next[0:0]$6359 $1\oper_r__rc__ok$next[0:0]$6343
+ assign $2\oper_r__rc__rc$next[0:0]$6360 $1\oper_r__rc__rc$next[0:0]$6344
+ assign $2\oper_r__sign_extend$next[0:0]$6361 $1\oper_r__sign_extend$next[0:0]$6345
+ assign $2\oper_r__zero_a$next[0:0]$6362 $1\oper_r__zero_a$next[0:0]$6346
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\oper_r__imm_data__data$next[63:0]$6437 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\oper_r__imm_data__ok$next[0:0]$6438 1'0
- assign $3\oper_r__rc__rc$next[0:0]$6442 1'0
- assign $3\oper_r__rc__ok$next[0:0]$6441 1'0
- assign $3\oper_r__oe__oe$next[0:0]$6439 1'0
- assign $3\oper_r__oe__ok$next[0:0]$6440 1'0
+ assign $3\oper_r__imm_data__data$next[63:0]$6363 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\oper_r__imm_data__ok$next[0:0]$6364 1'0
+ assign $3\oper_r__rc__rc$next[0:0]$6368 1'0
+ assign $3\oper_r__rc__ok$next[0:0]$6367 1'0
+ assign $3\oper_r__oe__oe$next[0:0]$6365 1'0
+ assign $3\oper_r__oe__ok$next[0:0]$6366 1'0
case
- assign $3\oper_r__imm_data__data$next[63:0]$6437 $2\oper_r__imm_data__data$next[63:0]$6424
- assign $3\oper_r__imm_data__ok$next[0:0]$6438 $2\oper_r__imm_data__ok$next[0:0]$6425
- assign $3\oper_r__oe__oe$next[0:0]$6439 $2\oper_r__oe__oe$next[0:0]$6431
- assign $3\oper_r__oe__ok$next[0:0]$6440 $2\oper_r__oe__ok$next[0:0]$6432
- assign $3\oper_r__rc__ok$next[0:0]$6441 $2\oper_r__rc__ok$next[0:0]$6433
- assign $3\oper_r__rc__rc$next[0:0]$6442 $2\oper_r__rc__rc$next[0:0]$6434
+ assign $3\oper_r__imm_data__data$next[63:0]$6363 $2\oper_r__imm_data__data$next[63:0]$6350
+ assign $3\oper_r__imm_data__ok$next[0:0]$6364 $2\oper_r__imm_data__ok$next[0:0]$6351
+ assign $3\oper_r__oe__oe$next[0:0]$6365 $2\oper_r__oe__oe$next[0:0]$6357
+ assign $3\oper_r__oe__ok$next[0:0]$6366 $2\oper_r__oe__ok$next[0:0]$6358
+ assign $3\oper_r__rc__ok$next[0:0]$6367 $2\oper_r__rc__ok$next[0:0]$6359
+ assign $3\oper_r__rc__rc$next[0:0]$6368 $2\oper_r__rc__rc$next[0:0]$6360
end
sync always
- update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6389
- update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6390
- update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6391
- update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6392
- update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6393
- update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6394
- update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6395
- update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6396
- update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6397
- update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6398
- update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6399
- update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6400
- update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6401
- update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6402
- update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6403
- update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6404
+ update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6315
+ update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6316
+ update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6317
+ update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6318
+ update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6319
+ update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6320
+ update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6321
+ update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6322
+ update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6323
+ update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6324
+ update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6325
+ update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6326
+ update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6327
+ update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6328
+ update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6329
+ update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6330
end
- attribute \src "libresoc.v:140520.3-140529.6"
- process $proc$libresoc.v:140520$6443
+ attribute \src "libresoc.v:138650.3-138659.6"
+ process $proc$libresoc.v:138650$6369
assign { } { }
assign { } { }
- assign $0\ldo_r$next[63:0]$6444 $1\ldo_r$next[63:0]$6445
- attribute \src "libresoc.v:140521.5-140521.29"
+ assign $0\ldo_r$next[63:0]$6370 $1\ldo_r$next[63:0]$6371
+ attribute \src "libresoc.v:138651.5-138651.29"
switch \initial
- attribute \src "libresoc.v:140521.9-140521.17"
+ attribute \src "libresoc.v:138651.9-138651.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldo_r$next[63:0]$6445 \ldd_o
+ assign $1\ldo_r$next[63:0]$6371 \ldd_o
case
- assign $1\ldo_r$next[63:0]$6445 \ldo_r
+ assign $1\ldo_r$next[63:0]$6371 \ldo_r
end
sync always
- update \ldo_r$next $0\ldo_r$next[63:0]$6444
+ update \ldo_r$next $0\ldo_r$next[63:0]$6370
end
- attribute \src "libresoc.v:140530.3-140545.6"
- process $proc$libresoc.v:140530$6446
+ attribute \src "libresoc.v:138660.3-138675.6"
+ process $proc$libresoc.v:138660$6372
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$6447 $2\src_r0$next[63:0]$6449
- attribute \src "libresoc.v:140531.5-140531.29"
+ assign $0\src_r0$next[63:0]$6373 $2\src_r0$next[63:0]$6375
+ attribute \src "libresoc.v:138661.5-138661.29"
switch \initial
- attribute \src "libresoc.v:140531.9-140531.17"
+ attribute \src "libresoc.v:138661.9-138661.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$6448 \src1_i
+ assign $1\src_r0$next[63:0]$6374 \src1_i
case
- assign $1\src_r0$next[63:0]$6448 \src_r0
+ assign $1\src_r0$next[63:0]$6374 \src_r0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r0$next[63:0]$6449 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r0$next[63:0]$6375 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r0$next[63:0]$6449 $1\src_r0$next[63:0]$6448
+ assign $2\src_r0$next[63:0]$6375 $1\src_r0$next[63:0]$6374
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$6447
+ update \src_r0$next $0\src_r0$next[63:0]$6373
end
- attribute \src "libresoc.v:140546.3-140561.6"
- process $proc$libresoc.v:140546$6450
+ attribute \src "libresoc.v:138676.3-138691.6"
+ process $proc$libresoc.v:138676$6376
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$6451 $2\src_r1$next[63:0]$6453
- attribute \src "libresoc.v:140547.5-140547.29"
+ assign $0\src_r1$next[63:0]$6377 $2\src_r1$next[63:0]$6379
+ attribute \src "libresoc.v:138677.5-138677.29"
switch \initial
- attribute \src "libresoc.v:140547.9-140547.17"
+ attribute \src "libresoc.v:138677.9-138677.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$6452 \src2_i
+ assign $1\src_r1$next[63:0]$6378 \src2_i
case
- assign $1\src_r1$next[63:0]$6452 \src_r1
+ assign $1\src_r1$next[63:0]$6378 \src_r1
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r1$next[63:0]$6453 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r1$next[63:0]$6379 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r1$next[63:0]$6453 $1\src_r1$next[63:0]$6452
+ assign $2\src_r1$next[63:0]$6379 $1\src_r1$next[63:0]$6378
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$6451
+ update \src_r1$next $0\src_r1$next[63:0]$6377
end
- attribute \src "libresoc.v:140562.3-140577.6"
- process $proc$libresoc.v:140562$6454
+ attribute \src "libresoc.v:138692.3-138707.6"
+ process $proc$libresoc.v:138692$6380
assign { } { }
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$6455 $2\src_r2$next[63:0]$6457
- attribute \src "libresoc.v:140563.5-140563.29"
+ assign $0\src_r2$next[63:0]$6381 $2\src_r2$next[63:0]$6383
+ attribute \src "libresoc.v:138693.5-138693.29"
switch \initial
- attribute \src "libresoc.v:140563.9-140563.17"
+ attribute \src "libresoc.v:138693.9-138693.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$6456 \src3_i
+ assign $1\src_r2$next[63:0]$6382 \src3_i
case
- assign $1\src_r2$next[63:0]$6456 \src_r2
+ assign $1\src_r2$next[63:0]$6382 \src_r2
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
switch \cu_issue_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src_r2$next[63:0]$6457 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\src_r2$next[63:0]$6383 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\src_r2$next[63:0]$6457 $1\src_r2$next[63:0]$6456
+ assign $2\src_r2$next[63:0]$6383 $1\src_r2$next[63:0]$6382
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$6455
+ update \src_r2$next $0\src_r2$next[63:0]$6381
end
- attribute \src "libresoc.v:140578.3-140587.6"
- process $proc$libresoc.v:140578$6458
+ attribute \src "libresoc.v:138708.3-138717.6"
+ process $proc$libresoc.v:138708$6384
assign { } { }
assign { } { }
- assign $0\ea_r$next[63:0]$6459 $1\ea_r$next[63:0]$6460
- attribute \src "libresoc.v:140579.5-140579.29"
+ assign $0\ea_r$next[63:0]$6385 $1\ea_r$next[63:0]$6386
+ attribute \src "libresoc.v:138709.5-138709.29"
switch \initial
- attribute \src "libresoc.v:140579.9-140579.17"
+ attribute \src "libresoc.v:138709.9-138709.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ea_r$next[63:0]$6460 \alu_o
+ assign $1\ea_r$next[63:0]$6386 \alu_o
case
- assign $1\ea_r$next[63:0]$6460 \ea_r
+ assign $1\ea_r$next[63:0]$6386 \ea_r
end
sync always
- update \ea_r$next $0\ea_r$next[63:0]$6459
+ update \ea_r$next $0\ea_r$next[63:0]$6385
end
- attribute \src "libresoc.v:140588.3-140597.6"
- process $proc$libresoc.v:140588$6461
+ attribute \src "libresoc.v:138718.3-138727.6"
+ process $proc$libresoc.v:138718$6387
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:140589.5-140589.29"
+ attribute \src "libresoc.v:138719.5-138719.29"
switch \initial
- attribute \src "libresoc.v:140589.9-140589.17"
+ attribute \src "libresoc.v:138719.9-138719.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:140598.3-140607.6"
- process $proc$libresoc.v:140598$6462
+ attribute \src "libresoc.v:138728.3-138737.6"
+ process $proc$libresoc.v:138728$6388
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:140599.5-140599.29"
+ attribute \src "libresoc.v:138729.5-138729.29"
switch \initial
- attribute \src "libresoc.v:140599.9-140599.17"
+ attribute \src "libresoc.v:138729.9-138729.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:140608.3-140616.6"
- process $proc$libresoc.v:140608$6463
+ attribute \src "libresoc.v:138738.3-138746.6"
+ process $proc$libresoc.v:138738$6389
assign { } { }
assign { } { }
- assign $0\ldst_port0_addr_i_ok$next[0:0]$6464 $1\ldst_port0_addr_i_ok$next[0:0]$6465
- attribute \src "libresoc.v:140609.5-140609.29"
+ assign $0\ldst_port0_addr_i_ok$next[0:0]$6390 $1\ldst_port0_addr_i_ok$next[0:0]$6391
+ attribute \src "libresoc.v:138739.5-138739.29"
switch \initial
- attribute \src "libresoc.v:140609.9-140609.17"
+ attribute \src "libresoc.v:138739.9-138739.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ldst_port0_addr_i_ok$next[0:0]$6465 1'0
+ assign $1\ldst_port0_addr_i_ok$next[0:0]$6391 1'0
case
- assign $1\ldst_port0_addr_i_ok$next[0:0]$6465 \$177
+ assign $1\ldst_port0_addr_i_ok$next[0:0]$6391 \$177
end
sync always
- update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6464
+ update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6390
end
- attribute \src "libresoc.v:140617.3-140640.6"
- process $proc$libresoc.v:140617$6466
+ attribute \src "libresoc.v:138747.3-138770.6"
+ process $proc$libresoc.v:138747$6392
assign { } { }
assign { } { }
assign $0\lddata_r[63:0] $1\lddata_r[63:0]
- attribute \src "libresoc.v:140618.5-140618.29"
+ attribute \src "libresoc.v:138748.5-138748.29"
switch \initial
- attribute \src "libresoc.v:140618.9-140618.17"
+ attribute \src "libresoc.v:138748.9-138748.17"
case 1'1
case
end
sync always
update \lddata_r $0\lddata_r[63:0]
end
- attribute \src "libresoc.v:140641.3-140652.6"
- process $proc$libresoc.v:140641$6467
+ attribute \src "libresoc.v:138771.3-138782.6"
+ process $proc$libresoc.v:138771$6393
assign { } { }
assign $0\revnorev[63:0] $1\revnorev[63:0]
- attribute \src "libresoc.v:140642.5-140642.29"
+ attribute \src "libresoc.v:138772.5-138772.29"
switch \initial
- attribute \src "libresoc.v:140642.9-140642.17"
+ attribute \src "libresoc.v:138772.9-138772.17"
case 1'1
case
end
sync always
update \revnorev $0\revnorev[63:0]
end
- attribute \src "libresoc.v:140653.3-140672.6"
- process $proc$libresoc.v:140653$6468
+ attribute \src "libresoc.v:138783.3-138802.6"
+ process $proc$libresoc.v:138783$6394
assign { } { }
assign $0\ldd_o[63:0] $1\ldd_o[63:0]
- attribute \src "libresoc.v:140654.5-140654.29"
+ attribute \src "libresoc.v:138784.5-138784.29"
switch \initial
- attribute \src "libresoc.v:140654.9-140654.17"
+ attribute \src "libresoc.v:138784.9-138784.17"
case 1'1
case
end
sync always
update \ldd_o $0\ldd_o[63:0]
end
- attribute \src "libresoc.v:140673.3-140696.6"
- process $proc$libresoc.v:140673$6469
+ attribute \src "libresoc.v:138803.3-138826.6"
+ process $proc$libresoc.v:138803$6395
assign { } { }
assign { } { }
assign $0\stdata_r[63:0] $1\stdata_r[63:0]
- attribute \src "libresoc.v:140674.5-140674.29"
+ attribute \src "libresoc.v:138804.5-138804.29"
switch \initial
- attribute \src "libresoc.v:140674.9-140674.17"
+ attribute \src "libresoc.v:138804.9-138804.17"
case 1'1
case
end
sync always
update \stdata_r $0\stdata_r[63:0]
end
- attribute \src "libresoc.v:140697.3-140708.6"
- process $proc$libresoc.v:140697$6470
+ attribute \src "libresoc.v:138827.3-138838.6"
+ process $proc$libresoc.v:138827$6396
assign { } { }
assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0]
- attribute \src "libresoc.v:140698.5-140698.29"
+ attribute \src "libresoc.v:138828.5-138828.29"
switch \initial
- attribute \src "libresoc.v:140698.9-140698.17"
+ attribute \src "libresoc.v:138828.9-138828.17"
case 1'1
case
end
sync always
update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0]
end
- connect \$100 $and$libresoc.v:140156$6229_Y
- connect \$102 $and$libresoc.v:140157$6230_Y
- connect \$104 $and$libresoc.v:140158$6231_Y
- connect \$106 $and$libresoc.v:140159$6232_Y
- connect \$108 $and$libresoc.v:140160$6233_Y
- connect \$10 $or$libresoc.v:140161$6234_Y
- connect \$110 $and$libresoc.v:140162$6235_Y
- connect \$112 $and$libresoc.v:140163$6236_Y
- connect \$114 $and$libresoc.v:140164$6237_Y
- connect \$116 $and$libresoc.v:140165$6238_Y
- connect \$118 $and$libresoc.v:140166$6239_Y
- connect \$120 $and$libresoc.v:140167$6240_Y
- connect \$122 $and$libresoc.v:140168$6241_Y
- connect \$124 $and$libresoc.v:140169$6242_Y
- connect \$126 $eq$libresoc.v:140170$6243_Y
- connect \$128 $and$libresoc.v:140171$6244_Y
- connect \$12 $or$libresoc.v:140172$6245_Y
- connect \$130 $and$libresoc.v:140173$6246_Y
- connect \$132 $and$libresoc.v:140174$6247_Y
- connect \$134 $or$libresoc.v:140175$6248_Y
- connect \$136 $or$libresoc.v:140176$6249_Y
- connect \$138 $or$libresoc.v:140177$6250_Y
- connect \$140 $and$libresoc.v:140178$6251_Y
- connect \$142 $and$libresoc.v:140179$6252_Y
- connect \$145 $or$libresoc.v:140180$6253_Y
- connect \$147 $or$libresoc.v:140181$6254_Y
- connect \$144 $not$libresoc.v:140182$6255_Y
- connect \$14 $or$libresoc.v:140183$6256_Y
- connect \$150 $and$libresoc.v:140184$6257_Y
- connect \$152 $or$libresoc.v:140185$6258_Y
- connect \$154 $and$libresoc.v:140186$6259_Y
- connect \$156 $not$libresoc.v:140187$6260_Y
- connect \$158 $or$libresoc.v:140188$6261_Y
- connect \$160 $and$libresoc.v:140189$6262_Y
- connect \$162 $eq$libresoc.v:140190$6263_Y
- connect \$164 $and$libresoc.v:140191$6264_Y
- connect \$167 $eq$libresoc.v:140192$6265_Y
- connect \$16 $or$libresoc.v:140193$6266_Y
- connect \$169 $and$libresoc.v:140194$6267_Y
- connect \$171 $and$libresoc.v:140195$6268_Y
- connect \$173 $and$libresoc.v:140196$6269_Y
- connect \$175 $pos$libresoc.v:140197$6271_Y
- connect \$177 $and$libresoc.v:140198$6272_Y
- connect \$186 $pos$libresoc.v:140199$6274_Y
- connect \$188 $pos$libresoc.v:140200$6275_Y
- connect \$18 $or$libresoc.v:140201$6276_Y
- connect \$190 $pos$libresoc.v:140202$6277_Y
- connect \$192 $eq$libresoc.v:140203$6278_Y
- connect \$194 $pos$libresoc.v:140204$6280_Y
- connect \$196 $pos$libresoc.v:140205$6281_Y
- connect \$198 $pos$libresoc.v:140206$6282_Y
- connect \$20 $or$libresoc.v:140207$6283_Y
- connect \$22 $eq$libresoc.v:140208$6284_Y
- connect \$24 $eq$libresoc.v:140209$6285_Y
- connect \$26 $and$libresoc.v:140210$6286_Y
- connect \$28 $and$libresoc.v:140211$6287_Y
- connect \$30 $not$libresoc.v:140212$6288_Y
- connect \$32 $and$libresoc.v:140213$6289_Y
- connect \$34 $not$libresoc.v:140214$6290_Y
- connect \$36 $and$libresoc.v:140215$6291_Y
- connect \$39 $not$libresoc.v:140216$6292_Y
- connect \$41 $eq$libresoc.v:140217$6293_Y
- connect \$43 $and$libresoc.v:140218$6294_Y
- connect \$45 $or$libresoc.v:140219$6295_Y
- connect \$47 $not$libresoc.v:140220$6296_Y
- connect \$49 $eq$libresoc.v:140221$6297_Y
- connect \$51 $and$libresoc.v:140222$6298_Y
- connect \$53 $or$libresoc.v:140223$6299_Y
- connect \$55 $or$libresoc.v:140224$6300_Y
- connect \$57 $and$libresoc.v:140225$6301_Y
- connect \$59 $or$libresoc.v:140226$6302_Y
- connect \$61 $or$libresoc.v:140227$6303_Y
- connect \$63 $or$libresoc.v:140228$6304_Y
- connect \$65 $ternary$libresoc.v:140229$6305_Y
- connect \$67 $ternary$libresoc.v:140230$6306_Y
- connect \$69 $ternary$libresoc.v:140231$6307_Y
- connect \$71 $ternary$libresoc.v:140232$6308_Y
- connect \$74 $add$libresoc.v:140233$6309_Y
- connect \$76 $and$libresoc.v:140234$6310_Y
- connect \$78 $not$libresoc.v:140235$6311_Y
- connect \$80 $and$libresoc.v:140236$6312_Y
- connect \$82 $not$libresoc.v:140237$6313_Y
- connect \$84 $and$libresoc.v:140238$6314_Y
- connect \$86 $and$libresoc.v:140239$6315_Y
- connect \$88 $and$libresoc.v:140240$6316_Y
- connect \$8 $or$libresoc.v:140241$6317_Y
- connect \$90 $or$libresoc.v:140242$6318_Y
- connect \$93 $or$libresoc.v:140243$6319_Y
- connect \$92 $not$libresoc.v:140244$6320_Y
- connect \$96 $and$libresoc.v:140245$6321_Y
- connect \$98 $not$libresoc.v:140246$6322_Y
+ connect \$100 $and$libresoc.v:138286$6155_Y
+ connect \$102 $and$libresoc.v:138287$6156_Y
+ connect \$104 $and$libresoc.v:138288$6157_Y
+ connect \$106 $and$libresoc.v:138289$6158_Y
+ connect \$108 $and$libresoc.v:138290$6159_Y
+ connect \$10 $or$libresoc.v:138291$6160_Y
+ connect \$110 $and$libresoc.v:138292$6161_Y
+ connect \$112 $and$libresoc.v:138293$6162_Y
+ connect \$114 $and$libresoc.v:138294$6163_Y
+ connect \$116 $and$libresoc.v:138295$6164_Y
+ connect \$118 $and$libresoc.v:138296$6165_Y
+ connect \$120 $and$libresoc.v:138297$6166_Y
+ connect \$122 $and$libresoc.v:138298$6167_Y
+ connect \$124 $and$libresoc.v:138299$6168_Y
+ connect \$126 $eq$libresoc.v:138300$6169_Y
+ connect \$128 $and$libresoc.v:138301$6170_Y
+ connect \$12 $or$libresoc.v:138302$6171_Y
+ connect \$130 $and$libresoc.v:138303$6172_Y
+ connect \$132 $and$libresoc.v:138304$6173_Y
+ connect \$134 $or$libresoc.v:138305$6174_Y
+ connect \$136 $or$libresoc.v:138306$6175_Y
+ connect \$138 $or$libresoc.v:138307$6176_Y
+ connect \$140 $and$libresoc.v:138308$6177_Y
+ connect \$142 $and$libresoc.v:138309$6178_Y
+ connect \$145 $or$libresoc.v:138310$6179_Y
+ connect \$147 $or$libresoc.v:138311$6180_Y
+ connect \$144 $not$libresoc.v:138312$6181_Y
+ connect \$14 $or$libresoc.v:138313$6182_Y
+ connect \$150 $and$libresoc.v:138314$6183_Y
+ connect \$152 $or$libresoc.v:138315$6184_Y
+ connect \$154 $and$libresoc.v:138316$6185_Y
+ connect \$156 $not$libresoc.v:138317$6186_Y
+ connect \$158 $or$libresoc.v:138318$6187_Y
+ connect \$160 $and$libresoc.v:138319$6188_Y
+ connect \$162 $eq$libresoc.v:138320$6189_Y
+ connect \$164 $and$libresoc.v:138321$6190_Y
+ connect \$167 $eq$libresoc.v:138322$6191_Y
+ connect \$16 $or$libresoc.v:138323$6192_Y
+ connect \$169 $and$libresoc.v:138324$6193_Y
+ connect \$171 $and$libresoc.v:138325$6194_Y
+ connect \$173 $and$libresoc.v:138326$6195_Y
+ connect \$175 $pos$libresoc.v:138327$6197_Y
+ connect \$177 $and$libresoc.v:138328$6198_Y
+ connect \$186 $pos$libresoc.v:138329$6200_Y
+ connect \$188 $pos$libresoc.v:138330$6201_Y
+ connect \$18 $or$libresoc.v:138331$6202_Y
+ connect \$190 $pos$libresoc.v:138332$6203_Y
+ connect \$192 $eq$libresoc.v:138333$6204_Y
+ connect \$194 $pos$libresoc.v:138334$6206_Y
+ connect \$196 $pos$libresoc.v:138335$6207_Y
+ connect \$198 $pos$libresoc.v:138336$6208_Y
+ connect \$20 $or$libresoc.v:138337$6209_Y
+ connect \$22 $eq$libresoc.v:138338$6210_Y
+ connect \$24 $eq$libresoc.v:138339$6211_Y
+ connect \$26 $and$libresoc.v:138340$6212_Y
+ connect \$28 $and$libresoc.v:138341$6213_Y
+ connect \$30 $not$libresoc.v:138342$6214_Y
+ connect \$32 $and$libresoc.v:138343$6215_Y
+ connect \$34 $not$libresoc.v:138344$6216_Y
+ connect \$36 $and$libresoc.v:138345$6217_Y
+ connect \$39 $not$libresoc.v:138346$6218_Y
+ connect \$41 $eq$libresoc.v:138347$6219_Y
+ connect \$43 $and$libresoc.v:138348$6220_Y
+ connect \$45 $or$libresoc.v:138349$6221_Y
+ connect \$47 $not$libresoc.v:138350$6222_Y
+ connect \$49 $eq$libresoc.v:138351$6223_Y
+ connect \$51 $and$libresoc.v:138352$6224_Y
+ connect \$53 $or$libresoc.v:138353$6225_Y
+ connect \$55 $or$libresoc.v:138354$6226_Y
+ connect \$57 $and$libresoc.v:138355$6227_Y
+ connect \$59 $or$libresoc.v:138356$6228_Y
+ connect \$61 $or$libresoc.v:138357$6229_Y
+ connect \$63 $or$libresoc.v:138358$6230_Y
+ connect \$65 $ternary$libresoc.v:138359$6231_Y
+ connect \$67 $ternary$libresoc.v:138360$6232_Y
+ connect \$69 $ternary$libresoc.v:138361$6233_Y
+ connect \$71 $ternary$libresoc.v:138362$6234_Y
+ connect \$74 $add$libresoc.v:138363$6235_Y
+ connect \$76 $and$libresoc.v:138364$6236_Y
+ connect \$78 $not$libresoc.v:138365$6237_Y
+ connect \$80 $and$libresoc.v:138366$6238_Y
+ connect \$82 $not$libresoc.v:138367$6239_Y
+ connect \$84 $and$libresoc.v:138368$6240_Y
+ connect \$86 $and$libresoc.v:138369$6241_Y
+ connect \$88 $and$libresoc.v:138370$6242_Y
+ connect \$8 $or$libresoc.v:138371$6243_Y
+ connect \$90 $or$libresoc.v:138372$6244_Y
+ connect \$93 $or$libresoc.v:138373$6245_Y
+ connect \$92 $not$libresoc.v:138374$6246_Y
+ connect \$96 $and$libresoc.v:138375$6247_Y
+ connect \$98 $not$libresoc.v:138376$6248_Y
connect \$38 \$55
connect \$73 \$74
connect \$166 \$169
connect \reset_o \$10
connect \reset_i \$8
end
-attribute \src "libresoc.v:140772.1-141359.10"
+attribute \src "libresoc.v:138902.1-139489.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask"
attribute \generator "nMigen"
module \left_mask
- attribute \src "libresoc.v:140773.7-140773.20"
+ attribute \src "libresoc.v:138903.7-138903.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire width 64 $0\mask[63:0]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $10\mask[9:9]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $11\mask[10:10]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $12\mask[11:11]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $13\mask[12:12]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $14\mask[13:13]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $15\mask[14:14]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $16\mask[15:15]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $17\mask[16:16]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $18\mask[17:17]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $19\mask[18:18]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $1\mask[0:0]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $20\mask[19:19]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $21\mask[20:20]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $22\mask[21:21]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $23\mask[22:22]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $24\mask[23:23]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $25\mask[24:24]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $26\mask[25:25]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $27\mask[26:26]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $28\mask[27:27]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $29\mask[28:28]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $2\mask[1:1]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $30\mask[29:29]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $31\mask[30:30]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $32\mask[31:31]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $33\mask[32:32]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $34\mask[33:33]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $35\mask[34:34]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $36\mask[35:35]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $37\mask[36:36]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $38\mask[37:37]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $39\mask[38:38]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $3\mask[2:2]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $40\mask[39:39]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $41\mask[40:40]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $42\mask[41:41]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $43\mask[42:42]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $44\mask[43:43]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $45\mask[44:44]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $46\mask[45:45]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $47\mask[46:46]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $48\mask[47:47]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $49\mask[48:48]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $4\mask[3:3]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $50\mask[49:49]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $51\mask[50:50]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $52\mask[51:51]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $53\mask[52:52]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $54\mask[53:53]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $55\mask[54:54]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $56\mask[55:55]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $57\mask[56:56]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $58\mask[57:57]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $59\mask[58:58]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $5\mask[4:4]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $60\mask[59:59]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $61\mask[60:60]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $62\mask[61:61]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $63\mask[62:62]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $64\mask[63:63]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $6\mask[5:5]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $7\mask[6:6]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $8\mask[7:7]
- attribute \src "libresoc.v:140971.3-141358.6"
+ attribute \src "libresoc.v:139101.3-139488.6"
wire $9\mask[8:8]
- attribute \src "libresoc.v:140907.17-140907.96"
- wire $gt$libresoc.v:140907$6507_Y
- attribute \src "libresoc.v:140908.18-140908.98"
- wire $gt$libresoc.v:140908$6508_Y
- attribute \src "libresoc.v:140909.19-140909.99"
- wire $gt$libresoc.v:140909$6509_Y
- attribute \src "libresoc.v:140910.19-140910.99"
- wire $gt$libresoc.v:140910$6510_Y
- attribute \src "libresoc.v:140911.19-140911.99"
- wire $gt$libresoc.v:140911$6511_Y
- attribute \src "libresoc.v:140912.19-140912.99"
- wire $gt$libresoc.v:140912$6512_Y
- attribute \src "libresoc.v:140913.19-140913.99"
- wire $gt$libresoc.v:140913$6513_Y
- attribute \src "libresoc.v:140914.19-140914.99"
- wire $gt$libresoc.v:140914$6514_Y
- attribute \src "libresoc.v:140915.19-140915.99"
- wire $gt$libresoc.v:140915$6515_Y
- attribute \src "libresoc.v:140916.19-140916.99"
- wire $gt$libresoc.v:140916$6516_Y
- attribute \src "libresoc.v:140917.19-140917.99"
- wire $gt$libresoc.v:140917$6517_Y
- attribute \src "libresoc.v:140918.18-140918.97"
- wire $gt$libresoc.v:140918$6518_Y
- attribute \src "libresoc.v:140919.19-140919.99"
- wire $gt$libresoc.v:140919$6519_Y
- attribute \src "libresoc.v:140920.19-140920.99"
- wire $gt$libresoc.v:140920$6520_Y
- attribute \src "libresoc.v:140921.19-140921.99"
- wire $gt$libresoc.v:140921$6521_Y
- attribute \src "libresoc.v:140922.19-140922.99"
- wire $gt$libresoc.v:140922$6522_Y
- attribute \src "libresoc.v:140923.19-140923.99"
- wire $gt$libresoc.v:140923$6523_Y
- attribute \src "libresoc.v:140924.18-140924.97"
- wire $gt$libresoc.v:140924$6524_Y
- attribute \src "libresoc.v:140925.18-140925.97"
- wire $gt$libresoc.v:140925$6525_Y
- attribute \src "libresoc.v:140926.18-140926.97"
- wire $gt$libresoc.v:140926$6526_Y
- attribute \src "libresoc.v:140927.17-140927.96"
- wire $gt$libresoc.v:140927$6527_Y
- attribute \src "libresoc.v:140928.18-140928.97"
- wire $gt$libresoc.v:140928$6528_Y
- attribute \src "libresoc.v:140929.18-140929.97"
- wire $gt$libresoc.v:140929$6529_Y
- attribute \src "libresoc.v:140930.18-140930.97"
- wire $gt$libresoc.v:140930$6530_Y
- attribute \src "libresoc.v:140931.18-140931.97"
- wire $gt$libresoc.v:140931$6531_Y
- attribute \src "libresoc.v:140932.18-140932.97"
- wire $gt$libresoc.v:140932$6532_Y
- attribute \src "libresoc.v:140933.18-140933.97"
- wire $gt$libresoc.v:140933$6533_Y
- attribute \src "libresoc.v:140934.18-140934.97"
- wire $gt$libresoc.v:140934$6534_Y
- attribute \src "libresoc.v:140935.18-140935.98"
- wire $gt$libresoc.v:140935$6535_Y
- attribute \src "libresoc.v:140936.18-140936.98"
- wire $gt$libresoc.v:140936$6536_Y
- attribute \src "libresoc.v:140937.18-140937.98"
- wire $gt$libresoc.v:140937$6537_Y
- attribute \src "libresoc.v:140938.17-140938.96"
- wire $gt$libresoc.v:140938$6538_Y
- attribute \src "libresoc.v:140939.18-140939.98"
- wire $gt$libresoc.v:140939$6539_Y
- attribute \src "libresoc.v:140940.18-140940.98"
- wire $gt$libresoc.v:140940$6540_Y
- attribute \src "libresoc.v:140941.18-140941.98"
- wire $gt$libresoc.v:140941$6541_Y
- attribute \src "libresoc.v:140942.18-140942.98"
- wire $gt$libresoc.v:140942$6542_Y
- attribute \src "libresoc.v:140943.18-140943.98"
- wire $gt$libresoc.v:140943$6543_Y
- attribute \src "libresoc.v:140944.18-140944.98"
- wire $gt$libresoc.v:140944$6544_Y
- attribute \src "libresoc.v:140945.18-140945.98"
- wire $gt$libresoc.v:140945$6545_Y
- attribute \src "libresoc.v:140946.18-140946.98"
- wire $gt$libresoc.v:140946$6546_Y
- attribute \src "libresoc.v:140947.18-140947.98"
- wire $gt$libresoc.v:140947$6547_Y
- attribute \src "libresoc.v:140948.18-140948.98"
- wire $gt$libresoc.v:140948$6548_Y
- attribute \src "libresoc.v:140949.17-140949.96"
- wire $gt$libresoc.v:140949$6549_Y
- attribute \src "libresoc.v:140950.18-140950.98"
- wire $gt$libresoc.v:140950$6550_Y
- attribute \src "libresoc.v:140951.18-140951.98"
- wire $gt$libresoc.v:140951$6551_Y
- attribute \src "libresoc.v:140952.18-140952.98"
- wire $gt$libresoc.v:140952$6552_Y
- attribute \src "libresoc.v:140953.18-140953.98"
- wire $gt$libresoc.v:140953$6553_Y
- attribute \src "libresoc.v:140954.18-140954.98"
- wire $gt$libresoc.v:140954$6554_Y
- attribute \src "libresoc.v:140955.18-140955.98"
- wire $gt$libresoc.v:140955$6555_Y
- attribute \src "libresoc.v:140956.18-140956.98"
- wire $gt$libresoc.v:140956$6556_Y
- attribute \src "libresoc.v:140957.18-140957.98"
- wire $gt$libresoc.v:140957$6557_Y
- attribute \src "libresoc.v:140958.18-140958.98"
- wire $gt$libresoc.v:140958$6558_Y
- attribute \src "libresoc.v:140959.18-140959.98"
- wire $gt$libresoc.v:140959$6559_Y
- attribute \src "libresoc.v:140960.17-140960.96"
- wire $gt$libresoc.v:140960$6560_Y
- attribute \src "libresoc.v:140961.18-140961.98"
- wire $gt$libresoc.v:140961$6561_Y
- attribute \src "libresoc.v:140962.18-140962.98"
- wire $gt$libresoc.v:140962$6562_Y
- attribute \src "libresoc.v:140963.18-140963.98"
- wire $gt$libresoc.v:140963$6563_Y
- attribute \src "libresoc.v:140964.18-140964.98"
- wire $gt$libresoc.v:140964$6564_Y
- attribute \src "libresoc.v:140965.18-140965.98"
- wire $gt$libresoc.v:140965$6565_Y
- attribute \src "libresoc.v:140966.18-140966.98"
- wire $gt$libresoc.v:140966$6566_Y
- attribute \src "libresoc.v:140967.18-140967.98"
- wire $gt$libresoc.v:140967$6567_Y
- attribute \src "libresoc.v:140968.18-140968.98"
- wire $gt$libresoc.v:140968$6568_Y
- attribute \src "libresoc.v:140969.18-140969.98"
- wire $gt$libresoc.v:140969$6569_Y
- attribute \src "libresoc.v:140970.18-140970.98"
- wire $gt$libresoc.v:140970$6570_Y
+ attribute \src "libresoc.v:139037.17-139037.96"
+ wire $gt$libresoc.v:139037$6433_Y
+ attribute \src "libresoc.v:139038.18-139038.98"
+ wire $gt$libresoc.v:139038$6434_Y
+ attribute \src "libresoc.v:139039.19-139039.99"
+ wire $gt$libresoc.v:139039$6435_Y
+ attribute \src "libresoc.v:139040.19-139040.99"
+ wire $gt$libresoc.v:139040$6436_Y
+ attribute \src "libresoc.v:139041.19-139041.99"
+ wire $gt$libresoc.v:139041$6437_Y
+ attribute \src "libresoc.v:139042.19-139042.99"
+ wire $gt$libresoc.v:139042$6438_Y
+ attribute \src "libresoc.v:139043.19-139043.99"
+ wire $gt$libresoc.v:139043$6439_Y
+ attribute \src "libresoc.v:139044.19-139044.99"
+ wire $gt$libresoc.v:139044$6440_Y
+ attribute \src "libresoc.v:139045.19-139045.99"
+ wire $gt$libresoc.v:139045$6441_Y
+ attribute \src "libresoc.v:139046.19-139046.99"
+ wire $gt$libresoc.v:139046$6442_Y
+ attribute \src "libresoc.v:139047.19-139047.99"
+ wire $gt$libresoc.v:139047$6443_Y
+ attribute \src "libresoc.v:139048.18-139048.97"
+ wire $gt$libresoc.v:139048$6444_Y
+ attribute \src "libresoc.v:139049.19-139049.99"
+ wire $gt$libresoc.v:139049$6445_Y
+ attribute \src "libresoc.v:139050.19-139050.99"
+ wire $gt$libresoc.v:139050$6446_Y
+ attribute \src "libresoc.v:139051.19-139051.99"
+ wire $gt$libresoc.v:139051$6447_Y
+ attribute \src "libresoc.v:139052.19-139052.99"
+ wire $gt$libresoc.v:139052$6448_Y
+ attribute \src "libresoc.v:139053.19-139053.99"
+ wire $gt$libresoc.v:139053$6449_Y
+ attribute \src "libresoc.v:139054.18-139054.97"
+ wire $gt$libresoc.v:139054$6450_Y
+ attribute \src "libresoc.v:139055.18-139055.97"
+ wire $gt$libresoc.v:139055$6451_Y
+ attribute \src "libresoc.v:139056.18-139056.97"
+ wire $gt$libresoc.v:139056$6452_Y
+ attribute \src "libresoc.v:139057.17-139057.96"
+ wire $gt$libresoc.v:139057$6453_Y
+ attribute \src "libresoc.v:139058.18-139058.97"
+ wire $gt$libresoc.v:139058$6454_Y
+ attribute \src "libresoc.v:139059.18-139059.97"
+ wire $gt$libresoc.v:139059$6455_Y
+ attribute \src "libresoc.v:139060.18-139060.97"
+ wire $gt$libresoc.v:139060$6456_Y
+ attribute \src "libresoc.v:139061.18-139061.97"
+ wire $gt$libresoc.v:139061$6457_Y
+ attribute \src "libresoc.v:139062.18-139062.97"
+ wire $gt$libresoc.v:139062$6458_Y
+ attribute \src "libresoc.v:139063.18-139063.97"
+ wire $gt$libresoc.v:139063$6459_Y
+ attribute \src "libresoc.v:139064.18-139064.97"
+ wire $gt$libresoc.v:139064$6460_Y
+ attribute \src "libresoc.v:139065.18-139065.98"
+ wire $gt$libresoc.v:139065$6461_Y
+ attribute \src "libresoc.v:139066.18-139066.98"
+ wire $gt$libresoc.v:139066$6462_Y
+ attribute \src "libresoc.v:139067.18-139067.98"
+ wire $gt$libresoc.v:139067$6463_Y
+ attribute \src "libresoc.v:139068.17-139068.96"
+ wire $gt$libresoc.v:139068$6464_Y
+ attribute \src "libresoc.v:139069.18-139069.98"
+ wire $gt$libresoc.v:139069$6465_Y
+ attribute \src "libresoc.v:139070.18-139070.98"
+ wire $gt$libresoc.v:139070$6466_Y
+ attribute \src "libresoc.v:139071.18-139071.98"
+ wire $gt$libresoc.v:139071$6467_Y
+ attribute \src "libresoc.v:139072.18-139072.98"
+ wire $gt$libresoc.v:139072$6468_Y
+ attribute \src "libresoc.v:139073.18-139073.98"
+ wire $gt$libresoc.v:139073$6469_Y
+ attribute \src "libresoc.v:139074.18-139074.98"
+ wire $gt$libresoc.v:139074$6470_Y
+ attribute \src "libresoc.v:139075.18-139075.98"
+ wire $gt$libresoc.v:139075$6471_Y
+ attribute \src "libresoc.v:139076.18-139076.98"
+ wire $gt$libresoc.v:139076$6472_Y
+ attribute \src "libresoc.v:139077.18-139077.98"
+ wire $gt$libresoc.v:139077$6473_Y
+ attribute \src "libresoc.v:139078.18-139078.98"
+ wire $gt$libresoc.v:139078$6474_Y
+ attribute \src "libresoc.v:139079.17-139079.96"
+ wire $gt$libresoc.v:139079$6475_Y
+ attribute \src "libresoc.v:139080.18-139080.98"
+ wire $gt$libresoc.v:139080$6476_Y
+ attribute \src "libresoc.v:139081.18-139081.98"
+ wire $gt$libresoc.v:139081$6477_Y
+ attribute \src "libresoc.v:139082.18-139082.98"
+ wire $gt$libresoc.v:139082$6478_Y
+ attribute \src "libresoc.v:139083.18-139083.98"
+ wire $gt$libresoc.v:139083$6479_Y
+ attribute \src "libresoc.v:139084.18-139084.98"
+ wire $gt$libresoc.v:139084$6480_Y
+ attribute \src "libresoc.v:139085.18-139085.98"
+ wire $gt$libresoc.v:139085$6481_Y
+ attribute \src "libresoc.v:139086.18-139086.98"
+ wire $gt$libresoc.v:139086$6482_Y
+ attribute \src "libresoc.v:139087.18-139087.98"
+ wire $gt$libresoc.v:139087$6483_Y
+ attribute \src "libresoc.v:139088.18-139088.98"
+ wire $gt$libresoc.v:139088$6484_Y
+ attribute \src "libresoc.v:139089.18-139089.98"
+ wire $gt$libresoc.v:139089$6485_Y
+ attribute \src "libresoc.v:139090.17-139090.96"
+ wire $gt$libresoc.v:139090$6486_Y
+ attribute \src "libresoc.v:139091.18-139091.98"
+ wire $gt$libresoc.v:139091$6487_Y
+ attribute \src "libresoc.v:139092.18-139092.98"
+ wire $gt$libresoc.v:139092$6488_Y
+ attribute \src "libresoc.v:139093.18-139093.98"
+ wire $gt$libresoc.v:139093$6489_Y
+ attribute \src "libresoc.v:139094.18-139094.98"
+ wire $gt$libresoc.v:139094$6490_Y
+ attribute \src "libresoc.v:139095.18-139095.98"
+ wire $gt$libresoc.v:139095$6491_Y
+ attribute \src "libresoc.v:139096.18-139096.98"
+ wire $gt$libresoc.v:139096$6492_Y
+ attribute \src "libresoc.v:139097.18-139097.98"
+ wire $gt$libresoc.v:139097$6493_Y
+ attribute \src "libresoc.v:139098.18-139098.98"
+ wire $gt$libresoc.v:139098$6494_Y
+ attribute \src "libresoc.v:139099.18-139099.98"
+ wire $gt$libresoc.v:139099$6495_Y
+ attribute \src "libresoc.v:139100.18-139100.98"
+ wire $gt$libresoc.v:139100$6496_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$99
- attribute \src "libresoc.v:140773.7-140773.15"
+ attribute \src "libresoc.v:138903.7-138903.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20"
wire width 64 output 1 \mask
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19"
wire width 7 input 2 \shift
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140907$6507
+ cell $gt $gt$libresoc.v:139037$6433
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'100
- connect \Y $gt$libresoc.v:140907$6507_Y
+ connect \Y $gt$libresoc.v:139037$6433_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140908$6508
+ cell $gt $gt$libresoc.v:139038$6434
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110001
- connect \Y $gt$libresoc.v:140908$6508_Y
+ connect \Y $gt$libresoc.v:139038$6434_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140909$6509
+ cell $gt $gt$libresoc.v:139039$6435
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110010
- connect \Y $gt$libresoc.v:140909$6509_Y
+ connect \Y $gt$libresoc.v:139039$6435_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140910$6510
+ cell $gt $gt$libresoc.v:139040$6436
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110011
- connect \Y $gt$libresoc.v:140910$6510_Y
+ connect \Y $gt$libresoc.v:139040$6436_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140911$6511
+ cell $gt $gt$libresoc.v:139041$6437
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110100
- connect \Y $gt$libresoc.v:140911$6511_Y
+ connect \Y $gt$libresoc.v:139041$6437_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140912$6512
+ cell $gt $gt$libresoc.v:139042$6438
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110101
- connect \Y $gt$libresoc.v:140912$6512_Y
+ connect \Y $gt$libresoc.v:139042$6438_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140913$6513
+ cell $gt $gt$libresoc.v:139043$6439
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110110
- connect \Y $gt$libresoc.v:140913$6513_Y
+ connect \Y $gt$libresoc.v:139043$6439_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140914$6514
+ cell $gt $gt$libresoc.v:139044$6440
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110111
- connect \Y $gt$libresoc.v:140914$6514_Y
+ connect \Y $gt$libresoc.v:139044$6440_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140915$6515
+ cell $gt $gt$libresoc.v:139045$6441
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111000
- connect \Y $gt$libresoc.v:140915$6515_Y
+ connect \Y $gt$libresoc.v:139045$6441_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140916$6516
+ cell $gt $gt$libresoc.v:139046$6442
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111001
- connect \Y $gt$libresoc.v:140916$6516_Y
+ connect \Y $gt$libresoc.v:139046$6442_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140917$6517
+ cell $gt $gt$libresoc.v:139047$6443
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111010
- connect \Y $gt$libresoc.v:140917$6517_Y
+ connect \Y $gt$libresoc.v:139047$6443_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140918$6518
+ cell $gt $gt$libresoc.v:139048$6444
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'101
- connect \Y $gt$libresoc.v:140918$6518_Y
+ connect \Y $gt$libresoc.v:139048$6444_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140919$6519
+ cell $gt $gt$libresoc.v:139049$6445
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111011
- connect \Y $gt$libresoc.v:140919$6519_Y
+ connect \Y $gt$libresoc.v:139049$6445_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140920$6520
+ cell $gt $gt$libresoc.v:139050$6446
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111100
- connect \Y $gt$libresoc.v:140920$6520_Y
+ connect \Y $gt$libresoc.v:139050$6446_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140921$6521
+ cell $gt $gt$libresoc.v:139051$6447
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111101
- connect \Y $gt$libresoc.v:140921$6521_Y
+ connect \Y $gt$libresoc.v:139051$6447_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140922$6522
+ cell $gt $gt$libresoc.v:139052$6448
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111110
- connect \Y $gt$libresoc.v:140922$6522_Y
+ connect \Y $gt$libresoc.v:139052$6448_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140923$6523
+ cell $gt $gt$libresoc.v:139053$6449
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111111
- connect \Y $gt$libresoc.v:140923$6523_Y
+ connect \Y $gt$libresoc.v:139053$6449_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140924$6524
+ cell $gt $gt$libresoc.v:139054$6450
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'110
- connect \Y $gt$libresoc.v:140924$6524_Y
+ connect \Y $gt$libresoc.v:139054$6450_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140925$6525
+ cell $gt $gt$libresoc.v:139055$6451
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'111
- connect \Y $gt$libresoc.v:140925$6525_Y
+ connect \Y $gt$libresoc.v:139055$6451_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140926$6526
+ cell $gt $gt$libresoc.v:139056$6452
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1000
- connect \Y $gt$libresoc.v:140926$6526_Y
+ connect \Y $gt$libresoc.v:139056$6452_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140927$6527
+ cell $gt $gt$libresoc.v:139057$6453
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'0
- connect \Y $gt$libresoc.v:140927$6527_Y
+ connect \Y $gt$libresoc.v:139057$6453_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140928$6528
+ cell $gt $gt$libresoc.v:139058$6454
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1001
- connect \Y $gt$libresoc.v:140928$6528_Y
+ connect \Y $gt$libresoc.v:139058$6454_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140929$6529
+ cell $gt $gt$libresoc.v:139059$6455
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1010
- connect \Y $gt$libresoc.v:140929$6529_Y
+ connect \Y $gt$libresoc.v:139059$6455_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140930$6530
+ cell $gt $gt$libresoc.v:139060$6456
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1011
- connect \Y $gt$libresoc.v:140930$6530_Y
+ connect \Y $gt$libresoc.v:139060$6456_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140931$6531
+ cell $gt $gt$libresoc.v:139061$6457
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1100
- connect \Y $gt$libresoc.v:140931$6531_Y
+ connect \Y $gt$libresoc.v:139061$6457_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140932$6532
+ cell $gt $gt$libresoc.v:139062$6458
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1101
- connect \Y $gt$libresoc.v:140932$6532_Y
+ connect \Y $gt$libresoc.v:139062$6458_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140933$6533
+ cell $gt $gt$libresoc.v:139063$6459
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1110
- connect \Y $gt$libresoc.v:140933$6533_Y
+ connect \Y $gt$libresoc.v:139063$6459_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140934$6534
+ cell $gt $gt$libresoc.v:139064$6460
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1111
- connect \Y $gt$libresoc.v:140934$6534_Y
+ connect \Y $gt$libresoc.v:139064$6460_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140935$6535
+ cell $gt $gt$libresoc.v:139065$6461
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10000
- connect \Y $gt$libresoc.v:140935$6535_Y
+ connect \Y $gt$libresoc.v:139065$6461_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140936$6536
+ cell $gt $gt$libresoc.v:139066$6462
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10001
- connect \Y $gt$libresoc.v:140936$6536_Y
+ connect \Y $gt$libresoc.v:139066$6462_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140937$6537
+ cell $gt $gt$libresoc.v:139067$6463
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10010
- connect \Y $gt$libresoc.v:140937$6537_Y
+ connect \Y $gt$libresoc.v:139067$6463_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140938$6538
+ cell $gt $gt$libresoc.v:139068$6464
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'1
- connect \Y $gt$libresoc.v:140938$6538_Y
+ connect \Y $gt$libresoc.v:139068$6464_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140939$6539
+ cell $gt $gt$libresoc.v:139069$6465
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10011
- connect \Y $gt$libresoc.v:140939$6539_Y
+ connect \Y $gt$libresoc.v:139069$6465_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140940$6540
+ cell $gt $gt$libresoc.v:139070$6466
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10100
- connect \Y $gt$libresoc.v:140940$6540_Y
+ connect \Y $gt$libresoc.v:139070$6466_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140941$6541
+ cell $gt $gt$libresoc.v:139071$6467
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10101
- connect \Y $gt$libresoc.v:140941$6541_Y
+ connect \Y $gt$libresoc.v:139071$6467_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140942$6542
+ cell $gt $gt$libresoc.v:139072$6468
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10110
- connect \Y $gt$libresoc.v:140942$6542_Y
+ connect \Y $gt$libresoc.v:139072$6468_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140943$6543
+ cell $gt $gt$libresoc.v:139073$6469
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10111
- connect \Y $gt$libresoc.v:140943$6543_Y
+ connect \Y $gt$libresoc.v:139073$6469_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140944$6544
+ cell $gt $gt$libresoc.v:139074$6470
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11000
- connect \Y $gt$libresoc.v:140944$6544_Y
+ connect \Y $gt$libresoc.v:139074$6470_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140945$6545
+ cell $gt $gt$libresoc.v:139075$6471
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11001
- connect \Y $gt$libresoc.v:140945$6545_Y
+ connect \Y $gt$libresoc.v:139075$6471_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140946$6546
+ cell $gt $gt$libresoc.v:139076$6472
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11010
- connect \Y $gt$libresoc.v:140946$6546_Y
+ connect \Y $gt$libresoc.v:139076$6472_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140947$6547
+ cell $gt $gt$libresoc.v:139077$6473
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11011
- connect \Y $gt$libresoc.v:140947$6547_Y
+ connect \Y $gt$libresoc.v:139077$6473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140948$6548
+ cell $gt $gt$libresoc.v:139078$6474
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11100
- connect \Y $gt$libresoc.v:140948$6548_Y
+ connect \Y $gt$libresoc.v:139078$6474_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140949$6549
+ cell $gt $gt$libresoc.v:139079$6475
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'10
- connect \Y $gt$libresoc.v:140949$6549_Y
+ connect \Y $gt$libresoc.v:139079$6475_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140950$6550
+ cell $gt $gt$libresoc.v:139080$6476
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11101
- connect \Y $gt$libresoc.v:140950$6550_Y
+ connect \Y $gt$libresoc.v:139080$6476_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140951$6551
+ cell $gt $gt$libresoc.v:139081$6477
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11110
- connect \Y $gt$libresoc.v:140951$6551_Y
+ connect \Y $gt$libresoc.v:139081$6477_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140952$6552
+ cell $gt $gt$libresoc.v:139082$6478
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11111
- connect \Y $gt$libresoc.v:140952$6552_Y
+ connect \Y $gt$libresoc.v:139082$6478_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140953$6553
+ cell $gt $gt$libresoc.v:139083$6479
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100000
- connect \Y $gt$libresoc.v:140953$6553_Y
+ connect \Y $gt$libresoc.v:139083$6479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140954$6554
+ cell $gt $gt$libresoc.v:139084$6480
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100001
- connect \Y $gt$libresoc.v:140954$6554_Y
+ connect \Y $gt$libresoc.v:139084$6480_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140955$6555
+ cell $gt $gt$libresoc.v:139085$6481
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100010
- connect \Y $gt$libresoc.v:140955$6555_Y
+ connect \Y $gt$libresoc.v:139085$6481_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140956$6556
+ cell $gt $gt$libresoc.v:139086$6482
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100011
- connect \Y $gt$libresoc.v:140956$6556_Y
+ connect \Y $gt$libresoc.v:139086$6482_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140957$6557
+ cell $gt $gt$libresoc.v:139087$6483
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100100
- connect \Y $gt$libresoc.v:140957$6557_Y
+ connect \Y $gt$libresoc.v:139087$6483_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140958$6558
+ cell $gt $gt$libresoc.v:139088$6484
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100101
- connect \Y $gt$libresoc.v:140958$6558_Y
+ connect \Y $gt$libresoc.v:139088$6484_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140959$6559
+ cell $gt $gt$libresoc.v:139089$6485
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100110
- connect \Y $gt$libresoc.v:140959$6559_Y
+ connect \Y $gt$libresoc.v:139089$6485_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140960$6560
+ cell $gt $gt$libresoc.v:139090$6486
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'11
- connect \Y $gt$libresoc.v:140960$6560_Y
+ connect \Y $gt$libresoc.v:139090$6486_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140961$6561
+ cell $gt $gt$libresoc.v:139091$6487
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100111
- connect \Y $gt$libresoc.v:140961$6561_Y
+ connect \Y $gt$libresoc.v:139091$6487_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140962$6562
+ cell $gt $gt$libresoc.v:139092$6488
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101000
- connect \Y $gt$libresoc.v:140962$6562_Y
+ connect \Y $gt$libresoc.v:139092$6488_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140963$6563
+ cell $gt $gt$libresoc.v:139093$6489
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101001
- connect \Y $gt$libresoc.v:140963$6563_Y
+ connect \Y $gt$libresoc.v:139093$6489_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140964$6564
+ cell $gt $gt$libresoc.v:139094$6490
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101010
- connect \Y $gt$libresoc.v:140964$6564_Y
+ connect \Y $gt$libresoc.v:139094$6490_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140965$6565
+ cell $gt $gt$libresoc.v:139095$6491
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101011
- connect \Y $gt$libresoc.v:140965$6565_Y
+ connect \Y $gt$libresoc.v:139095$6491_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140966$6566
+ cell $gt $gt$libresoc.v:139096$6492
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101100
- connect \Y $gt$libresoc.v:140966$6566_Y
+ connect \Y $gt$libresoc.v:139096$6492_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140967$6567
+ cell $gt $gt$libresoc.v:139097$6493
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101101
- connect \Y $gt$libresoc.v:140967$6567_Y
+ connect \Y $gt$libresoc.v:139097$6493_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140968$6568
+ cell $gt $gt$libresoc.v:139098$6494
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101110
- connect \Y $gt$libresoc.v:140968$6568_Y
+ connect \Y $gt$libresoc.v:139098$6494_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140969$6569
+ cell $gt $gt$libresoc.v:139099$6495
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101111
- connect \Y $gt$libresoc.v:140969$6569_Y
+ connect \Y $gt$libresoc.v:139099$6495_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:140970$6570
+ cell $gt $gt$libresoc.v:139100$6496
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110000
- connect \Y $gt$libresoc.v:140970$6570_Y
+ connect \Y $gt$libresoc.v:139100$6496_Y
end
- attribute \src "libresoc.v:140773.7-140773.20"
- process $proc$libresoc.v:140773$6572
+ attribute \src "libresoc.v:138903.7-138903.20"
+ process $proc$libresoc.v:138903$6498
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:140971.3-141358.6"
- process $proc$libresoc.v:140971$6571
+ attribute \src "libresoc.v:139101.3-139488.6"
+ process $proc$libresoc.v:139101$6497
assign { } { }
assign { } { }
assign $0\mask[63:0] [0] $1\mask[0:0]
assign $0\mask[63:0] [61] $62\mask[61:61]
assign $0\mask[63:0] [62] $63\mask[62:62]
assign $0\mask[63:0] [63] $64\mask[63:63]
- attribute \src "libresoc.v:140972.5-140972.29"
+ attribute \src "libresoc.v:139102.5-139102.29"
switch \initial
- attribute \src "libresoc.v:140972.9-140972.17"
+ attribute \src "libresoc.v:139102.9-139102.17"
case 1'1
case
end
sync always
update \mask $0\mask[63:0]
end
- connect \$9 $gt$libresoc.v:140907$6507_Y
- connect \$99 $gt$libresoc.v:140908$6508_Y
- connect \$101 $gt$libresoc.v:140909$6509_Y
- connect \$103 $gt$libresoc.v:140910$6510_Y
- connect \$105 $gt$libresoc.v:140911$6511_Y
- connect \$107 $gt$libresoc.v:140912$6512_Y
- connect \$109 $gt$libresoc.v:140913$6513_Y
- connect \$111 $gt$libresoc.v:140914$6514_Y
- connect \$113 $gt$libresoc.v:140915$6515_Y
- connect \$115 $gt$libresoc.v:140916$6516_Y
- connect \$117 $gt$libresoc.v:140917$6517_Y
- connect \$11 $gt$libresoc.v:140918$6518_Y
- connect \$119 $gt$libresoc.v:140919$6519_Y
- connect \$121 $gt$libresoc.v:140920$6520_Y
- connect \$123 $gt$libresoc.v:140921$6521_Y
- connect \$125 $gt$libresoc.v:140922$6522_Y
- connect \$127 $gt$libresoc.v:140923$6523_Y
- connect \$13 $gt$libresoc.v:140924$6524_Y
- connect \$15 $gt$libresoc.v:140925$6525_Y
- connect \$17 $gt$libresoc.v:140926$6526_Y
- connect \$1 $gt$libresoc.v:140927$6527_Y
- connect \$19 $gt$libresoc.v:140928$6528_Y
- connect \$21 $gt$libresoc.v:140929$6529_Y
- connect \$23 $gt$libresoc.v:140930$6530_Y
- connect \$25 $gt$libresoc.v:140931$6531_Y
- connect \$27 $gt$libresoc.v:140932$6532_Y
- connect \$29 $gt$libresoc.v:140933$6533_Y
- connect \$31 $gt$libresoc.v:140934$6534_Y
- connect \$33 $gt$libresoc.v:140935$6535_Y
- connect \$35 $gt$libresoc.v:140936$6536_Y
- connect \$37 $gt$libresoc.v:140937$6537_Y
- connect \$3 $gt$libresoc.v:140938$6538_Y
- connect \$39 $gt$libresoc.v:140939$6539_Y
- connect \$41 $gt$libresoc.v:140940$6540_Y
- connect \$43 $gt$libresoc.v:140941$6541_Y
- connect \$45 $gt$libresoc.v:140942$6542_Y
- connect \$47 $gt$libresoc.v:140943$6543_Y
- connect \$49 $gt$libresoc.v:140944$6544_Y
- connect \$51 $gt$libresoc.v:140945$6545_Y
- connect \$53 $gt$libresoc.v:140946$6546_Y
- connect \$55 $gt$libresoc.v:140947$6547_Y
- connect \$57 $gt$libresoc.v:140948$6548_Y
- connect \$5 $gt$libresoc.v:140949$6549_Y
- connect \$59 $gt$libresoc.v:140950$6550_Y
- connect \$61 $gt$libresoc.v:140951$6551_Y
- connect \$63 $gt$libresoc.v:140952$6552_Y
- connect \$65 $gt$libresoc.v:140953$6553_Y
- connect \$67 $gt$libresoc.v:140954$6554_Y
- connect \$69 $gt$libresoc.v:140955$6555_Y
- connect \$71 $gt$libresoc.v:140956$6556_Y
- connect \$73 $gt$libresoc.v:140957$6557_Y
- connect \$75 $gt$libresoc.v:140958$6558_Y
- connect \$77 $gt$libresoc.v:140959$6559_Y
- connect \$7 $gt$libresoc.v:140960$6560_Y
- connect \$79 $gt$libresoc.v:140961$6561_Y
- connect \$81 $gt$libresoc.v:140962$6562_Y
- connect \$83 $gt$libresoc.v:140963$6563_Y
- connect \$85 $gt$libresoc.v:140964$6564_Y
- connect \$87 $gt$libresoc.v:140965$6565_Y
- connect \$89 $gt$libresoc.v:140966$6566_Y
- connect \$91 $gt$libresoc.v:140967$6567_Y
- connect \$93 $gt$libresoc.v:140968$6568_Y
- connect \$95 $gt$libresoc.v:140969$6569_Y
- connect \$97 $gt$libresoc.v:140970$6570_Y
+ connect \$9 $gt$libresoc.v:139037$6433_Y
+ connect \$99 $gt$libresoc.v:139038$6434_Y
+ connect \$101 $gt$libresoc.v:139039$6435_Y
+ connect \$103 $gt$libresoc.v:139040$6436_Y
+ connect \$105 $gt$libresoc.v:139041$6437_Y
+ connect \$107 $gt$libresoc.v:139042$6438_Y
+ connect \$109 $gt$libresoc.v:139043$6439_Y
+ connect \$111 $gt$libresoc.v:139044$6440_Y
+ connect \$113 $gt$libresoc.v:139045$6441_Y
+ connect \$115 $gt$libresoc.v:139046$6442_Y
+ connect \$117 $gt$libresoc.v:139047$6443_Y
+ connect \$11 $gt$libresoc.v:139048$6444_Y
+ connect \$119 $gt$libresoc.v:139049$6445_Y
+ connect \$121 $gt$libresoc.v:139050$6446_Y
+ connect \$123 $gt$libresoc.v:139051$6447_Y
+ connect \$125 $gt$libresoc.v:139052$6448_Y
+ connect \$127 $gt$libresoc.v:139053$6449_Y
+ connect \$13 $gt$libresoc.v:139054$6450_Y
+ connect \$15 $gt$libresoc.v:139055$6451_Y
+ connect \$17 $gt$libresoc.v:139056$6452_Y
+ connect \$1 $gt$libresoc.v:139057$6453_Y
+ connect \$19 $gt$libresoc.v:139058$6454_Y
+ connect \$21 $gt$libresoc.v:139059$6455_Y
+ connect \$23 $gt$libresoc.v:139060$6456_Y
+ connect \$25 $gt$libresoc.v:139061$6457_Y
+ connect \$27 $gt$libresoc.v:139062$6458_Y
+ connect \$29 $gt$libresoc.v:139063$6459_Y
+ connect \$31 $gt$libresoc.v:139064$6460_Y
+ connect \$33 $gt$libresoc.v:139065$6461_Y
+ connect \$35 $gt$libresoc.v:139066$6462_Y
+ connect \$37 $gt$libresoc.v:139067$6463_Y
+ connect \$3 $gt$libresoc.v:139068$6464_Y
+ connect \$39 $gt$libresoc.v:139069$6465_Y
+ connect \$41 $gt$libresoc.v:139070$6466_Y
+ connect \$43 $gt$libresoc.v:139071$6467_Y
+ connect \$45 $gt$libresoc.v:139072$6468_Y
+ connect \$47 $gt$libresoc.v:139073$6469_Y
+ connect \$49 $gt$libresoc.v:139074$6470_Y
+ connect \$51 $gt$libresoc.v:139075$6471_Y
+ connect \$53 $gt$libresoc.v:139076$6472_Y
+ connect \$55 $gt$libresoc.v:139077$6473_Y
+ connect \$57 $gt$libresoc.v:139078$6474_Y
+ connect \$5 $gt$libresoc.v:139079$6475_Y
+ connect \$59 $gt$libresoc.v:139080$6476_Y
+ connect \$61 $gt$libresoc.v:139081$6477_Y
+ connect \$63 $gt$libresoc.v:139082$6478_Y
+ connect \$65 $gt$libresoc.v:139083$6479_Y
+ connect \$67 $gt$libresoc.v:139084$6480_Y
+ connect \$69 $gt$libresoc.v:139085$6481_Y
+ connect \$71 $gt$libresoc.v:139086$6482_Y
+ connect \$73 $gt$libresoc.v:139087$6483_Y
+ connect \$75 $gt$libresoc.v:139088$6484_Y
+ connect \$77 $gt$libresoc.v:139089$6485_Y
+ connect \$7 $gt$libresoc.v:139090$6486_Y
+ connect \$79 $gt$libresoc.v:139091$6487_Y
+ connect \$81 $gt$libresoc.v:139092$6488_Y
+ connect \$83 $gt$libresoc.v:139093$6489_Y
+ connect \$85 $gt$libresoc.v:139094$6490_Y
+ connect \$87 $gt$libresoc.v:139095$6491_Y
+ connect \$89 $gt$libresoc.v:139096$6492_Y
+ connect \$91 $gt$libresoc.v:139097$6493_Y
+ connect \$93 $gt$libresoc.v:139098$6494_Y
+ connect \$95 $gt$libresoc.v:139099$6495_Y
+ connect \$97 $gt$libresoc.v:139100$6496_Y
end
-attribute \src "libresoc.v:141363.1-141392.10"
+attribute \src "libresoc.v:139493.1-139522.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp"
attribute \generator "nMigen"
module \lenexp
- attribute \src "libresoc.v:141387.17-141387.101"
- wire width 64 $extend$libresoc.v:141387$6576_Y
- attribute \src "libresoc.v:141387.17-141387.101"
- wire width 64 $pos$libresoc.v:141387$6577_Y
- attribute \src "libresoc.v:141384.17-141384.111"
- wire width 20 $sshl$libresoc.v:141384$6573_Y
- attribute \src "libresoc.v:141386.17-141386.113"
- wire width 32 $sshl$libresoc.v:141386$6575_Y
- attribute \src "libresoc.v:141385.17-141385.107"
- wire width 21 $sub$libresoc.v:141385$6574_Y
+ attribute \src "libresoc.v:139517.17-139517.101"
+ wire width 64 $extend$libresoc.v:139517$6502_Y
+ attribute \src "libresoc.v:139517.17-139517.101"
+ wire width 64 $pos$libresoc.v:139517$6503_Y
+ attribute \src "libresoc.v:139514.17-139514.111"
+ wire width 20 $sshl$libresoc.v:139514$6499_Y
+ attribute \src "libresoc.v:139516.17-139516.113"
+ wire width 32 $sshl$libresoc.v:139516$6501_Y
+ attribute \src "libresoc.v:139515.17-139515.107"
+ wire width 21 $sub$libresoc.v:139515$6500_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
wire width 21 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
wire width 176 output 3 \rexp_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $pos $extend$libresoc.v:141387$6576
+ cell $pos $extend$libresoc.v:139517$6502
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \$7
- connect \Y $extend$libresoc.v:141387$6576_Y
+ connect \Y $extend$libresoc.v:139517$6502_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $pos $pos$libresoc.v:141387$6577
+ cell $pos $pos$libresoc.v:139517$6503
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:141387$6576_Y
- connect \Y $pos$libresoc.v:141387$6577_Y
+ connect \A $extend$libresoc.v:139517$6502_Y
+ connect \Y $pos$libresoc.v:139517$6503_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $sshl $sshl$libresoc.v:141384$6573
+ cell $sshl $sshl$libresoc.v:139514$6499
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A 5'00001
connect \B \len_i
- connect \Y $sshl$libresoc.v:141384$6573_Y
+ connect \Y $sshl$libresoc.v:139514$6499_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
- cell $sshl $sshl$libresoc.v:141386$6575
+ cell $sshl $sshl$libresoc.v:139516$6501
parameter \A_SIGNED 0
parameter \A_WIDTH 17
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \binlen
connect \B \addr_i
- connect \Y $sshl$libresoc.v:141386$6575_Y
+ connect \Y $sshl$libresoc.v:139516$6501_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $sub $sub$libresoc.v:141385$6574
+ cell $sub $sub$libresoc.v:139515$6500
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 21
connect \A \$2
connect \B 1'1
- connect \Y $sub$libresoc.v:141385$6574_Y
+ connect \Y $sub$libresoc.v:139515$6500_Y
end
- connect \$2 $sshl$libresoc.v:141384$6573_Y
- connect \$4 $sub$libresoc.v:141385$6574_Y
- connect \$7 $sshl$libresoc.v:141386$6575_Y
- connect \$6 $pos$libresoc.v:141387$6577_Y
+ connect \$2 $sshl$libresoc.v:139514$6499_Y
+ connect \$4 $sub$libresoc.v:139515$6500_Y
+ connect \$7 $sshl$libresoc.v:139516$6501_Y
+ connect \$6 $pos$libresoc.v:139517$6503_Y
connect \$1 \$4
connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] }
connect \lexp_o \$6
connect \binlen \$4 [16:0]
end
-attribute \src "libresoc.v:141396.1-141454.10"
+attribute \src "libresoc.v:139526.1-139584.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l"
attribute \generator "nMigen"
module \lod_l
- attribute \src "libresoc.v:141397.7-141397.20"
+ attribute \src "libresoc.v:139527.7-139527.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:141442.3-141450.6"
- wire $0\q_int$next[0:0]$6588
- attribute \src "libresoc.v:141440.3-141441.27"
+ attribute \src "libresoc.v:139572.3-139580.6"
+ wire $0\q_int$next[0:0]$6514
+ attribute \src "libresoc.v:139570.3-139571.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:141442.3-141450.6"
- wire $1\q_int$next[0:0]$6589
- attribute \src "libresoc.v:141419.7-141419.19"
+ attribute \src "libresoc.v:139572.3-139580.6"
+ wire $1\q_int$next[0:0]$6515
+ attribute \src "libresoc.v:139549.7-139549.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:141432.17-141432.96"
- wire $and$libresoc.v:141432$6578_Y
- attribute \src "libresoc.v:141437.17-141437.96"
- wire $and$libresoc.v:141437$6583_Y
- attribute \src "libresoc.v:141434.18-141434.93"
- wire $not$libresoc.v:141434$6580_Y
- attribute \src "libresoc.v:141436.17-141436.92"
- wire $not$libresoc.v:141436$6582_Y
- attribute \src "libresoc.v:141439.17-141439.92"
- wire $not$libresoc.v:141439$6585_Y
- attribute \src "libresoc.v:141433.18-141433.98"
- wire $or$libresoc.v:141433$6579_Y
- attribute \src "libresoc.v:141435.18-141435.99"
- wire $or$libresoc.v:141435$6581_Y
- attribute \src "libresoc.v:141438.17-141438.97"
- wire $or$libresoc.v:141438$6584_Y
+ attribute \src "libresoc.v:139562.17-139562.96"
+ wire $and$libresoc.v:139562$6504_Y
+ attribute \src "libresoc.v:139567.17-139567.96"
+ wire $and$libresoc.v:139567$6509_Y
+ attribute \src "libresoc.v:139564.18-139564.93"
+ wire $not$libresoc.v:139564$6506_Y
+ attribute \src "libresoc.v:139566.17-139566.92"
+ wire $not$libresoc.v:139566$6508_Y
+ attribute \src "libresoc.v:139569.17-139569.92"
+ wire $not$libresoc.v:139569$6511_Y
+ attribute \src "libresoc.v:139563.18-139563.98"
+ wire $or$libresoc.v:139563$6505_Y
+ attribute \src "libresoc.v:139565.18-139565.99"
+ wire $or$libresoc.v:139565$6507_Y
+ attribute \src "libresoc.v:139568.17-139568.97"
+ wire $or$libresoc.v:139568$6510_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:141397.7-141397.15"
+ attribute \src "libresoc.v:139527.7-139527.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_lod
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:141432$6578
+ cell $and $and$libresoc.v:139562$6504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:141432$6578_Y
+ connect \Y $and$libresoc.v:139562$6504_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:141437$6583
+ cell $and $and$libresoc.v:139567$6509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:141437$6583_Y
+ connect \Y $and$libresoc.v:139567$6509_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:141434$6580
+ cell $not $not$libresoc.v:139564$6506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_lod
- connect \Y $not$libresoc.v:141434$6580_Y
+ connect \Y $not$libresoc.v:139564$6506_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:141436$6582
+ cell $not $not$libresoc.v:139566$6508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lod
- connect \Y $not$libresoc.v:141436$6582_Y
+ connect \Y $not$libresoc.v:139566$6508_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:141439$6585
+ cell $not $not$libresoc.v:139569$6511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lod
- connect \Y $not$libresoc.v:141439$6585_Y
+ connect \Y $not$libresoc.v:139569$6511_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:141433$6579
+ cell $or $or$libresoc.v:139563$6505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_lod
- connect \Y $or$libresoc.v:141433$6579_Y
+ connect \Y $or$libresoc.v:139563$6505_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:141435$6581
+ cell $or $or$libresoc.v:139565$6507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_lod
connect \B \q_int
- connect \Y $or$libresoc.v:141435$6581_Y
+ connect \Y $or$libresoc.v:139565$6507_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:141438$6584
+ cell $or $or$libresoc.v:139568$6510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_lod
- connect \Y $or$libresoc.v:141438$6584_Y
+ connect \Y $or$libresoc.v:139568$6510_Y
end
- attribute \src "libresoc.v:141397.7-141397.20"
- process $proc$libresoc.v:141397$6590
+ attribute \src "libresoc.v:139527.7-139527.20"
+ process $proc$libresoc.v:139527$6516
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:141419.7-141419.19"
- process $proc$libresoc.v:141419$6591
+ attribute \src "libresoc.v:139549.7-139549.19"
+ process $proc$libresoc.v:139549$6517
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:141440.3-141441.27"
- process $proc$libresoc.v:141440$6586
+ attribute \src "libresoc.v:139570.3-139571.27"
+ process $proc$libresoc.v:139570$6512
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:141442.3-141450.6"
- process $proc$libresoc.v:141442$6587
+ attribute \src "libresoc.v:139572.3-139580.6"
+ process $proc$libresoc.v:139572$6513
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$6588 $1\q_int$next[0:0]$6589
- attribute \src "libresoc.v:141443.5-141443.29"
+ assign $0\q_int$next[0:0]$6514 $1\q_int$next[0:0]$6515
+ attribute \src "libresoc.v:139573.5-139573.29"
switch \initial
- attribute \src "libresoc.v:141443.9-141443.17"
+ attribute \src "libresoc.v:139573.9-139573.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$6589 1'0
+ assign $1\q_int$next[0:0]$6515 1'0
case
- assign $1\q_int$next[0:0]$6589 \$5
+ assign $1\q_int$next[0:0]$6515 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$6588
+ update \q_int$next $0\q_int$next[0:0]$6514
end
- connect \$9 $and$libresoc.v:141432$6578_Y
- connect \$11 $or$libresoc.v:141433$6579_Y
- connect \$13 $not$libresoc.v:141434$6580_Y
- connect \$15 $or$libresoc.v:141435$6581_Y
- connect \$1 $not$libresoc.v:141436$6582_Y
- connect \$3 $and$libresoc.v:141437$6583_Y
- connect \$5 $or$libresoc.v:141438$6584_Y
- connect \$7 $not$libresoc.v:141439$6585_Y
+ connect \$9 $and$libresoc.v:139562$6504_Y
+ connect \$11 $or$libresoc.v:139563$6505_Y
+ connect \$13 $not$libresoc.v:139564$6506_Y
+ connect \$15 $or$libresoc.v:139565$6507_Y
+ connect \$1 $not$libresoc.v:139566$6508_Y
+ connect \$3 $and$libresoc.v:139567$6509_Y
+ connect \$5 $or$libresoc.v:139568$6510_Y
+ connect \$7 $not$libresoc.v:139569$6511_Y
connect \qlq_lod \$15
connect \qn_lod \$13
connect \q_lod \$11
end
-attribute \src "libresoc.v:141458.1-142574.10"
+attribute \src "libresoc.v:139588.1-140704.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0"
attribute \generator "nMigen"
module \logical0
- attribute \src "libresoc.v:142199.3-142200.24"
+ attribute \src "libresoc.v:140329.3-140330.24"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:142197.3-142198.44"
+ attribute \src "libresoc.v:140327.3-140328.44"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:142504.3-142512.6"
- wire $0\alu_l_r_alu$next[0:0]$6792
- attribute \src "libresoc.v:142121.3-142122.39"
+ attribute \src "libresoc.v:140634.3-140642.6"
+ wire $0\alu_l_r_alu$next[0:0]$6718
+ attribute \src "libresoc.v:140251.3-140252.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6721
- attribute \src "libresoc.v:142171.3-142172.83"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6647
+ attribute \src "libresoc.v:140301.3-140302.83"
wire width 4 $0\alu_logical0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722
- attribute \src "libresoc.v:142141.3-142142.81"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648
+ attribute \src "libresoc.v:140271.3-140272.81"
wire width 13 $0\alu_logical0_logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723
- attribute \src "libresoc.v:142143.3-142144.95"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649
+ attribute \src "libresoc.v:140273.3-140274.95"
wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724
- attribute \src "libresoc.v:142145.3-142146.91"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650
+ attribute \src "libresoc.v:140275.3-140276.91"
wire $0\alu_logical0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6725
- attribute \src "libresoc.v:142159.3-142160.89"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6651
+ attribute \src "libresoc.v:140289.3-140290.89"
wire width 2 $0\alu_logical0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6726
- attribute \src "libresoc.v:142173.3-142174.75"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6652
+ attribute \src "libresoc.v:140303.3-140304.75"
wire width 32 $0\alu_logical0_logical_op__insn[31:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6727
- attribute \src "libresoc.v:142139.3-142140.85"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6653
+ attribute \src "libresoc.v:140269.3-140270.85"
wire width 7 $0\alu_logical0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6728
- attribute \src "libresoc.v:142155.3-142156.85"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6654
+ attribute \src "libresoc.v:140285.3-140286.85"
wire $0\alu_logical0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6729
- attribute \src "libresoc.v:142161.3-142162.87"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6655
+ attribute \src "libresoc.v:140291.3-140292.87"
wire $0\alu_logical0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730
- attribute \src "libresoc.v:142167.3-142168.83"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656
+ attribute \src "libresoc.v:140297.3-140298.83"
wire $0\alu_logical0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6731
- attribute \src "libresoc.v:142169.3-142170.85"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6657
+ attribute \src "libresoc.v:140299.3-140300.85"
wire $0\alu_logical0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732
- attribute \src "libresoc.v:142151.3-142152.79"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658
+ attribute \src "libresoc.v:140281.3-140282.79"
wire $0\alu_logical0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733
- attribute \src "libresoc.v:142153.3-142154.79"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659
+ attribute \src "libresoc.v:140283.3-140284.79"
wire $0\alu_logical0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6734
- attribute \src "libresoc.v:142165.3-142166.91"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6660
+ attribute \src "libresoc.v:140295.3-140296.91"
wire $0\alu_logical0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735
- attribute \src "libresoc.v:142149.3-142150.79"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661
+ attribute \src "libresoc.v:140279.3-140280.79"
wire $0\alu_logical0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736
- attribute \src "libresoc.v:142147.3-142148.79"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662
+ attribute \src "libresoc.v:140277.3-140278.79"
wire $0\alu_logical0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737
- attribute \src "libresoc.v:142163.3-142164.85"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663
+ attribute \src "libresoc.v:140293.3-140294.85"
wire $0\alu_logical0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6738
- attribute \src "libresoc.v:142157.3-142158.79"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6664
+ attribute \src "libresoc.v:140287.3-140288.79"
wire $0\alu_logical0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:142495.3-142503.6"
- wire $0\alui_l_r_alui$next[0:0]$6789
- attribute \src "libresoc.v:142123.3-142124.43"
+ attribute \src "libresoc.v:140625.3-140633.6"
+ wire $0\alui_l_r_alui$next[0:0]$6715
+ attribute \src "libresoc.v:140253.3-140254.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:142421.3-142442.6"
- wire width 64 $0\data_r0__o$next[63:0]$6764
- attribute \src "libresoc.v:142135.3-142136.37"
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire width 64 $0\data_r0__o$next[63:0]$6690
+ attribute \src "libresoc.v:140265.3-140266.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:142421.3-142442.6"
- wire $0\data_r0__o_ok$next[0:0]$6765
- attribute \src "libresoc.v:142137.3-142138.43"
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire $0\data_r0__o_ok$next[0:0]$6691
+ attribute \src "libresoc.v:140267.3-140268.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:142443.3-142464.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$6772
- attribute \src "libresoc.v:142131.3-142132.43"
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$6698
+ attribute \src "libresoc.v:140261.3-140262.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:142443.3-142464.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$6773
- attribute \src "libresoc.v:142133.3-142134.49"
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$6699
+ attribute \src "libresoc.v:140263.3-140264.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:142513.3-142522.6"
+ attribute \src "libresoc.v:140643.3-140652.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:142523.3-142532.6"
+ attribute \src "libresoc.v:140653.3-140662.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:141459.7-141459.20"
+ attribute \src "libresoc.v:139589.7-139589.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:142337.3-142345.6"
- wire $0\opc_l_r_opc$next[0:0]$6706
- attribute \src "libresoc.v:142183.3-142184.39"
+ attribute \src "libresoc.v:140467.3-140475.6"
+ wire $0\opc_l_r_opc$next[0:0]$6632
+ attribute \src "libresoc.v:140313.3-140314.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:142328.3-142336.6"
- wire $0\opc_l_s_opc$next[0:0]$6703
- attribute \src "libresoc.v:142185.3-142186.39"
+ attribute \src "libresoc.v:140458.3-140466.6"
+ wire $0\opc_l_s_opc$next[0:0]$6629
+ attribute \src "libresoc.v:140315.3-140316.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:142533.3-142541.6"
- wire width 2 $0\prev_wr_go$next[1:0]$6797
- attribute \src "libresoc.v:142195.3-142196.37"
+ attribute \src "libresoc.v:140663.3-140671.6"
+ wire width 2 $0\prev_wr_go$next[1:0]$6723
+ attribute \src "libresoc.v:140325.3-140326.37"
wire width 2 $0\prev_wr_go[1:0]
- attribute \src "libresoc.v:142282.3-142291.6"
+ attribute \src "libresoc.v:140412.3-140421.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:142373.3-142381.6"
- wire width 2 $0\req_l_r_req$next[1:0]$6718
- attribute \src "libresoc.v:142175.3-142176.39"
+ attribute \src "libresoc.v:140503.3-140511.6"
+ wire width 2 $0\req_l_r_req$next[1:0]$6644
+ attribute \src "libresoc.v:140305.3-140306.39"
wire width 2 $0\req_l_r_req[1:0]
- attribute \src "libresoc.v:142364.3-142372.6"
- wire width 2 $0\req_l_s_req$next[1:0]$6715
- attribute \src "libresoc.v:142177.3-142178.39"
+ attribute \src "libresoc.v:140494.3-140502.6"
+ wire width 2 $0\req_l_s_req$next[1:0]$6641
+ attribute \src "libresoc.v:140307.3-140308.39"
wire width 2 $0\req_l_s_req[1:0]
- attribute \src "libresoc.v:142301.3-142309.6"
- wire $0\rok_l_r_rdok$next[0:0]$6694
- attribute \src "libresoc.v:142191.3-142192.41"
+ attribute \src "libresoc.v:140431.3-140439.6"
+ wire $0\rok_l_r_rdok$next[0:0]$6620
+ attribute \src "libresoc.v:140321.3-140322.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:142292.3-142300.6"
- wire $0\rok_l_s_rdok$next[0:0]$6691
- attribute \src "libresoc.v:142193.3-142194.41"
+ attribute \src "libresoc.v:140422.3-140430.6"
+ wire $0\rok_l_s_rdok$next[0:0]$6617
+ attribute \src "libresoc.v:140323.3-140324.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:142319.3-142327.6"
- wire $0\rst_l_r_rst$next[0:0]$6700
- attribute \src "libresoc.v:142187.3-142188.39"
+ attribute \src "libresoc.v:140449.3-140457.6"
+ wire $0\rst_l_r_rst$next[0:0]$6626
+ attribute \src "libresoc.v:140317.3-140318.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:142310.3-142318.6"
- wire $0\rst_l_s_rst$next[0:0]$6697
- attribute \src "libresoc.v:142189.3-142190.39"
+ attribute \src "libresoc.v:140440.3-140448.6"
+ wire $0\rst_l_s_rst$next[0:0]$6623
+ attribute \src "libresoc.v:140319.3-140320.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:142355.3-142363.6"
- wire width 3 $0\src_l_r_src$next[2:0]$6712
- attribute \src "libresoc.v:142179.3-142180.39"
+ attribute \src "libresoc.v:140485.3-140493.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$6638
+ attribute \src "libresoc.v:140309.3-140310.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:142346.3-142354.6"
- wire width 3 $0\src_l_s_src$next[2:0]$6709
- attribute \src "libresoc.v:142181.3-142182.39"
+ attribute \src "libresoc.v:140476.3-140484.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$6635
+ attribute \src "libresoc.v:140311.3-140312.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:142465.3-142474.6"
- wire width 64 $0\src_r0$next[63:0]$6780
- attribute \src "libresoc.v:142129.3-142130.29"
+ attribute \src "libresoc.v:140595.3-140604.6"
+ wire width 64 $0\src_r0$next[63:0]$6706
+ attribute \src "libresoc.v:140259.3-140260.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:142475.3-142484.6"
- wire width 64 $0\src_r1$next[63:0]$6783
- attribute \src "libresoc.v:142127.3-142128.29"
+ attribute \src "libresoc.v:140605.3-140614.6"
+ wire width 64 $0\src_r1$next[63:0]$6709
+ attribute \src "libresoc.v:140257.3-140258.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:142485.3-142494.6"
- wire $0\src_r2$next[0:0]$6786
- attribute \src "libresoc.v:142125.3-142126.29"
+ attribute \src "libresoc.v:140615.3-140624.6"
+ wire $0\src_r2$next[0:0]$6712
+ attribute \src "libresoc.v:140255.3-140256.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:141577.7-141577.24"
+ attribute \src "libresoc.v:139707.7-139707.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:141587.7-141587.26"
+ attribute \src "libresoc.v:139717.7-139717.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:142504.3-142512.6"
- wire $1\alu_l_r_alu$next[0:0]$6793
- attribute \src "libresoc.v:141595.7-141595.25"
+ attribute \src "libresoc.v:140634.3-140642.6"
+ wire $1\alu_l_r_alu$next[0:0]$6719
+ attribute \src "libresoc.v:139725.7-139725.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6739
- attribute \src "libresoc.v:141603.13-141603.53"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6665
+ attribute \src "libresoc.v:139733.13-139733.53"
wire width 4 $1\alu_logical0_logical_op__data_len[3:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740
- attribute \src "libresoc.v:141621.14-141621.57"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666
+ attribute \src "libresoc.v:139751.14-139751.57"
wire width 13 $1\alu_logical0_logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741
- attribute \src "libresoc.v:141625.14-141625.76"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667
+ attribute \src "libresoc.v:139755.14-139755.76"
wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742
- attribute \src "libresoc.v:141629.7-141629.51"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668
+ attribute \src "libresoc.v:139759.7-139759.51"
wire $1\alu_logical0_logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743
- attribute \src "libresoc.v:141637.13-141637.56"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669
+ attribute \src "libresoc.v:139767.13-139767.56"
wire width 2 $1\alu_logical0_logical_op__input_carry[1:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6744
- attribute \src "libresoc.v:141641.14-141641.51"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6670
+ attribute \src "libresoc.v:139771.14-139771.51"
wire width 32 $1\alu_logical0_logical_op__insn[31:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745
- attribute \src "libresoc.v:141719.13-141719.55"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671
+ attribute \src "libresoc.v:139849.13-139849.55"
wire width 7 $1\alu_logical0_logical_op__insn_type[6:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6746
- attribute \src "libresoc.v:141723.7-141723.48"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6672
+ attribute \src "libresoc.v:139853.7-139853.48"
wire $1\alu_logical0_logical_op__invert_in[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6747
- attribute \src "libresoc.v:141727.7-141727.49"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6673
+ attribute \src "libresoc.v:139857.7-139857.49"
wire $1\alu_logical0_logical_op__invert_out[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748
- attribute \src "libresoc.v:141731.7-141731.47"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674
+ attribute \src "libresoc.v:139861.7-139861.47"
wire $1\alu_logical0_logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6749
- attribute \src "libresoc.v:141735.7-141735.48"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6675
+ attribute \src "libresoc.v:139865.7-139865.48"
wire $1\alu_logical0_logical_op__is_signed[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750
- attribute \src "libresoc.v:141739.7-141739.45"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676
+ attribute \src "libresoc.v:139869.7-139869.45"
wire $1\alu_logical0_logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751
- attribute \src "libresoc.v:141743.7-141743.45"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677
+ attribute \src "libresoc.v:139873.7-139873.45"
wire $1\alu_logical0_logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6752
- attribute \src "libresoc.v:141747.7-141747.51"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6678
+ attribute \src "libresoc.v:139877.7-139877.51"
wire $1\alu_logical0_logical_op__output_carry[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753
- attribute \src "libresoc.v:141751.7-141751.45"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679
+ attribute \src "libresoc.v:139881.7-139881.45"
wire $1\alu_logical0_logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754
- attribute \src "libresoc.v:141755.7-141755.45"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680
+ attribute \src "libresoc.v:139885.7-139885.45"
wire $1\alu_logical0_logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755
- attribute \src "libresoc.v:141759.7-141759.48"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681
+ attribute \src "libresoc.v:139889.7-139889.48"
wire $1\alu_logical0_logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6756
- attribute \src "libresoc.v:141763.7-141763.45"
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6682
+ attribute \src "libresoc.v:139893.7-139893.45"
wire $1\alu_logical0_logical_op__zero_a[0:0]
- attribute \src "libresoc.v:142495.3-142503.6"
- wire $1\alui_l_r_alui$next[0:0]$6790
- attribute \src "libresoc.v:141789.7-141789.27"
+ attribute \src "libresoc.v:140625.3-140633.6"
+ wire $1\alui_l_r_alui$next[0:0]$6716
+ attribute \src "libresoc.v:139919.7-139919.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:142421.3-142442.6"
- wire width 64 $1\data_r0__o$next[63:0]$6766
- attribute \src "libresoc.v:141823.14-141823.47"
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire width 64 $1\data_r0__o$next[63:0]$6692
+ attribute \src "libresoc.v:139953.14-139953.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:142421.3-142442.6"
- wire $1\data_r0__o_ok$next[0:0]$6767
- attribute \src "libresoc.v:141827.7-141827.27"
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire $1\data_r0__o_ok$next[0:0]$6693
+ attribute \src "libresoc.v:139957.7-139957.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:142443.3-142464.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$6774
- attribute \src "libresoc.v:141831.13-141831.33"
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$6700
+ attribute \src "libresoc.v:139961.13-139961.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:142443.3-142464.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$6775
- attribute \src "libresoc.v:141835.7-141835.30"
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$6701
+ attribute \src "libresoc.v:139965.7-139965.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:142513.3-142522.6"
+ attribute \src "libresoc.v:140643.3-140652.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:142523.3-142532.6"
+ attribute \src "libresoc.v:140653.3-140662.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:142337.3-142345.6"
- wire $1\opc_l_r_opc$next[0:0]$6707
- attribute \src "libresoc.v:141849.7-141849.25"
+ attribute \src "libresoc.v:140467.3-140475.6"
+ wire $1\opc_l_r_opc$next[0:0]$6633
+ attribute \src "libresoc.v:139979.7-139979.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:142328.3-142336.6"
- wire $1\opc_l_s_opc$next[0:0]$6704
- attribute \src "libresoc.v:141853.7-141853.25"
+ attribute \src "libresoc.v:140458.3-140466.6"
+ wire $1\opc_l_s_opc$next[0:0]$6630
+ attribute \src "libresoc.v:139983.7-139983.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:142533.3-142541.6"
- wire width 2 $1\prev_wr_go$next[1:0]$6798
- attribute \src "libresoc.v:141985.13-141985.30"
+ attribute \src "libresoc.v:140663.3-140671.6"
+ wire width 2 $1\prev_wr_go$next[1:0]$6724
+ attribute \src "libresoc.v:140115.13-140115.30"
wire width 2 $1\prev_wr_go[1:0]
- attribute \src "libresoc.v:142282.3-142291.6"
+ attribute \src "libresoc.v:140412.3-140421.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:142373.3-142381.6"
- wire width 2 $1\req_l_r_req$next[1:0]$6719
- attribute \src "libresoc.v:141993.13-141993.31"
+ attribute \src "libresoc.v:140503.3-140511.6"
+ wire width 2 $1\req_l_r_req$next[1:0]$6645
+ attribute \src "libresoc.v:140123.13-140123.31"
wire width 2 $1\req_l_r_req[1:0]
- attribute \src "libresoc.v:142364.3-142372.6"
- wire width 2 $1\req_l_s_req$next[1:0]$6716
- attribute \src "libresoc.v:141997.13-141997.31"
+ attribute \src "libresoc.v:140494.3-140502.6"
+ wire width 2 $1\req_l_s_req$next[1:0]$6642
+ attribute \src "libresoc.v:140127.13-140127.31"
wire width 2 $1\req_l_s_req[1:0]
- attribute \src "libresoc.v:142301.3-142309.6"
- wire $1\rok_l_r_rdok$next[0:0]$6695
- attribute \src "libresoc.v:142009.7-142009.26"
+ attribute \src "libresoc.v:140431.3-140439.6"
+ wire $1\rok_l_r_rdok$next[0:0]$6621
+ attribute \src "libresoc.v:140139.7-140139.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:142292.3-142300.6"
- wire $1\rok_l_s_rdok$next[0:0]$6692
- attribute \src "libresoc.v:142013.7-142013.26"
+ attribute \src "libresoc.v:140422.3-140430.6"
+ wire $1\rok_l_s_rdok$next[0:0]$6618
+ attribute \src "libresoc.v:140143.7-140143.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:142319.3-142327.6"
- wire $1\rst_l_r_rst$next[0:0]$6701
- attribute \src "libresoc.v:142017.7-142017.25"
+ attribute \src "libresoc.v:140449.3-140457.6"
+ wire $1\rst_l_r_rst$next[0:0]$6627
+ attribute \src "libresoc.v:140147.7-140147.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:142310.3-142318.6"
- wire $1\rst_l_s_rst$next[0:0]$6698
- attribute \src "libresoc.v:142021.7-142021.25"
+ attribute \src "libresoc.v:140440.3-140448.6"
+ wire $1\rst_l_s_rst$next[0:0]$6624
+ attribute \src "libresoc.v:140151.7-140151.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:142355.3-142363.6"
- wire width 3 $1\src_l_r_src$next[2:0]$6713
- attribute \src "libresoc.v:142035.13-142035.31"
+ attribute \src "libresoc.v:140485.3-140493.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$6639
+ attribute \src "libresoc.v:140165.13-140165.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:142346.3-142354.6"
- wire width 3 $1\src_l_s_src$next[2:0]$6710
- attribute \src "libresoc.v:142039.13-142039.31"
+ attribute \src "libresoc.v:140476.3-140484.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$6636
+ attribute \src "libresoc.v:140169.13-140169.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:142465.3-142474.6"
- wire width 64 $1\src_r0$next[63:0]$6781
- attribute \src "libresoc.v:142047.14-142047.43"
+ attribute \src "libresoc.v:140595.3-140604.6"
+ wire width 64 $1\src_r0$next[63:0]$6707
+ attribute \src "libresoc.v:140177.14-140177.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:142475.3-142484.6"
- wire width 64 $1\src_r1$next[63:0]$6784
- attribute \src "libresoc.v:142051.14-142051.43"
+ attribute \src "libresoc.v:140605.3-140614.6"
+ wire width 64 $1\src_r1$next[63:0]$6710
+ attribute \src "libresoc.v:140181.14-140181.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:142485.3-142494.6"
- wire $1\src_r2$next[0:0]$6787
- attribute \src "libresoc.v:142055.7-142055.20"
+ attribute \src "libresoc.v:140615.3-140624.6"
+ wire $1\src_r2$next[0:0]$6713
+ attribute \src "libresoc.v:140185.7-140185.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:142382.3-142420.6"
- wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761
- attribute \src "libresoc.v:142382.3-142420.6"
- wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762
- attribute \src "libresoc.v:142421.3-142442.6"
- wire width 64 $2\data_r0__o$next[63:0]$6768
- attribute \src "libresoc.v:142421.3-142442.6"
- wire $2\data_r0__o_ok$next[0:0]$6769
- attribute \src "libresoc.v:142443.3-142464.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$6776
- attribute \src "libresoc.v:142443.3-142464.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$6777
- attribute \src "libresoc.v:142421.3-142442.6"
- wire $3\data_r0__o_ok$next[0:0]$6770
- attribute \src "libresoc.v:142443.3-142464.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$6778
- attribute \src "libresoc.v:142064.17-142064.109"
- wire $and$libresoc.v:142064$6592_Y
- attribute \src "libresoc.v:142065.18-142065.130"
- wire width 3 $and$libresoc.v:142065$6593_Y
- attribute \src "libresoc.v:142067.19-142067.114"
- wire width 3 $and$libresoc.v:142067$6595_Y
- attribute \src "libresoc.v:142068.19-142068.125"
- wire $and$libresoc.v:142068$6596_Y
- attribute \src "libresoc.v:142069.19-142069.125"
- wire $and$libresoc.v:142069$6597_Y
- attribute \src "libresoc.v:142070.19-142070.133"
- wire width 2 $and$libresoc.v:142070$6598_Y
- attribute \src "libresoc.v:142071.19-142071.121"
- wire width 2 $and$libresoc.v:142071$6599_Y
- attribute \src "libresoc.v:142072.19-142072.127"
- wire $and$libresoc.v:142072$6600_Y
- attribute \src "libresoc.v:142073.19-142073.127"
- wire $and$libresoc.v:142073$6601_Y
- attribute \src "libresoc.v:142075.18-142075.98"
- wire $and$libresoc.v:142075$6603_Y
- attribute \src "libresoc.v:142077.18-142077.100"
- wire $and$libresoc.v:142077$6605_Y
- attribute \src "libresoc.v:142078.17-142078.123"
- wire $and$libresoc.v:142078$6606_Y
- attribute \src "libresoc.v:142079.18-142079.138"
- wire width 2 $and$libresoc.v:142079$6607_Y
- attribute \src "libresoc.v:142081.18-142081.119"
- wire width 2 $and$libresoc.v:142081$6609_Y
- attribute \src "libresoc.v:142084.18-142084.116"
- wire $and$libresoc.v:142084$6612_Y
- attribute \src "libresoc.v:142089.18-142089.113"
- wire $and$libresoc.v:142089$6617_Y
- attribute \src "libresoc.v:142090.18-142090.125"
- wire width 2 $and$libresoc.v:142090$6618_Y
- attribute \src "libresoc.v:142092.18-142092.112"
- wire $and$libresoc.v:142092$6620_Y
- attribute \src "libresoc.v:142095.18-142095.130"
- wire $and$libresoc.v:142095$6623_Y
- attribute \src "libresoc.v:142096.18-142096.130"
- wire $and$libresoc.v:142096$6624_Y
- attribute \src "libresoc.v:142097.18-142097.117"
- wire $and$libresoc.v:142097$6625_Y
- attribute \src "libresoc.v:142102.18-142102.134"
- wire $and$libresoc.v:142102$6630_Y
- attribute \src "libresoc.v:142103.18-142103.124"
- wire width 2 $and$libresoc.v:142103$6631_Y
- attribute \src "libresoc.v:142106.18-142106.116"
- wire $and$libresoc.v:142106$6634_Y
- attribute \src "libresoc.v:142107.18-142107.119"
- wire $and$libresoc.v:142107$6635_Y
- attribute \src "libresoc.v:142116.18-142116.138"
- wire $and$libresoc.v:142116$6644_Y
- attribute \src "libresoc.v:142117.18-142117.136"
- wire $and$libresoc.v:142117$6645_Y
- attribute \src "libresoc.v:142118.18-142118.149"
- wire width 3 $and$libresoc.v:142118$6646_Y
- attribute \src "libresoc.v:142091.18-142091.113"
- wire $eq$libresoc.v:142091$6619_Y
- attribute \src "libresoc.v:142093.18-142093.119"
- wire $eq$libresoc.v:142093$6621_Y
- attribute \src "libresoc.v:142066.19-142066.115"
- wire width 3 $not$libresoc.v:142066$6594_Y
- attribute \src "libresoc.v:142074.18-142074.97"
- wire $not$libresoc.v:142074$6602_Y
- attribute \src "libresoc.v:142076.18-142076.99"
- wire $not$libresoc.v:142076$6604_Y
- attribute \src "libresoc.v:142080.18-142080.113"
- wire width 2 $not$libresoc.v:142080$6608_Y
- attribute \src "libresoc.v:142083.18-142083.106"
- wire $not$libresoc.v:142083$6611_Y
- attribute \src "libresoc.v:142088.18-142088.124"
- wire $not$libresoc.v:142088$6616_Y
- attribute \src "libresoc.v:142094.17-142094.113"
- wire width 3 $not$libresoc.v:142094$6622_Y
- attribute \src "libresoc.v:142119.18-142119.133"
- wire $not$libresoc.v:142119$6647_Y
- attribute \src "libresoc.v:142120.18-142120.139"
- wire $not$libresoc.v:142120$6648_Y
- attribute \src "libresoc.v:142087.18-142087.112"
- wire $or$libresoc.v:142087$6615_Y
- attribute \src "libresoc.v:142098.18-142098.122"
- wire $or$libresoc.v:142098$6626_Y
- attribute \src "libresoc.v:142099.18-142099.124"
- wire $or$libresoc.v:142099$6627_Y
- attribute \src "libresoc.v:142100.18-142100.142"
- wire width 2 $or$libresoc.v:142100$6628_Y
- attribute \src "libresoc.v:142101.18-142101.155"
- wire width 3 $or$libresoc.v:142101$6629_Y
- attribute \src "libresoc.v:142104.18-142104.120"
- wire width 2 $or$libresoc.v:142104$6632_Y
- attribute \src "libresoc.v:142105.17-142105.117"
- wire width 3 $or$libresoc.v:142105$6633_Y
- attribute \src "libresoc.v:142111.17-142111.104"
- wire $reduce_and$libresoc.v:142111$6639_Y
- attribute \src "libresoc.v:142082.18-142082.106"
- wire $reduce_or$libresoc.v:142082$6610_Y
- attribute \src "libresoc.v:142085.18-142085.113"
- wire $reduce_or$libresoc.v:142085$6613_Y
- attribute \src "libresoc.v:142086.18-142086.112"
- wire $reduce_or$libresoc.v:142086$6614_Y
- attribute \src "libresoc.v:142108.18-142108.162"
- wire $ternary$libresoc.v:142108$6636_Y
- attribute \src "libresoc.v:142109.18-142109.163"
- wire width 64 $ternary$libresoc.v:142109$6637_Y
- attribute \src "libresoc.v:142110.18-142110.168"
- wire $ternary$libresoc.v:142110$6638_Y
- attribute \src "libresoc.v:142112.18-142112.188"
- wire width 64 $ternary$libresoc.v:142112$6640_Y
- attribute \src "libresoc.v:142113.18-142113.115"
- wire width 64 $ternary$libresoc.v:142113$6641_Y
- attribute \src "libresoc.v:142114.18-142114.125"
- wire width 64 $ternary$libresoc.v:142114$6642_Y
- attribute \src "libresoc.v:142115.18-142115.118"
- wire $ternary$libresoc.v:142115$6643_Y
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687
+ attribute \src "libresoc.v:140512.3-140550.6"
+ wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire width 64 $2\data_r0__o$next[63:0]$6694
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire $2\data_r0__o_ok$next[0:0]$6695
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$6702
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$6703
+ attribute \src "libresoc.v:140551.3-140572.6"
+ wire $3\data_r0__o_ok$next[0:0]$6696
+ attribute \src "libresoc.v:140573.3-140594.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$6704
+ attribute \src "libresoc.v:140194.17-140194.109"
+ wire $and$libresoc.v:140194$6518_Y
+ attribute \src "libresoc.v:140195.18-140195.130"
+ wire width 3 $and$libresoc.v:140195$6519_Y
+ attribute \src "libresoc.v:140197.19-140197.114"
+ wire width 3 $and$libresoc.v:140197$6521_Y
+ attribute \src "libresoc.v:140198.19-140198.125"
+ wire $and$libresoc.v:140198$6522_Y
+ attribute \src "libresoc.v:140199.19-140199.125"
+ wire $and$libresoc.v:140199$6523_Y
+ attribute \src "libresoc.v:140200.19-140200.133"
+ wire width 2 $and$libresoc.v:140200$6524_Y
+ attribute \src "libresoc.v:140201.19-140201.121"
+ wire width 2 $and$libresoc.v:140201$6525_Y
+ attribute \src "libresoc.v:140202.19-140202.127"
+ wire $and$libresoc.v:140202$6526_Y
+ attribute \src "libresoc.v:140203.19-140203.127"
+ wire $and$libresoc.v:140203$6527_Y
+ attribute \src "libresoc.v:140205.18-140205.98"
+ wire $and$libresoc.v:140205$6529_Y
+ attribute \src "libresoc.v:140207.18-140207.100"
+ wire $and$libresoc.v:140207$6531_Y
+ attribute \src "libresoc.v:140208.17-140208.123"
+ wire $and$libresoc.v:140208$6532_Y
+ attribute \src "libresoc.v:140209.18-140209.138"
+ wire width 2 $and$libresoc.v:140209$6533_Y
+ attribute \src "libresoc.v:140211.18-140211.119"
+ wire width 2 $and$libresoc.v:140211$6535_Y
+ attribute \src "libresoc.v:140214.18-140214.116"
+ wire $and$libresoc.v:140214$6538_Y
+ attribute \src "libresoc.v:140219.18-140219.113"
+ wire $and$libresoc.v:140219$6543_Y
+ attribute \src "libresoc.v:140220.18-140220.125"
+ wire width 2 $and$libresoc.v:140220$6544_Y
+ attribute \src "libresoc.v:140222.18-140222.112"
+ wire $and$libresoc.v:140222$6546_Y
+ attribute \src "libresoc.v:140225.18-140225.130"
+ wire $and$libresoc.v:140225$6549_Y
+ attribute \src "libresoc.v:140226.18-140226.130"
+ wire $and$libresoc.v:140226$6550_Y
+ attribute \src "libresoc.v:140227.18-140227.117"
+ wire $and$libresoc.v:140227$6551_Y
+ attribute \src "libresoc.v:140232.18-140232.134"
+ wire $and$libresoc.v:140232$6556_Y
+ attribute \src "libresoc.v:140233.18-140233.124"
+ wire width 2 $and$libresoc.v:140233$6557_Y
+ attribute \src "libresoc.v:140236.18-140236.116"
+ wire $and$libresoc.v:140236$6560_Y
+ attribute \src "libresoc.v:140237.18-140237.119"
+ wire $and$libresoc.v:140237$6561_Y
+ attribute \src "libresoc.v:140246.18-140246.138"
+ wire $and$libresoc.v:140246$6570_Y
+ attribute \src "libresoc.v:140247.18-140247.136"
+ wire $and$libresoc.v:140247$6571_Y
+ attribute \src "libresoc.v:140248.18-140248.149"
+ wire width 3 $and$libresoc.v:140248$6572_Y
+ attribute \src "libresoc.v:140221.18-140221.113"
+ wire $eq$libresoc.v:140221$6545_Y
+ attribute \src "libresoc.v:140223.18-140223.119"
+ wire $eq$libresoc.v:140223$6547_Y
+ attribute \src "libresoc.v:140196.19-140196.115"
+ wire width 3 $not$libresoc.v:140196$6520_Y
+ attribute \src "libresoc.v:140204.18-140204.97"
+ wire $not$libresoc.v:140204$6528_Y
+ attribute \src "libresoc.v:140206.18-140206.99"
+ wire $not$libresoc.v:140206$6530_Y
+ attribute \src "libresoc.v:140210.18-140210.113"
+ wire width 2 $not$libresoc.v:140210$6534_Y
+ attribute \src "libresoc.v:140213.18-140213.106"
+ wire $not$libresoc.v:140213$6537_Y
+ attribute \src "libresoc.v:140218.18-140218.124"
+ wire $not$libresoc.v:140218$6542_Y
+ attribute \src "libresoc.v:140224.17-140224.113"
+ wire width 3 $not$libresoc.v:140224$6548_Y
+ attribute \src "libresoc.v:140249.18-140249.133"
+ wire $not$libresoc.v:140249$6573_Y
+ attribute \src "libresoc.v:140250.18-140250.139"
+ wire $not$libresoc.v:140250$6574_Y
+ attribute \src "libresoc.v:140217.18-140217.112"
+ wire $or$libresoc.v:140217$6541_Y
+ attribute \src "libresoc.v:140228.18-140228.122"
+ wire $or$libresoc.v:140228$6552_Y
+ attribute \src "libresoc.v:140229.18-140229.124"
+ wire $or$libresoc.v:140229$6553_Y
+ attribute \src "libresoc.v:140230.18-140230.142"
+ wire width 2 $or$libresoc.v:140230$6554_Y
+ attribute \src "libresoc.v:140231.18-140231.155"
+ wire width 3 $or$libresoc.v:140231$6555_Y
+ attribute \src "libresoc.v:140234.18-140234.120"
+ wire width 2 $or$libresoc.v:140234$6558_Y
+ attribute \src "libresoc.v:140235.17-140235.117"
+ wire width 3 $or$libresoc.v:140235$6559_Y
+ attribute \src "libresoc.v:140241.17-140241.104"
+ wire $reduce_and$libresoc.v:140241$6565_Y
+ attribute \src "libresoc.v:140212.18-140212.106"
+ wire $reduce_or$libresoc.v:140212$6536_Y
+ attribute \src "libresoc.v:140215.18-140215.113"
+ wire $reduce_or$libresoc.v:140215$6539_Y
+ attribute \src "libresoc.v:140216.18-140216.112"
+ wire $reduce_or$libresoc.v:140216$6540_Y
+ attribute \src "libresoc.v:140238.18-140238.162"
+ wire $ternary$libresoc.v:140238$6562_Y
+ attribute \src "libresoc.v:140239.18-140239.163"
+ wire width 64 $ternary$libresoc.v:140239$6563_Y
+ attribute \src "libresoc.v:140240.18-140240.168"
+ wire $ternary$libresoc.v:140240$6564_Y
+ attribute \src "libresoc.v:140242.18-140242.188"
+ wire width 64 $ternary$libresoc.v:140242$6566_Y
+ attribute \src "libresoc.v:140243.18-140243.115"
+ wire width 64 $ternary$libresoc.v:140243$6567_Y
+ attribute \src "libresoc.v:140244.18-140244.125"
+ wire width 64 $ternary$libresoc.v:140244$6568_Y
+ attribute \src "libresoc.v:140245.18-140245.118"
+ wire $ternary$libresoc.v:140245$6569_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 32 \cr_a_ok
wire width 64 output 31 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 4 output 33 \dest2_o
- attribute \src "libresoc.v:141459.7-141459.15"
+ attribute \src "libresoc.v:139589.7-139589.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:142064$6592
+ cell $and $and$libresoc.v:140194$6518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $and$libresoc.v:142064$6592_Y
+ connect \Y $and$libresoc.v:140194$6518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:142065$6593
+ cell $and $and$libresoc.v:140195$6519
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$93
connect \B { 1'1 \$97 \$95 }
- connect \Y $and$libresoc.v:142065$6593_Y
+ connect \Y $and$libresoc.v:140195$6519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:142067$6595
+ cell $and $and$libresoc.v:140197$6521
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$99
connect \B \$101
- connect \Y $and$libresoc.v:142067$6595_Y
+ connect \Y $and$libresoc.v:140197$6521_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:142068$6596
+ cell $and $and$libresoc.v:140198$6522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142068$6596_Y
+ connect \Y $and$libresoc.v:140198$6522_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:142069$6597
+ cell $and $and$libresoc.v:140199$6523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:142069$6597_Y
+ connect \Y $and$libresoc.v:140199$6523_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:142070$6598
+ cell $and $and$libresoc.v:140200$6524
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \req_l_q_req
connect \B { \$105 \$107 }
- connect \Y $and$libresoc.v:142070$6598_Y
+ connect \Y $and$libresoc.v:140200$6524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:142071$6599
+ cell $and $and$libresoc.v:140201$6525
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$109
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:142071$6599_Y
+ connect \Y $and$libresoc.v:140201$6525_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:142072$6600
+ cell $and $and$libresoc.v:140202$6526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142072$6600_Y
+ connect \Y $and$libresoc.v:140202$6526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:142073$6601
+ cell $and $and$libresoc.v:140203$6527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142073$6601_Y
+ connect \Y $and$libresoc.v:140203$6527_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:142075$6603
+ cell $and $and$libresoc.v:140205$6529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$11
- connect \Y $and$libresoc.v:142075$6603_Y
+ connect \Y $and$libresoc.v:140205$6529_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:142077$6605
+ cell $and $and$libresoc.v:140207$6531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$15
- connect \Y $and$libresoc.v:142077$6605_Y
+ connect \Y $and$libresoc.v:140207$6531_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:142078$6606
+ cell $and $and$libresoc.v:140208$6532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:142078$6606_Y
+ connect \Y $and$libresoc.v:140208$6532_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:142079$6607
+ cell $and $and$libresoc.v:140209$6533
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:142079$6607_Y
+ connect \Y $and$libresoc.v:140209$6533_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:142081$6609
+ cell $and $and$libresoc.v:140211$6535
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__rel_o
connect \B \$23
- connect \Y $and$libresoc.v:142081$6609_Y
+ connect \Y $and$libresoc.v:140211$6535_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:142084$6612
+ cell $and $and$libresoc.v:140214$6538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$21
- connect \Y $and$libresoc.v:142084$6612_Y
+ connect \Y $and$libresoc.v:140214$6538_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:142089$6617
+ cell $and $and$libresoc.v:140219$6543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$37
- connect \Y $and$libresoc.v:142089$6617_Y
+ connect \Y $and$libresoc.v:140219$6543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:142090$6618
+ cell $and $and$libresoc.v:140220$6544
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:142090$6618_Y
+ connect \Y $and$libresoc.v:140220$6544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:142092$6620
+ cell $and $and$libresoc.v:140222$6546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$39
connect \B \$43
- connect \Y $and$libresoc.v:142092$6620_Y
+ connect \Y $and$libresoc.v:140222$6546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:142095$6623
+ cell $and $and$libresoc.v:140225$6549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$47
connect \B \alu_logical0_n_ready_i
- connect \Y $and$libresoc.v:142095$6623_Y
+ connect \Y $and$libresoc.v:140225$6549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:142096$6624
+ cell $and $and$libresoc.v:140226$6550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_logical0_n_valid_o
- connect \Y $and$libresoc.v:142096$6624_Y
+ connect \Y $and$libresoc.v:140226$6550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:142097$6625
+ cell $and $and$libresoc.v:140227$6551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142097$6625_Y
+ connect \Y $and$libresoc.v:140227$6551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:142102$6630
+ cell $and $and$libresoc.v:140232$6556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142102$6630_Y
+ connect \Y $and$libresoc.v:140232$6556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:142103$6631
+ cell $and $and$libresoc.v:140233$6557
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:142103$6631_Y
+ connect \Y $and$libresoc.v:140233$6557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:142106$6634
+ cell $and $and$libresoc.v:140236$6560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142106$6634_Y
+ connect \Y $and$libresoc.v:140236$6560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:142107$6635
+ cell $and $and$libresoc.v:140237$6561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:142107$6635_Y
+ connect \Y $and$libresoc.v:140237$6561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:142116$6644
+ cell $and $and$libresoc.v:140246$6570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:142116$6644_Y
+ connect \Y $and$libresoc.v:140246$6570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:142117$6645
+ cell $and $and$libresoc.v:140247$6571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:142117$6645_Y
+ connect \Y $and$libresoc.v:140247$6571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:142118$6646
+ cell $and $and$libresoc.v:140248$6572
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:142118$6646_Y
+ connect \Y $and$libresoc.v:140248$6572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:142091$6619
+ cell $eq $eq$libresoc.v:140221$6545
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B 1'0
- connect \Y $eq$libresoc.v:142091$6619_Y
+ connect \Y $eq$libresoc.v:140221$6545_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:142093$6621
+ cell $eq $eq$libresoc.v:140223$6547
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:142093$6621_Y
+ connect \Y $eq$libresoc.v:140223$6547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:142066$6594
+ cell $not $not$libresoc.v:140196$6520
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:142066$6594_Y
+ connect \Y $not$libresoc.v:140196$6520_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:142074$6602
+ cell $not $not$libresoc.v:140204$6528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:142074$6602_Y
+ connect \Y $not$libresoc.v:140204$6528_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:142076$6604
+ cell $not $not$libresoc.v:140206$6530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:142076$6604_Y
+ connect \Y $not$libresoc.v:140206$6530_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:142080$6608
+ cell $not $not$libresoc.v:140210$6534
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:142080$6608_Y
+ connect \Y $not$libresoc.v:140210$6534_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:142083$6611
+ cell $not $not$libresoc.v:140213$6537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$22
- connect \Y $not$libresoc.v:142083$6611_Y
+ connect \Y $not$libresoc.v:140213$6537_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:142088$6616
+ cell $not $not$libresoc.v:140218$6542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_ready_i
- connect \Y $not$libresoc.v:142088$6616_Y
+ connect \Y $not$libresoc.v:140218$6542_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:142094$6622
+ cell $not $not$libresoc.v:140224$6548
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:142094$6622_Y
+ connect \Y $not$libresoc.v:140224$6548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:142119$6647
+ cell $not $not$libresoc.v:140249$6573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_logical_op__zero_a
- connect \Y $not$libresoc.v:142119$6647_Y
+ connect \Y $not$libresoc.v:140249$6573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:142120$6648
+ cell $not $not$libresoc.v:140250$6574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_logical0_logical_op__imm_data__ok
- connect \Y $not$libresoc.v:142120$6648_Y
+ connect \Y $not$libresoc.v:140250$6574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:142087$6615
+ cell $or $or$libresoc.v:140217$6541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $or$libresoc.v:142087$6615_Y
+ connect \Y $or$libresoc.v:140217$6541_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:142098$6626
+ cell $or $or$libresoc.v:140228$6552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142098$6626_Y
+ connect \Y $or$libresoc.v:140228$6552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:142099$6627
+ cell $or $or$libresoc.v:140229$6553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:142099$6627_Y
+ connect \Y $or$libresoc.v:140229$6553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:142100$6628
+ cell $or $or$libresoc.v:140230$6554
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:142100$6628_Y
+ connect \Y $or$libresoc.v:140230$6554_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:142101$6629
+ cell $or $or$libresoc.v:140231$6555
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:142101$6629_Y
+ connect \Y $or$libresoc.v:140231$6555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:142104$6632
+ cell $or $or$libresoc.v:140234$6558
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:142104$6632_Y
+ connect \Y $or$libresoc.v:140234$6558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:142105$6633
+ cell $or $or$libresoc.v:140235$6559
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$4
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:142105$6633_Y
+ connect \Y $or$libresoc.v:140235$6559_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:142111$6639
+ cell $reduce_and $reduce_and$libresoc.v:140241$6565
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$6
- connect \Y $reduce_and$libresoc.v:142111$6639_Y
+ connect \Y $reduce_and$libresoc.v:140241$6565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:142082$6610
+ cell $reduce_or $reduce_or$libresoc.v:140212$6536
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \$25
- connect \Y $reduce_or$libresoc.v:142082$6610_Y
+ connect \Y $reduce_or$libresoc.v:140212$6536_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:142085$6613
+ cell $reduce_or $reduce_or$libresoc.v:140215$6539
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:142085$6613_Y
+ connect \Y $reduce_or$libresoc.v:140215$6539_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:142086$6614
+ cell $reduce_or $reduce_or$libresoc.v:140216$6540
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:142086$6614_Y
+ connect \Y $reduce_or$libresoc.v:140216$6540_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:142108$6636
+ cell $mux $ternary$libresoc.v:140238$6562
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \alu_logical0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:142108$6636_Y
+ connect \Y $ternary$libresoc.v:140238$6562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:142109$6637
+ cell $mux $ternary$libresoc.v:140239$6563
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \alu_logical0_logical_op__zero_a
- connect \Y $ternary$libresoc.v:142109$6637_Y
+ connect \Y $ternary$libresoc.v:140239$6563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:142110$6638
+ cell $mux $ternary$libresoc.v:140240$6564
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_logical0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:142110$6638_Y
+ connect \Y $ternary$libresoc.v:140240$6564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:142112$6640
+ cell $mux $ternary$libresoc.v:140242$6566
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_logical0_logical_op__imm_data__data
connect \S \alu_logical0_logical_op__imm_data__ok
- connect \Y $ternary$libresoc.v:142112$6640_Y
+ connect \Y $ternary$libresoc.v:140242$6566_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:142113$6641
+ cell $mux $ternary$libresoc.v:140243$6567
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:142113$6641_Y
+ connect \Y $ternary$libresoc.v:140243$6567_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:142114$6642
+ cell $mux $ternary$libresoc.v:140244$6568
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm$80
connect \S \src_sel$77
- connect \Y $ternary$libresoc.v:142114$6642_Y
+ connect \Y $ternary$libresoc.v:140244$6568_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:142115$6643
+ cell $mux $ternary$libresoc.v:140245$6569
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:142115$6643_Y
+ connect \Y $ternary$libresoc.v:140245$6569_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142201.14-142207.4"
+ attribute \src "libresoc.v:140331.14-140337.4"
cell \alu_l$61 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142208.16-142240.4"
+ attribute \src "libresoc.v:140338.16-140370.4"
cell \alu_logical0 \alu_logical0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so \alu_logical0_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142241.15-142247.4"
+ attribute \src "libresoc.v:140371.15-140377.4"
cell \alui_l$60 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142248.14-142254.4"
+ attribute \src "libresoc.v:140378.14-140384.4"
cell \opc_l$56 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142255.14-142261.4"
+ attribute \src "libresoc.v:140385.14-140391.4"
cell \req_l$57 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142262.14-142268.4"
+ attribute \src "libresoc.v:140392.14-140398.4"
cell \rok_l$59 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142269.14-142274.4"
+ attribute \src "libresoc.v:140399.14-140404.4"
cell \rst_l$58 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:142275.14-142281.4"
+ attribute \src "libresoc.v:140405.14-140411.4"
cell \src_l$55 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:141459.7-141459.20"
- process $proc$libresoc.v:141459$6799
+ attribute \src "libresoc.v:139589.7-139589.20"
+ process $proc$libresoc.v:139589$6725
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:141577.7-141577.24"
- process $proc$libresoc.v:141577$6800
+ attribute \src "libresoc.v:139707.7-139707.24"
+ process $proc$libresoc.v:139707$6726
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:141587.7-141587.26"
- process $proc$libresoc.v:141587$6801
+ attribute \src "libresoc.v:139717.7-139717.26"
+ process $proc$libresoc.v:139717$6727
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:141595.7-141595.25"
- process $proc$libresoc.v:141595$6802
+ attribute \src "libresoc.v:139725.7-139725.25"
+ process $proc$libresoc.v:139725$6728
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:141603.13-141603.53"
- process $proc$libresoc.v:141603$6803
+ attribute \src "libresoc.v:139733.13-139733.53"
+ process $proc$libresoc.v:139733$6729
assign { } { }
assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:141621.14-141621.57"
- process $proc$libresoc.v:141621$6804
+ attribute \src "libresoc.v:139751.14-139751.57"
+ process $proc$libresoc.v:139751$6730
assign { } { }
assign $1\alu_logical0_logical_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:141625.14-141625.76"
- process $proc$libresoc.v:141625$6805
+ attribute \src "libresoc.v:139755.14-139755.76"
+ process $proc$libresoc.v:139755$6731
assign { } { }
assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:141629.7-141629.51"
- process $proc$libresoc.v:141629$6806
+ attribute \src "libresoc.v:139759.7-139759.51"
+ process $proc$libresoc.v:139759$6732
assign { } { }
assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:141637.13-141637.56"
- process $proc$libresoc.v:141637$6807
+ attribute \src "libresoc.v:139767.13-139767.56"
+ process $proc$libresoc.v:139767$6733
assign { } { }
assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:141641.14-141641.51"
- process $proc$libresoc.v:141641$6808
+ attribute \src "libresoc.v:139771.14-139771.51"
+ process $proc$libresoc.v:139771$6734
assign { } { }
assign $1\alu_logical0_logical_op__insn[31:0] 0
sync always
sync init
update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:141719.13-141719.55"
- process $proc$libresoc.v:141719$6809
+ attribute \src "libresoc.v:139849.13-139849.55"
+ process $proc$libresoc.v:139849$6735
assign { } { }
assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:141723.7-141723.48"
- process $proc$libresoc.v:141723$6810
+ attribute \src "libresoc.v:139853.7-139853.48"
+ process $proc$libresoc.v:139853$6736
assign { } { }
assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:141727.7-141727.49"
- process $proc$libresoc.v:141727$6811
+ attribute \src "libresoc.v:139857.7-139857.49"
+ process $proc$libresoc.v:139857$6737
assign { } { }
assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:141731.7-141731.47"
- process $proc$libresoc.v:141731$6812
+ attribute \src "libresoc.v:139861.7-139861.47"
+ process $proc$libresoc.v:139861$6738
assign { } { }
assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:141735.7-141735.48"
- process $proc$libresoc.v:141735$6813
+ attribute \src "libresoc.v:139865.7-139865.48"
+ process $proc$libresoc.v:139865$6739
assign { } { }
assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:141739.7-141739.45"
- process $proc$libresoc.v:141739$6814
+ attribute \src "libresoc.v:139869.7-139869.45"
+ process $proc$libresoc.v:139869$6740
assign { } { }
assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:141743.7-141743.45"
- process $proc$libresoc.v:141743$6815
+ attribute \src "libresoc.v:139873.7-139873.45"
+ process $proc$libresoc.v:139873$6741
assign { } { }
assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:141747.7-141747.51"
- process $proc$libresoc.v:141747$6816
+ attribute \src "libresoc.v:139877.7-139877.51"
+ process $proc$libresoc.v:139877$6742
assign { } { }
assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:141751.7-141751.45"
- process $proc$libresoc.v:141751$6817
+ attribute \src "libresoc.v:139881.7-139881.45"
+ process $proc$libresoc.v:139881$6743
assign { } { }
assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:141755.7-141755.45"
- process $proc$libresoc.v:141755$6818
+ attribute \src "libresoc.v:139885.7-139885.45"
+ process $proc$libresoc.v:139885$6744
assign { } { }
assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:141759.7-141759.48"
- process $proc$libresoc.v:141759$6819
+ attribute \src "libresoc.v:139889.7-139889.48"
+ process $proc$libresoc.v:139889$6745
assign { } { }
assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:141763.7-141763.45"
- process $proc$libresoc.v:141763$6820
+ attribute \src "libresoc.v:139893.7-139893.45"
+ process $proc$libresoc.v:139893$6746
assign { } { }
assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:141789.7-141789.27"
- process $proc$libresoc.v:141789$6821
+ attribute \src "libresoc.v:139919.7-139919.27"
+ process $proc$libresoc.v:139919$6747
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:141823.14-141823.47"
- process $proc$libresoc.v:141823$6822
+ attribute \src "libresoc.v:139953.14-139953.47"
+ process $proc$libresoc.v:139953$6748
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:141827.7-141827.27"
- process $proc$libresoc.v:141827$6823
+ attribute \src "libresoc.v:139957.7-139957.27"
+ process $proc$libresoc.v:139957$6749
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:141831.13-141831.33"
- process $proc$libresoc.v:141831$6824
+ attribute \src "libresoc.v:139961.13-139961.33"
+ process $proc$libresoc.v:139961$6750
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:141835.7-141835.30"
- process $proc$libresoc.v:141835$6825
+ attribute \src "libresoc.v:139965.7-139965.30"
+ process $proc$libresoc.v:139965$6751
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:141849.7-141849.25"
- process $proc$libresoc.v:141849$6826
+ attribute \src "libresoc.v:139979.7-139979.25"
+ process $proc$libresoc.v:139979$6752
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:141853.7-141853.25"
- process $proc$libresoc.v:141853$6827
+ attribute \src "libresoc.v:139983.7-139983.25"
+ process $proc$libresoc.v:139983$6753
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:141985.13-141985.30"
- process $proc$libresoc.v:141985$6828
+ attribute \src "libresoc.v:140115.13-140115.30"
+ process $proc$libresoc.v:140115$6754
assign { } { }
assign $1\prev_wr_go[1:0] 2'00
sync always
sync init
update \prev_wr_go $1\prev_wr_go[1:0]
end
- attribute \src "libresoc.v:141993.13-141993.31"
- process $proc$libresoc.v:141993$6829
+ attribute \src "libresoc.v:140123.13-140123.31"
+ process $proc$libresoc.v:140123$6755
assign { } { }
assign $1\req_l_r_req[1:0] 2'11
sync always
sync init
update \req_l_r_req $1\req_l_r_req[1:0]
end
- attribute \src "libresoc.v:141997.13-141997.31"
- process $proc$libresoc.v:141997$6830
+ attribute \src "libresoc.v:140127.13-140127.31"
+ process $proc$libresoc.v:140127$6756
assign { } { }
assign $1\req_l_s_req[1:0] 2'00
sync always
sync init
update \req_l_s_req $1\req_l_s_req[1:0]
end
- attribute \src "libresoc.v:142009.7-142009.26"
- process $proc$libresoc.v:142009$6831
+ attribute \src "libresoc.v:140139.7-140139.26"
+ process $proc$libresoc.v:140139$6757
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:142013.7-142013.26"
- process $proc$libresoc.v:142013$6832
+ attribute \src "libresoc.v:140143.7-140143.26"
+ process $proc$libresoc.v:140143$6758
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:142017.7-142017.25"
- process $proc$libresoc.v:142017$6833
+ attribute \src "libresoc.v:140147.7-140147.25"
+ process $proc$libresoc.v:140147$6759
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:142021.7-142021.25"
- process $proc$libresoc.v:142021$6834
+ attribute \src "libresoc.v:140151.7-140151.25"
+ process $proc$libresoc.v:140151$6760
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:142035.13-142035.31"
- process $proc$libresoc.v:142035$6835
+ attribute \src "libresoc.v:140165.13-140165.31"
+ process $proc$libresoc.v:140165$6761
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:142039.13-142039.31"
- process $proc$libresoc.v:142039$6836
+ attribute \src "libresoc.v:140169.13-140169.31"
+ process $proc$libresoc.v:140169$6762
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:142047.14-142047.43"
- process $proc$libresoc.v:142047$6837
+ attribute \src "libresoc.v:140177.14-140177.43"
+ process $proc$libresoc.v:140177$6763
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:142051.14-142051.43"
- process $proc$libresoc.v:142051$6838
+ attribute \src "libresoc.v:140181.14-140181.43"
+ process $proc$libresoc.v:140181$6764
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:142055.7-142055.20"
- process $proc$libresoc.v:142055$6839
+ attribute \src "libresoc.v:140185.7-140185.20"
+ process $proc$libresoc.v:140185$6765
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:142121.3-142122.39"
- process $proc$libresoc.v:142121$6649
+ attribute \src "libresoc.v:140251.3-140252.39"
+ process $proc$libresoc.v:140251$6575
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:142123.3-142124.43"
- process $proc$libresoc.v:142123$6650
+ attribute \src "libresoc.v:140253.3-140254.43"
+ process $proc$libresoc.v:140253$6576
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:142125.3-142126.29"
- process $proc$libresoc.v:142125$6651
+ attribute \src "libresoc.v:140255.3-140256.29"
+ process $proc$libresoc.v:140255$6577
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:142127.3-142128.29"
- process $proc$libresoc.v:142127$6652
+ attribute \src "libresoc.v:140257.3-140258.29"
+ process $proc$libresoc.v:140257$6578
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:142129.3-142130.29"
- process $proc$libresoc.v:142129$6653
+ attribute \src "libresoc.v:140259.3-140260.29"
+ process $proc$libresoc.v:140259$6579
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:142131.3-142132.43"
- process $proc$libresoc.v:142131$6654
+ attribute \src "libresoc.v:140261.3-140262.43"
+ process $proc$libresoc.v:140261$6580
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:142133.3-142134.49"
- process $proc$libresoc.v:142133$6655
+ attribute \src "libresoc.v:140263.3-140264.49"
+ process $proc$libresoc.v:140263$6581
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:142135.3-142136.37"
- process $proc$libresoc.v:142135$6656
+ attribute \src "libresoc.v:140265.3-140266.37"
+ process $proc$libresoc.v:140265$6582
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:142137.3-142138.43"
- process $proc$libresoc.v:142137$6657
+ attribute \src "libresoc.v:140267.3-140268.43"
+ process $proc$libresoc.v:140267$6583
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:142139.3-142140.85"
- process $proc$libresoc.v:142139$6658
+ attribute \src "libresoc.v:140269.3-140270.85"
+ process $proc$libresoc.v:140269$6584
assign { } { }
assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:142141.3-142142.81"
- process $proc$libresoc.v:142141$6659
+ attribute \src "libresoc.v:140271.3-140272.81"
+ process $proc$libresoc.v:140271$6585
assign { } { }
assign $0\alu_logical0_logical_op__fn_unit[12:0] \alu_logical0_logical_op__fn_unit$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:142143.3-142144.95"
- process $proc$libresoc.v:142143$6660
+ attribute \src "libresoc.v:140273.3-140274.95"
+ process $proc$libresoc.v:140273$6586
assign { } { }
assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:142145.3-142146.91"
- process $proc$libresoc.v:142145$6661
+ attribute \src "libresoc.v:140275.3-140276.91"
+ process $proc$libresoc.v:140275$6587
assign { } { }
assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:142147.3-142148.79"
- process $proc$libresoc.v:142147$6662
+ attribute \src "libresoc.v:140277.3-140278.79"
+ process $proc$libresoc.v:140277$6588
assign { } { }
assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:142149.3-142150.79"
- process $proc$libresoc.v:142149$6663
+ attribute \src "libresoc.v:140279.3-140280.79"
+ process $proc$libresoc.v:140279$6589
assign { } { }
assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:142151.3-142152.79"
- process $proc$libresoc.v:142151$6664
+ attribute \src "libresoc.v:140281.3-140282.79"
+ process $proc$libresoc.v:140281$6590
assign { } { }
assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:142153.3-142154.79"
- process $proc$libresoc.v:142153$6665
+ attribute \src "libresoc.v:140283.3-140284.79"
+ process $proc$libresoc.v:140283$6591
assign { } { }
assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:142155.3-142156.85"
- process $proc$libresoc.v:142155$6666
+ attribute \src "libresoc.v:140285.3-140286.85"
+ process $proc$libresoc.v:140285$6592
assign { } { }
assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:142157.3-142158.79"
- process $proc$libresoc.v:142157$6667
+ attribute \src "libresoc.v:140287.3-140288.79"
+ process $proc$libresoc.v:140287$6593
assign { } { }
assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:142159.3-142160.89"
- process $proc$libresoc.v:142159$6668
+ attribute \src "libresoc.v:140289.3-140290.89"
+ process $proc$libresoc.v:140289$6594
assign { } { }
assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:142161.3-142162.87"
- process $proc$libresoc.v:142161$6669
+ attribute \src "libresoc.v:140291.3-140292.87"
+ process $proc$libresoc.v:140291$6595
assign { } { }
assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:142163.3-142164.85"
- process $proc$libresoc.v:142163$6670
+ attribute \src "libresoc.v:140293.3-140294.85"
+ process $proc$libresoc.v:140293$6596
assign { } { }
assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:142165.3-142166.91"
- process $proc$libresoc.v:142165$6671
+ attribute \src "libresoc.v:140295.3-140296.91"
+ process $proc$libresoc.v:140295$6597
assign { } { }
assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:142167.3-142168.83"
- process $proc$libresoc.v:142167$6672
+ attribute \src "libresoc.v:140297.3-140298.83"
+ process $proc$libresoc.v:140297$6598
assign { } { }
assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:142169.3-142170.85"
- process $proc$libresoc.v:142169$6673
+ attribute \src "libresoc.v:140299.3-140300.85"
+ process $proc$libresoc.v:140299$6599
assign { } { }
assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:142171.3-142172.83"
- process $proc$libresoc.v:142171$6674
+ attribute \src "libresoc.v:140301.3-140302.83"
+ process $proc$libresoc.v:140301$6600
assign { } { }
assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:142173.3-142174.75"
- process $proc$libresoc.v:142173$6675
+ attribute \src "libresoc.v:140303.3-140304.75"
+ process $proc$libresoc.v:140303$6601
assign { } { }
assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next
sync posedge \coresync_clk
update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0]
end
- attribute \src "libresoc.v:142175.3-142176.39"
- process $proc$libresoc.v:142175$6676
+ attribute \src "libresoc.v:140305.3-140306.39"
+ process $proc$libresoc.v:140305$6602
assign { } { }
assign $0\req_l_r_req[1:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[1:0]
end
- attribute \src "libresoc.v:142177.3-142178.39"
- process $proc$libresoc.v:142177$6677
+ attribute \src "libresoc.v:140307.3-140308.39"
+ process $proc$libresoc.v:140307$6603
assign { } { }
assign $0\req_l_s_req[1:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[1:0]
end
- attribute \src "libresoc.v:142179.3-142180.39"
- process $proc$libresoc.v:142179$6678
+ attribute \src "libresoc.v:140309.3-140310.39"
+ process $proc$libresoc.v:140309$6604
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:142181.3-142182.39"
- process $proc$libresoc.v:142181$6679
+ attribute \src "libresoc.v:140311.3-140312.39"
+ process $proc$libresoc.v:140311$6605
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:142183.3-142184.39"
- process $proc$libresoc.v:142183$6680
+ attribute \src "libresoc.v:140313.3-140314.39"
+ process $proc$libresoc.v:140313$6606
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:142185.3-142186.39"
- process $proc$libresoc.v:142185$6681
+ attribute \src "libresoc.v:140315.3-140316.39"
+ process $proc$libresoc.v:140315$6607
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:142187.3-142188.39"
- process $proc$libresoc.v:142187$6682
+ attribute \src "libresoc.v:140317.3-140318.39"
+ process $proc$libresoc.v:140317$6608
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:142189.3-142190.39"
- process $proc$libresoc.v:142189$6683
+ attribute \src "libresoc.v:140319.3-140320.39"
+ process $proc$libresoc.v:140319$6609
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:142191.3-142192.41"
- process $proc$libresoc.v:142191$6684
+ attribute \src "libresoc.v:140321.3-140322.41"
+ process $proc$libresoc.v:140321$6610
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:142193.3-142194.41"
- process $proc$libresoc.v:142193$6685
+ attribute \src "libresoc.v:140323.3-140324.41"
+ process $proc$libresoc.v:140323$6611
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:142195.3-142196.37"
- process $proc$libresoc.v:142195$6686
+ attribute \src "libresoc.v:140325.3-140326.37"
+ process $proc$libresoc.v:140325$6612
assign { } { }
assign $0\prev_wr_go[1:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[1:0]
end
- attribute \src "libresoc.v:142197.3-142198.44"
- process $proc$libresoc.v:142197$6687
+ attribute \src "libresoc.v:140327.3-140328.44"
+ process $proc$libresoc.v:140327$6613
assign { } { }
assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:142199.3-142200.24"
- process $proc$libresoc.v:142199$6688
+ attribute \src "libresoc.v:140329.3-140330.24"
+ process $proc$libresoc.v:140329$6614
assign { } { }
assign $0\all_rd_dly[0:0] \$9
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:142282.3-142291.6"
- process $proc$libresoc.v:142282$6689
+ attribute \src "libresoc.v:140412.3-140421.6"
+ process $proc$libresoc.v:140412$6615
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:142283.5-142283.29"
+ attribute \src "libresoc.v:140413.5-140413.29"
switch \initial
- attribute \src "libresoc.v:142283.9-142283.17"
+ attribute \src "libresoc.v:140413.9-140413.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:142292.3-142300.6"
- process $proc$libresoc.v:142292$6690
+ attribute \src "libresoc.v:140422.3-140430.6"
+ process $proc$libresoc.v:140422$6616
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$6691 $1\rok_l_s_rdok$next[0:0]$6692
- attribute \src "libresoc.v:142293.5-142293.29"
+ assign $0\rok_l_s_rdok$next[0:0]$6617 $1\rok_l_s_rdok$next[0:0]$6618
+ attribute \src "libresoc.v:140423.5-140423.29"
switch \initial
- attribute \src "libresoc.v:142293.9-142293.17"
+ attribute \src "libresoc.v:140423.9-140423.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$6692 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$6618 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$6692 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$6618 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6691
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6617
end
- attribute \src "libresoc.v:142301.3-142309.6"
- process $proc$libresoc.v:142301$6693
+ attribute \src "libresoc.v:140431.3-140439.6"
+ process $proc$libresoc.v:140431$6619
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$6694 $1\rok_l_r_rdok$next[0:0]$6695
- attribute \src "libresoc.v:142302.5-142302.29"
+ assign $0\rok_l_r_rdok$next[0:0]$6620 $1\rok_l_r_rdok$next[0:0]$6621
+ attribute \src "libresoc.v:140432.5-140432.29"
switch \initial
- attribute \src "libresoc.v:142302.9-142302.17"
+ attribute \src "libresoc.v:140432.9-140432.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$6695 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$6621 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$6695 \$63
+ assign $1\rok_l_r_rdok$next[0:0]$6621 \$63
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6694
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6620
end
- attribute \src "libresoc.v:142310.3-142318.6"
- process $proc$libresoc.v:142310$6696
+ attribute \src "libresoc.v:140440.3-140448.6"
+ process $proc$libresoc.v:140440$6622
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$6697 $1\rst_l_s_rst$next[0:0]$6698
- attribute \src "libresoc.v:142311.5-142311.29"
+ assign $0\rst_l_s_rst$next[0:0]$6623 $1\rst_l_s_rst$next[0:0]$6624
+ attribute \src "libresoc.v:140441.5-140441.29"
switch \initial
- attribute \src "libresoc.v:142311.9-142311.17"
+ attribute \src "libresoc.v:140441.9-140441.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$6698 1'0
+ assign $1\rst_l_s_rst$next[0:0]$6624 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$6698 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$6624 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6697
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6623
end
- attribute \src "libresoc.v:142319.3-142327.6"
- process $proc$libresoc.v:142319$6699
+ attribute \src "libresoc.v:140449.3-140457.6"
+ process $proc$libresoc.v:140449$6625
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$6700 $1\rst_l_r_rst$next[0:0]$6701
- attribute \src "libresoc.v:142320.5-142320.29"
+ assign $0\rst_l_r_rst$next[0:0]$6626 $1\rst_l_r_rst$next[0:0]$6627
+ attribute \src "libresoc.v:140450.5-140450.29"
switch \initial
- attribute \src "libresoc.v:142320.9-142320.17"
+ attribute \src "libresoc.v:140450.9-140450.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$6701 1'1
+ assign $1\rst_l_r_rst$next[0:0]$6627 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$6701 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$6627 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6700
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6626
end
- attribute \src "libresoc.v:142328.3-142336.6"
- process $proc$libresoc.v:142328$6702
+ attribute \src "libresoc.v:140458.3-140466.6"
+ process $proc$libresoc.v:140458$6628
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$6703 $1\opc_l_s_opc$next[0:0]$6704
- attribute \src "libresoc.v:142329.5-142329.29"
+ assign $0\opc_l_s_opc$next[0:0]$6629 $1\opc_l_s_opc$next[0:0]$6630
+ attribute \src "libresoc.v:140459.5-140459.29"
switch \initial
- attribute \src "libresoc.v:142329.9-142329.17"
+ attribute \src "libresoc.v:140459.9-140459.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$6704 1'0
+ assign $1\opc_l_s_opc$next[0:0]$6630 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$6704 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$6630 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6703
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6629
end
- attribute \src "libresoc.v:142337.3-142345.6"
- process $proc$libresoc.v:142337$6705
+ attribute \src "libresoc.v:140467.3-140475.6"
+ process $proc$libresoc.v:140467$6631
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$6706 $1\opc_l_r_opc$next[0:0]$6707
- attribute \src "libresoc.v:142338.5-142338.29"
+ assign $0\opc_l_r_opc$next[0:0]$6632 $1\opc_l_r_opc$next[0:0]$6633
+ attribute \src "libresoc.v:140468.5-140468.29"
switch \initial
- attribute \src "libresoc.v:142338.9-142338.17"
+ attribute \src "libresoc.v:140468.9-140468.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$6707 1'1
+ assign $1\opc_l_r_opc$next[0:0]$6633 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$6707 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$6633 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6706
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6632
end
- attribute \src "libresoc.v:142346.3-142354.6"
- process $proc$libresoc.v:142346$6708
+ attribute \src "libresoc.v:140476.3-140484.6"
+ process $proc$libresoc.v:140476$6634
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$6709 $1\src_l_s_src$next[2:0]$6710
- attribute \src "libresoc.v:142347.5-142347.29"
+ assign $0\src_l_s_src$next[2:0]$6635 $1\src_l_s_src$next[2:0]$6636
+ attribute \src "libresoc.v:140477.5-140477.29"
switch \initial
- attribute \src "libresoc.v:142347.9-142347.17"
+ attribute \src "libresoc.v:140477.9-140477.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$6710 3'000
+ assign $1\src_l_s_src$next[2:0]$6636 3'000
case
- assign $1\src_l_s_src$next[2:0]$6710 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$6636 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6709
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6635
end
- attribute \src "libresoc.v:142355.3-142363.6"
- process $proc$libresoc.v:142355$6711
+ attribute \src "libresoc.v:140485.3-140493.6"
+ process $proc$libresoc.v:140485$6637
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$6712 $1\src_l_r_src$next[2:0]$6713
- attribute \src "libresoc.v:142356.5-142356.29"
+ assign $0\src_l_r_src$next[2:0]$6638 $1\src_l_r_src$next[2:0]$6639
+ attribute \src "libresoc.v:140486.5-140486.29"
switch \initial
- attribute \src "libresoc.v:142356.9-142356.17"
+ attribute \src "libresoc.v:140486.9-140486.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$6713 3'111
+ assign $1\src_l_r_src$next[2:0]$6639 3'111
case
- assign $1\src_l_r_src$next[2:0]$6713 \reset_r
+ assign $1\src_l_r_src$next[2:0]$6639 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6712
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6638
end
- attribute \src "libresoc.v:142364.3-142372.6"
- process $proc$libresoc.v:142364$6714
+ attribute \src "libresoc.v:140494.3-140502.6"
+ process $proc$libresoc.v:140494$6640
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[1:0]$6715 $1\req_l_s_req$next[1:0]$6716
- attribute \src "libresoc.v:142365.5-142365.29"
+ assign $0\req_l_s_req$next[1:0]$6641 $1\req_l_s_req$next[1:0]$6642
+ attribute \src "libresoc.v:140495.5-140495.29"
switch \initial
- attribute \src "libresoc.v:142365.9-142365.17"
+ attribute \src "libresoc.v:140495.9-140495.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[1:0]$6716 2'00
+ assign $1\req_l_s_req$next[1:0]$6642 2'00
case
- assign $1\req_l_s_req$next[1:0]$6716 \$65
+ assign $1\req_l_s_req$next[1:0]$6642 \$65
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6715
+ update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6641
end
- attribute \src "libresoc.v:142373.3-142381.6"
- process $proc$libresoc.v:142373$6717
+ attribute \src "libresoc.v:140503.3-140511.6"
+ process $proc$libresoc.v:140503$6643
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[1:0]$6718 $1\req_l_r_req$next[1:0]$6719
- attribute \src "libresoc.v:142374.5-142374.29"
+ assign $0\req_l_r_req$next[1:0]$6644 $1\req_l_r_req$next[1:0]$6645
+ attribute \src "libresoc.v:140504.5-140504.29"
switch \initial
- attribute \src "libresoc.v:142374.9-142374.17"
+ attribute \src "libresoc.v:140504.9-140504.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[1:0]$6719 2'11
+ assign $1\req_l_r_req$next[1:0]$6645 2'11
case
- assign $1\req_l_r_req$next[1:0]$6719 \$67
+ assign $1\req_l_r_req$next[1:0]$6645 \$67
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6718
+ update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6644
end
- attribute \src "libresoc.v:142382.3-142420.6"
- process $proc$libresoc.v:142382$6720
+ attribute \src "libresoc.v:140512.3-140550.6"
+ process $proc$libresoc.v:140512$6646
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__data_len$next[3:0]$6721 $1\alu_logical0_logical_op__data_len$next[3:0]$6739
- assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740
+ assign $0\alu_logical0_logical_op__data_len$next[3:0]$6647 $1\alu_logical0_logical_op__data_len$next[3:0]$6665
+ assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6725 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743
- assign $0\alu_logical0_logical_op__insn$next[31:0]$6726 $1\alu_logical0_logical_op__insn$next[31:0]$6744
- assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6727 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745
- assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6728 $1\alu_logical0_logical_op__invert_in$next[0:0]$6746
- assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6729 $1\alu_logical0_logical_op__invert_out$next[0:0]$6747
- assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748
- assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6731 $1\alu_logical0_logical_op__is_signed$next[0:0]$6749
+ assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6651 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669
+ assign $0\alu_logical0_logical_op__insn$next[31:0]$6652 $1\alu_logical0_logical_op__insn$next[31:0]$6670
+ assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6653 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671
+ assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6654 $1\alu_logical0_logical_op__invert_in$next[0:0]$6672
+ assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6655 $1\alu_logical0_logical_op__invert_out$next[0:0]$6673
+ assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674
+ assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6657 $1\alu_logical0_logical_op__is_signed$next[0:0]$6675
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6734 $1\alu_logical0_logical_op__output_carry$next[0:0]$6752
+ assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6660 $1\alu_logical0_logical_op__output_carry$next[0:0]$6678
assign { } { }
assign { } { }
- assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755
- assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6738 $1\alu_logical0_logical_op__zero_a$next[0:0]$6756
- assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757
- assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758
- assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759
- assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760
- assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761
- assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762
- attribute \src "libresoc.v:142383.5-142383.29"
+ assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681
+ assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6664 $1\alu_logical0_logical_op__zero_a$next[0:0]$6682
+ assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683
+ assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684
+ assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685
+ assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686
+ assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687
+ assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688
+ attribute \src "libresoc.v:140513.5-140513.29"
switch \initial
- attribute \src "libresoc.v:142383.9-142383.17"
+ attribute \src "libresoc.v:140513.9-140513.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_logical0_logical_op__insn$next[31:0]$6744 $1\alu_logical0_logical_op__data_len$next[3:0]$6739 $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 $1\alu_logical0_logical_op__output_carry$next[0:0]$6752 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755 $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 $1\alu_logical0_logical_op__zero_a$next[0:0]$6756 $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
+ assign { $1\alu_logical0_logical_op__insn$next[31:0]$6670 $1\alu_logical0_logical_op__data_len$next[3:0]$6665 $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
case
- assign $1\alu_logical0_logical_op__data_len$next[3:0]$6739 \alu_logical0_logical_op__data_len
- assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 \alu_logical0_logical_op__fn_unit
- assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 \alu_logical0_logical_op__imm_data__data
- assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 \alu_logical0_logical_op__imm_data__ok
- assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 \alu_logical0_logical_op__input_carry
- assign $1\alu_logical0_logical_op__insn$next[31:0]$6744 \alu_logical0_logical_op__insn
- assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 \alu_logical0_logical_op__insn_type
- assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 \alu_logical0_logical_op__invert_in
- assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 \alu_logical0_logical_op__invert_out
- assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 \alu_logical0_logical_op__is_32bit
- assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 \alu_logical0_logical_op__is_signed
- assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 \alu_logical0_logical_op__oe__oe
- assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751 \alu_logical0_logical_op__oe__ok
- assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6752 \alu_logical0_logical_op__output_carry
- assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753 \alu_logical0_logical_op__rc__ok
- assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754 \alu_logical0_logical_op__rc__rc
- assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755 \alu_logical0_logical_op__write_cr0
- assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6756 \alu_logical0_logical_op__zero_a
+ assign $1\alu_logical0_logical_op__data_len$next[3:0]$6665 \alu_logical0_logical_op__data_len
+ assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 \alu_logical0_logical_op__fn_unit
+ assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 \alu_logical0_logical_op__imm_data__data
+ assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 \alu_logical0_logical_op__imm_data__ok
+ assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 \alu_logical0_logical_op__input_carry
+ assign $1\alu_logical0_logical_op__insn$next[31:0]$6670 \alu_logical0_logical_op__insn
+ assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 \alu_logical0_logical_op__insn_type
+ assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 \alu_logical0_logical_op__invert_in
+ assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 \alu_logical0_logical_op__invert_out
+ assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 \alu_logical0_logical_op__is_32bit
+ assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 \alu_logical0_logical_op__is_signed
+ assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 \alu_logical0_logical_op__oe__oe
+ assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 \alu_logical0_logical_op__oe__ok
+ assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 \alu_logical0_logical_op__output_carry
+ assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 \alu_logical0_logical_op__rc__ok
+ assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 \alu_logical0_logical_op__rc__rc
+ assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 \alu_logical0_logical_op__write_cr0
+ assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 \alu_logical0_logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758 1'0
- assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762 1'0
- assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761 1'0
- assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759 1'0
- assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760 1'0
+ assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 1'0
+ assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 1'0
+ assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 1'0
+ assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 1'0
+ assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 1'0
case
- assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741
- assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742
- assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750
- assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751
- assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753
- assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754
+ assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667
+ assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668
+ assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676
+ assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677
+ assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679
+ assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680
end
sync always
- update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6721
- update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722
- update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723
- update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724
- update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6725
- update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6726
- update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6727
- update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6728
- update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6729
- update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730
- update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6731
- update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732
- update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733
- update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6734
- update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735
- update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736
- update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737
- update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6738
+ update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6647
+ update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648
+ update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649
+ update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650
+ update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6651
+ update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6652
+ update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6653
+ update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6654
+ update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6655
+ update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656
+ update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6657
+ update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658
+ update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659
+ update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6660
+ update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661
+ update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662
+ update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663
+ update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6664
end
- attribute \src "libresoc.v:142421.3-142442.6"
- process $proc$libresoc.v:142421$6763
+ attribute \src "libresoc.v:140551.3-140572.6"
+ process $proc$libresoc.v:140551$6689
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$6764 $2\data_r0__o$next[63:0]$6768
+ assign $0\data_r0__o$next[63:0]$6690 $2\data_r0__o$next[63:0]$6694
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$6765 $3\data_r0__o_ok$next[0:0]$6770
- attribute \src "libresoc.v:142422.5-142422.29"
+ assign $0\data_r0__o_ok$next[0:0]$6691 $3\data_r0__o_ok$next[0:0]$6696
+ attribute \src "libresoc.v:140552.5-140552.29"
switch \initial
- attribute \src "libresoc.v:142422.9-142422.17"
+ attribute \src "libresoc.v:140552.9-140552.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$6767 $1\data_r0__o$next[63:0]$6766 } { \o_ok \alu_logical0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$6693 $1\data_r0__o$next[63:0]$6692 } { \o_ok \alu_logical0_o }
case
- assign $1\data_r0__o$next[63:0]$6766 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$6767 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$6692 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$6693 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$6769 $2\data_r0__o$next[63:0]$6768 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$6695 $2\data_r0__o$next[63:0]$6694 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$6768 $1\data_r0__o$next[63:0]$6766
- assign $2\data_r0__o_ok$next[0:0]$6769 $1\data_r0__o_ok$next[0:0]$6767
+ assign $2\data_r0__o$next[63:0]$6694 $1\data_r0__o$next[63:0]$6692
+ assign $2\data_r0__o_ok$next[0:0]$6695 $1\data_r0__o_ok$next[0:0]$6693
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$6770 1'0
+ assign $3\data_r0__o_ok$next[0:0]$6696 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$6770 $2\data_r0__o_ok$next[0:0]$6769
+ assign $3\data_r0__o_ok$next[0:0]$6696 $2\data_r0__o_ok$next[0:0]$6695
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$6764
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6765
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$6690
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6691
end
- attribute \src "libresoc.v:142443.3-142464.6"
- process $proc$libresoc.v:142443$6771
+ attribute \src "libresoc.v:140573.3-140594.6"
+ process $proc$libresoc.v:140573$6697
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$6772 $2\data_r1__cr_a$next[3:0]$6776
+ assign $0\data_r1__cr_a$next[3:0]$6698 $2\data_r1__cr_a$next[3:0]$6702
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$6773 $3\data_r1__cr_a_ok$next[0:0]$6778
- attribute \src "libresoc.v:142444.5-142444.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$6699 $3\data_r1__cr_a_ok$next[0:0]$6704
+ attribute \src "libresoc.v:140574.5-140574.29"
switch \initial
- attribute \src "libresoc.v:142444.9-142444.17"
+ attribute \src "libresoc.v:140574.9-140574.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$6775 $1\data_r1__cr_a$next[3:0]$6774 } { \cr_a_ok \alu_logical0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$6701 $1\data_r1__cr_a$next[3:0]$6700 } { \cr_a_ok \alu_logical0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$6774 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$6775 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$6700 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$6701 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$6777 $2\data_r1__cr_a$next[3:0]$6776 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$6703 $2\data_r1__cr_a$next[3:0]$6702 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$6776 $1\data_r1__cr_a$next[3:0]$6774
- assign $2\data_r1__cr_a_ok$next[0:0]$6777 $1\data_r1__cr_a_ok$next[0:0]$6775
+ assign $2\data_r1__cr_a$next[3:0]$6702 $1\data_r1__cr_a$next[3:0]$6700
+ assign $2\data_r1__cr_a_ok$next[0:0]$6703 $1\data_r1__cr_a_ok$next[0:0]$6701
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$6778 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$6704 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$6778 $2\data_r1__cr_a_ok$next[0:0]$6777
+ assign $3\data_r1__cr_a_ok$next[0:0]$6704 $2\data_r1__cr_a_ok$next[0:0]$6703
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6772
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6773
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6698
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6699
end
- attribute \src "libresoc.v:142465.3-142474.6"
- process $proc$libresoc.v:142465$6779
+ attribute \src "libresoc.v:140595.3-140604.6"
+ process $proc$libresoc.v:140595$6705
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$6780 $1\src_r0$next[63:0]$6781
- attribute \src "libresoc.v:142466.5-142466.29"
+ assign $0\src_r0$next[63:0]$6706 $1\src_r0$next[63:0]$6707
+ attribute \src "libresoc.v:140596.5-140596.29"
switch \initial
- attribute \src "libresoc.v:142466.9-142466.17"
+ attribute \src "libresoc.v:140596.9-140596.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$6781 \src_or_imm
+ assign $1\src_r0$next[63:0]$6707 \src_or_imm
case
- assign $1\src_r0$next[63:0]$6781 \src_r0
+ assign $1\src_r0$next[63:0]$6707 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$6780
+ update \src_r0$next $0\src_r0$next[63:0]$6706
end
- attribute \src "libresoc.v:142475.3-142484.6"
- process $proc$libresoc.v:142475$6782
+ attribute \src "libresoc.v:140605.3-140614.6"
+ process $proc$libresoc.v:140605$6708
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$6783 $1\src_r1$next[63:0]$6784
- attribute \src "libresoc.v:142476.5-142476.29"
+ assign $0\src_r1$next[63:0]$6709 $1\src_r1$next[63:0]$6710
+ attribute \src "libresoc.v:140606.5-140606.29"
switch \initial
- attribute \src "libresoc.v:142476.9-142476.17"
+ attribute \src "libresoc.v:140606.9-140606.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$6784 \src_or_imm$80
+ assign $1\src_r1$next[63:0]$6710 \src_or_imm$80
case
- assign $1\src_r1$next[63:0]$6784 \src_r1
+ assign $1\src_r1$next[63:0]$6710 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$6783
+ update \src_r1$next $0\src_r1$next[63:0]$6709
end
- attribute \src "libresoc.v:142485.3-142494.6"
- process $proc$libresoc.v:142485$6785
+ attribute \src "libresoc.v:140615.3-140624.6"
+ process $proc$libresoc.v:140615$6711
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$6786 $1\src_r2$next[0:0]$6787
- attribute \src "libresoc.v:142486.5-142486.29"
+ assign $0\src_r2$next[0:0]$6712 $1\src_r2$next[0:0]$6713
+ attribute \src "libresoc.v:140616.5-140616.29"
switch \initial
- attribute \src "libresoc.v:142486.9-142486.17"
+ attribute \src "libresoc.v:140616.9-140616.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$6787 \src3_i
+ assign $1\src_r2$next[0:0]$6713 \src3_i
case
- assign $1\src_r2$next[0:0]$6787 \src_r2
+ assign $1\src_r2$next[0:0]$6713 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$6786
+ update \src_r2$next $0\src_r2$next[0:0]$6712
end
- attribute \src "libresoc.v:142495.3-142503.6"
- process $proc$libresoc.v:142495$6788
+ attribute \src "libresoc.v:140625.3-140633.6"
+ process $proc$libresoc.v:140625$6714
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$6789 $1\alui_l_r_alui$next[0:0]$6790
- attribute \src "libresoc.v:142496.5-142496.29"
+ assign $0\alui_l_r_alui$next[0:0]$6715 $1\alui_l_r_alui$next[0:0]$6716
+ attribute \src "libresoc.v:140626.5-140626.29"
switch \initial
- attribute \src "libresoc.v:142496.9-142496.17"
+ attribute \src "libresoc.v:140626.9-140626.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$6790 1'1
+ assign $1\alui_l_r_alui$next[0:0]$6716 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$6790 \$89
+ assign $1\alui_l_r_alui$next[0:0]$6716 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6789
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6715
end
- attribute \src "libresoc.v:142504.3-142512.6"
- process $proc$libresoc.v:142504$6791
+ attribute \src "libresoc.v:140634.3-140642.6"
+ process $proc$libresoc.v:140634$6717
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$6792 $1\alu_l_r_alu$next[0:0]$6793
- attribute \src "libresoc.v:142505.5-142505.29"
+ assign $0\alu_l_r_alu$next[0:0]$6718 $1\alu_l_r_alu$next[0:0]$6719
+ attribute \src "libresoc.v:140635.5-140635.29"
switch \initial
- attribute \src "libresoc.v:142505.9-142505.17"
+ attribute \src "libresoc.v:140635.9-140635.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$6793 1'1
+ assign $1\alu_l_r_alu$next[0:0]$6719 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$6793 \$91
+ assign $1\alu_l_r_alu$next[0:0]$6719 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6792
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6718
end
- attribute \src "libresoc.v:142513.3-142522.6"
- process $proc$libresoc.v:142513$6794
+ attribute \src "libresoc.v:140643.3-140652.6"
+ process $proc$libresoc.v:140643$6720
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:142514.5-142514.29"
+ attribute \src "libresoc.v:140644.5-140644.29"
switch \initial
- attribute \src "libresoc.v:142514.9-142514.17"
+ attribute \src "libresoc.v:140644.9-140644.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:142523.3-142532.6"
- process $proc$libresoc.v:142523$6795
+ attribute \src "libresoc.v:140653.3-140662.6"
+ process $proc$libresoc.v:140653$6721
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:142524.5-142524.29"
+ attribute \src "libresoc.v:140654.5-140654.29"
switch \initial
- attribute \src "libresoc.v:142524.9-142524.17"
+ attribute \src "libresoc.v:140654.9-140654.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:142533.3-142541.6"
- process $proc$libresoc.v:142533$6796
+ attribute \src "libresoc.v:140663.3-140671.6"
+ process $proc$libresoc.v:140663$6722
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[1:0]$6797 $1\prev_wr_go$next[1:0]$6798
- attribute \src "libresoc.v:142534.5-142534.29"
+ assign $0\prev_wr_go$next[1:0]$6723 $1\prev_wr_go$next[1:0]$6724
+ attribute \src "libresoc.v:140664.5-140664.29"
switch \initial
- attribute \src "libresoc.v:142534.9-142534.17"
+ attribute \src "libresoc.v:140664.9-140664.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[1:0]$6798 2'00
- case
- assign $1\prev_wr_go$next[1:0]$6798 \$19
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6797
- end
- connect \$9 $and$libresoc.v:142064$6592_Y
- connect \$99 $and$libresoc.v:142065$6593_Y
- connect \$101 $not$libresoc.v:142066$6594_Y
- connect \$103 $and$libresoc.v:142067$6595_Y
- connect \$105 $and$libresoc.v:142068$6596_Y
- connect \$107 $and$libresoc.v:142069$6597_Y
- connect \$109 $and$libresoc.v:142070$6598_Y
- connect \$111 $and$libresoc.v:142071$6599_Y
- connect \$113 $and$libresoc.v:142072$6600_Y
- connect \$115 $and$libresoc.v:142073$6601_Y
- connect \$11 $not$libresoc.v:142074$6602_Y
- connect \$13 $and$libresoc.v:142075$6603_Y
- connect \$15 $not$libresoc.v:142076$6604_Y
- connect \$17 $and$libresoc.v:142077$6605_Y
- connect \$1 $and$libresoc.v:142078$6606_Y
- connect \$19 $and$libresoc.v:142079$6607_Y
- connect \$23 $not$libresoc.v:142080$6608_Y
- connect \$25 $and$libresoc.v:142081$6609_Y
- connect \$22 $reduce_or$libresoc.v:142082$6610_Y
- connect \$21 $not$libresoc.v:142083$6611_Y
- connect \$29 $and$libresoc.v:142084$6612_Y
- connect \$31 $reduce_or$libresoc.v:142085$6613_Y
- connect \$33 $reduce_or$libresoc.v:142086$6614_Y
- connect \$35 $or$libresoc.v:142087$6615_Y
- connect \$37 $not$libresoc.v:142088$6616_Y
- connect \$39 $and$libresoc.v:142089$6617_Y
- connect \$41 $and$libresoc.v:142090$6618_Y
- connect \$43 $eq$libresoc.v:142091$6619_Y
- connect \$45 $and$libresoc.v:142092$6620_Y
- connect \$47 $eq$libresoc.v:142093$6621_Y
- connect \$4 $not$libresoc.v:142094$6622_Y
- connect \$49 $and$libresoc.v:142095$6623_Y
- connect \$51 $and$libresoc.v:142096$6624_Y
- connect \$53 $and$libresoc.v:142097$6625_Y
- connect \$55 $or$libresoc.v:142098$6626_Y
- connect \$57 $or$libresoc.v:142099$6627_Y
- connect \$59 $or$libresoc.v:142100$6628_Y
- connect \$61 $or$libresoc.v:142101$6629_Y
- connect \$63 $and$libresoc.v:142102$6630_Y
- connect \$65 $and$libresoc.v:142103$6631_Y
- connect \$67 $or$libresoc.v:142104$6632_Y
- connect \$6 $or$libresoc.v:142105$6633_Y
- connect \$69 $and$libresoc.v:142106$6634_Y
- connect \$71 $and$libresoc.v:142107$6635_Y
- connect \$73 $ternary$libresoc.v:142108$6636_Y
- connect \$75 $ternary$libresoc.v:142109$6637_Y
- connect \$78 $ternary$libresoc.v:142110$6638_Y
- connect \$3 $reduce_and$libresoc.v:142111$6639_Y
- connect \$81 $ternary$libresoc.v:142112$6640_Y
- connect \$83 $ternary$libresoc.v:142113$6641_Y
- connect \$85 $ternary$libresoc.v:142114$6642_Y
- connect \$87 $ternary$libresoc.v:142115$6643_Y
- connect \$89 $and$libresoc.v:142116$6644_Y
- connect \$91 $and$libresoc.v:142117$6645_Y
- connect \$93 $and$libresoc.v:142118$6646_Y
- connect \$95 $not$libresoc.v:142119$6647_Y
- connect \$97 $not$libresoc.v:142120$6648_Y
+ assign $1\prev_wr_go$next[1:0]$6724 2'00
+ case
+ assign $1\prev_wr_go$next[1:0]$6724 \$19
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6723
+ end
+ connect \$9 $and$libresoc.v:140194$6518_Y
+ connect \$99 $and$libresoc.v:140195$6519_Y
+ connect \$101 $not$libresoc.v:140196$6520_Y
+ connect \$103 $and$libresoc.v:140197$6521_Y
+ connect \$105 $and$libresoc.v:140198$6522_Y
+ connect \$107 $and$libresoc.v:140199$6523_Y
+ connect \$109 $and$libresoc.v:140200$6524_Y
+ connect \$111 $and$libresoc.v:140201$6525_Y
+ connect \$113 $and$libresoc.v:140202$6526_Y
+ connect \$115 $and$libresoc.v:140203$6527_Y
+ connect \$11 $not$libresoc.v:140204$6528_Y
+ connect \$13 $and$libresoc.v:140205$6529_Y
+ connect \$15 $not$libresoc.v:140206$6530_Y
+ connect \$17 $and$libresoc.v:140207$6531_Y
+ connect \$1 $and$libresoc.v:140208$6532_Y
+ connect \$19 $and$libresoc.v:140209$6533_Y
+ connect \$23 $not$libresoc.v:140210$6534_Y
+ connect \$25 $and$libresoc.v:140211$6535_Y
+ connect \$22 $reduce_or$libresoc.v:140212$6536_Y
+ connect \$21 $not$libresoc.v:140213$6537_Y
+ connect \$29 $and$libresoc.v:140214$6538_Y
+ connect \$31 $reduce_or$libresoc.v:140215$6539_Y
+ connect \$33 $reduce_or$libresoc.v:140216$6540_Y
+ connect \$35 $or$libresoc.v:140217$6541_Y
+ connect \$37 $not$libresoc.v:140218$6542_Y
+ connect \$39 $and$libresoc.v:140219$6543_Y
+ connect \$41 $and$libresoc.v:140220$6544_Y
+ connect \$43 $eq$libresoc.v:140221$6545_Y
+ connect \$45 $and$libresoc.v:140222$6546_Y
+ connect \$47 $eq$libresoc.v:140223$6547_Y
+ connect \$4 $not$libresoc.v:140224$6548_Y
+ connect \$49 $and$libresoc.v:140225$6549_Y
+ connect \$51 $and$libresoc.v:140226$6550_Y
+ connect \$53 $and$libresoc.v:140227$6551_Y
+ connect \$55 $or$libresoc.v:140228$6552_Y
+ connect \$57 $or$libresoc.v:140229$6553_Y
+ connect \$59 $or$libresoc.v:140230$6554_Y
+ connect \$61 $or$libresoc.v:140231$6555_Y
+ connect \$63 $and$libresoc.v:140232$6556_Y
+ connect \$65 $and$libresoc.v:140233$6557_Y
+ connect \$67 $or$libresoc.v:140234$6558_Y
+ connect \$6 $or$libresoc.v:140235$6559_Y
+ connect \$69 $and$libresoc.v:140236$6560_Y
+ connect \$71 $and$libresoc.v:140237$6561_Y
+ connect \$73 $ternary$libresoc.v:140238$6562_Y
+ connect \$75 $ternary$libresoc.v:140239$6563_Y
+ connect \$78 $ternary$libresoc.v:140240$6564_Y
+ connect \$3 $reduce_and$libresoc.v:140241$6565_Y
+ connect \$81 $ternary$libresoc.v:140242$6566_Y
+ connect \$83 $ternary$libresoc.v:140243$6567_Y
+ connect \$85 $ternary$libresoc.v:140244$6568_Y
+ connect \$87 $ternary$libresoc.v:140245$6569_Y
+ connect \$89 $and$libresoc.v:140246$6570_Y
+ connect \$91 $and$libresoc.v:140247$6571_Y
+ connect \$93 $and$libresoc.v:140248$6572_Y
+ connect \$95 $not$libresoc.v:140249$6573_Y
+ connect \$97 $not$libresoc.v:140250$6574_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$111
connect \all_rd_dly$next \all_rd
connect \all_rd \$9
end
-attribute \src "libresoc.v:142578.1-143955.10"
+attribute \src "libresoc.v:140708.1-142085.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1"
attribute \generator "nMigen"
module \logical_pipe1
- attribute \src "libresoc.v:143894.3-143912.6"
- wire width 4 $0\cr_a$next[3:0]$6924
- attribute \src "libresoc.v:143654.3-143655.25"
+ attribute \src "libresoc.v:142024.3-142042.6"
+ wire width 4 $0\cr_a$next[3:0]$6850
+ attribute \src "libresoc.v:141784.3-141785.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:143894.3-143912.6"
- wire $0\cr_a_ok$next[0:0]$6925
- attribute \src "libresoc.v:143656.3-143657.31"
+ attribute \src "libresoc.v:142024.3-142042.6"
+ wire $0\cr_a_ok$next[0:0]$6851
+ attribute \src "libresoc.v:141786.3-141787.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:142579.7-142579.20"
+ attribute \src "libresoc.v:140709.7-140709.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 4 $0\logical_op__data_len$next[3:0]$6875
- attribute \src "libresoc.v:143694.3-143695.57"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 4 $0\logical_op__data_len$next[3:0]$6801
+ attribute \src "libresoc.v:141824.3-141825.57"
wire width 4 $0\logical_op__data_len[3:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 13 $0\logical_op__fn_unit$next[12:0]$6876
- attribute \src "libresoc.v:143664.3-143665.55"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 13 $0\logical_op__fn_unit$next[12:0]$6802
+ attribute \src "libresoc.v:141794.3-141795.55"
wire width 13 $0\logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 64 $0\logical_op__imm_data__data$next[63:0]$6877
- attribute \src "libresoc.v:143666.3-143667.69"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 64 $0\logical_op__imm_data__data$next[63:0]$6803
+ attribute \src "libresoc.v:141796.3-141797.69"
wire width 64 $0\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__imm_data__ok$next[0:0]$6878
- attribute \src "libresoc.v:143668.3-143669.65"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__imm_data__ok$next[0:0]$6804
+ attribute \src "libresoc.v:141798.3-141799.65"
wire $0\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 2 $0\logical_op__input_carry$next[1:0]$6879
- attribute \src "libresoc.v:143682.3-143683.63"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 2 $0\logical_op__input_carry$next[1:0]$6805
+ attribute \src "libresoc.v:141812.3-141813.63"
wire width 2 $0\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 32 $0\logical_op__insn$next[31:0]$6880
- attribute \src "libresoc.v:143696.3-143697.49"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 32 $0\logical_op__insn$next[31:0]$6806
+ attribute \src "libresoc.v:141826.3-141827.49"
wire width 32 $0\logical_op__insn[31:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 7 $0\logical_op__insn_type$next[6:0]$6881
- attribute \src "libresoc.v:143662.3-143663.59"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 7 $0\logical_op__insn_type$next[6:0]$6807
+ attribute \src "libresoc.v:141792.3-141793.59"
wire width 7 $0\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__invert_in$next[0:0]$6882
- attribute \src "libresoc.v:143678.3-143679.59"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__invert_in$next[0:0]$6808
+ attribute \src "libresoc.v:141808.3-141809.59"
wire $0\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__invert_out$next[0:0]$6883
- attribute \src "libresoc.v:143684.3-143685.61"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__invert_out$next[0:0]$6809
+ attribute \src "libresoc.v:141814.3-141815.61"
wire $0\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__is_32bit$next[0:0]$6884
- attribute \src "libresoc.v:143690.3-143691.57"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__is_32bit$next[0:0]$6810
+ attribute \src "libresoc.v:141820.3-141821.57"
wire $0\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__is_signed$next[0:0]$6885
- attribute \src "libresoc.v:143692.3-143693.59"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__is_signed$next[0:0]$6811
+ attribute \src "libresoc.v:141822.3-141823.59"
wire $0\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__oe__oe$next[0:0]$6886
- attribute \src "libresoc.v:143674.3-143675.53"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__oe__oe$next[0:0]$6812
+ attribute \src "libresoc.v:141804.3-141805.53"
wire $0\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__oe__ok$next[0:0]$6887
- attribute \src "libresoc.v:143676.3-143677.53"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__oe__ok$next[0:0]$6813
+ attribute \src "libresoc.v:141806.3-141807.53"
wire $0\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__output_carry$next[0:0]$6888
- attribute \src "libresoc.v:143688.3-143689.65"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__output_carry$next[0:0]$6814
+ attribute \src "libresoc.v:141818.3-141819.65"
wire $0\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__rc__ok$next[0:0]$6889
- attribute \src "libresoc.v:143672.3-143673.53"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__rc__ok$next[0:0]$6815
+ attribute \src "libresoc.v:141802.3-141803.53"
wire $0\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__rc__rc$next[0:0]$6890
- attribute \src "libresoc.v:143670.3-143671.53"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__rc__rc$next[0:0]$6816
+ attribute \src "libresoc.v:141800.3-141801.53"
wire $0\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__write_cr0$next[0:0]$6891
- attribute \src "libresoc.v:143686.3-143687.59"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__write_cr0$next[0:0]$6817
+ attribute \src "libresoc.v:141816.3-141817.59"
wire $0\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $0\logical_op__zero_a$next[0:0]$6892
- attribute \src "libresoc.v:143680.3-143681.53"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $0\logical_op__zero_a$next[0:0]$6818
+ attribute \src "libresoc.v:141810.3-141811.53"
wire $0\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:143820.3-143832.6"
- wire width 2 $0\muxid$next[1:0]$6872
- attribute \src "libresoc.v:143698.3-143699.27"
+ attribute \src "libresoc.v:141950.3-141962.6"
+ wire width 2 $0\muxid$next[1:0]$6798
+ attribute \src "libresoc.v:141828.3-141829.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:143875.3-143893.6"
- wire width 64 $0\o$next[63:0]$6918
- attribute \src "libresoc.v:143658.3-143659.19"
+ attribute \src "libresoc.v:142005.3-142023.6"
+ wire width 64 $0\o$next[63:0]$6844
+ attribute \src "libresoc.v:141788.3-141789.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:143875.3-143893.6"
- wire $0\o_ok$next[0:0]$6919
- attribute \src "libresoc.v:143660.3-143661.25"
+ attribute \src "libresoc.v:142005.3-142023.6"
+ wire $0\o_ok$next[0:0]$6845
+ attribute \src "libresoc.v:141790.3-141791.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:143802.3-143819.6"
- wire $0\r_busy$next[0:0]$6868
- attribute \src "libresoc.v:143700.3-143701.29"
+ attribute \src "libresoc.v:141932.3-141949.6"
+ wire $0\r_busy$next[0:0]$6794
+ attribute \src "libresoc.v:141830.3-141831.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:143913.3-143931.6"
- wire $0\xer_so$next[0:0]$6930
- attribute \src "libresoc.v:143650.3-143651.29"
+ attribute \src "libresoc.v:142043.3-142061.6"
+ wire $0\xer_so$next[0:0]$6856
+ attribute \src "libresoc.v:141780.3-141781.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:143913.3-143931.6"
- wire $0\xer_so_ok$next[0:0]$6931
- attribute \src "libresoc.v:143652.3-143653.35"
+ attribute \src "libresoc.v:142043.3-142061.6"
+ wire $0\xer_so_ok$next[0:0]$6857
+ attribute \src "libresoc.v:141782.3-141783.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:143894.3-143912.6"
- wire width 4 $1\cr_a$next[3:0]$6926
- attribute \src "libresoc.v:142588.13-142588.24"
+ attribute \src "libresoc.v:142024.3-142042.6"
+ wire width 4 $1\cr_a$next[3:0]$6852
+ attribute \src "libresoc.v:140718.13-140718.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:143894.3-143912.6"
- wire $1\cr_a_ok$next[0:0]$6927
- attribute \src "libresoc.v:142597.7-142597.21"
+ attribute \src "libresoc.v:142024.3-142042.6"
+ wire $1\cr_a_ok$next[0:0]$6853
+ attribute \src "libresoc.v:140727.7-140727.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 4 $1\logical_op__data_len$next[3:0]$6893
- attribute \src "libresoc.v:142878.13-142878.40"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 4 $1\logical_op__data_len$next[3:0]$6819
+ attribute \src "libresoc.v:141008.13-141008.40"
wire width 4 $1\logical_op__data_len[3:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 13 $1\logical_op__fn_unit$next[12:0]$6894
- attribute \src "libresoc.v:142901.14-142901.44"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 13 $1\logical_op__fn_unit$next[12:0]$6820
+ attribute \src "libresoc.v:141031.14-141031.44"
wire width 13 $1\logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 64 $1\logical_op__imm_data__data$next[63:0]$6895
- attribute \src "libresoc.v:142938.14-142938.63"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 64 $1\logical_op__imm_data__data$next[63:0]$6821
+ attribute \src "libresoc.v:141068.14-141068.63"
wire width 64 $1\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__imm_data__ok$next[0:0]$6896
- attribute \src "libresoc.v:142947.7-142947.38"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__imm_data__ok$next[0:0]$6822
+ attribute \src "libresoc.v:141077.7-141077.38"
wire $1\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 2 $1\logical_op__input_carry$next[1:0]$6897
- attribute \src "libresoc.v:142960.13-142960.43"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 2 $1\logical_op__input_carry$next[1:0]$6823
+ attribute \src "libresoc.v:141090.13-141090.43"
wire width 2 $1\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 32 $1\logical_op__insn$next[31:0]$6898
- attribute \src "libresoc.v:142977.14-142977.38"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 32 $1\logical_op__insn$next[31:0]$6824
+ attribute \src "libresoc.v:141107.14-141107.38"
wire width 32 $1\logical_op__insn[31:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 7 $1\logical_op__insn_type$next[6:0]$6899
- attribute \src "libresoc.v:143060.13-143060.42"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 7 $1\logical_op__insn_type$next[6:0]$6825
+ attribute \src "libresoc.v:141190.13-141190.42"
wire width 7 $1\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__invert_in$next[0:0]$6900
- attribute \src "libresoc.v:143217.7-143217.35"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__invert_in$next[0:0]$6826
+ attribute \src "libresoc.v:141347.7-141347.35"
wire $1\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__invert_out$next[0:0]$6901
- attribute \src "libresoc.v:143226.7-143226.36"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__invert_out$next[0:0]$6827
+ attribute \src "libresoc.v:141356.7-141356.36"
wire $1\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__is_32bit$next[0:0]$6902
- attribute \src "libresoc.v:143235.7-143235.34"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__is_32bit$next[0:0]$6828
+ attribute \src "libresoc.v:141365.7-141365.34"
wire $1\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__is_signed$next[0:0]$6903
- attribute \src "libresoc.v:143244.7-143244.35"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__is_signed$next[0:0]$6829
+ attribute \src "libresoc.v:141374.7-141374.35"
wire $1\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__oe__oe$next[0:0]$6904
- attribute \src "libresoc.v:143253.7-143253.32"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__oe__oe$next[0:0]$6830
+ attribute \src "libresoc.v:141383.7-141383.32"
wire $1\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__oe__ok$next[0:0]$6905
- attribute \src "libresoc.v:143262.7-143262.32"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__oe__ok$next[0:0]$6831
+ attribute \src "libresoc.v:141392.7-141392.32"
wire $1\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__output_carry$next[0:0]$6906
- attribute \src "libresoc.v:143271.7-143271.38"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__output_carry$next[0:0]$6832
+ attribute \src "libresoc.v:141401.7-141401.38"
wire $1\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__rc__ok$next[0:0]$6907
- attribute \src "libresoc.v:143280.7-143280.32"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__rc__ok$next[0:0]$6833
+ attribute \src "libresoc.v:141410.7-141410.32"
wire $1\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__rc__rc$next[0:0]$6908
- attribute \src "libresoc.v:143289.7-143289.32"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__rc__rc$next[0:0]$6834
+ attribute \src "libresoc.v:141419.7-141419.32"
wire $1\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__write_cr0$next[0:0]$6909
- attribute \src "libresoc.v:143298.7-143298.35"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__write_cr0$next[0:0]$6835
+ attribute \src "libresoc.v:141428.7-141428.35"
wire $1\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $1\logical_op__zero_a$next[0:0]$6910
- attribute \src "libresoc.v:143307.7-143307.32"
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $1\logical_op__zero_a$next[0:0]$6836
+ attribute \src "libresoc.v:141437.7-141437.32"
wire $1\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:143820.3-143832.6"
- wire width 2 $1\muxid$next[1:0]$6873
- attribute \src "libresoc.v:143588.13-143588.25"
+ attribute \src "libresoc.v:141950.3-141962.6"
+ wire width 2 $1\muxid$next[1:0]$6799
+ attribute \src "libresoc.v:141718.13-141718.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:143875.3-143893.6"
- wire width 64 $1\o$next[63:0]$6920
- attribute \src "libresoc.v:143603.14-143603.38"
+ attribute \src "libresoc.v:142005.3-142023.6"
+ wire width 64 $1\o$next[63:0]$6846
+ attribute \src "libresoc.v:141733.14-141733.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:143875.3-143893.6"
- wire $1\o_ok$next[0:0]$6921
- attribute \src "libresoc.v:143610.7-143610.18"
+ attribute \src "libresoc.v:142005.3-142023.6"
+ wire $1\o_ok$next[0:0]$6847
+ attribute \src "libresoc.v:141740.7-141740.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:143802.3-143819.6"
- wire $1\r_busy$next[0:0]$6869
- attribute \src "libresoc.v:143624.7-143624.20"
+ attribute \src "libresoc.v:141932.3-141949.6"
+ wire $1\r_busy$next[0:0]$6795
+ attribute \src "libresoc.v:141754.7-141754.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:143913.3-143931.6"
- wire $1\xer_so$next[0:0]$6932
- attribute \src "libresoc.v:143633.7-143633.20"
+ attribute \src "libresoc.v:142043.3-142061.6"
+ wire $1\xer_so$next[0:0]$6858
+ attribute \src "libresoc.v:141763.7-141763.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:143913.3-143931.6"
- wire $1\xer_so_ok$next[0:0]$6933
- attribute \src "libresoc.v:143642.7-143642.23"
+ attribute \src "libresoc.v:142043.3-142061.6"
+ wire $1\xer_so_ok$next[0:0]$6859
+ attribute \src "libresoc.v:141772.7-141772.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:143894.3-143912.6"
- wire $2\cr_a_ok$next[0:0]$6928
- attribute \src "libresoc.v:143833.3-143874.6"
- wire width 64 $2\logical_op__imm_data__data$next[63:0]$6911
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $2\logical_op__imm_data__ok$next[0:0]$6912
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $2\logical_op__oe__oe$next[0:0]$6913
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $2\logical_op__oe__ok$next[0:0]$6914
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $2\logical_op__rc__ok$next[0:0]$6915
- attribute \src "libresoc.v:143833.3-143874.6"
- wire $2\logical_op__rc__rc$next[0:0]$6916
- attribute \src "libresoc.v:143875.3-143893.6"
- wire $2\o_ok$next[0:0]$6922
- attribute \src "libresoc.v:143802.3-143819.6"
- wire $2\r_busy$next[0:0]$6870
- attribute \src "libresoc.v:143913.3-143931.6"
- wire $2\xer_so_ok$next[0:0]$6934
- attribute \src "libresoc.v:143649.18-143649.118"
- wire $and$libresoc.v:143649$6840_Y
+ attribute \src "libresoc.v:142024.3-142042.6"
+ wire $2\cr_a_ok$next[0:0]$6854
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire width 64 $2\logical_op__imm_data__data$next[63:0]$6837
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $2\logical_op__imm_data__ok$next[0:0]$6838
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $2\logical_op__oe__oe$next[0:0]$6839
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $2\logical_op__oe__ok$next[0:0]$6840
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $2\logical_op__rc__ok$next[0:0]$6841
+ attribute \src "libresoc.v:141963.3-142004.6"
+ wire $2\logical_op__rc__rc$next[0:0]$6842
+ attribute \src "libresoc.v:142005.3-142023.6"
+ wire $2\o_ok$next[0:0]$6848
+ attribute \src "libresoc.v:141932.3-141949.6"
+ wire $2\r_busy$next[0:0]$6796
+ attribute \src "libresoc.v:142043.3-142061.6"
+ wire $2\xer_so_ok$next[0:0]$6860
+ attribute \src "libresoc.v:141779.18-141779.118"
+ wire $and$libresoc.v:141779$6766_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
wire \cr_a_ok$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:142579.7-142579.15"
+ attribute \src "libresoc.v:140709.7-140709.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:143649$6840
+ cell $and $and$libresoc.v:141779$6766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$63
connect \B \p_ready_o
- connect \Y $and$libresoc.v:143649$6840_Y
+ connect \Y $and$libresoc.v:141779$6766_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:143702.14-143747.4"
+ attribute \src "libresoc.v:141832.14-141877.4"
cell \input$50 \input
connect \logical_op__data_len \input_logical_op__data_len
connect \logical_op__data_len$18 \input_logical_op__data_len$38
connect \xer_so$22 \input_xer_so$42
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:143748.13-143793.4"
+ attribute \src "libresoc.v:141878.13-141923.4"
cell \main$51 \main
connect \logical_op__data_len \main_logical_op__data_len
connect \logical_op__data_len$18 \main_logical_op__data_len$60
connect \xer_so$20 \main_xer_so$62
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:143794.10-143797.4"
+ attribute \src "libresoc.v:141924.10-141927.4"
cell \n$49 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:143798.10-143801.4"
+ attribute \src "libresoc.v:141928.10-141931.4"
cell \p$48 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:142579.7-142579.20"
- process $proc$libresoc.v:142579$6935
+ attribute \src "libresoc.v:140709.7-140709.20"
+ process $proc$libresoc.v:140709$6861
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:142588.13-142588.24"
- process $proc$libresoc.v:142588$6936
+ attribute \src "libresoc.v:140718.13-140718.24"
+ process $proc$libresoc.v:140718$6862
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:142597.7-142597.21"
- process $proc$libresoc.v:142597$6937
+ attribute \src "libresoc.v:140727.7-140727.21"
+ process $proc$libresoc.v:140727$6863
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:142878.13-142878.40"
- process $proc$libresoc.v:142878$6938
+ attribute \src "libresoc.v:141008.13-141008.40"
+ process $proc$libresoc.v:141008$6864
assign { } { }
assign $1\logical_op__data_len[3:0] 4'0000
sync always
sync init
update \logical_op__data_len $1\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:142901.14-142901.44"
- process $proc$libresoc.v:142901$6939
+ attribute \src "libresoc.v:141031.14-141031.44"
+ process $proc$libresoc.v:141031$6865
assign { } { }
assign $1\logical_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \logical_op__fn_unit $1\logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:142938.14-142938.63"
- process $proc$libresoc.v:142938$6940
+ attribute \src "libresoc.v:141068.14-141068.63"
+ process $proc$libresoc.v:141068$6866
assign { } { }
assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:142947.7-142947.38"
- process $proc$libresoc.v:142947$6941
+ attribute \src "libresoc.v:141077.7-141077.38"
+ process $proc$libresoc.v:141077$6867
assign { } { }
assign $1\logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:142960.13-142960.43"
- process $proc$libresoc.v:142960$6942
+ attribute \src "libresoc.v:141090.13-141090.43"
+ process $proc$libresoc.v:141090$6868
assign { } { }
assign $1\logical_op__input_carry[1:0] 2'00
sync always
sync init
update \logical_op__input_carry $1\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:142977.14-142977.38"
- process $proc$libresoc.v:142977$6943
+ attribute \src "libresoc.v:141107.14-141107.38"
+ process $proc$libresoc.v:141107$6869
assign { } { }
assign $1\logical_op__insn[31:0] 0
sync always
sync init
update \logical_op__insn $1\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:143060.13-143060.42"
- process $proc$libresoc.v:143060$6944
+ attribute \src "libresoc.v:141190.13-141190.42"
+ process $proc$libresoc.v:141190$6870
assign { } { }
assign $1\logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \logical_op__insn_type $1\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:143217.7-143217.35"
- process $proc$libresoc.v:143217$6945
+ attribute \src "libresoc.v:141347.7-141347.35"
+ process $proc$libresoc.v:141347$6871
assign { } { }
assign $1\logical_op__invert_in[0:0] 1'0
sync always
sync init
update \logical_op__invert_in $1\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:143226.7-143226.36"
- process $proc$libresoc.v:143226$6946
+ attribute \src "libresoc.v:141356.7-141356.36"
+ process $proc$libresoc.v:141356$6872
assign { } { }
assign $1\logical_op__invert_out[0:0] 1'0
sync always
sync init
update \logical_op__invert_out $1\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:143235.7-143235.34"
- process $proc$libresoc.v:143235$6947
+ attribute \src "libresoc.v:141365.7-141365.34"
+ process $proc$libresoc.v:141365$6873
assign { } { }
assign $1\logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \logical_op__is_32bit $1\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:143244.7-143244.35"
- process $proc$libresoc.v:143244$6948
+ attribute \src "libresoc.v:141374.7-141374.35"
+ process $proc$libresoc.v:141374$6874
assign { } { }
assign $1\logical_op__is_signed[0:0] 1'0
sync always
sync init
update \logical_op__is_signed $1\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:143253.7-143253.32"
- process $proc$libresoc.v:143253$6949
+ attribute \src "libresoc.v:141383.7-141383.32"
+ process $proc$libresoc.v:141383$6875
assign { } { }
assign $1\logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \logical_op__oe__oe $1\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:143262.7-143262.32"
- process $proc$libresoc.v:143262$6950
+ attribute \src "libresoc.v:141392.7-141392.32"
+ process $proc$libresoc.v:141392$6876
assign { } { }
assign $1\logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \logical_op__oe__ok $1\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:143271.7-143271.38"
- process $proc$libresoc.v:143271$6951
+ attribute \src "libresoc.v:141401.7-141401.38"
+ process $proc$libresoc.v:141401$6877
assign { } { }
assign $1\logical_op__output_carry[0:0] 1'0
sync always
sync init
update \logical_op__output_carry $1\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:143280.7-143280.32"
- process $proc$libresoc.v:143280$6952
+ attribute \src "libresoc.v:141410.7-141410.32"
+ process $proc$libresoc.v:141410$6878
assign { } { }
assign $1\logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \logical_op__rc__ok $1\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:143289.7-143289.32"
- process $proc$libresoc.v:143289$6953
+ attribute \src "libresoc.v:141419.7-141419.32"
+ process $proc$libresoc.v:141419$6879
assign { } { }
assign $1\logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \logical_op__rc__rc $1\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:143298.7-143298.35"
- process $proc$libresoc.v:143298$6954
+ attribute \src "libresoc.v:141428.7-141428.35"
+ process $proc$libresoc.v:141428$6880
assign { } { }
assign $1\logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:143307.7-143307.32"
- process $proc$libresoc.v:143307$6955
+ attribute \src "libresoc.v:141437.7-141437.32"
+ process $proc$libresoc.v:141437$6881
assign { } { }
assign $1\logical_op__zero_a[0:0] 1'0
sync always
sync init
update \logical_op__zero_a $1\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:143588.13-143588.25"
- process $proc$libresoc.v:143588$6956
+ attribute \src "libresoc.v:141718.13-141718.25"
+ process $proc$libresoc.v:141718$6882
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:143603.14-143603.38"
- process $proc$libresoc.v:143603$6957
+ attribute \src "libresoc.v:141733.14-141733.38"
+ process $proc$libresoc.v:141733$6883
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:143610.7-143610.18"
- process $proc$libresoc.v:143610$6958
+ attribute \src "libresoc.v:141740.7-141740.18"
+ process $proc$libresoc.v:141740$6884
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:143624.7-143624.20"
- process $proc$libresoc.v:143624$6959
+ attribute \src "libresoc.v:141754.7-141754.20"
+ process $proc$libresoc.v:141754$6885
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:143633.7-143633.20"
- process $proc$libresoc.v:143633$6960
+ attribute \src "libresoc.v:141763.7-141763.20"
+ process $proc$libresoc.v:141763$6886
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:143642.7-143642.23"
- process $proc$libresoc.v:143642$6961
+ attribute \src "libresoc.v:141772.7-141772.23"
+ process $proc$libresoc.v:141772$6887
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:143650.3-143651.29"
- process $proc$libresoc.v:143650$6841
+ attribute \src "libresoc.v:141780.3-141781.29"
+ process $proc$libresoc.v:141780$6767
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:143652.3-143653.35"
- process $proc$libresoc.v:143652$6842
+ attribute \src "libresoc.v:141782.3-141783.35"
+ process $proc$libresoc.v:141782$6768
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:143654.3-143655.25"
- process $proc$libresoc.v:143654$6843
+ attribute \src "libresoc.v:141784.3-141785.25"
+ process $proc$libresoc.v:141784$6769
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:143656.3-143657.31"
- process $proc$libresoc.v:143656$6844
+ attribute \src "libresoc.v:141786.3-141787.31"
+ process $proc$libresoc.v:141786$6770
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:143658.3-143659.19"
- process $proc$libresoc.v:143658$6845
+ attribute \src "libresoc.v:141788.3-141789.19"
+ process $proc$libresoc.v:141788$6771
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:143660.3-143661.25"
- process $proc$libresoc.v:143660$6846
+ attribute \src "libresoc.v:141790.3-141791.25"
+ process $proc$libresoc.v:141790$6772
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:143662.3-143663.59"
- process $proc$libresoc.v:143662$6847
+ attribute \src "libresoc.v:141792.3-141793.59"
+ process $proc$libresoc.v:141792$6773
assign { } { }
assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next
sync posedge \coresync_clk
update \logical_op__insn_type $0\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:143664.3-143665.55"
- process $proc$libresoc.v:143664$6848
+ attribute \src "libresoc.v:141794.3-141795.55"
+ process $proc$libresoc.v:141794$6774
assign { } { }
assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next
sync posedge \coresync_clk
update \logical_op__fn_unit $0\logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:143666.3-143667.69"
- process $proc$libresoc.v:143666$6849
+ attribute \src "libresoc.v:141796.3-141797.69"
+ process $proc$libresoc.v:141796$6775
assign { } { }
assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next
sync posedge \coresync_clk
update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:143668.3-143669.65"
- process $proc$libresoc.v:143668$6850
+ attribute \src "libresoc.v:141798.3-141799.65"
+ process $proc$libresoc.v:141798$6776
assign { } { }
assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:143670.3-143671.53"
- process $proc$libresoc.v:143670$6851
+ attribute \src "libresoc.v:141800.3-141801.53"
+ process $proc$libresoc.v:141800$6777
assign { } { }
assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next
sync posedge \coresync_clk
update \logical_op__rc__rc $0\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:143672.3-143673.53"
- process $proc$libresoc.v:143672$6852
+ attribute \src "libresoc.v:141802.3-141803.53"
+ process $proc$libresoc.v:141802$6778
assign { } { }
assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next
sync posedge \coresync_clk
update \logical_op__rc__ok $0\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:143674.3-143675.53"
- process $proc$libresoc.v:143674$6853
+ attribute \src "libresoc.v:141804.3-141805.53"
+ process $proc$libresoc.v:141804$6779
assign { } { }
assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next
sync posedge \coresync_clk
update \logical_op__oe__oe $0\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:143676.3-143677.53"
- process $proc$libresoc.v:143676$6854
+ attribute \src "libresoc.v:141806.3-141807.53"
+ process $proc$libresoc.v:141806$6780
assign { } { }
assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next
sync posedge \coresync_clk
update \logical_op__oe__ok $0\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:143678.3-143679.59"
- process $proc$libresoc.v:143678$6855
+ attribute \src "libresoc.v:141808.3-141809.59"
+ process $proc$libresoc.v:141808$6781
assign { } { }
assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next
sync posedge \coresync_clk
update \logical_op__invert_in $0\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:143680.3-143681.53"
- process $proc$libresoc.v:143680$6856
+ attribute \src "libresoc.v:141810.3-141811.53"
+ process $proc$libresoc.v:141810$6782
assign { } { }
assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next
sync posedge \coresync_clk
update \logical_op__zero_a $0\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:143682.3-143683.63"
- process $proc$libresoc.v:143682$6857
+ attribute \src "libresoc.v:141812.3-141813.63"
+ process $proc$libresoc.v:141812$6783
assign { } { }
assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next
sync posedge \coresync_clk
update \logical_op__input_carry $0\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:143684.3-143685.61"
- process $proc$libresoc.v:143684$6858
+ attribute \src "libresoc.v:141814.3-141815.61"
+ process $proc$libresoc.v:141814$6784
assign { } { }
assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next
sync posedge \coresync_clk
update \logical_op__invert_out $0\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:143686.3-143687.59"
- process $proc$libresoc.v:143686$6859
+ attribute \src "libresoc.v:141816.3-141817.59"
+ process $proc$libresoc.v:141816$6785
assign { } { }
assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next
sync posedge \coresync_clk
update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:143688.3-143689.65"
- process $proc$libresoc.v:143688$6860
+ attribute \src "libresoc.v:141818.3-141819.65"
+ process $proc$libresoc.v:141818$6786
assign { } { }
assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next
sync posedge \coresync_clk
update \logical_op__output_carry $0\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:143690.3-143691.57"
- process $proc$libresoc.v:143690$6861
+ attribute \src "libresoc.v:141820.3-141821.57"
+ process $proc$libresoc.v:141820$6787
assign { } { }
assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next
sync posedge \coresync_clk
update \logical_op__is_32bit $0\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:143692.3-143693.59"
- process $proc$libresoc.v:143692$6862
+ attribute \src "libresoc.v:141822.3-141823.59"
+ process $proc$libresoc.v:141822$6788
assign { } { }
assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next
sync posedge \coresync_clk
update \logical_op__is_signed $0\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:143694.3-143695.57"
- process $proc$libresoc.v:143694$6863
+ attribute \src "libresoc.v:141824.3-141825.57"
+ process $proc$libresoc.v:141824$6789
assign { } { }
assign $0\logical_op__data_len[3:0] \logical_op__data_len$next
sync posedge \coresync_clk
update \logical_op__data_len $0\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:143696.3-143697.49"
- process $proc$libresoc.v:143696$6864
+ attribute \src "libresoc.v:141826.3-141827.49"
+ process $proc$libresoc.v:141826$6790
assign { } { }
assign $0\logical_op__insn[31:0] \logical_op__insn$next
sync posedge \coresync_clk
update \logical_op__insn $0\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:143698.3-143699.27"
- process $proc$libresoc.v:143698$6865
+ attribute \src "libresoc.v:141828.3-141829.27"
+ process $proc$libresoc.v:141828$6791
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:143700.3-143701.29"
- process $proc$libresoc.v:143700$6866
+ attribute \src "libresoc.v:141830.3-141831.29"
+ process $proc$libresoc.v:141830$6792
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:143802.3-143819.6"
- process $proc$libresoc.v:143802$6867
+ attribute \src "libresoc.v:141932.3-141949.6"
+ process $proc$libresoc.v:141932$6793
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$6868 $2\r_busy$next[0:0]$6870
- attribute \src "libresoc.v:143803.5-143803.29"
+ assign $0\r_busy$next[0:0]$6794 $2\r_busy$next[0:0]$6796
+ attribute \src "libresoc.v:141933.5-141933.29"
switch \initial
- attribute \src "libresoc.v:143803.9-143803.17"
+ attribute \src "libresoc.v:141933.9-141933.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$6869 1'1
+ assign $1\r_busy$next[0:0]$6795 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$6869 1'0
+ assign $1\r_busy$next[0:0]$6795 1'0
case
- assign $1\r_busy$next[0:0]$6869 \r_busy
+ assign $1\r_busy$next[0:0]$6795 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$6870 1'0
+ assign $2\r_busy$next[0:0]$6796 1'0
case
- assign $2\r_busy$next[0:0]$6870 $1\r_busy$next[0:0]$6869
+ assign $2\r_busy$next[0:0]$6796 $1\r_busy$next[0:0]$6795
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$6868
+ update \r_busy$next $0\r_busy$next[0:0]$6794
end
- attribute \src "libresoc.v:143820.3-143832.6"
- process $proc$libresoc.v:143820$6871
+ attribute \src "libresoc.v:141950.3-141962.6"
+ process $proc$libresoc.v:141950$6797
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$6872 $1\muxid$next[1:0]$6873
- attribute \src "libresoc.v:143821.5-143821.29"
+ assign $0\muxid$next[1:0]$6798 $1\muxid$next[1:0]$6799
+ attribute \src "libresoc.v:141951.5-141951.29"
switch \initial
- attribute \src "libresoc.v:143821.9-143821.17"
+ attribute \src "libresoc.v:141951.9-141951.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$6873 \muxid$66
+ assign $1\muxid$next[1:0]$6799 \muxid$66
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$6873 \muxid$66
+ assign $1\muxid$next[1:0]$6799 \muxid$66
case
- assign $1\muxid$next[1:0]$6873 \muxid
+ assign $1\muxid$next[1:0]$6799 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$6872
+ update \muxid$next $0\muxid$next[1:0]$6798
end
- attribute \src "libresoc.v:143833.3-143874.6"
- process $proc$libresoc.v:143833$6874
+ attribute \src "libresoc.v:141963.3-142004.6"
+ process $proc$libresoc.v:141963$6800
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$next[3:0]$6875 $1\logical_op__data_len$next[3:0]$6893
- assign $0\logical_op__fn_unit$next[12:0]$6876 $1\logical_op__fn_unit$next[12:0]$6894
+ assign $0\logical_op__data_len$next[3:0]$6801 $1\logical_op__data_len$next[3:0]$6819
+ assign $0\logical_op__fn_unit$next[12:0]$6802 $1\logical_op__fn_unit$next[12:0]$6820
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$next[1:0]$6879 $1\logical_op__input_carry$next[1:0]$6897
- assign $0\logical_op__insn$next[31:0]$6880 $1\logical_op__insn$next[31:0]$6898
- assign $0\logical_op__insn_type$next[6:0]$6881 $1\logical_op__insn_type$next[6:0]$6899
- assign $0\logical_op__invert_in$next[0:0]$6882 $1\logical_op__invert_in$next[0:0]$6900
- assign $0\logical_op__invert_out$next[0:0]$6883 $1\logical_op__invert_out$next[0:0]$6901
- assign $0\logical_op__is_32bit$next[0:0]$6884 $1\logical_op__is_32bit$next[0:0]$6902
- assign $0\logical_op__is_signed$next[0:0]$6885 $1\logical_op__is_signed$next[0:0]$6903
+ assign $0\logical_op__input_carry$next[1:0]$6805 $1\logical_op__input_carry$next[1:0]$6823
+ assign $0\logical_op__insn$next[31:0]$6806 $1\logical_op__insn$next[31:0]$6824
+ assign $0\logical_op__insn_type$next[6:0]$6807 $1\logical_op__insn_type$next[6:0]$6825
+ assign $0\logical_op__invert_in$next[0:0]$6808 $1\logical_op__invert_in$next[0:0]$6826
+ assign $0\logical_op__invert_out$next[0:0]$6809 $1\logical_op__invert_out$next[0:0]$6827
+ assign $0\logical_op__is_32bit$next[0:0]$6810 $1\logical_op__is_32bit$next[0:0]$6828
+ assign $0\logical_op__is_signed$next[0:0]$6811 $1\logical_op__is_signed$next[0:0]$6829
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$next[0:0]$6888 $1\logical_op__output_carry$next[0:0]$6906
+ assign $0\logical_op__output_carry$next[0:0]$6814 $1\logical_op__output_carry$next[0:0]$6832
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$next[0:0]$6891 $1\logical_op__write_cr0$next[0:0]$6909
- assign $0\logical_op__zero_a$next[0:0]$6892 $1\logical_op__zero_a$next[0:0]$6910
- assign $0\logical_op__imm_data__data$next[63:0]$6877 $2\logical_op__imm_data__data$next[63:0]$6911
- assign $0\logical_op__imm_data__ok$next[0:0]$6878 $2\logical_op__imm_data__ok$next[0:0]$6912
- assign $0\logical_op__oe__oe$next[0:0]$6886 $2\logical_op__oe__oe$next[0:0]$6913
- assign $0\logical_op__oe__ok$next[0:0]$6887 $2\logical_op__oe__ok$next[0:0]$6914
- assign $0\logical_op__rc__ok$next[0:0]$6889 $2\logical_op__rc__ok$next[0:0]$6915
- assign $0\logical_op__rc__rc$next[0:0]$6890 $2\logical_op__rc__rc$next[0:0]$6916
- attribute \src "libresoc.v:143834.5-143834.29"
+ assign $0\logical_op__write_cr0$next[0:0]$6817 $1\logical_op__write_cr0$next[0:0]$6835
+ assign $0\logical_op__zero_a$next[0:0]$6818 $1\logical_op__zero_a$next[0:0]$6836
+ assign $0\logical_op__imm_data__data$next[63:0]$6803 $2\logical_op__imm_data__data$next[63:0]$6837
+ assign $0\logical_op__imm_data__ok$next[0:0]$6804 $2\logical_op__imm_data__ok$next[0:0]$6838
+ assign $0\logical_op__oe__oe$next[0:0]$6812 $2\logical_op__oe__oe$next[0:0]$6839
+ assign $0\logical_op__oe__ok$next[0:0]$6813 $2\logical_op__oe__ok$next[0:0]$6840
+ assign $0\logical_op__rc__ok$next[0:0]$6815 $2\logical_op__rc__ok$next[0:0]$6841
+ assign $0\logical_op__rc__rc$next[0:0]$6816 $2\logical_op__rc__rc$next[0:0]$6842
+ attribute \src "libresoc.v:141964.5-141964.29"
switch \initial
- attribute \src "libresoc.v:143834.9-143834.17"
+ attribute \src "libresoc.v:141964.9-141964.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$6898 $1\logical_op__data_len$next[3:0]$6893 $1\logical_op__is_signed$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6902 $1\logical_op__output_carry$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6909 $1\logical_op__invert_out$next[0:0]$6901 $1\logical_op__input_carry$next[1:0]$6897 $1\logical_op__zero_a$next[0:0]$6910 $1\logical_op__invert_in$next[0:0]$6900 $1\logical_op__oe__ok$next[0:0]$6905 $1\logical_op__oe__oe$next[0:0]$6904 $1\logical_op__rc__ok$next[0:0]$6907 $1\logical_op__rc__rc$next[0:0]$6908 $1\logical_op__imm_data__ok$next[0:0]$6896 $1\logical_op__imm_data__data$next[63:0]$6895 $1\logical_op__fn_unit$next[12:0]$6894 $1\logical_op__insn_type$next[6:0]$6899 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
+ assign { $1\logical_op__insn$next[31:0]$6824 $1\logical_op__data_len$next[3:0]$6819 $1\logical_op__is_signed$next[0:0]$6829 $1\logical_op__is_32bit$next[0:0]$6828 $1\logical_op__output_carry$next[0:0]$6832 $1\logical_op__write_cr0$next[0:0]$6835 $1\logical_op__invert_out$next[0:0]$6827 $1\logical_op__input_carry$next[1:0]$6823 $1\logical_op__zero_a$next[0:0]$6836 $1\logical_op__invert_in$next[0:0]$6826 $1\logical_op__oe__ok$next[0:0]$6831 $1\logical_op__oe__oe$next[0:0]$6830 $1\logical_op__rc__ok$next[0:0]$6833 $1\logical_op__rc__rc$next[0:0]$6834 $1\logical_op__imm_data__ok$next[0:0]$6822 $1\logical_op__imm_data__data$next[63:0]$6821 $1\logical_op__fn_unit$next[12:0]$6820 $1\logical_op__insn_type$next[6:0]$6825 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$next[31:0]$6898 $1\logical_op__data_len$next[3:0]$6893 $1\logical_op__is_signed$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6902 $1\logical_op__output_carry$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6909 $1\logical_op__invert_out$next[0:0]$6901 $1\logical_op__input_carry$next[1:0]$6897 $1\logical_op__zero_a$next[0:0]$6910 $1\logical_op__invert_in$next[0:0]$6900 $1\logical_op__oe__ok$next[0:0]$6905 $1\logical_op__oe__oe$next[0:0]$6904 $1\logical_op__rc__ok$next[0:0]$6907 $1\logical_op__rc__rc$next[0:0]$6908 $1\logical_op__imm_data__ok$next[0:0]$6896 $1\logical_op__imm_data__data$next[63:0]$6895 $1\logical_op__fn_unit$next[12:0]$6894 $1\logical_op__insn_type$next[6:0]$6899 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
+ assign { $1\logical_op__insn$next[31:0]$6824 $1\logical_op__data_len$next[3:0]$6819 $1\logical_op__is_signed$next[0:0]$6829 $1\logical_op__is_32bit$next[0:0]$6828 $1\logical_op__output_carry$next[0:0]$6832 $1\logical_op__write_cr0$next[0:0]$6835 $1\logical_op__invert_out$next[0:0]$6827 $1\logical_op__input_carry$next[1:0]$6823 $1\logical_op__zero_a$next[0:0]$6836 $1\logical_op__invert_in$next[0:0]$6826 $1\logical_op__oe__ok$next[0:0]$6831 $1\logical_op__oe__oe$next[0:0]$6830 $1\logical_op__rc__ok$next[0:0]$6833 $1\logical_op__rc__rc$next[0:0]$6834 $1\logical_op__imm_data__ok$next[0:0]$6822 $1\logical_op__imm_data__data$next[63:0]$6821 $1\logical_op__fn_unit$next[12:0]$6820 $1\logical_op__insn_type$next[6:0]$6825 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 }
case
- assign $1\logical_op__data_len$next[3:0]$6893 \logical_op__data_len
- assign $1\logical_op__fn_unit$next[12:0]$6894 \logical_op__fn_unit
- assign $1\logical_op__imm_data__data$next[63:0]$6895 \logical_op__imm_data__data
- assign $1\logical_op__imm_data__ok$next[0:0]$6896 \logical_op__imm_data__ok
- assign $1\logical_op__input_carry$next[1:0]$6897 \logical_op__input_carry
- assign $1\logical_op__insn$next[31:0]$6898 \logical_op__insn
- assign $1\logical_op__insn_type$next[6:0]$6899 \logical_op__insn_type
- assign $1\logical_op__invert_in$next[0:0]$6900 \logical_op__invert_in
- assign $1\logical_op__invert_out$next[0:0]$6901 \logical_op__invert_out
- assign $1\logical_op__is_32bit$next[0:0]$6902 \logical_op__is_32bit
- assign $1\logical_op__is_signed$next[0:0]$6903 \logical_op__is_signed
- assign $1\logical_op__oe__oe$next[0:0]$6904 \logical_op__oe__oe
- assign $1\logical_op__oe__ok$next[0:0]$6905 \logical_op__oe__ok
- assign $1\logical_op__output_carry$next[0:0]$6906 \logical_op__output_carry
- assign $1\logical_op__rc__ok$next[0:0]$6907 \logical_op__rc__ok
- assign $1\logical_op__rc__rc$next[0:0]$6908 \logical_op__rc__rc
- assign $1\logical_op__write_cr0$next[0:0]$6909 \logical_op__write_cr0
- assign $1\logical_op__zero_a$next[0:0]$6910 \logical_op__zero_a
+ assign $1\logical_op__data_len$next[3:0]$6819 \logical_op__data_len
+ assign $1\logical_op__fn_unit$next[12:0]$6820 \logical_op__fn_unit
+ assign $1\logical_op__imm_data__data$next[63:0]$6821 \logical_op__imm_data__data
+ assign $1\logical_op__imm_data__ok$next[0:0]$6822 \logical_op__imm_data__ok
+ assign $1\logical_op__input_carry$next[1:0]$6823 \logical_op__input_carry
+ assign $1\logical_op__insn$next[31:0]$6824 \logical_op__insn
+ assign $1\logical_op__insn_type$next[6:0]$6825 \logical_op__insn_type
+ assign $1\logical_op__invert_in$next[0:0]$6826 \logical_op__invert_in
+ assign $1\logical_op__invert_out$next[0:0]$6827 \logical_op__invert_out
+ assign $1\logical_op__is_32bit$next[0:0]$6828 \logical_op__is_32bit
+ assign $1\logical_op__is_signed$next[0:0]$6829 \logical_op__is_signed
+ assign $1\logical_op__oe__oe$next[0:0]$6830 \logical_op__oe__oe
+ assign $1\logical_op__oe__ok$next[0:0]$6831 \logical_op__oe__ok
+ assign $1\logical_op__output_carry$next[0:0]$6832 \logical_op__output_carry
+ assign $1\logical_op__rc__ok$next[0:0]$6833 \logical_op__rc__ok
+ assign $1\logical_op__rc__rc$next[0:0]$6834 \logical_op__rc__rc
+ assign $1\logical_op__write_cr0$next[0:0]$6835 \logical_op__write_cr0
+ assign $1\logical_op__zero_a$next[0:0]$6836 \logical_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$next[63:0]$6911 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$next[0:0]$6912 1'0
- assign $2\logical_op__rc__rc$next[0:0]$6916 1'0
- assign $2\logical_op__rc__ok$next[0:0]$6915 1'0
- assign $2\logical_op__oe__oe$next[0:0]$6913 1'0
- assign $2\logical_op__oe__ok$next[0:0]$6914 1'0
+ assign $2\logical_op__imm_data__data$next[63:0]$6837 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$next[0:0]$6838 1'0
+ assign $2\logical_op__rc__rc$next[0:0]$6842 1'0
+ assign $2\logical_op__rc__ok$next[0:0]$6841 1'0
+ assign $2\logical_op__oe__oe$next[0:0]$6839 1'0
+ assign $2\logical_op__oe__ok$next[0:0]$6840 1'0
case
- assign $2\logical_op__imm_data__data$next[63:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6895
- assign $2\logical_op__imm_data__ok$next[0:0]$6912 $1\logical_op__imm_data__ok$next[0:0]$6896
- assign $2\logical_op__oe__oe$next[0:0]$6913 $1\logical_op__oe__oe$next[0:0]$6904
- assign $2\logical_op__oe__ok$next[0:0]$6914 $1\logical_op__oe__ok$next[0:0]$6905
- assign $2\logical_op__rc__ok$next[0:0]$6915 $1\logical_op__rc__ok$next[0:0]$6907
- assign $2\logical_op__rc__rc$next[0:0]$6916 $1\logical_op__rc__rc$next[0:0]$6908
+ assign $2\logical_op__imm_data__data$next[63:0]$6837 $1\logical_op__imm_data__data$next[63:0]$6821
+ assign $2\logical_op__imm_data__ok$next[0:0]$6838 $1\logical_op__imm_data__ok$next[0:0]$6822
+ assign $2\logical_op__oe__oe$next[0:0]$6839 $1\logical_op__oe__oe$next[0:0]$6830
+ assign $2\logical_op__oe__ok$next[0:0]$6840 $1\logical_op__oe__ok$next[0:0]$6831
+ assign $2\logical_op__rc__ok$next[0:0]$6841 $1\logical_op__rc__ok$next[0:0]$6833
+ assign $2\logical_op__rc__rc$next[0:0]$6842 $1\logical_op__rc__rc$next[0:0]$6834
end
sync always
- update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6875
- update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6876
- update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6877
- update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6878
- update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6879
- update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6880
- update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6881
- update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6882
- update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6883
- update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6884
- update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6885
- update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6886
- update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6887
- update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6888
- update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6889
- update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6890
- update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6891
- update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6892
+ update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6801
+ update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6802
+ update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6803
+ update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6804
+ update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6805
+ update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6806
+ update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6807
+ update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6808
+ update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6809
+ update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6810
+ update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6811
+ update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6812
+ update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6813
+ update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6814
+ update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6815
+ update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6816
+ update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6817
+ update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6818
end
- attribute \src "libresoc.v:143875.3-143893.6"
- process $proc$libresoc.v:143875$6917
+ attribute \src "libresoc.v:142005.3-142023.6"
+ process $proc$libresoc.v:142005$6843
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$6918 $1\o$next[63:0]$6920
+ assign $0\o$next[63:0]$6844 $1\o$next[63:0]$6846
assign { } { }
- assign $0\o_ok$next[0:0]$6919 $2\o_ok$next[0:0]$6922
- attribute \src "libresoc.v:143876.5-143876.29"
+ assign $0\o_ok$next[0:0]$6845 $2\o_ok$next[0:0]$6848
+ attribute \src "libresoc.v:142006.5-142006.29"
switch \initial
- attribute \src "libresoc.v:143876.9-143876.17"
+ attribute \src "libresoc.v:142006.9-142006.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$6921 $1\o$next[63:0]$6920 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$6847 $1\o$next[63:0]$6846 } { \o_ok$86 \o$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$6921 $1\o$next[63:0]$6920 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$6847 $1\o$next[63:0]$6846 } { \o_ok$86 \o$85 }
case
- assign $1\o$next[63:0]$6920 \o
- assign $1\o_ok$next[0:0]$6921 \o_ok
+ assign $1\o$next[63:0]$6846 \o
+ assign $1\o_ok$next[0:0]$6847 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$6922 1'0
+ assign $2\o_ok$next[0:0]$6848 1'0
case
- assign $2\o_ok$next[0:0]$6922 $1\o_ok$next[0:0]$6921
+ assign $2\o_ok$next[0:0]$6848 $1\o_ok$next[0:0]$6847
end
sync always
- update \o$next $0\o$next[63:0]$6918
- update \o_ok$next $0\o_ok$next[0:0]$6919
+ update \o$next $0\o$next[63:0]$6844
+ update \o_ok$next $0\o_ok$next[0:0]$6845
end
- attribute \src "libresoc.v:143894.3-143912.6"
- process $proc$libresoc.v:143894$6923
+ attribute \src "libresoc.v:142024.3-142042.6"
+ process $proc$libresoc.v:142024$6849
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$6924 $1\cr_a$next[3:0]$6926
+ assign $0\cr_a$next[3:0]$6850 $1\cr_a$next[3:0]$6852
assign { } { }
- assign $0\cr_a_ok$next[0:0]$6925 $2\cr_a_ok$next[0:0]$6928
- attribute \src "libresoc.v:143895.5-143895.29"
+ assign $0\cr_a_ok$next[0:0]$6851 $2\cr_a_ok$next[0:0]$6854
+ attribute \src "libresoc.v:142025.5-142025.29"
switch \initial
- attribute \src "libresoc.v:143895.9-143895.17"
+ attribute \src "libresoc.v:142025.9-142025.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$6927 $1\cr_a$next[3:0]$6926 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$6853 $1\cr_a$next[3:0]$6852 } { \cr_a_ok$88 \cr_a$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$6927 $1\cr_a$next[3:0]$6926 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$6853 $1\cr_a$next[3:0]$6852 } { \cr_a_ok$88 \cr_a$87 }
case
- assign $1\cr_a$next[3:0]$6926 \cr_a
- assign $1\cr_a_ok$next[0:0]$6927 \cr_a_ok
+ assign $1\cr_a$next[3:0]$6852 \cr_a
+ assign $1\cr_a_ok$next[0:0]$6853 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$6928 1'0
+ assign $2\cr_a_ok$next[0:0]$6854 1'0
case
- assign $2\cr_a_ok$next[0:0]$6928 $1\cr_a_ok$next[0:0]$6927
+ assign $2\cr_a_ok$next[0:0]$6854 $1\cr_a_ok$next[0:0]$6853
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$6924
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6925
+ update \cr_a$next $0\cr_a$next[3:0]$6850
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6851
end
- attribute \src "libresoc.v:143913.3-143931.6"
- process $proc$libresoc.v:143913$6929
+ attribute \src "libresoc.v:142043.3-142061.6"
+ process $proc$libresoc.v:142043$6855
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$6930 $1\xer_so$next[0:0]$6932
+ assign $0\xer_so$next[0:0]$6856 $1\xer_so$next[0:0]$6858
assign { } { }
- assign $0\xer_so_ok$next[0:0]$6931 $2\xer_so_ok$next[0:0]$6934
- attribute \src "libresoc.v:143914.5-143914.29"
+ assign $0\xer_so_ok$next[0:0]$6857 $2\xer_so_ok$next[0:0]$6860
+ attribute \src "libresoc.v:142044.5-142044.29"
switch \initial
- attribute \src "libresoc.v:143914.9-143914.17"
+ attribute \src "libresoc.v:142044.9-142044.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$6933 $1\xer_so$next[0:0]$6932 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$6859 $1\xer_so$next[0:0]$6858 } { \xer_so_ok$92 \xer_so$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$6933 $1\xer_so$next[0:0]$6932 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$6859 $1\xer_so$next[0:0]$6858 } { \xer_so_ok$92 \xer_so$91 }
case
- assign $1\xer_so$next[0:0]$6932 \xer_so
- assign $1\xer_so_ok$next[0:0]$6933 \xer_so_ok
+ assign $1\xer_so$next[0:0]$6858 \xer_so
+ assign $1\xer_so_ok$next[0:0]$6859 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$6934 1'0
+ assign $2\xer_so_ok$next[0:0]$6860 1'0
case
- assign $2\xer_so_ok$next[0:0]$6934 $1\xer_so_ok$next[0:0]$6933
+ assign $2\xer_so_ok$next[0:0]$6860 $1\xer_so_ok$next[0:0]$6859
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$6930
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6931
+ update \xer_so$next $0\xer_so$next[0:0]$6856
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6857
end
- connect \$64 $and$libresoc.v:143649$6840_Y
+ connect \$64 $and$libresoc.v:141779$6766_Y
connect \cr_a$89 4'0000
connect \cr_a_ok$90 1'0
connect \xer_so_ok$93 1'0
connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:143959.1-144982.10"
+attribute \src "libresoc.v:142089.1-143112.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2"
attribute \generator "nMigen"
module \logical_pipe2
- attribute \src "libresoc.v:144949.3-144967.6"
- wire width 4 $0\cr_a$22$next[3:0]$7067
- attribute \src "libresoc.v:144753.3-144754.33"
- wire width 4 $0\cr_a$22[3:0]$6964
- attribute \src "libresoc.v:143971.13-143971.29"
- wire width 4 $0\cr_a$22[3:0]$7074
- attribute \src "libresoc.v:144949.3-144967.6"
- wire $0\cr_a_ok$23$next[0:0]$7068
- attribute \src "libresoc.v:144755.3-144756.39"
- wire $0\cr_a_ok$23[0:0]$6966
- attribute \src "libresoc.v:143980.7-143980.26"
- wire $0\cr_a_ok$23[0:0]$7076
- attribute \src "libresoc.v:143960.7-143960.20"
+ attribute \src "libresoc.v:143079.3-143097.6"
+ wire width 4 $0\cr_a$22$next[3:0]$6993
+ attribute \src "libresoc.v:142883.3-142884.33"
+ wire width 4 $0\cr_a$22[3:0]$6890
+ attribute \src "libresoc.v:142101.13-142101.29"
+ wire width 4 $0\cr_a$22[3:0]$7000
+ attribute \src "libresoc.v:143079.3-143097.6"
+ wire $0\cr_a_ok$23$next[0:0]$6994
+ attribute \src "libresoc.v:142885.3-142886.39"
+ wire $0\cr_a_ok$23[0:0]$6892
+ attribute \src "libresoc.v:142110.7-142110.26"
+ wire $0\cr_a_ok$23[0:0]$7002
+ attribute \src "libresoc.v:142090.7-142090.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 4 $0\logical_op__data_len$18$next[3:0]$7018
- attribute \src "libresoc.v:144793.3-144794.65"
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 4 $0\logical_op__data_len$18$next[3:0]$6944
+ attribute \src "libresoc.v:142923.3-142924.65"
+ wire width 4 $0\logical_op__data_len$18[3:0]$6930
+ attribute \src "libresoc.v:142121.13-142121.45"
wire width 4 $0\logical_op__data_len$18[3:0]$7004
- attribute \src "libresoc.v:143991.13-143991.45"
- wire width 4 $0\logical_op__data_len$18[3:0]$7078
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 13 $0\logical_op__fn_unit$3$next[12:0]$7019
- attribute \src "libresoc.v:144763.3-144764.61"
- wire width 13 $0\logical_op__fn_unit$3[12:0]$6974
- attribute \src "libresoc.v:144028.14-144028.48"
- wire width 13 $0\logical_op__fn_unit$3[12:0]$7080
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7020
- attribute \src "libresoc.v:144765.3-144766.75"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$6976
- attribute \src "libresoc.v:144051.14-144051.67"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$7082
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__imm_data__ok$5$next[0:0]$7021
- attribute \src "libresoc.v:144767.3-144768.71"
- wire $0\logical_op__imm_data__ok$5[0:0]$6978
- attribute \src "libresoc.v:144060.7-144060.42"
- wire $0\logical_op__imm_data__ok$5[0:0]$7084
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 2 $0\logical_op__input_carry$12$next[1:0]$7022
- attribute \src "libresoc.v:144781.3-144782.71"
- wire width 2 $0\logical_op__input_carry$12[1:0]$6992
- attribute \src "libresoc.v:144077.13-144077.48"
- wire width 2 $0\logical_op__input_carry$12[1:0]$7086
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 32 $0\logical_op__insn$19$next[31:0]$7023
- attribute \src "libresoc.v:144795.3-144796.57"
- wire width 32 $0\logical_op__insn$19[31:0]$7006
- attribute \src "libresoc.v:144090.14-144090.43"
- wire width 32 $0\logical_op__insn$19[31:0]$7088
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 7 $0\logical_op__insn_type$2$next[6:0]$7024
- attribute \src "libresoc.v:144761.3-144762.65"
- wire width 7 $0\logical_op__insn_type$2[6:0]$6972
- attribute \src "libresoc.v:144247.13-144247.46"
- wire width 7 $0\logical_op__insn_type$2[6:0]$7090
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__invert_in$10$next[0:0]$7025
- attribute \src "libresoc.v:144777.3-144778.67"
- wire $0\logical_op__invert_in$10[0:0]$6988
- attribute \src "libresoc.v:144330.7-144330.40"
- wire $0\logical_op__invert_in$10[0:0]$7092
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__invert_out$13$next[0:0]$7026
- attribute \src "libresoc.v:144783.3-144784.69"
- wire $0\logical_op__invert_out$13[0:0]$6994
- attribute \src "libresoc.v:144339.7-144339.41"
- wire $0\logical_op__invert_out$13[0:0]$7094
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__is_32bit$16$next[0:0]$7027
- attribute \src "libresoc.v:144789.3-144790.65"
- wire $0\logical_op__is_32bit$16[0:0]$7000
- attribute \src "libresoc.v:144348.7-144348.39"
- wire $0\logical_op__is_32bit$16[0:0]$7096
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__is_signed$17$next[0:0]$7028
- attribute \src "libresoc.v:144791.3-144792.67"
- wire $0\logical_op__is_signed$17[0:0]$7002
- attribute \src "libresoc.v:144357.7-144357.40"
- wire $0\logical_op__is_signed$17[0:0]$7098
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__oe__oe$8$next[0:0]$7029
- attribute \src "libresoc.v:144773.3-144774.59"
- wire $0\logical_op__oe__oe$8[0:0]$6984
- attribute \src "libresoc.v:144368.7-144368.36"
- wire $0\logical_op__oe__oe$8[0:0]$7100
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__oe__ok$9$next[0:0]$7030
- attribute \src "libresoc.v:144775.3-144776.59"
- wire $0\logical_op__oe__ok$9[0:0]$6986
- attribute \src "libresoc.v:144377.7-144377.36"
- wire $0\logical_op__oe__ok$9[0:0]$7102
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__output_carry$15$next[0:0]$7031
- attribute \src "libresoc.v:144787.3-144788.73"
- wire $0\logical_op__output_carry$15[0:0]$6998
- attribute \src "libresoc.v:144384.7-144384.43"
- wire $0\logical_op__output_carry$15[0:0]$7104
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__rc__ok$7$next[0:0]$7032
- attribute \src "libresoc.v:144771.3-144772.59"
- wire $0\logical_op__rc__ok$7[0:0]$6982
- attribute \src "libresoc.v:144395.7-144395.36"
- wire $0\logical_op__rc__ok$7[0:0]$7106
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__rc__rc$6$next[0:0]$7033
- attribute \src "libresoc.v:144769.3-144770.59"
- wire $0\logical_op__rc__rc$6[0:0]$6980
- attribute \src "libresoc.v:144404.7-144404.36"
- wire $0\logical_op__rc__rc$6[0:0]$7108
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__write_cr0$14$next[0:0]$7034
- attribute \src "libresoc.v:144785.3-144786.67"
- wire $0\logical_op__write_cr0$14[0:0]$6996
- attribute \src "libresoc.v:144411.7-144411.40"
- wire $0\logical_op__write_cr0$14[0:0]$7110
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $0\logical_op__zero_a$11$next[0:0]$7035
- attribute \src "libresoc.v:144779.3-144780.61"
- wire $0\logical_op__zero_a$11[0:0]$6990
- attribute \src "libresoc.v:144420.7-144420.37"
- wire $0\logical_op__zero_a$11[0:0]$7112
- attribute \src "libresoc.v:144875.3-144887.6"
- wire width 2 $0\muxid$1$next[1:0]$7015
- attribute \src "libresoc.v:144797.3-144798.33"
- wire width 2 $0\muxid$1[1:0]$7008
- attribute \src "libresoc.v:144429.13-144429.29"
- wire width 2 $0\muxid$1[1:0]$7114
- attribute \src "libresoc.v:144930.3-144948.6"
- wire width 64 $0\o$20$next[63:0]$7061
- attribute \src "libresoc.v:144757.3-144758.27"
- wire width 64 $0\o$20[63:0]$6968
- attribute \src "libresoc.v:144444.14-144444.43"
- wire width 64 $0\o$20[63:0]$7116
- attribute \src "libresoc.v:144930.3-144948.6"
- wire $0\o_ok$21$next[0:0]$7062
- attribute \src "libresoc.v:144759.3-144760.33"
- wire $0\o_ok$21[0:0]$6970
- attribute \src "libresoc.v:144453.7-144453.23"
- wire $0\o_ok$21[0:0]$7118
- attribute \src "libresoc.v:144857.3-144874.6"
- wire $0\r_busy$next[0:0]$7011
- attribute \src "libresoc.v:144799.3-144800.29"
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 13 $0\logical_op__fn_unit$3$next[12:0]$6945
+ attribute \src "libresoc.v:142893.3-142894.61"
+ wire width 13 $0\logical_op__fn_unit$3[12:0]$6900
+ attribute \src "libresoc.v:142158.14-142158.48"
+ wire width 13 $0\logical_op__fn_unit$3[12:0]$7006
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6946
+ attribute \src "libresoc.v:142895.3-142896.75"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$6902
+ attribute \src "libresoc.v:142181.14-142181.67"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$7008
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__imm_data__ok$5$next[0:0]$6947
+ attribute \src "libresoc.v:142897.3-142898.71"
+ wire $0\logical_op__imm_data__ok$5[0:0]$6904
+ attribute \src "libresoc.v:142190.7-142190.42"
+ wire $0\logical_op__imm_data__ok$5[0:0]$7010
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 2 $0\logical_op__input_carry$12$next[1:0]$6948
+ attribute \src "libresoc.v:142911.3-142912.71"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$6918
+ attribute \src "libresoc.v:142207.13-142207.48"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$7012
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 32 $0\logical_op__insn$19$next[31:0]$6949
+ attribute \src "libresoc.v:142925.3-142926.57"
+ wire width 32 $0\logical_op__insn$19[31:0]$6932
+ attribute \src "libresoc.v:142220.14-142220.43"
+ wire width 32 $0\logical_op__insn$19[31:0]$7014
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 7 $0\logical_op__insn_type$2$next[6:0]$6950
+ attribute \src "libresoc.v:142891.3-142892.65"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$6898
+ attribute \src "libresoc.v:142377.13-142377.46"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$7016
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__invert_in$10$next[0:0]$6951
+ attribute \src "libresoc.v:142907.3-142908.67"
+ wire $0\logical_op__invert_in$10[0:0]$6914
+ attribute \src "libresoc.v:142460.7-142460.40"
+ wire $0\logical_op__invert_in$10[0:0]$7018
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__invert_out$13$next[0:0]$6952
+ attribute \src "libresoc.v:142913.3-142914.69"
+ wire $0\logical_op__invert_out$13[0:0]$6920
+ attribute \src "libresoc.v:142469.7-142469.41"
+ wire $0\logical_op__invert_out$13[0:0]$7020
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__is_32bit$16$next[0:0]$6953
+ attribute \src "libresoc.v:142919.3-142920.65"
+ wire $0\logical_op__is_32bit$16[0:0]$6926
+ attribute \src "libresoc.v:142478.7-142478.39"
+ wire $0\logical_op__is_32bit$16[0:0]$7022
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__is_signed$17$next[0:0]$6954
+ attribute \src "libresoc.v:142921.3-142922.67"
+ wire $0\logical_op__is_signed$17[0:0]$6928
+ attribute \src "libresoc.v:142487.7-142487.40"
+ wire $0\logical_op__is_signed$17[0:0]$7024
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__oe__oe$8$next[0:0]$6955
+ attribute \src "libresoc.v:142903.3-142904.59"
+ wire $0\logical_op__oe__oe$8[0:0]$6910
+ attribute \src "libresoc.v:142498.7-142498.36"
+ wire $0\logical_op__oe__oe$8[0:0]$7026
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__oe__ok$9$next[0:0]$6956
+ attribute \src "libresoc.v:142905.3-142906.59"
+ wire $0\logical_op__oe__ok$9[0:0]$6912
+ attribute \src "libresoc.v:142507.7-142507.36"
+ wire $0\logical_op__oe__ok$9[0:0]$7028
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__output_carry$15$next[0:0]$6957
+ attribute \src "libresoc.v:142917.3-142918.73"
+ wire $0\logical_op__output_carry$15[0:0]$6924
+ attribute \src "libresoc.v:142514.7-142514.43"
+ wire $0\logical_op__output_carry$15[0:0]$7030
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__rc__ok$7$next[0:0]$6958
+ attribute \src "libresoc.v:142901.3-142902.59"
+ wire $0\logical_op__rc__ok$7[0:0]$6908
+ attribute \src "libresoc.v:142525.7-142525.36"
+ wire $0\logical_op__rc__ok$7[0:0]$7032
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__rc__rc$6$next[0:0]$6959
+ attribute \src "libresoc.v:142899.3-142900.59"
+ wire $0\logical_op__rc__rc$6[0:0]$6906
+ attribute \src "libresoc.v:142534.7-142534.36"
+ wire $0\logical_op__rc__rc$6[0:0]$7034
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__write_cr0$14$next[0:0]$6960
+ attribute \src "libresoc.v:142915.3-142916.67"
+ wire $0\logical_op__write_cr0$14[0:0]$6922
+ attribute \src "libresoc.v:142541.7-142541.40"
+ wire $0\logical_op__write_cr0$14[0:0]$7036
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $0\logical_op__zero_a$11$next[0:0]$6961
+ attribute \src "libresoc.v:142909.3-142910.61"
+ wire $0\logical_op__zero_a$11[0:0]$6916
+ attribute \src "libresoc.v:142550.7-142550.37"
+ wire $0\logical_op__zero_a$11[0:0]$7038
+ attribute \src "libresoc.v:143005.3-143017.6"
+ wire width 2 $0\muxid$1$next[1:0]$6941
+ attribute \src "libresoc.v:142927.3-142928.33"
+ wire width 2 $0\muxid$1[1:0]$6934
+ attribute \src "libresoc.v:142559.13-142559.29"
+ wire width 2 $0\muxid$1[1:0]$7040
+ attribute \src "libresoc.v:143060.3-143078.6"
+ wire width 64 $0\o$20$next[63:0]$6987
+ attribute \src "libresoc.v:142887.3-142888.27"
+ wire width 64 $0\o$20[63:0]$6894
+ attribute \src "libresoc.v:142574.14-142574.43"
+ wire width 64 $0\o$20[63:0]$7042
+ attribute \src "libresoc.v:143060.3-143078.6"
+ wire $0\o_ok$21$next[0:0]$6988
+ attribute \src "libresoc.v:142889.3-142890.33"
+ wire $0\o_ok$21[0:0]$6896
+ attribute \src "libresoc.v:142583.7-142583.23"
+ wire $0\o_ok$21[0:0]$7044
+ attribute \src "libresoc.v:142987.3-143004.6"
+ wire $0\r_busy$next[0:0]$6937
+ attribute \src "libresoc.v:142929.3-142930.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:144949.3-144967.6"
- wire width 4 $1\cr_a$22$next[3:0]$7069
- attribute \src "libresoc.v:144949.3-144967.6"
- wire $1\cr_a_ok$23$next[0:0]$7070
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 4 $1\logical_op__data_len$18$next[3:0]$7036
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 13 $1\logical_op__fn_unit$3$next[12:0]$7037
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7038
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__imm_data__ok$5$next[0:0]$7039
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 2 $1\logical_op__input_carry$12$next[1:0]$7040
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 32 $1\logical_op__insn$19$next[31:0]$7041
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 7 $1\logical_op__insn_type$2$next[6:0]$7042
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__invert_in$10$next[0:0]$7043
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__invert_out$13$next[0:0]$7044
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__is_32bit$16$next[0:0]$7045
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__is_signed$17$next[0:0]$7046
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__oe__oe$8$next[0:0]$7047
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__oe__ok$9$next[0:0]$7048
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__output_carry$15$next[0:0]$7049
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__rc__ok$7$next[0:0]$7050
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__rc__rc$6$next[0:0]$7051
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__write_cr0$14$next[0:0]$7052
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $1\logical_op__zero_a$11$next[0:0]$7053
- attribute \src "libresoc.v:144875.3-144887.6"
- wire width 2 $1\muxid$1$next[1:0]$7016
- attribute \src "libresoc.v:144930.3-144948.6"
- wire width 64 $1\o$20$next[63:0]$7063
- attribute \src "libresoc.v:144930.3-144948.6"
- wire $1\o_ok$21$next[0:0]$7064
- attribute \src "libresoc.v:144857.3-144874.6"
- wire $1\r_busy$next[0:0]$7012
- attribute \src "libresoc.v:144743.7-144743.20"
+ attribute \src "libresoc.v:143079.3-143097.6"
+ wire width 4 $1\cr_a$22$next[3:0]$6995
+ attribute \src "libresoc.v:143079.3-143097.6"
+ wire $1\cr_a_ok$23$next[0:0]$6996
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 4 $1\logical_op__data_len$18$next[3:0]$6962
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 13 $1\logical_op__fn_unit$3$next[12:0]$6963
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6964
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__imm_data__ok$5$next[0:0]$6965
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 2 $1\logical_op__input_carry$12$next[1:0]$6966
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 32 $1\logical_op__insn$19$next[31:0]$6967
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 7 $1\logical_op__insn_type$2$next[6:0]$6968
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__invert_in$10$next[0:0]$6969
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__invert_out$13$next[0:0]$6970
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__is_32bit$16$next[0:0]$6971
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__is_signed$17$next[0:0]$6972
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__oe__oe$8$next[0:0]$6973
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__oe__ok$9$next[0:0]$6974
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__output_carry$15$next[0:0]$6975
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__rc__ok$7$next[0:0]$6976
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__rc__rc$6$next[0:0]$6977
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__write_cr0$14$next[0:0]$6978
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $1\logical_op__zero_a$11$next[0:0]$6979
+ attribute \src "libresoc.v:143005.3-143017.6"
+ wire width 2 $1\muxid$1$next[1:0]$6942
+ attribute \src "libresoc.v:143060.3-143078.6"
+ wire width 64 $1\o$20$next[63:0]$6989
+ attribute \src "libresoc.v:143060.3-143078.6"
+ wire $1\o_ok$21$next[0:0]$6990
+ attribute \src "libresoc.v:142987.3-143004.6"
+ wire $1\r_busy$next[0:0]$6938
+ attribute \src "libresoc.v:142873.7-142873.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:144949.3-144967.6"
- wire $2\cr_a_ok$23$next[0:0]$7071
- attribute \src "libresoc.v:144888.3-144929.6"
- wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7054
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $2\logical_op__imm_data__ok$5$next[0:0]$7055
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $2\logical_op__oe__oe$8$next[0:0]$7056
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $2\logical_op__oe__ok$9$next[0:0]$7057
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $2\logical_op__rc__ok$7$next[0:0]$7058
- attribute \src "libresoc.v:144888.3-144929.6"
- wire $2\logical_op__rc__rc$6$next[0:0]$7059
- attribute \src "libresoc.v:144930.3-144948.6"
- wire $2\o_ok$21$next[0:0]$7065
- attribute \src "libresoc.v:144857.3-144874.6"
- wire $2\r_busy$next[0:0]$7013
- attribute \src "libresoc.v:144752.18-144752.118"
- wire $and$libresoc.v:144752$6962_Y
+ attribute \src "libresoc.v:143079.3-143097.6"
+ wire $2\cr_a_ok$23$next[0:0]$6997
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6980
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $2\logical_op__imm_data__ok$5$next[0:0]$6981
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $2\logical_op__oe__oe$8$next[0:0]$6982
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $2\logical_op__oe__ok$9$next[0:0]$6983
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $2\logical_op__rc__ok$7$next[0:0]$6984
+ attribute \src "libresoc.v:143018.3-143059.6"
+ wire $2\logical_op__rc__rc$6$next[0:0]$6985
+ attribute \src "libresoc.v:143060.3-143078.6"
+ wire $2\o_ok$21$next[0:0]$6991
+ attribute \src "libresoc.v:142987.3-143004.6"
+ wire $2\r_busy$next[0:0]$6939
+ attribute \src "libresoc.v:142882.18-142882.118"
+ wire $and$libresoc.v:142882$6888_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 54 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 25 \cr_a
wire \cr_a_ok$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$73
- attribute \src "libresoc.v:143960.7-143960.15"
+ attribute \src "libresoc.v:142090.7-142090.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$47
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:144752$6962
+ cell $and $and$libresoc.v:142882$6888
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$48
connect \B \p_ready_o
- connect \Y $and$libresoc.v:144752$6962_Y
+ connect \Y $and$libresoc.v:142882$6888_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144801.10-144804.4"
+ attribute \src "libresoc.v:142931.10-142934.4"
cell \n$53 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144805.15-144852.4"
+ attribute \src "libresoc.v:142935.15-142982.4"
cell \output$54 \output
connect \cr_a \output_cr_a
connect \cr_a$22 \output_cr_a$45
connect \xer_so \output_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:144853.10-144856.4"
+ attribute \src "libresoc.v:142983.10-142986.4"
cell \p$52 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:143960.7-143960.20"
- process $proc$libresoc.v:143960$7072
+ attribute \src "libresoc.v:142090.7-142090.20"
+ process $proc$libresoc.v:142090$6998
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:143971.13-143971.29"
- process $proc$libresoc.v:143971$7073
+ attribute \src "libresoc.v:142101.13-142101.29"
+ process $proc$libresoc.v:142101$6999
assign { } { }
- assign $0\cr_a$22[3:0]$7074 4'0000
+ assign $0\cr_a$22[3:0]$7000 4'0000
sync always
sync init
- update \cr_a$22 $0\cr_a$22[3:0]$7074
+ update \cr_a$22 $0\cr_a$22[3:0]$7000
end
- attribute \src "libresoc.v:143980.7-143980.26"
- process $proc$libresoc.v:143980$7075
+ attribute \src "libresoc.v:142110.7-142110.26"
+ process $proc$libresoc.v:142110$7001
assign { } { }
- assign $0\cr_a_ok$23[0:0]$7076 1'0
+ assign $0\cr_a_ok$23[0:0]$7002 1'0
sync always
sync init
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7076
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7002
end
- attribute \src "libresoc.v:143991.13-143991.45"
- process $proc$libresoc.v:143991$7077
+ attribute \src "libresoc.v:142121.13-142121.45"
+ process $proc$libresoc.v:142121$7003
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$7078 4'0000
+ assign $0\logical_op__data_len$18[3:0]$7004 4'0000
sync always
sync init
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7078
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7004
end
- attribute \src "libresoc.v:144028.14-144028.48"
- process $proc$libresoc.v:144028$7079
+ attribute \src "libresoc.v:142158.14-142158.48"
+ process $proc$libresoc.v:142158$7005
assign { } { }
- assign $0\logical_op__fn_unit$3[12:0]$7080 13'0000000000000
+ assign $0\logical_op__fn_unit$3[12:0]$7006 13'0000000000000
sync always
sync init
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7080
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7006
end
- attribute \src "libresoc.v:144051.14-144051.67"
- process $proc$libresoc.v:144051$7081
+ attribute \src "libresoc.v:142181.14-142181.67"
+ process $proc$libresoc.v:142181$7007
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$7082 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$4[63:0]$7008 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7082
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7008
end
- attribute \src "libresoc.v:144060.7-144060.42"
- process $proc$libresoc.v:144060$7083
+ attribute \src "libresoc.v:142190.7-142190.42"
+ process $proc$libresoc.v:142190$7009
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$7084 1'0
+ assign $0\logical_op__imm_data__ok$5[0:0]$7010 1'0
sync always
sync init
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7084
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7010
end
- attribute \src "libresoc.v:144077.13-144077.48"
- process $proc$libresoc.v:144077$7085
+ attribute \src "libresoc.v:142207.13-142207.48"
+ process $proc$libresoc.v:142207$7011
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$7086 2'00
+ assign $0\logical_op__input_carry$12[1:0]$7012 2'00
sync always
sync init
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7086
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7012
end
- attribute \src "libresoc.v:144090.14-144090.43"
- process $proc$libresoc.v:144090$7087
+ attribute \src "libresoc.v:142220.14-142220.43"
+ process $proc$libresoc.v:142220$7013
assign { } { }
- assign $0\logical_op__insn$19[31:0]$7088 0
+ assign $0\logical_op__insn$19[31:0]$7014 0
sync always
sync init
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7088
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7014
end
- attribute \src "libresoc.v:144247.13-144247.46"
- process $proc$libresoc.v:144247$7089
+ attribute \src "libresoc.v:142377.13-142377.46"
+ process $proc$libresoc.v:142377$7015
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$7090 7'0000000
+ assign $0\logical_op__insn_type$2[6:0]$7016 7'0000000
sync always
sync init
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7090
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7016
end
- attribute \src "libresoc.v:144330.7-144330.40"
- process $proc$libresoc.v:144330$7091
+ attribute \src "libresoc.v:142460.7-142460.40"
+ process $proc$libresoc.v:142460$7017
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$7092 1'0
+ assign $0\logical_op__invert_in$10[0:0]$7018 1'0
sync always
sync init
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7092
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7018
end
- attribute \src "libresoc.v:144339.7-144339.41"
- process $proc$libresoc.v:144339$7093
+ attribute \src "libresoc.v:142469.7-142469.41"
+ process $proc$libresoc.v:142469$7019
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$7094 1'0
+ assign $0\logical_op__invert_out$13[0:0]$7020 1'0
sync always
sync init
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7094
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7020
end
- attribute \src "libresoc.v:144348.7-144348.39"
- process $proc$libresoc.v:144348$7095
+ attribute \src "libresoc.v:142478.7-142478.39"
+ process $proc$libresoc.v:142478$7021
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$7096 1'0
+ assign $0\logical_op__is_32bit$16[0:0]$7022 1'0
sync always
sync init
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7096
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7022
end
- attribute \src "libresoc.v:144357.7-144357.40"
- process $proc$libresoc.v:144357$7097
+ attribute \src "libresoc.v:142487.7-142487.40"
+ process $proc$libresoc.v:142487$7023
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$7098 1'0
+ assign $0\logical_op__is_signed$17[0:0]$7024 1'0
sync always
sync init
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7098
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7024
end
- attribute \src "libresoc.v:144368.7-144368.36"
- process $proc$libresoc.v:144368$7099
+ attribute \src "libresoc.v:142498.7-142498.36"
+ process $proc$libresoc.v:142498$7025
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$7100 1'0
+ assign $0\logical_op__oe__oe$8[0:0]$7026 1'0
sync always
sync init
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7100
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7026
end
- attribute \src "libresoc.v:144377.7-144377.36"
- process $proc$libresoc.v:144377$7101
+ attribute \src "libresoc.v:142507.7-142507.36"
+ process $proc$libresoc.v:142507$7027
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$7102 1'0
+ assign $0\logical_op__oe__ok$9[0:0]$7028 1'0
sync always
sync init
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7102
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7028
end
- attribute \src "libresoc.v:144384.7-144384.43"
- process $proc$libresoc.v:144384$7103
+ attribute \src "libresoc.v:142514.7-142514.43"
+ process $proc$libresoc.v:142514$7029
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$7104 1'0
+ assign $0\logical_op__output_carry$15[0:0]$7030 1'0
sync always
sync init
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7104
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7030
end
- attribute \src "libresoc.v:144395.7-144395.36"
- process $proc$libresoc.v:144395$7105
+ attribute \src "libresoc.v:142525.7-142525.36"
+ process $proc$libresoc.v:142525$7031
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$7106 1'0
+ assign $0\logical_op__rc__ok$7[0:0]$7032 1'0
sync always
sync init
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7106
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7032
end
- attribute \src "libresoc.v:144404.7-144404.36"
- process $proc$libresoc.v:144404$7107
+ attribute \src "libresoc.v:142534.7-142534.36"
+ process $proc$libresoc.v:142534$7033
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$7108 1'0
+ assign $0\logical_op__rc__rc$6[0:0]$7034 1'0
sync always
sync init
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7108
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7034
end
- attribute \src "libresoc.v:144411.7-144411.40"
- process $proc$libresoc.v:144411$7109
+ attribute \src "libresoc.v:142541.7-142541.40"
+ process $proc$libresoc.v:142541$7035
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$7110 1'0
+ assign $0\logical_op__write_cr0$14[0:0]$7036 1'0
sync always
sync init
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7110
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7036
end
- attribute \src "libresoc.v:144420.7-144420.37"
- process $proc$libresoc.v:144420$7111
+ attribute \src "libresoc.v:142550.7-142550.37"
+ process $proc$libresoc.v:142550$7037
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$7112 1'0
+ assign $0\logical_op__zero_a$11[0:0]$7038 1'0
sync always
sync init
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7112
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7038
end
- attribute \src "libresoc.v:144429.13-144429.29"
- process $proc$libresoc.v:144429$7113
+ attribute \src "libresoc.v:142559.13-142559.29"
+ process $proc$libresoc.v:142559$7039
assign { } { }
- assign $0\muxid$1[1:0]$7114 2'00
+ assign $0\muxid$1[1:0]$7040 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$7114
+ update \muxid$1 $0\muxid$1[1:0]$7040
end
- attribute \src "libresoc.v:144444.14-144444.43"
- process $proc$libresoc.v:144444$7115
+ attribute \src "libresoc.v:142574.14-142574.43"
+ process $proc$libresoc.v:142574$7041
assign { } { }
- assign $0\o$20[63:0]$7116 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$20[63:0]$7042 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$20 $0\o$20[63:0]$7116
+ update \o$20 $0\o$20[63:0]$7042
end
- attribute \src "libresoc.v:144453.7-144453.23"
- process $proc$libresoc.v:144453$7117
+ attribute \src "libresoc.v:142583.7-142583.23"
+ process $proc$libresoc.v:142583$7043
assign { } { }
- assign $0\o_ok$21[0:0]$7118 1'0
+ assign $0\o_ok$21[0:0]$7044 1'0
sync always
sync init
- update \o_ok$21 $0\o_ok$21[0:0]$7118
+ update \o_ok$21 $0\o_ok$21[0:0]$7044
end
- attribute \src "libresoc.v:144743.7-144743.20"
- process $proc$libresoc.v:144743$7119
+ attribute \src "libresoc.v:142873.7-142873.20"
+ process $proc$libresoc.v:142873$7045
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:144753.3-144754.33"
- process $proc$libresoc.v:144753$6963
+ attribute \src "libresoc.v:142883.3-142884.33"
+ process $proc$libresoc.v:142883$6889
assign { } { }
- assign $0\cr_a$22[3:0]$6964 \cr_a$22$next
+ assign $0\cr_a$22[3:0]$6890 \cr_a$22$next
sync posedge \coresync_clk
- update \cr_a$22 $0\cr_a$22[3:0]$6964
+ update \cr_a$22 $0\cr_a$22[3:0]$6890
end
- attribute \src "libresoc.v:144755.3-144756.39"
- process $proc$libresoc.v:144755$6965
+ attribute \src "libresoc.v:142885.3-142886.39"
+ process $proc$libresoc.v:142885$6891
assign { } { }
- assign $0\cr_a_ok$23[0:0]$6966 \cr_a_ok$23$next
+ assign $0\cr_a_ok$23[0:0]$6892 \cr_a_ok$23$next
sync posedge \coresync_clk
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6966
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6892
end
- attribute \src "libresoc.v:144757.3-144758.27"
- process $proc$libresoc.v:144757$6967
+ attribute \src "libresoc.v:142887.3-142888.27"
+ process $proc$libresoc.v:142887$6893
assign { } { }
- assign $0\o$20[63:0]$6968 \o$20$next
+ assign $0\o$20[63:0]$6894 \o$20$next
sync posedge \coresync_clk
- update \o$20 $0\o$20[63:0]$6968
+ update \o$20 $0\o$20[63:0]$6894
end
- attribute \src "libresoc.v:144759.3-144760.33"
- process $proc$libresoc.v:144759$6969
+ attribute \src "libresoc.v:142889.3-142890.33"
+ process $proc$libresoc.v:142889$6895
assign { } { }
- assign $0\o_ok$21[0:0]$6970 \o_ok$21$next
+ assign $0\o_ok$21[0:0]$6896 \o_ok$21$next
sync posedge \coresync_clk
- update \o_ok$21 $0\o_ok$21[0:0]$6970
+ update \o_ok$21 $0\o_ok$21[0:0]$6896
end
- attribute \src "libresoc.v:144761.3-144762.65"
- process $proc$libresoc.v:144761$6971
+ attribute \src "libresoc.v:142891.3-142892.65"
+ process $proc$libresoc.v:142891$6897
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$6972 \logical_op__insn_type$2$next
+ assign $0\logical_op__insn_type$2[6:0]$6898 \logical_op__insn_type$2$next
sync posedge \coresync_clk
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6972
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6898
end
- attribute \src "libresoc.v:144763.3-144764.61"
- process $proc$libresoc.v:144763$6973
+ attribute \src "libresoc.v:142893.3-142894.61"
+ process $proc$libresoc.v:142893$6899
assign { } { }
- assign $0\logical_op__fn_unit$3[12:0]$6974 \logical_op__fn_unit$3$next
+ assign $0\logical_op__fn_unit$3[12:0]$6900 \logical_op__fn_unit$3$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6974
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6900
end
- attribute \src "libresoc.v:144765.3-144766.75"
- process $proc$libresoc.v:144765$6975
+ attribute \src "libresoc.v:142895.3-142896.75"
+ process $proc$libresoc.v:142895$6901
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$6976 \logical_op__imm_data__data$4$next
+ assign $0\logical_op__imm_data__data$4[63:0]$6902 \logical_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6976
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6902
end
- attribute \src "libresoc.v:144767.3-144768.71"
- process $proc$libresoc.v:144767$6977
+ attribute \src "libresoc.v:142897.3-142898.71"
+ process $proc$libresoc.v:142897$6903
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$6978 \logical_op__imm_data__ok$5$next
+ assign $0\logical_op__imm_data__ok$5[0:0]$6904 \logical_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6978
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6904
end
- attribute \src "libresoc.v:144769.3-144770.59"
- process $proc$libresoc.v:144769$6979
+ attribute \src "libresoc.v:142899.3-142900.59"
+ process $proc$libresoc.v:142899$6905
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$6980 \logical_op__rc__rc$6$next
+ assign $0\logical_op__rc__rc$6[0:0]$6906 \logical_op__rc__rc$6$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6980
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6906
end
- attribute \src "libresoc.v:144771.3-144772.59"
- process $proc$libresoc.v:144771$6981
+ attribute \src "libresoc.v:142901.3-142902.59"
+ process $proc$libresoc.v:142901$6907
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$6982 \logical_op__rc__ok$7$next
+ assign $0\logical_op__rc__ok$7[0:0]$6908 \logical_op__rc__ok$7$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6982
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6908
end
- attribute \src "libresoc.v:144773.3-144774.59"
- process $proc$libresoc.v:144773$6983
+ attribute \src "libresoc.v:142903.3-142904.59"
+ process $proc$libresoc.v:142903$6909
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$6984 \logical_op__oe__oe$8$next
+ assign $0\logical_op__oe__oe$8[0:0]$6910 \logical_op__oe__oe$8$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6984
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6910
end
- attribute \src "libresoc.v:144775.3-144776.59"
- process $proc$libresoc.v:144775$6985
+ attribute \src "libresoc.v:142905.3-142906.59"
+ process $proc$libresoc.v:142905$6911
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$6986 \logical_op__oe__ok$9$next
+ assign $0\logical_op__oe__ok$9[0:0]$6912 \logical_op__oe__ok$9$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6986
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6912
end
- attribute \src "libresoc.v:144777.3-144778.67"
- process $proc$libresoc.v:144777$6987
+ attribute \src "libresoc.v:142907.3-142908.67"
+ process $proc$libresoc.v:142907$6913
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$6988 \logical_op__invert_in$10$next
+ assign $0\logical_op__invert_in$10[0:0]$6914 \logical_op__invert_in$10$next
sync posedge \coresync_clk
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6988
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6914
end
- attribute \src "libresoc.v:144779.3-144780.61"
- process $proc$libresoc.v:144779$6989
+ attribute \src "libresoc.v:142909.3-142910.61"
+ process $proc$libresoc.v:142909$6915
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$6990 \logical_op__zero_a$11$next
+ assign $0\logical_op__zero_a$11[0:0]$6916 \logical_op__zero_a$11$next
sync posedge \coresync_clk
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6990
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6916
end
- attribute \src "libresoc.v:144781.3-144782.71"
- process $proc$libresoc.v:144781$6991
+ attribute \src "libresoc.v:142911.3-142912.71"
+ process $proc$libresoc.v:142911$6917
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$6992 \logical_op__input_carry$12$next
+ assign $0\logical_op__input_carry$12[1:0]$6918 \logical_op__input_carry$12$next
sync posedge \coresync_clk
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6992
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6918
end
- attribute \src "libresoc.v:144783.3-144784.69"
- process $proc$libresoc.v:144783$6993
+ attribute \src "libresoc.v:142913.3-142914.69"
+ process $proc$libresoc.v:142913$6919
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$6994 \logical_op__invert_out$13$next
+ assign $0\logical_op__invert_out$13[0:0]$6920 \logical_op__invert_out$13$next
sync posedge \coresync_clk
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6994
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6920
end
- attribute \src "libresoc.v:144785.3-144786.67"
- process $proc$libresoc.v:144785$6995
+ attribute \src "libresoc.v:142915.3-142916.67"
+ process $proc$libresoc.v:142915$6921
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$6996 \logical_op__write_cr0$14$next
+ assign $0\logical_op__write_cr0$14[0:0]$6922 \logical_op__write_cr0$14$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6996
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6922
end
- attribute \src "libresoc.v:144787.3-144788.73"
- process $proc$libresoc.v:144787$6997
+ attribute \src "libresoc.v:142917.3-142918.73"
+ process $proc$libresoc.v:142917$6923
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$6998 \logical_op__output_carry$15$next
+ assign $0\logical_op__output_carry$15[0:0]$6924 \logical_op__output_carry$15$next
sync posedge \coresync_clk
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6998
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6924
end
- attribute \src "libresoc.v:144789.3-144790.65"
- process $proc$libresoc.v:144789$6999
+ attribute \src "libresoc.v:142919.3-142920.65"
+ process $proc$libresoc.v:142919$6925
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$7000 \logical_op__is_32bit$16$next
+ assign $0\logical_op__is_32bit$16[0:0]$6926 \logical_op__is_32bit$16$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7000
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6926
end
- attribute \src "libresoc.v:144791.3-144792.67"
- process $proc$libresoc.v:144791$7001
+ attribute \src "libresoc.v:142921.3-142922.67"
+ process $proc$libresoc.v:142921$6927
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$7002 \logical_op__is_signed$17$next
+ assign $0\logical_op__is_signed$17[0:0]$6928 \logical_op__is_signed$17$next
sync posedge \coresync_clk
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7002
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6928
end
- attribute \src "libresoc.v:144793.3-144794.65"
- process $proc$libresoc.v:144793$7003
+ attribute \src "libresoc.v:142923.3-142924.65"
+ process $proc$libresoc.v:142923$6929
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$7004 \logical_op__data_len$18$next
+ assign $0\logical_op__data_len$18[3:0]$6930 \logical_op__data_len$18$next
sync posedge \coresync_clk
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7004
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6930
end
- attribute \src "libresoc.v:144795.3-144796.57"
- process $proc$libresoc.v:144795$7005
+ attribute \src "libresoc.v:142925.3-142926.57"
+ process $proc$libresoc.v:142925$6931
assign { } { }
- assign $0\logical_op__insn$19[31:0]$7006 \logical_op__insn$19$next
+ assign $0\logical_op__insn$19[31:0]$6932 \logical_op__insn$19$next
sync posedge \coresync_clk
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7006
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6932
end
- attribute \src "libresoc.v:144797.3-144798.33"
- process $proc$libresoc.v:144797$7007
+ attribute \src "libresoc.v:142927.3-142928.33"
+ process $proc$libresoc.v:142927$6933
assign { } { }
- assign $0\muxid$1[1:0]$7008 \muxid$1$next
+ assign $0\muxid$1[1:0]$6934 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$7008
+ update \muxid$1 $0\muxid$1[1:0]$6934
end
- attribute \src "libresoc.v:144799.3-144800.29"
- process $proc$libresoc.v:144799$7009
+ attribute \src "libresoc.v:142929.3-142930.29"
+ process $proc$libresoc.v:142929$6935
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:144857.3-144874.6"
- process $proc$libresoc.v:144857$7010
+ attribute \src "libresoc.v:142987.3-143004.6"
+ process $proc$libresoc.v:142987$6936
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$7011 $2\r_busy$next[0:0]$7013
- attribute \src "libresoc.v:144858.5-144858.29"
+ assign $0\r_busy$next[0:0]$6937 $2\r_busy$next[0:0]$6939
+ attribute \src "libresoc.v:142988.5-142988.29"
switch \initial
- attribute \src "libresoc.v:144858.9-144858.17"
+ attribute \src "libresoc.v:142988.9-142988.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$7012 1'1
+ assign $1\r_busy$next[0:0]$6938 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$7012 1'0
+ assign $1\r_busy$next[0:0]$6938 1'0
case
- assign $1\r_busy$next[0:0]$7012 \r_busy
+ assign $1\r_busy$next[0:0]$6938 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$7013 1'0
+ assign $2\r_busy$next[0:0]$6939 1'0
case
- assign $2\r_busy$next[0:0]$7013 $1\r_busy$next[0:0]$7012
+ assign $2\r_busy$next[0:0]$6939 $1\r_busy$next[0:0]$6938
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$7011
+ update \r_busy$next $0\r_busy$next[0:0]$6937
end
- attribute \src "libresoc.v:144875.3-144887.6"
- process $proc$libresoc.v:144875$7014
+ attribute \src "libresoc.v:143005.3-143017.6"
+ process $proc$libresoc.v:143005$6940
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$7015 $1\muxid$1$next[1:0]$7016
- attribute \src "libresoc.v:144876.5-144876.29"
+ assign $0\muxid$1$next[1:0]$6941 $1\muxid$1$next[1:0]$6942
+ attribute \src "libresoc.v:143006.5-143006.29"
switch \initial
- attribute \src "libresoc.v:144876.9-144876.17"
+ attribute \src "libresoc.v:143006.9-143006.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$7016 \muxid$51
+ assign $1\muxid$1$next[1:0]$6942 \muxid$51
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$7016 \muxid$51
+ assign $1\muxid$1$next[1:0]$6942 \muxid$51
case
- assign $1\muxid$1$next[1:0]$7016 \muxid$1
+ assign $1\muxid$1$next[1:0]$6942 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$7015
+ update \muxid$1$next $0\muxid$1$next[1:0]$6941
end
- attribute \src "libresoc.v:144888.3-144929.6"
- process $proc$libresoc.v:144888$7017
+ attribute \src "libresoc.v:143018.3-143059.6"
+ process $proc$libresoc.v:143018$6943
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$18$next[3:0]$7018 $1\logical_op__data_len$18$next[3:0]$7036
- assign $0\logical_op__fn_unit$3$next[12:0]$7019 $1\logical_op__fn_unit$3$next[12:0]$7037
+ assign $0\logical_op__data_len$18$next[3:0]$6944 $1\logical_op__data_len$18$next[3:0]$6962
+ assign $0\logical_op__fn_unit$3$next[12:0]$6945 $1\logical_op__fn_unit$3$next[12:0]$6963
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$12$next[1:0]$7022 $1\logical_op__input_carry$12$next[1:0]$7040
- assign $0\logical_op__insn$19$next[31:0]$7023 $1\logical_op__insn$19$next[31:0]$7041
- assign $0\logical_op__insn_type$2$next[6:0]$7024 $1\logical_op__insn_type$2$next[6:0]$7042
- assign $0\logical_op__invert_in$10$next[0:0]$7025 $1\logical_op__invert_in$10$next[0:0]$7043
- assign $0\logical_op__invert_out$13$next[0:0]$7026 $1\logical_op__invert_out$13$next[0:0]$7044
- assign $0\logical_op__is_32bit$16$next[0:0]$7027 $1\logical_op__is_32bit$16$next[0:0]$7045
- assign $0\logical_op__is_signed$17$next[0:0]$7028 $1\logical_op__is_signed$17$next[0:0]$7046
+ assign $0\logical_op__input_carry$12$next[1:0]$6948 $1\logical_op__input_carry$12$next[1:0]$6966
+ assign $0\logical_op__insn$19$next[31:0]$6949 $1\logical_op__insn$19$next[31:0]$6967
+ assign $0\logical_op__insn_type$2$next[6:0]$6950 $1\logical_op__insn_type$2$next[6:0]$6968
+ assign $0\logical_op__invert_in$10$next[0:0]$6951 $1\logical_op__invert_in$10$next[0:0]$6969
+ assign $0\logical_op__invert_out$13$next[0:0]$6952 $1\logical_op__invert_out$13$next[0:0]$6970
+ assign $0\logical_op__is_32bit$16$next[0:0]$6953 $1\logical_op__is_32bit$16$next[0:0]$6971
+ assign $0\logical_op__is_signed$17$next[0:0]$6954 $1\logical_op__is_signed$17$next[0:0]$6972
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$15$next[0:0]$7031 $1\logical_op__output_carry$15$next[0:0]$7049
+ assign $0\logical_op__output_carry$15$next[0:0]$6957 $1\logical_op__output_carry$15$next[0:0]$6975
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$14$next[0:0]$7034 $1\logical_op__write_cr0$14$next[0:0]$7052
- assign $0\logical_op__zero_a$11$next[0:0]$7035 $1\logical_op__zero_a$11$next[0:0]$7053
- assign $0\logical_op__imm_data__data$4$next[63:0]$7020 $2\logical_op__imm_data__data$4$next[63:0]$7054
- assign $0\logical_op__imm_data__ok$5$next[0:0]$7021 $2\logical_op__imm_data__ok$5$next[0:0]$7055
- assign $0\logical_op__oe__oe$8$next[0:0]$7029 $2\logical_op__oe__oe$8$next[0:0]$7056
- assign $0\logical_op__oe__ok$9$next[0:0]$7030 $2\logical_op__oe__ok$9$next[0:0]$7057
- assign $0\logical_op__rc__ok$7$next[0:0]$7032 $2\logical_op__rc__ok$7$next[0:0]$7058
- assign $0\logical_op__rc__rc$6$next[0:0]$7033 $2\logical_op__rc__rc$6$next[0:0]$7059
- attribute \src "libresoc.v:144889.5-144889.29"
+ assign $0\logical_op__write_cr0$14$next[0:0]$6960 $1\logical_op__write_cr0$14$next[0:0]$6978
+ assign $0\logical_op__zero_a$11$next[0:0]$6961 $1\logical_op__zero_a$11$next[0:0]$6979
+ assign $0\logical_op__imm_data__data$4$next[63:0]$6946 $2\logical_op__imm_data__data$4$next[63:0]$6980
+ assign $0\logical_op__imm_data__ok$5$next[0:0]$6947 $2\logical_op__imm_data__ok$5$next[0:0]$6981
+ assign $0\logical_op__oe__oe$8$next[0:0]$6955 $2\logical_op__oe__oe$8$next[0:0]$6982
+ assign $0\logical_op__oe__ok$9$next[0:0]$6956 $2\logical_op__oe__ok$9$next[0:0]$6983
+ assign $0\logical_op__rc__ok$7$next[0:0]$6958 $2\logical_op__rc__ok$7$next[0:0]$6984
+ assign $0\logical_op__rc__rc$6$next[0:0]$6959 $2\logical_op__rc__rc$6$next[0:0]$6985
+ attribute \src "libresoc.v:143019.5-143019.29"
switch \initial
- attribute \src "libresoc.v:144889.9-144889.17"
+ attribute \src "libresoc.v:143019.9-143019.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$7041 $1\logical_op__data_len$18$next[3:0]$7036 $1\logical_op__is_signed$17$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7045 $1\logical_op__output_carry$15$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7052 $1\logical_op__invert_out$13$next[0:0]$7044 $1\logical_op__input_carry$12$next[1:0]$7040 $1\logical_op__zero_a$11$next[0:0]$7053 $1\logical_op__invert_in$10$next[0:0]$7043 $1\logical_op__oe__ok$9$next[0:0]$7048 $1\logical_op__oe__oe$8$next[0:0]$7047 $1\logical_op__rc__ok$7$next[0:0]$7050 $1\logical_op__rc__rc$6$next[0:0]$7051 $1\logical_op__imm_data__ok$5$next[0:0]$7039 $1\logical_op__imm_data__data$4$next[63:0]$7038 $1\logical_op__fn_unit$3$next[12:0]$7037 $1\logical_op__insn_type$2$next[6:0]$7042 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
+ assign { $1\logical_op__insn$19$next[31:0]$6967 $1\logical_op__data_len$18$next[3:0]$6962 $1\logical_op__is_signed$17$next[0:0]$6972 $1\logical_op__is_32bit$16$next[0:0]$6971 $1\logical_op__output_carry$15$next[0:0]$6975 $1\logical_op__write_cr0$14$next[0:0]$6978 $1\logical_op__invert_out$13$next[0:0]$6970 $1\logical_op__input_carry$12$next[1:0]$6966 $1\logical_op__zero_a$11$next[0:0]$6979 $1\logical_op__invert_in$10$next[0:0]$6969 $1\logical_op__oe__ok$9$next[0:0]$6974 $1\logical_op__oe__oe$8$next[0:0]$6973 $1\logical_op__rc__ok$7$next[0:0]$6976 $1\logical_op__rc__rc$6$next[0:0]$6977 $1\logical_op__imm_data__ok$5$next[0:0]$6965 $1\logical_op__imm_data__data$4$next[63:0]$6964 $1\logical_op__fn_unit$3$next[12:0]$6963 $1\logical_op__insn_type$2$next[6:0]$6968 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$7041 $1\logical_op__data_len$18$next[3:0]$7036 $1\logical_op__is_signed$17$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7045 $1\logical_op__output_carry$15$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7052 $1\logical_op__invert_out$13$next[0:0]$7044 $1\logical_op__input_carry$12$next[1:0]$7040 $1\logical_op__zero_a$11$next[0:0]$7053 $1\logical_op__invert_in$10$next[0:0]$7043 $1\logical_op__oe__ok$9$next[0:0]$7048 $1\logical_op__oe__oe$8$next[0:0]$7047 $1\logical_op__rc__ok$7$next[0:0]$7050 $1\logical_op__rc__rc$6$next[0:0]$7051 $1\logical_op__imm_data__ok$5$next[0:0]$7039 $1\logical_op__imm_data__data$4$next[63:0]$7038 $1\logical_op__fn_unit$3$next[12:0]$7037 $1\logical_op__insn_type$2$next[6:0]$7042 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
+ assign { $1\logical_op__insn$19$next[31:0]$6967 $1\logical_op__data_len$18$next[3:0]$6962 $1\logical_op__is_signed$17$next[0:0]$6972 $1\logical_op__is_32bit$16$next[0:0]$6971 $1\logical_op__output_carry$15$next[0:0]$6975 $1\logical_op__write_cr0$14$next[0:0]$6978 $1\logical_op__invert_out$13$next[0:0]$6970 $1\logical_op__input_carry$12$next[1:0]$6966 $1\logical_op__zero_a$11$next[0:0]$6979 $1\logical_op__invert_in$10$next[0:0]$6969 $1\logical_op__oe__ok$9$next[0:0]$6974 $1\logical_op__oe__oe$8$next[0:0]$6973 $1\logical_op__rc__ok$7$next[0:0]$6976 $1\logical_op__rc__rc$6$next[0:0]$6977 $1\logical_op__imm_data__ok$5$next[0:0]$6965 $1\logical_op__imm_data__data$4$next[63:0]$6964 $1\logical_op__fn_unit$3$next[12:0]$6963 $1\logical_op__insn_type$2$next[6:0]$6968 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 }
case
- assign $1\logical_op__data_len$18$next[3:0]$7036 \logical_op__data_len$18
- assign $1\logical_op__fn_unit$3$next[12:0]$7037 \logical_op__fn_unit$3
- assign $1\logical_op__imm_data__data$4$next[63:0]$7038 \logical_op__imm_data__data$4
- assign $1\logical_op__imm_data__ok$5$next[0:0]$7039 \logical_op__imm_data__ok$5
- assign $1\logical_op__input_carry$12$next[1:0]$7040 \logical_op__input_carry$12
- assign $1\logical_op__insn$19$next[31:0]$7041 \logical_op__insn$19
- assign $1\logical_op__insn_type$2$next[6:0]$7042 \logical_op__insn_type$2
- assign $1\logical_op__invert_in$10$next[0:0]$7043 \logical_op__invert_in$10
- assign $1\logical_op__invert_out$13$next[0:0]$7044 \logical_op__invert_out$13
- assign $1\logical_op__is_32bit$16$next[0:0]$7045 \logical_op__is_32bit$16
- assign $1\logical_op__is_signed$17$next[0:0]$7046 \logical_op__is_signed$17
- assign $1\logical_op__oe__oe$8$next[0:0]$7047 \logical_op__oe__oe$8
- assign $1\logical_op__oe__ok$9$next[0:0]$7048 \logical_op__oe__ok$9
- assign $1\logical_op__output_carry$15$next[0:0]$7049 \logical_op__output_carry$15
- assign $1\logical_op__rc__ok$7$next[0:0]$7050 \logical_op__rc__ok$7
- assign $1\logical_op__rc__rc$6$next[0:0]$7051 \logical_op__rc__rc$6
- assign $1\logical_op__write_cr0$14$next[0:0]$7052 \logical_op__write_cr0$14
- assign $1\logical_op__zero_a$11$next[0:0]$7053 \logical_op__zero_a$11
+ assign $1\logical_op__data_len$18$next[3:0]$6962 \logical_op__data_len$18
+ assign $1\logical_op__fn_unit$3$next[12:0]$6963 \logical_op__fn_unit$3
+ assign $1\logical_op__imm_data__data$4$next[63:0]$6964 \logical_op__imm_data__data$4
+ assign $1\logical_op__imm_data__ok$5$next[0:0]$6965 \logical_op__imm_data__ok$5
+ assign $1\logical_op__input_carry$12$next[1:0]$6966 \logical_op__input_carry$12
+ assign $1\logical_op__insn$19$next[31:0]$6967 \logical_op__insn$19
+ assign $1\logical_op__insn_type$2$next[6:0]$6968 \logical_op__insn_type$2
+ assign $1\logical_op__invert_in$10$next[0:0]$6969 \logical_op__invert_in$10
+ assign $1\logical_op__invert_out$13$next[0:0]$6970 \logical_op__invert_out$13
+ assign $1\logical_op__is_32bit$16$next[0:0]$6971 \logical_op__is_32bit$16
+ assign $1\logical_op__is_signed$17$next[0:0]$6972 \logical_op__is_signed$17
+ assign $1\logical_op__oe__oe$8$next[0:0]$6973 \logical_op__oe__oe$8
+ assign $1\logical_op__oe__ok$9$next[0:0]$6974 \logical_op__oe__ok$9
+ assign $1\logical_op__output_carry$15$next[0:0]$6975 \logical_op__output_carry$15
+ assign $1\logical_op__rc__ok$7$next[0:0]$6976 \logical_op__rc__ok$7
+ assign $1\logical_op__rc__rc$6$next[0:0]$6977 \logical_op__rc__rc$6
+ assign $1\logical_op__write_cr0$14$next[0:0]$6978 \logical_op__write_cr0$14
+ assign $1\logical_op__zero_a$11$next[0:0]$6979 \logical_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$4$next[63:0]$7054 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$5$next[0:0]$7055 1'0
- assign $2\logical_op__rc__rc$6$next[0:0]$7059 1'0
- assign $2\logical_op__rc__ok$7$next[0:0]$7058 1'0
- assign $2\logical_op__oe__oe$8$next[0:0]$7056 1'0
- assign $2\logical_op__oe__ok$9$next[0:0]$7057 1'0
+ assign $2\logical_op__imm_data__data$4$next[63:0]$6980 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$6981 1'0
+ assign $2\logical_op__rc__rc$6$next[0:0]$6985 1'0
+ assign $2\logical_op__rc__ok$7$next[0:0]$6984 1'0
+ assign $2\logical_op__oe__oe$8$next[0:0]$6982 1'0
+ assign $2\logical_op__oe__ok$9$next[0:0]$6983 1'0
case
- assign $2\logical_op__imm_data__data$4$next[63:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7038
- assign $2\logical_op__imm_data__ok$5$next[0:0]$7055 $1\logical_op__imm_data__ok$5$next[0:0]$7039
- assign $2\logical_op__oe__oe$8$next[0:0]$7056 $1\logical_op__oe__oe$8$next[0:0]$7047
- assign $2\logical_op__oe__ok$9$next[0:0]$7057 $1\logical_op__oe__ok$9$next[0:0]$7048
- assign $2\logical_op__rc__ok$7$next[0:0]$7058 $1\logical_op__rc__ok$7$next[0:0]$7050
- assign $2\logical_op__rc__rc$6$next[0:0]$7059 $1\logical_op__rc__rc$6$next[0:0]$7051
+ assign $2\logical_op__imm_data__data$4$next[63:0]$6980 $1\logical_op__imm_data__data$4$next[63:0]$6964
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$6981 $1\logical_op__imm_data__ok$5$next[0:0]$6965
+ assign $2\logical_op__oe__oe$8$next[0:0]$6982 $1\logical_op__oe__oe$8$next[0:0]$6973
+ assign $2\logical_op__oe__ok$9$next[0:0]$6983 $1\logical_op__oe__ok$9$next[0:0]$6974
+ assign $2\logical_op__rc__ok$7$next[0:0]$6984 $1\logical_op__rc__ok$7$next[0:0]$6976
+ assign $2\logical_op__rc__rc$6$next[0:0]$6985 $1\logical_op__rc__rc$6$next[0:0]$6977
end
sync always
- update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7018
- update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$7019
- update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7020
- update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7021
- update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7022
- update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7023
- update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7024
- update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7025
- update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7026
- update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7027
- update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7028
- update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7029
- update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7030
- update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7031
- update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7032
- update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7033
- update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7034
- update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7035
+ update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6944
+ update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$6945
+ update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6946
+ update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6947
+ update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6948
+ update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6949
+ update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6950
+ update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6951
+ update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6952
+ update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6953
+ update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6954
+ update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6955
+ update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6956
+ update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6957
+ update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6958
+ update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6959
+ update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6960
+ update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6961
end
- attribute \src "libresoc.v:144930.3-144948.6"
- process $proc$libresoc.v:144930$7060
+ attribute \src "libresoc.v:143060.3-143078.6"
+ process $proc$libresoc.v:143060$6986
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$20$next[63:0]$7061 $1\o$20$next[63:0]$7063
+ assign $0\o$20$next[63:0]$6987 $1\o$20$next[63:0]$6989
assign { } { }
- assign $0\o_ok$21$next[0:0]$7062 $2\o_ok$21$next[0:0]$7065
- attribute \src "libresoc.v:144931.5-144931.29"
+ assign $0\o_ok$21$next[0:0]$6988 $2\o_ok$21$next[0:0]$6991
+ attribute \src "libresoc.v:143061.5-143061.29"
switch \initial
- attribute \src "libresoc.v:144931.9-144931.17"
+ attribute \src "libresoc.v:143061.9-143061.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$7064 $1\o$20$next[63:0]$7063 } { \o_ok$71 \o$70 }
+ assign { $1\o_ok$21$next[0:0]$6990 $1\o$20$next[63:0]$6989 } { \o_ok$71 \o$70 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$7064 $1\o$20$next[63:0]$7063 } { \o_ok$71 \o$70 }
+ assign { $1\o_ok$21$next[0:0]$6990 $1\o$20$next[63:0]$6989 } { \o_ok$71 \o$70 }
case
- assign $1\o$20$next[63:0]$7063 \o$20
- assign $1\o_ok$21$next[0:0]$7064 \o_ok$21
+ assign $1\o$20$next[63:0]$6989 \o$20
+ assign $1\o_ok$21$next[0:0]$6990 \o_ok$21
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$21$next[0:0]$7065 1'0
+ assign $2\o_ok$21$next[0:0]$6991 1'0
case
- assign $2\o_ok$21$next[0:0]$7065 $1\o_ok$21$next[0:0]$7064
+ assign $2\o_ok$21$next[0:0]$6991 $1\o_ok$21$next[0:0]$6990
end
sync always
- update \o$20$next $0\o$20$next[63:0]$7061
- update \o_ok$21$next $0\o_ok$21$next[0:0]$7062
+ update \o$20$next $0\o$20$next[63:0]$6987
+ update \o_ok$21$next $0\o_ok$21$next[0:0]$6988
end
- attribute \src "libresoc.v:144949.3-144967.6"
- process $proc$libresoc.v:144949$7066
+ attribute \src "libresoc.v:143079.3-143097.6"
+ process $proc$libresoc.v:143079$6992
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$22$next[3:0]$7067 $1\cr_a$22$next[3:0]$7069
+ assign $0\cr_a$22$next[3:0]$6993 $1\cr_a$22$next[3:0]$6995
assign { } { }
- assign $0\cr_a_ok$23$next[0:0]$7068 $2\cr_a_ok$23$next[0:0]$7071
- attribute \src "libresoc.v:144950.5-144950.29"
+ assign $0\cr_a_ok$23$next[0:0]$6994 $2\cr_a_ok$23$next[0:0]$6997
+ attribute \src "libresoc.v:143080.5-143080.29"
switch \initial
- attribute \src "libresoc.v:144950.9-144950.17"
+ attribute \src "libresoc.v:143080.9-143080.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$7070 $1\cr_a$22$next[3:0]$7069 } { \cr_a_ok$73 \cr_a$72 }
+ assign { $1\cr_a_ok$23$next[0:0]$6996 $1\cr_a$22$next[3:0]$6995 } { \cr_a_ok$73 \cr_a$72 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$7070 $1\cr_a$22$next[3:0]$7069 } { \cr_a_ok$73 \cr_a$72 }
+ assign { $1\cr_a_ok$23$next[0:0]$6996 $1\cr_a$22$next[3:0]$6995 } { \cr_a_ok$73 \cr_a$72 }
case
- assign $1\cr_a$22$next[3:0]$7069 \cr_a$22
- assign $1\cr_a_ok$23$next[0:0]$7070 \cr_a_ok$23
+ assign $1\cr_a$22$next[3:0]$6995 \cr_a$22
+ assign $1\cr_a_ok$23$next[0:0]$6996 \cr_a_ok$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$23$next[0:0]$7071 1'0
+ assign $2\cr_a_ok$23$next[0:0]$6997 1'0
case
- assign $2\cr_a_ok$23$next[0:0]$7071 $1\cr_a_ok$23$next[0:0]$7070
+ assign $2\cr_a_ok$23$next[0:0]$6997 $1\cr_a_ok$23$next[0:0]$6996
end
sync always
- update \cr_a$22$next $0\cr_a$22$next[3:0]$7067
- update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7068
+ update \cr_a$22$next $0\cr_a$22$next[3:0]$6993
+ update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6994
end
- connect \$49 $and$libresoc.v:144752$6962_Y
+ connect \$49 $and$libresoc.v:142882$6888_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 }
wire $0\builder_sync_rhs_array_muxed5[0:0]
attribute \src "ls180.v:7452.1-7468.4"
wire $0\builder_sync_rhs_array_muxed6[0:0]
+ attribute \src "ls180.v:198.11-198.24"
+ wire width 3 $0\eint_1[2:0]
attribute \src "ls180.v:4396.1-4400.4"
wire width 16 $0\gpio_o[15:0]
attribute \src "ls180.v:4401.1-4405.4"
wire $0\main_libresocsim_eventmanager_re[0:0]
attribute \src "ls180.v:7702.1-10346.4"
wire $0\main_libresocsim_eventmanager_storage[0:0]
+ attribute \src "ls180.v:179.12-179.74"
+ wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
+ attribute \src "ls180.v:172.5-172.69"
+ wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
+ attribute \src "ls180.v:176.5-176.72"
+ wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
+ attribute \src "ls180.v:183.12-183.78"
+ wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+ attribute \src "ls180.v:197.5-197.74"
+ wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
+ attribute \src "ls180.v:202.5-202.74"
+ wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
attribute \src "ls180.v:75.11-75.52"
wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0]
attribute \src "ls180.v:74.11-74.52"
wire $not$ls180.v:9062$2888_Y
attribute \src "ls180.v:9083.8-9083.21"
wire $not$ls180.v:9083$2889_Y
- attribute \src "ls180.v:10706.8-10706.51"
- wire $or$ls180.v:10706$3077_Y
+ attribute \src "ls180.v:10685.8-10685.51"
+ wire $or$ls180.v:10685$3077_Y
attribute \src "ls180.v:2931.10-2931.71"
wire $or$ls180.v:2931$57_Y
attribute \src "ls180.v:2991.10-2991.71"
wire \builder_sync_rhs_array_muxed6
attribute \src "ls180.v:2011.6-2011.18"
wire \builder_wait
- attribute \src "ls180.v:11.19-11.23"
- wire width 3 input 7 \eint
- attribute \src "ls180.v:175.12-175.18"
+ attribute \src "ls180.v:37.19-37.23"
+ wire width 3 input 33 \eint
+ attribute \src "ls180.v:198.11-198.17"
wire width 3 \eint_1
- attribute \src "ls180.v:7.20-7.26"
- wire width 16 input 3 \gpio_i
- attribute \src "ls180.v:8.20-8.26"
- wire width 16 output 4 \gpio_o
- attribute \src "ls180.v:9.20-9.27"
- wire width 16 output 5 \gpio_oe
- attribute \src "ls180.v:24.14-24.21"
- wire output 20 \i2c_scl
- attribute \src "ls180.v:25.13-25.22"
- wire input 21 \i2c_sda_i
- attribute \src "ls180.v:26.14-26.23"
- wire output 22 \i2c_sda_o
- attribute \src "ls180.v:27.14-27.24"
- wire output 23 \i2c_sda_oe
+ attribute \src "ls180.v:18.20-18.26"
+ wire width 16 input 14 \gpio_i
+ attribute \src "ls180.v:19.21-19.27"
+ wire width 16 output 15 \gpio_o
+ attribute \src "ls180.v:20.21-20.28"
+ wire width 16 output 16 \gpio_oe
+ attribute \src "ls180.v:7.14-7.21"
+ wire output 3 \i2c_scl
+ attribute \src "ls180.v:8.13-8.22"
+ wire input 4 \i2c_sda_i
+ attribute \src "ls180.v:9.14-9.23"
+ wire output 5 \i2c_sda_o
+ attribute \src "ls180.v:10.14-10.24"
+ wire output 6 \i2c_sda_oe
attribute \src "ls180.v:49.13-49.21"
wire input 45 \jtag_tck
attribute \src "ls180.v:50.13-50.21"
wire width 64 \main_libresocsim_libresoc2
attribute \src "ls180.v:169.12-169.45"
wire width 2 \main_libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:171.13-171.67"
+ attribute \src "ls180.v:179.12-179.66"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
- attribute \src "ls180.v:172.13-172.67"
+ attribute \src "ls180.v:180.13-180.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
- attribute \src "ls180.v:173.13-173.68"
+ attribute \src "ls180.v:181.13-181.68"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
- attribute \src "ls180.v:188.6-188.61"
+ attribute \src "ls180.v:171.6-171.61"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
- attribute \src "ls180.v:189.6-189.63"
+ attribute \src "ls180.v:172.5-172.62"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- attribute \src "ls180.v:190.6-190.63"
+ attribute \src "ls180.v:173.6-173.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- attribute \src "ls180.v:191.6-191.64"
+ attribute \src "ls180.v:174.6-174.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
- attribute \src "ls180.v:196.6-196.64"
+ attribute \src "ls180.v:175.6-175.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
- attribute \src "ls180.v:197.6-197.66"
+ attribute \src "ls180.v:176.5-176.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
- attribute \src "ls180.v:198.6-198.66"
+ attribute \src "ls180.v:177.6-177.66"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
- attribute \src "ls180.v:199.6-199.67"
+ attribute \src "ls180.v:178.6-178.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
- attribute \src "ls180.v:176.13-176.68"
+ attribute \src "ls180.v:182.13-182.68"
wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
- attribute \src "ls180.v:185.12-185.68"
+ attribute \src "ls180.v:191.12-191.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
- attribute \src "ls180.v:182.6-182.65"
+ attribute \src "ls180.v:188.6-188.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
- attribute \src "ls180.v:184.6-184.63"
+ attribute \src "ls180.v:190.6-190.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
- attribute \src "ls180.v:183.6-183.64"
+ attribute \src "ls180.v:189.6-189.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
- attribute \src "ls180.v:186.12-186.68"
+ attribute \src "ls180.v:192.12-192.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
- attribute \src "ls180.v:177.13-177.71"
+ attribute \src "ls180.v:183.12-183.70"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
- attribute \src "ls180.v:178.13-178.71"
+ attribute \src "ls180.v:184.13-184.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
- attribute \src "ls180.v:179.6-179.65"
+ attribute \src "ls180.v:185.6-185.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
- attribute \src "ls180.v:181.6-181.65"
+ attribute \src "ls180.v:187.6-187.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
- attribute \src "ls180.v:180.6-180.64"
+ attribute \src "ls180.v:186.6-186.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
- attribute \src "ls180.v:192.6-192.67"
+ attribute \src "ls180.v:194.6-194.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
- attribute \src "ls180.v:194.6-194.68"
+ attribute \src "ls180.v:196.6-196.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
- attribute \src "ls180.v:195.6-195.68"
+ attribute \src "ls180.v:197.5-197.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
- attribute \src "ls180.v:193.6-193.68"
+ attribute \src "ls180.v:195.6-195.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
- attribute \src "ls180.v:200.6-200.67"
+ attribute \src "ls180.v:199.6-199.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
- attribute \src "ls180.v:202.6-202.68"
+ attribute \src "ls180.v:201.6-201.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
- attribute \src "ls180.v:203.6-203.68"
+ attribute \src "ls180.v:202.5-202.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
- attribute \src "ls180.v:201.6-201.68"
+ attribute \src "ls180.v:200.6-200.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
attribute \src "ls180.v:72.6-72.40"
wire \main_libresocsim_libresoc_dbus_ack
wire width 24 input 48 \nc
attribute \src "ls180.v:338.6-338.13"
wire \por_clk
- attribute \src "ls180.v:10.19-10.22"
- wire width 2 output 6 \pwm
- attribute \src "ls180.v:174.12-174.17"
+ attribute \src "ls180.v:42.20-42.23"
+ wire width 2 output 38 \pwm
+ attribute \src "ls180.v:203.12-203.17"
wire width 2 \pwm_1
- attribute \src "ls180.v:32.13-32.23"
- wire output 28 \sdcard_clk
- attribute \src "ls180.v:33.13-33.25"
- wire input 29 \sdcard_cmd_i
- attribute \src "ls180.v:34.13-34.25"
- wire output 30 \sdcard_cmd_o
- attribute \src "ls180.v:35.13-35.26"
- wire output 31 \sdcard_cmd_oe
- attribute \src "ls180.v:36.19-36.32"
- wire width 4 input 32 \sdcard_data_i
- attribute \src "ls180.v:37.19-37.32"
- wire width 4 output 33 \sdcard_data_o
- attribute \src "ls180.v:38.13-38.27"
- wire output 34 \sdcard_data_oe
- attribute \src "ls180.v:12.20-12.27"
- wire width 13 output 8 \sdram_a
- attribute \src "ls180.v:21.19-21.27"
- wire width 2 output 17 \sdram_ba
- attribute \src "ls180.v:18.13-18.24"
- wire output 14 \sdram_cas_n
- attribute \src "ls180.v:20.13-20.22"
- wire output 16 \sdram_cke
- attribute \src "ls180.v:23.13-23.24"
- wire output 19 \sdram_clock
- attribute \src "ls180.v:187.6-187.19"
+ attribute \src "ls180.v:11.14-11.24"
+ wire output 7 \sdcard_clk
+ attribute \src "ls180.v:12.13-12.25"
+ wire input 8 \sdcard_cmd_i
+ attribute \src "ls180.v:13.14-13.26"
+ wire output 9 \sdcard_cmd_o
+ attribute \src "ls180.v:14.14-14.27"
+ wire output 10 \sdcard_cmd_oe
+ attribute \src "ls180.v:15.19-15.32"
+ wire width 4 input 11 \sdcard_data_i
+ attribute \src "ls180.v:16.19-16.32"
+ wire width 4 output 12 \sdcard_data_o
+ attribute \src "ls180.v:17.13-17.27"
+ wire output 13 \sdcard_data_oe
+ attribute \src "ls180.v:21.21-21.28"
+ wire width 13 output 17 \sdram_a
+ attribute \src "ls180.v:30.20-30.28"
+ wire width 2 output 26 \sdram_ba
+ attribute \src "ls180.v:27.14-27.25"
+ wire output 23 \sdram_cas_n
+ attribute \src "ls180.v:29.14-29.23"
+ wire output 25 \sdram_cke
+ attribute \src "ls180.v:32.14-32.25"
+ wire output 28 \sdram_clock
+ attribute \src "ls180.v:193.6-193.19"
wire \sdram_clock_1
- attribute \src "ls180.v:19.13-19.23"
- wire output 15 \sdram_cs_n
- attribute \src "ls180.v:22.19-22.27"
- wire width 2 output 18 \sdram_dm
- attribute \src "ls180.v:13.20-13.30"
- wire width 16 input 9 \sdram_dq_i
- attribute \src "ls180.v:14.20-14.30"
- wire width 16 output 10 \sdram_dq_o
- attribute \src "ls180.v:15.13-15.24"
- wire output 11 \sdram_dq_oe
- attribute \src "ls180.v:17.13-17.24"
- wire output 13 \sdram_ras_n
- attribute \src "ls180.v:16.13-16.23"
- wire output 12 \sdram_we_n
+ attribute \src "ls180.v:28.14-28.24"
+ wire output 24 \sdram_cs_n
+ attribute \src "ls180.v:31.20-31.28"
+ wire width 2 output 27 \sdram_dm
+ attribute \src "ls180.v:22.20-22.30"
+ wire width 16 input 18 \sdram_dq_i
+ attribute \src "ls180.v:23.21-23.31"
+ wire width 16 output 19 \sdram_dq_o
+ attribute \src "ls180.v:24.14-24.25"
+ wire output 20 \sdram_dq_oe
+ attribute \src "ls180.v:26.14-26.25"
+ wire output 22 \sdram_ras_n
+ attribute \src "ls180.v:25.14-25.24"
+ wire output 21 \sdram_we_n
attribute \src "ls180.v:2760.6-2760.15"
wire \sdrio_clk
attribute \src "ls180.v:2761.6-2761.17"
wire \sdrio_clk_8
attribute \src "ls180.v:2769.6-2769.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:28.13-28.26"
- wire output 24 \spimaster_clk
- attribute \src "ls180.v:30.13-30.27"
- wire output 26 \spimaster_cs_n
- attribute \src "ls180.v:31.13-31.27"
- wire input 27 \spimaster_miso
- attribute \src "ls180.v:29.13-29.27"
- wire output 25 \spimaster_mosi
- attribute \src "ls180.v:39.13-39.26"
- wire output 35 \spisdcard_clk
+ attribute \src "ls180.v:33.14-33.27"
+ wire output 29 \spimaster_clk
+ attribute \src "ls180.v:35.14-35.28"
+ wire output 31 \spimaster_cs_n
+ attribute \src "ls180.v:36.13-36.27"
+ wire input 32 \spimaster_miso
+ attribute \src "ls180.v:34.14-34.28"
+ wire output 30 \spimaster_mosi
+ attribute \src "ls180.v:38.14-38.27"
+ wire output 34 \spisdcard_clk
+ attribute \src "ls180.v:40.14-40.28"
+ wire output 36 \spisdcard_cs_n
attribute \src "ls180.v:41.13-41.27"
- wire output 37 \spisdcard_cs_n
- attribute \src "ls180.v:42.13-42.27"
- wire input 38 \spisdcard_miso
- attribute \src "ls180.v:40.13-40.27"
- wire output 36 \spisdcard_mosi
+ wire input 37 \spisdcard_miso
+ attribute \src "ls180.v:39.14-39.28"
+ wire output 35 \spisdcard_mosi
attribute \src "ls180.v:43.13-43.20"
wire input 39 \sys_clk
attribute \src "ls180.v:336.6-336.15"
connect \A \builder_done
connect \Y $not$ls180.v:9083$2889_Y
end
- attribute \src "ls180.v:10706.8-10706.51"
- cell $or $or$ls180.v:10706$3077
+ attribute \src "ls180.v:10685.8-10685.51"
+ cell $or $or$ls180.v:10685$3077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sys_rst_1
connect \B \main_libresocsim_libresoc_reset
- connect \Y $or$ls180.v:10706$3077_Y
+ connect \Y $or$ls180.v:10685$3077_Y
end
attribute \src "ls180.v:2931.10-2931.71"
cell $or $or$ls180.v:2931$57
connect \pwm_0__pad__o \pwm_1 [0]
connect \pwm_1__core__o \pwm [1]
connect \pwm_1__pad__o \pwm_1 [1]
- connect \rst $or$ls180.v:10706$3077_Y
+ connect \rst $or$ls180.v:10685$3077_Y
connect \sd0_clk__core__o \sdcard_clk
connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
connect \sd0_cmd__core__i \sdcard_cmd_i
connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$4086
+ process $proc$ls180.v:0$4093
sync always
sync init
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$4087
+ process $proc$ls180.v:0$4094
sync always
sync init
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$4088
+ process $proc$ls180.v:0$4095
sync always
sync init
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$4089
+ process $proc$ls180.v:0$4096
sync always
sync init
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$4090
+ process $proc$ls180.v:0$4097
sync always
sync init
end
update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0]
end
attribute \src "ls180.v:1009.5-1009.40"
- process $proc$ls180.v:1009$3478
+ process $proc$ls180.v:1009$3485
assign { } { }
assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0]
end
attribute \src "ls180.v:1010.5-1010.39"
- process $proc$ls180.v:1010$3479
+ process $proc$ls180.v:1010$3486
assign { } { }
assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1018.5-1018.38"
- process $proc$ls180.v:1018$3480
+ process $proc$ls180.v:1018$3487
assign { } { }
assign $1\main_uart_tx_fifo_readable[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0]
end
attribute \src "ls180.v:1025.11-1025.42"
- process $proc$ls180.v:1025$3481
+ process $proc$ls180.v:1025$3488
assign { } { }
assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
sync always
update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
end
attribute \src "ls180.v:1026.5-1026.37"
- process $proc$ls180.v:1026$3482
+ process $proc$ls180.v:1026$3489
assign { } { }
assign $0\main_uart_tx_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1027.11-1027.43"
- process $proc$ls180.v:1027$3483
+ process $proc$ls180.v:1027$3490
assign { } { }
assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
sync always
update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
end
attribute \src "ls180.v:1028.11-1028.43"
- process $proc$ls180.v:1028$3484
+ process $proc$ls180.v:1028$3491
assign { } { }
assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
sync always
update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
end
attribute \src "ls180.v:1029.11-1029.46"
- process $proc$ls180.v:1029$3485
+ process $proc$ls180.v:1029$3492
assign { } { }
assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
sync always
update $memwr$\storage_4$ls180.v:10549$45_EN $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052
end
attribute \src "ls180.v:1055.5-1055.38"
- process $proc$ls180.v:1055$3486
+ process $proc$ls180.v:1055$3493
assign { } { }
assign $1\main_uart_rx_fifo_readable[0:0] 1'0
sync always
sync posedge \sys_clk_1
end
attribute \src "ls180.v:1062.11-1062.42"
- process $proc$ls180.v:1062$3487
+ process $proc$ls180.v:1062$3494
assign { } { }
assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
sync always
update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
end
attribute \src "ls180.v:1063.5-1063.37"
- process $proc$ls180.v:1063$3488
+ process $proc$ls180.v:1063$3495
assign { } { }
assign $0\main_uart_rx_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1064.11-1064.43"
- process $proc$ls180.v:1064$3489
+ process $proc$ls180.v:1064$3496
assign { } { }
assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
sync always
update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
end
attribute \src "ls180.v:1065.11-1065.43"
- process $proc$ls180.v:1065$3490
+ process $proc$ls180.v:1065$3497
assign { } { }
assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
sync always
update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
end
attribute \src "ls180.v:1066.11-1066.46"
- process $proc$ls180.v:1066$3491
+ process $proc$ls180.v:1066$3498
assign { } { }
assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
sync always
update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
end
attribute \src "ls180.v:1081.5-1081.27"
- process $proc$ls180.v:1081$3492
+ process $proc$ls180.v:1081$3499
assign { } { }
assign $0\main_uart_reset[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1082.12-1082.53"
- process $proc$ls180.v:1082$3493
+ process $proc$ls180.v:1082$3500
assign { } { }
assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000
sync always
sync init
end
attribute \src "ls180.v:1083.12-1083.49"
- process $proc$ls180.v:1083$3494
+ process $proc$ls180.v:1083$3501
assign { } { }
assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000
sync always
update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0]
end
attribute \src "ls180.v:1084.12-1084.54"
- process $proc$ls180.v:1084$3495
+ process $proc$ls180.v:1084$3502
assign { } { }
assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000
sync always
sync init
end
attribute \src "ls180.v:1088.12-1088.53"
- process $proc$ls180.v:1088$3496
+ process $proc$ls180.v:1088$3503
assign { } { }
assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000
sync always
update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0]
end
attribute \src "ls180.v:1089.5-1089.40"
- process $proc$ls180.v:1089$3497
+ process $proc$ls180.v:1089$3504
assign { } { }
assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0
sync always
update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0]
end
attribute \src "ls180.v:1090.12-1090.49"
- process $proc$ls180.v:1090$3498
+ process $proc$ls180.v:1090$3505
assign { } { }
assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000
sync always
update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0]
end
attribute \src "ls180.v:1092.12-1092.54"
- process $proc$ls180.v:1092$3499
+ process $proc$ls180.v:1092$3506
assign { } { }
assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000
sync always
update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0]
end
attribute \src "ls180.v:1093.5-1093.41"
- process $proc$ls180.v:1093$3500
+ process $proc$ls180.v:1093$3507
assign { } { }
assign $1\main_gpiotristateasic1_out_re[0:0] 1'0
sync always
update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0]
end
attribute \src "ls180.v:1099.5-1099.32"
- process $proc$ls180.v:1099$3501
+ process $proc$ls180.v:1099$3508
assign { } { }
assign $1\main_spimaster2_done[0:0] 1'0
sync always
update \main_spimaster2_done $1\main_spimaster2_done[0:0]
end
attribute \src "ls180.v:1100.5-1100.31"
- process $proc$ls180.v:1100$3502
+ process $proc$ls180.v:1100$3509
assign { } { }
assign $1\main_spimaster3_irq[0:0] 1'0
sync always
update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
end
attribute \src "ls180.v:1102.11-1102.38"
- process $proc$ls180.v:1102$3503
+ process $proc$ls180.v:1102$3510
assign { } { }
assign $1\main_spimaster5_miso[7:0] 8'00000000
sync always
update \main_spimaster5_miso $1\main_spimaster5_miso[7:0]
end
attribute \src "ls180.v:1105.12-1105.47"
- process $proc$ls180.v:1105$3504
+ process $proc$ls180.v:1105$3511
assign { } { }
assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
sync always
sync init
end
attribute \src "ls180.v:1106.5-1106.33"
- process $proc$ls180.v:1106$3505
+ process $proc$ls180.v:1106$3512
assign { } { }
assign $1\main_spimaster9_start[0:0] 1'0
sync always
update \main_spimaster9_start $1\main_spimaster9_start[0:0]
end
attribute \src "ls180.v:1108.12-1108.44"
- process $proc$ls180.v:1108$3506
+ process $proc$ls180.v:1108$3513
assign { } { }
assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
sync always
update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
end
attribute \src "ls180.v:1109.5-1109.31"
- process $proc$ls180.v:1109$3507
+ process $proc$ls180.v:1109$3514
assign { } { }
assign $1\main_spimaster12_re[0:0] 1'0
sync always
update \main_spimaster12_re $1\main_spimaster12_re[0:0]
end
attribute \src "ls180.v:1113.11-1113.42"
- process $proc$ls180.v:1113$3508
+ process $proc$ls180.v:1113$3515
assign { } { }
assign $1\main_spimaster16_storage[7:0] 8'00000000
sync always
update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
end
attribute \src "ls180.v:1114.5-1114.31"
- process $proc$ls180.v:1114$3509
+ process $proc$ls180.v:1114$3516
assign { } { }
assign $1\main_spimaster17_re[0:0] 1'0
sync always
update \main_spimaster17_re $1\main_spimaster17_re[0:0]
end
attribute \src "ls180.v:1118.5-1118.36"
- process $proc$ls180.v:1118$3510
+ process $proc$ls180.v:1118$3517
assign { } { }
assign $1\main_spimaster21_storage[0:0] 1'1
sync always
update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
end
attribute \src "ls180.v:1119.5-1119.31"
- process $proc$ls180.v:1119$3511
+ process $proc$ls180.v:1119$3518
assign { } { }
assign $1\main_spimaster22_re[0:0] 1'0
sync always
update \main_spimaster22_re $1\main_spimaster22_re[0:0]
end
attribute \src "ls180.v:1120.5-1120.36"
- process $proc$ls180.v:1120$3512
+ process $proc$ls180.v:1120$3519
assign { } { }
assign $1\main_spimaster23_storage[0:0] 1'0
sync always
update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
end
attribute \src "ls180.v:1121.5-1121.31"
- process $proc$ls180.v:1121$3513
+ process $proc$ls180.v:1121$3520
assign { } { }
assign $1\main_spimaster24_re[0:0] 1'0
sync always
update \main_spimaster24_re $1\main_spimaster24_re[0:0]
end
attribute \src "ls180.v:1122.5-1122.39"
- process $proc$ls180.v:1122$3514
+ process $proc$ls180.v:1122$3521
assign { } { }
assign $1\main_spimaster25_clk_enable[0:0] 1'0
sync always
update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
end
attribute \src "ls180.v:1123.5-1123.38"
- process $proc$ls180.v:1123$3515
+ process $proc$ls180.v:1123$3522
assign { } { }
assign $1\main_spimaster26_cs_enable[0:0] 1'0
sync always
update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
end
attribute \src "ls180.v:1124.11-1124.40"
- process $proc$ls180.v:1124$3516
+ process $proc$ls180.v:1124$3523
assign { } { }
assign $1\main_spimaster27_count[2:0] 3'000
sync always
update \main_spimaster27_count $1\main_spimaster27_count[2:0]
end
attribute \src "ls180.v:1125.5-1125.39"
- process $proc$ls180.v:1125$3517
+ process $proc$ls180.v:1125$3524
assign { } { }
assign $1\main_spimaster28_mosi_latch[0:0] 1'0
sync always
update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
end
attribute \src "ls180.v:1126.5-1126.39"
- process $proc$ls180.v:1126$3518
+ process $proc$ls180.v:1126$3525
assign { } { }
assign $1\main_spimaster29_miso_latch[0:0] 1'0
sync always
update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
end
attribute \src "ls180.v:1127.12-1127.48"
- process $proc$ls180.v:1127$3519
+ process $proc$ls180.v:1127$3526
assign { } { }
assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
sync always
update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
end
attribute \src "ls180.v:1130.11-1130.44"
- process $proc$ls180.v:1130$3520
+ process $proc$ls180.v:1130$3527
assign { } { }
assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
sync always
update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
end
attribute \src "ls180.v:1131.11-1131.43"
- process $proc$ls180.v:1131$3521
+ process $proc$ls180.v:1131$3528
assign { } { }
assign $1\main_spimaster34_mosi_sel[2:0] 3'000
sync always
update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
end
attribute \src "ls180.v:1132.11-1132.44"
- process $proc$ls180.v:1132$3522
+ process $proc$ls180.v:1132$3529
assign { } { }
assign $1\main_spimaster35_miso_data[7:0] 8'00000000
sync always
update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
end
attribute \src "ls180.v:1135.5-1135.32"
- process $proc$ls180.v:1135$3523
+ process $proc$ls180.v:1135$3530
assign { } { }
assign $1\main_spisdcard_done0[0:0] 1'0
sync always
update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
end
attribute \src "ls180.v:1136.5-1136.30"
- process $proc$ls180.v:1136$3524
+ process $proc$ls180.v:1136$3531
assign { } { }
assign $1\main_spisdcard_irq[0:0] 1'0
sync always
update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
end
attribute \src "ls180.v:1138.11-1138.37"
- process $proc$ls180.v:1138$3525
+ process $proc$ls180.v:1138$3532
assign { } { }
assign $1\main_spisdcard_miso[7:0] 8'00000000
sync always
sync init
end
attribute \src "ls180.v:1142.5-1142.33"
- process $proc$ls180.v:1142$3526
+ process $proc$ls180.v:1142$3533
assign { } { }
assign $1\main_spisdcard_start1[0:0] 1'0
sync always
update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
end
attribute \src "ls180.v:1144.12-1144.50"
- process $proc$ls180.v:1144$3527
+ process $proc$ls180.v:1144$3534
assign { } { }
assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
sync always
update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
end
attribute \src "ls180.v:1145.5-1145.37"
- process $proc$ls180.v:1145$3528
+ process $proc$ls180.v:1145$3535
assign { } { }
assign $1\main_spisdcard_control_re[0:0] 1'0
sync always
update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
end
attribute \src "ls180.v:1149.11-1149.45"
- process $proc$ls180.v:1149$3529
+ process $proc$ls180.v:1149$3536
assign { } { }
assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
sync always
sync init
end
attribute \src "ls180.v:1150.5-1150.34"
- process $proc$ls180.v:1150$3530
+ process $proc$ls180.v:1150$3537
assign { } { }
assign $1\main_spisdcard_mosi_re[0:0] 1'0
sync always
update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
end
attribute \src "ls180.v:1154.5-1154.37"
- process $proc$ls180.v:1154$3531
+ process $proc$ls180.v:1154$3538
assign { } { }
assign $1\main_spisdcard_cs_storage[0:0] 1'1
sync always
update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
end
attribute \src "ls180.v:1155.5-1155.32"
- process $proc$ls180.v:1155$3532
+ process $proc$ls180.v:1155$3539
assign { } { }
assign $1\main_spisdcard_cs_re[0:0] 1'0
sync always
update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
end
attribute \src "ls180.v:1156.5-1156.43"
- process $proc$ls180.v:1156$3533
+ process $proc$ls180.v:1156$3540
assign { } { }
assign $1\main_spisdcard_loopback_storage[0:0] 1'0
sync always
update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
end
attribute \src "ls180.v:1157.5-1157.38"
- process $proc$ls180.v:1157$3534
+ process $proc$ls180.v:1157$3541
assign { } { }
assign $1\main_spisdcard_loopback_re[0:0] 1'0
sync always
update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
end
attribute \src "ls180.v:1158.5-1158.37"
- process $proc$ls180.v:1158$3535
+ process $proc$ls180.v:1158$3542
assign { } { }
assign $1\main_spisdcard_clk_enable[0:0] 1'0
sync always
update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
end
attribute \src "ls180.v:1159.5-1159.36"
- process $proc$ls180.v:1159$3536
+ process $proc$ls180.v:1159$3543
assign { } { }
assign $1\main_spisdcard_cs_enable[0:0] 1'0
sync always
update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
end
attribute \src "ls180.v:1160.11-1160.38"
- process $proc$ls180.v:1160$3537
+ process $proc$ls180.v:1160$3544
assign { } { }
assign $1\main_spisdcard_count[2:0] 3'000
sync always
update \main_spisdcard_count $1\main_spisdcard_count[2:0]
end
attribute \src "ls180.v:1161.5-1161.37"
- process $proc$ls180.v:1161$3538
+ process $proc$ls180.v:1161$3545
assign { } { }
assign $1\main_spisdcard_mosi_latch[0:0] 1'0
sync always
update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
end
attribute \src "ls180.v:1162.5-1162.37"
- process $proc$ls180.v:1162$3539
+ process $proc$ls180.v:1162$3546
assign { } { }
assign $1\main_spisdcard_miso_latch[0:0] 1'0
sync always
update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
end
attribute \src "ls180.v:1163.12-1163.47"
- process $proc$ls180.v:1163$3540
+ process $proc$ls180.v:1163$3547
assign { } { }
assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
sync always
update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
end
attribute \src "ls180.v:1166.11-1166.42"
- process $proc$ls180.v:1166$3541
+ process $proc$ls180.v:1166$3548
assign { } { }
assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
sync always
update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
end
attribute \src "ls180.v:1167.11-1167.41"
- process $proc$ls180.v:1167$3542
+ process $proc$ls180.v:1167$3549
assign { } { }
assign $1\main_spisdcard_mosi_sel[2:0] 3'000
sync always
update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
end
attribute \src "ls180.v:1168.11-1168.42"
- process $proc$ls180.v:1168$3543
+ process $proc$ls180.v:1168$3550
assign { } { }
assign $1\main_spisdcard_miso_data[7:0] 8'00000000
sync always
update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
end
attribute \src "ls180.v:1169.12-1169.45"
- process $proc$ls180.v:1169$3544
+ process $proc$ls180.v:1169$3551
assign { } { }
assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
sync always
update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
end
attribute \src "ls180.v:1170.5-1170.30"
- process $proc$ls180.v:1170$3545
+ process $proc$ls180.v:1170$3552
assign { } { }
assign $1\main_spimaster1_re[0:0] 1'0
sync always
update \main_spimaster1_re $1\main_spimaster1_re[0:0]
end
attribute \src "ls180.v:1172.12-1172.30"
- process $proc$ls180.v:1172$3546
+ process $proc$ls180.v:1172$3553
assign { } { }
assign $1\main_dummy[23:0] 24'000000000000000000000000
sync always
update \main_dummy $1\main_dummy[23:0]
end
attribute \src "ls180.v:1176.12-1176.37"
- process $proc$ls180.v:1176$3547
+ process $proc$ls180.v:1176$3554
assign { } { }
assign $1\main_pwm0_counter[31:0] 0
sync always
update \main_pwm0_counter $1\main_pwm0_counter[31:0]
end
attribute \src "ls180.v:1177.5-1177.36"
- process $proc$ls180.v:1177$3548
+ process $proc$ls180.v:1177$3555
assign { } { }
assign $1\main_pwm0_enable_storage[0:0] 1'0
sync always
update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
end
attribute \src "ls180.v:1178.5-1178.31"
- process $proc$ls180.v:1178$3549
+ process $proc$ls180.v:1178$3556
assign { } { }
assign $1\main_pwm0_enable_re[0:0] 1'0
sync always
update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
end
attribute \src "ls180.v:1179.12-1179.43"
- process $proc$ls180.v:1179$3550
+ process $proc$ls180.v:1179$3557
assign { } { }
assign $1\main_pwm0_width_storage[31:0] 0
sync always
update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
end
attribute \src "ls180.v:1180.5-1180.30"
- process $proc$ls180.v:1180$3551
+ process $proc$ls180.v:1180$3558
assign { } { }
assign $1\main_pwm0_width_re[0:0] 1'0
sync always
update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
end
attribute \src "ls180.v:1181.12-1181.44"
- process $proc$ls180.v:1181$3552
+ process $proc$ls180.v:1181$3559
assign { } { }
assign $1\main_pwm0_period_storage[31:0] 0
sync always
update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
end
attribute \src "ls180.v:1182.5-1182.31"
- process $proc$ls180.v:1182$3553
+ process $proc$ls180.v:1182$3560
assign { } { }
assign $1\main_pwm0_period_re[0:0] 1'0
sync always
update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
end
attribute \src "ls180.v:1186.12-1186.37"
- process $proc$ls180.v:1186$3554
+ process $proc$ls180.v:1186$3561
assign { } { }
assign $1\main_pwm1_counter[31:0] 0
sync always
update \main_pwm1_counter $1\main_pwm1_counter[31:0]
end
attribute \src "ls180.v:1187.5-1187.36"
- process $proc$ls180.v:1187$3555
+ process $proc$ls180.v:1187$3562
assign { } { }
assign $1\main_pwm1_enable_storage[0:0] 1'0
sync always
update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
end
attribute \src "ls180.v:1188.5-1188.31"
- process $proc$ls180.v:1188$3556
+ process $proc$ls180.v:1188$3563
assign { } { }
assign $1\main_pwm1_enable_re[0:0] 1'0
sync always
update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
end
attribute \src "ls180.v:1189.12-1189.43"
- process $proc$ls180.v:1189$3557
+ process $proc$ls180.v:1189$3564
assign { } { }
assign $1\main_pwm1_width_storage[31:0] 0
sync always
update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
end
attribute \src "ls180.v:1190.5-1190.30"
- process $proc$ls180.v:1190$3558
+ process $proc$ls180.v:1190$3565
assign { } { }
assign $1\main_pwm1_width_re[0:0] 1'0
sync always
update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
end
attribute \src "ls180.v:1191.12-1191.44"
- process $proc$ls180.v:1191$3559
+ process $proc$ls180.v:1191$3566
assign { } { }
assign $1\main_pwm1_period_storage[31:0] 0
sync always
update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
end
attribute \src "ls180.v:1192.5-1192.31"
- process $proc$ls180.v:1192$3560
+ process $proc$ls180.v:1192$3567
assign { } { }
assign $1\main_pwm1_period_re[0:0] 1'0
sync always
update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
end
attribute \src "ls180.v:1196.11-1196.34"
- process $proc$ls180.v:1196$3561
+ process $proc$ls180.v:1196$3568
assign { } { }
assign $1\main_i2c_storage[2:0] 3'000
sync always
update \main_i2c_storage $1\main_i2c_storage[2:0]
end
attribute \src "ls180.v:1197.5-1197.23"
- process $proc$ls180.v:1197$3562
+ process $proc$ls180.v:1197$3569
assign { } { }
assign $1\main_i2c_re[0:0] 1'0
sync always
update \main_i2c_re $1\main_i2c_re[0:0]
end
attribute \src "ls180.v:1203.11-1203.46"
- process $proc$ls180.v:1203$3563
+ process $proc$ls180.v:1203$3570
assign { } { }
assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
sync always
update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
end
attribute \src "ls180.v:1204.5-1204.33"
- process $proc$ls180.v:1204$3564
+ process $proc$ls180.v:1204$3571
assign { } { }
assign $1\main_sdphy_clocker_re[0:0] 1'0
sync always
update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
end
attribute \src "ls180.v:1206.5-1206.35"
- process $proc$ls180.v:1206$3565
+ process $proc$ls180.v:1206$3572
assign { } { }
assign $1\main_sdphy_clocker_clk0[0:0] 1'0
sync always
update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
end
attribute \src "ls180.v:1208.11-1208.41"
- process $proc$ls180.v:1208$3566
+ process $proc$ls180.v:1208$3573
assign { } { }
assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
sync always
update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
end
attribute \src "ls180.v:1209.5-1209.35"
- process $proc$ls180.v:1209$3567
+ process $proc$ls180.v:1209$3574
assign { } { }
assign $1\main_sdphy_clocker_clk1[0:0] 1'0
sync always
update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
end
attribute \src "ls180.v:1210.5-1210.36"
- process $proc$ls180.v:1210$3568
+ process $proc$ls180.v:1210$3575
assign { } { }
assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
sync always
update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
end
attribute \src "ls180.v:1214.5-1214.40"
- process $proc$ls180.v:1214$3569
+ process $proc$ls180.v:1214$3576
assign { } { }
assign $0\main_sdphy_init_initialize_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1219.5-1219.48"
- process $proc$ls180.v:1219$3570
+ process $proc$ls180.v:1219$3577
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1220.5-1220.50"
- process $proc$ls180.v:1220$3571
+ process $proc$ls180.v:1220$3578
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1221.5-1221.51"
- process $proc$ls180.v:1221$3572
+ process $proc$ls180.v:1221$3579
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1222.11-1222.57"
- process $proc$ls180.v:1222$3573
+ process $proc$ls180.v:1222$3580
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
end
attribute \src "ls180.v:1223.5-1223.52"
- process $proc$ls180.v:1223$3574
+ process $proc$ls180.v:1223$3581
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
end
attribute \src "ls180.v:1224.11-1224.39"
- process $proc$ls180.v:1224$3575
+ process $proc$ls180.v:1224$3582
assign { } { }
assign $1\main_sdphy_init_count[7:0] 8'00000000
sync always
update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
end
attribute \src "ls180.v:1229.5-1229.48"
- process $proc$ls180.v:1229$3576
+ process $proc$ls180.v:1229$3583
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1230.5-1230.50"
- process $proc$ls180.v:1230$3577
+ process $proc$ls180.v:1230$3584
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1231.5-1231.51"
- process $proc$ls180.v:1231$3578
+ process $proc$ls180.v:1231$3585
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1232.11-1232.57"
- process $proc$ls180.v:1232$3579
+ process $proc$ls180.v:1232$3586
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1233.5-1233.52"
- process $proc$ls180.v:1233$3580
+ process $proc$ls180.v:1233$3587
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1234.5-1234.38"
- process $proc$ls180.v:1234$3581
+ process $proc$ls180.v:1234$3588
assign { } { }
assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
end
attribute \src "ls180.v:1235.5-1235.38"
- process $proc$ls180.v:1235$3582
+ process $proc$ls180.v:1235$3589
assign { } { }
assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
end
attribute \src "ls180.v:1236.5-1236.37"
- process $proc$ls180.v:1236$3583
+ process $proc$ls180.v:1236$3590
assign { } { }
assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
end
attribute \src "ls180.v:1237.11-1237.51"
- process $proc$ls180.v:1237$3584
+ process $proc$ls180.v:1237$3591
assign { } { }
assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
end
attribute \src "ls180.v:1238.5-1238.32"
- process $proc$ls180.v:1238$3585
+ process $proc$ls180.v:1238$3592
assign { } { }
assign $1\main_sdphy_cmdw_done[0:0] 1'0
sync always
update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
end
attribute \src "ls180.v:1239.11-1239.39"
- process $proc$ls180.v:1239$3586
+ process $proc$ls180.v:1239$3593
assign { } { }
assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
end
attribute \src "ls180.v:1242.5-1242.49"
- process $proc$ls180.v:1242$3587
+ process $proc$ls180.v:1242$3594
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1243.5-1243.48"
- process $proc$ls180.v:1243$3588
+ process $proc$ls180.v:1243$3595
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1244.5-1244.55"
- process $proc$ls180.v:1244$3589
+ process $proc$ls180.v:1244$3596
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1246.5-1246.57"
- process $proc$ls180.v:1246$3590
+ process $proc$ls180.v:1246$3597
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1247.5-1247.58"
- process $proc$ls180.v:1247$3591
+ process $proc$ls180.v:1247$3598
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1249.11-1249.64"
- process $proc$ls180.v:1249$3592
+ process $proc$ls180.v:1249$3599
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1250.5-1250.59"
- process $proc$ls180.v:1250$3593
+ process $proc$ls180.v:1250$3600
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1252.5-1252.48"
- process $proc$ls180.v:1252$3594
+ process $proc$ls180.v:1252$3601
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1253.5-1253.50"
- process $proc$ls180.v:1253$3595
+ process $proc$ls180.v:1253$3602
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1254.5-1254.51"
- process $proc$ls180.v:1254$3596
+ process $proc$ls180.v:1254$3603
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1255.11-1255.57"
- process $proc$ls180.v:1255$3597
+ process $proc$ls180.v:1255$3604
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1256.5-1256.52"
- process $proc$ls180.v:1256$3598
+ process $proc$ls180.v:1256$3605
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1257.5-1257.38"
- process $proc$ls180.v:1257$3599
+ process $proc$ls180.v:1257$3606
assign { } { }
assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
end
attribute \src "ls180.v:1258.5-1258.38"
- process $proc$ls180.v:1258$3600
+ process $proc$ls180.v:1258$3607
assign { } { }
assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
end
attribute \src "ls180.v:1259.5-1259.37"
- process $proc$ls180.v:1259$3601
+ process $proc$ls180.v:1259$3608
assign { } { }
assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
end
attribute \src "ls180.v:1260.11-1260.53"
- process $proc$ls180.v:1260$3602
+ process $proc$ls180.v:1260$3609
assign { } { }
assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
end
attribute \src "ls180.v:1261.5-1261.40"
- process $proc$ls180.v:1261$3603
+ process $proc$ls180.v:1261$3610
assign { } { }
assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
end
attribute \src "ls180.v:1262.5-1262.40"
- process $proc$ls180.v:1262$3604
+ process $proc$ls180.v:1262$3611
assign { } { }
assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
end
attribute \src "ls180.v:1263.5-1263.39"
- process $proc$ls180.v:1263$3605
+ process $proc$ls180.v:1263$3612
assign { } { }
assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
end
attribute \src "ls180.v:1264.11-1264.53"
- process $proc$ls180.v:1264$3606
+ process $proc$ls180.v:1264$3613
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
end
attribute \src "ls180.v:1265.11-1265.55"
- process $proc$ls180.v:1265$3607
+ process $proc$ls180.v:1265$3614
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
sync always
update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
end
attribute \src "ls180.v:1266.12-1266.48"
- process $proc$ls180.v:1266$3608
+ process $proc$ls180.v:1266$3615
assign { } { }
assign $1\main_sdphy_cmdr_timeout[31:0] 500000
sync always
update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
end
attribute \src "ls180.v:1267.11-1267.39"
- process $proc$ls180.v:1267$3609
+ process $proc$ls180.v:1267$3616
assign { } { }
assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
end
attribute \src "ls180.v:1269.5-1269.46"
- process $proc$ls180.v:1269$3610
+ process $proc$ls180.v:1269$3617
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1280.5-1280.53"
- process $proc$ls180.v:1280$3611
+ process $proc$ls180.v:1280$3618
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
end
attribute \src "ls180.v:1285.5-1285.36"
- process $proc$ls180.v:1285$3612
+ process $proc$ls180.v:1285$3619
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
end
attribute \src "ls180.v:1288.5-1288.53"
- process $proc$ls180.v:1288$3613
+ process $proc$ls180.v:1288$3620
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1289.5-1289.52"
- process $proc$ls180.v:1289$3614
+ process $proc$ls180.v:1289$3621
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1293.5-1293.55"
- process $proc$ls180.v:1293$3615
+ process $proc$ls180.v:1293$3622
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
end
attribute \src "ls180.v:1294.5-1294.54"
- process $proc$ls180.v:1294$3616
+ process $proc$ls180.v:1294$3623
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
end
attribute \src "ls180.v:1295.11-1295.68"
- process $proc$ls180.v:1295$3617
+ process $proc$ls180.v:1295$3624
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1296.11-1296.81"
- process $proc$ls180.v:1296$3618
+ process $proc$ls180.v:1296$3625
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
end
attribute \src "ls180.v:1297.11-1297.54"
- process $proc$ls180.v:1297$3619
+ process $proc$ls180.v:1297$3626
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
sync always
update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
end
attribute \src "ls180.v:1299.5-1299.53"
- process $proc$ls180.v:1299$3620
+ process $proc$ls180.v:1299$3627
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1310.5-1310.49"
- process $proc$ls180.v:1310$3621
+ process $proc$ls180.v:1310$3628
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
end
attribute \src "ls180.v:1312.5-1312.49"
- process $proc$ls180.v:1312$3622
+ process $proc$ls180.v:1312$3629
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
end
attribute \src "ls180.v:1313.5-1313.48"
- process $proc$ls180.v:1313$3623
+ process $proc$ls180.v:1313$3630
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
end
attribute \src "ls180.v:1314.11-1314.62"
- process $proc$ls180.v:1314$3624
+ process $proc$ls180.v:1314$3631
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1315.5-1315.38"
- process $proc$ls180.v:1315$3625
+ process $proc$ls180.v:1315$3632
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
end
attribute \src "ls180.v:1320.5-1320.49"
- process $proc$ls180.v:1320$3626
+ process $proc$ls180.v:1320$3633
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1321.5-1321.51"
- process $proc$ls180.v:1321$3627
+ process $proc$ls180.v:1321$3634
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1322.5-1322.52"
- process $proc$ls180.v:1322$3628
+ process $proc$ls180.v:1322$3635
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1323.11-1323.58"
- process $proc$ls180.v:1323$3629
+ process $proc$ls180.v:1323$3636
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
end
attribute \src "ls180.v:1324.5-1324.53"
- process $proc$ls180.v:1324$3630
+ process $proc$ls180.v:1324$3637
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
end
attribute \src "ls180.v:1325.5-1325.39"
- process $proc$ls180.v:1325$3631
+ process $proc$ls180.v:1325$3638
assign { } { }
assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
end
attribute \src "ls180.v:1326.5-1326.39"
- process $proc$ls180.v:1326$3632
+ process $proc$ls180.v:1326$3639
assign { } { }
assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
end
attribute \src "ls180.v:1327.5-1327.39"
- process $proc$ls180.v:1327$3633
+ process $proc$ls180.v:1327$3640
assign { } { }
assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
end
attribute \src "ls180.v:1328.5-1328.38"
- process $proc$ls180.v:1328$3634
+ process $proc$ls180.v:1328$3641
assign { } { }
assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
end
attribute \src "ls180.v:1329.11-1329.52"
- process $proc$ls180.v:1329$3635
+ process $proc$ls180.v:1329$3642
assign { } { }
assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
end
attribute \src "ls180.v:1330.5-1330.33"
- process $proc$ls180.v:1330$3636
+ process $proc$ls180.v:1330$3643
assign { } { }
assign $1\main_sdphy_dataw_stop[0:0] 1'0
sync always
update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
end
attribute \src "ls180.v:1331.11-1331.40"
- process $proc$ls180.v:1331$3637
+ process $proc$ls180.v:1331$3644
assign { } { }
assign $1\main_sdphy_dataw_count[7:0] 8'00000000
sync always
update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
end
attribute \src "ls180.v:1332.5-1332.50"
- process $proc$ls180.v:1332$3638
+ process $proc$ls180.v:1332$3645
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1334.5-1334.50"
- process $proc$ls180.v:1334$3639
+ process $proc$ls180.v:1334$3646
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1335.5-1335.49"
- process $proc$ls180.v:1335$3640
+ process $proc$ls180.v:1335$3647
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1336.5-1336.56"
- process $proc$ls180.v:1336$3641
+ process $proc$ls180.v:1336$3648
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1337.5-1337.58"
- process $proc$ls180.v:1337$3642
+ process $proc$ls180.v:1337$3649
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1338.5-1338.58"
- process $proc$ls180.v:1338$3643
+ process $proc$ls180.v:1338$3650
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1339.5-1339.59"
- process $proc$ls180.v:1339$3644
+ process $proc$ls180.v:1339$3651
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1340.11-1340.65"
- process $proc$ls180.v:1340$3645
+ process $proc$ls180.v:1340$3652
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1341.11-1341.65"
- process $proc$ls180.v:1341$3646
+ process $proc$ls180.v:1341$3653
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1342.5-1342.60"
- process $proc$ls180.v:1342$3647
+ process $proc$ls180.v:1342$3654
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1343.5-1343.34"
- process $proc$ls180.v:1343$3648
+ process $proc$ls180.v:1343$3655
assign { } { }
assign $1\main_sdphy_dataw_start[0:0] 1'0
sync always
update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
end
attribute \src "ls180.v:1344.5-1344.34"
- process $proc$ls180.v:1344$3649
+ process $proc$ls180.v:1344$3656
assign { } { }
assign $1\main_sdphy_dataw_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
end
attribute \src "ls180.v:1345.5-1345.34"
- process $proc$ls180.v:1345$3650
+ process $proc$ls180.v:1345$3657
assign { } { }
assign $1\main_sdphy_dataw_error[0:0] 1'0
sync always
update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
end
attribute \src "ls180.v:1347.5-1347.47"
- process $proc$ls180.v:1347$3651
+ process $proc$ls180.v:1347$3658
assign { } { }
assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1358.5-1358.54"
- process $proc$ls180.v:1358$3652
+ process $proc$ls180.v:1358$3659
assign { } { }
assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
end
attribute \src "ls180.v:1363.5-1363.37"
- process $proc$ls180.v:1363$3653
+ process $proc$ls180.v:1363$3660
assign { } { }
assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
end
attribute \src "ls180.v:1366.5-1366.54"
- process $proc$ls180.v:1366$3654
+ process $proc$ls180.v:1366$3661
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1367.5-1367.53"
- process $proc$ls180.v:1367$3655
+ process $proc$ls180.v:1367$3662
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1371.5-1371.56"
- process $proc$ls180.v:1371$3656
+ process $proc$ls180.v:1371$3663
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
end
attribute \src "ls180.v:1372.5-1372.55"
- process $proc$ls180.v:1372$3657
+ process $proc$ls180.v:1372$3664
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
end
attribute \src "ls180.v:1373.11-1373.69"
- process $proc$ls180.v:1373$3658
+ process $proc$ls180.v:1373$3665
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1374.11-1374.82"
- process $proc$ls180.v:1374$3659
+ process $proc$ls180.v:1374$3666
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
end
attribute \src "ls180.v:1375.11-1375.55"
- process $proc$ls180.v:1375$3660
+ process $proc$ls180.v:1375$3667
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
sync always
update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
end
attribute \src "ls180.v:1377.5-1377.54"
- process $proc$ls180.v:1377$3661
+ process $proc$ls180.v:1377$3668
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1388.5-1388.50"
- process $proc$ls180.v:1388$3662
+ process $proc$ls180.v:1388$3669
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
end
attribute \src "ls180.v:1390.5-1390.50"
- process $proc$ls180.v:1390$3663
+ process $proc$ls180.v:1390$3670
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
end
attribute \src "ls180.v:1391.5-1391.49"
- process $proc$ls180.v:1391$3664
+ process $proc$ls180.v:1391$3671
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
end
attribute \src "ls180.v:1392.11-1392.63"
- process $proc$ls180.v:1392$3665
+ process $proc$ls180.v:1392$3672
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1393.5-1393.39"
- process $proc$ls180.v:1393$3666
+ process $proc$ls180.v:1393$3673
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
end
attribute \src "ls180.v:1396.5-1396.50"
- process $proc$ls180.v:1396$3667
+ process $proc$ls180.v:1396$3674
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1397.5-1397.49"
- process $proc$ls180.v:1397$3668
+ process $proc$ls180.v:1397$3675
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1398.5-1398.56"
- process $proc$ls180.v:1398$3669
+ process $proc$ls180.v:1398$3676
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1400.5-1400.58"
- process $proc$ls180.v:1400$3670
+ process $proc$ls180.v:1400$3677
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1401.5-1401.59"
- process $proc$ls180.v:1401$3671
+ process $proc$ls180.v:1401$3678
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1403.11-1403.65"
- process $proc$ls180.v:1403$3672
+ process $proc$ls180.v:1403$3679
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1404.5-1404.60"
- process $proc$ls180.v:1404$3673
+ process $proc$ls180.v:1404$3680
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1406.5-1406.49"
- process $proc$ls180.v:1406$3674
+ process $proc$ls180.v:1406$3681
assign { } { }
assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1407.5-1407.51"
- process $proc$ls180.v:1407$3675
+ process $proc$ls180.v:1407$3682
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1408.5-1408.52"
- process $proc$ls180.v:1408$3676
+ process $proc$ls180.v:1408$3683
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1409.11-1409.58"
- process $proc$ls180.v:1409$3677
+ process $proc$ls180.v:1409$3684
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1410.5-1410.53"
- process $proc$ls180.v:1410$3678
+ process $proc$ls180.v:1410$3685
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1411.5-1411.39"
- process $proc$ls180.v:1411$3679
+ process $proc$ls180.v:1411$3686
assign { } { }
assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
sync always
update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
end
attribute \src "ls180.v:1412.5-1412.39"
- process $proc$ls180.v:1412$3680
+ process $proc$ls180.v:1412$3687
assign { } { }
assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
sync always
update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
end
attribute \src "ls180.v:1413.5-1413.38"
- process $proc$ls180.v:1413$3681
+ process $proc$ls180.v:1413$3688
assign { } { }
assign $1\main_sdphy_datar_sink_last[0:0] 1'0
sync always
update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
end
attribute \src "ls180.v:1414.11-1414.61"
- process $proc$ls180.v:1414$3682
+ process $proc$ls180.v:1414$3689
assign { } { }
assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
sync always
update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
end
attribute \src "ls180.v:1415.5-1415.41"
- process $proc$ls180.v:1415$3683
+ process $proc$ls180.v:1415$3690
assign { } { }
assign $1\main_sdphy_datar_source_valid[0:0] 1'0
sync always
update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
end
attribute \src "ls180.v:1416.5-1416.41"
- process $proc$ls180.v:1416$3684
+ process $proc$ls180.v:1416$3691
assign { } { }
assign $1\main_sdphy_datar_source_ready[0:0] 1'0
sync always
update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
end
attribute \src "ls180.v:1417.5-1417.41"
- process $proc$ls180.v:1417$3685
+ process $proc$ls180.v:1417$3692
assign { } { }
assign $0\main_sdphy_datar_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1418.5-1418.40"
- process $proc$ls180.v:1418$3686
+ process $proc$ls180.v:1418$3693
assign { } { }
assign $1\main_sdphy_datar_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
end
attribute \src "ls180.v:1419.11-1419.54"
- process $proc$ls180.v:1419$3687
+ process $proc$ls180.v:1419$3694
assign { } { }
assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
end
attribute \src "ls180.v:1420.11-1420.56"
- process $proc$ls180.v:1420$3688
+ process $proc$ls180.v:1420$3695
assign { } { }
assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
sync always
update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
end
attribute \src "ls180.v:1421.5-1421.33"
- process $proc$ls180.v:1421$3689
+ process $proc$ls180.v:1421$3696
assign { } { }
assign $1\main_sdphy_datar_stop[0:0] 1'0
sync always
update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
end
attribute \src "ls180.v:1422.12-1422.49"
- process $proc$ls180.v:1422$3690
+ process $proc$ls180.v:1422$3697
assign { } { }
assign $1\main_sdphy_datar_timeout[31:0] 500000
sync always
update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
end
attribute \src "ls180.v:1423.11-1423.41"
- process $proc$ls180.v:1423$3691
+ process $proc$ls180.v:1423$3698
assign { } { }
assign $1\main_sdphy_datar_count[9:0] 10'0000000000
sync always
update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
end
attribute \src "ls180.v:1425.5-1425.48"
- process $proc$ls180.v:1425$3692
+ process $proc$ls180.v:1425$3699
assign { } { }
assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1436.5-1436.55"
- process $proc$ls180.v:1436$3693
+ process $proc$ls180.v:1436$3700
assign { } { }
assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
sync always
update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
end
attribute \src "ls180.v:1441.5-1441.38"
- process $proc$ls180.v:1441$3694
+ process $proc$ls180.v:1441$3701
assign { } { }
assign $1\main_sdphy_datar_datar_run[0:0] 1'0
sync always
update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
end
attribute \src "ls180.v:1444.5-1444.55"
- process $proc$ls180.v:1444$3695
+ process $proc$ls180.v:1444$3702
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1445.5-1445.54"
- process $proc$ls180.v:1445$3696
+ process $proc$ls180.v:1445$3703
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1449.5-1449.57"
- process $proc$ls180.v:1449$3697
+ process $proc$ls180.v:1449$3704
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
end
attribute \src "ls180.v:1450.5-1450.56"
- process $proc$ls180.v:1450$3698
+ process $proc$ls180.v:1450$3705
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
end
attribute \src "ls180.v:1451.11-1451.70"
- process $proc$ls180.v:1451$3699
+ process $proc$ls180.v:1451$3706
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1452.11-1452.83"
- process $proc$ls180.v:1452$3700
+ process $proc$ls180.v:1452$3707
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
sync always
update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
end
attribute \src "ls180.v:1453.5-1453.50"
- process $proc$ls180.v:1453$3701
+ process $proc$ls180.v:1453$3708
assign { } { }
assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
end
attribute \src "ls180.v:1455.5-1455.55"
- process $proc$ls180.v:1455$3702
+ process $proc$ls180.v:1455$3709
assign { } { }
assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1466.5-1466.51"
- process $proc$ls180.v:1466$3703
+ process $proc$ls180.v:1466$3710
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
end
attribute \src "ls180.v:1468.5-1468.51"
- process $proc$ls180.v:1468$3704
+ process $proc$ls180.v:1468$3711
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
end
attribute \src "ls180.v:1469.5-1469.50"
- process $proc$ls180.v:1469$3705
+ process $proc$ls180.v:1469$3712
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
end
attribute \src "ls180.v:1470.11-1470.64"
- process $proc$ls180.v:1470$3706
+ process $proc$ls180.v:1470$3713
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1471.5-1471.40"
- process $proc$ls180.v:1471$3707
+ process $proc$ls180.v:1471$3714
assign { } { }
assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
end
attribute \src "ls180.v:1473.5-1473.35"
- process $proc$ls180.v:1473$3708
+ process $proc$ls180.v:1473$3715
assign { } { }
assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
sync always
update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
end
attribute \src "ls180.v:1476.11-1476.42"
- process $proc$ls180.v:1476$3709
+ process $proc$ls180.v:1476$3716
assign { } { }
assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
sync always
update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
attribute \src "ls180.v:1489.12-1489.52"
- process $proc$ls180.v:1489$3710
+ process $proc$ls180.v:1489$3717
assign { } { }
assign $1\main_sdcore_cmd_argument_storage[31:0] 0
sync always
update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
end
attribute \src "ls180.v:1490.5-1490.39"
- process $proc$ls180.v:1490$3711
+ process $proc$ls180.v:1490$3718
assign { } { }
assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
sync always
update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
end
attribute \src "ls180.v:1491.12-1491.51"
- process $proc$ls180.v:1491$3712
+ process $proc$ls180.v:1491$3719
assign { } { }
assign $1\main_sdcore_cmd_command_storage[31:0] 0
sync always
update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
end
attribute \src "ls180.v:1492.5-1492.38"
- process $proc$ls180.v:1492$3713
+ process $proc$ls180.v:1492$3720
assign { } { }
assign $1\main_sdcore_cmd_command_re[0:0] 1'0
sync always
update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
end
attribute \src "ls180.v:1496.5-1496.34"
- process $proc$ls180.v:1496$3714
+ process $proc$ls180.v:1496$3721
assign { } { }
assign $0\main_sdcore_cmd_send_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1497.13-1497.53"
- process $proc$ls180.v:1497$3715
+ process $proc$ls180.v:1497$3722
assign { } { }
assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
end
attribute \src "ls180.v:1503.11-1503.51"
- process $proc$ls180.v:1503$3716
+ process $proc$ls180.v:1503$3723
assign { } { }
assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
sync always
update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
end
attribute \src "ls180.v:1504.5-1504.39"
- process $proc$ls180.v:1504$3717
+ process $proc$ls180.v:1504$3724
assign { } { }
assign $1\main_sdcore_block_length_re[0:0] 1'0
sync always
update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
end
attribute \src "ls180.v:1505.12-1505.51"
- process $proc$ls180.v:1505$3718
+ process $proc$ls180.v:1505$3725
assign { } { }
assign $1\main_sdcore_block_count_storage[31:0] 0
sync always
update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
end
attribute \src "ls180.v:1506.5-1506.38"
- process $proc$ls180.v:1506$3719
+ process $proc$ls180.v:1506$3726
assign { } { }
assign $1\main_sdcore_block_count_re[0:0] 1'0
sync always
update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
end
attribute \src "ls180.v:1507.11-1507.51"
- process $proc$ls180.v:1507$3720
+ process $proc$ls180.v:1507$3727
assign { } { }
assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
sync always
update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
end
attribute \src "ls180.v:1549.11-1549.47"
- process $proc$ls180.v:1549$3721
+ process $proc$ls180.v:1549$3728
assign { } { }
assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
sync always
update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
end
attribute \src "ls180.v:1553.5-1553.49"
- process $proc$ls180.v:1553$3722
+ process $proc$ls180.v:1553$3729
assign { } { }
assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
end
attribute \src "ls180.v:1557.5-1557.51"
- process $proc$ls180.v:1557$3723
+ process $proc$ls180.v:1557$3730
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
end
attribute \src "ls180.v:1558.5-1558.51"
- process $proc$ls180.v:1558$3724
+ process $proc$ls180.v:1558$3731
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
end
attribute \src "ls180.v:1559.5-1559.51"
- process $proc$ls180.v:1559$3725
+ process $proc$ls180.v:1559$3732
assign { } { }
assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1560.5-1560.50"
- process $proc$ls180.v:1560$3726
+ process $proc$ls180.v:1560$3733
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
end
attribute \src "ls180.v:1561.11-1561.64"
- process $proc$ls180.v:1561$3727
+ process $proc$ls180.v:1561$3734
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
end
attribute \src "ls180.v:1562.11-1562.48"
- process $proc$ls180.v:1562$3728
+ process $proc$ls180.v:1562$3735
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
sync always
update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
end
attribute \src "ls180.v:1563.12-1563.59"
- process $proc$ls180.v:1563$3729
+ process $proc$ls180.v:1563$3736
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
end
attribute \src "ls180.v:1567.12-1567.55"
- process $proc$ls180.v:1567$3730
+ process $proc$ls180.v:1567$3737
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
attribute \src "ls180.v:1570.12-1570.59"
- process $proc$ls180.v:1570$3731
+ process $proc$ls180.v:1570$3738
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
end
attribute \src "ls180.v:1574.12-1574.55"
- process $proc$ls180.v:1574$3732
+ process $proc$ls180.v:1574$3739
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
attribute \src "ls180.v:1577.12-1577.59"
- process $proc$ls180.v:1577$3733
+ process $proc$ls180.v:1577$3740
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
end
attribute \src "ls180.v:1581.12-1581.55"
- process $proc$ls180.v:1581$3734
+ process $proc$ls180.v:1581$3741
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
attribute \src "ls180.v:1584.12-1584.59"
- process $proc$ls180.v:1584$3735
+ process $proc$ls180.v:1584$3742
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
end
attribute \src "ls180.v:1588.12-1588.55"
- process $proc$ls180.v:1588$3736
+ process $proc$ls180.v:1588$3743
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
attribute \src "ls180.v:1591.12-1591.54"
- process $proc$ls180.v:1591$3737
+ process $proc$ls180.v:1591$3744
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
end
attribute \src "ls180.v:1592.12-1592.54"
- process $proc$ls180.v:1592$3738
+ process $proc$ls180.v:1592$3745
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
end
attribute \src "ls180.v:1593.12-1593.54"
- process $proc$ls180.v:1593$3739
+ process $proc$ls180.v:1593$3746
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
end
attribute \src "ls180.v:1594.12-1594.54"
- process $proc$ls180.v:1594$3740
+ process $proc$ls180.v:1594$3747
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
end
attribute \src "ls180.v:1595.5-1595.48"
- process $proc$ls180.v:1595$3741
+ process $proc$ls180.v:1595$3748
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
end
attribute \src "ls180.v:1596.5-1596.48"
- process $proc$ls180.v:1596$3742
+ process $proc$ls180.v:1596$3749
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
end
attribute \src "ls180.v:1597.5-1597.48"
- process $proc$ls180.v:1597$3743
+ process $proc$ls180.v:1597$3750
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
end
attribute \src "ls180.v:1598.5-1598.47"
- process $proc$ls180.v:1598$3744
+ process $proc$ls180.v:1598$3751
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
end
attribute \src "ls180.v:1599.11-1599.61"
- process $proc$ls180.v:1599$3745
+ process $proc$ls180.v:1599$3752
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
end
attribute \src "ls180.v:1600.5-1600.50"
- process $proc$ls180.v:1600$3746
+ process $proc$ls180.v:1600$3753
assign { } { }
assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
end
attribute \src "ls180.v:1602.5-1602.50"
- process $proc$ls180.v:1602$3747
+ process $proc$ls180.v:1602$3754
assign { } { }
assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1605.11-1605.47"
- process $proc$ls180.v:1605$3748
+ process $proc$ls180.v:1605$3755
assign { } { }
assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
sync always
update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
end
attribute \src "ls180.v:1606.11-1606.47"
- process $proc$ls180.v:1606$3749
+ process $proc$ls180.v:1606$3756
assign { } { }
assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
sync always
update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
end
attribute \src "ls180.v:1607.12-1607.58"
- process $proc$ls180.v:1607$3750
+ process $proc$ls180.v:1607$3757
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
end
attribute \src "ls180.v:1611.12-1611.54"
- process $proc$ls180.v:1611$3751
+ process $proc$ls180.v:1611$3758
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
end
attribute \src "ls180.v:1612.5-1612.46"
- process $proc$ls180.v:1612$3752
+ process $proc$ls180.v:1612$3759
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
end
attribute \src "ls180.v:1614.12-1614.58"
- process $proc$ls180.v:1614$3753
+ process $proc$ls180.v:1614$3760
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
end
attribute \src "ls180.v:1618.12-1618.54"
- process $proc$ls180.v:1618$3754
+ process $proc$ls180.v:1618$3761
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
end
attribute \src "ls180.v:1619.5-1619.46"
- process $proc$ls180.v:1619$3755
+ process $proc$ls180.v:1619$3762
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
end
attribute \src "ls180.v:1621.12-1621.58"
- process $proc$ls180.v:1621$3756
+ process $proc$ls180.v:1621$3763
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
end
attribute \src "ls180.v:1625.12-1625.54"
- process $proc$ls180.v:1625$3757
+ process $proc$ls180.v:1625$3764
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
end
attribute \src "ls180.v:1626.5-1626.46"
- process $proc$ls180.v:1626$3758
+ process $proc$ls180.v:1626$3765
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
end
attribute \src "ls180.v:1628.12-1628.58"
- process $proc$ls180.v:1628$3759
+ process $proc$ls180.v:1628$3766
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
end
attribute \src "ls180.v:1632.12-1632.54"
- process $proc$ls180.v:1632$3760
+ process $proc$ls180.v:1632$3767
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
end
attribute \src "ls180.v:1633.5-1633.46"
- process $proc$ls180.v:1633$3761
+ process $proc$ls180.v:1633$3768
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
end
attribute \src "ls180.v:1635.12-1635.53"
- process $proc$ls180.v:1635$3762
+ process $proc$ls180.v:1635$3769
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
end
attribute \src "ls180.v:1636.12-1636.53"
- process $proc$ls180.v:1636$3763
+ process $proc$ls180.v:1636$3770
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
end
attribute \src "ls180.v:1637.12-1637.53"
- process $proc$ls180.v:1637$3764
+ process $proc$ls180.v:1637$3771
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
end
attribute \src "ls180.v:1638.12-1638.53"
- process $proc$ls180.v:1638$3765
+ process $proc$ls180.v:1638$3772
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
end
attribute \src "ls180.v:1639.5-1639.43"
- process $proc$ls180.v:1639$3766
+ process $proc$ls180.v:1639$3773
assign { } { }
assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
end
attribute \src "ls180.v:1640.12-1640.51"
- process $proc$ls180.v:1640$3767
+ process $proc$ls180.v:1640$3774
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
end
attribute \src "ls180.v:1641.12-1641.51"
- process $proc$ls180.v:1641$3768
+ process $proc$ls180.v:1641$3775
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
end
attribute \src "ls180.v:1642.12-1642.51"
- process $proc$ls180.v:1642$3769
+ process $proc$ls180.v:1642$3776
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
end
attribute \src "ls180.v:1643.12-1643.51"
- process $proc$ls180.v:1643$3770
+ process $proc$ls180.v:1643$3777
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
end
attribute \src "ls180.v:1645.11-1645.39"
- process $proc$ls180.v:1645$3771
+ process $proc$ls180.v:1645$3778
assign { } { }
assign $1\main_sdcore_cmd_count[2:0] 3'000
sync always
update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
end
attribute \src "ls180.v:1646.5-1646.32"
- process $proc$ls180.v:1646$3772
+ process $proc$ls180.v:1646$3779
assign { } { }
assign $1\main_sdcore_cmd_done[0:0] 1'0
sync always
update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
end
attribute \src "ls180.v:1647.5-1647.33"
- process $proc$ls180.v:1647$3773
+ process $proc$ls180.v:1647$3780
assign { } { }
assign $1\main_sdcore_cmd_error[0:0] 1'0
sync always
update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
end
attribute \src "ls180.v:1648.5-1648.35"
- process $proc$ls180.v:1648$3774
+ process $proc$ls180.v:1648$3781
assign { } { }
assign $1\main_sdcore_cmd_timeout[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
end
attribute \src "ls180.v:1650.12-1650.42"
- process $proc$ls180.v:1650$3775
+ process $proc$ls180.v:1650$3782
assign { } { }
assign $1\main_sdcore_data_count[31:0] 0
sync always
update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
end
attribute \src "ls180.v:1651.5-1651.33"
- process $proc$ls180.v:1651$3776
+ process $proc$ls180.v:1651$3783
assign { } { }
assign $1\main_sdcore_data_done[0:0] 1'0
sync always
update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
end
attribute \src "ls180.v:1652.5-1652.34"
- process $proc$ls180.v:1652$3777
+ process $proc$ls180.v:1652$3784
assign { } { }
assign $1\main_sdcore_data_error[0:0] 1'0
sync always
update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
end
attribute \src "ls180.v:1653.5-1653.36"
- process $proc$ls180.v:1653$3778
+ process $proc$ls180.v:1653$3785
assign { } { }
assign $1\main_sdcore_data_timeout[0:0] 1'0
sync always
update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
end
attribute \src "ls180.v:1662.11-1662.41"
- process $proc$ls180.v:1662$3779
+ process $proc$ls180.v:1662$3786
assign { } { }
assign $0\main_interface0_bus_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:1663.11-1663.41"
- process $proc$ls180.v:1663$3780
+ process $proc$ls180.v:1663$3787
assign { } { }
assign $0\main_interface0_bus_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:1686.11-1686.45"
- process $proc$ls180.v:1686$3781
+ process $proc$ls180.v:1686$3788
assign { } { }
assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
sync always
update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
end
attribute \src "ls180.v:1687.5-1687.41"
- process $proc$ls180.v:1687$3782
+ process $proc$ls180.v:1687$3789
assign { } { }
assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1688.11-1688.47"
- process $proc$ls180.v:1688$3783
+ process $proc$ls180.v:1688$3790
assign { } { }
assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
sync always
update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
end
attribute \src "ls180.v:1689.11-1689.47"
- process $proc$ls180.v:1689$3784
+ process $proc$ls180.v:1689$3791
assign { } { }
assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
sync always
update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
end
attribute \src "ls180.v:1690.11-1690.50"
- process $proc$ls180.v:1690$3785
+ process $proc$ls180.v:1690$3792
assign { } { }
assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
sync always
update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
end
attribute \src "ls180.v:1710.5-1710.51"
- process $proc$ls180.v:1710$3786
+ process $proc$ls180.v:1710$3793
assign { } { }
assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
sync always
update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
end
attribute \src "ls180.v:1711.5-1711.50"
- process $proc$ls180.v:1711$3787
+ process $proc$ls180.v:1711$3794
assign { } { }
assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
sync always
update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
end
attribute \src "ls180.v:1712.12-1712.66"
- process $proc$ls180.v:1712$3788
+ process $proc$ls180.v:1712$3795
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0]
end
attribute \src "ls180.v:1713.11-1713.77"
- process $proc$ls180.v:1713$3789
+ process $proc$ls180.v:1713$3796
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0]
end
attribute \src "ls180.v:1714.11-1714.50"
- process $proc$ls180.v:1714$3790
+ process $proc$ls180.v:1714$3797
assign { } { }
assign $1\main_sdblock2mem_converter_demux[2:0] 3'000
sync always
update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0]
end
attribute \src "ls180.v:1716.5-1716.49"
- process $proc$ls180.v:1716$3791
+ process $proc$ls180.v:1716$3798
assign { } { }
assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
end
+ attribute \src "ls180.v:172.5-172.69"
+ process $proc$ls180.v:172$3150
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
+ sync init
+ end
attribute \src "ls180.v:1722.5-1722.45"
- process $proc$ls180.v:1722$3792
+ process $proc$ls180.v:1722$3799
assign { } { }
assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
sync always
update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
end
attribute \src "ls180.v:1724.12-1724.62"
- process $proc$ls180.v:1724$3793
+ process $proc$ls180.v:1724$3800
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
sync always
update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
end
attribute \src "ls180.v:1725.12-1725.60"
- process $proc$ls180.v:1725$3794
+ process $proc$ls180.v:1725$3801
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0]
end
attribute \src "ls180.v:1727.5-1727.57"
- process $proc$ls180.v:1727$3795
+ process $proc$ls180.v:1727$3802
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
end
attribute \src "ls180.v:1731.12-1731.67"
- process $proc$ls180.v:1731$3796
+ process $proc$ls180.v:1731$3803
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
end
attribute \src "ls180.v:1732.5-1732.54"
- process $proc$ls180.v:1732$3797
+ process $proc$ls180.v:1732$3804
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
end
attribute \src "ls180.v:1733.12-1733.69"
- process $proc$ls180.v:1733$3798
+ process $proc$ls180.v:1733$3805
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
end
attribute \src "ls180.v:1734.5-1734.56"
- process $proc$ls180.v:1734$3799
+ process $proc$ls180.v:1734$3806
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
end
attribute \src "ls180.v:1735.5-1735.61"
- process $proc$ls180.v:1735$3800
+ process $proc$ls180.v:1735$3807
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
end
attribute \src "ls180.v:1736.5-1736.56"
- process $proc$ls180.v:1736$3801
+ process $proc$ls180.v:1736$3808
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
end
attribute \src "ls180.v:1737.5-1737.53"
- process $proc$ls180.v:1737$3802
+ process $proc$ls180.v:1737$3809
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
end
attribute \src "ls180.v:1739.5-1739.59"
- process $proc$ls180.v:1739$3803
+ process $proc$ls180.v:1739$3810
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
end
attribute \src "ls180.v:1740.5-1740.54"
- process $proc$ls180.v:1740$3804
+ process $proc$ls180.v:1740$3811
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
end
attribute \src "ls180.v:1742.12-1742.61"
- process $proc$ls180.v:1742$3805
+ process $proc$ls180.v:1742$3812
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
end
attribute \src "ls180.v:1745.12-1745.43"
- process $proc$ls180.v:1745$3806
+ process $proc$ls180.v:1745$3813
assign { } { }
assign $1\main_interface1_bus_adr[31:0] 0
sync always
update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
end
attribute \src "ls180.v:1746.12-1746.45"
- process $proc$ls180.v:1746$3807
+ process $proc$ls180.v:1746$3814
assign { } { }
assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
end
attribute \src "ls180.v:1748.11-1748.41"
- process $proc$ls180.v:1748$3808
+ process $proc$ls180.v:1748$3815
assign { } { }
assign $1\main_interface1_bus_sel[7:0] 8'00000000
sync always
update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0]
end
attribute \src "ls180.v:1749.5-1749.35"
- process $proc$ls180.v:1749$3809
+ process $proc$ls180.v:1749$3816
assign { } { }
assign $1\main_interface1_bus_cyc[0:0] 1'0
sync always
update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
end
attribute \src "ls180.v:1750.5-1750.35"
- process $proc$ls180.v:1750$3810
+ process $proc$ls180.v:1750$3817
assign { } { }
assign $1\main_interface1_bus_stb[0:0] 1'0
sync always
update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
end
attribute \src "ls180.v:1752.5-1752.34"
- process $proc$ls180.v:1752$3811
+ process $proc$ls180.v:1752$3818
assign { } { }
assign $1\main_interface1_bus_we[0:0] 1'0
sync always
update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
end
attribute \src "ls180.v:1753.11-1753.41"
- process $proc$ls180.v:1753$3812
+ process $proc$ls180.v:1753$3819
assign { } { }
assign $0\main_interface1_bus_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:1754.11-1754.41"
- process $proc$ls180.v:1754$3813
+ process $proc$ls180.v:1754$3820
assign { } { }
assign $0\main_interface1_bus_bte[1:0] 2'00
sync always
update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
sync init
end
+ attribute \src "ls180.v:176.5-176.72"
+ process $proc$ls180.v:176$3151
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
+ sync init
+ end
attribute \src "ls180.v:1761.5-1761.43"
- process $proc$ls180.v:1761$3814
+ process $proc$ls180.v:1761$3821
assign { } { }
assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
end
attribute \src "ls180.v:1762.5-1762.43"
- process $proc$ls180.v:1762$3815
+ process $proc$ls180.v:1762$3822
assign { } { }
assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
end
attribute \src "ls180.v:1763.5-1763.42"
- process $proc$ls180.v:1763$3816
+ process $proc$ls180.v:1763$3823
assign { } { }
assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
end
attribute \src "ls180.v:1764.12-1764.61"
- process $proc$ls180.v:1764$3817
+ process $proc$ls180.v:1764$3824
assign { } { }
assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
sync always
update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
end
attribute \src "ls180.v:1765.5-1765.45"
- process $proc$ls180.v:1765$3818
+ process $proc$ls180.v:1765$3825
assign { } { }
assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
end
attribute \src "ls180.v:1767.5-1767.45"
- process $proc$ls180.v:1767$3819
+ process $proc$ls180.v:1767$3826
assign { } { }
assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1768.5-1768.44"
- process $proc$ls180.v:1768$3820
+ process $proc$ls180.v:1768$3827
assign { } { }
assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
end
attribute \src "ls180.v:1769.12-1769.60"
- process $proc$ls180.v:1769$3821
+ process $proc$ls180.v:1769$3828
assign { } { }
assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0]
end
attribute \src "ls180.v:1770.12-1770.45"
- process $proc$ls180.v:1770$3822
+ process $proc$ls180.v:1770$3829
assign { } { }
assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0]
end
attribute \src "ls180.v:1771.12-1771.53"
- process $proc$ls180.v:1771$3823
+ process $proc$ls180.v:1771$3830
assign { } { }
assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
end
attribute \src "ls180.v:1772.5-1772.40"
- process $proc$ls180.v:1772$3824
+ process $proc$ls180.v:1772$3831
assign { } { }
assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
end
attribute \src "ls180.v:1773.12-1773.55"
- process $proc$ls180.v:1773$3825
+ process $proc$ls180.v:1773$3832
assign { } { }
assign $1\main_sdmem2block_dma_length_storage[31:0] 0
sync always
update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
end
attribute \src "ls180.v:1774.5-1774.42"
- process $proc$ls180.v:1774$3826
+ process $proc$ls180.v:1774$3833
assign { } { }
assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
end
attribute \src "ls180.v:1775.5-1775.47"
- process $proc$ls180.v:1775$3827
+ process $proc$ls180.v:1775$3834
assign { } { }
assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
sync always
update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
end
attribute \src "ls180.v:1776.5-1776.42"
- process $proc$ls180.v:1776$3828
+ process $proc$ls180.v:1776$3835
assign { } { }
assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
end
attribute \src "ls180.v:1777.5-1777.44"
- process $proc$ls180.v:1777$3829
+ process $proc$ls180.v:1777$3836
assign { } { }
assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
sync always
update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
end
attribute \src "ls180.v:1779.5-1779.45"
- process $proc$ls180.v:1779$3830
+ process $proc$ls180.v:1779$3837
assign { } { }
assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
sync always
update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
end
attribute \src "ls180.v:1780.5-1780.40"
- process $proc$ls180.v:1780$3831
+ process $proc$ls180.v:1780$3838
assign { } { }
assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
end
attribute \src "ls180.v:1784.12-1784.47"
- process $proc$ls180.v:1784$3832
+ process $proc$ls180.v:1784$3839
assign { } { }
assign $1\main_sdmem2block_dma_offset[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
end
+ attribute \src "ls180.v:179.12-179.74"
+ process $proc$ls180.v:179$3152
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
+ sync init
+ end
attribute \src "ls180.v:1796.11-1796.64"
- process $proc$ls180.v:1796$3833
+ process $proc$ls180.v:1796$3840
assign { } { }
assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1798.11-1798.48"
- process $proc$ls180.v:1798$3834
+ process $proc$ls180.v:1798$3841
assign { } { }
assign $1\main_sdmem2block_converter_mux[2:0] 3'000
sync always
update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0]
end
attribute \src "ls180.v:1822.11-1822.45"
- process $proc$ls180.v:1822$3835
+ process $proc$ls180.v:1822$3842
assign { } { }
assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
sync always
update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
end
attribute \src "ls180.v:1823.5-1823.41"
- process $proc$ls180.v:1823$3836
+ process $proc$ls180.v:1823$3843
assign { } { }
assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1824.11-1824.47"
- process $proc$ls180.v:1824$3837
+ process $proc$ls180.v:1824$3844
assign { } { }
assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
sync always
update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
end
attribute \src "ls180.v:1825.11-1825.47"
- process $proc$ls180.v:1825$3838
+ process $proc$ls180.v:1825$3845
assign { } { }
assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
sync always
update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
end
attribute \src "ls180.v:1826.11-1826.50"
- process $proc$ls180.v:1826$3839
+ process $proc$ls180.v:1826$3846
assign { } { }
assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
end
+ attribute \src "ls180.v:183.12-183.78"
+ process $proc$ls180.v:183$3153
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+ sync init
+ end
attribute \src "ls180.v:1839.5-1839.36"
- process $proc$ls180.v:1839$3840
+ process $proc$ls180.v:1839$3847
assign { } { }
assign $1\builder_converter0_state[0:0] 1'0
sync always
update \builder_converter0_state $1\builder_converter0_state[0:0]
end
attribute \src "ls180.v:1840.5-1840.41"
- process $proc$ls180.v:1840$3841
+ process $proc$ls180.v:1840$3848
assign { } { }
assign $1\builder_converter0_next_state[0:0] 1'0
sync always
update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
end
attribute \src "ls180.v:1841.5-1841.57"
- process $proc$ls180.v:1841$3842
+ process $proc$ls180.v:1841$3849
assign { } { }
assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0
sync always
update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0]
end
attribute \src "ls180.v:1842.5-1842.60"
- process $proc$ls180.v:1842$3843
+ process $proc$ls180.v:1842$3850
assign { } { }
assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0
sync always
update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0]
end
attribute \src "ls180.v:1843.5-1843.36"
- process $proc$ls180.v:1843$3844
+ process $proc$ls180.v:1843$3851
assign { } { }
assign $1\builder_converter1_state[0:0] 1'0
sync always
update \builder_converter1_state $1\builder_converter1_state[0:0]
end
attribute \src "ls180.v:1844.5-1844.41"
- process $proc$ls180.v:1844$3845
+ process $proc$ls180.v:1844$3852
assign { } { }
assign $1\builder_converter1_next_state[0:0] 1'0
sync always
update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
end
attribute \src "ls180.v:1845.5-1845.57"
- process $proc$ls180.v:1845$3846
+ process $proc$ls180.v:1845$3853
assign { } { }
assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0
sync always
update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0]
end
attribute \src "ls180.v:1846.5-1846.60"
- process $proc$ls180.v:1846$3847
+ process $proc$ls180.v:1846$3854
assign { } { }
assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0
sync always
update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0]
end
attribute \src "ls180.v:1847.5-1847.36"
- process $proc$ls180.v:1847$3848
+ process $proc$ls180.v:1847$3855
assign { } { }
assign $1\builder_converter2_state[0:0] 1'0
sync always
update \builder_converter2_state $1\builder_converter2_state[0:0]
end
attribute \src "ls180.v:1848.5-1848.41"
- process $proc$ls180.v:1848$3849
+ process $proc$ls180.v:1848$3856
assign { } { }
assign $1\builder_converter2_next_state[0:0] 1'0
sync always
update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
end
attribute \src "ls180.v:1849.5-1849.60"
- process $proc$ls180.v:1849$3850
+ process $proc$ls180.v:1849$3857
assign { } { }
assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0
sync always
update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0]
end
attribute \src "ls180.v:1850.5-1850.63"
- process $proc$ls180.v:1850$3851
+ process $proc$ls180.v:1850$3858
assign { } { }
assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0
sync always
update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0]
end
attribute \src "ls180.v:1851.11-1851.41"
- process $proc$ls180.v:1851$3852
+ process $proc$ls180.v:1851$3859
assign { } { }
assign $1\builder_refresher_state[1:0] 2'00
sync always
update \builder_refresher_state $1\builder_refresher_state[1:0]
end
attribute \src "ls180.v:1852.11-1852.46"
- process $proc$ls180.v:1852$3853
+ process $proc$ls180.v:1852$3860
assign { } { }
assign $1\builder_refresher_next_state[1:0] 2'00
sync always
update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
end
attribute \src "ls180.v:1853.11-1853.44"
- process $proc$ls180.v:1853$3854
+ process $proc$ls180.v:1853$3861
assign { } { }
assign $1\builder_bankmachine0_state[2:0] 3'000
sync always
update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
end
attribute \src "ls180.v:1854.11-1854.49"
- process $proc$ls180.v:1854$3855
+ process $proc$ls180.v:1854$3862
assign { } { }
assign $1\builder_bankmachine0_next_state[2:0] 3'000
sync always
update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
end
attribute \src "ls180.v:1855.11-1855.44"
- process $proc$ls180.v:1855$3856
+ process $proc$ls180.v:1855$3863
assign { } { }
assign $1\builder_bankmachine1_state[2:0] 3'000
sync always
update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
end
attribute \src "ls180.v:1856.11-1856.49"
- process $proc$ls180.v:1856$3857
+ process $proc$ls180.v:1856$3864
assign { } { }
assign $1\builder_bankmachine1_next_state[2:0] 3'000
sync always
update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
end
attribute \src "ls180.v:1857.11-1857.44"
- process $proc$ls180.v:1857$3858
+ process $proc$ls180.v:1857$3865
assign { } { }
assign $1\builder_bankmachine2_state[2:0] 3'000
sync always
update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
end
attribute \src "ls180.v:1858.11-1858.49"
- process $proc$ls180.v:1858$3859
+ process $proc$ls180.v:1858$3866
assign { } { }
assign $1\builder_bankmachine2_next_state[2:0] 3'000
sync always
update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
end
attribute \src "ls180.v:1859.11-1859.44"
- process $proc$ls180.v:1859$3860
+ process $proc$ls180.v:1859$3867
assign { } { }
assign $1\builder_bankmachine3_state[2:0] 3'000
sync always
update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
end
attribute \src "ls180.v:1860.11-1860.49"
- process $proc$ls180.v:1860$3861
+ process $proc$ls180.v:1860$3868
assign { } { }
assign $1\builder_bankmachine3_next_state[2:0] 3'000
sync always
update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
end
attribute \src "ls180.v:1861.11-1861.43"
- process $proc$ls180.v:1861$3862
+ process $proc$ls180.v:1861$3869
assign { } { }
assign $1\builder_multiplexer_state[2:0] 3'000
sync always
update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
end
attribute \src "ls180.v:1862.11-1862.48"
- process $proc$ls180.v:1862$3863
+ process $proc$ls180.v:1862$3870
assign { } { }
assign $1\builder_multiplexer_next_state[2:0] 3'000
sync always
update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
end
attribute \src "ls180.v:1875.5-1875.27"
- process $proc$ls180.v:1875$3864
+ process $proc$ls180.v:1875$3871
assign { } { }
assign $0\builder_locked0[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1876.5-1876.27"
- process $proc$ls180.v:1876$3865
+ process $proc$ls180.v:1876$3872
assign { } { }
assign $0\builder_locked1[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1877.5-1877.27"
- process $proc$ls180.v:1877$3866
+ process $proc$ls180.v:1877$3873
assign { } { }
assign $0\builder_locked2[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1878.5-1878.27"
- process $proc$ls180.v:1878$3867
+ process $proc$ls180.v:1878$3874
assign { } { }
assign $0\builder_locked3[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1879.5-1879.42"
- process $proc$ls180.v:1879$3868
+ process $proc$ls180.v:1879$3875
assign { } { }
assign $1\builder_new_master_wdata_ready[0:0] 1'0
sync always
update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
end
attribute \src "ls180.v:1880.5-1880.43"
- process $proc$ls180.v:1880$3869
+ process $proc$ls180.v:1880$3876
assign { } { }
assign $1\builder_new_master_rdata_valid0[0:0] 1'0
sync always
update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
end
attribute \src "ls180.v:1881.5-1881.43"
- process $proc$ls180.v:1881$3870
+ process $proc$ls180.v:1881$3877
assign { } { }
assign $1\builder_new_master_rdata_valid1[0:0] 1'0
sync always
update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
end
attribute \src "ls180.v:1882.5-1882.43"
- process $proc$ls180.v:1882$3871
+ process $proc$ls180.v:1882$3878
assign { } { }
assign $1\builder_new_master_rdata_valid2[0:0] 1'0
sync always
update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
end
attribute \src "ls180.v:1883.5-1883.43"
- process $proc$ls180.v:1883$3872
+ process $proc$ls180.v:1883$3879
assign { } { }
assign $1\builder_new_master_rdata_valid3[0:0] 1'0
sync always
update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
end
attribute \src "ls180.v:1884.5-1884.35"
- process $proc$ls180.v:1884$3873
+ process $proc$ls180.v:1884$3880
assign { } { }
assign $1\builder_converter_state[0:0] 1'0
sync always
update \builder_converter_state $1\builder_converter_state[0:0]
end
attribute \src "ls180.v:1885.5-1885.40"
- process $proc$ls180.v:1885$3874
+ process $proc$ls180.v:1885$3881
assign { } { }
assign $1\builder_converter_next_state[0:0] 1'0
sync always
update \builder_converter_next_state $1\builder_converter_next_state[0:0]
end
attribute \src "ls180.v:1886.5-1886.55"
- process $proc$ls180.v:1886$3875
+ process $proc$ls180.v:1886$3882
assign { } { }
assign $1\main_converter_counter_converter_next_value[0:0] 1'0
sync always
update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
end
attribute \src "ls180.v:1887.5-1887.58"
- process $proc$ls180.v:1887$3876
+ process $proc$ls180.v:1887$3883
assign { } { }
assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
sync always
update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
end
attribute \src "ls180.v:1888.11-1888.42"
- process $proc$ls180.v:1888$3877
+ process $proc$ls180.v:1888$3884
assign { } { }
assign $1\builder_spimaster0_state[1:0] 2'00
sync always
update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
end
attribute \src "ls180.v:1889.11-1889.47"
- process $proc$ls180.v:1889$3878
+ process $proc$ls180.v:1889$3885
assign { } { }
assign $1\builder_spimaster0_next_state[1:0] 2'00
sync always
update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
end
attribute \src "ls180.v:1890.11-1890.62"
- process $proc$ls180.v:1890$3879
+ process $proc$ls180.v:1890$3886
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
sync always
update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
end
attribute \src "ls180.v:1891.5-1891.59"
- process $proc$ls180.v:1891$3880
+ process $proc$ls180.v:1891$3887
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
sync always
update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
end
attribute \src "ls180.v:1892.11-1892.42"
- process $proc$ls180.v:1892$3881
+ process $proc$ls180.v:1892$3888
assign { } { }
assign $1\builder_spimaster1_state[1:0] 2'00
sync always
update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
end
attribute \src "ls180.v:1893.11-1893.47"
- process $proc$ls180.v:1893$3882
+ process $proc$ls180.v:1893$3889
assign { } { }
assign $1\builder_spimaster1_next_state[1:0] 2'00
sync always
update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
end
attribute \src "ls180.v:1894.11-1894.60"
- process $proc$ls180.v:1894$3883
+ process $proc$ls180.v:1894$3890
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
sync always
update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
end
attribute \src "ls180.v:1895.5-1895.57"
- process $proc$ls180.v:1895$3884
+ process $proc$ls180.v:1895$3891
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
sync always
update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
attribute \src "ls180.v:1896.5-1896.41"
- process $proc$ls180.v:1896$3885
+ process $proc$ls180.v:1896$3892
assign { } { }
assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
sync always
update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
end
attribute \src "ls180.v:1897.5-1897.46"
- process $proc$ls180.v:1897$3886
+ process $proc$ls180.v:1897$3893
assign { } { }
assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
sync always
update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
end
attribute \src "ls180.v:1898.11-1898.66"
- process $proc$ls180.v:1898$3887
+ process $proc$ls180.v:1898$3894
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
sync always
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
end
attribute \src "ls180.v:1899.5-1899.63"
- process $proc$ls180.v:1899$3888
+ process $proc$ls180.v:1899$3895
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
attribute \src "ls180.v:1900.11-1900.47"
- process $proc$ls180.v:1900$3889
+ process $proc$ls180.v:1900$3896
assign { } { }
assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
sync always
update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
end
attribute \src "ls180.v:1901.11-1901.52"
- process $proc$ls180.v:1901$3890
+ process $proc$ls180.v:1901$3897
assign { } { }
assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
sync always
update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
end
attribute \src "ls180.v:1902.11-1902.66"
- process $proc$ls180.v:1902$3891
+ process $proc$ls180.v:1902$3898
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
end
attribute \src "ls180.v:1903.5-1903.63"
- process $proc$ls180.v:1903$3892
+ process $proc$ls180.v:1903$3899
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
attribute \src "ls180.v:1904.11-1904.47"
- process $proc$ls180.v:1904$3893
+ process $proc$ls180.v:1904$3900
assign { } { }
assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
sync always
update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
end
attribute \src "ls180.v:1905.11-1905.52"
- process $proc$ls180.v:1905$3894
+ process $proc$ls180.v:1905$3901
assign { } { }
assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
sync always
update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
end
attribute \src "ls180.v:1906.11-1906.67"
- process $proc$ls180.v:1906$3895
+ process $proc$ls180.v:1906$3902
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
end
attribute \src "ls180.v:1907.5-1907.64"
- process $proc$ls180.v:1907$3896
+ process $proc$ls180.v:1907$3903
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
sync always
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
end
attribute \src "ls180.v:1908.12-1908.71"
- process $proc$ls180.v:1908$3897
+ process $proc$ls180.v:1908$3904
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
sync always
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
end
attribute \src "ls180.v:1909.5-1909.66"
- process $proc$ls180.v:1909$3898
+ process $proc$ls180.v:1909$3905
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
sync always
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
end
attribute \src "ls180.v:1910.5-1910.66"
- process $proc$ls180.v:1910$3899
+ process $proc$ls180.v:1910$3906
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
end
attribute \src "ls180.v:1911.5-1911.69"
- process $proc$ls180.v:1911$3900
+ process $proc$ls180.v:1911$3907
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
attribute \src "ls180.v:1912.5-1912.41"
- process $proc$ls180.v:1912$3901
+ process $proc$ls180.v:1912$3908
assign { } { }
assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
sync always
update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
end
attribute \src "ls180.v:1913.5-1913.46"
- process $proc$ls180.v:1913$3902
+ process $proc$ls180.v:1913$3909
assign { } { }
assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
sync always
update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
end
attribute \src "ls180.v:1914.5-1914.66"
- process $proc$ls180.v:1914$3903
+ process $proc$ls180.v:1914$3910
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
end
attribute \src "ls180.v:1915.5-1915.69"
- process $proc$ls180.v:1915$3904
+ process $proc$ls180.v:1915$3911
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
attribute \src "ls180.v:1916.11-1916.41"
- process $proc$ls180.v:1916$3905
+ process $proc$ls180.v:1916$3912
assign { } { }
assign $1\builder_sdphy_fsm_state[2:0] 3'000
sync always
update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
end
attribute \src "ls180.v:1917.11-1917.46"
- process $proc$ls180.v:1917$3906
+ process $proc$ls180.v:1917$3913
assign { } { }
assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
sync always
update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
end
attribute \src "ls180.v:1918.11-1918.61"
- process $proc$ls180.v:1918$3907
+ process $proc$ls180.v:1918$3914
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
end
attribute \src "ls180.v:1919.5-1919.58"
- process $proc$ls180.v:1919$3908
+ process $proc$ls180.v:1919$3915
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:1920.11-1920.48"
- process $proc$ls180.v:1920$3909
+ process $proc$ls180.v:1920$3916
assign { } { }
assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
sync always
update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
end
attribute \src "ls180.v:1921.11-1921.53"
- process $proc$ls180.v:1921$3910
+ process $proc$ls180.v:1921$3917
assign { } { }
assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
sync always
update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
end
attribute \src "ls180.v:1922.11-1922.70"
- process $proc$ls180.v:1922$3911
+ process $proc$ls180.v:1922$3918
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
sync always
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
end
attribute \src "ls180.v:1923.5-1923.66"
- process $proc$ls180.v:1923$3912
+ process $proc$ls180.v:1923$3919
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
sync always
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
end
attribute \src "ls180.v:1924.12-1924.73"
- process $proc$ls180.v:1924$3913
+ process $proc$ls180.v:1924$3920
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
sync always
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
end
attribute \src "ls180.v:1925.5-1925.68"
- process $proc$ls180.v:1925$3914
+ process $proc$ls180.v:1925$3921
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
sync always
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
end
attribute \src "ls180.v:1926.5-1926.69"
- process $proc$ls180.v:1926$3915
+ process $proc$ls180.v:1926$3922
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
end
attribute \src "ls180.v:1927.5-1927.72"
- process $proc$ls180.v:1927$3916
+ process $proc$ls180.v:1927$3923
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
attribute \src "ls180.v:1928.5-1928.52"
- process $proc$ls180.v:1928$3917
+ process $proc$ls180.v:1928$3924
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
sync always
update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
end
attribute \src "ls180.v:1929.5-1929.57"
- process $proc$ls180.v:1929$3918
+ process $proc$ls180.v:1929$3925
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
sync always
update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
end
attribute \src "ls180.v:1930.12-1930.93"
- process $proc$ls180.v:1930$3919
+ process $proc$ls180.v:1930$3926
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
end
attribute \src "ls180.v:1931.5-1931.88"
- process $proc$ls180.v:1931$3920
+ process $proc$ls180.v:1931$3927
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
end
attribute \src "ls180.v:1932.12-1932.93"
- process $proc$ls180.v:1932$3921
+ process $proc$ls180.v:1932$3928
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
end
attribute \src "ls180.v:1933.5-1933.88"
- process $proc$ls180.v:1933$3922
+ process $proc$ls180.v:1933$3929
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
end
attribute \src "ls180.v:1934.12-1934.93"
- process $proc$ls180.v:1934$3923
+ process $proc$ls180.v:1934$3930
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
end
attribute \src "ls180.v:1935.5-1935.88"
- process $proc$ls180.v:1935$3924
+ process $proc$ls180.v:1935$3931
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
end
attribute \src "ls180.v:1936.12-1936.93"
- process $proc$ls180.v:1936$3925
+ process $proc$ls180.v:1936$3932
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
end
attribute \src "ls180.v:1937.5-1937.88"
- process $proc$ls180.v:1937$3926
+ process $proc$ls180.v:1937$3933
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
end
attribute \src "ls180.v:1938.11-1938.87"
- process $proc$ls180.v:1938$3927
+ process $proc$ls180.v:1938$3934
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
sync always
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
end
attribute \src "ls180.v:1939.5-1939.84"
- process $proc$ls180.v:1939$3928
+ process $proc$ls180.v:1939$3935
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
attribute \src "ls180.v:1940.11-1940.42"
- process $proc$ls180.v:1940$3929
+ process $proc$ls180.v:1940$3936
assign { } { }
assign $1\builder_sdcore_fsm_state[2:0] 3'000
sync always
update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
end
attribute \src "ls180.v:1941.11-1941.47"
- process $proc$ls180.v:1941$3930
+ process $proc$ls180.v:1941$3937
assign { } { }
assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
sync always
update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
end
attribute \src "ls180.v:1942.5-1942.55"
- process $proc$ls180.v:1942$3931
+ process $proc$ls180.v:1942$3938
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
sync always
update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
end
attribute \src "ls180.v:1943.5-1943.58"
- process $proc$ls180.v:1943$3932
+ process $proc$ls180.v:1943$3939
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
sync always
update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
end
attribute \src "ls180.v:1944.5-1944.56"
- process $proc$ls180.v:1944$3933
+ process $proc$ls180.v:1944$3940
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
sync always
update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
end
attribute \src "ls180.v:1945.5-1945.59"
- process $proc$ls180.v:1945$3934
+ process $proc$ls180.v:1945$3941
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
sync always
update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
end
attribute \src "ls180.v:1946.11-1946.62"
- process $proc$ls180.v:1946$3935
+ process $proc$ls180.v:1946$3942
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
sync always
update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
end
attribute \src "ls180.v:1947.5-1947.59"
- process $proc$ls180.v:1947$3936
+ process $proc$ls180.v:1947$3943
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
sync always
update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
end
attribute \src "ls180.v:1948.12-1948.65"
- process $proc$ls180.v:1948$3937
+ process $proc$ls180.v:1948$3944
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
sync always
update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
end
attribute \src "ls180.v:1949.5-1949.60"
- process $proc$ls180.v:1949$3938
+ process $proc$ls180.v:1949$3945
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
sync always
update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
end
attribute \src "ls180.v:1950.5-1950.56"
- process $proc$ls180.v:1950$3939
+ process $proc$ls180.v:1950$3946
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
sync always
update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
end
attribute \src "ls180.v:1951.5-1951.59"
- process $proc$ls180.v:1951$3940
+ process $proc$ls180.v:1951$3947
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
sync always
update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
end
attribute \src "ls180.v:1952.5-1952.58"
- process $proc$ls180.v:1952$3941
+ process $proc$ls180.v:1952$3948
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
end
attribute \src "ls180.v:1953.5-1953.61"
- process $proc$ls180.v:1953$3942
+ process $proc$ls180.v:1953$3949
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
end
attribute \src "ls180.v:1954.5-1954.57"
- process $proc$ls180.v:1954$3943
+ process $proc$ls180.v:1954$3950
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
sync always
update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
end
attribute \src "ls180.v:1955.5-1955.60"
- process $proc$ls180.v:1955$3944
+ process $proc$ls180.v:1955$3951
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
sync always
update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
end
attribute \src "ls180.v:1956.5-1956.59"
- process $proc$ls180.v:1956$3945
+ process $proc$ls180.v:1956$3952
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
sync always
update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
end
attribute \src "ls180.v:1957.5-1957.62"
- process $proc$ls180.v:1957$3946
+ process $proc$ls180.v:1957$3953
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
sync always
update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
end
attribute \src "ls180.v:1958.13-1958.76"
- process $proc$ls180.v:1958$3947
+ process $proc$ls180.v:1958$3954
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
end
attribute \src "ls180.v:1959.5-1959.69"
- process $proc$ls180.v:1959$3948
+ process $proc$ls180.v:1959$3955
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
sync always
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
attribute \src "ls180.v:1960.11-1960.46"
- process $proc$ls180.v:1960$3949
+ process $proc$ls180.v:1960$3956
assign { } { }
assign $1\builder_sdblock2memdma_state[1:0] 2'00
sync always
update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
end
attribute \src "ls180.v:1961.11-1961.51"
- process $proc$ls180.v:1961$3950
+ process $proc$ls180.v:1961$3957
assign { } { }
assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
sync always
update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
end
attribute \src "ls180.v:1962.12-1962.87"
- process $proc$ls180.v:1962$3951
+ process $proc$ls180.v:1962$3958
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
end
attribute \src "ls180.v:1963.5-1963.82"
- process $proc$ls180.v:1963$3952
+ process $proc$ls180.v:1963$3959
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
attribute \src "ls180.v:1964.5-1964.44"
- process $proc$ls180.v:1964$3953
+ process $proc$ls180.v:1964$3960
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
sync always
update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
end
attribute \src "ls180.v:1965.5-1965.49"
- process $proc$ls180.v:1965$3954
+ process $proc$ls180.v:1965$3961
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
sync always
update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
end
attribute \src "ls180.v:1966.12-1966.75"
- process $proc$ls180.v:1966$3955
+ process $proc$ls180.v:1966$3962
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0]
end
attribute \src "ls180.v:1967.5-1967.70"
- process $proc$ls180.v:1967$3956
+ process $proc$ls180.v:1967$3963
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:1968.11-1968.60"
- process $proc$ls180.v:1968$3957
+ process $proc$ls180.v:1968$3964
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
sync always
update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
end
attribute \src "ls180.v:1969.11-1969.65"
- process $proc$ls180.v:1969$3958
+ process $proc$ls180.v:1969$3965
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
sync always
sync init
update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
end
+ attribute \src "ls180.v:197.5-197.74"
+ process $proc$ls180.v:197$3154
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
+ sync init
+ end
attribute \src "ls180.v:1970.12-1970.87"
- process $proc$ls180.v:1970$3959
+ process $proc$ls180.v:1970$3966
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
end
attribute \src "ls180.v:1971.5-1971.82"
- process $proc$ls180.v:1971$3960
+ process $proc$ls180.v:1971$3967
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
attribute \src "ls180.v:1972.12-1972.43"
- process $proc$ls180.v:1972$3961
+ process $proc$ls180.v:1972$3968
assign { } { }
assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
sync always
update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
end
attribute \src "ls180.v:1973.5-1973.34"
- process $proc$ls180.v:1973$3962
+ process $proc$ls180.v:1973$3969
assign { } { }
assign $1\builder_libresocsim_we[0:0] 1'0
sync always
update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
end
attribute \src "ls180.v:1974.11-1974.43"
- process $proc$ls180.v:1974$3963
+ process $proc$ls180.v:1974$3970
assign { } { }
assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
sync always
update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
end
attribute \src "ls180.v:1976.12-1976.52"
- process $proc$ls180.v:1976$3964
+ process $proc$ls180.v:1976$3971
assign { } { }
assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
end
attribute \src "ls180.v:1977.12-1977.54"
- process $proc$ls180.v:1977$3965
+ process $proc$ls180.v:1977$3972
assign { } { }
assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0
sync always
sync init
end
attribute \src "ls180.v:1978.12-1978.54"
- process $proc$ls180.v:1978$3966
+ process $proc$ls180.v:1978$3973
assign { } { }
assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
sync always
update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
end
attribute \src "ls180.v:1979.11-1979.50"
- process $proc$ls180.v:1979$3967
+ process $proc$ls180.v:1979$3974
assign { } { }
assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000
sync always
update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0]
sync init
end
+ attribute \src "ls180.v:198.11-198.24"
+ process $proc$ls180.v:198$3155
+ assign { } { }
+ assign $0\eint_1[2:0] 3'000
+ sync always
+ update \eint_1 $0\eint_1[2:0]
+ sync init
+ end
attribute \src "ls180.v:1980.5-1980.44"
- process $proc$ls180.v:1980$3968
+ process $proc$ls180.v:1980$3975
assign { } { }
assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1981.5-1981.44"
- process $proc$ls180.v:1981$3969
+ process $proc$ls180.v:1981$3976
assign { } { }
assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1982.5-1982.44"
- process $proc$ls180.v:1982$3970
+ process $proc$ls180.v:1982$3977
assign { } { }
assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
sync always
update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
end
attribute \src "ls180.v:1983.5-1983.43"
- process $proc$ls180.v:1983$3971
+ process $proc$ls180.v:1983$3978
assign { } { }
assign $0\builder_libresocsim_wishbone_we[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1986.12-1986.65"
- process $proc$ls180.v:1986$3972
+ process $proc$ls180.v:1986$3979
assign { } { }
assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
end
attribute \src "ls180.v:1990.5-1990.55"
- process $proc$ls180.v:1990$3973
+ process $proc$ls180.v:1990$3980
assign { } { }
assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1994.5-1994.55"
- process $proc$ls180.v:1994$3974
+ process $proc$ls180.v:1994$3981
assign { } { }
assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1997.12-1997.40"
- process $proc$ls180.v:1997$3975
+ process $proc$ls180.v:1997$3982
assign { } { }
assign $1\builder_shared_dat_r[31:0] 0
sync always
update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
end
attribute \src "ls180.v:2001.5-2001.30"
- process $proc$ls180.v:2001$3976
+ process $proc$ls180.v:2001$3983
assign { } { }
assign $1\builder_shared_ack[0:0] 1'0
sync always
update \builder_shared_ack $1\builder_shared_ack[0:0]
end
attribute \src "ls180.v:2007.11-2007.31"
- process $proc$ls180.v:2007$3977
+ process $proc$ls180.v:2007$3984
assign { } { }
assign $1\builder_grant[2:0] 3'000
sync always
update \builder_grant $1\builder_grant[2:0]
end
attribute \src "ls180.v:2008.12-2008.37"
- process $proc$ls180.v:2008$3978
+ process $proc$ls180.v:2008$3985
assign { } { }
assign $1\builder_slave_sel[12:0] 13'0000000000000
sync always
update \builder_slave_sel $1\builder_slave_sel[12:0]
end
attribute \src "ls180.v:2009.12-2009.39"
- process $proc$ls180.v:2009$3979
+ process $proc$ls180.v:2009$3986
assign { } { }
assign $1\builder_slave_sel_r[12:0] 13'0000000000000
sync always
update \builder_slave_sel_r $1\builder_slave_sel_r[12:0]
end
attribute \src "ls180.v:2010.5-2010.25"
- process $proc$ls180.v:2010$3980
+ process $proc$ls180.v:2010$3987
assign { } { }
assign $1\builder_error[0:0] 1'0
sync always
update \builder_error $1\builder_error[0:0]
end
attribute \src "ls180.v:2013.12-2013.39"
- process $proc$ls180.v:2013$3981
+ process $proc$ls180.v:2013$3988
assign { } { }
assign $1\builder_count[19:0] 20'11110100001001000000
sync always
update \builder_count $1\builder_count[19:0]
end
attribute \src "ls180.v:2017.11-2017.51"
- process $proc$ls180.v:2017$3982
+ process $proc$ls180.v:2017$3989
assign { } { }
assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
end
+ attribute \src "ls180.v:202.5-202.74"
+ process $proc$ls180.v:202$3156
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
+ sync init
+ end
attribute \src "ls180.v:2058.11-2058.51"
- process $proc$ls180.v:2058$3983
+ process $proc$ls180.v:2058$3990
assign { } { }
assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2087.11-2087.51"
- process $proc$ls180.v:2087$3984
+ process $proc$ls180.v:2087$3991
assign { } { }
assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:210.5-210.40"
- process $proc$ls180.v:210$3150
+ process $proc$ls180.v:210$3157
assign { } { }
assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
sync always
update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
end
attribute \src "ls180.v:2100.11-2100.51"
- process $proc$ls180.v:2100$3985
+ process $proc$ls180.v:2100$3992
assign { } { }
assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:214.5-214.40"
- process $proc$ls180.v:214$3151
+ process $proc$ls180.v:214$3158
assign { } { }
assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:2141.11-2141.51"
- process $proc$ls180.v:2141$3986
+ process $proc$ls180.v:2141$3993
assign { } { }
assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:217.11-217.37"
- process $proc$ls180.v:217$3152
+ process $proc$ls180.v:217$3159
assign { } { }
assign $1\main_libresocsim_we[7:0] 8'00000000
sync always
update \main_libresocsim_we $1\main_libresocsim_we[7:0]
end
attribute \src "ls180.v:2182.11-2182.51"
- process $proc$ls180.v:2182$3987
+ process $proc$ls180.v:2182$3994
assign { } { }
assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:219.12-219.49"
- process $proc$ls180.v:219$3153
+ process $proc$ls180.v:219$3160
assign { } { }
assign $1\main_libresocsim_load_storage[31:0] 0
sync always
update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
end
attribute \src "ls180.v:220.5-220.36"
- process $proc$ls180.v:220$3154
+ process $proc$ls180.v:220$3161
assign { } { }
assign $1\main_libresocsim_load_re[0:0] 1'0
sync always
update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
end
attribute \src "ls180.v:221.12-221.51"
- process $proc$ls180.v:221$3155
+ process $proc$ls180.v:221$3162
assign { } { }
assign $1\main_libresocsim_reload_storage[31:0] 0
sync always
update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
end
attribute \src "ls180.v:222.5-222.38"
- process $proc$ls180.v:222$3156
+ process $proc$ls180.v:222$3163
assign { } { }
assign $1\main_libresocsim_reload_re[0:0] 1'0
sync always
update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
end
attribute \src "ls180.v:223.5-223.39"
- process $proc$ls180.v:223$3157
+ process $proc$ls180.v:223$3164
assign { } { }
assign $1\main_libresocsim_en_storage[0:0] 1'0
sync always
update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
end
attribute \src "ls180.v:224.5-224.34"
- process $proc$ls180.v:224$3158
+ process $proc$ls180.v:224$3165
assign { } { }
assign $1\main_libresocsim_en_re[0:0] 1'0
sync always
update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
end
attribute \src "ls180.v:2247.11-2247.51"
- process $proc$ls180.v:2247$3988
+ process $proc$ls180.v:2247$3995
assign { } { }
assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:225.5-225.49"
- process $proc$ls180.v:225$3159
+ process $proc$ls180.v:225$3166
assign { } { }
assign $1\main_libresocsim_update_value_storage[0:0] 1'0
sync always
update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
end
attribute \src "ls180.v:226.5-226.44"
- process $proc$ls180.v:226$3160
+ process $proc$ls180.v:226$3167
assign { } { }
assign $1\main_libresocsim_update_value_re[0:0] 1'0
sync always
update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
end
attribute \src "ls180.v:227.12-227.49"
- process $proc$ls180.v:227$3161
+ process $proc$ls180.v:227$3168
assign { } { }
assign $1\main_libresocsim_value_status[31:0] 0
sync always
update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
end
attribute \src "ls180.v:231.5-231.41"
- process $proc$ls180.v:231$3162
+ process $proc$ls180.v:231$3169
assign { } { }
assign $1\main_libresocsim_zero_pending[0:0] 1'0
sync always
update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
end
attribute \src "ls180.v:233.5-233.39"
- process $proc$ls180.v:233$3163
+ process $proc$ls180.v:233$3170
assign { } { }
assign $1\main_libresocsim_zero_clear[0:0] 1'0
sync always
update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
end
attribute \src "ls180.v:234.5-234.45"
- process $proc$ls180.v:234$3164
+ process $proc$ls180.v:234$3171
assign { } { }
assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
sync always
update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
end
attribute \src "ls180.v:2380.11-2380.51"
- process $proc$ls180.v:2380$3989
+ process $proc$ls180.v:2380$3996
assign { } { }
assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:243.5-243.49"
- process $proc$ls180.v:243$3165
+ process $proc$ls180.v:243$3172
assign { } { }
assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
sync always
update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
end
attribute \src "ls180.v:244.5-244.44"
- process $proc$ls180.v:244$3166
+ process $proc$ls180.v:244$3173
assign { } { }
assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
sync always
update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
end
attribute \src "ls180.v:245.12-245.42"
- process $proc$ls180.v:245$3167
+ process $proc$ls180.v:245$3174
assign { } { }
assign $1\main_libresocsim_value[31:0] 0
sync always
update \main_libresocsim_value $1\main_libresocsim_value[31:0]
end
attribute \src "ls180.v:2461.11-2461.51"
- process $proc$ls180.v:2461$3990
+ process $proc$ls180.v:2461$3997
assign { } { }
assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2478.11-2478.51"
- process $proc$ls180.v:2478$3991
+ process $proc$ls180.v:2478$3998
assign { } { }
assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2519.11-2519.52"
- process $proc$ls180.v:2519$3992
+ process $proc$ls180.v:2519$3999
assign { } { }
assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:252.5-252.39"
- process $proc$ls180.v:252$3168
+ process $proc$ls180.v:252$3175
assign { } { }
assign $1\main_interface0_ram_bus_ack[0:0] 1'0
sync always
update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0]
end
attribute \src "ls180.v:2552.11-2552.52"
- process $proc$ls180.v:2552$3993
+ process $proc$ls180.v:2552$4000
assign { } { }
assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:256.5-256.39"
- process $proc$ls180.v:256$3169
+ process $proc$ls180.v:256$3176
assign { } { }
assign $0\main_interface0_ram_bus_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:259.11-259.31"
- process $proc$ls180.v:259$3170
+ process $proc$ls180.v:259$3177
assign { } { }
assign $1\main_sram0_we[7:0] 8'00000000
sync always
update \main_sram0_we $1\main_sram0_we[7:0]
end
attribute \src "ls180.v:2593.11-2593.52"
- process $proc$ls180.v:2593$3994
+ process $proc$ls180.v:2593$4001
assign { } { }
assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2658.11-2658.52"
- process $proc$ls180.v:2658$3995
+ process $proc$ls180.v:2658$4002
assign { } { }
assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:267.5-267.39"
- process $proc$ls180.v:267$3171
+ process $proc$ls180.v:267$3178
assign { } { }
assign $1\main_interface1_ram_bus_ack[0:0] 1'0
sync always
update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0]
end
attribute \src "ls180.v:2683.11-2683.52"
- process $proc$ls180.v:2683$3996
+ process $proc$ls180.v:2683$4003
assign { } { }
assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2705.11-2705.31"
- process $proc$ls180.v:2705$3997
+ process $proc$ls180.v:2705$4004
assign { } { }
assign $1\builder_state[1:0] 2'00
sync always
update \builder_state $1\builder_state[1:0]
end
attribute \src "ls180.v:2706.11-2706.36"
- process $proc$ls180.v:2706$3998
+ process $proc$ls180.v:2706$4005
assign { } { }
assign $1\builder_next_state[1:0] 2'00
sync always
update \builder_next_state $1\builder_next_state[1:0]
end
attribute \src "ls180.v:2707.11-2707.55"
- process $proc$ls180.v:2707$3999
+ process $proc$ls180.v:2707$4006
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
sync always
update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
end
attribute \src "ls180.v:2708.5-2708.52"
- process $proc$ls180.v:2708$4000
+ process $proc$ls180.v:2708$4007
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
sync always
update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
end
attribute \src "ls180.v:2709.12-2709.55"
- process $proc$ls180.v:2709$4001
+ process $proc$ls180.v:2709$4008
assign { } { }
assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
sync always
update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
end
attribute \src "ls180.v:271.5-271.39"
- process $proc$ls180.v:271$3172
+ process $proc$ls180.v:271$3179
assign { } { }
assign $0\main_interface1_ram_bus_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:2710.5-2710.50"
- process $proc$ls180.v:2710$4002
+ process $proc$ls180.v:2710$4009
assign { } { }
assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
sync always
update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
end
attribute \src "ls180.v:2711.5-2711.46"
- process $proc$ls180.v:2711$4003
+ process $proc$ls180.v:2711$4010
assign { } { }
assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
end
attribute \src "ls180.v:2712.5-2712.49"
- process $proc$ls180.v:2712$4004
+ process $proc$ls180.v:2712$4011
assign { } { }
assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
end
attribute \src "ls180.v:2713.5-2713.41"
- process $proc$ls180.v:2713$4005
+ process $proc$ls180.v:2713$4012
assign { } { }
assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
end
attribute \src "ls180.v:2714.12-2714.49"
- process $proc$ls180.v:2714$4006
+ process $proc$ls180.v:2714$4013
assign { } { }
assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
sync always
update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:2715.11-2715.47"
- process $proc$ls180.v:2715$4007
+ process $proc$ls180.v:2715$4014
assign { } { }
assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
end
attribute \src "ls180.v:2716.5-2716.41"
- process $proc$ls180.v:2716$4008
+ process $proc$ls180.v:2716$4015
assign { } { }
assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
end
attribute \src "ls180.v:2717.5-2717.41"
- process $proc$ls180.v:2717$4009
+ process $proc$ls180.v:2717$4016
assign { } { }
assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
end
attribute \src "ls180.v:2718.5-2718.41"
- process $proc$ls180.v:2718$4010
+ process $proc$ls180.v:2718$4017
assign { } { }
assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
end
attribute \src "ls180.v:2719.5-2719.39"
- process $proc$ls180.v:2719$4011
+ process $proc$ls180.v:2719$4018
assign { } { }
assign $1\builder_comb_t_array_muxed0[0:0] 1'0
sync always
update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
end
attribute \src "ls180.v:2720.5-2720.39"
- process $proc$ls180.v:2720$4012
+ process $proc$ls180.v:2720$4019
assign { } { }
assign $1\builder_comb_t_array_muxed1[0:0] 1'0
sync always
update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
end
attribute \src "ls180.v:2721.5-2721.39"
- process $proc$ls180.v:2721$4013
+ process $proc$ls180.v:2721$4020
assign { } { }
assign $1\builder_comb_t_array_muxed2[0:0] 1'0
sync always
update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
end
attribute \src "ls180.v:2722.5-2722.41"
- process $proc$ls180.v:2722$4014
+ process $proc$ls180.v:2722$4021
assign { } { }
assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:2723.12-2723.49"
- process $proc$ls180.v:2723$4015
+ process $proc$ls180.v:2723$4022
assign { } { }
assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
sync always
update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
end
attribute \src "ls180.v:2724.11-2724.47"
- process $proc$ls180.v:2724$4016
+ process $proc$ls180.v:2724$4023
assign { } { }
assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
end
attribute \src "ls180.v:2725.5-2725.41"
- process $proc$ls180.v:2725$4017
+ process $proc$ls180.v:2725$4024
assign { } { }
assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
end
attribute \src "ls180.v:2726.5-2726.42"
- process $proc$ls180.v:2726$4018
+ process $proc$ls180.v:2726$4025
assign { } { }
assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
end
attribute \src "ls180.v:2727.5-2727.42"
- process $proc$ls180.v:2727$4019
+ process $proc$ls180.v:2727$4026
assign { } { }
assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
end
attribute \src "ls180.v:2728.5-2728.39"
- process $proc$ls180.v:2728$4020
+ process $proc$ls180.v:2728$4027
assign { } { }
assign $1\builder_comb_t_array_muxed3[0:0] 1'0
sync always
update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
end
attribute \src "ls180.v:2729.5-2729.39"
- process $proc$ls180.v:2729$4021
+ process $proc$ls180.v:2729$4028
assign { } { }
assign $1\builder_comb_t_array_muxed4[0:0] 1'0
sync always
update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
end
attribute \src "ls180.v:2730.5-2730.39"
- process $proc$ls180.v:2730$4022
+ process $proc$ls180.v:2730$4029
assign { } { }
assign $1\builder_comb_t_array_muxed5[0:0] 1'0
sync always
update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
end
attribute \src "ls180.v:2731.12-2731.50"
- process $proc$ls180.v:2731$4023
+ process $proc$ls180.v:2731$4030
assign { } { }
assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
end
attribute \src "ls180.v:2732.5-2732.42"
- process $proc$ls180.v:2732$4024
+ process $proc$ls180.v:2732$4031
assign { } { }
assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
end
attribute \src "ls180.v:2733.5-2733.42"
- process $proc$ls180.v:2733$4025
+ process $proc$ls180.v:2733$4032
assign { } { }
assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
end
attribute \src "ls180.v:2734.12-2734.50"
- process $proc$ls180.v:2734$4026
+ process $proc$ls180.v:2734$4033
assign { } { }
assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
end
attribute \src "ls180.v:2735.5-2735.42"
- process $proc$ls180.v:2735$4027
+ process $proc$ls180.v:2735$4034
assign { } { }
assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
end
attribute \src "ls180.v:2736.5-2736.42"
- process $proc$ls180.v:2736$4028
+ process $proc$ls180.v:2736$4035
assign { } { }
assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
end
attribute \src "ls180.v:2737.12-2737.50"
- process $proc$ls180.v:2737$4029
+ process $proc$ls180.v:2737$4036
assign { } { }
assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
end
attribute \src "ls180.v:2738.5-2738.42"
- process $proc$ls180.v:2738$4030
+ process $proc$ls180.v:2738$4037
assign { } { }
assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
end
attribute \src "ls180.v:2739.5-2739.42"
- process $proc$ls180.v:2739$4031
+ process $proc$ls180.v:2739$4038
assign { } { }
assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
end
attribute \src "ls180.v:274.11-274.31"
- process $proc$ls180.v:274$3173
+ process $proc$ls180.v:274$3180
assign { } { }
assign $1\main_sram1_we[7:0] 8'00000000
sync always
update \main_sram1_we $1\main_sram1_we[7:0]
end
attribute \src "ls180.v:2740.12-2740.50"
- process $proc$ls180.v:2740$4032
+ process $proc$ls180.v:2740$4039
assign { } { }
assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
end
attribute \src "ls180.v:2741.5-2741.42"
- process $proc$ls180.v:2741$4033
+ process $proc$ls180.v:2741$4040
assign { } { }
assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
end
attribute \src "ls180.v:2742.5-2742.42"
- process $proc$ls180.v:2742$4034
+ process $proc$ls180.v:2742$4041
assign { } { }
assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
end
attribute \src "ls180.v:2743.12-2743.50"
- process $proc$ls180.v:2743$4035
+ process $proc$ls180.v:2743$4042
assign { } { }
assign $1\builder_comb_rhs_array_muxed24[31:0] 0
sync always
update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
end
attribute \src "ls180.v:2744.12-2744.50"
- process $proc$ls180.v:2744$4036
+ process $proc$ls180.v:2744$4043
assign { } { }
assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0]
end
attribute \src "ls180.v:2745.11-2745.48"
- process $proc$ls180.v:2745$4037
+ process $proc$ls180.v:2745$4044
assign { } { }
assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000
sync always
update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0]
end
attribute \src "ls180.v:2746.5-2746.42"
- process $proc$ls180.v:2746$4038
+ process $proc$ls180.v:2746$4045
assign { } { }
assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
end
attribute \src "ls180.v:2747.5-2747.42"
- process $proc$ls180.v:2747$4039
+ process $proc$ls180.v:2747$4046
assign { } { }
assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
end
attribute \src "ls180.v:2748.5-2748.42"
- process $proc$ls180.v:2748$4040
+ process $proc$ls180.v:2748$4047
assign { } { }
assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
end
attribute \src "ls180.v:2749.11-2749.48"
- process $proc$ls180.v:2749$4041
+ process $proc$ls180.v:2749$4048
assign { } { }
assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
end
attribute \src "ls180.v:2750.11-2750.48"
- process $proc$ls180.v:2750$4042
+ process $proc$ls180.v:2750$4049
assign { } { }
assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
end
attribute \src "ls180.v:2751.11-2751.47"
- process $proc$ls180.v:2751$4043
+ process $proc$ls180.v:2751$4050
assign { } { }
assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
sync always
update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
end
attribute \src "ls180.v:2752.12-2752.49"
- process $proc$ls180.v:2752$4044
+ process $proc$ls180.v:2752$4051
assign { } { }
assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
sync always
update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:2753.5-2753.41"
- process $proc$ls180.v:2753$4045
+ process $proc$ls180.v:2753$4052
assign { } { }
assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
end
attribute \src "ls180.v:2754.5-2754.41"
- process $proc$ls180.v:2754$4046
+ process $proc$ls180.v:2754$4053
assign { } { }
assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
end
attribute \src "ls180.v:2755.5-2755.41"
- process $proc$ls180.v:2755$4047
+ process $proc$ls180.v:2755$4054
assign { } { }
assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
end
attribute \src "ls180.v:2756.5-2756.41"
- process $proc$ls180.v:2756$4048
+ process $proc$ls180.v:2756$4055
assign { } { }
assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
end
attribute \src "ls180.v:2757.5-2757.41"
- process $proc$ls180.v:2757$4049
+ process $proc$ls180.v:2757$4056
assign { } { }
assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:2758.5-2758.39"
- process $proc$ls180.v:2758$4050
+ process $proc$ls180.v:2758$4057
assign { } { }
assign $1\builder_sync_f_array_muxed0[0:0] 1'0
sync always
update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
end
attribute \src "ls180.v:2759.5-2759.39"
- process $proc$ls180.v:2759$4051
+ process $proc$ls180.v:2759$4058
assign { } { }
assign $1\builder_sync_f_array_muxed1[0:0] 1'0
sync always
update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
end
attribute \src "ls180.v:2816.32-2816.66"
- process $proc$ls180.v:2816$4052
+ process $proc$ls180.v:2816$4059
assign { } { }
assign $1\builder_multiregimpl0_regs0[0:0] 1'0
sync always
update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
end
attribute \src "ls180.v:2817.32-2817.66"
- process $proc$ls180.v:2817$4053
+ process $proc$ls180.v:2817$4060
assign { } { }
assign $1\builder_multiregimpl0_regs1[0:0] 1'0
sync always
update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
end
attribute \src "ls180.v:2818.32-2818.66"
- process $proc$ls180.v:2818$4054
+ process $proc$ls180.v:2818$4061
assign { } { }
assign $1\builder_multiregimpl1_regs0[0:0] 1'0
sync always
update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
end
attribute \src "ls180.v:2819.32-2819.66"
- process $proc$ls180.v:2819$4055
+ process $proc$ls180.v:2819$4062
assign { } { }
assign $1\builder_multiregimpl1_regs1[0:0] 1'0
sync always
update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
end
attribute \src "ls180.v:282.5-282.39"
- process $proc$ls180.v:282$3174
+ process $proc$ls180.v:282$3181
assign { } { }
assign $1\main_interface2_ram_bus_ack[0:0] 1'0
sync always
update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0]
end
attribute \src "ls180.v:2820.32-2820.66"
- process $proc$ls180.v:2820$4056
+ process $proc$ls180.v:2820$4063
assign { } { }
assign $1\builder_multiregimpl2_regs0[0:0] 1'0
sync always
update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
end
attribute \src "ls180.v:2821.32-2821.66"
- process $proc$ls180.v:2821$4057
+ process $proc$ls180.v:2821$4064
assign { } { }
assign $1\builder_multiregimpl2_regs1[0:0] 1'0
sync always
update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
end
attribute \src "ls180.v:2822.32-2822.66"
- process $proc$ls180.v:2822$4058
+ process $proc$ls180.v:2822$4065
assign { } { }
assign $1\builder_multiregimpl3_regs0[0:0] 1'0
sync always
update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
end
attribute \src "ls180.v:2823.32-2823.66"
- process $proc$ls180.v:2823$4059
+ process $proc$ls180.v:2823$4066
assign { } { }
assign $1\builder_multiregimpl3_regs1[0:0] 1'0
sync always
update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
end
attribute \src "ls180.v:2824.32-2824.66"
- process $proc$ls180.v:2824$4060
+ process $proc$ls180.v:2824$4067
assign { } { }
assign $1\builder_multiregimpl4_regs0[0:0] 1'0
sync always
update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
end
attribute \src "ls180.v:2825.32-2825.66"
- process $proc$ls180.v:2825$4061
+ process $proc$ls180.v:2825$4068
assign { } { }
assign $1\builder_multiregimpl4_regs1[0:0] 1'0
sync always
update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
end
attribute \src "ls180.v:2826.32-2826.66"
- process $proc$ls180.v:2826$4062
+ process $proc$ls180.v:2826$4069
assign { } { }
assign $1\builder_multiregimpl5_regs0[0:0] 1'0
sync always
update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
end
attribute \src "ls180.v:2827.32-2827.66"
- process $proc$ls180.v:2827$4063
+ process $proc$ls180.v:2827$4070
assign { } { }
assign $1\builder_multiregimpl5_regs1[0:0] 1'0
sync always
update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
end
attribute \src "ls180.v:2828.32-2828.66"
- process $proc$ls180.v:2828$4064
+ process $proc$ls180.v:2828$4071
assign { } { }
assign $1\builder_multiregimpl6_regs0[0:0] 1'0
sync always
update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
end
attribute \src "ls180.v:2829.32-2829.66"
- process $proc$ls180.v:2829$4065
+ process $proc$ls180.v:2829$4072
assign { } { }
assign $1\builder_multiregimpl6_regs1[0:0] 1'0
sync always
update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
end
attribute \src "ls180.v:2830.32-2830.66"
- process $proc$ls180.v:2830$4066
+ process $proc$ls180.v:2830$4073
assign { } { }
assign $1\builder_multiregimpl7_regs0[0:0] 1'0
sync always
update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
end
attribute \src "ls180.v:2831.32-2831.66"
- process $proc$ls180.v:2831$4067
+ process $proc$ls180.v:2831$4074
assign { } { }
assign $1\builder_multiregimpl7_regs1[0:0] 1'0
sync always
update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
end
attribute \src "ls180.v:2832.32-2832.66"
- process $proc$ls180.v:2832$4068
+ process $proc$ls180.v:2832$4075
assign { } { }
assign $1\builder_multiregimpl8_regs0[0:0] 1'0
sync always
update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
end
attribute \src "ls180.v:2833.32-2833.66"
- process $proc$ls180.v:2833$4069
+ process $proc$ls180.v:2833$4076
assign { } { }
assign $1\builder_multiregimpl8_regs1[0:0] 1'0
sync always
update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
end
attribute \src "ls180.v:2834.32-2834.66"
- process $proc$ls180.v:2834$4070
+ process $proc$ls180.v:2834$4077
assign { } { }
assign $1\builder_multiregimpl9_regs0[0:0] 1'0
sync always
update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
end
attribute \src "ls180.v:2835.32-2835.66"
- process $proc$ls180.v:2835$4071
+ process $proc$ls180.v:2835$4078
assign { } { }
assign $1\builder_multiregimpl9_regs1[0:0] 1'0
sync always
update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
end
attribute \src "ls180.v:2836.32-2836.67"
- process $proc$ls180.v:2836$4072
+ process $proc$ls180.v:2836$4079
assign { } { }
assign $1\builder_multiregimpl10_regs0[0:0] 1'0
sync always
update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
end
attribute \src "ls180.v:2837.32-2837.67"
- process $proc$ls180.v:2837$4073
+ process $proc$ls180.v:2837$4080
assign { } { }
assign $1\builder_multiregimpl10_regs1[0:0] 1'0
sync always
update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
end
attribute \src "ls180.v:2838.32-2838.67"
- process $proc$ls180.v:2838$4074
+ process $proc$ls180.v:2838$4081
assign { } { }
assign $1\builder_multiregimpl11_regs0[0:0] 1'0
sync always
update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
end
attribute \src "ls180.v:2839.32-2839.67"
- process $proc$ls180.v:2839$4075
+ process $proc$ls180.v:2839$4082
assign { } { }
assign $1\builder_multiregimpl11_regs1[0:0] 1'0
sync always
update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
end
attribute \src "ls180.v:2840.32-2840.67"
- process $proc$ls180.v:2840$4076
+ process $proc$ls180.v:2840$4083
assign { } { }
assign $1\builder_multiregimpl12_regs0[0:0] 1'0
sync always
update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
end
attribute \src "ls180.v:2841.32-2841.67"
- process $proc$ls180.v:2841$4077
+ process $proc$ls180.v:2841$4084
assign { } { }
assign $1\builder_multiregimpl12_regs1[0:0] 1'0
sync always
update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
end
attribute \src "ls180.v:2842.32-2842.67"
- process $proc$ls180.v:2842$4078
+ process $proc$ls180.v:2842$4085
assign { } { }
assign $1\builder_multiregimpl13_regs0[0:0] 1'0
sync always
update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
end
attribute \src "ls180.v:2843.32-2843.67"
- process $proc$ls180.v:2843$4079
+ process $proc$ls180.v:2843$4086
assign { } { }
assign $1\builder_multiregimpl13_regs1[0:0] 1'0
sync always
update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
end
attribute \src "ls180.v:2844.32-2844.67"
- process $proc$ls180.v:2844$4080
+ process $proc$ls180.v:2844$4087
assign { } { }
assign $1\builder_multiregimpl14_regs0[0:0] 1'0
sync always
update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
end
attribute \src "ls180.v:2845.32-2845.67"
- process $proc$ls180.v:2845$4081
+ process $proc$ls180.v:2845$4088
assign { } { }
assign $1\builder_multiregimpl14_regs1[0:0] 1'0
sync always
update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
end
attribute \src "ls180.v:2846.32-2846.67"
- process $proc$ls180.v:2846$4082
+ process $proc$ls180.v:2846$4089
assign { } { }
assign $1\builder_multiregimpl15_regs0[0:0] 1'0
sync always
update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
end
attribute \src "ls180.v:2847.32-2847.67"
- process $proc$ls180.v:2847$4083
+ process $proc$ls180.v:2847$4090
assign { } { }
assign $1\builder_multiregimpl15_regs1[0:0] 1'0
sync always
update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
end
attribute \src "ls180.v:2848.32-2848.67"
- process $proc$ls180.v:2848$4084
+ process $proc$ls180.v:2848$4091
assign { } { }
assign $1\builder_multiregimpl16_regs0[0:0] 1'0
sync always
update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
end
attribute \src "ls180.v:2849.32-2849.67"
- process $proc$ls180.v:2849$4085
+ process $proc$ls180.v:2849$4092
assign { } { }
assign $1\builder_multiregimpl16_regs1[0:0] 1'0
sync always
update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
end
attribute \src "ls180.v:286.5-286.39"
- process $proc$ls180.v:286$3175
+ process $proc$ls180.v:286$3182
assign { } { }
assign $0\main_interface2_ram_bus_err[0:0] 1'0
sync always
update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0]
end
attribute \src "ls180.v:289.11-289.31"
- process $proc$ls180.v:289$3176
+ process $proc$ls180.v:289$3183
assign { } { }
assign $1\main_sram2_we[7:0] 8'00000000
sync always
update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0]
end
attribute \src "ls180.v:297.5-297.39"
- process $proc$ls180.v:297$3177
+ process $proc$ls180.v:297$3184
assign { } { }
assign $1\main_interface3_ram_bus_ack[0:0] 1'0
sync always
update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0]
end
attribute \src "ls180.v:301.5-301.39"
- process $proc$ls180.v:301$3178
+ process $proc$ls180.v:301$3185
assign { } { }
assign $0\main_interface3_ram_bus_err[0:0] 1'0
sync always
update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0]
end
attribute \src "ls180.v:304.11-304.31"
- process $proc$ls180.v:304$3179
+ process $proc$ls180.v:304$3186
assign { } { }
assign $1\main_sram3_we[7:0] 8'00000000
sync always
update \main_sram1_we $0\main_sram1_we[7:0]
end
attribute \src "ls180.v:312.5-312.51"
- process $proc$ls180.v:312$3180
+ process $proc$ls180.v:312$3187
assign { } { }
assign $1\main_interface0_converted_interface_ack[0:0] 1'0
sync always
update \main_sram3_we $0\main_sram3_we[7:0]
end
attribute \src "ls180.v:316.5-316.51"
- process $proc$ls180.v:316$3181
+ process $proc$ls180.v:316$3188
assign { } { }
assign $0\main_interface0_converted_interface_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:317.5-317.32"
- process $proc$ls180.v:317$3182
+ process $proc$ls180.v:317$3189
assign { } { }
assign $1\main_converter0_skip[0:0] 1'0
sync always
update \main_converter0_skip $1\main_converter0_skip[0:0]
end
attribute \src "ls180.v:318.5-318.35"
- process $proc$ls180.v:318$3183
+ process $proc$ls180.v:318$3190
assign { } { }
assign $1\main_converter0_counter[0:0] 1'0
sync always
update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
end
attribute \src "ls180.v:320.12-320.41"
- process $proc$ls180.v:320$3184
+ process $proc$ls180.v:320$3191
assign { } { }
assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
end
attribute \src "ls180.v:327.5-327.51"
- process $proc$ls180.v:327$3185
+ process $proc$ls180.v:327$3192
assign { } { }
assign $1\main_interface1_converted_interface_ack[0:0] 1'0
sync always
update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
end
attribute \src "ls180.v:331.5-331.51"
- process $proc$ls180.v:331$3186
+ process $proc$ls180.v:331$3193
assign { } { }
assign $0\main_interface1_converted_interface_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:332.5-332.32"
- process $proc$ls180.v:332$3187
+ process $proc$ls180.v:332$3194
assign { } { }
assign $1\main_converter1_skip[0:0] 1'0
sync always
update \main_converter1_skip $1\main_converter1_skip[0:0]
end
attribute \src "ls180.v:333.5-333.35"
- process $proc$ls180.v:333$3188
+ process $proc$ls180.v:333$3195
assign { } { }
assign $1\main_converter1_counter[0:0] 1'0
sync always
update \main_converter1_counter $1\main_converter1_counter[0:0]
end
attribute \src "ls180.v:335.12-335.41"
- process $proc$ls180.v:335$3189
+ process $proc$ls180.v:335$3196
assign { } { }
assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:339.5-339.24"
- process $proc$ls180.v:339$3190
+ process $proc$ls180.v:339$3197
assign { } { }
assign $1\main_int_rst[0:0] 1'1
sync always
update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
end
attribute \src "ls180.v:354.12-354.38"
- process $proc$ls180.v:354$3191
+ process $proc$ls180.v:354$3198
assign { } { }
assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:355.5-355.36"
- process $proc$ls180.v:355$3192
+ process $proc$ls180.v:355$3199
assign { } { }
assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
sync always
update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0]
end
attribute \src "ls180.v:356.11-356.32"
- process $proc$ls180.v:356$3193
+ process $proc$ls180.v:356$3200
assign { } { }
assign $1\main_rddata_en[2:0] 3'000
sync always
update \main_rddata_en $1\main_rddata_en[2:0]
end
attribute \src "ls180.v:359.5-359.36"
- process $proc$ls180.v:359$3194
+ process $proc$ls180.v:359$3201
assign { } { }
assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
end
attribute \src "ls180.v:360.5-360.35"
- process $proc$ls180.v:360$3195
+ process $proc$ls180.v:360$3202
assign { } { }
assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
end
attribute \src "ls180.v:361.5-361.36"
- process $proc$ls180.v:361$3196
+ process $proc$ls180.v:361$3203
assign { } { }
assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
end
attribute \src "ls180.v:362.5-362.35"
- process $proc$ls180.v:362$3197
+ process $proc$ls180.v:362$3204
assign { } { }
assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
end
attribute \src "ls180.v:366.5-366.36"
- process $proc$ls180.v:366$3198
+ process $proc$ls180.v:366$3205
assign { } { }
assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:371.12-371.45"
- process $proc$ls180.v:371$3199
+ process $proc$ls180.v:371$3206
assign { } { }
assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
sync always
update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0]
end
attribute \src "ls180.v:372.5-372.43"
- process $proc$ls180.v:372$3200
+ process $proc$ls180.v:372$3207
assign { } { }
assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:387.12-387.46"
- process $proc$ls180.v:387$3201
+ process $proc$ls180.v:387$3208
assign { } { }
assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
sync always
update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
end
attribute \src "ls180.v:388.5-388.44"
- process $proc$ls180.v:388$3202
+ process $proc$ls180.v:388$3209
assign { } { }
assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
sync always
update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
end
attribute \src "ls180.v:389.12-389.48"
- process $proc$ls180.v:389$3203
+ process $proc$ls180.v:389$3210
assign { } { }
assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
sync always
update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
end
attribute \src "ls180.v:390.11-390.43"
- process $proc$ls180.v:390$3204
+ process $proc$ls180.v:390$3211
assign { } { }
assign $1\main_sdram_master_p0_bank[1:0] 2'00
sync always
update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
end
attribute \src "ls180.v:391.5-391.38"
- process $proc$ls180.v:391$3205
+ process $proc$ls180.v:391$3212
assign { } { }
assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
sync always
update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
end
attribute \src "ls180.v:392.5-392.37"
- process $proc$ls180.v:392$3206
+ process $proc$ls180.v:392$3213
assign { } { }
assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
end
attribute \src "ls180.v:393.5-393.38"
- process $proc$ls180.v:393$3207
+ process $proc$ls180.v:393$3214
assign { } { }
assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
end
attribute \src "ls180.v:394.5-394.37"
- process $proc$ls180.v:394$3208
+ process $proc$ls180.v:394$3215
assign { } { }
assign $1\main_sdram_master_p0_we_n[0:0] 1'1
sync always
update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
end
attribute \src "ls180.v:395.5-395.36"
- process $proc$ls180.v:395$3209
+ process $proc$ls180.v:395$3216
assign { } { }
assign $1\main_sdram_master_p0_cke[0:0] 1'0
sync always
update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
end
attribute \src "ls180.v:396.5-396.36"
- process $proc$ls180.v:396$3210
+ process $proc$ls180.v:396$3217
assign { } { }
assign $1\main_sdram_master_p0_odt[0:0] 1'0
sync always
update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
end
attribute \src "ls180.v:397.5-397.40"
- process $proc$ls180.v:397$3211
+ process $proc$ls180.v:397$3218
assign { } { }
assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
sync always
update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
end
attribute \src "ls180.v:398.5-398.38"
- process $proc$ls180.v:398$3212
+ process $proc$ls180.v:398$3219
assign { } { }
assign $1\main_sdram_master_p0_act_n[0:0] 1'1
sync always
update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
end
attribute \src "ls180.v:399.12-399.47"
- process $proc$ls180.v:399$3213
+ process $proc$ls180.v:399$3220
assign { } { }
assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
sync always
update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:400.5-400.42"
- process $proc$ls180.v:400$3214
+ process $proc$ls180.v:400$3221
assign { } { }
assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
attribute \src "ls180.v:401.11-401.50"
- process $proc$ls180.v:401$3215
+ process $proc$ls180.v:401$3222
assign { } { }
assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
sync always
update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
end
attribute \src "ls180.v:402.5-402.42"
- process $proc$ls180.v:402$3216
+ process $proc$ls180.v:402$3223
assign { } { }
assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
sync always
update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
end
attribute \src "ls180.v:409.11-409.36"
- process $proc$ls180.v:409$3217
+ process $proc$ls180.v:409$3224
assign { } { }
assign $1\main_sdram_storage[3:0] 4'0001
sync always
update \main_sdram_storage $1\main_sdram_storage[3:0]
end
attribute \src "ls180.v:410.5-410.25"
- process $proc$ls180.v:410$3218
+ process $proc$ls180.v:410$3225
assign { } { }
assign $1\main_sdram_re[0:0] 1'0
sync always
update \main_sdram_re $1\main_sdram_re[0:0]
end
attribute \src "ls180.v:411.11-411.44"
- process $proc$ls180.v:411$3219
+ process $proc$ls180.v:411$3226
assign { } { }
assign $1\main_sdram_command_storage[5:0] 6'000000
sync always
update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
end
attribute \src "ls180.v:412.5-412.33"
- process $proc$ls180.v:412$3220
+ process $proc$ls180.v:412$3227
assign { } { }
assign $1\main_sdram_command_re[0:0] 1'0
sync always
update \main_sdram_command_re $1\main_sdram_command_re[0:0]
end
attribute \src "ls180.v:416.5-416.38"
- process $proc$ls180.v:416$3221
+ process $proc$ls180.v:416$3228
assign { } { }
assign $0\main_sdram_command_issue_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:417.12-417.46"
- process $proc$ls180.v:417$3222
+ process $proc$ls180.v:417$3229
assign { } { }
assign $1\main_sdram_address_storage[12:0] 13'0000000000000
sync always
update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
end
attribute \src "ls180.v:418.5-418.33"
- process $proc$ls180.v:418$3223
+ process $proc$ls180.v:418$3230
assign { } { }
assign $1\main_sdram_address_re[0:0] 1'0
sync always
update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
end
attribute \src "ls180.v:419.11-419.45"
- process $proc$ls180.v:419$3224
+ process $proc$ls180.v:419$3231
assign { } { }
assign $1\main_sdram_baddress_storage[1:0] 2'00
sync always
update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
end
attribute \src "ls180.v:420.5-420.34"
- process $proc$ls180.v:420$3225
+ process $proc$ls180.v:420$3232
assign { } { }
assign $1\main_sdram_baddress_re[0:0] 1'0
sync always
update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
end
attribute \src "ls180.v:421.12-421.45"
- process $proc$ls180.v:421$3226
+ process $proc$ls180.v:421$3233
assign { } { }
assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
sync always
update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
end
attribute \src "ls180.v:422.5-422.32"
- process $proc$ls180.v:422$3227
+ process $proc$ls180.v:422$3234
assign { } { }
assign $1\main_sdram_wrdata_re[0:0] 1'0
sync always
update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
end
attribute \src "ls180.v:423.12-423.37"
- process $proc$ls180.v:423$3228
+ process $proc$ls180.v:423$3235
assign { } { }
assign $1\main_sdram_status[15:0] 16'0000000000000000
sync always
update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
attribute \src "ls180.v:453.12-453.46"
- process $proc$ls180.v:453$3229
+ process $proc$ls180.v:453$3236
assign { } { }
assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
sync always
update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
end
attribute \src "ls180.v:454.11-454.47"
- process $proc$ls180.v:454$3230
+ process $proc$ls180.v:454$3237
assign { } { }
assign $1\main_sdram_interface_wdata_we[1:0] 2'00
sync always
update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0]
end
attribute \src "ls180.v:456.12-456.45"
- process $proc$ls180.v:456$3231
+ process $proc$ls180.v:456$3238
assign { } { }
assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
sync always
update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
end
attribute \src "ls180.v:457.11-457.40"
- process $proc$ls180.v:457$3232
+ process $proc$ls180.v:457$3239
assign { } { }
assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
sync always
update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
end
attribute \src "ls180.v:458.5-458.35"
- process $proc$ls180.v:458$3233
+ process $proc$ls180.v:458$3240
assign { } { }
assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
sync always
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
attribute \src "ls180.v:459.5-459.34"
- process $proc$ls180.v:459$3234
+ process $proc$ls180.v:459$3241
assign { } { }
assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
end
attribute \src "ls180.v:460.5-460.35"
- process $proc$ls180.v:460$3235
+ process $proc$ls180.v:460$3242
assign { } { }
assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
end
attribute \src "ls180.v:461.5-461.34"
- process $proc$ls180.v:461$3236
+ process $proc$ls180.v:461$3243
assign { } { }
assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
attribute \src "ls180.v:465.5-465.35"
- process $proc$ls180.v:465$3237
+ process $proc$ls180.v:465$3244
assign { } { }
assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:467.5-467.39"
- process $proc$ls180.v:467$3238
+ process $proc$ls180.v:467$3245
assign { } { }
assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
sync always
update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
end
attribute \src "ls180.v:469.5-469.39"
- process $proc$ls180.v:469$3239
+ process $proc$ls180.v:469$3246
assign { } { }
assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
sync always
update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
end
attribute \src "ls180.v:472.5-472.32"
- process $proc$ls180.v:472$3240
+ process $proc$ls180.v:472$3247
assign { } { }
assign $1\main_sdram_cmd_valid[0:0] 1'0
sync always
update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
end
attribute \src "ls180.v:473.5-473.32"
- process $proc$ls180.v:473$3241
+ process $proc$ls180.v:473$3248
assign { } { }
assign $1\main_sdram_cmd_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
attribute \src "ls180.v:474.5-474.31"
- process $proc$ls180.v:474$3242
+ process $proc$ls180.v:474$3249
assign { } { }
assign $1\main_sdram_cmd_last[0:0] 1'0
sync always
update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
end
attribute \src "ls180.v:475.12-475.44"
- process $proc$ls180.v:475$3243
+ process $proc$ls180.v:475$3250
assign { } { }
assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
end
attribute \src "ls180.v:476.11-476.43"
- process $proc$ls180.v:476$3244
+ process $proc$ls180.v:476$3251
assign { } { }
assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
sync always
update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
end
attribute \src "ls180.v:477.5-477.38"
- process $proc$ls180.v:477$3245
+ process $proc$ls180.v:477$3252
assign { } { }
assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:478.5-478.38"
- process $proc$ls180.v:478$3246
+ process $proc$ls180.v:478$3253
assign { } { }
assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:479.5-479.37"
- process $proc$ls180.v:479$3247
+ process $proc$ls180.v:479$3254
assign { } { }
assign $1\main_sdram_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
end
attribute \src "ls180.v:480.5-480.42"
- process $proc$ls180.v:480$3248
+ process $proc$ls180.v:480$3255
assign { } { }
assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:481.5-481.43"
- process $proc$ls180.v:481$3249
+ process $proc$ls180.v:481$3256
assign { } { }
assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
attribute \src "ls180.v:487.11-487.44"
- process $proc$ls180.v:487$3250
+ process $proc$ls180.v:487$3257
assign { } { }
assign $1\main_sdram_timer_count1[9:0] 10'1100001101
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:489.5-489.38"
- process $proc$ls180.v:489$3251
+ process $proc$ls180.v:489$3258
assign { } { }
assign $1\main_sdram_postponer_req_o[0:0] 1'0
sync always
update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
end
attribute \src "ls180.v:490.5-490.38"
- process $proc$ls180.v:490$3252
+ process $proc$ls180.v:490$3259
assign { } { }
assign $1\main_sdram_postponer_count[0:0] 1'0
sync always
update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
end
attribute \src "ls180.v:491.5-491.39"
- process $proc$ls180.v:491$3253
+ process $proc$ls180.v:491$3260
assign { } { }
assign $1\main_sdram_sequencer_start0[0:0] 1'0
sync always
update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
end
attribute \src "ls180.v:494.5-494.38"
- process $proc$ls180.v:494$3254
+ process $proc$ls180.v:494$3261
assign { } { }
assign $1\main_sdram_sequencer_done1[0:0] 1'0
sync always
update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
end
attribute \src "ls180.v:495.11-495.46"
- process $proc$ls180.v:495$3255
+ process $proc$ls180.v:495$3262
assign { } { }
assign $1\main_sdram_sequencer_counter[3:0] 4'0000
sync always
update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
end
attribute \src "ls180.v:496.5-496.38"
- process $proc$ls180.v:496$3256
+ process $proc$ls180.v:496$3263
assign { } { }
assign $1\main_sdram_sequencer_count[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
attribute \src "ls180.v:502.5-502.51"
- process $proc$ls180.v:502$3257
+ process $proc$ls180.v:502$3264
assign { } { }
assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
end
attribute \src "ls180.v:503.5-503.51"
- process $proc$ls180.v:503$3258
+ process $proc$ls180.v:503$3265
assign { } { }
assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
end
attribute \src "ls180.v:505.5-505.47"
- process $proc$ls180.v:505$3259
+ process $proc$ls180.v:505$3266
assign { } { }
assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
end
attribute \src "ls180.v:506.5-506.45"
- process $proc$ls180.v:506$3260
+ process $proc$ls180.v:506$3267
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
end
attribute \src "ls180.v:507.5-507.45"
- process $proc$ls180.v:507$3261
+ process $proc$ls180.v:507$3268
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
end
attribute \src "ls180.v:508.12-508.57"
- process $proc$ls180.v:508$3262
+ process $proc$ls180.v:508$3269
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
attribute \src "ls180.v:510.5-510.51"
- process $proc$ls180.v:510$3263
+ process $proc$ls180.v:510$3270
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:511.5-511.51"
- process $proc$ls180.v:511$3264
+ process $proc$ls180.v:511$3271
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:512.5-512.50"
- process $proc$ls180.v:512$3265
+ process $proc$ls180.v:512$3272
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
end
attribute \src "ls180.v:513.5-513.54"
- process $proc$ls180.v:513$3266
+ process $proc$ls180.v:513$3273
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:514.5-514.55"
- process $proc$ls180.v:514$3267
+ process $proc$ls180.v:514$3274
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:515.5-515.56"
- process $proc$ls180.v:515$3268
+ process $proc$ls180.v:515$3275
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
end
attribute \src "ls180.v:516.5-516.50"
- process $proc$ls180.v:516$3269
+ process $proc$ls180.v:516$3276
assign { } { }
assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
attribute \src "ls180.v:519.5-519.67"
- process $proc$ls180.v:519$3270
+ process $proc$ls180.v:519$3277
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
attribute \src "ls180.v:520.5-520.66"
- process $proc$ls180.v:520$3271
+ process $proc$ls180.v:520$3278
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0]
end
attribute \src "ls180.v:535.11-535.68"
- process $proc$ls180.v:535$3272
+ process $proc$ls180.v:535$3279
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0]
end
attribute \src "ls180.v:536.5-536.64"
- process $proc$ls180.v:536$3273
+ process $proc$ls180.v:536$3280
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0]
end
attribute \src "ls180.v:537.11-537.70"
- process $proc$ls180.v:537$3274
+ process $proc$ls180.v:537$3281
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0]
end
attribute \src "ls180.v:538.11-538.70"
- process $proc$ls180.v:538$3275
+ process $proc$ls180.v:538$3282
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0]
end
attribute \src "ls180.v:539.11-539.73"
- process $proc$ls180.v:539$3276
+ process $proc$ls180.v:539$3283
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
end
attribute \src "ls180.v:560.5-560.59"
- process $proc$ls180.v:560$3277
+ process $proc$ls180.v:560$3284
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
end
attribute \src "ls180.v:562.5-562.59"
- process $proc$ls180.v:562$3278
+ process $proc$ls180.v:562$3285
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:563.5-563.58"
- process $proc$ls180.v:563$3279
+ process $proc$ls180.v:563$3286
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:564.5-564.64"
- process $proc$ls180.v:564$3280
+ process $proc$ls180.v:564$3287
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
attribute \src "ls180.v:565.12-565.74"
- process $proc$ls180.v:565$3281
+ process $proc$ls180.v:565$3288
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:566.12-566.47"
- process $proc$ls180.v:566$3282
+ process $proc$ls180.v:566$3289
assign { } { }
assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
end
attribute \src "ls180.v:567.5-567.46"
- process $proc$ls180.v:567$3283
+ process $proc$ls180.v:567$3290
assign { } { }
assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
sync always
update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
end
attribute \src "ls180.v:569.5-569.44"
- process $proc$ls180.v:569$3284
+ process $proc$ls180.v:569$3291
assign { } { }
assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
sync always
update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
end
attribute \src "ls180.v:570.5-570.45"
- process $proc$ls180.v:570$3285
+ process $proc$ls180.v:570$3292
assign { } { }
assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:571.5-571.54"
- process $proc$ls180.v:571$3286
+ process $proc$ls180.v:571$3293
assign { } { }
assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
end
attribute \src "ls180.v:573.32-573.76"
- process $proc$ls180.v:573$3287
+ process $proc$ls180.v:573$3294
assign { } { }
assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
end
attribute \src "ls180.v:574.11-574.55"
- process $proc$ls180.v:574$3288
+ process $proc$ls180.v:574$3295
assign { } { }
assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
attribute \src "ls180.v:576.32-576.75"
- process $proc$ls180.v:576$3289
+ process $proc$ls180.v:576$3296
assign { } { }
assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:578.32-578.76"
- process $proc$ls180.v:578$3290
+ process $proc$ls180.v:578$3297
assign { } { }
assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
sync always
update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
end
attribute \src "ls180.v:584.5-584.51"
- process $proc$ls180.v:584$3291
+ process $proc$ls180.v:584$3298
assign { } { }
assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
end
attribute \src "ls180.v:585.5-585.51"
- process $proc$ls180.v:585$3292
+ process $proc$ls180.v:585$3299
assign { } { }
assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
end
attribute \src "ls180.v:587.5-587.47"
- process $proc$ls180.v:587$3293
+ process $proc$ls180.v:587$3300
assign { } { }
assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
end
attribute \src "ls180.v:588.5-588.45"
- process $proc$ls180.v:588$3294
+ process $proc$ls180.v:588$3301
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
end
attribute \src "ls180.v:589.5-589.45"
- process $proc$ls180.v:589$3295
+ process $proc$ls180.v:589$3302
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
end
attribute \src "ls180.v:590.12-590.57"
- process $proc$ls180.v:590$3296
+ process $proc$ls180.v:590$3303
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
sync always
update \builder_slave_sel $0\builder_slave_sel[12:0]
end
attribute \src "ls180.v:592.5-592.51"
- process $proc$ls180.v:592$3297
+ process $proc$ls180.v:592$3304
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:593.5-593.51"
- process $proc$ls180.v:593$3298
+ process $proc$ls180.v:593$3305
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:594.5-594.50"
- process $proc$ls180.v:594$3299
+ process $proc$ls180.v:594$3306
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
end
attribute \src "ls180.v:595.5-595.54"
- process $proc$ls180.v:595$3300
+ process $proc$ls180.v:595$3307
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:596.5-596.55"
- process $proc$ls180.v:596$3301
+ process $proc$ls180.v:596$3308
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:597.5-597.56"
- process $proc$ls180.v:597$3302
+ process $proc$ls180.v:597$3309
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
end
attribute \src "ls180.v:598.5-598.50"
- process $proc$ls180.v:598$3303
+ process $proc$ls180.v:598$3310
assign { } { }
assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
sync always
update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
end
attribute \src "ls180.v:601.5-601.67"
- process $proc$ls180.v:601$3304
+ process $proc$ls180.v:601$3311
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:602.5-602.66"
- process $proc$ls180.v:602$3305
+ process $proc$ls180.v:602$3312
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \builder_error $0\builder_error[0:0]
end
attribute \src "ls180.v:617.11-617.68"
- process $proc$ls180.v:617$3306
+ process $proc$ls180.v:617$3313
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
end
attribute \src "ls180.v:618.5-618.64"
- process $proc$ls180.v:618$3307
+ process $proc$ls180.v:618$3314
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:619.11-619.70"
- process $proc$ls180.v:619$3308
+ process $proc$ls180.v:619$3315
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:620.11-620.70"
- process $proc$ls180.v:620$3309
+ process $proc$ls180.v:620$3316
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:621.11-621.73"
- process $proc$ls180.v:621$3310
+ process $proc$ls180.v:621$3317
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
end
attribute \src "ls180.v:642.5-642.59"
- process $proc$ls180.v:642$3311
+ process $proc$ls180.v:642$3318
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
end
attribute \src "ls180.v:644.5-644.59"
- process $proc$ls180.v:644$3312
+ process $proc$ls180.v:644$3319
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:645.5-645.58"
- process $proc$ls180.v:645$3313
+ process $proc$ls180.v:645$3320
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:646.5-646.64"
- process $proc$ls180.v:646$3314
+ process $proc$ls180.v:646$3321
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
end
attribute \src "ls180.v:647.12-647.74"
- process $proc$ls180.v:647$3315
+ process $proc$ls180.v:647$3322
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:648.12-648.47"
- process $proc$ls180.v:648$3316
+ process $proc$ls180.v:648$3323
assign { } { }
assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
end
attribute \src "ls180.v:649.5-649.46"
- process $proc$ls180.v:649$3317
+ process $proc$ls180.v:649$3324
assign { } { }
assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
sync always
update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
end
attribute \src "ls180.v:651.5-651.44"
- process $proc$ls180.v:651$3318
+ process $proc$ls180.v:651$3325
assign { } { }
assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
sync always
update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
end
attribute \src "ls180.v:652.5-652.45"
- process $proc$ls180.v:652$3319
+ process $proc$ls180.v:652$3326
assign { } { }
assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
end
attribute \src "ls180.v:653.5-653.54"
- process $proc$ls180.v:653$3320
+ process $proc$ls180.v:653$3327
assign { } { }
assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
attribute \src "ls180.v:655.32-655.76"
- process $proc$ls180.v:655$3321
+ process $proc$ls180.v:655$3328
assign { } { }
assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
sync always
update \main_spimaster9_start $0\main_spimaster9_start[0:0]
end
attribute \src "ls180.v:656.11-656.55"
- process $proc$ls180.v:656$3322
+ process $proc$ls180.v:656$3329
assign { } { }
assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
sync always
update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
end
attribute \src "ls180.v:658.32-658.75"
- process $proc$ls180.v:658$3323
+ process $proc$ls180.v:658$3330
assign { } { }
assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
sync always
update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
end
attribute \src "ls180.v:660.32-660.76"
- process $proc$ls180.v:660$3324
+ process $proc$ls180.v:660$3331
assign { } { }
assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:666.5-666.51"
- process $proc$ls180.v:666$3325
+ process $proc$ls180.v:666$3332
assign { } { }
assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
end
attribute \src "ls180.v:667.5-667.51"
- process $proc$ls180.v:667$3326
+ process $proc$ls180.v:667$3333
assign { } { }
assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
end
attribute \src "ls180.v:669.5-669.47"
- process $proc$ls180.v:669$3327
+ process $proc$ls180.v:669$3334
assign { } { }
assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
end
attribute \src "ls180.v:670.5-670.45"
- process $proc$ls180.v:670$3328
+ process $proc$ls180.v:670$3335
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
end
attribute \src "ls180.v:671.5-671.45"
- process $proc$ls180.v:671$3329
+ process $proc$ls180.v:671$3336
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
end
attribute \src "ls180.v:672.12-672.57"
- process $proc$ls180.v:672$3330
+ process $proc$ls180.v:672$3337
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
attribute \src "ls180.v:674.5-674.51"
- process $proc$ls180.v:674$3331
+ process $proc$ls180.v:674$3338
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:675.5-675.51"
- process $proc$ls180.v:675$3332
+ process $proc$ls180.v:675$3339
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:676.5-676.50"
- process $proc$ls180.v:676$3333
+ process $proc$ls180.v:676$3340
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
end
attribute \src "ls180.v:677.5-677.54"
- process $proc$ls180.v:677$3334
+ process $proc$ls180.v:677$3341
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:678.5-678.55"
- process $proc$ls180.v:678$3335
+ process $proc$ls180.v:678$3342
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
end
attribute \src "ls180.v:679.5-679.56"
- process $proc$ls180.v:679$3336
+ process $proc$ls180.v:679$3343
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
end
attribute \src "ls180.v:680.5-680.50"
- process $proc$ls180.v:680$3337
+ process $proc$ls180.v:680$3344
assign { } { }
assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0]
end
attribute \src "ls180.v:683.5-683.67"
- process $proc$ls180.v:683$3338
+ process $proc$ls180.v:683$3345
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0]
end
attribute \src "ls180.v:684.5-684.66"
- process $proc$ls180.v:684$3339
+ process $proc$ls180.v:684$3346
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
end
attribute \src "ls180.v:699.11-699.68"
- process $proc$ls180.v:699$3340
+ process $proc$ls180.v:699$3347
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
end
attribute \src "ls180.v:700.5-700.64"
- process $proc$ls180.v:700$3341
+ process $proc$ls180.v:700$3348
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
end
attribute \src "ls180.v:701.11-701.70"
- process $proc$ls180.v:701$3342
+ process $proc$ls180.v:701$3349
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:702.11-702.70"
- process $proc$ls180.v:702$3343
+ process $proc$ls180.v:702$3350
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0]
end
attribute \src "ls180.v:703.11-703.73"
- process $proc$ls180.v:703$3344
+ process $proc$ls180.v:703$3351
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0]
end
attribute \src "ls180.v:724.5-724.59"
- process $proc$ls180.v:724$3345
+ process $proc$ls180.v:724$3352
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0]
end
attribute \src "ls180.v:726.5-726.59"
- process $proc$ls180.v:726$3346
+ process $proc$ls180.v:726$3353
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:727.5-727.58"
- process $proc$ls180.v:727$3347
+ process $proc$ls180.v:727$3354
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0]
end
attribute \src "ls180.v:728.5-728.64"
- process $proc$ls180.v:728$3348
+ process $proc$ls180.v:728$3355
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
end
attribute \src "ls180.v:729.12-729.74"
- process $proc$ls180.v:729$3349
+ process $proc$ls180.v:729$3356
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0]
end
attribute \src "ls180.v:730.12-730.47"
- process $proc$ls180.v:730$3350
+ process $proc$ls180.v:730$3357
assign { } { }
assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
end
attribute \src "ls180.v:731.5-731.46"
- process $proc$ls180.v:731$3351
+ process $proc$ls180.v:731$3358
assign { } { }
assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0]
end
attribute \src "ls180.v:733.5-733.44"
- process $proc$ls180.v:733$3352
+ process $proc$ls180.v:733$3359
assign { } { }
assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0]
end
attribute \src "ls180.v:734.5-734.45"
- process $proc$ls180.v:734$3353
+ process $proc$ls180.v:734$3360
assign { } { }
assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
end
attribute \src "ls180.v:735.5-735.54"
- process $proc$ls180.v:735$3354
+ process $proc$ls180.v:735$3361
assign { } { }
assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:737.32-737.76"
- process $proc$ls180.v:737$3355
+ process $proc$ls180.v:737$3362
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
end
attribute \src "ls180.v:738.11-738.55"
- process $proc$ls180.v:738$3356
+ process $proc$ls180.v:738$3363
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:740.32-740.75"
- process $proc$ls180.v:740$3357
+ process $proc$ls180.v:740$3364
assign { } { }
assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
sync always
update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0]
end
attribute \src "ls180.v:742.32-742.76"
- process $proc$ls180.v:742$3358
+ process $proc$ls180.v:742$3365
assign { } { }
assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
sync always
update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
end
attribute \src "ls180.v:748.5-748.51"
- process $proc$ls180.v:748$3359
+ process $proc$ls180.v:748$3366
assign { } { }
assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
end
attribute \src "ls180.v:749.5-749.51"
- process $proc$ls180.v:749$3360
+ process $proc$ls180.v:749$3367
assign { } { }
assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:751.5-751.47"
- process $proc$ls180.v:751$3361
+ process $proc$ls180.v:751$3368
assign { } { }
assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
end
attribute \src "ls180.v:752.5-752.45"
- process $proc$ls180.v:752$3362
+ process $proc$ls180.v:752$3369
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
end
attribute \src "ls180.v:753.5-753.45"
- process $proc$ls180.v:753$3363
+ process $proc$ls180.v:753$3370
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
end
attribute \src "ls180.v:754.12-754.57"
- process $proc$ls180.v:754$3364
+ process $proc$ls180.v:754$3371
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
end
attribute \src "ls180.v:756.5-756.51"
- process $proc$ls180.v:756$3365
+ process $proc$ls180.v:756$3372
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:757.5-757.51"
- process $proc$ls180.v:757$3366
+ process $proc$ls180.v:757$3373
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:758.5-758.50"
- process $proc$ls180.v:758$3367
+ process $proc$ls180.v:758$3374
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
sync always
update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0]
end
attribute \src "ls180.v:759.5-759.54"
- process $proc$ls180.v:759$3368
+ process $proc$ls180.v:759$3375
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0]
end
attribute \src "ls180.v:760.5-760.55"
- process $proc$ls180.v:760$3369
+ process $proc$ls180.v:760$3376
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:761.5-761.56"
- process $proc$ls180.v:761$3370
+ process $proc$ls180.v:761$3377
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
end
attribute \src "ls180.v:762.5-762.50"
- process $proc$ls180.v:762$3371
+ process $proc$ls180.v:762$3378
assign { } { }
assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
sync always
assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3]
assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3]
sync posedge \sdrio_clk
+ update \sdcard_clk $0\sdcard_clk[0:0]
+ update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
+ update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
+ update \sdcard_data_o $0\sdcard_data_o[3:0]
+ update \sdcard_data_oe $0\sdcard_data_oe[0:0]
update \sdram_a $0\sdram_a[12:0]
update \sdram_dq_o $0\sdram_dq_o[15:0]
update \sdram_dq_oe $0\sdram_dq_oe[0:0]
update \sdram_ba $0\sdram_ba[1:0]
update \sdram_dm $0\sdram_dm[1:0]
update \sdram_clock $0\sdram_clock[0:0]
- update \sdcard_clk $0\sdcard_clk[0:0]
- update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
- update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
- update \sdcard_data_o $0\sdcard_data_o[3:0]
- update \sdcard_data_oe $0\sdcard_data_oe[0:0]
update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0]
update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
end
attribute \src "ls180.v:765.5-765.67"
- process $proc$ls180.v:765$3372
+ process $proc$ls180.v:765$3379
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:766.5-766.66"
- process $proc$ls180.v:766$3373
+ process $proc$ls180.v:766$3380
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
attribute \src "ls180.v:7702.1-10346.4"
process $proc$ls180.v:7702$2573
assign $0\uart_tx[0:0] \uart_tx
- assign $0\pwm[1:0] \pwm
assign $0\spimaster_clk[0:0] \spimaster_clk
assign $0\spimaster_mosi[0:0] \spimaster_mosi
assign { } { }
assign $0\spisdcard_clk[0:0] \spisdcard_clk
assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
assign { } { }
+ assign $0\pwm[1:0] \pwm
assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
assign { } { }
assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
assign $0\main_libresocsim_scratch_re[0:0] 1'0
assign $0\main_libresocsim_bus_errors[31:0] 0
assign $0\uart_tx[0:0] 1'1
- assign $0\pwm[1:0] 2'00
assign $0\spimaster_clk[0:0] 1'0
assign $0\spimaster_mosi[0:0] 1'0
assign $0\spimaster_cs_n[0:0] 1'0
assign $0\spisdcard_clk[0:0] 1'0
assign $0\spisdcard_mosi[0:0] 1'0
assign $0\spisdcard_cs_n[0:0] 1'0
+ assign $0\pwm[1:0] 2'00
assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
assign $0\main_libresocsim_load_storage[31:0] 0
assign $0\main_libresocsim_load_re[0:0] 1'0
end
sync posedge \sys_clk_1
update \uart_tx $0\uart_tx[0:0]
- update \pwm $0\pwm[1:0]
update \spimaster_clk $0\spimaster_clk[0:0]
update \spimaster_mosi $0\spimaster_mosi[0:0]
update \spimaster_cs_n $0\spimaster_cs_n[0:0]
update \spisdcard_clk $0\spisdcard_clk[0:0]
update \spisdcard_mosi $0\spisdcard_mosi[0:0]
update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
+ update \pwm $0\pwm[1:0]
update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
end
attribute \src "ls180.v:781.11-781.68"
- process $proc$ls180.v:781$3374
+ process $proc$ls180.v:781$3381
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
end
attribute \src "ls180.v:782.5-782.64"
- process $proc$ls180.v:782$3375
+ process $proc$ls180.v:782$3382
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:783.11-783.70"
- process $proc$ls180.v:783$3376
+ process $proc$ls180.v:783$3383
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:784.11-784.70"
- process $proc$ls180.v:784$3377
+ process $proc$ls180.v:784$3384
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:785.11-785.73"
- process $proc$ls180.v:785$3378
+ process $proc$ls180.v:785$3385
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:806.5-806.59"
- process $proc$ls180.v:806$3379
+ process $proc$ls180.v:806$3386
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
end
attribute \src "ls180.v:808.5-808.59"
- process $proc$ls180.v:808$3380
+ process $proc$ls180.v:808$3387
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:809.5-809.58"
- process $proc$ls180.v:809$3381
+ process $proc$ls180.v:809$3388
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:810.5-810.64"
- process $proc$ls180.v:810$3382
+ process $proc$ls180.v:810$3389
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
end
attribute \src "ls180.v:811.12-811.74"
- process $proc$ls180.v:811$3383
+ process $proc$ls180.v:811$3390
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:812.12-812.47"
- process $proc$ls180.v:812$3384
+ process $proc$ls180.v:812$3391
assign { } { }
assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
end
attribute \src "ls180.v:813.5-813.46"
- process $proc$ls180.v:813$3385
+ process $proc$ls180.v:813$3392
assign { } { }
assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
end
attribute \src "ls180.v:815.5-815.44"
- process $proc$ls180.v:815$3386
+ process $proc$ls180.v:815$3393
assign { } { }
assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
end
attribute \src "ls180.v:816.5-816.45"
- process $proc$ls180.v:816$3387
+ process $proc$ls180.v:816$3394
assign { } { }
assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
end
attribute \src "ls180.v:817.5-817.54"
- process $proc$ls180.v:817$3388
+ process $proc$ls180.v:817$3395
assign { } { }
assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
end
attribute \src "ls180.v:819.32-819.76"
- process $proc$ls180.v:819$3389
+ process $proc$ls180.v:819$3396
assign { } { }
assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
end
attribute \src "ls180.v:820.11-820.55"
- process $proc$ls180.v:820$3390
+ process $proc$ls180.v:820$3397
assign { } { }
assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
sync always
update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
end
attribute \src "ls180.v:822.32-822.75"
- process $proc$ls180.v:822$3391
+ process $proc$ls180.v:822$3398
assign { } { }
assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:824.32-824.76"
- process $proc$ls180.v:824$3392
+ process $proc$ls180.v:824$3399
assign { } { }
assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:827.5-827.44"
- process $proc$ls180.v:827$3393
+ process $proc$ls180.v:827$3400
assign { } { }
assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:828.5-828.45"
- process $proc$ls180.v:828$3394
+ process $proc$ls180.v:828$3401
assign { } { }
assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:829.5-829.43"
- process $proc$ls180.v:829$3395
+ process $proc$ls180.v:829$3402
assign { } { }
assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:830.5-830.48"
- process $proc$ls180.v:830$3396
+ process $proc$ls180.v:830$3403
assign { } { }
assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:832.5-832.43"
- process $proc$ls180.v:832$3397
+ process $proc$ls180.v:832$3404
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:835.5-835.49"
- process $proc$ls180.v:835$3398
+ process $proc$ls180.v:835$3405
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:836.5-836.49"
- process $proc$ls180.v:836$3399
+ process $proc$ls180.v:836$3406
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:837.5-837.48"
- process $proc$ls180.v:837$3400
+ process $proc$ls180.v:837$3407
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
attribute \src "ls180.v:841.11-841.46"
- process $proc$ls180.v:841$3401
+ process $proc$ls180.v:841$3408
assign { } { }
assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
sync always
update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
end
attribute \src "ls180.v:843.11-843.45"
- process $proc$ls180.v:843$3402
+ process $proc$ls180.v:843$3409
assign { } { }
assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
sync always
update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
end
attribute \src "ls180.v:845.5-845.44"
- process $proc$ls180.v:845$3403
+ process $proc$ls180.v:845$3410
assign { } { }
assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
sync always
update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
end
attribute \src "ls180.v:846.5-846.45"
- process $proc$ls180.v:846$3404
+ process $proc$ls180.v:846$3411
assign { } { }
assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
sync always
update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
end
attribute \src "ls180.v:848.5-848.48"
- process $proc$ls180.v:848$3405
+ process $proc$ls180.v:848$3412
assign { } { }
assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:850.5-850.43"
- process $proc$ls180.v:850$3406
+ process $proc$ls180.v:850$3413
assign { } { }
assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
end
attribute \src "ls180.v:853.5-853.49"
- process $proc$ls180.v:853$3407
+ process $proc$ls180.v:853$3414
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:854.5-854.49"
- process $proc$ls180.v:854$3408
+ process $proc$ls180.v:854$3415
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:855.5-855.48"
- process $proc$ls180.v:855$3409
+ process $proc$ls180.v:855$3416
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
end
attribute \src "ls180.v:859.11-859.46"
- process $proc$ls180.v:859$3410
+ process $proc$ls180.v:859$3417
assign { } { }
assign $1\main_sdram_choose_req_valids[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:861.11-861.45"
- process $proc$ls180.v:861$3411
+ process $proc$ls180.v:861$3418
assign { } { }
assign $1\main_sdram_choose_req_grant[1:0] 2'00
sync always
update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
end
attribute \src "ls180.v:863.12-863.36"
- process $proc$ls180.v:863$3412
+ process $proc$ls180.v:863$3419
assign { } { }
assign $0\main_sdram_nop_a[12:0] 13'0000000000000
sync always
sync init
end
attribute \src "ls180.v:864.11-864.35"
- process $proc$ls180.v:864$3413
+ process $proc$ls180.v:864$3420
assign { } { }
assign $0\main_sdram_nop_ba[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:865.11-865.40"
- process $proc$ls180.v:865$3414
+ process $proc$ls180.v:865$3421
assign { } { }
assign $1\main_sdram_steerer_sel[1:0] 2'00
sync always
update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
end
attribute \src "ls180.v:866.5-866.31"
- process $proc$ls180.v:866$3415
+ process $proc$ls180.v:866$3422
assign { } { }
assign $0\main_sdram_steerer0[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:867.5-867.31"
- process $proc$ls180.v:867$3416
+ process $proc$ls180.v:867$3423
assign { } { }
assign $0\main_sdram_steerer1[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:869.32-869.63"
- process $proc$ls180.v:869$3417
+ process $proc$ls180.v:869$3424
assign { } { }
assign $0\main_sdram_trrdcon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:871.32-871.63"
- process $proc$ls180.v:871$3418
+ process $proc$ls180.v:871$3425
assign { } { }
assign $0\main_sdram_tfawcon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:873.32-873.63"
- process $proc$ls180.v:873$3419
+ process $proc$ls180.v:873$3426
assign { } { }
assign $1\main_sdram_tccdcon_ready[0:0] 1'0
sync always
update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
end
attribute \src "ls180.v:874.5-874.36"
- process $proc$ls180.v:874$3420
+ process $proc$ls180.v:874$3427
assign { } { }
assign $1\main_sdram_tccdcon_count[0:0] 1'0
sync always
update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
end
attribute \src "ls180.v:876.32-876.63"
- process $proc$ls180.v:876$3421
+ process $proc$ls180.v:876$3428
assign { } { }
assign $1\main_sdram_twtrcon_ready[0:0] 1'0
sync always
update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
end
attribute \src "ls180.v:877.11-877.42"
- process $proc$ls180.v:877$3422
+ process $proc$ls180.v:877$3429
assign { } { }
assign $1\main_sdram_twtrcon_count[2:0] 3'000
sync always
update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0]
end
attribute \src "ls180.v:880.5-880.26"
- process $proc$ls180.v:880$3423
+ process $proc$ls180.v:880$3430
assign { } { }
assign $1\main_sdram_en0[0:0] 1'0
sync always
update \main_sdram_en0 $1\main_sdram_en0[0:0]
end
attribute \src "ls180.v:882.11-882.34"
- process $proc$ls180.v:882$3424
+ process $proc$ls180.v:882$3431
assign { } { }
assign $1\main_sdram_time0[4:0] 5'00000
sync always
update \main_sdram_time0 $1\main_sdram_time0[4:0]
end
attribute \src "ls180.v:883.5-883.26"
- process $proc$ls180.v:883$3425
+ process $proc$ls180.v:883$3432
assign { } { }
assign $1\main_sdram_en1[0:0] 1'0
sync always
update \main_sdram_en1 $1\main_sdram_en1[0:0]
end
attribute \src "ls180.v:885.11-885.34"
- process $proc$ls180.v:885$3426
+ process $proc$ls180.v:885$3433
assign { } { }
assign $1\main_sdram_time1[3:0] 4'0000
sync always
update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0]
end
attribute \src "ls180.v:900.12-900.37"
- process $proc$ls180.v:900$3427
+ process $proc$ls180.v:900$3434
assign { } { }
assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0]
end
attribute \src "ls180.v:901.12-901.39"
- process $proc$ls180.v:901$3428
+ process $proc$ls180.v:901$3435
assign { } { }
assign $1\main_wb_sdram_dat_w[31:0] 0
sync always
update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0]
end
attribute \src "ls180.v:903.11-903.35"
- process $proc$ls180.v:903$3429
+ process $proc$ls180.v:903$3436
assign { } { }
assign $1\main_wb_sdram_sel[3:0] 4'0000
sync always
update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0]
end
attribute \src "ls180.v:904.5-904.29"
- process $proc$ls180.v:904$3430
+ process $proc$ls180.v:904$3437
assign { } { }
assign $1\main_wb_sdram_cyc[0:0] 1'0
sync always
update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0]
end
attribute \src "ls180.v:905.5-905.29"
- process $proc$ls180.v:905$3431
+ process $proc$ls180.v:905$3438
assign { } { }
assign $1\main_wb_sdram_stb[0:0] 1'0
sync always
update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0]
end
attribute \src "ls180.v:906.5-906.29"
- process $proc$ls180.v:906$3432
+ process $proc$ls180.v:906$3439
assign { } { }
assign $1\main_wb_sdram_ack[0:0] 1'0
sync always
update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
end
attribute \src "ls180.v:907.5-907.28"
- process $proc$ls180.v:907$3433
+ process $proc$ls180.v:907$3440
assign { } { }
assign $1\main_wb_sdram_we[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0]
end
attribute \src "ls180.v:914.5-914.54"
- process $proc$ls180.v:914$3434
+ process $proc$ls180.v:914$3441
assign { } { }
assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0
sync always
update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0]
end
attribute \src "ls180.v:918.5-918.54"
- process $proc$ls180.v:918$3435
+ process $proc$ls180.v:918$3442
assign { } { }
assign $0\main_socbushandler_converted_interface_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:919.5-919.35"
- process $proc$ls180.v:919$3436
+ process $proc$ls180.v:919$3443
assign { } { }
assign $1\main_socbushandler_skip[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0]
end
attribute \src "ls180.v:920.5-920.38"
- process $proc$ls180.v:920$3437
+ process $proc$ls180.v:920$3444
assign { } { }
assign $1\main_socbushandler_counter[0:0] 1'0
sync always
update \main_socbushandler_counter $1\main_socbushandler_counter[0:0]
end
attribute \src "ls180.v:922.12-922.44"
- process $proc$ls180.v:922$3438
+ process $proc$ls180.v:922$3445
assign { } { }
assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0]
end
attribute \src "ls180.v:923.12-923.40"
- process $proc$ls180.v:923$3439
+ process $proc$ls180.v:923$3446
assign { } { }
assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
end
attribute \src "ls180.v:924.12-924.42"
- process $proc$ls180.v:924$3440
+ process $proc$ls180.v:924$3447
assign { } { }
assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
sync always
update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
end
attribute \src "ls180.v:926.11-926.38"
- process $proc$ls180.v:926$3441
+ process $proc$ls180.v:926$3448
assign { } { }
assign $1\main_litedram_wb_sel[1:0] 2'00
sync always
update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
end
attribute \src "ls180.v:927.5-927.32"
- process $proc$ls180.v:927$3442
+ process $proc$ls180.v:927$3449
assign { } { }
assign $1\main_litedram_wb_cyc[0:0] 1'0
sync always
update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
end
attribute \src "ls180.v:928.5-928.32"
- process $proc$ls180.v:928$3443
+ process $proc$ls180.v:928$3450
assign { } { }
assign $1\main_litedram_wb_stb[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0]
end
attribute \src "ls180.v:930.5-930.31"
- process $proc$ls180.v:930$3444
+ process $proc$ls180.v:930$3451
assign { } { }
assign $1\main_litedram_wb_we[0:0] 1'0
sync always
update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
end
attribute \src "ls180.v:931.5-931.31"
- process $proc$ls180.v:931$3445
+ process $proc$ls180.v:931$3452
assign { } { }
assign $1\main_converter_skip[0:0] 1'0
sync always
update \main_converter_skip $1\main_converter_skip[0:0]
end
attribute \src "ls180.v:932.5-932.34"
- process $proc$ls180.v:932$3446
+ process $proc$ls180.v:932$3453
assign { } { }
assign $1\main_converter_counter[0:0] 1'0
sync always
update \main_converter_counter $1\main_converter_counter[0:0]
end
attribute \src "ls180.v:934.12-934.40"
- process $proc$ls180.v:934$3447
+ process $proc$ls180.v:934$3454
assign { } { }
assign $1\main_converter_dat_r[31:0] 0
sync always
update \main_converter_dat_r $1\main_converter_dat_r[31:0]
end
attribute \src "ls180.v:935.5-935.29"
- process $proc$ls180.v:935$3448
+ process $proc$ls180.v:935$3455
assign { } { }
assign $1\main_cmd_consumed[0:0] 1'0
sync always
update \main_cmd_consumed $1\main_cmd_consumed[0:0]
end
attribute \src "ls180.v:936.5-936.31"
- process $proc$ls180.v:936$3449
+ process $proc$ls180.v:936$3456
assign { } { }
assign $1\main_wdata_consumed[0:0] 1'0
sync always
update \main_wdata_consumed $1\main_wdata_consumed[0:0]
end
attribute \src "ls180.v:940.12-940.47"
- process $proc$ls180.v:940$3450
+ process $proc$ls180.v:940$3457
assign { } { }
assign $1\main_uart_phy_storage[31:0] 9895604
sync always
update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
end
attribute \src "ls180.v:941.5-941.28"
- process $proc$ls180.v:941$3451
+ process $proc$ls180.v:941$3458
assign { } { }
assign $1\main_uart_phy_re[0:0] 1'0
sync always
update \main_uart_phy_re $1\main_uart_phy_re[0:0]
end
attribute \src "ls180.v:943.5-943.36"
- process $proc$ls180.v:943$3452
+ process $proc$ls180.v:943$3459
assign { } { }
assign $1\main_uart_phy_sink_ready[0:0] 1'0
sync always
update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
end
attribute \src "ls180.v:947.5-947.39"
- process $proc$ls180.v:947$3453
+ process $proc$ls180.v:947$3460
assign { } { }
assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
sync always
update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
end
attribute \src "ls180.v:948.12-948.54"
- process $proc$ls180.v:948$3454
+ process $proc$ls180.v:948$3461
assign { } { }
assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
sync always
update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
end
attribute \src "ls180.v:949.11-949.38"
- process $proc$ls180.v:949$3455
+ process $proc$ls180.v:949$3462
assign { } { }
assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
sync always
update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0]
end
attribute \src "ls180.v:950.11-950.43"
- process $proc$ls180.v:950$3456
+ process $proc$ls180.v:950$3463
assign { } { }
assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
sync always
update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
end
attribute \src "ls180.v:951.5-951.33"
- process $proc$ls180.v:951$3457
+ process $proc$ls180.v:951$3464
assign { } { }
assign $1\main_uart_phy_tx_busy[0:0] 1'0
sync always
update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
end
attribute \src "ls180.v:952.5-952.38"
- process $proc$ls180.v:952$3458
+ process $proc$ls180.v:952$3465
assign { } { }
assign $1\main_uart_phy_source_valid[0:0] 1'0
sync always
update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
end
attribute \src "ls180.v:954.5-954.38"
- process $proc$ls180.v:954$3459
+ process $proc$ls180.v:954$3466
assign { } { }
assign $0\main_uart_phy_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:955.5-955.37"
- process $proc$ls180.v:955$3460
+ process $proc$ls180.v:955$3467
assign { } { }
assign $0\main_uart_phy_source_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:956.11-956.51"
- process $proc$ls180.v:956$3461
+ process $proc$ls180.v:956$3468
assign { } { }
assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
sync always
update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
end
attribute \src "ls180.v:957.5-957.39"
- process $proc$ls180.v:957$3462
+ process $proc$ls180.v:957$3469
assign { } { }
assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
sync always
update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
end
attribute \src "ls180.v:958.12-958.54"
- process $proc$ls180.v:958$3463
+ process $proc$ls180.v:958$3470
assign { } { }
assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
sync always
update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
end
attribute \src "ls180.v:960.5-960.30"
- process $proc$ls180.v:960$3464
+ process $proc$ls180.v:960$3471
assign { } { }
assign $1\main_uart_phy_rx_r[0:0] 1'0
sync always
update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
end
attribute \src "ls180.v:961.11-961.38"
- process $proc$ls180.v:961$3465
+ process $proc$ls180.v:961$3472
assign { } { }
assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
sync always
update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
end
attribute \src "ls180.v:962.11-962.43"
- process $proc$ls180.v:962$3466
+ process $proc$ls180.v:962$3473
assign { } { }
assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
sync always
update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
end
attribute \src "ls180.v:963.5-963.33"
- process $proc$ls180.v:963$3467
+ process $proc$ls180.v:963$3474
assign { } { }
assign $1\main_uart_phy_rx_busy[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0]
end
attribute \src "ls180.v:974.5-974.32"
- process $proc$ls180.v:974$3468
+ process $proc$ls180.v:974$3475
assign { } { }
assign $1\main_uart_tx_pending[0:0] 1'0
sync always
update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
end
attribute \src "ls180.v:976.5-976.30"
- process $proc$ls180.v:976$3469
+ process $proc$ls180.v:976$3476
assign { } { }
assign $1\main_uart_tx_clear[0:0] 1'0
sync always
update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
end
attribute \src "ls180.v:977.5-977.36"
- process $proc$ls180.v:977$3470
+ process $proc$ls180.v:977$3477
assign { } { }
assign $1\main_uart_tx_old_trigger[0:0] 1'0
sync always
update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
end
attribute \src "ls180.v:979.5-979.32"
- process $proc$ls180.v:979$3471
+ process $proc$ls180.v:979$3478
assign { } { }
assign $1\main_uart_rx_pending[0:0] 1'0
sync always
update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0]
end
attribute \src "ls180.v:981.5-981.30"
- process $proc$ls180.v:981$3472
+ process $proc$ls180.v:981$3479
assign { } { }
assign $1\main_uart_rx_clear[0:0] 1'0
sync always
update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
end
attribute \src "ls180.v:982.5-982.36"
- process $proc$ls180.v:982$3473
+ process $proc$ls180.v:982$3480
assign { } { }
assign $1\main_uart_rx_old_trigger[0:0] 1'0
sync always
update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
end
attribute \src "ls180.v:986.11-986.49"
- process $proc$ls180.v:986$3474
+ process $proc$ls180.v:986$3481
assign { } { }
assign $1\main_uart_eventmanager_status_w[1:0] 2'00
sync always
update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
end
attribute \src "ls180.v:990.11-990.50"
- process $proc$ls180.v:990$3475
+ process $proc$ls180.v:990$3482
assign { } { }
assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
sync always
update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
end
attribute \src "ls180.v:991.11-991.48"
- process $proc$ls180.v:991$3476
+ process $proc$ls180.v:991$3483
assign { } { }
assign $1\main_uart_eventmanager_storage[1:0] 2'00
sync always
update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
end
attribute \src "ls180.v:992.5-992.37"
- process $proc$ls180.v:992$3477
+ process $proc$ls180.v:992$3484
assign { } { }
assign $1\main_uart_eventmanager_re[0:0] 1'0
sync always
connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10604$3076_DATA
end
-attribute \src "libresoc.v:144986.1-145044.10"
+attribute \src "libresoc.v:143116.1-143174.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l"
attribute \generator "nMigen"
module \lsd_l
- attribute \src "libresoc.v:144987.7-144987.20"
+ attribute \src "libresoc.v:143117.7-143117.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:145032.3-145040.6"
- wire $0\q_int$next[0:0]$7130
- attribute \src "libresoc.v:145030.3-145031.27"
+ attribute \src "libresoc.v:143162.3-143170.6"
+ wire $0\q_int$next[0:0]$7056
+ attribute \src "libresoc.v:143160.3-143161.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:145032.3-145040.6"
- wire $1\q_int$next[0:0]$7131
- attribute \src "libresoc.v:145009.7-145009.19"
+ attribute \src "libresoc.v:143162.3-143170.6"
+ wire $1\q_int$next[0:0]$7057
+ attribute \src "libresoc.v:143139.7-143139.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:145022.17-145022.96"
- wire $and$libresoc.v:145022$7120_Y
- attribute \src "libresoc.v:145027.17-145027.96"
- wire $and$libresoc.v:145027$7125_Y
- attribute \src "libresoc.v:145024.18-145024.93"
- wire $not$libresoc.v:145024$7122_Y
- attribute \src "libresoc.v:145026.17-145026.92"
- wire $not$libresoc.v:145026$7124_Y
- attribute \src "libresoc.v:145029.17-145029.92"
- wire $not$libresoc.v:145029$7127_Y
- attribute \src "libresoc.v:145023.18-145023.98"
- wire $or$libresoc.v:145023$7121_Y
- attribute \src "libresoc.v:145025.18-145025.99"
- wire $or$libresoc.v:145025$7123_Y
- attribute \src "libresoc.v:145028.17-145028.97"
- wire $or$libresoc.v:145028$7126_Y
+ attribute \src "libresoc.v:143152.17-143152.96"
+ wire $and$libresoc.v:143152$7046_Y
+ attribute \src "libresoc.v:143157.17-143157.96"
+ wire $and$libresoc.v:143157$7051_Y
+ attribute \src "libresoc.v:143154.18-143154.93"
+ wire $not$libresoc.v:143154$7048_Y
+ attribute \src "libresoc.v:143156.17-143156.92"
+ wire $not$libresoc.v:143156$7050_Y
+ attribute \src "libresoc.v:143159.17-143159.92"
+ wire $not$libresoc.v:143159$7053_Y
+ attribute \src "libresoc.v:143153.18-143153.98"
+ wire $or$libresoc.v:143153$7047_Y
+ attribute \src "libresoc.v:143155.18-143155.99"
+ wire $or$libresoc.v:143155$7049_Y
+ attribute \src "libresoc.v:143158.17-143158.97"
+ wire $or$libresoc.v:143158$7052_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:144987.7-144987.15"
+ attribute \src "libresoc.v:143117.7-143117.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_lsd
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:145022$7120
+ cell $and $and$libresoc.v:143152$7046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:145022$7120_Y
+ connect \Y $and$libresoc.v:143152$7046_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:145027$7125
+ cell $and $and$libresoc.v:143157$7051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:145027$7125_Y
+ connect \Y $and$libresoc.v:143157$7051_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:145024$7122
+ cell $not $not$libresoc.v:143154$7048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_lsd
- connect \Y $not$libresoc.v:145024$7122_Y
+ connect \Y $not$libresoc.v:143154$7048_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:145026$7124
+ cell $not $not$libresoc.v:143156$7050
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lsd
- connect \Y $not$libresoc.v:145026$7124_Y
+ connect \Y $not$libresoc.v:143156$7050_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:145029$7127
+ cell $not $not$libresoc.v:143159$7053
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_lsd
- connect \Y $not$libresoc.v:145029$7127_Y
+ connect \Y $not$libresoc.v:143159$7053_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:145023$7121
+ cell $or $or$libresoc.v:143153$7047
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_lsd
- connect \Y $or$libresoc.v:145023$7121_Y
+ connect \Y $or$libresoc.v:143153$7047_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:145025$7123
+ cell $or $or$libresoc.v:143155$7049
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_lsd
connect \B \q_int
- connect \Y $or$libresoc.v:145025$7123_Y
+ connect \Y $or$libresoc.v:143155$7049_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:145028$7126
+ cell $or $or$libresoc.v:143158$7052
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_lsd
- connect \Y $or$libresoc.v:145028$7126_Y
+ connect \Y $or$libresoc.v:143158$7052_Y
end
- attribute \src "libresoc.v:144987.7-144987.20"
- process $proc$libresoc.v:144987$7132
+ attribute \src "libresoc.v:143117.7-143117.20"
+ process $proc$libresoc.v:143117$7058
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:145009.7-145009.19"
- process $proc$libresoc.v:145009$7133
+ attribute \src "libresoc.v:143139.7-143139.19"
+ process $proc$libresoc.v:143139$7059
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:145030.3-145031.27"
- process $proc$libresoc.v:145030$7128
+ attribute \src "libresoc.v:143160.3-143161.27"
+ process $proc$libresoc.v:143160$7054
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:145032.3-145040.6"
- process $proc$libresoc.v:145032$7129
+ attribute \src "libresoc.v:143162.3-143170.6"
+ process $proc$libresoc.v:143162$7055
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$7130 $1\q_int$next[0:0]$7131
- attribute \src "libresoc.v:145033.5-145033.29"
+ assign $0\q_int$next[0:0]$7056 $1\q_int$next[0:0]$7057
+ attribute \src "libresoc.v:143163.5-143163.29"
switch \initial
- attribute \src "libresoc.v:145033.9-145033.17"
+ attribute \src "libresoc.v:143163.9-143163.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$7131 1'0
+ assign $1\q_int$next[0:0]$7057 1'0
case
- assign $1\q_int$next[0:0]$7131 \$5
+ assign $1\q_int$next[0:0]$7057 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$7130
+ update \q_int$next $0\q_int$next[0:0]$7056
end
- connect \$9 $and$libresoc.v:145022$7120_Y
- connect \$11 $or$libresoc.v:145023$7121_Y
- connect \$13 $not$libresoc.v:145024$7122_Y
- connect \$15 $or$libresoc.v:145025$7123_Y
- connect \$1 $not$libresoc.v:145026$7124_Y
- connect \$3 $and$libresoc.v:145027$7125_Y
- connect \$5 $or$libresoc.v:145028$7126_Y
- connect \$7 $not$libresoc.v:145029$7127_Y
+ connect \$9 $and$libresoc.v:143152$7046_Y
+ connect \$11 $or$libresoc.v:143153$7047_Y
+ connect \$13 $not$libresoc.v:143154$7048_Y
+ connect \$15 $or$libresoc.v:143155$7049_Y
+ connect \$1 $not$libresoc.v:143156$7050_Y
+ connect \$3 $and$libresoc.v:143157$7051_Y
+ connect \$5 $or$libresoc.v:143158$7052_Y
+ connect \$7 $not$libresoc.v:143159$7053_Y
connect \qlq_lsd \$15
connect \qn_lsd \$13
connect \q_lsd \$11
end
-attribute \src "libresoc.v:145048.1-145582.10"
+attribute \src "libresoc.v:143178.1-143712.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem"
attribute \generator "nMigen"
module \lsmem
- attribute \src "libresoc.v:145436.3-145461.6"
- wire width 45 $0\dbus__adr$next[44:0]$7219
- attribute \src "libresoc.v:145286.3-145287.35"
+ attribute \src "libresoc.v:143566.3-143591.6"
+ wire width 45 $0\dbus__adr$next[44:0]$7145
+ attribute \src "libresoc.v:143416.3-143417.35"
wire width 45 $0\dbus__adr[44:0]
- attribute \src "libresoc.v:145296.3-145323.6"
- wire $0\dbus__cyc$next[0:0]$7193
- attribute \src "libresoc.v:145294.3-145295.35"
+ attribute \src "libresoc.v:143426.3-143453.6"
+ wire $0\dbus__cyc$next[0:0]$7119
+ attribute \src "libresoc.v:143424.3-143425.35"
wire $0\dbus__cyc[0:0]
- attribute \src "libresoc.v:145488.3-145513.6"
- wire width 64 $0\dbus__dat_w$next[63:0]$7229
- attribute \src "libresoc.v:145282.3-145283.39"
+ attribute \src "libresoc.v:143618.3-143643.6"
+ wire width 64 $0\dbus__dat_w$next[63:0]$7155
+ attribute \src "libresoc.v:143412.3-143413.39"
wire width 64 $0\dbus__dat_w[63:0]
- attribute \src "libresoc.v:145380.3-145410.6"
- wire width 8 $0\dbus__sel$next[7:0]$7207
- attribute \src "libresoc.v:145290.3-145291.35"
+ attribute \src "libresoc.v:143510.3-143540.6"
+ wire width 8 $0\dbus__sel$next[7:0]$7133
+ attribute \src "libresoc.v:143420.3-143421.35"
wire width 8 $0\dbus__sel[7:0]
- attribute \src "libresoc.v:145324.3-145351.6"
- wire $0\dbus__stb$next[0:0]$7199
- attribute \src "libresoc.v:145292.3-145293.35"
+ attribute \src "libresoc.v:143454.3-143481.6"
+ wire $0\dbus__stb$next[0:0]$7125
+ attribute \src "libresoc.v:143422.3-143423.35"
wire $0\dbus__stb[0:0]
- attribute \src "libresoc.v:145462.3-145487.6"
- wire $0\dbus__we$next[0:0]$7224
- attribute \src "libresoc.v:145284.3-145285.33"
+ attribute \src "libresoc.v:143592.3-143617.6"
+ wire $0\dbus__we$next[0:0]$7150
+ attribute \src "libresoc.v:143414.3-143415.33"
wire $0\dbus__we[0:0]
- attribute \src "libresoc.v:145049.7-145049.20"
+ attribute \src "libresoc.v:143179.7-143179.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:145560.3-145579.6"
- wire width 45 $0\m_badaddr_o$next[44:0]$7244
- attribute \src "libresoc.v:145276.3-145277.39"
+ attribute \src "libresoc.v:143690.3-143709.6"
+ wire width 45 $0\m_badaddr_o$next[44:0]$7170
+ attribute \src "libresoc.v:143406.3-143407.39"
wire width 45 $0\m_badaddr_o[44:0]
- attribute \src "libresoc.v:145362.3-145379.6"
+ attribute \src "libresoc.v:143492.3-143509.6"
wire $0\m_busy_o[0:0]
- attribute \src "libresoc.v:145411.3-145435.6"
- wire width 64 $0\m_ld_data_o$next[63:0]$7213
- attribute \src "libresoc.v:145288.3-145289.39"
+ attribute \src "libresoc.v:143541.3-143565.6"
+ wire width 64 $0\m_ld_data_o$next[63:0]$7139
+ attribute \src "libresoc.v:143418.3-143419.39"
wire width 64 $0\m_ld_data_o[63:0]
- attribute \src "libresoc.v:145514.3-145536.6"
- wire $0\m_load_err_o$next[0:0]$7234
- attribute \src "libresoc.v:145280.3-145281.41"
+ attribute \src "libresoc.v:143644.3-143666.6"
+ wire $0\m_load_err_o$next[0:0]$7160
+ attribute \src "libresoc.v:143410.3-143411.41"
wire $0\m_load_err_o[0:0]
- attribute \src "libresoc.v:145537.3-145559.6"
- wire $0\m_store_err_o$next[0:0]$7239
- attribute \src "libresoc.v:145278.3-145279.43"
+ attribute \src "libresoc.v:143667.3-143689.6"
+ wire $0\m_store_err_o$next[0:0]$7165
+ attribute \src "libresoc.v:143408.3-143409.43"
wire $0\m_store_err_o[0:0]
- attribute \src "libresoc.v:145352.3-145361.6"
+ attribute \src "libresoc.v:143482.3-143491.6"
wire $0\x_busy_o[0:0]
- attribute \src "libresoc.v:145436.3-145461.6"
- wire width 45 $1\dbus__adr$next[44:0]$7220
- attribute \src "libresoc.v:145154.14-145154.42"
+ attribute \src "libresoc.v:143566.3-143591.6"
+ wire width 45 $1\dbus__adr$next[44:0]$7146
+ attribute \src "libresoc.v:143284.14-143284.42"
wire width 45 $1\dbus__adr[44:0]
- attribute \src "libresoc.v:145296.3-145323.6"
- wire $1\dbus__cyc$next[0:0]$7194
- attribute \src "libresoc.v:145159.7-145159.23"
+ attribute \src "libresoc.v:143426.3-143453.6"
+ wire $1\dbus__cyc$next[0:0]$7120
+ attribute \src "libresoc.v:143289.7-143289.23"
wire $1\dbus__cyc[0:0]
- attribute \src "libresoc.v:145488.3-145513.6"
- wire width 64 $1\dbus__dat_w$next[63:0]$7230
- attribute \src "libresoc.v:145166.14-145166.48"
+ attribute \src "libresoc.v:143618.3-143643.6"
+ wire width 64 $1\dbus__dat_w$next[63:0]$7156
+ attribute \src "libresoc.v:143296.14-143296.48"
wire width 64 $1\dbus__dat_w[63:0]
- attribute \src "libresoc.v:145380.3-145410.6"
- wire width 8 $1\dbus__sel$next[7:0]$7208
- attribute \src "libresoc.v:145173.13-145173.30"
+ attribute \src "libresoc.v:143510.3-143540.6"
+ wire width 8 $1\dbus__sel$next[7:0]$7134
+ attribute \src "libresoc.v:143303.13-143303.30"
wire width 8 $1\dbus__sel[7:0]
- attribute \src "libresoc.v:145324.3-145351.6"
- wire $1\dbus__stb$next[0:0]$7200
- attribute \src "libresoc.v:145178.7-145178.23"
+ attribute \src "libresoc.v:143454.3-143481.6"
+ wire $1\dbus__stb$next[0:0]$7126
+ attribute \src "libresoc.v:143308.7-143308.23"
wire $1\dbus__stb[0:0]
- attribute \src "libresoc.v:145462.3-145487.6"
- wire $1\dbus__we$next[0:0]$7225
- attribute \src "libresoc.v:145183.7-145183.22"
+ attribute \src "libresoc.v:143592.3-143617.6"
+ wire $1\dbus__we$next[0:0]$7151
+ attribute \src "libresoc.v:143313.7-143313.22"
wire $1\dbus__we[0:0]
- attribute \src "libresoc.v:145560.3-145579.6"
- wire width 45 $1\m_badaddr_o$next[44:0]$7245
- attribute \src "libresoc.v:145187.14-145187.44"
+ attribute \src "libresoc.v:143690.3-143709.6"
+ wire width 45 $1\m_badaddr_o$next[44:0]$7171
+ attribute \src "libresoc.v:143317.14-143317.44"
wire width 45 $1\m_badaddr_o[44:0]
- attribute \src "libresoc.v:145362.3-145379.6"
+ attribute \src "libresoc.v:143492.3-143509.6"
wire $1\m_busy_o[0:0]
- attribute \src "libresoc.v:145411.3-145435.6"
- wire width 64 $1\m_ld_data_o$next[63:0]$7214
- attribute \src "libresoc.v:145194.14-145194.48"
+ attribute \src "libresoc.v:143541.3-143565.6"
+ wire width 64 $1\m_ld_data_o$next[63:0]$7140
+ attribute \src "libresoc.v:143324.14-143324.48"
wire width 64 $1\m_ld_data_o[63:0]
- attribute \src "libresoc.v:145514.3-145536.6"
- wire $1\m_load_err_o$next[0:0]$7235
- attribute \src "libresoc.v:145198.7-145198.26"
+ attribute \src "libresoc.v:143644.3-143666.6"
+ wire $1\m_load_err_o$next[0:0]$7161
+ attribute \src "libresoc.v:143328.7-143328.26"
wire $1\m_load_err_o[0:0]
- attribute \src "libresoc.v:145537.3-145559.6"
- wire $1\m_store_err_o$next[0:0]$7240
- attribute \src "libresoc.v:145204.7-145204.27"
+ attribute \src "libresoc.v:143667.3-143689.6"
+ wire $1\m_store_err_o$next[0:0]$7166
+ attribute \src "libresoc.v:143334.7-143334.27"
wire $1\m_store_err_o[0:0]
- attribute \src "libresoc.v:145352.3-145361.6"
+ attribute \src "libresoc.v:143482.3-143491.6"
wire $1\x_busy_o[0:0]
- attribute \src "libresoc.v:145436.3-145461.6"
- wire width 45 $2\dbus__adr$next[44:0]$7221
- attribute \src "libresoc.v:145296.3-145323.6"
- wire $2\dbus__cyc$next[0:0]$7195
- attribute \src "libresoc.v:145488.3-145513.6"
- wire width 64 $2\dbus__dat_w$next[63:0]$7231
- attribute \src "libresoc.v:145380.3-145410.6"
- wire width 8 $2\dbus__sel$next[7:0]$7209
- attribute \src "libresoc.v:145324.3-145351.6"
- wire $2\dbus__stb$next[0:0]$7201
- attribute \src "libresoc.v:145462.3-145487.6"
- wire $2\dbus__we$next[0:0]$7226
- attribute \src "libresoc.v:145560.3-145579.6"
- wire width 45 $2\m_badaddr_o$next[44:0]$7246
- attribute \src "libresoc.v:145362.3-145379.6"
+ attribute \src "libresoc.v:143566.3-143591.6"
+ wire width 45 $2\dbus__adr$next[44:0]$7147
+ attribute \src "libresoc.v:143426.3-143453.6"
+ wire $2\dbus__cyc$next[0:0]$7121
+ attribute \src "libresoc.v:143618.3-143643.6"
+ wire width 64 $2\dbus__dat_w$next[63:0]$7157
+ attribute \src "libresoc.v:143510.3-143540.6"
+ wire width 8 $2\dbus__sel$next[7:0]$7135
+ attribute \src "libresoc.v:143454.3-143481.6"
+ wire $2\dbus__stb$next[0:0]$7127
+ attribute \src "libresoc.v:143592.3-143617.6"
+ wire $2\dbus__we$next[0:0]$7152
+ attribute \src "libresoc.v:143690.3-143709.6"
+ wire width 45 $2\m_badaddr_o$next[44:0]$7172
+ attribute \src "libresoc.v:143492.3-143509.6"
wire $2\m_busy_o[0:0]
- attribute \src "libresoc.v:145411.3-145435.6"
- wire width 64 $2\m_ld_data_o$next[63:0]$7215
- attribute \src "libresoc.v:145514.3-145536.6"
- wire $2\m_load_err_o$next[0:0]$7236
- attribute \src "libresoc.v:145537.3-145559.6"
- wire $2\m_store_err_o$next[0:0]$7241
- attribute \src "libresoc.v:145436.3-145461.6"
- wire width 45 $3\dbus__adr$next[44:0]$7222
- attribute \src "libresoc.v:145296.3-145323.6"
- wire $3\dbus__cyc$next[0:0]$7196
- attribute \src "libresoc.v:145488.3-145513.6"
- wire width 64 $3\dbus__dat_w$next[63:0]$7232
- attribute \src "libresoc.v:145380.3-145410.6"
- wire width 8 $3\dbus__sel$next[7:0]$7210
- attribute \src "libresoc.v:145324.3-145351.6"
- wire $3\dbus__stb$next[0:0]$7202
- attribute \src "libresoc.v:145462.3-145487.6"
- wire $3\dbus__we$next[0:0]$7227
- attribute \src "libresoc.v:145560.3-145579.6"
- wire width 45 $3\m_badaddr_o$next[44:0]$7247
- attribute \src "libresoc.v:145411.3-145435.6"
- wire width 64 $3\m_ld_data_o$next[63:0]$7216
- attribute \src "libresoc.v:145514.3-145536.6"
- wire $3\m_load_err_o$next[0:0]$7237
- attribute \src "libresoc.v:145537.3-145559.6"
- wire $3\m_store_err_o$next[0:0]$7242
- attribute \src "libresoc.v:145296.3-145323.6"
- wire $4\dbus__cyc$next[0:0]$7197
- attribute \src "libresoc.v:145380.3-145410.6"
- wire width 8 $4\dbus__sel$next[7:0]$7211
- attribute \src "libresoc.v:145324.3-145351.6"
- wire $4\dbus__stb$next[0:0]$7203
- attribute \src "libresoc.v:145411.3-145435.6"
- wire width 64 $4\m_ld_data_o$next[63:0]$7217
- attribute \src "libresoc.v:145232.18-145232.116"
- wire $and$libresoc.v:145232$7138_Y
- attribute \src "libresoc.v:145235.18-145235.111"
- wire $and$libresoc.v:145235$7141_Y
- attribute \src "libresoc.v:145240.18-145240.116"
- wire $and$libresoc.v:145240$7146_Y
- attribute \src "libresoc.v:145242.18-145242.111"
- wire $and$libresoc.v:145242$7148_Y
- attribute \src "libresoc.v:145244.17-145244.114"
- wire $and$libresoc.v:145244$7150_Y
- attribute \src "libresoc.v:145248.18-145248.116"
- wire $and$libresoc.v:145248$7154_Y
- attribute \src "libresoc.v:145250.18-145250.111"
- wire $and$libresoc.v:145250$7156_Y
- attribute \src "libresoc.v:145256.18-145256.116"
- wire $and$libresoc.v:145256$7162_Y
- attribute \src "libresoc.v:145258.18-145258.111"
- wire $and$libresoc.v:145258$7164_Y
- attribute \src "libresoc.v:145260.18-145260.116"
- wire $and$libresoc.v:145260$7166_Y
- attribute \src "libresoc.v:145262.18-145262.111"
- wire $and$libresoc.v:145262$7168_Y
- attribute \src "libresoc.v:145264.18-145264.116"
- wire $and$libresoc.v:145264$7170_Y
- attribute \src "libresoc.v:145266.17-145266.108"
- wire $and$libresoc.v:145266$7172_Y
- attribute \src "libresoc.v:145267.18-145267.111"
- wire $and$libresoc.v:145267$7173_Y
- attribute \src "libresoc.v:145268.18-145268.120"
- wire $and$libresoc.v:145268$7174_Y
- attribute \src "libresoc.v:145271.18-145271.120"
- wire $and$libresoc.v:145271$7177_Y
- attribute \src "libresoc.v:145273.18-145273.120"
- wire $and$libresoc.v:145273$7179_Y
- attribute \src "libresoc.v:145229.18-145229.110"
- wire $not$libresoc.v:145229$7135_Y
- attribute \src "libresoc.v:145234.18-145234.110"
- wire $not$libresoc.v:145234$7140_Y
- attribute \src "libresoc.v:145237.18-145237.110"
- wire $not$libresoc.v:145237$7143_Y
- attribute \src "libresoc.v:145241.18-145241.110"
- wire $not$libresoc.v:145241$7147_Y
- attribute \src "libresoc.v:145245.18-145245.110"
- wire $not$libresoc.v:145245$7151_Y
- attribute \src "libresoc.v:145249.18-145249.110"
- wire $not$libresoc.v:145249$7155_Y
- attribute \src "libresoc.v:145252.18-145252.110"
- wire $not$libresoc.v:145252$7158_Y
- attribute \src "libresoc.v:145255.17-145255.109"
- wire $not$libresoc.v:145255$7161_Y
- attribute \src "libresoc.v:145257.18-145257.110"
- wire $not$libresoc.v:145257$7163_Y
- attribute \src "libresoc.v:145261.18-145261.110"
- wire $not$libresoc.v:145261$7167_Y
- attribute \src "libresoc.v:145265.18-145265.110"
- wire $not$libresoc.v:145265$7171_Y
- attribute \src "libresoc.v:145269.18-145269.110"
- wire $not$libresoc.v:145269$7175_Y
- attribute \src "libresoc.v:145270.18-145270.109"
- wire $not$libresoc.v:145270$7176_Y
- attribute \src "libresoc.v:145272.18-145272.110"
- wire $not$libresoc.v:145272$7178_Y
- attribute \src "libresoc.v:145274.18-145274.110"
- wire $not$libresoc.v:145274$7180_Y
- attribute \src "libresoc.v:145228.17-145228.119"
- wire $or$libresoc.v:145228$7134_Y
- attribute \src "libresoc.v:145230.18-145230.110"
- wire $or$libresoc.v:145230$7136_Y
- attribute \src "libresoc.v:145231.18-145231.114"
- wire $or$libresoc.v:145231$7137_Y
- attribute \src "libresoc.v:145233.17-145233.113"
- wire $or$libresoc.v:145233$7139_Y
- attribute \src "libresoc.v:145236.18-145236.120"
- wire $or$libresoc.v:145236$7142_Y
- attribute \src "libresoc.v:145238.18-145238.111"
- wire $or$libresoc.v:145238$7144_Y
- attribute \src "libresoc.v:145239.18-145239.114"
- wire $or$libresoc.v:145239$7145_Y
- attribute \src "libresoc.v:145243.18-145243.120"
- wire $or$libresoc.v:145243$7149_Y
- attribute \src "libresoc.v:145246.18-145246.111"
- wire $or$libresoc.v:145246$7152_Y
- attribute \src "libresoc.v:145247.18-145247.114"
- wire $or$libresoc.v:145247$7153_Y
- attribute \src "libresoc.v:145251.18-145251.120"
- wire $or$libresoc.v:145251$7157_Y
- attribute \src "libresoc.v:145253.18-145253.111"
- wire $or$libresoc.v:145253$7159_Y
- attribute \src "libresoc.v:145254.18-145254.114"
- wire $or$libresoc.v:145254$7160_Y
- attribute \src "libresoc.v:145259.18-145259.114"
- wire $or$libresoc.v:145259$7165_Y
- attribute \src "libresoc.v:145263.18-145263.114"
- wire $or$libresoc.v:145263$7169_Y
- attribute \src "libresoc.v:145275.18-145275.127"
- wire $or$libresoc.v:145275$7181_Y
+ attribute \src "libresoc.v:143541.3-143565.6"
+ wire width 64 $2\m_ld_data_o$next[63:0]$7141
+ attribute \src "libresoc.v:143644.3-143666.6"
+ wire $2\m_load_err_o$next[0:0]$7162
+ attribute \src "libresoc.v:143667.3-143689.6"
+ wire $2\m_store_err_o$next[0:0]$7167
+ attribute \src "libresoc.v:143566.3-143591.6"
+ wire width 45 $3\dbus__adr$next[44:0]$7148
+ attribute \src "libresoc.v:143426.3-143453.6"
+ wire $3\dbus__cyc$next[0:0]$7122
+ attribute \src "libresoc.v:143618.3-143643.6"
+ wire width 64 $3\dbus__dat_w$next[63:0]$7158
+ attribute \src "libresoc.v:143510.3-143540.6"
+ wire width 8 $3\dbus__sel$next[7:0]$7136
+ attribute \src "libresoc.v:143454.3-143481.6"
+ wire $3\dbus__stb$next[0:0]$7128
+ attribute \src "libresoc.v:143592.3-143617.6"
+ wire $3\dbus__we$next[0:0]$7153
+ attribute \src "libresoc.v:143690.3-143709.6"
+ wire width 45 $3\m_badaddr_o$next[44:0]$7173
+ attribute \src "libresoc.v:143541.3-143565.6"
+ wire width 64 $3\m_ld_data_o$next[63:0]$7142
+ attribute \src "libresoc.v:143644.3-143666.6"
+ wire $3\m_load_err_o$next[0:0]$7163
+ attribute \src "libresoc.v:143667.3-143689.6"
+ wire $3\m_store_err_o$next[0:0]$7168
+ attribute \src "libresoc.v:143426.3-143453.6"
+ wire $4\dbus__cyc$next[0:0]$7123
+ attribute \src "libresoc.v:143510.3-143540.6"
+ wire width 8 $4\dbus__sel$next[7:0]$7137
+ attribute \src "libresoc.v:143454.3-143481.6"
+ wire $4\dbus__stb$next[0:0]$7129
+ attribute \src "libresoc.v:143541.3-143565.6"
+ wire width 64 $4\m_ld_data_o$next[63:0]$7143
+ attribute \src "libresoc.v:143362.18-143362.116"
+ wire $and$libresoc.v:143362$7064_Y
+ attribute \src "libresoc.v:143365.18-143365.111"
+ wire $and$libresoc.v:143365$7067_Y
+ attribute \src "libresoc.v:143370.18-143370.116"
+ wire $and$libresoc.v:143370$7072_Y
+ attribute \src "libresoc.v:143372.18-143372.111"
+ wire $and$libresoc.v:143372$7074_Y
+ attribute \src "libresoc.v:143374.17-143374.114"
+ wire $and$libresoc.v:143374$7076_Y
+ attribute \src "libresoc.v:143378.18-143378.116"
+ wire $and$libresoc.v:143378$7080_Y
+ attribute \src "libresoc.v:143380.18-143380.111"
+ wire $and$libresoc.v:143380$7082_Y
+ attribute \src "libresoc.v:143386.18-143386.116"
+ wire $and$libresoc.v:143386$7088_Y
+ attribute \src "libresoc.v:143388.18-143388.111"
+ wire $and$libresoc.v:143388$7090_Y
+ attribute \src "libresoc.v:143390.18-143390.116"
+ wire $and$libresoc.v:143390$7092_Y
+ attribute \src "libresoc.v:143392.18-143392.111"
+ wire $and$libresoc.v:143392$7094_Y
+ attribute \src "libresoc.v:143394.18-143394.116"
+ wire $and$libresoc.v:143394$7096_Y
+ attribute \src "libresoc.v:143396.17-143396.108"
+ wire $and$libresoc.v:143396$7098_Y
+ attribute \src "libresoc.v:143397.18-143397.111"
+ wire $and$libresoc.v:143397$7099_Y
+ attribute \src "libresoc.v:143398.18-143398.120"
+ wire $and$libresoc.v:143398$7100_Y
+ attribute \src "libresoc.v:143401.18-143401.120"
+ wire $and$libresoc.v:143401$7103_Y
+ attribute \src "libresoc.v:143403.18-143403.120"
+ wire $and$libresoc.v:143403$7105_Y
+ attribute \src "libresoc.v:143359.18-143359.110"
+ wire $not$libresoc.v:143359$7061_Y
+ attribute \src "libresoc.v:143364.18-143364.110"
+ wire $not$libresoc.v:143364$7066_Y
+ attribute \src "libresoc.v:143367.18-143367.110"
+ wire $not$libresoc.v:143367$7069_Y
+ attribute \src "libresoc.v:143371.18-143371.110"
+ wire $not$libresoc.v:143371$7073_Y
+ attribute \src "libresoc.v:143375.18-143375.110"
+ wire $not$libresoc.v:143375$7077_Y
+ attribute \src "libresoc.v:143379.18-143379.110"
+ wire $not$libresoc.v:143379$7081_Y
+ attribute \src "libresoc.v:143382.18-143382.110"
+ wire $not$libresoc.v:143382$7084_Y
+ attribute \src "libresoc.v:143385.17-143385.109"
+ wire $not$libresoc.v:143385$7087_Y
+ attribute \src "libresoc.v:143387.18-143387.110"
+ wire $not$libresoc.v:143387$7089_Y
+ attribute \src "libresoc.v:143391.18-143391.110"
+ wire $not$libresoc.v:143391$7093_Y
+ attribute \src "libresoc.v:143395.18-143395.110"
+ wire $not$libresoc.v:143395$7097_Y
+ attribute \src "libresoc.v:143399.18-143399.110"
+ wire $not$libresoc.v:143399$7101_Y
+ attribute \src "libresoc.v:143400.18-143400.109"
+ wire $not$libresoc.v:143400$7102_Y
+ attribute \src "libresoc.v:143402.18-143402.110"
+ wire $not$libresoc.v:143402$7104_Y
+ attribute \src "libresoc.v:143404.18-143404.110"
+ wire $not$libresoc.v:143404$7106_Y
+ attribute \src "libresoc.v:143358.17-143358.119"
+ wire $or$libresoc.v:143358$7060_Y
+ attribute \src "libresoc.v:143360.18-143360.110"
+ wire $or$libresoc.v:143360$7062_Y
+ attribute \src "libresoc.v:143361.18-143361.114"
+ wire $or$libresoc.v:143361$7063_Y
+ attribute \src "libresoc.v:143363.17-143363.113"
+ wire $or$libresoc.v:143363$7065_Y
+ attribute \src "libresoc.v:143366.18-143366.120"
+ wire $or$libresoc.v:143366$7068_Y
+ attribute \src "libresoc.v:143368.18-143368.111"
+ wire $or$libresoc.v:143368$7070_Y
+ attribute \src "libresoc.v:143369.18-143369.114"
+ wire $or$libresoc.v:143369$7071_Y
+ attribute \src "libresoc.v:143373.18-143373.120"
+ wire $or$libresoc.v:143373$7075_Y
+ attribute \src "libresoc.v:143376.18-143376.111"
+ wire $or$libresoc.v:143376$7078_Y
+ attribute \src "libresoc.v:143377.18-143377.114"
+ wire $or$libresoc.v:143377$7079_Y
+ attribute \src "libresoc.v:143381.18-143381.120"
+ wire $or$libresoc.v:143381$7083_Y
+ attribute \src "libresoc.v:143383.18-143383.111"
+ wire $or$libresoc.v:143383$7085_Y
+ attribute \src "libresoc.v:143384.18-143384.114"
+ wire $or$libresoc.v:143384$7086_Y
+ attribute \src "libresoc.v:143389.18-143389.114"
+ wire $or$libresoc.v:143389$7091_Y
+ attribute \src "libresoc.v:143393.18-143393.114"
+ wire $or$libresoc.v:143393$7095_Y
+ attribute \src "libresoc.v:143405.18-143405.127"
+ wire $or$libresoc.v:143405$7107_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
wire \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
wire \$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 13 \dbus__ack
wire output 19 \dbus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire \dbus__we$next
- attribute \src "libresoc.v:145049.7-145049.15"
+ attribute \src "libresoc.v:143179.7-143179.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77"
wire width 45 \m_badaddr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57"
wire input 10 \x_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145232$7138
+ cell $and $and$libresoc.v:143362$7064
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145232$7138_Y
+ connect \Y $and$libresoc.v:143362$7064_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145235$7141
+ cell $and $and$libresoc.v:143365$7067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$17
connect \B \$19
- connect \Y $and$libresoc.v:145235$7141_Y
+ connect \Y $and$libresoc.v:143365$7067_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145240$7146
+ cell $and $and$libresoc.v:143370$7072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145240$7146_Y
+ connect \Y $and$libresoc.v:143370$7072_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145242$7148
+ cell $and $and$libresoc.v:143372$7074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $and$libresoc.v:145242$7148_Y
+ connect \Y $and$libresoc.v:143372$7074_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145244$7150
+ cell $and $and$libresoc.v:143374$7076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145244$7150_Y
+ connect \Y $and$libresoc.v:143374$7076_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145248$7154
+ cell $and $and$libresoc.v:143378$7080
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145248$7154_Y
+ connect \Y $and$libresoc.v:143378$7080_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145250$7156
+ cell $and $and$libresoc.v:143380$7082
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$45
connect \B \$47
- connect \Y $and$libresoc.v:145250$7156_Y
+ connect \Y $and$libresoc.v:143380$7082_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145256$7162
+ cell $and $and$libresoc.v:143386$7088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$57
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145256$7162_Y
+ connect \Y $and$libresoc.v:143386$7088_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145258$7164
+ cell $and $and$libresoc.v:143388$7090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$59
connect \B \$61
- connect \Y $and$libresoc.v:145258$7164_Y
+ connect \Y $and$libresoc.v:143388$7090_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145260$7166
+ cell $and $and$libresoc.v:143390$7092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$65
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145260$7166_Y
+ connect \Y $and$libresoc.v:143390$7092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145262$7168
+ cell $and $and$libresoc.v:143392$7094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$67
connect \B \$69
- connect \Y $and$libresoc.v:145262$7168_Y
+ connect \Y $and$libresoc.v:143392$7094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145264$7170
+ cell $and $and$libresoc.v:143394$7096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \x_valid_i
- connect \Y $and$libresoc.v:145264$7170_Y
+ connect \Y $and$libresoc.v:143394$7096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145266$7172
+ cell $and $and$libresoc.v:143396$7098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:145266$7172_Y
+ connect \Y $and$libresoc.v:143396$7098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $and $and$libresoc.v:145267$7173
+ cell $and $and$libresoc.v:143397$7099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$75
connect \B \$77
- connect \Y $and$libresoc.v:145267$7173_Y
+ connect \Y $and$libresoc.v:143397$7099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:145268$7174
+ cell $and $and$libresoc.v:143398$7100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:145268$7174_Y
+ connect \Y $and$libresoc.v:143398$7100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:145271$7177
+ cell $and $and$libresoc.v:143401$7103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:145271$7177_Y
+ connect \Y $and$libresoc.v:143401$7103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
- cell $and $and$libresoc.v:145273$7179
+ cell $and $and$libresoc.v:143403$7105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__cyc
connect \B \dbus__err
- connect \Y $and$libresoc.v:145273$7179_Y
+ connect \Y $and$libresoc.v:143403$7105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:145229$7135
+ cell $not $not$libresoc.v:143359$7061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:145229$7135_Y
+ connect \Y $not$libresoc.v:143359$7061_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145234$7140
+ cell $not $not$libresoc.v:143364$7066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145234$7140_Y
+ connect \Y $not$libresoc.v:143364$7066_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:145237$7143
+ cell $not $not$libresoc.v:143367$7069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:145237$7143_Y
+ connect \Y $not$libresoc.v:143367$7069_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145241$7147
+ cell $not $not$libresoc.v:143371$7073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145241$7147_Y
+ connect \Y $not$libresoc.v:143371$7073_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:145245$7151
+ cell $not $not$libresoc.v:143375$7077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:145245$7151_Y
+ connect \Y $not$libresoc.v:143375$7077_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145249$7155
+ cell $not $not$libresoc.v:143379$7081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145249$7155_Y
+ connect \Y $not$libresoc.v:143379$7081_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $not $not$libresoc.v:145252$7158
+ cell $not $not$libresoc.v:143382$7084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_valid_i
- connect \Y $not$libresoc.v:145252$7158_Y
+ connect \Y $not$libresoc.v:143382$7084_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145255$7161
+ cell $not $not$libresoc.v:143385$7087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145255$7161_Y
+ connect \Y $not$libresoc.v:143385$7087_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145257$7163
+ cell $not $not$libresoc.v:143387$7089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145257$7163_Y
+ connect \Y $not$libresoc.v:143387$7089_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145261$7167
+ cell $not $not$libresoc.v:143391$7093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145261$7167_Y
+ connect \Y $not$libresoc.v:143391$7093_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $not $not$libresoc.v:145265$7171
+ cell $not $not$libresoc.v:143395$7097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_stall_i
- connect \Y $not$libresoc.v:145265$7171_Y
+ connect \Y $not$libresoc.v:143395$7097_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:145269$7175
+ cell $not $not$libresoc.v:143399$7101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:145269$7175_Y
+ connect \Y $not$libresoc.v:143399$7101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142"
- cell $not $not$libresoc.v:145270$7176
+ cell $not $not$libresoc.v:143400$7102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbus__we
- connect \Y $not$libresoc.v:145270$7176_Y
+ connect \Y $not$libresoc.v:143400$7102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:145272$7178
+ cell $not $not$libresoc.v:143402$7104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:145272$7178_Y
+ connect \Y $not$libresoc.v:143402$7104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146"
- cell $not $not$libresoc.v:145274$7180
+ cell $not $not$libresoc.v:143404$7106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \m_stall_i
- connect \Y $not$libresoc.v:145274$7180_Y
+ connect \Y $not$libresoc.v:143404$7106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145228$7134
+ cell $or $or$libresoc.v:143358$7060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:145228$7134_Y
+ connect \Y $or$libresoc.v:143358$7060_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145230$7136
+ cell $or $or$libresoc.v:143360$7062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \$11
- connect \Y $or$libresoc.v:145230$7136_Y
+ connect \Y $or$libresoc.v:143360$7062_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145231$7137
+ cell $or $or$libresoc.v:143361$7063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145231$7137_Y
+ connect \Y $or$libresoc.v:143361$7063_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145233$7139
+ cell $or $or$libresoc.v:143363$7065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145233$7139_Y
+ connect \Y $or$libresoc.v:143363$7065_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145236$7142
+ cell $or $or$libresoc.v:143366$7068
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:145236$7142_Y
+ connect \Y $or$libresoc.v:143366$7068_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145238$7144
+ cell $or $or$libresoc.v:143368$7070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $or$libresoc.v:145238$7144_Y
+ connect \Y $or$libresoc.v:143368$7070_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145239$7145
+ cell $or $or$libresoc.v:143369$7071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145239$7145_Y
+ connect \Y $or$libresoc.v:143369$7071_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145243$7149
+ cell $or $or$libresoc.v:143373$7075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:145243$7149_Y
+ connect \Y $or$libresoc.v:143373$7075_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145246$7152
+ cell $or $or$libresoc.v:143376$7078
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$37
connect \B \$39
- connect \Y $or$libresoc.v:145246$7152_Y
+ connect \Y $or$libresoc.v:143376$7078_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145247$7153
+ cell $or $or$libresoc.v:143377$7079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145247$7153_Y
+ connect \Y $or$libresoc.v:143377$7079_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145251$7157
+ cell $or $or$libresoc.v:143381$7083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dbus__ack
connect \B \dbus__err
- connect \Y $or$libresoc.v:145251$7157_Y
+ connect \Y $or$libresoc.v:143381$7083_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
- cell $or $or$libresoc.v:145253$7159
+ cell $or $or$libresoc.v:143383$7085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \$53
- connect \Y $or$libresoc.v:145253$7159_Y
+ connect \Y $or$libresoc.v:143383$7085_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145254$7160
+ cell $or $or$libresoc.v:143384$7086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145254$7160_Y
+ connect \Y $or$libresoc.v:143384$7086_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145259$7165
+ cell $or $or$libresoc.v:143389$7091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145259$7165_Y
+ connect \Y $or$libresoc.v:143389$7091_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
- cell $or $or$libresoc.v:145263$7169
+ cell $or $or$libresoc.v:143393$7095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_ld_i
connect \B \x_st_i
- connect \Y $or$libresoc.v:145263$7169_Y
+ connect \Y $or$libresoc.v:143393$7095_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
- cell $or $or$libresoc.v:145275$7181
+ cell $or $or$libresoc.v:143405$7107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \m_load_err_o
connect \B \m_store_err_o
- connect \Y $or$libresoc.v:145275$7181_Y
+ connect \Y $or$libresoc.v:143405$7107_Y
end
- attribute \src "libresoc.v:145049.7-145049.20"
- process $proc$libresoc.v:145049$7248
+ attribute \src "libresoc.v:143179.7-143179.20"
+ process $proc$libresoc.v:143179$7174
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:145154.14-145154.42"
- process $proc$libresoc.v:145154$7249
+ attribute \src "libresoc.v:143284.14-143284.42"
+ process $proc$libresoc.v:143284$7175
assign { } { }
assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \dbus__adr $1\dbus__adr[44:0]
end
- attribute \src "libresoc.v:145159.7-145159.23"
- process $proc$libresoc.v:145159$7250
+ attribute \src "libresoc.v:143289.7-143289.23"
+ process $proc$libresoc.v:143289$7176
assign { } { }
assign $1\dbus__cyc[0:0] 1'0
sync always
sync init
update \dbus__cyc $1\dbus__cyc[0:0]
end
- attribute \src "libresoc.v:145166.14-145166.48"
- process $proc$libresoc.v:145166$7251
+ attribute \src "libresoc.v:143296.14-143296.48"
+ process $proc$libresoc.v:143296$7177
assign { } { }
assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbus__dat_w $1\dbus__dat_w[63:0]
end
- attribute \src "libresoc.v:145173.13-145173.30"
- process $proc$libresoc.v:145173$7252
+ attribute \src "libresoc.v:143303.13-143303.30"
+ process $proc$libresoc.v:143303$7178
assign { } { }
assign $1\dbus__sel[7:0] 8'00000000
sync always
sync init
update \dbus__sel $1\dbus__sel[7:0]
end
- attribute \src "libresoc.v:145178.7-145178.23"
- process $proc$libresoc.v:145178$7253
+ attribute \src "libresoc.v:143308.7-143308.23"
+ process $proc$libresoc.v:143308$7179
assign { } { }
assign $1\dbus__stb[0:0] 1'0
sync always
sync init
update \dbus__stb $1\dbus__stb[0:0]
end
- attribute \src "libresoc.v:145183.7-145183.22"
- process $proc$libresoc.v:145183$7254
+ attribute \src "libresoc.v:143313.7-143313.22"
+ process $proc$libresoc.v:143313$7180
assign { } { }
assign $1\dbus__we[0:0] 1'0
sync always
sync init
update \dbus__we $1\dbus__we[0:0]
end
- attribute \src "libresoc.v:145187.14-145187.44"
- process $proc$libresoc.v:145187$7255
+ attribute \src "libresoc.v:143317.14-143317.44"
+ process $proc$libresoc.v:143317$7181
assign { } { }
assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \m_badaddr_o $1\m_badaddr_o[44:0]
end
- attribute \src "libresoc.v:145194.14-145194.48"
- process $proc$libresoc.v:145194$7256
+ attribute \src "libresoc.v:143324.14-143324.48"
+ process $proc$libresoc.v:143324$7182
assign { } { }
assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \m_ld_data_o $1\m_ld_data_o[63:0]
end
- attribute \src "libresoc.v:145198.7-145198.26"
- process $proc$libresoc.v:145198$7257
+ attribute \src "libresoc.v:143328.7-143328.26"
+ process $proc$libresoc.v:143328$7183
assign { } { }
assign $1\m_load_err_o[0:0] 1'0
sync always
sync init
update \m_load_err_o $1\m_load_err_o[0:0]
end
- attribute \src "libresoc.v:145204.7-145204.27"
- process $proc$libresoc.v:145204$7258
+ attribute \src "libresoc.v:143334.7-143334.27"
+ process $proc$libresoc.v:143334$7184
assign { } { }
assign $1\m_store_err_o[0:0] 1'0
sync always
sync init
update \m_store_err_o $1\m_store_err_o[0:0]
end
- attribute \src "libresoc.v:145276.3-145277.39"
- process $proc$libresoc.v:145276$7182
+ attribute \src "libresoc.v:143406.3-143407.39"
+ process $proc$libresoc.v:143406$7108
assign { } { }
assign $0\m_badaddr_o[44:0] \m_badaddr_o$next
sync posedge \coresync_clk
update \m_badaddr_o $0\m_badaddr_o[44:0]
end
- attribute \src "libresoc.v:145278.3-145279.43"
- process $proc$libresoc.v:145278$7183
+ attribute \src "libresoc.v:143408.3-143409.43"
+ process $proc$libresoc.v:143408$7109
assign { } { }
assign $0\m_store_err_o[0:0] \m_store_err_o$next
sync posedge \coresync_clk
update \m_store_err_o $0\m_store_err_o[0:0]
end
- attribute \src "libresoc.v:145280.3-145281.41"
- process $proc$libresoc.v:145280$7184
+ attribute \src "libresoc.v:143410.3-143411.41"
+ process $proc$libresoc.v:143410$7110
assign { } { }
assign $0\m_load_err_o[0:0] \m_load_err_o$next
sync posedge \coresync_clk
update \m_load_err_o $0\m_load_err_o[0:0]
end
- attribute \src "libresoc.v:145282.3-145283.39"
- process $proc$libresoc.v:145282$7185
+ attribute \src "libresoc.v:143412.3-143413.39"
+ process $proc$libresoc.v:143412$7111
assign { } { }
assign $0\dbus__dat_w[63:0] \dbus__dat_w$next
sync posedge \coresync_clk
update \dbus__dat_w $0\dbus__dat_w[63:0]
end
- attribute \src "libresoc.v:145284.3-145285.33"
- process $proc$libresoc.v:145284$7186
+ attribute \src "libresoc.v:143414.3-143415.33"
+ process $proc$libresoc.v:143414$7112
assign { } { }
assign $0\dbus__we[0:0] \dbus__we$next
sync posedge \coresync_clk
update \dbus__we $0\dbus__we[0:0]
end
- attribute \src "libresoc.v:145286.3-145287.35"
- process $proc$libresoc.v:145286$7187
+ attribute \src "libresoc.v:143416.3-143417.35"
+ process $proc$libresoc.v:143416$7113
assign { } { }
assign $0\dbus__adr[44:0] \dbus__adr$next
sync posedge \coresync_clk
update \dbus__adr $0\dbus__adr[44:0]
end
- attribute \src "libresoc.v:145288.3-145289.39"
- process $proc$libresoc.v:145288$7188
+ attribute \src "libresoc.v:143418.3-143419.39"
+ process $proc$libresoc.v:143418$7114
assign { } { }
assign $0\m_ld_data_o[63:0] \m_ld_data_o$next
sync posedge \coresync_clk
update \m_ld_data_o $0\m_ld_data_o[63:0]
end
- attribute \src "libresoc.v:145290.3-145291.35"
- process $proc$libresoc.v:145290$7189
+ attribute \src "libresoc.v:143420.3-143421.35"
+ process $proc$libresoc.v:143420$7115
assign { } { }
assign $0\dbus__sel[7:0] \dbus__sel$next
sync posedge \coresync_clk
update \dbus__sel $0\dbus__sel[7:0]
end
- attribute \src "libresoc.v:145292.3-145293.35"
- process $proc$libresoc.v:145292$7190
+ attribute \src "libresoc.v:143422.3-143423.35"
+ process $proc$libresoc.v:143422$7116
assign { } { }
assign $0\dbus__stb[0:0] \dbus__stb$next
sync posedge \coresync_clk
update \dbus__stb $0\dbus__stb[0:0]
end
- attribute \src "libresoc.v:145294.3-145295.35"
- process $proc$libresoc.v:145294$7191
+ attribute \src "libresoc.v:143424.3-143425.35"
+ process $proc$libresoc.v:143424$7117
assign { } { }
assign $0\dbus__cyc[0:0] \dbus__cyc$next
sync posedge \coresync_clk
update \dbus__cyc $0\dbus__cyc[0:0]
end
- attribute \src "libresoc.v:145296.3-145323.6"
- process $proc$libresoc.v:145296$7192
+ attribute \src "libresoc.v:143426.3-143453.6"
+ process $proc$libresoc.v:143426$7118
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__cyc$next[0:0]$7193 $4\dbus__cyc$next[0:0]$7197
- attribute \src "libresoc.v:145297.5-145297.29"
+ assign $0\dbus__cyc$next[0:0]$7119 $4\dbus__cyc$next[0:0]$7123
+ attribute \src "libresoc.v:143427.5-143427.29"
switch \initial
- attribute \src "libresoc.v:145297.9-145297.17"
+ attribute \src "libresoc.v:143427.9-143427.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__cyc$next[0:0]$7194 $2\dbus__cyc$next[0:0]$7195
+ assign $1\dbus__cyc$next[0:0]$7120 $2\dbus__cyc$next[0:0]$7121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$7 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__cyc$next[0:0]$7195 $3\dbus__cyc$next[0:0]$7196
+ assign $2\dbus__cyc$next[0:0]$7121 $3\dbus__cyc$next[0:0]$7122
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$13
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__cyc$next[0:0]$7196 1'0
+ assign $3\dbus__cyc$next[0:0]$7122 1'0
case
- assign $3\dbus__cyc$next[0:0]$7196 \dbus__cyc
+ assign $3\dbus__cyc$next[0:0]$7122 \dbus__cyc
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__cyc$next[0:0]$7195 1'1
+ assign $2\dbus__cyc$next[0:0]$7121 1'1
case
- assign $2\dbus__cyc$next[0:0]$7195 \dbus__cyc
+ assign $2\dbus__cyc$next[0:0]$7121 \dbus__cyc
end
case
- assign $1\dbus__cyc$next[0:0]$7194 \dbus__cyc
+ assign $1\dbus__cyc$next[0:0]$7120 \dbus__cyc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__cyc$next[0:0]$7197 1'0
+ assign $4\dbus__cyc$next[0:0]$7123 1'0
case
- assign $4\dbus__cyc$next[0:0]$7197 $1\dbus__cyc$next[0:0]$7194
+ assign $4\dbus__cyc$next[0:0]$7123 $1\dbus__cyc$next[0:0]$7120
end
sync always
- update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7193
+ update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7119
end
- attribute \src "libresoc.v:145324.3-145351.6"
- process $proc$libresoc.v:145324$7198
+ attribute \src "libresoc.v:143454.3-143481.6"
+ process $proc$libresoc.v:143454$7124
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__stb$next[0:0]$7199 $4\dbus__stb$next[0:0]$7203
- attribute \src "libresoc.v:145325.5-145325.29"
+ assign $0\dbus__stb$next[0:0]$7125 $4\dbus__stb$next[0:0]$7129
+ attribute \src "libresoc.v:143455.5-143455.29"
switch \initial
- attribute \src "libresoc.v:145325.9-145325.17"
+ attribute \src "libresoc.v:143455.9-143455.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__stb$next[0:0]$7200 $2\dbus__stb$next[0:0]$7201
+ assign $1\dbus__stb$next[0:0]$7126 $2\dbus__stb$next[0:0]$7127
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$21 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__stb$next[0:0]$7201 $3\dbus__stb$next[0:0]$7202
+ assign $2\dbus__stb$next[0:0]$7127 $3\dbus__stb$next[0:0]$7128
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$27
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__stb$next[0:0]$7202 1'0
+ assign $3\dbus__stb$next[0:0]$7128 1'0
case
- assign $3\dbus__stb$next[0:0]$7202 \dbus__stb
+ assign $3\dbus__stb$next[0:0]$7128 \dbus__stb
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__stb$next[0:0]$7201 1'1
+ assign $2\dbus__stb$next[0:0]$7127 1'1
case
- assign $2\dbus__stb$next[0:0]$7201 \dbus__stb
+ assign $2\dbus__stb$next[0:0]$7127 \dbus__stb
end
case
- assign $1\dbus__stb$next[0:0]$7200 \dbus__stb
+ assign $1\dbus__stb$next[0:0]$7126 \dbus__stb
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__stb$next[0:0]$7203 1'0
+ assign $4\dbus__stb$next[0:0]$7129 1'0
case
- assign $4\dbus__stb$next[0:0]$7203 $1\dbus__stb$next[0:0]$7200
+ assign $4\dbus__stb$next[0:0]$7129 $1\dbus__stb$next[0:0]$7126
end
sync always
- update \dbus__stb$next $0\dbus__stb$next[0:0]$7199
+ update \dbus__stb$next $0\dbus__stb$next[0:0]$7125
end
- attribute \src "libresoc.v:145352.3-145361.6"
- process $proc$libresoc.v:145352$7204
+ attribute \src "libresoc.v:143482.3-143491.6"
+ process $proc$libresoc.v:143482$7130
assign { } { }
assign { } { }
assign $0\x_busy_o[0:0] $1\x_busy_o[0:0]
- attribute \src "libresoc.v:145353.5-145353.29"
+ attribute \src "libresoc.v:143483.5-143483.29"
switch \initial
- attribute \src "libresoc.v:145353.9-145353.17"
+ attribute \src "libresoc.v:143483.9-143483.17"
case 1'1
case
end
sync always
update \x_busy_o $0\x_busy_o[0:0]
end
- attribute \src "libresoc.v:145362.3-145379.6"
- process $proc$libresoc.v:145362$7205
+ attribute \src "libresoc.v:143492.3-143509.6"
+ process $proc$libresoc.v:143492$7131
assign { } { }
assign { } { }
assign $0\m_busy_o[0:0] $1\m_busy_o[0:0]
- attribute \src "libresoc.v:145363.5-145363.29"
+ attribute \src "libresoc.v:143493.5-143493.29"
switch \initial
- attribute \src "libresoc.v:145363.9-145363.17"
+ attribute \src "libresoc.v:143493.9-143493.17"
case 1'1
case
end
sync always
update \m_busy_o $0\m_busy_o[0:0]
end
- attribute \src "libresoc.v:145380.3-145410.6"
- process $proc$libresoc.v:145380$7206
+ attribute \src "libresoc.v:143510.3-143540.6"
+ process $proc$libresoc.v:143510$7132
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__sel$next[7:0]$7207 $4\dbus__sel$next[7:0]$7211
- attribute \src "libresoc.v:145381.5-145381.29"
+ assign $0\dbus__sel$next[7:0]$7133 $4\dbus__sel$next[7:0]$7137
+ attribute \src "libresoc.v:143511.5-143511.29"
switch \initial
- attribute \src "libresoc.v:145381.9-145381.17"
+ attribute \src "libresoc.v:143511.9-143511.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__sel$next[7:0]$7208 $2\dbus__sel$next[7:0]$7209
+ assign $1\dbus__sel$next[7:0]$7134 $2\dbus__sel$next[7:0]$7135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$35 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\dbus__sel$next[7:0]$7209 $3\dbus__sel$next[7:0]$7210
+ assign $2\dbus__sel$next[7:0]$7135 $3\dbus__sel$next[7:0]$7136
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$41
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__sel$next[7:0]$7210 8'00000000
+ assign $3\dbus__sel$next[7:0]$7136 8'00000000
case
- assign $3\dbus__sel$next[7:0]$7210 \dbus__sel
+ assign $3\dbus__sel$next[7:0]$7136 \dbus__sel
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__sel$next[7:0]$7209 \x_mask_i
+ assign $2\dbus__sel$next[7:0]$7135 \x_mask_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__sel$next[7:0]$7209 8'00000000
+ assign $2\dbus__sel$next[7:0]$7135 8'00000000
end
case
- assign $1\dbus__sel$next[7:0]$7208 \dbus__sel
+ assign $1\dbus__sel$next[7:0]$7134 \dbus__sel
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dbus__sel$next[7:0]$7211 8'00000000
+ assign $4\dbus__sel$next[7:0]$7137 8'00000000
case
- assign $4\dbus__sel$next[7:0]$7211 $1\dbus__sel$next[7:0]$7208
+ assign $4\dbus__sel$next[7:0]$7137 $1\dbus__sel$next[7:0]$7134
end
sync always
- update \dbus__sel$next $0\dbus__sel$next[7:0]$7207
+ update \dbus__sel$next $0\dbus__sel$next[7:0]$7133
end
- attribute \src "libresoc.v:145411.3-145435.6"
- process $proc$libresoc.v:145411$7212
+ attribute \src "libresoc.v:143541.3-143565.6"
+ process $proc$libresoc.v:143541$7138
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_ld_data_o$next[63:0]$7213 $4\m_ld_data_o$next[63:0]$7217
- attribute \src "libresoc.v:145412.5-145412.29"
+ assign $0\m_ld_data_o$next[63:0]$7139 $4\m_ld_data_o$next[63:0]$7143
+ attribute \src "libresoc.v:143542.5-143542.29"
switch \initial
- attribute \src "libresoc.v:145412.9-145412.17"
+ attribute \src "libresoc.v:143542.9-143542.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_ld_data_o$next[63:0]$7214 $2\m_ld_data_o$next[63:0]$7215
+ assign $1\m_ld_data_o$next[63:0]$7140 $2\m_ld_data_o$next[63:0]$7141
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$49 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_ld_data_o$next[63:0]$7215 $3\m_ld_data_o$next[63:0]$7216
+ assign $2\m_ld_data_o$next[63:0]$7141 $3\m_ld_data_o$next[63:0]$7142
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
switch \$55
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_ld_data_o$next[63:0]$7216 \dbus__dat_r
+ assign $3\m_ld_data_o$next[63:0]$7142 \dbus__dat_r
case
- assign $3\m_ld_data_o$next[63:0]$7216 \m_ld_data_o
+ assign $3\m_ld_data_o$next[63:0]$7142 \m_ld_data_o
end
case
- assign $2\m_ld_data_o$next[63:0]$7215 \m_ld_data_o
+ assign $2\m_ld_data_o$next[63:0]$7141 \m_ld_data_o
end
case
- assign $1\m_ld_data_o$next[63:0]$7214 \m_ld_data_o
+ assign $1\m_ld_data_o$next[63:0]$7140 \m_ld_data_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\m_ld_data_o$next[63:0]$7217 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $4\m_ld_data_o$next[63:0]$7143 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $4\m_ld_data_o$next[63:0]$7217 $1\m_ld_data_o$next[63:0]$7214
+ assign $4\m_ld_data_o$next[63:0]$7143 $1\m_ld_data_o$next[63:0]$7140
end
sync always
- update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7213
+ update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7139
end
- attribute \src "libresoc.v:145436.3-145461.6"
- process $proc$libresoc.v:145436$7218
+ attribute \src "libresoc.v:143566.3-143591.6"
+ process $proc$libresoc.v:143566$7144
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__adr$next[44:0]$7219 $3\dbus__adr$next[44:0]$7222
- attribute \src "libresoc.v:145437.5-145437.29"
+ assign $0\dbus__adr$next[44:0]$7145 $3\dbus__adr$next[44:0]$7148
+ attribute \src "libresoc.v:143567.5-143567.29"
switch \initial
- attribute \src "libresoc.v:145437.9-145437.17"
+ attribute \src "libresoc.v:143567.9-143567.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__adr$next[44:0]$7220 $2\dbus__adr$next[44:0]$7221
+ assign $1\dbus__adr$next[44:0]$7146 $2\dbus__adr$next[44:0]$7147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$63 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__adr$next[44:0]$7221 \dbus__adr
+ assign $2\dbus__adr$next[44:0]$7147 \dbus__adr
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__adr$next[44:0]$7221 \x_addr_i [47:3]
+ assign $2\dbus__adr$next[44:0]$7147 \x_addr_i [47:3]
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__adr$next[44:0]$7221 45'000000000000000000000000000000000000000000000
+ assign $2\dbus__adr$next[44:0]$7147 45'000000000000000000000000000000000000000000000
end
case
- assign $1\dbus__adr$next[44:0]$7220 \dbus__adr
+ assign $1\dbus__adr$next[44:0]$7146 \dbus__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__adr$next[44:0]$7222 45'000000000000000000000000000000000000000000000
+ assign $3\dbus__adr$next[44:0]$7148 45'000000000000000000000000000000000000000000000
case
- assign $3\dbus__adr$next[44:0]$7222 $1\dbus__adr$next[44:0]$7220
+ assign $3\dbus__adr$next[44:0]$7148 $1\dbus__adr$next[44:0]$7146
end
sync always
- update \dbus__adr$next $0\dbus__adr$next[44:0]$7219
+ update \dbus__adr$next $0\dbus__adr$next[44:0]$7145
end
- attribute \src "libresoc.v:145462.3-145487.6"
- process $proc$libresoc.v:145462$7223
+ attribute \src "libresoc.v:143592.3-143617.6"
+ process $proc$libresoc.v:143592$7149
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__we$next[0:0]$7224 $3\dbus__we$next[0:0]$7227
- attribute \src "libresoc.v:145463.5-145463.29"
+ assign $0\dbus__we$next[0:0]$7150 $3\dbus__we$next[0:0]$7153
+ attribute \src "libresoc.v:143593.5-143593.29"
switch \initial
- attribute \src "libresoc.v:145463.9-145463.17"
+ attribute \src "libresoc.v:143593.9-143593.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__we$next[0:0]$7225 $2\dbus__we$next[0:0]$7226
+ assign $1\dbus__we$next[0:0]$7151 $2\dbus__we$next[0:0]$7152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$71 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__we$next[0:0]$7226 \dbus__we
+ assign $2\dbus__we$next[0:0]$7152 \dbus__we
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__we$next[0:0]$7226 \x_st_i
+ assign $2\dbus__we$next[0:0]$7152 \x_st_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__we$next[0:0]$7226 1'0
+ assign $2\dbus__we$next[0:0]$7152 1'0
end
case
- assign $1\dbus__we$next[0:0]$7225 \dbus__we
+ assign $1\dbus__we$next[0:0]$7151 \dbus__we
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__we$next[0:0]$7227 1'0
+ assign $3\dbus__we$next[0:0]$7153 1'0
case
- assign $3\dbus__we$next[0:0]$7227 $1\dbus__we$next[0:0]$7225
+ assign $3\dbus__we$next[0:0]$7153 $1\dbus__we$next[0:0]$7151
end
sync always
- update \dbus__we$next $0\dbus__we$next[0:0]$7224
+ update \dbus__we$next $0\dbus__we$next[0:0]$7150
end
- attribute \src "libresoc.v:145488.3-145513.6"
- process $proc$libresoc.v:145488$7228
+ attribute \src "libresoc.v:143618.3-143643.6"
+ process $proc$libresoc.v:143618$7154
assign { } { }
assign { } { }
assign { } { }
- assign $0\dbus__dat_w$next[63:0]$7229 $3\dbus__dat_w$next[63:0]$7232
- attribute \src "libresoc.v:145489.5-145489.29"
+ assign $0\dbus__dat_w$next[63:0]$7155 $3\dbus__dat_w$next[63:0]$7158
+ attribute \src "libresoc.v:143619.5-143619.29"
switch \initial
- attribute \src "libresoc.v:145489.9-145489.17"
+ attribute \src "libresoc.v:143619.9-143619.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbus__dat_w$next[63:0]$7230 $2\dbus__dat_w$next[63:0]$7231
+ assign $1\dbus__dat_w$next[63:0]$7156 $2\dbus__dat_w$next[63:0]$7157
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113"
switch { \$79 \dbus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $2\dbus__dat_w$next[63:0]$7231 \dbus__dat_w
+ assign $2\dbus__dat_w$next[63:0]$7157 \dbus__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\dbus__dat_w$next[63:0]$7231 \x_st_data_i
+ assign $2\dbus__dat_w$next[63:0]$7157 \x_st_data_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dbus__dat_w$next[63:0]$7231 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dbus__dat_w$next[63:0]$7157 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $1\dbus__dat_w$next[63:0]$7230 \dbus__dat_w
+ assign $1\dbus__dat_w$next[63:0]$7156 \dbus__dat_w
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dbus__dat_w$next[63:0]$7232 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dbus__dat_w$next[63:0]$7158 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dbus__dat_w$next[63:0]$7232 $1\dbus__dat_w$next[63:0]$7230
+ assign $3\dbus__dat_w$next[63:0]$7158 $1\dbus__dat_w$next[63:0]$7156
end
sync always
- update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7229
+ update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7155
end
- attribute \src "libresoc.v:145514.3-145536.6"
- process $proc$libresoc.v:145514$7233
+ attribute \src "libresoc.v:143644.3-143666.6"
+ process $proc$libresoc.v:143644$7159
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_load_err_o$next[0:0]$7234 $3\m_load_err_o$next[0:0]$7237
- attribute \src "libresoc.v:145515.5-145515.29"
+ assign $0\m_load_err_o$next[0:0]$7160 $3\m_load_err_o$next[0:0]$7163
+ attribute \src "libresoc.v:143645.5-143645.29"
switch \initial
- attribute \src "libresoc.v:145515.9-145515.17"
+ attribute \src "libresoc.v:143645.9-143645.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_load_err_o$next[0:0]$7235 $2\m_load_err_o$next[0:0]$7236
+ assign $1\m_load_err_o$next[0:0]$7161 $2\m_load_err_o$next[0:0]$7162
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$83 \$81 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_load_err_o$next[0:0]$7236 \$85
+ assign $2\m_load_err_o$next[0:0]$7162 \$85
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\m_load_err_o$next[0:0]$7236 1'0
+ assign $2\m_load_err_o$next[0:0]$7162 1'0
case
- assign $2\m_load_err_o$next[0:0]$7236 \m_load_err_o
+ assign $2\m_load_err_o$next[0:0]$7162 \m_load_err_o
end
case
- assign $1\m_load_err_o$next[0:0]$7235 \m_load_err_o
+ assign $1\m_load_err_o$next[0:0]$7161 \m_load_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_load_err_o$next[0:0]$7237 1'0
+ assign $3\m_load_err_o$next[0:0]$7163 1'0
case
- assign $3\m_load_err_o$next[0:0]$7237 $1\m_load_err_o$next[0:0]$7235
+ assign $3\m_load_err_o$next[0:0]$7163 $1\m_load_err_o$next[0:0]$7161
end
sync always
- update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7234
+ update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7160
end
- attribute \src "libresoc.v:145537.3-145559.6"
- process $proc$libresoc.v:145537$7238
+ attribute \src "libresoc.v:143667.3-143689.6"
+ process $proc$libresoc.v:143667$7164
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_store_err_o$next[0:0]$7239 $3\m_store_err_o$next[0:0]$7242
- attribute \src "libresoc.v:145538.5-145538.29"
+ assign $0\m_store_err_o$next[0:0]$7165 $3\m_store_err_o$next[0:0]$7168
+ attribute \src "libresoc.v:143668.5-143668.29"
switch \initial
- attribute \src "libresoc.v:145538.9-145538.17"
+ attribute \src "libresoc.v:143668.9-143668.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_store_err_o$next[0:0]$7240 $2\m_store_err_o$next[0:0]$7241
+ assign $1\m_store_err_o$next[0:0]$7166 $2\m_store_err_o$next[0:0]$7167
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$89 \$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_store_err_o$next[0:0]$7241 \dbus__we
+ assign $2\m_store_err_o$next[0:0]$7167 \dbus__we
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $2\m_store_err_o$next[0:0]$7241 1'0
+ assign $2\m_store_err_o$next[0:0]$7167 1'0
case
- assign $2\m_store_err_o$next[0:0]$7241 \m_store_err_o
+ assign $2\m_store_err_o$next[0:0]$7167 \m_store_err_o
end
case
- assign $1\m_store_err_o$next[0:0]$7240 \m_store_err_o
+ assign $1\m_store_err_o$next[0:0]$7166 \m_store_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_store_err_o$next[0:0]$7242 1'0
+ assign $3\m_store_err_o$next[0:0]$7168 1'0
case
- assign $3\m_store_err_o$next[0:0]$7242 $1\m_store_err_o$next[0:0]$7240
+ assign $3\m_store_err_o$next[0:0]$7168 $1\m_store_err_o$next[0:0]$7166
end
sync always
- update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7239
+ update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7165
end
- attribute \src "libresoc.v:145560.3-145579.6"
- process $proc$libresoc.v:145560$7243
+ attribute \src "libresoc.v:143690.3-143709.6"
+ process $proc$libresoc.v:143690$7169
assign { } { }
assign { } { }
assign { } { }
- assign $0\m_badaddr_o$next[44:0]$7244 $3\m_badaddr_o$next[44:0]$7247
- attribute \src "libresoc.v:145561.5-145561.29"
+ assign $0\m_badaddr_o$next[44:0]$7170 $3\m_badaddr_o$next[44:0]$7173
+ attribute \src "libresoc.v:143691.5-143691.29"
switch \initial
- attribute \src "libresoc.v:145561.9-145561.17"
+ attribute \src "libresoc.v:143691.9-143691.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\m_badaddr_o$next[44:0]$7245 $2\m_badaddr_o$next[44:0]$7246
+ assign $1\m_badaddr_o$next[44:0]$7171 $2\m_badaddr_o$next[44:0]$7172
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140"
switch { \$93 \$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $2\m_badaddr_o$next[44:0]$7246 \dbus__adr
+ assign $2\m_badaddr_o$next[44:0]$7172 \dbus__adr
case
- assign $2\m_badaddr_o$next[44:0]$7246 \m_badaddr_o
+ assign $2\m_badaddr_o$next[44:0]$7172 \m_badaddr_o
end
case
- assign $1\m_badaddr_o$next[44:0]$7245 \m_badaddr_o
+ assign $1\m_badaddr_o$next[44:0]$7171 \m_badaddr_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\m_badaddr_o$next[44:0]$7247 45'000000000000000000000000000000000000000000000
- case
- assign $3\m_badaddr_o$next[44:0]$7247 $1\m_badaddr_o$next[44:0]$7245
- end
- sync always
- update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7244
- end
- connect \$9 $or$libresoc.v:145228$7134_Y
- connect \$11 $not$libresoc.v:145229$7135_Y
- connect \$13 $or$libresoc.v:145230$7136_Y
- connect \$15 $or$libresoc.v:145231$7137_Y
- connect \$17 $and$libresoc.v:145232$7138_Y
- connect \$1 $or$libresoc.v:145233$7139_Y
- connect \$19 $not$libresoc.v:145234$7140_Y
- connect \$21 $and$libresoc.v:145235$7141_Y
- connect \$23 $or$libresoc.v:145236$7142_Y
- connect \$25 $not$libresoc.v:145237$7143_Y
- connect \$27 $or$libresoc.v:145238$7144_Y
- connect \$29 $or$libresoc.v:145239$7145_Y
- connect \$31 $and$libresoc.v:145240$7146_Y
- connect \$33 $not$libresoc.v:145241$7147_Y
- connect \$35 $and$libresoc.v:145242$7148_Y
- connect \$37 $or$libresoc.v:145243$7149_Y
- connect \$3 $and$libresoc.v:145244$7150_Y
- connect \$39 $not$libresoc.v:145245$7151_Y
- connect \$41 $or$libresoc.v:145246$7152_Y
- connect \$43 $or$libresoc.v:145247$7153_Y
- connect \$45 $and$libresoc.v:145248$7154_Y
- connect \$47 $not$libresoc.v:145249$7155_Y
- connect \$49 $and$libresoc.v:145250$7156_Y
- connect \$51 $or$libresoc.v:145251$7157_Y
- connect \$53 $not$libresoc.v:145252$7158_Y
- connect \$55 $or$libresoc.v:145253$7159_Y
- connect \$57 $or$libresoc.v:145254$7160_Y
- connect \$5 $not$libresoc.v:145255$7161_Y
- connect \$59 $and$libresoc.v:145256$7162_Y
- connect \$61 $not$libresoc.v:145257$7163_Y
- connect \$63 $and$libresoc.v:145258$7164_Y
- connect \$65 $or$libresoc.v:145259$7165_Y
- connect \$67 $and$libresoc.v:145260$7166_Y
- connect \$69 $not$libresoc.v:145261$7167_Y
- connect \$71 $and$libresoc.v:145262$7168_Y
- connect \$73 $or$libresoc.v:145263$7169_Y
- connect \$75 $and$libresoc.v:145264$7170_Y
- connect \$77 $not$libresoc.v:145265$7171_Y
- connect \$7 $and$libresoc.v:145266$7172_Y
- connect \$79 $and$libresoc.v:145267$7173_Y
- connect \$81 $and$libresoc.v:145268$7174_Y
- connect \$83 $not$libresoc.v:145269$7175_Y
- connect \$85 $not$libresoc.v:145270$7176_Y
- connect \$87 $and$libresoc.v:145271$7177_Y
- connect \$89 $not$libresoc.v:145272$7178_Y
- connect \$91 $and$libresoc.v:145273$7179_Y
- connect \$93 $not$libresoc.v:145274$7180_Y
- connect \$95 $or$libresoc.v:145275$7181_Y
+ assign $3\m_badaddr_o$next[44:0]$7173 45'000000000000000000000000000000000000000000000
+ case
+ assign $3\m_badaddr_o$next[44:0]$7173 $1\m_badaddr_o$next[44:0]$7171
+ end
+ sync always
+ update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7170
+ end
+ connect \$9 $or$libresoc.v:143358$7060_Y
+ connect \$11 $not$libresoc.v:143359$7061_Y
+ connect \$13 $or$libresoc.v:143360$7062_Y
+ connect \$15 $or$libresoc.v:143361$7063_Y
+ connect \$17 $and$libresoc.v:143362$7064_Y
+ connect \$1 $or$libresoc.v:143363$7065_Y
+ connect \$19 $not$libresoc.v:143364$7066_Y
+ connect \$21 $and$libresoc.v:143365$7067_Y
+ connect \$23 $or$libresoc.v:143366$7068_Y
+ connect \$25 $not$libresoc.v:143367$7069_Y
+ connect \$27 $or$libresoc.v:143368$7070_Y
+ connect \$29 $or$libresoc.v:143369$7071_Y
+ connect \$31 $and$libresoc.v:143370$7072_Y
+ connect \$33 $not$libresoc.v:143371$7073_Y
+ connect \$35 $and$libresoc.v:143372$7074_Y
+ connect \$37 $or$libresoc.v:143373$7075_Y
+ connect \$3 $and$libresoc.v:143374$7076_Y
+ connect \$39 $not$libresoc.v:143375$7077_Y
+ connect \$41 $or$libresoc.v:143376$7078_Y
+ connect \$43 $or$libresoc.v:143377$7079_Y
+ connect \$45 $and$libresoc.v:143378$7080_Y
+ connect \$47 $not$libresoc.v:143379$7081_Y
+ connect \$49 $and$libresoc.v:143380$7082_Y
+ connect \$51 $or$libresoc.v:143381$7083_Y
+ connect \$53 $not$libresoc.v:143382$7084_Y
+ connect \$55 $or$libresoc.v:143383$7085_Y
+ connect \$57 $or$libresoc.v:143384$7086_Y
+ connect \$5 $not$libresoc.v:143385$7087_Y
+ connect \$59 $and$libresoc.v:143386$7088_Y
+ connect \$61 $not$libresoc.v:143387$7089_Y
+ connect \$63 $and$libresoc.v:143388$7090_Y
+ connect \$65 $or$libresoc.v:143389$7091_Y
+ connect \$67 $and$libresoc.v:143390$7092_Y
+ connect \$69 $not$libresoc.v:143391$7093_Y
+ connect \$71 $and$libresoc.v:143392$7094_Y
+ connect \$73 $or$libresoc.v:143393$7095_Y
+ connect \$75 $and$libresoc.v:143394$7096_Y
+ connect \$77 $not$libresoc.v:143395$7097_Y
+ connect \$7 $and$libresoc.v:143396$7098_Y
+ connect \$79 $and$libresoc.v:143397$7099_Y
+ connect \$81 $and$libresoc.v:143398$7100_Y
+ connect \$83 $not$libresoc.v:143399$7101_Y
+ connect \$85 $not$libresoc.v:143400$7102_Y
+ connect \$87 $and$libresoc.v:143401$7103_Y
+ connect \$89 $not$libresoc.v:143402$7104_Y
+ connect \$91 $and$libresoc.v:143403$7105_Y
+ connect \$93 $not$libresoc.v:143404$7106_Y
+ connect \$95 $or$libresoc.v:143405$7107_Y
connect \x_stall_i 1'0
connect \m_stall_i 1'0
end
-attribute \src "libresoc.v:145586.1-146543.10"
+attribute \src "libresoc.v:143716.1-144673.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main"
attribute \generator "nMigen"
module \main
- attribute \src "libresoc.v:146115.3-146137.6"
+ attribute \src "libresoc.v:144245.3-144267.6"
wire width 64 $0\a_i[63:0]
- attribute \src "libresoc.v:146214.3-146240.6"
+ attribute \src "libresoc.v:144344.3-144370.6"
wire $0\a_lt[0:0]
- attribute \src "libresoc.v:146495.3-146505.6"
+ attribute \src "libresoc.v:144625.3-144635.6"
wire width 64 $0\a_n[63:0]
- attribute \src "libresoc.v:146465.3-146474.6"
+ attribute \src "libresoc.v:144595.3-144604.6"
wire width 66 $0\add_a[65:0]
- attribute \src "libresoc.v:146475.3-146484.6"
+ attribute \src "libresoc.v:144605.3-144614.6"
wire width 66 $0\add_b[65:0]
- attribute \src "libresoc.v:146485.3-146494.6"
+ attribute \src "libresoc.v:144615.3-144624.6"
wire width 66 $0\add_o[65:0]
- attribute \src "libresoc.v:146353.3-146375.6"
+ attribute \src "libresoc.v:144483.3-144505.6"
wire width 64 $0\b_i[63:0]
- attribute \src "libresoc.v:146339.3-146352.6"
+ attribute \src "libresoc.v:144469.3-144482.6"
wire width 2 $0\ca[1:0]
- attribute \src "libresoc.v:146506.3-146516.6"
+ attribute \src "libresoc.v:144636.3-144646.6"
wire $0\carry_32[0:0]
- attribute \src "libresoc.v:146517.3-146527.6"
+ attribute \src "libresoc.v:144647.3-144657.6"
wire $0\carry_64[0:0]
- attribute \src "libresoc.v:146241.3-146266.6"
+ attribute \src "libresoc.v:144371.3-144396.6"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:146267.3-146281.6"
+ attribute \src "libresoc.v:144397.3-144411.6"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:146445.3-146464.6"
+ attribute \src "libresoc.v:144575.3-144594.6"
wire width 8 $0\eqs[7:0]
- attribute \src "libresoc.v:145587.7-145587.20"
+ attribute \src "libresoc.v:143717.7-143717.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:146105.3-146114.6"
+ attribute \src "libresoc.v:144235.3-144244.6"
wire $0\is_32bit[0:0]
- attribute \src "libresoc.v:146176.3-146194.6"
+ attribute \src "libresoc.v:144306.3-144324.6"
wire $0\msb_a[0:0]
- attribute \src "libresoc.v:146195.3-146213.6"
+ attribute \src "libresoc.v:144325.3-144343.6"
wire $0\msb_b[0:0]
- attribute \src "libresoc.v:146282.3-146319.6"
+ attribute \src "libresoc.v:144412.3-144449.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:146320.3-146338.6"
+ attribute \src "libresoc.v:144450.3-144468.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:146398.3-146411.6"
+ attribute \src "libresoc.v:144528.3-144541.6"
wire width 2 $0\ov[1:0]
- attribute \src "libresoc.v:146434.3-146444.6"
+ attribute \src "libresoc.v:144564.3-144574.6"
wire width 8 $0\src1[7:0]
- attribute \src "libresoc.v:146149.3-146175.6"
+ attribute \src "libresoc.v:144279.3-144305.6"
wire width 5 $0\tval[4:0]
- attribute \src "libresoc.v:146376.3-146386.6"
- wire width 2 $0\xer_ca$20[1:0]$7334
- attribute \src "libresoc.v:146387.3-146397.6"
+ attribute \src "libresoc.v:144506.3-144516.6"
+ wire width 2 $0\xer_ca$20[1:0]$7260
+ attribute \src "libresoc.v:144517.3-144527.6"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:146412.3-146422.6"
+ attribute \src "libresoc.v:144542.3-144552.6"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:146423.3-146433.6"
+ attribute \src "libresoc.v:144553.3-144563.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:146138.3-146148.6"
+ attribute \src "libresoc.v:144268.3-144278.6"
wire $0\zerohi[0:0]
- attribute \src "libresoc.v:146528.3-146538.6"
+ attribute \src "libresoc.v:144658.3-144668.6"
wire $0\zerolo[0:0]
- attribute \src "libresoc.v:146115.3-146137.6"
+ attribute \src "libresoc.v:144245.3-144267.6"
wire width 64 $1\a_i[63:0]
- attribute \src "libresoc.v:146214.3-146240.6"
+ attribute \src "libresoc.v:144344.3-144370.6"
wire $1\a_lt[0:0]
- attribute \src "libresoc.v:146495.3-146505.6"
+ attribute \src "libresoc.v:144625.3-144635.6"
wire width 64 $1\a_n[63:0]
- attribute \src "libresoc.v:146465.3-146474.6"
+ attribute \src "libresoc.v:144595.3-144604.6"
wire width 66 $1\add_a[65:0]
- attribute \src "libresoc.v:146475.3-146484.6"
+ attribute \src "libresoc.v:144605.3-144614.6"
wire width 66 $1\add_b[65:0]
- attribute \src "libresoc.v:146485.3-146494.6"
+ attribute \src "libresoc.v:144615.3-144624.6"
wire width 66 $1\add_o[65:0]
- attribute \src "libresoc.v:146353.3-146375.6"
+ attribute \src "libresoc.v:144483.3-144505.6"
wire width 64 $1\b_i[63:0]
- attribute \src "libresoc.v:146339.3-146352.6"
+ attribute \src "libresoc.v:144469.3-144482.6"
wire width 2 $1\ca[1:0]
- attribute \src "libresoc.v:146506.3-146516.6"
+ attribute \src "libresoc.v:144636.3-144646.6"
wire $1\carry_32[0:0]
- attribute \src "libresoc.v:146517.3-146527.6"
+ attribute \src "libresoc.v:144647.3-144657.6"
wire $1\carry_64[0:0]
- attribute \src "libresoc.v:146241.3-146266.6"
+ attribute \src "libresoc.v:144371.3-144396.6"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:146267.3-146281.6"
+ attribute \src "libresoc.v:144397.3-144411.6"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:146445.3-146464.6"
+ attribute \src "libresoc.v:144575.3-144594.6"
wire width 8 $1\eqs[7:0]
- attribute \src "libresoc.v:146105.3-146114.6"
+ attribute \src "libresoc.v:144235.3-144244.6"
wire $1\is_32bit[0:0]
- attribute \src "libresoc.v:146176.3-146194.6"
+ attribute \src "libresoc.v:144306.3-144324.6"
wire $1\msb_a[0:0]
- attribute \src "libresoc.v:146195.3-146213.6"
+ attribute \src "libresoc.v:144325.3-144343.6"
wire $1\msb_b[0:0]
- attribute \src "libresoc.v:146282.3-146319.6"
+ attribute \src "libresoc.v:144412.3-144449.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:146320.3-146338.6"
+ attribute \src "libresoc.v:144450.3-144468.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:146398.3-146411.6"
+ attribute \src "libresoc.v:144528.3-144541.6"
wire width 2 $1\ov[1:0]
- attribute \src "libresoc.v:146434.3-146444.6"
+ attribute \src "libresoc.v:144564.3-144574.6"
wire width 8 $1\src1[7:0]
- attribute \src "libresoc.v:146149.3-146175.6"
+ attribute \src "libresoc.v:144279.3-144305.6"
wire width 5 $1\tval[4:0]
- attribute \src "libresoc.v:146376.3-146386.6"
- wire width 2 $1\xer_ca$20[1:0]$7335
- attribute \src "libresoc.v:146387.3-146397.6"
+ attribute \src "libresoc.v:144506.3-144516.6"
+ wire width 2 $1\xer_ca$20[1:0]$7261
+ attribute \src "libresoc.v:144517.3-144527.6"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:146412.3-146422.6"
+ attribute \src "libresoc.v:144542.3-144552.6"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:146423.3-146433.6"
+ attribute \src "libresoc.v:144553.3-144563.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:146138.3-146148.6"
+ attribute \src "libresoc.v:144268.3-144278.6"
wire $1\zerohi[0:0]
- attribute \src "libresoc.v:146528.3-146538.6"
+ attribute \src "libresoc.v:144658.3-144668.6"
wire $1\zerolo[0:0]
- attribute \src "libresoc.v:146115.3-146137.6"
+ attribute \src "libresoc.v:144245.3-144267.6"
wire width 64 $2\a_i[63:0]
- attribute \src "libresoc.v:146214.3-146240.6"
+ attribute \src "libresoc.v:144344.3-144370.6"
wire $2\a_lt[0:0]
- attribute \src "libresoc.v:146353.3-146375.6"
+ attribute \src "libresoc.v:144483.3-144505.6"
wire width 64 $2\b_i[63:0]
- attribute \src "libresoc.v:146241.3-146266.6"
+ attribute \src "libresoc.v:144371.3-144396.6"
wire width 2 $2\cr_a[3:2]
- attribute \src "libresoc.v:146176.3-146194.6"
+ attribute \src "libresoc.v:144306.3-144324.6"
wire $2\msb_a[0:0]
- attribute \src "libresoc.v:146195.3-146213.6"
+ attribute \src "libresoc.v:144325.3-144343.6"
wire $2\msb_b[0:0]
- attribute \src "libresoc.v:146282.3-146319.6"
+ attribute \src "libresoc.v:144412.3-144449.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:146149.3-146175.6"
+ attribute \src "libresoc.v:144279.3-144305.6"
wire width 5 $2\tval[4:0]
- attribute \src "libresoc.v:146214.3-146240.6"
+ attribute \src "libresoc.v:144344.3-144370.6"
wire $3\a_lt[0:0]
- attribute \src "libresoc.v:146282.3-146319.6"
+ attribute \src "libresoc.v:144412.3-144449.6"
wire width 64 $3\o[63:0]
- attribute \src "libresoc.v:146149.3-146175.6"
+ attribute \src "libresoc.v:144279.3-144305.6"
wire width 5 $3\tval[4:0]
- attribute \src "libresoc.v:146282.3-146319.6"
+ attribute \src "libresoc.v:144412.3-144449.6"
wire width 64 $4\o[63:0]
- attribute \src "libresoc.v:146080.18-146080.105"
- wire width 67 $add$libresoc.v:146080$7295_Y
- attribute \src "libresoc.v:146054.19-146054.107"
- wire $and$libresoc.v:146054$7269_Y
- attribute \src "libresoc.v:146058.19-146058.107"
- wire $and$libresoc.v:146058$7273_Y
- attribute \src "libresoc.v:146091.18-146091.106"
- wire $and$libresoc.v:146091$7306_Y
- attribute \src "libresoc.v:146096.18-146096.106"
- wire $and$libresoc.v:146096$7311_Y
- attribute \src "libresoc.v:146099.18-146099.106"
- wire $and$libresoc.v:146099$7314_Y
- attribute \src "libresoc.v:146102.18-146102.106"
- wire $and$libresoc.v:146102$7317_Y
- attribute \src "libresoc.v:146045.19-146045.118"
- wire $eq$libresoc.v:146045$7260_Y
- attribute \src "libresoc.v:146046.19-146046.118"
- wire $eq$libresoc.v:146046$7261_Y
- attribute \src "libresoc.v:146047.19-146047.118"
- wire $eq$libresoc.v:146047$7262_Y
- attribute \src "libresoc.v:146059.19-146059.109"
- wire $eq$libresoc.v:146059$7274_Y
- attribute \src "libresoc.v:146060.19-146060.110"
- wire $eq$libresoc.v:146060$7275_Y
- attribute \src "libresoc.v:146061.19-146061.111"
- wire $eq$libresoc.v:146061$7276_Y
- attribute \src "libresoc.v:146062.19-146062.111"
- wire $eq$libresoc.v:146062$7277_Y
- attribute \src "libresoc.v:146063.19-146063.111"
- wire $eq$libresoc.v:146063$7278_Y
- attribute \src "libresoc.v:146064.19-146064.111"
- wire $eq$libresoc.v:146064$7279_Y
- attribute \src "libresoc.v:146065.19-146065.111"
- wire $eq$libresoc.v:146065$7280_Y
- attribute \src "libresoc.v:146066.19-146066.111"
- wire $eq$libresoc.v:146066$7281_Y
- attribute \src "libresoc.v:146067.18-146067.118"
- wire $eq$libresoc.v:146067$7282_Y
- attribute \src "libresoc.v:146069.18-146069.118"
- wire $eq$libresoc.v:146069$7284_Y
- attribute \src "libresoc.v:146070.18-146070.118"
- wire $eq$libresoc.v:146070$7285_Y
- attribute \src "libresoc.v:146071.18-146071.118"
- wire $eq$libresoc.v:146071$7286_Y
- attribute \src "libresoc.v:146072.18-146072.118"
- wire $eq$libresoc.v:146072$7287_Y
- attribute \src "libresoc.v:146074.18-146074.118"
- wire $eq$libresoc.v:146074$7289_Y
- attribute \src "libresoc.v:146075.18-146075.118"
- wire $eq$libresoc.v:146075$7290_Y
- attribute \src "libresoc.v:146077.18-146077.118"
- wire $eq$libresoc.v:146077$7292_Y
- attribute \src "libresoc.v:146078.18-146078.118"
- wire $eq$libresoc.v:146078$7293_Y
- attribute \src "libresoc.v:146092.18-146092.107"
- wire $ne$libresoc.v:146092$7307_Y
- attribute \src "libresoc.v:146103.18-146103.107"
- wire $ne$libresoc.v:146103$7318_Y
- attribute \src "libresoc.v:146053.19-146053.100"
- wire $not$libresoc.v:146053$7268_Y
- attribute \src "libresoc.v:146057.19-146057.100"
- wire $not$libresoc.v:146057$7272_Y
- attribute \src "libresoc.v:146068.18-146068.110"
- wire $not$libresoc.v:146068$7283_Y
- attribute \src "libresoc.v:146081.18-146081.97"
- wire width 64 $not$libresoc.v:146081$7296_Y
- attribute \src "libresoc.v:146086.18-146086.99"
- wire $not$libresoc.v:146086$7301_Y
- attribute \src "libresoc.v:146089.18-146089.99"
- wire $not$libresoc.v:146089$7304_Y
- attribute \src "libresoc.v:146093.18-146093.99"
- wire $not$libresoc.v:146093$7308_Y
- attribute \src "libresoc.v:146094.18-146094.99"
- wire $not$libresoc.v:146094$7309_Y
- attribute \src "libresoc.v:146073.18-146073.104"
- wire $or$libresoc.v:146073$7288_Y
- attribute \src "libresoc.v:146076.18-146076.104"
- wire $or$libresoc.v:146076$7291_Y
- attribute \src "libresoc.v:146079.18-146079.104"
- wire $or$libresoc.v:146079$7294_Y
- attribute \src "libresoc.v:146090.18-146090.110"
- wire $or$libresoc.v:146090$7305_Y
- attribute \src "libresoc.v:146095.18-146095.110"
- wire $or$libresoc.v:146095$7310_Y
- attribute \src "libresoc.v:146098.18-146098.110"
- wire $or$libresoc.v:146098$7313_Y
- attribute \src "libresoc.v:146101.18-146101.110"
- wire $or$libresoc.v:146101$7316_Y
- attribute \src "libresoc.v:146044.18-146044.98"
- wire $reduce_or$libresoc.v:146044$7259_Y
- attribute \src "libresoc.v:146048.19-146048.99"
- wire $reduce_or$libresoc.v:146048$7263_Y
- attribute \src "libresoc.v:146085.18-146085.99"
- wire $reduce_or$libresoc.v:146085$7300_Y
- attribute \src "libresoc.v:146088.18-146088.99"
- wire $reduce_or$libresoc.v:146088$7303_Y
- attribute \src "libresoc.v:146097.18-146097.121"
- wire $ternary$libresoc.v:146097$7312_Y
- attribute \src "libresoc.v:146100.18-146100.119"
- wire $ternary$libresoc.v:146100$7315_Y
- attribute \src "libresoc.v:146104.18-146104.123"
- wire $ternary$libresoc.v:146104$7319_Y
- attribute \src "libresoc.v:146049.19-146049.111"
- wire $xor$libresoc.v:146049$7264_Y
- attribute \src "libresoc.v:146050.19-146050.111"
- wire $xor$libresoc.v:146050$7265_Y
- attribute \src "libresoc.v:146051.19-146051.110"
- wire $xor$libresoc.v:146051$7266_Y
- attribute \src "libresoc.v:146052.19-146052.110"
- wire $xor$libresoc.v:146052$7267_Y
- attribute \src "libresoc.v:146055.19-146055.110"
- wire $xor$libresoc.v:146055$7270_Y
- attribute \src "libresoc.v:146056.19-146056.110"
- wire $xor$libresoc.v:146056$7271_Y
- attribute \src "libresoc.v:146082.18-146082.111"
- wire $xor$libresoc.v:146082$7297_Y
- attribute \src "libresoc.v:146083.18-146083.107"
- wire $xor$libresoc.v:146083$7298_Y
- attribute \src "libresoc.v:146084.18-146084.113"
- wire width 32 $xor$libresoc.v:146084$7299_Y
- attribute \src "libresoc.v:146087.18-146087.115"
- wire width 32 $xor$libresoc.v:146087$7302_Y
+ attribute \src "libresoc.v:144210.18-144210.105"
+ wire width 67 $add$libresoc.v:144210$7221_Y
+ attribute \src "libresoc.v:144184.19-144184.107"
+ wire $and$libresoc.v:144184$7195_Y
+ attribute \src "libresoc.v:144188.19-144188.107"
+ wire $and$libresoc.v:144188$7199_Y
+ attribute \src "libresoc.v:144221.18-144221.106"
+ wire $and$libresoc.v:144221$7232_Y
+ attribute \src "libresoc.v:144226.18-144226.106"
+ wire $and$libresoc.v:144226$7237_Y
+ attribute \src "libresoc.v:144229.18-144229.106"
+ wire $and$libresoc.v:144229$7240_Y
+ attribute \src "libresoc.v:144232.18-144232.106"
+ wire $and$libresoc.v:144232$7243_Y
+ attribute \src "libresoc.v:144175.19-144175.118"
+ wire $eq$libresoc.v:144175$7186_Y
+ attribute \src "libresoc.v:144176.19-144176.118"
+ wire $eq$libresoc.v:144176$7187_Y
+ attribute \src "libresoc.v:144177.19-144177.118"
+ wire $eq$libresoc.v:144177$7188_Y
+ attribute \src "libresoc.v:144189.19-144189.109"
+ wire $eq$libresoc.v:144189$7200_Y
+ attribute \src "libresoc.v:144190.19-144190.110"
+ wire $eq$libresoc.v:144190$7201_Y
+ attribute \src "libresoc.v:144191.19-144191.111"
+ wire $eq$libresoc.v:144191$7202_Y
+ attribute \src "libresoc.v:144192.19-144192.111"
+ wire $eq$libresoc.v:144192$7203_Y
+ attribute \src "libresoc.v:144193.19-144193.111"
+ wire $eq$libresoc.v:144193$7204_Y
+ attribute \src "libresoc.v:144194.19-144194.111"
+ wire $eq$libresoc.v:144194$7205_Y
+ attribute \src "libresoc.v:144195.19-144195.111"
+ wire $eq$libresoc.v:144195$7206_Y
+ attribute \src "libresoc.v:144196.19-144196.111"
+ wire $eq$libresoc.v:144196$7207_Y
+ attribute \src "libresoc.v:144197.18-144197.118"
+ wire $eq$libresoc.v:144197$7208_Y
+ attribute \src "libresoc.v:144199.18-144199.118"
+ wire $eq$libresoc.v:144199$7210_Y
+ attribute \src "libresoc.v:144200.18-144200.118"
+ wire $eq$libresoc.v:144200$7211_Y
+ attribute \src "libresoc.v:144201.18-144201.118"
+ wire $eq$libresoc.v:144201$7212_Y
+ attribute \src "libresoc.v:144202.18-144202.118"
+ wire $eq$libresoc.v:144202$7213_Y
+ attribute \src "libresoc.v:144204.18-144204.118"
+ wire $eq$libresoc.v:144204$7215_Y
+ attribute \src "libresoc.v:144205.18-144205.118"
+ wire $eq$libresoc.v:144205$7216_Y
+ attribute \src "libresoc.v:144207.18-144207.118"
+ wire $eq$libresoc.v:144207$7218_Y
+ attribute \src "libresoc.v:144208.18-144208.118"
+ wire $eq$libresoc.v:144208$7219_Y
+ attribute \src "libresoc.v:144222.18-144222.107"
+ wire $ne$libresoc.v:144222$7233_Y
+ attribute \src "libresoc.v:144233.18-144233.107"
+ wire $ne$libresoc.v:144233$7244_Y
+ attribute \src "libresoc.v:144183.19-144183.100"
+ wire $not$libresoc.v:144183$7194_Y
+ attribute \src "libresoc.v:144187.19-144187.100"
+ wire $not$libresoc.v:144187$7198_Y
+ attribute \src "libresoc.v:144198.18-144198.110"
+ wire $not$libresoc.v:144198$7209_Y
+ attribute \src "libresoc.v:144211.18-144211.97"
+ wire width 64 $not$libresoc.v:144211$7222_Y
+ attribute \src "libresoc.v:144216.18-144216.99"
+ wire $not$libresoc.v:144216$7227_Y
+ attribute \src "libresoc.v:144219.18-144219.99"
+ wire $not$libresoc.v:144219$7230_Y
+ attribute \src "libresoc.v:144223.18-144223.99"
+ wire $not$libresoc.v:144223$7234_Y
+ attribute \src "libresoc.v:144224.18-144224.99"
+ wire $not$libresoc.v:144224$7235_Y
+ attribute \src "libresoc.v:144203.18-144203.104"
+ wire $or$libresoc.v:144203$7214_Y
+ attribute \src "libresoc.v:144206.18-144206.104"
+ wire $or$libresoc.v:144206$7217_Y
+ attribute \src "libresoc.v:144209.18-144209.104"
+ wire $or$libresoc.v:144209$7220_Y
+ attribute \src "libresoc.v:144220.18-144220.110"
+ wire $or$libresoc.v:144220$7231_Y
+ attribute \src "libresoc.v:144225.18-144225.110"
+ wire $or$libresoc.v:144225$7236_Y
+ attribute \src "libresoc.v:144228.18-144228.110"
+ wire $or$libresoc.v:144228$7239_Y
+ attribute \src "libresoc.v:144231.18-144231.110"
+ wire $or$libresoc.v:144231$7242_Y
+ attribute \src "libresoc.v:144174.18-144174.98"
+ wire $reduce_or$libresoc.v:144174$7185_Y
+ attribute \src "libresoc.v:144178.19-144178.99"
+ wire $reduce_or$libresoc.v:144178$7189_Y
+ attribute \src "libresoc.v:144215.18-144215.99"
+ wire $reduce_or$libresoc.v:144215$7226_Y
+ attribute \src "libresoc.v:144218.18-144218.99"
+ wire $reduce_or$libresoc.v:144218$7229_Y
+ attribute \src "libresoc.v:144227.18-144227.121"
+ wire $ternary$libresoc.v:144227$7238_Y
+ attribute \src "libresoc.v:144230.18-144230.119"
+ wire $ternary$libresoc.v:144230$7241_Y
+ attribute \src "libresoc.v:144234.18-144234.123"
+ wire $ternary$libresoc.v:144234$7245_Y
+ attribute \src "libresoc.v:144179.19-144179.111"
+ wire $xor$libresoc.v:144179$7190_Y
+ attribute \src "libresoc.v:144180.19-144180.111"
+ wire $xor$libresoc.v:144180$7191_Y
+ attribute \src "libresoc.v:144181.19-144181.110"
+ wire $xor$libresoc.v:144181$7192_Y
+ attribute \src "libresoc.v:144182.19-144182.110"
+ wire $xor$libresoc.v:144182$7193_Y
+ attribute \src "libresoc.v:144185.19-144185.110"
+ wire $xor$libresoc.v:144185$7196_Y
+ attribute \src "libresoc.v:144186.19-144186.110"
+ wire $xor$libresoc.v:144186$7197_Y
+ attribute \src "libresoc.v:144212.18-144212.111"
+ wire $xor$libresoc.v:144212$7223_Y
+ attribute \src "libresoc.v:144213.18-144213.107"
+ wire $xor$libresoc.v:144213$7224_Y
+ attribute \src "libresoc.v:144214.18-144214.113"
+ wire width 32 $xor$libresoc.v:144214$7225_Y
+ attribute \src "libresoc.v:144217.18-144217.115"
+ wire width 32 $xor$libresoc.v:144217$7228_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168"
wire output 45 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178"
wire width 8 \eqs
- attribute \src "libresoc.v:145587.7-145587.15"
+ attribute \src "libresoc.v:143717.7-143717.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
wire \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
wire \zerolo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86"
- cell $add $add$libresoc.v:146080$7295
+ cell $add $add$libresoc.v:144210$7221
parameter \A_SIGNED 0
parameter \A_WIDTH 66
parameter \B_SIGNED 0
parameter \Y_WIDTH 67
connect \A \add_a
connect \B \add_b
- connect \Y $add$libresoc.v:146080$7295_Y
+ connect \Y $add$libresoc.v:144210$7221_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $and $and$libresoc.v:146054$7269
+ cell $and $and$libresoc.v:144184$7195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$113
connect \B \$115
- connect \Y $and$libresoc.v:146054$7269_Y
+ connect \Y $and$libresoc.v:144184$7195_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $and $and$libresoc.v:146058$7273
+ cell $and $and$libresoc.v:144188$7199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$121
connect \B \$123
- connect \Y $and$libresoc.v:146058$7273_Y
+ connect \Y $and$libresoc.v:144188$7199_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:146091$7306
+ cell $and $and$libresoc.v:144221$7232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$69
- connect \Y $and$libresoc.v:146091$7306_Y
+ connect \Y $and$libresoc.v:144221$7232_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:146096$7311
+ cell $and $and$libresoc.v:144226$7237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$79
- connect \Y $and$libresoc.v:146096$7311_Y
+ connect \Y $and$libresoc.v:144226$7237_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:146099$7314
+ cell $and $and$libresoc.v:144229$7240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$85
- connect \Y $and$libresoc.v:146099$7314_Y
+ connect \Y $and$libresoc.v:144229$7240_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $and $and$libresoc.v:146102$7317
+ cell $and $and$libresoc.v:144232$7243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \zerolo
connect \B \$91
- connect \Y $and$libresoc.v:146102$7317_Y
+ connect \Y $and$libresoc.v:144232$7243_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166"
- cell $eq $eq$libresoc.v:146045$7260
+ cell $eq $eq$libresoc.v:144175$7186
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 1'1
- connect \Y $eq$libresoc.v:146045$7260_Y
+ connect \Y $eq$libresoc.v:144175$7186_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168"
- cell $eq $eq$libresoc.v:146046$7261
+ cell $eq $eq$libresoc.v:144176$7187
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 2'10
- connect \Y $eq$libresoc.v:146046$7261_Y
+ connect \Y $eq$libresoc.v:144176$7187_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170"
- cell $eq $eq$libresoc.v:146047$7262
+ cell $eq $eq$libresoc.v:144177$7188
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__data_len
connect \B 3'100
- connect \Y $eq$libresoc.v:146047$7262_Y
+ connect \Y $eq$libresoc.v:144177$7188_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146059$7274
+ cell $eq $eq$libresoc.v:144189$7200
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:146059$7274_Y
+ connect \Y $eq$libresoc.v:144189$7200_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146060$7275
+ cell $eq $eq$libresoc.v:144190$7201
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:146060$7275_Y
+ connect \Y $eq$libresoc.v:144190$7201_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146061$7276
+ cell $eq $eq$libresoc.v:144191$7202
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:146061$7276_Y
+ connect \Y $eq$libresoc.v:144191$7202_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146062$7277
+ cell $eq $eq$libresoc.v:144192$7203
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:146062$7277_Y
+ connect \Y $eq$libresoc.v:144192$7203_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146063$7278
+ cell $eq $eq$libresoc.v:144193$7204
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:146063$7278_Y
+ connect \Y $eq$libresoc.v:144193$7204_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146064$7279
+ cell $eq $eq$libresoc.v:144194$7205
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:146064$7279_Y
+ connect \Y $eq$libresoc.v:144194$7205_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146065$7280
+ cell $eq $eq$libresoc.v:144195$7206
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:146065$7280_Y
+ connect \Y $eq$libresoc.v:144195$7206_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182"
- cell $eq $eq$libresoc.v:146066$7281
+ cell $eq $eq$libresoc.v:144196$7207
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:146066$7281_Y
+ connect \Y $eq$libresoc.v:144196$7207_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56"
- cell $eq $eq$libresoc.v:146067$7282
+ cell $eq $eq$libresoc.v:144197$7208
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146067$7282_Y
+ connect \Y $eq$libresoc.v:144197$7208_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67"
- cell $eq $eq$libresoc.v:146069$7284
+ cell $eq $eq$libresoc.v:144199$7210
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146069$7284_Y
+ connect \Y $eq$libresoc.v:144199$7210_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67"
- cell $eq $eq$libresoc.v:146070$7285
+ cell $eq $eq$libresoc.v:144200$7211
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146070$7285_Y
+ connect \Y $eq$libresoc.v:144200$7211_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:146071$7286
+ cell $eq $eq$libresoc.v:144201$7212
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:146071$7286_Y
+ connect \Y $eq$libresoc.v:144201$7212_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:146072$7287
+ cell $eq $eq$libresoc.v:144202$7213
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146072$7287_Y
+ connect \Y $eq$libresoc.v:144202$7213_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:146074$7289
+ cell $eq $eq$libresoc.v:144204$7215
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:146074$7289_Y
+ connect \Y $eq$libresoc.v:144204$7215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:146075$7290
+ cell $eq $eq$libresoc.v:144205$7216
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146075$7290_Y
+ connect \Y $eq$libresoc.v:144205$7216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81"
- cell $eq $eq$libresoc.v:146077$7292
+ cell $eq $eq$libresoc.v:144207$7218
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0000010
- connect \Y $eq$libresoc.v:146077$7292_Y
+ connect \Y $eq$libresoc.v:144207$7218_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $eq $eq$libresoc.v:146078$7293
+ cell $eq $eq$libresoc.v:144208$7219
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:146078$7293_Y
+ connect \Y $eq$libresoc.v:144208$7219_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123"
- cell $ne $ne$libresoc.v:146092$7307
+ cell $ne $ne$libresoc.v:144222$7233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msb_a
connect \B \msb_b
- connect \Y $ne$libresoc.v:146092$7307_Y
+ connect \Y $ne$libresoc.v:144222$7233_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123"
- cell $ne $ne$libresoc.v:146103$7318
+ cell $ne $ne$libresoc.v:144233$7244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msb_a
connect \B \msb_b
- connect \Y $ne$libresoc.v:146103$7318_Y
+ connect \Y $ne$libresoc.v:144233$7244_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $not $not$libresoc.v:146053$7268
+ cell $not $not$libresoc.v:144183$7194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$116
- connect \Y $not$libresoc.v:146053$7268_Y
+ connect \Y $not$libresoc.v:144183$7194_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $not $not$libresoc.v:146057$7272
+ cell $not $not$libresoc.v:144187$7198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$124
- connect \Y $not$libresoc.v:146057$7272_Y
+ connect \Y $not$libresoc.v:144187$7198_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57"
- cell $not $not$libresoc.v:146068$7283
+ cell $not $not$libresoc.v:144198$7209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_op__insn [21]
- connect \Y $not$libresoc.v:146068$7283_Y
+ connect \Y $not$libresoc.v:144198$7209_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
- cell $not $not$libresoc.v:146081$7296
+ cell $not $not$libresoc.v:144211$7222
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $not$libresoc.v:146081$7296_Y
+ connect \Y $not$libresoc.v:144211$7222_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $not $not$libresoc.v:146086$7301
+ cell $not $not$libresoc.v:144216$7227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$58
- connect \Y $not$libresoc.v:146086$7301_Y
+ connect \Y $not$libresoc.v:144216$7227_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $not $not$libresoc.v:146089$7304
+ cell $not $not$libresoc.v:144219$7230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$64
- connect \Y $not$libresoc.v:146089$7304_Y
+ connect \Y $not$libresoc.v:144219$7230_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132"
- cell $not $not$libresoc.v:146093$7308
+ cell $not $not$libresoc.v:144223$7234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_lt
- connect \Y $not$libresoc.v:146093$7308_Y
+ connect \Y $not$libresoc.v:144223$7234_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132"
- cell $not $not$libresoc.v:146094$7309
+ cell $not $not$libresoc.v:144224$7235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_lt
- connect \Y $not$libresoc.v:146094$7309_Y
+ connect \Y $not$libresoc.v:144224$7235_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:146073$7288
+ cell $or $or$libresoc.v:144203$7214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$30
connect \B \$32
- connect \Y $or$libresoc.v:146073$7288_Y
+ connect \Y $or$libresoc.v:144203$7214_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:146076$7291
+ cell $or $or$libresoc.v:144206$7217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \$38
- connect \Y $or$libresoc.v:146076$7291_Y
+ connect \Y $or$libresoc.v:144206$7217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
- cell $or $or$libresoc.v:146079$7294
+ cell $or $or$libresoc.v:144209$7220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B \$44
- connect \Y $or$libresoc.v:146079$7294_Y
+ connect \Y $or$libresoc.v:144209$7220_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:146090$7305
+ cell $or $or$libresoc.v:144220$7231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:146090$7305_Y
+ connect \Y $or$libresoc.v:144220$7231_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:146095$7310
+ cell $or $or$libresoc.v:144225$7236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:146095$7310_Y
+ connect \Y $or$libresoc.v:144225$7236_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:146098$7313
+ cell $or $or$libresoc.v:144228$7239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:146098$7313_Y
+ connect \Y $or$libresoc.v:144228$7239_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116"
- cell $or $or$libresoc.v:146101$7316
+ cell $or $or$libresoc.v:144231$7242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_32bit
connect \B \zerohi
- connect \Y $or$libresoc.v:146101$7316_Y
+ connect \Y $or$libresoc.v:144231$7242_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185"
- cell $reduce_or $reduce_or$libresoc.v:146044$7259
+ cell $reduce_or $reduce_or$libresoc.v:144174$7185
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
- connect \Y $reduce_or$libresoc.v:146044$7259_Y
+ connect \Y $reduce_or$libresoc.v:144174$7185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183"
- cell $reduce_or $reduce_or$libresoc.v:146048$7263
+ cell $reduce_or $reduce_or$libresoc.v:144178$7189
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
- connect \Y $reduce_or$libresoc.v:146048$7263_Y
+ connect \Y $reduce_or$libresoc.v:144178$7189_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $reduce_or $reduce_or$libresoc.v:146085$7300
+ cell $reduce_or $reduce_or$libresoc.v:144215$7226
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 1
connect \A \$59
- connect \Y $reduce_or$libresoc.v:146085$7300_Y
+ connect \Y $reduce_or$libresoc.v:144215$7226_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $reduce_or $reduce_or$libresoc.v:146088$7303
+ cell $reduce_or $reduce_or$libresoc.v:144218$7229
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 1
connect \A \$65
- connect \Y $reduce_or$libresoc.v:146088$7303_Y
+ connect \Y $reduce_or$libresoc.v:144218$7229_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120"
- cell $mux $ternary$libresoc.v:146097$7312
+ cell $mux $ternary$libresoc.v:144227$7238
parameter \WIDTH 1
connect \A \a_n [63]
connect \B \a_n [31]
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:146097$7312_Y
+ connect \Y $ternary$libresoc.v:144227$7238_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121"
- cell $mux $ternary$libresoc.v:146100$7315
+ cell $mux $ternary$libresoc.v:144230$7241
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:146100$7315_Y
+ connect \Y $ternary$libresoc.v:144230$7241_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131"
- cell $mux $ternary$libresoc.v:146104$7319
+ cell $mux $ternary$libresoc.v:144234$7245
parameter \WIDTH 1
connect \A \carry_64
connect \B \carry_32
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:146104$7319_Y
+ connect \Y $ternary$libresoc.v:144234$7245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152"
- cell $xor $xor$libresoc.v:146049$7264
+ cell $xor $xor$libresoc.v:144179$7190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [32]
connect \B \b_i [32]
- connect \Y $xor$libresoc.v:146049$7264_Y
+ connect \Y $xor$libresoc.v:144179$7190_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152"
- cell $xor $xor$libresoc.v:146050$7265
+ cell $xor $xor$libresoc.v:144180$7191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \add_o [33]
connect \B \$109
- connect \Y $xor$libresoc.v:146050$7265_Y
+ connect \Y $xor$libresoc.v:144180$7191_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:146051$7266
+ cell $xor $xor$libresoc.v:144181$7192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [0]
connect \B \add_o [64]
- connect \Y $xor$libresoc.v:146051$7266_Y
+ connect \Y $xor$libresoc.v:144181$7192_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:146052$7267
+ cell $xor $xor$libresoc.v:144182$7193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [63]
connect \B \b_i [63]
- connect \Y $xor$libresoc.v:146052$7267_Y
+ connect \Y $xor$libresoc.v:144182$7193_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:146055$7270
+ cell $xor $xor$libresoc.v:144185$7196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [1]
connect \B \add_o [32]
- connect \Y $xor$libresoc.v:146055$7270_Y
+ connect \Y $xor$libresoc.v:144185$7196_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25"
- cell $xor $xor$libresoc.v:146056$7271
+ cell $xor $xor$libresoc.v:144186$7197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_i [31]
connect \B \b_i [31]
- connect \Y $xor$libresoc.v:146056$7271_Y
+ connect \Y $xor$libresoc.v:144186$7197_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110"
- cell $xor $xor$libresoc.v:146082$7297
+ cell $xor $xor$libresoc.v:144212$7223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \add_o [33]
connect \B \ra [32]
- connect \Y $xor$libresoc.v:146082$7297_Y
+ connect \Y $xor$libresoc.v:144212$7223_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110"
- cell $xor $xor$libresoc.v:146083$7298
+ cell $xor $xor$libresoc.v:144213$7224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \rb [32]
- connect \Y $xor$libresoc.v:146083$7298_Y
+ connect \Y $xor$libresoc.v:144213$7224_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113"
- cell $xor $xor$libresoc.v:146084$7299
+ cell $xor $xor$libresoc.v:144214$7225
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \a_n [31:0]
connect \B \rb [31:0]
- connect \Y $xor$libresoc.v:146084$7299_Y
+ connect \Y $xor$libresoc.v:144214$7225_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
- cell $xor $xor$libresoc.v:146087$7302
+ cell $xor $xor$libresoc.v:144217$7228
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \a_n [63:32]
connect \B \rb [63:32]
- connect \Y $xor$libresoc.v:146087$7302_Y
+ connect \Y $xor$libresoc.v:144217$7228_Y
end
- attribute \src "libresoc.v:145587.7-145587.20"
- process $proc$libresoc.v:145587$7349
+ attribute \src "libresoc.v:143717.7-143717.20"
+ process $proc$libresoc.v:143717$7275
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:146105.3-146114.6"
- process $proc$libresoc.v:146105$7320
+ attribute \src "libresoc.v:144235.3-144244.6"
+ process $proc$libresoc.v:144235$7246
assign { } { }
assign { } { }
assign $0\is_32bit[0:0] $1\is_32bit[0:0]
- attribute \src "libresoc.v:146106.5-146106.29"
+ attribute \src "libresoc.v:144236.5-144236.29"
switch \initial
- attribute \src "libresoc.v:146106.9-146106.17"
+ attribute \src "libresoc.v:144236.9-144236.17"
case 1'1
case
end
sync always
update \is_32bit $0\is_32bit[0:0]
end
- attribute \src "libresoc.v:146115.3-146137.6"
- process $proc$libresoc.v:146115$7321
+ attribute \src "libresoc.v:144245.3-144267.6"
+ process $proc$libresoc.v:144245$7247
assign { } { }
assign $0\a_i[63:0] $1\a_i[63:0]
- attribute \src "libresoc.v:146116.5-146116.29"
+ attribute \src "libresoc.v:144246.5-144246.29"
switch \initial
- attribute \src "libresoc.v:146116.9-146116.17"
+ attribute \src "libresoc.v:144246.9-144246.17"
case 1'1
case
end
sync always
update \a_i $0\a_i[63:0]
end
- attribute \src "libresoc.v:146138.3-146148.6"
- process $proc$libresoc.v:146138$7322
+ attribute \src "libresoc.v:144268.3-144278.6"
+ process $proc$libresoc.v:144268$7248
assign { } { }
assign { } { }
assign $0\zerohi[0:0] $1\zerohi[0:0]
- attribute \src "libresoc.v:146139.5-146139.29"
+ attribute \src "libresoc.v:144269.5-144269.29"
switch \initial
- attribute \src "libresoc.v:146139.9-146139.17"
+ attribute \src "libresoc.v:144269.9-144269.17"
case 1'1
case
end
sync always
update \zerohi $0\zerohi[0:0]
end
- attribute \src "libresoc.v:146149.3-146175.6"
- process $proc$libresoc.v:146149$7323
+ attribute \src "libresoc.v:144279.3-144305.6"
+ process $proc$libresoc.v:144279$7249
assign { } { }
assign { } { }
assign $0\tval[4:0] $1\tval[4:0]
- attribute \src "libresoc.v:146150.5-146150.29"
+ attribute \src "libresoc.v:144280.5-144280.29"
switch \initial
- attribute \src "libresoc.v:146150.9-146150.17"
+ attribute \src "libresoc.v:144280.9-144280.17"
case 1'1
case
end
sync always
update \tval $0\tval[4:0]
end
- attribute \src "libresoc.v:146176.3-146194.6"
- process $proc$libresoc.v:146176$7324
+ attribute \src "libresoc.v:144306.3-144324.6"
+ process $proc$libresoc.v:144306$7250
assign { } { }
assign { } { }
assign $0\msb_a[0:0] $1\msb_a[0:0]
- attribute \src "libresoc.v:146177.5-146177.29"
+ attribute \src "libresoc.v:144307.5-144307.29"
switch \initial
- attribute \src "libresoc.v:146177.9-146177.17"
+ attribute \src "libresoc.v:144307.9-144307.17"
case 1'1
case
end
sync always
update \msb_a $0\msb_a[0:0]
end
- attribute \src "libresoc.v:146195.3-146213.6"
- process $proc$libresoc.v:146195$7325
+ attribute \src "libresoc.v:144325.3-144343.6"
+ process $proc$libresoc.v:144325$7251
assign { } { }
assign { } { }
assign $0\msb_b[0:0] $1\msb_b[0:0]
- attribute \src "libresoc.v:146196.5-146196.29"
+ attribute \src "libresoc.v:144326.5-144326.29"
switch \initial
- attribute \src "libresoc.v:146196.9-146196.17"
+ attribute \src "libresoc.v:144326.9-144326.17"
case 1'1
case
end
sync always
update \msb_b $0\msb_b[0:0]
end
- attribute \src "libresoc.v:146214.3-146240.6"
- process $proc$libresoc.v:146214$7326
+ attribute \src "libresoc.v:144344.3-144370.6"
+ process $proc$libresoc.v:144344$7252
assign { } { }
assign { } { }
assign $0\a_lt[0:0] $1\a_lt[0:0]
- attribute \src "libresoc.v:146215.5-146215.29"
+ attribute \src "libresoc.v:144345.5-144345.29"
switch \initial
- attribute \src "libresoc.v:146215.9-146215.17"
+ attribute \src "libresoc.v:144345.9-144345.17"
case 1'1
case
end
sync always
update \a_lt $0\a_lt[0:0]
end
- attribute \src "libresoc.v:146241.3-146266.6"
- process $proc$libresoc.v:146241$7327
+ attribute \src "libresoc.v:144371.3-144396.6"
+ process $proc$libresoc.v:144371$7253
assign { } { }
assign { } { }
assign $0\cr_a[3:0] $1\cr_a[3:0]
- attribute \src "libresoc.v:146242.5-146242.29"
+ attribute \src "libresoc.v:144372.5-144372.29"
switch \initial
- attribute \src "libresoc.v:146242.9-146242.17"
+ attribute \src "libresoc.v:144372.9-144372.17"
case 1'1
case
end
sync always
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:146267.3-146281.6"
- process $proc$libresoc.v:146267$7328
+ attribute \src "libresoc.v:144397.3-144411.6"
+ process $proc$libresoc.v:144397$7254
assign { } { }
assign { } { }
assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:146268.5-146268.29"
+ attribute \src "libresoc.v:144398.5-144398.29"
switch \initial
- attribute \src "libresoc.v:146268.9-146268.17"
+ attribute \src "libresoc.v:144398.9-144398.17"
case 1'1
case
end
sync always
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:146282.3-146319.6"
- process $proc$libresoc.v:146282$7329
+ attribute \src "libresoc.v:144412.3-144449.6"
+ process $proc$libresoc.v:144412$7255
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:146283.5-146283.29"
+ attribute \src "libresoc.v:144413.5-144413.29"
switch \initial
- attribute \src "libresoc.v:146283.9-146283.17"
+ attribute \src "libresoc.v:144413.9-144413.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:146320.3-146338.6"
- process $proc$libresoc.v:146320$7330
+ attribute \src "libresoc.v:144450.3-144468.6"
+ process $proc$libresoc.v:144450$7256
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:146321.5-146321.29"
+ attribute \src "libresoc.v:144451.5-144451.29"
switch \initial
- attribute \src "libresoc.v:146321.9-146321.17"
+ attribute \src "libresoc.v:144451.9-144451.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:146339.3-146352.6"
- process $proc$libresoc.v:146339$7331
+ attribute \src "libresoc.v:144469.3-144482.6"
+ process $proc$libresoc.v:144469$7257
assign { } { }
assign { } { }
assign $0\ca[1:0] $1\ca[1:0]
- attribute \src "libresoc.v:146340.5-146340.29"
+ attribute \src "libresoc.v:144470.5-144470.29"
switch \initial
- attribute \src "libresoc.v:146340.9-146340.17"
+ attribute \src "libresoc.v:144470.9-144470.17"
case 1'1
case
end
sync always
update \ca $0\ca[1:0]
end
- attribute \src "libresoc.v:146353.3-146375.6"
- process $proc$libresoc.v:146353$7332
+ attribute \src "libresoc.v:144483.3-144505.6"
+ process $proc$libresoc.v:144483$7258
assign { } { }
assign $0\b_i[63:0] $1\b_i[63:0]
- attribute \src "libresoc.v:146354.5-146354.29"
+ attribute \src "libresoc.v:144484.5-144484.29"
switch \initial
- attribute \src "libresoc.v:146354.9-146354.17"
+ attribute \src "libresoc.v:144484.9-144484.17"
case 1'1
case
end
sync always
update \b_i $0\b_i[63:0]
end
- attribute \src "libresoc.v:146376.3-146386.6"
- process $proc$libresoc.v:146376$7333
+ attribute \src "libresoc.v:144506.3-144516.6"
+ process $proc$libresoc.v:144506$7259
assign { } { }
assign { } { }
- assign $0\xer_ca$20[1:0]$7334 $1\xer_ca$20[1:0]$7335
- attribute \src "libresoc.v:146377.5-146377.29"
+ assign $0\xer_ca$20[1:0]$7260 $1\xer_ca$20[1:0]$7261
+ attribute \src "libresoc.v:144507.5-144507.29"
switch \initial
- attribute \src "libresoc.v:146377.9-146377.17"
+ attribute \src "libresoc.v:144507.9-144507.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0000010
assign { } { }
- assign $1\xer_ca$20[1:0]$7335 \ca
+ assign $1\xer_ca$20[1:0]$7261 \ca
case
- assign $1\xer_ca$20[1:0]$7335 2'00
+ assign $1\xer_ca$20[1:0]$7261 2'00
end
sync always
- update \xer_ca$20 $0\xer_ca$20[1:0]$7334
+ update \xer_ca$20 $0\xer_ca$20[1:0]$7260
end
- attribute \src "libresoc.v:146387.3-146397.6"
- process $proc$libresoc.v:146387$7336
+ attribute \src "libresoc.v:144517.3-144527.6"
+ process $proc$libresoc.v:144517$7262
assign { } { }
assign { } { }
assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:146388.5-146388.29"
+ attribute \src "libresoc.v:144518.5-144518.29"
switch \initial
- attribute \src "libresoc.v:146388.9-146388.17"
+ attribute \src "libresoc.v:144518.9-144518.17"
case 1'1
case
end
sync always
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:146398.3-146411.6"
- process $proc$libresoc.v:146398$7337
+ attribute \src "libresoc.v:144528.3-144541.6"
+ process $proc$libresoc.v:144528$7263
assign { } { }
assign { } { }
assign $0\ov[1:0] $1\ov[1:0]
- attribute \src "libresoc.v:146399.5-146399.29"
+ attribute \src "libresoc.v:144529.5-144529.29"
switch \initial
- attribute \src "libresoc.v:146399.9-146399.17"
+ attribute \src "libresoc.v:144529.9-144529.17"
case 1'1
case
end
sync always
update \ov $0\ov[1:0]
end
- attribute \src "libresoc.v:146412.3-146422.6"
- process $proc$libresoc.v:146412$7338
+ attribute \src "libresoc.v:144542.3-144552.6"
+ process $proc$libresoc.v:144542$7264
assign { } { }
assign { } { }
assign $0\xer_ov[1:0] $1\xer_ov[1:0]
- attribute \src "libresoc.v:146413.5-146413.29"
+ attribute \src "libresoc.v:144543.5-144543.29"
switch \initial
- attribute \src "libresoc.v:146413.9-146413.17"
+ attribute \src "libresoc.v:144543.9-144543.17"
case 1'1
case
end
sync always
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:146423.3-146433.6"
- process $proc$libresoc.v:146423$7339
+ attribute \src "libresoc.v:144553.3-144563.6"
+ process $proc$libresoc.v:144553$7265
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:146424.5-146424.29"
+ attribute \src "libresoc.v:144554.5-144554.29"
switch \initial
- attribute \src "libresoc.v:146424.9-146424.17"
+ attribute \src "libresoc.v:144554.9-144554.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:146434.3-146444.6"
- process $proc$libresoc.v:146434$7340
+ attribute \src "libresoc.v:144564.3-144574.6"
+ process $proc$libresoc.v:144564$7266
assign { } { }
assign { } { }
assign $0\src1[7:0] $1\src1[7:0]
- attribute \src "libresoc.v:146435.5-146435.29"
+ attribute \src "libresoc.v:144565.5-144565.29"
switch \initial
- attribute \src "libresoc.v:146435.9-146435.17"
+ attribute \src "libresoc.v:144565.9-144565.17"
case 1'1
case
end
sync always
update \src1 $0\src1[7:0]
end
- attribute \src "libresoc.v:146445.3-146464.6"
- process $proc$libresoc.v:146445$7341
+ attribute \src "libresoc.v:144575.3-144594.6"
+ process $proc$libresoc.v:144575$7267
assign { } { }
assign { } { }
assign $0\eqs[7:0] $1\eqs[7:0]
- attribute \src "libresoc.v:146446.5-146446.29"
+ attribute \src "libresoc.v:144576.5-144576.29"
switch \initial
- attribute \src "libresoc.v:146446.9-146446.17"
+ attribute \src "libresoc.v:144576.9-144576.17"
case 1'1
case
end
sync always
update \eqs $0\eqs[7:0]
end
- attribute \src "libresoc.v:146465.3-146474.6"
- process $proc$libresoc.v:146465$7342
+ attribute \src "libresoc.v:144595.3-144604.6"
+ process $proc$libresoc.v:144595$7268
assign { } { }
assign { } { }
assign $0\add_a[65:0] $1\add_a[65:0]
- attribute \src "libresoc.v:146466.5-146466.29"
+ attribute \src "libresoc.v:144596.5-144596.29"
switch \initial
- attribute \src "libresoc.v:146466.9-146466.17"
+ attribute \src "libresoc.v:144596.9-144596.17"
case 1'1
case
end
sync always
update \add_a $0\add_a[65:0]
end
- attribute \src "libresoc.v:146475.3-146484.6"
- process $proc$libresoc.v:146475$7343
+ attribute \src "libresoc.v:144605.3-144614.6"
+ process $proc$libresoc.v:144605$7269
assign { } { }
assign { } { }
assign $0\add_b[65:0] $1\add_b[65:0]
- attribute \src "libresoc.v:146476.5-146476.29"
+ attribute \src "libresoc.v:144606.5-144606.29"
switch \initial
- attribute \src "libresoc.v:146476.9-146476.17"
+ attribute \src "libresoc.v:144606.9-144606.17"
case 1'1
case
end
sync always
update \add_b $0\add_b[65:0]
end
- attribute \src "libresoc.v:146485.3-146494.6"
- process $proc$libresoc.v:146485$7344
+ attribute \src "libresoc.v:144615.3-144624.6"
+ process $proc$libresoc.v:144615$7270
assign { } { }
assign { } { }
assign $0\add_o[65:0] $1\add_o[65:0]
- attribute \src "libresoc.v:146486.5-146486.29"
+ attribute \src "libresoc.v:144616.5-144616.29"
switch \initial
- attribute \src "libresoc.v:146486.9-146486.17"
+ attribute \src "libresoc.v:144616.9-144616.17"
case 1'1
case
end
sync always
update \add_o $0\add_o[65:0]
end
- attribute \src "libresoc.v:146495.3-146505.6"
- process $proc$libresoc.v:146495$7345
+ attribute \src "libresoc.v:144625.3-144635.6"
+ process $proc$libresoc.v:144625$7271
assign { } { }
assign { } { }
assign $0\a_n[63:0] $1\a_n[63:0]
- attribute \src "libresoc.v:146496.5-146496.29"
+ attribute \src "libresoc.v:144626.5-144626.29"
switch \initial
- attribute \src "libresoc.v:146496.9-146496.17"
+ attribute \src "libresoc.v:144626.9-144626.17"
case 1'1
case
end
sync always
update \a_n $0\a_n[63:0]
end
- attribute \src "libresoc.v:146506.3-146516.6"
- process $proc$libresoc.v:146506$7346
+ attribute \src "libresoc.v:144636.3-144646.6"
+ process $proc$libresoc.v:144636$7272
assign { } { }
assign { } { }
assign $0\carry_32[0:0] $1\carry_32[0:0]
- attribute \src "libresoc.v:146507.5-146507.29"
+ attribute \src "libresoc.v:144637.5-144637.29"
switch \initial
- attribute \src "libresoc.v:146507.9-146507.17"
+ attribute \src "libresoc.v:144637.9-144637.17"
case 1'1
case
end
sync always
update \carry_32 $0\carry_32[0:0]
end
- attribute \src "libresoc.v:146517.3-146527.6"
- process $proc$libresoc.v:146517$7347
+ attribute \src "libresoc.v:144647.3-144657.6"
+ process $proc$libresoc.v:144647$7273
assign { } { }
assign { } { }
assign $0\carry_64[0:0] $1\carry_64[0:0]
- attribute \src "libresoc.v:146518.5-146518.29"
+ attribute \src "libresoc.v:144648.5-144648.29"
switch \initial
- attribute \src "libresoc.v:146518.9-146518.17"
+ attribute \src "libresoc.v:144648.9-144648.17"
case 1'1
case
end
sync always
update \carry_64 $0\carry_64[0:0]
end
- attribute \src "libresoc.v:146528.3-146538.6"
- process $proc$libresoc.v:146528$7348
+ attribute \src "libresoc.v:144658.3-144668.6"
+ process $proc$libresoc.v:144658$7274
assign { } { }
assign { } { }
assign $0\zerolo[0:0] $1\zerolo[0:0]
- attribute \src "libresoc.v:146529.5-146529.29"
+ attribute \src "libresoc.v:144659.5-144659.29"
switch \initial
- attribute \src "libresoc.v:146529.9-146529.17"
+ attribute \src "libresoc.v:144659.9-144659.17"
case 1'1
case
end
sync always
update \zerolo $0\zerolo[0:0]
end
- connect \$99 $reduce_or$libresoc.v:146044$7259_Y
- connect \$101 $eq$libresoc.v:146045$7260_Y
- connect \$103 $eq$libresoc.v:146046$7261_Y
- connect \$105 $eq$libresoc.v:146047$7262_Y
- connect \$107 $reduce_or$libresoc.v:146048$7263_Y
- connect \$109 $xor$libresoc.v:146049$7264_Y
- connect \$111 $xor$libresoc.v:146050$7265_Y
- connect \$113 $xor$libresoc.v:146051$7266_Y
- connect \$116 $xor$libresoc.v:146052$7267_Y
- connect \$115 $not$libresoc.v:146053$7268_Y
- connect \$119 $and$libresoc.v:146054$7269_Y
- connect \$121 $xor$libresoc.v:146055$7270_Y
- connect \$124 $xor$libresoc.v:146056$7271_Y
- connect \$123 $not$libresoc.v:146057$7272_Y
- connect \$127 $and$libresoc.v:146058$7273_Y
- connect \$129 $eq$libresoc.v:146059$7274_Y
- connect \$131 $eq$libresoc.v:146060$7275_Y
- connect \$133 $eq$libresoc.v:146061$7276_Y
- connect \$135 $eq$libresoc.v:146062$7277_Y
- connect \$137 $eq$libresoc.v:146063$7278_Y
- connect \$139 $eq$libresoc.v:146064$7279_Y
- connect \$141 $eq$libresoc.v:146065$7280_Y
- connect \$143 $eq$libresoc.v:146066$7281_Y
- connect \$22 $eq$libresoc.v:146067$7282_Y
- connect \$24 $not$libresoc.v:146068$7283_Y
- connect \$26 $eq$libresoc.v:146069$7284_Y
- connect \$28 $eq$libresoc.v:146070$7285_Y
- connect \$30 $eq$libresoc.v:146071$7286_Y
- connect \$32 $eq$libresoc.v:146072$7287_Y
- connect \$34 $or$libresoc.v:146073$7288_Y
- connect \$36 $eq$libresoc.v:146074$7289_Y
- connect \$38 $eq$libresoc.v:146075$7290_Y
- connect \$40 $or$libresoc.v:146076$7291_Y
- connect \$42 $eq$libresoc.v:146077$7292_Y
- connect \$44 $eq$libresoc.v:146078$7293_Y
- connect \$46 $or$libresoc.v:146079$7294_Y
- connect \$49 $add$libresoc.v:146080$7295_Y
- connect \$51 $not$libresoc.v:146081$7296_Y
- connect \$53 $xor$libresoc.v:146082$7297_Y
- connect \$55 $xor$libresoc.v:146083$7298_Y
- connect \$59 $xor$libresoc.v:146084$7299_Y
- connect \$58 $reduce_or$libresoc.v:146085$7300_Y
- connect \$57 $not$libresoc.v:146086$7301_Y
- connect \$65 $xor$libresoc.v:146087$7302_Y
- connect \$64 $reduce_or$libresoc.v:146088$7303_Y
- connect \$63 $not$libresoc.v:146089$7304_Y
- connect \$69 $or$libresoc.v:146090$7305_Y
- connect \$71 $and$libresoc.v:146091$7306_Y
- connect \$73 $ne$libresoc.v:146092$7307_Y
- connect \$75 $not$libresoc.v:146093$7308_Y
- connect \$77 $not$libresoc.v:146094$7309_Y
- connect \$79 $or$libresoc.v:146095$7310_Y
- connect \$81 $and$libresoc.v:146096$7311_Y
- connect \$83 $ternary$libresoc.v:146097$7312_Y
- connect \$85 $or$libresoc.v:146098$7313_Y
- connect \$87 $and$libresoc.v:146099$7314_Y
- connect \$89 $ternary$libresoc.v:146100$7315_Y
- connect \$91 $or$libresoc.v:146101$7316_Y
- connect \$93 $and$libresoc.v:146102$7317_Y
- connect \$95 $ne$libresoc.v:146103$7318_Y
- connect \$97 $ternary$libresoc.v:146104$7319_Y
+ connect \$99 $reduce_or$libresoc.v:144174$7185_Y
+ connect \$101 $eq$libresoc.v:144175$7186_Y
+ connect \$103 $eq$libresoc.v:144176$7187_Y
+ connect \$105 $eq$libresoc.v:144177$7188_Y
+ connect \$107 $reduce_or$libresoc.v:144178$7189_Y
+ connect \$109 $xor$libresoc.v:144179$7190_Y
+ connect \$111 $xor$libresoc.v:144180$7191_Y
+ connect \$113 $xor$libresoc.v:144181$7192_Y
+ connect \$116 $xor$libresoc.v:144182$7193_Y
+ connect \$115 $not$libresoc.v:144183$7194_Y
+ connect \$119 $and$libresoc.v:144184$7195_Y
+ connect \$121 $xor$libresoc.v:144185$7196_Y
+ connect \$124 $xor$libresoc.v:144186$7197_Y
+ connect \$123 $not$libresoc.v:144187$7198_Y
+ connect \$127 $and$libresoc.v:144188$7199_Y
+ connect \$129 $eq$libresoc.v:144189$7200_Y
+ connect \$131 $eq$libresoc.v:144190$7201_Y
+ connect \$133 $eq$libresoc.v:144191$7202_Y
+ connect \$135 $eq$libresoc.v:144192$7203_Y
+ connect \$137 $eq$libresoc.v:144193$7204_Y
+ connect \$139 $eq$libresoc.v:144194$7205_Y
+ connect \$141 $eq$libresoc.v:144195$7206_Y
+ connect \$143 $eq$libresoc.v:144196$7207_Y
+ connect \$22 $eq$libresoc.v:144197$7208_Y
+ connect \$24 $not$libresoc.v:144198$7209_Y
+ connect \$26 $eq$libresoc.v:144199$7210_Y
+ connect \$28 $eq$libresoc.v:144200$7211_Y
+ connect \$30 $eq$libresoc.v:144201$7212_Y
+ connect \$32 $eq$libresoc.v:144202$7213_Y
+ connect \$34 $or$libresoc.v:144203$7214_Y
+ connect \$36 $eq$libresoc.v:144204$7215_Y
+ connect \$38 $eq$libresoc.v:144205$7216_Y
+ connect \$40 $or$libresoc.v:144206$7217_Y
+ connect \$42 $eq$libresoc.v:144207$7218_Y
+ connect \$44 $eq$libresoc.v:144208$7219_Y
+ connect \$46 $or$libresoc.v:144209$7220_Y
+ connect \$49 $add$libresoc.v:144210$7221_Y
+ connect \$51 $not$libresoc.v:144211$7222_Y
+ connect \$53 $xor$libresoc.v:144212$7223_Y
+ connect \$55 $xor$libresoc.v:144213$7224_Y
+ connect \$59 $xor$libresoc.v:144214$7225_Y
+ connect \$58 $reduce_or$libresoc.v:144215$7226_Y
+ connect \$57 $not$libresoc.v:144216$7227_Y
+ connect \$65 $xor$libresoc.v:144217$7228_Y
+ connect \$64 $reduce_or$libresoc.v:144218$7229_Y
+ connect \$63 $not$libresoc.v:144219$7230_Y
+ connect \$69 $or$libresoc.v:144220$7231_Y
+ connect \$71 $and$libresoc.v:144221$7232_Y
+ connect \$73 $ne$libresoc.v:144222$7233_Y
+ connect \$75 $not$libresoc.v:144223$7234_Y
+ connect \$77 $not$libresoc.v:144224$7235_Y
+ connect \$79 $or$libresoc.v:144225$7236_Y
+ connect \$81 $and$libresoc.v:144226$7237_Y
+ connect \$83 $ternary$libresoc.v:144227$7238_Y
+ connect \$85 $or$libresoc.v:144228$7239_Y
+ connect \$87 $and$libresoc.v:144229$7240_Y
+ connect \$89 $ternary$libresoc.v:144230$7241_Y
+ connect \$91 $or$libresoc.v:144231$7242_Y
+ connect \$93 $and$libresoc.v:144232$7243_Y
+ connect \$95 $ne$libresoc.v:144233$7244_Y
+ connect \$97 $ternary$libresoc.v:144234$7245_Y
connect \$48 \$49
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$21 \xer_so
end
-attribute \src "libresoc.v:146547.1-146957.10"
+attribute \src "libresoc.v:144677.1-145087.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main"
attribute \generator "nMigen"
module \main$114
- attribute \src "libresoc.v:146548.7-146548.20"
+ attribute \src "libresoc.v:144678.7-144678.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:146909.3-146939.6"
+ attribute \src "libresoc.v:145039.3-145069.6"
wire width 4 $0\mode[3:0]
- attribute \src "libresoc.v:146874.3-146908.6"
+ attribute \src "libresoc.v:145004.3-145038.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:146909.3-146939.6"
+ attribute \src "libresoc.v:145039.3-145069.6"
wire width 4 $1\mode[3:0]
- attribute \src "libresoc.v:146874.3-146908.6"
+ attribute \src "libresoc.v:145004.3-145038.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:146548.7-146548.15"
+ attribute \src "libresoc.v:144678.7-144678.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46"
wire width 5 \mb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 42 \xer_so$19
attribute \module_not_derived 1
- attribute \src "libresoc.v:146858.11-146873.4"
+ attribute \src "libresoc.v:144988.11-145003.4"
cell \rotator \rotator
connect \arith \rotator_arith
connect \carry_out_o \rotator_carry_out_o
connect \shift \rotator_shift
connect \sign_ext_rs \rotator_sign_ext_rs
end
- attribute \src "libresoc.v:146548.7-146548.20"
- process $proc$libresoc.v:146548$7352
+ attribute \src "libresoc.v:144678.7-144678.20"
+ process $proc$libresoc.v:144678$7278
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:146874.3-146908.6"
- process $proc$libresoc.v:146874$7350
+ attribute \src "libresoc.v:145004.3-145038.6"
+ process $proc$libresoc.v:145004$7276
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:146875.5-146875.29"
+ attribute \src "libresoc.v:145005.5-145005.29"
switch \initial
- attribute \src "libresoc.v:146875.9-146875.17"
+ attribute \src "libresoc.v:145005.9-145005.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:146909.3-146939.6"
- process $proc$libresoc.v:146909$7351
+ attribute \src "libresoc.v:145039.3-145069.6"
+ process $proc$libresoc.v:145039$7277
assign { } { }
assign { } { }
assign $0\mode[3:0] $1\mode[3:0]
- attribute \src "libresoc.v:146910.5-146910.29"
+ attribute \src "libresoc.v:145040.5-145040.29"
switch \initial
- attribute \src "libresoc.v:146910.9-146910.17"
+ attribute \src "libresoc.v:145040.9-145040.17"
case 1'1
case
end
connect \me \sr_op__insn [5:1]
connect \mb \sr_op__insn [10:6]
end
-attribute \src "libresoc.v:146961.1-147493.10"
+attribute \src "libresoc.v:145091.1-145623.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main"
attribute \generator "nMigen"
module \main$22
- attribute \src "libresoc.v:147400.3-147423.6"
+ attribute \src "libresoc.v:145530.3-145553.6"
wire $0\bc_taken[0:0]
- attribute \src "libresoc.v:147279.3-147290.6"
+ attribute \src "libresoc.v:145409.3-145420.6"
wire width 64 $0\br_addr[63:0]
- attribute \src "libresoc.v:147291.3-147317.6"
+ attribute \src "libresoc.v:145421.3-145447.6"
wire width 64 $0\br_imm_addr[63:0]
- attribute \src "libresoc.v:147318.3-147336.6"
+ attribute \src "libresoc.v:145448.3-145466.6"
wire $0\br_taken[0:0]
- attribute \src "libresoc.v:147372.3-147386.6"
+ attribute \src "libresoc.v:145502.3-145516.6"
wire $0\cr_bit[0:0]
- attribute \src "libresoc.v:147450.3-147470.6"
+ attribute \src "libresoc.v:145580.3-145600.6"
wire width 64 $0\ctr_m[63:0]
- attribute \src "libresoc.v:147424.3-147436.6"
+ attribute \src "libresoc.v:145554.3-145566.6"
wire width 64 $0\ctr_n[63:0]
- attribute \src "libresoc.v:147387.3-147399.6"
+ attribute \src "libresoc.v:145517.3-145529.6"
wire $0\ctr_write[0:0]
- attribute \src "libresoc.v:147471.3-147483.6"
+ attribute \src "libresoc.v:145601.3-145613.6"
wire $0\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:147437.3-147449.6"
- wire width 64 $0\fast1$10[63:0]$7385
- attribute \src "libresoc.v:147337.3-147351.6"
+ attribute \src "libresoc.v:145567.3-145579.6"
+ wire width 64 $0\fast1$10[63:0]$7311
+ attribute \src "libresoc.v:145467.3-145481.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:147352.3-147361.6"
- wire width 64 $0\fast2$11[63:0]$7377
- attribute \src "libresoc.v:147362.3-147371.6"
+ attribute \src "libresoc.v:145482.3-145491.6"
+ wire width 64 $0\fast2$11[63:0]$7303
+ attribute \src "libresoc.v:145492.3-145501.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:146962.7-146962.20"
+ attribute \src "libresoc.v:145092.7-145092.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:147400.3-147423.6"
+ attribute \src "libresoc.v:145530.3-145553.6"
wire $1\bc_taken[0:0]
- attribute \src "libresoc.v:147279.3-147290.6"
+ attribute \src "libresoc.v:145409.3-145420.6"
wire width 64 $1\br_addr[63:0]
- attribute \src "libresoc.v:147291.3-147317.6"
+ attribute \src "libresoc.v:145421.3-145447.6"
wire width 64 $1\br_imm_addr[63:0]
- attribute \src "libresoc.v:147318.3-147336.6"
+ attribute \src "libresoc.v:145448.3-145466.6"
wire $1\br_taken[0:0]
- attribute \src "libresoc.v:147372.3-147386.6"
+ attribute \src "libresoc.v:145502.3-145516.6"
wire $1\cr_bit[0:0]
- attribute \src "libresoc.v:147450.3-147470.6"
+ attribute \src "libresoc.v:145580.3-145600.6"
wire width 64 $1\ctr_m[63:0]
- attribute \src "libresoc.v:147424.3-147436.6"
+ attribute \src "libresoc.v:145554.3-145566.6"
wire width 64 $1\ctr_n[63:0]
- attribute \src "libresoc.v:147387.3-147399.6"
+ attribute \src "libresoc.v:145517.3-145529.6"
wire $1\ctr_write[0:0]
- attribute \src "libresoc.v:147471.3-147483.6"
+ attribute \src "libresoc.v:145601.3-145613.6"
wire $1\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:147437.3-147449.6"
- wire width 64 $1\fast1$10[63:0]$7386
- attribute \src "libresoc.v:147337.3-147351.6"
+ attribute \src "libresoc.v:145567.3-145579.6"
+ wire width 64 $1\fast1$10[63:0]$7312
+ attribute \src "libresoc.v:145467.3-145481.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:147352.3-147361.6"
- wire width 64 $1\fast2$11[63:0]$7378
- attribute \src "libresoc.v:147362.3-147371.6"
+ attribute \src "libresoc.v:145482.3-145491.6"
+ wire width 64 $1\fast2$11[63:0]$7304
+ attribute \src "libresoc.v:145492.3-145501.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:147400.3-147423.6"
+ attribute \src "libresoc.v:145530.3-145553.6"
wire $2\bc_taken[0:0]
- attribute \src "libresoc.v:147291.3-147317.6"
+ attribute \src "libresoc.v:145421.3-145447.6"
wire width 64 $2\br_imm_addr[63:0]
- attribute \src "libresoc.v:147450.3-147470.6"
+ attribute \src "libresoc.v:145580.3-145600.6"
wire width 64 $2\ctr_m[63:0]
- attribute \src "libresoc.v:147263.18-147263.119"
- wire width 65 $add$libresoc.v:147263$7355_Y
- attribute \src "libresoc.v:147278.18-147278.113"
- wire width 65 $add$libresoc.v:147278$7371_Y
- attribute \src "libresoc.v:147270.18-147270.115"
- wire $and$libresoc.v:147270$7362_Y
- attribute \src "libresoc.v:147271.18-147271.117"
- wire $and$libresoc.v:147271$7363_Y
- attribute \src "libresoc.v:147277.18-147277.118"
- wire $and$libresoc.v:147277$7370_Y
- attribute \src "libresoc.v:147261.18-147261.120"
- wire $eq$libresoc.v:147261$7353_Y
- attribute \src "libresoc.v:147264.18-147264.111"
- wire $eq$libresoc.v:147264$7356_Y
- attribute \src "libresoc.v:147266.18-147266.111"
- wire $eq$libresoc.v:147266$7358_Y
- attribute \src "libresoc.v:147267.18-147267.111"
- wire $eq$libresoc.v:147267$7359_Y
- attribute \src "libresoc.v:147268.18-147268.109"
- wire $eq$libresoc.v:147268$7360_Y
- attribute \src "libresoc.v:147273.18-147273.98"
- wire width 64 $extend$libresoc.v:147273$7365_Y
- attribute \src "libresoc.v:147269.18-147269.104"
- wire $not$libresoc.v:147269$7361_Y
- attribute \src "libresoc.v:147276.18-147276.112"
- wire $not$libresoc.v:147276$7369_Y
- attribute \src "libresoc.v:147262.18-147262.116"
- wire $or$libresoc.v:147262$7354_Y
- attribute \src "libresoc.v:147265.18-147265.109"
- wire $or$libresoc.v:147265$7357_Y
- attribute \src "libresoc.v:147273.18-147273.98"
- wire width 64 $pos$libresoc.v:147273$7366_Y
- attribute \src "libresoc.v:147274.18-147274.103"
- wire $reduce_or$libresoc.v:147274$7367_Y
- attribute \src "libresoc.v:147272.18-147272.108"
- wire width 65 $sub$libresoc.v:147272$7364_Y
- attribute \src "libresoc.v:147275.18-147275.108"
- wire $xor$libresoc.v:147275$7368_Y
+ attribute \src "libresoc.v:145393.18-145393.119"
+ wire width 65 $add$libresoc.v:145393$7281_Y
+ attribute \src "libresoc.v:145408.18-145408.113"
+ wire width 65 $add$libresoc.v:145408$7297_Y
+ attribute \src "libresoc.v:145400.18-145400.115"
+ wire $and$libresoc.v:145400$7288_Y
+ attribute \src "libresoc.v:145401.18-145401.117"
+ wire $and$libresoc.v:145401$7289_Y
+ attribute \src "libresoc.v:145407.18-145407.118"
+ wire $and$libresoc.v:145407$7296_Y
+ attribute \src "libresoc.v:145391.18-145391.120"
+ wire $eq$libresoc.v:145391$7279_Y
+ attribute \src "libresoc.v:145394.18-145394.111"
+ wire $eq$libresoc.v:145394$7282_Y
+ attribute \src "libresoc.v:145396.18-145396.111"
+ wire $eq$libresoc.v:145396$7284_Y
+ attribute \src "libresoc.v:145397.18-145397.111"
+ wire $eq$libresoc.v:145397$7285_Y
+ attribute \src "libresoc.v:145398.18-145398.109"
+ wire $eq$libresoc.v:145398$7286_Y
+ attribute \src "libresoc.v:145403.18-145403.98"
+ wire width 64 $extend$libresoc.v:145403$7291_Y
+ attribute \src "libresoc.v:145399.18-145399.104"
+ wire $not$libresoc.v:145399$7287_Y
+ attribute \src "libresoc.v:145406.18-145406.112"
+ wire $not$libresoc.v:145406$7295_Y
+ attribute \src "libresoc.v:145392.18-145392.116"
+ wire $or$libresoc.v:145392$7280_Y
+ attribute \src "libresoc.v:145395.18-145395.109"
+ wire $or$libresoc.v:145395$7283_Y
+ attribute \src "libresoc.v:145403.18-145403.98"
+ wire width 64 $pos$libresoc.v:145403$7292_Y
+ attribute \src "libresoc.v:145404.18-145404.103"
+ wire $reduce_or$libresoc.v:145404$7293_Y
+ attribute \src "libresoc.v:145402.18-145402.108"
+ wire width 65 $sub$libresoc.v:145402$7290_Y
+ attribute \src "libresoc.v:145405.18-145405.108"
+ wire $xor$libresoc.v:145405$7294_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
wire \$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
wire width 64 output 23 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 24 \fast2_ok
- attribute \src "libresoc.v:146962.7-146962.15"
+ attribute \src "libresoc.v:145092.7-145092.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 27 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 26 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95"
- cell $add $add$libresoc.v:147263$7355
+ cell $add $add$libresoc.v:145393$7281
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \br_imm_addr
connect \B \br_op__cia
- connect \Y $add$libresoc.v:147263$7355_Y
+ connect \Y $add$libresoc.v:145393$7281_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175"
- cell $add $add$libresoc.v:147278$7371
+ cell $add $add$libresoc.v:145408$7297
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \br_op__cia
connect \B 3'100
- connect \Y $add$libresoc.v:147278$7371_Y
+ connect \Y $add$libresoc.v:145408$7297_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138"
- cell $and $and$libresoc.v:147270$7362
+ cell $and $and$libresoc.v:145400$7288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
connect \B \$29
- connect \Y $and$libresoc.v:147270$7362_Y
+ connect \Y $and$libresoc.v:145400$7288_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140"
- cell $and $and$libresoc.v:147271$7363
+ cell $and $and$libresoc.v:145401$7289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
connect \B \cr_bit
- connect \Y $and$libresoc.v:147271$7363_Y
+ connect \Y $and$libresoc.v:145401$7289_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160"
- cell $and $and$libresoc.v:147277$7370
+ cell $and $and$libresoc.v:145407$7296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn [10]
connect \B \$44
- connect \Y $and$libresoc.v:147277$7370_Y
+ connect \Y $and$libresoc.v:145407$7296_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
- cell $eq $eq$libresoc.v:147261$7353
+ cell $eq $eq$libresoc.v:145391$7279
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn_type
connect \B 7'0001000
- connect \Y $eq$libresoc.v:147261$7353_Y
+ connect \Y $eq$libresoc.v:145391$7279_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121"
- cell $eq $eq$libresoc.v:147264$7356
+ cell $eq $eq$libresoc.v:145394$7282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_bit
connect \B \bo [3]
- connect \Y $eq$libresoc.v:147264$7356_Y
+ connect \Y $eq$libresoc.v:145394$7282_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- cell $eq $eq$libresoc.v:147266$7358
+ cell $eq $eq$libresoc.v:145396$7284
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4:3]
connect \B 1'0
- connect \Y $eq$libresoc.v:147266$7358_Y
+ connect \Y $eq$libresoc.v:145396$7284_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
- cell $eq $eq$libresoc.v:147267$7359
+ cell $eq $eq$libresoc.v:145397$7285
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4:3]
connect \B 1'1
- connect \Y $eq$libresoc.v:147267$7359_Y
+ connect \Y $eq$libresoc.v:145397$7285_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141"
- cell $eq $eq$libresoc.v:147268$7360
+ cell $eq $eq$libresoc.v:145398$7286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [4]
connect \B 1'1
- connect \Y $eq$libresoc.v:147268$7360_Y
+ connect \Y $eq$libresoc.v:145398$7286_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:147273$7365
+ cell $pos $extend$libresoc.v:145403$7291
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \fast1 [31:0]
- connect \Y $extend$libresoc.v:147273$7365_Y
+ connect \Y $extend$libresoc.v:145403$7291_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138"
- cell $not $not$libresoc.v:147269$7361
+ cell $not $not$libresoc.v:145399$7287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cr_bit
- connect \Y $not$libresoc.v:147269$7361_Y
+ connect \Y $not$libresoc.v:145399$7287_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160"
- cell $not $not$libresoc.v:147276$7369
+ cell $not $not$libresoc.v:145406$7295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \br_op__insn [6]
- connect \Y $not$libresoc.v:147276$7369_Y
+ connect \Y $not$libresoc.v:145406$7295_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
- cell $or $or$libresoc.v:147262$7354
+ cell $or $or$libresoc.v:145392$7280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \br_op__insn [1]
connect \B \$12
- connect \Y $or$libresoc.v:147262$7354_Y
+ connect \Y $or$libresoc.v:145392$7280_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121"
- cell $or $or$libresoc.v:147265$7357
+ cell $or $or$libresoc.v:145395$7283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \bo [4]
- connect \Y $or$libresoc.v:147265$7357_Y
+ connect \Y $or$libresoc.v:145395$7283_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:147273$7366
+ cell $pos $pos$libresoc.v:145403$7292
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:147273$7365_Y
- connect \Y $pos$libresoc.v:147273$7366_Y
+ connect \A $extend$libresoc.v:145403$7291_Y
+ connect \Y $pos$libresoc.v:145403$7292_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136"
- cell $reduce_or $reduce_or$libresoc.v:147274$7367
+ cell $reduce_or $reduce_or$libresoc.v:145404$7293
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \ctr_n
- connect \Y $reduce_or$libresoc.v:147274$7367_Y
+ connect \Y $reduce_or$libresoc.v:145404$7293_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125"
- cell $sub $sub$libresoc.v:147272$7364
+ cell $sub $sub$libresoc.v:145402$7290
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \fast1
connect \B 1'1
- connect \Y $sub$libresoc.v:147272$7364_Y
+ connect \Y $sub$libresoc.v:145402$7290_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136"
- cell $xor $xor$libresoc.v:147275$7368
+ cell $xor $xor$libresoc.v:145405$7294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \bo [1]
connect \B \$40
- connect \Y $xor$libresoc.v:147275$7368_Y
+ connect \Y $xor$libresoc.v:145405$7294_Y
end
- attribute \src "libresoc.v:146962.7-146962.20"
- process $proc$libresoc.v:146962$7389
+ attribute \src "libresoc.v:145092.7-145092.20"
+ process $proc$libresoc.v:145092$7315
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:147279.3-147290.6"
- process $proc$libresoc.v:147279$7372
+ attribute \src "libresoc.v:145409.3-145420.6"
+ process $proc$libresoc.v:145409$7298
assign { } { }
assign $0\br_addr[63:0] $1\br_addr[63:0]
- attribute \src "libresoc.v:147280.5-147280.29"
+ attribute \src "libresoc.v:145410.5-145410.29"
switch \initial
- attribute \src "libresoc.v:147280.9-147280.17"
+ attribute \src "libresoc.v:145410.9-145410.17"
case 1'1
case
end
sync always
update \br_addr $0\br_addr[63:0]
end
- attribute \src "libresoc.v:147291.3-147317.6"
- process $proc$libresoc.v:147291$7373
+ attribute \src "libresoc.v:145421.3-145447.6"
+ process $proc$libresoc.v:145421$7299
assign { } { }
assign { } { }
assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0]
- attribute \src "libresoc.v:147292.5-147292.29"
+ attribute \src "libresoc.v:145422.5-145422.29"
switch \initial
- attribute \src "libresoc.v:147292.9-147292.17"
+ attribute \src "libresoc.v:145422.9-145422.17"
case 1'1
case
end
sync always
update \br_imm_addr $0\br_imm_addr[63:0]
end
- attribute \src "libresoc.v:147318.3-147336.6"
- process $proc$libresoc.v:147318$7374
+ attribute \src "libresoc.v:145448.3-145466.6"
+ process $proc$libresoc.v:145448$7300
assign { } { }
assign { } { }
assign $0\br_taken[0:0] $1\br_taken[0:0]
- attribute \src "libresoc.v:147319.5-147319.29"
+ attribute \src "libresoc.v:145449.5-145449.29"
switch \initial
- attribute \src "libresoc.v:147319.9-147319.17"
+ attribute \src "libresoc.v:145449.9-145449.17"
case 1'1
case
end
sync always
update \br_taken $0\br_taken[0:0]
end
- attribute \src "libresoc.v:147337.3-147351.6"
- process $proc$libresoc.v:147337$7375
+ attribute \src "libresoc.v:145467.3-145481.6"
+ process $proc$libresoc.v:145467$7301
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:147338.5-147338.29"
+ attribute \src "libresoc.v:145468.5-145468.29"
switch \initial
- attribute \src "libresoc.v:147338.9-147338.17"
+ attribute \src "libresoc.v:145468.9-145468.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:147352.3-147361.6"
- process $proc$libresoc.v:147352$7376
+ attribute \src "libresoc.v:145482.3-145491.6"
+ process $proc$libresoc.v:145482$7302
assign { } { }
assign { } { }
- assign $0\fast2$11[63:0]$7377 $1\fast2$11[63:0]$7378
- attribute \src "libresoc.v:147353.5-147353.29"
+ assign $0\fast2$11[63:0]$7303 $1\fast2$11[63:0]$7304
+ attribute \src "libresoc.v:145483.5-145483.29"
switch \initial
- attribute \src "libresoc.v:147353.9-147353.17"
+ attribute \src "libresoc.v:145483.9-145483.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\fast2$11[63:0]$7378 \$48 [63:0]
+ assign $1\fast2$11[63:0]$7304 \$48 [63:0]
case
- assign $1\fast2$11[63:0]$7378 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$11[63:0]$7304 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast2$11 $0\fast2$11[63:0]$7377
+ update \fast2$11 $0\fast2$11[63:0]$7303
end
- attribute \src "libresoc.v:147362.3-147371.6"
- process $proc$libresoc.v:147362$7379
+ attribute \src "libresoc.v:145492.3-145501.6"
+ process $proc$libresoc.v:145492$7305
assign { } { }
assign { } { }
assign $0\fast2_ok[0:0] $1\fast2_ok[0:0]
- attribute \src "libresoc.v:147363.5-147363.29"
+ attribute \src "libresoc.v:145493.5-145493.29"
switch \initial
- attribute \src "libresoc.v:147363.9-147363.17"
+ attribute \src "libresoc.v:145493.9-145493.17"
case 1'1
case
end
sync always
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:147372.3-147386.6"
- process $proc$libresoc.v:147372$7380
+ attribute \src "libresoc.v:145502.3-145516.6"
+ process $proc$libresoc.v:145502$7306
assign { } { }
assign { } { }
assign $0\cr_bit[0:0] $1\cr_bit[0:0]
- attribute \src "libresoc.v:147373.5-147373.29"
+ attribute \src "libresoc.v:145503.5-145503.29"
switch \initial
- attribute \src "libresoc.v:147373.9-147373.17"
+ attribute \src "libresoc.v:145503.9-145503.17"
case 1'1
case
end
sync always
update \cr_bit $0\cr_bit[0:0]
end
- attribute \src "libresoc.v:147387.3-147399.6"
- process $proc$libresoc.v:147387$7381
+ attribute \src "libresoc.v:145517.3-145529.6"
+ process $proc$libresoc.v:145517$7307
assign { } { }
assign { } { }
assign $0\ctr_write[0:0] $1\ctr_write[0:0]
- attribute \src "libresoc.v:147388.5-147388.29"
+ attribute \src "libresoc.v:145518.5-145518.29"
switch \initial
- attribute \src "libresoc.v:147388.9-147388.17"
+ attribute \src "libresoc.v:145518.9-145518.17"
case 1'1
case
end
sync always
update \ctr_write $0\ctr_write[0:0]
end
- attribute \src "libresoc.v:147400.3-147423.6"
- process $proc$libresoc.v:147400$7382
+ attribute \src "libresoc.v:145530.3-145553.6"
+ process $proc$libresoc.v:145530$7308
assign { } { }
assign { } { }
assign $0\bc_taken[0:0] $1\bc_taken[0:0]
- attribute \src "libresoc.v:147401.5-147401.29"
+ attribute \src "libresoc.v:145531.5-145531.29"
switch \initial
- attribute \src "libresoc.v:147401.9-147401.17"
+ attribute \src "libresoc.v:145531.9-145531.17"
case 1'1
case
end
sync always
update \bc_taken $0\bc_taken[0:0]
end
- attribute \src "libresoc.v:147424.3-147436.6"
- process $proc$libresoc.v:147424$7383
+ attribute \src "libresoc.v:145554.3-145566.6"
+ process $proc$libresoc.v:145554$7309
assign { } { }
assign { } { }
assign $0\ctr_n[63:0] $1\ctr_n[63:0]
- attribute \src "libresoc.v:147425.5-147425.29"
+ attribute \src "libresoc.v:145555.5-145555.29"
switch \initial
- attribute \src "libresoc.v:147425.9-147425.17"
+ attribute \src "libresoc.v:145555.9-145555.17"
case 1'1
case
end
sync always
update \ctr_n $0\ctr_n[63:0]
end
- attribute \src "libresoc.v:147437.3-147449.6"
- process $proc$libresoc.v:147437$7384
+ attribute \src "libresoc.v:145567.3-145579.6"
+ process $proc$libresoc.v:145567$7310
assign { } { }
assign { } { }
- assign $0\fast1$10[63:0]$7385 $1\fast1$10[63:0]$7386
- attribute \src "libresoc.v:147438.5-147438.29"
+ assign $0\fast1$10[63:0]$7311 $1\fast1$10[63:0]$7312
+ attribute \src "libresoc.v:145568.5-145568.29"
switch \initial
- attribute \src "libresoc.v:147438.9-147438.17"
+ attribute \src "libresoc.v:145568.9-145568.17"
case 1'1
case
end
switch \bo [2]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $1\fast1$10[63:0]$7386 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$10[63:0]$7312 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\fast1$10[63:0]$7386 \ctr_n
+ assign $1\fast1$10[63:0]$7312 \ctr_n
end
sync always
- update \fast1$10 $0\fast1$10[63:0]$7385
+ update \fast1$10 $0\fast1$10[63:0]$7311
end
- attribute \src "libresoc.v:147450.3-147470.6"
- process $proc$libresoc.v:147450$7387
+ attribute \src "libresoc.v:145580.3-145600.6"
+ process $proc$libresoc.v:145580$7313
assign { } { }
assign { } { }
assign $0\ctr_m[63:0] $1\ctr_m[63:0]
- attribute \src "libresoc.v:147451.5-147451.29"
+ attribute \src "libresoc.v:145581.5-145581.29"
switch \initial
- attribute \src "libresoc.v:147451.9-147451.17"
+ attribute \src "libresoc.v:145581.9-145581.17"
case 1'1
case
end
sync always
update \ctr_m $0\ctr_m[63:0]
end
- attribute \src "libresoc.v:147471.3-147483.6"
- process $proc$libresoc.v:147471$7388
+ attribute \src "libresoc.v:145601.3-145613.6"
+ process $proc$libresoc.v:145601$7314
assign { } { }
assign { } { }
assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0]
- attribute \src "libresoc.v:147472.5-147472.29"
+ attribute \src "libresoc.v:145602.5-145602.29"
switch \initial
- attribute \src "libresoc.v:147472.9-147472.17"
+ attribute \src "libresoc.v:145602.9-145602.17"
case 1'1
case
end
sync always
update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0]
end
- connect \$12 $eq$libresoc.v:147261$7353_Y
- connect \$14 $or$libresoc.v:147262$7354_Y
- connect \$17 $add$libresoc.v:147263$7355_Y
- connect \$19 $eq$libresoc.v:147264$7356_Y
- connect \$21 $or$libresoc.v:147265$7357_Y
- connect \$23 $eq$libresoc.v:147266$7358_Y
- connect \$25 $eq$libresoc.v:147267$7359_Y
- connect \$27 $eq$libresoc.v:147268$7360_Y
- connect \$29 $not$libresoc.v:147269$7361_Y
- connect \$31 $and$libresoc.v:147270$7362_Y
- connect \$33 $and$libresoc.v:147271$7363_Y
- connect \$36 $sub$libresoc.v:147272$7364_Y
- connect \$38 $pos$libresoc.v:147273$7366_Y
- connect \$40 $reduce_or$libresoc.v:147274$7367_Y
- connect \$42 $xor$libresoc.v:147275$7368_Y
- connect \$44 $not$libresoc.v:147276$7369_Y
- connect \$46 $and$libresoc.v:147277$7370_Y
- connect \$49 $add$libresoc.v:147278$7371_Y
+ connect \$12 $eq$libresoc.v:145391$7279_Y
+ connect \$14 $or$libresoc.v:145392$7280_Y
+ connect \$17 $add$libresoc.v:145393$7281_Y
+ connect \$19 $eq$libresoc.v:145394$7282_Y
+ connect \$21 $or$libresoc.v:145395$7283_Y
+ connect \$23 $eq$libresoc.v:145396$7284_Y
+ connect \$25 $eq$libresoc.v:145397$7285_Y
+ connect \$27 $eq$libresoc.v:145398$7286_Y
+ connect \$29 $not$libresoc.v:145399$7287_Y
+ connect \$31 $and$libresoc.v:145400$7288_Y
+ connect \$33 $and$libresoc.v:145401$7289_Y
+ connect \$36 $sub$libresoc.v:145402$7290_Y
+ connect \$38 $pos$libresoc.v:145403$7292_Y
+ connect \$40 $reduce_or$libresoc.v:145404$7293_Y
+ connect \$42 $xor$libresoc.v:145405$7294_Y
+ connect \$44 $not$libresoc.v:145406$7295_Y
+ connect \$46 $and$libresoc.v:145407$7296_Y
+ connect \$49 $add$libresoc.v:145408$7297_Y
connect \$16 \$17
connect \$35 \$36
connect \$48 \$49
connect \bi \br_op__insn [17:16]
connect \bo \br_op__insn [25:21]
end
-attribute \src "libresoc.v:147497.1-148443.10"
+attribute \src "libresoc.v:145627.1-146573.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main"
attribute \generator "nMigen"
module \main$38
- attribute \src "libresoc.v:148408.3-148419.6"
+ attribute \src "libresoc.v:146538.3-146549.6"
wire width 64 $0\a[63:0]
- attribute \src "libresoc.v:147906.3-147917.6"
+ attribute \src "libresoc.v:146036.3-146047.6"
wire width 64 $0\a_s[63:0]
- attribute \src "libresoc.v:148420.3-148431.6"
+ attribute \src "libresoc.v:146550.3-146561.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:148189.3-148200.6"
+ attribute \src "libresoc.v:146319.3-146330.6"
wire width 64 $0\b_s[63:0]
- attribute \src "libresoc.v:147982.3-148013.6"
- wire width 64 $0\fast1$11[63:0]$7435
- attribute \src "libresoc.v:148014.3-148045.6"
+ attribute \src "libresoc.v:146112.3-146143.6"
+ wire width 64 $0\fast1$11[63:0]$7361
+ attribute \src "libresoc.v:146144.3-146175.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire width 64 $0\fast2$12[63:0]$7440
- attribute \src "libresoc.v:148129.3-148160.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire width 64 $0\fast2$12[63:0]$7366
+ attribute \src "libresoc.v:146259.3-146290.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:147498.7-147498.20"
+ attribute \src "libresoc.v:145628.7-145628.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $0\msr_ok[0:0]
- attribute \src "libresoc.v:147918.3-147949.6"
+ attribute \src "libresoc.v:146048.3-146079.6"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:147950.3-147981.6"
+ attribute \src "libresoc.v:146080.3-146111.6"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:148370.3-148388.6"
+ attribute \src "libresoc.v:146500.3-146518.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:148389.3-148407.6"
+ attribute \src "libresoc.v:146519.3-146537.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$60[0:0]$7454
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$61[0:0]$7455
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$62[0:0]$7456
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$67[0:0]$7457
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$68[0:0]$7458
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$69[0:0]$7459
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal$70[0:0]$7460
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $0\trapexc_$signal[0:0]$7453
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $10\fast2$12[19:19]$7450
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$60[0:0]$7380
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$61[0:0]$7381
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$62[0:0]$7382
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$67[0:0]$7383
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$68[0:0]$7384
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$69[0:0]$7385
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal$70[0:0]$7386
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $0\trapexc_$signal[0:0]$7379
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $10\fast2$12[19:19]$7376
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 2 $10\msr[5:4]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $11\msr[15:15]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $12\msr[12:12]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $13\msr[60:60]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $14\msr[12:12]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $15\msr[12:12]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 2 $16\msr[5:4]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $17\msr[15:15]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 3 $18\msr[34:32]
- attribute \src "libresoc.v:148408.3-148419.6"
+ attribute \src "libresoc.v:146538.3-146549.6"
wire width 64 $1\a[63:0]
- attribute \src "libresoc.v:147906.3-147917.6"
+ attribute \src "libresoc.v:146036.3-146047.6"
wire width 64 $1\a_s[63:0]
- attribute \src "libresoc.v:148420.3-148431.6"
+ attribute \src "libresoc.v:146550.3-146561.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:148189.3-148200.6"
+ attribute \src "libresoc.v:146319.3-146330.6"
wire width 64 $1\b_s[63:0]
- attribute \src "libresoc.v:147982.3-148013.6"
- wire width 64 $1\fast1$11[63:0]$7436
- attribute \src "libresoc.v:148014.3-148045.6"
+ attribute \src "libresoc.v:146112.3-146143.6"
+ wire width 64 $1\fast1$11[63:0]$7362
+ attribute \src "libresoc.v:146144.3-146175.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire width 64 $1\fast2$12[63:0]$7441
- attribute \src "libresoc.v:148129.3-148160.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire width 64 $1\fast2$12[63:0]$7367
+ attribute \src "libresoc.v:146259.3-146290.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $1\msr_ok[0:0]
- attribute \src "libresoc.v:147918.3-147949.6"
+ attribute \src "libresoc.v:146048.3-146079.6"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:147950.3-147981.6"
+ attribute \src "libresoc.v:146080.3-146111.6"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:148370.3-148388.6"
+ attribute \src "libresoc.v:146500.3-146518.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:148389.3-148407.6"
+ attribute \src "libresoc.v:146519.3-146537.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$60[0:0]$7462
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$61[0:0]$7463
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$62[0:0]$7464
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$67[0:0]$7465
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$68[0:0]$7466
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$69[0:0]$7467
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal$70[0:0]$7468
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $1\trapexc_$signal[0:0]$7461
- attribute \src "libresoc.v:147982.3-148013.6"
- wire width 64 $2\fast1$11[63:0]$7437
- attribute \src "libresoc.v:148014.3-148045.6"
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$60[0:0]$7388
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$61[0:0]$7389
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$62[0:0]$7390
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$67[0:0]$7391
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$68[0:0]$7392
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$69[0:0]$7393
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal$70[0:0]$7394
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $1\trapexc_$signal[0:0]$7387
+ attribute \src "libresoc.v:146112.3-146143.6"
+ wire width 64 $2\fast1$11[63:0]$7363
+ attribute \src "libresoc.v:146144.3-146175.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire width 64 $2\fast2$12[63:0]$7442
- attribute \src "libresoc.v:148129.3-148160.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire width 64 $2\fast2$12[63:0]$7368
+ attribute \src "libresoc.v:146259.3-146290.6"
wire $2\fast2_ok[0:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 64 $2\msr[63:0]
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146331.3-146499.6"
wire $2\msr_ok[0:0]
- attribute \src "libresoc.v:147918.3-147949.6"
+ attribute \src "libresoc.v:146048.3-146079.6"
wire width 64 $2\nia[63:0]
- attribute \src "libresoc.v:147950.3-147981.6"
+ attribute \src "libresoc.v:146080.3-146111.6"
wire $2\nia_ok[0:0]
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$60[0:0]$7470
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$61[0:0]$7471
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$62[0:0]$7472
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$67[0:0]$7473
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$68[0:0]$7474
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$69[0:0]$7475
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal$70[0:0]$7476
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $2\trapexc_$signal[0:0]$7469
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $3\fast2$12[17:17]$7443
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$60[0:0]$7396
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$61[0:0]$7397
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$62[0:0]$7398
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$67[0:0]$7399
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$68[0:0]$7400
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$69[0:0]$7401
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal$70[0:0]$7402
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $2\trapexc_$signal[0:0]$7395
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $3\fast2$12[17:17]$7369
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 11 $3\msr[11:1]
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$60[0:0]$7478
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$61[0:0]$7479
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$62[0:0]$7480
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$67[0:0]$7481
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$68[0:0]$7482
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$69[0:0]$7483
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal$70[0:0]$7484
- attribute \src "libresoc.v:148161.3-148188.6"
- wire $3\trapexc_$signal[0:0]$7477
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $4\fast2$12[18:18]$7444
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$60[0:0]$7404
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$61[0:0]$7405
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$62[0:0]$7406
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$67[0:0]$7407
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$68[0:0]$7408
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$69[0:0]$7409
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal$70[0:0]$7410
+ attribute \src "libresoc.v:146291.3-146318.6"
+ wire $3\trapexc_$signal[0:0]$7403
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $4\fast2$12[18:18]$7370
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 47 $4\msr[59:13]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $5\fast2$12[20:20]$7445
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $5\fast2$12[20:20]$7371
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 3 $5\msr[63:61]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $6\fast2$12[16:16]$7446
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $6\fast2$12[16:16]$7372
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 11 $6\msr[11:1]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire width 2 $7\fast2$12[19:18]$7447
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire width 2 $7\fast2$12[19:18]$7373
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 47 $7\msr[59:13]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $8\fast2$12[28:28]$7448
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $8\fast2$12[28:28]$7374
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 3 $8\msr[63:61]
- attribute \src "libresoc.v:148046.3-148128.6"
- wire $9\fast2$12[30:30]$7449
- attribute \src "libresoc.v:148201.3-148369.6"
+ attribute \src "libresoc.v:146176.3-146258.6"
+ wire $9\fast2$12[30:30]$7375
+ attribute \src "libresoc.v:146331.3-146499.6"
wire width 3 $9\msr[34:32]
- attribute \src "libresoc.v:147882.18-147882.113"
- wire width 65 $add$libresoc.v:147882$7406_Y
- attribute \src "libresoc.v:147876.18-147876.108"
- wire width 5 $and$libresoc.v:147876$7399_Y
- attribute \src "libresoc.v:147884.18-147884.118"
- wire width 8 $and$libresoc.v:147884$7408_Y
- attribute \src "libresoc.v:147886.18-147886.118"
- wire width 8 $and$libresoc.v:147886$7410_Y
- attribute \src "libresoc.v:147888.18-147888.118"
- wire width 8 $and$libresoc.v:147888$7412_Y
- attribute \src "libresoc.v:147890.18-147890.119"
- wire width 8 $and$libresoc.v:147890$7414_Y
- attribute \src "libresoc.v:147892.18-147892.119"
- wire width 8 $and$libresoc.v:147892$7416_Y
- attribute \src "libresoc.v:147894.18-147894.119"
- wire width 8 $and$libresoc.v:147894$7418_Y
- attribute \src "libresoc.v:147900.18-147900.106"
- wire $and$libresoc.v:147900$7425_Y
- attribute \src "libresoc.v:147905.18-147905.106"
- wire $and$libresoc.v:147905$7430_Y
- attribute \src "libresoc.v:147875.18-147875.100"
- wire $eq$libresoc.v:147875$7398_Y
- attribute \src "libresoc.v:147883.18-147883.119"
- wire $eq$libresoc.v:147883$7407_Y
- attribute \src "libresoc.v:147897.18-147897.121"
- wire $eq$libresoc.v:147897$7422_Y
- attribute \src "libresoc.v:147898.18-147898.121"
- wire $eq$libresoc.v:147898$7423_Y
- attribute \src "libresoc.v:147899.18-147899.111"
- wire $eq$libresoc.v:147899$7424_Y
- attribute \src "libresoc.v:147903.18-147903.121"
- wire $eq$libresoc.v:147903$7428_Y
- attribute \src "libresoc.v:147904.18-147904.114"
- wire $eq$libresoc.v:147904$7429_Y
- attribute \src "libresoc.v:147869.18-147869.95"
- wire width 64 $extend$libresoc.v:147869$7390_Y
- attribute \src "libresoc.v:147870.18-147870.95"
- wire width 64 $extend$libresoc.v:147870$7392_Y
- attribute \src "libresoc.v:147881.18-147881.100"
- wire width 64 $extend$libresoc.v:147881$7404_Y
- attribute \src "libresoc.v:147896.18-147896.109"
- wire width 65 $extend$libresoc.v:147896$7420_Y
- attribute \src "libresoc.v:147872.18-147872.121"
- wire $gt$libresoc.v:147872$7395_Y
- attribute \src "libresoc.v:147874.18-147874.99"
- wire $gt$libresoc.v:147874$7397_Y
- attribute \src "libresoc.v:147871.18-147871.121"
- wire $lt$libresoc.v:147871$7394_Y
- attribute \src "libresoc.v:147873.18-147873.99"
- wire $lt$libresoc.v:147873$7396_Y
- attribute \src "libresoc.v:147901.18-147901.112"
- wire $not$libresoc.v:147901$7426_Y
- attribute \src "libresoc.v:147902.18-147902.112"
- wire $not$libresoc.v:147902$7427_Y
- attribute \src "libresoc.v:147879.18-147879.106"
- wire $or$libresoc.v:147879$7402_Y
- attribute \src "libresoc.v:147869.18-147869.95"
- wire width 64 $pos$libresoc.v:147869$7391_Y
- attribute \src "libresoc.v:147870.18-147870.95"
- wire width 64 $pos$libresoc.v:147870$7393_Y
- attribute \src "libresoc.v:147881.18-147881.100"
- wire width 64 $pos$libresoc.v:147881$7405_Y
- attribute \src "libresoc.v:147896.18-147896.109"
- wire width 65 $pos$libresoc.v:147896$7421_Y
- attribute \src "libresoc.v:147877.18-147877.100"
- wire $reduce_or$libresoc.v:147877$7400_Y
- attribute \src "libresoc.v:147878.18-147878.113"
- wire $reduce_or$libresoc.v:147878$7401_Y
- attribute \src "libresoc.v:147885.18-147885.91"
- wire $reduce_or$libresoc.v:147885$7409_Y
- attribute \src "libresoc.v:147887.18-147887.91"
- wire $reduce_or$libresoc.v:147887$7411_Y
- attribute \src "libresoc.v:147889.18-147889.91"
- wire $reduce_or$libresoc.v:147889$7413_Y
- attribute \src "libresoc.v:147891.18-147891.91"
- wire $reduce_or$libresoc.v:147891$7415_Y
- attribute \src "libresoc.v:147893.18-147893.91"
- wire $reduce_or$libresoc.v:147893$7417_Y
- attribute \src "libresoc.v:147895.18-147895.91"
- wire $reduce_or$libresoc.v:147895$7419_Y
- attribute \src "libresoc.v:147880.18-147880.120"
- wire width 20 $sshl$libresoc.v:147880$7403_Y
+ attribute \src "libresoc.v:146012.18-146012.113"
+ wire width 65 $add$libresoc.v:146012$7332_Y
+ attribute \src "libresoc.v:146006.18-146006.108"
+ wire width 5 $and$libresoc.v:146006$7325_Y
+ attribute \src "libresoc.v:146014.18-146014.118"
+ wire width 8 $and$libresoc.v:146014$7334_Y
+ attribute \src "libresoc.v:146016.18-146016.118"
+ wire width 8 $and$libresoc.v:146016$7336_Y
+ attribute \src "libresoc.v:146018.18-146018.118"
+ wire width 8 $and$libresoc.v:146018$7338_Y
+ attribute \src "libresoc.v:146020.18-146020.119"
+ wire width 8 $and$libresoc.v:146020$7340_Y
+ attribute \src "libresoc.v:146022.18-146022.119"
+ wire width 8 $and$libresoc.v:146022$7342_Y
+ attribute \src "libresoc.v:146024.18-146024.119"
+ wire width 8 $and$libresoc.v:146024$7344_Y
+ attribute \src "libresoc.v:146030.18-146030.106"
+ wire $and$libresoc.v:146030$7351_Y
+ attribute \src "libresoc.v:146035.18-146035.106"
+ wire $and$libresoc.v:146035$7356_Y
+ attribute \src "libresoc.v:146005.18-146005.100"
+ wire $eq$libresoc.v:146005$7324_Y
+ attribute \src "libresoc.v:146013.18-146013.119"
+ wire $eq$libresoc.v:146013$7333_Y
+ attribute \src "libresoc.v:146027.18-146027.121"
+ wire $eq$libresoc.v:146027$7348_Y
+ attribute \src "libresoc.v:146028.18-146028.121"
+ wire $eq$libresoc.v:146028$7349_Y
+ attribute \src "libresoc.v:146029.18-146029.111"
+ wire $eq$libresoc.v:146029$7350_Y
+ attribute \src "libresoc.v:146033.18-146033.121"
+ wire $eq$libresoc.v:146033$7354_Y
+ attribute \src "libresoc.v:146034.18-146034.114"
+ wire $eq$libresoc.v:146034$7355_Y
+ attribute \src "libresoc.v:145999.18-145999.95"
+ wire width 64 $extend$libresoc.v:145999$7316_Y
+ attribute \src "libresoc.v:146000.18-146000.95"
+ wire width 64 $extend$libresoc.v:146000$7318_Y
+ attribute \src "libresoc.v:146011.18-146011.100"
+ wire width 64 $extend$libresoc.v:146011$7330_Y
+ attribute \src "libresoc.v:146026.18-146026.109"
+ wire width 65 $extend$libresoc.v:146026$7346_Y
+ attribute \src "libresoc.v:146002.18-146002.121"
+ wire $gt$libresoc.v:146002$7321_Y
+ attribute \src "libresoc.v:146004.18-146004.99"
+ wire $gt$libresoc.v:146004$7323_Y
+ attribute \src "libresoc.v:146001.18-146001.121"
+ wire $lt$libresoc.v:146001$7320_Y
+ attribute \src "libresoc.v:146003.18-146003.99"
+ wire $lt$libresoc.v:146003$7322_Y
+ attribute \src "libresoc.v:146031.18-146031.112"
+ wire $not$libresoc.v:146031$7352_Y
+ attribute \src "libresoc.v:146032.18-146032.112"
+ wire $not$libresoc.v:146032$7353_Y
+ attribute \src "libresoc.v:146009.18-146009.106"
+ wire $or$libresoc.v:146009$7328_Y
+ attribute \src "libresoc.v:145999.18-145999.95"
+ wire width 64 $pos$libresoc.v:145999$7317_Y
+ attribute \src "libresoc.v:146000.18-146000.95"
+ wire width 64 $pos$libresoc.v:146000$7319_Y
+ attribute \src "libresoc.v:146011.18-146011.100"
+ wire width 64 $pos$libresoc.v:146011$7331_Y
+ attribute \src "libresoc.v:146026.18-146026.109"
+ wire width 65 $pos$libresoc.v:146026$7347_Y
+ attribute \src "libresoc.v:146007.18-146007.100"
+ wire $reduce_or$libresoc.v:146007$7326_Y
+ attribute \src "libresoc.v:146008.18-146008.113"
+ wire $reduce_or$libresoc.v:146008$7327_Y
+ attribute \src "libresoc.v:146015.18-146015.91"
+ wire $reduce_or$libresoc.v:146015$7335_Y
+ attribute \src "libresoc.v:146017.18-146017.91"
+ wire $reduce_or$libresoc.v:146017$7337_Y
+ attribute \src "libresoc.v:146019.18-146019.91"
+ wire $reduce_or$libresoc.v:146019$7339_Y
+ attribute \src "libresoc.v:146021.18-146021.91"
+ wire $reduce_or$libresoc.v:146021$7341_Y
+ attribute \src "libresoc.v:146023.18-146023.91"
+ wire $reduce_or$libresoc.v:146023$7343_Y
+ attribute \src "libresoc.v:146025.18-146025.91"
+ wire $reduce_or$libresoc.v:146025$7345_Y
+ attribute \src "libresoc.v:146010.18-146010.120"
+ wire width 20 $sshl$libresoc.v:146010$7329_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire width 64 \$13
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire \gt_s
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160"
wire \gt_u
- attribute \src "libresoc.v:147498.7-147498.15"
+ attribute \src "libresoc.v:145628.7-145628.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
wire \lt_s
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \trapexc_$signal$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315"
- cell $add $add$libresoc.v:147882$7406
+ cell $add $add$libresoc.v:146012$7332
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \trap_op__cia
connect \B 3'100
- connect \Y $add$libresoc.v:147882$7406_Y
+ connect \Y $add$libresoc.v:146012$7332_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $and $and$libresoc.v:147876$7399
+ cell $and $and$libresoc.v:146006$7325
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \trap_bits
connect \B \to
- connect \Y $and$libresoc.v:147876$7399_Y
+ connect \Y $and$libresoc.v:146006$7325_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193"
- cell $and $and$libresoc.v:147884$7408
+ cell $and $and$libresoc.v:146014$7334
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 2'10
- connect \Y $and$libresoc.v:147884$7408_Y
+ connect \Y $and$libresoc.v:146014$7334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
- cell $and $and$libresoc.v:147886$7410
+ cell $and $and$libresoc.v:146016$7336
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 1'1
- connect \Y $and$libresoc.v:147886$7410_Y
+ connect \Y $and$libresoc.v:146016$7336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197"
- cell $and $and$libresoc.v:147888$7412
+ cell $and $and$libresoc.v:146018$7338
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 4'1000
- connect \Y $and$libresoc.v:147888$7412_Y
+ connect \Y $and$libresoc.v:146018$7338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
- cell $and $and$libresoc.v:147890$7414
+ cell $and $and$libresoc.v:146020$7340
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 7'1000000
- connect \Y $and$libresoc.v:147890$7414_Y
+ connect \Y $and$libresoc.v:146020$7340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
- cell $and $and$libresoc.v:147892$7416
+ cell $and $and$libresoc.v:146022$7342
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 8'10000000
- connect \Y $and$libresoc.v:147892$7416_Y
+ connect \Y $and$libresoc.v:146022$7342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
- cell $and $and$libresoc.v:147894$7418
+ cell $and $and$libresoc.v:146024$7344
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \trap_op__traptype
connect \B 7'1000000
- connect \Y $and$libresoc.v:147894$7418_Y
+ connect \Y $and$libresoc.v:146024$7344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
- cell $and $and$libresoc.v:147900$7425
+ cell $and $and$libresoc.v:146030$7351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$79
connect \B \$81
- connect \Y $and$libresoc.v:147900$7425_Y
+ connect \Y $and$libresoc.v:146030$7351_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296"
- cell $and $and$libresoc.v:147905$7430
+ cell $and $and$libresoc.v:146035$7356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$89
connect \B \$91
- connect \Y $and$libresoc.v:147905$7430_Y
+ connect \Y $and$libresoc.v:146035$7356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- cell $eq $eq$libresoc.v:147875$7398
+ cell $eq $eq$libresoc.v:146005$7324
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $eq$libresoc.v:147875$7398_Y
+ connect \Y $eq$libresoc.v:146005$7324_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190"
- cell $eq $eq$libresoc.v:147883$7407
+ cell $eq $eq$libresoc.v:146013$7333
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__traptype
connect \B 1'0
- connect \Y $eq$libresoc.v:147883$7407_Y
+ connect \Y $eq$libresoc.v:146013$7333_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234"
- cell $eq $eq$libresoc.v:147897$7422
+ cell $eq $eq$libresoc.v:146027$7348
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__insn_type
connect \B 7'1001000
- connect \Y $eq$libresoc.v:147897$7422_Y
+ connect \Y $eq$libresoc.v:146027$7348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240"
- cell $eq $eq$libresoc.v:147898$7423
+ cell $eq $eq$libresoc.v:146028$7349
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__msr [34:32]
connect \B 3'010
- connect \Y $eq$libresoc.v:147898$7423_Y
+ connect \Y $eq$libresoc.v:146028$7349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
- cell $eq $eq$libresoc.v:147899$7424
+ cell $eq $eq$libresoc.v:146029$7350
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [34:32]
connect \B 3'000
- connect \Y $eq$libresoc.v:147899$7424_Y
+ connect \Y $eq$libresoc.v:146029$7350_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295"
- cell $eq $eq$libresoc.v:147903$7428
+ cell $eq $eq$libresoc.v:146033$7354
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \trap_op__msr [34:32]
connect \B 3'010
- connect \Y $eq$libresoc.v:147903$7428_Y
+ connect \Y $eq$libresoc.v:146033$7354_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296"
- cell $eq $eq$libresoc.v:147904$7429
+ cell $eq $eq$libresoc.v:146034$7355
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast2 [34:32]
connect \B 3'000
- connect \Y $eq$libresoc.v:147904$7429_Y
+ connect \Y $eq$libresoc.v:146034$7355_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:147869$7390
+ cell $pos $extend$libresoc.v:145999$7316
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \ra [31:0]
- connect \Y $extend$libresoc.v:147869$7390_Y
+ connect \Y $extend$libresoc.v:145999$7316_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:147870$7392
+ cell $pos $extend$libresoc.v:146000$7318
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \rb [31:0]
- connect \Y $extend$libresoc.v:147870$7392_Y
+ connect \Y $extend$libresoc.v:146000$7318_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $pos $extend$libresoc.v:147881$7404
+ cell $pos $extend$libresoc.v:146011$7330
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \Y_WIDTH 64
connect \A \$36
- connect \Y $extend$libresoc.v:147881$7404_Y
+ connect \Y $extend$libresoc.v:146011$7330_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $extend$libresoc.v:147896$7420
+ cell $pos $extend$libresoc.v:146026$7346
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \trap_op__msr
- connect \Y $extend$libresoc.v:147896$7420_Y
+ connect \Y $extend$libresoc.v:146026$7346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
- cell $gt $gt$libresoc.v:147872$7395
+ cell $gt $gt$libresoc.v:146002$7321
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $gt$libresoc.v:147872$7395_Y
+ connect \Y $gt$libresoc.v:146002$7321_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166"
- cell $gt $gt$libresoc.v:147874$7397
+ cell $gt $gt$libresoc.v:146004$7323
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $gt$libresoc.v:147874$7397_Y
+ connect \Y $gt$libresoc.v:146004$7323_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
- cell $lt $lt$libresoc.v:147871$7394
+ cell $lt $lt$libresoc.v:146001$7320
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $lt$libresoc.v:147871$7394_Y
+ connect \Y $lt$libresoc.v:146001$7320_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165"
- cell $lt $lt$libresoc.v:147873$7396
+ cell $lt $lt$libresoc.v:146003$7322
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $lt$libresoc.v:147873$7396_Y
+ connect \Y $lt$libresoc.v:146003$7322_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256"
- cell $not $not$libresoc.v:147901$7426
+ cell $not $not$libresoc.v:146031$7352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \trap_op__msr [60]
- connect \Y $not$libresoc.v:147901$7426_Y
+ connect \Y $not$libresoc.v:146031$7352_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
- cell $not $not$libresoc.v:147902$7427
+ cell $not $not$libresoc.v:146032$7353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \trap_op__insn [9]
- connect \Y $not$libresoc.v:147902$7427_Y
+ connect \Y $not$libresoc.v:146032$7353_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $or $or$libresoc.v:147879$7402
+ cell $or $or$libresoc.v:146009$7328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$27
connect \B \$31
- connect \Y $or$libresoc.v:147879$7402_Y
+ connect \Y $or$libresoc.v:146009$7328_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:147869$7391
+ cell $pos $pos$libresoc.v:145999$7317
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:147869$7390_Y
- connect \Y $pos$libresoc.v:147869$7391_Y
+ connect \A $extend$libresoc.v:145999$7316_Y
+ connect \Y $pos$libresoc.v:145999$7317_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:147870$7393
+ cell $pos $pos$libresoc.v:146000$7319
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:147870$7392_Y
- connect \Y $pos$libresoc.v:147870$7393_Y
+ connect \A $extend$libresoc.v:146000$7318_Y
+ connect \Y $pos$libresoc.v:146000$7319_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $pos $pos$libresoc.v:147881$7405
+ cell $pos $pos$libresoc.v:146011$7331
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:147881$7404_Y
- connect \Y $pos$libresoc.v:147881$7405_Y
+ connect \A $extend$libresoc.v:146011$7330_Y
+ connect \Y $pos$libresoc.v:146011$7331_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $pos$libresoc.v:147896$7421
+ cell $pos $pos$libresoc.v:146026$7347
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:147896$7420_Y
- connect \Y $pos$libresoc.v:147896$7421_Y
+ connect \A $extend$libresoc.v:146026$7346_Y
+ connect \Y $pos$libresoc.v:146026$7347_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $reduce_or $reduce_or$libresoc.v:147877$7400
+ cell $reduce_or $reduce_or$libresoc.v:146007$7326
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $reduce_or$libresoc.v:147877$7400_Y
+ connect \Y $reduce_or$libresoc.v:146007$7326_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
- cell $reduce_or $reduce_or$libresoc.v:147878$7401
+ cell $reduce_or $reduce_or$libresoc.v:146008$7327
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \trap_op__traptype
- connect \Y $reduce_or$libresoc.v:147878$7401_Y
+ connect \Y $reduce_or$libresoc.v:146008$7327_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147885$7409
+ cell $reduce_or $reduce_or$libresoc.v:146015$7335
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$45
- connect \Y $reduce_or$libresoc.v:147885$7409_Y
+ connect \Y $reduce_or$libresoc.v:146015$7335_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147887$7411
+ cell $reduce_or $reduce_or$libresoc.v:146017$7337
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$49
- connect \Y $reduce_or$libresoc.v:147887$7411_Y
+ connect \Y $reduce_or$libresoc.v:146017$7337_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147889$7413
+ cell $reduce_or $reduce_or$libresoc.v:146019$7339
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$53
- connect \Y $reduce_or$libresoc.v:147889$7413_Y
+ connect \Y $reduce_or$libresoc.v:146019$7339_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147891$7415
+ cell $reduce_or $reduce_or$libresoc.v:146021$7341
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$57
- connect \Y $reduce_or$libresoc.v:147891$7415_Y
+ connect \Y $reduce_or$libresoc.v:146021$7341_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147893$7417
+ cell $reduce_or $reduce_or$libresoc.v:146023$7343
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$64
- connect \Y $reduce_or$libresoc.v:147893$7417_Y
+ connect \Y $reduce_or$libresoc.v:146023$7343_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:147895$7419
+ cell $reduce_or $reduce_or$libresoc.v:146025$7345
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \$72
- connect \Y $reduce_or$libresoc.v:147895$7419_Y
+ connect \Y $reduce_or$libresoc.v:146025$7345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
- cell $sshl $sshl$libresoc.v:147880$7403
+ cell $sshl $sshl$libresoc.v:146010$7329
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \trap_op__trapaddr
connect \B 3'100
- connect \Y $sshl$libresoc.v:147880$7403_Y
+ connect \Y $sshl$libresoc.v:146010$7329_Y
end
- attribute \src "libresoc.v:147498.7-147498.20"
- process $proc$libresoc.v:147498$7491
+ attribute \src "libresoc.v:145628.7-145628.20"
+ process $proc$libresoc.v:145628$7417
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:147906.3-147917.6"
- process $proc$libresoc.v:147906$7431
+ attribute \src "libresoc.v:146036.3-146047.6"
+ process $proc$libresoc.v:146036$7357
assign { } { }
assign $0\a_s[63:0] $1\a_s[63:0]
- attribute \src "libresoc.v:147907.5-147907.29"
+ attribute \src "libresoc.v:146037.5-146037.29"
switch \initial
- attribute \src "libresoc.v:147907.9-147907.17"
+ attribute \src "libresoc.v:146037.9-146037.17"
case 1'1
case
end
sync always
update \a_s $0\a_s[63:0]
end
- attribute \src "libresoc.v:147918.3-147949.6"
- process $proc$libresoc.v:147918$7432
+ attribute \src "libresoc.v:146048.3-146079.6"
+ process $proc$libresoc.v:146048$7358
assign { } { }
assign { } { }
assign $0\nia[63:0] $1\nia[63:0]
- attribute \src "libresoc.v:147919.5-147919.29"
+ attribute \src "libresoc.v:146049.5-146049.29"
switch \initial
- attribute \src "libresoc.v:147919.9-147919.17"
+ attribute \src "libresoc.v:146049.9-146049.17"
case 1'1
case
end
sync always
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:147950.3-147981.6"
- process $proc$libresoc.v:147950$7433
+ attribute \src "libresoc.v:146080.3-146111.6"
+ process $proc$libresoc.v:146080$7359
assign { } { }
assign { } { }
assign $0\nia_ok[0:0] $1\nia_ok[0:0]
- attribute \src "libresoc.v:147951.5-147951.29"
+ attribute \src "libresoc.v:146081.5-146081.29"
switch \initial
- attribute \src "libresoc.v:147951.9-147951.17"
+ attribute \src "libresoc.v:146081.9-146081.17"
case 1'1
case
end
sync always
update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:147982.3-148013.6"
- process $proc$libresoc.v:147982$7434
+ attribute \src "libresoc.v:146112.3-146143.6"
+ process $proc$libresoc.v:146112$7360
assign { } { }
assign { } { }
- assign $0\fast1$11[63:0]$7435 $1\fast1$11[63:0]$7436
- attribute \src "libresoc.v:147983.5-147983.29"
+ assign $0\fast1$11[63:0]$7361 $1\fast1$11[63:0]$7362
+ attribute \src "libresoc.v:146113.5-146113.29"
switch \initial
- attribute \src "libresoc.v:147983.9-147983.17"
+ attribute \src "libresoc.v:146113.9-146113.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0111111
assign { } { }
- assign $1\fast1$11[63:0]$7436 $2\fast1$11[63:0]$7437
+ assign $1\fast1$11[63:0]$7362 $2\fast1$11[63:0]$7363
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1$11[63:0]$7437 \trap_op__cia
+ assign $2\fast1$11[63:0]$7363 \trap_op__cia
case
- assign $2\fast1$11[63:0]$7437 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast1$11[63:0]$7363 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
case 7'1001000 , 7'1001010
- assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000111
- assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000110
- assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1001001
assign { } { }
- assign $1\fast1$11[63:0]$7436 \$39 [63:0]
+ assign $1\fast1$11[63:0]$7362 \$39 [63:0]
case
- assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast1$11 $0\fast1$11[63:0]$7435
+ update \fast1$11 $0\fast1$11[63:0]$7361
end
- attribute \src "libresoc.v:148014.3-148045.6"
- process $proc$libresoc.v:148014$7438
+ attribute \src "libresoc.v:146144.3-146175.6"
+ process $proc$libresoc.v:146144$7364
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:148015.5-148015.29"
+ attribute \src "libresoc.v:146145.5-146145.29"
switch \initial
- attribute \src "libresoc.v:148015.9-148015.17"
+ attribute \src "libresoc.v:146145.9-146145.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:148046.3-148128.6"
- process $proc$libresoc.v:148046$7439
+ attribute \src "libresoc.v:146176.3-146258.6"
+ process $proc$libresoc.v:146176$7365
assign { } { }
assign { } { }
- assign $0\fast2$12[63:0]$7440 $1\fast2$12[63:0]$7441
- attribute \src "libresoc.v:148047.5-148047.29"
+ assign $0\fast2$12[63:0]$7366 $1\fast2$12[63:0]$7367
+ attribute \src "libresoc.v:146177.5-146177.29"
switch \initial
- attribute \src "libresoc.v:148047.9-148047.17"
+ attribute \src "libresoc.v:146177.9-146177.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0111111
assign { } { }
- assign $1\fast2$12[63:0]$7441 $2\fast2$12[63:0]$7442
+ assign $1\fast2$12[63:0]$7367 $2\fast2$12[63:0]$7368
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign { $2\fast2$12[63:0]$7442 [29] $2\fast2$12[63:0]$7442 [27] $2\fast2$12[63:0]$7442 [21] } 3'000
- assign $2\fast2$12[63:0]$7442 [15:0] \trap_op__msr [15:0]
- assign $2\fast2$12[63:0]$7442 [26:22] \trap_op__msr [26:22]
- assign $2\fast2$12[63:0]$7442 [63:31] \trap_op__msr [63:31]
- assign $2\fast2$12[63:0]$7442 [17] $3\fast2$12[17:17]$7443
- assign { } { }
- assign $2\fast2$12[63:0]$7442 [20] $5\fast2$12[20:20]$7445
- assign $2\fast2$12[63:0]$7442 [16] $6\fast2$12[16:16]$7446
- assign $2\fast2$12[63:0]$7442 [18] $7\fast2$12[19:18]$7447 [0]
- assign $2\fast2$12[63:0]$7442 [28] $8\fast2$12[28:28]$7448
- assign $2\fast2$12[63:0]$7442 [30] $9\fast2$12[30:30]$7449
- assign $2\fast2$12[63:0]$7442 [19] $10\fast2$12[19:19]$7450
+ assign { $2\fast2$12[63:0]$7368 [29] $2\fast2$12[63:0]$7368 [27] $2\fast2$12[63:0]$7368 [21] } 3'000
+ assign $2\fast2$12[63:0]$7368 [15:0] \trap_op__msr [15:0]
+ assign $2\fast2$12[63:0]$7368 [26:22] \trap_op__msr [26:22]
+ assign $2\fast2$12[63:0]$7368 [63:31] \trap_op__msr [63:31]
+ assign $2\fast2$12[63:0]$7368 [17] $3\fast2$12[17:17]$7369
+ assign { } { }
+ assign $2\fast2$12[63:0]$7368 [20] $5\fast2$12[20:20]$7371
+ assign $2\fast2$12[63:0]$7368 [16] $6\fast2$12[16:16]$7372
+ assign $2\fast2$12[63:0]$7368 [18] $7\fast2$12[19:18]$7373 [0]
+ assign $2\fast2$12[63:0]$7368 [28] $8\fast2$12[28:28]$7374
+ assign $2\fast2$12[63:0]$7368 [30] $9\fast2$12[30:30]$7375
+ assign $2\fast2$12[63:0]$7368 [19] $10\fast2$12[19:19]$7376
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190"
switch \$42
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fast2$12[17:17]$7443 1'1
+ assign $3\fast2$12[17:17]$7369 1'1
case
- assign $3\fast2$12[17:17]$7443 1'0
+ assign $3\fast2$12[17:17]$7369 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193"
switch \$44
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fast2$12[18:18]$7444 1'1
+ assign $4\fast2$12[18:18]$7370 1'1
case
- assign $4\fast2$12[18:18]$7444 1'0
+ assign $4\fast2$12[18:18]$7370 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
switch \$48
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fast2$12[20:20]$7445 1'1
+ assign $5\fast2$12[20:20]$7371 1'1
case
- assign $5\fast2$12[20:20]$7445 1'0
+ assign $5\fast2$12[20:20]$7371 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197"
switch \$52
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\fast2$12[16:16]$7446 1'1
+ assign $6\fast2$12[16:16]$7372 1'1
case
- assign $6\fast2$12[16:16]$7446 1'0
+ assign $6\fast2$12[16:16]$7372 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
switch \$56
assign { } { }
assign { } { }
assign { } { }
- assign $9\fast2$12[30:30]$7449 \trapexc_$signal
- assign $8\fast2$12[28:28]$7448 \trapexc_$signal$60
- assign $7\fast2$12[19:18]$7447 [1] \trapexc_$signal$61
- assign $7\fast2$12[19:18]$7447 [0] \trapexc_$signal$62
+ assign $9\fast2$12[30:30]$7375 \trapexc_$signal
+ assign $8\fast2$12[28:28]$7374 \trapexc_$signal$60
+ assign $7\fast2$12[19:18]$7373 [1] \trapexc_$signal$61
+ assign $7\fast2$12[19:18]$7373 [0] \trapexc_$signal$62
case
- assign $7\fast2$12[19:18]$7447 { 1'0 $4\fast2$12[18:18]$7444 }
- assign $8\fast2$12[28:28]$7448 1'0
- assign $9\fast2$12[30:30]$7449 1'0
+ assign $7\fast2$12[19:18]$7373 { 1'0 $4\fast2$12[18:18]$7370 }
+ assign $8\fast2$12[28:28]$7374 1'0
+ assign $9\fast2$12[30:30]$7375 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
switch \$63
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $10\fast2$12[19:19]$7450 1'1
+ assign $10\fast2$12[19:19]$7376 1'1
case
- assign $10\fast2$12[19:19]$7450 $7\fast2$12[19:18]$7447 [1]
+ assign $10\fast2$12[19:19]$7376 $7\fast2$12[19:18]$7373 [1]
end
case
- assign $2\fast2$12[63:0]$7442 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast2$12[63:0]$7368 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
case 7'1001000 , 7'1001010
- assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000111
- assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1000110
- assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 7'1001001
assign { } { }
- assign { $1\fast2$12[63:0]$7441 [30:27] $1\fast2$12[63:0]$7441 [21:16] } 10'0000000000
- assign $1\fast2$12[63:0]$7441 [15:0] \trap_op__msr [15:0]
- assign $1\fast2$12[63:0]$7441 [26:22] \trap_op__msr [26:22]
- assign $1\fast2$12[63:0]$7441 [63:31] \trap_op__msr [63:31]
+ assign { $1\fast2$12[63:0]$7367 [30:27] $1\fast2$12[63:0]$7367 [21:16] } 10'0000000000
+ assign $1\fast2$12[63:0]$7367 [15:0] \trap_op__msr [15:0]
+ assign $1\fast2$12[63:0]$7367 [26:22] \trap_op__msr [26:22]
+ assign $1\fast2$12[63:0]$7367 [63:31] \trap_op__msr [63:31]
case
- assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast2$12 $0\fast2$12[63:0]$7440
+ update \fast2$12 $0\fast2$12[63:0]$7366
end
- attribute \src "libresoc.v:148129.3-148160.6"
- process $proc$libresoc.v:148129$7451
+ attribute \src "libresoc.v:146259.3-146290.6"
+ process $proc$libresoc.v:146259$7377
assign { } { }
assign { } { }
assign $0\fast2_ok[0:0] $1\fast2_ok[0:0]
- attribute \src "libresoc.v:148130.5-148130.29"
+ attribute \src "libresoc.v:146260.5-146260.29"
switch \initial
- attribute \src "libresoc.v:148130.9-148130.17"
+ attribute \src "libresoc.v:146260.9-146260.17"
case 1'1
case
end
sync always
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:148161.3-148188.6"
- process $proc$libresoc.v:148161$7452
+ attribute \src "libresoc.v:146291.3-146318.6"
+ process $proc$libresoc.v:146291$7378
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trapexc_$signal[0:0]$7453 $1\trapexc_$signal[0:0]$7461
- assign $0\trapexc_$signal$60[0:0]$7454 $1\trapexc_$signal$60[0:0]$7462
- assign $0\trapexc_$signal$61[0:0]$7455 $1\trapexc_$signal$61[0:0]$7463
- assign $0\trapexc_$signal$62[0:0]$7456 $1\trapexc_$signal$62[0:0]$7464
- assign $0\trapexc_$signal$67[0:0]$7457 $1\trapexc_$signal$67[0:0]$7465
- assign $0\trapexc_$signal$68[0:0]$7458 $1\trapexc_$signal$68[0:0]$7466
- assign $0\trapexc_$signal$69[0:0]$7459 $1\trapexc_$signal$69[0:0]$7467
- assign $0\trapexc_$signal$70[0:0]$7460 $1\trapexc_$signal$70[0:0]$7468
- attribute \src "libresoc.v:148162.5-148162.29"
+ assign $0\trapexc_$signal[0:0]$7379 $1\trapexc_$signal[0:0]$7387
+ assign $0\trapexc_$signal$60[0:0]$7380 $1\trapexc_$signal$60[0:0]$7388
+ assign $0\trapexc_$signal$61[0:0]$7381 $1\trapexc_$signal$61[0:0]$7389
+ assign $0\trapexc_$signal$62[0:0]$7382 $1\trapexc_$signal$62[0:0]$7390
+ assign $0\trapexc_$signal$67[0:0]$7383 $1\trapexc_$signal$67[0:0]$7391
+ assign $0\trapexc_$signal$68[0:0]$7384 $1\trapexc_$signal$68[0:0]$7392
+ assign $0\trapexc_$signal$69[0:0]$7385 $1\trapexc_$signal$69[0:0]$7393
+ assign $0\trapexc_$signal$70[0:0]$7386 $1\trapexc_$signal$70[0:0]$7394
+ attribute \src "libresoc.v:146292.5-146292.29"
switch \initial
- attribute \src "libresoc.v:148162.9-148162.17"
+ attribute \src "libresoc.v:146292.9-146292.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\trapexc_$signal[0:0]$7461 $2\trapexc_$signal[0:0]$7469
- assign $1\trapexc_$signal$60[0:0]$7462 $2\trapexc_$signal$60[0:0]$7470
- assign $1\trapexc_$signal$61[0:0]$7463 $2\trapexc_$signal$61[0:0]$7471
- assign $1\trapexc_$signal$62[0:0]$7464 $2\trapexc_$signal$62[0:0]$7472
- assign $1\trapexc_$signal$67[0:0]$7465 $2\trapexc_$signal$67[0:0]$7473
- assign $1\trapexc_$signal$68[0:0]$7466 $2\trapexc_$signal$68[0:0]$7474
- assign $1\trapexc_$signal$69[0:0]$7467 $2\trapexc_$signal$69[0:0]$7475
- assign $1\trapexc_$signal$70[0:0]$7468 $2\trapexc_$signal$70[0:0]$7476
+ assign $1\trapexc_$signal[0:0]$7387 $2\trapexc_$signal[0:0]$7395
+ assign $1\trapexc_$signal$60[0:0]$7388 $2\trapexc_$signal$60[0:0]$7396
+ assign $1\trapexc_$signal$61[0:0]$7389 $2\trapexc_$signal$61[0:0]$7397
+ assign $1\trapexc_$signal$62[0:0]$7390 $2\trapexc_$signal$62[0:0]$7398
+ assign $1\trapexc_$signal$67[0:0]$7391 $2\trapexc_$signal$67[0:0]$7399
+ assign $1\trapexc_$signal$68[0:0]$7392 $2\trapexc_$signal$68[0:0]$7400
+ assign $1\trapexc_$signal$69[0:0]$7393 $2\trapexc_$signal$69[0:0]$7401
+ assign $1\trapexc_$signal$70[0:0]$7394 $2\trapexc_$signal$70[0:0]$7402
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
switch \should_trap
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\trapexc_$signal[0:0]$7469 $3\trapexc_$signal[0:0]$7477
- assign $2\trapexc_$signal$60[0:0]$7470 $3\trapexc_$signal$60[0:0]$7478
- assign $2\trapexc_$signal$61[0:0]$7471 $3\trapexc_$signal$61[0:0]$7479
- assign $2\trapexc_$signal$62[0:0]$7472 $3\trapexc_$signal$62[0:0]$7480
- assign $2\trapexc_$signal$67[0:0]$7473 $3\trapexc_$signal$67[0:0]$7481
- assign $2\trapexc_$signal$68[0:0]$7474 $3\trapexc_$signal$68[0:0]$7482
- assign $2\trapexc_$signal$69[0:0]$7475 $3\trapexc_$signal$69[0:0]$7483
- assign $2\trapexc_$signal$70[0:0]$7476 $3\trapexc_$signal$70[0:0]$7484
+ assign $2\trapexc_$signal[0:0]$7395 $3\trapexc_$signal[0:0]$7403
+ assign $2\trapexc_$signal$60[0:0]$7396 $3\trapexc_$signal$60[0:0]$7404
+ assign $2\trapexc_$signal$61[0:0]$7397 $3\trapexc_$signal$61[0:0]$7405
+ assign $2\trapexc_$signal$62[0:0]$7398 $3\trapexc_$signal$62[0:0]$7406
+ assign $2\trapexc_$signal$67[0:0]$7399 $3\trapexc_$signal$67[0:0]$7407
+ assign $2\trapexc_$signal$68[0:0]$7400 $3\trapexc_$signal$68[0:0]$7408
+ assign $2\trapexc_$signal$69[0:0]$7401 $3\trapexc_$signal$69[0:0]$7409
+ assign $2\trapexc_$signal$70[0:0]$7402 $3\trapexc_$signal$70[0:0]$7410
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
switch \$71
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $3\trapexc_$signal$70[0:0]$7484 $3\trapexc_$signal$62[0:0]$7480 $3\trapexc_$signal$60[0:0]$7478 $3\trapexc_$signal$61[0:0]$7479 $3\trapexc_$signal[0:0]$7477 $3\trapexc_$signal$69[0:0]$7483 $3\trapexc_$signal$68[0:0]$7482 $3\trapexc_$signal$67[0:0]$7481 } \trap_op__ldst_exc
+ assign { $3\trapexc_$signal$70[0:0]$7410 $3\trapexc_$signal$62[0:0]$7406 $3\trapexc_$signal$60[0:0]$7404 $3\trapexc_$signal$61[0:0]$7405 $3\trapexc_$signal[0:0]$7403 $3\trapexc_$signal$69[0:0]$7409 $3\trapexc_$signal$68[0:0]$7408 $3\trapexc_$signal$67[0:0]$7407 } \trap_op__ldst_exc
case
- assign $3\trapexc_$signal[0:0]$7477 1'0
- assign $3\trapexc_$signal$60[0:0]$7478 1'0
- assign $3\trapexc_$signal$61[0:0]$7479 1'0
- assign $3\trapexc_$signal$62[0:0]$7480 1'0
- assign $3\trapexc_$signal$67[0:0]$7481 1'0
- assign $3\trapexc_$signal$68[0:0]$7482 1'0
- assign $3\trapexc_$signal$69[0:0]$7483 1'0
- assign $3\trapexc_$signal$70[0:0]$7484 1'0
+ assign $3\trapexc_$signal[0:0]$7403 1'0
+ assign $3\trapexc_$signal$60[0:0]$7404 1'0
+ assign $3\trapexc_$signal$61[0:0]$7405 1'0
+ assign $3\trapexc_$signal$62[0:0]$7406 1'0
+ assign $3\trapexc_$signal$67[0:0]$7407 1'0
+ assign $3\trapexc_$signal$68[0:0]$7408 1'0
+ assign $3\trapexc_$signal$69[0:0]$7409 1'0
+ assign $3\trapexc_$signal$70[0:0]$7410 1'0
end
case
- assign $2\trapexc_$signal[0:0]$7469 1'0
- assign $2\trapexc_$signal$60[0:0]$7470 1'0
- assign $2\trapexc_$signal$61[0:0]$7471 1'0
- assign $2\trapexc_$signal$62[0:0]$7472 1'0
- assign $2\trapexc_$signal$67[0:0]$7473 1'0
- assign $2\trapexc_$signal$68[0:0]$7474 1'0
- assign $2\trapexc_$signal$69[0:0]$7475 1'0
- assign $2\trapexc_$signal$70[0:0]$7476 1'0
- end
- case
- assign $1\trapexc_$signal[0:0]$7461 1'0
- assign $1\trapexc_$signal$60[0:0]$7462 1'0
- assign $1\trapexc_$signal$61[0:0]$7463 1'0
- assign $1\trapexc_$signal$62[0:0]$7464 1'0
- assign $1\trapexc_$signal$67[0:0]$7465 1'0
- assign $1\trapexc_$signal$68[0:0]$7466 1'0
- assign $1\trapexc_$signal$69[0:0]$7467 1'0
- assign $1\trapexc_$signal$70[0:0]$7468 1'0
- end
- sync always
- update \trapexc_$signal $0\trapexc_$signal[0:0]$7453
- update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7454
- update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7455
- update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7456
- update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7457
- update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7458
- update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7459
- update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7460
- end
- attribute \src "libresoc.v:148189.3-148200.6"
- process $proc$libresoc.v:148189$7485
+ assign $2\trapexc_$signal[0:0]$7395 1'0
+ assign $2\trapexc_$signal$60[0:0]$7396 1'0
+ assign $2\trapexc_$signal$61[0:0]$7397 1'0
+ assign $2\trapexc_$signal$62[0:0]$7398 1'0
+ assign $2\trapexc_$signal$67[0:0]$7399 1'0
+ assign $2\trapexc_$signal$68[0:0]$7400 1'0
+ assign $2\trapexc_$signal$69[0:0]$7401 1'0
+ assign $2\trapexc_$signal$70[0:0]$7402 1'0
+ end
+ case
+ assign $1\trapexc_$signal[0:0]$7387 1'0
+ assign $1\trapexc_$signal$60[0:0]$7388 1'0
+ assign $1\trapexc_$signal$61[0:0]$7389 1'0
+ assign $1\trapexc_$signal$62[0:0]$7390 1'0
+ assign $1\trapexc_$signal$67[0:0]$7391 1'0
+ assign $1\trapexc_$signal$68[0:0]$7392 1'0
+ assign $1\trapexc_$signal$69[0:0]$7393 1'0
+ assign $1\trapexc_$signal$70[0:0]$7394 1'0
+ end
+ sync always
+ update \trapexc_$signal $0\trapexc_$signal[0:0]$7379
+ update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7380
+ update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7381
+ update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7382
+ update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7383
+ update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7384
+ update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7385
+ update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7386
+ end
+ attribute \src "libresoc.v:146319.3-146330.6"
+ process $proc$libresoc.v:146319$7411
assign { } { }
assign $0\b_s[63:0] $1\b_s[63:0]
- attribute \src "libresoc.v:148190.5-148190.29"
+ attribute \src "libresoc.v:146320.5-146320.29"
switch \initial
- attribute \src "libresoc.v:148190.9-148190.17"
+ attribute \src "libresoc.v:146320.9-146320.17"
case 1'1
case
end
sync always
update \b_s $0\b_s[63:0]
end
- attribute \src "libresoc.v:148201.3-148369.6"
- process $proc$libresoc.v:148201$7486
+ attribute \src "libresoc.v:146331.3-146499.6"
+ process $proc$libresoc.v:146331$7412
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\msr[63:0] $1\msr[63:0]
assign $0\msr_ok[0:0] $1\msr_ok[0:0]
- attribute \src "libresoc.v:148202.5-148202.29"
+ attribute \src "libresoc.v:146332.5-146332.29"
switch \initial
- attribute \src "libresoc.v:148202.9-148202.17"
+ attribute \src "libresoc.v:146332.9-146332.17"
case 1'1
case
end
update \msr $0\msr[63:0]
update \msr_ok $0\msr_ok[0:0]
end
- attribute \src "libresoc.v:148370.3-148388.6"
- process $proc$libresoc.v:148370$7487
+ attribute \src "libresoc.v:146500.3-146518.6"
+ process $proc$libresoc.v:146500$7413
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:148371.5-148371.29"
+ attribute \src "libresoc.v:146501.5-146501.29"
switch \initial
- attribute \src "libresoc.v:148371.9-148371.17"
+ attribute \src "libresoc.v:146501.9-146501.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:148389.3-148407.6"
- process $proc$libresoc.v:148389$7488
+ attribute \src "libresoc.v:146519.3-146537.6"
+ process $proc$libresoc.v:146519$7414
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:148390.5-148390.29"
+ attribute \src "libresoc.v:146520.5-146520.29"
switch \initial
- attribute \src "libresoc.v:148390.9-148390.17"
+ attribute \src "libresoc.v:146520.9-146520.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:148408.3-148419.6"
- process $proc$libresoc.v:148408$7489
+ attribute \src "libresoc.v:146538.3-146549.6"
+ process $proc$libresoc.v:146538$7415
assign { } { }
assign $0\a[63:0] $1\a[63:0]
- attribute \src "libresoc.v:148409.5-148409.29"
+ attribute \src "libresoc.v:146539.5-146539.29"
switch \initial
- attribute \src "libresoc.v:148409.9-148409.17"
+ attribute \src "libresoc.v:146539.9-146539.17"
case 1'1
case
end
sync always
update \a $0\a[63:0]
end
- attribute \src "libresoc.v:148420.3-148431.6"
- process $proc$libresoc.v:148420$7490
+ attribute \src "libresoc.v:146550.3-146561.6"
+ process $proc$libresoc.v:146550$7416
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:148421.5-148421.29"
+ attribute \src "libresoc.v:146551.5-146551.29"
switch \initial
- attribute \src "libresoc.v:148421.9-148421.17"
+ attribute \src "libresoc.v:146551.9-146551.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- connect \$13 $pos$libresoc.v:147869$7391_Y
- connect \$15 $pos$libresoc.v:147870$7393_Y
- connect \$17 $lt$libresoc.v:147871$7394_Y
- connect \$19 $gt$libresoc.v:147872$7395_Y
- connect \$21 $lt$libresoc.v:147873$7396_Y
- connect \$23 $gt$libresoc.v:147874$7397_Y
- connect \$25 $eq$libresoc.v:147875$7398_Y
- connect \$28 $and$libresoc.v:147876$7399_Y
- connect \$27 $reduce_or$libresoc.v:147877$7400_Y
- connect \$31 $reduce_or$libresoc.v:147878$7401_Y
- connect \$33 $or$libresoc.v:147879$7402_Y
- connect \$36 $sshl$libresoc.v:147880$7403_Y
- connect \$35 $pos$libresoc.v:147881$7405_Y
- connect \$40 $add$libresoc.v:147882$7406_Y
- connect \$42 $eq$libresoc.v:147883$7407_Y
- connect \$45 $and$libresoc.v:147884$7408_Y
- connect \$44 $reduce_or$libresoc.v:147885$7409_Y
- connect \$49 $and$libresoc.v:147886$7410_Y
- connect \$48 $reduce_or$libresoc.v:147887$7411_Y
- connect \$53 $and$libresoc.v:147888$7412_Y
- connect \$52 $reduce_or$libresoc.v:147889$7413_Y
- connect \$57 $and$libresoc.v:147890$7414_Y
- connect \$56 $reduce_or$libresoc.v:147891$7415_Y
- connect \$64 $and$libresoc.v:147892$7416_Y
- connect \$63 $reduce_or$libresoc.v:147893$7417_Y
- connect \$72 $and$libresoc.v:147894$7418_Y
- connect \$71 $reduce_or$libresoc.v:147895$7419_Y
- connect \$75 $pos$libresoc.v:147896$7421_Y
- connect \$77 $eq$libresoc.v:147897$7422_Y
- connect \$79 $eq$libresoc.v:147898$7423_Y
- connect \$81 $eq$libresoc.v:147899$7424_Y
- connect \$83 $and$libresoc.v:147900$7425_Y
- connect \$85 $not$libresoc.v:147901$7426_Y
- connect \$87 $not$libresoc.v:147902$7427_Y
- connect \$89 $eq$libresoc.v:147903$7428_Y
- connect \$91 $eq$libresoc.v:147904$7429_Y
- connect \$93 $and$libresoc.v:147905$7430_Y
+ connect \$13 $pos$libresoc.v:145999$7317_Y
+ connect \$15 $pos$libresoc.v:146000$7319_Y
+ connect \$17 $lt$libresoc.v:146001$7320_Y
+ connect \$19 $gt$libresoc.v:146002$7321_Y
+ connect \$21 $lt$libresoc.v:146003$7322_Y
+ connect \$23 $gt$libresoc.v:146004$7323_Y
+ connect \$25 $eq$libresoc.v:146005$7324_Y
+ connect \$28 $and$libresoc.v:146006$7325_Y
+ connect \$27 $reduce_or$libresoc.v:146007$7326_Y
+ connect \$31 $reduce_or$libresoc.v:146008$7327_Y
+ connect \$33 $or$libresoc.v:146009$7328_Y
+ connect \$36 $sshl$libresoc.v:146010$7329_Y
+ connect \$35 $pos$libresoc.v:146011$7331_Y
+ connect \$40 $add$libresoc.v:146012$7332_Y
+ connect \$42 $eq$libresoc.v:146013$7333_Y
+ connect \$45 $and$libresoc.v:146014$7334_Y
+ connect \$44 $reduce_or$libresoc.v:146015$7335_Y
+ connect \$49 $and$libresoc.v:146016$7336_Y
+ connect \$48 $reduce_or$libresoc.v:146017$7337_Y
+ connect \$53 $and$libresoc.v:146018$7338_Y
+ connect \$52 $reduce_or$libresoc.v:146019$7339_Y
+ connect \$57 $and$libresoc.v:146020$7340_Y
+ connect \$56 $reduce_or$libresoc.v:146021$7341_Y
+ connect \$64 $and$libresoc.v:146022$7342_Y
+ connect \$63 $reduce_or$libresoc.v:146023$7343_Y
+ connect \$72 $and$libresoc.v:146024$7344_Y
+ connect \$71 $reduce_or$libresoc.v:146025$7345_Y
+ connect \$75 $pos$libresoc.v:146026$7347_Y
+ connect \$77 $eq$libresoc.v:146027$7348_Y
+ connect \$79 $eq$libresoc.v:146028$7349_Y
+ connect \$81 $eq$libresoc.v:146029$7350_Y
+ connect \$83 $and$libresoc.v:146030$7351_Y
+ connect \$85 $not$libresoc.v:146031$7352_Y
+ connect \$87 $not$libresoc.v:146032$7353_Y
+ connect \$89 $eq$libresoc.v:146033$7354_Y
+ connect \$91 $eq$libresoc.v:146034$7355_Y
+ connect \$93 $and$libresoc.v:146035$7356_Y
connect \$39 \$40
connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \muxid$1 \muxid
connect \lt_s \$17
connect \to \trap_op__insn [25:21]
end
-attribute \src "libresoc.v:148447.1-149192.10"
+attribute \src "libresoc.v:146577.1-147322.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main"
attribute \generator "nMigen"
module \main$51
- attribute \src "libresoc.v:149159.3-149169.6"
+ attribute \src "libresoc.v:147289.3-147299.6"
wire width 32 $0\a32[31:0]
- attribute \src "libresoc.v:149104.3-149114.6"
+ attribute \src "libresoc.v:147234.3-147244.6"
wire width 64 $0\b[63:0]
- attribute \src "libresoc.v:149082.3-149092.6"
+ attribute \src "libresoc.v:147212.3-147222.6"
wire width 64 $0\bpermd_rb[63:0]
- attribute \src "libresoc.v:149071.3-149081.6"
+ attribute \src "libresoc.v:147201.3-147211.6"
wire width 64 $0\bpermd_rs[63:0]
- attribute \src "libresoc.v:149060.3-149070.6"
+ attribute \src "libresoc.v:147190.3-147200.6"
wire width 64 $0\clz_sig_in[63:0]
- attribute \src "libresoc.v:149170.3-149188.6"
+ attribute \src "libresoc.v:147300.3-147318.6"
wire width 64 $0\cntz_i[63:0]
- attribute \src "libresoc.v:149148.3-149158.6"
+ attribute \src "libresoc.v:147278.3-147288.6"
wire $0\count_right[0:0]
- attribute \src "libresoc.v:148448.7-148448.20"
+ attribute \src "libresoc.v:146578.7-146578.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:149005.3-149059.6"
+ attribute \src "libresoc.v:147135.3-147189.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:149005.3-149059.6"
+ attribute \src "libresoc.v:147135.3-147189.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:149126.3-149136.6"
+ attribute \src "libresoc.v:147256.3-147266.6"
wire $0\par0[0:0]
- attribute \src "libresoc.v:149137.3-149147.6"
+ attribute \src "libresoc.v:147267.3-147277.6"
wire $0\par1[0:0]
- attribute \src "libresoc.v:149093.3-149103.6"
+ attribute \src "libresoc.v:147223.3-147233.6"
wire width 64 $0\popcount_a[63:0]
- attribute \src "libresoc.v:149115.3-149125.6"
+ attribute \src "libresoc.v:147245.3-147255.6"
wire width 64 $0\popcount_data_len[63:0]
- attribute \src "libresoc.v:149159.3-149169.6"
+ attribute \src "libresoc.v:147289.3-147299.6"
wire width 32 $1\a32[31:0]
- attribute \src "libresoc.v:149104.3-149114.6"
+ attribute \src "libresoc.v:147234.3-147244.6"
wire width 64 $1\b[63:0]
- attribute \src "libresoc.v:149082.3-149092.6"
+ attribute \src "libresoc.v:147212.3-147222.6"
wire width 64 $1\bpermd_rb[63:0]
- attribute \src "libresoc.v:149071.3-149081.6"
+ attribute \src "libresoc.v:147201.3-147211.6"
wire width 64 $1\bpermd_rs[63:0]
- attribute \src "libresoc.v:149060.3-149070.6"
+ attribute \src "libresoc.v:147190.3-147200.6"
wire width 64 $1\clz_sig_in[63:0]
- attribute \src "libresoc.v:149170.3-149188.6"
+ attribute \src "libresoc.v:147300.3-147318.6"
wire width 64 $1\cntz_i[63:0]
- attribute \src "libresoc.v:149148.3-149158.6"
+ attribute \src "libresoc.v:147278.3-147288.6"
wire $1\count_right[0:0]
- attribute \src "libresoc.v:149005.3-149059.6"
+ attribute \src "libresoc.v:147135.3-147189.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:149005.3-149059.6"
+ attribute \src "libresoc.v:147135.3-147189.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:149126.3-149136.6"
+ attribute \src "libresoc.v:147256.3-147266.6"
wire $1\par0[0:0]
- attribute \src "libresoc.v:149137.3-149147.6"
+ attribute \src "libresoc.v:147267.3-147277.6"
wire $1\par1[0:0]
- attribute \src "libresoc.v:149093.3-149103.6"
+ attribute \src "libresoc.v:147223.3-147233.6"
wire width 64 $1\popcount_a[63:0]
- attribute \src "libresoc.v:149115.3-149125.6"
+ attribute \src "libresoc.v:147245.3-147255.6"
wire width 64 $1\popcount_data_len[63:0]
- attribute \src "libresoc.v:149170.3-149188.6"
+ attribute \src "libresoc.v:147300.3-147318.6"
wire width 64 $2\cntz_i[63:0]
- attribute \src "libresoc.v:149005.3-149059.6"
+ attribute \src "libresoc.v:147135.3-147189.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:148952.18-148952.103"
- wire width 64 $and$libresoc.v:148952$7538_Y
- attribute \src "libresoc.v:148911.18-148911.118"
- wire $eq$libresoc.v:148911$7492_Y
- attribute \src "libresoc.v:148912.19-148912.119"
- wire $eq$libresoc.v:148912$7493_Y
- attribute \src "libresoc.v:148913.19-148913.119"
- wire $eq$libresoc.v:148913$7494_Y
- attribute \src "libresoc.v:148914.19-148914.119"
- wire $eq$libresoc.v:148914$7495_Y
- attribute \src "libresoc.v:148915.19-148915.119"
- wire $eq$libresoc.v:148915$7496_Y
- attribute \src "libresoc.v:148916.19-148916.119"
- wire $eq$libresoc.v:148916$7497_Y
- attribute \src "libresoc.v:148917.19-148917.119"
- wire $eq$libresoc.v:148917$7498_Y
- attribute \src "libresoc.v:148918.19-148918.119"
- wire $eq$libresoc.v:148918$7499_Y
- attribute \src "libresoc.v:148919.19-148919.119"
- wire $eq$libresoc.v:148919$7500_Y
- attribute \src "libresoc.v:148920.19-148920.119"
- wire $eq$libresoc.v:148920$7501_Y
- attribute \src "libresoc.v:148921.19-148921.119"
- wire $eq$libresoc.v:148921$7502_Y
- attribute \src "libresoc.v:148922.19-148922.119"
- wire $eq$libresoc.v:148922$7503_Y
- attribute \src "libresoc.v:148923.19-148923.119"
- wire $eq$libresoc.v:148923$7504_Y
- attribute \src "libresoc.v:148924.19-148924.119"
- wire $eq$libresoc.v:148924$7505_Y
- attribute \src "libresoc.v:148925.19-148925.119"
- wire $eq$libresoc.v:148925$7506_Y
- attribute \src "libresoc.v:148926.19-148926.119"
- wire $eq$libresoc.v:148926$7507_Y
- attribute \src "libresoc.v:148927.19-148927.119"
- wire $eq$libresoc.v:148927$7508_Y
- attribute \src "libresoc.v:148928.19-148928.119"
- wire $eq$libresoc.v:148928$7509_Y
- attribute \src "libresoc.v:148929.19-148929.119"
- wire $eq$libresoc.v:148929$7510_Y
- attribute \src "libresoc.v:148930.19-148930.119"
- wire $eq$libresoc.v:148930$7511_Y
- attribute \src "libresoc.v:148931.19-148931.119"
- wire $eq$libresoc.v:148931$7512_Y
- attribute \src "libresoc.v:148932.19-148932.119"
- wire $eq$libresoc.v:148932$7513_Y
- attribute \src "libresoc.v:148933.19-148933.119"
- wire $eq$libresoc.v:148933$7514_Y
- attribute \src "libresoc.v:148934.19-148934.119"
- wire $eq$libresoc.v:148934$7515_Y
- attribute \src "libresoc.v:148935.19-148935.119"
- wire $eq$libresoc.v:148935$7516_Y
- attribute \src "libresoc.v:148936.19-148936.119"
- wire $eq$libresoc.v:148936$7517_Y
- attribute \src "libresoc.v:148937.19-148937.119"
- wire $eq$libresoc.v:148937$7518_Y
- attribute \src "libresoc.v:148938.19-148938.119"
- wire $eq$libresoc.v:148938$7519_Y
- attribute \src "libresoc.v:148939.19-148939.128"
- wire $eq$libresoc.v:148939$7520_Y
- attribute \src "libresoc.v:148955.18-148955.114"
- wire $eq$libresoc.v:148955$7541_Y
- attribute \src "libresoc.v:148956.18-148956.114"
- wire $eq$libresoc.v:148956$7542_Y
- attribute \src "libresoc.v:148957.18-148957.114"
- wire $eq$libresoc.v:148957$7543_Y
- attribute \src "libresoc.v:148958.18-148958.114"
- wire $eq$libresoc.v:148958$7544_Y
- attribute \src "libresoc.v:148959.18-148959.114"
- wire $eq$libresoc.v:148959$7545_Y
- attribute \src "libresoc.v:148960.18-148960.114"
- wire $eq$libresoc.v:148960$7546_Y
- attribute \src "libresoc.v:148961.18-148961.114"
- wire $eq$libresoc.v:148961$7547_Y
- attribute \src "libresoc.v:148962.18-148962.114"
- wire $eq$libresoc.v:148962$7548_Y
- attribute \src "libresoc.v:148963.18-148963.116"
- wire $eq$libresoc.v:148963$7549_Y
- attribute \src "libresoc.v:148964.18-148964.116"
- wire $eq$libresoc.v:148964$7550_Y
- attribute \src "libresoc.v:148965.18-148965.116"
- wire $eq$libresoc.v:148965$7551_Y
- attribute \src "libresoc.v:148966.18-148966.116"
- wire $eq$libresoc.v:148966$7552_Y
- attribute \src "libresoc.v:148967.18-148967.116"
- wire $eq$libresoc.v:148967$7553_Y
- attribute \src "libresoc.v:148968.18-148968.116"
- wire $eq$libresoc.v:148968$7554_Y
- attribute \src "libresoc.v:148969.18-148969.116"
- wire $eq$libresoc.v:148969$7555_Y
- attribute \src "libresoc.v:148970.18-148970.116"
- wire $eq$libresoc.v:148970$7556_Y
- attribute \src "libresoc.v:148971.18-148971.118"
- wire $eq$libresoc.v:148971$7557_Y
- attribute \src "libresoc.v:148972.18-148972.118"
- wire $eq$libresoc.v:148972$7558_Y
- attribute \src "libresoc.v:148973.18-148973.118"
- wire $eq$libresoc.v:148973$7559_Y
- attribute \src "libresoc.v:148974.18-148974.118"
- wire $eq$libresoc.v:148974$7560_Y
- attribute \src "libresoc.v:148975.18-148975.118"
- wire $eq$libresoc.v:148975$7561_Y
- attribute \src "libresoc.v:148976.18-148976.118"
- wire $eq$libresoc.v:148976$7562_Y
- attribute \src "libresoc.v:148977.18-148977.118"
- wire $eq$libresoc.v:148977$7563_Y
- attribute \src "libresoc.v:148978.18-148978.118"
- wire $eq$libresoc.v:148978$7564_Y
- attribute \src "libresoc.v:148979.18-148979.118"
- wire $eq$libresoc.v:148979$7565_Y
- attribute \src "libresoc.v:148980.18-148980.118"
- wire $eq$libresoc.v:148980$7566_Y
- attribute \src "libresoc.v:148981.18-148981.118"
- wire $eq$libresoc.v:148981$7567_Y
- attribute \src "libresoc.v:148982.18-148982.118"
- wire $eq$libresoc.v:148982$7568_Y
- attribute \src "libresoc.v:148983.18-148983.118"
- wire $eq$libresoc.v:148983$7569_Y
- attribute \src "libresoc.v:148984.18-148984.118"
- wire $eq$libresoc.v:148984$7570_Y
- attribute \src "libresoc.v:148985.18-148985.118"
- wire $eq$libresoc.v:148985$7571_Y
- attribute \src "libresoc.v:148986.18-148986.118"
- wire $eq$libresoc.v:148986$7572_Y
- attribute \src "libresoc.v:148987.18-148987.118"
- wire $eq$libresoc.v:148987$7573_Y
- attribute \src "libresoc.v:148988.18-148988.118"
- wire $eq$libresoc.v:148988$7574_Y
- attribute \src "libresoc.v:148989.18-148989.118"
- wire $eq$libresoc.v:148989$7575_Y
- attribute \src "libresoc.v:148990.18-148990.118"
- wire $eq$libresoc.v:148990$7576_Y
- attribute \src "libresoc.v:148941.19-148941.104"
- wire width 64 $extend$libresoc.v:148941$7522_Y
- attribute \src "libresoc.v:148943.19-148943.93"
- wire width 8 $extend$libresoc.v:148943$7525_Y
- attribute \src "libresoc.v:148945.19-148945.105"
- wire width 64 $extend$libresoc.v:148945$7528_Y
- attribute \src "libresoc.v:148946.19-148946.118"
- wire width 64 $extend$libresoc.v:148946$7530_Y
- attribute \src "libresoc.v:148950.19-148950.105"
- wire width 64 $extend$libresoc.v:148950$7535_Y
- attribute \src "libresoc.v:148953.18-148953.103"
- wire width 64 $or$libresoc.v:148953$7539_Y
- attribute \src "libresoc.v:148941.19-148941.104"
- wire width 64 $pos$libresoc.v:148941$7523_Y
- attribute \src "libresoc.v:148943.19-148943.93"
- wire width 8 $pos$libresoc.v:148943$7526_Y
- attribute \src "libresoc.v:148945.19-148945.105"
- wire width 64 $pos$libresoc.v:148945$7529_Y
- attribute \src "libresoc.v:148946.19-148946.118"
- wire width 64 $pos$libresoc.v:148946$7531_Y
- attribute \src "libresoc.v:148950.19-148950.105"
- wire width 64 $pos$libresoc.v:148950$7536_Y
- attribute \src "libresoc.v:148947.19-148947.131"
- wire $reduce_xor$libresoc.v:148947$7532_Y
- attribute \src "libresoc.v:148948.19-148948.133"
- wire $reduce_xor$libresoc.v:148948$7533_Y
- attribute \src "libresoc.v:148942.19-148942.112"
- wire width 8 $sub$libresoc.v:148942$7524_Y
- attribute \src "libresoc.v:148944.19-148944.135"
- wire width 8 $ternary$libresoc.v:148944$7527_Y
- attribute \src "libresoc.v:148949.19-148949.398"
- wire width 32 $ternary$libresoc.v:148949$7534_Y
- attribute \src "libresoc.v:148951.19-148951.621"
- wire width 64 $ternary$libresoc.v:148951$7537_Y
- attribute \src "libresoc.v:148940.19-148940.108"
- wire $xor$libresoc.v:148940$7521_Y
- attribute \src "libresoc.v:148954.18-148954.103"
- wire width 64 $xor$libresoc.v:148954$7540_Y
+ attribute \src "libresoc.v:147082.18-147082.103"
+ wire width 64 $and$libresoc.v:147082$7464_Y
+ attribute \src "libresoc.v:147041.18-147041.118"
+ wire $eq$libresoc.v:147041$7418_Y
+ attribute \src "libresoc.v:147042.19-147042.119"
+ wire $eq$libresoc.v:147042$7419_Y
+ attribute \src "libresoc.v:147043.19-147043.119"
+ wire $eq$libresoc.v:147043$7420_Y
+ attribute \src "libresoc.v:147044.19-147044.119"
+ wire $eq$libresoc.v:147044$7421_Y
+ attribute \src "libresoc.v:147045.19-147045.119"
+ wire $eq$libresoc.v:147045$7422_Y
+ attribute \src "libresoc.v:147046.19-147046.119"
+ wire $eq$libresoc.v:147046$7423_Y
+ attribute \src "libresoc.v:147047.19-147047.119"
+ wire $eq$libresoc.v:147047$7424_Y
+ attribute \src "libresoc.v:147048.19-147048.119"
+ wire $eq$libresoc.v:147048$7425_Y
+ attribute \src "libresoc.v:147049.19-147049.119"
+ wire $eq$libresoc.v:147049$7426_Y
+ attribute \src "libresoc.v:147050.19-147050.119"
+ wire $eq$libresoc.v:147050$7427_Y
+ attribute \src "libresoc.v:147051.19-147051.119"
+ wire $eq$libresoc.v:147051$7428_Y
+ attribute \src "libresoc.v:147052.19-147052.119"
+ wire $eq$libresoc.v:147052$7429_Y
+ attribute \src "libresoc.v:147053.19-147053.119"
+ wire $eq$libresoc.v:147053$7430_Y
+ attribute \src "libresoc.v:147054.19-147054.119"
+ wire $eq$libresoc.v:147054$7431_Y
+ attribute \src "libresoc.v:147055.19-147055.119"
+ wire $eq$libresoc.v:147055$7432_Y
+ attribute \src "libresoc.v:147056.19-147056.119"
+ wire $eq$libresoc.v:147056$7433_Y
+ attribute \src "libresoc.v:147057.19-147057.119"
+ wire $eq$libresoc.v:147057$7434_Y
+ attribute \src "libresoc.v:147058.19-147058.119"
+ wire $eq$libresoc.v:147058$7435_Y
+ attribute \src "libresoc.v:147059.19-147059.119"
+ wire $eq$libresoc.v:147059$7436_Y
+ attribute \src "libresoc.v:147060.19-147060.119"
+ wire $eq$libresoc.v:147060$7437_Y
+ attribute \src "libresoc.v:147061.19-147061.119"
+ wire $eq$libresoc.v:147061$7438_Y
+ attribute \src "libresoc.v:147062.19-147062.119"
+ wire $eq$libresoc.v:147062$7439_Y
+ attribute \src "libresoc.v:147063.19-147063.119"
+ wire $eq$libresoc.v:147063$7440_Y
+ attribute \src "libresoc.v:147064.19-147064.119"
+ wire $eq$libresoc.v:147064$7441_Y
+ attribute \src "libresoc.v:147065.19-147065.119"
+ wire $eq$libresoc.v:147065$7442_Y
+ attribute \src "libresoc.v:147066.19-147066.119"
+ wire $eq$libresoc.v:147066$7443_Y
+ attribute \src "libresoc.v:147067.19-147067.119"
+ wire $eq$libresoc.v:147067$7444_Y
+ attribute \src "libresoc.v:147068.19-147068.119"
+ wire $eq$libresoc.v:147068$7445_Y
+ attribute \src "libresoc.v:147069.19-147069.128"
+ wire $eq$libresoc.v:147069$7446_Y
+ attribute \src "libresoc.v:147085.18-147085.114"
+ wire $eq$libresoc.v:147085$7467_Y
+ attribute \src "libresoc.v:147086.18-147086.114"
+ wire $eq$libresoc.v:147086$7468_Y
+ attribute \src "libresoc.v:147087.18-147087.114"
+ wire $eq$libresoc.v:147087$7469_Y
+ attribute \src "libresoc.v:147088.18-147088.114"
+ wire $eq$libresoc.v:147088$7470_Y
+ attribute \src "libresoc.v:147089.18-147089.114"
+ wire $eq$libresoc.v:147089$7471_Y
+ attribute \src "libresoc.v:147090.18-147090.114"
+ wire $eq$libresoc.v:147090$7472_Y
+ attribute \src "libresoc.v:147091.18-147091.114"
+ wire $eq$libresoc.v:147091$7473_Y
+ attribute \src "libresoc.v:147092.18-147092.114"
+ wire $eq$libresoc.v:147092$7474_Y
+ attribute \src "libresoc.v:147093.18-147093.116"
+ wire $eq$libresoc.v:147093$7475_Y
+ attribute \src "libresoc.v:147094.18-147094.116"
+ wire $eq$libresoc.v:147094$7476_Y
+ attribute \src "libresoc.v:147095.18-147095.116"
+ wire $eq$libresoc.v:147095$7477_Y
+ attribute \src "libresoc.v:147096.18-147096.116"
+ wire $eq$libresoc.v:147096$7478_Y
+ attribute \src "libresoc.v:147097.18-147097.116"
+ wire $eq$libresoc.v:147097$7479_Y
+ attribute \src "libresoc.v:147098.18-147098.116"
+ wire $eq$libresoc.v:147098$7480_Y
+ attribute \src "libresoc.v:147099.18-147099.116"
+ wire $eq$libresoc.v:147099$7481_Y
+ attribute \src "libresoc.v:147100.18-147100.116"
+ wire $eq$libresoc.v:147100$7482_Y
+ attribute \src "libresoc.v:147101.18-147101.118"
+ wire $eq$libresoc.v:147101$7483_Y
+ attribute \src "libresoc.v:147102.18-147102.118"
+ wire $eq$libresoc.v:147102$7484_Y
+ attribute \src "libresoc.v:147103.18-147103.118"
+ wire $eq$libresoc.v:147103$7485_Y
+ attribute \src "libresoc.v:147104.18-147104.118"
+ wire $eq$libresoc.v:147104$7486_Y
+ attribute \src "libresoc.v:147105.18-147105.118"
+ wire $eq$libresoc.v:147105$7487_Y
+ attribute \src "libresoc.v:147106.18-147106.118"
+ wire $eq$libresoc.v:147106$7488_Y
+ attribute \src "libresoc.v:147107.18-147107.118"
+ wire $eq$libresoc.v:147107$7489_Y
+ attribute \src "libresoc.v:147108.18-147108.118"
+ wire $eq$libresoc.v:147108$7490_Y
+ attribute \src "libresoc.v:147109.18-147109.118"
+ wire $eq$libresoc.v:147109$7491_Y
+ attribute \src "libresoc.v:147110.18-147110.118"
+ wire $eq$libresoc.v:147110$7492_Y
+ attribute \src "libresoc.v:147111.18-147111.118"
+ wire $eq$libresoc.v:147111$7493_Y
+ attribute \src "libresoc.v:147112.18-147112.118"
+ wire $eq$libresoc.v:147112$7494_Y
+ attribute \src "libresoc.v:147113.18-147113.118"
+ wire $eq$libresoc.v:147113$7495_Y
+ attribute \src "libresoc.v:147114.18-147114.118"
+ wire $eq$libresoc.v:147114$7496_Y
+ attribute \src "libresoc.v:147115.18-147115.118"
+ wire $eq$libresoc.v:147115$7497_Y
+ attribute \src "libresoc.v:147116.18-147116.118"
+ wire $eq$libresoc.v:147116$7498_Y
+ attribute \src "libresoc.v:147117.18-147117.118"
+ wire $eq$libresoc.v:147117$7499_Y
+ attribute \src "libresoc.v:147118.18-147118.118"
+ wire $eq$libresoc.v:147118$7500_Y
+ attribute \src "libresoc.v:147119.18-147119.118"
+ wire $eq$libresoc.v:147119$7501_Y
+ attribute \src "libresoc.v:147120.18-147120.118"
+ wire $eq$libresoc.v:147120$7502_Y
+ attribute \src "libresoc.v:147071.19-147071.104"
+ wire width 64 $extend$libresoc.v:147071$7448_Y
+ attribute \src "libresoc.v:147073.19-147073.93"
+ wire width 8 $extend$libresoc.v:147073$7451_Y
+ attribute \src "libresoc.v:147075.19-147075.105"
+ wire width 64 $extend$libresoc.v:147075$7454_Y
+ attribute \src "libresoc.v:147076.19-147076.118"
+ wire width 64 $extend$libresoc.v:147076$7456_Y
+ attribute \src "libresoc.v:147080.19-147080.105"
+ wire width 64 $extend$libresoc.v:147080$7461_Y
+ attribute \src "libresoc.v:147083.18-147083.103"
+ wire width 64 $or$libresoc.v:147083$7465_Y
+ attribute \src "libresoc.v:147071.19-147071.104"
+ wire width 64 $pos$libresoc.v:147071$7449_Y
+ attribute \src "libresoc.v:147073.19-147073.93"
+ wire width 8 $pos$libresoc.v:147073$7452_Y
+ attribute \src "libresoc.v:147075.19-147075.105"
+ wire width 64 $pos$libresoc.v:147075$7455_Y
+ attribute \src "libresoc.v:147076.19-147076.118"
+ wire width 64 $pos$libresoc.v:147076$7457_Y
+ attribute \src "libresoc.v:147080.19-147080.105"
+ wire width 64 $pos$libresoc.v:147080$7462_Y
+ attribute \src "libresoc.v:147077.19-147077.131"
+ wire $reduce_xor$libresoc.v:147077$7458_Y
+ attribute \src "libresoc.v:147078.19-147078.133"
+ wire $reduce_xor$libresoc.v:147078$7459_Y
+ attribute \src "libresoc.v:147072.19-147072.112"
+ wire width 8 $sub$libresoc.v:147072$7450_Y
+ attribute \src "libresoc.v:147074.19-147074.135"
+ wire width 8 $ternary$libresoc.v:147074$7453_Y
+ attribute \src "libresoc.v:147079.19-147079.398"
+ wire width 32 $ternary$libresoc.v:147079$7460_Y
+ attribute \src "libresoc.v:147081.19-147081.621"
+ wire width 64 $ternary$libresoc.v:147081$7463_Y
+ attribute \src "libresoc.v:147070.19-147070.108"
+ wire $xor$libresoc.v:147070$7447_Y
+ attribute \src "libresoc.v:147084.18-147084.103"
+ wire width 64 $xor$libresoc.v:147084$7466_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
wire width 64 \cntz_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99"
wire \count_right
- attribute \src "libresoc.v:148448.7-148448.15"
+ attribute \src "libresoc.v:146578.7-146578.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 43 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
- cell $and $and$libresoc.v:148952$7538
+ cell $and $and$libresoc.v:147082$7464
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $and$libresoc.v:148952$7538_Y
+ connect \Y $and$libresoc.v:147082$7464_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148911$7492
+ cell $eq $eq$libresoc.v:147041$7418
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148911$7492_Y
+ connect \Y $eq$libresoc.v:147041$7418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148912$7493
+ cell $eq $eq$libresoc.v:147042$7419
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148912$7493_Y
+ connect \Y $eq$libresoc.v:147042$7419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148913$7494
+ cell $eq $eq$libresoc.v:147043$7420
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148913$7494_Y
+ connect \Y $eq$libresoc.v:147043$7420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148914$7495
+ cell $eq $eq$libresoc.v:147044$7421
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148914$7495_Y
+ connect \Y $eq$libresoc.v:147044$7421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148915$7496
+ cell $eq $eq$libresoc.v:147045$7422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148915$7496_Y
+ connect \Y $eq$libresoc.v:147045$7422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148916$7497
+ cell $eq $eq$libresoc.v:147046$7423
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148916$7497_Y
+ connect \Y $eq$libresoc.v:147046$7423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148917$7498
+ cell $eq $eq$libresoc.v:147047$7424
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148917$7498_Y
+ connect \Y $eq$libresoc.v:147047$7424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148918$7499
+ cell $eq $eq$libresoc.v:147048$7425
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148918$7499_Y
+ connect \Y $eq$libresoc.v:147048$7425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148919$7500
+ cell $eq $eq$libresoc.v:147049$7426
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148919$7500_Y
+ connect \Y $eq$libresoc.v:147049$7426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148920$7501
+ cell $eq $eq$libresoc.v:147050$7427
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148920$7501_Y
+ connect \Y $eq$libresoc.v:147050$7427_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148921$7502
+ cell $eq $eq$libresoc.v:147051$7428
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148921$7502_Y
+ connect \Y $eq$libresoc.v:147051$7428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148922$7503
+ cell $eq $eq$libresoc.v:147052$7429
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [47:40]
connect \B \rb [47:40]
- connect \Y $eq$libresoc.v:148922$7503_Y
+ connect \Y $eq$libresoc.v:147052$7429_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148923$7504
+ cell $eq $eq$libresoc.v:147053$7430
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148923$7504_Y
+ connect \Y $eq$libresoc.v:147053$7430_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148924$7505
+ cell $eq $eq$libresoc.v:147054$7431
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148924$7505_Y
+ connect \Y $eq$libresoc.v:147054$7431_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148925$7506
+ cell $eq $eq$libresoc.v:147055$7432
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148925$7506_Y
+ connect \Y $eq$libresoc.v:147055$7432_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148926$7507
+ cell $eq $eq$libresoc.v:147056$7433
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148926$7507_Y
+ connect \Y $eq$libresoc.v:147056$7433_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148927$7508
+ cell $eq $eq$libresoc.v:147057$7434
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148927$7508_Y
+ connect \Y $eq$libresoc.v:147057$7434_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148928$7509
+ cell $eq $eq$libresoc.v:147058$7435
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148928$7509_Y
+ connect \Y $eq$libresoc.v:147058$7435_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148929$7510
+ cell $eq $eq$libresoc.v:147059$7436
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148929$7510_Y
+ connect \Y $eq$libresoc.v:147059$7436_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148930$7511
+ cell $eq $eq$libresoc.v:147060$7437
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [55:48]
connect \B \rb [55:48]
- connect \Y $eq$libresoc.v:148930$7511_Y
+ connect \Y $eq$libresoc.v:147060$7437_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148931$7512
+ cell $eq $eq$libresoc.v:147061$7438
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148931$7512_Y
+ connect \Y $eq$libresoc.v:147061$7438_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148932$7513
+ cell $eq $eq$libresoc.v:147062$7439
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148932$7513_Y
+ connect \Y $eq$libresoc.v:147062$7439_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148933$7514
+ cell $eq $eq$libresoc.v:147063$7440
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148933$7514_Y
+ connect \Y $eq$libresoc.v:147063$7440_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148934$7515
+ cell $eq $eq$libresoc.v:147064$7441
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148934$7515_Y
+ connect \Y $eq$libresoc.v:147064$7441_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148935$7516
+ cell $eq $eq$libresoc.v:147065$7442
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148935$7516_Y
+ connect \Y $eq$libresoc.v:147065$7442_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148936$7517
+ cell $eq $eq$libresoc.v:147066$7443
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148936$7517_Y
+ connect \Y $eq$libresoc.v:147066$7443_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148937$7518
+ cell $eq $eq$libresoc.v:147067$7444
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148937$7518_Y
+ connect \Y $eq$libresoc.v:147067$7444_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148938$7519
+ cell $eq $eq$libresoc.v:147068$7445
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63:56]
connect \B \rb [63:56]
- connect \Y $eq$libresoc.v:148938$7519_Y
+ connect \Y $eq$libresoc.v:147068$7445_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
- cell $eq $eq$libresoc.v:148939$7520
+ cell $eq $eq$libresoc.v:147069$7446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__data_len [3]
connect \B 1'1
- connect \Y $eq$libresoc.v:148939$7520_Y
+ connect \Y $eq$libresoc.v:147069$7446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148955$7541
+ cell $eq $eq$libresoc.v:147085$7467
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148955$7541_Y
+ connect \Y $eq$libresoc.v:147085$7467_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148956$7542
+ cell $eq $eq$libresoc.v:147086$7468
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148956$7542_Y
+ connect \Y $eq$libresoc.v:147086$7468_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148957$7543
+ cell $eq $eq$libresoc.v:147087$7469
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148957$7543_Y
+ connect \Y $eq$libresoc.v:147087$7469_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148958$7544
+ cell $eq $eq$libresoc.v:147088$7470
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148958$7544_Y
+ connect \Y $eq$libresoc.v:147088$7470_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148959$7545
+ cell $eq $eq$libresoc.v:147089$7471
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148959$7545_Y
+ connect \Y $eq$libresoc.v:147089$7471_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148960$7546
+ cell $eq $eq$libresoc.v:147090$7472
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148960$7546_Y
+ connect \Y $eq$libresoc.v:147090$7472_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148961$7547
+ cell $eq $eq$libresoc.v:147091$7473
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148961$7547_Y
+ connect \Y $eq$libresoc.v:147091$7473_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148962$7548
+ cell $eq $eq$libresoc.v:147092$7474
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [7:0]
connect \B \rb [7:0]
- connect \Y $eq$libresoc.v:148962$7548_Y
+ connect \Y $eq$libresoc.v:147092$7474_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148963$7549
+ cell $eq $eq$libresoc.v:147093$7475
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148963$7549_Y
+ connect \Y $eq$libresoc.v:147093$7475_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148964$7550
+ cell $eq $eq$libresoc.v:147094$7476
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148964$7550_Y
+ connect \Y $eq$libresoc.v:147094$7476_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148965$7551
+ cell $eq $eq$libresoc.v:147095$7477
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148965$7551_Y
+ connect \Y $eq$libresoc.v:147095$7477_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148966$7552
+ cell $eq $eq$libresoc.v:147096$7478
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148966$7552_Y
+ connect \Y $eq$libresoc.v:147096$7478_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148967$7553
+ cell $eq $eq$libresoc.v:147097$7479
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148967$7553_Y
+ connect \Y $eq$libresoc.v:147097$7479_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148968$7554
+ cell $eq $eq$libresoc.v:147098$7480
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148968$7554_Y
+ connect \Y $eq$libresoc.v:147098$7480_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148969$7555
+ cell $eq $eq$libresoc.v:147099$7481
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148969$7555_Y
+ connect \Y $eq$libresoc.v:147099$7481_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148970$7556
+ cell $eq $eq$libresoc.v:147100$7482
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [15:8]
connect \B \rb [15:8]
- connect \Y $eq$libresoc.v:148970$7556_Y
+ connect \Y $eq$libresoc.v:147100$7482_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148971$7557
+ cell $eq $eq$libresoc.v:147101$7483
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148971$7557_Y
+ connect \Y $eq$libresoc.v:147101$7483_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148972$7558
+ cell $eq $eq$libresoc.v:147102$7484
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148972$7558_Y
+ connect \Y $eq$libresoc.v:147102$7484_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148973$7559
+ cell $eq $eq$libresoc.v:147103$7485
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148973$7559_Y
+ connect \Y $eq$libresoc.v:147103$7485_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148974$7560
+ cell $eq $eq$libresoc.v:147104$7486
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148974$7560_Y
+ connect \Y $eq$libresoc.v:147104$7486_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148975$7561
+ cell $eq $eq$libresoc.v:147105$7487
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148975$7561_Y
+ connect \Y $eq$libresoc.v:147105$7487_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148976$7562
+ cell $eq $eq$libresoc.v:147106$7488
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148976$7562_Y
+ connect \Y $eq$libresoc.v:147106$7488_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148977$7563
+ cell $eq $eq$libresoc.v:147107$7489
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148977$7563_Y
+ connect \Y $eq$libresoc.v:147107$7489_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148978$7564
+ cell $eq $eq$libresoc.v:147108$7490
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [23:16]
connect \B \rb [23:16]
- connect \Y $eq$libresoc.v:148978$7564_Y
+ connect \Y $eq$libresoc.v:147108$7490_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148979$7565
+ cell $eq $eq$libresoc.v:147109$7491
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148979$7565_Y
+ connect \Y $eq$libresoc.v:147109$7491_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148980$7566
+ cell $eq $eq$libresoc.v:147110$7492
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148980$7566_Y
+ connect \Y $eq$libresoc.v:147110$7492_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148981$7567
+ cell $eq $eq$libresoc.v:147111$7493
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148981$7567_Y
+ connect \Y $eq$libresoc.v:147111$7493_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148982$7568
+ cell $eq $eq$libresoc.v:147112$7494
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148982$7568_Y
+ connect \Y $eq$libresoc.v:147112$7494_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148983$7569
+ cell $eq $eq$libresoc.v:147113$7495
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148983$7569_Y
+ connect \Y $eq$libresoc.v:147113$7495_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148984$7570
+ cell $eq $eq$libresoc.v:147114$7496
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148984$7570_Y
+ connect \Y $eq$libresoc.v:147114$7496_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148985$7571
+ cell $eq $eq$libresoc.v:147115$7497
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148985$7571_Y
+ connect \Y $eq$libresoc.v:147115$7497_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148986$7572
+ cell $eq $eq$libresoc.v:147116$7498
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31:24]
connect \B \rb [31:24]
- connect \Y $eq$libresoc.v:148986$7572_Y
+ connect \Y $eq$libresoc.v:147116$7498_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148987$7573
+ cell $eq $eq$libresoc.v:147117$7499
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148987$7573_Y
+ connect \Y $eq$libresoc.v:147117$7499_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148988$7574
+ cell $eq $eq$libresoc.v:147118$7500
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148988$7574_Y
+ connect \Y $eq$libresoc.v:147118$7500_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148989$7575
+ cell $eq $eq$libresoc.v:147119$7501
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148989$7575_Y
+ connect \Y $eq$libresoc.v:147119$7501_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67"
- cell $eq $eq$libresoc.v:148990$7576
+ cell $eq $eq$libresoc.v:147120$7502
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [39:32]
connect \B \rb [39:32]
- connect \Y $eq$libresoc.v:148990$7576_Y
+ connect \Y $eq$libresoc.v:147120$7502_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $pos $extend$libresoc.v:148941$7522
+ cell $pos $extend$libresoc.v:147071$7448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 64
connect \A \$158
- connect \Y $extend$libresoc.v:148941$7522_Y
+ connect \Y $extend$libresoc.v:147071$7448_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18"
- cell $pos $extend$libresoc.v:148943$7525
+ cell $pos $extend$libresoc.v:147073$7451
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 8
connect \A \clz_lz
- connect \Y $extend$libresoc.v:148943$7525_Y
+ connect \Y $extend$libresoc.v:147073$7451_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $pos $extend$libresoc.v:148945$7528
+ cell $pos $extend$libresoc.v:147075$7454
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
connect \A \$166
- connect \Y $extend$libresoc.v:148945$7528_Y
+ connect \Y $extend$libresoc.v:147075$7454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $extend$libresoc.v:148946$7530
+ cell $pos $extend$libresoc.v:147076$7456
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 64
connect \A \logical_op__data_len
- connect \Y $extend$libresoc.v:148946$7530_Y
+ connect \Y $extend$libresoc.v:147076$7456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $pos $extend$libresoc.v:148950$7535
+ cell $pos $extend$libresoc.v:147080$7461
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \$176
- connect \Y $extend$libresoc.v:148950$7535_Y
+ connect \Y $extend$libresoc.v:147080$7461_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
- cell $or $or$libresoc.v:148953$7539
+ cell $or $or$libresoc.v:147083$7465
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $or$libresoc.v:148953$7539_Y
+ connect \Y $or$libresoc.v:147083$7465_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $pos $pos$libresoc.v:148941$7523
+ cell $pos $pos$libresoc.v:147071$7449
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:148941$7522_Y
- connect \Y $pos$libresoc.v:148941$7523_Y
+ connect \A $extend$libresoc.v:147071$7448_Y
+ connect \Y $pos$libresoc.v:147071$7449_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18"
- cell $pos $pos$libresoc.v:148943$7526
+ cell $pos $pos$libresoc.v:147073$7452
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:148943$7525_Y
- connect \Y $pos$libresoc.v:148943$7526_Y
+ connect \A $extend$libresoc.v:147073$7451_Y
+ connect \Y $pos$libresoc.v:147073$7452_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $pos $pos$libresoc.v:148945$7529
+ cell $pos $pos$libresoc.v:147075$7455
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:148945$7528_Y
- connect \Y $pos$libresoc.v:148945$7529_Y
+ connect \A $extend$libresoc.v:147075$7454_Y
+ connect \Y $pos$libresoc.v:147075$7455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
- cell $pos $pos$libresoc.v:148946$7531
+ cell $pos $pos$libresoc.v:147076$7457
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:148946$7530_Y
- connect \Y $pos$libresoc.v:148946$7531_Y
+ connect \A $extend$libresoc.v:147076$7456_Y
+ connect \Y $pos$libresoc.v:147076$7457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $pos $pos$libresoc.v:148950$7536
+ cell $pos $pos$libresoc.v:147080$7462
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:148950$7535_Y
- connect \Y $pos$libresoc.v:148950$7536_Y
+ connect \A $extend$libresoc.v:147080$7461_Y
+ connect \Y $pos$libresoc.v:147080$7462_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
- cell $reduce_xor $reduce_xor$libresoc.v:148947$7532
+ cell $reduce_xor $reduce_xor$libresoc.v:147077$7458
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [24] \ra [16] \ra [8] \ra [0] }
- connect \Y $reduce_xor$libresoc.v:148947$7532_Y
+ connect \Y $reduce_xor$libresoc.v:147077$7458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
- cell $reduce_xor $reduce_xor$libresoc.v:148948$7533
+ cell $reduce_xor $reduce_xor$libresoc.v:147078$7459
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [56] \ra [48] \ra [40] \ra [32] }
- connect \Y $reduce_xor$libresoc.v:148948$7533_Y
+ connect \Y $reduce_xor$libresoc.v:147078$7459_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $sub $sub$libresoc.v:148942$7524
+ cell $sub $sub$libresoc.v:147072$7450
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \clz_lz
connect \B 6'100000
- connect \Y $sub$libresoc.v:148942$7524_Y
+ connect \Y $sub$libresoc.v:147072$7450_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113"
- cell $mux $ternary$libresoc.v:148944$7527
+ cell $mux $ternary$libresoc.v:147074$7453
parameter \WIDTH 8
connect \A \$164
connect \B \$162
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:148944$7527_Y
+ connect \Y $ternary$libresoc.v:147074$7453_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
- cell $mux $ternary$libresoc.v:148949$7534
+ cell $mux $ternary$libresoc.v:147079$7460
parameter \WIDTH 32
connect \A \a32
connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] }
connect \S \count_right
- connect \Y $ternary$libresoc.v:148949$7534_Y
+ connect \Y $ternary$libresoc.v:147079$7460_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109"
- cell $mux $ternary$libresoc.v:148951$7537
+ cell $mux $ternary$libresoc.v:147081$7463
parameter \WIDTH 64
connect \A \ra
connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] }
connect \S \count_right
- connect \Y $ternary$libresoc.v:148951$7537_Y
+ connect \Y $ternary$libresoc.v:147081$7463_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
- cell $xor $xor$libresoc.v:148940$7521
+ cell $xor $xor$libresoc.v:147070$7447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \par0
connect \B \par1
- connect \Y $xor$libresoc.v:148940$7521_Y
+ connect \Y $xor$libresoc.v:147070$7447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
- cell $xor $xor$libresoc.v:148954$7540
+ cell $xor $xor$libresoc.v:147084$7466
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $xor$libresoc.v:148954$7540_Y
+ connect \Y $xor$libresoc.v:147084$7466_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:148991.10-148995.4"
+ attribute \src "libresoc.v:147121.10-147125.4"
cell \bpermd \bpermd
connect \ra \bpermd_ra
connect \rb \bpermd_rb
connect \rs \bpermd_rs
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:148996.7-148999.4"
+ attribute \src "libresoc.v:147126.7-147129.4"
cell \clz \clz
connect \lz \clz_lz
connect \sig_in \clz_sig_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:149000.12-149004.4"
+ attribute \src "libresoc.v:147130.12-147134.4"
cell \popcount \popcount
connect \a \popcount_a
connect \data_len \popcount_data_len
connect \o \popcount_o
end
- attribute \src "libresoc.v:148448.7-148448.20"
- process $proc$libresoc.v:148448$7589
+ attribute \src "libresoc.v:146578.7-146578.20"
+ process $proc$libresoc.v:146578$7515
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:149005.3-149059.6"
- process $proc$libresoc.v:149005$7577
+ attribute \src "libresoc.v:147135.3-147189.6"
+ process $proc$libresoc.v:147135$7503
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:149006.5-149006.29"
+ attribute \src "libresoc.v:147136.5-147136.29"
switch \initial
- attribute \src "libresoc.v:149006.9-149006.17"
+ attribute \src "libresoc.v:147136.9-147136.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:149060.3-149070.6"
- process $proc$libresoc.v:149060$7578
+ attribute \src "libresoc.v:147190.3-147200.6"
+ process $proc$libresoc.v:147190$7504
assign { } { }
assign { } { }
assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0]
- attribute \src "libresoc.v:149061.5-149061.29"
+ attribute \src "libresoc.v:147191.5-147191.29"
switch \initial
- attribute \src "libresoc.v:149061.9-149061.17"
+ attribute \src "libresoc.v:147191.9-147191.17"
case 1'1
case
end
sync always
update \clz_sig_in $0\clz_sig_in[63:0]
end
- attribute \src "libresoc.v:149071.3-149081.6"
- process $proc$libresoc.v:149071$7579
+ attribute \src "libresoc.v:147201.3-147211.6"
+ process $proc$libresoc.v:147201$7505
assign { } { }
assign { } { }
assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0]
- attribute \src "libresoc.v:149072.5-149072.29"
+ attribute \src "libresoc.v:147202.5-147202.29"
switch \initial
- attribute \src "libresoc.v:149072.9-149072.17"
+ attribute \src "libresoc.v:147202.9-147202.17"
case 1'1
case
end
sync always
update \bpermd_rs $0\bpermd_rs[63:0]
end
- attribute \src "libresoc.v:149082.3-149092.6"
- process $proc$libresoc.v:149082$7580
+ attribute \src "libresoc.v:147212.3-147222.6"
+ process $proc$libresoc.v:147212$7506
assign { } { }
assign { } { }
assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0]
- attribute \src "libresoc.v:149083.5-149083.29"
+ attribute \src "libresoc.v:147213.5-147213.29"
switch \initial
- attribute \src "libresoc.v:149083.9-149083.17"
+ attribute \src "libresoc.v:147213.9-147213.17"
case 1'1
case
end
sync always
update \bpermd_rb $0\bpermd_rb[63:0]
end
- attribute \src "libresoc.v:149093.3-149103.6"
- process $proc$libresoc.v:149093$7581
+ attribute \src "libresoc.v:147223.3-147233.6"
+ process $proc$libresoc.v:147223$7507
assign { } { }
assign { } { }
assign $0\popcount_a[63:0] $1\popcount_a[63:0]
- attribute \src "libresoc.v:149094.5-149094.29"
+ attribute \src "libresoc.v:147224.5-147224.29"
switch \initial
- attribute \src "libresoc.v:149094.9-149094.17"
+ attribute \src "libresoc.v:147224.9-147224.17"
case 1'1
case
end
sync always
update \popcount_a $0\popcount_a[63:0]
end
- attribute \src "libresoc.v:149104.3-149114.6"
- process $proc$libresoc.v:149104$7582
+ attribute \src "libresoc.v:147234.3-147244.6"
+ process $proc$libresoc.v:147234$7508
assign { } { }
assign { } { }
assign $0\b[63:0] $1\b[63:0]
- attribute \src "libresoc.v:149105.5-149105.29"
+ attribute \src "libresoc.v:147235.5-147235.29"
switch \initial
- attribute \src "libresoc.v:149105.9-149105.17"
+ attribute \src "libresoc.v:147235.9-147235.17"
case 1'1
case
end
sync always
update \b $0\b[63:0]
end
- attribute \src "libresoc.v:149115.3-149125.6"
- process $proc$libresoc.v:149115$7583
+ attribute \src "libresoc.v:147245.3-147255.6"
+ process $proc$libresoc.v:147245$7509
assign { } { }
assign { } { }
assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0]
- attribute \src "libresoc.v:149116.5-149116.29"
+ attribute \src "libresoc.v:147246.5-147246.29"
switch \initial
- attribute \src "libresoc.v:149116.9-149116.17"
+ attribute \src "libresoc.v:147246.9-147246.17"
case 1'1
case
end
sync always
update \popcount_data_len $0\popcount_data_len[63:0]
end
- attribute \src "libresoc.v:149126.3-149136.6"
- process $proc$libresoc.v:149126$7584
+ attribute \src "libresoc.v:147256.3-147266.6"
+ process $proc$libresoc.v:147256$7510
assign { } { }
assign { } { }
assign $0\par0[0:0] $1\par0[0:0]
- attribute \src "libresoc.v:149127.5-149127.29"
+ attribute \src "libresoc.v:147257.5-147257.29"
switch \initial
- attribute \src "libresoc.v:149127.9-149127.17"
+ attribute \src "libresoc.v:147257.9-147257.17"
case 1'1
case
end
sync always
update \par0 $0\par0[0:0]
end
- attribute \src "libresoc.v:149137.3-149147.6"
- process $proc$libresoc.v:149137$7585
+ attribute \src "libresoc.v:147267.3-147277.6"
+ process $proc$libresoc.v:147267$7511
assign { } { }
assign { } { }
assign $0\par1[0:0] $1\par1[0:0]
- attribute \src "libresoc.v:149138.5-149138.29"
+ attribute \src "libresoc.v:147268.5-147268.29"
switch \initial
- attribute \src "libresoc.v:149138.9-149138.17"
+ attribute \src "libresoc.v:147268.9-147268.17"
case 1'1
case
end
sync always
update \par1 $0\par1[0:0]
end
- attribute \src "libresoc.v:149148.3-149158.6"
- process $proc$libresoc.v:149148$7586
+ attribute \src "libresoc.v:147278.3-147288.6"
+ process $proc$libresoc.v:147278$7512
assign { } { }
assign { } { }
assign $0\count_right[0:0] $1\count_right[0:0]
- attribute \src "libresoc.v:149149.5-149149.29"
+ attribute \src "libresoc.v:147279.5-147279.29"
switch \initial
- attribute \src "libresoc.v:149149.9-149149.17"
+ attribute \src "libresoc.v:147279.9-147279.17"
case 1'1
case
end
sync always
update \count_right $0\count_right[0:0]
end
- attribute \src "libresoc.v:149159.3-149169.6"
- process $proc$libresoc.v:149159$7587
+ attribute \src "libresoc.v:147289.3-147299.6"
+ process $proc$libresoc.v:147289$7513
assign { } { }
assign { } { }
assign $0\a32[31:0] $1\a32[31:0]
- attribute \src "libresoc.v:149160.5-149160.29"
+ attribute \src "libresoc.v:147290.5-147290.29"
switch \initial
- attribute \src "libresoc.v:149160.9-149160.17"
+ attribute \src "libresoc.v:147290.9-147290.17"
case 1'1
case
end
sync always
update \a32 $0\a32[31:0]
end
- attribute \src "libresoc.v:149170.3-149188.6"
- process $proc$libresoc.v:149170$7588
+ attribute \src "libresoc.v:147300.3-147318.6"
+ process $proc$libresoc.v:147300$7514
assign { } { }
assign { } { }
assign $0\cntz_i[63:0] $1\cntz_i[63:0]
- attribute \src "libresoc.v:149171.5-149171.29"
+ attribute \src "libresoc.v:147301.5-147301.29"
switch \initial
- attribute \src "libresoc.v:149171.9-149171.17"
+ attribute \src "libresoc.v:147301.9-147301.17"
case 1'1
case
end
sync always
update \cntz_i $0\cntz_i[63:0]
end
- connect \$99 $eq$libresoc.v:148911$7492_Y
- connect \$101 $eq$libresoc.v:148912$7493_Y
- connect \$103 $eq$libresoc.v:148913$7494_Y
- connect \$105 $eq$libresoc.v:148914$7495_Y
- connect \$107 $eq$libresoc.v:148915$7496_Y
- connect \$109 $eq$libresoc.v:148916$7497_Y
- connect \$111 $eq$libresoc.v:148917$7498_Y
- connect \$113 $eq$libresoc.v:148918$7499_Y
- connect \$115 $eq$libresoc.v:148919$7500_Y
- connect \$117 $eq$libresoc.v:148920$7501_Y
- connect \$119 $eq$libresoc.v:148921$7502_Y
- connect \$121 $eq$libresoc.v:148922$7503_Y
- connect \$123 $eq$libresoc.v:148923$7504_Y
- connect \$125 $eq$libresoc.v:148924$7505_Y
- connect \$127 $eq$libresoc.v:148925$7506_Y
- connect \$129 $eq$libresoc.v:148926$7507_Y
- connect \$131 $eq$libresoc.v:148927$7508_Y
- connect \$133 $eq$libresoc.v:148928$7509_Y
- connect \$135 $eq$libresoc.v:148929$7510_Y
- connect \$137 $eq$libresoc.v:148930$7511_Y
- connect \$139 $eq$libresoc.v:148931$7512_Y
- connect \$141 $eq$libresoc.v:148932$7513_Y
- connect \$143 $eq$libresoc.v:148933$7514_Y
- connect \$145 $eq$libresoc.v:148934$7515_Y
- connect \$147 $eq$libresoc.v:148935$7516_Y
- connect \$149 $eq$libresoc.v:148936$7517_Y
- connect \$151 $eq$libresoc.v:148937$7518_Y
- connect \$153 $eq$libresoc.v:148938$7519_Y
- connect \$155 $eq$libresoc.v:148939$7520_Y
- connect \$158 $xor$libresoc.v:148940$7521_Y
- connect \$157 $pos$libresoc.v:148941$7523_Y
- connect \$162 $sub$libresoc.v:148942$7524_Y
- connect \$164 $pos$libresoc.v:148943$7526_Y
- connect \$166 $ternary$libresoc.v:148944$7527_Y
- connect \$161 $pos$libresoc.v:148945$7529_Y
- connect \$169 $pos$libresoc.v:148946$7531_Y
- connect \$171 $reduce_xor$libresoc.v:148947$7532_Y
- connect \$173 $reduce_xor$libresoc.v:148948$7533_Y
- connect \$176 $ternary$libresoc.v:148949$7534_Y
- connect \$175 $pos$libresoc.v:148950$7536_Y
- connect \$179 $ternary$libresoc.v:148951$7537_Y
- connect \$21 $and$libresoc.v:148952$7538_Y
- connect \$23 $or$libresoc.v:148953$7539_Y
- connect \$25 $xor$libresoc.v:148954$7540_Y
- connect \$27 $eq$libresoc.v:148955$7541_Y
- connect \$29 $eq$libresoc.v:148956$7542_Y
- connect \$31 $eq$libresoc.v:148957$7543_Y
- connect \$33 $eq$libresoc.v:148958$7544_Y
- connect \$35 $eq$libresoc.v:148959$7545_Y
- connect \$37 $eq$libresoc.v:148960$7546_Y
- connect \$39 $eq$libresoc.v:148961$7547_Y
- connect \$41 $eq$libresoc.v:148962$7548_Y
- connect \$43 $eq$libresoc.v:148963$7549_Y
- connect \$45 $eq$libresoc.v:148964$7550_Y
- connect \$47 $eq$libresoc.v:148965$7551_Y
- connect \$49 $eq$libresoc.v:148966$7552_Y
- connect \$51 $eq$libresoc.v:148967$7553_Y
- connect \$53 $eq$libresoc.v:148968$7554_Y
- connect \$55 $eq$libresoc.v:148969$7555_Y
- connect \$57 $eq$libresoc.v:148970$7556_Y
- connect \$59 $eq$libresoc.v:148971$7557_Y
- connect \$61 $eq$libresoc.v:148972$7558_Y
- connect \$63 $eq$libresoc.v:148973$7559_Y
- connect \$65 $eq$libresoc.v:148974$7560_Y
- connect \$67 $eq$libresoc.v:148975$7561_Y
- connect \$69 $eq$libresoc.v:148976$7562_Y
- connect \$71 $eq$libresoc.v:148977$7563_Y
- connect \$73 $eq$libresoc.v:148978$7564_Y
- connect \$75 $eq$libresoc.v:148979$7565_Y
- connect \$77 $eq$libresoc.v:148980$7566_Y
- connect \$79 $eq$libresoc.v:148981$7567_Y
- connect \$81 $eq$libresoc.v:148982$7568_Y
- connect \$83 $eq$libresoc.v:148983$7569_Y
- connect \$85 $eq$libresoc.v:148984$7570_Y
- connect \$87 $eq$libresoc.v:148985$7571_Y
- connect \$89 $eq$libresoc.v:148986$7572_Y
- connect \$91 $eq$libresoc.v:148987$7573_Y
- connect \$93 $eq$libresoc.v:148988$7574_Y
- connect \$95 $eq$libresoc.v:148989$7575_Y
- connect \$97 $eq$libresoc.v:148990$7576_Y
+ connect \$99 $eq$libresoc.v:147041$7418_Y
+ connect \$101 $eq$libresoc.v:147042$7419_Y
+ connect \$103 $eq$libresoc.v:147043$7420_Y
+ connect \$105 $eq$libresoc.v:147044$7421_Y
+ connect \$107 $eq$libresoc.v:147045$7422_Y
+ connect \$109 $eq$libresoc.v:147046$7423_Y
+ connect \$111 $eq$libresoc.v:147047$7424_Y
+ connect \$113 $eq$libresoc.v:147048$7425_Y
+ connect \$115 $eq$libresoc.v:147049$7426_Y
+ connect \$117 $eq$libresoc.v:147050$7427_Y
+ connect \$119 $eq$libresoc.v:147051$7428_Y
+ connect \$121 $eq$libresoc.v:147052$7429_Y
+ connect \$123 $eq$libresoc.v:147053$7430_Y
+ connect \$125 $eq$libresoc.v:147054$7431_Y
+ connect \$127 $eq$libresoc.v:147055$7432_Y
+ connect \$129 $eq$libresoc.v:147056$7433_Y
+ connect \$131 $eq$libresoc.v:147057$7434_Y
+ connect \$133 $eq$libresoc.v:147058$7435_Y
+ connect \$135 $eq$libresoc.v:147059$7436_Y
+ connect \$137 $eq$libresoc.v:147060$7437_Y
+ connect \$139 $eq$libresoc.v:147061$7438_Y
+ connect \$141 $eq$libresoc.v:147062$7439_Y
+ connect \$143 $eq$libresoc.v:147063$7440_Y
+ connect \$145 $eq$libresoc.v:147064$7441_Y
+ connect \$147 $eq$libresoc.v:147065$7442_Y
+ connect \$149 $eq$libresoc.v:147066$7443_Y
+ connect \$151 $eq$libresoc.v:147067$7444_Y
+ connect \$153 $eq$libresoc.v:147068$7445_Y
+ connect \$155 $eq$libresoc.v:147069$7446_Y
+ connect \$158 $xor$libresoc.v:147070$7447_Y
+ connect \$157 $pos$libresoc.v:147071$7449_Y
+ connect \$162 $sub$libresoc.v:147072$7450_Y
+ connect \$164 $pos$libresoc.v:147073$7452_Y
+ connect \$166 $ternary$libresoc.v:147074$7453_Y
+ connect \$161 $pos$libresoc.v:147075$7455_Y
+ connect \$169 $pos$libresoc.v:147076$7457_Y
+ connect \$171 $reduce_xor$libresoc.v:147077$7458_Y
+ connect \$173 $reduce_xor$libresoc.v:147078$7459_Y
+ connect \$176 $ternary$libresoc.v:147079$7460_Y
+ connect \$175 $pos$libresoc.v:147080$7462_Y
+ connect \$179 $ternary$libresoc.v:147081$7463_Y
+ connect \$21 $and$libresoc.v:147082$7464_Y
+ connect \$23 $or$libresoc.v:147083$7465_Y
+ connect \$25 $xor$libresoc.v:147084$7466_Y
+ connect \$27 $eq$libresoc.v:147085$7467_Y
+ connect \$29 $eq$libresoc.v:147086$7468_Y
+ connect \$31 $eq$libresoc.v:147087$7469_Y
+ connect \$33 $eq$libresoc.v:147088$7470_Y
+ connect \$35 $eq$libresoc.v:147089$7471_Y
+ connect \$37 $eq$libresoc.v:147090$7472_Y
+ connect \$39 $eq$libresoc.v:147091$7473_Y
+ connect \$41 $eq$libresoc.v:147092$7474_Y
+ connect \$43 $eq$libresoc.v:147093$7475_Y
+ connect \$45 $eq$libresoc.v:147094$7476_Y
+ connect \$47 $eq$libresoc.v:147095$7477_Y
+ connect \$49 $eq$libresoc.v:147096$7478_Y
+ connect \$51 $eq$libresoc.v:147097$7479_Y
+ connect \$53 $eq$libresoc.v:147098$7480_Y
+ connect \$55 $eq$libresoc.v:147099$7481_Y
+ connect \$57 $eq$libresoc.v:147100$7482_Y
+ connect \$59 $eq$libresoc.v:147101$7483_Y
+ connect \$61 $eq$libresoc.v:147102$7484_Y
+ connect \$63 $eq$libresoc.v:147103$7485_Y
+ connect \$65 $eq$libresoc.v:147104$7486_Y
+ connect \$67 $eq$libresoc.v:147105$7487_Y
+ connect \$69 $eq$libresoc.v:147106$7488_Y
+ connect \$71 $eq$libresoc.v:147107$7489_Y
+ connect \$73 $eq$libresoc.v:147108$7490_Y
+ connect \$75 $eq$libresoc.v:147109$7491_Y
+ connect \$77 $eq$libresoc.v:147110$7492_Y
+ connect \$79 $eq$libresoc.v:147111$7493_Y
+ connect \$81 $eq$libresoc.v:147112$7494_Y
+ connect \$83 $eq$libresoc.v:147113$7495_Y
+ connect \$85 $eq$libresoc.v:147114$7496_Y
+ connect \$87 $eq$libresoc.v:147115$7497_Y
+ connect \$89 $eq$libresoc.v:147116$7498_Y
+ connect \$91 $eq$libresoc.v:147117$7499_Y
+ connect \$93 $eq$libresoc.v:147118$7500_Y
+ connect \$95 $eq$libresoc.v:147119$7501_Y
+ connect \$97 $eq$libresoc.v:147120$7502_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$20 \xer_so
end
-attribute \src "libresoc.v:149196.1-149707.10"
+attribute \src "libresoc.v:147326.1-147837.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main"
attribute \generator "nMigen"
module \main$9
- attribute \src "libresoc.v:149562.3-149572.6"
+ attribute \src "libresoc.v:147692.3-147702.6"
wire width 2 $0\BC[1:0]
- attribute \src "libresoc.v:149616.3-149626.6"
+ attribute \src "libresoc.v:147746.3-147756.6"
wire width 2 $0\ba[1:0]
- attribute \src "libresoc.v:149627.3-149637.6"
+ attribute \src "libresoc.v:147757.3-147767.6"
wire width 2 $0\bb[1:0]
- attribute \src "libresoc.v:149638.3-149658.6"
+ attribute \src "libresoc.v:147768.3-147788.6"
wire $0\bit_a[0:0]
- attribute \src "libresoc.v:149659.3-149679.6"
+ attribute \src "libresoc.v:147789.3-147809.6"
wire $0\bit_b[0:0]
- attribute \src "libresoc.v:149680.3-149690.6"
+ attribute \src "libresoc.v:147810.3-147820.6"
wire $0\bit_o[0:0]
- attribute \src "libresoc.v:149605.3-149615.6"
+ attribute \src "libresoc.v:147735.3-147745.6"
wire width 2 $0\bt[1:0]
- attribute \src "libresoc.v:149474.3-149508.6"
- wire width 4 $0\cr_a$6[3:0]$7604
- attribute \src "libresoc.v:149474.3-149508.6"
+ attribute \src "libresoc.v:147604.3-147638.6"
+ wire width 4 $0\cr_a$6[3:0]$7530
+ attribute \src "libresoc.v:147604.3-147638.6"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:149573.3-149593.6"
+ attribute \src "libresoc.v:147703.3-147723.6"
wire $0\cr_bit[0:0]
- attribute \src "libresoc.v:149691.3-149701.6"
- wire width 32 $0\full_cr$5[31:0]$7619
- attribute \src "libresoc.v:149509.3-149519.6"
+ attribute \src "libresoc.v:147821.3-147831.6"
+ wire width 32 $0\full_cr$5[31:0]$7545
+ attribute \src "libresoc.v:147639.3-147649.6"
wire $0\full_cr_ok[0:0]
- attribute \src "libresoc.v:149197.7-149197.20"
+ attribute \src "libresoc.v:147327.7-147327.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:149594.3-149604.6"
+ attribute \src "libresoc.v:147724.3-147734.6"
wire width 4 $0\lut[3:0]
- attribute \src "libresoc.v:149520.3-149561.6"
+ attribute \src "libresoc.v:147650.3-147691.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:149520.3-149561.6"
+ attribute \src "libresoc.v:147650.3-147691.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:149562.3-149572.6"
+ attribute \src "libresoc.v:147692.3-147702.6"
wire width 2 $1\BC[1:0]
- attribute \src "libresoc.v:149616.3-149626.6"
+ attribute \src "libresoc.v:147746.3-147756.6"
wire width 2 $1\ba[1:0]
- attribute \src "libresoc.v:149627.3-149637.6"
+ attribute \src "libresoc.v:147757.3-147767.6"
wire width 2 $1\bb[1:0]
- attribute \src "libresoc.v:149638.3-149658.6"
+ attribute \src "libresoc.v:147768.3-147788.6"
wire $1\bit_a[0:0]
- attribute \src "libresoc.v:149659.3-149679.6"
+ attribute \src "libresoc.v:147789.3-147809.6"
wire $1\bit_b[0:0]
- attribute \src "libresoc.v:149680.3-149690.6"
+ attribute \src "libresoc.v:147810.3-147820.6"
wire $1\bit_o[0:0]
- attribute \src "libresoc.v:149605.3-149615.6"
+ attribute \src "libresoc.v:147735.3-147745.6"
wire width 2 $1\bt[1:0]
- attribute \src "libresoc.v:149474.3-149508.6"
- wire width 4 $1\cr_a$6[3:0]$7605
- attribute \src "libresoc.v:149474.3-149508.6"
+ attribute \src "libresoc.v:147604.3-147638.6"
+ wire width 4 $1\cr_a$6[3:0]$7531
+ attribute \src "libresoc.v:147604.3-147638.6"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:149573.3-149593.6"
+ attribute \src "libresoc.v:147703.3-147723.6"
wire $1\cr_bit[0:0]
- attribute \src "libresoc.v:149691.3-149701.6"
- wire width 32 $1\full_cr$5[31:0]$7620
- attribute \src "libresoc.v:149509.3-149519.6"
+ attribute \src "libresoc.v:147821.3-147831.6"
+ wire width 32 $1\full_cr$5[31:0]$7546
+ attribute \src "libresoc.v:147639.3-147649.6"
wire $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:149594.3-149604.6"
+ attribute \src "libresoc.v:147724.3-147734.6"
wire width 4 $1\lut[3:0]
- attribute \src "libresoc.v:149520.3-149561.6"
+ attribute \src "libresoc.v:147650.3-147691.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:149520.3-149561.6"
+ attribute \src "libresoc.v:147650.3-147691.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:149638.3-149658.6"
+ attribute \src "libresoc.v:147768.3-147788.6"
wire $2\bit_a[0:0]
- attribute \src "libresoc.v:149659.3-149679.6"
+ attribute \src "libresoc.v:147789.3-147809.6"
wire $2\bit_b[0:0]
- attribute \src "libresoc.v:149474.3-149508.6"
- wire width 4 $2\cr_a$6[3:0]$7606
- attribute \src "libresoc.v:149573.3-149593.6"
+ attribute \src "libresoc.v:147604.3-147638.6"
+ wire width 4 $2\cr_a$6[3:0]$7532
+ attribute \src "libresoc.v:147703.3-147723.6"
wire $2\cr_bit[0:0]
- attribute \src "libresoc.v:149520.3-149561.6"
+ attribute \src "libresoc.v:147650.3-147691.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:149470.18-149470.96"
- wire width 64 $extend$libresoc.v:149470$7596_Y
- attribute \src "libresoc.v:149472.18-149472.98"
- wire width 65 $extend$libresoc.v:149472$7599_Y
- attribute \src "libresoc.v:149473.17-149473.92"
- wire width 5 $extend$libresoc.v:149473$7601_Y
- attribute \src "libresoc.v:149470.18-149470.96"
- wire width 64 $pos$libresoc.v:149470$7597_Y
- attribute \src "libresoc.v:149472.18-149472.98"
- wire width 65 $pos$libresoc.v:149472$7600_Y
- attribute \src "libresoc.v:149473.17-149473.92"
- wire width 5 $pos$libresoc.v:149473$7602_Y
- attribute \src "libresoc.v:149464.18-149464.116"
- wire width 3 $sub$libresoc.v:149464$7590_Y
- attribute \src "libresoc.v:149465.18-149465.116"
- wire width 3 $sub$libresoc.v:149465$7591_Y
- attribute \src "libresoc.v:149466.18-149466.116"
- wire width 3 $sub$libresoc.v:149466$7592_Y
- attribute \src "libresoc.v:149467.18-149467.114"
- wire $ternary$libresoc.v:149467$7593_Y
- attribute \src "libresoc.v:149468.18-149468.115"
- wire $ternary$libresoc.v:149468$7594_Y
- attribute \src "libresoc.v:149469.18-149469.112"
- wire $ternary$libresoc.v:149469$7595_Y
- attribute \src "libresoc.v:149471.18-149471.108"
- wire width 64 $ternary$libresoc.v:149471$7598_Y
+ attribute \src "libresoc.v:147600.18-147600.96"
+ wire width 64 $extend$libresoc.v:147600$7522_Y
+ attribute \src "libresoc.v:147602.18-147602.98"
+ wire width 65 $extend$libresoc.v:147602$7525_Y
+ attribute \src "libresoc.v:147603.17-147603.92"
+ wire width 5 $extend$libresoc.v:147603$7527_Y
+ attribute \src "libresoc.v:147600.18-147600.96"
+ wire width 64 $pos$libresoc.v:147600$7523_Y
+ attribute \src "libresoc.v:147602.18-147602.98"
+ wire width 65 $pos$libresoc.v:147602$7526_Y
+ attribute \src "libresoc.v:147603.17-147603.92"
+ wire width 5 $pos$libresoc.v:147603$7528_Y
+ attribute \src "libresoc.v:147594.18-147594.116"
+ wire width 3 $sub$libresoc.v:147594$7516_Y
+ attribute \src "libresoc.v:147595.18-147595.116"
+ wire width 3 $sub$libresoc.v:147595$7517_Y
+ attribute \src "libresoc.v:147596.18-147596.116"
+ wire width 3 $sub$libresoc.v:147596$7518_Y
+ attribute \src "libresoc.v:147597.18-147597.114"
+ wire $ternary$libresoc.v:147597$7519_Y
+ attribute \src "libresoc.v:147598.18-147598.115"
+ wire $ternary$libresoc.v:147598$7520_Y
+ attribute \src "libresoc.v:147599.18-147599.112"
+ wire $ternary$libresoc.v:147599$7521_Y
+ attribute \src "libresoc.v:147601.18-147601.108"
+ wire width 64 $ternary$libresoc.v:147601$7524_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86"
wire width 3 \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87"
wire width 32 output 16 \full_cr$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 17 \full_cr_ok
- attribute \src "libresoc.v:149197.7-149197.15"
+ attribute \src "libresoc.v:147327.7-147327.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70"
wire width 4 \lut
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 5 \rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:149470$7596
+ cell $pos $extend$libresoc.v:147600$7522
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \full_cr
- connect \Y $extend$libresoc.v:149470$7596_Y
+ connect \Y $extend$libresoc.v:147600$7522_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $pos $extend$libresoc.v:149472$7599
+ cell $pos $extend$libresoc.v:147602$7525
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$27
- connect \Y $extend$libresoc.v:149472$7599_Y
+ connect \Y $extend$libresoc.v:147602$7525_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:149473$7601
+ cell $pos $extend$libresoc.v:147603$7527
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 5
connect \A \cr_a
- connect \Y $extend$libresoc.v:149473$7601_Y
+ connect \Y $extend$libresoc.v:147603$7527_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:149470$7597
+ cell $pos $pos$libresoc.v:147600$7523
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:149470$7596_Y
- connect \Y $pos$libresoc.v:149470$7597_Y
+ connect \A $extend$libresoc.v:147600$7522_Y
+ connect \Y $pos$libresoc.v:147600$7523_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $pos $pos$libresoc.v:149472$7600
+ cell $pos $pos$libresoc.v:147602$7526
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:149472$7599_Y
- connect \Y $pos$libresoc.v:149472$7600_Y
+ connect \A $extend$libresoc.v:147602$7525_Y
+ connect \Y $pos$libresoc.v:147602$7526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:149473$7602
+ cell $pos $pos$libresoc.v:147603$7528
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
- connect \A $extend$libresoc.v:149473$7601_Y
- connect \Y $pos$libresoc.v:149473$7602_Y
+ connect \A $extend$libresoc.v:147603$7527_Y
+ connect \Y $pos$libresoc.v:147603$7528_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86"
- cell $sub $sub$libresoc.v:149464$7590
+ cell $sub $sub$libresoc.v:147594$7516
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [22:21]
- connect \Y $sub$libresoc.v:149464$7590_Y
+ connect \Y $sub$libresoc.v:147594$7516_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87"
- cell $sub $sub$libresoc.v:149465$7591
+ cell $sub $sub$libresoc.v:147595$7517
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [17:16]
- connect \Y $sub$libresoc.v:149465$7591_Y
+ connect \Y $sub$libresoc.v:147595$7517_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88"
- cell $sub $sub$libresoc.v:149466$7592
+ cell $sub $sub$libresoc.v:147596$7518
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \cr_op__insn [12:11]
- connect \Y $sub$libresoc.v:149466$7592_Y
+ connect \Y $sub$libresoc.v:147596$7518_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99"
- cell $mux $ternary$libresoc.v:149467$7593
+ cell $mux $ternary$libresoc.v:147597$7519
parameter \WIDTH 1
connect \A \lut [1]
connect \B \lut [3]
connect \S \bit_a
- connect \Y $ternary$libresoc.v:149467$7593_Y
+ connect \Y $ternary$libresoc.v:147597$7519_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100"
- cell $mux $ternary$libresoc.v:149468$7594
+ cell $mux $ternary$libresoc.v:147598$7520
parameter \WIDTH 1
connect \A \lut [0]
connect \B \lut [2]
connect \S \bit_a
- connect \Y $ternary$libresoc.v:149468$7594_Y
+ connect \Y $ternary$libresoc.v:147598$7520_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100"
- cell $mux $ternary$libresoc.v:149469$7595
+ cell $mux $ternary$libresoc.v:147599$7521
parameter \WIDTH 1
connect \A \$20
connect \B \$18
connect \S \bit_b
- connect \Y $ternary$libresoc.v:149469$7595_Y
+ connect \Y $ternary$libresoc.v:147599$7521_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140"
- cell $mux $ternary$libresoc.v:149471$7598
+ cell $mux $ternary$libresoc.v:147601$7524
parameter \WIDTH 64
connect \A \rb
connect \B \ra
connect \S \cr_bit
- connect \Y $ternary$libresoc.v:149471$7598_Y
+ connect \Y $ternary$libresoc.v:147601$7524_Y
end
- attribute \src "libresoc.v:149197.7-149197.20"
- process $proc$libresoc.v:149197$7621
+ attribute \src "libresoc.v:147327.7-147327.20"
+ process $proc$libresoc.v:147327$7547
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:149474.3-149508.6"
- process $proc$libresoc.v:149474$7603
+ attribute \src "libresoc.v:147604.3-147638.6"
+ process $proc$libresoc.v:147604$7529
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0]
- assign $0\cr_a$6[3:0]$7604 $1\cr_a$6[3:0]$7605
- attribute \src "libresoc.v:149475.5-149475.29"
+ assign $0\cr_a$6[3:0]$7530 $1\cr_a$6[3:0]$7531
+ attribute \src "libresoc.v:147605.5-147605.29"
switch \initial
- attribute \src "libresoc.v:149475.9-149475.17"
+ attribute \src "libresoc.v:147605.9-147605.17"
case 1'1
case
end
case 7'0101010
assign { } { }
assign { } { }
- assign $1\cr_a$6[3:0]$7605 \$7 [3:0]
+ assign $1\cr_a$6[3:0]$7531 \$7 [3:0]
assign $1\cr_a_ok[0:0] 1'1
attribute \src "libresoc.v:0.0-0.0"
case 7'1000101
assign { } { }
assign { } { }
assign { } { }
- assign $1\cr_a$6[3:0]$7605 $2\cr_a$6[3:0]$7606
+ assign $1\cr_a$6[3:0]$7531 $2\cr_a$6[3:0]$7532
assign $1\cr_a_ok[0:0] 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105"
switch \bt
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $2\cr_a$6[3:0]$7606 [3:1] \cr_c [3:1]
- assign $2\cr_a$6[3:0]$7606 [0] \bit_o
+ assign $2\cr_a$6[3:0]$7532 [3:1] \cr_c [3:1]
+ assign $2\cr_a$6[3:0]$7532 [0] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'01
- assign { $2\cr_a$6[3:0]$7606 [3:2] $2\cr_a$6[3:0]$7606 [0] } { \cr_c [3:2] \cr_c [0] }
- assign $2\cr_a$6[3:0]$7606 [1] \bit_o
+ assign { $2\cr_a$6[3:0]$7532 [3:2] $2\cr_a$6[3:0]$7532 [0] } { \cr_c [3:2] \cr_c [0] }
+ assign $2\cr_a$6[3:0]$7532 [1] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'10
- assign { $2\cr_a$6[3:0]$7606 [3] $2\cr_a$6[3:0]$7606 [1:0] } { \cr_c [3] \cr_c [1:0] }
- assign $2\cr_a$6[3:0]$7606 [2] \bit_o
+ assign { $2\cr_a$6[3:0]$7532 [3] $2\cr_a$6[3:0]$7532 [1:0] } { \cr_c [3] \cr_c [1:0] }
+ assign $2\cr_a$6[3:0]$7532 [2] \bit_o
attribute \src "libresoc.v:0.0-0.0"
case 2'--
- assign $2\cr_a$6[3:0]$7606 [2:0] \cr_c [2:0]
- assign $2\cr_a$6[3:0]$7606 [3] \bit_o
+ assign $2\cr_a$6[3:0]$7532 [2:0] \cr_c [2:0]
+ assign $2\cr_a$6[3:0]$7532 [3] \bit_o
case
- assign $2\cr_a$6[3:0]$7606 \cr_c
+ assign $2\cr_a$6[3:0]$7532 \cr_c
end
case
assign $1\cr_a_ok[0:0] 1'0
- assign $1\cr_a$6[3:0]$7605 4'0000
+ assign $1\cr_a$6[3:0]$7531 4'0000
end
sync always
update \cr_a_ok $0\cr_a_ok[0:0]
- update \cr_a$6 $0\cr_a$6[3:0]$7604
+ update \cr_a$6 $0\cr_a$6[3:0]$7530
end
- attribute \src "libresoc.v:149509.3-149519.6"
- process $proc$libresoc.v:149509$7607
+ attribute \src "libresoc.v:147639.3-147649.6"
+ process $proc$libresoc.v:147639$7533
assign { } { }
assign { } { }
assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:149510.5-149510.29"
+ attribute \src "libresoc.v:147640.5-147640.29"
switch \initial
- attribute \src "libresoc.v:149510.9-149510.17"
+ attribute \src "libresoc.v:147640.9-147640.17"
case 1'1
case
end
sync always
update \full_cr_ok $0\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:149520.3-149561.6"
- process $proc$libresoc.v:149520$7608
+ attribute \src "libresoc.v:147650.3-147691.6"
+ process $proc$libresoc.v:147650$7534
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:149521.5-149521.29"
+ attribute \src "libresoc.v:147651.5-147651.29"
switch \initial
- attribute \src "libresoc.v:149521.9-149521.17"
+ attribute \src "libresoc.v:147651.9-147651.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:149562.3-149572.6"
- process $proc$libresoc.v:149562$7609
+ attribute \src "libresoc.v:147692.3-147702.6"
+ process $proc$libresoc.v:147692$7535
assign { } { }
assign { } { }
assign $0\BC[1:0] $1\BC[1:0]
- attribute \src "libresoc.v:149563.5-149563.29"
+ attribute \src "libresoc.v:147693.5-147693.29"
switch \initial
- attribute \src "libresoc.v:149563.9-149563.17"
+ attribute \src "libresoc.v:147693.9-147693.17"
case 1'1
case
end
sync always
update \BC $0\BC[1:0]
end
- attribute \src "libresoc.v:149573.3-149593.6"
- process $proc$libresoc.v:149573$7610
+ attribute \src "libresoc.v:147703.3-147723.6"
+ process $proc$libresoc.v:147703$7536
assign { } { }
assign { } { }
assign $0\cr_bit[0:0] $1\cr_bit[0:0]
- attribute \src "libresoc.v:149574.5-149574.29"
+ attribute \src "libresoc.v:147704.5-147704.29"
switch \initial
- attribute \src "libresoc.v:149574.9-149574.17"
+ attribute \src "libresoc.v:147704.9-147704.17"
case 1'1
case
end
sync always
update \cr_bit $0\cr_bit[0:0]
end
- attribute \src "libresoc.v:149594.3-149604.6"
- process $proc$libresoc.v:149594$7611
+ attribute \src "libresoc.v:147724.3-147734.6"
+ process $proc$libresoc.v:147724$7537
assign { } { }
assign { } { }
assign $0\lut[3:0] $1\lut[3:0]
- attribute \src "libresoc.v:149595.5-149595.29"
+ attribute \src "libresoc.v:147725.5-147725.29"
switch \initial
- attribute \src "libresoc.v:149595.9-149595.17"
+ attribute \src "libresoc.v:147725.9-147725.17"
case 1'1
case
end
sync always
update \lut $0\lut[3:0]
end
- attribute \src "libresoc.v:149605.3-149615.6"
- process $proc$libresoc.v:149605$7612
+ attribute \src "libresoc.v:147735.3-147745.6"
+ process $proc$libresoc.v:147735$7538
assign { } { }
assign { } { }
assign $0\bt[1:0] $1\bt[1:0]
- attribute \src "libresoc.v:149606.5-149606.29"
+ attribute \src "libresoc.v:147736.5-147736.29"
switch \initial
- attribute \src "libresoc.v:149606.9-149606.17"
+ attribute \src "libresoc.v:147736.9-147736.17"
case 1'1
case
end
sync always
update \bt $0\bt[1:0]
end
- attribute \src "libresoc.v:149616.3-149626.6"
- process $proc$libresoc.v:149616$7613
+ attribute \src "libresoc.v:147746.3-147756.6"
+ process $proc$libresoc.v:147746$7539
assign { } { }
assign { } { }
assign $0\ba[1:0] $1\ba[1:0]
- attribute \src "libresoc.v:149617.5-149617.29"
+ attribute \src "libresoc.v:147747.5-147747.29"
switch \initial
- attribute \src "libresoc.v:149617.9-149617.17"
+ attribute \src "libresoc.v:147747.9-147747.17"
case 1'1
case
end
sync always
update \ba $0\ba[1:0]
end
- attribute \src "libresoc.v:149627.3-149637.6"
- process $proc$libresoc.v:149627$7614
+ attribute \src "libresoc.v:147757.3-147767.6"
+ process $proc$libresoc.v:147757$7540
assign { } { }
assign { } { }
assign $0\bb[1:0] $1\bb[1:0]
- attribute \src "libresoc.v:149628.5-149628.29"
+ attribute \src "libresoc.v:147758.5-147758.29"
switch \initial
- attribute \src "libresoc.v:149628.9-149628.17"
+ attribute \src "libresoc.v:147758.9-147758.17"
case 1'1
case
end
sync always
update \bb $0\bb[1:0]
end
- attribute \src "libresoc.v:149638.3-149658.6"
- process $proc$libresoc.v:149638$7615
+ attribute \src "libresoc.v:147768.3-147788.6"
+ process $proc$libresoc.v:147768$7541
assign { } { }
assign { } { }
assign $0\bit_a[0:0] $1\bit_a[0:0]
- attribute \src "libresoc.v:149639.5-149639.29"
+ attribute \src "libresoc.v:147769.5-147769.29"
switch \initial
- attribute \src "libresoc.v:149639.9-149639.17"
+ attribute \src "libresoc.v:147769.9-147769.17"
case 1'1
case
end
sync always
update \bit_a $0\bit_a[0:0]
end
- attribute \src "libresoc.v:149659.3-149679.6"
- process $proc$libresoc.v:149659$7616
+ attribute \src "libresoc.v:147789.3-147809.6"
+ process $proc$libresoc.v:147789$7542
assign { } { }
assign { } { }
assign $0\bit_b[0:0] $1\bit_b[0:0]
- attribute \src "libresoc.v:149660.5-149660.29"
+ attribute \src "libresoc.v:147790.5-147790.29"
switch \initial
- attribute \src "libresoc.v:149660.9-149660.17"
+ attribute \src "libresoc.v:147790.9-147790.17"
case 1'1
case
end
sync always
update \bit_b $0\bit_b[0:0]
end
- attribute \src "libresoc.v:149680.3-149690.6"
- process $proc$libresoc.v:149680$7617
+ attribute \src "libresoc.v:147810.3-147820.6"
+ process $proc$libresoc.v:147810$7543
assign { } { }
assign { } { }
assign $0\bit_o[0:0] $1\bit_o[0:0]
- attribute \src "libresoc.v:149681.5-149681.29"
+ attribute \src "libresoc.v:147811.5-147811.29"
switch \initial
- attribute \src "libresoc.v:149681.9-149681.17"
+ attribute \src "libresoc.v:147811.9-147811.17"
case 1'1
case
end
sync always
update \bit_o $0\bit_o[0:0]
end
- attribute \src "libresoc.v:149691.3-149701.6"
- process $proc$libresoc.v:149691$7618
+ attribute \src "libresoc.v:147821.3-147831.6"
+ process $proc$libresoc.v:147821$7544
assign { } { }
assign { } { }
- assign $0\full_cr$5[31:0]$7619 $1\full_cr$5[31:0]$7620
- attribute \src "libresoc.v:149692.5-149692.29"
+ assign $0\full_cr$5[31:0]$7545 $1\full_cr$5[31:0]$7546
+ attribute \src "libresoc.v:147822.5-147822.29"
switch \initial
- attribute \src "libresoc.v:149692.9-149692.17"
+ attribute \src "libresoc.v:147822.9-147822.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110000
assign { } { }
- assign $1\full_cr$5[31:0]$7620 \ra [31:0]
+ assign $1\full_cr$5[31:0]$7546 \ra [31:0]
case
- assign $1\full_cr$5[31:0]$7620 0
+ assign $1\full_cr$5[31:0]$7546 0
end
sync always
- update \full_cr$5 $0\full_cr$5[31:0]$7619
+ update \full_cr$5 $0\full_cr$5[31:0]$7545
end
- connect \$10 $sub$libresoc.v:149464$7590_Y
- connect \$13 $sub$libresoc.v:149465$7591_Y
- connect \$16 $sub$libresoc.v:149466$7592_Y
- connect \$18 $ternary$libresoc.v:149467$7593_Y
- connect \$20 $ternary$libresoc.v:149468$7594_Y
- connect \$22 $ternary$libresoc.v:149469$7595_Y
- connect \$24 $pos$libresoc.v:149470$7597_Y
- connect \$27 $ternary$libresoc.v:149471$7598_Y
- connect \$26 $pos$libresoc.v:149472$7600_Y
- connect \$7 $pos$libresoc.v:149473$7602_Y
+ connect \$10 $sub$libresoc.v:147594$7516_Y
+ connect \$13 $sub$libresoc.v:147595$7517_Y
+ connect \$16 $sub$libresoc.v:147596$7518_Y
+ connect \$18 $ternary$libresoc.v:147597$7519_Y
+ connect \$20 $ternary$libresoc.v:147598$7520_Y
+ connect \$22 $ternary$libresoc.v:147599$7521_Y
+ connect \$24 $pos$libresoc.v:147600$7523_Y
+ connect \$27 $ternary$libresoc.v:147601$7524_Y
+ connect \$26 $pos$libresoc.v:147602$7526_Y
+ connect \$7 $pos$libresoc.v:147603$7528_Y
connect \$9 \$10
connect \$12 \$13
connect \$15 \$16
connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
connect \muxid$1 \muxid
end
-attribute \src "libresoc.v:149711.1-150868.10"
+attribute \src "libresoc.v:147841.1-148998.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0"
attribute \generator "nMigen"
module \mul0
- attribute \src "libresoc.v:150439.3-150440.25"
+ attribute \src "libresoc.v:148569.3-148570.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:150437.3-150438.40"
+ attribute \src "libresoc.v:148567.3-148568.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:150780.3-150788.6"
- wire $0\alu_l_r_alu$next[0:0]$7827
- attribute \src "libresoc.v:150365.3-150366.39"
+ attribute \src "libresoc.v:148910.3-148918.6"
+ wire $0\alu_l_r_alu$next[0:0]$7753
+ attribute \src "libresoc.v:148495.3-148496.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752
- attribute \src "libresoc.v:150393.3-150394.65"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678
+ attribute \src "libresoc.v:148523.3-148524.65"
wire width 13 $0\alu_mul0_mul_op__fn_unit[12:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753
- attribute \src "libresoc.v:150395.3-150396.79"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679
+ attribute \src "libresoc.v:148525.3-148526.79"
wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754
- attribute \src "libresoc.v:150397.3-150398.75"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680
+ attribute \src "libresoc.v:148527.3-148528.75"
wire $0\alu_mul0_mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7755
- attribute \src "libresoc.v:150413.3-150414.59"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7681
+ attribute \src "libresoc.v:148543.3-148544.59"
wire width 32 $0\alu_mul0_mul_op__insn[31:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7756
- attribute \src "libresoc.v:150391.3-150392.69"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7682
+ attribute \src "libresoc.v:148521.3-148522.69"
wire width 7 $0\alu_mul0_mul_op__insn_type[6:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757
- attribute \src "libresoc.v:150409.3-150410.67"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683
+ attribute \src "libresoc.v:148539.3-148540.67"
wire $0\alu_mul0_mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7758
- attribute \src "libresoc.v:150411.3-150412.69"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7684
+ attribute \src "libresoc.v:148541.3-148542.69"
wire $0\alu_mul0_mul_op__is_signed[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759
- attribute \src "libresoc.v:150403.3-150404.63"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685
+ attribute \src "libresoc.v:148533.3-148534.63"
wire $0\alu_mul0_mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760
- attribute \src "libresoc.v:150405.3-150406.63"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686
+ attribute \src "libresoc.v:148535.3-148536.63"
wire $0\alu_mul0_mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761
- attribute \src "libresoc.v:150401.3-150402.63"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687
+ attribute \src "libresoc.v:148531.3-148532.63"
wire $0\alu_mul0_mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762
- attribute \src "libresoc.v:150399.3-150400.63"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688
+ attribute \src "libresoc.v:148529.3-148530.63"
wire $0\alu_mul0_mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763
- attribute \src "libresoc.v:150407.3-150408.69"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689
+ attribute \src "libresoc.v:148537.3-148538.69"
wire $0\alu_mul0_mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:150771.3-150779.6"
- wire $0\alui_l_r_alui$next[0:0]$7824
- attribute \src "libresoc.v:150367.3-150368.43"
+ attribute \src "libresoc.v:148901.3-148909.6"
+ wire $0\alui_l_r_alui$next[0:0]$7750
+ attribute \src "libresoc.v:148497.3-148498.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:150653.3-150674.6"
- wire width 64 $0\data_r0__o$next[63:0]$7783
- attribute \src "libresoc.v:150387.3-150388.37"
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire width 64 $0\data_r0__o$next[63:0]$7709
+ attribute \src "libresoc.v:148517.3-148518.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:150653.3-150674.6"
- wire $0\data_r0__o_ok$next[0:0]$7784
- attribute \src "libresoc.v:150389.3-150390.43"
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire $0\data_r0__o_ok$next[0:0]$7710
+ attribute \src "libresoc.v:148519.3-148520.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:150675.3-150696.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$7791
- attribute \src "libresoc.v:150383.3-150384.43"
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$7717
+ attribute \src "libresoc.v:148513.3-148514.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:150675.3-150696.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$7792
- attribute \src "libresoc.v:150385.3-150386.49"
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$7718
+ attribute \src "libresoc.v:148515.3-148516.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:150697.3-150718.6"
- wire width 2 $0\data_r2__xer_ov$next[1:0]$7799
- attribute \src "libresoc.v:150379.3-150380.47"
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire width 2 $0\data_r2__xer_ov$next[1:0]$7725
+ attribute \src "libresoc.v:148509.3-148510.47"
wire width 2 $0\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:150697.3-150718.6"
- wire $0\data_r2__xer_ov_ok$next[0:0]$7800
- attribute \src "libresoc.v:150381.3-150382.53"
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire $0\data_r2__xer_ov_ok$next[0:0]$7726
+ attribute \src "libresoc.v:148511.3-148512.53"
wire $0\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $0\data_r3__xer_so$next[0:0]$7807
- attribute \src "libresoc.v:150375.3-150376.47"
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $0\data_r3__xer_so$next[0:0]$7733
+ attribute \src "libresoc.v:148505.3-148506.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$7808
- attribute \src "libresoc.v:150377.3-150378.53"
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$7734
+ attribute \src "libresoc.v:148507.3-148508.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:150789.3-150798.6"
+ attribute \src "libresoc.v:148919.3-148928.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:150799.3-150808.6"
+ attribute \src "libresoc.v:148929.3-148938.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:150809.3-150818.6"
+ attribute \src "libresoc.v:148939.3-148948.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:150819.3-150828.6"
+ attribute \src "libresoc.v:148949.3-148958.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:149712.7-149712.20"
+ attribute \src "libresoc.v:147842.7-147842.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:150575.3-150583.6"
- wire $0\opc_l_r_opc$next[0:0]$7737
- attribute \src "libresoc.v:150423.3-150424.39"
+ attribute \src "libresoc.v:148705.3-148713.6"
+ wire $0\opc_l_r_opc$next[0:0]$7663
+ attribute \src "libresoc.v:148553.3-148554.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:150566.3-150574.6"
- wire $0\opc_l_s_opc$next[0:0]$7734
- attribute \src "libresoc.v:150425.3-150426.39"
+ attribute \src "libresoc.v:148696.3-148704.6"
+ wire $0\opc_l_s_opc$next[0:0]$7660
+ attribute \src "libresoc.v:148555.3-148556.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:150829.3-150837.6"
- wire width 4 $0\prev_wr_go$next[3:0]$7834
- attribute \src "libresoc.v:150435.3-150436.37"
+ attribute \src "libresoc.v:148959.3-148967.6"
+ wire width 4 $0\prev_wr_go$next[3:0]$7760
+ attribute \src "libresoc.v:148565.3-148566.37"
wire width 4 $0\prev_wr_go[3:0]
- attribute \src "libresoc.v:150520.3-150529.6"
+ attribute \src "libresoc.v:148650.3-148659.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:150611.3-150619.6"
- wire width 4 $0\req_l_r_req$next[3:0]$7749
- attribute \src "libresoc.v:150415.3-150416.39"
+ attribute \src "libresoc.v:148741.3-148749.6"
+ wire width 4 $0\req_l_r_req$next[3:0]$7675
+ attribute \src "libresoc.v:148545.3-148546.39"
wire width 4 $0\req_l_r_req[3:0]
- attribute \src "libresoc.v:150602.3-150610.6"
- wire width 4 $0\req_l_s_req$next[3:0]$7746
- attribute \src "libresoc.v:150417.3-150418.39"
+ attribute \src "libresoc.v:148732.3-148740.6"
+ wire width 4 $0\req_l_s_req$next[3:0]$7672
+ attribute \src "libresoc.v:148547.3-148548.39"
wire width 4 $0\req_l_s_req[3:0]
- attribute \src "libresoc.v:150539.3-150547.6"
- wire $0\rok_l_r_rdok$next[0:0]$7725
- attribute \src "libresoc.v:150431.3-150432.41"
+ attribute \src "libresoc.v:148669.3-148677.6"
+ wire $0\rok_l_r_rdok$next[0:0]$7651
+ attribute \src "libresoc.v:148561.3-148562.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:150530.3-150538.6"
- wire $0\rok_l_s_rdok$next[0:0]$7722
- attribute \src "libresoc.v:150433.3-150434.41"
+ attribute \src "libresoc.v:148660.3-148668.6"
+ wire $0\rok_l_s_rdok$next[0:0]$7648
+ attribute \src "libresoc.v:148563.3-148564.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:150557.3-150565.6"
- wire $0\rst_l_r_rst$next[0:0]$7731
- attribute \src "libresoc.v:150427.3-150428.39"
+ attribute \src "libresoc.v:148687.3-148695.6"
+ wire $0\rst_l_r_rst$next[0:0]$7657
+ attribute \src "libresoc.v:148557.3-148558.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:150548.3-150556.6"
- wire $0\rst_l_s_rst$next[0:0]$7728
- attribute \src "libresoc.v:150429.3-150430.39"
+ attribute \src "libresoc.v:148678.3-148686.6"
+ wire $0\rst_l_s_rst$next[0:0]$7654
+ attribute \src "libresoc.v:148559.3-148560.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:150593.3-150601.6"
- wire width 3 $0\src_l_r_src$next[2:0]$7743
- attribute \src "libresoc.v:150419.3-150420.39"
+ attribute \src "libresoc.v:148723.3-148731.6"
+ wire width 3 $0\src_l_r_src$next[2:0]$7669
+ attribute \src "libresoc.v:148549.3-148550.39"
wire width 3 $0\src_l_r_src[2:0]
- attribute \src "libresoc.v:150584.3-150592.6"
- wire width 3 $0\src_l_s_src$next[2:0]$7740
- attribute \src "libresoc.v:150421.3-150422.39"
+ attribute \src "libresoc.v:148714.3-148722.6"
+ wire width 3 $0\src_l_s_src$next[2:0]$7666
+ attribute \src "libresoc.v:148551.3-148552.39"
wire width 3 $0\src_l_s_src[2:0]
- attribute \src "libresoc.v:150741.3-150750.6"
- wire width 64 $0\src_r0$next[63:0]$7815
- attribute \src "libresoc.v:150373.3-150374.29"
+ attribute \src "libresoc.v:148871.3-148880.6"
+ wire width 64 $0\src_r0$next[63:0]$7741
+ attribute \src "libresoc.v:148503.3-148504.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:150751.3-150760.6"
- wire width 64 $0\src_r1$next[63:0]$7818
- attribute \src "libresoc.v:150371.3-150372.29"
+ attribute \src "libresoc.v:148881.3-148890.6"
+ wire width 64 $0\src_r1$next[63:0]$7744
+ attribute \src "libresoc.v:148501.3-148502.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:150761.3-150770.6"
- wire $0\src_r2$next[0:0]$7821
- attribute \src "libresoc.v:150369.3-150370.29"
+ attribute \src "libresoc.v:148891.3-148900.6"
+ wire $0\src_r2$next[0:0]$7747
+ attribute \src "libresoc.v:148499.3-148500.29"
wire $0\src_r2[0:0]
- attribute \src "libresoc.v:149836.7-149836.24"
+ attribute \src "libresoc.v:147966.7-147966.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:149846.7-149846.26"
+ attribute \src "libresoc.v:147976.7-147976.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:150780.3-150788.6"
- wire $1\alu_l_r_alu$next[0:0]$7828
- attribute \src "libresoc.v:149854.7-149854.25"
+ attribute \src "libresoc.v:148910.3-148918.6"
+ wire $1\alu_l_r_alu$next[0:0]$7754
+ attribute \src "libresoc.v:147984.7-147984.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764
- attribute \src "libresoc.v:149876.14-149876.49"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690
+ attribute \src "libresoc.v:148006.14-148006.49"
wire width 13 $1\alu_mul0_mul_op__fn_unit[12:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765
- attribute \src "libresoc.v:149880.14-149880.68"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691
+ attribute \src "libresoc.v:148010.14-148010.68"
wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766
- attribute \src "libresoc.v:149884.7-149884.43"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692
+ attribute \src "libresoc.v:148014.7-148014.43"
wire $1\alu_mul0_mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7767
- attribute \src "libresoc.v:149888.14-149888.43"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7693
+ attribute \src "libresoc.v:148018.14-148018.43"
wire width 32 $1\alu_mul0_mul_op__insn[31:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768
- attribute \src "libresoc.v:149966.13-149966.47"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694
+ attribute \src "libresoc.v:148096.13-148096.47"
wire width 7 $1\alu_mul0_mul_op__insn_type[6:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769
- attribute \src "libresoc.v:149970.7-149970.39"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695
+ attribute \src "libresoc.v:148100.7-148100.39"
wire $1\alu_mul0_mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7770
- attribute \src "libresoc.v:149974.7-149974.40"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7696
+ attribute \src "libresoc.v:148104.7-148104.40"
wire $1\alu_mul0_mul_op__is_signed[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771
- attribute \src "libresoc.v:149978.7-149978.37"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697
+ attribute \src "libresoc.v:148108.7-148108.37"
wire $1\alu_mul0_mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772
- attribute \src "libresoc.v:149982.7-149982.37"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698
+ attribute \src "libresoc.v:148112.7-148112.37"
wire $1\alu_mul0_mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773
- attribute \src "libresoc.v:149986.7-149986.37"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699
+ attribute \src "libresoc.v:148116.7-148116.37"
wire $1\alu_mul0_mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774
- attribute \src "libresoc.v:149990.7-149990.37"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700
+ attribute \src "libresoc.v:148120.7-148120.37"
wire $1\alu_mul0_mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775
- attribute \src "libresoc.v:149994.7-149994.40"
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701
+ attribute \src "libresoc.v:148124.7-148124.40"
wire $1\alu_mul0_mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:150771.3-150779.6"
- wire $1\alui_l_r_alui$next[0:0]$7825
- attribute \src "libresoc.v:150024.7-150024.27"
+ attribute \src "libresoc.v:148901.3-148909.6"
+ wire $1\alui_l_r_alui$next[0:0]$7751
+ attribute \src "libresoc.v:148154.7-148154.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:150653.3-150674.6"
- wire width 64 $1\data_r0__o$next[63:0]$7785
- attribute \src "libresoc.v:150058.14-150058.47"
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire width 64 $1\data_r0__o$next[63:0]$7711
+ attribute \src "libresoc.v:148188.14-148188.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:150653.3-150674.6"
- wire $1\data_r0__o_ok$next[0:0]$7786
- attribute \src "libresoc.v:150062.7-150062.27"
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire $1\data_r0__o_ok$next[0:0]$7712
+ attribute \src "libresoc.v:148192.7-148192.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:150675.3-150696.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$7793
- attribute \src "libresoc.v:150066.13-150066.33"
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$7719
+ attribute \src "libresoc.v:148196.13-148196.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:150675.3-150696.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$7794
- attribute \src "libresoc.v:150070.7-150070.30"
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$7720
+ attribute \src "libresoc.v:148200.7-148200.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:150697.3-150718.6"
- wire width 2 $1\data_r2__xer_ov$next[1:0]$7801
- attribute \src "libresoc.v:150074.13-150074.35"
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire width 2 $1\data_r2__xer_ov$next[1:0]$7727
+ attribute \src "libresoc.v:148204.13-148204.35"
wire width 2 $1\data_r2__xer_ov[1:0]
- attribute \src "libresoc.v:150697.3-150718.6"
- wire $1\data_r2__xer_ov_ok$next[0:0]$7802
- attribute \src "libresoc.v:150078.7-150078.32"
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire $1\data_r2__xer_ov_ok$next[0:0]$7728
+ attribute \src "libresoc.v:148208.7-148208.32"
wire $1\data_r2__xer_ov_ok[0:0]
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $1\data_r3__xer_so$next[0:0]$7809
- attribute \src "libresoc.v:150082.7-150082.29"
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $1\data_r3__xer_so$next[0:0]$7735
+ attribute \src "libresoc.v:148212.7-148212.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$7810
- attribute \src "libresoc.v:150086.7-150086.32"
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$7736
+ attribute \src "libresoc.v:148216.7-148216.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:150789.3-150798.6"
+ attribute \src "libresoc.v:148919.3-148928.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:150799.3-150808.6"
+ attribute \src "libresoc.v:148929.3-148938.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:150809.3-150818.6"
+ attribute \src "libresoc.v:148939.3-148948.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:150819.3-150828.6"
+ attribute \src "libresoc.v:148949.3-148958.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:150575.3-150583.6"
- wire $1\opc_l_r_opc$next[0:0]$7738
- attribute \src "libresoc.v:150106.7-150106.25"
+ attribute \src "libresoc.v:148705.3-148713.6"
+ wire $1\opc_l_r_opc$next[0:0]$7664
+ attribute \src "libresoc.v:148236.7-148236.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:150566.3-150574.6"
- wire $1\opc_l_s_opc$next[0:0]$7735
- attribute \src "libresoc.v:150110.7-150110.25"
+ attribute \src "libresoc.v:148696.3-148704.6"
+ wire $1\opc_l_s_opc$next[0:0]$7661
+ attribute \src "libresoc.v:148240.7-148240.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:150829.3-150837.6"
- wire width 4 $1\prev_wr_go$next[3:0]$7835
- attribute \src "libresoc.v:150226.13-150226.30"
+ attribute \src "libresoc.v:148959.3-148967.6"
+ wire width 4 $1\prev_wr_go$next[3:0]$7761
+ attribute \src "libresoc.v:148356.13-148356.30"
wire width 4 $1\prev_wr_go[3:0]
- attribute \src "libresoc.v:150520.3-150529.6"
+ attribute \src "libresoc.v:148650.3-148659.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:150611.3-150619.6"
- wire width 4 $1\req_l_r_req$next[3:0]$7750
- attribute \src "libresoc.v:150234.13-150234.31"
+ attribute \src "libresoc.v:148741.3-148749.6"
+ wire width 4 $1\req_l_r_req$next[3:0]$7676
+ attribute \src "libresoc.v:148364.13-148364.31"
wire width 4 $1\req_l_r_req[3:0]
- attribute \src "libresoc.v:150602.3-150610.6"
- wire width 4 $1\req_l_s_req$next[3:0]$7747
- attribute \src "libresoc.v:150238.13-150238.31"
+ attribute \src "libresoc.v:148732.3-148740.6"
+ wire width 4 $1\req_l_s_req$next[3:0]$7673
+ attribute \src "libresoc.v:148368.13-148368.31"
wire width 4 $1\req_l_s_req[3:0]
- attribute \src "libresoc.v:150539.3-150547.6"
- wire $1\rok_l_r_rdok$next[0:0]$7726
- attribute \src "libresoc.v:150250.7-150250.26"
+ attribute \src "libresoc.v:148669.3-148677.6"
+ wire $1\rok_l_r_rdok$next[0:0]$7652
+ attribute \src "libresoc.v:148380.7-148380.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:150530.3-150538.6"
- wire $1\rok_l_s_rdok$next[0:0]$7723
- attribute \src "libresoc.v:150254.7-150254.26"
+ attribute \src "libresoc.v:148660.3-148668.6"
+ wire $1\rok_l_s_rdok$next[0:0]$7649
+ attribute \src "libresoc.v:148384.7-148384.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:150557.3-150565.6"
- wire $1\rst_l_r_rst$next[0:0]$7732
- attribute \src "libresoc.v:150258.7-150258.25"
+ attribute \src "libresoc.v:148687.3-148695.6"
+ wire $1\rst_l_r_rst$next[0:0]$7658
+ attribute \src "libresoc.v:148388.7-148388.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:150548.3-150556.6"
- wire $1\rst_l_s_rst$next[0:0]$7729
- attribute \src "libresoc.v:150262.7-150262.25"
+ attribute \src "libresoc.v:148678.3-148686.6"
+ wire $1\rst_l_s_rst$next[0:0]$7655
+ attribute \src "libresoc.v:148392.7-148392.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:150593.3-150601.6"
- wire width 3 $1\src_l_r_src$next[2:0]$7744
- attribute \src "libresoc.v:150276.13-150276.31"
+ attribute \src "libresoc.v:148723.3-148731.6"
+ wire width 3 $1\src_l_r_src$next[2:0]$7670
+ attribute \src "libresoc.v:148406.13-148406.31"
wire width 3 $1\src_l_r_src[2:0]
- attribute \src "libresoc.v:150584.3-150592.6"
- wire width 3 $1\src_l_s_src$next[2:0]$7741
- attribute \src "libresoc.v:150280.13-150280.31"
+ attribute \src "libresoc.v:148714.3-148722.6"
+ wire width 3 $1\src_l_s_src$next[2:0]$7667
+ attribute \src "libresoc.v:148410.13-148410.31"
wire width 3 $1\src_l_s_src[2:0]
- attribute \src "libresoc.v:150741.3-150750.6"
- wire width 64 $1\src_r0$next[63:0]$7816
- attribute \src "libresoc.v:150286.14-150286.43"
+ attribute \src "libresoc.v:148871.3-148880.6"
+ wire width 64 $1\src_r0$next[63:0]$7742
+ attribute \src "libresoc.v:148416.14-148416.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:150751.3-150760.6"
- wire width 64 $1\src_r1$next[63:0]$7819
- attribute \src "libresoc.v:150290.14-150290.43"
+ attribute \src "libresoc.v:148881.3-148890.6"
+ wire width 64 $1\src_r1$next[63:0]$7745
+ attribute \src "libresoc.v:148420.14-148420.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:150761.3-150770.6"
- wire $1\src_r2$next[0:0]$7822
- attribute \src "libresoc.v:150294.7-150294.20"
+ attribute \src "libresoc.v:148891.3-148900.6"
+ wire $1\src_r2$next[0:0]$7748
+ attribute \src "libresoc.v:148424.7-148424.20"
wire $1\src_r2[0:0]
- attribute \src "libresoc.v:150620.3-150652.6"
- wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780
- attribute \src "libresoc.v:150620.3-150652.6"
- wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781
- attribute \src "libresoc.v:150653.3-150674.6"
- wire width 64 $2\data_r0__o$next[63:0]$7787
- attribute \src "libresoc.v:150653.3-150674.6"
- wire $2\data_r0__o_ok$next[0:0]$7788
- attribute \src "libresoc.v:150675.3-150696.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$7795
- attribute \src "libresoc.v:150675.3-150696.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$7796
- attribute \src "libresoc.v:150697.3-150718.6"
- wire width 2 $2\data_r2__xer_ov$next[1:0]$7803
- attribute \src "libresoc.v:150697.3-150718.6"
- wire $2\data_r2__xer_ov_ok$next[0:0]$7804
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $2\data_r3__xer_so$next[0:0]$7811
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$7812
- attribute \src "libresoc.v:150653.3-150674.6"
- wire $3\data_r0__o_ok$next[0:0]$7789
- attribute \src "libresoc.v:150675.3-150696.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$7797
- attribute \src "libresoc.v:150697.3-150718.6"
- wire $3\data_r2__xer_ov_ok$next[0:0]$7805
- attribute \src "libresoc.v:150719.3-150740.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$7813
- attribute \src "libresoc.v:150305.19-150305.113"
- wire width 3 $and$libresoc.v:150305$7622_Y
- attribute \src "libresoc.v:150306.19-150306.125"
- wire $and$libresoc.v:150306$7623_Y
- attribute \src "libresoc.v:150307.19-150307.125"
- wire $and$libresoc.v:150307$7624_Y
- attribute \src "libresoc.v:150308.19-150308.125"
- wire $and$libresoc.v:150308$7625_Y
- attribute \src "libresoc.v:150309.19-150309.125"
- wire $and$libresoc.v:150309$7626_Y
- attribute \src "libresoc.v:150310.18-150310.110"
- wire $and$libresoc.v:150310$7627_Y
- attribute \src "libresoc.v:150311.19-150311.149"
- wire width 4 $and$libresoc.v:150311$7628_Y
- attribute \src "libresoc.v:150312.19-150312.121"
- wire width 4 $and$libresoc.v:150312$7629_Y
- attribute \src "libresoc.v:150313.19-150313.127"
- wire $and$libresoc.v:150313$7630_Y
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- wire $and$libresoc.v:150314$7631_Y
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- wire $and$libresoc.v:150315$7632_Y
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- wire $and$libresoc.v:150316$7633_Y
- attribute \src "libresoc.v:150318.18-150318.98"
- wire $and$libresoc.v:150318$7635_Y
- attribute \src "libresoc.v:150320.18-150320.100"
- wire $and$libresoc.v:150320$7637_Y
- attribute \src "libresoc.v:150321.18-150321.160"
- wire width 4 $and$libresoc.v:150321$7638_Y
- attribute \src "libresoc.v:150323.18-150323.119"
- wire width 4 $and$libresoc.v:150323$7640_Y
- attribute \src "libresoc.v:150326.17-150326.123"
- wire $and$libresoc.v:150326$7643_Y
- attribute \src "libresoc.v:150327.18-150327.116"
- wire $and$libresoc.v:150327$7644_Y
- attribute \src "libresoc.v:150332.18-150332.113"
- wire $and$libresoc.v:150332$7649_Y
- attribute \src "libresoc.v:150333.18-150333.125"
- wire width 4 $and$libresoc.v:150333$7650_Y
- attribute \src "libresoc.v:150335.18-150335.112"
- wire $and$libresoc.v:150335$7652_Y
- attribute \src "libresoc.v:150337.18-150337.126"
- wire $and$libresoc.v:150337$7654_Y
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- wire $and$libresoc.v:150338$7655_Y
- attribute \src "libresoc.v:150339.18-150339.117"
- wire $and$libresoc.v:150339$7656_Y
- attribute \src "libresoc.v:150345.18-150345.130"
- wire $and$libresoc.v:150345$7662_Y
- attribute \src "libresoc.v:150346.18-150346.124"
- wire width 4 $and$libresoc.v:150346$7663_Y
- attribute \src "libresoc.v:150348.18-150348.116"
- wire $and$libresoc.v:150348$7665_Y
- attribute \src "libresoc.v:150349.18-150349.119"
- wire $and$libresoc.v:150349$7666_Y
- attribute \src "libresoc.v:150350.18-150350.121"
- wire $and$libresoc.v:150350$7667_Y
- attribute \src "libresoc.v:150351.18-150351.121"
- wire $and$libresoc.v:150351$7668_Y
- attribute \src "libresoc.v:150358.18-150358.134"
- wire $and$libresoc.v:150358$7675_Y
- attribute \src "libresoc.v:150360.18-150360.132"
- wire $and$libresoc.v:150360$7677_Y
- attribute \src "libresoc.v:150361.18-150361.149"
- wire width 3 $and$libresoc.v:150361$7678_Y
- attribute \src "libresoc.v:150363.18-150363.129"
- wire width 3 $and$libresoc.v:150363$7680_Y
- attribute \src "libresoc.v:150334.18-150334.113"
- wire $eq$libresoc.v:150334$7651_Y
- attribute \src "libresoc.v:150336.18-150336.119"
- wire $eq$libresoc.v:150336$7653_Y
- attribute \src "libresoc.v:150317.18-150317.97"
- wire $not$libresoc.v:150317$7634_Y
- attribute \src "libresoc.v:150319.18-150319.99"
- wire $not$libresoc.v:150319$7636_Y
- attribute \src "libresoc.v:150322.18-150322.113"
- wire width 4 $not$libresoc.v:150322$7639_Y
- attribute \src "libresoc.v:150325.18-150325.106"
- wire $not$libresoc.v:150325$7642_Y
- attribute \src "libresoc.v:150331.18-150331.120"
- wire $not$libresoc.v:150331$7648_Y
- attribute \src "libresoc.v:150342.17-150342.113"
- wire width 3 $not$libresoc.v:150342$7659_Y
- attribute \src "libresoc.v:150362.18-150362.131"
- wire $not$libresoc.v:150362$7679_Y
- attribute \src "libresoc.v:150364.18-150364.114"
- wire width 3 $not$libresoc.v:150364$7681_Y
- attribute \src "libresoc.v:150330.18-150330.112"
- wire $or$libresoc.v:150330$7647_Y
- attribute \src "libresoc.v:150340.18-150340.122"
- wire $or$libresoc.v:150340$7657_Y
- attribute \src "libresoc.v:150341.18-150341.124"
- wire $or$libresoc.v:150341$7658_Y
- attribute \src "libresoc.v:150343.18-150343.168"
- wire width 4 $or$libresoc.v:150343$7660_Y
- attribute \src "libresoc.v:150344.18-150344.155"
- wire width 3 $or$libresoc.v:150344$7661_Y
- attribute \src "libresoc.v:150347.18-150347.120"
- wire width 4 $or$libresoc.v:150347$7664_Y
- attribute \src "libresoc.v:150353.17-150353.117"
- wire width 3 $or$libresoc.v:150353$7670_Y
- attribute \src "libresoc.v:150359.17-150359.104"
- wire $reduce_and$libresoc.v:150359$7676_Y
- attribute \src "libresoc.v:150324.18-150324.106"
- wire $reduce_or$libresoc.v:150324$7641_Y
- attribute \src "libresoc.v:150328.18-150328.113"
- wire $reduce_or$libresoc.v:150328$7645_Y
- attribute \src "libresoc.v:150329.18-150329.112"
- wire $reduce_or$libresoc.v:150329$7646_Y
- attribute \src "libresoc.v:150352.18-150352.160"
- wire $ternary$libresoc.v:150352$7669_Y
- attribute \src "libresoc.v:150354.18-150354.172"
- wire width 64 $ternary$libresoc.v:150354$7671_Y
- attribute \src "libresoc.v:150355.18-150355.118"
- wire width 64 $ternary$libresoc.v:150355$7672_Y
- attribute \src "libresoc.v:150356.18-150356.115"
- wire width 64 $ternary$libresoc.v:150356$7673_Y
- attribute \src "libresoc.v:150357.18-150357.118"
- wire $ternary$libresoc.v:150357$7674_Y
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706
+ attribute \src "libresoc.v:148750.3-148782.6"
+ wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire width 64 $2\data_r0__o$next[63:0]$7713
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire $2\data_r0__o_ok$next[0:0]$7714
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$7721
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$7722
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire width 2 $2\data_r2__xer_ov$next[1:0]$7729
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire $2\data_r2__xer_ov_ok$next[0:0]$7730
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $2\data_r3__xer_so$next[0:0]$7737
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$7738
+ attribute \src "libresoc.v:148783.3-148804.6"
+ wire $3\data_r0__o_ok$next[0:0]$7715
+ attribute \src "libresoc.v:148805.3-148826.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$7723
+ attribute \src "libresoc.v:148827.3-148848.6"
+ wire $3\data_r2__xer_ov_ok$next[0:0]$7731
+ attribute \src "libresoc.v:148849.3-148870.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$7739
+ attribute \src "libresoc.v:148435.19-148435.113"
+ wire width 3 $and$libresoc.v:148435$7548_Y
+ attribute \src "libresoc.v:148436.19-148436.125"
+ wire $and$libresoc.v:148436$7549_Y
+ attribute \src "libresoc.v:148437.19-148437.125"
+ wire $and$libresoc.v:148437$7550_Y
+ attribute \src "libresoc.v:148438.19-148438.125"
+ wire $and$libresoc.v:148438$7551_Y
+ attribute \src "libresoc.v:148439.19-148439.125"
+ wire $and$libresoc.v:148439$7552_Y
+ attribute \src "libresoc.v:148440.18-148440.110"
+ wire $and$libresoc.v:148440$7553_Y
+ attribute \src "libresoc.v:148441.19-148441.149"
+ wire width 4 $and$libresoc.v:148441$7554_Y
+ attribute \src "libresoc.v:148442.19-148442.121"
+ wire width 4 $and$libresoc.v:148442$7555_Y
+ attribute \src "libresoc.v:148443.19-148443.127"
+ wire $and$libresoc.v:148443$7556_Y
+ attribute \src "libresoc.v:148444.19-148444.127"
+ wire $and$libresoc.v:148444$7557_Y
+ attribute \src "libresoc.v:148445.19-148445.127"
+ wire $and$libresoc.v:148445$7558_Y
+ attribute \src "libresoc.v:148446.19-148446.127"
+ wire $and$libresoc.v:148446$7559_Y
+ attribute \src "libresoc.v:148448.18-148448.98"
+ wire $and$libresoc.v:148448$7561_Y
+ attribute \src "libresoc.v:148450.18-148450.100"
+ wire $and$libresoc.v:148450$7563_Y
+ attribute \src "libresoc.v:148451.18-148451.160"
+ wire width 4 $and$libresoc.v:148451$7564_Y
+ attribute \src "libresoc.v:148453.18-148453.119"
+ wire width 4 $and$libresoc.v:148453$7566_Y
+ attribute \src "libresoc.v:148456.17-148456.123"
+ wire $and$libresoc.v:148456$7569_Y
+ attribute \src "libresoc.v:148457.18-148457.116"
+ wire $and$libresoc.v:148457$7570_Y
+ attribute \src "libresoc.v:148462.18-148462.113"
+ wire $and$libresoc.v:148462$7575_Y
+ attribute \src "libresoc.v:148463.18-148463.125"
+ wire width 4 $and$libresoc.v:148463$7576_Y
+ attribute \src "libresoc.v:148465.18-148465.112"
+ wire $and$libresoc.v:148465$7578_Y
+ attribute \src "libresoc.v:148467.18-148467.126"
+ wire $and$libresoc.v:148467$7580_Y
+ attribute \src "libresoc.v:148468.18-148468.126"
+ wire $and$libresoc.v:148468$7581_Y
+ attribute \src "libresoc.v:148469.18-148469.117"
+ wire $and$libresoc.v:148469$7582_Y
+ attribute \src "libresoc.v:148475.18-148475.130"
+ wire $and$libresoc.v:148475$7588_Y
+ attribute \src "libresoc.v:148476.18-148476.124"
+ wire width 4 $and$libresoc.v:148476$7589_Y
+ attribute \src "libresoc.v:148478.18-148478.116"
+ wire $and$libresoc.v:148478$7591_Y
+ attribute \src "libresoc.v:148479.18-148479.119"
+ wire $and$libresoc.v:148479$7592_Y
+ attribute \src "libresoc.v:148480.18-148480.121"
+ wire $and$libresoc.v:148480$7593_Y
+ attribute \src "libresoc.v:148481.18-148481.121"
+ wire $and$libresoc.v:148481$7594_Y
+ attribute \src "libresoc.v:148488.18-148488.134"
+ wire $and$libresoc.v:148488$7601_Y
+ attribute \src "libresoc.v:148490.18-148490.132"
+ wire $and$libresoc.v:148490$7603_Y
+ attribute \src "libresoc.v:148491.18-148491.149"
+ wire width 3 $and$libresoc.v:148491$7604_Y
+ attribute \src "libresoc.v:148493.18-148493.129"
+ wire width 3 $and$libresoc.v:148493$7606_Y
+ attribute \src "libresoc.v:148464.18-148464.113"
+ wire $eq$libresoc.v:148464$7577_Y
+ attribute \src "libresoc.v:148466.18-148466.119"
+ wire $eq$libresoc.v:148466$7579_Y
+ attribute \src "libresoc.v:148447.18-148447.97"
+ wire $not$libresoc.v:148447$7560_Y
+ attribute \src "libresoc.v:148449.18-148449.99"
+ wire $not$libresoc.v:148449$7562_Y
+ attribute \src "libresoc.v:148452.18-148452.113"
+ wire width 4 $not$libresoc.v:148452$7565_Y
+ attribute \src "libresoc.v:148455.18-148455.106"
+ wire $not$libresoc.v:148455$7568_Y
+ attribute \src "libresoc.v:148461.18-148461.120"
+ wire $not$libresoc.v:148461$7574_Y
+ attribute \src "libresoc.v:148472.17-148472.113"
+ wire width 3 $not$libresoc.v:148472$7585_Y
+ attribute \src "libresoc.v:148492.18-148492.131"
+ wire $not$libresoc.v:148492$7605_Y
+ attribute \src "libresoc.v:148494.18-148494.114"
+ wire width 3 $not$libresoc.v:148494$7607_Y
+ attribute \src "libresoc.v:148460.18-148460.112"
+ wire $or$libresoc.v:148460$7573_Y
+ attribute \src "libresoc.v:148470.18-148470.122"
+ wire $or$libresoc.v:148470$7583_Y
+ attribute \src "libresoc.v:148471.18-148471.124"
+ wire $or$libresoc.v:148471$7584_Y
+ attribute \src "libresoc.v:148473.18-148473.168"
+ wire width 4 $or$libresoc.v:148473$7586_Y
+ attribute \src "libresoc.v:148474.18-148474.155"
+ wire width 3 $or$libresoc.v:148474$7587_Y
+ attribute \src "libresoc.v:148477.18-148477.120"
+ wire width 4 $or$libresoc.v:148477$7590_Y
+ attribute \src "libresoc.v:148483.17-148483.117"
+ wire width 3 $or$libresoc.v:148483$7596_Y
+ attribute \src "libresoc.v:148489.17-148489.104"
+ wire $reduce_and$libresoc.v:148489$7602_Y
+ attribute \src "libresoc.v:148454.18-148454.106"
+ wire $reduce_or$libresoc.v:148454$7567_Y
+ attribute \src "libresoc.v:148458.18-148458.113"
+ wire $reduce_or$libresoc.v:148458$7571_Y
+ attribute \src "libresoc.v:148459.18-148459.112"
+ wire $reduce_or$libresoc.v:148459$7572_Y
+ attribute \src "libresoc.v:148482.18-148482.160"
+ wire $ternary$libresoc.v:148482$7595_Y
+ attribute \src "libresoc.v:148484.18-148484.172"
+ wire width 64 $ternary$libresoc.v:148484$7597_Y
+ attribute \src "libresoc.v:148485.18-148485.118"
+ wire width 64 $ternary$libresoc.v:148485$7598_Y
+ attribute \src "libresoc.v:148486.18-148486.115"
+ wire width 64 $ternary$libresoc.v:148486$7599_Y
+ attribute \src "libresoc.v:148487.18-148487.118"
+ wire $ternary$libresoc.v:148487$7600_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 26 \cr_a_ok
wire width 2 output 29 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire output 31 \dest4_o
- attribute \src "libresoc.v:149712.7-149712.15"
+ attribute \src "libresoc.v:147842.7-147842.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 22 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 30 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:150305$7622
+ cell $and $and$libresoc.v:148435$7548
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$96
connect \B \$98
- connect \Y $and$libresoc.v:150305$7622_Y
+ connect \Y $and$libresoc.v:148435$7548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:150306$7623
+ cell $and $and$libresoc.v:148436$7549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:150306$7623_Y
+ connect \Y $and$libresoc.v:148436$7549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:150307$7624
+ cell $and $and$libresoc.v:148437$7550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:150307$7624_Y
+ connect \Y $and$libresoc.v:148437$7550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:150308$7625
+ cell $and $and$libresoc.v:148438$7551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:150308$7625_Y
+ connect \Y $and$libresoc.v:148438$7551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:150309$7626
+ cell $and $and$libresoc.v:148439$7552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:150309$7626_Y
+ connect \Y $and$libresoc.v:148439$7552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:150310$7627
+ cell $and $and$libresoc.v:148440$7553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:150310$7627_Y
+ connect \Y $and$libresoc.v:148440$7553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:150311$7628
+ cell $and $and$libresoc.v:148441$7554
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B { \$102 \$104 \$106 \$108 }
- connect \Y $and$libresoc.v:150311$7628_Y
+ connect \Y $and$libresoc.v:148441$7554_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:150312$7629
+ cell $and $and$libresoc.v:148442$7555
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$110
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:150312$7629_Y
+ connect \Y $and$libresoc.v:148442$7555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:150313$7630
+ cell $and $and$libresoc.v:148443$7556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150313$7630_Y
+ connect \Y $and$libresoc.v:148443$7556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:150314$7631
+ cell $and $and$libresoc.v:148444$7557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150314$7631_Y
+ connect \Y $and$libresoc.v:148444$7557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:150315$7632
+ cell $and $and$libresoc.v:148445$7558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150315$7632_Y
+ connect \Y $and$libresoc.v:148445$7558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:150316$7633
+ cell $and $and$libresoc.v:148446$7559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150316$7633_Y
+ connect \Y $and$libresoc.v:148446$7559_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:150318$7635
+ cell $and $and$libresoc.v:148448$7561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:150318$7635_Y
+ connect \Y $and$libresoc.v:148448$7561_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:150320$7637
+ cell $and $and$libresoc.v:148450$7563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:150320$7637_Y
+ connect \Y $and$libresoc.v:148450$7563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:150321$7638
+ cell $and $and$libresoc.v:148451$7564
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:150321$7638_Y
+ connect \Y $and$libresoc.v:148451$7564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:150323$7640
+ cell $and $and$libresoc.v:148453$7566
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:150323$7640_Y
+ connect \Y $and$libresoc.v:148453$7566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:150326$7643
+ cell $and $and$libresoc.v:148456$7569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:150326$7643_Y
+ connect \Y $and$libresoc.v:148456$7569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:150327$7644
+ cell $and $and$libresoc.v:148457$7570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:150327$7644_Y
+ connect \Y $and$libresoc.v:148457$7570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:150332$7649
+ cell $and $and$libresoc.v:148462$7575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:150332$7649_Y
+ connect \Y $and$libresoc.v:148462$7575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:150333$7650
+ cell $and $and$libresoc.v:148463$7576
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:150333$7650_Y
+ connect \Y $and$libresoc.v:148463$7576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:150335$7652
+ cell $and $and$libresoc.v:148465$7578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:150335$7652_Y
+ connect \Y $and$libresoc.v:148465$7578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:150337$7654
+ cell $and $and$libresoc.v:148467$7580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_mul0_n_ready_i
- connect \Y $and$libresoc.v:150337$7654_Y
+ connect \Y $and$libresoc.v:148467$7580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:150338$7655
+ cell $and $and$libresoc.v:148468$7581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_mul0_n_valid_o
- connect \Y $and$libresoc.v:150338$7655_Y
+ connect \Y $and$libresoc.v:148468$7581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:150339$7656
+ cell $and $and$libresoc.v:148469$7582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150339$7656_Y
+ connect \Y $and$libresoc.v:148469$7582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:150345$7662
+ cell $and $and$libresoc.v:148475$7588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150345$7662_Y
+ connect \Y $and$libresoc.v:148475$7588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:150346$7663
+ cell $and $and$libresoc.v:148476$7589
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:150346$7663_Y
+ connect \Y $and$libresoc.v:148476$7589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:150348$7665
+ cell $and $and$libresoc.v:148478$7591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150348$7665_Y
+ connect \Y $and$libresoc.v:148478$7591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:150349$7666
+ cell $and $and$libresoc.v:148479$7592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150349$7666_Y
+ connect \Y $and$libresoc.v:148479$7592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:150350$7667
+ cell $and $and$libresoc.v:148480$7593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150350$7667_Y
+ connect \Y $and$libresoc.v:148480$7593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:150351$7668
+ cell $and $and$libresoc.v:148481$7594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:150351$7668_Y
+ connect \Y $and$libresoc.v:148481$7594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:150358$7675
+ cell $and $and$libresoc.v:148488$7601
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:150358$7675_Y
+ connect \Y $and$libresoc.v:148488$7601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:150360$7677
+ cell $and $and$libresoc.v:148490$7603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:150360$7677_Y
+ connect \Y $and$libresoc.v:148490$7603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:150361$7678
+ cell $and $and$libresoc.v:148491$7604
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:150361$7678_Y
+ connect \Y $and$libresoc.v:148491$7604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:150363$7680
+ cell $and $and$libresoc.v:148493$7606
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$92
connect \B { 1'1 \$94 1'1 }
- connect \Y $and$libresoc.v:150363$7680_Y
+ connect \Y $and$libresoc.v:148493$7606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:150334$7651
+ cell $eq $eq$libresoc.v:148464$7577
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:150334$7651_Y
+ connect \Y $eq$libresoc.v:148464$7577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:150336$7653
+ cell $eq $eq$libresoc.v:148466$7579
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:150336$7653_Y
+ connect \Y $eq$libresoc.v:148466$7579_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:150317$7634
+ cell $not $not$libresoc.v:148447$7560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:150317$7634_Y
+ connect \Y $not$libresoc.v:148447$7560_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:150319$7636
+ cell $not $not$libresoc.v:148449$7562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:150319$7636_Y
+ connect \Y $not$libresoc.v:148449$7562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:150322$7639
+ cell $not $not$libresoc.v:148452$7565
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:150322$7639_Y
+ connect \Y $not$libresoc.v:148452$7565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:150325$7642
+ cell $not $not$libresoc.v:148455$7568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:150325$7642_Y
+ connect \Y $not$libresoc.v:148455$7568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:150331$7648
+ cell $not $not$libresoc.v:148461$7574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_mul0_n_ready_i
- connect \Y $not$libresoc.v:150331$7648_Y
+ connect \Y $not$libresoc.v:148461$7574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:150342$7659
+ cell $not $not$libresoc.v:148472$7585
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:150342$7659_Y
+ connect \Y $not$libresoc.v:148472$7585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:150362$7679
+ cell $not $not$libresoc.v:148492$7605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_mul0_mul_op__imm_data__ok
- connect \Y $not$libresoc.v:150362$7679_Y
+ connect \Y $not$libresoc.v:148492$7605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:150364$7681
+ cell $not $not$libresoc.v:148494$7607
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:150364$7681_Y
+ connect \Y $not$libresoc.v:148494$7607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:150330$7647
+ cell $or $or$libresoc.v:148460$7573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:150330$7647_Y
+ connect \Y $or$libresoc.v:148460$7573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:150340$7657
+ cell $or $or$libresoc.v:148470$7583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:150340$7657_Y
+ connect \Y $or$libresoc.v:148470$7583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:150341$7658
+ cell $or $or$libresoc.v:148471$7584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:150341$7658_Y
+ connect \Y $or$libresoc.v:148471$7584_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:150343$7660
+ cell $or $or$libresoc.v:148473$7586
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:150343$7660_Y
+ connect \Y $or$libresoc.v:148473$7586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:150344$7661
+ cell $or $or$libresoc.v:148474$7587
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:150344$7661_Y
+ connect \Y $or$libresoc.v:148474$7587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:150347$7664
+ cell $or $or$libresoc.v:148477$7590
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:150347$7664_Y
+ connect \Y $or$libresoc.v:148477$7590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:150353$7670
+ cell $or $or$libresoc.v:148483$7596
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:150353$7670_Y
+ connect \Y $or$libresoc.v:148483$7596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:150359$7676
+ cell $reduce_and $reduce_and$libresoc.v:148489$7602
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:150359$7676_Y
+ connect \Y $reduce_and$libresoc.v:148489$7602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:150324$7641
+ cell $reduce_or $reduce_or$libresoc.v:148454$7567
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:150324$7641_Y
+ connect \Y $reduce_or$libresoc.v:148454$7567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:150328$7645
+ cell $reduce_or $reduce_or$libresoc.v:148458$7571
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:150328$7645_Y
+ connect \Y $reduce_or$libresoc.v:148458$7571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:150329$7646
+ cell $reduce_or $reduce_or$libresoc.v:148459$7572
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:150329$7646_Y
+ connect \Y $reduce_or$libresoc.v:148459$7572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:150352$7669
+ cell $mux $ternary$libresoc.v:148482$7595
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_mul0_mul_op__imm_data__ok
- connect \Y $ternary$libresoc.v:150352$7669_Y
+ connect \Y $ternary$libresoc.v:148482$7595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:150354$7671
+ cell $mux $ternary$libresoc.v:148484$7597
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_mul0_mul_op__imm_data__data
connect \S \alu_mul0_mul_op__imm_data__ok
- connect \Y $ternary$libresoc.v:150354$7671_Y
+ connect \Y $ternary$libresoc.v:148484$7597_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:150355$7672
+ cell $mux $ternary$libresoc.v:148485$7598
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:150355$7672_Y
+ connect \Y $ternary$libresoc.v:148485$7598_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:150356$7673
+ cell $mux $ternary$libresoc.v:148486$7599
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:150356$7673_Y
+ connect \Y $ternary$libresoc.v:148486$7599_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:150357$7674
+ cell $mux $ternary$libresoc.v:148487$7600
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:150357$7674_Y
+ connect \Y $ternary$libresoc.v:148487$7600_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150441.15-150447.4"
+ attribute \src "libresoc.v:148571.15-148577.4"
cell \alu_l$107 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150448.12-150478.4"
+ attribute \src "libresoc.v:148578.12-148608.4"
cell \alu_mul0 \alu_mul0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150479.16-150485.4"
+ attribute \src "libresoc.v:148609.16-148615.4"
cell \alui_l$106 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150486.15-150492.4"
+ attribute \src "libresoc.v:148616.15-148622.4"
cell \opc_l$102 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150493.15-150499.4"
+ attribute \src "libresoc.v:148623.15-148629.4"
cell \req_l$103 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150500.15-150506.4"
+ attribute \src "libresoc.v:148630.15-148636.4"
cell \rok_l$105 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150507.15-150512.4"
+ attribute \src "libresoc.v:148637.15-148642.4"
cell \rst_l$104 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:150513.15-150519.4"
+ attribute \src "libresoc.v:148643.15-148649.4"
cell \src_l$101 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:149712.7-149712.20"
- process $proc$libresoc.v:149712$7836
+ attribute \src "libresoc.v:147842.7-147842.20"
+ process $proc$libresoc.v:147842$7762
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:149836.7-149836.24"
- process $proc$libresoc.v:149836$7837
+ attribute \src "libresoc.v:147966.7-147966.24"
+ process $proc$libresoc.v:147966$7763
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:149846.7-149846.26"
- process $proc$libresoc.v:149846$7838
+ attribute \src "libresoc.v:147976.7-147976.26"
+ process $proc$libresoc.v:147976$7764
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:149854.7-149854.25"
- process $proc$libresoc.v:149854$7839
+ attribute \src "libresoc.v:147984.7-147984.25"
+ process $proc$libresoc.v:147984$7765
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:149876.14-149876.49"
- process $proc$libresoc.v:149876$7840
+ attribute \src "libresoc.v:148006.14-148006.49"
+ process $proc$libresoc.v:148006$7766
assign { } { }
assign $1\alu_mul0_mul_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:149880.14-149880.68"
- process $proc$libresoc.v:149880$7841
+ attribute \src "libresoc.v:148010.14-148010.68"
+ process $proc$libresoc.v:148010$7767
assign { } { }
assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:149884.7-149884.43"
- process $proc$libresoc.v:149884$7842
+ attribute \src "libresoc.v:148014.7-148014.43"
+ process $proc$libresoc.v:148014$7768
assign { } { }
assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:149888.14-149888.43"
- process $proc$libresoc.v:149888$7843
+ attribute \src "libresoc.v:148018.14-148018.43"
+ process $proc$libresoc.v:148018$7769
assign { } { }
assign $1\alu_mul0_mul_op__insn[31:0] 0
sync always
sync init
update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0]
end
- attribute \src "libresoc.v:149966.13-149966.47"
- process $proc$libresoc.v:149966$7844
+ attribute \src "libresoc.v:148096.13-148096.47"
+ process $proc$libresoc.v:148096$7770
assign { } { }
assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:149970.7-149970.39"
- process $proc$libresoc.v:149970$7845
+ attribute \src "libresoc.v:148100.7-148100.39"
+ process $proc$libresoc.v:148100$7771
assign { } { }
assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:149974.7-149974.40"
- process $proc$libresoc.v:149974$7846
+ attribute \src "libresoc.v:148104.7-148104.40"
+ process $proc$libresoc.v:148104$7772
assign { } { }
assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:149978.7-149978.37"
- process $proc$libresoc.v:149978$7847
+ attribute \src "libresoc.v:148108.7-148108.37"
+ process $proc$libresoc.v:148108$7773
assign { } { }
assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:149982.7-149982.37"
- process $proc$libresoc.v:149982$7848
+ attribute \src "libresoc.v:148112.7-148112.37"
+ process $proc$libresoc.v:148112$7774
assign { } { }
assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:149986.7-149986.37"
- process $proc$libresoc.v:149986$7849
+ attribute \src "libresoc.v:148116.7-148116.37"
+ process $proc$libresoc.v:148116$7775
assign { } { }
assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:149990.7-149990.37"
- process $proc$libresoc.v:149990$7850
+ attribute \src "libresoc.v:148120.7-148120.37"
+ process $proc$libresoc.v:148120$7776
assign { } { }
assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:149994.7-149994.40"
- process $proc$libresoc.v:149994$7851
+ attribute \src "libresoc.v:148124.7-148124.40"
+ process $proc$libresoc.v:148124$7777
assign { } { }
assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:150024.7-150024.27"
- process $proc$libresoc.v:150024$7852
+ attribute \src "libresoc.v:148154.7-148154.27"
+ process $proc$libresoc.v:148154$7778
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:150058.14-150058.47"
- process $proc$libresoc.v:150058$7853
+ attribute \src "libresoc.v:148188.14-148188.47"
+ process $proc$libresoc.v:148188$7779
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:150062.7-150062.27"
- process $proc$libresoc.v:150062$7854
+ attribute \src "libresoc.v:148192.7-148192.27"
+ process $proc$libresoc.v:148192$7780
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:150066.13-150066.33"
- process $proc$libresoc.v:150066$7855
+ attribute \src "libresoc.v:148196.13-148196.33"
+ process $proc$libresoc.v:148196$7781
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:150070.7-150070.30"
- process $proc$libresoc.v:150070$7856
+ attribute \src "libresoc.v:148200.7-148200.30"
+ process $proc$libresoc.v:148200$7782
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:150074.13-150074.35"
- process $proc$libresoc.v:150074$7857
+ attribute \src "libresoc.v:148204.13-148204.35"
+ process $proc$libresoc.v:148204$7783
assign { } { }
assign $1\data_r2__xer_ov[1:0] 2'00
sync always
sync init
update \data_r2__xer_ov $1\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:150078.7-150078.32"
- process $proc$libresoc.v:150078$7858
+ attribute \src "libresoc.v:148208.7-148208.32"
+ process $proc$libresoc.v:148208$7784
assign { } { }
assign $1\data_r2__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:150082.7-150082.29"
- process $proc$libresoc.v:150082$7859
+ attribute \src "libresoc.v:148212.7-148212.29"
+ process $proc$libresoc.v:148212$7785
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:150086.7-150086.32"
- process $proc$libresoc.v:150086$7860
+ attribute \src "libresoc.v:148216.7-148216.32"
+ process $proc$libresoc.v:148216$7786
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:150106.7-150106.25"
- process $proc$libresoc.v:150106$7861
+ attribute \src "libresoc.v:148236.7-148236.25"
+ process $proc$libresoc.v:148236$7787
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:150110.7-150110.25"
- process $proc$libresoc.v:150110$7862
+ attribute \src "libresoc.v:148240.7-148240.25"
+ process $proc$libresoc.v:148240$7788
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:150226.13-150226.30"
- process $proc$libresoc.v:150226$7863
+ attribute \src "libresoc.v:148356.13-148356.30"
+ process $proc$libresoc.v:148356$7789
assign { } { }
assign $1\prev_wr_go[3:0] 4'0000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:150234.13-150234.31"
- process $proc$libresoc.v:150234$7864
+ attribute \src "libresoc.v:148364.13-148364.31"
+ process $proc$libresoc.v:148364$7790
assign { } { }
assign $1\req_l_r_req[3:0] 4'1111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:150238.13-150238.31"
- process $proc$libresoc.v:150238$7865
+ attribute \src "libresoc.v:148368.13-148368.31"
+ process $proc$libresoc.v:148368$7791
assign { } { }
assign $1\req_l_s_req[3:0] 4'0000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:150250.7-150250.26"
- process $proc$libresoc.v:150250$7866
+ attribute \src "libresoc.v:148380.7-148380.26"
+ process $proc$libresoc.v:148380$7792
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:150254.7-150254.26"
- process $proc$libresoc.v:150254$7867
+ attribute \src "libresoc.v:148384.7-148384.26"
+ process $proc$libresoc.v:148384$7793
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:150258.7-150258.25"
- process $proc$libresoc.v:150258$7868
+ attribute \src "libresoc.v:148388.7-148388.25"
+ process $proc$libresoc.v:148388$7794
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:150262.7-150262.25"
- process $proc$libresoc.v:150262$7869
+ attribute \src "libresoc.v:148392.7-148392.25"
+ process $proc$libresoc.v:148392$7795
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:150276.13-150276.31"
- process $proc$libresoc.v:150276$7870
+ attribute \src "libresoc.v:148406.13-148406.31"
+ process $proc$libresoc.v:148406$7796
assign { } { }
assign $1\src_l_r_src[2:0] 3'111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:150280.13-150280.31"
- process $proc$libresoc.v:150280$7871
+ attribute \src "libresoc.v:148410.13-148410.31"
+ process $proc$libresoc.v:148410$7797
assign { } { }
assign $1\src_l_s_src[2:0] 3'000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:150286.14-150286.43"
- process $proc$libresoc.v:150286$7872
+ attribute \src "libresoc.v:148416.14-148416.43"
+ process $proc$libresoc.v:148416$7798
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:150290.14-150290.43"
- process $proc$libresoc.v:150290$7873
+ attribute \src "libresoc.v:148420.14-148420.43"
+ process $proc$libresoc.v:148420$7799
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:150294.7-150294.20"
- process $proc$libresoc.v:150294$7874
+ attribute \src "libresoc.v:148424.7-148424.20"
+ process $proc$libresoc.v:148424$7800
assign { } { }
assign $1\src_r2[0:0] 1'0
sync always
sync init
update \src_r2 $1\src_r2[0:0]
end
- attribute \src "libresoc.v:150365.3-150366.39"
- process $proc$libresoc.v:150365$7682
+ attribute \src "libresoc.v:148495.3-148496.39"
+ process $proc$libresoc.v:148495$7608
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:150367.3-150368.43"
- process $proc$libresoc.v:150367$7683
+ attribute \src "libresoc.v:148497.3-148498.43"
+ process $proc$libresoc.v:148497$7609
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:150369.3-150370.29"
- process $proc$libresoc.v:150369$7684
+ attribute \src "libresoc.v:148499.3-148500.29"
+ process $proc$libresoc.v:148499$7610
assign { } { }
assign $0\src_r2[0:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[0:0]
end
- attribute \src "libresoc.v:150371.3-150372.29"
- process $proc$libresoc.v:150371$7685
+ attribute \src "libresoc.v:148501.3-148502.29"
+ process $proc$libresoc.v:148501$7611
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:150373.3-150374.29"
- process $proc$libresoc.v:150373$7686
+ attribute \src "libresoc.v:148503.3-148504.29"
+ process $proc$libresoc.v:148503$7612
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:150375.3-150376.47"
- process $proc$libresoc.v:150375$7687
+ attribute \src "libresoc.v:148505.3-148506.47"
+ process $proc$libresoc.v:148505$7613
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:150377.3-150378.53"
- process $proc$libresoc.v:150377$7688
+ attribute \src "libresoc.v:148507.3-148508.53"
+ process $proc$libresoc.v:148507$7614
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:150379.3-150380.47"
- process $proc$libresoc.v:150379$7689
+ attribute \src "libresoc.v:148509.3-148510.47"
+ process $proc$libresoc.v:148509$7615
assign { } { }
assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next
sync posedge \coresync_clk
update \data_r2__xer_ov $0\data_r2__xer_ov[1:0]
end
- attribute \src "libresoc.v:150381.3-150382.53"
- process $proc$libresoc.v:150381$7690
+ attribute \src "libresoc.v:148511.3-148512.53"
+ process $proc$libresoc.v:148511$7616
assign { } { }
assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:150383.3-150384.43"
- process $proc$libresoc.v:150383$7691
+ attribute \src "libresoc.v:148513.3-148514.43"
+ process $proc$libresoc.v:148513$7617
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:150385.3-150386.49"
- process $proc$libresoc.v:150385$7692
+ attribute \src "libresoc.v:148515.3-148516.49"
+ process $proc$libresoc.v:148515$7618
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:150387.3-150388.37"
- process $proc$libresoc.v:150387$7693
+ attribute \src "libresoc.v:148517.3-148518.37"
+ process $proc$libresoc.v:148517$7619
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:150389.3-150390.43"
- process $proc$libresoc.v:150389$7694
+ attribute \src "libresoc.v:148519.3-148520.43"
+ process $proc$libresoc.v:148519$7620
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:150391.3-150392.69"
- process $proc$libresoc.v:150391$7695
+ attribute \src "libresoc.v:148521.3-148522.69"
+ process $proc$libresoc.v:148521$7621
assign { } { }
assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:150393.3-150394.65"
- process $proc$libresoc.v:150393$7696
+ attribute \src "libresoc.v:148523.3-148524.65"
+ process $proc$libresoc.v:148523$7622
assign { } { }
assign $0\alu_mul0_mul_op__fn_unit[12:0] \alu_mul0_mul_op__fn_unit$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:150395.3-150396.79"
- process $proc$libresoc.v:150395$7697
+ attribute \src "libresoc.v:148525.3-148526.79"
+ process $proc$libresoc.v:148525$7623
assign { } { }
assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:150397.3-150398.75"
- process $proc$libresoc.v:150397$7698
+ attribute \src "libresoc.v:148527.3-148528.75"
+ process $proc$libresoc.v:148527$7624
assign { } { }
assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:150399.3-150400.63"
- process $proc$libresoc.v:150399$7699
+ attribute \src "libresoc.v:148529.3-148530.63"
+ process $proc$libresoc.v:148529$7625
assign { } { }
assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:150401.3-150402.63"
- process $proc$libresoc.v:150401$7700
+ attribute \src "libresoc.v:148531.3-148532.63"
+ process $proc$libresoc.v:148531$7626
assign { } { }
assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:150403.3-150404.63"
- process $proc$libresoc.v:150403$7701
+ attribute \src "libresoc.v:148533.3-148534.63"
+ process $proc$libresoc.v:148533$7627
assign { } { }
assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:150405.3-150406.63"
- process $proc$libresoc.v:150405$7702
+ attribute \src "libresoc.v:148535.3-148536.63"
+ process $proc$libresoc.v:148535$7628
assign { } { }
assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:150407.3-150408.69"
- process $proc$libresoc.v:150407$7703
+ attribute \src "libresoc.v:148537.3-148538.69"
+ process $proc$libresoc.v:148537$7629
assign { } { }
assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:150409.3-150410.67"
- process $proc$libresoc.v:150409$7704
+ attribute \src "libresoc.v:148539.3-148540.67"
+ process $proc$libresoc.v:148539$7630
assign { } { }
assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:150411.3-150412.69"
- process $proc$libresoc.v:150411$7705
+ attribute \src "libresoc.v:148541.3-148542.69"
+ process $proc$libresoc.v:148541$7631
assign { } { }
assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:150413.3-150414.59"
- process $proc$libresoc.v:150413$7706
+ attribute \src "libresoc.v:148543.3-148544.59"
+ process $proc$libresoc.v:148543$7632
assign { } { }
assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next
sync posedge \coresync_clk
update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0]
end
- attribute \src "libresoc.v:150415.3-150416.39"
- process $proc$libresoc.v:150415$7707
+ attribute \src "libresoc.v:148545.3-148546.39"
+ process $proc$libresoc.v:148545$7633
assign { } { }
assign $0\req_l_r_req[3:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[3:0]
end
- attribute \src "libresoc.v:150417.3-150418.39"
- process $proc$libresoc.v:150417$7708
+ attribute \src "libresoc.v:148547.3-148548.39"
+ process $proc$libresoc.v:148547$7634
assign { } { }
assign $0\req_l_s_req[3:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[3:0]
end
- attribute \src "libresoc.v:150419.3-150420.39"
- process $proc$libresoc.v:150419$7709
+ attribute \src "libresoc.v:148549.3-148550.39"
+ process $proc$libresoc.v:148549$7635
assign { } { }
assign $0\src_l_r_src[2:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[2:0]
end
- attribute \src "libresoc.v:150421.3-150422.39"
- process $proc$libresoc.v:150421$7710
+ attribute \src "libresoc.v:148551.3-148552.39"
+ process $proc$libresoc.v:148551$7636
assign { } { }
assign $0\src_l_s_src[2:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[2:0]
end
- attribute \src "libresoc.v:150423.3-150424.39"
- process $proc$libresoc.v:150423$7711
+ attribute \src "libresoc.v:148553.3-148554.39"
+ process $proc$libresoc.v:148553$7637
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:150425.3-150426.39"
- process $proc$libresoc.v:150425$7712
+ attribute \src "libresoc.v:148555.3-148556.39"
+ process $proc$libresoc.v:148555$7638
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:150427.3-150428.39"
- process $proc$libresoc.v:150427$7713
+ attribute \src "libresoc.v:148557.3-148558.39"
+ process $proc$libresoc.v:148557$7639
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:150429.3-150430.39"
- process $proc$libresoc.v:150429$7714
+ attribute \src "libresoc.v:148559.3-148560.39"
+ process $proc$libresoc.v:148559$7640
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:150431.3-150432.41"
- process $proc$libresoc.v:150431$7715
+ attribute \src "libresoc.v:148561.3-148562.41"
+ process $proc$libresoc.v:148561$7641
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:150433.3-150434.41"
- process $proc$libresoc.v:150433$7716
+ attribute \src "libresoc.v:148563.3-148564.41"
+ process $proc$libresoc.v:148563$7642
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:150435.3-150436.37"
- process $proc$libresoc.v:150435$7717
+ attribute \src "libresoc.v:148565.3-148566.37"
+ process $proc$libresoc.v:148565$7643
assign { } { }
assign $0\prev_wr_go[3:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[3:0]
end
- attribute \src "libresoc.v:150437.3-150438.40"
- process $proc$libresoc.v:150437$7718
+ attribute \src "libresoc.v:148567.3-148568.40"
+ process $proc$libresoc.v:148567$7644
assign { } { }
assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:150439.3-150440.25"
- process $proc$libresoc.v:150439$7719
+ attribute \src "libresoc.v:148569.3-148570.25"
+ process $proc$libresoc.v:148569$7645
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:150520.3-150529.6"
- process $proc$libresoc.v:150520$7720
+ attribute \src "libresoc.v:148650.3-148659.6"
+ process $proc$libresoc.v:148650$7646
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:150521.5-150521.29"
+ attribute \src "libresoc.v:148651.5-148651.29"
switch \initial
- attribute \src "libresoc.v:150521.9-150521.17"
+ attribute \src "libresoc.v:148651.9-148651.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:150530.3-150538.6"
- process $proc$libresoc.v:150530$7721
+ attribute \src "libresoc.v:148660.3-148668.6"
+ process $proc$libresoc.v:148660$7647
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$7722 $1\rok_l_s_rdok$next[0:0]$7723
- attribute \src "libresoc.v:150531.5-150531.29"
+ assign $0\rok_l_s_rdok$next[0:0]$7648 $1\rok_l_s_rdok$next[0:0]$7649
+ attribute \src "libresoc.v:148661.5-148661.29"
switch \initial
- attribute \src "libresoc.v:150531.9-150531.17"
+ attribute \src "libresoc.v:148661.9-148661.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$7723 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$7649 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$7723 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$7649 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7722
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7648
end
- attribute \src "libresoc.v:150539.3-150547.6"
- process $proc$libresoc.v:150539$7724
+ attribute \src "libresoc.v:148669.3-148677.6"
+ process $proc$libresoc.v:148669$7650
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$7725 $1\rok_l_r_rdok$next[0:0]$7726
- attribute \src "libresoc.v:150540.5-150540.29"
+ assign $0\rok_l_r_rdok$next[0:0]$7651 $1\rok_l_r_rdok$next[0:0]$7652
+ attribute \src "libresoc.v:148670.5-148670.29"
switch \initial
- attribute \src "libresoc.v:150540.9-150540.17"
+ attribute \src "libresoc.v:148670.9-148670.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$7726 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$7652 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$7726 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$7652 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7725
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7651
end
- attribute \src "libresoc.v:150548.3-150556.6"
- process $proc$libresoc.v:150548$7727
+ attribute \src "libresoc.v:148678.3-148686.6"
+ process $proc$libresoc.v:148678$7653
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$7728 $1\rst_l_s_rst$next[0:0]$7729
- attribute \src "libresoc.v:150549.5-150549.29"
+ assign $0\rst_l_s_rst$next[0:0]$7654 $1\rst_l_s_rst$next[0:0]$7655
+ attribute \src "libresoc.v:148679.5-148679.29"
switch \initial
- attribute \src "libresoc.v:150549.9-150549.17"
+ attribute \src "libresoc.v:148679.9-148679.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$7729 1'0
+ assign $1\rst_l_s_rst$next[0:0]$7655 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$7729 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$7655 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7728
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7654
end
- attribute \src "libresoc.v:150557.3-150565.6"
- process $proc$libresoc.v:150557$7730
+ attribute \src "libresoc.v:148687.3-148695.6"
+ process $proc$libresoc.v:148687$7656
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$7731 $1\rst_l_r_rst$next[0:0]$7732
- attribute \src "libresoc.v:150558.5-150558.29"
+ assign $0\rst_l_r_rst$next[0:0]$7657 $1\rst_l_r_rst$next[0:0]$7658
+ attribute \src "libresoc.v:148688.5-148688.29"
switch \initial
- attribute \src "libresoc.v:150558.9-150558.17"
+ attribute \src "libresoc.v:148688.9-148688.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$7732 1'1
+ assign $1\rst_l_r_rst$next[0:0]$7658 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$7732 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$7658 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7731
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7657
end
- attribute \src "libresoc.v:150566.3-150574.6"
- process $proc$libresoc.v:150566$7733
+ attribute \src "libresoc.v:148696.3-148704.6"
+ process $proc$libresoc.v:148696$7659
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$7734 $1\opc_l_s_opc$next[0:0]$7735
- attribute \src "libresoc.v:150567.5-150567.29"
+ assign $0\opc_l_s_opc$next[0:0]$7660 $1\opc_l_s_opc$next[0:0]$7661
+ attribute \src "libresoc.v:148697.5-148697.29"
switch \initial
- attribute \src "libresoc.v:150567.9-150567.17"
+ attribute \src "libresoc.v:148697.9-148697.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$7735 1'0
+ assign $1\opc_l_s_opc$next[0:0]$7661 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$7735 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$7661 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7734
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7660
end
- attribute \src "libresoc.v:150575.3-150583.6"
- process $proc$libresoc.v:150575$7736
+ attribute \src "libresoc.v:148705.3-148713.6"
+ process $proc$libresoc.v:148705$7662
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$7737 $1\opc_l_r_opc$next[0:0]$7738
- attribute \src "libresoc.v:150576.5-150576.29"
+ assign $0\opc_l_r_opc$next[0:0]$7663 $1\opc_l_r_opc$next[0:0]$7664
+ attribute \src "libresoc.v:148706.5-148706.29"
switch \initial
- attribute \src "libresoc.v:150576.9-150576.17"
+ attribute \src "libresoc.v:148706.9-148706.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$7738 1'1
+ assign $1\opc_l_r_opc$next[0:0]$7664 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$7738 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$7664 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7737
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7663
end
- attribute \src "libresoc.v:150584.3-150592.6"
- process $proc$libresoc.v:150584$7739
+ attribute \src "libresoc.v:148714.3-148722.6"
+ process $proc$libresoc.v:148714$7665
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[2:0]$7740 $1\src_l_s_src$next[2:0]$7741
- attribute \src "libresoc.v:150585.5-150585.29"
+ assign $0\src_l_s_src$next[2:0]$7666 $1\src_l_s_src$next[2:0]$7667
+ attribute \src "libresoc.v:148715.5-148715.29"
switch \initial
- attribute \src "libresoc.v:150585.9-150585.17"
+ attribute \src "libresoc.v:148715.9-148715.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[2:0]$7741 3'000
+ assign $1\src_l_s_src$next[2:0]$7667 3'000
case
- assign $1\src_l_s_src$next[2:0]$7741 { \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[2:0]$7667 { \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7740
+ update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7666
end
- attribute \src "libresoc.v:150593.3-150601.6"
- process $proc$libresoc.v:150593$7742
+ attribute \src "libresoc.v:148723.3-148731.6"
+ process $proc$libresoc.v:148723$7668
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[2:0]$7743 $1\src_l_r_src$next[2:0]$7744
- attribute \src "libresoc.v:150594.5-150594.29"
+ assign $0\src_l_r_src$next[2:0]$7669 $1\src_l_r_src$next[2:0]$7670
+ attribute \src "libresoc.v:148724.5-148724.29"
switch \initial
- attribute \src "libresoc.v:150594.9-150594.17"
+ attribute \src "libresoc.v:148724.9-148724.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[2:0]$7744 3'111
+ assign $1\src_l_r_src$next[2:0]$7670 3'111
case
- assign $1\src_l_r_src$next[2:0]$7744 \reset_r
+ assign $1\src_l_r_src$next[2:0]$7670 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7743
+ update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7669
end
- attribute \src "libresoc.v:150602.3-150610.6"
- process $proc$libresoc.v:150602$7745
+ attribute \src "libresoc.v:148732.3-148740.6"
+ process $proc$libresoc.v:148732$7671
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[3:0]$7746 $1\req_l_s_req$next[3:0]$7747
- attribute \src "libresoc.v:150603.5-150603.29"
+ assign $0\req_l_s_req$next[3:0]$7672 $1\req_l_s_req$next[3:0]$7673
+ attribute \src "libresoc.v:148733.5-148733.29"
switch \initial
- attribute \src "libresoc.v:150603.9-150603.17"
+ attribute \src "libresoc.v:148733.9-148733.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[3:0]$7747 4'0000
+ assign $1\req_l_s_req$next[3:0]$7673 4'0000
case
- assign $1\req_l_s_req$next[3:0]$7747 \$66
+ assign $1\req_l_s_req$next[3:0]$7673 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7746
+ update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7672
end
- attribute \src "libresoc.v:150611.3-150619.6"
- process $proc$libresoc.v:150611$7748
+ attribute \src "libresoc.v:148741.3-148749.6"
+ process $proc$libresoc.v:148741$7674
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[3:0]$7749 $1\req_l_r_req$next[3:0]$7750
- attribute \src "libresoc.v:150612.5-150612.29"
+ assign $0\req_l_r_req$next[3:0]$7675 $1\req_l_r_req$next[3:0]$7676
+ attribute \src "libresoc.v:148742.5-148742.29"
switch \initial
- attribute \src "libresoc.v:150612.9-150612.17"
+ attribute \src "libresoc.v:148742.9-148742.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[3:0]$7750 4'1111
+ assign $1\req_l_r_req$next[3:0]$7676 4'1111
case
- assign $1\req_l_r_req$next[3:0]$7750 \$68
+ assign $1\req_l_r_req$next[3:0]$7676 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7749
+ update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7675
end
- attribute \src "libresoc.v:150620.3-150652.6"
- process $proc$libresoc.v:150620$7751
+ attribute \src "libresoc.v:148750.3-148782.6"
+ process $proc$libresoc.v:148750$7677
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764
+ assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__insn$next[31:0]$7755 $1\alu_mul0_mul_op__insn$next[31:0]$7767
- assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7756 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768
- assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769
- assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7758 $1\alu_mul0_mul_op__is_signed$next[0:0]$7770
+ assign $0\alu_mul0_mul_op__insn$next[31:0]$7681 $1\alu_mul0_mul_op__insn$next[31:0]$7693
+ assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7682 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694
+ assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695
+ assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7684 $1\alu_mul0_mul_op__is_signed$next[0:0]$7696
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775
- assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776
- assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777
- assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778
- assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779
- assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780
- assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781
- attribute \src "libresoc.v:150621.5-150621.29"
+ assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701
+ assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702
+ assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703
+ assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704
+ assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705
+ assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706
+ assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707
+ attribute \src "libresoc.v:148751.5-148751.29"
switch \initial
- attribute \src "libresoc.v:150621.9-150621.17"
+ attribute \src "libresoc.v:148751.9-148751.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_mul0_mul_op__insn$next[31:0]$7767 $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
+ assign { $1\alu_mul0_mul_op__insn$next[31:0]$7693 $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
case
- assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 \alu_mul0_mul_op__fn_unit
- assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 \alu_mul0_mul_op__imm_data__data
- assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 \alu_mul0_mul_op__imm_data__ok
- assign $1\alu_mul0_mul_op__insn$next[31:0]$7767 \alu_mul0_mul_op__insn
- assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 \alu_mul0_mul_op__insn_type
- assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 \alu_mul0_mul_op__is_32bit
- assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 \alu_mul0_mul_op__is_signed
- assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 \alu_mul0_mul_op__oe__oe
- assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 \alu_mul0_mul_op__oe__ok
- assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 \alu_mul0_mul_op__rc__ok
- assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 \alu_mul0_mul_op__rc__rc
- assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 \alu_mul0_mul_op__write_cr0
+ assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 \alu_mul0_mul_op__fn_unit
+ assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 \alu_mul0_mul_op__imm_data__data
+ assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 \alu_mul0_mul_op__imm_data__ok
+ assign $1\alu_mul0_mul_op__insn$next[31:0]$7693 \alu_mul0_mul_op__insn
+ assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 \alu_mul0_mul_op__insn_type
+ assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 \alu_mul0_mul_op__is_32bit
+ assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 \alu_mul0_mul_op__is_signed
+ assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 \alu_mul0_mul_op__oe__oe
+ assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 \alu_mul0_mul_op__oe__ok
+ assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 \alu_mul0_mul_op__rc__ok
+ assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 \alu_mul0_mul_op__rc__rc
+ assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 \alu_mul0_mul_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 1'0
- assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 1'0
- assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 1'0
- assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 1'0
- assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 1'0
+ assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 1'0
+ assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 1'0
+ assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 1'0
+ assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 1'0
+ assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 1'0
case
- assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765
- assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766
- assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771
- assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772
- assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773
- assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774
+ assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691
+ assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692
+ assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697
+ assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698
+ assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699
+ assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700
end
sync always
- update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752
- update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753
- update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754
- update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7755
- update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7756
- update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757
- update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7758
- update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759
- update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760
- update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761
- update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762
- update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763
+ update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678
+ update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679
+ update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680
+ update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7681
+ update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7682
+ update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683
+ update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7684
+ update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685
+ update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686
+ update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687
+ update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688
+ update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689
end
- attribute \src "libresoc.v:150653.3-150674.6"
- process $proc$libresoc.v:150653$7782
+ attribute \src "libresoc.v:148783.3-148804.6"
+ process $proc$libresoc.v:148783$7708
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$7783 $2\data_r0__o$next[63:0]$7787
+ assign $0\data_r0__o$next[63:0]$7709 $2\data_r0__o$next[63:0]$7713
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$7784 $3\data_r0__o_ok$next[0:0]$7789
- attribute \src "libresoc.v:150654.5-150654.29"
+ assign $0\data_r0__o_ok$next[0:0]$7710 $3\data_r0__o_ok$next[0:0]$7715
+ attribute \src "libresoc.v:148784.5-148784.29"
switch \initial
- attribute \src "libresoc.v:150654.9-150654.17"
+ attribute \src "libresoc.v:148784.9-148784.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$7786 $1\data_r0__o$next[63:0]$7785 } { \o_ok \alu_mul0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$7712 $1\data_r0__o$next[63:0]$7711 } { \o_ok \alu_mul0_o }
case
- assign $1\data_r0__o$next[63:0]$7785 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$7786 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$7711 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$7712 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$7788 $2\data_r0__o$next[63:0]$7787 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$7714 $2\data_r0__o$next[63:0]$7713 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$7787 $1\data_r0__o$next[63:0]$7785
- assign $2\data_r0__o_ok$next[0:0]$7788 $1\data_r0__o_ok$next[0:0]$7786
+ assign $2\data_r0__o$next[63:0]$7713 $1\data_r0__o$next[63:0]$7711
+ assign $2\data_r0__o_ok$next[0:0]$7714 $1\data_r0__o_ok$next[0:0]$7712
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$7789 1'0
+ assign $3\data_r0__o_ok$next[0:0]$7715 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$7789 $2\data_r0__o_ok$next[0:0]$7788
+ assign $3\data_r0__o_ok$next[0:0]$7715 $2\data_r0__o_ok$next[0:0]$7714
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$7783
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7784
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$7709
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7710
end
- attribute \src "libresoc.v:150675.3-150696.6"
- process $proc$libresoc.v:150675$7790
+ attribute \src "libresoc.v:148805.3-148826.6"
+ process $proc$libresoc.v:148805$7716
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$7791 $2\data_r1__cr_a$next[3:0]$7795
+ assign $0\data_r1__cr_a$next[3:0]$7717 $2\data_r1__cr_a$next[3:0]$7721
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$7792 $3\data_r1__cr_a_ok$next[0:0]$7797
- attribute \src "libresoc.v:150676.5-150676.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$7718 $3\data_r1__cr_a_ok$next[0:0]$7723
+ attribute \src "libresoc.v:148806.5-148806.29"
switch \initial
- attribute \src "libresoc.v:150676.9-150676.17"
+ attribute \src "libresoc.v:148806.9-148806.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$7794 $1\data_r1__cr_a$next[3:0]$7793 } { \cr_a_ok \alu_mul0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$7720 $1\data_r1__cr_a$next[3:0]$7719 } { \cr_a_ok \alu_mul0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$7793 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$7794 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$7719 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$7720 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$7796 $2\data_r1__cr_a$next[3:0]$7795 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$7722 $2\data_r1__cr_a$next[3:0]$7721 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$7795 $1\data_r1__cr_a$next[3:0]$7793
- assign $2\data_r1__cr_a_ok$next[0:0]$7796 $1\data_r1__cr_a_ok$next[0:0]$7794
+ assign $2\data_r1__cr_a$next[3:0]$7721 $1\data_r1__cr_a$next[3:0]$7719
+ assign $2\data_r1__cr_a_ok$next[0:0]$7722 $1\data_r1__cr_a_ok$next[0:0]$7720
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$7797 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$7723 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$7797 $2\data_r1__cr_a_ok$next[0:0]$7796
+ assign $3\data_r1__cr_a_ok$next[0:0]$7723 $2\data_r1__cr_a_ok$next[0:0]$7722
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7791
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7792
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7717
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7718
end
- attribute \src "libresoc.v:150697.3-150718.6"
- process $proc$libresoc.v:150697$7798
+ attribute \src "libresoc.v:148827.3-148848.6"
+ process $proc$libresoc.v:148827$7724
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ov$next[1:0]$7799 $2\data_r2__xer_ov$next[1:0]$7803
+ assign $0\data_r2__xer_ov$next[1:0]$7725 $2\data_r2__xer_ov$next[1:0]$7729
assign { } { }
- assign $0\data_r2__xer_ov_ok$next[0:0]$7800 $3\data_r2__xer_ov_ok$next[0:0]$7805
- attribute \src "libresoc.v:150698.5-150698.29"
+ assign $0\data_r2__xer_ov_ok$next[0:0]$7726 $3\data_r2__xer_ov_ok$next[0:0]$7731
+ attribute \src "libresoc.v:148828.5-148828.29"
switch \initial
- attribute \src "libresoc.v:150698.9-150698.17"
+ attribute \src "libresoc.v:148828.9-148828.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ov_ok$next[0:0]$7802 $1\data_r2__xer_ov$next[1:0]$7801 } { \xer_ov_ok \alu_mul0_xer_ov }
+ assign { $1\data_r2__xer_ov_ok$next[0:0]$7728 $1\data_r2__xer_ov$next[1:0]$7727 } { \xer_ov_ok \alu_mul0_xer_ov }
case
- assign $1\data_r2__xer_ov$next[1:0]$7801 \data_r2__xer_ov
- assign $1\data_r2__xer_ov_ok$next[0:0]$7802 \data_r2__xer_ov_ok
+ assign $1\data_r2__xer_ov$next[1:0]$7727 \data_r2__xer_ov
+ assign $1\data_r2__xer_ov_ok$next[0:0]$7728 \data_r2__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ov_ok$next[0:0]$7804 $2\data_r2__xer_ov$next[1:0]$7803 } 3'000
+ assign { $2\data_r2__xer_ov_ok$next[0:0]$7730 $2\data_r2__xer_ov$next[1:0]$7729 } 3'000
case
- assign $2\data_r2__xer_ov$next[1:0]$7803 $1\data_r2__xer_ov$next[1:0]$7801
- assign $2\data_r2__xer_ov_ok$next[0:0]$7804 $1\data_r2__xer_ov_ok$next[0:0]$7802
+ assign $2\data_r2__xer_ov$next[1:0]$7729 $1\data_r2__xer_ov$next[1:0]$7727
+ assign $2\data_r2__xer_ov_ok$next[0:0]$7730 $1\data_r2__xer_ov_ok$next[0:0]$7728
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ov_ok$next[0:0]$7805 1'0
+ assign $3\data_r2__xer_ov_ok$next[0:0]$7731 1'0
case
- assign $3\data_r2__xer_ov_ok$next[0:0]$7805 $2\data_r2__xer_ov_ok$next[0:0]$7804
+ assign $3\data_r2__xer_ov_ok$next[0:0]$7731 $2\data_r2__xer_ov_ok$next[0:0]$7730
end
sync always
- update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7799
- update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7800
+ update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7725
+ update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7726
end
- attribute \src "libresoc.v:150719.3-150740.6"
- process $proc$libresoc.v:150719$7806
+ attribute \src "libresoc.v:148849.3-148870.6"
+ process $proc$libresoc.v:148849$7732
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$7807 $2\data_r3__xer_so$next[0:0]$7811
+ assign $0\data_r3__xer_so$next[0:0]$7733 $2\data_r3__xer_so$next[0:0]$7737
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$7808 $3\data_r3__xer_so_ok$next[0:0]$7813
- attribute \src "libresoc.v:150720.5-150720.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$7734 $3\data_r3__xer_so_ok$next[0:0]$7739
+ attribute \src "libresoc.v:148850.5-148850.29"
switch \initial
- attribute \src "libresoc.v:150720.9-150720.17"
+ attribute \src "libresoc.v:148850.9-148850.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$7810 $1\data_r3__xer_so$next[0:0]$7809 } { \xer_so_ok \alu_mul0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$7736 $1\data_r3__xer_so$next[0:0]$7735 } { \xer_so_ok \alu_mul0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$7809 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$7810 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$7735 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$7736 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$7812 $2\data_r3__xer_so$next[0:0]$7811 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$7738 $2\data_r3__xer_so$next[0:0]$7737 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$7811 $1\data_r3__xer_so$next[0:0]$7809
- assign $2\data_r3__xer_so_ok$next[0:0]$7812 $1\data_r3__xer_so_ok$next[0:0]$7810
+ assign $2\data_r3__xer_so$next[0:0]$7737 $1\data_r3__xer_so$next[0:0]$7735
+ assign $2\data_r3__xer_so_ok$next[0:0]$7738 $1\data_r3__xer_so_ok$next[0:0]$7736
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$7813 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$7739 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$7813 $2\data_r3__xer_so_ok$next[0:0]$7812
+ assign $3\data_r3__xer_so_ok$next[0:0]$7739 $2\data_r3__xer_so_ok$next[0:0]$7738
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7807
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7808
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7733
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7734
end
- attribute \src "libresoc.v:150741.3-150750.6"
- process $proc$libresoc.v:150741$7814
+ attribute \src "libresoc.v:148871.3-148880.6"
+ process $proc$libresoc.v:148871$7740
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$7815 $1\src_r0$next[63:0]$7816
- attribute \src "libresoc.v:150742.5-150742.29"
+ assign $0\src_r0$next[63:0]$7741 $1\src_r0$next[63:0]$7742
+ attribute \src "libresoc.v:148872.5-148872.29"
switch \initial
- attribute \src "libresoc.v:150742.9-150742.17"
+ attribute \src "libresoc.v:148872.9-148872.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$7816 \src1_i
+ assign $1\src_r0$next[63:0]$7742 \src1_i
case
- assign $1\src_r0$next[63:0]$7816 \src_r0
+ assign $1\src_r0$next[63:0]$7742 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$7815
+ update \src_r0$next $0\src_r0$next[63:0]$7741
end
- attribute \src "libresoc.v:150751.3-150760.6"
- process $proc$libresoc.v:150751$7817
+ attribute \src "libresoc.v:148881.3-148890.6"
+ process $proc$libresoc.v:148881$7743
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$7818 $1\src_r1$next[63:0]$7819
- attribute \src "libresoc.v:150752.5-150752.29"
+ assign $0\src_r1$next[63:0]$7744 $1\src_r1$next[63:0]$7745
+ attribute \src "libresoc.v:148882.5-148882.29"
switch \initial
- attribute \src "libresoc.v:150752.9-150752.17"
+ attribute \src "libresoc.v:148882.9-148882.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$7819 \src_or_imm
+ assign $1\src_r1$next[63:0]$7745 \src_or_imm
case
- assign $1\src_r1$next[63:0]$7819 \src_r1
+ assign $1\src_r1$next[63:0]$7745 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$7818
+ update \src_r1$next $0\src_r1$next[63:0]$7744
end
- attribute \src "libresoc.v:150761.3-150770.6"
- process $proc$libresoc.v:150761$7820
+ attribute \src "libresoc.v:148891.3-148900.6"
+ process $proc$libresoc.v:148891$7746
assign { } { }
assign { } { }
- assign $0\src_r2$next[0:0]$7821 $1\src_r2$next[0:0]$7822
- attribute \src "libresoc.v:150762.5-150762.29"
+ assign $0\src_r2$next[0:0]$7747 $1\src_r2$next[0:0]$7748
+ attribute \src "libresoc.v:148892.5-148892.29"
switch \initial
- attribute \src "libresoc.v:150762.9-150762.17"
+ attribute \src "libresoc.v:148892.9-148892.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[0:0]$7822 \src3_i
+ assign $1\src_r2$next[0:0]$7748 \src3_i
case
- assign $1\src_r2$next[0:0]$7822 \src_r2
+ assign $1\src_r2$next[0:0]$7748 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[0:0]$7821
+ update \src_r2$next $0\src_r2$next[0:0]$7747
end
- attribute \src "libresoc.v:150771.3-150779.6"
- process $proc$libresoc.v:150771$7823
+ attribute \src "libresoc.v:148901.3-148909.6"
+ process $proc$libresoc.v:148901$7749
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$7824 $1\alui_l_r_alui$next[0:0]$7825
- attribute \src "libresoc.v:150772.5-150772.29"
+ assign $0\alui_l_r_alui$next[0:0]$7750 $1\alui_l_r_alui$next[0:0]$7751
+ attribute \src "libresoc.v:148902.5-148902.29"
switch \initial
- attribute \src "libresoc.v:150772.9-150772.17"
+ attribute \src "libresoc.v:148902.9-148902.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$7825 1'1
+ assign $1\alui_l_r_alui$next[0:0]$7751 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$7825 \$88
+ assign $1\alui_l_r_alui$next[0:0]$7751 \$88
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7824
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7750
end
- attribute \src "libresoc.v:150780.3-150788.6"
- process $proc$libresoc.v:150780$7826
+ attribute \src "libresoc.v:148910.3-148918.6"
+ process $proc$libresoc.v:148910$7752
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$7827 $1\alu_l_r_alu$next[0:0]$7828
- attribute \src "libresoc.v:150781.5-150781.29"
+ assign $0\alu_l_r_alu$next[0:0]$7753 $1\alu_l_r_alu$next[0:0]$7754
+ attribute \src "libresoc.v:148911.5-148911.29"
switch \initial
- attribute \src "libresoc.v:150781.9-150781.17"
+ attribute \src "libresoc.v:148911.9-148911.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$7828 1'1
+ assign $1\alu_l_r_alu$next[0:0]$7754 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$7828 \$90
+ assign $1\alu_l_r_alu$next[0:0]$7754 \$90
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7827
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7753
end
- attribute \src "libresoc.v:150789.3-150798.6"
- process $proc$libresoc.v:150789$7829
+ attribute \src "libresoc.v:148919.3-148928.6"
+ process $proc$libresoc.v:148919$7755
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:150790.5-150790.29"
+ attribute \src "libresoc.v:148920.5-148920.29"
switch \initial
- attribute \src "libresoc.v:150790.9-150790.17"
+ attribute \src "libresoc.v:148920.9-148920.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:150799.3-150808.6"
- process $proc$libresoc.v:150799$7830
+ attribute \src "libresoc.v:148929.3-148938.6"
+ process $proc$libresoc.v:148929$7756
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:150800.5-150800.29"
+ attribute \src "libresoc.v:148930.5-148930.29"
switch \initial
- attribute \src "libresoc.v:150800.9-150800.17"
+ attribute \src "libresoc.v:148930.9-148930.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:150809.3-150818.6"
- process $proc$libresoc.v:150809$7831
+ attribute \src "libresoc.v:148939.3-148948.6"
+ process $proc$libresoc.v:148939$7757
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:150810.5-150810.29"
+ attribute \src "libresoc.v:148940.5-148940.29"
switch \initial
- attribute \src "libresoc.v:150810.9-150810.17"
+ attribute \src "libresoc.v:148940.9-148940.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:150819.3-150828.6"
- process $proc$libresoc.v:150819$7832
+ attribute \src "libresoc.v:148949.3-148958.6"
+ process $proc$libresoc.v:148949$7758
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:150820.5-150820.29"
+ attribute \src "libresoc.v:148950.5-148950.29"
switch \initial
- attribute \src "libresoc.v:150820.9-150820.17"
+ attribute \src "libresoc.v:148950.9-148950.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:150829.3-150837.6"
- process $proc$libresoc.v:150829$7833
+ attribute \src "libresoc.v:148959.3-148967.6"
+ process $proc$libresoc.v:148959$7759
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[3:0]$7834 $1\prev_wr_go$next[3:0]$7835
- attribute \src "libresoc.v:150830.5-150830.29"
+ assign $0\prev_wr_go$next[3:0]$7760 $1\prev_wr_go$next[3:0]$7761
+ attribute \src "libresoc.v:148960.5-148960.29"
switch \initial
- attribute \src "libresoc.v:150830.9-150830.17"
+ attribute \src "libresoc.v:148960.9-148960.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[3:0]$7835 4'0000
- case
- assign $1\prev_wr_go$next[3:0]$7835 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7834
- end
- connect \$100 $and$libresoc.v:150305$7622_Y
- connect \$102 $and$libresoc.v:150306$7623_Y
- connect \$104 $and$libresoc.v:150307$7624_Y
- connect \$106 $and$libresoc.v:150308$7625_Y
- connect \$108 $and$libresoc.v:150309$7626_Y
- connect \$10 $and$libresoc.v:150310$7627_Y
- connect \$110 $and$libresoc.v:150311$7628_Y
- connect \$112 $and$libresoc.v:150312$7629_Y
- connect \$114 $and$libresoc.v:150313$7630_Y
- connect \$116 $and$libresoc.v:150314$7631_Y
- connect \$118 $and$libresoc.v:150315$7632_Y
- connect \$120 $and$libresoc.v:150316$7633_Y
- connect \$12 $not$libresoc.v:150317$7634_Y
- connect \$14 $and$libresoc.v:150318$7635_Y
- connect \$16 $not$libresoc.v:150319$7636_Y
- connect \$18 $and$libresoc.v:150320$7637_Y
- connect \$20 $and$libresoc.v:150321$7638_Y
- connect \$24 $not$libresoc.v:150322$7639_Y
- connect \$26 $and$libresoc.v:150323$7640_Y
- connect \$23 $reduce_or$libresoc.v:150324$7641_Y
- connect \$22 $not$libresoc.v:150325$7642_Y
- connect \$2 $and$libresoc.v:150326$7643_Y
- connect \$30 $and$libresoc.v:150327$7644_Y
- connect \$32 $reduce_or$libresoc.v:150328$7645_Y
- connect \$34 $reduce_or$libresoc.v:150329$7646_Y
- connect \$36 $or$libresoc.v:150330$7647_Y
- connect \$38 $not$libresoc.v:150331$7648_Y
- connect \$40 $and$libresoc.v:150332$7649_Y
- connect \$42 $and$libresoc.v:150333$7650_Y
- connect \$44 $eq$libresoc.v:150334$7651_Y
- connect \$46 $and$libresoc.v:150335$7652_Y
- connect \$48 $eq$libresoc.v:150336$7653_Y
- connect \$50 $and$libresoc.v:150337$7654_Y
- connect \$52 $and$libresoc.v:150338$7655_Y
- connect \$54 $and$libresoc.v:150339$7656_Y
- connect \$56 $or$libresoc.v:150340$7657_Y
- connect \$58 $or$libresoc.v:150341$7658_Y
- connect \$5 $not$libresoc.v:150342$7659_Y
- connect \$60 $or$libresoc.v:150343$7660_Y
- connect \$62 $or$libresoc.v:150344$7661_Y
- connect \$64 $and$libresoc.v:150345$7662_Y
- connect \$66 $and$libresoc.v:150346$7663_Y
- connect \$68 $or$libresoc.v:150347$7664_Y
- connect \$70 $and$libresoc.v:150348$7665_Y
- connect \$72 $and$libresoc.v:150349$7666_Y
- connect \$74 $and$libresoc.v:150350$7667_Y
- connect \$76 $and$libresoc.v:150351$7668_Y
- connect \$78 $ternary$libresoc.v:150352$7669_Y
- connect \$7 $or$libresoc.v:150353$7670_Y
- connect \$80 $ternary$libresoc.v:150354$7671_Y
- connect \$82 $ternary$libresoc.v:150355$7672_Y
- connect \$84 $ternary$libresoc.v:150356$7673_Y
- connect \$86 $ternary$libresoc.v:150357$7674_Y
- connect \$88 $and$libresoc.v:150358$7675_Y
- connect \$4 $reduce_and$libresoc.v:150359$7676_Y
- connect \$90 $and$libresoc.v:150360$7677_Y
- connect \$92 $and$libresoc.v:150361$7678_Y
- connect \$94 $not$libresoc.v:150362$7679_Y
- connect \$96 $and$libresoc.v:150363$7680_Y
- connect \$98 $not$libresoc.v:150364$7681_Y
+ assign $1\prev_wr_go$next[3:0]$7761 4'0000
+ case
+ assign $1\prev_wr_go$next[3:0]$7761 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7760
+ end
+ connect \$100 $and$libresoc.v:148435$7548_Y
+ connect \$102 $and$libresoc.v:148436$7549_Y
+ connect \$104 $and$libresoc.v:148437$7550_Y
+ connect \$106 $and$libresoc.v:148438$7551_Y
+ connect \$108 $and$libresoc.v:148439$7552_Y
+ connect \$10 $and$libresoc.v:148440$7553_Y
+ connect \$110 $and$libresoc.v:148441$7554_Y
+ connect \$112 $and$libresoc.v:148442$7555_Y
+ connect \$114 $and$libresoc.v:148443$7556_Y
+ connect \$116 $and$libresoc.v:148444$7557_Y
+ connect \$118 $and$libresoc.v:148445$7558_Y
+ connect \$120 $and$libresoc.v:148446$7559_Y
+ connect \$12 $not$libresoc.v:148447$7560_Y
+ connect \$14 $and$libresoc.v:148448$7561_Y
+ connect \$16 $not$libresoc.v:148449$7562_Y
+ connect \$18 $and$libresoc.v:148450$7563_Y
+ connect \$20 $and$libresoc.v:148451$7564_Y
+ connect \$24 $not$libresoc.v:148452$7565_Y
+ connect \$26 $and$libresoc.v:148453$7566_Y
+ connect \$23 $reduce_or$libresoc.v:148454$7567_Y
+ connect \$22 $not$libresoc.v:148455$7568_Y
+ connect \$2 $and$libresoc.v:148456$7569_Y
+ connect \$30 $and$libresoc.v:148457$7570_Y
+ connect \$32 $reduce_or$libresoc.v:148458$7571_Y
+ connect \$34 $reduce_or$libresoc.v:148459$7572_Y
+ connect \$36 $or$libresoc.v:148460$7573_Y
+ connect \$38 $not$libresoc.v:148461$7574_Y
+ connect \$40 $and$libresoc.v:148462$7575_Y
+ connect \$42 $and$libresoc.v:148463$7576_Y
+ connect \$44 $eq$libresoc.v:148464$7577_Y
+ connect \$46 $and$libresoc.v:148465$7578_Y
+ connect \$48 $eq$libresoc.v:148466$7579_Y
+ connect \$50 $and$libresoc.v:148467$7580_Y
+ connect \$52 $and$libresoc.v:148468$7581_Y
+ connect \$54 $and$libresoc.v:148469$7582_Y
+ connect \$56 $or$libresoc.v:148470$7583_Y
+ connect \$58 $or$libresoc.v:148471$7584_Y
+ connect \$5 $not$libresoc.v:148472$7585_Y
+ connect \$60 $or$libresoc.v:148473$7586_Y
+ connect \$62 $or$libresoc.v:148474$7587_Y
+ connect \$64 $and$libresoc.v:148475$7588_Y
+ connect \$66 $and$libresoc.v:148476$7589_Y
+ connect \$68 $or$libresoc.v:148477$7590_Y
+ connect \$70 $and$libresoc.v:148478$7591_Y
+ connect \$72 $and$libresoc.v:148479$7592_Y
+ connect \$74 $and$libresoc.v:148480$7593_Y
+ connect \$76 $and$libresoc.v:148481$7594_Y
+ connect \$78 $ternary$libresoc.v:148482$7595_Y
+ connect \$7 $or$libresoc.v:148483$7596_Y
+ connect \$80 $ternary$libresoc.v:148484$7597_Y
+ connect \$82 $ternary$libresoc.v:148485$7598_Y
+ connect \$84 $ternary$libresoc.v:148486$7599_Y
+ connect \$86 $ternary$libresoc.v:148487$7600_Y
+ connect \$88 $and$libresoc.v:148488$7601_Y
+ connect \$4 $reduce_and$libresoc.v:148489$7602_Y
+ connect \$90 $and$libresoc.v:148490$7603_Y
+ connect \$92 $and$libresoc.v:148491$7604_Y
+ connect \$94 $not$libresoc.v:148492$7605_Y
+ connect \$96 $and$libresoc.v:148493$7606_Y
+ connect \$98 $not$libresoc.v:148494$7607_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$112
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:150872.1-151201.10"
+attribute \src "libresoc.v:149002.1-149331.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
attribute \generator "nMigen"
module \mul1
- attribute \src "libresoc.v:151168.18-151168.116"
- wire $and$libresoc.v:151168$7876_Y
- attribute \src "libresoc.v:151170.18-151170.116"
- wire $and$libresoc.v:151170$7878_Y
- attribute \src "libresoc.v:151171.18-151171.117"
- wire $and$libresoc.v:151171$7879_Y
- attribute \src "libresoc.v:151172.18-151172.117"
- wire $and$libresoc.v:151172$7880_Y
- attribute \src "libresoc.v:151175.18-151175.95"
- wire width 65 $extend$libresoc.v:151175$7883_Y
- attribute \src "libresoc.v:151176.18-151176.91"
- wire width 65 $extend$libresoc.v:151176$7885_Y
- attribute \src "libresoc.v:151178.18-151178.95"
- wire width 65 $extend$libresoc.v:151178$7888_Y
- attribute \src "libresoc.v:151179.18-151179.91"
- wire width 65 $extend$libresoc.v:151179$7890_Y
- attribute \src "libresoc.v:151175.18-151175.95"
- wire width 65 $neg$libresoc.v:151175$7884_Y
- attribute \src "libresoc.v:151178.18-151178.95"
- wire width 65 $neg$libresoc.v:151178$7889_Y
- attribute \src "libresoc.v:151176.18-151176.91"
- wire width 65 $pos$libresoc.v:151176$7886_Y
- attribute \src "libresoc.v:151179.18-151179.91"
- wire width 65 $pos$libresoc.v:151179$7891_Y
- attribute \src "libresoc.v:151167.18-151167.125"
- wire $ternary$libresoc.v:151167$7875_Y
- attribute \src "libresoc.v:151169.18-151169.125"
- wire $ternary$libresoc.v:151169$7877_Y
- attribute \src "libresoc.v:151177.18-151177.112"
- wire width 65 $ternary$libresoc.v:151177$7887_Y
- attribute \src "libresoc.v:151180.18-151180.112"
- wire width 65 $ternary$libresoc.v:151180$7892_Y
- attribute \src "libresoc.v:151181.18-151181.116"
- wire width 32 $ternary$libresoc.v:151181$7893_Y
- attribute \src "libresoc.v:151182.18-151182.116"
- wire width 32 $ternary$libresoc.v:151182$7894_Y
- attribute \src "libresoc.v:151173.18-151173.106"
- wire $xor$libresoc.v:151173$7881_Y
- attribute \src "libresoc.v:151174.18-151174.110"
- wire $xor$libresoc.v:151174$7882_Y
+ attribute \src "libresoc.v:149298.18-149298.116"
+ wire $and$libresoc.v:149298$7802_Y
+ attribute \src "libresoc.v:149300.18-149300.116"
+ wire $and$libresoc.v:149300$7804_Y
+ attribute \src "libresoc.v:149301.18-149301.117"
+ wire $and$libresoc.v:149301$7805_Y
+ attribute \src "libresoc.v:149302.18-149302.117"
+ wire $and$libresoc.v:149302$7806_Y
+ attribute \src "libresoc.v:149305.18-149305.95"
+ wire width 65 $extend$libresoc.v:149305$7809_Y
+ attribute \src "libresoc.v:149306.18-149306.91"
+ wire width 65 $extend$libresoc.v:149306$7811_Y
+ attribute \src "libresoc.v:149308.18-149308.95"
+ wire width 65 $extend$libresoc.v:149308$7814_Y
+ attribute \src "libresoc.v:149309.18-149309.91"
+ wire width 65 $extend$libresoc.v:149309$7816_Y
+ attribute \src "libresoc.v:149305.18-149305.95"
+ wire width 65 $neg$libresoc.v:149305$7810_Y
+ attribute \src "libresoc.v:149308.18-149308.95"
+ wire width 65 $neg$libresoc.v:149308$7815_Y
+ attribute \src "libresoc.v:149306.18-149306.91"
+ wire width 65 $pos$libresoc.v:149306$7812_Y
+ attribute \src "libresoc.v:149309.18-149309.91"
+ wire width 65 $pos$libresoc.v:149309$7817_Y
+ attribute \src "libresoc.v:149297.18-149297.125"
+ wire $ternary$libresoc.v:149297$7801_Y
+ attribute \src "libresoc.v:149299.18-149299.125"
+ wire $ternary$libresoc.v:149299$7803_Y
+ attribute \src "libresoc.v:149307.18-149307.112"
+ wire width 65 $ternary$libresoc.v:149307$7813_Y
+ attribute \src "libresoc.v:149310.18-149310.112"
+ wire width 65 $ternary$libresoc.v:149310$7818_Y
+ attribute \src "libresoc.v:149311.18-149311.116"
+ wire width 32 $ternary$libresoc.v:149311$7819_Y
+ attribute \src "libresoc.v:149312.18-149312.116"
+ wire width 32 $ternary$libresoc.v:149312$7820_Y
+ attribute \src "libresoc.v:149303.18-149303.106"
+ wire $xor$libresoc.v:149303$7807_Y
+ attribute \src "libresoc.v:149304.18-149304.110"
+ wire $xor$libresoc.v:149304$7808_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
wire \$17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 31 \xer_so$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
- cell $and $and$libresoc.v:151168$7876
+ cell $and $and$libresoc.v:149298$7802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$17
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:151168$7876_Y
+ connect \Y $and$libresoc.v:149298$7802_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
- cell $and $and$libresoc.v:151170$7878
+ cell $and $and$libresoc.v:149300$7804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$21
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:151170$7878_Y
+ connect \Y $and$libresoc.v:149300$7804_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
- cell $and $and$libresoc.v:151171$7879
+ cell $and $and$libresoc.v:149301$7805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31]
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:151171$7879_Y
+ connect \Y $and$libresoc.v:149301$7805_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
- cell $and $and$libresoc.v:151172$7880
+ cell $and $and$libresoc.v:149302$7806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rb [31]
connect \B \mul_op__is_signed
- connect \Y $and$libresoc.v:151172$7880_Y
+ connect \Y $and$libresoc.v:149302$7806_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $pos $extend$libresoc.v:151175$7883
+ cell $pos $extend$libresoc.v:149305$7809
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:151175$7883_Y
+ connect \Y $extend$libresoc.v:149305$7809_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:151176$7885
+ cell $pos $extend$libresoc.v:149306$7811
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:151176$7885_Y
+ connect \Y $extend$libresoc.v:149306$7811_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $pos $extend$libresoc.v:151178$7888
+ cell $pos $extend$libresoc.v:149308$7814
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:151178$7888_Y
+ connect \Y $extend$libresoc.v:149308$7814_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:151179$7890
+ cell $pos $extend$libresoc.v:149309$7816
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:151179$7890_Y
+ connect \Y $extend$libresoc.v:149309$7816_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $neg $neg$libresoc.v:151175$7884
+ cell $neg $neg$libresoc.v:149305$7810
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:151175$7883_Y
- connect \Y $neg$libresoc.v:151175$7884_Y
+ connect \A $extend$libresoc.v:149305$7809_Y
+ connect \Y $neg$libresoc.v:149305$7810_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $neg $neg$libresoc.v:151178$7889
+ cell $neg $neg$libresoc.v:149308$7815
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:151178$7888_Y
- connect \Y $neg$libresoc.v:151178$7889_Y
+ connect \A $extend$libresoc.v:149308$7814_Y
+ connect \Y $neg$libresoc.v:149308$7815_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:151176$7886
+ cell $pos $pos$libresoc.v:149306$7812
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:151176$7885_Y
- connect \Y $pos$libresoc.v:151176$7886_Y
+ connect \A $extend$libresoc.v:149306$7811_Y
+ connect \Y $pos$libresoc.v:149306$7812_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:151179$7891
+ cell $pos $pos$libresoc.v:149309$7817
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:151179$7890_Y
- connect \Y $pos$libresoc.v:151179$7891_Y
+ connect \A $extend$libresoc.v:149309$7816_Y
+ connect \Y $pos$libresoc.v:149309$7817_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
- cell $mux $ternary$libresoc.v:151167$7875
+ cell $mux $ternary$libresoc.v:149297$7801
parameter \WIDTH 1
connect \A \ra [63]
connect \B \ra [31]
connect \S \mul_op__is_32bit
- connect \Y $ternary$libresoc.v:151167$7875_Y
+ connect \Y $ternary$libresoc.v:149297$7801_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
- cell $mux $ternary$libresoc.v:151169$7877
+ cell $mux $ternary$libresoc.v:149299$7803
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \mul_op__is_32bit
- connect \Y $ternary$libresoc.v:151169$7877_Y
+ connect \Y $ternary$libresoc.v:149299$7803_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
- cell $mux $ternary$libresoc.v:151177$7887
+ cell $mux $ternary$libresoc.v:149307$7813
parameter \WIDTH 65
connect \A \$36
connect \B \$34
connect \S \sign_a
- connect \Y $ternary$libresoc.v:151177$7887_Y
+ connect \Y $ternary$libresoc.v:149307$7813_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
- cell $mux $ternary$libresoc.v:151180$7892
+ cell $mux $ternary$libresoc.v:149310$7818
parameter \WIDTH 65
connect \A \$43
connect \B \$41
connect \S \sign_b
- connect \Y $ternary$libresoc.v:151180$7892_Y
+ connect \Y $ternary$libresoc.v:149310$7818_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:151181$7893
+ cell $mux $ternary$libresoc.v:149311$7819
parameter \WIDTH 32
connect \A \abs_a [63:32]
connect \B 0
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:151181$7893_Y
+ connect \Y $ternary$libresoc.v:149311$7819_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:151182$7894
+ cell $mux $ternary$libresoc.v:149312$7820
parameter \WIDTH 32
connect \A \abs_b [63:32]
connect \B 0
connect \S \is_32bit
- connect \Y $ternary$libresoc.v:151182$7894_Y
+ connect \Y $ternary$libresoc.v:149312$7820_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
- cell $xor $xor$libresoc.v:151173$7881
+ cell $xor $xor$libresoc.v:149303$7807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sign_a
connect \B \sign_b
- connect \Y $xor$libresoc.v:151173$7881_Y
+ connect \Y $xor$libresoc.v:149303$7807_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
- cell $xor $xor$libresoc.v:151174$7882
+ cell $xor $xor$libresoc.v:149304$7808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sign32_a
connect \B \sign32_b
- connect \Y $xor$libresoc.v:151174$7882_Y
- end
- connect \$17 $ternary$libresoc.v:151167$7875_Y
- connect \$19 $and$libresoc.v:151168$7876_Y
- connect \$21 $ternary$libresoc.v:151169$7877_Y
- connect \$23 $and$libresoc.v:151170$7878_Y
- connect \$25 $and$libresoc.v:151171$7879_Y
- connect \$27 $and$libresoc.v:151172$7880_Y
- connect \$29 $xor$libresoc.v:151173$7881_Y
- connect \$31 $xor$libresoc.v:151174$7882_Y
- connect \$34 $neg$libresoc.v:151175$7884_Y
- connect \$36 $pos$libresoc.v:151176$7886_Y
- connect \$38 $ternary$libresoc.v:151177$7887_Y
- connect \$41 $neg$libresoc.v:151178$7889_Y
- connect \$43 $pos$libresoc.v:151179$7891_Y
- connect \$45 $ternary$libresoc.v:151180$7892_Y
- connect \$47 $ternary$libresoc.v:151181$7893_Y
- connect \$49 $ternary$libresoc.v:151182$7894_Y
+ connect \Y $xor$libresoc.v:149304$7808_Y
+ end
+ connect \$17 $ternary$libresoc.v:149297$7801_Y
+ connect \$19 $and$libresoc.v:149298$7802_Y
+ connect \$21 $ternary$libresoc.v:149299$7803_Y
+ connect \$23 $and$libresoc.v:149300$7804_Y
+ connect \$25 $and$libresoc.v:149301$7805_Y
+ connect \$27 $and$libresoc.v:149302$7806_Y
+ connect \$29 $xor$libresoc.v:149303$7807_Y
+ connect \$31 $xor$libresoc.v:149304$7808_Y
+ connect \$34 $neg$libresoc.v:149305$7810_Y
+ connect \$36 $pos$libresoc.v:149306$7812_Y
+ connect \$38 $ternary$libresoc.v:149307$7813_Y
+ connect \$41 $neg$libresoc.v:149308$7815_Y
+ connect \$43 $pos$libresoc.v:149309$7817_Y
+ connect \$45 $ternary$libresoc.v:149310$7818_Y
+ connect \$47 $ternary$libresoc.v:149311$7819_Y
+ connect \$49 $ternary$libresoc.v:149312$7820_Y
connect \$33 \$38
connect \$40 \$45
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \sign_a \$19
connect \is_32bit \mul_op__is_32bit
end
-attribute \src "libresoc.v:151205.1-151464.10"
+attribute \src "libresoc.v:149335.1-149594.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
attribute \generator "nMigen"
module \mul2
- attribute \src "libresoc.v:151457.18-151457.98"
- wire width 129 $extend$libresoc.v:151457$7896_Y
- attribute \src "libresoc.v:151456.18-151456.99"
- wire width 128 $mul$libresoc.v:151456$7895_Y
- attribute \src "libresoc.v:151457.18-151457.98"
- wire width 129 $pos$libresoc.v:151457$7897_Y
+ attribute \src "libresoc.v:149587.18-149587.98"
+ wire width 129 $extend$libresoc.v:149587$7822_Y
+ attribute \src "libresoc.v:149586.18-149586.99"
+ wire width 128 $mul$libresoc.v:149586$7821_Y
+ attribute \src "libresoc.v:149587.18-149587.98"
+ wire width 129 $pos$libresoc.v:149587$7823_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
wire width 129 \$17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 32 \xer_so$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $pos $extend$libresoc.v:151457$7896
+ cell $pos $extend$libresoc.v:149587$7822
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \Y_WIDTH 129
connect \A \$18
- connect \Y $extend$libresoc.v:151457$7896_Y
+ connect \Y $extend$libresoc.v:149587$7822_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $mul $mul$libresoc.v:151456$7895
+ cell $mul $mul$libresoc.v:149586$7821
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 128
connect \A \ra
connect \B \rb
- connect \Y $mul$libresoc.v:151456$7895_Y
+ connect \Y $mul$libresoc.v:149586$7821_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
- cell $pos $pos$libresoc.v:151457$7897
+ cell $pos $pos$libresoc.v:149587$7823
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 129
- connect \A $extend$libresoc.v:151457$7896_Y
- connect \Y $pos$libresoc.v:151457$7897_Y
+ connect \A $extend$libresoc.v:149587$7822_Y
+ connect \Y $pos$libresoc.v:149587$7823_Y
end
- connect \$18 $mul$libresoc.v:151456$7895_Y
- connect \$17 $pos$libresoc.v:151457$7897_Y
+ connect \$18 $mul$libresoc.v:149586$7821_Y
+ connect \$17 $pos$libresoc.v:149587$7823_Y
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \xer_so$14 \xer_so
connect \neg_res$15 \neg_res
connect \o \$17
end
-attribute \src "libresoc.v:151468.1-151849.10"
+attribute \src "libresoc.v:149598.1-149979.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
attribute \generator "nMigen"
module \mul3
- attribute \src "libresoc.v:151469.7-151469.20"
+ attribute \src "libresoc.v:149599.7-149599.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:151802.3-151820.6"
+ attribute \src "libresoc.v:149932.3-149950.6"
wire $0\mul_ov[0:0]
- attribute \src "libresoc.v:151764.3-151782.6"
- wire width 64 $0\o$14[63:0]$7914
- attribute \src "libresoc.v:151783.3-151801.6"
+ attribute \src "libresoc.v:149894.3-149912.6"
+ wire width 64 $0\o$14[63:0]$7840
+ attribute \src "libresoc.v:149913.3-149931.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:151821.3-151831.6"
+ attribute \src "libresoc.v:149951.3-149961.6"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:151832.3-151842.6"
+ attribute \src "libresoc.v:149962.3-149972.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:151802.3-151820.6"
+ attribute \src "libresoc.v:149932.3-149950.6"
wire $1\mul_ov[0:0]
- attribute \src "libresoc.v:151764.3-151782.6"
- wire width 64 $1\o$14[63:0]$7915
- attribute \src "libresoc.v:151783.3-151801.6"
+ attribute \src "libresoc.v:149894.3-149912.6"
+ wire width 64 $1\o$14[63:0]$7841
+ attribute \src "libresoc.v:149913.3-149931.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:151821.3-151831.6"
+ attribute \src "libresoc.v:149951.3-149961.6"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:151832.3-151842.6"
+ attribute \src "libresoc.v:149962.3-149972.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:151802.3-151820.6"
+ attribute \src "libresoc.v:149932.3-149950.6"
wire $2\mul_ov[0:0]
- attribute \src "libresoc.v:151758.18-151758.104"
- wire $and$libresoc.v:151758$7906_Y
- attribute \src "libresoc.v:151762.18-151762.104"
- wire $and$libresoc.v:151762$7910_Y
- attribute \src "libresoc.v:151752.18-151752.95"
- wire width 130 $extend$libresoc.v:151752$7898_Y
- attribute \src "libresoc.v:151753.18-151753.90"
- wire width 130 $extend$libresoc.v:151753$7900_Y
- attribute \src "libresoc.v:151763.18-151763.95"
- wire width 2 $extend$libresoc.v:151763$7911_Y
- attribute \src "libresoc.v:151752.18-151752.95"
- wire width 130 $neg$libresoc.v:151752$7899_Y
- attribute \src "libresoc.v:151757.18-151757.98"
- wire $not$libresoc.v:151757$7905_Y
- attribute \src "libresoc.v:151761.18-151761.98"
- wire $not$libresoc.v:151761$7909_Y
- attribute \src "libresoc.v:151753.18-151753.90"
- wire width 130 $pos$libresoc.v:151753$7901_Y
- attribute \src "libresoc.v:151763.18-151763.95"
- wire width 2 $pos$libresoc.v:151763$7912_Y
- attribute \src "libresoc.v:151756.18-151756.106"
- wire $reduce_and$libresoc.v:151756$7904_Y
- attribute \src "libresoc.v:151760.18-151760.107"
- wire $reduce_and$libresoc.v:151760$7908_Y
- attribute \src "libresoc.v:151755.18-151755.106"
- wire $reduce_or$libresoc.v:151755$7903_Y
- attribute \src "libresoc.v:151759.18-151759.107"
- wire $reduce_or$libresoc.v:151759$7907_Y
- attribute \src "libresoc.v:151754.18-151754.114"
- wire width 130 $ternary$libresoc.v:151754$7902_Y
+ attribute \src "libresoc.v:149888.18-149888.104"
+ wire $and$libresoc.v:149888$7832_Y
+ attribute \src "libresoc.v:149892.18-149892.104"
+ wire $and$libresoc.v:149892$7836_Y
+ attribute \src "libresoc.v:149882.18-149882.95"
+ wire width 130 $extend$libresoc.v:149882$7824_Y
+ attribute \src "libresoc.v:149883.18-149883.90"
+ wire width 130 $extend$libresoc.v:149883$7826_Y
+ attribute \src "libresoc.v:149893.18-149893.95"
+ wire width 2 $extend$libresoc.v:149893$7837_Y
+ attribute \src "libresoc.v:149882.18-149882.95"
+ wire width 130 $neg$libresoc.v:149882$7825_Y
+ attribute \src "libresoc.v:149887.18-149887.98"
+ wire $not$libresoc.v:149887$7831_Y
+ attribute \src "libresoc.v:149891.18-149891.98"
+ wire $not$libresoc.v:149891$7835_Y
+ attribute \src "libresoc.v:149883.18-149883.90"
+ wire width 130 $pos$libresoc.v:149883$7827_Y
+ attribute \src "libresoc.v:149893.18-149893.95"
+ wire width 2 $pos$libresoc.v:149893$7838_Y
+ attribute \src "libresoc.v:149886.18-149886.106"
+ wire $reduce_and$libresoc.v:149886$7830_Y
+ attribute \src "libresoc.v:149890.18-149890.107"
+ wire $reduce_and$libresoc.v:149890$7834_Y
+ attribute \src "libresoc.v:149885.18-149885.106"
+ wire $reduce_or$libresoc.v:149885$7829_Y
+ attribute \src "libresoc.v:149889.18-149889.107"
+ wire $reduce_or$libresoc.v:149889$7833_Y
+ attribute \src "libresoc.v:149884.18-149884.114"
+ wire width 130 $ternary$libresoc.v:149884$7828_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
wire width 130 \$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
wire \$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \$39
- attribute \src "libresoc.v:151469.7-151469.15"
+ attribute \src "libresoc.v:149599.7-149599.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
wire \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 34 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $and $and$libresoc.v:151758$7906
+ cell $and $and$libresoc.v:149888$7832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $and$libresoc.v:151758$7906_Y
+ connect \Y $and$libresoc.v:149888$7832_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $and $and$libresoc.v:151762$7910
+ cell $and $and$libresoc.v:149892$7836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$31
connect \B \$33
- connect \Y $and$libresoc.v:151762$7910_Y
+ connect \Y $and$libresoc.v:149892$7836_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $pos $extend$libresoc.v:151752$7898
+ cell $pos $extend$libresoc.v:149882$7824
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 130
connect \A \o
- connect \Y $extend$libresoc.v:151752$7898_Y
+ connect \Y $extend$libresoc.v:149882$7824_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:151753$7900
+ cell $pos $extend$libresoc.v:149883$7826
parameter \A_SIGNED 0
parameter \A_WIDTH 129
parameter \Y_WIDTH 130
connect \A \o
- connect \Y $extend$libresoc.v:151753$7900_Y
+ connect \Y $extend$libresoc.v:149883$7826_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:151763$7911
+ cell $pos $extend$libresoc.v:149893$7837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 2
connect \A \xer_so
- connect \Y $extend$libresoc.v:151763$7911_Y
+ connect \Y $extend$libresoc.v:149893$7837_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $neg $neg$libresoc.v:151752$7899
+ cell $neg $neg$libresoc.v:149882$7825
parameter \A_SIGNED 0
parameter \A_WIDTH 130
parameter \Y_WIDTH 130
- connect \A $extend$libresoc.v:151752$7898_Y
- connect \Y $neg$libresoc.v:151752$7899_Y
+ connect \A $extend$libresoc.v:149882$7824_Y
+ connect \Y $neg$libresoc.v:149882$7825_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $not $not$libresoc.v:151757$7905
+ cell $not $not$libresoc.v:149887$7831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $not$libresoc.v:151757$7905_Y
+ connect \Y $not$libresoc.v:149887$7831_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $not $not$libresoc.v:151761$7909
+ cell $not $not$libresoc.v:149891$7835
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$34
- connect \Y $not$libresoc.v:151761$7909_Y
+ connect \Y $not$libresoc.v:149891$7835_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:151753$7901
+ cell $pos $pos$libresoc.v:149883$7827
parameter \A_SIGNED 0
parameter \A_WIDTH 130
parameter \Y_WIDTH 130
- connect \A $extend$libresoc.v:151753$7900_Y
- connect \Y $pos$libresoc.v:151753$7901_Y
+ connect \A $extend$libresoc.v:149883$7826_Y
+ connect \Y $pos$libresoc.v:149883$7827_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:151763$7912
+ cell $pos $pos$libresoc.v:149893$7838
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $extend$libresoc.v:151763$7911_Y
- connect \Y $pos$libresoc.v:151763$7912_Y
+ connect \A $extend$libresoc.v:149893$7837_Y
+ connect \Y $pos$libresoc.v:149893$7838_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $reduce_and $reduce_and$libresoc.v:151756$7904
+ cell $reduce_and $reduce_and$libresoc.v:149886$7830
parameter \A_SIGNED 0
parameter \A_WIDTH 33
parameter \Y_WIDTH 1
connect \A \mul_o [63:31]
- connect \Y $reduce_and$libresoc.v:151756$7904_Y
+ connect \Y $reduce_and$libresoc.v:149886$7830_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $reduce_and $reduce_and$libresoc.v:151760$7908
+ cell $reduce_and $reduce_and$libresoc.v:149890$7834
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 1
connect \A \mul_o [127:63]
- connect \Y $reduce_and$libresoc.v:151760$7908_Y
+ connect \Y $reduce_and$libresoc.v:149890$7834_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
- cell $reduce_or $reduce_or$libresoc.v:151755$7903
+ cell $reduce_or $reduce_or$libresoc.v:149885$7829
parameter \A_SIGNED 0
parameter \A_WIDTH 33
parameter \Y_WIDTH 1
connect \A \mul_o [63:31]
- connect \Y $reduce_or$libresoc.v:151755$7903_Y
+ connect \Y $reduce_or$libresoc.v:149885$7829_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70"
- cell $reduce_or $reduce_or$libresoc.v:151759$7907
+ cell $reduce_or $reduce_or$libresoc.v:149889$7833
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 1
connect \A \mul_o [127:63]
- connect \Y $reduce_or$libresoc.v:151759$7907_Y
+ connect \Y $reduce_or$libresoc.v:149889$7833_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
- cell $mux $ternary$libresoc.v:151754$7902
+ cell $mux $ternary$libresoc.v:149884$7828
parameter \WIDTH 130
connect \A \$19
connect \B \$17
connect \S \neg_res
- connect \Y $ternary$libresoc.v:151754$7902_Y
+ connect \Y $ternary$libresoc.v:149884$7828_Y
end
- attribute \src "libresoc.v:151469.7-151469.20"
- process $proc$libresoc.v:151469$7920
+ attribute \src "libresoc.v:149599.7-149599.20"
+ process $proc$libresoc.v:149599$7846
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:151764.3-151782.6"
- process $proc$libresoc.v:151764$7913
+ attribute \src "libresoc.v:149894.3-149912.6"
+ process $proc$libresoc.v:149894$7839
assign { } { }
assign { } { }
- assign $0\o$14[63:0]$7914 $1\o$14[63:0]$7915
- attribute \src "libresoc.v:151765.5-151765.29"
+ assign $0\o$14[63:0]$7840 $1\o$14[63:0]$7841
+ attribute \src "libresoc.v:149895.5-149895.29"
switch \initial
- attribute \src "libresoc.v:151765.9-151765.17"
+ attribute \src "libresoc.v:149895.9-149895.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110100
assign { } { }
- assign $1\o$14[63:0]$7915 { \mul_o [63:32] \mul_o [63:32] }
+ assign $1\o$14[63:0]$7841 { \mul_o [63:32] \mul_o [63:32] }
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011
assign { } { }
- assign $1\o$14[63:0]$7915 \mul_o [127:64]
+ assign $1\o$14[63:0]$7841 \mul_o [127:64]
attribute \src "libresoc.v:0.0-0.0"
case 7'0110010
assign { } { }
- assign $1\o$14[63:0]$7915 \mul_o [63:0]
+ assign $1\o$14[63:0]$7841 \mul_o [63:0]
case
- assign $1\o$14[63:0]$7915 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\o$14[63:0]$7841 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \o$14 $0\o$14[63:0]$7914
+ update \o$14 $0\o$14[63:0]$7840
end
- attribute \src "libresoc.v:151783.3-151801.6"
- process $proc$libresoc.v:151783$7916
+ attribute \src "libresoc.v:149913.3-149931.6"
+ process $proc$libresoc.v:149913$7842
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
- attribute \src "libresoc.v:151784.5-151784.29"
+ attribute \src "libresoc.v:149914.5-149914.29"
switch \initial
- attribute \src "libresoc.v:151784.9-151784.17"
+ attribute \src "libresoc.v:149914.9-149914.17"
case 1'1
case
end
sync always
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:151802.3-151820.6"
- process $proc$libresoc.v:151802$7917
+ attribute \src "libresoc.v:149932.3-149950.6"
+ process $proc$libresoc.v:149932$7843
assign { } { }
assign { } { }
assign $0\mul_ov[0:0] $1\mul_ov[0:0]
- attribute \src "libresoc.v:151803.5-151803.29"
+ attribute \src "libresoc.v:149933.5-149933.29"
switch \initial
- attribute \src "libresoc.v:151803.9-151803.17"
+ attribute \src "libresoc.v:149933.9-149933.17"
case 1'1
case
end
sync always
update \mul_ov $0\mul_ov[0:0]
end
- attribute \src "libresoc.v:151821.3-151831.6"
- process $proc$libresoc.v:151821$7918
+ attribute \src "libresoc.v:149951.3-149961.6"
+ process $proc$libresoc.v:149951$7844
assign { } { }
assign { } { }
assign $0\xer_ov[1:0] $1\xer_ov[1:0]
- attribute \src "libresoc.v:151822.5-151822.29"
+ attribute \src "libresoc.v:149952.5-149952.29"
switch \initial
- attribute \src "libresoc.v:151822.9-151822.17"
+ attribute \src "libresoc.v:149952.9-149952.17"
case 1'1
case
end
sync always
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:151832.3-151842.6"
- process $proc$libresoc.v:151832$7919
+ attribute \src "libresoc.v:149962.3-149972.6"
+ process $proc$libresoc.v:149962$7845
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:151833.5-151833.29"
+ attribute \src "libresoc.v:149963.5-149963.29"
switch \initial
- attribute \src "libresoc.v:151833.9-151833.17"
+ attribute \src "libresoc.v:149963.9-149963.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$17 $neg$libresoc.v:151752$7899_Y
- connect \$19 $pos$libresoc.v:151753$7901_Y
- connect \$21 $ternary$libresoc.v:151754$7902_Y
- connect \$23 $reduce_or$libresoc.v:151755$7903_Y
- connect \$26 $reduce_and$libresoc.v:151756$7904_Y
- connect \$25 $not$libresoc.v:151757$7905_Y
- connect \$29 $and$libresoc.v:151758$7906_Y
- connect \$31 $reduce_or$libresoc.v:151759$7907_Y
- connect \$34 $reduce_and$libresoc.v:151760$7908_Y
- connect \$33 $not$libresoc.v:151761$7909_Y
- connect \$37 $and$libresoc.v:151762$7910_Y
- connect \$39 $pos$libresoc.v:151763$7912_Y
+ connect \$17 $neg$libresoc.v:149882$7825_Y
+ connect \$19 $pos$libresoc.v:149883$7827_Y
+ connect \$21 $ternary$libresoc.v:149884$7828_Y
+ connect \$23 $reduce_or$libresoc.v:149885$7829_Y
+ connect \$26 $reduce_and$libresoc.v:149886$7830_Y
+ connect \$25 $not$libresoc.v:149887$7831_Y
+ connect \$29 $and$libresoc.v:149888$7832_Y
+ connect \$31 $reduce_or$libresoc.v:149889$7833_Y
+ connect \$34 $reduce_and$libresoc.v:149890$7834_Y
+ connect \$33 $not$libresoc.v:149891$7835_Y
+ connect \$37 $and$libresoc.v:149892$7836_Y
+ connect \$39 $pos$libresoc.v:149893$7838_Y
connect \$16 \$21
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \mul_o \$21 [128:0]
connect \is_32bit \mul_op__is_32bit
end
-attribute \src "libresoc.v:151853.1-153056.10"
+attribute \src "libresoc.v:149983.1-151186.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1"
attribute \generator "nMigen"
module \mul_pipe1
- attribute \src "libresoc.v:151854.7-151854.20"
+ attribute \src "libresoc.v:149984.7-149984.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 13 $0\mul_op__fn_unit$next[12:0]$7949
- attribute \src "libresoc.v:152798.3-152799.47"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 13 $0\mul_op__fn_unit$next[12:0]$7875
+ attribute \src "libresoc.v:150928.3-150929.47"
wire width 13 $0\mul_op__fn_unit[12:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 64 $0\mul_op__imm_data__data$next[63:0]$7950
- attribute \src "libresoc.v:152800.3-152801.61"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 64 $0\mul_op__imm_data__data$next[63:0]$7876
+ attribute \src "libresoc.v:150930.3-150931.61"
wire width 64 $0\mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__imm_data__ok$next[0:0]$7951
- attribute \src "libresoc.v:152802.3-152803.57"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__imm_data__ok$next[0:0]$7877
+ attribute \src "libresoc.v:150932.3-150933.57"
wire $0\mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 32 $0\mul_op__insn$next[31:0]$7952
- attribute \src "libresoc.v:152818.3-152819.41"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 32 $0\mul_op__insn$next[31:0]$7878
+ attribute \src "libresoc.v:150948.3-150949.41"
wire width 32 $0\mul_op__insn[31:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 7 $0\mul_op__insn_type$next[6:0]$7953
- attribute \src "libresoc.v:152796.3-152797.51"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 7 $0\mul_op__insn_type$next[6:0]$7879
+ attribute \src "libresoc.v:150926.3-150927.51"
wire width 7 $0\mul_op__insn_type[6:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__is_32bit$next[0:0]$7954
- attribute \src "libresoc.v:152814.3-152815.49"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__is_32bit$next[0:0]$7880
+ attribute \src "libresoc.v:150944.3-150945.49"
wire $0\mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__is_signed$next[0:0]$7955
- attribute \src "libresoc.v:152816.3-152817.51"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__is_signed$next[0:0]$7881
+ attribute \src "libresoc.v:150946.3-150947.51"
wire $0\mul_op__is_signed[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__oe__oe$next[0:0]$7956
- attribute \src "libresoc.v:152808.3-152809.45"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__oe__oe$next[0:0]$7882
+ attribute \src "libresoc.v:150938.3-150939.45"
wire $0\mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__oe__ok$next[0:0]$7957
- attribute \src "libresoc.v:152810.3-152811.45"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__oe__ok$next[0:0]$7883
+ attribute \src "libresoc.v:150940.3-150941.45"
wire $0\mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__rc__ok$next[0:0]$7958
- attribute \src "libresoc.v:152806.3-152807.45"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__rc__ok$next[0:0]$7884
+ attribute \src "libresoc.v:150936.3-150937.45"
wire $0\mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__rc__rc$next[0:0]$7959
- attribute \src "libresoc.v:152804.3-152805.45"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__rc__rc$next[0:0]$7885
+ attribute \src "libresoc.v:150934.3-150935.45"
wire $0\mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $0\mul_op__write_cr0$next[0:0]$7960
- attribute \src "libresoc.v:152812.3-152813.51"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $0\mul_op__write_cr0$next[0:0]$7886
+ attribute \src "libresoc.v:150942.3-150943.51"
wire $0\mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:152920.3-152932.6"
- wire width 2 $0\muxid$next[1:0]$7946
- attribute \src "libresoc.v:152820.3-152821.27"
+ attribute \src "libresoc.v:151050.3-151062.6"
+ wire width 2 $0\muxid$next[1:0]$7872
+ attribute \src "libresoc.v:150950.3-150951.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:153008.3-153020.6"
- wire $0\neg_res$next[0:0]$7989
- attribute \src "libresoc.v:153021.3-153033.6"
- wire $0\neg_res32$next[0:0]$7992
- attribute \src "libresoc.v:152786.3-152787.35"
+ attribute \src "libresoc.v:151138.3-151150.6"
+ wire $0\neg_res$next[0:0]$7915
+ attribute \src "libresoc.v:151151.3-151163.6"
+ wire $0\neg_res32$next[0:0]$7918
+ attribute \src "libresoc.v:150916.3-150917.35"
wire $0\neg_res32[0:0]
- attribute \src "libresoc.v:152788.3-152789.31"
+ attribute \src "libresoc.v:150918.3-150919.31"
wire $0\neg_res[0:0]
- attribute \src "libresoc.v:152902.3-152919.6"
- wire $0\r_busy$next[0:0]$7942
- attribute \src "libresoc.v:152822.3-152823.29"
+ attribute \src "libresoc.v:151032.3-151049.6"
+ wire $0\r_busy$next[0:0]$7868
+ attribute \src "libresoc.v:150952.3-150953.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:152969.3-152981.6"
- wire width 64 $0\ra$next[63:0]$7980
- attribute \src "libresoc.v:152794.3-152795.21"
+ attribute \src "libresoc.v:151099.3-151111.6"
+ wire width 64 $0\ra$next[63:0]$7906
+ attribute \src "libresoc.v:150924.3-150925.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:152982.3-152994.6"
- wire width 64 $0\rb$next[63:0]$7983
- attribute \src "libresoc.v:152792.3-152793.21"
+ attribute \src "libresoc.v:151112.3-151124.6"
+ wire width 64 $0\rb$next[63:0]$7909
+ attribute \src "libresoc.v:150922.3-150923.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:152995.3-153007.6"
- wire $0\xer_so$next[0:0]$7986
- attribute \src "libresoc.v:152790.3-152791.29"
+ attribute \src "libresoc.v:151125.3-151137.6"
+ wire $0\xer_so$next[0:0]$7912
+ attribute \src "libresoc.v:150920.3-150921.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 13 $1\mul_op__fn_unit$next[12:0]$7961
- attribute \src "libresoc.v:152361.14-152361.40"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 13 $1\mul_op__fn_unit$next[12:0]$7887
+ attribute \src "libresoc.v:150491.14-150491.40"
wire width 13 $1\mul_op__fn_unit[12:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 64 $1\mul_op__imm_data__data$next[63:0]$7962
- attribute \src "libresoc.v:152398.14-152398.59"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 64 $1\mul_op__imm_data__data$next[63:0]$7888
+ attribute \src "libresoc.v:150528.14-150528.59"
wire width 64 $1\mul_op__imm_data__data[63:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__imm_data__ok$next[0:0]$7963
- attribute \src "libresoc.v:152407.7-152407.34"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__imm_data__ok$next[0:0]$7889
+ attribute \src "libresoc.v:150537.7-150537.34"
wire $1\mul_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 32 $1\mul_op__insn$next[31:0]$7964
- attribute \src "libresoc.v:152416.14-152416.34"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 32 $1\mul_op__insn$next[31:0]$7890
+ attribute \src "libresoc.v:150546.14-150546.34"
wire width 32 $1\mul_op__insn[31:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 7 $1\mul_op__insn_type$next[6:0]$7965
- attribute \src "libresoc.v:152499.13-152499.38"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 7 $1\mul_op__insn_type$next[6:0]$7891
+ attribute \src "libresoc.v:150629.13-150629.38"
wire width 7 $1\mul_op__insn_type[6:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__is_32bit$next[0:0]$7966
- attribute \src "libresoc.v:152656.7-152656.30"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__is_32bit$next[0:0]$7892
+ attribute \src "libresoc.v:150786.7-150786.30"
wire $1\mul_op__is_32bit[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__is_signed$next[0:0]$7967
- attribute \src "libresoc.v:152665.7-152665.31"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__is_signed$next[0:0]$7893
+ attribute \src "libresoc.v:150795.7-150795.31"
wire $1\mul_op__is_signed[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__oe__oe$next[0:0]$7968
- attribute \src "libresoc.v:152674.7-152674.28"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__oe__oe$next[0:0]$7894
+ attribute \src "libresoc.v:150804.7-150804.28"
wire $1\mul_op__oe__oe[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__oe__ok$next[0:0]$7969
- attribute \src "libresoc.v:152683.7-152683.28"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__oe__ok$next[0:0]$7895
+ attribute \src "libresoc.v:150813.7-150813.28"
wire $1\mul_op__oe__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__rc__ok$next[0:0]$7970
- attribute \src "libresoc.v:152692.7-152692.28"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__rc__ok$next[0:0]$7896
+ attribute \src "libresoc.v:150822.7-150822.28"
wire $1\mul_op__rc__ok[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__rc__rc$next[0:0]$7971
- attribute \src "libresoc.v:152701.7-152701.28"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__rc__rc$next[0:0]$7897
+ attribute \src "libresoc.v:150831.7-150831.28"
wire $1\mul_op__rc__rc[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $1\mul_op__write_cr0$next[0:0]$7972
- attribute \src "libresoc.v:152710.7-152710.31"
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $1\mul_op__write_cr0$next[0:0]$7898
+ attribute \src "libresoc.v:150840.7-150840.31"
wire $1\mul_op__write_cr0[0:0]
- attribute \src "libresoc.v:152920.3-152932.6"
- wire width 2 $1\muxid$next[1:0]$7947
- attribute \src "libresoc.v:152719.13-152719.25"
+ attribute \src "libresoc.v:151050.3-151062.6"
+ wire width 2 $1\muxid$next[1:0]$7873
+ attribute \src "libresoc.v:150849.13-150849.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:153008.3-153020.6"
- wire $1\neg_res$next[0:0]$7990
- attribute \src "libresoc.v:153021.3-153033.6"
- wire $1\neg_res32$next[0:0]$7993
- attribute \src "libresoc.v:152741.7-152741.23"
+ attribute \src "libresoc.v:151138.3-151150.6"
+ wire $1\neg_res$next[0:0]$7916
+ attribute \src "libresoc.v:151151.3-151163.6"
+ wire $1\neg_res32$next[0:0]$7919
+ attribute \src "libresoc.v:150871.7-150871.23"
wire $1\neg_res32[0:0]
- attribute \src "libresoc.v:152734.7-152734.21"
+ attribute \src "libresoc.v:150864.7-150864.21"
wire $1\neg_res[0:0]
- attribute \src "libresoc.v:152902.3-152919.6"
- wire $1\r_busy$next[0:0]$7943
- attribute \src "libresoc.v:152755.7-152755.20"
+ attribute \src "libresoc.v:151032.3-151049.6"
+ wire $1\r_busy$next[0:0]$7869
+ attribute \src "libresoc.v:150885.7-150885.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:152969.3-152981.6"
- wire width 64 $1\ra$next[63:0]$7981
- attribute \src "libresoc.v:152760.14-152760.39"
+ attribute \src "libresoc.v:151099.3-151111.6"
+ wire width 64 $1\ra$next[63:0]$7907
+ attribute \src "libresoc.v:150890.14-150890.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:152982.3-152994.6"
- wire width 64 $1\rb$next[63:0]$7984
- attribute \src "libresoc.v:152769.14-152769.39"
+ attribute \src "libresoc.v:151112.3-151124.6"
+ wire width 64 $1\rb$next[63:0]$7910
+ attribute \src "libresoc.v:150899.14-150899.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:152995.3-153007.6"
- wire $1\xer_so$next[0:0]$7987
- attribute \src "libresoc.v:152778.7-152778.20"
+ attribute \src "libresoc.v:151125.3-151137.6"
+ wire $1\xer_so$next[0:0]$7913
+ attribute \src "libresoc.v:150908.7-150908.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:152933.3-152968.6"
- wire width 64 $2\mul_op__imm_data__data$next[63:0]$7973
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $2\mul_op__imm_data__ok$next[0:0]$7974
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $2\mul_op__oe__oe$next[0:0]$7975
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $2\mul_op__oe__ok$next[0:0]$7976
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $2\mul_op__rc__ok$next[0:0]$7977
- attribute \src "libresoc.v:152933.3-152968.6"
- wire $2\mul_op__rc__rc$next[0:0]$7978
- attribute \src "libresoc.v:152902.3-152919.6"
- wire $2\r_busy$next[0:0]$7944
- attribute \src "libresoc.v:152785.18-152785.118"
- wire $and$libresoc.v:152785$7921_Y
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire width 64 $2\mul_op__imm_data__data$next[63:0]$7899
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $2\mul_op__imm_data__ok$next[0:0]$7900
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $2\mul_op__oe__oe$next[0:0]$7901
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $2\mul_op__oe__ok$next[0:0]$7902
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $2\mul_op__rc__ok$next[0:0]$7903
+ attribute \src "libresoc.v:151063.3-151098.6"
+ wire $2\mul_op__rc__rc$next[0:0]$7904
+ attribute \src "libresoc.v:151032.3-151049.6"
+ wire $2\r_busy$next[0:0]$7870
+ attribute \src "libresoc.v:150915.18-150915.118"
+ wire $and$libresoc.v:150915$7847_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:151854.7-151854.15"
+ attribute \src "libresoc.v:149984.7-149984.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:152785$7921
+ cell $and $and$libresoc.v:150915$7847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$49
connect \B \p_ready_o
- connect \Y $and$libresoc.v:152785$7921_Y
+ connect \Y $and$libresoc.v:150915$7847_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:152824.14-152857.4"
+ attribute \src "libresoc.v:150954.14-150987.4"
cell \input$95 \input
connect \mul_op__fn_unit \input_mul_op__fn_unit
connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19
connect \xer_so$16 \input_xer_so$32
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:152858.8-152893.4"
+ attribute \src "libresoc.v:150988.8-151023.4"
cell \mul1 \mul1
connect \mul_op__fn_unit \mul1_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35
connect \xer_so$16 \mul1_xer_so$48
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:152894.10-152897.4"
+ attribute \src "libresoc.v:151024.10-151027.4"
cell \n$94 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:152898.10-152901.4"
+ attribute \src "libresoc.v:151028.10-151031.4"
cell \p$93 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:151854.7-151854.20"
- process $proc$libresoc.v:151854$7994
+ attribute \src "libresoc.v:149984.7-149984.20"
+ process $proc$libresoc.v:149984$7920
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:152361.14-152361.40"
- process $proc$libresoc.v:152361$7995
+ attribute \src "libresoc.v:150491.14-150491.40"
+ process $proc$libresoc.v:150491$7921
assign { } { }
assign $1\mul_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \mul_op__fn_unit $1\mul_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:152398.14-152398.59"
- process $proc$libresoc.v:152398$7996
+ attribute \src "libresoc.v:150528.14-150528.59"
+ process $proc$libresoc.v:150528$7922
assign { } { }
assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:152407.7-152407.34"
- process $proc$libresoc.v:152407$7997
+ attribute \src "libresoc.v:150537.7-150537.34"
+ process $proc$libresoc.v:150537$7923
assign { } { }
assign $1\mul_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:152416.14-152416.34"
- process $proc$libresoc.v:152416$7998
+ attribute \src "libresoc.v:150546.14-150546.34"
+ process $proc$libresoc.v:150546$7924
assign { } { }
assign $1\mul_op__insn[31:0] 0
sync always
sync init
update \mul_op__insn $1\mul_op__insn[31:0]
end
- attribute \src "libresoc.v:152499.13-152499.38"
- process $proc$libresoc.v:152499$7999
+ attribute \src "libresoc.v:150629.13-150629.38"
+ process $proc$libresoc.v:150629$7925
assign { } { }
assign $1\mul_op__insn_type[6:0] 7'0000000
sync always
sync init
update \mul_op__insn_type $1\mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:152656.7-152656.30"
- process $proc$libresoc.v:152656$8000
+ attribute \src "libresoc.v:150786.7-150786.30"
+ process $proc$libresoc.v:150786$7926
assign { } { }
assign $1\mul_op__is_32bit[0:0] 1'0
sync always
sync init
update \mul_op__is_32bit $1\mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:152665.7-152665.31"
- process $proc$libresoc.v:152665$8001
+ attribute \src "libresoc.v:150795.7-150795.31"
+ process $proc$libresoc.v:150795$7927
assign { } { }
assign $1\mul_op__is_signed[0:0] 1'0
sync always
sync init
update \mul_op__is_signed $1\mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:152674.7-152674.28"
- process $proc$libresoc.v:152674$8002
+ attribute \src "libresoc.v:150804.7-150804.28"
+ process $proc$libresoc.v:150804$7928
assign { } { }
assign $1\mul_op__oe__oe[0:0] 1'0
sync always
sync init
update \mul_op__oe__oe $1\mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:152683.7-152683.28"
- process $proc$libresoc.v:152683$8003
+ attribute \src "libresoc.v:150813.7-150813.28"
+ process $proc$libresoc.v:150813$7929
assign { } { }
assign $1\mul_op__oe__ok[0:0] 1'0
sync always
sync init
update \mul_op__oe__ok $1\mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:152692.7-152692.28"
- process $proc$libresoc.v:152692$8004
+ attribute \src "libresoc.v:150822.7-150822.28"
+ process $proc$libresoc.v:150822$7930
assign { } { }
assign $1\mul_op__rc__ok[0:0] 1'0
sync always
sync init
update \mul_op__rc__ok $1\mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:152701.7-152701.28"
- process $proc$libresoc.v:152701$8005
+ attribute \src "libresoc.v:150831.7-150831.28"
+ process $proc$libresoc.v:150831$7931
assign { } { }
assign $1\mul_op__rc__rc[0:0] 1'0
sync always
sync init
update \mul_op__rc__rc $1\mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:152710.7-152710.31"
- process $proc$libresoc.v:152710$8006
+ attribute \src "libresoc.v:150840.7-150840.31"
+ process $proc$libresoc.v:150840$7932
assign { } { }
assign $1\mul_op__write_cr0[0:0] 1'0
sync always
sync init
update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:152719.13-152719.25"
- process $proc$libresoc.v:152719$8007
+ attribute \src "libresoc.v:150849.13-150849.25"
+ process $proc$libresoc.v:150849$7933
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:152734.7-152734.21"
- process $proc$libresoc.v:152734$8008
+ attribute \src "libresoc.v:150864.7-150864.21"
+ process $proc$libresoc.v:150864$7934
assign { } { }
assign $1\neg_res[0:0] 1'0
sync always
sync init
update \neg_res $1\neg_res[0:0]
end
- attribute \src "libresoc.v:152741.7-152741.23"
- process $proc$libresoc.v:152741$8009
+ attribute \src "libresoc.v:150871.7-150871.23"
+ process $proc$libresoc.v:150871$7935
assign { } { }
assign $1\neg_res32[0:0] 1'0
sync always
sync init
update \neg_res32 $1\neg_res32[0:0]
end
- attribute \src "libresoc.v:152755.7-152755.20"
- process $proc$libresoc.v:152755$8010
+ attribute \src "libresoc.v:150885.7-150885.20"
+ process $proc$libresoc.v:150885$7936
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:152760.14-152760.39"
- process $proc$libresoc.v:152760$8011
+ attribute \src "libresoc.v:150890.14-150890.39"
+ process $proc$libresoc.v:150890$7937
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:152769.14-152769.39"
- process $proc$libresoc.v:152769$8012
+ attribute \src "libresoc.v:150899.14-150899.39"
+ process $proc$libresoc.v:150899$7938
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:152778.7-152778.20"
- process $proc$libresoc.v:152778$8013
+ attribute \src "libresoc.v:150908.7-150908.20"
+ process $proc$libresoc.v:150908$7939
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:152786.3-152787.35"
- process $proc$libresoc.v:152786$7922
+ attribute \src "libresoc.v:150916.3-150917.35"
+ process $proc$libresoc.v:150916$7848
assign { } { }
assign $0\neg_res32[0:0] \neg_res32$next
sync posedge \coresync_clk
update \neg_res32 $0\neg_res32[0:0]
end
- attribute \src "libresoc.v:152788.3-152789.31"
- process $proc$libresoc.v:152788$7923
+ attribute \src "libresoc.v:150918.3-150919.31"
+ process $proc$libresoc.v:150918$7849
assign { } { }
assign $0\neg_res[0:0] \neg_res$next
sync posedge \coresync_clk
update \neg_res $0\neg_res[0:0]
end
- attribute \src "libresoc.v:152790.3-152791.29"
- process $proc$libresoc.v:152790$7924
+ attribute \src "libresoc.v:150920.3-150921.29"
+ process $proc$libresoc.v:150920$7850
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:152792.3-152793.21"
- process $proc$libresoc.v:152792$7925
+ attribute \src "libresoc.v:150922.3-150923.21"
+ process $proc$libresoc.v:150922$7851
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:152794.3-152795.21"
- process $proc$libresoc.v:152794$7926
+ attribute \src "libresoc.v:150924.3-150925.21"
+ process $proc$libresoc.v:150924$7852
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:152796.3-152797.51"
- process $proc$libresoc.v:152796$7927
+ attribute \src "libresoc.v:150926.3-150927.51"
+ process $proc$libresoc.v:150926$7853
assign { } { }
assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next
sync posedge \coresync_clk
update \mul_op__insn_type $0\mul_op__insn_type[6:0]
end
- attribute \src "libresoc.v:152798.3-152799.47"
- process $proc$libresoc.v:152798$7928
+ attribute \src "libresoc.v:150928.3-150929.47"
+ process $proc$libresoc.v:150928$7854
assign { } { }
assign $0\mul_op__fn_unit[12:0] \mul_op__fn_unit$next
sync posedge \coresync_clk
update \mul_op__fn_unit $0\mul_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:152800.3-152801.61"
- process $proc$libresoc.v:152800$7929
+ attribute \src "libresoc.v:150930.3-150931.61"
+ process $proc$libresoc.v:150930$7855
assign { } { }
assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next
sync posedge \coresync_clk
update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:152802.3-152803.57"
- process $proc$libresoc.v:152802$7930
+ attribute \src "libresoc.v:150932.3-150933.57"
+ process $proc$libresoc.v:150932$7856
assign { } { }
assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next
sync posedge \coresync_clk
update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:152804.3-152805.45"
- process $proc$libresoc.v:152804$7931
+ attribute \src "libresoc.v:150934.3-150935.45"
+ process $proc$libresoc.v:150934$7857
assign { } { }
assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next
sync posedge \coresync_clk
update \mul_op__rc__rc $0\mul_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:152806.3-152807.45"
- process $proc$libresoc.v:152806$7932
+ attribute \src "libresoc.v:150936.3-150937.45"
+ process $proc$libresoc.v:150936$7858
assign { } { }
assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next
sync posedge \coresync_clk
update \mul_op__rc__ok $0\mul_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:152808.3-152809.45"
- process $proc$libresoc.v:152808$7933
+ attribute \src "libresoc.v:150938.3-150939.45"
+ process $proc$libresoc.v:150938$7859
assign { } { }
assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next
sync posedge \coresync_clk
update \mul_op__oe__oe $0\mul_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:152810.3-152811.45"
- process $proc$libresoc.v:152810$7934
+ attribute \src "libresoc.v:150940.3-150941.45"
+ process $proc$libresoc.v:150940$7860
assign { } { }
assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next
sync posedge \coresync_clk
update \mul_op__oe__ok $0\mul_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:152812.3-152813.51"
- process $proc$libresoc.v:152812$7935
+ attribute \src "libresoc.v:150942.3-150943.51"
+ process $proc$libresoc.v:150942$7861
assign { } { }
assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next
sync posedge \coresync_clk
update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:152814.3-152815.49"
- process $proc$libresoc.v:152814$7936
+ attribute \src "libresoc.v:150944.3-150945.49"
+ process $proc$libresoc.v:150944$7862
assign { } { }
assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next
sync posedge \coresync_clk
update \mul_op__is_32bit $0\mul_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:152816.3-152817.51"
- process $proc$libresoc.v:152816$7937
+ attribute \src "libresoc.v:150946.3-150947.51"
+ process $proc$libresoc.v:150946$7863
assign { } { }
assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next
sync posedge \coresync_clk
update \mul_op__is_signed $0\mul_op__is_signed[0:0]
end
- attribute \src "libresoc.v:152818.3-152819.41"
- process $proc$libresoc.v:152818$7938
+ attribute \src "libresoc.v:150948.3-150949.41"
+ process $proc$libresoc.v:150948$7864
assign { } { }
assign $0\mul_op__insn[31:0] \mul_op__insn$next
sync posedge \coresync_clk
update \mul_op__insn $0\mul_op__insn[31:0]
end
- attribute \src "libresoc.v:152820.3-152821.27"
- process $proc$libresoc.v:152820$7939
+ attribute \src "libresoc.v:150950.3-150951.27"
+ process $proc$libresoc.v:150950$7865
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:152822.3-152823.29"
- process $proc$libresoc.v:152822$7940
+ attribute \src "libresoc.v:150952.3-150953.29"
+ process $proc$libresoc.v:150952$7866
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:152902.3-152919.6"
- process $proc$libresoc.v:152902$7941
+ attribute \src "libresoc.v:151032.3-151049.6"
+ process $proc$libresoc.v:151032$7867
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$7942 $2\r_busy$next[0:0]$7944
- attribute \src "libresoc.v:152903.5-152903.29"
+ assign $0\r_busy$next[0:0]$7868 $2\r_busy$next[0:0]$7870
+ attribute \src "libresoc.v:151033.5-151033.29"
switch \initial
- attribute \src "libresoc.v:152903.9-152903.17"
+ attribute \src "libresoc.v:151033.9-151033.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$7943 1'1
+ assign $1\r_busy$next[0:0]$7869 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$7943 1'0
+ assign $1\r_busy$next[0:0]$7869 1'0
case
- assign $1\r_busy$next[0:0]$7943 \r_busy
+ assign $1\r_busy$next[0:0]$7869 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$7944 1'0
+ assign $2\r_busy$next[0:0]$7870 1'0
case
- assign $2\r_busy$next[0:0]$7944 $1\r_busy$next[0:0]$7943
+ assign $2\r_busy$next[0:0]$7870 $1\r_busy$next[0:0]$7869
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$7942
+ update \r_busy$next $0\r_busy$next[0:0]$7868
end
- attribute \src "libresoc.v:152920.3-152932.6"
- process $proc$libresoc.v:152920$7945
+ attribute \src "libresoc.v:151050.3-151062.6"
+ process $proc$libresoc.v:151050$7871
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$7946 $1\muxid$next[1:0]$7947
- attribute \src "libresoc.v:152921.5-152921.29"
+ assign $0\muxid$next[1:0]$7872 $1\muxid$next[1:0]$7873
+ attribute \src "libresoc.v:151051.5-151051.29"
switch \initial
- attribute \src "libresoc.v:152921.9-152921.17"
+ attribute \src "libresoc.v:151051.9-151051.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$7947 \muxid$52
+ assign $1\muxid$next[1:0]$7873 \muxid$52
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$7947 \muxid$52
+ assign $1\muxid$next[1:0]$7873 \muxid$52
case
- assign $1\muxid$next[1:0]$7947 \muxid
+ assign $1\muxid$next[1:0]$7873 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$7946
+ update \muxid$next $0\muxid$next[1:0]$7872
end
- attribute \src "libresoc.v:152933.3-152968.6"
- process $proc$libresoc.v:152933$7948
+ attribute \src "libresoc.v:151063.3-151098.6"
+ process $proc$libresoc.v:151063$7874
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$next[12:0]$7949 $1\mul_op__fn_unit$next[12:0]$7961
+ assign $0\mul_op__fn_unit$next[12:0]$7875 $1\mul_op__fn_unit$next[12:0]$7887
assign { } { }
assign { } { }
- assign $0\mul_op__insn$next[31:0]$7952 $1\mul_op__insn$next[31:0]$7964
- assign $0\mul_op__insn_type$next[6:0]$7953 $1\mul_op__insn_type$next[6:0]$7965
- assign $0\mul_op__is_32bit$next[0:0]$7954 $1\mul_op__is_32bit$next[0:0]$7966
- assign $0\mul_op__is_signed$next[0:0]$7955 $1\mul_op__is_signed$next[0:0]$7967
+ assign $0\mul_op__insn$next[31:0]$7878 $1\mul_op__insn$next[31:0]$7890
+ assign $0\mul_op__insn_type$next[6:0]$7879 $1\mul_op__insn_type$next[6:0]$7891
+ assign $0\mul_op__is_32bit$next[0:0]$7880 $1\mul_op__is_32bit$next[0:0]$7892
+ assign $0\mul_op__is_signed$next[0:0]$7881 $1\mul_op__is_signed$next[0:0]$7893
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$next[0:0]$7960 $1\mul_op__write_cr0$next[0:0]$7972
- assign $0\mul_op__imm_data__data$next[63:0]$7950 $2\mul_op__imm_data__data$next[63:0]$7973
- assign $0\mul_op__imm_data__ok$next[0:0]$7951 $2\mul_op__imm_data__ok$next[0:0]$7974
- assign $0\mul_op__oe__oe$next[0:0]$7956 $2\mul_op__oe__oe$next[0:0]$7975
- assign $0\mul_op__oe__ok$next[0:0]$7957 $2\mul_op__oe__ok$next[0:0]$7976
- assign $0\mul_op__rc__ok$next[0:0]$7958 $2\mul_op__rc__ok$next[0:0]$7977
- assign $0\mul_op__rc__rc$next[0:0]$7959 $2\mul_op__rc__rc$next[0:0]$7978
- attribute \src "libresoc.v:152934.5-152934.29"
+ assign $0\mul_op__write_cr0$next[0:0]$7886 $1\mul_op__write_cr0$next[0:0]$7898
+ assign $0\mul_op__imm_data__data$next[63:0]$7876 $2\mul_op__imm_data__data$next[63:0]$7899
+ assign $0\mul_op__imm_data__ok$next[0:0]$7877 $2\mul_op__imm_data__ok$next[0:0]$7900
+ assign $0\mul_op__oe__oe$next[0:0]$7882 $2\mul_op__oe__oe$next[0:0]$7901
+ assign $0\mul_op__oe__ok$next[0:0]$7883 $2\mul_op__oe__ok$next[0:0]$7902
+ assign $0\mul_op__rc__ok$next[0:0]$7884 $2\mul_op__rc__ok$next[0:0]$7903
+ assign $0\mul_op__rc__rc$next[0:0]$7885 $2\mul_op__rc__rc$next[0:0]$7904
+ attribute \src "libresoc.v:151064.5-151064.29"
switch \initial
- attribute \src "libresoc.v:152934.9-152934.17"
+ attribute \src "libresoc.v:151064.9-151064.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$next[31:0]$7964 $1\mul_op__is_signed$next[0:0]$7967 $1\mul_op__is_32bit$next[0:0]$7966 $1\mul_op__write_cr0$next[0:0]$7972 $1\mul_op__oe__ok$next[0:0]$7969 $1\mul_op__oe__oe$next[0:0]$7968 $1\mul_op__rc__ok$next[0:0]$7970 $1\mul_op__rc__rc$next[0:0]$7971 $1\mul_op__imm_data__ok$next[0:0]$7963 $1\mul_op__imm_data__data$next[63:0]$7962 $1\mul_op__fn_unit$next[12:0]$7961 $1\mul_op__insn_type$next[6:0]$7965 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
+ assign { $1\mul_op__insn$next[31:0]$7890 $1\mul_op__is_signed$next[0:0]$7893 $1\mul_op__is_32bit$next[0:0]$7892 $1\mul_op__write_cr0$next[0:0]$7898 $1\mul_op__oe__ok$next[0:0]$7895 $1\mul_op__oe__oe$next[0:0]$7894 $1\mul_op__rc__ok$next[0:0]$7896 $1\mul_op__rc__rc$next[0:0]$7897 $1\mul_op__imm_data__ok$next[0:0]$7889 $1\mul_op__imm_data__data$next[63:0]$7888 $1\mul_op__fn_unit$next[12:0]$7887 $1\mul_op__insn_type$next[6:0]$7891 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$next[31:0]$7964 $1\mul_op__is_signed$next[0:0]$7967 $1\mul_op__is_32bit$next[0:0]$7966 $1\mul_op__write_cr0$next[0:0]$7972 $1\mul_op__oe__ok$next[0:0]$7969 $1\mul_op__oe__oe$next[0:0]$7968 $1\mul_op__rc__ok$next[0:0]$7970 $1\mul_op__rc__rc$next[0:0]$7971 $1\mul_op__imm_data__ok$next[0:0]$7963 $1\mul_op__imm_data__data$next[63:0]$7962 $1\mul_op__fn_unit$next[12:0]$7961 $1\mul_op__insn_type$next[6:0]$7965 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
+ assign { $1\mul_op__insn$next[31:0]$7890 $1\mul_op__is_signed$next[0:0]$7893 $1\mul_op__is_32bit$next[0:0]$7892 $1\mul_op__write_cr0$next[0:0]$7898 $1\mul_op__oe__ok$next[0:0]$7895 $1\mul_op__oe__oe$next[0:0]$7894 $1\mul_op__rc__ok$next[0:0]$7896 $1\mul_op__rc__rc$next[0:0]$7897 $1\mul_op__imm_data__ok$next[0:0]$7889 $1\mul_op__imm_data__data$next[63:0]$7888 $1\mul_op__fn_unit$next[12:0]$7887 $1\mul_op__insn_type$next[6:0]$7891 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 }
case
- assign $1\mul_op__fn_unit$next[12:0]$7961 \mul_op__fn_unit
- assign $1\mul_op__imm_data__data$next[63:0]$7962 \mul_op__imm_data__data
- assign $1\mul_op__imm_data__ok$next[0:0]$7963 \mul_op__imm_data__ok
- assign $1\mul_op__insn$next[31:0]$7964 \mul_op__insn
- assign $1\mul_op__insn_type$next[6:0]$7965 \mul_op__insn_type
- assign $1\mul_op__is_32bit$next[0:0]$7966 \mul_op__is_32bit
- assign $1\mul_op__is_signed$next[0:0]$7967 \mul_op__is_signed
- assign $1\mul_op__oe__oe$next[0:0]$7968 \mul_op__oe__oe
- assign $1\mul_op__oe__ok$next[0:0]$7969 \mul_op__oe__ok
- assign $1\mul_op__rc__ok$next[0:0]$7970 \mul_op__rc__ok
- assign $1\mul_op__rc__rc$next[0:0]$7971 \mul_op__rc__rc
- assign $1\mul_op__write_cr0$next[0:0]$7972 \mul_op__write_cr0
+ assign $1\mul_op__fn_unit$next[12:0]$7887 \mul_op__fn_unit
+ assign $1\mul_op__imm_data__data$next[63:0]$7888 \mul_op__imm_data__data
+ assign $1\mul_op__imm_data__ok$next[0:0]$7889 \mul_op__imm_data__ok
+ assign $1\mul_op__insn$next[31:0]$7890 \mul_op__insn
+ assign $1\mul_op__insn_type$next[6:0]$7891 \mul_op__insn_type
+ assign $1\mul_op__is_32bit$next[0:0]$7892 \mul_op__is_32bit
+ assign $1\mul_op__is_signed$next[0:0]$7893 \mul_op__is_signed
+ assign $1\mul_op__oe__oe$next[0:0]$7894 \mul_op__oe__oe
+ assign $1\mul_op__oe__ok$next[0:0]$7895 \mul_op__oe__ok
+ assign $1\mul_op__rc__ok$next[0:0]$7896 \mul_op__rc__ok
+ assign $1\mul_op__rc__rc$next[0:0]$7897 \mul_op__rc__rc
+ assign $1\mul_op__write_cr0$next[0:0]$7898 \mul_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$next[63:0]$7973 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$next[0:0]$7974 1'0
- assign $2\mul_op__rc__rc$next[0:0]$7978 1'0
- assign $2\mul_op__rc__ok$next[0:0]$7977 1'0
- assign $2\mul_op__oe__oe$next[0:0]$7975 1'0
- assign $2\mul_op__oe__ok$next[0:0]$7976 1'0
+ assign $2\mul_op__imm_data__data$next[63:0]$7899 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$next[0:0]$7900 1'0
+ assign $2\mul_op__rc__rc$next[0:0]$7904 1'0
+ assign $2\mul_op__rc__ok$next[0:0]$7903 1'0
+ assign $2\mul_op__oe__oe$next[0:0]$7901 1'0
+ assign $2\mul_op__oe__ok$next[0:0]$7902 1'0
case
- assign $2\mul_op__imm_data__data$next[63:0]$7973 $1\mul_op__imm_data__data$next[63:0]$7962
- assign $2\mul_op__imm_data__ok$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7963
- assign $2\mul_op__oe__oe$next[0:0]$7975 $1\mul_op__oe__oe$next[0:0]$7968
- assign $2\mul_op__oe__ok$next[0:0]$7976 $1\mul_op__oe__ok$next[0:0]$7969
- assign $2\mul_op__rc__ok$next[0:0]$7977 $1\mul_op__rc__ok$next[0:0]$7970
- assign $2\mul_op__rc__rc$next[0:0]$7978 $1\mul_op__rc__rc$next[0:0]$7971
+ assign $2\mul_op__imm_data__data$next[63:0]$7899 $1\mul_op__imm_data__data$next[63:0]$7888
+ assign $2\mul_op__imm_data__ok$next[0:0]$7900 $1\mul_op__imm_data__ok$next[0:0]$7889
+ assign $2\mul_op__oe__oe$next[0:0]$7901 $1\mul_op__oe__oe$next[0:0]$7894
+ assign $2\mul_op__oe__ok$next[0:0]$7902 $1\mul_op__oe__ok$next[0:0]$7895
+ assign $2\mul_op__rc__ok$next[0:0]$7903 $1\mul_op__rc__ok$next[0:0]$7896
+ assign $2\mul_op__rc__rc$next[0:0]$7904 $1\mul_op__rc__rc$next[0:0]$7897
end
sync always
- update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7949
- update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7950
- update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7951
- update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7952
- update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7953
- update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7954
- update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7955
- update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7956
- update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7957
- update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7958
- update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7959
- update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7960
+ update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7875
+ update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7876
+ update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7877
+ update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7878
+ update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7879
+ update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7880
+ update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7881
+ update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7882
+ update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7883
+ update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7884
+ update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7885
+ update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7886
end
- attribute \src "libresoc.v:152969.3-152981.6"
- process $proc$libresoc.v:152969$7979
+ attribute \src "libresoc.v:151099.3-151111.6"
+ process $proc$libresoc.v:151099$7905
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$7980 $1\ra$next[63:0]$7981
- attribute \src "libresoc.v:152970.5-152970.29"
+ assign $0\ra$next[63:0]$7906 $1\ra$next[63:0]$7907
+ attribute \src "libresoc.v:151100.5-151100.29"
switch \initial
- attribute \src "libresoc.v:152970.9-152970.17"
+ attribute \src "libresoc.v:151100.9-151100.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$7981 \ra$65
+ assign $1\ra$next[63:0]$7907 \ra$65
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$7981 \ra$65
+ assign $1\ra$next[63:0]$7907 \ra$65
case
- assign $1\ra$next[63:0]$7981 \ra
+ assign $1\ra$next[63:0]$7907 \ra
end
sync always
- update \ra$next $0\ra$next[63:0]$7980
+ update \ra$next $0\ra$next[63:0]$7906
end
- attribute \src "libresoc.v:152982.3-152994.6"
- process $proc$libresoc.v:152982$7982
+ attribute \src "libresoc.v:151112.3-151124.6"
+ process $proc$libresoc.v:151112$7908
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$7983 $1\rb$next[63:0]$7984
- attribute \src "libresoc.v:152983.5-152983.29"
+ assign $0\rb$next[63:0]$7909 $1\rb$next[63:0]$7910
+ attribute \src "libresoc.v:151113.5-151113.29"
switch \initial
- attribute \src "libresoc.v:152983.9-152983.17"
+ attribute \src "libresoc.v:151113.9-151113.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$7984 \rb$66
+ assign $1\rb$next[63:0]$7910 \rb$66
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$7984 \rb$66
+ assign $1\rb$next[63:0]$7910 \rb$66
case
- assign $1\rb$next[63:0]$7984 \rb
+ assign $1\rb$next[63:0]$7910 \rb
end
sync always
- update \rb$next $0\rb$next[63:0]$7983
+ update \rb$next $0\rb$next[63:0]$7909
end
- attribute \src "libresoc.v:152995.3-153007.6"
- process $proc$libresoc.v:152995$7985
+ attribute \src "libresoc.v:151125.3-151137.6"
+ process $proc$libresoc.v:151125$7911
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$7986 $1\xer_so$next[0:0]$7987
- attribute \src "libresoc.v:152996.5-152996.29"
+ assign $0\xer_so$next[0:0]$7912 $1\xer_so$next[0:0]$7913
+ attribute \src "libresoc.v:151126.5-151126.29"
switch \initial
- attribute \src "libresoc.v:152996.9-152996.17"
+ attribute \src "libresoc.v:151126.9-151126.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$next[0:0]$7987 \xer_so$67
+ assign $1\xer_so$next[0:0]$7913 \xer_so$67
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$next[0:0]$7987 \xer_so$67
+ assign $1\xer_so$next[0:0]$7913 \xer_so$67
case
- assign $1\xer_so$next[0:0]$7987 \xer_so
+ assign $1\xer_so$next[0:0]$7913 \xer_so
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$7986
+ update \xer_so$next $0\xer_so$next[0:0]$7912
end
- attribute \src "libresoc.v:153008.3-153020.6"
- process $proc$libresoc.v:153008$7988
+ attribute \src "libresoc.v:151138.3-151150.6"
+ process $proc$libresoc.v:151138$7914
assign { } { }
assign { } { }
- assign $0\neg_res$next[0:0]$7989 $1\neg_res$next[0:0]$7990
- attribute \src "libresoc.v:153009.5-153009.29"
+ assign $0\neg_res$next[0:0]$7915 $1\neg_res$next[0:0]$7916
+ attribute \src "libresoc.v:151139.5-151139.29"
switch \initial
- attribute \src "libresoc.v:153009.9-153009.17"
+ attribute \src "libresoc.v:151139.9-151139.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res$next[0:0]$7990 \neg_res$68
+ assign $1\neg_res$next[0:0]$7916 \neg_res$68
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res$next[0:0]$7990 \neg_res$68
+ assign $1\neg_res$next[0:0]$7916 \neg_res$68
case
- assign $1\neg_res$next[0:0]$7990 \neg_res
+ assign $1\neg_res$next[0:0]$7916 \neg_res
end
sync always
- update \neg_res$next $0\neg_res$next[0:0]$7989
+ update \neg_res$next $0\neg_res$next[0:0]$7915
end
- attribute \src "libresoc.v:153021.3-153033.6"
- process $proc$libresoc.v:153021$7991
+ attribute \src "libresoc.v:151151.3-151163.6"
+ process $proc$libresoc.v:151151$7917
assign { } { }
assign { } { }
- assign $0\neg_res32$next[0:0]$7992 $1\neg_res32$next[0:0]$7993
- attribute \src "libresoc.v:153022.5-153022.29"
+ assign $0\neg_res32$next[0:0]$7918 $1\neg_res32$next[0:0]$7919
+ attribute \src "libresoc.v:151152.5-151152.29"
switch \initial
- attribute \src "libresoc.v:153022.9-153022.17"
+ attribute \src "libresoc.v:151152.9-151152.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res32$next[0:0]$7993 \neg_res32$69
+ assign $1\neg_res32$next[0:0]$7919 \neg_res32$69
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res32$next[0:0]$7993 \neg_res32$69
+ assign $1\neg_res32$next[0:0]$7919 \neg_res32$69
case
- assign $1\neg_res32$next[0:0]$7993 \neg_res32
+ assign $1\neg_res32$next[0:0]$7919 \neg_res32
end
sync always
- update \neg_res32$next $0\neg_res32$next[0:0]$7992
+ update \neg_res32$next $0\neg_res32$next[0:0]$7918
end
- connect \$50 $and$libresoc.v:152785$7921_Y
+ connect \$50 $and$libresoc.v:150915$7847_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \neg_res32$69 \mul1_neg_res32
connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:153060.1-153970.10"
+attribute \src "libresoc.v:151190.1-152100.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2"
attribute \generator "nMigen"
module \mul_pipe2
- attribute \src "libresoc.v:153061.7-153061.20"
+ attribute \src "libresoc.v:151191.7-151191.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8057
- attribute \src "libresoc.v:153762.3-153763.53"
- wire width 13 $0\mul_op__fn_unit$3[12:0]$8025
- attribute \src "libresoc.v:153346.14-153346.44"
- wire width 13 $0\mul_op__fn_unit$3[12:0]$8101
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8058
- attribute \src "libresoc.v:153764.3-153765.67"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8027
- attribute \src "libresoc.v:153371.14-153371.63"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8103
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__imm_data__ok$5$next[0:0]$8059
- attribute \src "libresoc.v:153766.3-153767.63"
- wire $0\mul_op__imm_data__ok$5[0:0]$8029
- attribute \src "libresoc.v:153380.7-153380.38"
- wire $0\mul_op__imm_data__ok$5[0:0]$8105
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 32 $0\mul_op__insn$13$next[31:0]$8060
- attribute \src "libresoc.v:153782.3-153783.49"
- wire width 32 $0\mul_op__insn$13[31:0]$8045
- attribute \src "libresoc.v:153387.14-153387.39"
- wire width 32 $0\mul_op__insn$13[31:0]$8107
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 7 $0\mul_op__insn_type$2$next[6:0]$8061
- attribute \src "libresoc.v:153760.3-153761.57"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8023
- attribute \src "libresoc.v:153544.13-153544.42"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8109
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__is_32bit$11$next[0:0]$8062
- attribute \src "libresoc.v:153778.3-153779.57"
- wire $0\mul_op__is_32bit$11[0:0]$8041
- attribute \src "libresoc.v:153627.7-153627.35"
- wire $0\mul_op__is_32bit$11[0:0]$8111
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__is_signed$12$next[0:0]$8063
- attribute \src "libresoc.v:153780.3-153781.59"
- wire $0\mul_op__is_signed$12[0:0]$8043
- attribute \src "libresoc.v:153636.7-153636.36"
- wire $0\mul_op__is_signed$12[0:0]$8113
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__oe__oe$8$next[0:0]$8064
- attribute \src "libresoc.v:153772.3-153773.51"
- wire $0\mul_op__oe__oe$8[0:0]$8035
- attribute \src "libresoc.v:153647.7-153647.32"
- wire $0\mul_op__oe__oe$8[0:0]$8115
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__oe__ok$9$next[0:0]$8065
- attribute \src "libresoc.v:153774.3-153775.51"
- wire $0\mul_op__oe__ok$9[0:0]$8037
- attribute \src "libresoc.v:153656.7-153656.32"
- wire $0\mul_op__oe__ok$9[0:0]$8117
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__rc__ok$7$next[0:0]$8066
- attribute \src "libresoc.v:153770.3-153771.51"
- wire $0\mul_op__rc__ok$7[0:0]$8033
- attribute \src "libresoc.v:153665.7-153665.32"
- wire $0\mul_op__rc__ok$7[0:0]$8119
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__rc__rc$6$next[0:0]$8067
- attribute \src "libresoc.v:153768.3-153769.51"
- wire $0\mul_op__rc__rc$6[0:0]$8031
- attribute \src "libresoc.v:153674.7-153674.32"
- wire $0\mul_op__rc__rc$6[0:0]$8121
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $0\mul_op__write_cr0$10$next[0:0]$8068
- attribute \src "libresoc.v:153776.3-153777.59"
- wire $0\mul_op__write_cr0$10[0:0]$8039
- attribute \src "libresoc.v:153681.7-153681.36"
- wire $0\mul_op__write_cr0$10[0:0]$8123
- attribute \src "libresoc.v:153851.3-153863.6"
- wire width 2 $0\muxid$1$next[1:0]$8054
- attribute \src "libresoc.v:153784.3-153785.33"
- wire width 2 $0\muxid$1[1:0]$8047
- attribute \src "libresoc.v:153690.13-153690.29"
- wire width 2 $0\muxid$1[1:0]$8125
- attribute \src "libresoc.v:153926.3-153938.6"
- wire $0\neg_res$15$next[0:0]$8094
- attribute \src "libresoc.v:153754.3-153755.39"
- wire $0\neg_res$15[0:0]$8018
- attribute \src "libresoc.v:153705.7-153705.26"
- wire $0\neg_res$15[0:0]$8127
- attribute \src "libresoc.v:153939.3-153951.6"
- wire $0\neg_res32$16$next[0:0]$8097
- attribute \src "libresoc.v:153752.3-153753.43"
- wire $0\neg_res32$16[0:0]$8016
- attribute \src "libresoc.v:153714.7-153714.28"
- wire $0\neg_res32$16[0:0]$8129
- attribute \src "libresoc.v:153900.3-153912.6"
- wire width 129 $0\o$next[128:0]$8088
- attribute \src "libresoc.v:153758.3-153759.19"
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 13 $0\mul_op__fn_unit$3$next[12:0]$7983
+ attribute \src "libresoc.v:151892.3-151893.53"
+ wire width 13 $0\mul_op__fn_unit$3[12:0]$7951
+ attribute \src "libresoc.v:151476.14-151476.44"
+ wire width 13 $0\mul_op__fn_unit$3[12:0]$8027
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7984
+ attribute \src "libresoc.v:151894.3-151895.67"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$7953
+ attribute \src "libresoc.v:151501.14-151501.63"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8029
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__imm_data__ok$5$next[0:0]$7985
+ attribute \src "libresoc.v:151896.3-151897.63"
+ wire $0\mul_op__imm_data__ok$5[0:0]$7955
+ attribute \src "libresoc.v:151510.7-151510.38"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8031
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 32 $0\mul_op__insn$13$next[31:0]$7986
+ attribute \src "libresoc.v:151912.3-151913.49"
+ wire width 32 $0\mul_op__insn$13[31:0]$7971
+ attribute \src "libresoc.v:151517.14-151517.39"
+ wire width 32 $0\mul_op__insn$13[31:0]$8033
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 7 $0\mul_op__insn_type$2$next[6:0]$7987
+ attribute \src "libresoc.v:151890.3-151891.57"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$7949
+ attribute \src "libresoc.v:151674.13-151674.42"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8035
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__is_32bit$11$next[0:0]$7988
+ attribute \src "libresoc.v:151908.3-151909.57"
+ wire $0\mul_op__is_32bit$11[0:0]$7967
+ attribute \src "libresoc.v:151757.7-151757.35"
+ wire $0\mul_op__is_32bit$11[0:0]$8037
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__is_signed$12$next[0:0]$7989
+ attribute \src "libresoc.v:151910.3-151911.59"
+ wire $0\mul_op__is_signed$12[0:0]$7969
+ attribute \src "libresoc.v:151766.7-151766.36"
+ wire $0\mul_op__is_signed$12[0:0]$8039
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__oe__oe$8$next[0:0]$7990
+ attribute \src "libresoc.v:151902.3-151903.51"
+ wire $0\mul_op__oe__oe$8[0:0]$7961
+ attribute \src "libresoc.v:151777.7-151777.32"
+ wire $0\mul_op__oe__oe$8[0:0]$8041
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__oe__ok$9$next[0:0]$7991
+ attribute \src "libresoc.v:151904.3-151905.51"
+ wire $0\mul_op__oe__ok$9[0:0]$7963
+ attribute \src "libresoc.v:151786.7-151786.32"
+ wire $0\mul_op__oe__ok$9[0:0]$8043
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__rc__ok$7$next[0:0]$7992
+ attribute \src "libresoc.v:151900.3-151901.51"
+ wire $0\mul_op__rc__ok$7[0:0]$7959
+ attribute \src "libresoc.v:151795.7-151795.32"
+ wire $0\mul_op__rc__ok$7[0:0]$8045
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__rc__rc$6$next[0:0]$7993
+ attribute \src "libresoc.v:151898.3-151899.51"
+ wire $0\mul_op__rc__rc$6[0:0]$7957
+ attribute \src "libresoc.v:151804.7-151804.32"
+ wire $0\mul_op__rc__rc$6[0:0]$8047
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $0\mul_op__write_cr0$10$next[0:0]$7994
+ attribute \src "libresoc.v:151906.3-151907.59"
+ wire $0\mul_op__write_cr0$10[0:0]$7965
+ attribute \src "libresoc.v:151811.7-151811.36"
+ wire $0\mul_op__write_cr0$10[0:0]$8049
+ attribute \src "libresoc.v:151981.3-151993.6"
+ wire width 2 $0\muxid$1$next[1:0]$7980
+ attribute \src "libresoc.v:151914.3-151915.33"
+ wire width 2 $0\muxid$1[1:0]$7973
+ attribute \src "libresoc.v:151820.13-151820.29"
+ wire width 2 $0\muxid$1[1:0]$8051
+ attribute \src "libresoc.v:152056.3-152068.6"
+ wire $0\neg_res$15$next[0:0]$8020
+ attribute \src "libresoc.v:151884.3-151885.39"
+ wire $0\neg_res$15[0:0]$7944
+ attribute \src "libresoc.v:151835.7-151835.26"
+ wire $0\neg_res$15[0:0]$8053
+ attribute \src "libresoc.v:152069.3-152081.6"
+ wire $0\neg_res32$16$next[0:0]$8023
+ attribute \src "libresoc.v:151882.3-151883.43"
+ wire $0\neg_res32$16[0:0]$7942
+ attribute \src "libresoc.v:151844.7-151844.28"
+ wire $0\neg_res32$16[0:0]$8055
+ attribute \src "libresoc.v:152030.3-152042.6"
+ wire width 129 $0\o$next[128:0]$8014
+ attribute \src "libresoc.v:151888.3-151889.19"
wire width 129 $0\o[128:0]
- attribute \src "libresoc.v:153833.3-153850.6"
- wire $0\r_busy$next[0:0]$8050
- attribute \src "libresoc.v:153786.3-153787.29"
+ attribute \src "libresoc.v:151963.3-151980.6"
+ wire $0\r_busy$next[0:0]$7976
+ attribute \src "libresoc.v:151916.3-151917.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:153913.3-153925.6"
- wire $0\xer_so$14$next[0:0]$8091
- attribute \src "libresoc.v:153756.3-153757.37"
- wire $0\xer_so$14[0:0]$8020
- attribute \src "libresoc.v:153746.7-153746.25"
- wire $0\xer_so$14[0:0]$8133
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8069
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8070
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__imm_data__ok$5$next[0:0]$8071
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 32 $1\mul_op__insn$13$next[31:0]$8072
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 7 $1\mul_op__insn_type$2$next[6:0]$8073
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__is_32bit$11$next[0:0]$8074
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__is_signed$12$next[0:0]$8075
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__oe__oe$8$next[0:0]$8076
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__oe__ok$9$next[0:0]$8077
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__rc__ok$7$next[0:0]$8078
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__rc__rc$6$next[0:0]$8079
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $1\mul_op__write_cr0$10$next[0:0]$8080
- attribute \src "libresoc.v:153851.3-153863.6"
- wire width 2 $1\muxid$1$next[1:0]$8055
- attribute \src "libresoc.v:153926.3-153938.6"
- wire $1\neg_res$15$next[0:0]$8095
- attribute \src "libresoc.v:153939.3-153951.6"
- wire $1\neg_res32$16$next[0:0]$8098
- attribute \src "libresoc.v:153900.3-153912.6"
- wire width 129 $1\o$next[128:0]$8089
- attribute \src "libresoc.v:153721.15-153721.57"
+ attribute \src "libresoc.v:152043.3-152055.6"
+ wire $0\xer_so$14$next[0:0]$8017
+ attribute \src "libresoc.v:151886.3-151887.37"
+ wire $0\xer_so$14[0:0]$7946
+ attribute \src "libresoc.v:151876.7-151876.25"
+ wire $0\xer_so$14[0:0]$8059
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 13 $1\mul_op__fn_unit$3$next[12:0]$7995
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7996
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__imm_data__ok$5$next[0:0]$7997
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 32 $1\mul_op__insn$13$next[31:0]$7998
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 7 $1\mul_op__insn_type$2$next[6:0]$7999
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__is_32bit$11$next[0:0]$8000
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__is_signed$12$next[0:0]$8001
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__oe__oe$8$next[0:0]$8002
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__oe__ok$9$next[0:0]$8003
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__rc__ok$7$next[0:0]$8004
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__rc__rc$6$next[0:0]$8005
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $1\mul_op__write_cr0$10$next[0:0]$8006
+ attribute \src "libresoc.v:151981.3-151993.6"
+ wire width 2 $1\muxid$1$next[1:0]$7981
+ attribute \src "libresoc.v:152056.3-152068.6"
+ wire $1\neg_res$15$next[0:0]$8021
+ attribute \src "libresoc.v:152069.3-152081.6"
+ wire $1\neg_res32$16$next[0:0]$8024
+ attribute \src "libresoc.v:152030.3-152042.6"
+ wire width 129 $1\o$next[128:0]$8015
+ attribute \src "libresoc.v:151851.15-151851.57"
wire width 129 $1\o[128:0]
- attribute \src "libresoc.v:153833.3-153850.6"
- wire $1\r_busy$next[0:0]$8051
- attribute \src "libresoc.v:153735.7-153735.20"
+ attribute \src "libresoc.v:151963.3-151980.6"
+ wire $1\r_busy$next[0:0]$7977
+ attribute \src "libresoc.v:151865.7-151865.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:153913.3-153925.6"
- wire $1\xer_so$14$next[0:0]$8092
- attribute \src "libresoc.v:153864.3-153899.6"
- wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8081
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $2\mul_op__imm_data__ok$5$next[0:0]$8082
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $2\mul_op__oe__oe$8$next[0:0]$8083
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $2\mul_op__oe__ok$9$next[0:0]$8084
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $2\mul_op__rc__ok$7$next[0:0]$8085
- attribute \src "libresoc.v:153864.3-153899.6"
- wire $2\mul_op__rc__rc$6$next[0:0]$8086
- attribute \src "libresoc.v:153833.3-153850.6"
- wire $2\r_busy$next[0:0]$8052
- attribute \src "libresoc.v:153751.18-153751.118"
- wire $and$libresoc.v:153751$8014_Y
+ attribute \src "libresoc.v:152043.3-152055.6"
+ wire $1\xer_so$14$next[0:0]$8018
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8007
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $2\mul_op__imm_data__ok$5$next[0:0]$8008
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $2\mul_op__oe__oe$8$next[0:0]$8009
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $2\mul_op__oe__ok$9$next[0:0]$8010
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $2\mul_op__rc__ok$7$next[0:0]$8011
+ attribute \src "libresoc.v:151994.3-152029.6"
+ wire $2\mul_op__rc__rc$6$next[0:0]$8012
+ attribute \src "libresoc.v:151963.3-151980.6"
+ wire $2\r_busy$next[0:0]$7978
+ attribute \src "libresoc.v:151881.18-151881.118"
+ wire $and$libresoc.v:151881$7940_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:153061.7-153061.15"
+ attribute \src "libresoc.v:151191.7-151191.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$50
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:153751$8014
+ cell $and $and$libresoc.v:151881$7940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$33
connect \B \p_ready_o
- connect \Y $and$libresoc.v:153751$8014_Y
+ connect \Y $and$libresoc.v:151881$7940_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153788.8-153824.4"
+ attribute \src "libresoc.v:151918.8-151954.4"
cell \mul2 \mul2
connect \mul_op__fn_unit \mul2_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19
connect \xer_so$14 \mul2_xer_so$30
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153825.10-153828.4"
+ attribute \src "libresoc.v:151955.10-151958.4"
cell \n$97 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:153829.10-153832.4"
+ attribute \src "libresoc.v:151959.10-151962.4"
cell \p$96 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:153061.7-153061.20"
- process $proc$libresoc.v:153061$8099
+ attribute \src "libresoc.v:151191.7-151191.20"
+ process $proc$libresoc.v:151191$8025
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:153346.14-153346.44"
- process $proc$libresoc.v:153346$8100
+ attribute \src "libresoc.v:151476.14-151476.44"
+ process $proc$libresoc.v:151476$8026
assign { } { }
- assign $0\mul_op__fn_unit$3[12:0]$8101 13'0000000000000
+ assign $0\mul_op__fn_unit$3[12:0]$8027 13'0000000000000
sync always
sync init
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8101
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8027
end
- attribute \src "libresoc.v:153371.14-153371.63"
- process $proc$libresoc.v:153371$8102
+ attribute \src "libresoc.v:151501.14-151501.63"
+ process $proc$libresoc.v:151501$8028
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8103 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\mul_op__imm_data__data$4[63:0]$8029 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8103
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8029
end
- attribute \src "libresoc.v:153380.7-153380.38"
- process $proc$libresoc.v:153380$8104
+ attribute \src "libresoc.v:151510.7-151510.38"
+ process $proc$libresoc.v:151510$8030
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8105 1'0
+ assign $0\mul_op__imm_data__ok$5[0:0]$8031 1'0
sync always
sync init
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8105
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8031
end
- attribute \src "libresoc.v:153387.14-153387.39"
- process $proc$libresoc.v:153387$8106
+ attribute \src "libresoc.v:151517.14-151517.39"
+ process $proc$libresoc.v:151517$8032
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8107 0
+ assign $0\mul_op__insn$13[31:0]$8033 0
sync always
sync init
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8107
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8033
end
- attribute \src "libresoc.v:153544.13-153544.42"
- process $proc$libresoc.v:153544$8108
+ attribute \src "libresoc.v:151674.13-151674.42"
+ process $proc$libresoc.v:151674$8034
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8109 7'0000000
+ assign $0\mul_op__insn_type$2[6:0]$8035 7'0000000
sync always
sync init
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8109
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8035
end
- attribute \src "libresoc.v:153627.7-153627.35"
- process $proc$libresoc.v:153627$8110
+ attribute \src "libresoc.v:151757.7-151757.35"
+ process $proc$libresoc.v:151757$8036
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8111 1'0
+ assign $0\mul_op__is_32bit$11[0:0]$8037 1'0
sync always
sync init
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8111
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8037
end
- attribute \src "libresoc.v:153636.7-153636.36"
- process $proc$libresoc.v:153636$8112
+ attribute \src "libresoc.v:151766.7-151766.36"
+ process $proc$libresoc.v:151766$8038
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8113 1'0
+ assign $0\mul_op__is_signed$12[0:0]$8039 1'0
sync always
sync init
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8113
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8039
end
- attribute \src "libresoc.v:153647.7-153647.32"
- process $proc$libresoc.v:153647$8114
+ attribute \src "libresoc.v:151777.7-151777.32"
+ process $proc$libresoc.v:151777$8040
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8115 1'0
+ assign $0\mul_op__oe__oe$8[0:0]$8041 1'0
sync always
sync init
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8115
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8041
end
- attribute \src "libresoc.v:153656.7-153656.32"
- process $proc$libresoc.v:153656$8116
+ attribute \src "libresoc.v:151786.7-151786.32"
+ process $proc$libresoc.v:151786$8042
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8117 1'0
+ assign $0\mul_op__oe__ok$9[0:0]$8043 1'0
sync always
sync init
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8117
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8043
end
- attribute \src "libresoc.v:153665.7-153665.32"
- process $proc$libresoc.v:153665$8118
+ attribute \src "libresoc.v:151795.7-151795.32"
+ process $proc$libresoc.v:151795$8044
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8119 1'0
+ assign $0\mul_op__rc__ok$7[0:0]$8045 1'0
sync always
sync init
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8119
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8045
end
- attribute \src "libresoc.v:153674.7-153674.32"
- process $proc$libresoc.v:153674$8120
+ attribute \src "libresoc.v:151804.7-151804.32"
+ process $proc$libresoc.v:151804$8046
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8121 1'0
+ assign $0\mul_op__rc__rc$6[0:0]$8047 1'0
sync always
sync init
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8121
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8047
end
- attribute \src "libresoc.v:153681.7-153681.36"
- process $proc$libresoc.v:153681$8122
+ attribute \src "libresoc.v:151811.7-151811.36"
+ process $proc$libresoc.v:151811$8048
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8123 1'0
+ assign $0\mul_op__write_cr0$10[0:0]$8049 1'0
sync always
sync init
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8123
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8049
end
- attribute \src "libresoc.v:153690.13-153690.29"
- process $proc$libresoc.v:153690$8124
+ attribute \src "libresoc.v:151820.13-151820.29"
+ process $proc$libresoc.v:151820$8050
assign { } { }
- assign $0\muxid$1[1:0]$8125 2'00
+ assign $0\muxid$1[1:0]$8051 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8125
+ update \muxid$1 $0\muxid$1[1:0]$8051
end
- attribute \src "libresoc.v:153705.7-153705.26"
- process $proc$libresoc.v:153705$8126
+ attribute \src "libresoc.v:151835.7-151835.26"
+ process $proc$libresoc.v:151835$8052
assign { } { }
- assign $0\neg_res$15[0:0]$8127 1'0
+ assign $0\neg_res$15[0:0]$8053 1'0
sync always
sync init
- update \neg_res$15 $0\neg_res$15[0:0]$8127
+ update \neg_res$15 $0\neg_res$15[0:0]$8053
end
- attribute \src "libresoc.v:153714.7-153714.28"
- process $proc$libresoc.v:153714$8128
+ attribute \src "libresoc.v:151844.7-151844.28"
+ process $proc$libresoc.v:151844$8054
assign { } { }
- assign $0\neg_res32$16[0:0]$8129 1'0
+ assign $0\neg_res32$16[0:0]$8055 1'0
sync always
sync init
- update \neg_res32$16 $0\neg_res32$16[0:0]$8129
+ update \neg_res32$16 $0\neg_res32$16[0:0]$8055
end
- attribute \src "libresoc.v:153721.15-153721.57"
- process $proc$libresoc.v:153721$8130
+ attribute \src "libresoc.v:151851.15-151851.57"
+ process $proc$libresoc.v:151851$8056
assign { } { }
assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[128:0]
end
- attribute \src "libresoc.v:153735.7-153735.20"
- process $proc$libresoc.v:153735$8131
+ attribute \src "libresoc.v:151865.7-151865.20"
+ process $proc$libresoc.v:151865$8057
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:153746.7-153746.25"
- process $proc$libresoc.v:153746$8132
+ attribute \src "libresoc.v:151876.7-151876.25"
+ process $proc$libresoc.v:151876$8058
assign { } { }
- assign $0\xer_so$14[0:0]$8133 1'0
+ assign $0\xer_so$14[0:0]$8059 1'0
sync always
sync init
- update \xer_so$14 $0\xer_so$14[0:0]$8133
+ update \xer_so$14 $0\xer_so$14[0:0]$8059
end
- attribute \src "libresoc.v:153752.3-153753.43"
- process $proc$libresoc.v:153752$8015
+ attribute \src "libresoc.v:151882.3-151883.43"
+ process $proc$libresoc.v:151882$7941
assign { } { }
- assign $0\neg_res32$16[0:0]$8016 \neg_res32$16$next
+ assign $0\neg_res32$16[0:0]$7942 \neg_res32$16$next
sync posedge \coresync_clk
- update \neg_res32$16 $0\neg_res32$16[0:0]$8016
+ update \neg_res32$16 $0\neg_res32$16[0:0]$7942
end
- attribute \src "libresoc.v:153754.3-153755.39"
- process $proc$libresoc.v:153754$8017
+ attribute \src "libresoc.v:151884.3-151885.39"
+ process $proc$libresoc.v:151884$7943
assign { } { }
- assign $0\neg_res$15[0:0]$8018 \neg_res$15$next
+ assign $0\neg_res$15[0:0]$7944 \neg_res$15$next
sync posedge \coresync_clk
- update \neg_res$15 $0\neg_res$15[0:0]$8018
+ update \neg_res$15 $0\neg_res$15[0:0]$7944
end
- attribute \src "libresoc.v:153756.3-153757.37"
- process $proc$libresoc.v:153756$8019
+ attribute \src "libresoc.v:151886.3-151887.37"
+ process $proc$libresoc.v:151886$7945
assign { } { }
- assign $0\xer_so$14[0:0]$8020 \xer_so$14$next
+ assign $0\xer_so$14[0:0]$7946 \xer_so$14$next
sync posedge \coresync_clk
- update \xer_so$14 $0\xer_so$14[0:0]$8020
+ update \xer_so$14 $0\xer_so$14[0:0]$7946
end
- attribute \src "libresoc.v:153758.3-153759.19"
- process $proc$libresoc.v:153758$8021
+ attribute \src "libresoc.v:151888.3-151889.19"
+ process $proc$libresoc.v:151888$7947
assign { } { }
assign $0\o[128:0] \o$next
sync posedge \coresync_clk
update \o $0\o[128:0]
end
- attribute \src "libresoc.v:153760.3-153761.57"
- process $proc$libresoc.v:153760$8022
+ attribute \src "libresoc.v:151890.3-151891.57"
+ process $proc$libresoc.v:151890$7948
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8023 \mul_op__insn_type$2$next
+ assign $0\mul_op__insn_type$2[6:0]$7949 \mul_op__insn_type$2$next
sync posedge \coresync_clk
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8023
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7949
end
- attribute \src "libresoc.v:153762.3-153763.53"
- process $proc$libresoc.v:153762$8024
+ attribute \src "libresoc.v:151892.3-151893.53"
+ process $proc$libresoc.v:151892$7950
assign { } { }
- assign $0\mul_op__fn_unit$3[12:0]$8025 \mul_op__fn_unit$3$next
+ assign $0\mul_op__fn_unit$3[12:0]$7951 \mul_op__fn_unit$3$next
sync posedge \coresync_clk
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8025
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$7951
end
- attribute \src "libresoc.v:153764.3-153765.67"
- process $proc$libresoc.v:153764$8026
+ attribute \src "libresoc.v:151894.3-151895.67"
+ process $proc$libresoc.v:151894$7952
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8027 \mul_op__imm_data__data$4$next
+ assign $0\mul_op__imm_data__data$4[63:0]$7953 \mul_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8027
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7953
end
- attribute \src "libresoc.v:153766.3-153767.63"
- process $proc$libresoc.v:153766$8028
+ attribute \src "libresoc.v:151896.3-151897.63"
+ process $proc$libresoc.v:151896$7954
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8029 \mul_op__imm_data__ok$5$next
+ assign $0\mul_op__imm_data__ok$5[0:0]$7955 \mul_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8029
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7955
end
- attribute \src "libresoc.v:153768.3-153769.51"
- process $proc$libresoc.v:153768$8030
+ attribute \src "libresoc.v:151898.3-151899.51"
+ process $proc$libresoc.v:151898$7956
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8031 \mul_op__rc__rc$6$next
+ assign $0\mul_op__rc__rc$6[0:0]$7957 \mul_op__rc__rc$6$next
sync posedge \coresync_clk
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8031
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7957
end
- attribute \src "libresoc.v:153770.3-153771.51"
- process $proc$libresoc.v:153770$8032
+ attribute \src "libresoc.v:151900.3-151901.51"
+ process $proc$libresoc.v:151900$7958
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8033 \mul_op__rc__ok$7$next
+ assign $0\mul_op__rc__ok$7[0:0]$7959 \mul_op__rc__ok$7$next
sync posedge \coresync_clk
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8033
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7959
end
- attribute \src "libresoc.v:153772.3-153773.51"
- process $proc$libresoc.v:153772$8034
+ attribute \src "libresoc.v:151902.3-151903.51"
+ process $proc$libresoc.v:151902$7960
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8035 \mul_op__oe__oe$8$next
+ assign $0\mul_op__oe__oe$8[0:0]$7961 \mul_op__oe__oe$8$next
sync posedge \coresync_clk
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8035
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7961
end
- attribute \src "libresoc.v:153774.3-153775.51"
- process $proc$libresoc.v:153774$8036
+ attribute \src "libresoc.v:151904.3-151905.51"
+ process $proc$libresoc.v:151904$7962
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8037 \mul_op__oe__ok$9$next
+ assign $0\mul_op__oe__ok$9[0:0]$7963 \mul_op__oe__ok$9$next
sync posedge \coresync_clk
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8037
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7963
end
- attribute \src "libresoc.v:153776.3-153777.59"
- process $proc$libresoc.v:153776$8038
+ attribute \src "libresoc.v:151906.3-151907.59"
+ process $proc$libresoc.v:151906$7964
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8039 \mul_op__write_cr0$10$next
+ assign $0\mul_op__write_cr0$10[0:0]$7965 \mul_op__write_cr0$10$next
sync posedge \coresync_clk
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8039
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7965
end
- attribute \src "libresoc.v:153778.3-153779.57"
- process $proc$libresoc.v:153778$8040
+ attribute \src "libresoc.v:151908.3-151909.57"
+ process $proc$libresoc.v:151908$7966
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8041 \mul_op__is_32bit$11$next
+ assign $0\mul_op__is_32bit$11[0:0]$7967 \mul_op__is_32bit$11$next
sync posedge \coresync_clk
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8041
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7967
end
- attribute \src "libresoc.v:153780.3-153781.59"
- process $proc$libresoc.v:153780$8042
+ attribute \src "libresoc.v:151910.3-151911.59"
+ process $proc$libresoc.v:151910$7968
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8043 \mul_op__is_signed$12$next
+ assign $0\mul_op__is_signed$12[0:0]$7969 \mul_op__is_signed$12$next
sync posedge \coresync_clk
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8043
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7969
end
- attribute \src "libresoc.v:153782.3-153783.49"
- process $proc$libresoc.v:153782$8044
+ attribute \src "libresoc.v:151912.3-151913.49"
+ process $proc$libresoc.v:151912$7970
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8045 \mul_op__insn$13$next
+ assign $0\mul_op__insn$13[31:0]$7971 \mul_op__insn$13$next
sync posedge \coresync_clk
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8045
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7971
end
- attribute \src "libresoc.v:153784.3-153785.33"
- process $proc$libresoc.v:153784$8046
+ attribute \src "libresoc.v:151914.3-151915.33"
+ process $proc$libresoc.v:151914$7972
assign { } { }
- assign $0\muxid$1[1:0]$8047 \muxid$1$next
+ assign $0\muxid$1[1:0]$7973 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8047
+ update \muxid$1 $0\muxid$1[1:0]$7973
end
- attribute \src "libresoc.v:153786.3-153787.29"
- process $proc$libresoc.v:153786$8048
+ attribute \src "libresoc.v:151916.3-151917.29"
+ process $proc$libresoc.v:151916$7974
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:153833.3-153850.6"
- process $proc$libresoc.v:153833$8049
+ attribute \src "libresoc.v:151963.3-151980.6"
+ process $proc$libresoc.v:151963$7975
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8050 $2\r_busy$next[0:0]$8052
- attribute \src "libresoc.v:153834.5-153834.29"
+ assign $0\r_busy$next[0:0]$7976 $2\r_busy$next[0:0]$7978
+ attribute \src "libresoc.v:151964.5-151964.29"
switch \initial
- attribute \src "libresoc.v:153834.9-153834.17"
+ attribute \src "libresoc.v:151964.9-151964.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8051 1'1
+ assign $1\r_busy$next[0:0]$7977 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8051 1'0
+ assign $1\r_busy$next[0:0]$7977 1'0
case
- assign $1\r_busy$next[0:0]$8051 \r_busy
+ assign $1\r_busy$next[0:0]$7977 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8052 1'0
+ assign $2\r_busy$next[0:0]$7978 1'0
case
- assign $2\r_busy$next[0:0]$8052 $1\r_busy$next[0:0]$8051
+ assign $2\r_busy$next[0:0]$7978 $1\r_busy$next[0:0]$7977
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8050
+ update \r_busy$next $0\r_busy$next[0:0]$7976
end
- attribute \src "libresoc.v:153851.3-153863.6"
- process $proc$libresoc.v:153851$8053
+ attribute \src "libresoc.v:151981.3-151993.6"
+ process $proc$libresoc.v:151981$7979
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8054 $1\muxid$1$next[1:0]$8055
- attribute \src "libresoc.v:153852.5-153852.29"
+ assign $0\muxid$1$next[1:0]$7980 $1\muxid$1$next[1:0]$7981
+ attribute \src "libresoc.v:151982.5-151982.29"
switch \initial
- attribute \src "libresoc.v:153852.9-153852.17"
+ attribute \src "libresoc.v:151982.9-151982.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8055 \muxid$36
+ assign $1\muxid$1$next[1:0]$7981 \muxid$36
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8055 \muxid$36
+ assign $1\muxid$1$next[1:0]$7981 \muxid$36
case
- assign $1\muxid$1$next[1:0]$8055 \muxid$1
+ assign $1\muxid$1$next[1:0]$7981 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8054
+ update \muxid$1$next $0\muxid$1$next[1:0]$7980
end
- attribute \src "libresoc.v:153864.3-153899.6"
- process $proc$libresoc.v:153864$8056
+ attribute \src "libresoc.v:151994.3-152029.6"
+ process $proc$libresoc.v:151994$7982
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$3$next[12:0]$8057 $1\mul_op__fn_unit$3$next[12:0]$8069
+ assign $0\mul_op__fn_unit$3$next[12:0]$7983 $1\mul_op__fn_unit$3$next[12:0]$7995
assign { } { }
assign { } { }
- assign $0\mul_op__insn$13$next[31:0]$8060 $1\mul_op__insn$13$next[31:0]$8072
- assign $0\mul_op__insn_type$2$next[6:0]$8061 $1\mul_op__insn_type$2$next[6:0]$8073
- assign $0\mul_op__is_32bit$11$next[0:0]$8062 $1\mul_op__is_32bit$11$next[0:0]$8074
- assign $0\mul_op__is_signed$12$next[0:0]$8063 $1\mul_op__is_signed$12$next[0:0]$8075
+ assign $0\mul_op__insn$13$next[31:0]$7986 $1\mul_op__insn$13$next[31:0]$7998
+ assign $0\mul_op__insn_type$2$next[6:0]$7987 $1\mul_op__insn_type$2$next[6:0]$7999
+ assign $0\mul_op__is_32bit$11$next[0:0]$7988 $1\mul_op__is_32bit$11$next[0:0]$8000
+ assign $0\mul_op__is_signed$12$next[0:0]$7989 $1\mul_op__is_signed$12$next[0:0]$8001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$10$next[0:0]$8068 $1\mul_op__write_cr0$10$next[0:0]$8080
- assign $0\mul_op__imm_data__data$4$next[63:0]$8058 $2\mul_op__imm_data__data$4$next[63:0]$8081
- assign $0\mul_op__imm_data__ok$5$next[0:0]$8059 $2\mul_op__imm_data__ok$5$next[0:0]$8082
- assign $0\mul_op__oe__oe$8$next[0:0]$8064 $2\mul_op__oe__oe$8$next[0:0]$8083
- assign $0\mul_op__oe__ok$9$next[0:0]$8065 $2\mul_op__oe__ok$9$next[0:0]$8084
- assign $0\mul_op__rc__ok$7$next[0:0]$8066 $2\mul_op__rc__ok$7$next[0:0]$8085
- assign $0\mul_op__rc__rc$6$next[0:0]$8067 $2\mul_op__rc__rc$6$next[0:0]$8086
- attribute \src "libresoc.v:153865.5-153865.29"
+ assign $0\mul_op__write_cr0$10$next[0:0]$7994 $1\mul_op__write_cr0$10$next[0:0]$8006
+ assign $0\mul_op__imm_data__data$4$next[63:0]$7984 $2\mul_op__imm_data__data$4$next[63:0]$8007
+ assign $0\mul_op__imm_data__ok$5$next[0:0]$7985 $2\mul_op__imm_data__ok$5$next[0:0]$8008
+ assign $0\mul_op__oe__oe$8$next[0:0]$7990 $2\mul_op__oe__oe$8$next[0:0]$8009
+ assign $0\mul_op__oe__ok$9$next[0:0]$7991 $2\mul_op__oe__ok$9$next[0:0]$8010
+ assign $0\mul_op__rc__ok$7$next[0:0]$7992 $2\mul_op__rc__ok$7$next[0:0]$8011
+ assign $0\mul_op__rc__rc$6$next[0:0]$7993 $2\mul_op__rc__rc$6$next[0:0]$8012
+ attribute \src "libresoc.v:151995.5-151995.29"
switch \initial
- attribute \src "libresoc.v:153865.9-153865.17"
+ attribute \src "libresoc.v:151995.9-151995.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8072 $1\mul_op__is_signed$12$next[0:0]$8075 $1\mul_op__is_32bit$11$next[0:0]$8074 $1\mul_op__write_cr0$10$next[0:0]$8080 $1\mul_op__oe__ok$9$next[0:0]$8077 $1\mul_op__oe__oe$8$next[0:0]$8076 $1\mul_op__rc__ok$7$next[0:0]$8078 $1\mul_op__rc__rc$6$next[0:0]$8079 $1\mul_op__imm_data__ok$5$next[0:0]$8071 $1\mul_op__imm_data__data$4$next[63:0]$8070 $1\mul_op__fn_unit$3$next[12:0]$8069 $1\mul_op__insn_type$2$next[6:0]$8073 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
+ assign { $1\mul_op__insn$13$next[31:0]$7998 $1\mul_op__is_signed$12$next[0:0]$8001 $1\mul_op__is_32bit$11$next[0:0]$8000 $1\mul_op__write_cr0$10$next[0:0]$8006 $1\mul_op__oe__ok$9$next[0:0]$8003 $1\mul_op__oe__oe$8$next[0:0]$8002 $1\mul_op__rc__ok$7$next[0:0]$8004 $1\mul_op__rc__rc$6$next[0:0]$8005 $1\mul_op__imm_data__ok$5$next[0:0]$7997 $1\mul_op__imm_data__data$4$next[63:0]$7996 $1\mul_op__fn_unit$3$next[12:0]$7995 $1\mul_op__insn_type$2$next[6:0]$7999 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8072 $1\mul_op__is_signed$12$next[0:0]$8075 $1\mul_op__is_32bit$11$next[0:0]$8074 $1\mul_op__write_cr0$10$next[0:0]$8080 $1\mul_op__oe__ok$9$next[0:0]$8077 $1\mul_op__oe__oe$8$next[0:0]$8076 $1\mul_op__rc__ok$7$next[0:0]$8078 $1\mul_op__rc__rc$6$next[0:0]$8079 $1\mul_op__imm_data__ok$5$next[0:0]$8071 $1\mul_op__imm_data__data$4$next[63:0]$8070 $1\mul_op__fn_unit$3$next[12:0]$8069 $1\mul_op__insn_type$2$next[6:0]$8073 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
+ assign { $1\mul_op__insn$13$next[31:0]$7998 $1\mul_op__is_signed$12$next[0:0]$8001 $1\mul_op__is_32bit$11$next[0:0]$8000 $1\mul_op__write_cr0$10$next[0:0]$8006 $1\mul_op__oe__ok$9$next[0:0]$8003 $1\mul_op__oe__oe$8$next[0:0]$8002 $1\mul_op__rc__ok$7$next[0:0]$8004 $1\mul_op__rc__rc$6$next[0:0]$8005 $1\mul_op__imm_data__ok$5$next[0:0]$7997 $1\mul_op__imm_data__data$4$next[63:0]$7996 $1\mul_op__fn_unit$3$next[12:0]$7995 $1\mul_op__insn_type$2$next[6:0]$7999 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 }
case
- assign $1\mul_op__fn_unit$3$next[12:0]$8069 \mul_op__fn_unit$3
- assign $1\mul_op__imm_data__data$4$next[63:0]$8070 \mul_op__imm_data__data$4
- assign $1\mul_op__imm_data__ok$5$next[0:0]$8071 \mul_op__imm_data__ok$5
- assign $1\mul_op__insn$13$next[31:0]$8072 \mul_op__insn$13
- assign $1\mul_op__insn_type$2$next[6:0]$8073 \mul_op__insn_type$2
- assign $1\mul_op__is_32bit$11$next[0:0]$8074 \mul_op__is_32bit$11
- assign $1\mul_op__is_signed$12$next[0:0]$8075 \mul_op__is_signed$12
- assign $1\mul_op__oe__oe$8$next[0:0]$8076 \mul_op__oe__oe$8
- assign $1\mul_op__oe__ok$9$next[0:0]$8077 \mul_op__oe__ok$9
- assign $1\mul_op__rc__ok$7$next[0:0]$8078 \mul_op__rc__ok$7
- assign $1\mul_op__rc__rc$6$next[0:0]$8079 \mul_op__rc__rc$6
- assign $1\mul_op__write_cr0$10$next[0:0]$8080 \mul_op__write_cr0$10
+ assign $1\mul_op__fn_unit$3$next[12:0]$7995 \mul_op__fn_unit$3
+ assign $1\mul_op__imm_data__data$4$next[63:0]$7996 \mul_op__imm_data__data$4
+ assign $1\mul_op__imm_data__ok$5$next[0:0]$7997 \mul_op__imm_data__ok$5
+ assign $1\mul_op__insn$13$next[31:0]$7998 \mul_op__insn$13
+ assign $1\mul_op__insn_type$2$next[6:0]$7999 \mul_op__insn_type$2
+ assign $1\mul_op__is_32bit$11$next[0:0]$8000 \mul_op__is_32bit$11
+ assign $1\mul_op__is_signed$12$next[0:0]$8001 \mul_op__is_signed$12
+ assign $1\mul_op__oe__oe$8$next[0:0]$8002 \mul_op__oe__oe$8
+ assign $1\mul_op__oe__ok$9$next[0:0]$8003 \mul_op__oe__ok$9
+ assign $1\mul_op__rc__ok$7$next[0:0]$8004 \mul_op__rc__ok$7
+ assign $1\mul_op__rc__rc$6$next[0:0]$8005 \mul_op__rc__rc$6
+ assign $1\mul_op__write_cr0$10$next[0:0]$8006 \mul_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$4$next[63:0]$8081 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8082 1'0
- assign $2\mul_op__rc__rc$6$next[0:0]$8086 1'0
- assign $2\mul_op__rc__ok$7$next[0:0]$8085 1'0
- assign $2\mul_op__oe__oe$8$next[0:0]$8083 1'0
- assign $2\mul_op__oe__ok$9$next[0:0]$8084 1'0
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8007 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8008 1'0
+ assign $2\mul_op__rc__rc$6$next[0:0]$8012 1'0
+ assign $2\mul_op__rc__ok$7$next[0:0]$8011 1'0
+ assign $2\mul_op__oe__oe$8$next[0:0]$8009 1'0
+ assign $2\mul_op__oe__ok$9$next[0:0]$8010 1'0
case
- assign $2\mul_op__imm_data__data$4$next[63:0]$8081 $1\mul_op__imm_data__data$4$next[63:0]$8070
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8071
- assign $2\mul_op__oe__oe$8$next[0:0]$8083 $1\mul_op__oe__oe$8$next[0:0]$8076
- assign $2\mul_op__oe__ok$9$next[0:0]$8084 $1\mul_op__oe__ok$9$next[0:0]$8077
- assign $2\mul_op__rc__ok$7$next[0:0]$8085 $1\mul_op__rc__ok$7$next[0:0]$8078
- assign $2\mul_op__rc__rc$6$next[0:0]$8086 $1\mul_op__rc__rc$6$next[0:0]$8079
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8007 $1\mul_op__imm_data__data$4$next[63:0]$7996
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8008 $1\mul_op__imm_data__ok$5$next[0:0]$7997
+ assign $2\mul_op__oe__oe$8$next[0:0]$8009 $1\mul_op__oe__oe$8$next[0:0]$8002
+ assign $2\mul_op__oe__ok$9$next[0:0]$8010 $1\mul_op__oe__ok$9$next[0:0]$8003
+ assign $2\mul_op__rc__ok$7$next[0:0]$8011 $1\mul_op__rc__ok$7$next[0:0]$8004
+ assign $2\mul_op__rc__rc$6$next[0:0]$8012 $1\mul_op__rc__rc$6$next[0:0]$8005
end
sync always
- update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8057
- update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8058
- update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8059
- update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8060
- update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8061
- update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8062
- update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8063
- update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8064
- update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8065
- update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8066
- update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8067
- update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8068
+ update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$7983
+ update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7984
+ update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7985
+ update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7986
+ update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7987
+ update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7988
+ update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7989
+ update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7990
+ update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7991
+ update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7992
+ update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7993
+ update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7994
end
- attribute \src "libresoc.v:153900.3-153912.6"
- process $proc$libresoc.v:153900$8087
+ attribute \src "libresoc.v:152030.3-152042.6"
+ process $proc$libresoc.v:152030$8013
assign { } { }
assign { } { }
- assign $0\o$next[128:0]$8088 $1\o$next[128:0]$8089
- attribute \src "libresoc.v:153901.5-153901.29"
+ assign $0\o$next[128:0]$8014 $1\o$next[128:0]$8015
+ attribute \src "libresoc.v:152031.5-152031.29"
switch \initial
- attribute \src "libresoc.v:153901.9-153901.17"
+ attribute \src "libresoc.v:152031.9-152031.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\o$next[128:0]$8089 \o$49
+ assign $1\o$next[128:0]$8015 \o$49
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\o$next[128:0]$8089 \o$49
+ assign $1\o$next[128:0]$8015 \o$49
case
- assign $1\o$next[128:0]$8089 \o
+ assign $1\o$next[128:0]$8015 \o
end
sync always
- update \o$next $0\o$next[128:0]$8088
+ update \o$next $0\o$next[128:0]$8014
end
- attribute \src "libresoc.v:153913.3-153925.6"
- process $proc$libresoc.v:153913$8090
+ attribute \src "libresoc.v:152043.3-152055.6"
+ process $proc$libresoc.v:152043$8016
assign { } { }
assign { } { }
- assign $0\xer_so$14$next[0:0]$8091 $1\xer_so$14$next[0:0]$8092
- attribute \src "libresoc.v:153914.5-153914.29"
+ assign $0\xer_so$14$next[0:0]$8017 $1\xer_so$14$next[0:0]$8018
+ attribute \src "libresoc.v:152044.5-152044.29"
switch \initial
- attribute \src "libresoc.v:153914.9-153914.17"
+ attribute \src "libresoc.v:152044.9-152044.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$14$next[0:0]$8092 \xer_so$50
+ assign $1\xer_so$14$next[0:0]$8018 \xer_so$50
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$14$next[0:0]$8092 \xer_so$50
+ assign $1\xer_so$14$next[0:0]$8018 \xer_so$50
case
- assign $1\xer_so$14$next[0:0]$8092 \xer_so$14
+ assign $1\xer_so$14$next[0:0]$8018 \xer_so$14
end
sync always
- update \xer_so$14$next $0\xer_so$14$next[0:0]$8091
+ update \xer_so$14$next $0\xer_so$14$next[0:0]$8017
end
- attribute \src "libresoc.v:153926.3-153938.6"
- process $proc$libresoc.v:153926$8093
+ attribute \src "libresoc.v:152056.3-152068.6"
+ process $proc$libresoc.v:152056$8019
assign { } { }
assign { } { }
- assign $0\neg_res$15$next[0:0]$8094 $1\neg_res$15$next[0:0]$8095
- attribute \src "libresoc.v:153927.5-153927.29"
+ assign $0\neg_res$15$next[0:0]$8020 $1\neg_res$15$next[0:0]$8021
+ attribute \src "libresoc.v:152057.5-152057.29"
switch \initial
- attribute \src "libresoc.v:153927.9-153927.17"
+ attribute \src "libresoc.v:152057.9-152057.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res$15$next[0:0]$8095 \neg_res$51
+ assign $1\neg_res$15$next[0:0]$8021 \neg_res$51
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res$15$next[0:0]$8095 \neg_res$51
+ assign $1\neg_res$15$next[0:0]$8021 \neg_res$51
case
- assign $1\neg_res$15$next[0:0]$8095 \neg_res$15
+ assign $1\neg_res$15$next[0:0]$8021 \neg_res$15
end
sync always
- update \neg_res$15$next $0\neg_res$15$next[0:0]$8094
+ update \neg_res$15$next $0\neg_res$15$next[0:0]$8020
end
- attribute \src "libresoc.v:153939.3-153951.6"
- process $proc$libresoc.v:153939$8096
+ attribute \src "libresoc.v:152069.3-152081.6"
+ process $proc$libresoc.v:152069$8022
assign { } { }
assign { } { }
- assign $0\neg_res32$16$next[0:0]$8097 $1\neg_res32$16$next[0:0]$8098
- attribute \src "libresoc.v:153940.5-153940.29"
+ assign $0\neg_res32$16$next[0:0]$8023 $1\neg_res32$16$next[0:0]$8024
+ attribute \src "libresoc.v:152070.5-152070.29"
switch \initial
- attribute \src "libresoc.v:153940.9-153940.17"
+ attribute \src "libresoc.v:152070.9-152070.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$52
+ assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$52
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$52
+ assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$52
case
- assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$16
+ assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$16
end
sync always
- update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8097
+ update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8023
end
- connect \$34 $and$libresoc.v:153751$8014_Y
+ connect \$34 $and$libresoc.v:151881$7940_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \neg_res32$52 \mul2_neg_res32$32
connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \mul2_muxid \muxid
end
-attribute \src "libresoc.v:153974.1-155256.10"
+attribute \src "libresoc.v:152104.1-153386.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3"
attribute \generator "nMigen"
module \mul_pipe3
- attribute \src "libresoc.v:155174.3-155192.6"
- wire width 4 $0\cr_a$next[3:0]$8217
- attribute \src "libresoc.v:154966.3-154967.25"
+ attribute \src "libresoc.v:153304.3-153322.6"
+ wire width 4 $0\cr_a$next[3:0]$8143
+ attribute \src "libresoc.v:153096.3-153097.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:155174.3-155192.6"
- wire $0\cr_a_ok$next[0:0]$8218
- attribute \src "libresoc.v:154968.3-154969.31"
+ attribute \src "libresoc.v:153304.3-153322.6"
+ wire $0\cr_a_ok$next[0:0]$8144
+ attribute \src "libresoc.v:153098.3-153099.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:153975.7-153975.20"
+ attribute \src "libresoc.v:152105.7-152105.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8180
- attribute \src "libresoc.v:154976.3-154977.53"
- wire width 13 $0\mul_op__fn_unit$3[12:0]$8148
- attribute \src "libresoc.v:154280.14-154280.44"
- wire width 13 $0\mul_op__fn_unit$3[12:0]$8238
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8181
- attribute \src "libresoc.v:154978.3-154979.67"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8150
- attribute \src "libresoc.v:154303.14-154303.63"
- wire width 64 $0\mul_op__imm_data__data$4[63:0]$8240
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__imm_data__ok$5$next[0:0]$8182
- attribute \src "libresoc.v:154980.3-154981.63"
- wire $0\mul_op__imm_data__ok$5[0:0]$8152
- attribute \src "libresoc.v:154312.7-154312.38"
- wire $0\mul_op__imm_data__ok$5[0:0]$8242
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 32 $0\mul_op__insn$13$next[31:0]$8183
- attribute \src "libresoc.v:154996.3-154997.49"
- wire width 32 $0\mul_op__insn$13[31:0]$8168
- attribute \src "libresoc.v:154321.14-154321.39"
- wire width 32 $0\mul_op__insn$13[31:0]$8244
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 7 $0\mul_op__insn_type$2$next[6:0]$8184
- attribute \src "libresoc.v:154974.3-154975.57"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8146
- attribute \src "libresoc.v:154478.13-154478.42"
- wire width 7 $0\mul_op__insn_type$2[6:0]$8246
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__is_32bit$11$next[0:0]$8185
- attribute \src "libresoc.v:154992.3-154993.57"
- wire $0\mul_op__is_32bit$11[0:0]$8164
- attribute \src "libresoc.v:154561.7-154561.35"
- wire $0\mul_op__is_32bit$11[0:0]$8248
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__is_signed$12$next[0:0]$8186
- attribute \src "libresoc.v:154994.3-154995.59"
- wire $0\mul_op__is_signed$12[0:0]$8166
- attribute \src "libresoc.v:154570.7-154570.36"
- wire $0\mul_op__is_signed$12[0:0]$8250
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__oe__oe$8$next[0:0]$8187
- attribute \src "libresoc.v:154986.3-154987.51"
- wire $0\mul_op__oe__oe$8[0:0]$8158
- attribute \src "libresoc.v:154581.7-154581.32"
- wire $0\mul_op__oe__oe$8[0:0]$8252
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__oe__ok$9$next[0:0]$8188
- attribute \src "libresoc.v:154988.3-154989.51"
- wire $0\mul_op__oe__ok$9[0:0]$8160
- attribute \src "libresoc.v:154590.7-154590.32"
- wire $0\mul_op__oe__ok$9[0:0]$8254
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__rc__ok$7$next[0:0]$8189
- attribute \src "libresoc.v:154984.3-154985.51"
- wire $0\mul_op__rc__ok$7[0:0]$8156
- attribute \src "libresoc.v:154599.7-154599.32"
- wire $0\mul_op__rc__ok$7[0:0]$8256
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__rc__rc$6$next[0:0]$8190
- attribute \src "libresoc.v:154982.3-154983.51"
- wire $0\mul_op__rc__rc$6[0:0]$8154
- attribute \src "libresoc.v:154606.7-154606.32"
- wire $0\mul_op__rc__rc$6[0:0]$8258
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $0\mul_op__write_cr0$10$next[0:0]$8191
- attribute \src "libresoc.v:154990.3-154991.59"
- wire $0\mul_op__write_cr0$10[0:0]$8162
- attribute \src "libresoc.v:154615.7-154615.36"
- wire $0\mul_op__write_cr0$10[0:0]$8260
- attribute \src "libresoc.v:155106.3-155118.6"
- wire width 2 $0\muxid$1$next[1:0]$8177
- attribute \src "libresoc.v:154998.3-154999.33"
- wire width 2 $0\muxid$1[1:0]$8170
- attribute \src "libresoc.v:154624.13-154624.29"
- wire width 2 $0\muxid$1[1:0]$8262
- attribute \src "libresoc.v:155155.3-155173.6"
- wire width 64 $0\o$14$next[63:0]$8212
- attribute \src "libresoc.v:154970.3-154971.27"
- wire width 64 $0\o$14[63:0]$8143
- attribute \src "libresoc.v:154645.14-154645.43"
- wire width 64 $0\o$14[63:0]$8264
- attribute \src "libresoc.v:155155.3-155173.6"
- wire $0\o_ok$next[0:0]$8211
- attribute \src "libresoc.v:154972.3-154973.25"
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8106
+ attribute \src "libresoc.v:153106.3-153107.53"
+ wire width 13 $0\mul_op__fn_unit$3[12:0]$8074
+ attribute \src "libresoc.v:152410.14-152410.44"
+ wire width 13 $0\mul_op__fn_unit$3[12:0]$8164
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8107
+ attribute \src "libresoc.v:153108.3-153109.67"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8076
+ attribute \src "libresoc.v:152433.14-152433.63"
+ wire width 64 $0\mul_op__imm_data__data$4[63:0]$8166
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__imm_data__ok$5$next[0:0]$8108
+ attribute \src "libresoc.v:153110.3-153111.63"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8078
+ attribute \src "libresoc.v:152442.7-152442.38"
+ wire $0\mul_op__imm_data__ok$5[0:0]$8168
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 32 $0\mul_op__insn$13$next[31:0]$8109
+ attribute \src "libresoc.v:153126.3-153127.49"
+ wire width 32 $0\mul_op__insn$13[31:0]$8094
+ attribute \src "libresoc.v:152451.14-152451.39"
+ wire width 32 $0\mul_op__insn$13[31:0]$8170
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 7 $0\mul_op__insn_type$2$next[6:0]$8110
+ attribute \src "libresoc.v:153104.3-153105.57"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8072
+ attribute \src "libresoc.v:152608.13-152608.42"
+ wire width 7 $0\mul_op__insn_type$2[6:0]$8172
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__is_32bit$11$next[0:0]$8111
+ attribute \src "libresoc.v:153122.3-153123.57"
+ wire $0\mul_op__is_32bit$11[0:0]$8090
+ attribute \src "libresoc.v:152691.7-152691.35"
+ wire $0\mul_op__is_32bit$11[0:0]$8174
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__is_signed$12$next[0:0]$8112
+ attribute \src "libresoc.v:153124.3-153125.59"
+ wire $0\mul_op__is_signed$12[0:0]$8092
+ attribute \src "libresoc.v:152700.7-152700.36"
+ wire $0\mul_op__is_signed$12[0:0]$8176
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__oe__oe$8$next[0:0]$8113
+ attribute \src "libresoc.v:153116.3-153117.51"
+ wire $0\mul_op__oe__oe$8[0:0]$8084
+ attribute \src "libresoc.v:152711.7-152711.32"
+ wire $0\mul_op__oe__oe$8[0:0]$8178
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__oe__ok$9$next[0:0]$8114
+ attribute \src "libresoc.v:153118.3-153119.51"
+ wire $0\mul_op__oe__ok$9[0:0]$8086
+ attribute \src "libresoc.v:152720.7-152720.32"
+ wire $0\mul_op__oe__ok$9[0:0]$8180
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__rc__ok$7$next[0:0]$8115
+ attribute \src "libresoc.v:153114.3-153115.51"
+ wire $0\mul_op__rc__ok$7[0:0]$8082
+ attribute \src "libresoc.v:152729.7-152729.32"
+ wire $0\mul_op__rc__ok$7[0:0]$8182
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__rc__rc$6$next[0:0]$8116
+ attribute \src "libresoc.v:153112.3-153113.51"
+ wire $0\mul_op__rc__rc$6[0:0]$8080
+ attribute \src "libresoc.v:152736.7-152736.32"
+ wire $0\mul_op__rc__rc$6[0:0]$8184
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $0\mul_op__write_cr0$10$next[0:0]$8117
+ attribute \src "libresoc.v:153120.3-153121.59"
+ wire $0\mul_op__write_cr0$10[0:0]$8088
+ attribute \src "libresoc.v:152745.7-152745.36"
+ wire $0\mul_op__write_cr0$10[0:0]$8186
+ attribute \src "libresoc.v:153236.3-153248.6"
+ wire width 2 $0\muxid$1$next[1:0]$8103
+ attribute \src "libresoc.v:153128.3-153129.33"
+ wire width 2 $0\muxid$1[1:0]$8096
+ attribute \src "libresoc.v:152754.13-152754.29"
+ wire width 2 $0\muxid$1[1:0]$8188
+ attribute \src "libresoc.v:153285.3-153303.6"
+ wire width 64 $0\o$14$next[63:0]$8138
+ attribute \src "libresoc.v:153100.3-153101.27"
+ wire width 64 $0\o$14[63:0]$8069
+ attribute \src "libresoc.v:152775.14-152775.43"
+ wire width 64 $0\o$14[63:0]$8190
+ attribute \src "libresoc.v:153285.3-153303.6"
+ wire $0\o_ok$next[0:0]$8137
+ attribute \src "libresoc.v:153102.3-153103.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:155088.3-155105.6"
- wire $0\r_busy$next[0:0]$8173
- attribute \src "libresoc.v:155000.3-155001.29"
+ attribute \src "libresoc.v:153218.3-153235.6"
+ wire $0\r_busy$next[0:0]$8099
+ attribute \src "libresoc.v:153130.3-153131.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:155193.3-155211.6"
- wire width 2 $0\xer_ov$next[1:0]$8223
- attribute \src "libresoc.v:154962.3-154963.29"
+ attribute \src "libresoc.v:153323.3-153341.6"
+ wire width 2 $0\xer_ov$next[1:0]$8149
+ attribute \src "libresoc.v:153092.3-153093.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:155193.3-155211.6"
- wire $0\xer_ov_ok$next[0:0]$8224
- attribute \src "libresoc.v:154964.3-154965.35"
+ attribute \src "libresoc.v:153323.3-153341.6"
+ wire $0\xer_ov_ok$next[0:0]$8150
+ attribute \src "libresoc.v:153094.3-153095.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:155212.3-155230.6"
- wire $0\xer_so$15$next[0:0]$8230
- attribute \src "libresoc.v:154958.3-154959.37"
- wire $0\xer_so$15[0:0]$8136
- attribute \src "libresoc.v:154943.7-154943.25"
- wire $0\xer_so$15[0:0]$8270
- attribute \src "libresoc.v:155212.3-155230.6"
- wire $0\xer_so_ok$next[0:0]$8229
- attribute \src "libresoc.v:154960.3-154961.35"
+ attribute \src "libresoc.v:153342.3-153360.6"
+ wire $0\xer_so$15$next[0:0]$8156
+ attribute \src "libresoc.v:153088.3-153089.37"
+ wire $0\xer_so$15[0:0]$8062
+ attribute \src "libresoc.v:153073.7-153073.25"
+ wire $0\xer_so$15[0:0]$8196
+ attribute \src "libresoc.v:153342.3-153360.6"
+ wire $0\xer_so_ok$next[0:0]$8155
+ attribute \src "libresoc.v:153090.3-153091.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:155174.3-155192.6"
- wire width 4 $1\cr_a$next[3:0]$8219
- attribute \src "libresoc.v:153984.13-153984.24"
+ attribute \src "libresoc.v:153304.3-153322.6"
+ wire width 4 $1\cr_a$next[3:0]$8145
+ attribute \src "libresoc.v:152114.13-152114.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:155174.3-155192.6"
- wire $1\cr_a_ok$next[0:0]$8220
- attribute \src "libresoc.v:153993.7-153993.21"
+ attribute \src "libresoc.v:153304.3-153322.6"
+ wire $1\cr_a_ok$next[0:0]$8146
+ attribute \src "libresoc.v:152123.7-152123.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8192
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8193
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__imm_data__ok$5$next[0:0]$8194
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 32 $1\mul_op__insn$13$next[31:0]$8195
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 7 $1\mul_op__insn_type$2$next[6:0]$8196
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__is_32bit$11$next[0:0]$8197
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__is_signed$12$next[0:0]$8198
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__oe__oe$8$next[0:0]$8199
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__oe__ok$9$next[0:0]$8200
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__rc__ok$7$next[0:0]$8201
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__rc__rc$6$next[0:0]$8202
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $1\mul_op__write_cr0$10$next[0:0]$8203
- attribute \src "libresoc.v:155106.3-155118.6"
- wire width 2 $1\muxid$1$next[1:0]$8178
- attribute \src "libresoc.v:155155.3-155173.6"
- wire width 64 $1\o$14$next[63:0]$8214
- attribute \src "libresoc.v:155155.3-155173.6"
- wire $1\o_ok$next[0:0]$8213
- attribute \src "libresoc.v:154652.7-154652.18"
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8118
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8119
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__imm_data__ok$5$next[0:0]$8120
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 32 $1\mul_op__insn$13$next[31:0]$8121
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 7 $1\mul_op__insn_type$2$next[6:0]$8122
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__is_32bit$11$next[0:0]$8123
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__is_signed$12$next[0:0]$8124
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__oe__oe$8$next[0:0]$8125
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__oe__ok$9$next[0:0]$8126
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__rc__ok$7$next[0:0]$8127
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__rc__rc$6$next[0:0]$8128
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $1\mul_op__write_cr0$10$next[0:0]$8129
+ attribute \src "libresoc.v:153236.3-153248.6"
+ wire width 2 $1\muxid$1$next[1:0]$8104
+ attribute \src "libresoc.v:153285.3-153303.6"
+ wire width 64 $1\o$14$next[63:0]$8140
+ attribute \src "libresoc.v:153285.3-153303.6"
+ wire $1\o_ok$next[0:0]$8139
+ attribute \src "libresoc.v:152782.7-152782.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:155088.3-155105.6"
- wire $1\r_busy$next[0:0]$8174
- attribute \src "libresoc.v:154920.7-154920.20"
+ attribute \src "libresoc.v:153218.3-153235.6"
+ wire $1\r_busy$next[0:0]$8100
+ attribute \src "libresoc.v:153050.7-153050.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:155193.3-155211.6"
- wire width 2 $1\xer_ov$next[1:0]$8225
- attribute \src "libresoc.v:154925.13-154925.26"
+ attribute \src "libresoc.v:153323.3-153341.6"
+ wire width 2 $1\xer_ov$next[1:0]$8151
+ attribute \src "libresoc.v:153055.13-153055.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:155193.3-155211.6"
- wire $1\xer_ov_ok$next[0:0]$8226
- attribute \src "libresoc.v:154932.7-154932.23"
+ attribute \src "libresoc.v:153323.3-153341.6"
+ wire $1\xer_ov_ok$next[0:0]$8152
+ attribute \src "libresoc.v:153062.7-153062.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:155212.3-155230.6"
- wire $1\xer_so$15$next[0:0]$8232
- attribute \src "libresoc.v:155212.3-155230.6"
- wire $1\xer_so_ok$next[0:0]$8231
- attribute \src "libresoc.v:154950.7-154950.23"
+ attribute \src "libresoc.v:153342.3-153360.6"
+ wire $1\xer_so$15$next[0:0]$8158
+ attribute \src "libresoc.v:153342.3-153360.6"
+ wire $1\xer_so_ok$next[0:0]$8157
+ attribute \src "libresoc.v:153080.7-153080.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:155174.3-155192.6"
- wire $2\cr_a_ok$next[0:0]$8221
- attribute \src "libresoc.v:155119.3-155154.6"
- wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8204
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $2\mul_op__imm_data__ok$5$next[0:0]$8205
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $2\mul_op__oe__oe$8$next[0:0]$8206
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $2\mul_op__oe__ok$9$next[0:0]$8207
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $2\mul_op__rc__ok$7$next[0:0]$8208
- attribute \src "libresoc.v:155119.3-155154.6"
- wire $2\mul_op__rc__rc$6$next[0:0]$8209
- attribute \src "libresoc.v:155155.3-155173.6"
- wire $2\o_ok$next[0:0]$8215
- attribute \src "libresoc.v:155088.3-155105.6"
- wire $2\r_busy$next[0:0]$8175
- attribute \src "libresoc.v:155193.3-155211.6"
- wire $2\xer_ov_ok$next[0:0]$8227
- attribute \src "libresoc.v:155212.3-155230.6"
- wire $2\xer_so_ok$next[0:0]$8233
- attribute \src "libresoc.v:154957.18-154957.118"
- wire $and$libresoc.v:154957$8134_Y
+ attribute \src "libresoc.v:153304.3-153322.6"
+ wire $2\cr_a_ok$next[0:0]$8147
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8130
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $2\mul_op__imm_data__ok$5$next[0:0]$8131
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $2\mul_op__oe__oe$8$next[0:0]$8132
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $2\mul_op__oe__ok$9$next[0:0]$8133
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $2\mul_op__rc__ok$7$next[0:0]$8134
+ attribute \src "libresoc.v:153249.3-153284.6"
+ wire $2\mul_op__rc__rc$6$next[0:0]$8135
+ attribute \src "libresoc.v:153285.3-153303.6"
+ wire $2\o_ok$next[0:0]$8141
+ attribute \src "libresoc.v:153218.3-153235.6"
+ wire $2\r_busy$next[0:0]$8101
+ attribute \src "libresoc.v:153323.3-153341.6"
+ wire $2\xer_ov_ok$next[0:0]$8153
+ attribute \src "libresoc.v:153342.3-153360.6"
+ wire $2\xer_so_ok$next[0:0]$8159
+ attribute \src "libresoc.v:153087.18-153087.118"
+ wire $and$libresoc.v:153087$8060_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 44 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 38 \cr_a
wire \cr_a_ok$74
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:153975.7-153975.15"
+ attribute \src "libresoc.v:152105.7-152105.15"
wire \initial
attribute \enum_base_type "Function"
attribute \enum_value_0000000000000 "NONE"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:154957$8134
+ cell $and $and$libresoc.v:153087$8060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$55
connect \B \p_ready_o
- connect \Y $and$libresoc.v:154957$8134_Y
+ connect \Y $and$libresoc.v:153087$8060_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155002.8-155038.4"
+ attribute \src "libresoc.v:153132.8-153168.4"
cell \mul3 \mul3
connect \mul_op__fn_unit \mul3_mul_op__fn_unit
connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18
connect \xer_so_ok \mul3_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155039.10-155042.4"
+ attribute \src "libresoc.v:153169.10-153172.4"
cell \n$99 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155043.16-155083.4"
+ attribute \src "libresoc.v:153173.16-153213.4"
cell \output$100 \output
connect \cr_a \output_cr_a
connect \cr_a$16 \output_cr_a$46
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:155084.10-155087.4"
+ attribute \src "libresoc.v:153214.10-153217.4"
cell \p$98 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:153975.7-153975.20"
- process $proc$libresoc.v:153975$8234
+ attribute \src "libresoc.v:152105.7-152105.20"
+ process $proc$libresoc.v:152105$8160
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:153984.13-153984.24"
- process $proc$libresoc.v:153984$8235
+ attribute \src "libresoc.v:152114.13-152114.24"
+ process $proc$libresoc.v:152114$8161
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:153993.7-153993.21"
- process $proc$libresoc.v:153993$8236
+ attribute \src "libresoc.v:152123.7-152123.21"
+ process $proc$libresoc.v:152123$8162
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:154280.14-154280.44"
- process $proc$libresoc.v:154280$8237
+ attribute \src "libresoc.v:152410.14-152410.44"
+ process $proc$libresoc.v:152410$8163
assign { } { }
- assign $0\mul_op__fn_unit$3[12:0]$8238 13'0000000000000
+ assign $0\mul_op__fn_unit$3[12:0]$8164 13'0000000000000
sync always
sync init
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8238
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8164
end
- attribute \src "libresoc.v:154303.14-154303.63"
- process $proc$libresoc.v:154303$8239
+ attribute \src "libresoc.v:152433.14-152433.63"
+ process $proc$libresoc.v:152433$8165
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8240 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\mul_op__imm_data__data$4[63:0]$8166 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8240
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8166
end
- attribute \src "libresoc.v:154312.7-154312.38"
- process $proc$libresoc.v:154312$8241
+ attribute \src "libresoc.v:152442.7-152442.38"
+ process $proc$libresoc.v:152442$8167
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8242 1'0
+ assign $0\mul_op__imm_data__ok$5[0:0]$8168 1'0
sync always
sync init
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8242
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8168
end
- attribute \src "libresoc.v:154321.14-154321.39"
- process $proc$libresoc.v:154321$8243
+ attribute \src "libresoc.v:152451.14-152451.39"
+ process $proc$libresoc.v:152451$8169
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8244 0
+ assign $0\mul_op__insn$13[31:0]$8170 0
sync always
sync init
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8244
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8170
end
- attribute \src "libresoc.v:154478.13-154478.42"
- process $proc$libresoc.v:154478$8245
+ attribute \src "libresoc.v:152608.13-152608.42"
+ process $proc$libresoc.v:152608$8171
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8246 7'0000000
+ assign $0\mul_op__insn_type$2[6:0]$8172 7'0000000
sync always
sync init
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8246
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8172
end
- attribute \src "libresoc.v:154561.7-154561.35"
- process $proc$libresoc.v:154561$8247
+ attribute \src "libresoc.v:152691.7-152691.35"
+ process $proc$libresoc.v:152691$8173
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8248 1'0
+ assign $0\mul_op__is_32bit$11[0:0]$8174 1'0
sync always
sync init
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8248
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8174
end
- attribute \src "libresoc.v:154570.7-154570.36"
- process $proc$libresoc.v:154570$8249
+ attribute \src "libresoc.v:152700.7-152700.36"
+ process $proc$libresoc.v:152700$8175
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8250 1'0
+ assign $0\mul_op__is_signed$12[0:0]$8176 1'0
sync always
sync init
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8250
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8176
end
- attribute \src "libresoc.v:154581.7-154581.32"
- process $proc$libresoc.v:154581$8251
+ attribute \src "libresoc.v:152711.7-152711.32"
+ process $proc$libresoc.v:152711$8177
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8252 1'0
+ assign $0\mul_op__oe__oe$8[0:0]$8178 1'0
sync always
sync init
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8252
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8178
end
- attribute \src "libresoc.v:154590.7-154590.32"
- process $proc$libresoc.v:154590$8253
+ attribute \src "libresoc.v:152720.7-152720.32"
+ process $proc$libresoc.v:152720$8179
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8254 1'0
+ assign $0\mul_op__oe__ok$9[0:0]$8180 1'0
sync always
sync init
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8254
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8180
end
- attribute \src "libresoc.v:154599.7-154599.32"
- process $proc$libresoc.v:154599$8255
+ attribute \src "libresoc.v:152729.7-152729.32"
+ process $proc$libresoc.v:152729$8181
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8256 1'0
+ assign $0\mul_op__rc__ok$7[0:0]$8182 1'0
sync always
sync init
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8256
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8182
end
- attribute \src "libresoc.v:154606.7-154606.32"
- process $proc$libresoc.v:154606$8257
+ attribute \src "libresoc.v:152736.7-152736.32"
+ process $proc$libresoc.v:152736$8183
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8258 1'0
+ assign $0\mul_op__rc__rc$6[0:0]$8184 1'0
sync always
sync init
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8258
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8184
end
- attribute \src "libresoc.v:154615.7-154615.36"
- process $proc$libresoc.v:154615$8259
+ attribute \src "libresoc.v:152745.7-152745.36"
+ process $proc$libresoc.v:152745$8185
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8260 1'0
+ assign $0\mul_op__write_cr0$10[0:0]$8186 1'0
sync always
sync init
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8260
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8186
end
- attribute \src "libresoc.v:154624.13-154624.29"
- process $proc$libresoc.v:154624$8261
+ attribute \src "libresoc.v:152754.13-152754.29"
+ process $proc$libresoc.v:152754$8187
assign { } { }
- assign $0\muxid$1[1:0]$8262 2'00
+ assign $0\muxid$1[1:0]$8188 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8262
+ update \muxid$1 $0\muxid$1[1:0]$8188
end
- attribute \src "libresoc.v:154645.14-154645.43"
- process $proc$libresoc.v:154645$8263
+ attribute \src "libresoc.v:152775.14-152775.43"
+ process $proc$libresoc.v:152775$8189
assign { } { }
- assign $0\o$14[63:0]$8264 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$14[63:0]$8190 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$14 $0\o$14[63:0]$8264
+ update \o$14 $0\o$14[63:0]$8190
end
- attribute \src "libresoc.v:154652.7-154652.18"
- process $proc$libresoc.v:154652$8265
+ attribute \src "libresoc.v:152782.7-152782.18"
+ process $proc$libresoc.v:152782$8191
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:154920.7-154920.20"
- process $proc$libresoc.v:154920$8266
+ attribute \src "libresoc.v:153050.7-153050.20"
+ process $proc$libresoc.v:153050$8192
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:154925.13-154925.26"
- process $proc$libresoc.v:154925$8267
+ attribute \src "libresoc.v:153055.13-153055.26"
+ process $proc$libresoc.v:153055$8193
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:154932.7-154932.23"
- process $proc$libresoc.v:154932$8268
+ attribute \src "libresoc.v:153062.7-153062.23"
+ process $proc$libresoc.v:153062$8194
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:154943.7-154943.25"
- process $proc$libresoc.v:154943$8269
+ attribute \src "libresoc.v:153073.7-153073.25"
+ process $proc$libresoc.v:153073$8195
assign { } { }
- assign $0\xer_so$15[0:0]$8270 1'0
+ assign $0\xer_so$15[0:0]$8196 1'0
sync always
sync init
- update \xer_so$15 $0\xer_so$15[0:0]$8270
+ update \xer_so$15 $0\xer_so$15[0:0]$8196
end
- attribute \src "libresoc.v:154950.7-154950.23"
- process $proc$libresoc.v:154950$8271
+ attribute \src "libresoc.v:153080.7-153080.23"
+ process $proc$libresoc.v:153080$8197
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:154958.3-154959.37"
- process $proc$libresoc.v:154958$8135
+ attribute \src "libresoc.v:153088.3-153089.37"
+ process $proc$libresoc.v:153088$8061
assign { } { }
- assign $0\xer_so$15[0:0]$8136 \xer_so$15$next
+ assign $0\xer_so$15[0:0]$8062 \xer_so$15$next
sync posedge \coresync_clk
- update \xer_so$15 $0\xer_so$15[0:0]$8136
+ update \xer_so$15 $0\xer_so$15[0:0]$8062
end
- attribute \src "libresoc.v:154960.3-154961.35"
- process $proc$libresoc.v:154960$8137
+ attribute \src "libresoc.v:153090.3-153091.35"
+ process $proc$libresoc.v:153090$8063
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:154962.3-154963.29"
- process $proc$libresoc.v:154962$8138
+ attribute \src "libresoc.v:153092.3-153093.29"
+ process $proc$libresoc.v:153092$8064
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:154964.3-154965.35"
- process $proc$libresoc.v:154964$8139
+ attribute \src "libresoc.v:153094.3-153095.35"
+ process $proc$libresoc.v:153094$8065
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:154966.3-154967.25"
- process $proc$libresoc.v:154966$8140
+ attribute \src "libresoc.v:153096.3-153097.25"
+ process $proc$libresoc.v:153096$8066
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:154968.3-154969.31"
- process $proc$libresoc.v:154968$8141
+ attribute \src "libresoc.v:153098.3-153099.31"
+ process $proc$libresoc.v:153098$8067
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:154970.3-154971.27"
- process $proc$libresoc.v:154970$8142
+ attribute \src "libresoc.v:153100.3-153101.27"
+ process $proc$libresoc.v:153100$8068
assign { } { }
- assign $0\o$14[63:0]$8143 \o$14$next
+ assign $0\o$14[63:0]$8069 \o$14$next
sync posedge \coresync_clk
- update \o$14 $0\o$14[63:0]$8143
+ update \o$14 $0\o$14[63:0]$8069
end
- attribute \src "libresoc.v:154972.3-154973.25"
- process $proc$libresoc.v:154972$8144
+ attribute \src "libresoc.v:153102.3-153103.25"
+ process $proc$libresoc.v:153102$8070
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:154974.3-154975.57"
- process $proc$libresoc.v:154974$8145
+ attribute \src "libresoc.v:153104.3-153105.57"
+ process $proc$libresoc.v:153104$8071
assign { } { }
- assign $0\mul_op__insn_type$2[6:0]$8146 \mul_op__insn_type$2$next
+ assign $0\mul_op__insn_type$2[6:0]$8072 \mul_op__insn_type$2$next
sync posedge \coresync_clk
- update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8146
+ update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8072
end
- attribute \src "libresoc.v:154976.3-154977.53"
- process $proc$libresoc.v:154976$8147
+ attribute \src "libresoc.v:153106.3-153107.53"
+ process $proc$libresoc.v:153106$8073
assign { } { }
- assign $0\mul_op__fn_unit$3[12:0]$8148 \mul_op__fn_unit$3$next
+ assign $0\mul_op__fn_unit$3[12:0]$8074 \mul_op__fn_unit$3$next
sync posedge \coresync_clk
- update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8148
+ update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8074
end
- attribute \src "libresoc.v:154978.3-154979.67"
- process $proc$libresoc.v:154978$8149
+ attribute \src "libresoc.v:153108.3-153109.67"
+ process $proc$libresoc.v:153108$8075
assign { } { }
- assign $0\mul_op__imm_data__data$4[63:0]$8150 \mul_op__imm_data__data$4$next
+ assign $0\mul_op__imm_data__data$4[63:0]$8076 \mul_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8150
+ update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8076
end
- attribute \src "libresoc.v:154980.3-154981.63"
- process $proc$libresoc.v:154980$8151
+ attribute \src "libresoc.v:153110.3-153111.63"
+ process $proc$libresoc.v:153110$8077
assign { } { }
- assign $0\mul_op__imm_data__ok$5[0:0]$8152 \mul_op__imm_data__ok$5$next
+ assign $0\mul_op__imm_data__ok$5[0:0]$8078 \mul_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8152
+ update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8078
end
- attribute \src "libresoc.v:154982.3-154983.51"
- process $proc$libresoc.v:154982$8153
+ attribute \src "libresoc.v:153112.3-153113.51"
+ process $proc$libresoc.v:153112$8079
assign { } { }
- assign $0\mul_op__rc__rc$6[0:0]$8154 \mul_op__rc__rc$6$next
+ assign $0\mul_op__rc__rc$6[0:0]$8080 \mul_op__rc__rc$6$next
sync posedge \coresync_clk
- update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8154
+ update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8080
end
- attribute \src "libresoc.v:154984.3-154985.51"
- process $proc$libresoc.v:154984$8155
+ attribute \src "libresoc.v:153114.3-153115.51"
+ process $proc$libresoc.v:153114$8081
assign { } { }
- assign $0\mul_op__rc__ok$7[0:0]$8156 \mul_op__rc__ok$7$next
+ assign $0\mul_op__rc__ok$7[0:0]$8082 \mul_op__rc__ok$7$next
sync posedge \coresync_clk
- update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8156
+ update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8082
end
- attribute \src "libresoc.v:154986.3-154987.51"
- process $proc$libresoc.v:154986$8157
+ attribute \src "libresoc.v:153116.3-153117.51"
+ process $proc$libresoc.v:153116$8083
assign { } { }
- assign $0\mul_op__oe__oe$8[0:0]$8158 \mul_op__oe__oe$8$next
+ assign $0\mul_op__oe__oe$8[0:0]$8084 \mul_op__oe__oe$8$next
sync posedge \coresync_clk
- update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8158
+ update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8084
end
- attribute \src "libresoc.v:154988.3-154989.51"
- process $proc$libresoc.v:154988$8159
+ attribute \src "libresoc.v:153118.3-153119.51"
+ process $proc$libresoc.v:153118$8085
assign { } { }
- assign $0\mul_op__oe__ok$9[0:0]$8160 \mul_op__oe__ok$9$next
+ assign $0\mul_op__oe__ok$9[0:0]$8086 \mul_op__oe__ok$9$next
sync posedge \coresync_clk
- update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8160
+ update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8086
end
- attribute \src "libresoc.v:154990.3-154991.59"
- process $proc$libresoc.v:154990$8161
+ attribute \src "libresoc.v:153120.3-153121.59"
+ process $proc$libresoc.v:153120$8087
assign { } { }
- assign $0\mul_op__write_cr0$10[0:0]$8162 \mul_op__write_cr0$10$next
+ assign $0\mul_op__write_cr0$10[0:0]$8088 \mul_op__write_cr0$10$next
sync posedge \coresync_clk
- update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8162
+ update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8088
end
- attribute \src "libresoc.v:154992.3-154993.57"
- process $proc$libresoc.v:154992$8163
+ attribute \src "libresoc.v:153122.3-153123.57"
+ process $proc$libresoc.v:153122$8089
assign { } { }
- assign $0\mul_op__is_32bit$11[0:0]$8164 \mul_op__is_32bit$11$next
+ assign $0\mul_op__is_32bit$11[0:0]$8090 \mul_op__is_32bit$11$next
sync posedge \coresync_clk
- update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8164
+ update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8090
end
- attribute \src "libresoc.v:154994.3-154995.59"
- process $proc$libresoc.v:154994$8165
+ attribute \src "libresoc.v:153124.3-153125.59"
+ process $proc$libresoc.v:153124$8091
assign { } { }
- assign $0\mul_op__is_signed$12[0:0]$8166 \mul_op__is_signed$12$next
+ assign $0\mul_op__is_signed$12[0:0]$8092 \mul_op__is_signed$12$next
sync posedge \coresync_clk
- update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8166
+ update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8092
end
- attribute \src "libresoc.v:154996.3-154997.49"
- process $proc$libresoc.v:154996$8167
+ attribute \src "libresoc.v:153126.3-153127.49"
+ process $proc$libresoc.v:153126$8093
assign { } { }
- assign $0\mul_op__insn$13[31:0]$8168 \mul_op__insn$13$next
+ assign $0\mul_op__insn$13[31:0]$8094 \mul_op__insn$13$next
sync posedge \coresync_clk
- update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8168
+ update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8094
end
- attribute \src "libresoc.v:154998.3-154999.33"
- process $proc$libresoc.v:154998$8169
+ attribute \src "libresoc.v:153128.3-153129.33"
+ process $proc$libresoc.v:153128$8095
assign { } { }
- assign $0\muxid$1[1:0]$8170 \muxid$1$next
+ assign $0\muxid$1[1:0]$8096 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8170
+ update \muxid$1 $0\muxid$1[1:0]$8096
end
- attribute \src "libresoc.v:155000.3-155001.29"
- process $proc$libresoc.v:155000$8171
+ attribute \src "libresoc.v:153130.3-153131.29"
+ process $proc$libresoc.v:153130$8097
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:155088.3-155105.6"
- process $proc$libresoc.v:155088$8172
+ attribute \src "libresoc.v:153218.3-153235.6"
+ process $proc$libresoc.v:153218$8098
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8173 $2\r_busy$next[0:0]$8175
- attribute \src "libresoc.v:155089.5-155089.29"
+ assign $0\r_busy$next[0:0]$8099 $2\r_busy$next[0:0]$8101
+ attribute \src "libresoc.v:153219.5-153219.29"
switch \initial
- attribute \src "libresoc.v:155089.9-155089.17"
+ attribute \src "libresoc.v:153219.9-153219.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8174 1'1
+ assign $1\r_busy$next[0:0]$8100 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8174 1'0
+ assign $1\r_busy$next[0:0]$8100 1'0
case
- assign $1\r_busy$next[0:0]$8174 \r_busy
+ assign $1\r_busy$next[0:0]$8100 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8175 1'0
+ assign $2\r_busy$next[0:0]$8101 1'0
case
- assign $2\r_busy$next[0:0]$8175 $1\r_busy$next[0:0]$8174
+ assign $2\r_busy$next[0:0]$8101 $1\r_busy$next[0:0]$8100
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8173
+ update \r_busy$next $0\r_busy$next[0:0]$8099
end
- attribute \src "libresoc.v:155106.3-155118.6"
- process $proc$libresoc.v:155106$8176
+ attribute \src "libresoc.v:153236.3-153248.6"
+ process $proc$libresoc.v:153236$8102
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8177 $1\muxid$1$next[1:0]$8178
- attribute \src "libresoc.v:155107.5-155107.29"
+ assign $0\muxid$1$next[1:0]$8103 $1\muxid$1$next[1:0]$8104
+ attribute \src "libresoc.v:153237.5-153237.29"
switch \initial
- attribute \src "libresoc.v:155107.9-155107.17"
+ attribute \src "libresoc.v:153237.9-153237.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8178 \muxid$58
+ assign $1\muxid$1$next[1:0]$8104 \muxid$58
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8178 \muxid$58
+ assign $1\muxid$1$next[1:0]$8104 \muxid$58
case
- assign $1\muxid$1$next[1:0]$8178 \muxid$1
+ assign $1\muxid$1$next[1:0]$8104 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8177
+ update \muxid$1$next $0\muxid$1$next[1:0]$8103
end
- attribute \src "libresoc.v:155119.3-155154.6"
- process $proc$libresoc.v:155119$8179
+ attribute \src "libresoc.v:153249.3-153284.6"
+ process $proc$libresoc.v:153249$8105
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__fn_unit$3$next[12:0]$8180 $1\mul_op__fn_unit$3$next[12:0]$8192
+ assign $0\mul_op__fn_unit$3$next[12:0]$8106 $1\mul_op__fn_unit$3$next[12:0]$8118
assign { } { }
assign { } { }
- assign $0\mul_op__insn$13$next[31:0]$8183 $1\mul_op__insn$13$next[31:0]$8195
- assign $0\mul_op__insn_type$2$next[6:0]$8184 $1\mul_op__insn_type$2$next[6:0]$8196
- assign $0\mul_op__is_32bit$11$next[0:0]$8185 $1\mul_op__is_32bit$11$next[0:0]$8197
- assign $0\mul_op__is_signed$12$next[0:0]$8186 $1\mul_op__is_signed$12$next[0:0]$8198
+ assign $0\mul_op__insn$13$next[31:0]$8109 $1\mul_op__insn$13$next[31:0]$8121
+ assign $0\mul_op__insn_type$2$next[6:0]$8110 $1\mul_op__insn_type$2$next[6:0]$8122
+ assign $0\mul_op__is_32bit$11$next[0:0]$8111 $1\mul_op__is_32bit$11$next[0:0]$8123
+ assign $0\mul_op__is_signed$12$next[0:0]$8112 $1\mul_op__is_signed$12$next[0:0]$8124
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mul_op__write_cr0$10$next[0:0]$8191 $1\mul_op__write_cr0$10$next[0:0]$8203
- assign $0\mul_op__imm_data__data$4$next[63:0]$8181 $2\mul_op__imm_data__data$4$next[63:0]$8204
- assign $0\mul_op__imm_data__ok$5$next[0:0]$8182 $2\mul_op__imm_data__ok$5$next[0:0]$8205
- assign $0\mul_op__oe__oe$8$next[0:0]$8187 $2\mul_op__oe__oe$8$next[0:0]$8206
- assign $0\mul_op__oe__ok$9$next[0:0]$8188 $2\mul_op__oe__ok$9$next[0:0]$8207
- assign $0\mul_op__rc__ok$7$next[0:0]$8189 $2\mul_op__rc__ok$7$next[0:0]$8208
- assign $0\mul_op__rc__rc$6$next[0:0]$8190 $2\mul_op__rc__rc$6$next[0:0]$8209
- attribute \src "libresoc.v:155120.5-155120.29"
+ assign $0\mul_op__write_cr0$10$next[0:0]$8117 $1\mul_op__write_cr0$10$next[0:0]$8129
+ assign $0\mul_op__imm_data__data$4$next[63:0]$8107 $2\mul_op__imm_data__data$4$next[63:0]$8130
+ assign $0\mul_op__imm_data__ok$5$next[0:0]$8108 $2\mul_op__imm_data__ok$5$next[0:0]$8131
+ assign $0\mul_op__oe__oe$8$next[0:0]$8113 $2\mul_op__oe__oe$8$next[0:0]$8132
+ assign $0\mul_op__oe__ok$9$next[0:0]$8114 $2\mul_op__oe__ok$9$next[0:0]$8133
+ assign $0\mul_op__rc__ok$7$next[0:0]$8115 $2\mul_op__rc__ok$7$next[0:0]$8134
+ assign $0\mul_op__rc__rc$6$next[0:0]$8116 $2\mul_op__rc__rc$6$next[0:0]$8135
+ attribute \src "libresoc.v:153250.5-153250.29"
switch \initial
- attribute \src "libresoc.v:155120.9-155120.17"
+ attribute \src "libresoc.v:153250.9-153250.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8195 $1\mul_op__is_signed$12$next[0:0]$8198 $1\mul_op__is_32bit$11$next[0:0]$8197 $1\mul_op__write_cr0$10$next[0:0]$8203 $1\mul_op__oe__ok$9$next[0:0]$8200 $1\mul_op__oe__oe$8$next[0:0]$8199 $1\mul_op__rc__ok$7$next[0:0]$8201 $1\mul_op__rc__rc$6$next[0:0]$8202 $1\mul_op__imm_data__ok$5$next[0:0]$8194 $1\mul_op__imm_data__data$4$next[63:0]$8193 $1\mul_op__fn_unit$3$next[12:0]$8192 $1\mul_op__insn_type$2$next[6:0]$8196 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
+ assign { $1\mul_op__insn$13$next[31:0]$8121 $1\mul_op__is_signed$12$next[0:0]$8124 $1\mul_op__is_32bit$11$next[0:0]$8123 $1\mul_op__write_cr0$10$next[0:0]$8129 $1\mul_op__oe__ok$9$next[0:0]$8126 $1\mul_op__oe__oe$8$next[0:0]$8125 $1\mul_op__rc__ok$7$next[0:0]$8127 $1\mul_op__rc__rc$6$next[0:0]$8128 $1\mul_op__imm_data__ok$5$next[0:0]$8120 $1\mul_op__imm_data__data$4$next[63:0]$8119 $1\mul_op__fn_unit$3$next[12:0]$8118 $1\mul_op__insn_type$2$next[6:0]$8122 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\mul_op__insn$13$next[31:0]$8195 $1\mul_op__is_signed$12$next[0:0]$8198 $1\mul_op__is_32bit$11$next[0:0]$8197 $1\mul_op__write_cr0$10$next[0:0]$8203 $1\mul_op__oe__ok$9$next[0:0]$8200 $1\mul_op__oe__oe$8$next[0:0]$8199 $1\mul_op__rc__ok$7$next[0:0]$8201 $1\mul_op__rc__rc$6$next[0:0]$8202 $1\mul_op__imm_data__ok$5$next[0:0]$8194 $1\mul_op__imm_data__data$4$next[63:0]$8193 $1\mul_op__fn_unit$3$next[12:0]$8192 $1\mul_op__insn_type$2$next[6:0]$8196 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
+ assign { $1\mul_op__insn$13$next[31:0]$8121 $1\mul_op__is_signed$12$next[0:0]$8124 $1\mul_op__is_32bit$11$next[0:0]$8123 $1\mul_op__write_cr0$10$next[0:0]$8129 $1\mul_op__oe__ok$9$next[0:0]$8126 $1\mul_op__oe__oe$8$next[0:0]$8125 $1\mul_op__rc__ok$7$next[0:0]$8127 $1\mul_op__rc__rc$6$next[0:0]$8128 $1\mul_op__imm_data__ok$5$next[0:0]$8120 $1\mul_op__imm_data__data$4$next[63:0]$8119 $1\mul_op__fn_unit$3$next[12:0]$8118 $1\mul_op__insn_type$2$next[6:0]$8122 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 }
case
- assign $1\mul_op__fn_unit$3$next[12:0]$8192 \mul_op__fn_unit$3
- assign $1\mul_op__imm_data__data$4$next[63:0]$8193 \mul_op__imm_data__data$4
- assign $1\mul_op__imm_data__ok$5$next[0:0]$8194 \mul_op__imm_data__ok$5
- assign $1\mul_op__insn$13$next[31:0]$8195 \mul_op__insn$13
- assign $1\mul_op__insn_type$2$next[6:0]$8196 \mul_op__insn_type$2
- assign $1\mul_op__is_32bit$11$next[0:0]$8197 \mul_op__is_32bit$11
- assign $1\mul_op__is_signed$12$next[0:0]$8198 \mul_op__is_signed$12
- assign $1\mul_op__oe__oe$8$next[0:0]$8199 \mul_op__oe__oe$8
- assign $1\mul_op__oe__ok$9$next[0:0]$8200 \mul_op__oe__ok$9
- assign $1\mul_op__rc__ok$7$next[0:0]$8201 \mul_op__rc__ok$7
- assign $1\mul_op__rc__rc$6$next[0:0]$8202 \mul_op__rc__rc$6
- assign $1\mul_op__write_cr0$10$next[0:0]$8203 \mul_op__write_cr0$10
+ assign $1\mul_op__fn_unit$3$next[12:0]$8118 \mul_op__fn_unit$3
+ assign $1\mul_op__imm_data__data$4$next[63:0]$8119 \mul_op__imm_data__data$4
+ assign $1\mul_op__imm_data__ok$5$next[0:0]$8120 \mul_op__imm_data__ok$5
+ assign $1\mul_op__insn$13$next[31:0]$8121 \mul_op__insn$13
+ assign $1\mul_op__insn_type$2$next[6:0]$8122 \mul_op__insn_type$2
+ assign $1\mul_op__is_32bit$11$next[0:0]$8123 \mul_op__is_32bit$11
+ assign $1\mul_op__is_signed$12$next[0:0]$8124 \mul_op__is_signed$12
+ assign $1\mul_op__oe__oe$8$next[0:0]$8125 \mul_op__oe__oe$8
+ assign $1\mul_op__oe__ok$9$next[0:0]$8126 \mul_op__oe__ok$9
+ assign $1\mul_op__rc__ok$7$next[0:0]$8127 \mul_op__rc__ok$7
+ assign $1\mul_op__rc__rc$6$next[0:0]$8128 \mul_op__rc__rc$6
+ assign $1\mul_op__write_cr0$10$next[0:0]$8129 \mul_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\mul_op__imm_data__data$4$next[63:0]$8204 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8205 1'0
- assign $2\mul_op__rc__rc$6$next[0:0]$8209 1'0
- assign $2\mul_op__rc__ok$7$next[0:0]$8208 1'0
- assign $2\mul_op__oe__oe$8$next[0:0]$8206 1'0
- assign $2\mul_op__oe__ok$9$next[0:0]$8207 1'0
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8130 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8131 1'0
+ assign $2\mul_op__rc__rc$6$next[0:0]$8135 1'0
+ assign $2\mul_op__rc__ok$7$next[0:0]$8134 1'0
+ assign $2\mul_op__oe__oe$8$next[0:0]$8132 1'0
+ assign $2\mul_op__oe__ok$9$next[0:0]$8133 1'0
case
- assign $2\mul_op__imm_data__data$4$next[63:0]$8204 $1\mul_op__imm_data__data$4$next[63:0]$8193
- assign $2\mul_op__imm_data__ok$5$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8194
- assign $2\mul_op__oe__oe$8$next[0:0]$8206 $1\mul_op__oe__oe$8$next[0:0]$8199
- assign $2\mul_op__oe__ok$9$next[0:0]$8207 $1\mul_op__oe__ok$9$next[0:0]$8200
- assign $2\mul_op__rc__ok$7$next[0:0]$8208 $1\mul_op__rc__ok$7$next[0:0]$8201
- assign $2\mul_op__rc__rc$6$next[0:0]$8209 $1\mul_op__rc__rc$6$next[0:0]$8202
+ assign $2\mul_op__imm_data__data$4$next[63:0]$8130 $1\mul_op__imm_data__data$4$next[63:0]$8119
+ assign $2\mul_op__imm_data__ok$5$next[0:0]$8131 $1\mul_op__imm_data__ok$5$next[0:0]$8120
+ assign $2\mul_op__oe__oe$8$next[0:0]$8132 $1\mul_op__oe__oe$8$next[0:0]$8125
+ assign $2\mul_op__oe__ok$9$next[0:0]$8133 $1\mul_op__oe__ok$9$next[0:0]$8126
+ assign $2\mul_op__rc__ok$7$next[0:0]$8134 $1\mul_op__rc__ok$7$next[0:0]$8127
+ assign $2\mul_op__rc__rc$6$next[0:0]$8135 $1\mul_op__rc__rc$6$next[0:0]$8128
end
sync always
- update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8180
- update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8181
- update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8182
- update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8183
- update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8184
- update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8185
- update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8186
- update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8187
- update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8188
- update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8189
- update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8190
- update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8191
+ update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8106
+ update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8107
+ update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8108
+ update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8109
+ update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8110
+ update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8111
+ update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8112
+ update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8113
+ update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8114
+ update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8115
+ update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8116
+ update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8117
end
- attribute \src "libresoc.v:155155.3-155173.6"
- process $proc$libresoc.v:155155$8210
+ attribute \src "libresoc.v:153285.3-153303.6"
+ process $proc$libresoc.v:153285$8136
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$14$next[63:0]$8212 $1\o$14$next[63:0]$8214
- assign $0\o_ok$next[0:0]$8211 $2\o_ok$next[0:0]$8215
- attribute \src "libresoc.v:155156.5-155156.29"
+ assign $0\o$14$next[63:0]$8138 $1\o$14$next[63:0]$8140
+ assign $0\o_ok$next[0:0]$8137 $2\o_ok$next[0:0]$8141
+ attribute \src "libresoc.v:153286.5-153286.29"
switch \initial
- attribute \src "libresoc.v:155156.9-155156.17"
+ attribute \src "libresoc.v:153286.9-153286.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8213 $1\o$14$next[63:0]$8214 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$next[0:0]$8139 $1\o$14$next[63:0]$8140 } { \o_ok$72 \o$71 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8213 $1\o$14$next[63:0]$8214 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$next[0:0]$8139 $1\o$14$next[63:0]$8140 } { \o_ok$72 \o$71 }
case
- assign $1\o_ok$next[0:0]$8213 \o_ok
- assign $1\o$14$next[63:0]$8214 \o$14
+ assign $1\o_ok$next[0:0]$8139 \o_ok
+ assign $1\o$14$next[63:0]$8140 \o$14
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8215 1'0
+ assign $2\o_ok$next[0:0]$8141 1'0
case
- assign $2\o_ok$next[0:0]$8215 $1\o_ok$next[0:0]$8213
+ assign $2\o_ok$next[0:0]$8141 $1\o_ok$next[0:0]$8139
end
sync always
- update \o_ok$next $0\o_ok$next[0:0]$8211
- update \o$14$next $0\o$14$next[63:0]$8212
+ update \o_ok$next $0\o_ok$next[0:0]$8137
+ update \o$14$next $0\o$14$next[63:0]$8138
end
- attribute \src "libresoc.v:155174.3-155192.6"
- process $proc$libresoc.v:155174$8216
+ attribute \src "libresoc.v:153304.3-153322.6"
+ process $proc$libresoc.v:153304$8142
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$8217 $1\cr_a$next[3:0]$8219
+ assign $0\cr_a$next[3:0]$8143 $1\cr_a$next[3:0]$8145
assign { } { }
- assign $0\cr_a_ok$next[0:0]$8218 $2\cr_a_ok$next[0:0]$8221
- attribute \src "libresoc.v:155175.5-155175.29"
+ assign $0\cr_a_ok$next[0:0]$8144 $2\cr_a_ok$next[0:0]$8147
+ attribute \src "libresoc.v:153305.5-153305.29"
switch \initial
- attribute \src "libresoc.v:155175.9-155175.17"
+ attribute \src "libresoc.v:153305.9-153305.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8220 $1\cr_a$next[3:0]$8219 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$next[0:0]$8146 $1\cr_a$next[3:0]$8145 } { \cr_a_ok$74 \cr_a$73 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8220 $1\cr_a$next[3:0]$8219 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$next[0:0]$8146 $1\cr_a$next[3:0]$8145 } { \cr_a_ok$74 \cr_a$73 }
case
- assign $1\cr_a$next[3:0]$8219 \cr_a
- assign $1\cr_a_ok$next[0:0]$8220 \cr_a_ok
+ assign $1\cr_a$next[3:0]$8145 \cr_a
+ assign $1\cr_a_ok$next[0:0]$8146 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$8221 1'0
+ assign $2\cr_a_ok$next[0:0]$8147 1'0
case
- assign $2\cr_a_ok$next[0:0]$8221 $1\cr_a_ok$next[0:0]$8220
+ assign $2\cr_a_ok$next[0:0]$8147 $1\cr_a_ok$next[0:0]$8146
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$8217
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8218
+ update \cr_a$next $0\cr_a$next[3:0]$8143
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8144
end
- attribute \src "libresoc.v:155193.3-155211.6"
- process $proc$libresoc.v:155193$8222
+ attribute \src "libresoc.v:153323.3-153341.6"
+ process $proc$libresoc.v:153323$8148
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$8223 $1\xer_ov$next[1:0]$8225
+ assign $0\xer_ov$next[1:0]$8149 $1\xer_ov$next[1:0]$8151
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$8224 $2\xer_ov_ok$next[0:0]$8227
- attribute \src "libresoc.v:155194.5-155194.29"
+ assign $0\xer_ov_ok$next[0:0]$8150 $2\xer_ov_ok$next[0:0]$8153
+ attribute \src "libresoc.v:153324.5-153324.29"
switch \initial
- attribute \src "libresoc.v:155194.9-155194.17"
+ attribute \src "libresoc.v:153324.9-153324.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8226 $1\xer_ov$next[1:0]$8225 } { \xer_ov_ok$76 \xer_ov$75 }
+ assign { $1\xer_ov_ok$next[0:0]$8152 $1\xer_ov$next[1:0]$8151 } { \xer_ov_ok$76 \xer_ov$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8226 $1\xer_ov$next[1:0]$8225 } { \xer_ov_ok$76 \xer_ov$75 }
+ assign { $1\xer_ov_ok$next[0:0]$8152 $1\xer_ov$next[1:0]$8151 } { \xer_ov_ok$76 \xer_ov$75 }
case
- assign $1\xer_ov$next[1:0]$8225 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$8226 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$8151 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$8152 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$8227 1'0
+ assign $2\xer_ov_ok$next[0:0]$8153 1'0
case
- assign $2\xer_ov_ok$next[0:0]$8227 $1\xer_ov_ok$next[0:0]$8226
+ assign $2\xer_ov_ok$next[0:0]$8153 $1\xer_ov_ok$next[0:0]$8152
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$8223
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8224
+ update \xer_ov$next $0\xer_ov$next[1:0]$8149
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8150
end
- attribute \src "libresoc.v:155212.3-155230.6"
- process $proc$libresoc.v:155212$8228
+ attribute \src "libresoc.v:153342.3-153360.6"
+ process $proc$libresoc.v:153342$8154
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$15$next[0:0]$8230 $1\xer_so$15$next[0:0]$8232
- assign $0\xer_so_ok$next[0:0]$8229 $2\xer_so_ok$next[0:0]$8233
- attribute \src "libresoc.v:155213.5-155213.29"
+ assign $0\xer_so$15$next[0:0]$8156 $1\xer_so$15$next[0:0]$8158
+ assign $0\xer_so_ok$next[0:0]$8155 $2\xer_so_ok$next[0:0]$8159
+ attribute \src "libresoc.v:153343.5-153343.29"
switch \initial
- attribute \src "libresoc.v:155213.9-155213.17"
+ attribute \src "libresoc.v:153343.9-153343.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8231 $1\xer_so$15$next[0:0]$8232 } { \xer_so_ok$78 \xer_so$77 }
+ assign { $1\xer_so_ok$next[0:0]$8157 $1\xer_so$15$next[0:0]$8158 } { \xer_so_ok$78 \xer_so$77 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8231 $1\xer_so$15$next[0:0]$8232 } { \xer_so_ok$78 \xer_so$77 }
+ assign { $1\xer_so_ok$next[0:0]$8157 $1\xer_so$15$next[0:0]$8158 } { \xer_so_ok$78 \xer_so$77 }
case
- assign $1\xer_so_ok$next[0:0]$8231 \xer_so_ok
- assign $1\xer_so$15$next[0:0]$8232 \xer_so$15
+ assign $1\xer_so_ok$next[0:0]$8157 \xer_so_ok
+ assign $1\xer_so$15$next[0:0]$8158 \xer_so$15
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$8233 1'0
+ assign $2\xer_so_ok$next[0:0]$8159 1'0
case
- assign $2\xer_so_ok$next[0:0]$8233 $1\xer_so_ok$next[0:0]$8231
+ assign $2\xer_so_ok$next[0:0]$8159 $1\xer_so_ok$next[0:0]$8157
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8229
- update \xer_so$15$next $0\xer_so$15$next[0:0]$8230
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8155
+ update \xer_so$15$next $0\xer_so$15$next[0:0]$8156
end
- connect \$56 $and$libresoc.v:154957$8134_Y
+ connect \$56 $and$libresoc.v:153087$8060_Y
connect \cr_a$51 4'0000
connect \cr_a_ok$52 1'0
connect \p_ready_o \n_i_rdy_data
connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \mul3_muxid \muxid
end
-attribute \src "libresoc.v:155260.1-155271.10"
+attribute \src "libresoc.v:153390.1-153401.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n"
attribute \generator "nMigen"
module \n
- attribute \src "libresoc.v:155269.17-155269.111"
- wire $and$libresoc.v:155269$8272_Y
+ attribute \src "libresoc.v:153399.17-153399.111"
+ wire $and$libresoc.v:153399$8198_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155269$8272
+ cell $and $and$libresoc.v:153399$8198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155269$8272_Y
+ connect \Y $and$libresoc.v:153399$8198_Y
end
- connect \$1 $and$libresoc.v:155269$8272_Y
+ connect \$1 $and$libresoc.v:153399$8198_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155275.1-155286.10"
+attribute \src "libresoc.v:153405.1-153416.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n"
attribute \generator "nMigen"
module \n$109
- attribute \src "libresoc.v:155284.17-155284.111"
- wire $and$libresoc.v:155284$8273_Y
+ attribute \src "libresoc.v:153414.17-153414.111"
+ wire $and$libresoc.v:153414$8199_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155284$8273
+ cell $and $and$libresoc.v:153414$8199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155284$8273_Y
+ connect \Y $and$libresoc.v:153414$8199_Y
end
- connect \$1 $and$libresoc.v:155284$8273_Y
+ connect \$1 $and$libresoc.v:153414$8199_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155290.1-155301.10"
+attribute \src "libresoc.v:153420.1-153431.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n"
attribute \generator "nMigen"
module \n$112
- attribute \src "libresoc.v:155299.17-155299.111"
- wire $and$libresoc.v:155299$8274_Y
+ attribute \src "libresoc.v:153429.17-153429.111"
+ wire $and$libresoc.v:153429$8200_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155299$8274
+ cell $and $and$libresoc.v:153429$8200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155299$8274_Y
+ connect \Y $and$libresoc.v:153429$8200_Y
end
- connect \$1 $and$libresoc.v:155299$8274_Y
+ connect \$1 $and$libresoc.v:153429$8200_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155305.1-155316.10"
+attribute \src "libresoc.v:153435.1-153446.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n"
attribute \generator "nMigen"
module \n$117
- attribute \src "libresoc.v:155314.17-155314.111"
- wire $and$libresoc.v:155314$8275_Y
+ attribute \src "libresoc.v:153444.17-153444.111"
+ wire $and$libresoc.v:153444$8201_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155314$8275
+ cell $and $and$libresoc.v:153444$8201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155314$8275_Y
+ connect \Y $and$libresoc.v:153444$8201_Y
end
- connect \$1 $and$libresoc.v:155314$8275_Y
+ connect \$1 $and$libresoc.v:153444$8201_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155320.1-155331.10"
+attribute \src "libresoc.v:153450.1-153461.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n"
attribute \generator "nMigen"
module \n$18
- attribute \src "libresoc.v:155329.17-155329.111"
- wire $and$libresoc.v:155329$8276_Y
+ attribute \src "libresoc.v:153459.17-153459.111"
+ wire $and$libresoc.v:153459$8202_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155329$8276
+ cell $and $and$libresoc.v:153459$8202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155329$8276_Y
+ connect \Y $and$libresoc.v:153459$8202_Y
end
- connect \$1 $and$libresoc.v:155329$8276_Y
+ connect \$1 $and$libresoc.v:153459$8202_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155335.1-155346.10"
+attribute \src "libresoc.v:153465.1-153476.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n"
attribute \generator "nMigen"
module \n$2
- attribute \src "libresoc.v:155344.17-155344.111"
- wire $and$libresoc.v:155344$8277_Y
+ attribute \src "libresoc.v:153474.17-153474.111"
+ wire $and$libresoc.v:153474$8203_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155344$8277
+ cell $and $and$libresoc.v:153474$8203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155344$8277_Y
+ connect \Y $and$libresoc.v:153474$8203_Y
end
- connect \$1 $and$libresoc.v:155344$8277_Y
+ connect \$1 $and$libresoc.v:153474$8203_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155350.1-155361.10"
+attribute \src "libresoc.v:153480.1-153491.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n"
attribute \generator "nMigen"
module \n$21
- attribute \src "libresoc.v:155359.17-155359.111"
- wire $and$libresoc.v:155359$8278_Y
+ attribute \src "libresoc.v:153489.17-153489.111"
+ wire $and$libresoc.v:153489$8204_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155359$8278
+ cell $and $and$libresoc.v:153489$8204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155359$8278_Y
+ connect \Y $and$libresoc.v:153489$8204_Y
end
- connect \$1 $and$libresoc.v:155359$8278_Y
+ connect \$1 $and$libresoc.v:153489$8204_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155365.1-155376.10"
+attribute \src "libresoc.v:153495.1-153506.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n"
attribute \generator "nMigen"
module \n$31
- attribute \src "libresoc.v:155374.17-155374.111"
- wire $and$libresoc.v:155374$8279_Y
+ attribute \src "libresoc.v:153504.17-153504.111"
+ wire $and$libresoc.v:153504$8205_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155374$8279
+ cell $and $and$libresoc.v:153504$8205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155374$8279_Y
+ connect \Y $and$libresoc.v:153504$8205_Y
end
- connect \$1 $and$libresoc.v:155374$8279_Y
+ connect \$1 $and$libresoc.v:153504$8205_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155380.1-155391.10"
+attribute \src "libresoc.v:153510.1-153521.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n"
attribute \generator "nMigen"
module \n$34
- attribute \src "libresoc.v:155389.17-155389.111"
- wire $and$libresoc.v:155389$8280_Y
+ attribute \src "libresoc.v:153519.17-153519.111"
+ wire $and$libresoc.v:153519$8206_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155389$8280
+ cell $and $and$libresoc.v:153519$8206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155389$8280_Y
+ connect \Y $and$libresoc.v:153519$8206_Y
end
- connect \$1 $and$libresoc.v:155389$8280_Y
+ connect \$1 $and$libresoc.v:153519$8206_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155395.1-155406.10"
+attribute \src "libresoc.v:153525.1-153536.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n"
attribute \generator "nMigen"
module \n$37
- attribute \src "libresoc.v:155404.17-155404.111"
- wire $and$libresoc.v:155404$8281_Y
+ attribute \src "libresoc.v:153534.17-153534.111"
+ wire $and$libresoc.v:153534$8207_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155404$8281
+ cell $and $and$libresoc.v:153534$8207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155404$8281_Y
+ connect \Y $and$libresoc.v:153534$8207_Y
end
- connect \$1 $and$libresoc.v:155404$8281_Y
+ connect \$1 $and$libresoc.v:153534$8207_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155410.1-155421.10"
+attribute \src "libresoc.v:153540.1-153551.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n"
attribute \generator "nMigen"
module \n$4
- attribute \src "libresoc.v:155419.17-155419.111"
- wire $and$libresoc.v:155419$8282_Y
+ attribute \src "libresoc.v:153549.17-153549.111"
+ wire $and$libresoc.v:153549$8208_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155419$8282
+ cell $and $and$libresoc.v:153549$8208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155419$8282_Y
+ connect \Y $and$libresoc.v:153549$8208_Y
end
- connect \$1 $and$libresoc.v:155419$8282_Y
+ connect \$1 $and$libresoc.v:153549$8208_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155425.1-155436.10"
+attribute \src "libresoc.v:153555.1-153566.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n"
attribute \generator "nMigen"
module \n$47
- attribute \src "libresoc.v:155434.17-155434.111"
- wire $and$libresoc.v:155434$8283_Y
+ attribute \src "libresoc.v:153564.17-153564.111"
+ wire $and$libresoc.v:153564$8209_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155434$8283
+ cell $and $and$libresoc.v:153564$8209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155434$8283_Y
+ connect \Y $and$libresoc.v:153564$8209_Y
end
- connect \$1 $and$libresoc.v:155434$8283_Y
+ connect \$1 $and$libresoc.v:153564$8209_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155440.1-155451.10"
+attribute \src "libresoc.v:153570.1-153581.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n"
attribute \generator "nMigen"
module \n$49
- attribute \src "libresoc.v:155449.17-155449.111"
- wire $and$libresoc.v:155449$8284_Y
+ attribute \src "libresoc.v:153579.17-153579.111"
+ wire $and$libresoc.v:153579$8210_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155449$8284
+ cell $and $and$libresoc.v:153579$8210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155449$8284_Y
+ connect \Y $and$libresoc.v:153579$8210_Y
end
- connect \$1 $and$libresoc.v:155449$8284_Y
+ connect \$1 $and$libresoc.v:153579$8210_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155455.1-155466.10"
+attribute \src "libresoc.v:153585.1-153596.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n"
attribute \generator "nMigen"
module \n$53
- attribute \src "libresoc.v:155464.17-155464.111"
- wire $and$libresoc.v:155464$8285_Y
+ attribute \src "libresoc.v:153594.17-153594.111"
+ wire $and$libresoc.v:153594$8211_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155464$8285
+ cell $and $and$libresoc.v:153594$8211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155464$8285_Y
+ connect \Y $and$libresoc.v:153594$8211_Y
end
- connect \$1 $and$libresoc.v:155464$8285_Y
+ connect \$1 $and$libresoc.v:153594$8211_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155470.1-155481.10"
+attribute \src "libresoc.v:153600.1-153611.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n"
attribute \generator "nMigen"
module \n$6
- attribute \src "libresoc.v:155479.17-155479.111"
- wire $and$libresoc.v:155479$8286_Y
+ attribute \src "libresoc.v:153609.17-153609.111"
+ wire $and$libresoc.v:153609$8212_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155479$8286
+ cell $and $and$libresoc.v:153609$8212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155479$8286_Y
+ connect \Y $and$libresoc.v:153609$8212_Y
end
- connect \$1 $and$libresoc.v:155479$8286_Y
+ connect \$1 $and$libresoc.v:153609$8212_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155485.1-155496.10"
+attribute \src "libresoc.v:153615.1-153626.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n"
attribute \generator "nMigen"
module \n$63
- attribute \src "libresoc.v:155494.17-155494.111"
- wire $and$libresoc.v:155494$8287_Y
+ attribute \src "libresoc.v:153624.17-153624.111"
+ wire $and$libresoc.v:153624$8213_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155494$8287
+ cell $and $and$libresoc.v:153624$8213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155494$8287_Y
+ connect \Y $and$libresoc.v:153624$8213_Y
end
- connect \$1 $and$libresoc.v:155494$8287_Y
+ connect \$1 $and$libresoc.v:153624$8213_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155500.1-155511.10"
+attribute \src "libresoc.v:153630.1-153641.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n"
attribute \generator "nMigen"
module \n$66
- attribute \src "libresoc.v:155509.17-155509.111"
- wire $and$libresoc.v:155509$8288_Y
+ attribute \src "libresoc.v:153639.17-153639.111"
+ wire $and$libresoc.v:153639$8214_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155509$8288
+ cell $and $and$libresoc.v:153639$8214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155509$8288_Y
+ connect \Y $and$libresoc.v:153639$8214_Y
end
- connect \$1 $and$libresoc.v:155509$8288_Y
+ connect \$1 $and$libresoc.v:153639$8214_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155515.1-155526.10"
+attribute \src "libresoc.v:153645.1-153656.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n"
attribute \generator "nMigen"
module \n$75
- attribute \src "libresoc.v:155524.17-155524.111"
- wire $and$libresoc.v:155524$8289_Y
+ attribute \src "libresoc.v:153654.17-153654.111"
+ wire $and$libresoc.v:153654$8215_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155524$8289
+ cell $and $and$libresoc.v:153654$8215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155524$8289_Y
+ connect \Y $and$libresoc.v:153654$8215_Y
end
- connect \$1 $and$libresoc.v:155524$8289_Y
+ connect \$1 $and$libresoc.v:153654$8215_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155530.1-155541.10"
+attribute \src "libresoc.v:153660.1-153671.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n"
attribute \generator "nMigen"
module \n$77
- attribute \src "libresoc.v:155539.17-155539.111"
- wire $and$libresoc.v:155539$8290_Y
+ attribute \src "libresoc.v:153669.17-153669.111"
+ wire $and$libresoc.v:153669$8216_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155539$8290
+ cell $and $and$libresoc.v:153669$8216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155539$8290_Y
+ connect \Y $and$libresoc.v:153669$8216_Y
end
- connect \$1 $and$libresoc.v:155539$8290_Y
+ connect \$1 $and$libresoc.v:153669$8216_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155545.1-155556.10"
+attribute \src "libresoc.v:153675.1-153686.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n"
attribute \generator "nMigen"
module \n$8
- attribute \src "libresoc.v:155554.17-155554.111"
- wire $and$libresoc.v:155554$8291_Y
+ attribute \src "libresoc.v:153684.17-153684.111"
+ wire $and$libresoc.v:153684$8217_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155554$8291
+ cell $and $and$libresoc.v:153684$8217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155554$8291_Y
+ connect \Y $and$libresoc.v:153684$8217_Y
end
- connect \$1 $and$libresoc.v:155554$8291_Y
+ connect \$1 $and$libresoc.v:153684$8217_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155560.1-155571.10"
+attribute \src "libresoc.v:153690.1-153701.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n"
attribute \generator "nMigen"
module \n$80
- attribute \src "libresoc.v:155569.17-155569.111"
- wire $and$libresoc.v:155569$8292_Y
+ attribute \src "libresoc.v:153699.17-153699.111"
+ wire $and$libresoc.v:153699$8218_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155569$8292
+ cell $and $and$libresoc.v:153699$8218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155569$8292_Y
+ connect \Y $and$libresoc.v:153699$8218_Y
end
- connect \$1 $and$libresoc.v:155569$8292_Y
+ connect \$1 $and$libresoc.v:153699$8218_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155575.1-155586.10"
+attribute \src "libresoc.v:153705.1-153716.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n"
attribute \generator "nMigen"
module \n$82
- attribute \src "libresoc.v:155584.17-155584.111"
- wire $and$libresoc.v:155584$8293_Y
+ attribute \src "libresoc.v:153714.17-153714.111"
+ wire $and$libresoc.v:153714$8219_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155584$8293
+ cell $and $and$libresoc.v:153714$8219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155584$8293_Y
+ connect \Y $and$libresoc.v:153714$8219_Y
end
- connect \$1 $and$libresoc.v:155584$8293_Y
+ connect \$1 $and$libresoc.v:153714$8219_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155590.1-155601.10"
+attribute \src "libresoc.v:153720.1-153731.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n"
attribute \generator "nMigen"
module \n$92
- attribute \src "libresoc.v:155599.17-155599.111"
- wire $and$libresoc.v:155599$8294_Y
+ attribute \src "libresoc.v:153729.17-153729.111"
+ wire $and$libresoc.v:153729$8220_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155599$8294
+ cell $and $and$libresoc.v:153729$8220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155599$8294_Y
+ connect \Y $and$libresoc.v:153729$8220_Y
end
- connect \$1 $and$libresoc.v:155599$8294_Y
+ connect \$1 $and$libresoc.v:153729$8220_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155605.1-155616.10"
+attribute \src "libresoc.v:153735.1-153746.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n"
attribute \generator "nMigen"
module \n$94
- attribute \src "libresoc.v:155614.17-155614.111"
- wire $and$libresoc.v:155614$8295_Y
+ attribute \src "libresoc.v:153744.17-153744.111"
+ wire $and$libresoc.v:153744$8221_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155614$8295
+ cell $and $and$libresoc.v:153744$8221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155614$8295_Y
+ connect \Y $and$libresoc.v:153744$8221_Y
end
- connect \$1 $and$libresoc.v:155614$8295_Y
+ connect \$1 $and$libresoc.v:153744$8221_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155620.1-155631.10"
+attribute \src "libresoc.v:153750.1-153761.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n"
attribute \generator "nMigen"
module \n$97
- attribute \src "libresoc.v:155629.17-155629.111"
- wire $and$libresoc.v:155629$8296_Y
+ attribute \src "libresoc.v:153759.17-153759.111"
+ wire $and$libresoc.v:153759$8222_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155629$8296
+ cell $and $and$libresoc.v:153759$8222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155629$8296_Y
+ connect \Y $and$libresoc.v:153759$8222_Y
end
- connect \$1 $and$libresoc.v:155629$8296_Y
+ connect \$1 $and$libresoc.v:153759$8222_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155635.1-155646.10"
+attribute \src "libresoc.v:153765.1-153776.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n"
attribute \generator "nMigen"
module \n$99
- attribute \src "libresoc.v:155644.17-155644.111"
- wire $and$libresoc.v:155644$8297_Y
+ attribute \src "libresoc.v:153774.17-153774.111"
+ wire $and$libresoc.v:153774$8223_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304"
- cell $and $and$libresoc.v:155644$8297
+ cell $and $and$libresoc.v:153774$8223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:155644$8297_Y
+ connect \Y $and$libresoc.v:153774$8223_Y
end
- connect \$1 $and$libresoc.v:155644$8297_Y
+ connect \$1 $and$libresoc.v:153774$8223_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:155650.1-155811.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.o2_svdec"
-attribute \generator "nMigen"
-module \o2_svdec
- attribute \src "libresoc.v:155745.3-155761.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:155762.3-155778.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:155779.3-155795.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:155651.7-155651.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:155796.3-155807.6"
- wire width 7 $0\reg_out[6:0]
- attribute \src "libresoc.v:155686.3-155744.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:155745.3-155761.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:155762.3-155778.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:155779.3-155795.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:155796.3-155807.6"
- wire width 7 $1\reg_out[6:0]
- attribute \src "libresoc.v:155686.3-155744.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:155745.3-155761.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:155762.3-155778.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:155779.3-155795.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:155686.3-155744.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:155686.3-155744.6"
- wire width 3 $3\spec[2:0]
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 1 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 5 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 \idx
- attribute \src "libresoc.v:155651.7-155651.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire output 3 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 input 2 \reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 output 4 \reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101"
- wire width 2 \spec_aug
- attribute \src "libresoc.v:155651.7-155651.20"
- process $proc$libresoc.v:155651$8303
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:155686.3-155744.6"
- process $proc$libresoc.v:155686$8298
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:155687.5-155687.29"
- switch \initial
- attribute \src "libresoc.v:155687.9-155687.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:155745.3-155761.6"
- process $proc$libresoc.v:155745$8299
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:155746.5-155746.29"
- switch \initial
- attribute \src "libresoc.v:155746.9-155746.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:155762.3-155778.6"
- process $proc$libresoc.v:155762$8300
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:155763.5-155763.29"
- switch \initial
- attribute \src "libresoc.v:155763.9-155763.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:155779.3-155795.6"
- process $proc$libresoc.v:155779$8301
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:155780.5-155780.29"
- switch \initial
- attribute \src "libresoc.v:155780.9-155780.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:155796.3-155807.6"
- process $proc$libresoc.v:155796$8302
- assign { } { }
- assign $0\reg_out[6:0] $1\reg_out[6:0]
- attribute \src "libresoc.v:155797.5-155797.29"
- switch \initial
- attribute \src "libresoc.v:155797.9-155797.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg_out[6:0] { \reg_in \spec_aug }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\reg_out[6:0] { \spec_aug \reg_in }
- end
- sync always
- update \reg_out $0\reg_out[6:0]
- end
- connect \idx 3'000
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:155815.1-155975.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.dec2.o_svdec"
-attribute \generator "nMigen"
-module \o_svdec
- attribute \src "libresoc.v:155910.3-155926.6"
- wire width 3 $0\extra3_idx0[2:0]
- attribute \src "libresoc.v:155927.3-155943.6"
- wire width 3 $0\extra3_idx1[2:0]
- attribute \src "libresoc.v:155944.3-155960.6"
- wire width 3 $0\extra3_idx2[2:0]
- attribute \src "libresoc.v:155816.7-155816.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:155961.3-155972.6"
- wire width 7 $0\reg_out[6:0]
- attribute \src "libresoc.v:155851.3-155909.6"
- wire width 3 $0\spec[2:0]
- attribute \src "libresoc.v:155910.3-155926.6"
- wire width 3 $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:155927.3-155943.6"
- wire width 3 $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:155944.3-155960.6"
- wire width 3 $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:155961.3-155972.6"
- wire width 7 $1\reg_out[6:0]
- attribute \src "libresoc.v:155851.3-155909.6"
- wire width 3 $1\spec[2:0]
- attribute \src "libresoc.v:155910.3-155926.6"
- wire width 3 $2\extra3_idx0[2:0]
- attribute \src "libresoc.v:155927.3-155943.6"
- wire width 3 $2\extra3_idx1[2:0]
- attribute \src "libresoc.v:155944.3-155960.6"
- wire width 3 $2\extra3_idx2[2:0]
- attribute \src "libresoc.v:155851.3-155909.6"
- wire width 2 $2\spec[2:1]
- attribute \src "libresoc.v:155851.3-155909.6"
- wire width 3 $3\spec[2:0]
- attribute \enum_base_type "SVEtype"
- attribute \enum_value_00 "NONE"
- attribute \enum_value_01 "EXTRA2"
- attribute \enum_value_10 "EXTRA3"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23"
- wire width 2 input 1 \etype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22"
- wire width 9 input 6 \extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57"
- wire width 3 \extra3_idx0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60"
- wire width 3 \extra3_idx1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63"
- wire width 3 \extra3_idx2
- attribute \enum_base_type "SVEXTRA"
- attribute \enum_value_000 "NONE"
- attribute \enum_value_001 "Idx0"
- attribute \enum_value_010 "Idx1"
- attribute \enum_value_011 "Idx2"
- attribute \enum_value_100 "Idx3"
- attribute \enum_value_101 "Idx_1_2"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24"
- wire width 3 input 5 \idx
- attribute \src "libresoc.v:155816.7-155816.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85"
- wire output 3 \isvec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83"
- wire width 5 input 2 \reg_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84"
- wire width 7 output 4 \reg_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25"
- wire width 3 \spec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101"
- wire width 2 \spec_aug
- attribute \src "libresoc.v:155816.7-155816.20"
- process $proc$libresoc.v:155816$8309
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:155851.3-155909.6"
- process $proc$libresoc.v:155851$8304
- assign { } { }
- assign { } { }
- assign $0\spec[2:0] $1\spec[2:0]
- attribute \src "libresoc.v:155852.5-155852.29"
- switch \initial
- attribute \src "libresoc.v:155852.9-155852.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign $1\spec[2:0] [0] 1'0
- assign $1\spec[2:0] [2:1] $2\spec[2:1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\spec[2:1] [1] \extra [8]
- assign $2\spec[2:1] [0] \extra [7]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\spec[2:1] [1] \extra [6]
- assign $2\spec[2:1] [0] \extra [5]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\spec[2:1] [1] \extra [4]
- assign $2\spec[2:1] [0] \extra [3]
- attribute \src "libresoc.v:0.0-0.0"
- case 3'100
- assign { } { }
- assign $2\spec[2:1] [1] \extra [2]
- assign $2\spec[2:1] [0] \extra [1]
- case
- assign $2\spec[2:1] 2'00
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\spec[2:0] $3\spec[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $3\spec[2:0] \extra3_idx0
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $3\spec[2:0] \extra3_idx1
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $3\spec[2:0] \extra3_idx2
- case
- assign $3\spec[2:0] 3'000
- end
- case
- assign $1\spec[2:0] 3'000
- end
- sync always
- update \spec $0\spec[2:0]
- end
- attribute \src "libresoc.v:155910.3-155926.6"
- process $proc$libresoc.v:155910$8305
- assign { } { }
- assign { } { }
- assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0]
- attribute \src "libresoc.v:155911.5-155911.29"
- switch \initial
- attribute \src "libresoc.v:155911.9-155911.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'001
- assign { } { }
- assign $2\extra3_idx0[2:0] \extra [8:6]
- case
- assign $2\extra3_idx0[2:0] 3'000
- end
- case
- assign $1\extra3_idx0[2:0] 3'000
- end
- sync always
- update \extra3_idx0 $0\extra3_idx0[2:0]
- end
- attribute \src "libresoc.v:155927.3-155943.6"
- process $proc$libresoc.v:155927$8306
- assign { } { }
- assign { } { }
- assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0]
- attribute \src "libresoc.v:155928.5-155928.29"
- switch \initial
- attribute \src "libresoc.v:155928.9-155928.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $2\extra3_idx1[2:0] \extra [5:3]
- case
- assign $2\extra3_idx1[2:0] 3'000
- end
- case
- assign $1\extra3_idx1[2:0] 3'000
- end
- sync always
- update \extra3_idx1 $0\extra3_idx1[2:0]
- end
- attribute \src "libresoc.v:155944.3-155960.6"
- process $proc$libresoc.v:155944$8307
- assign { } { }
- assign { } { }
- assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0]
- attribute \src "libresoc.v:155945.5-155945.29"
- switch \initial
- attribute \src "libresoc.v:155945.9-155945.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37"
- switch \etype
- attribute \src "libresoc.v:0.0-0.0"
- case 2'10
- assign { } { }
- assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55"
- switch \idx
- attribute \src "libresoc.v:0.0-0.0"
- case 3'011
- assign { } { }
- assign $2\extra3_idx2[2:0] \extra [2:0]
- case
- assign $2\extra3_idx2[2:0] 3'000
- end
- case
- assign $1\extra3_idx2[2:0] 3'000
- end
- sync always
- update \extra3_idx2 $0\extra3_idx2[2:0]
- end
- attribute \src "libresoc.v:155961.3-155972.6"
- process $proc$libresoc.v:155961$8308
- assign { } { }
- assign $0\reg_out[6:0] $1\reg_out[6:0]
- attribute \src "libresoc.v:155962.5-155962.29"
- switch \initial
- attribute \src "libresoc.v:155962.9-155962.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105"
- switch \isvec
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\reg_out[6:0] { \reg_in \spec_aug }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\reg_out[6:0] { \spec_aug \reg_in }
- end
- sync always
- update \reg_out $0\reg_out[6:0]
- end
- connect \spec_aug \spec [1:0]
- connect \isvec \spec [2]
-end
-attribute \src "libresoc.v:155979.1-156037.10"
+attribute \src "libresoc.v:153780.1-153838.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l"
attribute \generator "nMigen"
module \opc_l
- attribute \src "libresoc.v:155980.7-155980.20"
+ attribute \src "libresoc.v:153781.7-153781.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156025.3-156033.6"
- wire $0\q_int$next[0:0]$8320
- attribute \src "libresoc.v:156023.3-156024.27"
+ attribute \src "libresoc.v:153826.3-153834.6"
+ wire $0\q_int$next[0:0]$8234
+ attribute \src "libresoc.v:153824.3-153825.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156025.3-156033.6"
- wire $1\q_int$next[0:0]$8321
- attribute \src "libresoc.v:156002.7-156002.19"
+ attribute \src "libresoc.v:153826.3-153834.6"
+ wire $1\q_int$next[0:0]$8235
+ attribute \src "libresoc.v:153803.7-153803.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156015.17-156015.96"
- wire $and$libresoc.v:156015$8310_Y
- attribute \src "libresoc.v:156020.17-156020.96"
- wire $and$libresoc.v:156020$8315_Y
- attribute \src "libresoc.v:156017.18-156017.93"
- wire $not$libresoc.v:156017$8312_Y
- attribute \src "libresoc.v:156019.17-156019.92"
- wire $not$libresoc.v:156019$8314_Y
- attribute \src "libresoc.v:156022.17-156022.92"
- wire $not$libresoc.v:156022$8317_Y
- attribute \src "libresoc.v:156016.18-156016.98"
- wire $or$libresoc.v:156016$8311_Y
- attribute \src "libresoc.v:156018.18-156018.99"
- wire $or$libresoc.v:156018$8313_Y
- attribute \src "libresoc.v:156021.17-156021.97"
- wire $or$libresoc.v:156021$8316_Y
+ attribute \src "libresoc.v:153816.17-153816.96"
+ wire $and$libresoc.v:153816$8224_Y
+ attribute \src "libresoc.v:153821.17-153821.96"
+ wire $and$libresoc.v:153821$8229_Y
+ attribute \src "libresoc.v:153818.18-153818.93"
+ wire $not$libresoc.v:153818$8226_Y
+ attribute \src "libresoc.v:153820.17-153820.92"
+ wire $not$libresoc.v:153820$8228_Y
+ attribute \src "libresoc.v:153823.17-153823.92"
+ wire $not$libresoc.v:153823$8231_Y
+ attribute \src "libresoc.v:153817.18-153817.98"
+ wire $or$libresoc.v:153817$8225_Y
+ attribute \src "libresoc.v:153819.18-153819.99"
+ wire $or$libresoc.v:153819$8227_Y
+ attribute \src "libresoc.v:153822.17-153822.97"
+ wire $or$libresoc.v:153822$8230_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:155980.7-155980.15"
+ attribute \src "libresoc.v:153781.7-153781.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156015$8310
+ cell $and $and$libresoc.v:153816$8224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156015$8310_Y
+ connect \Y $and$libresoc.v:153816$8224_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156020$8315
+ cell $and $and$libresoc.v:153821$8229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156020$8315_Y
+ connect \Y $and$libresoc.v:153821$8229_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156017$8312
+ cell $not $not$libresoc.v:153818$8226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156017$8312_Y
+ connect \Y $not$libresoc.v:153818$8226_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156019$8314
+ cell $not $not$libresoc.v:153820$8228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156019$8314_Y
+ connect \Y $not$libresoc.v:153820$8228_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156022$8317
+ cell $not $not$libresoc.v:153823$8231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156022$8317_Y
+ connect \Y $not$libresoc.v:153823$8231_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156016$8311
+ cell $or $or$libresoc.v:153817$8225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156016$8311_Y
+ connect \Y $or$libresoc.v:153817$8225_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156018$8313
+ cell $or $or$libresoc.v:153819$8227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156018$8313_Y
+ connect \Y $or$libresoc.v:153819$8227_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156021$8316
+ cell $or $or$libresoc.v:153822$8230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156021$8316_Y
+ connect \Y $or$libresoc.v:153822$8230_Y
end
- attribute \src "libresoc.v:155980.7-155980.20"
- process $proc$libresoc.v:155980$8322
+ attribute \src "libresoc.v:153781.7-153781.20"
+ process $proc$libresoc.v:153781$8236
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156002.7-156002.19"
- process $proc$libresoc.v:156002$8323
+ attribute \src "libresoc.v:153803.7-153803.19"
+ process $proc$libresoc.v:153803$8237
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156023.3-156024.27"
- process $proc$libresoc.v:156023$8318
+ attribute \src "libresoc.v:153824.3-153825.27"
+ process $proc$libresoc.v:153824$8232
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156025.3-156033.6"
- process $proc$libresoc.v:156025$8319
+ attribute \src "libresoc.v:153826.3-153834.6"
+ process $proc$libresoc.v:153826$8233
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8320 $1\q_int$next[0:0]$8321
- attribute \src "libresoc.v:156026.5-156026.29"
+ assign $0\q_int$next[0:0]$8234 $1\q_int$next[0:0]$8235
+ attribute \src "libresoc.v:153827.5-153827.29"
switch \initial
- attribute \src "libresoc.v:156026.9-156026.17"
+ attribute \src "libresoc.v:153827.9-153827.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8321 1'0
+ assign $1\q_int$next[0:0]$8235 1'0
case
- assign $1\q_int$next[0:0]$8321 \$5
+ assign $1\q_int$next[0:0]$8235 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8320
+ update \q_int$next $0\q_int$next[0:0]$8234
end
- connect \$9 $and$libresoc.v:156015$8310_Y
- connect \$11 $or$libresoc.v:156016$8311_Y
- connect \$13 $not$libresoc.v:156017$8312_Y
- connect \$15 $or$libresoc.v:156018$8313_Y
- connect \$1 $not$libresoc.v:156019$8314_Y
- connect \$3 $and$libresoc.v:156020$8315_Y
- connect \$5 $or$libresoc.v:156021$8316_Y
- connect \$7 $not$libresoc.v:156022$8317_Y
+ connect \$9 $and$libresoc.v:153816$8224_Y
+ connect \$11 $or$libresoc.v:153817$8225_Y
+ connect \$13 $not$libresoc.v:153818$8226_Y
+ connect \$15 $or$libresoc.v:153819$8227_Y
+ connect \$1 $not$libresoc.v:153820$8228_Y
+ connect \$3 $and$libresoc.v:153821$8229_Y
+ connect \$5 $or$libresoc.v:153822$8230_Y
+ connect \$7 $not$libresoc.v:153823$8231_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156041.1-156099.10"
+attribute \src "libresoc.v:153842.1-153900.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l"
attribute \generator "nMigen"
module \opc_l$102
- attribute \src "libresoc.v:156042.7-156042.20"
+ attribute \src "libresoc.v:153843.7-153843.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156087.3-156095.6"
- wire $0\q_int$next[0:0]$8334
- attribute \src "libresoc.v:156085.3-156086.27"
+ attribute \src "libresoc.v:153888.3-153896.6"
+ wire $0\q_int$next[0:0]$8248
+ attribute \src "libresoc.v:153886.3-153887.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156087.3-156095.6"
- wire $1\q_int$next[0:0]$8335
- attribute \src "libresoc.v:156064.7-156064.19"
+ attribute \src "libresoc.v:153888.3-153896.6"
+ wire $1\q_int$next[0:0]$8249
+ attribute \src "libresoc.v:153865.7-153865.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156077.17-156077.96"
- wire $and$libresoc.v:156077$8324_Y
- attribute \src "libresoc.v:156082.17-156082.96"
- wire $and$libresoc.v:156082$8329_Y
- attribute \src "libresoc.v:156079.18-156079.93"
- wire $not$libresoc.v:156079$8326_Y
- attribute \src "libresoc.v:156081.17-156081.92"
- wire $not$libresoc.v:156081$8328_Y
- attribute \src "libresoc.v:156084.17-156084.92"
- wire $not$libresoc.v:156084$8331_Y
- attribute \src "libresoc.v:156078.18-156078.98"
- wire $or$libresoc.v:156078$8325_Y
- attribute \src "libresoc.v:156080.18-156080.99"
- wire $or$libresoc.v:156080$8327_Y
- attribute \src "libresoc.v:156083.17-156083.97"
- wire $or$libresoc.v:156083$8330_Y
+ attribute \src "libresoc.v:153878.17-153878.96"
+ wire $and$libresoc.v:153878$8238_Y
+ attribute \src "libresoc.v:153883.17-153883.96"
+ wire $and$libresoc.v:153883$8243_Y
+ attribute \src "libresoc.v:153880.18-153880.93"
+ wire $not$libresoc.v:153880$8240_Y
+ attribute \src "libresoc.v:153882.17-153882.92"
+ wire $not$libresoc.v:153882$8242_Y
+ attribute \src "libresoc.v:153885.17-153885.92"
+ wire $not$libresoc.v:153885$8245_Y
+ attribute \src "libresoc.v:153879.18-153879.98"
+ wire $or$libresoc.v:153879$8239_Y
+ attribute \src "libresoc.v:153881.18-153881.99"
+ wire $or$libresoc.v:153881$8241_Y
+ attribute \src "libresoc.v:153884.17-153884.97"
+ wire $or$libresoc.v:153884$8244_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156042.7-156042.15"
+ attribute \src "libresoc.v:153843.7-153843.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156077$8324
+ cell $and $and$libresoc.v:153878$8238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156077$8324_Y
+ connect \Y $and$libresoc.v:153878$8238_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156082$8329
+ cell $and $and$libresoc.v:153883$8243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156082$8329_Y
+ connect \Y $and$libresoc.v:153883$8243_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156079$8326
+ cell $not $not$libresoc.v:153880$8240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156079$8326_Y
+ connect \Y $not$libresoc.v:153880$8240_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156081$8328
+ cell $not $not$libresoc.v:153882$8242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156081$8328_Y
+ connect \Y $not$libresoc.v:153882$8242_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156084$8331
+ cell $not $not$libresoc.v:153885$8245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156084$8331_Y
+ connect \Y $not$libresoc.v:153885$8245_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156078$8325
+ cell $or $or$libresoc.v:153879$8239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156078$8325_Y
+ connect \Y $or$libresoc.v:153879$8239_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156080$8327
+ cell $or $or$libresoc.v:153881$8241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156080$8327_Y
+ connect \Y $or$libresoc.v:153881$8241_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156083$8330
+ cell $or $or$libresoc.v:153884$8244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156083$8330_Y
+ connect \Y $or$libresoc.v:153884$8244_Y
end
- attribute \src "libresoc.v:156042.7-156042.20"
- process $proc$libresoc.v:156042$8336
+ attribute \src "libresoc.v:153843.7-153843.20"
+ process $proc$libresoc.v:153843$8250
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156064.7-156064.19"
- process $proc$libresoc.v:156064$8337
+ attribute \src "libresoc.v:153865.7-153865.19"
+ process $proc$libresoc.v:153865$8251
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156085.3-156086.27"
- process $proc$libresoc.v:156085$8332
+ attribute \src "libresoc.v:153886.3-153887.27"
+ process $proc$libresoc.v:153886$8246
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156087.3-156095.6"
- process $proc$libresoc.v:156087$8333
+ attribute \src "libresoc.v:153888.3-153896.6"
+ process $proc$libresoc.v:153888$8247
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8334 $1\q_int$next[0:0]$8335
- attribute \src "libresoc.v:156088.5-156088.29"
+ assign $0\q_int$next[0:0]$8248 $1\q_int$next[0:0]$8249
+ attribute \src "libresoc.v:153889.5-153889.29"
switch \initial
- attribute \src "libresoc.v:156088.9-156088.17"
+ attribute \src "libresoc.v:153889.9-153889.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8335 1'0
+ assign $1\q_int$next[0:0]$8249 1'0
case
- assign $1\q_int$next[0:0]$8335 \$5
+ assign $1\q_int$next[0:0]$8249 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8334
+ update \q_int$next $0\q_int$next[0:0]$8248
end
- connect \$9 $and$libresoc.v:156077$8324_Y
- connect \$11 $or$libresoc.v:156078$8325_Y
- connect \$13 $not$libresoc.v:156079$8326_Y
- connect \$15 $or$libresoc.v:156080$8327_Y
- connect \$1 $not$libresoc.v:156081$8328_Y
- connect \$3 $and$libresoc.v:156082$8329_Y
- connect \$5 $or$libresoc.v:156083$8330_Y
- connect \$7 $not$libresoc.v:156084$8331_Y
+ connect \$9 $and$libresoc.v:153878$8238_Y
+ connect \$11 $or$libresoc.v:153879$8239_Y
+ connect \$13 $not$libresoc.v:153880$8240_Y
+ connect \$15 $or$libresoc.v:153881$8241_Y
+ connect \$1 $not$libresoc.v:153882$8242_Y
+ connect \$3 $and$libresoc.v:153883$8243_Y
+ connect \$5 $or$libresoc.v:153884$8244_Y
+ connect \$7 $not$libresoc.v:153885$8245_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156103.1-156161.10"
+attribute \src "libresoc.v:153904.1-153962.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l"
attribute \generator "nMigen"
module \opc_l$11
- attribute \src "libresoc.v:156104.7-156104.20"
+ attribute \src "libresoc.v:153905.7-153905.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156149.3-156157.6"
- wire $0\q_int$next[0:0]$8348
- attribute \src "libresoc.v:156147.3-156148.27"
+ attribute \src "libresoc.v:153950.3-153958.6"
+ wire $0\q_int$next[0:0]$8262
+ attribute \src "libresoc.v:153948.3-153949.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156149.3-156157.6"
- wire $1\q_int$next[0:0]$8349
- attribute \src "libresoc.v:156126.7-156126.19"
+ attribute \src "libresoc.v:153950.3-153958.6"
+ wire $1\q_int$next[0:0]$8263
+ attribute \src "libresoc.v:153927.7-153927.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156139.17-156139.96"
- wire $and$libresoc.v:156139$8338_Y
- attribute \src "libresoc.v:156144.17-156144.96"
- wire $and$libresoc.v:156144$8343_Y
- attribute \src "libresoc.v:156141.18-156141.93"
- wire $not$libresoc.v:156141$8340_Y
- attribute \src "libresoc.v:156143.17-156143.92"
- wire $not$libresoc.v:156143$8342_Y
- attribute \src "libresoc.v:156146.17-156146.92"
- wire $not$libresoc.v:156146$8345_Y
- attribute \src "libresoc.v:156140.18-156140.98"
- wire $or$libresoc.v:156140$8339_Y
- attribute \src "libresoc.v:156142.18-156142.99"
- wire $or$libresoc.v:156142$8341_Y
- attribute \src "libresoc.v:156145.17-156145.97"
- wire $or$libresoc.v:156145$8344_Y
+ attribute \src "libresoc.v:153940.17-153940.96"
+ wire $and$libresoc.v:153940$8252_Y
+ attribute \src "libresoc.v:153945.17-153945.96"
+ wire $and$libresoc.v:153945$8257_Y
+ attribute \src "libresoc.v:153942.18-153942.93"
+ wire $not$libresoc.v:153942$8254_Y
+ attribute \src "libresoc.v:153944.17-153944.92"
+ wire $not$libresoc.v:153944$8256_Y
+ attribute \src "libresoc.v:153947.17-153947.92"
+ wire $not$libresoc.v:153947$8259_Y
+ attribute \src "libresoc.v:153941.18-153941.98"
+ wire $or$libresoc.v:153941$8253_Y
+ attribute \src "libresoc.v:153943.18-153943.99"
+ wire $or$libresoc.v:153943$8255_Y
+ attribute \src "libresoc.v:153946.17-153946.97"
+ wire $or$libresoc.v:153946$8258_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156104.7-156104.15"
+ attribute \src "libresoc.v:153905.7-153905.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156139$8338
+ cell $and $and$libresoc.v:153940$8252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156139$8338_Y
+ connect \Y $and$libresoc.v:153940$8252_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156144$8343
+ cell $and $and$libresoc.v:153945$8257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156144$8343_Y
+ connect \Y $and$libresoc.v:153945$8257_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156141$8340
+ cell $not $not$libresoc.v:153942$8254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156141$8340_Y
+ connect \Y $not$libresoc.v:153942$8254_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156143$8342
+ cell $not $not$libresoc.v:153944$8256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156143$8342_Y
+ connect \Y $not$libresoc.v:153944$8256_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156146$8345
+ cell $not $not$libresoc.v:153947$8259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156146$8345_Y
+ connect \Y $not$libresoc.v:153947$8259_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156140$8339
+ cell $or $or$libresoc.v:153941$8253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156140$8339_Y
+ connect \Y $or$libresoc.v:153941$8253_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156142$8341
+ cell $or $or$libresoc.v:153943$8255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156142$8341_Y
+ connect \Y $or$libresoc.v:153943$8255_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156145$8344
+ cell $or $or$libresoc.v:153946$8258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156145$8344_Y
+ connect \Y $or$libresoc.v:153946$8258_Y
end
- attribute \src "libresoc.v:156104.7-156104.20"
- process $proc$libresoc.v:156104$8350
+ attribute \src "libresoc.v:153905.7-153905.20"
+ process $proc$libresoc.v:153905$8264
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156126.7-156126.19"
- process $proc$libresoc.v:156126$8351
+ attribute \src "libresoc.v:153927.7-153927.19"
+ process $proc$libresoc.v:153927$8265
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156147.3-156148.27"
- process $proc$libresoc.v:156147$8346
+ attribute \src "libresoc.v:153948.3-153949.27"
+ process $proc$libresoc.v:153948$8260
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156149.3-156157.6"
- process $proc$libresoc.v:156149$8347
+ attribute \src "libresoc.v:153950.3-153958.6"
+ process $proc$libresoc.v:153950$8261
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8348 $1\q_int$next[0:0]$8349
- attribute \src "libresoc.v:156150.5-156150.29"
+ assign $0\q_int$next[0:0]$8262 $1\q_int$next[0:0]$8263
+ attribute \src "libresoc.v:153951.5-153951.29"
switch \initial
- attribute \src "libresoc.v:156150.9-156150.17"
+ attribute \src "libresoc.v:153951.9-153951.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8349 1'0
+ assign $1\q_int$next[0:0]$8263 1'0
case
- assign $1\q_int$next[0:0]$8349 \$5
+ assign $1\q_int$next[0:0]$8263 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8348
+ update \q_int$next $0\q_int$next[0:0]$8262
end
- connect \$9 $and$libresoc.v:156139$8338_Y
- connect \$11 $or$libresoc.v:156140$8339_Y
- connect \$13 $not$libresoc.v:156141$8340_Y
- connect \$15 $or$libresoc.v:156142$8341_Y
- connect \$1 $not$libresoc.v:156143$8342_Y
- connect \$3 $and$libresoc.v:156144$8343_Y
- connect \$5 $or$libresoc.v:156145$8344_Y
- connect \$7 $not$libresoc.v:156146$8345_Y
+ connect \$9 $and$libresoc.v:153940$8252_Y
+ connect \$11 $or$libresoc.v:153941$8253_Y
+ connect \$13 $not$libresoc.v:153942$8254_Y
+ connect \$15 $or$libresoc.v:153943$8255_Y
+ connect \$1 $not$libresoc.v:153944$8256_Y
+ connect \$3 $and$libresoc.v:153945$8257_Y
+ connect \$5 $or$libresoc.v:153946$8258_Y
+ connect \$7 $not$libresoc.v:153947$8259_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156165.1-156223.10"
+attribute \src "libresoc.v:153966.1-154024.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l"
attribute \generator "nMigen"
module \opc_l$120
- attribute \src "libresoc.v:156166.7-156166.20"
+ attribute \src "libresoc.v:153967.7-153967.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156211.3-156219.6"
- wire $0\q_int$next[0:0]$8362
- attribute \src "libresoc.v:156209.3-156210.27"
+ attribute \src "libresoc.v:154012.3-154020.6"
+ wire $0\q_int$next[0:0]$8276
+ attribute \src "libresoc.v:154010.3-154011.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156211.3-156219.6"
- wire $1\q_int$next[0:0]$8363
- attribute \src "libresoc.v:156188.7-156188.19"
+ attribute \src "libresoc.v:154012.3-154020.6"
+ wire $1\q_int$next[0:0]$8277
+ attribute \src "libresoc.v:153989.7-153989.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156201.17-156201.96"
- wire $and$libresoc.v:156201$8352_Y
- attribute \src "libresoc.v:156206.17-156206.96"
- wire $and$libresoc.v:156206$8357_Y
- attribute \src "libresoc.v:156203.18-156203.93"
- wire $not$libresoc.v:156203$8354_Y
- attribute \src "libresoc.v:156205.17-156205.92"
- wire $not$libresoc.v:156205$8356_Y
- attribute \src "libresoc.v:156208.17-156208.92"
- wire $not$libresoc.v:156208$8359_Y
- attribute \src "libresoc.v:156202.18-156202.98"
- wire $or$libresoc.v:156202$8353_Y
- attribute \src "libresoc.v:156204.18-156204.99"
- wire $or$libresoc.v:156204$8355_Y
- attribute \src "libresoc.v:156207.17-156207.97"
- wire $or$libresoc.v:156207$8358_Y
+ attribute \src "libresoc.v:154002.17-154002.96"
+ wire $and$libresoc.v:154002$8266_Y
+ attribute \src "libresoc.v:154007.17-154007.96"
+ wire $and$libresoc.v:154007$8271_Y
+ attribute \src "libresoc.v:154004.18-154004.93"
+ wire $not$libresoc.v:154004$8268_Y
+ attribute \src "libresoc.v:154006.17-154006.92"
+ wire $not$libresoc.v:154006$8270_Y
+ attribute \src "libresoc.v:154009.17-154009.92"
+ wire $not$libresoc.v:154009$8273_Y
+ attribute \src "libresoc.v:154003.18-154003.98"
+ wire $or$libresoc.v:154003$8267_Y
+ attribute \src "libresoc.v:154005.18-154005.99"
+ wire $or$libresoc.v:154005$8269_Y
+ attribute \src "libresoc.v:154008.17-154008.97"
+ wire $or$libresoc.v:154008$8272_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156166.7-156166.15"
+ attribute \src "libresoc.v:153967.7-153967.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156201$8352
+ cell $and $and$libresoc.v:154002$8266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156201$8352_Y
+ connect \Y $and$libresoc.v:154002$8266_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156206$8357
+ cell $and $and$libresoc.v:154007$8271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156206$8357_Y
+ connect \Y $and$libresoc.v:154007$8271_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156203$8354
+ cell $not $not$libresoc.v:154004$8268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156203$8354_Y
+ connect \Y $not$libresoc.v:154004$8268_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156205$8356
+ cell $not $not$libresoc.v:154006$8270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156205$8356_Y
+ connect \Y $not$libresoc.v:154006$8270_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156208$8359
+ cell $not $not$libresoc.v:154009$8273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156208$8359_Y
+ connect \Y $not$libresoc.v:154009$8273_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156202$8353
+ cell $or $or$libresoc.v:154003$8267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156202$8353_Y
+ connect \Y $or$libresoc.v:154003$8267_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156204$8355
+ cell $or $or$libresoc.v:154005$8269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156204$8355_Y
+ connect \Y $or$libresoc.v:154005$8269_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156207$8358
+ cell $or $or$libresoc.v:154008$8272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156207$8358_Y
+ connect \Y $or$libresoc.v:154008$8272_Y
end
- attribute \src "libresoc.v:156166.7-156166.20"
- process $proc$libresoc.v:156166$8364
+ attribute \src "libresoc.v:153967.7-153967.20"
+ process $proc$libresoc.v:153967$8278
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156188.7-156188.19"
- process $proc$libresoc.v:156188$8365
+ attribute \src "libresoc.v:153989.7-153989.19"
+ process $proc$libresoc.v:153989$8279
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156209.3-156210.27"
- process $proc$libresoc.v:156209$8360
+ attribute \src "libresoc.v:154010.3-154011.27"
+ process $proc$libresoc.v:154010$8274
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156211.3-156219.6"
- process $proc$libresoc.v:156211$8361
+ attribute \src "libresoc.v:154012.3-154020.6"
+ process $proc$libresoc.v:154012$8275
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8362 $1\q_int$next[0:0]$8363
- attribute \src "libresoc.v:156212.5-156212.29"
+ assign $0\q_int$next[0:0]$8276 $1\q_int$next[0:0]$8277
+ attribute \src "libresoc.v:154013.5-154013.29"
switch \initial
- attribute \src "libresoc.v:156212.9-156212.17"
+ attribute \src "libresoc.v:154013.9-154013.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8363 1'0
+ assign $1\q_int$next[0:0]$8277 1'0
case
- assign $1\q_int$next[0:0]$8363 \$5
+ assign $1\q_int$next[0:0]$8277 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8362
+ update \q_int$next $0\q_int$next[0:0]$8276
end
- connect \$9 $and$libresoc.v:156201$8352_Y
- connect \$11 $or$libresoc.v:156202$8353_Y
- connect \$13 $not$libresoc.v:156203$8354_Y
- connect \$15 $or$libresoc.v:156204$8355_Y
- connect \$1 $not$libresoc.v:156205$8356_Y
- connect \$3 $and$libresoc.v:156206$8357_Y
- connect \$5 $or$libresoc.v:156207$8358_Y
- connect \$7 $not$libresoc.v:156208$8359_Y
+ connect \$9 $and$libresoc.v:154002$8266_Y
+ connect \$11 $or$libresoc.v:154003$8267_Y
+ connect \$13 $not$libresoc.v:154004$8268_Y
+ connect \$15 $or$libresoc.v:154005$8269_Y
+ connect \$1 $not$libresoc.v:154006$8270_Y
+ connect \$3 $and$libresoc.v:154007$8271_Y
+ connect \$5 $or$libresoc.v:154008$8272_Y
+ connect \$7 $not$libresoc.v:154009$8273_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156227.1-156285.10"
+attribute \src "libresoc.v:154028.1-154086.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l"
attribute \generator "nMigen"
module \opc_l$126
- attribute \src "libresoc.v:156228.7-156228.20"
+ attribute \src "libresoc.v:154029.7-154029.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156273.3-156281.6"
- wire $0\q_int$next[0:0]$8376
- attribute \src "libresoc.v:156271.3-156272.27"
+ attribute \src "libresoc.v:154074.3-154082.6"
+ wire $0\q_int$next[0:0]$8290
+ attribute \src "libresoc.v:154072.3-154073.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156273.3-156281.6"
- wire $1\q_int$next[0:0]$8377
- attribute \src "libresoc.v:156250.7-156250.19"
+ attribute \src "libresoc.v:154074.3-154082.6"
+ wire $1\q_int$next[0:0]$8291
+ attribute \src "libresoc.v:154051.7-154051.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156263.17-156263.96"
- wire $and$libresoc.v:156263$8366_Y
- attribute \src "libresoc.v:156268.17-156268.96"
- wire $and$libresoc.v:156268$8371_Y
- attribute \src "libresoc.v:156265.18-156265.93"
- wire $not$libresoc.v:156265$8368_Y
- attribute \src "libresoc.v:156267.17-156267.92"
- wire $not$libresoc.v:156267$8370_Y
- attribute \src "libresoc.v:156270.17-156270.92"
- wire $not$libresoc.v:156270$8373_Y
- attribute \src "libresoc.v:156264.18-156264.98"
- wire $or$libresoc.v:156264$8367_Y
- attribute \src "libresoc.v:156266.18-156266.99"
- wire $or$libresoc.v:156266$8369_Y
- attribute \src "libresoc.v:156269.17-156269.97"
- wire $or$libresoc.v:156269$8372_Y
+ attribute \src "libresoc.v:154064.17-154064.96"
+ wire $and$libresoc.v:154064$8280_Y
+ attribute \src "libresoc.v:154069.17-154069.96"
+ wire $and$libresoc.v:154069$8285_Y
+ attribute \src "libresoc.v:154066.18-154066.93"
+ wire $not$libresoc.v:154066$8282_Y
+ attribute \src "libresoc.v:154068.17-154068.92"
+ wire $not$libresoc.v:154068$8284_Y
+ attribute \src "libresoc.v:154071.17-154071.92"
+ wire $not$libresoc.v:154071$8287_Y
+ attribute \src "libresoc.v:154065.18-154065.98"
+ wire $or$libresoc.v:154065$8281_Y
+ attribute \src "libresoc.v:154067.18-154067.99"
+ wire $or$libresoc.v:154067$8283_Y
+ attribute \src "libresoc.v:154070.17-154070.97"
+ wire $or$libresoc.v:154070$8286_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156228.7-156228.15"
+ attribute \src "libresoc.v:154029.7-154029.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156263$8366
+ cell $and $and$libresoc.v:154064$8280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156263$8366_Y
+ connect \Y $and$libresoc.v:154064$8280_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156268$8371
+ cell $and $and$libresoc.v:154069$8285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156268$8371_Y
+ connect \Y $and$libresoc.v:154069$8285_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156265$8368
+ cell $not $not$libresoc.v:154066$8282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156265$8368_Y
+ connect \Y $not$libresoc.v:154066$8282_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156267$8370
+ cell $not $not$libresoc.v:154068$8284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156267$8370_Y
+ connect \Y $not$libresoc.v:154068$8284_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156270$8373
+ cell $not $not$libresoc.v:154071$8287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156270$8373_Y
+ connect \Y $not$libresoc.v:154071$8287_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156264$8367
+ cell $or $or$libresoc.v:154065$8281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156264$8367_Y
+ connect \Y $or$libresoc.v:154065$8281_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156266$8369
+ cell $or $or$libresoc.v:154067$8283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156266$8369_Y
+ connect \Y $or$libresoc.v:154067$8283_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156269$8372
+ cell $or $or$libresoc.v:154070$8286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156269$8372_Y
+ connect \Y $or$libresoc.v:154070$8286_Y
end
- attribute \src "libresoc.v:156228.7-156228.20"
- process $proc$libresoc.v:156228$8378
+ attribute \src "libresoc.v:154029.7-154029.20"
+ process $proc$libresoc.v:154029$8292
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156250.7-156250.19"
- process $proc$libresoc.v:156250$8379
+ attribute \src "libresoc.v:154051.7-154051.19"
+ process $proc$libresoc.v:154051$8293
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156271.3-156272.27"
- process $proc$libresoc.v:156271$8374
+ attribute \src "libresoc.v:154072.3-154073.27"
+ process $proc$libresoc.v:154072$8288
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156273.3-156281.6"
- process $proc$libresoc.v:156273$8375
+ attribute \src "libresoc.v:154074.3-154082.6"
+ process $proc$libresoc.v:154074$8289
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8376 $1\q_int$next[0:0]$8377
- attribute \src "libresoc.v:156274.5-156274.29"
+ assign $0\q_int$next[0:0]$8290 $1\q_int$next[0:0]$8291
+ attribute \src "libresoc.v:154075.5-154075.29"
switch \initial
- attribute \src "libresoc.v:156274.9-156274.17"
+ attribute \src "libresoc.v:154075.9-154075.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8377 1'0
+ assign $1\q_int$next[0:0]$8291 1'0
case
- assign $1\q_int$next[0:0]$8377 \$5
+ assign $1\q_int$next[0:0]$8291 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8376
+ update \q_int$next $0\q_int$next[0:0]$8290
end
- connect \$9 $and$libresoc.v:156263$8366_Y
- connect \$11 $or$libresoc.v:156264$8367_Y
- connect \$13 $not$libresoc.v:156265$8368_Y
- connect \$15 $or$libresoc.v:156266$8369_Y
- connect \$1 $not$libresoc.v:156267$8370_Y
- connect \$3 $and$libresoc.v:156268$8371_Y
- connect \$5 $or$libresoc.v:156269$8372_Y
- connect \$7 $not$libresoc.v:156270$8373_Y
+ connect \$9 $and$libresoc.v:154064$8280_Y
+ connect \$11 $or$libresoc.v:154065$8281_Y
+ connect \$13 $not$libresoc.v:154066$8282_Y
+ connect \$15 $or$libresoc.v:154067$8283_Y
+ connect \$1 $not$libresoc.v:154068$8284_Y
+ connect \$3 $and$libresoc.v:154069$8285_Y
+ connect \$5 $or$libresoc.v:154070$8286_Y
+ connect \$7 $not$libresoc.v:154071$8287_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156289.1-156347.10"
+attribute \src "libresoc.v:154090.1-154148.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l"
attribute \generator "nMigen"
module \opc_l$24
- attribute \src "libresoc.v:156290.7-156290.20"
+ attribute \src "libresoc.v:154091.7-154091.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156335.3-156343.6"
- wire $0\q_int$next[0:0]$8390
- attribute \src "libresoc.v:156333.3-156334.27"
+ attribute \src "libresoc.v:154136.3-154144.6"
+ wire $0\q_int$next[0:0]$8304
+ attribute \src "libresoc.v:154134.3-154135.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156335.3-156343.6"
- wire $1\q_int$next[0:0]$8391
- attribute \src "libresoc.v:156312.7-156312.19"
+ attribute \src "libresoc.v:154136.3-154144.6"
+ wire $1\q_int$next[0:0]$8305
+ attribute \src "libresoc.v:154113.7-154113.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156325.17-156325.96"
- wire $and$libresoc.v:156325$8380_Y
- attribute \src "libresoc.v:156330.17-156330.96"
- wire $and$libresoc.v:156330$8385_Y
- attribute \src "libresoc.v:156327.18-156327.93"
- wire $not$libresoc.v:156327$8382_Y
- attribute \src "libresoc.v:156329.17-156329.92"
- wire $not$libresoc.v:156329$8384_Y
- attribute \src "libresoc.v:156332.17-156332.92"
- wire $not$libresoc.v:156332$8387_Y
- attribute \src "libresoc.v:156326.18-156326.98"
- wire $or$libresoc.v:156326$8381_Y
- attribute \src "libresoc.v:156328.18-156328.99"
- wire $or$libresoc.v:156328$8383_Y
- attribute \src "libresoc.v:156331.17-156331.97"
- wire $or$libresoc.v:156331$8386_Y
+ attribute \src "libresoc.v:154126.17-154126.96"
+ wire $and$libresoc.v:154126$8294_Y
+ attribute \src "libresoc.v:154131.17-154131.96"
+ wire $and$libresoc.v:154131$8299_Y
+ attribute \src "libresoc.v:154128.18-154128.93"
+ wire $not$libresoc.v:154128$8296_Y
+ attribute \src "libresoc.v:154130.17-154130.92"
+ wire $not$libresoc.v:154130$8298_Y
+ attribute \src "libresoc.v:154133.17-154133.92"
+ wire $not$libresoc.v:154133$8301_Y
+ attribute \src "libresoc.v:154127.18-154127.98"
+ wire $or$libresoc.v:154127$8295_Y
+ attribute \src "libresoc.v:154129.18-154129.99"
+ wire $or$libresoc.v:154129$8297_Y
+ attribute \src "libresoc.v:154132.17-154132.97"
+ wire $or$libresoc.v:154132$8300_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156290.7-156290.15"
+ attribute \src "libresoc.v:154091.7-154091.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156325$8380
+ cell $and $and$libresoc.v:154126$8294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156325$8380_Y
+ connect \Y $and$libresoc.v:154126$8294_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156330$8385
+ cell $and $and$libresoc.v:154131$8299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156330$8385_Y
+ connect \Y $and$libresoc.v:154131$8299_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156327$8382
+ cell $not $not$libresoc.v:154128$8296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156327$8382_Y
+ connect \Y $not$libresoc.v:154128$8296_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156329$8384
+ cell $not $not$libresoc.v:154130$8298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156329$8384_Y
+ connect \Y $not$libresoc.v:154130$8298_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156332$8387
+ cell $not $not$libresoc.v:154133$8301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156332$8387_Y
+ connect \Y $not$libresoc.v:154133$8301_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156326$8381
+ cell $or $or$libresoc.v:154127$8295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156326$8381_Y
+ connect \Y $or$libresoc.v:154127$8295_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156328$8383
+ cell $or $or$libresoc.v:154129$8297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156328$8383_Y
+ connect \Y $or$libresoc.v:154129$8297_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156331$8386
+ cell $or $or$libresoc.v:154132$8300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156331$8386_Y
+ connect \Y $or$libresoc.v:154132$8300_Y
end
- attribute \src "libresoc.v:156290.7-156290.20"
- process $proc$libresoc.v:156290$8392
+ attribute \src "libresoc.v:154091.7-154091.20"
+ process $proc$libresoc.v:154091$8306
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156312.7-156312.19"
- process $proc$libresoc.v:156312$8393
+ attribute \src "libresoc.v:154113.7-154113.19"
+ process $proc$libresoc.v:154113$8307
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156333.3-156334.27"
- process $proc$libresoc.v:156333$8388
+ attribute \src "libresoc.v:154134.3-154135.27"
+ process $proc$libresoc.v:154134$8302
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156335.3-156343.6"
- process $proc$libresoc.v:156335$8389
+ attribute \src "libresoc.v:154136.3-154144.6"
+ process $proc$libresoc.v:154136$8303
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8390 $1\q_int$next[0:0]$8391
- attribute \src "libresoc.v:156336.5-156336.29"
+ assign $0\q_int$next[0:0]$8304 $1\q_int$next[0:0]$8305
+ attribute \src "libresoc.v:154137.5-154137.29"
switch \initial
- attribute \src "libresoc.v:156336.9-156336.17"
+ attribute \src "libresoc.v:154137.9-154137.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8391 1'0
+ assign $1\q_int$next[0:0]$8305 1'0
case
- assign $1\q_int$next[0:0]$8391 \$5
+ assign $1\q_int$next[0:0]$8305 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8390
+ update \q_int$next $0\q_int$next[0:0]$8304
end
- connect \$9 $and$libresoc.v:156325$8380_Y
- connect \$11 $or$libresoc.v:156326$8381_Y
- connect \$13 $not$libresoc.v:156327$8382_Y
- connect \$15 $or$libresoc.v:156328$8383_Y
- connect \$1 $not$libresoc.v:156329$8384_Y
- connect \$3 $and$libresoc.v:156330$8385_Y
- connect \$5 $or$libresoc.v:156331$8386_Y
- connect \$7 $not$libresoc.v:156332$8387_Y
+ connect \$9 $and$libresoc.v:154126$8294_Y
+ connect \$11 $or$libresoc.v:154127$8295_Y
+ connect \$13 $not$libresoc.v:154128$8296_Y
+ connect \$15 $or$libresoc.v:154129$8297_Y
+ connect \$1 $not$libresoc.v:154130$8298_Y
+ connect \$3 $and$libresoc.v:154131$8299_Y
+ connect \$5 $or$libresoc.v:154132$8300_Y
+ connect \$7 $not$libresoc.v:154133$8301_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156351.1-156409.10"
+attribute \src "libresoc.v:154152.1-154210.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l"
attribute \generator "nMigen"
module \opc_l$40
- attribute \src "libresoc.v:156352.7-156352.20"
+ attribute \src "libresoc.v:154153.7-154153.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156397.3-156405.6"
- wire $0\q_int$next[0:0]$8404
- attribute \src "libresoc.v:156395.3-156396.27"
+ attribute \src "libresoc.v:154198.3-154206.6"
+ wire $0\q_int$next[0:0]$8318
+ attribute \src "libresoc.v:154196.3-154197.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156397.3-156405.6"
- wire $1\q_int$next[0:0]$8405
- attribute \src "libresoc.v:156374.7-156374.19"
+ attribute \src "libresoc.v:154198.3-154206.6"
+ wire $1\q_int$next[0:0]$8319
+ attribute \src "libresoc.v:154175.7-154175.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156387.17-156387.96"
- wire $and$libresoc.v:156387$8394_Y
- attribute \src "libresoc.v:156392.17-156392.96"
- wire $and$libresoc.v:156392$8399_Y
- attribute \src "libresoc.v:156389.18-156389.93"
- wire $not$libresoc.v:156389$8396_Y
- attribute \src "libresoc.v:156391.17-156391.92"
- wire $not$libresoc.v:156391$8398_Y
- attribute \src "libresoc.v:156394.17-156394.92"
- wire $not$libresoc.v:156394$8401_Y
- attribute \src "libresoc.v:156388.18-156388.98"
- wire $or$libresoc.v:156388$8395_Y
- attribute \src "libresoc.v:156390.18-156390.99"
- wire $or$libresoc.v:156390$8397_Y
- attribute \src "libresoc.v:156393.17-156393.97"
- wire $or$libresoc.v:156393$8400_Y
+ attribute \src "libresoc.v:154188.17-154188.96"
+ wire $and$libresoc.v:154188$8308_Y
+ attribute \src "libresoc.v:154193.17-154193.96"
+ wire $and$libresoc.v:154193$8313_Y
+ attribute \src "libresoc.v:154190.18-154190.93"
+ wire $not$libresoc.v:154190$8310_Y
+ attribute \src "libresoc.v:154192.17-154192.92"
+ wire $not$libresoc.v:154192$8312_Y
+ attribute \src "libresoc.v:154195.17-154195.92"
+ wire $not$libresoc.v:154195$8315_Y
+ attribute \src "libresoc.v:154189.18-154189.98"
+ wire $or$libresoc.v:154189$8309_Y
+ attribute \src "libresoc.v:154191.18-154191.99"
+ wire $or$libresoc.v:154191$8311_Y
+ attribute \src "libresoc.v:154194.17-154194.97"
+ wire $or$libresoc.v:154194$8314_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156352.7-156352.15"
+ attribute \src "libresoc.v:154153.7-154153.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156387$8394
+ cell $and $and$libresoc.v:154188$8308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156387$8394_Y
+ connect \Y $and$libresoc.v:154188$8308_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156392$8399
+ cell $and $and$libresoc.v:154193$8313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156392$8399_Y
+ connect \Y $and$libresoc.v:154193$8313_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156389$8396
+ cell $not $not$libresoc.v:154190$8310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156389$8396_Y
+ connect \Y $not$libresoc.v:154190$8310_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156391$8398
+ cell $not $not$libresoc.v:154192$8312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156391$8398_Y
+ connect \Y $not$libresoc.v:154192$8312_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156394$8401
+ cell $not $not$libresoc.v:154195$8315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156394$8401_Y
+ connect \Y $not$libresoc.v:154195$8315_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156388$8395
+ cell $or $or$libresoc.v:154189$8309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156388$8395_Y
+ connect \Y $or$libresoc.v:154189$8309_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156390$8397
+ cell $or $or$libresoc.v:154191$8311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156390$8397_Y
+ connect \Y $or$libresoc.v:154191$8311_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156393$8400
+ cell $or $or$libresoc.v:154194$8314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156393$8400_Y
+ connect \Y $or$libresoc.v:154194$8314_Y
end
- attribute \src "libresoc.v:156352.7-156352.20"
- process $proc$libresoc.v:156352$8406
+ attribute \src "libresoc.v:154153.7-154153.20"
+ process $proc$libresoc.v:154153$8320
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156374.7-156374.19"
- process $proc$libresoc.v:156374$8407
+ attribute \src "libresoc.v:154175.7-154175.19"
+ process $proc$libresoc.v:154175$8321
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156395.3-156396.27"
- process $proc$libresoc.v:156395$8402
+ attribute \src "libresoc.v:154196.3-154197.27"
+ process $proc$libresoc.v:154196$8316
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156397.3-156405.6"
- process $proc$libresoc.v:156397$8403
+ attribute \src "libresoc.v:154198.3-154206.6"
+ process $proc$libresoc.v:154198$8317
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8404 $1\q_int$next[0:0]$8405
- attribute \src "libresoc.v:156398.5-156398.29"
+ assign $0\q_int$next[0:0]$8318 $1\q_int$next[0:0]$8319
+ attribute \src "libresoc.v:154199.5-154199.29"
switch \initial
- attribute \src "libresoc.v:156398.9-156398.17"
+ attribute \src "libresoc.v:154199.9-154199.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8405 1'0
+ assign $1\q_int$next[0:0]$8319 1'0
case
- assign $1\q_int$next[0:0]$8405 \$5
+ assign $1\q_int$next[0:0]$8319 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8404
+ update \q_int$next $0\q_int$next[0:0]$8318
end
- connect \$9 $and$libresoc.v:156387$8394_Y
- connect \$11 $or$libresoc.v:156388$8395_Y
- connect \$13 $not$libresoc.v:156389$8396_Y
- connect \$15 $or$libresoc.v:156390$8397_Y
- connect \$1 $not$libresoc.v:156391$8398_Y
- connect \$3 $and$libresoc.v:156392$8399_Y
- connect \$5 $or$libresoc.v:156393$8400_Y
- connect \$7 $not$libresoc.v:156394$8401_Y
+ connect \$9 $and$libresoc.v:154188$8308_Y
+ connect \$11 $or$libresoc.v:154189$8309_Y
+ connect \$13 $not$libresoc.v:154190$8310_Y
+ connect \$15 $or$libresoc.v:154191$8311_Y
+ connect \$1 $not$libresoc.v:154192$8312_Y
+ connect \$3 $and$libresoc.v:154193$8313_Y
+ connect \$5 $or$libresoc.v:154194$8314_Y
+ connect \$7 $not$libresoc.v:154195$8315_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156413.1-156471.10"
+attribute \src "libresoc.v:154214.1-154272.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l"
attribute \generator "nMigen"
module \opc_l$56
- attribute \src "libresoc.v:156414.7-156414.20"
+ attribute \src "libresoc.v:154215.7-154215.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156459.3-156467.6"
- wire $0\q_int$next[0:0]$8418
- attribute \src "libresoc.v:156457.3-156458.27"
+ attribute \src "libresoc.v:154260.3-154268.6"
+ wire $0\q_int$next[0:0]$8332
+ attribute \src "libresoc.v:154258.3-154259.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156459.3-156467.6"
- wire $1\q_int$next[0:0]$8419
- attribute \src "libresoc.v:156436.7-156436.19"
+ attribute \src "libresoc.v:154260.3-154268.6"
+ wire $1\q_int$next[0:0]$8333
+ attribute \src "libresoc.v:154237.7-154237.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156449.17-156449.96"
- wire $and$libresoc.v:156449$8408_Y
- attribute \src "libresoc.v:156454.17-156454.96"
- wire $and$libresoc.v:156454$8413_Y
- attribute \src "libresoc.v:156451.18-156451.93"
- wire $not$libresoc.v:156451$8410_Y
- attribute \src "libresoc.v:156453.17-156453.92"
- wire $not$libresoc.v:156453$8412_Y
- attribute \src "libresoc.v:156456.17-156456.92"
- wire $not$libresoc.v:156456$8415_Y
- attribute \src "libresoc.v:156450.18-156450.98"
- wire $or$libresoc.v:156450$8409_Y
- attribute \src "libresoc.v:156452.18-156452.99"
- wire $or$libresoc.v:156452$8411_Y
- attribute \src "libresoc.v:156455.17-156455.97"
- wire $or$libresoc.v:156455$8414_Y
+ attribute \src "libresoc.v:154250.17-154250.96"
+ wire $and$libresoc.v:154250$8322_Y
+ attribute \src "libresoc.v:154255.17-154255.96"
+ wire $and$libresoc.v:154255$8327_Y
+ attribute \src "libresoc.v:154252.18-154252.93"
+ wire $not$libresoc.v:154252$8324_Y
+ attribute \src "libresoc.v:154254.17-154254.92"
+ wire $not$libresoc.v:154254$8326_Y
+ attribute \src "libresoc.v:154257.17-154257.92"
+ wire $not$libresoc.v:154257$8329_Y
+ attribute \src "libresoc.v:154251.18-154251.98"
+ wire $or$libresoc.v:154251$8323_Y
+ attribute \src "libresoc.v:154253.18-154253.99"
+ wire $or$libresoc.v:154253$8325_Y
+ attribute \src "libresoc.v:154256.17-154256.97"
+ wire $or$libresoc.v:154256$8328_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156414.7-156414.15"
+ attribute \src "libresoc.v:154215.7-154215.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156449$8408
+ cell $and $and$libresoc.v:154250$8322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156449$8408_Y
+ connect \Y $and$libresoc.v:154250$8322_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156454$8413
+ cell $and $and$libresoc.v:154255$8327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156454$8413_Y
+ connect \Y $and$libresoc.v:154255$8327_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156451$8410
+ cell $not $not$libresoc.v:154252$8324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156451$8410_Y
+ connect \Y $not$libresoc.v:154252$8324_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156453$8412
+ cell $not $not$libresoc.v:154254$8326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156453$8412_Y
+ connect \Y $not$libresoc.v:154254$8326_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156456$8415
+ cell $not $not$libresoc.v:154257$8329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156456$8415_Y
+ connect \Y $not$libresoc.v:154257$8329_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156450$8409
+ cell $or $or$libresoc.v:154251$8323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156450$8409_Y
+ connect \Y $or$libresoc.v:154251$8323_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156452$8411
+ cell $or $or$libresoc.v:154253$8325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156452$8411_Y
+ connect \Y $or$libresoc.v:154253$8325_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156455$8414
+ cell $or $or$libresoc.v:154256$8328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156455$8414_Y
+ connect \Y $or$libresoc.v:154256$8328_Y
end
- attribute \src "libresoc.v:156414.7-156414.20"
- process $proc$libresoc.v:156414$8420
+ attribute \src "libresoc.v:154215.7-154215.20"
+ process $proc$libresoc.v:154215$8334
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156436.7-156436.19"
- process $proc$libresoc.v:156436$8421
+ attribute \src "libresoc.v:154237.7-154237.19"
+ process $proc$libresoc.v:154237$8335
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156457.3-156458.27"
- process $proc$libresoc.v:156457$8416
+ attribute \src "libresoc.v:154258.3-154259.27"
+ process $proc$libresoc.v:154258$8330
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156459.3-156467.6"
- process $proc$libresoc.v:156459$8417
+ attribute \src "libresoc.v:154260.3-154268.6"
+ process $proc$libresoc.v:154260$8331
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8418 $1\q_int$next[0:0]$8419
- attribute \src "libresoc.v:156460.5-156460.29"
+ assign $0\q_int$next[0:0]$8332 $1\q_int$next[0:0]$8333
+ attribute \src "libresoc.v:154261.5-154261.29"
switch \initial
- attribute \src "libresoc.v:156460.9-156460.17"
+ attribute \src "libresoc.v:154261.9-154261.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8419 1'0
+ assign $1\q_int$next[0:0]$8333 1'0
case
- assign $1\q_int$next[0:0]$8419 \$5
+ assign $1\q_int$next[0:0]$8333 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8418
+ update \q_int$next $0\q_int$next[0:0]$8332
end
- connect \$9 $and$libresoc.v:156449$8408_Y
- connect \$11 $or$libresoc.v:156450$8409_Y
- connect \$13 $not$libresoc.v:156451$8410_Y
- connect \$15 $or$libresoc.v:156452$8411_Y
- connect \$1 $not$libresoc.v:156453$8412_Y
- connect \$3 $and$libresoc.v:156454$8413_Y
- connect \$5 $or$libresoc.v:156455$8414_Y
- connect \$7 $not$libresoc.v:156456$8415_Y
+ connect \$9 $and$libresoc.v:154250$8322_Y
+ connect \$11 $or$libresoc.v:154251$8323_Y
+ connect \$13 $not$libresoc.v:154252$8324_Y
+ connect \$15 $or$libresoc.v:154253$8325_Y
+ connect \$1 $not$libresoc.v:154254$8326_Y
+ connect \$3 $and$libresoc.v:154255$8327_Y
+ connect \$5 $or$libresoc.v:154256$8328_Y
+ connect \$7 $not$libresoc.v:154257$8329_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156475.1-156533.10"
+attribute \src "libresoc.v:154276.1-154334.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l"
attribute \generator "nMigen"
module \opc_l$68
- attribute \src "libresoc.v:156476.7-156476.20"
+ attribute \src "libresoc.v:154277.7-154277.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156521.3-156529.6"
- wire $0\q_int$next[0:0]$8432
- attribute \src "libresoc.v:156519.3-156520.27"
+ attribute \src "libresoc.v:154322.3-154330.6"
+ wire $0\q_int$next[0:0]$8346
+ attribute \src "libresoc.v:154320.3-154321.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156521.3-156529.6"
- wire $1\q_int$next[0:0]$8433
- attribute \src "libresoc.v:156498.7-156498.19"
+ attribute \src "libresoc.v:154322.3-154330.6"
+ wire $1\q_int$next[0:0]$8347
+ attribute \src "libresoc.v:154299.7-154299.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156511.17-156511.96"
- wire $and$libresoc.v:156511$8422_Y
- attribute \src "libresoc.v:156516.17-156516.96"
- wire $and$libresoc.v:156516$8427_Y
- attribute \src "libresoc.v:156513.18-156513.93"
- wire $not$libresoc.v:156513$8424_Y
- attribute \src "libresoc.v:156515.17-156515.92"
- wire $not$libresoc.v:156515$8426_Y
- attribute \src "libresoc.v:156518.17-156518.92"
- wire $not$libresoc.v:156518$8429_Y
- attribute \src "libresoc.v:156512.18-156512.98"
- wire $or$libresoc.v:156512$8423_Y
- attribute \src "libresoc.v:156514.18-156514.99"
- wire $or$libresoc.v:156514$8425_Y
- attribute \src "libresoc.v:156517.17-156517.97"
- wire $or$libresoc.v:156517$8428_Y
+ attribute \src "libresoc.v:154312.17-154312.96"
+ wire $and$libresoc.v:154312$8336_Y
+ attribute \src "libresoc.v:154317.17-154317.96"
+ wire $and$libresoc.v:154317$8341_Y
+ attribute \src "libresoc.v:154314.18-154314.93"
+ wire $not$libresoc.v:154314$8338_Y
+ attribute \src "libresoc.v:154316.17-154316.92"
+ wire $not$libresoc.v:154316$8340_Y
+ attribute \src "libresoc.v:154319.17-154319.92"
+ wire $not$libresoc.v:154319$8343_Y
+ attribute \src "libresoc.v:154313.18-154313.98"
+ wire $or$libresoc.v:154313$8337_Y
+ attribute \src "libresoc.v:154315.18-154315.99"
+ wire $or$libresoc.v:154315$8339_Y
+ attribute \src "libresoc.v:154318.17-154318.97"
+ wire $or$libresoc.v:154318$8342_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156476.7-156476.15"
+ attribute \src "libresoc.v:154277.7-154277.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156511$8422
+ cell $and $and$libresoc.v:154312$8336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156511$8422_Y
+ connect \Y $and$libresoc.v:154312$8336_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156516$8427
+ cell $and $and$libresoc.v:154317$8341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156516$8427_Y
+ connect \Y $and$libresoc.v:154317$8341_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156513$8424
+ cell $not $not$libresoc.v:154314$8338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156513$8424_Y
+ connect \Y $not$libresoc.v:154314$8338_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156515$8426
+ cell $not $not$libresoc.v:154316$8340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156515$8426_Y
+ connect \Y $not$libresoc.v:154316$8340_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156518$8429
+ cell $not $not$libresoc.v:154319$8343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156518$8429_Y
+ connect \Y $not$libresoc.v:154319$8343_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156512$8423
+ cell $or $or$libresoc.v:154313$8337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156512$8423_Y
+ connect \Y $or$libresoc.v:154313$8337_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156514$8425
+ cell $or $or$libresoc.v:154315$8339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156514$8425_Y
+ connect \Y $or$libresoc.v:154315$8339_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156517$8428
+ cell $or $or$libresoc.v:154318$8342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156517$8428_Y
+ connect \Y $or$libresoc.v:154318$8342_Y
end
- attribute \src "libresoc.v:156476.7-156476.20"
- process $proc$libresoc.v:156476$8434
+ attribute \src "libresoc.v:154277.7-154277.20"
+ process $proc$libresoc.v:154277$8348
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156498.7-156498.19"
- process $proc$libresoc.v:156498$8435
+ attribute \src "libresoc.v:154299.7-154299.19"
+ process $proc$libresoc.v:154299$8349
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156519.3-156520.27"
- process $proc$libresoc.v:156519$8430
+ attribute \src "libresoc.v:154320.3-154321.27"
+ process $proc$libresoc.v:154320$8344
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156521.3-156529.6"
- process $proc$libresoc.v:156521$8431
+ attribute \src "libresoc.v:154322.3-154330.6"
+ process $proc$libresoc.v:154322$8345
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8432 $1\q_int$next[0:0]$8433
- attribute \src "libresoc.v:156522.5-156522.29"
+ assign $0\q_int$next[0:0]$8346 $1\q_int$next[0:0]$8347
+ attribute \src "libresoc.v:154323.5-154323.29"
switch \initial
- attribute \src "libresoc.v:156522.9-156522.17"
+ attribute \src "libresoc.v:154323.9-154323.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8433 1'0
+ assign $1\q_int$next[0:0]$8347 1'0
case
- assign $1\q_int$next[0:0]$8433 \$5
+ assign $1\q_int$next[0:0]$8347 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8432
+ update \q_int$next $0\q_int$next[0:0]$8346
end
- connect \$9 $and$libresoc.v:156511$8422_Y
- connect \$11 $or$libresoc.v:156512$8423_Y
- connect \$13 $not$libresoc.v:156513$8424_Y
- connect \$15 $or$libresoc.v:156514$8425_Y
- connect \$1 $not$libresoc.v:156515$8426_Y
- connect \$3 $and$libresoc.v:156516$8427_Y
- connect \$5 $or$libresoc.v:156517$8428_Y
- connect \$7 $not$libresoc.v:156518$8429_Y
+ connect \$9 $and$libresoc.v:154312$8336_Y
+ connect \$11 $or$libresoc.v:154313$8337_Y
+ connect \$13 $not$libresoc.v:154314$8338_Y
+ connect \$15 $or$libresoc.v:154315$8339_Y
+ connect \$1 $not$libresoc.v:154316$8340_Y
+ connect \$3 $and$libresoc.v:154317$8341_Y
+ connect \$5 $or$libresoc.v:154318$8342_Y
+ connect \$7 $not$libresoc.v:154319$8343_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156537.1-156595.10"
+attribute \src "libresoc.v:154338.1-154396.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l"
attribute \generator "nMigen"
module \opc_l$85
- attribute \src "libresoc.v:156538.7-156538.20"
+ attribute \src "libresoc.v:154339.7-154339.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156583.3-156591.6"
- wire $0\q_int$next[0:0]$8446
- attribute \src "libresoc.v:156581.3-156582.27"
+ attribute \src "libresoc.v:154384.3-154392.6"
+ wire $0\q_int$next[0:0]$8360
+ attribute \src "libresoc.v:154382.3-154383.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:156583.3-156591.6"
- wire $1\q_int$next[0:0]$8447
- attribute \src "libresoc.v:156560.7-156560.19"
+ attribute \src "libresoc.v:154384.3-154392.6"
+ wire $1\q_int$next[0:0]$8361
+ attribute \src "libresoc.v:154361.7-154361.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:156573.17-156573.96"
- wire $and$libresoc.v:156573$8436_Y
- attribute \src "libresoc.v:156578.17-156578.96"
- wire $and$libresoc.v:156578$8441_Y
- attribute \src "libresoc.v:156575.18-156575.93"
- wire $not$libresoc.v:156575$8438_Y
- attribute \src "libresoc.v:156577.17-156577.92"
- wire $not$libresoc.v:156577$8440_Y
- attribute \src "libresoc.v:156580.17-156580.92"
- wire $not$libresoc.v:156580$8443_Y
- attribute \src "libresoc.v:156574.18-156574.98"
- wire $or$libresoc.v:156574$8437_Y
- attribute \src "libresoc.v:156576.18-156576.99"
- wire $or$libresoc.v:156576$8439_Y
- attribute \src "libresoc.v:156579.17-156579.97"
- wire $or$libresoc.v:156579$8442_Y
+ attribute \src "libresoc.v:154374.17-154374.96"
+ wire $and$libresoc.v:154374$8350_Y
+ attribute \src "libresoc.v:154379.17-154379.96"
+ wire $and$libresoc.v:154379$8355_Y
+ attribute \src "libresoc.v:154376.18-154376.93"
+ wire $not$libresoc.v:154376$8352_Y
+ attribute \src "libresoc.v:154378.17-154378.92"
+ wire $not$libresoc.v:154378$8354_Y
+ attribute \src "libresoc.v:154381.17-154381.92"
+ wire $not$libresoc.v:154381$8357_Y
+ attribute \src "libresoc.v:154375.18-154375.98"
+ wire $or$libresoc.v:154375$8351_Y
+ attribute \src "libresoc.v:154377.18-154377.99"
+ wire $or$libresoc.v:154377$8353_Y
+ attribute \src "libresoc.v:154380.17-154380.97"
+ wire $or$libresoc.v:154380$8356_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:156538.7-156538.15"
+ attribute \src "libresoc.v:154339.7-154339.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:156573$8436
+ cell $and $and$libresoc.v:154374$8350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:156573$8436_Y
+ connect \Y $and$libresoc.v:154374$8350_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:156578$8441
+ cell $and $and$libresoc.v:154379$8355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:156578$8441_Y
+ connect \Y $and$libresoc.v:154379$8355_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:156575$8438
+ cell $not $not$libresoc.v:154376$8352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_opc
- connect \Y $not$libresoc.v:156575$8438_Y
+ connect \Y $not$libresoc.v:154376$8352_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:156577$8440
+ cell $not $not$libresoc.v:154378$8354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156577$8440_Y
+ connect \Y $not$libresoc.v:154378$8354_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:156580$8443
+ cell $not $not$libresoc.v:154381$8357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_opc
- connect \Y $not$libresoc.v:156580$8443_Y
+ connect \Y $not$libresoc.v:154381$8357_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:156574$8437
+ cell $or $or$libresoc.v:154375$8351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_opc
- connect \Y $or$libresoc.v:156574$8437_Y
+ connect \Y $or$libresoc.v:154375$8351_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:156576$8439
+ cell $or $or$libresoc.v:154377$8353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_opc
connect \B \q_int
- connect \Y $or$libresoc.v:156576$8439_Y
+ connect \Y $or$libresoc.v:154377$8353_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:156579$8442
+ cell $or $or$libresoc.v:154380$8356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_opc
- connect \Y $or$libresoc.v:156579$8442_Y
+ connect \Y $or$libresoc.v:154380$8356_Y
end
- attribute \src "libresoc.v:156538.7-156538.20"
- process $proc$libresoc.v:156538$8448
+ attribute \src "libresoc.v:154339.7-154339.20"
+ process $proc$libresoc.v:154339$8362
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156560.7-156560.19"
- process $proc$libresoc.v:156560$8449
+ attribute \src "libresoc.v:154361.7-154361.19"
+ process $proc$libresoc.v:154361$8363
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:156581.3-156582.27"
- process $proc$libresoc.v:156581$8444
+ attribute \src "libresoc.v:154382.3-154383.27"
+ process $proc$libresoc.v:154382$8358
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:156583.3-156591.6"
- process $proc$libresoc.v:156583$8445
+ attribute \src "libresoc.v:154384.3-154392.6"
+ process $proc$libresoc.v:154384$8359
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$8446 $1\q_int$next[0:0]$8447
- attribute \src "libresoc.v:156584.5-156584.29"
+ assign $0\q_int$next[0:0]$8360 $1\q_int$next[0:0]$8361
+ attribute \src "libresoc.v:154385.5-154385.29"
switch \initial
- attribute \src "libresoc.v:156584.9-156584.17"
+ attribute \src "libresoc.v:154385.9-154385.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$8447 1'0
+ assign $1\q_int$next[0:0]$8361 1'0
case
- assign $1\q_int$next[0:0]$8447 \$5
+ assign $1\q_int$next[0:0]$8361 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$8446
+ update \q_int$next $0\q_int$next[0:0]$8360
end
- connect \$9 $and$libresoc.v:156573$8436_Y
- connect \$11 $or$libresoc.v:156574$8437_Y
- connect \$13 $not$libresoc.v:156575$8438_Y
- connect \$15 $or$libresoc.v:156576$8439_Y
- connect \$1 $not$libresoc.v:156577$8440_Y
- connect \$3 $and$libresoc.v:156578$8441_Y
- connect \$5 $or$libresoc.v:156579$8442_Y
- connect \$7 $not$libresoc.v:156580$8443_Y
+ connect \$9 $and$libresoc.v:154374$8350_Y
+ connect \$11 $or$libresoc.v:154375$8351_Y
+ connect \$13 $not$libresoc.v:154376$8352_Y
+ connect \$15 $or$libresoc.v:154377$8353_Y
+ connect \$1 $not$libresoc.v:154378$8354_Y
+ connect \$3 $and$libresoc.v:154379$8355_Y
+ connect \$5 $or$libresoc.v:154380$8356_Y
+ connect \$7 $not$libresoc.v:154381$8357_Y
connect \qlq_opc \$15
connect \qn_opc \$13
connect \q_opc \$11
end
-attribute \src "libresoc.v:156599.1-157053.10"
+attribute \src "libresoc.v:154400.1-154854.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output"
attribute \generator "nMigen"
module \output
- attribute \src "libresoc.v:156972.3-156983.6"
+ attribute \src "libresoc.v:154773.3-154784.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:156600.7-156600.20"
+ attribute \src "libresoc.v:154401.7-154401.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:156984.3-156995.6"
- wire width 65 $0\o$28[64:0]$8468
- attribute \src "libresoc.v:156960.3-156971.6"
+ attribute \src "libresoc.v:154785.3-154796.6"
+ wire width 65 $0\o$28[64:0]$8382
+ attribute \src "libresoc.v:154761.3-154772.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:157016.3-157025.6"
- wire width 2 $0\xer_ov$24[1:0]$8475
- attribute \src "libresoc.v:157026.3-157035.6"
+ attribute \src "libresoc.v:154817.3-154826.6"
+ wire width 2 $0\xer_ov$24[1:0]$8389
+ attribute \src "libresoc.v:154827.3-154836.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:156996.3-157005.6"
- wire $0\xer_so$25[0:0]$8471
- attribute \src "libresoc.v:157006.3-157015.6"
+ attribute \src "libresoc.v:154797.3-154806.6"
+ wire $0\xer_so$25[0:0]$8385
+ attribute \src "libresoc.v:154807.3-154816.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:156972.3-156983.6"
+ attribute \src "libresoc.v:154773.3-154784.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:156984.3-156995.6"
- wire width 65 $1\o$28[64:0]$8469
- attribute \src "libresoc.v:156960.3-156971.6"
+ attribute \src "libresoc.v:154785.3-154796.6"
+ wire width 65 $1\o$28[64:0]$8383
+ attribute \src "libresoc.v:154761.3-154772.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:157016.3-157025.6"
- wire width 2 $1\xer_ov$24[1:0]$8476
- attribute \src "libresoc.v:157026.3-157035.6"
+ attribute \src "libresoc.v:154817.3-154826.6"
+ wire width 2 $1\xer_ov$24[1:0]$8390
+ attribute \src "libresoc.v:154827.3-154836.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:156996.3-157005.6"
- wire $1\xer_so$25[0:0]$8472
- attribute \src "libresoc.v:157006.3-157015.6"
+ attribute \src "libresoc.v:154797.3-154806.6"
+ wire $1\xer_so$25[0:0]$8386
+ attribute \src "libresoc.v:154807.3-154816.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:156947.18-156947.128"
- wire $and$libresoc.v:156947$8450_Y
- attribute \src "libresoc.v:156955.18-156955.112"
- wire $and$libresoc.v:156955$8460_Y
- attribute \src "libresoc.v:156958.18-156958.125"
- wire $and$libresoc.v:156958$8463_Y
- attribute \src "libresoc.v:156951.18-156951.123"
- wire $eq$libresoc.v:156951$8456_Y
- attribute \src "libresoc.v:156952.18-156952.123"
- wire $eq$libresoc.v:156952$8457_Y
- attribute \src "libresoc.v:156949.18-156949.103"
- wire width 65 $extend$libresoc.v:156949$8452_Y
- attribute \src "libresoc.v:156950.18-156950.101"
- wire width 65 $extend$libresoc.v:156950$8454_Y
- attribute \src "libresoc.v:156948.18-156948.100"
- wire width 64 $not$libresoc.v:156948$8451_Y
- attribute \src "libresoc.v:156954.18-156954.107"
- wire $not$libresoc.v:156954$8459_Y
- attribute \src "libresoc.v:156957.18-156957.107"
- wire $not$libresoc.v:156957$8462_Y
- attribute \src "libresoc.v:156956.18-156956.115"
- wire $or$libresoc.v:156956$8461_Y
- attribute \src "libresoc.v:156959.18-156959.112"
- wire $or$libresoc.v:156959$8464_Y
- attribute \src "libresoc.v:156949.18-156949.103"
- wire width 65 $pos$libresoc.v:156949$8453_Y
- attribute \src "libresoc.v:156950.18-156950.101"
- wire width 65 $pos$libresoc.v:156950$8455_Y
- attribute \src "libresoc.v:156953.18-156953.105"
- wire $reduce_or$libresoc.v:156953$8458_Y
+ attribute \src "libresoc.v:154748.18-154748.128"
+ wire $and$libresoc.v:154748$8364_Y
+ attribute \src "libresoc.v:154756.18-154756.112"
+ wire $and$libresoc.v:154756$8374_Y
+ attribute \src "libresoc.v:154759.18-154759.125"
+ wire $and$libresoc.v:154759$8377_Y
+ attribute \src "libresoc.v:154752.18-154752.123"
+ wire $eq$libresoc.v:154752$8370_Y
+ attribute \src "libresoc.v:154753.18-154753.123"
+ wire $eq$libresoc.v:154753$8371_Y
+ attribute \src "libresoc.v:154750.18-154750.103"
+ wire width 65 $extend$libresoc.v:154750$8366_Y
+ attribute \src "libresoc.v:154751.18-154751.101"
+ wire width 65 $extend$libresoc.v:154751$8368_Y
+ attribute \src "libresoc.v:154749.18-154749.100"
+ wire width 64 $not$libresoc.v:154749$8365_Y
+ attribute \src "libresoc.v:154755.18-154755.107"
+ wire $not$libresoc.v:154755$8373_Y
+ attribute \src "libresoc.v:154758.18-154758.107"
+ wire $not$libresoc.v:154758$8376_Y
+ attribute \src "libresoc.v:154757.18-154757.115"
+ wire $or$libresoc.v:154757$8375_Y
+ attribute \src "libresoc.v:154760.18-154760.112"
+ wire $or$libresoc.v:154760$8378_Y
+ attribute \src "libresoc.v:154750.18-154750.103"
+ wire width 65 $pos$libresoc.v:154750$8367_Y
+ attribute \src "libresoc.v:154751.18-154751.101"
+ wire width 65 $pos$libresoc.v:154751$8369_Y
+ attribute \src "libresoc.v:154754.18-154754.105"
+ wire $reduce_or$libresoc.v:154754$8372_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 46 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 47 \cr_a_ok
- attribute \src "libresoc.v:156600.7-156600.15"
+ attribute \src "libresoc.v:154401.7-154401.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 53 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:156947$8450
+ cell $and $and$libresoc.v:154748$8364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__oe__oe
connect \B \alu_op__oe__ok
- connect \Y $and$libresoc.v:156947$8450_Y
+ connect \Y $and$libresoc.v:154748$8364_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:156955$8460
+ cell $and $and$libresoc.v:154756$8374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$41
- connect \Y $and$libresoc.v:156955$8460_Y
+ connect \Y $and$libresoc.v:154756$8374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:156958$8463
+ cell $and $and$libresoc.v:154759$8377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__oe__oe
connect \B \alu_op__oe__ok
- connect \Y $and$libresoc.v:156958$8463_Y
+ connect \Y $and$libresoc.v:154759$8377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:156951$8456
+ cell $eq $eq$libresoc.v:154752$8370
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:156951$8456_Y
+ connect \Y $eq$libresoc.v:154752$8370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:156952$8457
+ cell $eq $eq$libresoc.v:154753$8371
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:156952$8457_Y
+ connect \Y $eq$libresoc.v:154753$8371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:156949$8452
+ cell $pos $extend$libresoc.v:154750$8366
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$30
- connect \Y $extend$libresoc.v:156949$8452_Y
+ connect \Y $extend$libresoc.v:154750$8366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:156950$8454
+ cell $pos $extend$libresoc.v:154751$8368
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:156950$8454_Y
+ connect \Y $extend$libresoc.v:154751$8368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:156948$8451
+ cell $not $not$libresoc.v:154749$8365
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:156948$8451_Y
+ connect \Y $not$libresoc.v:154749$8365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:156954$8459
+ cell $not $not$libresoc.v:154755$8373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:156954$8459_Y
+ connect \Y $not$libresoc.v:154755$8373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:156957$8462
+ cell $not $not$libresoc.v:154758$8376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:156957$8462_Y
+ connect \Y $not$libresoc.v:154758$8376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:156956$8461
+ cell $or $or$libresoc.v:154757$8375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:156956$8461_Y
+ connect \Y $or$libresoc.v:154757$8375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:156959$8464
+ cell $or $or$libresoc.v:154760$8378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:156959$8464_Y
+ connect \Y $or$libresoc.v:154760$8378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:156949$8453
+ cell $pos $pos$libresoc.v:154750$8367
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:156949$8452_Y
- connect \Y $pos$libresoc.v:156949$8453_Y
+ connect \A $extend$libresoc.v:154750$8366_Y
+ connect \Y $pos$libresoc.v:154750$8367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:156950$8455
+ cell $pos $pos$libresoc.v:154751$8369
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:156950$8454_Y
- connect \Y $pos$libresoc.v:156950$8455_Y
+ connect \A $extend$libresoc.v:154751$8368_Y
+ connect \Y $pos$libresoc.v:154751$8369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:156953$8458
+ cell $reduce_or $reduce_or$libresoc.v:154754$8372
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:156953$8458_Y
+ connect \Y $reduce_or$libresoc.v:154754$8372_Y
end
- attribute \src "libresoc.v:156600.7-156600.20"
- process $proc$libresoc.v:156600$8478
+ attribute \src "libresoc.v:154401.7-154401.20"
+ process $proc$libresoc.v:154401$8392
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:156960.3-156971.6"
- process $proc$libresoc.v:156960$8465
+ attribute \src "libresoc.v:154761.3-154772.6"
+ process $proc$libresoc.v:154761$8379
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:156961.5-156961.29"
+ attribute \src "libresoc.v:154762.5-154762.29"
switch \initial
- attribute \src "libresoc.v:156961.9-156961.17"
+ attribute \src "libresoc.v:154762.9-154762.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:156972.3-156983.6"
- process $proc$libresoc.v:156972$8466
+ attribute \src "libresoc.v:154773.3-154784.6"
+ process $proc$libresoc.v:154773$8380
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:156973.5-156973.29"
+ attribute \src "libresoc.v:154774.5-154774.29"
switch \initial
- attribute \src "libresoc.v:156973.9-156973.17"
+ attribute \src "libresoc.v:154774.9-154774.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:156984.3-156995.6"
- process $proc$libresoc.v:156984$8467
+ attribute \src "libresoc.v:154785.3-154796.6"
+ process $proc$libresoc.v:154785$8381
assign { } { }
- assign $0\o$28[64:0]$8468 $1\o$28[64:0]$8469
- attribute \src "libresoc.v:156985.5-156985.29"
+ assign $0\o$28[64:0]$8382 $1\o$28[64:0]$8383
+ attribute \src "libresoc.v:154786.5-154786.29"
switch \initial
- attribute \src "libresoc.v:156985.9-156985.17"
+ attribute \src "libresoc.v:154786.9-154786.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$28[64:0]$8469 \$29
+ assign $1\o$28[64:0]$8383 \$29
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$28[64:0]$8469 \$33
+ assign $1\o$28[64:0]$8383 \$33
end
sync always
- update \o$28 $0\o$28[64:0]$8468
+ update \o$28 $0\o$28[64:0]$8382
end
- attribute \src "libresoc.v:156996.3-157005.6"
- process $proc$libresoc.v:156996$8470
+ attribute \src "libresoc.v:154797.3-154806.6"
+ process $proc$libresoc.v:154797$8384
assign { } { }
assign { } { }
- assign $0\xer_so$25[0:0]$8471 $1\xer_so$25[0:0]$8472
- attribute \src "libresoc.v:156997.5-156997.29"
+ assign $0\xer_so$25[0:0]$8385 $1\xer_so$25[0:0]$8386
+ attribute \src "libresoc.v:154798.5-154798.29"
switch \initial
- attribute \src "libresoc.v:156997.9-156997.17"
+ attribute \src "libresoc.v:154798.9-154798.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$25[0:0]$8472 \$52
+ assign $1\xer_so$25[0:0]$8386 \$52
case
- assign $1\xer_so$25[0:0]$8472 1'0
+ assign $1\xer_so$25[0:0]$8386 1'0
end
sync always
- update \xer_so$25 $0\xer_so$25[0:0]$8471
+ update \xer_so$25 $0\xer_so$25[0:0]$8385
end
- attribute \src "libresoc.v:157006.3-157015.6"
- process $proc$libresoc.v:157006$8473
+ attribute \src "libresoc.v:154807.3-154816.6"
+ process $proc$libresoc.v:154807$8387
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:157007.5-157007.29"
+ attribute \src "libresoc.v:154808.5-154808.29"
switch \initial
- attribute \src "libresoc.v:157007.9-157007.17"
+ attribute \src "libresoc.v:154808.9-154808.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:157016.3-157025.6"
- process $proc$libresoc.v:157016$8474
+ attribute \src "libresoc.v:154817.3-154826.6"
+ process $proc$libresoc.v:154817$8388
assign { } { }
assign { } { }
- assign $0\xer_ov$24[1:0]$8475 $1\xer_ov$24[1:0]$8476
- attribute \src "libresoc.v:157017.5-157017.29"
+ assign $0\xer_ov$24[1:0]$8389 $1\xer_ov$24[1:0]$8390
+ attribute \src "libresoc.v:154818.5-154818.29"
switch \initial
- attribute \src "libresoc.v:157017.9-157017.17"
+ attribute \src "libresoc.v:154818.9-154818.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$24[1:0]$8476 \xer_ov
+ assign $1\xer_ov$24[1:0]$8390 \xer_ov
case
- assign $1\xer_ov$24[1:0]$8476 2'00
+ assign $1\xer_ov$24[1:0]$8390 2'00
end
sync always
- update \xer_ov$24 $0\xer_ov$24[1:0]$8475
+ update \xer_ov$24 $0\xer_ov$24[1:0]$8389
end
- attribute \src "libresoc.v:157026.3-157035.6"
- process $proc$libresoc.v:157026$8477
+ attribute \src "libresoc.v:154827.3-154836.6"
+ process $proc$libresoc.v:154827$8391
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:157027.5-157027.29"
+ attribute \src "libresoc.v:154828.5-154828.29"
switch \initial
- attribute \src "libresoc.v:157027.9-157027.17"
+ attribute \src "libresoc.v:154828.9-154828.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$26 $and$libresoc.v:156947$8450_Y
- connect \$30 $not$libresoc.v:156948$8451_Y
- connect \$29 $pos$libresoc.v:156949$8453_Y
- connect \$33 $pos$libresoc.v:156950$8455_Y
- connect \$35 $eq$libresoc.v:156951$8456_Y
- connect \$37 $eq$libresoc.v:156952$8457_Y
- connect \$39 $reduce_or$libresoc.v:156953$8458_Y
- connect \$41 $not$libresoc.v:156954$8459_Y
- connect \$43 $and$libresoc.v:156955$8460_Y
- connect \$45 $or$libresoc.v:156956$8461_Y
- connect \$47 $not$libresoc.v:156957$8462_Y
- connect \$50 $and$libresoc.v:156958$8463_Y
- connect \$52 $or$libresoc.v:156959$8464_Y
+ connect \$26 $and$libresoc.v:154748$8364_Y
+ connect \$30 $not$libresoc.v:154749$8365_Y
+ connect \$29 $pos$libresoc.v:154750$8367_Y
+ connect \$33 $pos$libresoc.v:154751$8369_Y
+ connect \$35 $eq$libresoc.v:154752$8370_Y
+ connect \$37 $eq$libresoc.v:154753$8371_Y
+ connect \$39 $reduce_or$libresoc.v:154754$8372_Y
+ connect \$41 $not$libresoc.v:154755$8373_Y
+ connect \$43 $and$libresoc.v:154756$8374_Y
+ connect \$45 $or$libresoc.v:154757$8375_Y
+ connect \$47 $not$libresoc.v:154758$8376_Y
+ connect \$50 $and$libresoc.v:154759$8377_Y
+ connect \$52 $or$libresoc.v:154760$8378_Y
connect \oe$49 \$50
connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \muxid$1 \muxid
connect \target \o$28 [63:0]
connect \oe \$26
end
-attribute \src "libresoc.v:157057.1-157454.10"
+attribute \src "libresoc.v:154858.1-155255.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output"
attribute \generator "nMigen"
module \output$100
- attribute \src "libresoc.v:157386.3-157397.6"
+ attribute \src "libresoc.v:155187.3-155198.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:157058.7-157058.20"
+ attribute \src "libresoc.v:154859.7-154859.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:157374.3-157385.6"
+ attribute \src "libresoc.v:155175.3-155186.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:157418.3-157427.6"
- wire width 2 $0\xer_ov$17[1:0]$8498
- attribute \src "libresoc.v:157428.3-157437.6"
+ attribute \src "libresoc.v:155219.3-155228.6"
+ wire width 2 $0\xer_ov$17[1:0]$8412
+ attribute \src "libresoc.v:155229.3-155238.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:157398.3-157407.6"
- wire $0\xer_so$18[0:0]$8494
- attribute \src "libresoc.v:157408.3-157417.6"
+ attribute \src "libresoc.v:155199.3-155208.6"
+ wire $0\xer_so$18[0:0]$8408
+ attribute \src "libresoc.v:155209.3-155218.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:157386.3-157397.6"
+ attribute \src "libresoc.v:155187.3-155198.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:157374.3-157385.6"
+ attribute \src "libresoc.v:155175.3-155186.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:157418.3-157427.6"
- wire width 2 $1\xer_ov$17[1:0]$8499
- attribute \src "libresoc.v:157428.3-157437.6"
+ attribute \src "libresoc.v:155219.3-155228.6"
+ wire width 2 $1\xer_ov$17[1:0]$8413
+ attribute \src "libresoc.v:155229.3-155238.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:157398.3-157407.6"
- wire $1\xer_so$18[0:0]$8495
- attribute \src "libresoc.v:157408.3-157417.6"
+ attribute \src "libresoc.v:155199.3-155208.6"
+ wire $1\xer_so$18[0:0]$8409
+ attribute \src "libresoc.v:155209.3-155218.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:157363.18-157363.128"
- wire $and$libresoc.v:157363$8479_Y
- attribute \src "libresoc.v:157369.18-157369.112"
- wire $and$libresoc.v:157369$8486_Y
- attribute \src "libresoc.v:157372.18-157372.125"
- wire $and$libresoc.v:157372$8489_Y
- attribute \src "libresoc.v:157365.18-157365.123"
- wire $eq$libresoc.v:157365$8482_Y
- attribute \src "libresoc.v:157366.18-157366.123"
- wire $eq$libresoc.v:157366$8483_Y
- attribute \src "libresoc.v:157364.18-157364.101"
- wire width 65 $extend$libresoc.v:157364$8480_Y
- attribute \src "libresoc.v:157368.18-157368.107"
- wire $not$libresoc.v:157368$8485_Y
- attribute \src "libresoc.v:157371.18-157371.107"
- wire $not$libresoc.v:157371$8488_Y
- attribute \src "libresoc.v:157370.18-157370.115"
- wire $or$libresoc.v:157370$8487_Y
- attribute \src "libresoc.v:157373.18-157373.112"
- wire $or$libresoc.v:157373$8490_Y
- attribute \src "libresoc.v:157364.18-157364.101"
- wire width 65 $pos$libresoc.v:157364$8481_Y
- attribute \src "libresoc.v:157367.18-157367.105"
- wire $reduce_or$libresoc.v:157367$8484_Y
+ attribute \src "libresoc.v:155164.18-155164.128"
+ wire $and$libresoc.v:155164$8393_Y
+ attribute \src "libresoc.v:155170.18-155170.112"
+ wire $and$libresoc.v:155170$8400_Y
+ attribute \src "libresoc.v:155173.18-155173.125"
+ wire $and$libresoc.v:155173$8403_Y
+ attribute \src "libresoc.v:155166.18-155166.123"
+ wire $eq$libresoc.v:155166$8396_Y
+ attribute \src "libresoc.v:155167.18-155167.123"
+ wire $eq$libresoc.v:155167$8397_Y
+ attribute \src "libresoc.v:155165.18-155165.101"
+ wire width 65 $extend$libresoc.v:155165$8394_Y
+ attribute \src "libresoc.v:155169.18-155169.107"
+ wire $not$libresoc.v:155169$8399_Y
+ attribute \src "libresoc.v:155172.18-155172.107"
+ wire $not$libresoc.v:155172$8402_Y
+ attribute \src "libresoc.v:155171.18-155171.115"
+ wire $or$libresoc.v:155171$8401_Y
+ attribute \src "libresoc.v:155174.18-155174.112"
+ wire $or$libresoc.v:155174$8404_Y
+ attribute \src "libresoc.v:155165.18-155165.101"
+ wire width 65 $pos$libresoc.v:155165$8395_Y
+ attribute \src "libresoc.v:155168.18-155168.105"
+ wire $reduce_or$libresoc.v:155168$8398_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 33 \cr_a$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 34 \cr_a_ok
- attribute \src "libresoc.v:157058.7-157058.15"
+ attribute \src "libresoc.v:154859.7-154859.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 38 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:157363$8479
+ cell $and $and$libresoc.v:155164$8393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__oe__oe
connect \B \mul_op__oe__ok
- connect \Y $and$libresoc.v:157363$8479_Y
+ connect \Y $and$libresoc.v:155164$8393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:157369$8486
+ cell $and $and$libresoc.v:155170$8400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$30
- connect \Y $and$libresoc.v:157369$8486_Y
+ connect \Y $and$libresoc.v:155170$8400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:157372$8489
+ cell $and $and$libresoc.v:155173$8403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__oe__oe
connect \B \mul_op__oe__ok
- connect \Y $and$libresoc.v:157372$8489_Y
+ connect \Y $and$libresoc.v:155173$8403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:157365$8482
+ cell $eq $eq$libresoc.v:155166$8396
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:157365$8482_Y
+ connect \Y $eq$libresoc.v:155166$8396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:157366$8483
+ cell $eq $eq$libresoc.v:155167$8397
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mul_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:157366$8483_Y
+ connect \Y $eq$libresoc.v:155167$8397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:157364$8480
+ cell $pos $extend$libresoc.v:155165$8394
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:157364$8480_Y
+ connect \Y $extend$libresoc.v:155165$8394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:157368$8485
+ cell $not $not$libresoc.v:155169$8399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:157368$8485_Y
+ connect \Y $not$libresoc.v:155169$8399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:157371$8488
+ cell $not $not$libresoc.v:155172$8402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:157371$8488_Y
+ connect \Y $not$libresoc.v:155172$8402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:157370$8487
+ cell $or $or$libresoc.v:155171$8401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:157370$8487_Y
+ connect \Y $or$libresoc.v:155171$8401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:157373$8490
+ cell $or $or$libresoc.v:155174$8404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:157373$8490_Y
+ connect \Y $or$libresoc.v:155174$8404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:157364$8481
+ cell $pos $pos$libresoc.v:155165$8395
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:157364$8480_Y
- connect \Y $pos$libresoc.v:157364$8481_Y
+ connect \A $extend$libresoc.v:155165$8394_Y
+ connect \Y $pos$libresoc.v:155165$8395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:157367$8484
+ cell $reduce_or $reduce_or$libresoc.v:155168$8398
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:157367$8484_Y
+ connect \Y $reduce_or$libresoc.v:155168$8398_Y
end
- attribute \src "libresoc.v:157058.7-157058.20"
- process $proc$libresoc.v:157058$8501
+ attribute \src "libresoc.v:154859.7-154859.20"
+ process $proc$libresoc.v:154859$8415
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:157374.3-157385.6"
- process $proc$libresoc.v:157374$8491
+ attribute \src "libresoc.v:155175.3-155186.6"
+ process $proc$libresoc.v:155175$8405
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:157375.5-157375.29"
+ attribute \src "libresoc.v:155176.5-155176.29"
switch \initial
- attribute \src "libresoc.v:157375.9-157375.17"
+ attribute \src "libresoc.v:155176.9-155176.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:157386.3-157397.6"
- process $proc$libresoc.v:157386$8492
+ attribute \src "libresoc.v:155187.3-155198.6"
+ process $proc$libresoc.v:155187$8406
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:157387.5-157387.29"
+ attribute \src "libresoc.v:155188.5-155188.29"
switch \initial
- attribute \src "libresoc.v:157387.9-157387.17"
+ attribute \src "libresoc.v:155188.9-155188.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:157398.3-157407.6"
- process $proc$libresoc.v:157398$8493
+ attribute \src "libresoc.v:155199.3-155208.6"
+ process $proc$libresoc.v:155199$8407
assign { } { }
assign { } { }
- assign $0\xer_so$18[0:0]$8494 $1\xer_so$18[0:0]$8495
- attribute \src "libresoc.v:157399.5-157399.29"
+ assign $0\xer_so$18[0:0]$8408 $1\xer_so$18[0:0]$8409
+ attribute \src "libresoc.v:155200.5-155200.29"
switch \initial
- attribute \src "libresoc.v:157399.9-157399.17"
+ attribute \src "libresoc.v:155200.9-155200.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$18[0:0]$8495 \$41
+ assign $1\xer_so$18[0:0]$8409 \$41
case
- assign $1\xer_so$18[0:0]$8495 1'0
+ assign $1\xer_so$18[0:0]$8409 1'0
end
sync always
- update \xer_so$18 $0\xer_so$18[0:0]$8494
+ update \xer_so$18 $0\xer_so$18[0:0]$8408
end
- attribute \src "libresoc.v:157408.3-157417.6"
- process $proc$libresoc.v:157408$8496
+ attribute \src "libresoc.v:155209.3-155218.6"
+ process $proc$libresoc.v:155209$8410
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:157409.5-157409.29"
+ attribute \src "libresoc.v:155210.5-155210.29"
switch \initial
- attribute \src "libresoc.v:157409.9-157409.17"
+ attribute \src "libresoc.v:155210.9-155210.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:157418.3-157427.6"
- process $proc$libresoc.v:157418$8497
+ attribute \src "libresoc.v:155219.3-155228.6"
+ process $proc$libresoc.v:155219$8411
assign { } { }
assign { } { }
- assign $0\xer_ov$17[1:0]$8498 $1\xer_ov$17[1:0]$8499
- attribute \src "libresoc.v:157419.5-157419.29"
+ assign $0\xer_ov$17[1:0]$8412 $1\xer_ov$17[1:0]$8413
+ attribute \src "libresoc.v:155220.5-155220.29"
switch \initial
- attribute \src "libresoc.v:157419.9-157419.17"
+ attribute \src "libresoc.v:155220.9-155220.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$17[1:0]$8499 \xer_ov
+ assign $1\xer_ov$17[1:0]$8413 \xer_ov
case
- assign $1\xer_ov$17[1:0]$8499 2'00
+ assign $1\xer_ov$17[1:0]$8413 2'00
end
sync always
- update \xer_ov$17 $0\xer_ov$17[1:0]$8498
+ update \xer_ov$17 $0\xer_ov$17[1:0]$8412
end
- attribute \src "libresoc.v:157428.3-157437.6"
- process $proc$libresoc.v:157428$8500
+ attribute \src "libresoc.v:155229.3-155238.6"
+ process $proc$libresoc.v:155229$8414
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:157429.5-157429.29"
+ attribute \src "libresoc.v:155230.5-155230.29"
switch \initial
- attribute \src "libresoc.v:157429.9-157429.17"
+ attribute \src "libresoc.v:155230.9-155230.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$19 $and$libresoc.v:157363$8479_Y
- connect \$22 $pos$libresoc.v:157364$8481_Y
- connect \$24 $eq$libresoc.v:157365$8482_Y
- connect \$26 $eq$libresoc.v:157366$8483_Y
- connect \$28 $reduce_or$libresoc.v:157367$8484_Y
- connect \$30 $not$libresoc.v:157368$8485_Y
- connect \$32 $and$libresoc.v:157369$8486_Y
- connect \$34 $or$libresoc.v:157370$8487_Y
- connect \$36 $not$libresoc.v:157371$8488_Y
- connect \$39 $and$libresoc.v:157372$8489_Y
- connect \$41 $or$libresoc.v:157373$8490_Y
+ connect \$19 $and$libresoc.v:155164$8393_Y
+ connect \$22 $pos$libresoc.v:155165$8395_Y
+ connect \$24 $eq$libresoc.v:155166$8396_Y
+ connect \$26 $eq$libresoc.v:155167$8397_Y
+ connect \$28 $reduce_or$libresoc.v:155168$8398_Y
+ connect \$30 $not$libresoc.v:155169$8399_Y
+ connect \$32 $and$libresoc.v:155170$8400_Y
+ connect \$34 $or$libresoc.v:155171$8401_Y
+ connect \$36 $not$libresoc.v:155172$8402_Y
+ connect \$39 $and$libresoc.v:155173$8403_Y
+ connect \$41 $or$libresoc.v:155174$8404_Y
connect \oe$38 \$39
connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type }
connect \muxid$1 \muxid
connect \o$21 \$22
connect \oe \$19
end
-attribute \src "libresoc.v:157458.1-157808.10"
+attribute \src "libresoc.v:155259.1-155609.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output"
attribute \generator "nMigen"
module \output$118
- attribute \src "libresoc.v:157780.3-157791.6"
+ attribute \src "libresoc.v:155581.3-155592.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:157459.7-157459.20"
+ attribute \src "libresoc.v:155260.7-155260.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:157780.3-157791.6"
+ attribute \src "libresoc.v:155581.3-155592.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:157777.18-157777.112"
- wire $and$libresoc.v:157777$8508_Y
- attribute \src "libresoc.v:157773.18-157773.122"
- wire $eq$libresoc.v:157773$8504_Y
- attribute \src "libresoc.v:157774.18-157774.122"
- wire $eq$libresoc.v:157774$8505_Y
- attribute \src "libresoc.v:157772.18-157772.101"
- wire width 65 $extend$libresoc.v:157772$8502_Y
- attribute \src "libresoc.v:157776.18-157776.107"
- wire $not$libresoc.v:157776$8507_Y
- attribute \src "libresoc.v:157779.18-157779.107"
- wire $not$libresoc.v:157779$8510_Y
- attribute \src "libresoc.v:157778.18-157778.115"
- wire $or$libresoc.v:157778$8509_Y
- attribute \src "libresoc.v:157772.18-157772.101"
- wire width 65 $pos$libresoc.v:157772$8503_Y
- attribute \src "libresoc.v:157775.18-157775.105"
- wire $reduce_or$libresoc.v:157775$8506_Y
+ attribute \src "libresoc.v:155578.18-155578.112"
+ wire $and$libresoc.v:155578$8422_Y
+ attribute \src "libresoc.v:155574.18-155574.122"
+ wire $eq$libresoc.v:155574$8418_Y
+ attribute \src "libresoc.v:155575.18-155575.122"
+ wire $eq$libresoc.v:155575$8419_Y
+ attribute \src "libresoc.v:155573.18-155573.101"
+ wire width 65 $extend$libresoc.v:155573$8416_Y
+ attribute \src "libresoc.v:155577.18-155577.107"
+ wire $not$libresoc.v:155577$8421_Y
+ attribute \src "libresoc.v:155580.18-155580.107"
+ wire $not$libresoc.v:155580$8424_Y
+ attribute \src "libresoc.v:155579.18-155579.115"
+ wire $or$libresoc.v:155579$8423_Y
+ attribute \src "libresoc.v:155573.18-155573.101"
+ wire width 65 $pos$libresoc.v:155573$8417_Y
+ attribute \src "libresoc.v:155576.18-155576.105"
+ wire $reduce_or$libresoc.v:155576$8420_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire width 4 output 43 \cr_a$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 44 \cr_a_ok
- attribute \src "libresoc.v:157459.7-157459.15"
+ attribute \src "libresoc.v:155260.7-155260.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 21 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:157777$8508
+ cell $and $and$libresoc.v:155578$8422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$32
- connect \Y $and$libresoc.v:157777$8508_Y
+ connect \Y $and$libresoc.v:155578$8422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:157773$8504
+ cell $eq $eq$libresoc.v:155574$8418
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:157773$8504_Y
+ connect \Y $eq$libresoc.v:155574$8418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:157774$8505
+ cell $eq $eq$libresoc.v:155575$8419
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:157774$8505_Y
+ connect \Y $eq$libresoc.v:155575$8419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:157772$8502
+ cell $pos $extend$libresoc.v:155573$8416
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:157772$8502_Y
+ connect \Y $extend$libresoc.v:155573$8416_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:157776$8507
+ cell $not $not$libresoc.v:155577$8421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:157776$8507_Y
+ connect \Y $not$libresoc.v:155577$8421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:157779$8510
+ cell $not $not$libresoc.v:155580$8424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:157779$8510_Y
+ connect \Y $not$libresoc.v:155580$8424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:157778$8509
+ cell $or $or$libresoc.v:155579$8423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:157778$8509_Y
+ connect \Y $or$libresoc.v:155579$8423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:157772$8503
+ cell $pos $pos$libresoc.v:155573$8417
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:157772$8502_Y
- connect \Y $pos$libresoc.v:157772$8503_Y
+ connect \A $extend$libresoc.v:155573$8416_Y
+ connect \Y $pos$libresoc.v:155573$8417_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:157775$8506
+ cell $reduce_or $reduce_or$libresoc.v:155576$8420
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:157775$8506_Y
+ connect \Y $reduce_or$libresoc.v:155576$8420_Y
end
- attribute \src "libresoc.v:157459.7-157459.20"
- process $proc$libresoc.v:157459$8512
+ attribute \src "libresoc.v:155260.7-155260.20"
+ process $proc$libresoc.v:155260$8426
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:157780.3-157791.6"
- process $proc$libresoc.v:157780$8511
+ attribute \src "libresoc.v:155581.3-155592.6"
+ process $proc$libresoc.v:155581$8425
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:157781.5-157781.29"
+ attribute \src "libresoc.v:155582.5-155582.29"
switch \initial
- attribute \src "libresoc.v:157781.9-157781.17"
+ attribute \src "libresoc.v:155582.9-155582.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- connect \$24 $pos$libresoc.v:157772$8503_Y
- connect \$26 $eq$libresoc.v:157773$8504_Y
- connect \$28 $eq$libresoc.v:157774$8505_Y
- connect \$30 $reduce_or$libresoc.v:157775$8506_Y
- connect \$32 $not$libresoc.v:157776$8507_Y
- connect \$34 $and$libresoc.v:157777$8508_Y
- connect \$36 $or$libresoc.v:157778$8509_Y
- connect \$38 $not$libresoc.v:157779$8510_Y
+ connect \$24 $pos$libresoc.v:155573$8417_Y
+ connect \$26 $eq$libresoc.v:155574$8418_Y
+ connect \$28 $eq$libresoc.v:155575$8419_Y
+ connect \$30 $reduce_or$libresoc.v:155576$8420_Y
+ connect \$32 $not$libresoc.v:155577$8421_Y
+ connect \$34 $and$libresoc.v:155578$8422_Y
+ connect \$36 $or$libresoc.v:155579$8423_Y
+ connect \$38 $not$libresoc.v:155580$8424_Y
connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \muxid$1 \muxid
connect \cr_a_ok \sr_op__write_cr0
connect \target \o$23 [63:0]
connect \o$23 \$24
end
-attribute \src "libresoc.v:157812.1-158175.10"
+attribute \src "libresoc.v:155613.1-155976.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output"
attribute \generator "nMigen"
module \output$54
- attribute \src "libresoc.v:158150.3-158161.6"
+ attribute \src "libresoc.v:155951.3-155962.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:157813.7-157813.20"
+ attribute \src "libresoc.v:155614.7-155614.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158138.3-158149.6"
- wire width 65 $0\o$23[64:0]$8526
- attribute \src "libresoc.v:158150.3-158161.6"
+ attribute \src "libresoc.v:155939.3-155950.6"
+ wire width 65 $0\o$23[64:0]$8440
+ attribute \src "libresoc.v:155951.3-155962.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:158138.3-158149.6"
- wire width 65 $1\o$23[64:0]$8527
- attribute \src "libresoc.v:158135.18-158135.112"
- wire $and$libresoc.v:158135$8522_Y
- attribute \src "libresoc.v:158131.18-158131.127"
- wire $eq$libresoc.v:158131$8518_Y
- attribute \src "libresoc.v:158132.18-158132.127"
- wire $eq$libresoc.v:158132$8519_Y
- attribute \src "libresoc.v:158129.18-158129.103"
- wire width 65 $extend$libresoc.v:158129$8514_Y
- attribute \src "libresoc.v:158130.18-158130.101"
- wire width 65 $extend$libresoc.v:158130$8516_Y
- attribute \src "libresoc.v:158128.18-158128.100"
- wire width 64 $not$libresoc.v:158128$8513_Y
- attribute \src "libresoc.v:158134.18-158134.107"
- wire $not$libresoc.v:158134$8521_Y
- attribute \src "libresoc.v:158137.18-158137.107"
- wire $not$libresoc.v:158137$8524_Y
- attribute \src "libresoc.v:158136.18-158136.115"
- wire $or$libresoc.v:158136$8523_Y
- attribute \src "libresoc.v:158129.18-158129.103"
- wire width 65 $pos$libresoc.v:158129$8515_Y
- attribute \src "libresoc.v:158130.18-158130.101"
- wire width 65 $pos$libresoc.v:158130$8517_Y
- attribute \src "libresoc.v:158133.18-158133.105"
- wire $reduce_or$libresoc.v:158133$8520_Y
+ attribute \src "libresoc.v:155939.3-155950.6"
+ wire width 65 $1\o$23[64:0]$8441
+ attribute \src "libresoc.v:155936.18-155936.112"
+ wire $and$libresoc.v:155936$8436_Y
+ attribute \src "libresoc.v:155932.18-155932.127"
+ wire $eq$libresoc.v:155932$8432_Y
+ attribute \src "libresoc.v:155933.18-155933.127"
+ wire $eq$libresoc.v:155933$8433_Y
+ attribute \src "libresoc.v:155930.18-155930.103"
+ wire width 65 $extend$libresoc.v:155930$8428_Y
+ attribute \src "libresoc.v:155931.18-155931.101"
+ wire width 65 $extend$libresoc.v:155931$8430_Y
+ attribute \src "libresoc.v:155929.18-155929.100"
+ wire width 64 $not$libresoc.v:155929$8427_Y
+ attribute \src "libresoc.v:155935.18-155935.107"
+ wire $not$libresoc.v:155935$8435_Y
+ attribute \src "libresoc.v:155938.18-155938.107"
+ wire $not$libresoc.v:155938$8438_Y
+ attribute \src "libresoc.v:155937.18-155937.115"
+ wire $or$libresoc.v:155937$8437_Y
+ attribute \src "libresoc.v:155930.18-155930.103"
+ wire width 65 $pos$libresoc.v:155930$8429_Y
+ attribute \src "libresoc.v:155931.18-155931.101"
+ wire width 65 $pos$libresoc.v:155931$8431_Y
+ attribute \src "libresoc.v:155934.18-155934.105"
+ wire $reduce_or$libresoc.v:155934$8434_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 44 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 45 \cr_a_ok
- attribute \src "libresoc.v:157813.7-157813.15"
+ attribute \src "libresoc.v:155614.7-155614.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 22 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:158135$8522
+ cell $and $and$libresoc.v:155936$8436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$36
- connect \Y $and$libresoc.v:158135$8522_Y
+ connect \Y $and$libresoc.v:155936$8436_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:158131$8518
+ cell $eq $eq$libresoc.v:155932$8432
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:158131$8518_Y
+ connect \Y $eq$libresoc.v:155932$8432_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:158132$8519
+ cell $eq $eq$libresoc.v:155933$8433
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:158132$8519_Y
+ connect \Y $eq$libresoc.v:155933$8433_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:158129$8514
+ cell $pos $extend$libresoc.v:155930$8428
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$25
- connect \Y $extend$libresoc.v:158129$8514_Y
+ connect \Y $extend$libresoc.v:155930$8428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:158130$8516
+ cell $pos $extend$libresoc.v:155931$8430
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:158130$8516_Y
+ connect \Y $extend$libresoc.v:155931$8430_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:158128$8513
+ cell $not $not$libresoc.v:155929$8427
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:158128$8513_Y
+ connect \Y $not$libresoc.v:155929$8427_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:158134$8521
+ cell $not $not$libresoc.v:155935$8435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:158134$8521_Y
+ connect \Y $not$libresoc.v:155935$8435_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:158137$8524
+ cell $not $not$libresoc.v:155938$8438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:158137$8524_Y
+ connect \Y $not$libresoc.v:155938$8438_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:158136$8523
+ cell $or $or$libresoc.v:155937$8437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:158136$8523_Y
+ connect \Y $or$libresoc.v:155937$8437_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:158129$8515
+ cell $pos $pos$libresoc.v:155930$8429
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158129$8514_Y
- connect \Y $pos$libresoc.v:158129$8515_Y
+ connect \A $extend$libresoc.v:155930$8428_Y
+ connect \Y $pos$libresoc.v:155930$8429_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:158130$8517
+ cell $pos $pos$libresoc.v:155931$8431
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158130$8516_Y
- connect \Y $pos$libresoc.v:158130$8517_Y
+ connect \A $extend$libresoc.v:155931$8430_Y
+ connect \Y $pos$libresoc.v:155931$8431_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:158133$8520
+ cell $reduce_or $reduce_or$libresoc.v:155934$8434
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:158133$8520_Y
+ connect \Y $reduce_or$libresoc.v:155934$8434_Y
end
- attribute \src "libresoc.v:157813.7-157813.20"
- process $proc$libresoc.v:157813$8529
+ attribute \src "libresoc.v:155614.7-155614.20"
+ process $proc$libresoc.v:155614$8443
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158138.3-158149.6"
- process $proc$libresoc.v:158138$8525
+ attribute \src "libresoc.v:155939.3-155950.6"
+ process $proc$libresoc.v:155939$8439
assign { } { }
- assign $0\o$23[64:0]$8526 $1\o$23[64:0]$8527
- attribute \src "libresoc.v:158139.5-158139.29"
+ assign $0\o$23[64:0]$8440 $1\o$23[64:0]$8441
+ attribute \src "libresoc.v:155940.5-155940.29"
switch \initial
- attribute \src "libresoc.v:158139.9-158139.17"
+ attribute \src "libresoc.v:155940.9-155940.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$23[64:0]$8527 \$24
+ assign $1\o$23[64:0]$8441 \$24
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$23[64:0]$8527 \$28
+ assign $1\o$23[64:0]$8441 \$28
end
sync always
- update \o$23 $0\o$23[64:0]$8526
+ update \o$23 $0\o$23[64:0]$8440
end
- attribute \src "libresoc.v:158150.3-158161.6"
- process $proc$libresoc.v:158150$8528
+ attribute \src "libresoc.v:155951.3-155962.6"
+ process $proc$libresoc.v:155951$8442
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:158151.5-158151.29"
+ attribute \src "libresoc.v:155952.5-155952.29"
switch \initial
- attribute \src "libresoc.v:158151.9-158151.17"
+ attribute \src "libresoc.v:155952.9-155952.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- connect \$25 $not$libresoc.v:158128$8513_Y
- connect \$24 $pos$libresoc.v:158129$8515_Y
- connect \$28 $pos$libresoc.v:158130$8517_Y
- connect \$30 $eq$libresoc.v:158131$8518_Y
- connect \$32 $eq$libresoc.v:158132$8519_Y
- connect \$34 $reduce_or$libresoc.v:158133$8520_Y
- connect \$36 $not$libresoc.v:158134$8521_Y
- connect \$38 $and$libresoc.v:158135$8522_Y
- connect \$40 $or$libresoc.v:158136$8523_Y
- connect \$42 $not$libresoc.v:158137$8524_Y
+ connect \$25 $not$libresoc.v:155929$8427_Y
+ connect \$24 $pos$libresoc.v:155930$8429_Y
+ connect \$28 $pos$libresoc.v:155931$8431_Y
+ connect \$30 $eq$libresoc.v:155932$8432_Y
+ connect \$32 $eq$libresoc.v:155933$8433_Y
+ connect \$34 $reduce_or$libresoc.v:155934$8434_Y
+ connect \$36 $not$libresoc.v:155935$8435_Y
+ connect \$38 $and$libresoc.v:155936$8436_Y
+ connect \$40 $or$libresoc.v:155937$8437_Y
+ connect \$42 $not$libresoc.v:155938$8438_Y
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \cr_a_ok \logical_op__write_cr0
connect \is_cmp \$30
connect \target \o$23 [63:0]
end
-attribute \src "libresoc.v:158179.1-158625.10"
+attribute \src "libresoc.v:155980.1-156426.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output"
attribute \generator "nMigen"
module \output$83
- attribute \src "libresoc.v:158546.3-158557.6"
+ attribute \src "libresoc.v:156347.3-156358.6"
wire width 4 $0\cr0[3:0]
- attribute \src "libresoc.v:158180.7-158180.20"
+ attribute \src "libresoc.v:155981.7-155981.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158558.3-158569.6"
- wire width 65 $0\o$27[64:0]$8548
- attribute \src "libresoc.v:158534.3-158545.6"
+ attribute \src "libresoc.v:156359.3-156370.6"
+ wire width 65 $0\o$27[64:0]$8462
+ attribute \src "libresoc.v:156335.3-156346.6"
wire $0\so[0:0]
- attribute \src "libresoc.v:158590.3-158599.6"
- wire width 2 $0\xer_ov$23[1:0]$8555
- attribute \src "libresoc.v:158600.3-158609.6"
+ attribute \src "libresoc.v:156391.3-156400.6"
+ wire width 2 $0\xer_ov$23[1:0]$8469
+ attribute \src "libresoc.v:156401.3-156410.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:158570.3-158579.6"
- wire $0\xer_so$24[0:0]$8551
- attribute \src "libresoc.v:158580.3-158589.6"
+ attribute \src "libresoc.v:156371.3-156380.6"
+ wire $0\xer_so$24[0:0]$8465
+ attribute \src "libresoc.v:156381.3-156390.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:158546.3-158557.6"
+ attribute \src "libresoc.v:156347.3-156358.6"
wire width 4 $1\cr0[3:0]
- attribute \src "libresoc.v:158558.3-158569.6"
- wire width 65 $1\o$27[64:0]$8549
- attribute \src "libresoc.v:158534.3-158545.6"
+ attribute \src "libresoc.v:156359.3-156370.6"
+ wire width 65 $1\o$27[64:0]$8463
+ attribute \src "libresoc.v:156335.3-156346.6"
wire $1\so[0:0]
- attribute \src "libresoc.v:158590.3-158599.6"
- wire width 2 $1\xer_ov$23[1:0]$8556
- attribute \src "libresoc.v:158600.3-158609.6"
+ attribute \src "libresoc.v:156391.3-156400.6"
+ wire width 2 $1\xer_ov$23[1:0]$8470
+ attribute \src "libresoc.v:156401.3-156410.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:158570.3-158579.6"
- wire $1\xer_so$24[0:0]$8552
- attribute \src "libresoc.v:158580.3-158589.6"
+ attribute \src "libresoc.v:156371.3-156380.6"
+ wire $1\xer_so$24[0:0]$8466
+ attribute \src "libresoc.v:156381.3-156390.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:158521.18-158521.136"
- wire $and$libresoc.v:158521$8530_Y
- attribute \src "libresoc.v:158529.18-158529.112"
- wire $and$libresoc.v:158529$8540_Y
- attribute \src "libresoc.v:158532.18-158532.133"
- wire $and$libresoc.v:158532$8543_Y
- attribute \src "libresoc.v:158525.18-158525.127"
- wire $eq$libresoc.v:158525$8536_Y
- attribute \src "libresoc.v:158526.18-158526.127"
- wire $eq$libresoc.v:158526$8537_Y
- attribute \src "libresoc.v:158523.18-158523.103"
- wire width 65 $extend$libresoc.v:158523$8532_Y
- attribute \src "libresoc.v:158524.18-158524.101"
- wire width 65 $extend$libresoc.v:158524$8534_Y
- attribute \src "libresoc.v:158522.18-158522.100"
- wire width 64 $not$libresoc.v:158522$8531_Y
- attribute \src "libresoc.v:158528.18-158528.107"
- wire $not$libresoc.v:158528$8539_Y
- attribute \src "libresoc.v:158531.18-158531.107"
- wire $not$libresoc.v:158531$8542_Y
- attribute \src "libresoc.v:158530.18-158530.115"
- wire $or$libresoc.v:158530$8541_Y
- attribute \src "libresoc.v:158533.18-158533.112"
- wire $or$libresoc.v:158533$8544_Y
- attribute \src "libresoc.v:158523.18-158523.103"
- wire width 65 $pos$libresoc.v:158523$8533_Y
- attribute \src "libresoc.v:158524.18-158524.101"
- wire width 65 $pos$libresoc.v:158524$8535_Y
- attribute \src "libresoc.v:158527.18-158527.105"
- wire $reduce_or$libresoc.v:158527$8538_Y
+ attribute \src "libresoc.v:156322.18-156322.136"
+ wire $and$libresoc.v:156322$8444_Y
+ attribute \src "libresoc.v:156330.18-156330.112"
+ wire $and$libresoc.v:156330$8454_Y
+ attribute \src "libresoc.v:156333.18-156333.133"
+ wire $and$libresoc.v:156333$8457_Y
+ attribute \src "libresoc.v:156326.18-156326.127"
+ wire $eq$libresoc.v:156326$8450_Y
+ attribute \src "libresoc.v:156327.18-156327.127"
+ wire $eq$libresoc.v:156327$8451_Y
+ attribute \src "libresoc.v:156324.18-156324.103"
+ wire width 65 $extend$libresoc.v:156324$8446_Y
+ attribute \src "libresoc.v:156325.18-156325.101"
+ wire width 65 $extend$libresoc.v:156325$8448_Y
+ attribute \src "libresoc.v:156323.18-156323.100"
+ wire width 64 $not$libresoc.v:156323$8445_Y
+ attribute \src "libresoc.v:156329.18-156329.107"
+ wire $not$libresoc.v:156329$8453_Y
+ attribute \src "libresoc.v:156332.18-156332.107"
+ wire $not$libresoc.v:156332$8456_Y
+ attribute \src "libresoc.v:156331.18-156331.115"
+ wire $or$libresoc.v:156331$8455_Y
+ attribute \src "libresoc.v:156334.18-156334.112"
+ wire $or$libresoc.v:156334$8458_Y
+ attribute \src "libresoc.v:156324.18-156324.103"
+ wire width 65 $pos$libresoc.v:156324$8447_Y
+ attribute \src "libresoc.v:156325.18-156325.101"
+ wire width 65 $pos$libresoc.v:156325$8449_Y
+ attribute \src "libresoc.v:156328.18-156328.105"
+ wire $reduce_or$libresoc.v:156328$8452_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 4 output 45 \cr_a$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 46 \cr_a_ok
- attribute \src "libresoc.v:158180.7-158180.15"
+ attribute \src "libresoc.v:155981.7-155981.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69"
wire \is_cmp
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 50 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- cell $and $and$libresoc.v:158521$8530
+ cell $and $and$libresoc.v:156322$8444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__oe__oe
connect \B \logical_op__oe__ok
- connect \Y $and$libresoc.v:158521$8530_Y
+ connect \Y $and$libresoc.v:156322$8444_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $and $and$libresoc.v:158529$8540
+ cell $and $and$libresoc.v:156330$8454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_nzero
connect \B \$40
- connect \Y $and$libresoc.v:158529$8540_Y
+ connect \Y $and$libresoc.v:156330$8454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $and$libresoc.v:158532$8543
+ cell $and $and$libresoc.v:156333$8457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__oe__oe
connect \B \logical_op__oe__ok
- connect \Y $and$libresoc.v:158532$8543_Y
+ connect \Y $and$libresoc.v:156333$8457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
- cell $eq $eq$libresoc.v:158525$8536
+ cell $eq $eq$libresoc.v:156326$8450
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001010
- connect \Y $eq$libresoc.v:158525$8536_Y
+ connect \Y $eq$libresoc.v:156326$8450_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78"
- cell $eq $eq$libresoc.v:158526$8537
+ cell $eq $eq$libresoc.v:156327$8451
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0001100
- connect \Y $eq$libresoc.v:158526$8537_Y
+ connect \Y $eq$libresoc.v:156327$8451_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $extend$libresoc.v:158523$8532
+ cell $pos $extend$libresoc.v:156324$8446
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \$29
- connect \Y $extend$libresoc.v:158523$8532_Y
+ connect \Y $extend$libresoc.v:156324$8446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:158524$8534
+ cell $pos $extend$libresoc.v:156325$8448
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $extend$libresoc.v:158524$8534_Y
+ connect \Y $extend$libresoc.v:156325$8448_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $not $not$libresoc.v:158522$8531
+ cell $not $not$libresoc.v:156323$8445
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $not$libresoc.v:158522$8531_Y
+ connect \Y $not$libresoc.v:156323$8445_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
- cell $not $not$libresoc.v:158528$8539
+ cell $not $not$libresoc.v:156329$8453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $not$libresoc.v:158528$8539_Y
+ connect \Y $not$libresoc.v:156329$8453_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88"
- cell $not $not$libresoc.v:158531$8542
+ cell $not $not$libresoc.v:156332$8456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $not$libresoc.v:158531$8542_Y
+ connect \Y $not$libresoc.v:156332$8456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85"
- cell $or $or$libresoc.v:158530$8541
+ cell $or $or$libresoc.v:156331$8455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_cmpeqb
connect \B \is_cmp
- connect \Y $or$libresoc.v:158530$8541_Y
+ connect \Y $or$libresoc.v:156331$8455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33"
- cell $or $or$libresoc.v:158533$8544
+ cell $or $or$libresoc.v:156334$8458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so
connect \B \xer_ov [0]
- connect \Y $or$libresoc.v:158533$8544_Y
+ connect \Y $or$libresoc.v:156334$8458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- cell $pos $pos$libresoc.v:158523$8533
+ cell $pos $pos$libresoc.v:156324$8447
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158523$8532_Y
- connect \Y $pos$libresoc.v:158523$8533_Y
+ connect \A $extend$libresoc.v:156324$8446_Y
+ connect \Y $pos$libresoc.v:156324$8447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:158524$8535
+ cell $pos $pos$libresoc.v:156325$8449
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158524$8534_Y
- connect \Y $pos$libresoc.v:158524$8535_Y
+ connect \A $extend$libresoc.v:156325$8448_Y
+ connect \Y $pos$libresoc.v:156325$8449_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
- cell $reduce_or $reduce_or$libresoc.v:158527$8538
+ cell $reduce_or $reduce_or$libresoc.v:156328$8452
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $reduce_or$libresoc.v:158527$8538_Y
+ connect \Y $reduce_or$libresoc.v:156328$8452_Y
end
- attribute \src "libresoc.v:158180.7-158180.20"
- process $proc$libresoc.v:158180$8558
+ attribute \src "libresoc.v:155981.7-155981.20"
+ process $proc$libresoc.v:155981$8472
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158534.3-158545.6"
- process $proc$libresoc.v:158534$8545
+ attribute \src "libresoc.v:156335.3-156346.6"
+ process $proc$libresoc.v:156335$8459
assign { } { }
assign $0\so[0:0] $1\so[0:0]
- attribute \src "libresoc.v:158535.5-158535.29"
+ attribute \src "libresoc.v:156336.5-156336.29"
switch \initial
- attribute \src "libresoc.v:158535.9-158535.17"
+ attribute \src "libresoc.v:156336.9-156336.17"
case 1'1
case
end
sync always
update \so $0\so[0:0]
end
- attribute \src "libresoc.v:158546.3-158557.6"
- process $proc$libresoc.v:158546$8546
+ attribute \src "libresoc.v:156347.3-156358.6"
+ process $proc$libresoc.v:156347$8460
assign { } { }
assign $0\cr0[3:0] $1\cr0[3:0]
- attribute \src "libresoc.v:158547.5-158547.29"
+ attribute \src "libresoc.v:156348.5-156348.29"
switch \initial
- attribute \src "libresoc.v:158547.9-158547.17"
+ attribute \src "libresoc.v:156348.9-156348.17"
case 1'1
case
end
sync always
update \cr0 $0\cr0[3:0]
end
- attribute \src "libresoc.v:158558.3-158569.6"
- process $proc$libresoc.v:158558$8547
+ attribute \src "libresoc.v:156359.3-156370.6"
+ process $proc$libresoc.v:156359$8461
assign { } { }
- assign $0\o$27[64:0]$8548 $1\o$27[64:0]$8549
- attribute \src "libresoc.v:158559.5-158559.29"
+ assign $0\o$27[64:0]$8462 $1\o$27[64:0]$8463
+ attribute \src "libresoc.v:156360.5-156360.29"
switch \initial
- attribute \src "libresoc.v:158559.9-158559.17"
+ attribute \src "libresoc.v:156360.9-156360.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\o$27[64:0]$8549 \$28
+ assign $1\o$27[64:0]$8463 \$28
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\o$27[64:0]$8549 \$32
+ assign $1\o$27[64:0]$8463 \$32
end
sync always
- update \o$27 $0\o$27[64:0]$8548
+ update \o$27 $0\o$27[64:0]$8462
end
- attribute \src "libresoc.v:158570.3-158579.6"
- process $proc$libresoc.v:158570$8550
+ attribute \src "libresoc.v:156371.3-156380.6"
+ process $proc$libresoc.v:156371$8464
assign { } { }
assign { } { }
- assign $0\xer_so$24[0:0]$8551 $1\xer_so$24[0:0]$8552
- attribute \src "libresoc.v:158571.5-158571.29"
+ assign $0\xer_so$24[0:0]$8465 $1\xer_so$24[0:0]$8466
+ attribute \src "libresoc.v:156372.5-156372.29"
switch \initial
- attribute \src "libresoc.v:158571.9-158571.17"
+ attribute \src "libresoc.v:156372.9-156372.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$24[0:0]$8552 \$51
+ assign $1\xer_so$24[0:0]$8466 \$51
case
- assign $1\xer_so$24[0:0]$8552 1'0
+ assign $1\xer_so$24[0:0]$8466 1'0
end
sync always
- update \xer_so$24 $0\xer_so$24[0:0]$8551
+ update \xer_so$24 $0\xer_so$24[0:0]$8465
end
- attribute \src "libresoc.v:158580.3-158589.6"
- process $proc$libresoc.v:158580$8553
+ attribute \src "libresoc.v:156381.3-156390.6"
+ process $proc$libresoc.v:156381$8467
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:158581.5-158581.29"
+ attribute \src "libresoc.v:156382.5-156382.29"
switch \initial
- attribute \src "libresoc.v:158581.9-158581.17"
+ attribute \src "libresoc.v:156382.9-156382.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:158590.3-158599.6"
- process $proc$libresoc.v:158590$8554
+ attribute \src "libresoc.v:156391.3-156400.6"
+ process $proc$libresoc.v:156391$8468
assign { } { }
assign { } { }
- assign $0\xer_ov$23[1:0]$8555 $1\xer_ov$23[1:0]$8556
- attribute \src "libresoc.v:158591.5-158591.29"
+ assign $0\xer_ov$23[1:0]$8469 $1\xer_ov$23[1:0]$8470
+ attribute \src "libresoc.v:156392.5-156392.29"
switch \initial
- attribute \src "libresoc.v:158591.9-158591.17"
+ attribute \src "libresoc.v:156392.9-156392.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_ov$23[1:0]$8556 \xer_ov
+ assign $1\xer_ov$23[1:0]$8470 \xer_ov
case
- assign $1\xer_ov$23[1:0]$8556 2'00
+ assign $1\xer_ov$23[1:0]$8470 2'00
end
sync always
- update \xer_ov$23 $0\xer_ov$23[1:0]$8555
+ update \xer_ov$23 $0\xer_ov$23[1:0]$8469
end
- attribute \src "libresoc.v:158600.3-158609.6"
- process $proc$libresoc.v:158600$8557
+ attribute \src "libresoc.v:156401.3-156410.6"
+ process $proc$libresoc.v:156401$8471
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:158601.5-158601.29"
+ attribute \src "libresoc.v:156402.5-156402.29"
switch \initial
- attribute \src "libresoc.v:158601.9-158601.17"
+ attribute \src "libresoc.v:156402.9-156402.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- connect \$25 $and$libresoc.v:158521$8530_Y
- connect \$29 $not$libresoc.v:158522$8531_Y
- connect \$28 $pos$libresoc.v:158523$8533_Y
- connect \$32 $pos$libresoc.v:158524$8535_Y
- connect \$34 $eq$libresoc.v:158525$8536_Y
- connect \$36 $eq$libresoc.v:158526$8537_Y
- connect \$38 $reduce_or$libresoc.v:158527$8538_Y
- connect \$40 $not$libresoc.v:158528$8539_Y
- connect \$42 $and$libresoc.v:158529$8540_Y
- connect \$44 $or$libresoc.v:158530$8541_Y
- connect \$46 $not$libresoc.v:158531$8542_Y
- connect \$49 $and$libresoc.v:158532$8543_Y
- connect \$51 $or$libresoc.v:158533$8544_Y
+ connect \$25 $and$libresoc.v:156322$8444_Y
+ connect \$29 $not$libresoc.v:156323$8445_Y
+ connect \$28 $pos$libresoc.v:156324$8447_Y
+ connect \$32 $pos$libresoc.v:156325$8449_Y
+ connect \$34 $eq$libresoc.v:156326$8450_Y
+ connect \$36 $eq$libresoc.v:156327$8451_Y
+ connect \$38 $reduce_or$libresoc.v:156328$8452_Y
+ connect \$40 $not$libresoc.v:156329$8453_Y
+ connect \$42 $and$libresoc.v:156330$8454_Y
+ connect \$44 $or$libresoc.v:156331$8455_Y
+ connect \$46 $not$libresoc.v:156332$8456_Y
+ connect \$49 $and$libresoc.v:156333$8457_Y
+ connect \$51 $or$libresoc.v:156334$8458_Y
connect \oe$48 \$49
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \target \o$27 [63:0]
connect \oe \$25
end
-attribute \src "libresoc.v:158629.1-159107.10"
+attribute \src "libresoc.v:156430.1-156908.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage"
attribute \generator "nMigen"
module \output_stage
- attribute \src "libresoc.v:158630.7-158630.20"
+ attribute \src "libresoc.v:156431.7-156431.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:159060.3-159093.6"
+ attribute \src "libresoc.v:156861.3-156894.6"
wire $0\ov[0:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:159060.3-159093.6"
+ attribute \src "libresoc.v:156861.3-156894.6"
wire $1\ov[0:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:159060.3-159093.6"
+ attribute \src "libresoc.v:156861.3-156894.6"
wire $2\ov[0:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $3\o[63:0]
- attribute \src "libresoc.v:159060.3-159093.6"
+ attribute \src "libresoc.v:156861.3-156894.6"
wire $3\ov[0:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $4\o[63:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $5\o[63:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $6\o[63:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $7\o[63:0]
- attribute \src "libresoc.v:158988.3-159059.6"
+ attribute \src "libresoc.v:156789.3-156860.6"
wire width 64 $8\o[63:0]
- attribute \src "libresoc.v:158979.18-158979.122"
- wire $and$libresoc.v:158979$8572_Y
- attribute \src "libresoc.v:158971.18-158971.109"
- wire width 65 $extend$libresoc.v:158971$8560_Y
- attribute \src "libresoc.v:158972.18-158972.100"
- wire width 65 $extend$libresoc.v:158972$8562_Y
- attribute \src "libresoc.v:158974.18-158974.113"
- wire width 65 $extend$libresoc.v:158974$8565_Y
- attribute \src "libresoc.v:158975.18-158975.104"
- wire width 65 $extend$libresoc.v:158975$8567_Y
- attribute \src "libresoc.v:158983.18-158983.114"
- wire width 64 $extend$libresoc.v:158983$8576_Y
- attribute \src "libresoc.v:158984.18-158984.114"
- wire width 64 $extend$libresoc.v:158984$8578_Y
- attribute \src "libresoc.v:158985.18-158985.114"
- wire width 64 $extend$libresoc.v:158985$8580_Y
- attribute \src "libresoc.v:158986.18-158986.114"
- wire width 64 $extend$libresoc.v:158986$8582_Y
- attribute \src "libresoc.v:158987.18-158987.115"
- wire width 64 $extend$libresoc.v:158987$8584_Y
- attribute \src "libresoc.v:158980.18-158980.128"
- wire $ne$libresoc.v:158980$8573_Y
- attribute \src "libresoc.v:158971.18-158971.109"
- wire width 65 $neg$libresoc.v:158971$8561_Y
- attribute \src "libresoc.v:158974.18-158974.113"
- wire width 65 $neg$libresoc.v:158974$8566_Y
- attribute \src "libresoc.v:158977.18-158977.116"
- wire $not$libresoc.v:158977$8570_Y
- attribute \src "libresoc.v:158982.18-158982.99"
- wire $not$libresoc.v:158982$8575_Y
- attribute \src "libresoc.v:158972.18-158972.100"
- wire width 65 $pos$libresoc.v:158972$8563_Y
- attribute \src "libresoc.v:158975.18-158975.104"
- wire width 65 $pos$libresoc.v:158975$8568_Y
- attribute \src "libresoc.v:158981.18-158981.118"
- wire width 64 $pos$libresoc.v:158981$8574_Y
- attribute \src "libresoc.v:158983.18-158983.114"
- wire width 64 $pos$libresoc.v:158983$8577_Y
- attribute \src "libresoc.v:158984.18-158984.114"
- wire width 64 $pos$libresoc.v:158984$8579_Y
- attribute \src "libresoc.v:158985.18-158985.114"
- wire width 64 $pos$libresoc.v:158985$8581_Y
- attribute \src "libresoc.v:158986.18-158986.114"
- wire width 64 $pos$libresoc.v:158986$8583_Y
- attribute \src "libresoc.v:158987.18-158987.115"
- wire width 64 $pos$libresoc.v:158987$8585_Y
- attribute \src "libresoc.v:158973.18-158973.121"
- wire width 65 $ternary$libresoc.v:158973$8564_Y
- attribute \src "libresoc.v:158976.18-158976.122"
- wire width 65 $ternary$libresoc.v:158976$8569_Y
- attribute \src "libresoc.v:158970.18-158970.120"
- wire $xor$libresoc.v:158970$8559_Y
- attribute \src "libresoc.v:158978.18-158978.127"
- wire $xor$libresoc.v:158978$8571_Y
+ attribute \src "libresoc.v:156780.18-156780.122"
+ wire $and$libresoc.v:156780$8486_Y
+ attribute \src "libresoc.v:156772.18-156772.109"
+ wire width 65 $extend$libresoc.v:156772$8474_Y
+ attribute \src "libresoc.v:156773.18-156773.100"
+ wire width 65 $extend$libresoc.v:156773$8476_Y
+ attribute \src "libresoc.v:156775.18-156775.113"
+ wire width 65 $extend$libresoc.v:156775$8479_Y
+ attribute \src "libresoc.v:156776.18-156776.104"
+ wire width 65 $extend$libresoc.v:156776$8481_Y
+ attribute \src "libresoc.v:156784.18-156784.114"
+ wire width 64 $extend$libresoc.v:156784$8490_Y
+ attribute \src "libresoc.v:156785.18-156785.114"
+ wire width 64 $extend$libresoc.v:156785$8492_Y
+ attribute \src "libresoc.v:156786.18-156786.114"
+ wire width 64 $extend$libresoc.v:156786$8494_Y
+ attribute \src "libresoc.v:156787.18-156787.114"
+ wire width 64 $extend$libresoc.v:156787$8496_Y
+ attribute \src "libresoc.v:156788.18-156788.115"
+ wire width 64 $extend$libresoc.v:156788$8498_Y
+ attribute \src "libresoc.v:156781.18-156781.128"
+ wire $ne$libresoc.v:156781$8487_Y
+ attribute \src "libresoc.v:156772.18-156772.109"
+ wire width 65 $neg$libresoc.v:156772$8475_Y
+ attribute \src "libresoc.v:156775.18-156775.113"
+ wire width 65 $neg$libresoc.v:156775$8480_Y
+ attribute \src "libresoc.v:156778.18-156778.116"
+ wire $not$libresoc.v:156778$8484_Y
+ attribute \src "libresoc.v:156783.18-156783.99"
+ wire $not$libresoc.v:156783$8489_Y
+ attribute \src "libresoc.v:156773.18-156773.100"
+ wire width 65 $pos$libresoc.v:156773$8477_Y
+ attribute \src "libresoc.v:156776.18-156776.104"
+ wire width 65 $pos$libresoc.v:156776$8482_Y
+ attribute \src "libresoc.v:156782.18-156782.118"
+ wire width 64 $pos$libresoc.v:156782$8488_Y
+ attribute \src "libresoc.v:156784.18-156784.114"
+ wire width 64 $pos$libresoc.v:156784$8491_Y
+ attribute \src "libresoc.v:156785.18-156785.114"
+ wire width 64 $pos$libresoc.v:156785$8493_Y
+ attribute \src "libresoc.v:156786.18-156786.114"
+ wire width 64 $pos$libresoc.v:156786$8495_Y
+ attribute \src "libresoc.v:156787.18-156787.114"
+ wire width 64 $pos$libresoc.v:156787$8497_Y
+ attribute \src "libresoc.v:156788.18-156788.115"
+ wire width 64 $pos$libresoc.v:156788$8499_Y
+ attribute \src "libresoc.v:156774.18-156774.121"
+ wire width 65 $ternary$libresoc.v:156774$8478_Y
+ attribute \src "libresoc.v:156777.18-156777.122"
+ wire width 65 $ternary$libresoc.v:156777$8483_Y
+ attribute \src "libresoc.v:156771.18-156771.120"
+ wire $xor$libresoc.v:156771$8473_Y
+ attribute \src "libresoc.v:156779.18-156779.127"
+ wire $xor$libresoc.v:156779$8485_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
wire \$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
wire input 21 \dividend_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
wire input 20 \divisor_neg
- attribute \src "libresoc.v:158630.7-158630.15"
+ attribute \src "libresoc.v:156431.7-156431.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 50 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
- cell $and $and$libresoc.v:158979$8572
+ cell $and $and$libresoc.v:156780$8486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__is_signed
connect \B \$38
- connect \Y $and$libresoc.v:158979$8572_Y
+ connect \Y $and$libresoc.v:156780$8486_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $pos $extend$libresoc.v:158971$8560
+ cell $pos $extend$libresoc.v:156772$8474
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \quotient_root
- connect \Y $extend$libresoc.v:158971$8560_Y
+ connect \Y $extend$libresoc.v:156772$8474_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
- cell $pos $extend$libresoc.v:158972$8562
+ cell $pos $extend$libresoc.v:156773$8476
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \quotient_root
- connect \Y $extend$libresoc.v:158972$8562_Y
+ connect \Y $extend$libresoc.v:156773$8476_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $pos $extend$libresoc.v:158974$8565
+ cell $pos $extend$libresoc.v:156775$8479
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \remainder [127:64]
- connect \Y $extend$libresoc.v:158974$8565_Y
+ connect \Y $extend$libresoc.v:156775$8479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:158975$8567
+ cell $pos $extend$libresoc.v:156776$8481
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \remainder [127:64]
- connect \Y $extend$libresoc.v:158975$8567_Y
+ connect \Y $extend$libresoc.v:156776$8481_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
- cell $pos $extend$libresoc.v:158983$8576
+ cell $pos $extend$libresoc.v:156784$8490
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:158983$8576_Y
+ connect \Y $extend$libresoc.v:156784$8490_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110"
- cell $pos $extend$libresoc.v:158984$8578
+ cell $pos $extend$libresoc.v:156785$8492
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:158984$8578_Y
+ connect \Y $extend$libresoc.v:156785$8492_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
- cell $pos $extend$libresoc.v:158985$8580
+ cell $pos $extend$libresoc.v:156786$8494
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:158985$8580_Y
+ connect \Y $extend$libresoc.v:156786$8494_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119"
- cell $pos $extend$libresoc.v:158986$8582
+ cell $pos $extend$libresoc.v:156787$8496
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \quotient_65 [31:0]
- connect \Y $extend$libresoc.v:158986$8582_Y
+ connect \Y $extend$libresoc.v:156787$8496_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128"
- cell $pos $extend$libresoc.v:158987$8584
+ cell $pos $extend$libresoc.v:156788$8498
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \remainder_64 [31:0]
- connect \Y $extend$libresoc.v:158987$8584_Y
+ connect \Y $extend$libresoc.v:156788$8498_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
- cell $ne $ne$libresoc.v:158980$8573
+ cell $ne $ne$libresoc.v:156781$8487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \quotient_65 [32]
connect \B \quotient_65 [31]
- connect \Y $ne$libresoc.v:158980$8573_Y
+ connect \Y $ne$libresoc.v:156781$8487_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $neg $neg$libresoc.v:158971$8561
+ cell $neg $neg$libresoc.v:156772$8475
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158971$8560_Y
- connect \Y $neg$libresoc.v:158971$8561_Y
+ connect \A $extend$libresoc.v:156772$8474_Y
+ connect \Y $neg$libresoc.v:156772$8475_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $neg $neg$libresoc.v:158974$8566
+ cell $neg $neg$libresoc.v:156775$8480
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158974$8565_Y
- connect \Y $neg$libresoc.v:158974$8566_Y
+ connect \A $extend$libresoc.v:156775$8479_Y
+ connect \Y $neg$libresoc.v:156775$8480_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78"
- cell $not $not$libresoc.v:158977$8570
+ cell $not $not$libresoc.v:156778$8484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \logical_op__is_32bit
- connect \Y $not$libresoc.v:158977$8570_Y
+ connect \Y $not$libresoc.v:156778$8484_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102"
- cell $not $not$libresoc.v:158982$8575
+ cell $not $not$libresoc.v:156783$8489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ov
- connect \Y $not$libresoc.v:158982$8575_Y
+ connect \Y $not$libresoc.v:156783$8489_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
- cell $pos $pos$libresoc.v:158972$8563
+ cell $pos $pos$libresoc.v:156773$8477
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158972$8562_Y
- connect \Y $pos$libresoc.v:158972$8563_Y
+ connect \A $extend$libresoc.v:156773$8476_Y
+ connect \Y $pos$libresoc.v:156773$8477_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:158975$8568
+ cell $pos $pos$libresoc.v:156776$8482
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:158975$8567_Y
- connect \Y $pos$libresoc.v:158975$8568_Y
+ connect \A $extend$libresoc.v:156776$8481_Y
+ connect \Y $pos$libresoc.v:156776$8482_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97"
- cell $pos $pos$libresoc.v:158981$8574
+ cell $pos $pos$libresoc.v:156782$8488
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 }
- connect \Y $pos$libresoc.v:158981$8574_Y
+ connect \Y $pos$libresoc.v:156782$8488_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
- cell $pos $pos$libresoc.v:158983$8577
+ cell $pos $pos$libresoc.v:156784$8491
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:158983$8576_Y
- connect \Y $pos$libresoc.v:158983$8577_Y
+ connect \A $extend$libresoc.v:156784$8490_Y
+ connect \Y $pos$libresoc.v:156784$8491_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110"
- cell $pos $pos$libresoc.v:158984$8579
+ cell $pos $pos$libresoc.v:156785$8493
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:158984$8578_Y
- connect \Y $pos$libresoc.v:158984$8579_Y
+ connect \A $extend$libresoc.v:156785$8492_Y
+ connect \Y $pos$libresoc.v:156785$8493_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
- cell $pos $pos$libresoc.v:158985$8581
+ cell $pos $pos$libresoc.v:156786$8495
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:158985$8580_Y
- connect \Y $pos$libresoc.v:158985$8581_Y
+ connect \A $extend$libresoc.v:156786$8494_Y
+ connect \Y $pos$libresoc.v:156786$8495_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119"
- cell $pos $pos$libresoc.v:158986$8583
+ cell $pos $pos$libresoc.v:156787$8497
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:158986$8582_Y
- connect \Y $pos$libresoc.v:158986$8583_Y
+ connect \A $extend$libresoc.v:156787$8496_Y
+ connect \Y $pos$libresoc.v:156787$8497_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128"
- cell $pos $pos$libresoc.v:158987$8585
+ cell $pos $pos$libresoc.v:156788$8499
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:158987$8584_Y
- connect \Y $pos$libresoc.v:158987$8585_Y
+ connect \A $extend$libresoc.v:156788$8498_Y
+ connect \Y $pos$libresoc.v:156788$8499_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
- cell $mux $ternary$libresoc.v:158973$8564
+ cell $mux $ternary$libresoc.v:156774$8478
parameter \WIDTH 65
connect \A \$25
connect \B \$23
connect \S \quotient_neg
- connect \Y $ternary$libresoc.v:158973$8564_Y
+ connect \Y $ternary$libresoc.v:156774$8478_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
- cell $mux $ternary$libresoc.v:158976$8569
+ cell $mux $ternary$libresoc.v:156777$8483
parameter \WIDTH 65
connect \A \$32
connect \B \$30
connect \S \remainder_neg
- connect \Y $ternary$libresoc.v:158976$8569_Y
+ connect \Y $ternary$libresoc.v:156777$8483_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
- cell $xor $xor$libresoc.v:158970$8559
+ cell $xor $xor$libresoc.v:156771$8473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dividend_neg
connect \B \divisor_neg
- connect \Y $xor$libresoc.v:158970$8559_Y
+ connect \Y $xor$libresoc.v:156771$8473_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
- cell $xor $xor$libresoc.v:158978$8571
+ cell $xor $xor$libresoc.v:156779$8485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \quotient_65 [64]
connect \B \quotient_65 [63]
- connect \Y $xor$libresoc.v:158978$8571_Y
+ connect \Y $xor$libresoc.v:156779$8485_Y
end
- attribute \src "libresoc.v:158630.7-158630.20"
- process $proc$libresoc.v:158630$8588
+ attribute \src "libresoc.v:156431.7-156431.20"
+ process $proc$libresoc.v:156431$8502
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:158988.3-159059.6"
- process $proc$libresoc.v:158988$8586
+ attribute \src "libresoc.v:156789.3-156860.6"
+ process $proc$libresoc.v:156789$8500
assign { } { }
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:158989.5-158989.29"
+ attribute \src "libresoc.v:156790.5-156790.29"
switch \initial
- attribute \src "libresoc.v:158989.9-158989.17"
+ attribute \src "libresoc.v:156790.9-156790.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:159060.3-159093.6"
- process $proc$libresoc.v:159060$8587
+ attribute \src "libresoc.v:156861.3-156894.6"
+ process $proc$libresoc.v:156861$8501
assign { } { }
assign $0\ov[0:0] $1\ov[0:0]
- attribute \src "libresoc.v:159061.5-159061.29"
+ attribute \src "libresoc.v:156862.5-156862.29"
switch \initial
- attribute \src "libresoc.v:159061.9-159061.17"
+ attribute \src "libresoc.v:156862.9-156862.17"
case 1'1
case
end
sync always
update \ov $0\ov[0:0]
end
- connect \$21 $xor$libresoc.v:158970$8559_Y
- connect \$23 $neg$libresoc.v:158971$8561_Y
- connect \$25 $pos$libresoc.v:158972$8563_Y
- connect \$27 $ternary$libresoc.v:158973$8564_Y
- connect \$30 $neg$libresoc.v:158974$8566_Y
- connect \$32 $pos$libresoc.v:158975$8568_Y
- connect \$34 $ternary$libresoc.v:158976$8569_Y
- connect \$36 $not$libresoc.v:158977$8570_Y
- connect \$38 $xor$libresoc.v:158978$8571_Y
- connect \$40 $and$libresoc.v:158979$8572_Y
- connect \$42 $ne$libresoc.v:158980$8573_Y
- connect \$44 $pos$libresoc.v:158981$8574_Y
- connect \$46 $not$libresoc.v:158982$8575_Y
- connect \$48 $pos$libresoc.v:158983$8577_Y
- connect \$50 $pos$libresoc.v:158984$8579_Y
- connect \$52 $pos$libresoc.v:158985$8581_Y
- connect \$54 $pos$libresoc.v:158986$8583_Y
- connect \$56 $pos$libresoc.v:158987$8585_Y
+ connect \$21 $xor$libresoc.v:156771$8473_Y
+ connect \$23 $neg$libresoc.v:156772$8475_Y
+ connect \$25 $pos$libresoc.v:156773$8477_Y
+ connect \$27 $ternary$libresoc.v:156774$8478_Y
+ connect \$30 $neg$libresoc.v:156775$8480_Y
+ connect \$32 $pos$libresoc.v:156776$8482_Y
+ connect \$34 $ternary$libresoc.v:156777$8483_Y
+ connect \$36 $not$libresoc.v:156778$8484_Y
+ connect \$38 $xor$libresoc.v:156779$8485_Y
+ connect \$40 $and$libresoc.v:156780$8486_Y
+ connect \$42 $ne$libresoc.v:156781$8487_Y
+ connect \$44 $pos$libresoc.v:156782$8488_Y
+ connect \$46 $not$libresoc.v:156783$8489_Y
+ connect \$48 $pos$libresoc.v:156784$8491_Y
+ connect \$50 $pos$libresoc.v:156785$8493_Y
+ connect \$52 $pos$libresoc.v:156786$8495_Y
+ connect \$54 $pos$libresoc.v:156787$8497_Y
+ connect \$56 $pos$libresoc.v:156788$8499_Y
connect \$29 \$34
connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \muxid$1 \muxid
connect \remainder_neg \dividend_neg
connect \quotient_neg \$21
end
-attribute \src "libresoc.v:159111.1-159122.10"
+attribute \src "libresoc.v:156912.1-156923.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p"
attribute \generator "nMigen"
module \p
- attribute \src "libresoc.v:159120.17-159120.111"
- wire $and$libresoc.v:159120$8589_Y
+ attribute \src "libresoc.v:156921.17-156921.111"
+ wire $and$libresoc.v:156921$8503_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159120$8589
+ cell $and $and$libresoc.v:156921$8503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159120$8589_Y
+ connect \Y $and$libresoc.v:156921$8503_Y
end
- connect \$1 $and$libresoc.v:159120$8589_Y
+ connect \$1 $and$libresoc.v:156921$8503_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159126.1-159137.10"
+attribute \src "libresoc.v:156927.1-156938.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p"
attribute \generator "nMigen"
module \p$1
- attribute \src "libresoc.v:159135.17-159135.111"
- wire $and$libresoc.v:159135$8590_Y
+ attribute \src "libresoc.v:156936.17-156936.111"
+ wire $and$libresoc.v:156936$8504_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159135$8590
+ cell $and $and$libresoc.v:156936$8504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159135$8590_Y
+ connect \Y $and$libresoc.v:156936$8504_Y
end
- connect \$1 $and$libresoc.v:159135$8590_Y
+ connect \$1 $and$libresoc.v:156936$8504_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159141.1-159152.10"
+attribute \src "libresoc.v:156942.1-156953.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p"
attribute \generator "nMigen"
module \p$108
- attribute \src "libresoc.v:159150.17-159150.111"
- wire $and$libresoc.v:159150$8591_Y
+ attribute \src "libresoc.v:156951.17-156951.111"
+ wire $and$libresoc.v:156951$8505_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159150$8591
+ cell $and $and$libresoc.v:156951$8505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159150$8591_Y
+ connect \Y $and$libresoc.v:156951$8505_Y
end
- connect \$1 $and$libresoc.v:159150$8591_Y
+ connect \$1 $and$libresoc.v:156951$8505_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159156.1-159167.10"
+attribute \src "libresoc.v:156957.1-156968.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p"
attribute \generator "nMigen"
module \p$111
- attribute \src "libresoc.v:159165.17-159165.111"
- wire $and$libresoc.v:159165$8592_Y
+ attribute \src "libresoc.v:156966.17-156966.111"
+ wire $and$libresoc.v:156966$8506_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159165$8592
+ cell $and $and$libresoc.v:156966$8506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159165$8592_Y
+ connect \Y $and$libresoc.v:156966$8506_Y
end
- connect \$1 $and$libresoc.v:159165$8592_Y
+ connect \$1 $and$libresoc.v:156966$8506_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159171.1-159182.10"
+attribute \src "libresoc.v:156972.1-156983.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p"
attribute \generator "nMigen"
module \p$116
- attribute \src "libresoc.v:159180.17-159180.111"
- wire $and$libresoc.v:159180$8593_Y
+ attribute \src "libresoc.v:156981.17-156981.111"
+ wire $and$libresoc.v:156981$8507_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159180$8593
+ cell $and $and$libresoc.v:156981$8507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159180$8593_Y
+ connect \Y $and$libresoc.v:156981$8507_Y
end
- connect \$1 $and$libresoc.v:159180$8593_Y
+ connect \$1 $and$libresoc.v:156981$8507_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159186.1-159197.10"
+attribute \src "libresoc.v:156987.1-156998.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p"
attribute \generator "nMigen"
module \p$17
- attribute \src "libresoc.v:159195.17-159195.111"
- wire $and$libresoc.v:159195$8594_Y
+ attribute \src "libresoc.v:156996.17-156996.111"
+ wire $and$libresoc.v:156996$8508_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159195$8594
+ cell $and $and$libresoc.v:156996$8508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159195$8594_Y
+ connect \Y $and$libresoc.v:156996$8508_Y
end
- connect \$1 $and$libresoc.v:159195$8594_Y
+ connect \$1 $and$libresoc.v:156996$8508_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159201.1-159212.10"
+attribute \src "libresoc.v:157002.1-157013.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p"
attribute \generator "nMigen"
module \p$20
- attribute \src "libresoc.v:159210.17-159210.111"
- wire $and$libresoc.v:159210$8595_Y
+ attribute \src "libresoc.v:157011.17-157011.111"
+ wire $and$libresoc.v:157011$8509_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159210$8595
+ cell $and $and$libresoc.v:157011$8509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159210$8595_Y
+ connect \Y $and$libresoc.v:157011$8509_Y
end
- connect \$1 $and$libresoc.v:159210$8595_Y
+ connect \$1 $and$libresoc.v:157011$8509_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159216.1-159227.10"
+attribute \src "libresoc.v:157017.1-157028.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p"
attribute \generator "nMigen"
module \p$3
- attribute \src "libresoc.v:159225.17-159225.111"
- wire $and$libresoc.v:159225$8596_Y
+ attribute \src "libresoc.v:157026.17-157026.111"
+ wire $and$libresoc.v:157026$8510_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159225$8596
+ cell $and $and$libresoc.v:157026$8510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159225$8596_Y
+ connect \Y $and$libresoc.v:157026$8510_Y
end
- connect \$1 $and$libresoc.v:159225$8596_Y
+ connect \$1 $and$libresoc.v:157026$8510_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159231.1-159242.10"
+attribute \src "libresoc.v:157032.1-157043.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p"
attribute \generator "nMigen"
module \p$30
- attribute \src "libresoc.v:159240.17-159240.111"
- wire $and$libresoc.v:159240$8597_Y
+ attribute \src "libresoc.v:157041.17-157041.111"
+ wire $and$libresoc.v:157041$8511_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159240$8597
+ cell $and $and$libresoc.v:157041$8511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159240$8597_Y
+ connect \Y $and$libresoc.v:157041$8511_Y
end
- connect \$1 $and$libresoc.v:159240$8597_Y
+ connect \$1 $and$libresoc.v:157041$8511_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159246.1-159257.10"
+attribute \src "libresoc.v:157047.1-157058.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p"
attribute \generator "nMigen"
module \p$33
- attribute \src "libresoc.v:159255.17-159255.111"
- wire $and$libresoc.v:159255$8598_Y
+ attribute \src "libresoc.v:157056.17-157056.111"
+ wire $and$libresoc.v:157056$8512_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159255$8598
+ cell $and $and$libresoc.v:157056$8512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159255$8598_Y
+ connect \Y $and$libresoc.v:157056$8512_Y
end
- connect \$1 $and$libresoc.v:159255$8598_Y
+ connect \$1 $and$libresoc.v:157056$8512_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159261.1-159272.10"
+attribute \src "libresoc.v:157062.1-157073.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p"
attribute \generator "nMigen"
module \p$36
- attribute \src "libresoc.v:159270.17-159270.111"
- wire $and$libresoc.v:159270$8599_Y
+ attribute \src "libresoc.v:157071.17-157071.111"
+ wire $and$libresoc.v:157071$8513_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159270$8599
+ cell $and $and$libresoc.v:157071$8513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159270$8599_Y
+ connect \Y $and$libresoc.v:157071$8513_Y
end
- connect \$1 $and$libresoc.v:159270$8599_Y
+ connect \$1 $and$libresoc.v:157071$8513_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159276.1-159287.10"
+attribute \src "libresoc.v:157077.1-157088.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p"
attribute \generator "nMigen"
module \p$46
- attribute \src "libresoc.v:159285.17-159285.111"
- wire $and$libresoc.v:159285$8600_Y
+ attribute \src "libresoc.v:157086.17-157086.111"
+ wire $and$libresoc.v:157086$8514_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159285$8600
+ cell $and $and$libresoc.v:157086$8514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159285$8600_Y
+ connect \Y $and$libresoc.v:157086$8514_Y
end
- connect \$1 $and$libresoc.v:159285$8600_Y
+ connect \$1 $and$libresoc.v:157086$8514_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159291.1-159302.10"
+attribute \src "libresoc.v:157092.1-157103.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p"
attribute \generator "nMigen"
module \p$48
- attribute \src "libresoc.v:159300.17-159300.111"
- wire $and$libresoc.v:159300$8601_Y
+ attribute \src "libresoc.v:157101.17-157101.111"
+ wire $and$libresoc.v:157101$8515_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159300$8601
+ cell $and $and$libresoc.v:157101$8515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159300$8601_Y
+ connect \Y $and$libresoc.v:157101$8515_Y
end
- connect \$1 $and$libresoc.v:159300$8601_Y
+ connect \$1 $and$libresoc.v:157101$8515_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159306.1-159317.10"
+attribute \src "libresoc.v:157107.1-157118.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p"
attribute \generator "nMigen"
module \p$5
- attribute \src "libresoc.v:159315.17-159315.111"
- wire $and$libresoc.v:159315$8602_Y
+ attribute \src "libresoc.v:157116.17-157116.111"
+ wire $and$libresoc.v:157116$8516_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159315$8602
+ cell $and $and$libresoc.v:157116$8516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159315$8602_Y
+ connect \Y $and$libresoc.v:157116$8516_Y
end
- connect \$1 $and$libresoc.v:159315$8602_Y
+ connect \$1 $and$libresoc.v:157116$8516_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159321.1-159332.10"
+attribute \src "libresoc.v:157122.1-157133.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p"
attribute \generator "nMigen"
module \p$52
- attribute \src "libresoc.v:159330.17-159330.111"
- wire $and$libresoc.v:159330$8603_Y
+ attribute \src "libresoc.v:157131.17-157131.111"
+ wire $and$libresoc.v:157131$8517_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159330$8603
+ cell $and $and$libresoc.v:157131$8517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159330$8603_Y
+ connect \Y $and$libresoc.v:157131$8517_Y
end
- connect \$1 $and$libresoc.v:159330$8603_Y
+ connect \$1 $and$libresoc.v:157131$8517_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159336.1-159347.10"
+attribute \src "libresoc.v:157137.1-157148.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p"
attribute \generator "nMigen"
module \p$62
- attribute \src "libresoc.v:159345.17-159345.111"
- wire $and$libresoc.v:159345$8604_Y
+ attribute \src "libresoc.v:157146.17-157146.111"
+ wire $and$libresoc.v:157146$8518_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159345$8604
+ cell $and $and$libresoc.v:157146$8518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159345$8604_Y
+ connect \Y $and$libresoc.v:157146$8518_Y
end
- connect \$1 $and$libresoc.v:159345$8604_Y
+ connect \$1 $and$libresoc.v:157146$8518_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159351.1-159362.10"
+attribute \src "libresoc.v:157152.1-157163.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p"
attribute \generator "nMigen"
module \p$65
- attribute \src "libresoc.v:159360.17-159360.111"
- wire $and$libresoc.v:159360$8605_Y
+ attribute \src "libresoc.v:157161.17-157161.111"
+ wire $and$libresoc.v:157161$8519_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159360$8605
+ cell $and $and$libresoc.v:157161$8519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159360$8605_Y
+ connect \Y $and$libresoc.v:157161$8519_Y
end
- connect \$1 $and$libresoc.v:159360$8605_Y
+ connect \$1 $and$libresoc.v:157161$8519_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159366.1-159377.10"
+attribute \src "libresoc.v:157167.1-157178.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p"
attribute \generator "nMigen"
module \p$7
- attribute \src "libresoc.v:159375.17-159375.111"
- wire $and$libresoc.v:159375$8606_Y
+ attribute \src "libresoc.v:157176.17-157176.111"
+ wire $and$libresoc.v:157176$8520_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159375$8606
+ cell $and $and$libresoc.v:157176$8520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159375$8606_Y
+ connect \Y $and$libresoc.v:157176$8520_Y
end
- connect \$1 $and$libresoc.v:159375$8606_Y
+ connect \$1 $and$libresoc.v:157176$8520_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159381.1-159392.10"
+attribute \src "libresoc.v:157182.1-157193.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p"
attribute \generator "nMigen"
module \p$74
- attribute \src "libresoc.v:159390.17-159390.111"
- wire $and$libresoc.v:159390$8607_Y
+ attribute \src "libresoc.v:157191.17-157191.111"
+ wire $and$libresoc.v:157191$8521_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159390$8607
+ cell $and $and$libresoc.v:157191$8521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159390$8607_Y
+ connect \Y $and$libresoc.v:157191$8521_Y
end
- connect \$1 $and$libresoc.v:159390$8607_Y
+ connect \$1 $and$libresoc.v:157191$8521_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159396.1-159407.10"
+attribute \src "libresoc.v:157197.1-157208.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p"
attribute \generator "nMigen"
module \p$76
- attribute \src "libresoc.v:159405.17-159405.111"
- wire $and$libresoc.v:159405$8608_Y
+ attribute \src "libresoc.v:157206.17-157206.111"
+ wire $and$libresoc.v:157206$8522_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159405$8608
+ cell $and $and$libresoc.v:157206$8522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159405$8608_Y
+ connect \Y $and$libresoc.v:157206$8522_Y
end
- connect \$1 $and$libresoc.v:159405$8608_Y
+ connect \$1 $and$libresoc.v:157206$8522_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159411.1-159422.10"
+attribute \src "libresoc.v:157212.1-157223.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p"
attribute \generator "nMigen"
module \p$79
- attribute \src "libresoc.v:159420.17-159420.111"
- wire $and$libresoc.v:159420$8609_Y
+ attribute \src "libresoc.v:157221.17-157221.111"
+ wire $and$libresoc.v:157221$8523_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159420$8609
+ cell $and $and$libresoc.v:157221$8523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159420$8609_Y
+ connect \Y $and$libresoc.v:157221$8523_Y
end
- connect \$1 $and$libresoc.v:159420$8609_Y
+ connect \$1 $and$libresoc.v:157221$8523_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159426.1-159437.10"
+attribute \src "libresoc.v:157227.1-157238.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p"
attribute \generator "nMigen"
module \p$81
- attribute \src "libresoc.v:159435.17-159435.111"
- wire $and$libresoc.v:159435$8610_Y
+ attribute \src "libresoc.v:157236.17-157236.111"
+ wire $and$libresoc.v:157236$8524_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159435$8610
+ cell $and $and$libresoc.v:157236$8524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159435$8610_Y
+ connect \Y $and$libresoc.v:157236$8524_Y
end
- connect \$1 $and$libresoc.v:159435$8610_Y
+ connect \$1 $and$libresoc.v:157236$8524_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159441.1-159452.10"
+attribute \src "libresoc.v:157242.1-157253.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p"
attribute \generator "nMigen"
module \p$91
- attribute \src "libresoc.v:159450.17-159450.111"
- wire $and$libresoc.v:159450$8611_Y
+ attribute \src "libresoc.v:157251.17-157251.111"
+ wire $and$libresoc.v:157251$8525_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159450$8611
+ cell $and $and$libresoc.v:157251$8525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159450$8611_Y
+ connect \Y $and$libresoc.v:157251$8525_Y
end
- connect \$1 $and$libresoc.v:159450$8611_Y
+ connect \$1 $and$libresoc.v:157251$8525_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159456.1-159467.10"
+attribute \src "libresoc.v:157257.1-157268.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p"
attribute \generator "nMigen"
module \p$93
- attribute \src "libresoc.v:159465.17-159465.111"
- wire $and$libresoc.v:159465$8612_Y
+ attribute \src "libresoc.v:157266.17-157266.111"
+ wire $and$libresoc.v:157266$8526_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159465$8612
+ cell $and $and$libresoc.v:157266$8526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159465$8612_Y
+ connect \Y $and$libresoc.v:157266$8526_Y
end
- connect \$1 $and$libresoc.v:159465$8612_Y
+ connect \$1 $and$libresoc.v:157266$8526_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159471.1-159482.10"
+attribute \src "libresoc.v:157272.1-157283.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p"
attribute \generator "nMigen"
module \p$96
- attribute \src "libresoc.v:159480.17-159480.111"
- wire $and$libresoc.v:159480$8613_Y
+ attribute \src "libresoc.v:157281.17-157281.111"
+ wire $and$libresoc.v:157281$8527_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159480$8613
+ cell $and $and$libresoc.v:157281$8527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159480$8613_Y
+ connect \Y $and$libresoc.v:157281$8527_Y
end
- connect \$1 $and$libresoc.v:159480$8613_Y
+ connect \$1 $and$libresoc.v:157281$8527_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159486.1-159497.10"
+attribute \src "libresoc.v:157287.1-157298.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p"
attribute \generator "nMigen"
module \p$98
- attribute \src "libresoc.v:159495.17-159495.111"
- wire $and$libresoc.v:159495$8614_Y
+ attribute \src "libresoc.v:157296.17-157296.111"
+ wire $and$libresoc.v:157296$8528_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164"
wire \trigger
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211"
- cell $and $and$libresoc.v:159495$8614
+ cell $and $and$libresoc.v:157296$8528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i
connect \B \p_ready_o
- connect \Y $and$libresoc.v:159495$8614_Y
+ connect \Y $and$libresoc.v:157296$8528_Y
end
- connect \$1 $and$libresoc.v:159495$8614_Y
+ connect \$1 $and$libresoc.v:157296$8528_Y
connect \trigger \$1
end
-attribute \src "libresoc.v:159501.1-159524.10"
+attribute \src "libresoc.v:157302.1-157325.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick"
attribute \generator "nMigen"
module \pick
- attribute \src "libresoc.v:159502.7-159502.20"
+ attribute \src "libresoc.v:157303.7-157303.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:159513.3-159522.6"
+ attribute \src "libresoc.v:157314.3-157323.6"
wire $0\o[0:0]
- attribute \src "libresoc.v:159513.3-159522.6"
+ attribute \src "libresoc.v:157314.3-157323.6"
wire $1\o[0:0]
- attribute \src "libresoc.v:159512.17-159512.95"
- wire $eq$libresoc.v:159512$8615_Y
+ attribute \src "libresoc.v:157313.17-157313.95"
+ wire $eq$libresoc.v:157313$8529_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
wire input 3 \i
- attribute \src "libresoc.v:159502.7-159502.15"
+ attribute \src "libresoc.v:157303.7-157303.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
wire output 2 \n
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
wire output 1 \o
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
- cell $eq $eq$libresoc.v:159512$8615
+ cell $eq $eq$libresoc.v:157313$8529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \i
connect \B 1'0
- connect \Y $eq$libresoc.v:159512$8615_Y
+ connect \Y $eq$libresoc.v:157313$8529_Y
end
- attribute \src "libresoc.v:159502.7-159502.20"
- process $proc$libresoc.v:159502$8617
+ attribute \src "libresoc.v:157303.7-157303.20"
+ process $proc$libresoc.v:157303$8531
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159513.3-159522.6"
- process $proc$libresoc.v:159513$8616
+ attribute \src "libresoc.v:157314.3-157323.6"
+ process $proc$libresoc.v:157314$8530
assign { } { }
assign { } { }
assign $0\o[0:0] $1\o[0:0]
- attribute \src "libresoc.v:159514.5-159514.29"
+ attribute \src "libresoc.v:157315.5-157315.29"
switch \initial
- attribute \src "libresoc.v:159514.9-159514.17"
+ attribute \src "libresoc.v:157315.9-157315.17"
case 1'1
case
end
sync always
update \o $0\o[0:0]
end
- connect \$1 $eq$libresoc.v:159512$8615_Y
+ connect \$1 $eq$libresoc.v:157313$8529_Y
connect \n \$1
end
-attribute \src "libresoc.v:159528.1-160342.10"
+attribute \src "libresoc.v:157329.1-158143.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem"
attribute \generator "nMigen"
module \pimem
- attribute \src "libresoc.v:160305.3-160320.6"
+ attribute \src "libresoc.v:158106.3-158121.6"
wire $0\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $0\adrok_l_s_addr_acked$next[0:0]$8707
- attribute \src "libresoc.v:159827.3-159828.57"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $0\adrok_l_s_addr_acked$next[0:0]$8621
+ attribute \src "libresoc.v:157628.3-157629.57"
wire $0\adrok_l_s_addr_acked[0:0]
- attribute \src "libresoc.v:159919.3-159927.6"
- wire $0\busy_delay$next[0:0]$8675
- attribute \src "libresoc.v:159825.3-159826.37"
+ attribute \src "libresoc.v:157720.3-157728.6"
+ wire $0\busy_delay$next[0:0]$8589
+ attribute \src "libresoc.v:157626.3-157627.37"
wire $0\busy_delay[0:0]
- attribute \src "libresoc.v:160253.3-160268.6"
+ attribute \src "libresoc.v:158054.3-158069.6"
wire $0\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:160243.3-160252.6"
+ attribute \src "libresoc.v:158044.3-158053.6"
wire $0\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:160233.3-160242.6"
+ attribute \src "libresoc.v:158034.3-158043.6"
wire $0\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:160214.3-160223.6"
+ attribute \src "libresoc.v:158015.3-158024.6"
wire $0\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $0\fsm_state$next[1:0]$8693
- attribute \src "libresoc.v:159817.3-159818.35"
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $0\fsm_state$next[1:0]$8607
+ attribute \src "libresoc.v:157618.3-157619.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:159529.7-159529.20"
+ attribute \src "libresoc.v:157330.7-157330.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:160115.3-160124.6"
+ attribute \src "libresoc.v:157916.3-157925.6"
wire $0\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:159823.3-159824.35"
+ attribute \src "libresoc.v:157624.3-157625.35"
wire $0\lds_dly[0:0]
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $0\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:160105.3-160114.6"
+ attribute \src "libresoc.v:157906.3-157915.6"
wire width 64 $0\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:160125.3-160134.6"
+ attribute \src "libresoc.v:157926.3-157935.6"
wire $0\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:159954.3-159969.6"
+ attribute \src "libresoc.v:157755.3-157770.6"
wire width 4 $0\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:159938.3-159953.6"
+ attribute \src "libresoc.v:157739.3-157754.6"
wire width 4 $0\lenexp_len_i[3:0]
- attribute \src "libresoc.v:160224.3-160232.6"
- wire $0\lsui_active_dly$next[0:0]$8701
- attribute \src "libresoc.v:159815.3-159816.47"
+ attribute \src "libresoc.v:158025.3-158033.6"
+ wire $0\lsui_active_dly$next[0:0]$8615
+ attribute \src "libresoc.v:157616.3-157617.47"
wire $0\lsui_active_dly[0:0]
- attribute \src "libresoc.v:160155.3-160174.6"
+ attribute \src "libresoc.v:157956.3-157975.6"
wire $0\lsui_busy[0:0]
- attribute \src "libresoc.v:159819.3-159820.36"
+ attribute \src "libresoc.v:157620.3-157621.36"
wire $0\reset_delay[0:0]
- attribute \src "libresoc.v:160095.3-160104.6"
+ attribute \src "libresoc.v:157896.3-157905.6"
wire $0\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:160079.3-160094.6"
+ attribute \src "libresoc.v:157880.3-157895.6"
wire $0\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:159928.3-159937.6"
+ attribute \src "libresoc.v:157729.3-157738.6"
wire $0\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:159909.3-159918.6"
+ attribute \src "libresoc.v:157710.3-157719.6"
wire $0\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:159894.3-159908.6"
- wire $0\st_done_s_st_done$next[0:0]$8670
- attribute \src "libresoc.v:159829.3-159830.51"
+ attribute \src "libresoc.v:157695.3-157709.6"
+ wire $0\st_done_s_st_done$next[0:0]$8584
+ attribute \src "libresoc.v:157630.3-157631.51"
wire $0\st_done_s_st_done[0:0]
- attribute \src "libresoc.v:160135.3-160144.6"
+ attribute \src "libresoc.v:157936.3-157945.6"
wire width 64 $0\stdata[63:0]
- attribute \src "libresoc.v:159821.3-159822.35"
+ attribute \src "libresoc.v:157622.3-157623.35"
wire $0\sts_dly[0:0]
- attribute \src "libresoc.v:159970.3-159995.6"
+ attribute \src "libresoc.v:157771.3-157796.6"
wire $0\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:160022.3-160047.6"
+ attribute \src "libresoc.v:157823.3-157848.6"
wire width 48 $0\x_addr_i[47:0]
- attribute \src "libresoc.v:159996.3-160021.6"
+ attribute \src "libresoc.v:157797.3-157822.6"
wire width 8 $0\x_mask_i[7:0]
- attribute \src "libresoc.v:160145.3-160154.6"
+ attribute \src "libresoc.v:157946.3-157955.6"
wire width 64 $0\x_st_data_i[63:0]
- attribute \src "libresoc.v:160305.3-160320.6"
+ attribute \src "libresoc.v:158106.3-158121.6"
wire $1\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $1\adrok_l_s_addr_acked$next[0:0]$8708
- attribute \src "libresoc.v:159623.7-159623.34"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $1\adrok_l_s_addr_acked$next[0:0]$8622
+ attribute \src "libresoc.v:157424.7-157424.34"
wire $1\adrok_l_s_addr_acked[0:0]
- attribute \src "libresoc.v:159919.3-159927.6"
- wire $1\busy_delay$next[0:0]$8676
- attribute \src "libresoc.v:159627.7-159627.24"
+ attribute \src "libresoc.v:157720.3-157728.6"
+ wire $1\busy_delay$next[0:0]$8590
+ attribute \src "libresoc.v:157428.7-157428.24"
wire $1\busy_delay[0:0]
- attribute \src "libresoc.v:160253.3-160268.6"
+ attribute \src "libresoc.v:158054.3-158069.6"
wire $1\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:160243.3-160252.6"
+ attribute \src "libresoc.v:158044.3-158053.6"
wire $1\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:160233.3-160242.6"
+ attribute \src "libresoc.v:158034.3-158043.6"
wire $1\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:160214.3-160223.6"
+ attribute \src "libresoc.v:158015.3-158024.6"
wire $1\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $1\fsm_state$next[1:0]$8694
- attribute \src "libresoc.v:159649.13-159649.29"
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $1\fsm_state$next[1:0]$8608
+ attribute \src "libresoc.v:157450.13-157450.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:160115.3-160124.6"
+ attribute \src "libresoc.v:157916.3-157925.6"
wire $1\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:159663.7-159663.21"
+ attribute \src "libresoc.v:157464.7-157464.21"
wire $1\lds_dly[0:0]
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $1\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:160105.3-160114.6"
+ attribute \src "libresoc.v:157906.3-157915.6"
wire width 64 $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:160125.3-160134.6"
+ attribute \src "libresoc.v:157926.3-157935.6"
wire $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:159954.3-159969.6"
+ attribute \src "libresoc.v:157755.3-157770.6"
wire width 4 $1\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:159938.3-159953.6"
+ attribute \src "libresoc.v:157739.3-157754.6"
wire width 4 $1\lenexp_len_i[3:0]
- attribute \src "libresoc.v:160224.3-160232.6"
- wire $1\lsui_active_dly$next[0:0]$8702
- attribute \src "libresoc.v:159706.7-159706.29"
+ attribute \src "libresoc.v:158025.3-158033.6"
+ wire $1\lsui_active_dly$next[0:0]$8616
+ attribute \src "libresoc.v:157507.7-157507.29"
wire $1\lsui_active_dly[0:0]
- attribute \src "libresoc.v:160155.3-160174.6"
+ attribute \src "libresoc.v:157956.3-157975.6"
wire $1\lsui_busy[0:0]
- attribute \src "libresoc.v:159718.7-159718.25"
+ attribute \src "libresoc.v:157519.7-157519.25"
wire $1\reset_delay[0:0]
- attribute \src "libresoc.v:160095.3-160104.6"
+ attribute \src "libresoc.v:157896.3-157905.6"
wire $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:160079.3-160094.6"
+ attribute \src "libresoc.v:157880.3-157895.6"
wire $1\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:159928.3-159937.6"
+ attribute \src "libresoc.v:157729.3-157738.6"
wire $1\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:159909.3-159918.6"
+ attribute \src "libresoc.v:157710.3-157719.6"
wire $1\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:159894.3-159908.6"
- wire $1\st_done_s_st_done$next[0:0]$8671
- attribute \src "libresoc.v:159738.7-159738.31"
+ attribute \src "libresoc.v:157695.3-157709.6"
+ wire $1\st_done_s_st_done$next[0:0]$8585
+ attribute \src "libresoc.v:157539.7-157539.31"
wire $1\st_done_s_st_done[0:0]
- attribute \src "libresoc.v:160135.3-160144.6"
+ attribute \src "libresoc.v:157936.3-157945.6"
wire width 64 $1\stdata[63:0]
- attribute \src "libresoc.v:159746.7-159746.21"
+ attribute \src "libresoc.v:157547.7-157547.21"
wire $1\sts_dly[0:0]
- attribute \src "libresoc.v:159970.3-159995.6"
+ attribute \src "libresoc.v:157771.3-157796.6"
wire $1\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:160022.3-160047.6"
+ attribute \src "libresoc.v:157823.3-157848.6"
wire width 48 $1\x_addr_i[47:0]
- attribute \src "libresoc.v:159996.3-160021.6"
+ attribute \src "libresoc.v:157797.3-157822.6"
wire width 8 $1\x_mask_i[7:0]
- attribute \src "libresoc.v:160145.3-160154.6"
+ attribute \src "libresoc.v:157946.3-157955.6"
wire width 64 $1\x_st_data_i[63:0]
- attribute \src "libresoc.v:160305.3-160320.6"
+ attribute \src "libresoc.v:158106.3-158121.6"
wire $2\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $2\adrok_l_s_addr_acked$next[0:0]$8709
- attribute \src "libresoc.v:160253.3-160268.6"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $2\adrok_l_s_addr_acked$next[0:0]$8623
+ attribute \src "libresoc.v:158054.3-158069.6"
wire $2\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $2\fsm_state$next[1:0]$8695
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $2\fsm_state$next[1:0]$8609
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $2\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:159954.3-159969.6"
+ attribute \src "libresoc.v:157755.3-157770.6"
wire width 4 $2\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:159938.3-159953.6"
+ attribute \src "libresoc.v:157739.3-157754.6"
wire width 4 $2\lenexp_len_i[3:0]
- attribute \src "libresoc.v:160155.3-160174.6"
+ attribute \src "libresoc.v:157956.3-157975.6"
wire $2\lsui_busy[0:0]
- attribute \src "libresoc.v:160079.3-160094.6"
+ attribute \src "libresoc.v:157880.3-157895.6"
wire $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:159894.3-159908.6"
- wire $2\st_done_s_st_done$next[0:0]$8672
- attribute \src "libresoc.v:159970.3-159995.6"
+ attribute \src "libresoc.v:157695.3-157709.6"
+ wire $2\st_done_s_st_done$next[0:0]$8586
+ attribute \src "libresoc.v:157771.3-157796.6"
wire $2\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:160022.3-160047.6"
+ attribute \src "libresoc.v:157823.3-157848.6"
wire width 48 $2\x_addr_i[47:0]
- attribute \src "libresoc.v:159996.3-160021.6"
+ attribute \src "libresoc.v:157797.3-157822.6"
wire width 8 $2\x_mask_i[7:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $3\adrok_l_s_addr_acked$next[0:0]$8710
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $3\fsm_state$next[1:0]$8696
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $3\adrok_l_s_addr_acked$next[0:0]$8624
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $3\fsm_state$next[1:0]$8610
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $3\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:159970.3-159995.6"
+ attribute \src "libresoc.v:157771.3-157796.6"
wire $3\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:160022.3-160047.6"
+ attribute \src "libresoc.v:157823.3-157848.6"
wire width 48 $3\x_addr_i[47:0]
- attribute \src "libresoc.v:159996.3-160021.6"
+ attribute \src "libresoc.v:157797.3-157822.6"
wire width 8 $3\x_mask_i[7:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $4\adrok_l_s_addr_acked$next[0:0]$8711
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $4\fsm_state$next[1:0]$8697
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $4\adrok_l_s_addr_acked$next[0:0]$8625
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $4\fsm_state$next[1:0]$8611
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $4\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:159970.3-159995.6"
+ attribute \src "libresoc.v:157771.3-157796.6"
wire $4\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:160022.3-160047.6"
+ attribute \src "libresoc.v:157823.3-157848.6"
wire width 48 $4\x_addr_i[47:0]
- attribute \src "libresoc.v:159996.3-160021.6"
+ attribute \src "libresoc.v:157797.3-157822.6"
wire width 8 $4\x_mask_i[7:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $5\adrok_l_s_addr_acked$next[0:0]$8712
- attribute \src "libresoc.v:160175.3-160213.6"
- wire width 2 $5\fsm_state$next[1:0]$8698
- attribute \src "libresoc.v:160048.3-160078.6"
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $5\adrok_l_s_addr_acked$next[0:0]$8626
+ attribute \src "libresoc.v:157976.3-158014.6"
+ wire width 2 $5\fsm_state$next[1:0]$8612
+ attribute \src "libresoc.v:157849.3-157879.6"
wire $5\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:160269.3-160304.6"
- wire $6\adrok_l_s_addr_acked$next[0:0]$8713
- attribute \src "libresoc.v:159775.18-159775.115"
- wire $and$libresoc.v:159775$8619_Y
- attribute \src "libresoc.v:159777.18-159777.95"
- wire $and$libresoc.v:159777$8621_Y
- attribute \src "libresoc.v:159779.17-159779.138"
- wire $and$libresoc.v:159779$8623_Y
- attribute \src "libresoc.v:159780.18-159780.95"
- wire $and$libresoc.v:159780$8624_Y
- attribute \src "libresoc.v:159783.18-159783.136"
- wire $and$libresoc.v:159783$8629_Y
- attribute \src "libresoc.v:159784.18-159784.136"
- wire $and$libresoc.v:159784$8630_Y
- attribute \src "libresoc.v:159785.18-159785.136"
- wire $and$libresoc.v:159785$8631_Y
- attribute \src "libresoc.v:159786.18-159786.136"
- wire $and$libresoc.v:159786$8632_Y
- attribute \src "libresoc.v:159787.18-159787.136"
- wire $and$libresoc.v:159787$8633_Y
- attribute \src "libresoc.v:159792.18-159792.119"
- wire width 176 $and$libresoc.v:159792$8638_Y
- attribute \src "libresoc.v:159795.18-159795.136"
- wire $and$libresoc.v:159795$8641_Y
- attribute \src "libresoc.v:159796.18-159796.136"
- wire $and$libresoc.v:159796$8642_Y
- attribute \src "libresoc.v:159798.18-159798.139"
- wire $and$libresoc.v:159798$8644_Y
- attribute \src "libresoc.v:159802.18-159802.139"
- wire $and$libresoc.v:159802$8648_Y
- attribute \src "libresoc.v:159804.18-159804.114"
- wire $and$libresoc.v:159804$8650_Y
- attribute \src "libresoc.v:159806.18-159806.114"
- wire $and$libresoc.v:159806$8652_Y
- attribute \src "libresoc.v:159810.18-159810.103"
- wire $and$libresoc.v:159810$8656_Y
- attribute \src "libresoc.v:159811.17-159811.135"
- wire $and$libresoc.v:159811$8657_Y
- attribute \src "libresoc.v:159814.18-159814.103"
- wire $and$libresoc.v:159814$8660_Y
- attribute \src "libresoc.v:159781.18-159781.109"
- wire width 4 $extend$libresoc.v:159781$8625_Y
- attribute \src "libresoc.v:159782.18-159782.109"
- wire width 4 $extend$libresoc.v:159782$8627_Y
- attribute \src "libresoc.v:159793.18-159793.112"
- wire width 8 $mul$libresoc.v:159793$8639_Y
- attribute \src "libresoc.v:159799.18-159799.112"
- wire width 8 $mul$libresoc.v:159799$8645_Y
- attribute \src "libresoc.v:159774.17-159774.103"
- wire $not$libresoc.v:159774$8618_Y
- attribute \src "libresoc.v:159776.18-159776.94"
- wire $not$libresoc.v:159776$8620_Y
- attribute \src "libresoc.v:159778.18-159778.94"
- wire $not$libresoc.v:159778$8622_Y
- attribute \src "libresoc.v:159788.18-159788.102"
- wire $not$libresoc.v:159788$8634_Y
- attribute \src "libresoc.v:159791.18-159791.97"
- wire $not$libresoc.v:159791$8637_Y
- attribute \src "libresoc.v:159797.18-159797.102"
- wire $not$libresoc.v:159797$8643_Y
- attribute \src "libresoc.v:159800.17-159800.103"
- wire $not$libresoc.v:159800$8646_Y
- attribute \src "libresoc.v:159807.18-159807.101"
- wire $not$libresoc.v:159807$8653_Y
- attribute \src "libresoc.v:159808.18-159808.111"
- wire $not$libresoc.v:159808$8654_Y
- attribute \src "libresoc.v:159809.18-159809.110"
- wire $not$libresoc.v:159809$8655_Y
- attribute \src "libresoc.v:159812.18-159812.102"
- wire $not$libresoc.v:159812$8658_Y
- attribute \src "libresoc.v:159813.18-159813.102"
- wire $not$libresoc.v:159813$8659_Y
- attribute \src "libresoc.v:159789.18-159789.111"
- wire $or$libresoc.v:159789$8635_Y
- attribute \src "libresoc.v:159790.17-159790.130"
- wire $or$libresoc.v:159790$8636_Y
- attribute \src "libresoc.v:159803.18-159803.130"
- wire $or$libresoc.v:159803$8649_Y
- attribute \src "libresoc.v:159805.18-159805.130"
- wire $or$libresoc.v:159805$8651_Y
- attribute \src "libresoc.v:159781.18-159781.109"
- wire width 4 $pos$libresoc.v:159781$8626_Y
- attribute \src "libresoc.v:159782.18-159782.109"
- wire width 4 $pos$libresoc.v:159782$8628_Y
- attribute \src "libresoc.v:159801.18-159801.121"
- wire width 319 $sshl$libresoc.v:159801$8647_Y
- attribute \src "libresoc.v:159794.18-159794.106"
- wire width 176 $sshr$libresoc.v:159794$8640_Y
+ attribute \src "libresoc.v:158070.3-158105.6"
+ wire $6\adrok_l_s_addr_acked$next[0:0]$8627
+ attribute \src "libresoc.v:157576.18-157576.115"
+ wire $and$libresoc.v:157576$8533_Y
+ attribute \src "libresoc.v:157578.18-157578.95"
+ wire $and$libresoc.v:157578$8535_Y
+ attribute \src "libresoc.v:157580.17-157580.138"
+ wire $and$libresoc.v:157580$8537_Y
+ attribute \src "libresoc.v:157581.18-157581.95"
+ wire $and$libresoc.v:157581$8538_Y
+ attribute \src "libresoc.v:157584.18-157584.136"
+ wire $and$libresoc.v:157584$8543_Y
+ attribute \src "libresoc.v:157585.18-157585.136"
+ wire $and$libresoc.v:157585$8544_Y
+ attribute \src "libresoc.v:157586.18-157586.136"
+ wire $and$libresoc.v:157586$8545_Y
+ attribute \src "libresoc.v:157587.18-157587.136"
+ wire $and$libresoc.v:157587$8546_Y
+ attribute \src "libresoc.v:157588.18-157588.136"
+ wire $and$libresoc.v:157588$8547_Y
+ attribute \src "libresoc.v:157593.18-157593.119"
+ wire width 176 $and$libresoc.v:157593$8552_Y
+ attribute \src "libresoc.v:157596.18-157596.136"
+ wire $and$libresoc.v:157596$8555_Y
+ attribute \src "libresoc.v:157597.18-157597.136"
+ wire $and$libresoc.v:157597$8556_Y
+ attribute \src "libresoc.v:157599.18-157599.139"
+ wire $and$libresoc.v:157599$8558_Y
+ attribute \src "libresoc.v:157603.18-157603.139"
+ wire $and$libresoc.v:157603$8562_Y
+ attribute \src "libresoc.v:157605.18-157605.114"
+ wire $and$libresoc.v:157605$8564_Y
+ attribute \src "libresoc.v:157607.18-157607.114"
+ wire $and$libresoc.v:157607$8566_Y
+ attribute \src "libresoc.v:157611.18-157611.103"
+ wire $and$libresoc.v:157611$8570_Y
+ attribute \src "libresoc.v:157612.17-157612.135"
+ wire $and$libresoc.v:157612$8571_Y
+ attribute \src "libresoc.v:157615.18-157615.103"
+ wire $and$libresoc.v:157615$8574_Y
+ attribute \src "libresoc.v:157582.18-157582.109"
+ wire width 4 $extend$libresoc.v:157582$8539_Y
+ attribute \src "libresoc.v:157583.18-157583.109"
+ wire width 4 $extend$libresoc.v:157583$8541_Y
+ attribute \src "libresoc.v:157594.18-157594.112"
+ wire width 8 $mul$libresoc.v:157594$8553_Y
+ attribute \src "libresoc.v:157600.18-157600.112"
+ wire width 8 $mul$libresoc.v:157600$8559_Y
+ attribute \src "libresoc.v:157575.17-157575.103"
+ wire $not$libresoc.v:157575$8532_Y
+ attribute \src "libresoc.v:157577.18-157577.94"
+ wire $not$libresoc.v:157577$8534_Y
+ attribute \src "libresoc.v:157579.18-157579.94"
+ wire $not$libresoc.v:157579$8536_Y
+ attribute \src "libresoc.v:157589.18-157589.102"
+ wire $not$libresoc.v:157589$8548_Y
+ attribute \src "libresoc.v:157592.18-157592.97"
+ wire $not$libresoc.v:157592$8551_Y
+ attribute \src "libresoc.v:157598.18-157598.102"
+ wire $not$libresoc.v:157598$8557_Y
+ attribute \src "libresoc.v:157601.17-157601.103"
+ wire $not$libresoc.v:157601$8560_Y
+ attribute \src "libresoc.v:157608.18-157608.101"
+ wire $not$libresoc.v:157608$8567_Y
+ attribute \src "libresoc.v:157609.18-157609.111"
+ wire $not$libresoc.v:157609$8568_Y
+ attribute \src "libresoc.v:157610.18-157610.110"
+ wire $not$libresoc.v:157610$8569_Y
+ attribute \src "libresoc.v:157613.18-157613.102"
+ wire $not$libresoc.v:157613$8572_Y
+ attribute \src "libresoc.v:157614.18-157614.102"
+ wire $not$libresoc.v:157614$8573_Y
+ attribute \src "libresoc.v:157590.18-157590.111"
+ wire $or$libresoc.v:157590$8549_Y
+ attribute \src "libresoc.v:157591.17-157591.130"
+ wire $or$libresoc.v:157591$8550_Y
+ attribute \src "libresoc.v:157604.18-157604.130"
+ wire $or$libresoc.v:157604$8563_Y
+ attribute \src "libresoc.v:157606.18-157606.130"
+ wire $or$libresoc.v:157606$8565_Y
+ attribute \src "libresoc.v:157582.18-157582.109"
+ wire width 4 $pos$libresoc.v:157582$8540_Y
+ attribute \src "libresoc.v:157583.18-157583.109"
+ wire width 4 $pos$libresoc.v:157583$8542_Y
+ attribute \src "libresoc.v:157602.18-157602.121"
+ wire width 319 $sshl$libresoc.v:157602$8561_Y
+ attribute \src "libresoc.v:157595.18-157595.106"
+ wire width 176 $sshr$libresoc.v:157595$8554_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
wire \busy_l_r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \busy_l_s_busy
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \cyc_l_q_cyc
wire width 2 \fsm_state
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85"
wire width 2 \fsm_state$next
- attribute \src "libresoc.v:159529.7-159529.15"
+ attribute \src "libresoc.v:157330.7-157330.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \ld_active_q_ld_active
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57"
wire output 22 \x_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
- cell $and $and$libresoc.v:159775$8619
+ cell $and $and$libresoc.v:157576$8533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
connect \B \$9
- connect \Y $and$libresoc.v:159775$8619_Y
+ connect \Y $and$libresoc.v:157576$8533_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:159777$8621
+ cell $and $and$libresoc.v:157578$8535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lds
connect \B \$13
- connect \Y $and$libresoc.v:159777$8621_Y
+ connect \Y $and$libresoc.v:157578$8535_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:159779$8623
+ cell $and $and$libresoc.v:157580$8537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:159779$8623_Y
+ connect \Y $and$libresoc.v:157580$8537_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:159780$8624
+ cell $and $and$libresoc.v:157581$8538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sts
connect \B \$17
- connect \Y $and$libresoc.v:159780$8624_Y
+ connect \Y $and$libresoc.v:157581$8538_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:159783$8629
+ cell $and $and$libresoc.v:157584$8543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:159783$8629_Y
+ connect \Y $and$libresoc.v:157584$8543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:159784$8630
+ cell $and $and$libresoc.v:157585$8544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:159784$8630_Y
+ connect \Y $and$libresoc.v:157585$8544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:159785$8631
+ cell $and $and$libresoc.v:157586$8545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:159785$8631_Y
+ connect \Y $and$libresoc.v:157586$8545_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:159786$8632
+ cell $and $and$libresoc.v:157587$8546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:159786$8632_Y
+ connect \Y $and$libresoc.v:157587$8546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:159787$8633
+ cell $and $and$libresoc.v:157588$8547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:159787$8633_Y
+ connect \Y $and$libresoc.v:157588$8547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
- cell $and $and$libresoc.v:159792$8638
+ cell $and $and$libresoc.v:157593$8552
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 176
connect \A \m_ld_data_o
connect \B \lenexp_rexp_o
- connect \Y $and$libresoc.v:159792$8638_Y
+ connect \Y $and$libresoc.v:157593$8552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:159795$8641
+ cell $and $and$libresoc.v:157596$8555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:159795$8641_Y
+ connect \Y $and$libresoc.v:157596$8555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
- cell $and $and$libresoc.v:159796$8642
+ cell $and $and$libresoc.v:157597$8556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ld_active_q_ld_active
connect \B \adrok_l_q_addr_acked
- connect \Y $and$libresoc.v:159796$8642_Y
+ connect \Y $and$libresoc.v:157597$8556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:159798$8644
+ cell $and $and$libresoc.v:157599$8558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:159798$8644_Y
+ connect \Y $and$libresoc.v:157599$8558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267"
- cell $and $and$libresoc.v:159802$8648
+ cell $and $and$libresoc.v:157603$8562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st_active_q_st_active
connect \B \ldst_port0_st_data_i_ok
- connect \Y $and$libresoc.v:159802$8648_Y
+ connect \Y $and$libresoc.v:157603$8562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $and $and$libresoc.v:159804$8650
+ cell $and $and$libresoc.v:157605$8564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$63
connect \B \valid_l_q_valid
- connect \Y $and$libresoc.v:159804$8650_Y
+ connect \Y $and$libresoc.v:157605$8564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $and $and$libresoc.v:159806$8652
+ cell $and $and$libresoc.v:157607$8566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$67
connect \B \valid_l_q_valid
- connect \Y $and$libresoc.v:159806$8652_Y
+ connect \Y $and$libresoc.v:157607$8566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $and $and$libresoc.v:159810$8656
+ cell $and $and$libresoc.v:157611$8570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$73
connect \B \$75
- connect \Y $and$libresoc.v:159810$8656_Y
+ connect \Y $and$libresoc.v:157611$8570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
- cell $and $and$libresoc.v:159811$8657
+ cell $and $and$libresoc.v:157612$8571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_addr_i_ok
connect \B \adrok_l_qn_addr_acked
- connect \Y $and$libresoc.v:159811$8657_Y
+ connect \Y $and$libresoc.v:157612$8571_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:159814$8660
+ cell $and $and$libresoc.v:157615$8574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lsui_active
connect \B \$81
- connect \Y $and$libresoc.v:159814$8660_Y
+ connect \Y $and$libresoc.v:157615$8574_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:159781$8625
+ cell $pos $extend$libresoc.v:157582$8539
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 4
connect \A \ldst_port0_addr_i [2:0]
- connect \Y $extend$libresoc.v:159781$8625_Y
+ connect \Y $extend$libresoc.v:157582$8539_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $extend$libresoc.v:159782$8627
+ cell $pos $extend$libresoc.v:157583$8541
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 4
connect \A \ldst_port0_addr_i [2:0]
- connect \Y $extend$libresoc.v:159782$8627_Y
+ connect \Y $extend$libresoc.v:157583$8541_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258"
- cell $mul $mul$libresoc.v:159793$8639
+ cell $mul $mul$libresoc.v:157594$8553
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \lenexp_addr_i
connect \B 4'1000
- connect \Y $mul$libresoc.v:159793$8639_Y
+ connect \Y $mul$libresoc.v:157594$8553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
- cell $mul $mul$libresoc.v:159799$8645
+ cell $mul $mul$libresoc.v:157600$8559
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \lenexp_addr_i
connect \B 4'1000
- connect \Y $mul$libresoc.v:159799$8645_Y
+ connect \Y $mul$libresoc.v:157600$8559_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216"
- cell $not $not$libresoc.v:159774$8618
+ cell $not $not$libresoc.v:157575$8532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_delay
- connect \Y $not$libresoc.v:159774$8618_Y
+ connect \Y $not$libresoc.v:157575$8532_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:159776$8620
+ cell $not $not$libresoc.v:157577$8534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lds_dly
- connect \Y $not$libresoc.v:159776$8620_Y
+ connect \Y $not$libresoc.v:157577$8534_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:159778$8622
+ cell $not $not$libresoc.v:157579$8536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sts_dly
- connect \Y $not$libresoc.v:159778$8622_Y
+ connect \Y $not$libresoc.v:157579$8536_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64"
- cell $not $not$libresoc.v:159788$8634
+ cell $not $not$libresoc.v:157589$8548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_busy
- connect \Y $not$libresoc.v:159788$8634_Y
+ connect \Y $not$libresoc.v:157589$8548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
- cell $not $not$libresoc.v:159791$8637
+ cell $not $not$libresoc.v:157592$8551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$38
- connect \Y $not$libresoc.v:159791$8637_Y
+ connect \Y $not$libresoc.v:157592$8551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64"
- cell $not $not$libresoc.v:159797$8643
+ cell $not $not$libresoc.v:157598$8557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_busy
- connect \Y $not$libresoc.v:159797$8643_Y
+ connect \Y $not$libresoc.v:157598$8557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
- cell $not $not$libresoc.v:159800$8646
+ cell $not $not$libresoc.v:157601$8560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_delay
- connect \Y $not$libresoc.v:159800$8646_Y
+ connect \Y $not$libresoc.v:157601$8560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
- cell $not $not$libresoc.v:159807$8653
+ cell $not $not$libresoc.v:157608$8567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_busy_o
- connect \Y $not$libresoc.v:159807$8653_Y
+ connect \Y $not$libresoc.v:157608$8567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $not $not$libresoc.v:159808$8654
+ cell $not $not$libresoc.v:157609$8568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_st_i
- connect \Y $not$libresoc.v:159808$8654_Y
+ connect \Y $not$libresoc.v:157609$8568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
- cell $not $not$libresoc.v:159809$8655
+ cell $not $not$libresoc.v:157610$8569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_busy_o
- connect \Y $not$libresoc.v:159809$8655_Y
+ connect \Y $not$libresoc.v:157610$8569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108"
- cell $not $not$libresoc.v:159812$8658
+ cell $not $not$libresoc.v:157613$8572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x_busy_o
- connect \Y $not$libresoc.v:159812$8658_Y
+ connect \Y $not$libresoc.v:157613$8572_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:159813$8659
+ cell $not $not$libresoc.v:157614$8573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \lsui_active_dly
- connect \Y $not$libresoc.v:159813$8659_Y
+ connect \Y $not$libresoc.v:157614$8573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
- cell $or $or$libresoc.v:159789$8635
+ cell $or $or$libresoc.v:157590$8549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \x_busy_o
connect \B \lsui_busy
- connect \Y $or$libresoc.v:159789$8635_Y
+ connect \Y $or$libresoc.v:157590$8549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223"
- cell $or $or$libresoc.v:159790$8636
+ cell $or $or$libresoc.v:157591$8550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:159790$8636_Y
+ connect \Y $or$libresoc.v:157591$8550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $or $or$libresoc.v:159803$8649
+ cell $or $or$libresoc.v:157604$8563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:159803$8649_Y
+ connect \Y $or$libresoc.v:157604$8563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
- cell $or $or$libresoc.v:159805$8651
+ cell $or $or$libresoc.v:157606$8565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $or$libresoc.v:159805$8651_Y
+ connect \Y $or$libresoc.v:157606$8565_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:159781$8626
+ cell $pos $pos$libresoc.v:157582$8540
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $extend$libresoc.v:159781$8625_Y
- connect \Y $pos$libresoc.v:159781$8626_Y
+ connect \A $extend$libresoc.v:157582$8539_Y
+ connect \Y $pos$libresoc.v:157582$8540_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
- cell $pos $pos$libresoc.v:159782$8628
+ cell $pos $pos$libresoc.v:157583$8542
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $extend$libresoc.v:159782$8627_Y
- connect \Y $pos$libresoc.v:159782$8628_Y
+ connect \A $extend$libresoc.v:157583$8541_Y
+ connect \Y $pos$libresoc.v:157583$8542_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
- cell $sshl $sshl$libresoc.v:159801$8647
+ cell $sshl $sshl$libresoc.v:157602$8561
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 319
connect \A \ldst_port0_st_data_i
connect \B \$57
- connect \Y $sshl$libresoc.v:159801$8647_Y
+ connect \Y $sshl$libresoc.v:157602$8561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258"
- cell $sshr $sshr$libresoc.v:159794$8640
+ cell $sshr $sshr$libresoc.v:157595$8554
parameter \A_SIGNED 0
parameter \A_WIDTH 176
parameter \B_SIGNED 0
parameter \Y_WIDTH 176
connect \A \$42
connect \B \$44
- connect \Y $sshr$libresoc.v:159794$8640_Y
+ connect \Y $sshr$libresoc.v:157595$8554_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159831.11-159838.4"
+ attribute \src "libresoc.v:157632.11-157639.4"
cell \adrok_l \adrok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_addr_acked \adrok_l_s_addr_acked
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159839.10-159845.4"
+ attribute \src "libresoc.v:157640.10-157646.4"
cell \busy_l \busy_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_busy \busy_l_s_busy
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159846.9-159852.4"
+ attribute \src "libresoc.v:157647.9-157653.4"
cell \cyc_l \cyc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_cyc \cyc_l_s_cyc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159853.13-159859.4"
+ attribute \src "libresoc.v:157654.13-157660.4"
cell \ld_active \ld_active
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_ld_active \ld_active_s_ld_active
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159860.10-159865.4"
+ attribute \src "libresoc.v:157661.10-157666.4"
cell \lenexp \lenexp
connect \addr_i \lenexp_addr_i
connect \len_i \lenexp_len_i
connect \rexp_o \lenexp_rexp_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159866.11-159872.4"
+ attribute \src "libresoc.v:157667.11-157673.4"
cell \reset_l \reset_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_reset \reset_l_s_reset
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159873.13-159879.4"
+ attribute \src "libresoc.v:157674.13-157680.4"
cell \st_active \st_active
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_st_active \st_active_s_st_active
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159880.11-159886.4"
+ attribute \src "libresoc.v:157681.11-157687.4"
cell \st_done \st_done
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_st_done \st_done_s_st_done
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:159887.11-159893.4"
+ attribute \src "libresoc.v:157688.11-157694.4"
cell \valid_l \valid_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_valid \valid_l_r_valid
connect \s_valid \valid_l_s_valid
end
- attribute \src "libresoc.v:159529.7-159529.20"
- process $proc$libresoc.v:159529$8715
+ attribute \src "libresoc.v:157330.7-157330.20"
+ process $proc$libresoc.v:157330$8629
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:159623.7-159623.34"
- process $proc$libresoc.v:159623$8716
+ attribute \src "libresoc.v:157424.7-157424.34"
+ process $proc$libresoc.v:157424$8630
assign { } { }
assign $1\adrok_l_s_addr_acked[0:0] 1'0
sync always
sync init
update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0]
end
- attribute \src "libresoc.v:159627.7-159627.24"
- process $proc$libresoc.v:159627$8717
+ attribute \src "libresoc.v:157428.7-157428.24"
+ process $proc$libresoc.v:157428$8631
assign { } { }
assign $1\busy_delay[0:0] 1'0
sync always
sync init
update \busy_delay $1\busy_delay[0:0]
end
- attribute \src "libresoc.v:159649.13-159649.29"
- process $proc$libresoc.v:159649$8718
+ attribute \src "libresoc.v:157450.13-157450.29"
+ process $proc$libresoc.v:157450$8632
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:159663.7-159663.21"
- process $proc$libresoc.v:159663$8719
+ attribute \src "libresoc.v:157464.7-157464.21"
+ process $proc$libresoc.v:157464$8633
assign { } { }
assign $1\lds_dly[0:0] 1'0
sync always
sync init
update \lds_dly $1\lds_dly[0:0]
end
- attribute \src "libresoc.v:159706.7-159706.29"
- process $proc$libresoc.v:159706$8720
+ attribute \src "libresoc.v:157507.7-157507.29"
+ process $proc$libresoc.v:157507$8634
assign { } { }
assign $1\lsui_active_dly[0:0] 1'0
sync always
sync init
update \lsui_active_dly $1\lsui_active_dly[0:0]
end
- attribute \src "libresoc.v:159718.7-159718.25"
- process $proc$libresoc.v:159718$8721
+ attribute \src "libresoc.v:157519.7-157519.25"
+ process $proc$libresoc.v:157519$8635
assign { } { }
assign $1\reset_delay[0:0] 1'0
sync always
sync init
update \reset_delay $1\reset_delay[0:0]
end
- attribute \src "libresoc.v:159738.7-159738.31"
- process $proc$libresoc.v:159738$8722
+ attribute \src "libresoc.v:157539.7-157539.31"
+ process $proc$libresoc.v:157539$8636
assign { } { }
assign $1\st_done_s_st_done[0:0] 1'0
sync always
sync init
update \st_done_s_st_done $1\st_done_s_st_done[0:0]
end
- attribute \src "libresoc.v:159746.7-159746.21"
- process $proc$libresoc.v:159746$8723
+ attribute \src "libresoc.v:157547.7-157547.21"
+ process $proc$libresoc.v:157547$8637
assign { } { }
assign $1\sts_dly[0:0] 1'0
sync always
sync init
update \sts_dly $1\sts_dly[0:0]
end
- attribute \src "libresoc.v:159815.3-159816.47"
- process $proc$libresoc.v:159815$8661
+ attribute \src "libresoc.v:157616.3-157617.47"
+ process $proc$libresoc.v:157616$8575
assign { } { }
assign $0\lsui_active_dly[0:0] \lsui_active_dly$next
sync posedge \coresync_clk
update \lsui_active_dly $0\lsui_active_dly[0:0]
end
- attribute \src "libresoc.v:159817.3-159818.35"
- process $proc$libresoc.v:159817$8662
+ attribute \src "libresoc.v:157618.3-157619.35"
+ process $proc$libresoc.v:157618$8576
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \coresync_clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:159819.3-159820.36"
- process $proc$libresoc.v:159819$8663
+ attribute \src "libresoc.v:157620.3-157621.36"
+ process $proc$libresoc.v:157620$8577
assign { } { }
assign $0\reset_delay[0:0] \reset_l_q_reset
sync posedge \coresync_clk
update \reset_delay $0\reset_delay[0:0]
end
- attribute \src "libresoc.v:159821.3-159822.35"
- process $proc$libresoc.v:159821$8664
+ attribute \src "libresoc.v:157622.3-157623.35"
+ process $proc$libresoc.v:157622$8578
assign { } { }
assign $0\sts_dly[0:0] \ldst_port0_is_st_i
sync posedge \coresync_clk
update \sts_dly $0\sts_dly[0:0]
end
- attribute \src "libresoc.v:159823.3-159824.35"
- process $proc$libresoc.v:159823$8665
+ attribute \src "libresoc.v:157624.3-157625.35"
+ process $proc$libresoc.v:157624$8579
assign { } { }
assign $0\lds_dly[0:0] \ldst_port0_is_ld_i
sync posedge \coresync_clk
update \lds_dly $0\lds_dly[0:0]
end
- attribute \src "libresoc.v:159825.3-159826.37"
- process $proc$libresoc.v:159825$8666
+ attribute \src "libresoc.v:157626.3-157627.37"
+ process $proc$libresoc.v:157626$8580
assign { } { }
assign $0\busy_delay[0:0] \busy_delay$next
sync posedge \coresync_clk
update \busy_delay $0\busy_delay[0:0]
end
- attribute \src "libresoc.v:159827.3-159828.57"
- process $proc$libresoc.v:159827$8667
+ attribute \src "libresoc.v:157628.3-157629.57"
+ process $proc$libresoc.v:157628$8581
assign { } { }
assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next
sync posedge \coresync_clk
update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0]
end
- attribute \src "libresoc.v:159829.3-159830.51"
- process $proc$libresoc.v:159829$8668
+ attribute \src "libresoc.v:157630.3-157631.51"
+ process $proc$libresoc.v:157630$8582
assign { } { }
assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next
sync posedge \coresync_clk
update \st_done_s_st_done $0\st_done_s_st_done[0:0]
end
- attribute \src "libresoc.v:159894.3-159908.6"
- process $proc$libresoc.v:159894$8669
+ attribute \src "libresoc.v:157695.3-157709.6"
+ process $proc$libresoc.v:157695$8583
assign { } { }
assign { } { }
assign { } { }
- assign $0\st_done_s_st_done$next[0:0]$8670 $2\st_done_s_st_done$next[0:0]$8672
- attribute \src "libresoc.v:159895.5-159895.29"
+ assign $0\st_done_s_st_done$next[0:0]$8584 $2\st_done_s_st_done$next[0:0]$8586
+ attribute \src "libresoc.v:157696.5-157696.29"
switch \initial
- attribute \src "libresoc.v:159895.9-159895.17"
+ attribute \src "libresoc.v:157696.9-157696.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\st_done_s_st_done$next[0:0]$8671 1'1
+ assign $1\st_done_s_st_done$next[0:0]$8585 1'1
case
- assign $1\st_done_s_st_done$next[0:0]$8671 1'0
+ assign $1\st_done_s_st_done$next[0:0]$8585 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\st_done_s_st_done$next[0:0]$8672 1'0
+ assign $2\st_done_s_st_done$next[0:0]$8586 1'0
case
- assign $2\st_done_s_st_done$next[0:0]$8672 $1\st_done_s_st_done$next[0:0]$8671
+ assign $2\st_done_s_st_done$next[0:0]$8586 $1\st_done_s_st_done$next[0:0]$8585
end
sync always
- update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8670
+ update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8584
end
- attribute \src "libresoc.v:159909.3-159918.6"
- process $proc$libresoc.v:159909$8673
+ attribute \src "libresoc.v:157710.3-157719.6"
+ process $proc$libresoc.v:157710$8587
assign { } { }
assign { } { }
assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0]
- attribute \src "libresoc.v:159910.5-159910.29"
+ attribute \src "libresoc.v:157711.5-157711.29"
switch \initial
- attribute \src "libresoc.v:159910.9-159910.17"
+ attribute \src "libresoc.v:157711.9-157711.17"
case 1'1
case
end
sync always
update \st_done_r_st_done $0\st_done_r_st_done[0:0]
end
- attribute \src "libresoc.v:159919.3-159927.6"
- process $proc$libresoc.v:159919$8674
+ attribute \src "libresoc.v:157720.3-157728.6"
+ process $proc$libresoc.v:157720$8588
assign { } { }
assign { } { }
- assign $0\busy_delay$next[0:0]$8675 $1\busy_delay$next[0:0]$8676
- attribute \src "libresoc.v:159920.5-159920.29"
+ assign $0\busy_delay$next[0:0]$8589 $1\busy_delay$next[0:0]$8590
+ attribute \src "libresoc.v:157721.5-157721.29"
switch \initial
- attribute \src "libresoc.v:159920.9-159920.17"
+ attribute \src "libresoc.v:157721.9-157721.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\busy_delay$next[0:0]$8676 1'0
+ assign $1\busy_delay$next[0:0]$8590 1'0
case
- assign $1\busy_delay$next[0:0]$8676 \ldst_port0_busy_o
+ assign $1\busy_delay$next[0:0]$8590 \ldst_port0_busy_o
end
sync always
- update \busy_delay$next $0\busy_delay$next[0:0]$8675
+ update \busy_delay$next $0\busy_delay$next[0:0]$8589
end
- attribute \src "libresoc.v:159928.3-159937.6"
- process $proc$libresoc.v:159928$8677
+ attribute \src "libresoc.v:157729.3-157738.6"
+ process $proc$libresoc.v:157729$8591
assign { } { }
assign { } { }
assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0]
- attribute \src "libresoc.v:159929.5-159929.29"
+ attribute \src "libresoc.v:157730.5-157730.29"
switch \initial
- attribute \src "libresoc.v:159929.9-159929.17"
+ attribute \src "libresoc.v:157730.9-157730.17"
case 1'1
case
end
sync always
update \st_active_r_st_active $0\st_active_r_st_active[0:0]
end
- attribute \src "libresoc.v:159938.3-159953.6"
- process $proc$libresoc.v:159938$8678
+ attribute \src "libresoc.v:157739.3-157754.6"
+ process $proc$libresoc.v:157739$8592
assign { } { }
assign { } { }
assign { } { }
assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0]
- attribute \src "libresoc.v:159939.5-159939.29"
+ attribute \src "libresoc.v:157740.5-157740.29"
switch \initial
- attribute \src "libresoc.v:159939.9-159939.17"
+ attribute \src "libresoc.v:157740.9-157740.17"
case 1'1
case
end
sync always
update \lenexp_len_i $0\lenexp_len_i[3:0]
end
- attribute \src "libresoc.v:159954.3-159969.6"
- process $proc$libresoc.v:159954$8679
+ attribute \src "libresoc.v:157755.3-157770.6"
+ process $proc$libresoc.v:157755$8593
assign { } { }
assign { } { }
assign { } { }
assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0]
- attribute \src "libresoc.v:159955.5-159955.29"
+ attribute \src "libresoc.v:157756.5-157756.29"
switch \initial
- attribute \src "libresoc.v:159955.9-159955.17"
+ attribute \src "libresoc.v:157756.9-157756.17"
case 1'1
case
end
sync always
update \lenexp_addr_i $0\lenexp_addr_i[3:0]
end
- attribute \src "libresoc.v:159970.3-159995.6"
- process $proc$libresoc.v:159970$8680
+ attribute \src "libresoc.v:157771.3-157796.6"
+ process $proc$libresoc.v:157771$8594
assign { } { }
assign { } { }
assign { } { }
assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0]
- attribute \src "libresoc.v:159971.5-159971.29"
+ attribute \src "libresoc.v:157772.5-157772.29"
switch \initial
- attribute \src "libresoc.v:159971.9-159971.17"
+ attribute \src "libresoc.v:157772.9-157772.17"
case 1'1
case
end
sync always
update \valid_l_s_valid $0\valid_l_s_valid[0:0]
end
- attribute \src "libresoc.v:159996.3-160021.6"
- process $proc$libresoc.v:159996$8681
+ attribute \src "libresoc.v:157797.3-157822.6"
+ process $proc$libresoc.v:157797$8595
assign { } { }
assign { } { }
assign { } { }
assign $0\x_mask_i[7:0] $3\x_mask_i[7:0]
- attribute \src "libresoc.v:159997.5-159997.29"
+ attribute \src "libresoc.v:157798.5-157798.29"
switch \initial
- attribute \src "libresoc.v:159997.9-159997.17"
+ attribute \src "libresoc.v:157798.9-157798.17"
case 1'1
case
end
sync always
update \x_mask_i $0\x_mask_i[7:0]
end
- attribute \src "libresoc.v:160022.3-160047.6"
- process $proc$libresoc.v:160022$8682
+ attribute \src "libresoc.v:157823.3-157848.6"
+ process $proc$libresoc.v:157823$8596
assign { } { }
assign { } { }
assign { } { }
assign $0\x_addr_i[47:0] $3\x_addr_i[47:0]
- attribute \src "libresoc.v:160023.5-160023.29"
+ attribute \src "libresoc.v:157824.5-157824.29"
switch \initial
- attribute \src "libresoc.v:160023.9-160023.17"
+ attribute \src "libresoc.v:157824.9-157824.17"
case 1'1
case
end
sync always
update \x_addr_i $0\x_addr_i[47:0]
end
- attribute \src "libresoc.v:160048.3-160078.6"
- process $proc$libresoc.v:160048$8683
+ attribute \src "libresoc.v:157849.3-157879.6"
+ process $proc$libresoc.v:157849$8597
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0]
- attribute \src "libresoc.v:160049.5-160049.29"
+ attribute \src "libresoc.v:157850.5-157850.29"
switch \initial
- attribute \src "libresoc.v:160049.9-160049.17"
+ attribute \src "libresoc.v:157850.9-157850.17"
case 1'1
case
end
sync always
update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0]
end
- attribute \src "libresoc.v:160079.3-160094.6"
- process $proc$libresoc.v:160079$8684
+ attribute \src "libresoc.v:157880.3-157895.6"
+ process $proc$libresoc.v:157880$8598
assign { } { }
assign { } { }
assign { } { }
assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0]
- attribute \src "libresoc.v:160080.5-160080.29"
+ attribute \src "libresoc.v:157881.5-157881.29"
switch \initial
- attribute \src "libresoc.v:160080.9-160080.17"
+ attribute \src "libresoc.v:157881.9-157881.17"
case 1'1
case
end
sync always
update \reset_l_s_reset $0\reset_l_s_reset[0:0]
end
- attribute \src "libresoc.v:160095.3-160104.6"
- process $proc$libresoc.v:160095$8685
+ attribute \src "libresoc.v:157896.3-157905.6"
+ process $proc$libresoc.v:157896$8599
assign { } { }
assign { } { }
assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0]
- attribute \src "libresoc.v:160096.5-160096.29"
+ attribute \src "libresoc.v:157897.5-157897.29"
switch \initial
- attribute \src "libresoc.v:160096.9-160096.17"
+ attribute \src "libresoc.v:157897.9-157897.17"
case 1'1
case
end
sync always
update \reset_l_r_reset $0\reset_l_r_reset[0:0]
end
- attribute \src "libresoc.v:160105.3-160114.6"
- process $proc$libresoc.v:160105$8686
+ attribute \src "libresoc.v:157906.3-157915.6"
+ process $proc$libresoc.v:157906$8600
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0]
- attribute \src "libresoc.v:160106.5-160106.29"
+ attribute \src "libresoc.v:157907.5-157907.29"
switch \initial
- attribute \src "libresoc.v:160106.9-160106.17"
+ attribute \src "libresoc.v:157907.9-157907.17"
case 1'1
case
end
sync always
update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0]
end
- attribute \src "libresoc.v:160115.3-160124.6"
- process $proc$libresoc.v:160115$8687
+ attribute \src "libresoc.v:157916.3-157925.6"
+ process $proc$libresoc.v:157916$8601
assign { } { }
assign { } { }
assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0]
- attribute \src "libresoc.v:160116.5-160116.29"
+ attribute \src "libresoc.v:157917.5-157917.29"
switch \initial
- attribute \src "libresoc.v:160116.9-160116.17"
+ attribute \src "libresoc.v:157917.9-157917.17"
case 1'1
case
end
sync always
update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0]
end
- attribute \src "libresoc.v:160125.3-160134.6"
- process $proc$libresoc.v:160125$8688
+ attribute \src "libresoc.v:157926.3-157935.6"
+ process $proc$libresoc.v:157926$8602
assign { } { }
assign { } { }
assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0]
- attribute \src "libresoc.v:160126.5-160126.29"
+ attribute \src "libresoc.v:157927.5-157927.29"
switch \initial
- attribute \src "libresoc.v:160126.9-160126.17"
+ attribute \src "libresoc.v:157927.9-157927.17"
case 1'1
case
end
sync always
update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0]
end
- attribute \src "libresoc.v:160135.3-160144.6"
- process $proc$libresoc.v:160135$8689
+ attribute \src "libresoc.v:157936.3-157945.6"
+ process $proc$libresoc.v:157936$8603
assign { } { }
assign { } { }
assign $0\stdata[63:0] $1\stdata[63:0]
- attribute \src "libresoc.v:160136.5-160136.29"
+ attribute \src "libresoc.v:157937.5-157937.29"
switch \initial
- attribute \src "libresoc.v:160136.9-160136.17"
+ attribute \src "libresoc.v:157937.9-157937.17"
case 1'1
case
end
sync always
update \stdata $0\stdata[63:0]
end
- attribute \src "libresoc.v:160145.3-160154.6"
- process $proc$libresoc.v:160145$8690
+ attribute \src "libresoc.v:157946.3-157955.6"
+ process $proc$libresoc.v:157946$8604
assign { } { }
assign { } { }
assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0]
- attribute \src "libresoc.v:160146.5-160146.29"
+ attribute \src "libresoc.v:157947.5-157947.29"
switch \initial
- attribute \src "libresoc.v:160146.9-160146.17"
+ attribute \src "libresoc.v:157947.9-157947.17"
case 1'1
case
end
sync always
update \x_st_data_i $0\x_st_data_i[63:0]
end
- attribute \src "libresoc.v:160155.3-160174.6"
- process $proc$libresoc.v:160155$8691
+ attribute \src "libresoc.v:157956.3-157975.6"
+ process $proc$libresoc.v:157956$8605
assign { } { }
assign { } { }
assign $0\lsui_busy[0:0] $1\lsui_busy[0:0]
- attribute \src "libresoc.v:160156.5-160156.29"
+ attribute \src "libresoc.v:157957.5-157957.29"
switch \initial
- attribute \src "libresoc.v:160156.9-160156.17"
+ attribute \src "libresoc.v:157957.9-157957.17"
case 1'1
case
end
sync always
update \lsui_busy $0\lsui_busy[0:0]
end
- attribute \src "libresoc.v:160175.3-160213.6"
- process $proc$libresoc.v:160175$8692
+ attribute \src "libresoc.v:157976.3-158014.6"
+ process $proc$libresoc.v:157976$8606
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$8693 $5\fsm_state$next[1:0]$8698
- attribute \src "libresoc.v:160176.5-160176.29"
+ assign $0\fsm_state$next[1:0]$8607 $5\fsm_state$next[1:0]$8612
+ attribute \src "libresoc.v:157977.5-157977.29"
switch \initial
- attribute \src "libresoc.v:160176.9-160176.17"
+ attribute \src "libresoc.v:157977.9-157977.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$8694 $2\fsm_state$next[1:0]$8695
+ assign $1\fsm_state$next[1:0]$8608 $2\fsm_state$next[1:0]$8609
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88"
switch \$69
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$8695 2'01
+ assign $2\fsm_state$next[1:0]$8609 2'01
case
- assign $2\fsm_state$next[1:0]$8695 \fsm_state
+ assign $2\fsm_state$next[1:0]$8609 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$8694 $3\fsm_state$next[1:0]$8696
+ assign $1\fsm_state$next[1:0]$8608 $3\fsm_state$next[1:0]$8610
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
switch \$71
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$next[1:0]$8696 2'10
+ assign $3\fsm_state$next[1:0]$8610 2'10
case
- assign $3\fsm_state$next[1:0]$8696 \fsm_state
+ assign $3\fsm_state$next[1:0]$8610 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$8694 $4\fsm_state$next[1:0]$8697
+ assign $1\fsm_state$next[1:0]$8608 $4\fsm_state$next[1:0]$8611
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99"
switch \$77
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[1:0]$8697 2'00
+ assign $4\fsm_state$next[1:0]$8611 2'00
case
- assign $4\fsm_state$next[1:0]$8697 \fsm_state
+ assign $4\fsm_state$next[1:0]$8611 \fsm_state
end
case
- assign $1\fsm_state$next[1:0]$8694 \fsm_state
+ assign $1\fsm_state$next[1:0]$8608 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[1:0]$8698 2'00
+ assign $5\fsm_state$next[1:0]$8612 2'00
case
- assign $5\fsm_state$next[1:0]$8698 $1\fsm_state$next[1:0]$8694
+ assign $5\fsm_state$next[1:0]$8612 $1\fsm_state$next[1:0]$8608
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$8693
+ update \fsm_state$next $0\fsm_state$next[1:0]$8607
end
- attribute \src "libresoc.v:160214.3-160223.6"
- process $proc$libresoc.v:160214$8699
+ attribute \src "libresoc.v:158015.3-158024.6"
+ process $proc$libresoc.v:158015$8613
assign { } { }
assign { } { }
assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0]
- attribute \src "libresoc.v:160215.5-160215.29"
+ attribute \src "libresoc.v:158016.5-158016.29"
switch \initial
- attribute \src "libresoc.v:160215.9-160215.17"
+ attribute \src "libresoc.v:158016.9-158016.17"
case 1'1
case
end
sync always
update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0]
end
- attribute \src "libresoc.v:160224.3-160232.6"
- process $proc$libresoc.v:160224$8700
+ attribute \src "libresoc.v:158025.3-158033.6"
+ process $proc$libresoc.v:158025$8614
assign { } { }
assign { } { }
- assign $0\lsui_active_dly$next[0:0]$8701 $1\lsui_active_dly$next[0:0]$8702
- attribute \src "libresoc.v:160225.5-160225.29"
+ assign $0\lsui_active_dly$next[0:0]$8615 $1\lsui_active_dly$next[0:0]$8616
+ attribute \src "libresoc.v:158026.5-158026.29"
switch \initial
- attribute \src "libresoc.v:160225.9-160225.17"
+ attribute \src "libresoc.v:158026.9-158026.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\lsui_active_dly$next[0:0]$8702 1'0
+ assign $1\lsui_active_dly$next[0:0]$8616 1'0
case
- assign $1\lsui_active_dly$next[0:0]$8702 \lsui_active
+ assign $1\lsui_active_dly$next[0:0]$8616 \lsui_active
end
sync always
- update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8701
+ update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8615
end
- attribute \src "libresoc.v:160233.3-160242.6"
- process $proc$libresoc.v:160233$8703
+ attribute \src "libresoc.v:158034.3-158043.6"
+ process $proc$libresoc.v:158034$8617
assign { } { }
assign { } { }
assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0]
- attribute \src "libresoc.v:160234.5-160234.29"
+ attribute \src "libresoc.v:158035.5-158035.29"
switch \initial
- attribute \src "libresoc.v:160234.9-160234.17"
+ attribute \src "libresoc.v:158035.9-158035.17"
case 1'1
case
end
sync always
update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0]
end
- attribute \src "libresoc.v:160243.3-160252.6"
- process $proc$libresoc.v:160243$8704
+ attribute \src "libresoc.v:158044.3-158053.6"
+ process $proc$libresoc.v:158044$8618
assign { } { }
assign { } { }
assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0]
- attribute \src "libresoc.v:160244.5-160244.29"
+ attribute \src "libresoc.v:158045.5-158045.29"
switch \initial
- attribute \src "libresoc.v:160244.9-160244.17"
+ attribute \src "libresoc.v:158045.9-158045.17"
case 1'1
case
end
sync always
update \busy_l_s_busy $0\busy_l_s_busy[0:0]
end
- attribute \src "libresoc.v:160253.3-160268.6"
- process $proc$libresoc.v:160253$8705
+ attribute \src "libresoc.v:158054.3-158069.6"
+ process $proc$libresoc.v:158054$8619
assign { } { }
assign { } { }
assign { } { }
assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0]
- attribute \src "libresoc.v:160254.5-160254.29"
+ attribute \src "libresoc.v:158055.5-158055.29"
switch \initial
- attribute \src "libresoc.v:160254.9-160254.17"
+ attribute \src "libresoc.v:158055.9-158055.17"
case 1'1
case
end
sync always
update \busy_l_r_busy $0\busy_l_r_busy[0:0]
end
- attribute \src "libresoc.v:160269.3-160304.6"
- process $proc$libresoc.v:160269$8706
+ attribute \src "libresoc.v:158070.3-158105.6"
+ process $proc$libresoc.v:158070$8620
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\adrok_l_s_addr_acked$next[0:0]$8707 $6\adrok_l_s_addr_acked$next[0:0]$8713
- attribute \src "libresoc.v:160270.5-160270.29"
+ assign $0\adrok_l_s_addr_acked$next[0:0]$8621 $6\adrok_l_s_addr_acked$next[0:0]$8627
+ attribute \src "libresoc.v:158071.5-158071.29"
switch \initial
- attribute \src "libresoc.v:160270.9-160270.17"
+ attribute \src "libresoc.v:158071.9-158071.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\adrok_l_s_addr_acked$next[0:0]$8708 $2\adrok_l_s_addr_acked$next[0:0]$8709
+ assign $1\adrok_l_s_addr_acked$next[0:0]$8622 $2\adrok_l_s_addr_acked$next[0:0]$8623
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
switch \$7
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\adrok_l_s_addr_acked$next[0:0]$8709 1'1
+ assign $2\adrok_l_s_addr_acked$next[0:0]$8623 1'1
case
- assign $2\adrok_l_s_addr_acked$next[0:0]$8709 1'0
+ assign $2\adrok_l_s_addr_acked$next[0:0]$8623 1'0
end
case
- assign $1\adrok_l_s_addr_acked$next[0:0]$8708 1'0
+ assign $1\adrok_l_s_addr_acked$next[0:0]$8622 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
switch \st_active_q_st_active
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\adrok_l_s_addr_acked$next[0:0]$8710 $4\adrok_l_s_addr_acked$next[0:0]$8711
+ assign $3\adrok_l_s_addr_acked$next[0:0]$8624 $4\adrok_l_s_addr_acked$next[0:0]$8625
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245"
switch \ldst_port0_addr_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\adrok_l_s_addr_acked$next[0:0]$8711 $5\adrok_l_s_addr_acked$next[0:0]$8712
+ assign $4\adrok_l_s_addr_acked$next[0:0]$8625 $5\adrok_l_s_addr_acked$next[0:0]$8626
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247"
switch \adrok_l_qn_addr_acked
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\adrok_l_s_addr_acked$next[0:0]$8712 1'1
+ assign $5\adrok_l_s_addr_acked$next[0:0]$8626 1'1
case
- assign $5\adrok_l_s_addr_acked$next[0:0]$8712 $1\adrok_l_s_addr_acked$next[0:0]$8708
+ assign $5\adrok_l_s_addr_acked$next[0:0]$8626 $1\adrok_l_s_addr_acked$next[0:0]$8622
end
case
- assign $4\adrok_l_s_addr_acked$next[0:0]$8711 $1\adrok_l_s_addr_acked$next[0:0]$8708
+ assign $4\adrok_l_s_addr_acked$next[0:0]$8625 $1\adrok_l_s_addr_acked$next[0:0]$8622
end
case
- assign $3\adrok_l_s_addr_acked$next[0:0]$8710 $1\adrok_l_s_addr_acked$next[0:0]$8708
+ assign $3\adrok_l_s_addr_acked$next[0:0]$8624 $1\adrok_l_s_addr_acked$next[0:0]$8622
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\adrok_l_s_addr_acked$next[0:0]$8713 1'0
+ assign $6\adrok_l_s_addr_acked$next[0:0]$8627 1'0
case
- assign $6\adrok_l_s_addr_acked$next[0:0]$8713 $3\adrok_l_s_addr_acked$next[0:0]$8710
+ assign $6\adrok_l_s_addr_acked$next[0:0]$8627 $3\adrok_l_s_addr_acked$next[0:0]$8624
end
sync always
- update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8707
+ update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8621
end
- attribute \src "libresoc.v:160305.3-160320.6"
- process $proc$libresoc.v:160305$8714
+ attribute \src "libresoc.v:158106.3-158121.6"
+ process $proc$libresoc.v:158106$8628
assign { } { }
assign { } { }
assign { } { }
assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0]
- attribute \src "libresoc.v:160306.5-160306.29"
+ attribute \src "libresoc.v:158107.5-158107.29"
switch \initial
- attribute \src "libresoc.v:160306.9-160306.17"
+ attribute \src "libresoc.v:158107.9-158107.17"
case 1'1
case
end
sync always
update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0]
end
- connect \$9 $not$libresoc.v:159774$8618_Y
- connect \$11 $and$libresoc.v:159775$8619_Y
- connect \$13 $not$libresoc.v:159776$8620_Y
- connect \$15 $and$libresoc.v:159777$8621_Y
- connect \$17 $not$libresoc.v:159778$8622_Y
- connect \$1 $and$libresoc.v:159779$8623_Y
- connect \$19 $and$libresoc.v:159780$8624_Y
- connect \$21 $pos$libresoc.v:159781$8626_Y
- connect \$23 $pos$libresoc.v:159782$8628_Y
- connect \$25 $and$libresoc.v:159783$8629_Y
- connect \$27 $and$libresoc.v:159784$8630_Y
- connect \$29 $and$libresoc.v:159785$8631_Y
- connect \$31 $and$libresoc.v:159786$8632_Y
- connect \$33 $and$libresoc.v:159787$8633_Y
- connect \$35 $not$libresoc.v:159788$8634_Y
- connect \$38 $or$libresoc.v:159789$8635_Y
- connect \$3 $or$libresoc.v:159790$8636_Y
- connect \$37 $not$libresoc.v:159791$8637_Y
- connect \$42 $and$libresoc.v:159792$8638_Y
- connect \$44 $mul$libresoc.v:159793$8639_Y
- connect \$46 $sshr$libresoc.v:159794$8640_Y
- connect \$48 $and$libresoc.v:159795$8641_Y
- connect \$50 $and$libresoc.v:159796$8642_Y
- connect \$52 $not$libresoc.v:159797$8643_Y
- connect \$54 $and$libresoc.v:159798$8644_Y
- connect \$57 $mul$libresoc.v:159799$8645_Y
- connect \$5 $not$libresoc.v:159800$8646_Y
- connect \$59 $sshl$libresoc.v:159801$8647_Y
- connect \$61 $and$libresoc.v:159802$8648_Y
- connect \$63 $or$libresoc.v:159803$8649_Y
- connect \$65 $and$libresoc.v:159804$8650_Y
- connect \$67 $or$libresoc.v:159805$8651_Y
- connect \$69 $and$libresoc.v:159806$8652_Y
- connect \$71 $not$libresoc.v:159807$8653_Y
- connect \$73 $not$libresoc.v:159808$8654_Y
- connect \$75 $not$libresoc.v:159809$8655_Y
- connect \$77 $and$libresoc.v:159810$8656_Y
- connect \$7 $and$libresoc.v:159811$8657_Y
- connect \$79 $not$libresoc.v:159812$8658_Y
- connect \$81 $not$libresoc.v:159813$8659_Y
- connect \$83 $and$libresoc.v:159814$8660_Y
+ connect \$9 $not$libresoc.v:157575$8532_Y
+ connect \$11 $and$libresoc.v:157576$8533_Y
+ connect \$13 $not$libresoc.v:157577$8534_Y
+ connect \$15 $and$libresoc.v:157578$8535_Y
+ connect \$17 $not$libresoc.v:157579$8536_Y
+ connect \$1 $and$libresoc.v:157580$8537_Y
+ connect \$19 $and$libresoc.v:157581$8538_Y
+ connect \$21 $pos$libresoc.v:157582$8540_Y
+ connect \$23 $pos$libresoc.v:157583$8542_Y
+ connect \$25 $and$libresoc.v:157584$8543_Y
+ connect \$27 $and$libresoc.v:157585$8544_Y
+ connect \$29 $and$libresoc.v:157586$8545_Y
+ connect \$31 $and$libresoc.v:157587$8546_Y
+ connect \$33 $and$libresoc.v:157588$8547_Y
+ connect \$35 $not$libresoc.v:157589$8548_Y
+ connect \$38 $or$libresoc.v:157590$8549_Y
+ connect \$3 $or$libresoc.v:157591$8550_Y
+ connect \$37 $not$libresoc.v:157592$8551_Y
+ connect \$42 $and$libresoc.v:157593$8552_Y
+ connect \$44 $mul$libresoc.v:157594$8553_Y
+ connect \$46 $sshr$libresoc.v:157595$8554_Y
+ connect \$48 $and$libresoc.v:157596$8555_Y
+ connect \$50 $and$libresoc.v:157597$8556_Y
+ connect \$52 $not$libresoc.v:157598$8557_Y
+ connect \$54 $and$libresoc.v:157599$8558_Y
+ connect \$57 $mul$libresoc.v:157600$8559_Y
+ connect \$5 $not$libresoc.v:157601$8560_Y
+ connect \$59 $sshl$libresoc.v:157602$8561_Y
+ connect \$61 $and$libresoc.v:157603$8562_Y
+ connect \$63 $or$libresoc.v:157604$8563_Y
+ connect \$65 $and$libresoc.v:157605$8564_Y
+ connect \$67 $or$libresoc.v:157606$8565_Y
+ connect \$69 $and$libresoc.v:157607$8566_Y
+ connect \$71 $not$libresoc.v:157608$8567_Y
+ connect \$73 $not$libresoc.v:157609$8568_Y
+ connect \$75 $not$libresoc.v:157610$8569_Y
+ connect \$77 $and$libresoc.v:157611$8570_Y
+ connect \$7 $and$libresoc.v:157612$8571_Y
+ connect \$79 $not$libresoc.v:157613$8572_Y
+ connect \$81 $not$libresoc.v:157614$8573_Y
+ connect \$83 $and$libresoc.v:157615$8574_Y
connect \$41 \$46
connect \$56 \$59
connect \valid_l_r_valid \lsui_active_rise
connect \sts \ldst_port0_is_st_i
connect \lds \ldst_port0_is_ld_i
end
-attribute \src "libresoc.v:160346.1-161116.10"
+attribute \src "libresoc.v:158147.1-158917.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe"
attribute \generator "nMigen"
module \pipe
- attribute \src "libresoc.v:161079.3-161097.6"
- wire width 4 $0\cr_a$6$next[3:0]$8770
- attribute \src "libresoc.v:160943.3-160944.31"
- wire width 4 $0\cr_a$6[3:0]$8726
- attribute \src "libresoc.v:160360.13-160360.28"
- wire width 4 $0\cr_a$6[3:0]$8776
- attribute \src "libresoc.v:161079.3-161097.6"
- wire $0\cr_a_ok$next[0:0]$8769
- attribute \src "libresoc.v:160945.3-160946.31"
+ attribute \src "libresoc.v:158880.3-158898.6"
+ wire width 4 $0\cr_a$6$next[3:0]$8684
+ attribute \src "libresoc.v:158744.3-158745.31"
+ wire width 4 $0\cr_a$6[3:0]$8640
+ attribute \src "libresoc.v:158161.13-158161.28"
+ wire width 4 $0\cr_a$6[3:0]$8690
+ attribute \src "libresoc.v:158880.3-158898.6"
+ wire $0\cr_a_ok$next[0:0]$8683
+ attribute \src "libresoc.v:158746.3-158747.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8750
- attribute \src "libresoc.v:160957.3-160958.51"
- wire width 13 $0\cr_op__fn_unit$3[12:0]$8736
- attribute \src "libresoc.v:160422.14-160422.43"
- wire width 13 $0\cr_op__fn_unit$3[12:0]$8779
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 32 $0\cr_op__insn$4$next[31:0]$8751
- attribute \src "libresoc.v:160959.3-160960.45"
- wire width 32 $0\cr_op__insn$4[31:0]$8738
- attribute \src "libresoc.v:160431.14-160431.37"
- wire width 32 $0\cr_op__insn$4[31:0]$8781
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 7 $0\cr_op__insn_type$2$next[6:0]$8752
- attribute \src "libresoc.v:160955.3-160956.55"
- wire width 7 $0\cr_op__insn_type$2[6:0]$8734
- attribute \src "libresoc.v:160662.13-160662.41"
- wire width 7 $0\cr_op__insn_type$2[6:0]$8783
- attribute \src "libresoc.v:161060.3-161078.6"
- wire width 32 $0\full_cr$5$next[31:0]$8763
- attribute \src "libresoc.v:160947.3-160948.37"
- wire width 32 $0\full_cr$5[31:0]$8729
- attribute \src "libresoc.v:160671.14-160671.33"
- wire width 32 $0\full_cr$5[31:0]$8785
- attribute \src "libresoc.v:161060.3-161078.6"
- wire $0\full_cr_ok$next[0:0]$8764
- attribute \src "libresoc.v:160949.3-160950.37"
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8664
+ attribute \src "libresoc.v:158758.3-158759.51"
+ wire width 13 $0\cr_op__fn_unit$3[12:0]$8650
+ attribute \src "libresoc.v:158223.14-158223.43"
+ wire width 13 $0\cr_op__fn_unit$3[12:0]$8693
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 32 $0\cr_op__insn$4$next[31:0]$8665
+ attribute \src "libresoc.v:158760.3-158761.45"
+ wire width 32 $0\cr_op__insn$4[31:0]$8652
+ attribute \src "libresoc.v:158232.14-158232.37"
+ wire width 32 $0\cr_op__insn$4[31:0]$8695
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 7 $0\cr_op__insn_type$2$next[6:0]$8666
+ attribute \src "libresoc.v:158756.3-158757.55"
+ wire width 7 $0\cr_op__insn_type$2[6:0]$8648
+ attribute \src "libresoc.v:158463.13-158463.41"
+ wire width 7 $0\cr_op__insn_type$2[6:0]$8697
+ attribute \src "libresoc.v:158861.3-158879.6"
+ wire width 32 $0\full_cr$5$next[31:0]$8677
+ attribute \src "libresoc.v:158748.3-158749.37"
+ wire width 32 $0\full_cr$5[31:0]$8643
+ attribute \src "libresoc.v:158472.14-158472.33"
+ wire width 32 $0\full_cr$5[31:0]$8699
+ attribute \src "libresoc.v:158861.3-158879.6"
+ wire $0\full_cr_ok$next[0:0]$8678
+ attribute \src "libresoc.v:158750.3-158751.37"
wire $0\full_cr_ok[0:0]
- attribute \src "libresoc.v:160347.7-160347.20"
+ attribute \src "libresoc.v:158148.7-158148.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:161013.3-161025.6"
- wire width 2 $0\muxid$1$next[1:0]$8747
- attribute \src "libresoc.v:160961.3-160962.33"
- wire width 2 $0\muxid$1[1:0]$8740
- attribute \src "libresoc.v:160901.13-160901.29"
- wire width 2 $0\muxid$1[1:0]$8788
- attribute \src "libresoc.v:161041.3-161059.6"
- wire width 64 $0\o$next[63:0]$8757
- attribute \src "libresoc.v:160951.3-160952.19"
+ attribute \src "libresoc.v:158814.3-158826.6"
+ wire width 2 $0\muxid$1$next[1:0]$8661
+ attribute \src "libresoc.v:158762.3-158763.33"
+ wire width 2 $0\muxid$1[1:0]$8654
+ attribute \src "libresoc.v:158702.13-158702.29"
+ wire width 2 $0\muxid$1[1:0]$8702
+ attribute \src "libresoc.v:158842.3-158860.6"
+ wire width 64 $0\o$next[63:0]$8671
+ attribute \src "libresoc.v:158752.3-158753.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:161041.3-161059.6"
- wire $0\o_ok$next[0:0]$8758
- attribute \src "libresoc.v:160953.3-160954.25"
+ attribute \src "libresoc.v:158842.3-158860.6"
+ wire $0\o_ok$next[0:0]$8672
+ attribute \src "libresoc.v:158754.3-158755.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:160995.3-161012.6"
- wire $0\r_busy$next[0:0]$8743
- attribute \src "libresoc.v:160963.3-160964.29"
+ attribute \src "libresoc.v:158796.3-158813.6"
+ wire $0\r_busy$next[0:0]$8657
+ attribute \src "libresoc.v:158764.3-158765.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:161079.3-161097.6"
- wire width 4 $1\cr_a$6$next[3:0]$8772
- attribute \src "libresoc.v:161079.3-161097.6"
- wire $1\cr_a_ok$next[0:0]$8771
- attribute \src "libresoc.v:160365.7-160365.21"
+ attribute \src "libresoc.v:158880.3-158898.6"
+ wire width 4 $1\cr_a$6$next[3:0]$8686
+ attribute \src "libresoc.v:158880.3-158898.6"
+ wire $1\cr_a_ok$next[0:0]$8685
+ attribute \src "libresoc.v:158166.7-158166.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 13 $1\cr_op__fn_unit$3$next[12:0]$8753
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 32 $1\cr_op__insn$4$next[31:0]$8754
- attribute \src "libresoc.v:161026.3-161040.6"
- wire width 7 $1\cr_op__insn_type$2$next[6:0]$8755
- attribute \src "libresoc.v:161060.3-161078.6"
- wire width 32 $1\full_cr$5$next[31:0]$8765
- attribute \src "libresoc.v:161060.3-161078.6"
- wire $1\full_cr_ok$next[0:0]$8766
- attribute \src "libresoc.v:160676.7-160676.24"
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 13 $1\cr_op__fn_unit$3$next[12:0]$8667
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 32 $1\cr_op__insn$4$next[31:0]$8668
+ attribute \src "libresoc.v:158827.3-158841.6"
+ wire width 7 $1\cr_op__insn_type$2$next[6:0]$8669
+ attribute \src "libresoc.v:158861.3-158879.6"
+ wire width 32 $1\full_cr$5$next[31:0]$8679
+ attribute \src "libresoc.v:158861.3-158879.6"
+ wire $1\full_cr_ok$next[0:0]$8680
+ attribute \src "libresoc.v:158477.7-158477.24"
wire $1\full_cr_ok[0:0]
- attribute \src "libresoc.v:161013.3-161025.6"
- wire width 2 $1\muxid$1$next[1:0]$8748
- attribute \src "libresoc.v:161041.3-161059.6"
- wire width 64 $1\o$next[63:0]$8759
- attribute \src "libresoc.v:160914.14-160914.38"
+ attribute \src "libresoc.v:158814.3-158826.6"
+ wire width 2 $1\muxid$1$next[1:0]$8662
+ attribute \src "libresoc.v:158842.3-158860.6"
+ wire width 64 $1\o$next[63:0]$8673
+ attribute \src "libresoc.v:158715.14-158715.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:161041.3-161059.6"
- wire $1\o_ok$next[0:0]$8760
- attribute \src "libresoc.v:160921.7-160921.18"
+ attribute \src "libresoc.v:158842.3-158860.6"
+ wire $1\o_ok$next[0:0]$8674
+ attribute \src "libresoc.v:158722.7-158722.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:160995.3-161012.6"
- wire $1\r_busy$next[0:0]$8744
- attribute \src "libresoc.v:160935.7-160935.20"
+ attribute \src "libresoc.v:158796.3-158813.6"
+ wire $1\r_busy$next[0:0]$8658
+ attribute \src "libresoc.v:158736.7-158736.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:161079.3-161097.6"
- wire $2\cr_a_ok$next[0:0]$8773
- attribute \src "libresoc.v:161060.3-161078.6"
- wire $2\full_cr_ok$next[0:0]$8767
- attribute \src "libresoc.v:161041.3-161059.6"
- wire $2\o_ok$next[0:0]$8761
- attribute \src "libresoc.v:160995.3-161012.6"
- wire $2\r_busy$next[0:0]$8745
- attribute \src "libresoc.v:160942.18-160942.118"
- wire $and$libresoc.v:160942$8724_Y
+ attribute \src "libresoc.v:158880.3-158898.6"
+ wire $2\cr_a_ok$next[0:0]$8687
+ attribute \src "libresoc.v:158861.3-158879.6"
+ wire $2\full_cr_ok$next[0:0]$8681
+ attribute \src "libresoc.v:158842.3-158860.6"
+ wire $2\o_ok$next[0:0]$8675
+ attribute \src "libresoc.v:158796.3-158813.6"
+ wire $2\r_busy$next[0:0]$8659
+ attribute \src "libresoc.v:158743.18-158743.118"
+ wire $and$libresoc.v:158743$8638_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 11 \cr_a
wire \full_cr_ok$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \full_cr_ok$next
- attribute \src "libresoc.v:160347.7-160347.15"
+ attribute \src "libresoc.v:158148.7-158148.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \main_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 9 \rb
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:160942$8724
+ cell $and $and$libresoc.v:158743$8638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$13
connect \B \p_ready_o
- connect \Y $and$libresoc.v:160942$8724_Y
+ connect \Y $and$libresoc.v:158743$8638_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:160965.12-160986.4"
+ attribute \src "libresoc.v:158766.12-158787.4"
cell \main$9 \main
connect \cr_a \main_cr_a
connect \cr_a$6 \main_cr_a$12
connect \rb \main_rb
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:160987.9-160990.4"
+ attribute \src "libresoc.v:158788.9-158791.4"
cell \n$8 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:160991.9-160994.4"
+ attribute \src "libresoc.v:158792.9-158795.4"
cell \p$7 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:160347.7-160347.20"
- process $proc$libresoc.v:160347$8774
+ attribute \src "libresoc.v:158148.7-158148.20"
+ process $proc$libresoc.v:158148$8688
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:160360.13-160360.28"
- process $proc$libresoc.v:160360$8775
+ attribute \src "libresoc.v:158161.13-158161.28"
+ process $proc$libresoc.v:158161$8689
assign { } { }
- assign $0\cr_a$6[3:0]$8776 4'0000
+ assign $0\cr_a$6[3:0]$8690 4'0000
sync always
sync init
- update \cr_a$6 $0\cr_a$6[3:0]$8776
+ update \cr_a$6 $0\cr_a$6[3:0]$8690
end
- attribute \src "libresoc.v:160365.7-160365.21"
- process $proc$libresoc.v:160365$8777
+ attribute \src "libresoc.v:158166.7-158166.21"
+ process $proc$libresoc.v:158166$8691
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:160422.14-160422.43"
- process $proc$libresoc.v:160422$8778
+ attribute \src "libresoc.v:158223.14-158223.43"
+ process $proc$libresoc.v:158223$8692
assign { } { }
- assign $0\cr_op__fn_unit$3[12:0]$8779 13'0000000000000
+ assign $0\cr_op__fn_unit$3[12:0]$8693 13'0000000000000
sync always
sync init
- update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8779
+ update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8693
end
- attribute \src "libresoc.v:160431.14-160431.37"
- process $proc$libresoc.v:160431$8780
+ attribute \src "libresoc.v:158232.14-158232.37"
+ process $proc$libresoc.v:158232$8694
assign { } { }
- assign $0\cr_op__insn$4[31:0]$8781 0
+ assign $0\cr_op__insn$4[31:0]$8695 0
sync always
sync init
- update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8781
+ update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8695
end
- attribute \src "libresoc.v:160662.13-160662.41"
- process $proc$libresoc.v:160662$8782
+ attribute \src "libresoc.v:158463.13-158463.41"
+ process $proc$libresoc.v:158463$8696
assign { } { }
- assign $0\cr_op__insn_type$2[6:0]$8783 7'0000000
+ assign $0\cr_op__insn_type$2[6:0]$8697 7'0000000
sync always
sync init
- update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8783
+ update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8697
end
- attribute \src "libresoc.v:160671.14-160671.33"
- process $proc$libresoc.v:160671$8784
+ attribute \src "libresoc.v:158472.14-158472.33"
+ process $proc$libresoc.v:158472$8698
assign { } { }
- assign $0\full_cr$5[31:0]$8785 0
+ assign $0\full_cr$5[31:0]$8699 0
sync always
sync init
- update \full_cr$5 $0\full_cr$5[31:0]$8785
+ update \full_cr$5 $0\full_cr$5[31:0]$8699
end
- attribute \src "libresoc.v:160676.7-160676.24"
- process $proc$libresoc.v:160676$8786
+ attribute \src "libresoc.v:158477.7-158477.24"
+ process $proc$libresoc.v:158477$8700
assign { } { }
assign $1\full_cr_ok[0:0] 1'0
sync always
sync init
update \full_cr_ok $1\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:160901.13-160901.29"
- process $proc$libresoc.v:160901$8787
+ attribute \src "libresoc.v:158702.13-158702.29"
+ process $proc$libresoc.v:158702$8701
assign { } { }
- assign $0\muxid$1[1:0]$8788 2'00
+ assign $0\muxid$1[1:0]$8702 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8788
+ update \muxid$1 $0\muxid$1[1:0]$8702
end
- attribute \src "libresoc.v:160914.14-160914.38"
- process $proc$libresoc.v:160914$8789
+ attribute \src "libresoc.v:158715.14-158715.38"
+ process $proc$libresoc.v:158715$8703
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:160921.7-160921.18"
- process $proc$libresoc.v:160921$8790
+ attribute \src "libresoc.v:158722.7-158722.18"
+ process $proc$libresoc.v:158722$8704
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:160935.7-160935.20"
- process $proc$libresoc.v:160935$8791
+ attribute \src "libresoc.v:158736.7-158736.20"
+ process $proc$libresoc.v:158736$8705
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:160943.3-160944.31"
- process $proc$libresoc.v:160943$8725
+ attribute \src "libresoc.v:158744.3-158745.31"
+ process $proc$libresoc.v:158744$8639
assign { } { }
- assign $0\cr_a$6[3:0]$8726 \cr_a$6$next
+ assign $0\cr_a$6[3:0]$8640 \cr_a$6$next
sync posedge \coresync_clk
- update \cr_a$6 $0\cr_a$6[3:0]$8726
+ update \cr_a$6 $0\cr_a$6[3:0]$8640
end
- attribute \src "libresoc.v:160945.3-160946.31"
- process $proc$libresoc.v:160945$8727
+ attribute \src "libresoc.v:158746.3-158747.31"
+ process $proc$libresoc.v:158746$8641
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:160947.3-160948.37"
- process $proc$libresoc.v:160947$8728
+ attribute \src "libresoc.v:158748.3-158749.37"
+ process $proc$libresoc.v:158748$8642
assign { } { }
- assign $0\full_cr$5[31:0]$8729 \full_cr$5$next
+ assign $0\full_cr$5[31:0]$8643 \full_cr$5$next
sync posedge \coresync_clk
- update \full_cr$5 $0\full_cr$5[31:0]$8729
+ update \full_cr$5 $0\full_cr$5[31:0]$8643
end
- attribute \src "libresoc.v:160949.3-160950.37"
- process $proc$libresoc.v:160949$8730
+ attribute \src "libresoc.v:158750.3-158751.37"
+ process $proc$libresoc.v:158750$8644
assign { } { }
assign $0\full_cr_ok[0:0] \full_cr_ok$next
sync posedge \coresync_clk
update \full_cr_ok $0\full_cr_ok[0:0]
end
- attribute \src "libresoc.v:160951.3-160952.19"
- process $proc$libresoc.v:160951$8731
+ attribute \src "libresoc.v:158752.3-158753.19"
+ process $proc$libresoc.v:158752$8645
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:160953.3-160954.25"
- process $proc$libresoc.v:160953$8732
+ attribute \src "libresoc.v:158754.3-158755.25"
+ process $proc$libresoc.v:158754$8646
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:160955.3-160956.55"
- process $proc$libresoc.v:160955$8733
+ attribute \src "libresoc.v:158756.3-158757.55"
+ process $proc$libresoc.v:158756$8647
assign { } { }
- assign $0\cr_op__insn_type$2[6:0]$8734 \cr_op__insn_type$2$next
+ assign $0\cr_op__insn_type$2[6:0]$8648 \cr_op__insn_type$2$next
sync posedge \coresync_clk
- update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8734
+ update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8648
end
- attribute \src "libresoc.v:160957.3-160958.51"
- process $proc$libresoc.v:160957$8735
+ attribute \src "libresoc.v:158758.3-158759.51"
+ process $proc$libresoc.v:158758$8649
assign { } { }
- assign $0\cr_op__fn_unit$3[12:0]$8736 \cr_op__fn_unit$3$next
+ assign $0\cr_op__fn_unit$3[12:0]$8650 \cr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8736
+ update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8650
end
- attribute \src "libresoc.v:160959.3-160960.45"
- process $proc$libresoc.v:160959$8737
+ attribute \src "libresoc.v:158760.3-158761.45"
+ process $proc$libresoc.v:158760$8651
assign { } { }
- assign $0\cr_op__insn$4[31:0]$8738 \cr_op__insn$4$next
+ assign $0\cr_op__insn$4[31:0]$8652 \cr_op__insn$4$next
sync posedge \coresync_clk
- update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8738
+ update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8652
end
- attribute \src "libresoc.v:160961.3-160962.33"
- process $proc$libresoc.v:160961$8739
+ attribute \src "libresoc.v:158762.3-158763.33"
+ process $proc$libresoc.v:158762$8653
assign { } { }
- assign $0\muxid$1[1:0]$8740 \muxid$1$next
+ assign $0\muxid$1[1:0]$8654 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8740
+ update \muxid$1 $0\muxid$1[1:0]$8654
end
- attribute \src "libresoc.v:160963.3-160964.29"
- process $proc$libresoc.v:160963$8741
+ attribute \src "libresoc.v:158764.3-158765.29"
+ process $proc$libresoc.v:158764$8655
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:160995.3-161012.6"
- process $proc$libresoc.v:160995$8742
+ attribute \src "libresoc.v:158796.3-158813.6"
+ process $proc$libresoc.v:158796$8656
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8743 $2\r_busy$next[0:0]$8745
- attribute \src "libresoc.v:160996.5-160996.29"
+ assign $0\r_busy$next[0:0]$8657 $2\r_busy$next[0:0]$8659
+ attribute \src "libresoc.v:158797.5-158797.29"
switch \initial
- attribute \src "libresoc.v:160996.9-160996.17"
+ attribute \src "libresoc.v:158797.9-158797.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8744 1'1
+ assign $1\r_busy$next[0:0]$8658 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8744 1'0
+ assign $1\r_busy$next[0:0]$8658 1'0
case
- assign $1\r_busy$next[0:0]$8744 \r_busy
+ assign $1\r_busy$next[0:0]$8658 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8745 1'0
+ assign $2\r_busy$next[0:0]$8659 1'0
case
- assign $2\r_busy$next[0:0]$8745 $1\r_busy$next[0:0]$8744
+ assign $2\r_busy$next[0:0]$8659 $1\r_busy$next[0:0]$8658
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8743
+ update \r_busy$next $0\r_busy$next[0:0]$8657
end
- attribute \src "libresoc.v:161013.3-161025.6"
- process $proc$libresoc.v:161013$8746
+ attribute \src "libresoc.v:158814.3-158826.6"
+ process $proc$libresoc.v:158814$8660
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8747 $1\muxid$1$next[1:0]$8748
- attribute \src "libresoc.v:161014.5-161014.29"
+ assign $0\muxid$1$next[1:0]$8661 $1\muxid$1$next[1:0]$8662
+ attribute \src "libresoc.v:158815.5-158815.29"
switch \initial
- attribute \src "libresoc.v:161014.9-161014.17"
+ attribute \src "libresoc.v:158815.9-158815.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8748 \muxid$16
+ assign $1\muxid$1$next[1:0]$8662 \muxid$16
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8748 \muxid$16
+ assign $1\muxid$1$next[1:0]$8662 \muxid$16
case
- assign $1\muxid$1$next[1:0]$8748 \muxid$1
+ assign $1\muxid$1$next[1:0]$8662 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8747
+ update \muxid$1$next $0\muxid$1$next[1:0]$8661
end
- attribute \src "libresoc.v:161026.3-161040.6"
- process $proc$libresoc.v:161026$8749
+ attribute \src "libresoc.v:158827.3-158841.6"
+ process $proc$libresoc.v:158827$8663
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_op__fn_unit$3$next[12:0]$8750 $1\cr_op__fn_unit$3$next[12:0]$8753
- assign $0\cr_op__insn$4$next[31:0]$8751 $1\cr_op__insn$4$next[31:0]$8754
- assign $0\cr_op__insn_type$2$next[6:0]$8752 $1\cr_op__insn_type$2$next[6:0]$8755
- attribute \src "libresoc.v:161027.5-161027.29"
+ assign $0\cr_op__fn_unit$3$next[12:0]$8664 $1\cr_op__fn_unit$3$next[12:0]$8667
+ assign $0\cr_op__insn$4$next[31:0]$8665 $1\cr_op__insn$4$next[31:0]$8668
+ assign $0\cr_op__insn_type$2$next[6:0]$8666 $1\cr_op__insn_type$2$next[6:0]$8669
+ attribute \src "libresoc.v:158828.5-158828.29"
switch \initial
- attribute \src "libresoc.v:161027.9-161027.17"
+ attribute \src "libresoc.v:158828.9-158828.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\cr_op__insn$4$next[31:0]$8754 $1\cr_op__fn_unit$3$next[12:0]$8753 $1\cr_op__insn_type$2$next[6:0]$8755 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
+ assign { $1\cr_op__insn$4$next[31:0]$8668 $1\cr_op__fn_unit$3$next[12:0]$8667 $1\cr_op__insn_type$2$next[6:0]$8669 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
- assign { $1\cr_op__insn$4$next[31:0]$8754 $1\cr_op__fn_unit$3$next[12:0]$8753 $1\cr_op__insn_type$2$next[6:0]$8755 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
+ assign { $1\cr_op__insn$4$next[31:0]$8668 $1\cr_op__fn_unit$3$next[12:0]$8667 $1\cr_op__insn_type$2$next[6:0]$8669 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 }
case
- assign $1\cr_op__fn_unit$3$next[12:0]$8753 \cr_op__fn_unit$3
- assign $1\cr_op__insn$4$next[31:0]$8754 \cr_op__insn$4
- assign $1\cr_op__insn_type$2$next[6:0]$8755 \cr_op__insn_type$2
+ assign $1\cr_op__fn_unit$3$next[12:0]$8667 \cr_op__fn_unit$3
+ assign $1\cr_op__insn$4$next[31:0]$8668 \cr_op__insn$4
+ assign $1\cr_op__insn_type$2$next[6:0]$8669 \cr_op__insn_type$2
end
sync always
- update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8750
- update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8751
- update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8752
+ update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8664
+ update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8665
+ update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8666
end
- attribute \src "libresoc.v:161041.3-161059.6"
- process $proc$libresoc.v:161041$8756
+ attribute \src "libresoc.v:158842.3-158860.6"
+ process $proc$libresoc.v:158842$8670
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$8757 $1\o$next[63:0]$8759
+ assign $0\o$next[63:0]$8671 $1\o$next[63:0]$8673
assign { } { }
- assign $0\o_ok$next[0:0]$8758 $2\o_ok$next[0:0]$8761
- attribute \src "libresoc.v:161042.5-161042.29"
+ assign $0\o_ok$next[0:0]$8672 $2\o_ok$next[0:0]$8675
+ attribute \src "libresoc.v:158843.5-158843.29"
switch \initial
- attribute \src "libresoc.v:161042.9-161042.17"
+ attribute \src "libresoc.v:158843.9-158843.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8760 $1\o$next[63:0]$8759 } { \o_ok$21 \o$20 }
+ assign { $1\o_ok$next[0:0]$8674 $1\o$next[63:0]$8673 } { \o_ok$21 \o$20 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8760 $1\o$next[63:0]$8759 } { \o_ok$21 \o$20 }
+ assign { $1\o_ok$next[0:0]$8674 $1\o$next[63:0]$8673 } { \o_ok$21 \o$20 }
case
- assign $1\o$next[63:0]$8759 \o
- assign $1\o_ok$next[0:0]$8760 \o_ok
+ assign $1\o$next[63:0]$8673 \o
+ assign $1\o_ok$next[0:0]$8674 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8761 1'0
+ assign $2\o_ok$next[0:0]$8675 1'0
case
- assign $2\o_ok$next[0:0]$8761 $1\o_ok$next[0:0]$8760
+ assign $2\o_ok$next[0:0]$8675 $1\o_ok$next[0:0]$8674
end
sync always
- update \o$next $0\o$next[63:0]$8757
- update \o_ok$next $0\o_ok$next[0:0]$8758
+ update \o$next $0\o$next[63:0]$8671
+ update \o_ok$next $0\o_ok$next[0:0]$8672
end
- attribute \src "libresoc.v:161060.3-161078.6"
- process $proc$libresoc.v:161060$8762
+ attribute \src "libresoc.v:158861.3-158879.6"
+ process $proc$libresoc.v:158861$8676
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\full_cr$5$next[31:0]$8763 $1\full_cr$5$next[31:0]$8765
+ assign $0\full_cr$5$next[31:0]$8677 $1\full_cr$5$next[31:0]$8679
assign { } { }
- assign $0\full_cr_ok$next[0:0]$8764 $2\full_cr_ok$next[0:0]$8767
- attribute \src "libresoc.v:161061.5-161061.29"
+ assign $0\full_cr_ok$next[0:0]$8678 $2\full_cr_ok$next[0:0]$8681
+ attribute \src "libresoc.v:158862.5-158862.29"
switch \initial
- attribute \src "libresoc.v:161061.9-161061.17"
+ attribute \src "libresoc.v:158862.9-158862.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\full_cr_ok$next[0:0]$8766 $1\full_cr$5$next[31:0]$8765 } { \full_cr_ok$23 \full_cr$22 }
+ assign { $1\full_cr_ok$next[0:0]$8680 $1\full_cr$5$next[31:0]$8679 } { \full_cr_ok$23 \full_cr$22 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\full_cr_ok$next[0:0]$8766 $1\full_cr$5$next[31:0]$8765 } { \full_cr_ok$23 \full_cr$22 }
+ assign { $1\full_cr_ok$next[0:0]$8680 $1\full_cr$5$next[31:0]$8679 } { \full_cr_ok$23 \full_cr$22 }
case
- assign $1\full_cr$5$next[31:0]$8765 \full_cr$5
- assign $1\full_cr_ok$next[0:0]$8766 \full_cr_ok
+ assign $1\full_cr$5$next[31:0]$8679 \full_cr$5
+ assign $1\full_cr_ok$next[0:0]$8680 \full_cr_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\full_cr_ok$next[0:0]$8767 1'0
+ assign $2\full_cr_ok$next[0:0]$8681 1'0
case
- assign $2\full_cr_ok$next[0:0]$8767 $1\full_cr_ok$next[0:0]$8766
+ assign $2\full_cr_ok$next[0:0]$8681 $1\full_cr_ok$next[0:0]$8680
end
sync always
- update \full_cr$5$next $0\full_cr$5$next[31:0]$8763
- update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8764
+ update \full_cr$5$next $0\full_cr$5$next[31:0]$8677
+ update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8678
end
- attribute \src "libresoc.v:161079.3-161097.6"
- process $proc$libresoc.v:161079$8768
+ attribute \src "libresoc.v:158880.3-158898.6"
+ process $proc$libresoc.v:158880$8682
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$6$next[3:0]$8770 $1\cr_a$6$next[3:0]$8772
- assign $0\cr_a_ok$next[0:0]$8769 $2\cr_a_ok$next[0:0]$8773
- attribute \src "libresoc.v:161080.5-161080.29"
+ assign $0\cr_a$6$next[3:0]$8684 $1\cr_a$6$next[3:0]$8686
+ assign $0\cr_a_ok$next[0:0]$8683 $2\cr_a_ok$next[0:0]$8687
+ attribute \src "libresoc.v:158881.5-158881.29"
switch \initial
- attribute \src "libresoc.v:161080.9-161080.17"
+ attribute \src "libresoc.v:158881.9-158881.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8771 $1\cr_a$6$next[3:0]$8772 } { \cr_a_ok$25 \cr_a$24 }
+ assign { $1\cr_a_ok$next[0:0]$8685 $1\cr_a$6$next[3:0]$8686 } { \cr_a_ok$25 \cr_a$24 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$8771 $1\cr_a$6$next[3:0]$8772 } { \cr_a_ok$25 \cr_a$24 }
+ assign { $1\cr_a_ok$next[0:0]$8685 $1\cr_a$6$next[3:0]$8686 } { \cr_a_ok$25 \cr_a$24 }
case
- assign $1\cr_a_ok$next[0:0]$8771 \cr_a_ok
- assign $1\cr_a$6$next[3:0]$8772 \cr_a$6
+ assign $1\cr_a_ok$next[0:0]$8685 \cr_a_ok
+ assign $1\cr_a$6$next[3:0]$8686 \cr_a$6
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$8773 1'0
+ assign $2\cr_a_ok$next[0:0]$8687 1'0
case
- assign $2\cr_a_ok$next[0:0]$8773 $1\cr_a_ok$next[0:0]$8771
+ assign $2\cr_a_ok$next[0:0]$8687 $1\cr_a_ok$next[0:0]$8685
end
sync always
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8769
- update \cr_a$6$next $0\cr_a$6$next[3:0]$8770
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8683
+ update \cr_a$6$next $0\cr_a$6$next[3:0]$8684
end
- connect \$14 $and$libresoc.v:160942$8724_Y
+ connect \$14 $and$libresoc.v:158743$8638_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 }
connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:161120.1-161970.10"
+attribute \src "libresoc.v:158921.1-159771.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe"
attribute \generator "nMigen"
module \pipe$19
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 64 $0\br_op__cia$2$next[63:0]$8828
- attribute \src "libresoc.v:161782.3-161783.43"
- wire width 64 $0\br_op__cia$2[63:0]$8802
- attribute \src "libresoc.v:161128.14-161128.51"
- wire width 64 $0\br_op__cia$2[63:0]$8866
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 13 $0\br_op__fn_unit$4$next[12:0]$8829
- attribute \src "libresoc.v:161786.3-161787.51"
- wire width 13 $0\br_op__fn_unit$4[12:0]$8806
- attribute \src "libresoc.v:161181.14-161181.43"
- wire width 13 $0\br_op__fn_unit$4[12:0]$8868
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8830
- attribute \src "libresoc.v:161790.3-161791.65"
- wire width 64 $0\br_op__imm_data__data$6[63:0]$8810
- attribute \src "libresoc.v:161190.14-161190.62"
- wire width 64 $0\br_op__imm_data__data$6[63:0]$8870
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $0\br_op__imm_data__ok$7$next[0:0]$8831
- attribute \src "libresoc.v:161792.3-161793.61"
- wire $0\br_op__imm_data__ok$7[0:0]$8812
- attribute \src "libresoc.v:161199.7-161199.37"
- wire $0\br_op__imm_data__ok$7[0:0]$8872
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 32 $0\br_op__insn$5$next[31:0]$8832
- attribute \src "libresoc.v:161788.3-161789.45"
- wire width 32 $0\br_op__insn$5[31:0]$8808
- attribute \src "libresoc.v:161208.14-161208.37"
- wire width 32 $0\br_op__insn$5[31:0]$8874
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 7 $0\br_op__insn_type$3$next[6:0]$8833
- attribute \src "libresoc.v:161784.3-161785.55"
- wire width 7 $0\br_op__insn_type$3[6:0]$8804
- attribute \src "libresoc.v:161439.13-161439.41"
- wire width 7 $0\br_op__insn_type$3[6:0]$8876
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $0\br_op__is_32bit$9$next[0:0]$8834
- attribute \src "libresoc.v:161796.3-161797.53"
- wire $0\br_op__is_32bit$9[0:0]$8816
- attribute \src "libresoc.v:161448.7-161448.33"
- wire $0\br_op__is_32bit$9[0:0]$8878
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $0\br_op__lk$8$next[0:0]$8835
- attribute \src "libresoc.v:161794.3-161795.41"
- wire $0\br_op__lk$8[0:0]$8814
- attribute \src "libresoc.v:161457.7-161457.27"
- wire $0\br_op__lk$8[0:0]$8880
- attribute \src "libresoc.v:161898.3-161916.6"
- wire width 64 $0\fast1$10$next[63:0]$8847
- attribute \src "libresoc.v:161778.3-161779.35"
- wire width 64 $0\fast1$10[63:0]$8799
- attribute \src "libresoc.v:161470.14-161470.47"
- wire width 64 $0\fast1$10[63:0]$8882
- attribute \src "libresoc.v:161898.3-161916.6"
- wire $0\fast1_ok$next[0:0]$8848
- attribute \src "libresoc.v:161780.3-161781.33"
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 64 $0\br_op__cia$2$next[63:0]$8742
+ attribute \src "libresoc.v:159583.3-159584.43"
+ wire width 64 $0\br_op__cia$2[63:0]$8716
+ attribute \src "libresoc.v:158929.14-158929.51"
+ wire width 64 $0\br_op__cia$2[63:0]$8780
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 13 $0\br_op__fn_unit$4$next[12:0]$8743
+ attribute \src "libresoc.v:159587.3-159588.51"
+ wire width 13 $0\br_op__fn_unit$4[12:0]$8720
+ attribute \src "libresoc.v:158982.14-158982.43"
+ wire width 13 $0\br_op__fn_unit$4[12:0]$8782
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8744
+ attribute \src "libresoc.v:159591.3-159592.65"
+ wire width 64 $0\br_op__imm_data__data$6[63:0]$8724
+ attribute \src "libresoc.v:158991.14-158991.62"
+ wire width 64 $0\br_op__imm_data__data$6[63:0]$8784
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $0\br_op__imm_data__ok$7$next[0:0]$8745
+ attribute \src "libresoc.v:159593.3-159594.61"
+ wire $0\br_op__imm_data__ok$7[0:0]$8726
+ attribute \src "libresoc.v:159000.7-159000.37"
+ wire $0\br_op__imm_data__ok$7[0:0]$8786
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 32 $0\br_op__insn$5$next[31:0]$8746
+ attribute \src "libresoc.v:159589.3-159590.45"
+ wire width 32 $0\br_op__insn$5[31:0]$8722
+ attribute \src "libresoc.v:159009.14-159009.37"
+ wire width 32 $0\br_op__insn$5[31:0]$8788
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 7 $0\br_op__insn_type$3$next[6:0]$8747
+ attribute \src "libresoc.v:159585.3-159586.55"
+ wire width 7 $0\br_op__insn_type$3[6:0]$8718
+ attribute \src "libresoc.v:159240.13-159240.41"
+ wire width 7 $0\br_op__insn_type$3[6:0]$8790
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $0\br_op__is_32bit$9$next[0:0]$8748
+ attribute \src "libresoc.v:159597.3-159598.53"
+ wire $0\br_op__is_32bit$9[0:0]$8730
+ attribute \src "libresoc.v:159249.7-159249.33"
+ wire $0\br_op__is_32bit$9[0:0]$8792
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $0\br_op__lk$8$next[0:0]$8749
+ attribute \src "libresoc.v:159595.3-159596.41"
+ wire $0\br_op__lk$8[0:0]$8728
+ attribute \src "libresoc.v:159258.7-159258.27"
+ wire $0\br_op__lk$8[0:0]$8794
+ attribute \src "libresoc.v:159699.3-159717.6"
+ wire width 64 $0\fast1$10$next[63:0]$8761
+ attribute \src "libresoc.v:159579.3-159580.35"
+ wire width 64 $0\fast1$10[63:0]$8713
+ attribute \src "libresoc.v:159271.14-159271.47"
+ wire width 64 $0\fast1$10[63:0]$8796
+ attribute \src "libresoc.v:159699.3-159717.6"
+ wire $0\fast1_ok$next[0:0]$8762
+ attribute \src "libresoc.v:159581.3-159582.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:161917.3-161935.6"
- wire width 64 $0\fast2$11$next[63:0]$8853
- attribute \src "libresoc.v:161774.3-161775.35"
- wire width 64 $0\fast2$11[63:0]$8796
- attribute \src "libresoc.v:161486.14-161486.47"
- wire width 64 $0\fast2$11[63:0]$8885
- attribute \src "libresoc.v:161917.3-161935.6"
- wire $0\fast2_ok$next[0:0]$8854
- attribute \src "libresoc.v:161776.3-161777.33"
+ attribute \src "libresoc.v:159718.3-159736.6"
+ wire width 64 $0\fast2$11$next[63:0]$8767
+ attribute \src "libresoc.v:159575.3-159576.35"
+ wire width 64 $0\fast2$11[63:0]$8710
+ attribute \src "libresoc.v:159287.14-159287.47"
+ wire width 64 $0\fast2$11[63:0]$8799
+ attribute \src "libresoc.v:159718.3-159736.6"
+ wire $0\fast2_ok$next[0:0]$8768
+ attribute \src "libresoc.v:159577.3-159578.33"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:161121.7-161121.20"
+ attribute \src "libresoc.v:158922.7-158922.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:161857.3-161869.6"
- wire width 2 $0\muxid$1$next[1:0]$8825
- attribute \src "libresoc.v:161798.3-161799.33"
- wire width 2 $0\muxid$1[1:0]$8818
- attribute \src "libresoc.v:161732.13-161732.29"
- wire width 2 $0\muxid$1[1:0]$8888
- attribute \src "libresoc.v:161936.3-161954.6"
- wire width 64 $0\nia$next[63:0]$8859
- attribute \src "libresoc.v:161770.3-161771.23"
+ attribute \src "libresoc.v:159658.3-159670.6"
+ wire width 2 $0\muxid$1$next[1:0]$8739
+ attribute \src "libresoc.v:159599.3-159600.33"
+ wire width 2 $0\muxid$1[1:0]$8732
+ attribute \src "libresoc.v:159533.13-159533.29"
+ wire width 2 $0\muxid$1[1:0]$8802
+ attribute \src "libresoc.v:159737.3-159755.6"
+ wire width 64 $0\nia$next[63:0]$8773
+ attribute \src "libresoc.v:159571.3-159572.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:161936.3-161954.6"
- wire $0\nia_ok$next[0:0]$8860
- attribute \src "libresoc.v:161772.3-161773.29"
+ attribute \src "libresoc.v:159737.3-159755.6"
+ wire $0\nia_ok$next[0:0]$8774
+ attribute \src "libresoc.v:159573.3-159574.29"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:161839.3-161856.6"
- wire $0\r_busy$next[0:0]$8821
- attribute \src "libresoc.v:161800.3-161801.29"
+ attribute \src "libresoc.v:159640.3-159657.6"
+ wire $0\r_busy$next[0:0]$8735
+ attribute \src "libresoc.v:159601.3-159602.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 64 $1\br_op__cia$2$next[63:0]$8836
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 13 $1\br_op__fn_unit$4$next[12:0]$8837
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8838
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $1\br_op__imm_data__ok$7$next[0:0]$8839
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 32 $1\br_op__insn$5$next[31:0]$8840
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 7 $1\br_op__insn_type$3$next[6:0]$8841
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $1\br_op__is_32bit$9$next[0:0]$8842
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $1\br_op__lk$8$next[0:0]$8843
- attribute \src "libresoc.v:161898.3-161916.6"
- wire width 64 $1\fast1$10$next[63:0]$8849
- attribute \src "libresoc.v:161898.3-161916.6"
- wire $1\fast1_ok$next[0:0]$8850
- attribute \src "libresoc.v:161477.7-161477.22"
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 64 $1\br_op__cia$2$next[63:0]$8750
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 13 $1\br_op__fn_unit$4$next[12:0]$8751
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8752
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $1\br_op__imm_data__ok$7$next[0:0]$8753
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 32 $1\br_op__insn$5$next[31:0]$8754
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 7 $1\br_op__insn_type$3$next[6:0]$8755
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $1\br_op__is_32bit$9$next[0:0]$8756
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $1\br_op__lk$8$next[0:0]$8757
+ attribute \src "libresoc.v:159699.3-159717.6"
+ wire width 64 $1\fast1$10$next[63:0]$8763
+ attribute \src "libresoc.v:159699.3-159717.6"
+ wire $1\fast1_ok$next[0:0]$8764
+ attribute \src "libresoc.v:159278.7-159278.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:161917.3-161935.6"
- wire width 64 $1\fast2$11$next[63:0]$8855
- attribute \src "libresoc.v:161917.3-161935.6"
- wire $1\fast2_ok$next[0:0]$8856
- attribute \src "libresoc.v:161493.7-161493.22"
+ attribute \src "libresoc.v:159718.3-159736.6"
+ wire width 64 $1\fast2$11$next[63:0]$8769
+ attribute \src "libresoc.v:159718.3-159736.6"
+ wire $1\fast2_ok$next[0:0]$8770
+ attribute \src "libresoc.v:159294.7-159294.22"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:161857.3-161869.6"
- wire width 2 $1\muxid$1$next[1:0]$8826
- attribute \src "libresoc.v:161936.3-161954.6"
- wire width 64 $1\nia$next[63:0]$8861
- attribute \src "libresoc.v:161745.14-161745.40"
+ attribute \src "libresoc.v:159658.3-159670.6"
+ wire width 2 $1\muxid$1$next[1:0]$8740
+ attribute \src "libresoc.v:159737.3-159755.6"
+ wire width 64 $1\nia$next[63:0]$8775
+ attribute \src "libresoc.v:159546.14-159546.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:161936.3-161954.6"
- wire $1\nia_ok$next[0:0]$8862
- attribute \src "libresoc.v:161752.7-161752.20"
+ attribute \src "libresoc.v:159737.3-159755.6"
+ wire $1\nia_ok$next[0:0]$8776
+ attribute \src "libresoc.v:159553.7-159553.20"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:161839.3-161856.6"
- wire $1\r_busy$next[0:0]$8822
- attribute \src "libresoc.v:161766.7-161766.20"
+ attribute \src "libresoc.v:159640.3-159657.6"
+ wire $1\r_busy$next[0:0]$8736
+ attribute \src "libresoc.v:159567.7-159567.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:161870.3-161897.6"
- wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8844
- attribute \src "libresoc.v:161870.3-161897.6"
- wire $2\br_op__imm_data__ok$7$next[0:0]$8845
- attribute \src "libresoc.v:161898.3-161916.6"
- wire $2\fast1_ok$next[0:0]$8851
- attribute \src "libresoc.v:161917.3-161935.6"
- wire $2\fast2_ok$next[0:0]$8857
- attribute \src "libresoc.v:161936.3-161954.6"
- wire $2\nia_ok$next[0:0]$8863
- attribute \src "libresoc.v:161839.3-161856.6"
- wire $2\r_busy$next[0:0]$8823
- attribute \src "libresoc.v:161769.18-161769.118"
- wire $and$libresoc.v:161769$8792_Y
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8758
+ attribute \src "libresoc.v:159671.3-159698.6"
+ wire $2\br_op__imm_data__ok$7$next[0:0]$8759
+ attribute \src "libresoc.v:159699.3-159717.6"
+ wire $2\fast1_ok$next[0:0]$8765
+ attribute \src "libresoc.v:159718.3-159736.6"
+ wire $2\fast2_ok$next[0:0]$8771
+ attribute \src "libresoc.v:159737.3-159755.6"
+ wire $2\nia_ok$next[0:0]$8777
+ attribute \src "libresoc.v:159640.3-159657.6"
+ wire $2\r_busy$next[0:0]$8737
+ attribute \src "libresoc.v:159570.18-159570.118"
+ wire $and$libresoc.v:159570$8706_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire output 25 \br_op__lk$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 15 \cr_a
wire \fast2_ok$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast2_ok$next
- attribute \src "libresoc.v:161121.7-161121.15"
+ attribute \src "libresoc.v:158922.7-158922.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 64 \main_br_op__cia
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire \r_busy$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:161769$8792
+ cell $and $and$libresoc.v:159570$8706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$23
connect \B \p_ready_o
- connect \Y $and$libresoc.v:161769$8792_Y
+ connect \Y $and$libresoc.v:159570$8706_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:161802.13-161830.4"
+ attribute \src "libresoc.v:159603.13-159631.4"
cell \main$22 \main
connect \br_op__cia \main_br_op__cia
connect \br_op__cia$2 \main_br_op__cia$13
connect \nia_ok \main_nia_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:161831.10-161834.4"
+ attribute \src "libresoc.v:159632.10-159635.4"
cell \n$21 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:161835.10-161838.4"
+ attribute \src "libresoc.v:159636.10-159639.4"
cell \p$20 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:161121.7-161121.20"
- process $proc$libresoc.v:161121$8864
+ attribute \src "libresoc.v:158922.7-158922.20"
+ process $proc$libresoc.v:158922$8778
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:161128.14-161128.51"
- process $proc$libresoc.v:161128$8865
+ attribute \src "libresoc.v:158929.14-158929.51"
+ process $proc$libresoc.v:158929$8779
assign { } { }
- assign $0\br_op__cia$2[63:0]$8866 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\br_op__cia$2[63:0]$8780 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \br_op__cia$2 $0\br_op__cia$2[63:0]$8866
+ update \br_op__cia$2 $0\br_op__cia$2[63:0]$8780
end
- attribute \src "libresoc.v:161181.14-161181.43"
- process $proc$libresoc.v:161181$8867
+ attribute \src "libresoc.v:158982.14-158982.43"
+ process $proc$libresoc.v:158982$8781
assign { } { }
- assign $0\br_op__fn_unit$4[12:0]$8868 13'0000000000000
+ assign $0\br_op__fn_unit$4[12:0]$8782 13'0000000000000
sync always
sync init
- update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8868
+ update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8782
end
- attribute \src "libresoc.v:161190.14-161190.62"
- process $proc$libresoc.v:161190$8869
+ attribute \src "libresoc.v:158991.14-158991.62"
+ process $proc$libresoc.v:158991$8783
assign { } { }
- assign $0\br_op__imm_data__data$6[63:0]$8870 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\br_op__imm_data__data$6[63:0]$8784 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8870
+ update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8784
end
- attribute \src "libresoc.v:161199.7-161199.37"
- process $proc$libresoc.v:161199$8871
+ attribute \src "libresoc.v:159000.7-159000.37"
+ process $proc$libresoc.v:159000$8785
assign { } { }
- assign $0\br_op__imm_data__ok$7[0:0]$8872 1'0
+ assign $0\br_op__imm_data__ok$7[0:0]$8786 1'0
sync always
sync init
- update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8872
+ update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8786
end
- attribute \src "libresoc.v:161208.14-161208.37"
- process $proc$libresoc.v:161208$8873
+ attribute \src "libresoc.v:159009.14-159009.37"
+ process $proc$libresoc.v:159009$8787
assign { } { }
- assign $0\br_op__insn$5[31:0]$8874 0
+ assign $0\br_op__insn$5[31:0]$8788 0
sync always
sync init
- update \br_op__insn$5 $0\br_op__insn$5[31:0]$8874
+ update \br_op__insn$5 $0\br_op__insn$5[31:0]$8788
end
- attribute \src "libresoc.v:161439.13-161439.41"
- process $proc$libresoc.v:161439$8875
+ attribute \src "libresoc.v:159240.13-159240.41"
+ process $proc$libresoc.v:159240$8789
assign { } { }
- assign $0\br_op__insn_type$3[6:0]$8876 7'0000000
+ assign $0\br_op__insn_type$3[6:0]$8790 7'0000000
sync always
sync init
- update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8876
+ update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8790
end
- attribute \src "libresoc.v:161448.7-161448.33"
- process $proc$libresoc.v:161448$8877
+ attribute \src "libresoc.v:159249.7-159249.33"
+ process $proc$libresoc.v:159249$8791
assign { } { }
- assign $0\br_op__is_32bit$9[0:0]$8878 1'0
+ assign $0\br_op__is_32bit$9[0:0]$8792 1'0
sync always
sync init
- update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8878
+ update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8792
end
- attribute \src "libresoc.v:161457.7-161457.27"
- process $proc$libresoc.v:161457$8879
+ attribute \src "libresoc.v:159258.7-159258.27"
+ process $proc$libresoc.v:159258$8793
assign { } { }
- assign $0\br_op__lk$8[0:0]$8880 1'0
+ assign $0\br_op__lk$8[0:0]$8794 1'0
sync always
sync init
- update \br_op__lk$8 $0\br_op__lk$8[0:0]$8880
+ update \br_op__lk$8 $0\br_op__lk$8[0:0]$8794
end
- attribute \src "libresoc.v:161470.14-161470.47"
- process $proc$libresoc.v:161470$8881
+ attribute \src "libresoc.v:159271.14-159271.47"
+ process $proc$libresoc.v:159271$8795
assign { } { }
- assign $0\fast1$10[63:0]$8882 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$10[63:0]$8796 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$10 $0\fast1$10[63:0]$8882
+ update \fast1$10 $0\fast1$10[63:0]$8796
end
- attribute \src "libresoc.v:161477.7-161477.22"
- process $proc$libresoc.v:161477$8883
+ attribute \src "libresoc.v:159278.7-159278.22"
+ process $proc$libresoc.v:159278$8797
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:161486.14-161486.47"
- process $proc$libresoc.v:161486$8884
+ attribute \src "libresoc.v:159287.14-159287.47"
+ process $proc$libresoc.v:159287$8798
assign { } { }
- assign $0\fast2$11[63:0]$8885 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast2$11[63:0]$8799 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast2$11 $0\fast2$11[63:0]$8885
+ update \fast2$11 $0\fast2$11[63:0]$8799
end
- attribute \src "libresoc.v:161493.7-161493.22"
- process $proc$libresoc.v:161493$8886
+ attribute \src "libresoc.v:159294.7-159294.22"
+ process $proc$libresoc.v:159294$8800
assign { } { }
assign $1\fast2_ok[0:0] 1'0
sync always
sync init
update \fast2_ok $1\fast2_ok[0:0]
end
- attribute \src "libresoc.v:161732.13-161732.29"
- process $proc$libresoc.v:161732$8887
+ attribute \src "libresoc.v:159533.13-159533.29"
+ process $proc$libresoc.v:159533$8801
assign { } { }
- assign $0\muxid$1[1:0]$8888 2'00
+ assign $0\muxid$1[1:0]$8802 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8888
+ update \muxid$1 $0\muxid$1[1:0]$8802
end
- attribute \src "libresoc.v:161745.14-161745.40"
- process $proc$libresoc.v:161745$8889
+ attribute \src "libresoc.v:159546.14-159546.40"
+ process $proc$libresoc.v:159546$8803
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:161752.7-161752.20"
- process $proc$libresoc.v:161752$8890
+ attribute \src "libresoc.v:159553.7-159553.20"
+ process $proc$libresoc.v:159553$8804
assign { } { }
assign $1\nia_ok[0:0] 1'0
sync always
sync init
update \nia_ok $1\nia_ok[0:0]
end
- attribute \src "libresoc.v:161766.7-161766.20"
- process $proc$libresoc.v:161766$8891
+ attribute \src "libresoc.v:159567.7-159567.20"
+ process $proc$libresoc.v:159567$8805
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:161770.3-161771.23"
- process $proc$libresoc.v:161770$8793
+ attribute \src "libresoc.v:159571.3-159572.23"
+ process $proc$libresoc.v:159571$8707
assign { } { }
assign $0\nia[63:0] \nia$next
sync posedge \coresync_clk
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:161772.3-161773.29"
- process $proc$libresoc.v:161772$8794
+ attribute \src "libresoc.v:159573.3-159574.29"
+ process $proc$libresoc.v:159573$8708
assign { } { }
assign $0\nia_ok[0:0] \nia_ok$next
sync posedge \coresync_clk
update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:161774.3-161775.35"
- process $proc$libresoc.v:161774$8795
+ attribute \src "libresoc.v:159575.3-159576.35"
+ process $proc$libresoc.v:159575$8709
assign { } { }
- assign $0\fast2$11[63:0]$8796 \fast2$11$next
+ assign $0\fast2$11[63:0]$8710 \fast2$11$next
sync posedge \coresync_clk
- update \fast2$11 $0\fast2$11[63:0]$8796
+ update \fast2$11 $0\fast2$11[63:0]$8710
end
- attribute \src "libresoc.v:161776.3-161777.33"
- process $proc$libresoc.v:161776$8797
+ attribute \src "libresoc.v:159577.3-159578.33"
+ process $proc$libresoc.v:159577$8711
assign { } { }
assign $0\fast2_ok[0:0] \fast2_ok$next
sync posedge \coresync_clk
update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:161778.3-161779.35"
- process $proc$libresoc.v:161778$8798
+ attribute \src "libresoc.v:159579.3-159580.35"
+ process $proc$libresoc.v:159579$8712
assign { } { }
- assign $0\fast1$10[63:0]$8799 \fast1$10$next
+ assign $0\fast1$10[63:0]$8713 \fast1$10$next
sync posedge \coresync_clk
- update \fast1$10 $0\fast1$10[63:0]$8799
+ update \fast1$10 $0\fast1$10[63:0]$8713
end
- attribute \src "libresoc.v:161780.3-161781.33"
- process $proc$libresoc.v:161780$8800
+ attribute \src "libresoc.v:159581.3-159582.33"
+ process $proc$libresoc.v:159581$8714
assign { } { }
assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:161782.3-161783.43"
- process $proc$libresoc.v:161782$8801
+ attribute \src "libresoc.v:159583.3-159584.43"
+ process $proc$libresoc.v:159583$8715
assign { } { }
- assign $0\br_op__cia$2[63:0]$8802 \br_op__cia$2$next
+ assign $0\br_op__cia$2[63:0]$8716 \br_op__cia$2$next
sync posedge \coresync_clk
- update \br_op__cia$2 $0\br_op__cia$2[63:0]$8802
+ update \br_op__cia$2 $0\br_op__cia$2[63:0]$8716
end
- attribute \src "libresoc.v:161784.3-161785.55"
- process $proc$libresoc.v:161784$8803
+ attribute \src "libresoc.v:159585.3-159586.55"
+ process $proc$libresoc.v:159585$8717
assign { } { }
- assign $0\br_op__insn_type$3[6:0]$8804 \br_op__insn_type$3$next
+ assign $0\br_op__insn_type$3[6:0]$8718 \br_op__insn_type$3$next
sync posedge \coresync_clk
- update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8804
+ update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8718
end
- attribute \src "libresoc.v:161786.3-161787.51"
- process $proc$libresoc.v:161786$8805
+ attribute \src "libresoc.v:159587.3-159588.51"
+ process $proc$libresoc.v:159587$8719
assign { } { }
- assign $0\br_op__fn_unit$4[12:0]$8806 \br_op__fn_unit$4$next
+ assign $0\br_op__fn_unit$4[12:0]$8720 \br_op__fn_unit$4$next
sync posedge \coresync_clk
- update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8806
+ update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8720
end
- attribute \src "libresoc.v:161788.3-161789.45"
- process $proc$libresoc.v:161788$8807
+ attribute \src "libresoc.v:159589.3-159590.45"
+ process $proc$libresoc.v:159589$8721
assign { } { }
- assign $0\br_op__insn$5[31:0]$8808 \br_op__insn$5$next
+ assign $0\br_op__insn$5[31:0]$8722 \br_op__insn$5$next
sync posedge \coresync_clk
- update \br_op__insn$5 $0\br_op__insn$5[31:0]$8808
+ update \br_op__insn$5 $0\br_op__insn$5[31:0]$8722
end
- attribute \src "libresoc.v:161790.3-161791.65"
- process $proc$libresoc.v:161790$8809
+ attribute \src "libresoc.v:159591.3-159592.65"
+ process $proc$libresoc.v:159591$8723
assign { } { }
- assign $0\br_op__imm_data__data$6[63:0]$8810 \br_op__imm_data__data$6$next
+ assign $0\br_op__imm_data__data$6[63:0]$8724 \br_op__imm_data__data$6$next
sync posedge \coresync_clk
- update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8810
+ update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8724
end
- attribute \src "libresoc.v:161792.3-161793.61"
- process $proc$libresoc.v:161792$8811
+ attribute \src "libresoc.v:159593.3-159594.61"
+ process $proc$libresoc.v:159593$8725
assign { } { }
- assign $0\br_op__imm_data__ok$7[0:0]$8812 \br_op__imm_data__ok$7$next
+ assign $0\br_op__imm_data__ok$7[0:0]$8726 \br_op__imm_data__ok$7$next
sync posedge \coresync_clk
- update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8812
+ update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8726
end
- attribute \src "libresoc.v:161794.3-161795.41"
- process $proc$libresoc.v:161794$8813
+ attribute \src "libresoc.v:159595.3-159596.41"
+ process $proc$libresoc.v:159595$8727
assign { } { }
- assign $0\br_op__lk$8[0:0]$8814 \br_op__lk$8$next
+ assign $0\br_op__lk$8[0:0]$8728 \br_op__lk$8$next
sync posedge \coresync_clk
- update \br_op__lk$8 $0\br_op__lk$8[0:0]$8814
+ update \br_op__lk$8 $0\br_op__lk$8[0:0]$8728
end
- attribute \src "libresoc.v:161796.3-161797.53"
- process $proc$libresoc.v:161796$8815
+ attribute \src "libresoc.v:159597.3-159598.53"
+ process $proc$libresoc.v:159597$8729
assign { } { }
- assign $0\br_op__is_32bit$9[0:0]$8816 \br_op__is_32bit$9$next
+ assign $0\br_op__is_32bit$9[0:0]$8730 \br_op__is_32bit$9$next
sync posedge \coresync_clk
- update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8816
+ update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8730
end
- attribute \src "libresoc.v:161798.3-161799.33"
- process $proc$libresoc.v:161798$8817
+ attribute \src "libresoc.v:159599.3-159600.33"
+ process $proc$libresoc.v:159599$8731
assign { } { }
- assign $0\muxid$1[1:0]$8818 \muxid$1$next
+ assign $0\muxid$1[1:0]$8732 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8818
+ update \muxid$1 $0\muxid$1[1:0]$8732
end
- attribute \src "libresoc.v:161800.3-161801.29"
- process $proc$libresoc.v:161800$8819
+ attribute \src "libresoc.v:159601.3-159602.29"
+ process $proc$libresoc.v:159601$8733
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:161839.3-161856.6"
- process $proc$libresoc.v:161839$8820
+ attribute \src "libresoc.v:159640.3-159657.6"
+ process $proc$libresoc.v:159640$8734
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8821 $2\r_busy$next[0:0]$8823
- attribute \src "libresoc.v:161840.5-161840.29"
+ assign $0\r_busy$next[0:0]$8735 $2\r_busy$next[0:0]$8737
+ attribute \src "libresoc.v:159641.5-159641.29"
switch \initial
- attribute \src "libresoc.v:161840.9-161840.17"
+ attribute \src "libresoc.v:159641.9-159641.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8822 1'1
+ assign $1\r_busy$next[0:0]$8736 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8822 1'0
+ assign $1\r_busy$next[0:0]$8736 1'0
case
- assign $1\r_busy$next[0:0]$8822 \r_busy
+ assign $1\r_busy$next[0:0]$8736 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8823 1'0
+ assign $2\r_busy$next[0:0]$8737 1'0
case
- assign $2\r_busy$next[0:0]$8823 $1\r_busy$next[0:0]$8822
+ assign $2\r_busy$next[0:0]$8737 $1\r_busy$next[0:0]$8736
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8821
+ update \r_busy$next $0\r_busy$next[0:0]$8735
end
- attribute \src "libresoc.v:161857.3-161869.6"
- process $proc$libresoc.v:161857$8824
+ attribute \src "libresoc.v:159658.3-159670.6"
+ process $proc$libresoc.v:159658$8738
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8825 $1\muxid$1$next[1:0]$8826
- attribute \src "libresoc.v:161858.5-161858.29"
+ assign $0\muxid$1$next[1:0]$8739 $1\muxid$1$next[1:0]$8740
+ attribute \src "libresoc.v:159659.5-159659.29"
switch \initial
- attribute \src "libresoc.v:161858.9-161858.17"
+ attribute \src "libresoc.v:159659.9-159659.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8826 \muxid$26
+ assign $1\muxid$1$next[1:0]$8740 \muxid$26
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8826 \muxid$26
+ assign $1\muxid$1$next[1:0]$8740 \muxid$26
case
- assign $1\muxid$1$next[1:0]$8826 \muxid$1
+ assign $1\muxid$1$next[1:0]$8740 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8825
+ update \muxid$1$next $0\muxid$1$next[1:0]$8739
end
- attribute \src "libresoc.v:161870.3-161897.6"
- process $proc$libresoc.v:161870$8827
+ attribute \src "libresoc.v:159671.3-159698.6"
+ process $proc$libresoc.v:159671$8741
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\br_op__cia$2$next[63:0]$8828 $1\br_op__cia$2$next[63:0]$8836
- assign $0\br_op__fn_unit$4$next[12:0]$8829 $1\br_op__fn_unit$4$next[12:0]$8837
+ assign $0\br_op__cia$2$next[63:0]$8742 $1\br_op__cia$2$next[63:0]$8750
+ assign $0\br_op__fn_unit$4$next[12:0]$8743 $1\br_op__fn_unit$4$next[12:0]$8751
assign { } { }
assign { } { }
- assign $0\br_op__insn$5$next[31:0]$8832 $1\br_op__insn$5$next[31:0]$8840
- assign $0\br_op__insn_type$3$next[6:0]$8833 $1\br_op__insn_type$3$next[6:0]$8841
- assign $0\br_op__is_32bit$9$next[0:0]$8834 $1\br_op__is_32bit$9$next[0:0]$8842
- assign $0\br_op__lk$8$next[0:0]$8835 $1\br_op__lk$8$next[0:0]$8843
- assign $0\br_op__imm_data__data$6$next[63:0]$8830 $2\br_op__imm_data__data$6$next[63:0]$8844
- assign $0\br_op__imm_data__ok$7$next[0:0]$8831 $2\br_op__imm_data__ok$7$next[0:0]$8845
- attribute \src "libresoc.v:161871.5-161871.29"
+ assign $0\br_op__insn$5$next[31:0]$8746 $1\br_op__insn$5$next[31:0]$8754
+ assign $0\br_op__insn_type$3$next[6:0]$8747 $1\br_op__insn_type$3$next[6:0]$8755
+ assign $0\br_op__is_32bit$9$next[0:0]$8748 $1\br_op__is_32bit$9$next[0:0]$8756
+ assign $0\br_op__lk$8$next[0:0]$8749 $1\br_op__lk$8$next[0:0]$8757
+ assign $0\br_op__imm_data__data$6$next[63:0]$8744 $2\br_op__imm_data__data$6$next[63:0]$8758
+ assign $0\br_op__imm_data__ok$7$next[0:0]$8745 $2\br_op__imm_data__ok$7$next[0:0]$8759
+ attribute \src "libresoc.v:159672.5-159672.29"
switch \initial
- attribute \src "libresoc.v:161871.9-161871.17"
+ attribute \src "libresoc.v:159672.9-159672.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\br_op__is_32bit$9$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8843 $1\br_op__imm_data__ok$7$next[0:0]$8839 $1\br_op__imm_data__data$6$next[63:0]$8838 $1\br_op__insn$5$next[31:0]$8840 $1\br_op__fn_unit$4$next[12:0]$8837 $1\br_op__insn_type$3$next[6:0]$8841 $1\br_op__cia$2$next[63:0]$8836 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
+ assign { $1\br_op__is_32bit$9$next[0:0]$8756 $1\br_op__lk$8$next[0:0]$8757 $1\br_op__imm_data__ok$7$next[0:0]$8753 $1\br_op__imm_data__data$6$next[63:0]$8752 $1\br_op__insn$5$next[31:0]$8754 $1\br_op__fn_unit$4$next[12:0]$8751 $1\br_op__insn_type$3$next[6:0]$8755 $1\br_op__cia$2$next[63:0]$8750 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\br_op__is_32bit$9$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8843 $1\br_op__imm_data__ok$7$next[0:0]$8839 $1\br_op__imm_data__data$6$next[63:0]$8838 $1\br_op__insn$5$next[31:0]$8840 $1\br_op__fn_unit$4$next[12:0]$8837 $1\br_op__insn_type$3$next[6:0]$8841 $1\br_op__cia$2$next[63:0]$8836 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
+ assign { $1\br_op__is_32bit$9$next[0:0]$8756 $1\br_op__lk$8$next[0:0]$8757 $1\br_op__imm_data__ok$7$next[0:0]$8753 $1\br_op__imm_data__data$6$next[63:0]$8752 $1\br_op__insn$5$next[31:0]$8754 $1\br_op__fn_unit$4$next[12:0]$8751 $1\br_op__insn_type$3$next[6:0]$8755 $1\br_op__cia$2$next[63:0]$8750 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
case
- assign $1\br_op__cia$2$next[63:0]$8836 \br_op__cia$2
- assign $1\br_op__fn_unit$4$next[12:0]$8837 \br_op__fn_unit$4
- assign $1\br_op__imm_data__data$6$next[63:0]$8838 \br_op__imm_data__data$6
- assign $1\br_op__imm_data__ok$7$next[0:0]$8839 \br_op__imm_data__ok$7
- assign $1\br_op__insn$5$next[31:0]$8840 \br_op__insn$5
- assign $1\br_op__insn_type$3$next[6:0]$8841 \br_op__insn_type$3
- assign $1\br_op__is_32bit$9$next[0:0]$8842 \br_op__is_32bit$9
- assign $1\br_op__lk$8$next[0:0]$8843 \br_op__lk$8
+ assign $1\br_op__cia$2$next[63:0]$8750 \br_op__cia$2
+ assign $1\br_op__fn_unit$4$next[12:0]$8751 \br_op__fn_unit$4
+ assign $1\br_op__imm_data__data$6$next[63:0]$8752 \br_op__imm_data__data$6
+ assign $1\br_op__imm_data__ok$7$next[0:0]$8753 \br_op__imm_data__ok$7
+ assign $1\br_op__insn$5$next[31:0]$8754 \br_op__insn$5
+ assign $1\br_op__insn_type$3$next[6:0]$8755 \br_op__insn_type$3
+ assign $1\br_op__is_32bit$9$next[0:0]$8756 \br_op__is_32bit$9
+ assign $1\br_op__lk$8$next[0:0]$8757 \br_op__lk$8
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
case 1'1
assign { } { }
assign { } { }
- assign $2\br_op__imm_data__data$6$next[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\br_op__imm_data__ok$7$next[0:0]$8845 1'0
+ assign $2\br_op__imm_data__data$6$next[63:0]$8758 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\br_op__imm_data__ok$7$next[0:0]$8759 1'0
case
- assign $2\br_op__imm_data__data$6$next[63:0]$8844 $1\br_op__imm_data__data$6$next[63:0]$8838
- assign $2\br_op__imm_data__ok$7$next[0:0]$8845 $1\br_op__imm_data__ok$7$next[0:0]$8839
+ assign $2\br_op__imm_data__data$6$next[63:0]$8758 $1\br_op__imm_data__data$6$next[63:0]$8752
+ assign $2\br_op__imm_data__ok$7$next[0:0]$8759 $1\br_op__imm_data__ok$7$next[0:0]$8753
end
sync always
- update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8828
- update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8829
- update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8830
- update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8831
- update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8832
- update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8833
- update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8834
- update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8835
+ update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8742
+ update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8743
+ update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8744
+ update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8745
+ update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8746
+ update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8747
+ update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8748
+ update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8749
end
- attribute \src "libresoc.v:161898.3-161916.6"
- process $proc$libresoc.v:161898$8846
+ attribute \src "libresoc.v:159699.3-159717.6"
+ process $proc$libresoc.v:159699$8760
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$10$next[63:0]$8847 $1\fast1$10$next[63:0]$8849
+ assign $0\fast1$10$next[63:0]$8761 $1\fast1$10$next[63:0]$8763
assign { } { }
- assign $0\fast1_ok$next[0:0]$8848 $2\fast1_ok$next[0:0]$8851
- attribute \src "libresoc.v:161899.5-161899.29"
+ assign $0\fast1_ok$next[0:0]$8762 $2\fast1_ok$next[0:0]$8765
+ attribute \src "libresoc.v:159700.5-159700.29"
switch \initial
- attribute \src "libresoc.v:161899.9-161899.17"
+ attribute \src "libresoc.v:159700.9-159700.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8850 $1\fast1$10$next[63:0]$8849 } { \fast1_ok$36 \fast1$35 }
+ assign { $1\fast1_ok$next[0:0]$8764 $1\fast1$10$next[63:0]$8763 } { \fast1_ok$36 \fast1$35 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8850 $1\fast1$10$next[63:0]$8849 } { \fast1_ok$36 \fast1$35 }
+ assign { $1\fast1_ok$next[0:0]$8764 $1\fast1$10$next[63:0]$8763 } { \fast1_ok$36 \fast1$35 }
case
- assign $1\fast1$10$next[63:0]$8849 \fast1$10
- assign $1\fast1_ok$next[0:0]$8850 \fast1_ok
+ assign $1\fast1$10$next[63:0]$8763 \fast1$10
+ assign $1\fast1_ok$next[0:0]$8764 \fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$8851 1'0
+ assign $2\fast1_ok$next[0:0]$8765 1'0
case
- assign $2\fast1_ok$next[0:0]$8851 $1\fast1_ok$next[0:0]$8850
+ assign $2\fast1_ok$next[0:0]$8765 $1\fast1_ok$next[0:0]$8764
end
sync always
- update \fast1$10$next $0\fast1$10$next[63:0]$8847
- update \fast1_ok$next $0\fast1_ok$next[0:0]$8848
+ update \fast1$10$next $0\fast1$10$next[63:0]$8761
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$8762
end
- attribute \src "libresoc.v:161917.3-161935.6"
- process $proc$libresoc.v:161917$8852
+ attribute \src "libresoc.v:159718.3-159736.6"
+ process $proc$libresoc.v:159718$8766
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast2$11$next[63:0]$8853 $1\fast2$11$next[63:0]$8855
+ assign $0\fast2$11$next[63:0]$8767 $1\fast2$11$next[63:0]$8769
assign { } { }
- assign $0\fast2_ok$next[0:0]$8854 $2\fast2_ok$next[0:0]$8857
- attribute \src "libresoc.v:161918.5-161918.29"
+ assign $0\fast2_ok$next[0:0]$8768 $2\fast2_ok$next[0:0]$8771
+ attribute \src "libresoc.v:159719.5-159719.29"
switch \initial
- attribute \src "libresoc.v:161918.9-161918.17"
+ attribute \src "libresoc.v:159719.9-159719.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$8856 $1\fast2$11$next[63:0]$8855 } { \fast2_ok$38 \fast2$37 }
+ assign { $1\fast2_ok$next[0:0]$8770 $1\fast2$11$next[63:0]$8769 } { \fast2_ok$38 \fast2$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$8856 $1\fast2$11$next[63:0]$8855 } { \fast2_ok$38 \fast2$37 }
+ assign { $1\fast2_ok$next[0:0]$8770 $1\fast2$11$next[63:0]$8769 } { \fast2_ok$38 \fast2$37 }
case
- assign $1\fast2$11$next[63:0]$8855 \fast2$11
- assign $1\fast2_ok$next[0:0]$8856 \fast2_ok
+ assign $1\fast2$11$next[63:0]$8769 \fast2$11
+ assign $1\fast2_ok$next[0:0]$8770 \fast2_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast2_ok$next[0:0]$8857 1'0
+ assign $2\fast2_ok$next[0:0]$8771 1'0
case
- assign $2\fast2_ok$next[0:0]$8857 $1\fast2_ok$next[0:0]$8856
+ assign $2\fast2_ok$next[0:0]$8771 $1\fast2_ok$next[0:0]$8770
end
sync always
- update \fast2$11$next $0\fast2$11$next[63:0]$8853
- update \fast2_ok$next $0\fast2_ok$next[0:0]$8854
+ update \fast2$11$next $0\fast2$11$next[63:0]$8767
+ update \fast2_ok$next $0\fast2_ok$next[0:0]$8768
end
- attribute \src "libresoc.v:161936.3-161954.6"
- process $proc$libresoc.v:161936$8858
+ attribute \src "libresoc.v:159737.3-159755.6"
+ process $proc$libresoc.v:159737$8772
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$8859 $1\nia$next[63:0]$8861
+ assign $0\nia$next[63:0]$8773 $1\nia$next[63:0]$8775
assign { } { }
- assign $0\nia_ok$next[0:0]$8860 $2\nia_ok$next[0:0]$8863
- attribute \src "libresoc.v:161937.5-161937.29"
+ assign $0\nia_ok$next[0:0]$8774 $2\nia_ok$next[0:0]$8777
+ attribute \src "libresoc.v:159738.5-159738.29"
switch \initial
- attribute \src "libresoc.v:161937.9-161937.17"
+ attribute \src "libresoc.v:159738.9-159738.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$8862 $1\nia$next[63:0]$8861 } { \nia_ok$40 \nia$39 }
+ assign { $1\nia_ok$next[0:0]$8776 $1\nia$next[63:0]$8775 } { \nia_ok$40 \nia$39 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$8862 $1\nia$next[63:0]$8861 } { \nia_ok$40 \nia$39 }
+ assign { $1\nia_ok$next[0:0]$8776 $1\nia$next[63:0]$8775 } { \nia_ok$40 \nia$39 }
case
- assign $1\nia$next[63:0]$8861 \nia
- assign $1\nia_ok$next[0:0]$8862 \nia_ok
+ assign $1\nia$next[63:0]$8775 \nia
+ assign $1\nia_ok$next[0:0]$8776 \nia_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\nia_ok$next[0:0]$8863 1'0
+ assign $2\nia_ok$next[0:0]$8777 1'0
case
- assign $2\nia_ok$next[0:0]$8863 $1\nia_ok$next[0:0]$8862
+ assign $2\nia_ok$next[0:0]$8777 $1\nia_ok$next[0:0]$8776
end
sync always
- update \nia$next $0\nia$next[63:0]$8859
- update \nia_ok$next $0\nia_ok$next[0:0]$8860
+ update \nia$next $0\nia$next[63:0]$8773
+ update \nia_ok$next $0\nia_ok$next[0:0]$8774
end
- connect \$24 $and$libresoc.v:161769$8792_Y
+ connect \$24 $and$libresoc.v:159570$8706_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia }
connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:161974.1-162894.10"
+attribute \src "libresoc.v:159775.1-160695.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe"
attribute \generator "nMigen"
module \pipe$64
- attribute \src "libresoc.v:162797.3-162815.6"
- wire width 64 $0\fast1$7$next[63:0]$8951
- attribute \src "libresoc.v:162650.3-162651.33"
- wire width 64 $0\fast1$7[63:0]$8903
- attribute \src "libresoc.v:161988.14-161988.46"
- wire width 64 $0\fast1$7[63:0]$8975
- attribute \src "libresoc.v:162797.3-162815.6"
- wire $0\fast1_ok$next[0:0]$8950
- attribute \src "libresoc.v:162652.3-162653.33"
+ attribute \src "libresoc.v:160598.3-160616.6"
+ wire width 64 $0\fast1$7$next[63:0]$8865
+ attribute \src "libresoc.v:160451.3-160452.33"
+ wire width 64 $0\fast1$7[63:0]$8817
+ attribute \src "libresoc.v:159789.14-159789.46"
+ wire width 64 $0\fast1$7[63:0]$8889
+ attribute \src "libresoc.v:160598.3-160616.6"
+ wire $0\fast1_ok$next[0:0]$8864
+ attribute \src "libresoc.v:160453.3-160454.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:161975.7-161975.20"
+ attribute \src "libresoc.v:159776.7-159776.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:162730.3-162742.6"
- wire width 2 $0\muxid$1$next[1:0]$8926
- attribute \src "libresoc.v:162670.3-162671.33"
- wire width 2 $0\muxid$1[1:0]$8919
- attribute \src "libresoc.v:162002.13-162002.29"
- wire width 2 $0\muxid$1[1:0]$8978
- attribute \src "libresoc.v:162759.3-162777.6"
- wire width 64 $0\o$next[63:0]$8938
- attribute \src "libresoc.v:162658.3-162659.19"
+ attribute \src "libresoc.v:160531.3-160543.6"
+ wire width 2 $0\muxid$1$next[1:0]$8840
+ attribute \src "libresoc.v:160471.3-160472.33"
+ wire width 2 $0\muxid$1[1:0]$8833
+ attribute \src "libresoc.v:159803.13-159803.29"
+ wire width 2 $0\muxid$1[1:0]$8892
+ attribute \src "libresoc.v:160560.3-160578.6"
+ wire width 64 $0\o$next[63:0]$8852
+ attribute \src "libresoc.v:160459.3-160460.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:162759.3-162777.6"
- wire $0\o_ok$next[0:0]$8939
- attribute \src "libresoc.v:162660.3-162661.25"
+ attribute \src "libresoc.v:160560.3-160578.6"
+ wire $0\o_ok$next[0:0]$8853
+ attribute \src "libresoc.v:160461.3-160462.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:162712.3-162729.6"
- wire $0\r_busy$next[0:0]$8922
- attribute \src "libresoc.v:162672.3-162673.29"
+ attribute \src "libresoc.v:160513.3-160530.6"
+ wire $0\r_busy$next[0:0]$8836
+ attribute \src "libresoc.v:160473.3-160474.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:162778.3-162796.6"
- wire width 64 $0\spr1$6$next[63:0]$8944
- attribute \src "libresoc.v:162654.3-162655.31"
- wire width 64 $0\spr1$6[63:0]$8906
- attribute \src "libresoc.v:162047.14-162047.45"
- wire width 64 $0\spr1$6[63:0]$8983
- attribute \src "libresoc.v:162778.3-162796.6"
- wire $0\spr1_ok$next[0:0]$8945
- attribute \src "libresoc.v:162656.3-162657.31"
+ attribute \src "libresoc.v:160579.3-160597.6"
+ wire width 64 $0\spr1$6$next[63:0]$8858
+ attribute \src "libresoc.v:160455.3-160456.31"
+ wire width 64 $0\spr1$6[63:0]$8820
+ attribute \src "libresoc.v:159848.14-159848.45"
+ wire width 64 $0\spr1$6[63:0]$8897
+ attribute \src "libresoc.v:160579.3-160597.6"
+ wire $0\spr1_ok$next[0:0]$8859
+ attribute \src "libresoc.v:160457.3-160458.31"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8929
- attribute \src "libresoc.v:162664.3-162665.53"
- wire width 13 $0\spr_op__fn_unit$3[12:0]$8913
- attribute \src "libresoc.v:162337.14-162337.44"
- wire width 13 $0\spr_op__fn_unit$3[12:0]$8986
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 32 $0\spr_op__insn$4$next[31:0]$8930
- attribute \src "libresoc.v:162666.3-162667.47"
- wire width 32 $0\spr_op__insn$4[31:0]$8915
- attribute \src "libresoc.v:162346.14-162346.38"
- wire width 32 $0\spr_op__insn$4[31:0]$8988
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 7 $0\spr_op__insn_type$2$next[6:0]$8931
- attribute \src "libresoc.v:162662.3-162663.57"
- wire width 7 $0\spr_op__insn_type$2[6:0]$8911
- attribute \src "libresoc.v:162501.13-162501.42"
- wire width 7 $0\spr_op__insn_type$2[6:0]$8990
- attribute \src "libresoc.v:162743.3-162758.6"
- wire $0\spr_op__is_32bit$5$next[0:0]$8932
- attribute \src "libresoc.v:162668.3-162669.55"
- wire $0\spr_op__is_32bit$5[0:0]$8917
- attribute \src "libresoc.v:162586.7-162586.34"
- wire $0\spr_op__is_32bit$5[0:0]$8992
- attribute \src "libresoc.v:162854.3-162872.6"
- wire width 2 $0\xer_ca$10$next[1:0]$8968
- attribute \src "libresoc.v:162638.3-162639.37"
- wire width 2 $0\xer_ca$10[1:0]$8894
- attribute \src "libresoc.v:162593.13-162593.31"
- wire width 2 $0\xer_ca$10[1:0]$8994
- attribute \src "libresoc.v:162854.3-162872.6"
- wire $0\xer_ca_ok$next[0:0]$8969
- attribute \src "libresoc.v:162640.3-162641.35"
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8843
+ attribute \src "libresoc.v:160465.3-160466.53"
+ wire width 13 $0\spr_op__fn_unit$3[12:0]$8827
+ attribute \src "libresoc.v:160138.14-160138.44"
+ wire width 13 $0\spr_op__fn_unit$3[12:0]$8900
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 32 $0\spr_op__insn$4$next[31:0]$8844
+ attribute \src "libresoc.v:160467.3-160468.47"
+ wire width 32 $0\spr_op__insn$4[31:0]$8829
+ attribute \src "libresoc.v:160147.14-160147.38"
+ wire width 32 $0\spr_op__insn$4[31:0]$8902
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 7 $0\spr_op__insn_type$2$next[6:0]$8845
+ attribute \src "libresoc.v:160463.3-160464.57"
+ wire width 7 $0\spr_op__insn_type$2[6:0]$8825
+ attribute \src "libresoc.v:160302.13-160302.42"
+ wire width 7 $0\spr_op__insn_type$2[6:0]$8904
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire $0\spr_op__is_32bit$5$next[0:0]$8846
+ attribute \src "libresoc.v:160469.3-160470.55"
+ wire $0\spr_op__is_32bit$5[0:0]$8831
+ attribute \src "libresoc.v:160387.7-160387.34"
+ wire $0\spr_op__is_32bit$5[0:0]$8906
+ attribute \src "libresoc.v:160655.3-160673.6"
+ wire width 2 $0\xer_ca$10$next[1:0]$8882
+ attribute \src "libresoc.v:160439.3-160440.37"
+ wire width 2 $0\xer_ca$10[1:0]$8808
+ attribute \src "libresoc.v:160394.13-160394.31"
+ wire width 2 $0\xer_ca$10[1:0]$8908
+ attribute \src "libresoc.v:160655.3-160673.6"
+ wire $0\xer_ca_ok$next[0:0]$8883
+ attribute \src "libresoc.v:160441.3-160442.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:162835.3-162853.6"
- wire width 2 $0\xer_ov$9$next[1:0]$8963
- attribute \src "libresoc.v:162642.3-162643.35"
- wire width 2 $0\xer_ov$9[1:0]$8897
- attribute \src "libresoc.v:162611.13-162611.30"
- wire width 2 $0\xer_ov$9[1:0]$8997
- attribute \src "libresoc.v:162835.3-162853.6"
- wire $0\xer_ov_ok$next[0:0]$8962
- attribute \src "libresoc.v:162644.3-162645.35"
+ attribute \src "libresoc.v:160636.3-160654.6"
+ wire width 2 $0\xer_ov$9$next[1:0]$8877
+ attribute \src "libresoc.v:160443.3-160444.35"
+ wire width 2 $0\xer_ov$9[1:0]$8811
+ attribute \src "libresoc.v:160412.13-160412.30"
+ wire width 2 $0\xer_ov$9[1:0]$8911
+ attribute \src "libresoc.v:160636.3-160654.6"
+ wire $0\xer_ov_ok$next[0:0]$8876
+ attribute \src "libresoc.v:160445.3-160446.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:162816.3-162834.6"
- wire $0\xer_so$8$next[0:0]$8957
- attribute \src "libresoc.v:162646.3-162647.35"
- wire $0\xer_so$8[0:0]$8900
- attribute \src "libresoc.v:162627.7-162627.24"
- wire $0\xer_so$8[0:0]$9000
- attribute \src "libresoc.v:162816.3-162834.6"
- wire $0\xer_so_ok$next[0:0]$8956
- attribute \src "libresoc.v:162648.3-162649.35"
+ attribute \src "libresoc.v:160617.3-160635.6"
+ wire $0\xer_so$8$next[0:0]$8871
+ attribute \src "libresoc.v:160447.3-160448.35"
+ wire $0\xer_so$8[0:0]$8814
+ attribute \src "libresoc.v:160428.7-160428.24"
+ wire $0\xer_so$8[0:0]$8914
+ attribute \src "libresoc.v:160617.3-160635.6"
+ wire $0\xer_so_ok$next[0:0]$8870
+ attribute \src "libresoc.v:160449.3-160450.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:162797.3-162815.6"
- wire width 64 $1\fast1$7$next[63:0]$8953
- attribute \src "libresoc.v:162797.3-162815.6"
- wire $1\fast1_ok$next[0:0]$8952
- attribute \src "libresoc.v:161993.7-161993.22"
+ attribute \src "libresoc.v:160598.3-160616.6"
+ wire width 64 $1\fast1$7$next[63:0]$8867
+ attribute \src "libresoc.v:160598.3-160616.6"
+ wire $1\fast1_ok$next[0:0]$8866
+ attribute \src "libresoc.v:159794.7-159794.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:162730.3-162742.6"
- wire width 2 $1\muxid$1$next[1:0]$8927
- attribute \src "libresoc.v:162759.3-162777.6"
- wire width 64 $1\o$next[63:0]$8940
- attribute \src "libresoc.v:162015.14-162015.38"
+ attribute \src "libresoc.v:160531.3-160543.6"
+ wire width 2 $1\muxid$1$next[1:0]$8841
+ attribute \src "libresoc.v:160560.3-160578.6"
+ wire width 64 $1\o$next[63:0]$8854
+ attribute \src "libresoc.v:159816.14-159816.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:162759.3-162777.6"
- wire $1\o_ok$next[0:0]$8941
- attribute \src "libresoc.v:162022.7-162022.18"
+ attribute \src "libresoc.v:160560.3-160578.6"
+ wire $1\o_ok$next[0:0]$8855
+ attribute \src "libresoc.v:159823.7-159823.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:162712.3-162729.6"
- wire $1\r_busy$next[0:0]$8923
- attribute \src "libresoc.v:162036.7-162036.20"
+ attribute \src "libresoc.v:160513.3-160530.6"
+ wire $1\r_busy$next[0:0]$8837
+ attribute \src "libresoc.v:159837.7-159837.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:162778.3-162796.6"
- wire width 64 $1\spr1$6$next[63:0]$8946
- attribute \src "libresoc.v:162778.3-162796.6"
- wire $1\spr1_ok$next[0:0]$8947
- attribute \src "libresoc.v:162052.7-162052.21"
+ attribute \src "libresoc.v:160579.3-160597.6"
+ wire width 64 $1\spr1$6$next[63:0]$8860
+ attribute \src "libresoc.v:160579.3-160597.6"
+ wire $1\spr1_ok$next[0:0]$8861
+ attribute \src "libresoc.v:159853.7-159853.21"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8933
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 32 $1\spr_op__insn$4$next[31:0]$8934
- attribute \src "libresoc.v:162743.3-162758.6"
- wire width 7 $1\spr_op__insn_type$2$next[6:0]$8935
- attribute \src "libresoc.v:162743.3-162758.6"
- wire $1\spr_op__is_32bit$5$next[0:0]$8936
- attribute \src "libresoc.v:162854.3-162872.6"
- wire width 2 $1\xer_ca$10$next[1:0]$8970
- attribute \src "libresoc.v:162854.3-162872.6"
- wire $1\xer_ca_ok$next[0:0]$8971
- attribute \src "libresoc.v:162600.7-162600.23"
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8847
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 32 $1\spr_op__insn$4$next[31:0]$8848
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire width 7 $1\spr_op__insn_type$2$next[6:0]$8849
+ attribute \src "libresoc.v:160544.3-160559.6"
+ wire $1\spr_op__is_32bit$5$next[0:0]$8850
+ attribute \src "libresoc.v:160655.3-160673.6"
+ wire width 2 $1\xer_ca$10$next[1:0]$8884
+ attribute \src "libresoc.v:160655.3-160673.6"
+ wire $1\xer_ca_ok$next[0:0]$8885
+ attribute \src "libresoc.v:160401.7-160401.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:162835.3-162853.6"
- wire width 2 $1\xer_ov$9$next[1:0]$8965
- attribute \src "libresoc.v:162835.3-162853.6"
- wire $1\xer_ov_ok$next[0:0]$8964
- attribute \src "libresoc.v:162616.7-162616.23"
+ attribute \src "libresoc.v:160636.3-160654.6"
+ wire width 2 $1\xer_ov$9$next[1:0]$8879
+ attribute \src "libresoc.v:160636.3-160654.6"
+ wire $1\xer_ov_ok$next[0:0]$8878
+ attribute \src "libresoc.v:160417.7-160417.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:162816.3-162834.6"
- wire $1\xer_so$8$next[0:0]$8959
- attribute \src "libresoc.v:162816.3-162834.6"
- wire $1\xer_so_ok$next[0:0]$8958
- attribute \src "libresoc.v:162632.7-162632.23"
+ attribute \src "libresoc.v:160617.3-160635.6"
+ wire $1\xer_so$8$next[0:0]$8873
+ attribute \src "libresoc.v:160617.3-160635.6"
+ wire $1\xer_so_ok$next[0:0]$8872
+ attribute \src "libresoc.v:160433.7-160433.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:162797.3-162815.6"
- wire $2\fast1_ok$next[0:0]$8954
- attribute \src "libresoc.v:162759.3-162777.6"
- wire $2\o_ok$next[0:0]$8942
- attribute \src "libresoc.v:162712.3-162729.6"
- wire $2\r_busy$next[0:0]$8924
- attribute \src "libresoc.v:162778.3-162796.6"
- wire $2\spr1_ok$next[0:0]$8948
- attribute \src "libresoc.v:162854.3-162872.6"
- wire $2\xer_ca_ok$next[0:0]$8972
- attribute \src "libresoc.v:162835.3-162853.6"
- wire $2\xer_ov_ok$next[0:0]$8966
- attribute \src "libresoc.v:162816.3-162834.6"
- wire $2\xer_so_ok$next[0:0]$8960
- attribute \src "libresoc.v:162637.18-162637.118"
- wire $and$libresoc.v:162637$8892_Y
+ attribute \src "libresoc.v:160598.3-160616.6"
+ wire $2\fast1_ok$next[0:0]$8868
+ attribute \src "libresoc.v:160560.3-160578.6"
+ wire $2\o_ok$next[0:0]$8856
+ attribute \src "libresoc.v:160513.3-160530.6"
+ wire $2\r_busy$next[0:0]$8838
+ attribute \src "libresoc.v:160579.3-160597.6"
+ wire $2\spr1_ok$next[0:0]$8862
+ attribute \src "libresoc.v:160655.3-160673.6"
+ wire $2\xer_ca_ok$next[0:0]$8886
+ attribute \src "libresoc.v:160636.3-160654.6"
+ wire $2\xer_ov_ok$next[0:0]$8880
+ attribute \src "libresoc.v:160617.3-160635.6"
+ wire $2\xer_so_ok$next[0:0]$8874
+ attribute \src "libresoc.v:160438.18-160438.118"
+ wire $and$libresoc.v:160438$8806_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 11 \fast1
wire \fast1_ok$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast1_ok$next
- attribute \src "libresoc.v:161975.7-161975.15"
+ attribute \src "libresoc.v:159776.7-159776.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:162637$8892
+ cell $and $and$libresoc.v:160438$8806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$21
connect \B \p_ready_o
- connect \Y $and$libresoc.v:162637$8892_Y
+ connect \Y $and$libresoc.v:160438$8806_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162674.10-162677.4"
+ attribute \src "libresoc.v:160475.10-160478.4"
cell \n$66 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162678.10-162681.4"
+ attribute \src "libresoc.v:160479.10-160482.4"
cell \p$65 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:162682.12-162711.4"
+ attribute \src "libresoc.v:160483.12-160512.4"
cell \spr_main \spr_main
connect \fast1 \spr_main_fast1
connect \fast1$7 \spr_main_fast1$17
connect \xer_so$8 \spr_main_xer_so$18
connect \xer_so_ok \spr_main_xer_so_ok
end
- attribute \src "libresoc.v:161975.7-161975.20"
- process $proc$libresoc.v:161975$8973
+ attribute \src "libresoc.v:159776.7-159776.20"
+ process $proc$libresoc.v:159776$8887
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:161988.14-161988.46"
- process $proc$libresoc.v:161988$8974
+ attribute \src "libresoc.v:159789.14-159789.46"
+ process $proc$libresoc.v:159789$8888
assign { } { }
- assign $0\fast1$7[63:0]$8975 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$7[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$7 $0\fast1$7[63:0]$8975
+ update \fast1$7 $0\fast1$7[63:0]$8889
end
- attribute \src "libresoc.v:161993.7-161993.22"
- process $proc$libresoc.v:161993$8976
+ attribute \src "libresoc.v:159794.7-159794.22"
+ process $proc$libresoc.v:159794$8890
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:162002.13-162002.29"
- process $proc$libresoc.v:162002$8977
+ attribute \src "libresoc.v:159803.13-159803.29"
+ process $proc$libresoc.v:159803$8891
assign { } { }
- assign $0\muxid$1[1:0]$8978 2'00
+ assign $0\muxid$1[1:0]$8892 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$8978
+ update \muxid$1 $0\muxid$1[1:0]$8892
end
- attribute \src "libresoc.v:162015.14-162015.38"
- process $proc$libresoc.v:162015$8979
+ attribute \src "libresoc.v:159816.14-159816.38"
+ process $proc$libresoc.v:159816$8893
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:162022.7-162022.18"
- process $proc$libresoc.v:162022$8980
+ attribute \src "libresoc.v:159823.7-159823.18"
+ process $proc$libresoc.v:159823$8894
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:162036.7-162036.20"
- process $proc$libresoc.v:162036$8981
+ attribute \src "libresoc.v:159837.7-159837.20"
+ process $proc$libresoc.v:159837$8895
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:162047.14-162047.45"
- process $proc$libresoc.v:162047$8982
+ attribute \src "libresoc.v:159848.14-159848.45"
+ process $proc$libresoc.v:159848$8896
assign { } { }
- assign $0\spr1$6[63:0]$8983 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\spr1$6[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \spr1$6 $0\spr1$6[63:0]$8983
+ update \spr1$6 $0\spr1$6[63:0]$8897
end
- attribute \src "libresoc.v:162052.7-162052.21"
- process $proc$libresoc.v:162052$8984
+ attribute \src "libresoc.v:159853.7-159853.21"
+ process $proc$libresoc.v:159853$8898
assign { } { }
assign $1\spr1_ok[0:0] 1'0
sync always
sync init
update \spr1_ok $1\spr1_ok[0:0]
end
- attribute \src "libresoc.v:162337.14-162337.44"
- process $proc$libresoc.v:162337$8985
+ attribute \src "libresoc.v:160138.14-160138.44"
+ process $proc$libresoc.v:160138$8899
assign { } { }
- assign $0\spr_op__fn_unit$3[12:0]$8986 13'0000000000000
+ assign $0\spr_op__fn_unit$3[12:0]$8900 13'0000000000000
sync always
sync init
- update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8986
+ update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8900
end
- attribute \src "libresoc.v:162346.14-162346.38"
- process $proc$libresoc.v:162346$8987
+ attribute \src "libresoc.v:160147.14-160147.38"
+ process $proc$libresoc.v:160147$8901
assign { } { }
- assign $0\spr_op__insn$4[31:0]$8988 0
+ assign $0\spr_op__insn$4[31:0]$8902 0
sync always
sync init
- update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8988
+ update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8902
end
- attribute \src "libresoc.v:162501.13-162501.42"
- process $proc$libresoc.v:162501$8989
+ attribute \src "libresoc.v:160302.13-160302.42"
+ process $proc$libresoc.v:160302$8903
assign { } { }
- assign $0\spr_op__insn_type$2[6:0]$8990 7'0000000
+ assign $0\spr_op__insn_type$2[6:0]$8904 7'0000000
sync always
sync init
- update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8990
+ update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8904
end
- attribute \src "libresoc.v:162586.7-162586.34"
- process $proc$libresoc.v:162586$8991
+ attribute \src "libresoc.v:160387.7-160387.34"
+ process $proc$libresoc.v:160387$8905
assign { } { }
- assign $0\spr_op__is_32bit$5[0:0]$8992 1'0
+ assign $0\spr_op__is_32bit$5[0:0]$8906 1'0
sync always
sync init
- update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8992
+ update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8906
end
- attribute \src "libresoc.v:162593.13-162593.31"
- process $proc$libresoc.v:162593$8993
+ attribute \src "libresoc.v:160394.13-160394.31"
+ process $proc$libresoc.v:160394$8907
assign { } { }
- assign $0\xer_ca$10[1:0]$8994 2'00
+ assign $0\xer_ca$10[1:0]$8908 2'00
sync always
sync init
- update \xer_ca$10 $0\xer_ca$10[1:0]$8994
+ update \xer_ca$10 $0\xer_ca$10[1:0]$8908
end
- attribute \src "libresoc.v:162600.7-162600.23"
- process $proc$libresoc.v:162600$8995
+ attribute \src "libresoc.v:160401.7-160401.23"
+ process $proc$libresoc.v:160401$8909
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:162611.13-162611.30"
- process $proc$libresoc.v:162611$8996
+ attribute \src "libresoc.v:160412.13-160412.30"
+ process $proc$libresoc.v:160412$8910
assign { } { }
- assign $0\xer_ov$9[1:0]$8997 2'00
+ assign $0\xer_ov$9[1:0]$8911 2'00
sync always
sync init
- update \xer_ov$9 $0\xer_ov$9[1:0]$8997
+ update \xer_ov$9 $0\xer_ov$9[1:0]$8911
end
- attribute \src "libresoc.v:162616.7-162616.23"
- process $proc$libresoc.v:162616$8998
+ attribute \src "libresoc.v:160417.7-160417.23"
+ process $proc$libresoc.v:160417$8912
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:162627.7-162627.24"
- process $proc$libresoc.v:162627$8999
+ attribute \src "libresoc.v:160428.7-160428.24"
+ process $proc$libresoc.v:160428$8913
assign { } { }
- assign $0\xer_so$8[0:0]$9000 1'0
+ assign $0\xer_so$8[0:0]$8914 1'0
sync always
sync init
- update \xer_so$8 $0\xer_so$8[0:0]$9000
+ update \xer_so$8 $0\xer_so$8[0:0]$8914
end
- attribute \src "libresoc.v:162632.7-162632.23"
- process $proc$libresoc.v:162632$9001
+ attribute \src "libresoc.v:160433.7-160433.23"
+ process $proc$libresoc.v:160433$8915
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:162638.3-162639.37"
- process $proc$libresoc.v:162638$8893
+ attribute \src "libresoc.v:160439.3-160440.37"
+ process $proc$libresoc.v:160439$8807
assign { } { }
- assign $0\xer_ca$10[1:0]$8894 \xer_ca$10$next
+ assign $0\xer_ca$10[1:0]$8808 \xer_ca$10$next
sync posedge \coresync_clk
- update \xer_ca$10 $0\xer_ca$10[1:0]$8894
+ update \xer_ca$10 $0\xer_ca$10[1:0]$8808
end
- attribute \src "libresoc.v:162640.3-162641.35"
- process $proc$libresoc.v:162640$8895
+ attribute \src "libresoc.v:160441.3-160442.35"
+ process $proc$libresoc.v:160441$8809
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:162642.3-162643.35"
- process $proc$libresoc.v:162642$8896
+ attribute \src "libresoc.v:160443.3-160444.35"
+ process $proc$libresoc.v:160443$8810
assign { } { }
- assign $0\xer_ov$9[1:0]$8897 \xer_ov$9$next
+ assign $0\xer_ov$9[1:0]$8811 \xer_ov$9$next
sync posedge \coresync_clk
- update \xer_ov$9 $0\xer_ov$9[1:0]$8897
+ update \xer_ov$9 $0\xer_ov$9[1:0]$8811
end
- attribute \src "libresoc.v:162644.3-162645.35"
- process $proc$libresoc.v:162644$8898
+ attribute \src "libresoc.v:160445.3-160446.35"
+ process $proc$libresoc.v:160445$8812
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:162646.3-162647.35"
- process $proc$libresoc.v:162646$8899
+ attribute \src "libresoc.v:160447.3-160448.35"
+ process $proc$libresoc.v:160447$8813
assign { } { }
- assign $0\xer_so$8[0:0]$8900 \xer_so$8$next
+ assign $0\xer_so$8[0:0]$8814 \xer_so$8$next
sync posedge \coresync_clk
- update \xer_so$8 $0\xer_so$8[0:0]$8900
+ update \xer_so$8 $0\xer_so$8[0:0]$8814
end
- attribute \src "libresoc.v:162648.3-162649.35"
- process $proc$libresoc.v:162648$8901
+ attribute \src "libresoc.v:160449.3-160450.35"
+ process $proc$libresoc.v:160449$8815
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:162650.3-162651.33"
- process $proc$libresoc.v:162650$8902
+ attribute \src "libresoc.v:160451.3-160452.33"
+ process $proc$libresoc.v:160451$8816
assign { } { }
- assign $0\fast1$7[63:0]$8903 \fast1$7$next
+ assign $0\fast1$7[63:0]$8817 \fast1$7$next
sync posedge \coresync_clk
- update \fast1$7 $0\fast1$7[63:0]$8903
+ update \fast1$7 $0\fast1$7[63:0]$8817
end
- attribute \src "libresoc.v:162652.3-162653.33"
- process $proc$libresoc.v:162652$8904
+ attribute \src "libresoc.v:160453.3-160454.33"
+ process $proc$libresoc.v:160453$8818
assign { } { }
assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:162654.3-162655.31"
- process $proc$libresoc.v:162654$8905
+ attribute \src "libresoc.v:160455.3-160456.31"
+ process $proc$libresoc.v:160455$8819
assign { } { }
- assign $0\spr1$6[63:0]$8906 \spr1$6$next
+ assign $0\spr1$6[63:0]$8820 \spr1$6$next
sync posedge \coresync_clk
- update \spr1$6 $0\spr1$6[63:0]$8906
+ update \spr1$6 $0\spr1$6[63:0]$8820
end
- attribute \src "libresoc.v:162656.3-162657.31"
- process $proc$libresoc.v:162656$8907
+ attribute \src "libresoc.v:160457.3-160458.31"
+ process $proc$libresoc.v:160457$8821
assign { } { }
assign $0\spr1_ok[0:0] \spr1_ok$next
sync posedge \coresync_clk
update \spr1_ok $0\spr1_ok[0:0]
end
- attribute \src "libresoc.v:162658.3-162659.19"
- process $proc$libresoc.v:162658$8908
+ attribute \src "libresoc.v:160459.3-160460.19"
+ process $proc$libresoc.v:160459$8822
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:162660.3-162661.25"
- process $proc$libresoc.v:162660$8909
+ attribute \src "libresoc.v:160461.3-160462.25"
+ process $proc$libresoc.v:160461$8823
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:162662.3-162663.57"
- process $proc$libresoc.v:162662$8910
+ attribute \src "libresoc.v:160463.3-160464.57"
+ process $proc$libresoc.v:160463$8824
assign { } { }
- assign $0\spr_op__insn_type$2[6:0]$8911 \spr_op__insn_type$2$next
+ assign $0\spr_op__insn_type$2[6:0]$8825 \spr_op__insn_type$2$next
sync posedge \coresync_clk
- update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8911
+ update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8825
end
- attribute \src "libresoc.v:162664.3-162665.53"
- process $proc$libresoc.v:162664$8912
+ attribute \src "libresoc.v:160465.3-160466.53"
+ process $proc$libresoc.v:160465$8826
assign { } { }
- assign $0\spr_op__fn_unit$3[12:0]$8913 \spr_op__fn_unit$3$next
+ assign $0\spr_op__fn_unit$3[12:0]$8827 \spr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8913
+ update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8827
end
- attribute \src "libresoc.v:162666.3-162667.47"
- process $proc$libresoc.v:162666$8914
+ attribute \src "libresoc.v:160467.3-160468.47"
+ process $proc$libresoc.v:160467$8828
assign { } { }
- assign $0\spr_op__insn$4[31:0]$8915 \spr_op__insn$4$next
+ assign $0\spr_op__insn$4[31:0]$8829 \spr_op__insn$4$next
sync posedge \coresync_clk
- update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8915
+ update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8829
end
- attribute \src "libresoc.v:162668.3-162669.55"
- process $proc$libresoc.v:162668$8916
+ attribute \src "libresoc.v:160469.3-160470.55"
+ process $proc$libresoc.v:160469$8830
assign { } { }
- assign $0\spr_op__is_32bit$5[0:0]$8917 \spr_op__is_32bit$5$next
+ assign $0\spr_op__is_32bit$5[0:0]$8831 \spr_op__is_32bit$5$next
sync posedge \coresync_clk
- update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8917
+ update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8831
end
- attribute \src "libresoc.v:162670.3-162671.33"
- process $proc$libresoc.v:162670$8918
+ attribute \src "libresoc.v:160471.3-160472.33"
+ process $proc$libresoc.v:160471$8832
assign { } { }
- assign $0\muxid$1[1:0]$8919 \muxid$1$next
+ assign $0\muxid$1[1:0]$8833 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$8919
+ update \muxid$1 $0\muxid$1[1:0]$8833
end
- attribute \src "libresoc.v:162672.3-162673.29"
- process $proc$libresoc.v:162672$8920
+ attribute \src "libresoc.v:160473.3-160474.29"
+ process $proc$libresoc.v:160473$8834
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:162712.3-162729.6"
- process $proc$libresoc.v:162712$8921
+ attribute \src "libresoc.v:160513.3-160530.6"
+ process $proc$libresoc.v:160513$8835
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$8922 $2\r_busy$next[0:0]$8924
- attribute \src "libresoc.v:162713.5-162713.29"
+ assign $0\r_busy$next[0:0]$8836 $2\r_busy$next[0:0]$8838
+ attribute \src "libresoc.v:160514.5-160514.29"
switch \initial
- attribute \src "libresoc.v:162713.9-162713.17"
+ attribute \src "libresoc.v:160514.9-160514.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$8923 1'1
+ assign $1\r_busy$next[0:0]$8837 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$8923 1'0
+ assign $1\r_busy$next[0:0]$8837 1'0
case
- assign $1\r_busy$next[0:0]$8923 \r_busy
+ assign $1\r_busy$next[0:0]$8837 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$8924 1'0
+ assign $2\r_busy$next[0:0]$8838 1'0
case
- assign $2\r_busy$next[0:0]$8924 $1\r_busy$next[0:0]$8923
+ assign $2\r_busy$next[0:0]$8838 $1\r_busy$next[0:0]$8837
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$8922
+ update \r_busy$next $0\r_busy$next[0:0]$8836
end
- attribute \src "libresoc.v:162730.3-162742.6"
- process $proc$libresoc.v:162730$8925
+ attribute \src "libresoc.v:160531.3-160543.6"
+ process $proc$libresoc.v:160531$8839
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$8926 $1\muxid$1$next[1:0]$8927
- attribute \src "libresoc.v:162731.5-162731.29"
+ assign $0\muxid$1$next[1:0]$8840 $1\muxid$1$next[1:0]$8841
+ attribute \src "libresoc.v:160532.5-160532.29"
switch \initial
- attribute \src "libresoc.v:162731.9-162731.17"
+ attribute \src "libresoc.v:160532.9-160532.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$8927 \muxid$24
+ assign $1\muxid$1$next[1:0]$8841 \muxid$24
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$8927 \muxid$24
+ assign $1\muxid$1$next[1:0]$8841 \muxid$24
case
- assign $1\muxid$1$next[1:0]$8927 \muxid$1
+ assign $1\muxid$1$next[1:0]$8841 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$8926
+ update \muxid$1$next $0\muxid$1$next[1:0]$8840
end
- attribute \src "libresoc.v:162743.3-162758.6"
- process $proc$libresoc.v:162743$8928
+ attribute \src "libresoc.v:160544.3-160559.6"
+ process $proc$libresoc.v:160544$8842
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\spr_op__fn_unit$3$next[12:0]$8929 $1\spr_op__fn_unit$3$next[12:0]$8933
- assign $0\spr_op__insn$4$next[31:0]$8930 $1\spr_op__insn$4$next[31:0]$8934
- assign $0\spr_op__insn_type$2$next[6:0]$8931 $1\spr_op__insn_type$2$next[6:0]$8935
- assign $0\spr_op__is_32bit$5$next[0:0]$8932 $1\spr_op__is_32bit$5$next[0:0]$8936
- attribute \src "libresoc.v:162744.5-162744.29"
+ assign $0\spr_op__fn_unit$3$next[12:0]$8843 $1\spr_op__fn_unit$3$next[12:0]$8847
+ assign $0\spr_op__insn$4$next[31:0]$8844 $1\spr_op__insn$4$next[31:0]$8848
+ assign $0\spr_op__insn_type$2$next[6:0]$8845 $1\spr_op__insn_type$2$next[6:0]$8849
+ assign $0\spr_op__is_32bit$5$next[0:0]$8846 $1\spr_op__is_32bit$5$next[0:0]$8850
+ attribute \src "libresoc.v:160545.5-160545.29"
switch \initial
- attribute \src "libresoc.v:162744.9-162744.17"
+ attribute \src "libresoc.v:160545.9-160545.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\spr_op__is_32bit$5$next[0:0]$8936 $1\spr_op__insn$4$next[31:0]$8934 $1\spr_op__fn_unit$3$next[12:0]$8933 $1\spr_op__insn_type$2$next[6:0]$8935 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
+ assign { $1\spr_op__is_32bit$5$next[0:0]$8850 $1\spr_op__insn$4$next[31:0]$8848 $1\spr_op__fn_unit$3$next[12:0]$8847 $1\spr_op__insn_type$2$next[6:0]$8849 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\spr_op__is_32bit$5$next[0:0]$8936 $1\spr_op__insn$4$next[31:0]$8934 $1\spr_op__fn_unit$3$next[12:0]$8933 $1\spr_op__insn_type$2$next[6:0]$8935 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
+ assign { $1\spr_op__is_32bit$5$next[0:0]$8850 $1\spr_op__insn$4$next[31:0]$8848 $1\spr_op__fn_unit$3$next[12:0]$8847 $1\spr_op__insn_type$2$next[6:0]$8849 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
case
- assign $1\spr_op__fn_unit$3$next[12:0]$8933 \spr_op__fn_unit$3
- assign $1\spr_op__insn$4$next[31:0]$8934 \spr_op__insn$4
- assign $1\spr_op__insn_type$2$next[6:0]$8935 \spr_op__insn_type$2
- assign $1\spr_op__is_32bit$5$next[0:0]$8936 \spr_op__is_32bit$5
+ assign $1\spr_op__fn_unit$3$next[12:0]$8847 \spr_op__fn_unit$3
+ assign $1\spr_op__insn$4$next[31:0]$8848 \spr_op__insn$4
+ assign $1\spr_op__insn_type$2$next[6:0]$8849 \spr_op__insn_type$2
+ assign $1\spr_op__is_32bit$5$next[0:0]$8850 \spr_op__is_32bit$5
end
sync always
- update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8929
- update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8930
- update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8931
- update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8932
+ update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8843
+ update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8844
+ update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8845
+ update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8846
end
- attribute \src "libresoc.v:162759.3-162777.6"
- process $proc$libresoc.v:162759$8937
+ attribute \src "libresoc.v:160560.3-160578.6"
+ process $proc$libresoc.v:160560$8851
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$8938 $1\o$next[63:0]$8940
+ assign $0\o$next[63:0]$8852 $1\o$next[63:0]$8854
assign { } { }
- assign $0\o_ok$next[0:0]$8939 $2\o_ok$next[0:0]$8942
- attribute \src "libresoc.v:162760.5-162760.29"
+ assign $0\o_ok$next[0:0]$8853 $2\o_ok$next[0:0]$8856
+ attribute \src "libresoc.v:160561.5-160561.29"
switch \initial
- attribute \src "libresoc.v:162760.9-162760.17"
+ attribute \src "libresoc.v:160561.9-160561.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8941 $1\o$next[63:0]$8940 } { \o_ok$30 \o$29 }
+ assign { $1\o_ok$next[0:0]$8855 $1\o$next[63:0]$8854 } { \o_ok$30 \o$29 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$8941 $1\o$next[63:0]$8940 } { \o_ok$30 \o$29 }
+ assign { $1\o_ok$next[0:0]$8855 $1\o$next[63:0]$8854 } { \o_ok$30 \o$29 }
case
- assign $1\o$next[63:0]$8940 \o
- assign $1\o_ok$next[0:0]$8941 \o_ok
+ assign $1\o$next[63:0]$8854 \o
+ assign $1\o_ok$next[0:0]$8855 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$8942 1'0
+ assign $2\o_ok$next[0:0]$8856 1'0
case
- assign $2\o_ok$next[0:0]$8942 $1\o_ok$next[0:0]$8941
+ assign $2\o_ok$next[0:0]$8856 $1\o_ok$next[0:0]$8855
end
sync always
- update \o$next $0\o$next[63:0]$8938
- update \o_ok$next $0\o_ok$next[0:0]$8939
+ update \o$next $0\o$next[63:0]$8852
+ update \o_ok$next $0\o_ok$next[0:0]$8853
end
- attribute \src "libresoc.v:162778.3-162796.6"
- process $proc$libresoc.v:162778$8943
+ attribute \src "libresoc.v:160579.3-160597.6"
+ process $proc$libresoc.v:160579$8857
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\spr1$6$next[63:0]$8944 $1\spr1$6$next[63:0]$8946
+ assign $0\spr1$6$next[63:0]$8858 $1\spr1$6$next[63:0]$8860
assign { } { }
- assign $0\spr1_ok$next[0:0]$8945 $2\spr1_ok$next[0:0]$8948
- attribute \src "libresoc.v:162779.5-162779.29"
+ assign $0\spr1_ok$next[0:0]$8859 $2\spr1_ok$next[0:0]$8862
+ attribute \src "libresoc.v:160580.5-160580.29"
switch \initial
- attribute \src "libresoc.v:162779.9-162779.17"
+ attribute \src "libresoc.v:160580.9-160580.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\spr1_ok$next[0:0]$8947 $1\spr1$6$next[63:0]$8946 } { \spr1_ok$32 \spr1$31 }
+ assign { $1\spr1_ok$next[0:0]$8861 $1\spr1$6$next[63:0]$8860 } { \spr1_ok$32 \spr1$31 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\spr1_ok$next[0:0]$8947 $1\spr1$6$next[63:0]$8946 } { \spr1_ok$32 \spr1$31 }
+ assign { $1\spr1_ok$next[0:0]$8861 $1\spr1$6$next[63:0]$8860 } { \spr1_ok$32 \spr1$31 }
case
- assign $1\spr1$6$next[63:0]$8946 \spr1$6
- assign $1\spr1_ok$next[0:0]$8947 \spr1_ok
+ assign $1\spr1$6$next[63:0]$8860 \spr1$6
+ assign $1\spr1_ok$next[0:0]$8861 \spr1_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\spr1_ok$next[0:0]$8948 1'0
+ assign $2\spr1_ok$next[0:0]$8862 1'0
case
- assign $2\spr1_ok$next[0:0]$8948 $1\spr1_ok$next[0:0]$8947
+ assign $2\spr1_ok$next[0:0]$8862 $1\spr1_ok$next[0:0]$8861
end
sync always
- update \spr1$6$next $0\spr1$6$next[63:0]$8944
- update \spr1_ok$next $0\spr1_ok$next[0:0]$8945
+ update \spr1$6$next $0\spr1$6$next[63:0]$8858
+ update \spr1_ok$next $0\spr1_ok$next[0:0]$8859
end
- attribute \src "libresoc.v:162797.3-162815.6"
- process $proc$libresoc.v:162797$8949
+ attribute \src "libresoc.v:160598.3-160616.6"
+ process $proc$libresoc.v:160598$8863
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$7$next[63:0]$8951 $1\fast1$7$next[63:0]$8953
- assign $0\fast1_ok$next[0:0]$8950 $2\fast1_ok$next[0:0]$8954
- attribute \src "libresoc.v:162798.5-162798.29"
+ assign $0\fast1$7$next[63:0]$8865 $1\fast1$7$next[63:0]$8867
+ assign $0\fast1_ok$next[0:0]$8864 $2\fast1_ok$next[0:0]$8868
+ attribute \src "libresoc.v:160599.5-160599.29"
switch \initial
- attribute \src "libresoc.v:162798.9-162798.17"
+ attribute \src "libresoc.v:160599.9-160599.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8952 $1\fast1$7$next[63:0]$8953 } { \fast1_ok$34 \fast1$33 }
+ assign { $1\fast1_ok$next[0:0]$8866 $1\fast1$7$next[63:0]$8867 } { \fast1_ok$34 \fast1$33 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$8952 $1\fast1$7$next[63:0]$8953 } { \fast1_ok$34 \fast1$33 }
+ assign { $1\fast1_ok$next[0:0]$8866 $1\fast1$7$next[63:0]$8867 } { \fast1_ok$34 \fast1$33 }
case
- assign $1\fast1_ok$next[0:0]$8952 \fast1_ok
- assign $1\fast1$7$next[63:0]$8953 \fast1$7
+ assign $1\fast1_ok$next[0:0]$8866 \fast1_ok
+ assign $1\fast1$7$next[63:0]$8867 \fast1$7
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$8954 1'0
+ assign $2\fast1_ok$next[0:0]$8868 1'0
case
- assign $2\fast1_ok$next[0:0]$8954 $1\fast1_ok$next[0:0]$8952
+ assign $2\fast1_ok$next[0:0]$8868 $1\fast1_ok$next[0:0]$8866
end
sync always
- update \fast1_ok$next $0\fast1_ok$next[0:0]$8950
- update \fast1$7$next $0\fast1$7$next[63:0]$8951
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$8864
+ update \fast1$7$next $0\fast1$7$next[63:0]$8865
end
- attribute \src "libresoc.v:162816.3-162834.6"
- process $proc$libresoc.v:162816$8955
+ attribute \src "libresoc.v:160617.3-160635.6"
+ process $proc$libresoc.v:160617$8869
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$8$next[0:0]$8957 $1\xer_so$8$next[0:0]$8959
- assign $0\xer_so_ok$next[0:0]$8956 $2\xer_so_ok$next[0:0]$8960
- attribute \src "libresoc.v:162817.5-162817.29"
+ assign $0\xer_so$8$next[0:0]$8871 $1\xer_so$8$next[0:0]$8873
+ assign $0\xer_so_ok$next[0:0]$8870 $2\xer_so_ok$next[0:0]$8874
+ attribute \src "libresoc.v:160618.5-160618.29"
switch \initial
- attribute \src "libresoc.v:162817.9-162817.17"
+ attribute \src "libresoc.v:160618.9-160618.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8958 $1\xer_so$8$next[0:0]$8959 } { \xer_so_ok$36 \xer_so$35 }
+ assign { $1\xer_so_ok$next[0:0]$8872 $1\xer_so$8$next[0:0]$8873 } { \xer_so_ok$36 \xer_so$35 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$8958 $1\xer_so$8$next[0:0]$8959 } { \xer_so_ok$36 \xer_so$35 }
+ assign { $1\xer_so_ok$next[0:0]$8872 $1\xer_so$8$next[0:0]$8873 } { \xer_so_ok$36 \xer_so$35 }
case
- assign $1\xer_so_ok$next[0:0]$8958 \xer_so_ok
- assign $1\xer_so$8$next[0:0]$8959 \xer_so$8
+ assign $1\xer_so_ok$next[0:0]$8872 \xer_so_ok
+ assign $1\xer_so$8$next[0:0]$8873 \xer_so$8
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$8960 1'0
+ assign $2\xer_so_ok$next[0:0]$8874 1'0
case
- assign $2\xer_so_ok$next[0:0]$8960 $1\xer_so_ok$next[0:0]$8958
+ assign $2\xer_so_ok$next[0:0]$8874 $1\xer_so_ok$next[0:0]$8872
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8956
- update \xer_so$8$next $0\xer_so$8$next[0:0]$8957
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8870
+ update \xer_so$8$next $0\xer_so$8$next[0:0]$8871
end
- attribute \src "libresoc.v:162835.3-162853.6"
- process $proc$libresoc.v:162835$8961
+ attribute \src "libresoc.v:160636.3-160654.6"
+ process $proc$libresoc.v:160636$8875
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$9$next[1:0]$8963 $1\xer_ov$9$next[1:0]$8965
- assign $0\xer_ov_ok$next[0:0]$8962 $2\xer_ov_ok$next[0:0]$8966
- attribute \src "libresoc.v:162836.5-162836.29"
+ assign $0\xer_ov$9$next[1:0]$8877 $1\xer_ov$9$next[1:0]$8879
+ assign $0\xer_ov_ok$next[0:0]$8876 $2\xer_ov_ok$next[0:0]$8880
+ attribute \src "libresoc.v:160637.5-160637.29"
switch \initial
- attribute \src "libresoc.v:162836.9-162836.17"
+ attribute \src "libresoc.v:160637.9-160637.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8964 $1\xer_ov$9$next[1:0]$8965 } { \xer_ov_ok$38 \xer_ov$37 }
+ assign { $1\xer_ov_ok$next[0:0]$8878 $1\xer_ov$9$next[1:0]$8879 } { \xer_ov_ok$38 \xer_ov$37 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$8964 $1\xer_ov$9$next[1:0]$8965 } { \xer_ov_ok$38 \xer_ov$37 }
+ assign { $1\xer_ov_ok$next[0:0]$8878 $1\xer_ov$9$next[1:0]$8879 } { \xer_ov_ok$38 \xer_ov$37 }
case
- assign $1\xer_ov_ok$next[0:0]$8964 \xer_ov_ok
- assign $1\xer_ov$9$next[1:0]$8965 \xer_ov$9
+ assign $1\xer_ov_ok$next[0:0]$8878 \xer_ov_ok
+ assign $1\xer_ov$9$next[1:0]$8879 \xer_ov$9
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$8966 1'0
+ assign $2\xer_ov_ok$next[0:0]$8880 1'0
case
- assign $2\xer_ov_ok$next[0:0]$8966 $1\xer_ov_ok$next[0:0]$8964
+ assign $2\xer_ov_ok$next[0:0]$8880 $1\xer_ov_ok$next[0:0]$8878
end
sync always
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8962
- update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8963
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8876
+ update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8877
end
- attribute \src "libresoc.v:162854.3-162872.6"
- process $proc$libresoc.v:162854$8967
+ attribute \src "libresoc.v:160655.3-160673.6"
+ process $proc$libresoc.v:160655$8881
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$10$next[1:0]$8968 $1\xer_ca$10$next[1:0]$8970
+ assign $0\xer_ca$10$next[1:0]$8882 $1\xer_ca$10$next[1:0]$8884
assign { } { }
- assign $0\xer_ca_ok$next[0:0]$8969 $2\xer_ca_ok$next[0:0]$8972
- attribute \src "libresoc.v:162855.5-162855.29"
+ assign $0\xer_ca_ok$next[0:0]$8883 $2\xer_ca_ok$next[0:0]$8886
+ attribute \src "libresoc.v:160656.5-160656.29"
switch \initial
- attribute \src "libresoc.v:162855.9-162855.17"
+ attribute \src "libresoc.v:160656.9-160656.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$8971 $1\xer_ca$10$next[1:0]$8970 } { \xer_ca_ok$40 \xer_ca$39 }
+ assign { $1\xer_ca_ok$next[0:0]$8885 $1\xer_ca$10$next[1:0]$8884 } { \xer_ca_ok$40 \xer_ca$39 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$8971 $1\xer_ca$10$next[1:0]$8970 } { \xer_ca_ok$40 \xer_ca$39 }
+ assign { $1\xer_ca_ok$next[0:0]$8885 $1\xer_ca$10$next[1:0]$8884 } { \xer_ca_ok$40 \xer_ca$39 }
case
- assign $1\xer_ca$10$next[1:0]$8970 \xer_ca$10
- assign $1\xer_ca_ok$next[0:0]$8971 \xer_ca_ok
+ assign $1\xer_ca$10$next[1:0]$8884 \xer_ca$10
+ assign $1\xer_ca_ok$next[0:0]$8885 \xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$8972 1'0
+ assign $2\xer_ca_ok$next[0:0]$8886 1'0
case
- assign $2\xer_ca_ok$next[0:0]$8972 $1\xer_ca_ok$next[0:0]$8971
+ assign $2\xer_ca_ok$next[0:0]$8886 $1\xer_ca_ok$next[0:0]$8885
end
sync always
- update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8968
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8969
+ update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8882
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8883
end
- connect \$22 $and$libresoc.v:162637$8892_Y
+ connect \$22 $and$libresoc.v:160438$8806_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 }
connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
connect \spr_main_muxid \muxid
end
-attribute \src "libresoc.v:162898.1-164376.10"
+attribute \src "libresoc.v:160699.1-162177.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1"
attribute \generator "nMigen"
module \pipe1
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 4 $0\alu_op__data_len$next[3:0]$9065
- attribute \src "libresoc.v:164066.3-164067.49"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 4 $0\alu_op__data_len$next[3:0]$8979
+ attribute \src "libresoc.v:161867.3-161868.49"
wire width 4 $0\alu_op__data_len[3:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 13 $0\alu_op__fn_unit$next[12:0]$9066
- attribute \src "libresoc.v:164036.3-164037.47"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 13 $0\alu_op__fn_unit$next[12:0]$8980
+ attribute \src "libresoc.v:161837.3-161838.47"
wire width 13 $0\alu_op__fn_unit[12:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 64 $0\alu_op__imm_data__data$next[63:0]$9067
- attribute \src "libresoc.v:164038.3-164039.61"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 64 $0\alu_op__imm_data__data$next[63:0]$8981
+ attribute \src "libresoc.v:161839.3-161840.61"
wire width 64 $0\alu_op__imm_data__data[63:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__imm_data__ok$next[0:0]$9068
- attribute \src "libresoc.v:164040.3-164041.57"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__imm_data__ok$next[0:0]$8982
+ attribute \src "libresoc.v:161841.3-161842.57"
wire $0\alu_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 2 $0\alu_op__input_carry$next[1:0]$9069
- attribute \src "libresoc.v:164058.3-164059.55"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 2 $0\alu_op__input_carry$next[1:0]$8983
+ attribute \src "libresoc.v:161859.3-161860.55"
wire width 2 $0\alu_op__input_carry[1:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 32 $0\alu_op__insn$next[31:0]$9070
- attribute \src "libresoc.v:164068.3-164069.41"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 32 $0\alu_op__insn$next[31:0]$8984
+ attribute \src "libresoc.v:161869.3-161870.41"
wire width 32 $0\alu_op__insn[31:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 7 $0\alu_op__insn_type$next[6:0]$9071
- attribute \src "libresoc.v:164034.3-164035.51"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 7 $0\alu_op__insn_type$next[6:0]$8985
+ attribute \src "libresoc.v:161835.3-161836.51"
wire width 7 $0\alu_op__insn_type[6:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__invert_in$next[0:0]$9072
- attribute \src "libresoc.v:164050.3-164051.51"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__invert_in$next[0:0]$8986
+ attribute \src "libresoc.v:161851.3-161852.51"
wire $0\alu_op__invert_in[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__invert_out$next[0:0]$9073
- attribute \src "libresoc.v:164054.3-164055.53"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__invert_out$next[0:0]$8987
+ attribute \src "libresoc.v:161855.3-161856.53"
wire $0\alu_op__invert_out[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__is_32bit$next[0:0]$9074
- attribute \src "libresoc.v:164062.3-164063.49"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__is_32bit$next[0:0]$8988
+ attribute \src "libresoc.v:161863.3-161864.49"
wire $0\alu_op__is_32bit[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__is_signed$next[0:0]$9075
- attribute \src "libresoc.v:164064.3-164065.51"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__is_signed$next[0:0]$8989
+ attribute \src "libresoc.v:161865.3-161866.51"
wire $0\alu_op__is_signed[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__oe__oe$next[0:0]$9076
- attribute \src "libresoc.v:164046.3-164047.45"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__oe__oe$next[0:0]$8990
+ attribute \src "libresoc.v:161847.3-161848.45"
wire $0\alu_op__oe__oe[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__oe__ok$next[0:0]$9077
- attribute \src "libresoc.v:164048.3-164049.45"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__oe__ok$next[0:0]$8991
+ attribute \src "libresoc.v:161849.3-161850.45"
wire $0\alu_op__oe__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__output_carry$next[0:0]$9078
- attribute \src "libresoc.v:164060.3-164061.57"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__output_carry$next[0:0]$8992
+ attribute \src "libresoc.v:161861.3-161862.57"
wire $0\alu_op__output_carry[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__rc__ok$next[0:0]$9079
- attribute \src "libresoc.v:164044.3-164045.45"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__rc__ok$next[0:0]$8993
+ attribute \src "libresoc.v:161845.3-161846.45"
wire $0\alu_op__rc__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__rc__rc$next[0:0]$9080
- attribute \src "libresoc.v:164042.3-164043.45"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__rc__rc$next[0:0]$8994
+ attribute \src "libresoc.v:161843.3-161844.45"
wire $0\alu_op__rc__rc[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__write_cr0$next[0:0]$9081
- attribute \src "libresoc.v:164056.3-164057.51"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__write_cr0$next[0:0]$8995
+ attribute \src "libresoc.v:161857.3-161858.51"
wire $0\alu_op__write_cr0[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $0\alu_op__zero_a$next[0:0]$9082
- attribute \src "libresoc.v:164052.3-164053.45"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $0\alu_op__zero_a$next[0:0]$8996
+ attribute \src "libresoc.v:161853.3-161854.45"
wire $0\alu_op__zero_a[0:0]
- attribute \src "libresoc.v:164183.3-164201.6"
- wire width 4 $0\cr_a$next[3:0]$9034
- attribute \src "libresoc.v:164026.3-164027.25"
+ attribute \src "libresoc.v:161984.3-162002.6"
+ wire width 4 $0\cr_a$next[3:0]$8948
+ attribute \src "libresoc.v:161827.3-161828.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:164183.3-164201.6"
- wire $0\cr_a_ok$next[0:0]$9035
- attribute \src "libresoc.v:164028.3-164029.31"
+ attribute \src "libresoc.v:161984.3-162002.6"
+ wire $0\cr_a_ok$next[0:0]$8949
+ attribute \src "libresoc.v:161829.3-161830.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:162899.7-162899.20"
+ attribute \src "libresoc.v:160700.7-160700.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:164277.3-164289.6"
- wire width 2 $0\muxid$next[1:0]$9062
- attribute \src "libresoc.v:164070.3-164071.27"
+ attribute \src "libresoc.v:162078.3-162090.6"
+ wire width 2 $0\muxid$next[1:0]$8976
+ attribute \src "libresoc.v:161871.3-161872.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:164332.3-164350.6"
- wire width 64 $0\o$next[63:0]$9108
- attribute \src "libresoc.v:164030.3-164031.19"
+ attribute \src "libresoc.v:162133.3-162151.6"
+ wire width 64 $0\o$next[63:0]$9022
+ attribute \src "libresoc.v:161831.3-161832.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:164332.3-164350.6"
- wire $0\o_ok$next[0:0]$9109
- attribute \src "libresoc.v:164032.3-164033.25"
+ attribute \src "libresoc.v:162133.3-162151.6"
+ wire $0\o_ok$next[0:0]$9023
+ attribute \src "libresoc.v:161833.3-161834.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:164259.3-164276.6"
- wire $0\r_busy$next[0:0]$9058
- attribute \src "libresoc.v:164072.3-164073.29"
+ attribute \src "libresoc.v:162060.3-162077.6"
+ wire $0\r_busy$next[0:0]$8972
+ attribute \src "libresoc.v:161873.3-161874.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:164202.3-164220.6"
- wire width 2 $0\xer_ca$next[1:0]$9041
- attribute \src "libresoc.v:164022.3-164023.29"
+ attribute \src "libresoc.v:162003.3-162021.6"
+ wire width 2 $0\xer_ca$next[1:0]$8955
+ attribute \src "libresoc.v:161823.3-161824.29"
wire width 2 $0\xer_ca[1:0]
- attribute \src "libresoc.v:164202.3-164220.6"
- wire $0\xer_ca_ok$next[0:0]$9040
- attribute \src "libresoc.v:164024.3-164025.35"
+ attribute \src "libresoc.v:162003.3-162021.6"
+ wire $0\xer_ca_ok$next[0:0]$8954
+ attribute \src "libresoc.v:161825.3-161826.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:164221.3-164239.6"
- wire width 2 $0\xer_ov$next[1:0]$9046
- attribute \src "libresoc.v:164018.3-164019.29"
+ attribute \src "libresoc.v:162022.3-162040.6"
+ wire width 2 $0\xer_ov$next[1:0]$8960
+ attribute \src "libresoc.v:161819.3-161820.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:164221.3-164239.6"
- wire $0\xer_ov_ok$next[0:0]$9047
- attribute \src "libresoc.v:164020.3-164021.35"
+ attribute \src "libresoc.v:162022.3-162040.6"
+ wire $0\xer_ov_ok$next[0:0]$8961
+ attribute \src "libresoc.v:161821.3-161822.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:164240.3-164258.6"
- wire $0\xer_so$next[0:0]$9052
- attribute \src "libresoc.v:164014.3-164015.29"
+ attribute \src "libresoc.v:162041.3-162059.6"
+ wire $0\xer_so$next[0:0]$8966
+ attribute \src "libresoc.v:161815.3-161816.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:164240.3-164258.6"
- wire $0\xer_so_ok$next[0:0]$9053
- attribute \src "libresoc.v:164016.3-164017.35"
+ attribute \src "libresoc.v:162041.3-162059.6"
+ wire $0\xer_so_ok$next[0:0]$8967
+ attribute \src "libresoc.v:161817.3-161818.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 4 $1\alu_op__data_len$next[3:0]$9083
- attribute \src "libresoc.v:162904.13-162904.36"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 4 $1\alu_op__data_len$next[3:0]$8997
+ attribute \src "libresoc.v:160705.13-160705.36"
wire width 4 $1\alu_op__data_len[3:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 13 $1\alu_op__fn_unit$next[12:0]$9084
- attribute \src "libresoc.v:162927.14-162927.40"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 13 $1\alu_op__fn_unit$next[12:0]$8998
+ attribute \src "libresoc.v:160728.14-160728.40"
wire width 13 $1\alu_op__fn_unit[12:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 64 $1\alu_op__imm_data__data$next[63:0]$9085
- attribute \src "libresoc.v:162964.14-162964.59"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 64 $1\alu_op__imm_data__data$next[63:0]$8999
+ attribute \src "libresoc.v:160765.14-160765.59"
wire width 64 $1\alu_op__imm_data__data[63:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__imm_data__ok$next[0:0]$9086
- attribute \src "libresoc.v:162973.7-162973.34"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__imm_data__ok$next[0:0]$9000
+ attribute \src "libresoc.v:160774.7-160774.34"
wire $1\alu_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 2 $1\alu_op__input_carry$next[1:0]$9087
- attribute \src "libresoc.v:162986.13-162986.39"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 2 $1\alu_op__input_carry$next[1:0]$9001
+ attribute \src "libresoc.v:160787.13-160787.39"
wire width 2 $1\alu_op__input_carry[1:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 32 $1\alu_op__insn$next[31:0]$9088
- attribute \src "libresoc.v:163003.14-163003.34"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 32 $1\alu_op__insn$next[31:0]$9002
+ attribute \src "libresoc.v:160804.14-160804.34"
wire width 32 $1\alu_op__insn[31:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 7 $1\alu_op__insn_type$next[6:0]$9089
- attribute \src "libresoc.v:163086.13-163086.38"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 7 $1\alu_op__insn_type$next[6:0]$9003
+ attribute \src "libresoc.v:160887.13-160887.38"
wire width 7 $1\alu_op__insn_type[6:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__invert_in$next[0:0]$9090
- attribute \src "libresoc.v:163243.7-163243.31"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__invert_in$next[0:0]$9004
+ attribute \src "libresoc.v:161044.7-161044.31"
wire $1\alu_op__invert_in[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__invert_out$next[0:0]$9091
- attribute \src "libresoc.v:163252.7-163252.32"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__invert_out$next[0:0]$9005
+ attribute \src "libresoc.v:161053.7-161053.32"
wire $1\alu_op__invert_out[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__is_32bit$next[0:0]$9092
- attribute \src "libresoc.v:163261.7-163261.30"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__is_32bit$next[0:0]$9006
+ attribute \src "libresoc.v:161062.7-161062.30"
wire $1\alu_op__is_32bit[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__is_signed$next[0:0]$9093
- attribute \src "libresoc.v:163270.7-163270.31"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__is_signed$next[0:0]$9007
+ attribute \src "libresoc.v:161071.7-161071.31"
wire $1\alu_op__is_signed[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__oe__oe$next[0:0]$9094
- attribute \src "libresoc.v:163279.7-163279.28"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__oe__oe$next[0:0]$9008
+ attribute \src "libresoc.v:161080.7-161080.28"
wire $1\alu_op__oe__oe[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__oe__ok$next[0:0]$9095
- attribute \src "libresoc.v:163288.7-163288.28"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__oe__ok$next[0:0]$9009
+ attribute \src "libresoc.v:161089.7-161089.28"
wire $1\alu_op__oe__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__output_carry$next[0:0]$9096
- attribute \src "libresoc.v:163297.7-163297.34"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__output_carry$next[0:0]$9010
+ attribute \src "libresoc.v:161098.7-161098.34"
wire $1\alu_op__output_carry[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__rc__ok$next[0:0]$9097
- attribute \src "libresoc.v:163306.7-163306.28"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__rc__ok$next[0:0]$9011
+ attribute \src "libresoc.v:161107.7-161107.28"
wire $1\alu_op__rc__ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__rc__rc$next[0:0]$9098
- attribute \src "libresoc.v:163315.7-163315.28"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__rc__rc$next[0:0]$9012
+ attribute \src "libresoc.v:161116.7-161116.28"
wire $1\alu_op__rc__rc[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__write_cr0$next[0:0]$9099
- attribute \src "libresoc.v:163324.7-163324.31"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__write_cr0$next[0:0]$9013
+ attribute \src "libresoc.v:161125.7-161125.31"
wire $1\alu_op__write_cr0[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $1\alu_op__zero_a$next[0:0]$9100
- attribute \src "libresoc.v:163333.7-163333.28"
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $1\alu_op__zero_a$next[0:0]$9014
+ attribute \src "libresoc.v:161134.7-161134.28"
wire $1\alu_op__zero_a[0:0]
- attribute \src "libresoc.v:164183.3-164201.6"
- wire width 4 $1\cr_a$next[3:0]$9036
- attribute \src "libresoc.v:163346.13-163346.24"
+ attribute \src "libresoc.v:161984.3-162002.6"
+ wire width 4 $1\cr_a$next[3:0]$8950
+ attribute \src "libresoc.v:161147.13-161147.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:164183.3-164201.6"
- wire $1\cr_a_ok$next[0:0]$9037
- attribute \src "libresoc.v:163353.7-163353.21"
+ attribute \src "libresoc.v:161984.3-162002.6"
+ wire $1\cr_a_ok$next[0:0]$8951
+ attribute \src "libresoc.v:161154.7-161154.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:164277.3-164289.6"
- wire width 2 $1\muxid$next[1:0]$9063
- attribute \src "libresoc.v:163922.13-163922.25"
+ attribute \src "libresoc.v:162078.3-162090.6"
+ wire width 2 $1\muxid$next[1:0]$8977
+ attribute \src "libresoc.v:161723.13-161723.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:164332.3-164350.6"
- wire width 64 $1\o$next[63:0]$9110
- attribute \src "libresoc.v:163937.14-163937.38"
+ attribute \src "libresoc.v:162133.3-162151.6"
+ wire width 64 $1\o$next[63:0]$9024
+ attribute \src "libresoc.v:161738.14-161738.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:164332.3-164350.6"
- wire $1\o_ok$next[0:0]$9111
- attribute \src "libresoc.v:163944.7-163944.18"
+ attribute \src "libresoc.v:162133.3-162151.6"
+ wire $1\o_ok$next[0:0]$9025
+ attribute \src "libresoc.v:161745.7-161745.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:164259.3-164276.6"
- wire $1\r_busy$next[0:0]$9059
- attribute \src "libresoc.v:163958.7-163958.20"
+ attribute \src "libresoc.v:162060.3-162077.6"
+ wire $1\r_busy$next[0:0]$8973
+ attribute \src "libresoc.v:161759.7-161759.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:164202.3-164220.6"
- wire width 2 $1\xer_ca$next[1:0]$9043
- attribute \src "libresoc.v:163967.13-163967.26"
+ attribute \src "libresoc.v:162003.3-162021.6"
+ wire width 2 $1\xer_ca$next[1:0]$8957
+ attribute \src "libresoc.v:161768.13-161768.26"
wire width 2 $1\xer_ca[1:0]
- attribute \src "libresoc.v:164202.3-164220.6"
- wire $1\xer_ca_ok$next[0:0]$9042
- attribute \src "libresoc.v:163976.7-163976.23"
+ attribute \src "libresoc.v:162003.3-162021.6"
+ wire $1\xer_ca_ok$next[0:0]$8956
+ attribute \src "libresoc.v:161777.7-161777.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:164221.3-164239.6"
- wire width 2 $1\xer_ov$next[1:0]$9048
- attribute \src "libresoc.v:163983.13-163983.26"
+ attribute \src "libresoc.v:162022.3-162040.6"
+ wire width 2 $1\xer_ov$next[1:0]$8962
+ attribute \src "libresoc.v:161784.13-161784.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:164221.3-164239.6"
- wire $1\xer_ov_ok$next[0:0]$9049
- attribute \src "libresoc.v:163990.7-163990.23"
+ attribute \src "libresoc.v:162022.3-162040.6"
+ wire $1\xer_ov_ok$next[0:0]$8963
+ attribute \src "libresoc.v:161791.7-161791.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:164240.3-164258.6"
- wire $1\xer_so$next[0:0]$9054
- attribute \src "libresoc.v:163997.7-163997.20"
+ attribute \src "libresoc.v:162041.3-162059.6"
+ wire $1\xer_so$next[0:0]$8968
+ attribute \src "libresoc.v:161798.7-161798.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:164240.3-164258.6"
- wire $1\xer_so_ok$next[0:0]$9055
- attribute \src "libresoc.v:164006.7-164006.23"
+ attribute \src "libresoc.v:162041.3-162059.6"
+ wire $1\xer_so_ok$next[0:0]$8969
+ attribute \src "libresoc.v:161807.7-161807.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:164290.3-164331.6"
- wire width 64 $2\alu_op__imm_data__data$next[63:0]$9101
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $2\alu_op__imm_data__ok$next[0:0]$9102
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $2\alu_op__oe__oe$next[0:0]$9103
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $2\alu_op__oe__ok$next[0:0]$9104
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $2\alu_op__rc__ok$next[0:0]$9105
- attribute \src "libresoc.v:164290.3-164331.6"
- wire $2\alu_op__rc__rc$next[0:0]$9106
- attribute \src "libresoc.v:164183.3-164201.6"
- wire $2\cr_a_ok$next[0:0]$9038
- attribute \src "libresoc.v:164332.3-164350.6"
- wire $2\o_ok$next[0:0]$9112
- attribute \src "libresoc.v:164259.3-164276.6"
- wire $2\r_busy$next[0:0]$9060
- attribute \src "libresoc.v:164202.3-164220.6"
- wire $2\xer_ca_ok$next[0:0]$9044
- attribute \src "libresoc.v:164221.3-164239.6"
- wire $2\xer_ov_ok$next[0:0]$9050
- attribute \src "libresoc.v:164240.3-164258.6"
- wire $2\xer_so_ok$next[0:0]$9056
- attribute \src "libresoc.v:164013.18-164013.118"
- wire $and$libresoc.v:164013$9002_Y
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire width 64 $2\alu_op__imm_data__data$next[63:0]$9015
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $2\alu_op__imm_data__ok$next[0:0]$9016
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $2\alu_op__oe__oe$next[0:0]$9017
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $2\alu_op__oe__ok$next[0:0]$9018
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $2\alu_op__rc__ok$next[0:0]$9019
+ attribute \src "libresoc.v:162091.3-162132.6"
+ wire $2\alu_op__rc__rc$next[0:0]$9020
+ attribute \src "libresoc.v:161984.3-162002.6"
+ wire $2\cr_a_ok$next[0:0]$8952
+ attribute \src "libresoc.v:162133.3-162151.6"
+ wire $2\o_ok$next[0:0]$9026
+ attribute \src "libresoc.v:162060.3-162077.6"
+ wire $2\r_busy$next[0:0]$8974
+ attribute \src "libresoc.v:162003.3-162021.6"
+ wire $2\xer_ca_ok$next[0:0]$8958
+ attribute \src "libresoc.v:162022.3-162040.6"
+ wire $2\xer_ov_ok$next[0:0]$8964
+ attribute \src "libresoc.v:162041.3-162059.6"
+ wire $2\xer_so_ok$next[0:0]$8970
+ attribute \src "libresoc.v:161814.18-161814.118"
+ wire $and$libresoc.v:161814$8916_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 25 \cr_a
wire \cr_a_ok$91
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:162899.7-162899.15"
+ attribute \src "libresoc.v:160700.7-160700.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_alu_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:164013$9002
+ cell $and $and$libresoc.v:161814$8916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$66
connect \B \p_ready_o
- connect \Y $and$libresoc.v:164013$9002_Y
+ connect \Y $and$libresoc.v:161814$8916_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164074.11-164121.4"
+ attribute \src "libresoc.v:161875.11-161922.4"
cell \input \input
connect \alu_op__data_len \input_alu_op__data_len
connect \alu_op__data_len$18 \input_alu_op__data_len$39
connect \xer_so$22 \input_xer_so$43
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164122.8-164174.4"
+ attribute \src "libresoc.v:161923.8-161975.4"
cell \main \main
connect \alu_op__data_len \main_alu_op__data_len
connect \alu_op__data_len$18 \main_alu_op__data_len$62
connect \xer_so$21 \main_xer_so$65
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164175.9-164178.4"
+ attribute \src "libresoc.v:161976.9-161979.4"
cell \n$2 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:164179.9-164182.4"
+ attribute \src "libresoc.v:161980.9-161983.4"
cell \p$1 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:162899.7-162899.20"
- process $proc$libresoc.v:162899$9113
+ attribute \src "libresoc.v:160700.7-160700.20"
+ process $proc$libresoc.v:160700$9027
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:162904.13-162904.36"
- process $proc$libresoc.v:162904$9114
+ attribute \src "libresoc.v:160705.13-160705.36"
+ process $proc$libresoc.v:160705$9028
assign { } { }
assign $1\alu_op__data_len[3:0] 4'0000
sync always
sync init
update \alu_op__data_len $1\alu_op__data_len[3:0]
end
- attribute \src "libresoc.v:162927.14-162927.40"
- process $proc$libresoc.v:162927$9115
+ attribute \src "libresoc.v:160728.14-160728.40"
+ process $proc$libresoc.v:160728$9029
assign { } { }
assign $1\alu_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_op__fn_unit $1\alu_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:162964.14-162964.59"
- process $proc$libresoc.v:162964$9116
+ attribute \src "libresoc.v:160765.14-160765.59"
+ process $proc$libresoc.v:160765$9030
assign { } { }
assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:162973.7-162973.34"
- process $proc$libresoc.v:162973$9117
+ attribute \src "libresoc.v:160774.7-160774.34"
+ process $proc$libresoc.v:160774$9031
assign { } { }
assign $1\alu_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:162986.13-162986.39"
- process $proc$libresoc.v:162986$9118
+ attribute \src "libresoc.v:160787.13-160787.39"
+ process $proc$libresoc.v:160787$9032
assign { } { }
assign $1\alu_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_op__input_carry $1\alu_op__input_carry[1:0]
end
- attribute \src "libresoc.v:163003.14-163003.34"
- process $proc$libresoc.v:163003$9119
+ attribute \src "libresoc.v:160804.14-160804.34"
+ process $proc$libresoc.v:160804$9033
assign { } { }
assign $1\alu_op__insn[31:0] 0
sync always
sync init
update \alu_op__insn $1\alu_op__insn[31:0]
end
- attribute \src "libresoc.v:163086.13-163086.38"
- process $proc$libresoc.v:163086$9120
+ attribute \src "libresoc.v:160887.13-160887.38"
+ process $proc$libresoc.v:160887$9034
assign { } { }
assign $1\alu_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_op__insn_type $1\alu_op__insn_type[6:0]
end
- attribute \src "libresoc.v:163243.7-163243.31"
- process $proc$libresoc.v:163243$9121
+ attribute \src "libresoc.v:161044.7-161044.31"
+ process $proc$libresoc.v:161044$9035
assign { } { }
assign $1\alu_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_op__invert_in $1\alu_op__invert_in[0:0]
end
- attribute \src "libresoc.v:163252.7-163252.32"
- process $proc$libresoc.v:163252$9122
+ attribute \src "libresoc.v:161053.7-161053.32"
+ process $proc$libresoc.v:161053$9036
assign { } { }
assign $1\alu_op__invert_out[0:0] 1'0
sync always
sync init
update \alu_op__invert_out $1\alu_op__invert_out[0:0]
end
- attribute \src "libresoc.v:163261.7-163261.30"
- process $proc$libresoc.v:163261$9123
+ attribute \src "libresoc.v:161062.7-161062.30"
+ process $proc$libresoc.v:161062$9037
assign { } { }
assign $1\alu_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_op__is_32bit $1\alu_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:163270.7-163270.31"
- process $proc$libresoc.v:163270$9124
+ attribute \src "libresoc.v:161071.7-161071.31"
+ process $proc$libresoc.v:161071$9038
assign { } { }
assign $1\alu_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_op__is_signed $1\alu_op__is_signed[0:0]
end
- attribute \src "libresoc.v:163279.7-163279.28"
- process $proc$libresoc.v:163279$9125
+ attribute \src "libresoc.v:161080.7-161080.28"
+ process $proc$libresoc.v:161080$9039
assign { } { }
assign $1\alu_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_op__oe__oe $1\alu_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:163288.7-163288.28"
- process $proc$libresoc.v:163288$9126
+ attribute \src "libresoc.v:161089.7-161089.28"
+ process $proc$libresoc.v:161089$9040
assign { } { }
assign $1\alu_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_op__oe__ok $1\alu_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:163297.7-163297.34"
- process $proc$libresoc.v:163297$9127
+ attribute \src "libresoc.v:161098.7-161098.34"
+ process $proc$libresoc.v:161098$9041
assign { } { }
assign $1\alu_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_op__output_carry $1\alu_op__output_carry[0:0]
end
- attribute \src "libresoc.v:163306.7-163306.28"
- process $proc$libresoc.v:163306$9128
+ attribute \src "libresoc.v:161107.7-161107.28"
+ process $proc$libresoc.v:161107$9042
assign { } { }
assign $1\alu_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_op__rc__ok $1\alu_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:163315.7-163315.28"
- process $proc$libresoc.v:163315$9129
+ attribute \src "libresoc.v:161116.7-161116.28"
+ process $proc$libresoc.v:161116$9043
assign { } { }
assign $1\alu_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_op__rc__rc $1\alu_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:163324.7-163324.31"
- process $proc$libresoc.v:163324$9130
+ attribute \src "libresoc.v:161125.7-161125.31"
+ process $proc$libresoc.v:161125$9044
assign { } { }
assign $1\alu_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:163333.7-163333.28"
- process $proc$libresoc.v:163333$9131
+ attribute \src "libresoc.v:161134.7-161134.28"
+ process $proc$libresoc.v:161134$9045
assign { } { }
assign $1\alu_op__zero_a[0:0] 1'0
sync always
sync init
update \alu_op__zero_a $1\alu_op__zero_a[0:0]
end
- attribute \src "libresoc.v:163346.13-163346.24"
- process $proc$libresoc.v:163346$9132
+ attribute \src "libresoc.v:161147.13-161147.24"
+ process $proc$libresoc.v:161147$9046
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:163353.7-163353.21"
- process $proc$libresoc.v:163353$9133
+ attribute \src "libresoc.v:161154.7-161154.21"
+ process $proc$libresoc.v:161154$9047
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:163922.13-163922.25"
- process $proc$libresoc.v:163922$9134
+ attribute \src "libresoc.v:161723.13-161723.25"
+ process $proc$libresoc.v:161723$9048
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:163937.14-163937.38"
- process $proc$libresoc.v:163937$9135
+ attribute \src "libresoc.v:161738.14-161738.38"
+ process $proc$libresoc.v:161738$9049
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:163944.7-163944.18"
- process $proc$libresoc.v:163944$9136
+ attribute \src "libresoc.v:161745.7-161745.18"
+ process $proc$libresoc.v:161745$9050
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:163958.7-163958.20"
- process $proc$libresoc.v:163958$9137
+ attribute \src "libresoc.v:161759.7-161759.20"
+ process $proc$libresoc.v:161759$9051
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:163967.13-163967.26"
- process $proc$libresoc.v:163967$9138
+ attribute \src "libresoc.v:161768.13-161768.26"
+ process $proc$libresoc.v:161768$9052
assign { } { }
assign $1\xer_ca[1:0] 2'00
sync always
sync init
update \xer_ca $1\xer_ca[1:0]
end
- attribute \src "libresoc.v:163976.7-163976.23"
- process $proc$libresoc.v:163976$9139
+ attribute \src "libresoc.v:161777.7-161777.23"
+ process $proc$libresoc.v:161777$9053
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:163983.13-163983.26"
- process $proc$libresoc.v:163983$9140
+ attribute \src "libresoc.v:161784.13-161784.26"
+ process $proc$libresoc.v:161784$9054
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:163990.7-163990.23"
- process $proc$libresoc.v:163990$9141
+ attribute \src "libresoc.v:161791.7-161791.23"
+ process $proc$libresoc.v:161791$9055
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:163997.7-163997.20"
- process $proc$libresoc.v:163997$9142
+ attribute \src "libresoc.v:161798.7-161798.20"
+ process $proc$libresoc.v:161798$9056
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:164006.7-164006.23"
- process $proc$libresoc.v:164006$9143
+ attribute \src "libresoc.v:161807.7-161807.23"
+ process $proc$libresoc.v:161807$9057
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:164014.3-164015.29"
- process $proc$libresoc.v:164014$9003
+ attribute \src "libresoc.v:161815.3-161816.29"
+ process $proc$libresoc.v:161815$8917
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:164016.3-164017.35"
- process $proc$libresoc.v:164016$9004
+ attribute \src "libresoc.v:161817.3-161818.35"
+ process $proc$libresoc.v:161817$8918
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:164018.3-164019.29"
- process $proc$libresoc.v:164018$9005
+ attribute \src "libresoc.v:161819.3-161820.29"
+ process $proc$libresoc.v:161819$8919
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:164020.3-164021.35"
- process $proc$libresoc.v:164020$9006
+ attribute \src "libresoc.v:161821.3-161822.35"
+ process $proc$libresoc.v:161821$8920
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:164022.3-164023.29"
- process $proc$libresoc.v:164022$9007
+ attribute \src "libresoc.v:161823.3-161824.29"
+ process $proc$libresoc.v:161823$8921
assign { } { }
assign $0\xer_ca[1:0] \xer_ca$next
sync posedge \coresync_clk
update \xer_ca $0\xer_ca[1:0]
end
- attribute \src "libresoc.v:164024.3-164025.35"
- process $proc$libresoc.v:164024$9008
+ attribute \src "libresoc.v:161825.3-161826.35"
+ process $proc$libresoc.v:161825$8922
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:164026.3-164027.25"
- process $proc$libresoc.v:164026$9009
+ attribute \src "libresoc.v:161827.3-161828.25"
+ process $proc$libresoc.v:161827$8923
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:164028.3-164029.31"
- process $proc$libresoc.v:164028$9010
+ attribute \src "libresoc.v:161829.3-161830.31"
+ process $proc$libresoc.v:161829$8924
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:164030.3-164031.19"
- process $proc$libresoc.v:164030$9011
+ attribute \src "libresoc.v:161831.3-161832.19"
+ process $proc$libresoc.v:161831$8925
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:164032.3-164033.25"
- process $proc$libresoc.v:164032$9012
+ attribute \src "libresoc.v:161833.3-161834.25"
+ process $proc$libresoc.v:161833$8926
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:164034.3-164035.51"
- process $proc$libresoc.v:164034$9013
+ attribute \src "libresoc.v:161835.3-161836.51"
+ process $proc$libresoc.v:161835$8927
assign { } { }
assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next
sync posedge \coresync_clk
update \alu_op__insn_type $0\alu_op__insn_type[6:0]
end
- attribute \src "libresoc.v:164036.3-164037.47"
- process $proc$libresoc.v:164036$9014
+ attribute \src "libresoc.v:161837.3-161838.47"
+ process $proc$libresoc.v:161837$8928
assign { } { }
assign $0\alu_op__fn_unit[12:0] \alu_op__fn_unit$next
sync posedge \coresync_clk
update \alu_op__fn_unit $0\alu_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:164038.3-164039.61"
- process $proc$libresoc.v:164038$9015
+ attribute \src "libresoc.v:161839.3-161840.61"
+ process $proc$libresoc.v:161839$8929
assign { } { }
assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:164040.3-164041.57"
- process $proc$libresoc.v:164040$9016
+ attribute \src "libresoc.v:161841.3-161842.57"
+ process $proc$libresoc.v:161841$8930
assign { } { }
assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:164042.3-164043.45"
- process $proc$libresoc.v:164042$9017
+ attribute \src "libresoc.v:161843.3-161844.45"
+ process $proc$libresoc.v:161843$8931
assign { } { }
assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next
sync posedge \coresync_clk
update \alu_op__rc__rc $0\alu_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:164044.3-164045.45"
- process $proc$libresoc.v:164044$9018
+ attribute \src "libresoc.v:161845.3-161846.45"
+ process $proc$libresoc.v:161845$8932
assign { } { }
assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next
sync posedge \coresync_clk
update \alu_op__rc__ok $0\alu_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:164046.3-164047.45"
- process $proc$libresoc.v:164046$9019
+ attribute \src "libresoc.v:161847.3-161848.45"
+ process $proc$libresoc.v:161847$8933
assign { } { }
assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next
sync posedge \coresync_clk
update \alu_op__oe__oe $0\alu_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:164048.3-164049.45"
- process $proc$libresoc.v:164048$9020
+ attribute \src "libresoc.v:161849.3-161850.45"
+ process $proc$libresoc.v:161849$8934
assign { } { }
assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next
sync posedge \coresync_clk
update \alu_op__oe__ok $0\alu_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:164050.3-164051.51"
- process $proc$libresoc.v:164050$9021
+ attribute \src "libresoc.v:161851.3-161852.51"
+ process $proc$libresoc.v:161851$8935
assign { } { }
assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next
sync posedge \coresync_clk
update \alu_op__invert_in $0\alu_op__invert_in[0:0]
end
- attribute \src "libresoc.v:164052.3-164053.45"
- process $proc$libresoc.v:164052$9022
+ attribute \src "libresoc.v:161853.3-161854.45"
+ process $proc$libresoc.v:161853$8936
assign { } { }
assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next
sync posedge \coresync_clk
update \alu_op__zero_a $0\alu_op__zero_a[0:0]
end
- attribute \src "libresoc.v:164054.3-164055.53"
- process $proc$libresoc.v:164054$9023
+ attribute \src "libresoc.v:161855.3-161856.53"
+ process $proc$libresoc.v:161855$8937
assign { } { }
assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next
sync posedge \coresync_clk
update \alu_op__invert_out $0\alu_op__invert_out[0:0]
end
- attribute \src "libresoc.v:164056.3-164057.51"
- process $proc$libresoc.v:164056$9024
+ attribute \src "libresoc.v:161857.3-161858.51"
+ process $proc$libresoc.v:161857$8938
assign { } { }
assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next
sync posedge \coresync_clk
update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:164058.3-164059.55"
- process $proc$libresoc.v:164058$9025
+ attribute \src "libresoc.v:161859.3-161860.55"
+ process $proc$libresoc.v:161859$8939
assign { } { }
assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next
sync posedge \coresync_clk
update \alu_op__input_carry $0\alu_op__input_carry[1:0]
end
- attribute \src "libresoc.v:164060.3-164061.57"
- process $proc$libresoc.v:164060$9026
+ attribute \src "libresoc.v:161861.3-161862.57"
+ process $proc$libresoc.v:161861$8940
assign { } { }
assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next
sync posedge \coresync_clk
update \alu_op__output_carry $0\alu_op__output_carry[0:0]
end
- attribute \src "libresoc.v:164062.3-164063.49"
- process $proc$libresoc.v:164062$9027
+ attribute \src "libresoc.v:161863.3-161864.49"
+ process $proc$libresoc.v:161863$8941
assign { } { }
assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next
sync posedge \coresync_clk
update \alu_op__is_32bit $0\alu_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:164064.3-164065.51"
- process $proc$libresoc.v:164064$9028
+ attribute \src "libresoc.v:161865.3-161866.51"
+ process $proc$libresoc.v:161865$8942
assign { } { }
assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next
sync posedge \coresync_clk
update \alu_op__is_signed $0\alu_op__is_signed[0:0]
end
- attribute \src "libresoc.v:164066.3-164067.49"
- process $proc$libresoc.v:164066$9029
+ attribute \src "libresoc.v:161867.3-161868.49"
+ process $proc$libresoc.v:161867$8943
assign { } { }
assign $0\alu_op__data_len[3:0] \alu_op__data_len$next
sync posedge \coresync_clk
update \alu_op__data_len $0\alu_op__data_len[3:0]
end
- attribute \src "libresoc.v:164068.3-164069.41"
- process $proc$libresoc.v:164068$9030
+ attribute \src "libresoc.v:161869.3-161870.41"
+ process $proc$libresoc.v:161869$8944
assign { } { }
assign $0\alu_op__insn[31:0] \alu_op__insn$next
sync posedge \coresync_clk
update \alu_op__insn $0\alu_op__insn[31:0]
end
- attribute \src "libresoc.v:164070.3-164071.27"
- process $proc$libresoc.v:164070$9031
+ attribute \src "libresoc.v:161871.3-161872.27"
+ process $proc$libresoc.v:161871$8945
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:164072.3-164073.29"
- process $proc$libresoc.v:164072$9032
+ attribute \src "libresoc.v:161873.3-161874.29"
+ process $proc$libresoc.v:161873$8946
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:164183.3-164201.6"
- process $proc$libresoc.v:164183$9033
+ attribute \src "libresoc.v:161984.3-162002.6"
+ process $proc$libresoc.v:161984$8947
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9034 $1\cr_a$next[3:0]$9036
+ assign $0\cr_a$next[3:0]$8948 $1\cr_a$next[3:0]$8950
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9035 $2\cr_a_ok$next[0:0]$9038
- attribute \src "libresoc.v:164184.5-164184.29"
+ assign $0\cr_a_ok$next[0:0]$8949 $2\cr_a_ok$next[0:0]$8952
+ attribute \src "libresoc.v:161985.5-161985.29"
switch \initial
- attribute \src "libresoc.v:164184.9-164184.17"
+ attribute \src "libresoc.v:161985.9-161985.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9037 $1\cr_a$next[3:0]$9036 } { \cr_a_ok$91 \cr_a$90 }
+ assign { $1\cr_a_ok$next[0:0]$8951 $1\cr_a$next[3:0]$8950 } { \cr_a_ok$91 \cr_a$90 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9037 $1\cr_a$next[3:0]$9036 } { \cr_a_ok$91 \cr_a$90 }
+ assign { $1\cr_a_ok$next[0:0]$8951 $1\cr_a$next[3:0]$8950 } { \cr_a_ok$91 \cr_a$90 }
case
- assign $1\cr_a$next[3:0]$9036 \cr_a
- assign $1\cr_a_ok$next[0:0]$9037 \cr_a_ok
+ assign $1\cr_a$next[3:0]$8950 \cr_a
+ assign $1\cr_a_ok$next[0:0]$8951 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9038 1'0
+ assign $2\cr_a_ok$next[0:0]$8952 1'0
case
- assign $2\cr_a_ok$next[0:0]$9038 $1\cr_a_ok$next[0:0]$9037
+ assign $2\cr_a_ok$next[0:0]$8952 $1\cr_a_ok$next[0:0]$8951
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9034
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9035
+ update \cr_a$next $0\cr_a$next[3:0]$8948
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8949
end
- attribute \src "libresoc.v:164202.3-164220.6"
- process $proc$libresoc.v:164202$9039
+ attribute \src "libresoc.v:162003.3-162021.6"
+ process $proc$libresoc.v:162003$8953
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$next[1:0]$9041 $1\xer_ca$next[1:0]$9043
- assign $0\xer_ca_ok$next[0:0]$9040 $2\xer_ca_ok$next[0:0]$9044
- attribute \src "libresoc.v:164203.5-164203.29"
+ assign $0\xer_ca$next[1:0]$8955 $1\xer_ca$next[1:0]$8957
+ assign $0\xer_ca_ok$next[0:0]$8954 $2\xer_ca_ok$next[0:0]$8958
+ attribute \src "libresoc.v:162004.5-162004.29"
switch \initial
- attribute \src "libresoc.v:164203.9-164203.17"
+ attribute \src "libresoc.v:162004.9-162004.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9042 $1\xer_ca$next[1:0]$9043 } { \xer_ca_ok$93 \xer_ca$92 }
+ assign { $1\xer_ca_ok$next[0:0]$8956 $1\xer_ca$next[1:0]$8957 } { \xer_ca_ok$93 \xer_ca$92 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9042 $1\xer_ca$next[1:0]$9043 } { \xer_ca_ok$93 \xer_ca$92 }
+ assign { $1\xer_ca_ok$next[0:0]$8956 $1\xer_ca$next[1:0]$8957 } { \xer_ca_ok$93 \xer_ca$92 }
case
- assign $1\xer_ca_ok$next[0:0]$9042 \xer_ca_ok
- assign $1\xer_ca$next[1:0]$9043 \xer_ca
+ assign $1\xer_ca_ok$next[0:0]$8956 \xer_ca_ok
+ assign $1\xer_ca$next[1:0]$8957 \xer_ca
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$9044 1'0
+ assign $2\xer_ca_ok$next[0:0]$8958 1'0
case
- assign $2\xer_ca_ok$next[0:0]$9044 $1\xer_ca_ok$next[0:0]$9042
+ assign $2\xer_ca_ok$next[0:0]$8958 $1\xer_ca_ok$next[0:0]$8956
end
sync always
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9040
- update \xer_ca$next $0\xer_ca$next[1:0]$9041
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8954
+ update \xer_ca$next $0\xer_ca$next[1:0]$8955
end
- attribute \src "libresoc.v:164221.3-164239.6"
- process $proc$libresoc.v:164221$9045
+ attribute \src "libresoc.v:162022.3-162040.6"
+ process $proc$libresoc.v:162022$8959
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$9046 $1\xer_ov$next[1:0]$9048
+ assign $0\xer_ov$next[1:0]$8960 $1\xer_ov$next[1:0]$8962
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$9047 $2\xer_ov_ok$next[0:0]$9050
- attribute \src "libresoc.v:164222.5-164222.29"
+ assign $0\xer_ov_ok$next[0:0]$8961 $2\xer_ov_ok$next[0:0]$8964
+ attribute \src "libresoc.v:162023.5-162023.29"
switch \initial
- attribute \src "libresoc.v:164222.9-164222.17"
+ attribute \src "libresoc.v:162023.9-162023.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9049 $1\xer_ov$next[1:0]$9048 } { \xer_ov_ok$95 \xer_ov$94 }
+ assign { $1\xer_ov_ok$next[0:0]$8963 $1\xer_ov$next[1:0]$8962 } { \xer_ov_ok$95 \xer_ov$94 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9049 $1\xer_ov$next[1:0]$9048 } { \xer_ov_ok$95 \xer_ov$94 }
+ assign { $1\xer_ov_ok$next[0:0]$8963 $1\xer_ov$next[1:0]$8962 } { \xer_ov_ok$95 \xer_ov$94 }
case
- assign $1\xer_ov$next[1:0]$9048 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$9049 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$8962 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$8963 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$9050 1'0
+ assign $2\xer_ov_ok$next[0:0]$8964 1'0
case
- assign $2\xer_ov_ok$next[0:0]$9050 $1\xer_ov_ok$next[0:0]$9049
+ assign $2\xer_ov_ok$next[0:0]$8964 $1\xer_ov_ok$next[0:0]$8963
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$9046
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9047
+ update \xer_ov$next $0\xer_ov$next[1:0]$8960
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8961
end
- attribute \src "libresoc.v:164240.3-164258.6"
- process $proc$libresoc.v:164240$9051
+ attribute \src "libresoc.v:162041.3-162059.6"
+ process $proc$libresoc.v:162041$8965
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$9052 $1\xer_so$next[0:0]$9054
+ assign $0\xer_so$next[0:0]$8966 $1\xer_so$next[0:0]$8968
assign { } { }
- assign $0\xer_so_ok$next[0:0]$9053 $2\xer_so_ok$next[0:0]$9056
- attribute \src "libresoc.v:164241.5-164241.29"
+ assign $0\xer_so_ok$next[0:0]$8967 $2\xer_so_ok$next[0:0]$8970
+ attribute \src "libresoc.v:162042.5-162042.29"
switch \initial
- attribute \src "libresoc.v:164241.9-164241.17"
+ attribute \src "libresoc.v:162042.9-162042.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9055 $1\xer_so$next[0:0]$9054 } { \xer_so_ok$97 \xer_so$96 }
+ assign { $1\xer_so_ok$next[0:0]$8969 $1\xer_so$next[0:0]$8968 } { \xer_so_ok$97 \xer_so$96 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9055 $1\xer_so$next[0:0]$9054 } { \xer_so_ok$97 \xer_so$96 }
+ assign { $1\xer_so_ok$next[0:0]$8969 $1\xer_so$next[0:0]$8968 } { \xer_so_ok$97 \xer_so$96 }
case
- assign $1\xer_so$next[0:0]$9054 \xer_so
- assign $1\xer_so_ok$next[0:0]$9055 \xer_so_ok
+ assign $1\xer_so$next[0:0]$8968 \xer_so
+ assign $1\xer_so_ok$next[0:0]$8969 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9056 1'0
+ assign $2\xer_so_ok$next[0:0]$8970 1'0
case
- assign $2\xer_so_ok$next[0:0]$9056 $1\xer_so_ok$next[0:0]$9055
+ assign $2\xer_so_ok$next[0:0]$8970 $1\xer_so_ok$next[0:0]$8969
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$9052
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9053
+ update \xer_so$next $0\xer_so$next[0:0]$8966
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8967
end
- attribute \src "libresoc.v:164259.3-164276.6"
- process $proc$libresoc.v:164259$9057
+ attribute \src "libresoc.v:162060.3-162077.6"
+ process $proc$libresoc.v:162060$8971
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9058 $2\r_busy$next[0:0]$9060
- attribute \src "libresoc.v:164260.5-164260.29"
+ assign $0\r_busy$next[0:0]$8972 $2\r_busy$next[0:0]$8974
+ attribute \src "libresoc.v:162061.5-162061.29"
switch \initial
- attribute \src "libresoc.v:164260.9-164260.17"
+ attribute \src "libresoc.v:162061.9-162061.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9059 1'1
+ assign $1\r_busy$next[0:0]$8973 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9059 1'0
+ assign $1\r_busy$next[0:0]$8973 1'0
case
- assign $1\r_busy$next[0:0]$9059 \r_busy
+ assign $1\r_busy$next[0:0]$8973 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9060 1'0
+ assign $2\r_busy$next[0:0]$8974 1'0
case
- assign $2\r_busy$next[0:0]$9060 $1\r_busy$next[0:0]$9059
+ assign $2\r_busy$next[0:0]$8974 $1\r_busy$next[0:0]$8973
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9058
+ update \r_busy$next $0\r_busy$next[0:0]$8972
end
- attribute \src "libresoc.v:164277.3-164289.6"
- process $proc$libresoc.v:164277$9061
+ attribute \src "libresoc.v:162078.3-162090.6"
+ process $proc$libresoc.v:162078$8975
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9062 $1\muxid$next[1:0]$9063
- attribute \src "libresoc.v:164278.5-164278.29"
+ assign $0\muxid$next[1:0]$8976 $1\muxid$next[1:0]$8977
+ attribute \src "libresoc.v:162079.5-162079.29"
switch \initial
- attribute \src "libresoc.v:164278.9-164278.17"
+ attribute \src "libresoc.v:162079.9-162079.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9063 \muxid$69
+ assign $1\muxid$next[1:0]$8977 \muxid$69
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9063 \muxid$69
+ assign $1\muxid$next[1:0]$8977 \muxid$69
case
- assign $1\muxid$next[1:0]$9063 \muxid
+ assign $1\muxid$next[1:0]$8977 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9062
+ update \muxid$next $0\muxid$next[1:0]$8976
end
- attribute \src "libresoc.v:164290.3-164331.6"
- process $proc$libresoc.v:164290$9064
+ attribute \src "libresoc.v:162091.3-162132.6"
+ process $proc$libresoc.v:162091$8978
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_op__data_len$next[3:0]$9065 $1\alu_op__data_len$next[3:0]$9083
- assign $0\alu_op__fn_unit$next[12:0]$9066 $1\alu_op__fn_unit$next[12:0]$9084
+ assign $0\alu_op__data_len$next[3:0]$8979 $1\alu_op__data_len$next[3:0]$8997
+ assign $0\alu_op__fn_unit$next[12:0]$8980 $1\alu_op__fn_unit$next[12:0]$8998
assign { } { }
assign { } { }
- assign $0\alu_op__input_carry$next[1:0]$9069 $1\alu_op__input_carry$next[1:0]$9087
- assign $0\alu_op__insn$next[31:0]$9070 $1\alu_op__insn$next[31:0]$9088
- assign $0\alu_op__insn_type$next[6:0]$9071 $1\alu_op__insn_type$next[6:0]$9089
- assign $0\alu_op__invert_in$next[0:0]$9072 $1\alu_op__invert_in$next[0:0]$9090
- assign $0\alu_op__invert_out$next[0:0]$9073 $1\alu_op__invert_out$next[0:0]$9091
- assign $0\alu_op__is_32bit$next[0:0]$9074 $1\alu_op__is_32bit$next[0:0]$9092
- assign $0\alu_op__is_signed$next[0:0]$9075 $1\alu_op__is_signed$next[0:0]$9093
+ assign $0\alu_op__input_carry$next[1:0]$8983 $1\alu_op__input_carry$next[1:0]$9001
+ assign $0\alu_op__insn$next[31:0]$8984 $1\alu_op__insn$next[31:0]$9002
+ assign $0\alu_op__insn_type$next[6:0]$8985 $1\alu_op__insn_type$next[6:0]$9003
+ assign $0\alu_op__invert_in$next[0:0]$8986 $1\alu_op__invert_in$next[0:0]$9004
+ assign $0\alu_op__invert_out$next[0:0]$8987 $1\alu_op__invert_out$next[0:0]$9005
+ assign $0\alu_op__is_32bit$next[0:0]$8988 $1\alu_op__is_32bit$next[0:0]$9006
+ assign $0\alu_op__is_signed$next[0:0]$8989 $1\alu_op__is_signed$next[0:0]$9007
assign { } { }
assign { } { }
- assign $0\alu_op__output_carry$next[0:0]$9078 $1\alu_op__output_carry$next[0:0]$9096
+ assign $0\alu_op__output_carry$next[0:0]$8992 $1\alu_op__output_carry$next[0:0]$9010
assign { } { }
assign { } { }
- assign $0\alu_op__write_cr0$next[0:0]$9081 $1\alu_op__write_cr0$next[0:0]$9099
- assign $0\alu_op__zero_a$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9100
- assign $0\alu_op__imm_data__data$next[63:0]$9067 $2\alu_op__imm_data__data$next[63:0]$9101
- assign $0\alu_op__imm_data__ok$next[0:0]$9068 $2\alu_op__imm_data__ok$next[0:0]$9102
- assign $0\alu_op__oe__oe$next[0:0]$9076 $2\alu_op__oe__oe$next[0:0]$9103
- assign $0\alu_op__oe__ok$next[0:0]$9077 $2\alu_op__oe__ok$next[0:0]$9104
- assign $0\alu_op__rc__ok$next[0:0]$9079 $2\alu_op__rc__ok$next[0:0]$9105
- assign $0\alu_op__rc__rc$next[0:0]$9080 $2\alu_op__rc__rc$next[0:0]$9106
- attribute \src "libresoc.v:164291.5-164291.29"
+ assign $0\alu_op__write_cr0$next[0:0]$8995 $1\alu_op__write_cr0$next[0:0]$9013
+ assign $0\alu_op__zero_a$next[0:0]$8996 $1\alu_op__zero_a$next[0:0]$9014
+ assign $0\alu_op__imm_data__data$next[63:0]$8981 $2\alu_op__imm_data__data$next[63:0]$9015
+ assign $0\alu_op__imm_data__ok$next[0:0]$8982 $2\alu_op__imm_data__ok$next[0:0]$9016
+ assign $0\alu_op__oe__oe$next[0:0]$8990 $2\alu_op__oe__oe$next[0:0]$9017
+ assign $0\alu_op__oe__ok$next[0:0]$8991 $2\alu_op__oe__ok$next[0:0]$9018
+ assign $0\alu_op__rc__ok$next[0:0]$8993 $2\alu_op__rc__ok$next[0:0]$9019
+ assign $0\alu_op__rc__rc$next[0:0]$8994 $2\alu_op__rc__rc$next[0:0]$9020
+ attribute \src "libresoc.v:162092.5-162092.29"
switch \initial
- attribute \src "libresoc.v:164291.9-164291.17"
+ attribute \src "libresoc.v:162092.9-162092.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$next[31:0]$9088 $1\alu_op__data_len$next[3:0]$9083 $1\alu_op__is_signed$next[0:0]$9093 $1\alu_op__is_32bit$next[0:0]$9092 $1\alu_op__output_carry$next[0:0]$9096 $1\alu_op__input_carry$next[1:0]$9087 $1\alu_op__write_cr0$next[0:0]$9099 $1\alu_op__invert_out$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9100 $1\alu_op__invert_in$next[0:0]$9090 $1\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__rc__ok$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9098 $1\alu_op__imm_data__ok$next[0:0]$9086 $1\alu_op__imm_data__data$next[63:0]$9085 $1\alu_op__fn_unit$next[12:0]$9084 $1\alu_op__insn_type$next[6:0]$9089 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
+ assign { $1\alu_op__insn$next[31:0]$9002 $1\alu_op__data_len$next[3:0]$8997 $1\alu_op__is_signed$next[0:0]$9007 $1\alu_op__is_32bit$next[0:0]$9006 $1\alu_op__output_carry$next[0:0]$9010 $1\alu_op__input_carry$next[1:0]$9001 $1\alu_op__write_cr0$next[0:0]$9013 $1\alu_op__invert_out$next[0:0]$9005 $1\alu_op__zero_a$next[0:0]$9014 $1\alu_op__invert_in$next[0:0]$9004 $1\alu_op__oe__ok$next[0:0]$9009 $1\alu_op__oe__oe$next[0:0]$9008 $1\alu_op__rc__ok$next[0:0]$9011 $1\alu_op__rc__rc$next[0:0]$9012 $1\alu_op__imm_data__ok$next[0:0]$9000 $1\alu_op__imm_data__data$next[63:0]$8999 $1\alu_op__fn_unit$next[12:0]$8998 $1\alu_op__insn_type$next[6:0]$9003 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$next[31:0]$9088 $1\alu_op__data_len$next[3:0]$9083 $1\alu_op__is_signed$next[0:0]$9093 $1\alu_op__is_32bit$next[0:0]$9092 $1\alu_op__output_carry$next[0:0]$9096 $1\alu_op__input_carry$next[1:0]$9087 $1\alu_op__write_cr0$next[0:0]$9099 $1\alu_op__invert_out$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9100 $1\alu_op__invert_in$next[0:0]$9090 $1\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__rc__ok$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9098 $1\alu_op__imm_data__ok$next[0:0]$9086 $1\alu_op__imm_data__data$next[63:0]$9085 $1\alu_op__fn_unit$next[12:0]$9084 $1\alu_op__insn_type$next[6:0]$9089 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
+ assign { $1\alu_op__insn$next[31:0]$9002 $1\alu_op__data_len$next[3:0]$8997 $1\alu_op__is_signed$next[0:0]$9007 $1\alu_op__is_32bit$next[0:0]$9006 $1\alu_op__output_carry$next[0:0]$9010 $1\alu_op__input_carry$next[1:0]$9001 $1\alu_op__write_cr0$next[0:0]$9013 $1\alu_op__invert_out$next[0:0]$9005 $1\alu_op__zero_a$next[0:0]$9014 $1\alu_op__invert_in$next[0:0]$9004 $1\alu_op__oe__ok$next[0:0]$9009 $1\alu_op__oe__oe$next[0:0]$9008 $1\alu_op__rc__ok$next[0:0]$9011 $1\alu_op__rc__rc$next[0:0]$9012 $1\alu_op__imm_data__ok$next[0:0]$9000 $1\alu_op__imm_data__data$next[63:0]$8999 $1\alu_op__fn_unit$next[12:0]$8998 $1\alu_op__insn_type$next[6:0]$9003 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 }
case
- assign $1\alu_op__data_len$next[3:0]$9083 \alu_op__data_len
- assign $1\alu_op__fn_unit$next[12:0]$9084 \alu_op__fn_unit
- assign $1\alu_op__imm_data__data$next[63:0]$9085 \alu_op__imm_data__data
- assign $1\alu_op__imm_data__ok$next[0:0]$9086 \alu_op__imm_data__ok
- assign $1\alu_op__input_carry$next[1:0]$9087 \alu_op__input_carry
- assign $1\alu_op__insn$next[31:0]$9088 \alu_op__insn
- assign $1\alu_op__insn_type$next[6:0]$9089 \alu_op__insn_type
- assign $1\alu_op__invert_in$next[0:0]$9090 \alu_op__invert_in
- assign $1\alu_op__invert_out$next[0:0]$9091 \alu_op__invert_out
- assign $1\alu_op__is_32bit$next[0:0]$9092 \alu_op__is_32bit
- assign $1\alu_op__is_signed$next[0:0]$9093 \alu_op__is_signed
- assign $1\alu_op__oe__oe$next[0:0]$9094 \alu_op__oe__oe
- assign $1\alu_op__oe__ok$next[0:0]$9095 \alu_op__oe__ok
- assign $1\alu_op__output_carry$next[0:0]$9096 \alu_op__output_carry
- assign $1\alu_op__rc__ok$next[0:0]$9097 \alu_op__rc__ok
- assign $1\alu_op__rc__rc$next[0:0]$9098 \alu_op__rc__rc
- assign $1\alu_op__write_cr0$next[0:0]$9099 \alu_op__write_cr0
- assign $1\alu_op__zero_a$next[0:0]$9100 \alu_op__zero_a
+ assign $1\alu_op__data_len$next[3:0]$8997 \alu_op__data_len
+ assign $1\alu_op__fn_unit$next[12:0]$8998 \alu_op__fn_unit
+ assign $1\alu_op__imm_data__data$next[63:0]$8999 \alu_op__imm_data__data
+ assign $1\alu_op__imm_data__ok$next[0:0]$9000 \alu_op__imm_data__ok
+ assign $1\alu_op__input_carry$next[1:0]$9001 \alu_op__input_carry
+ assign $1\alu_op__insn$next[31:0]$9002 \alu_op__insn
+ assign $1\alu_op__insn_type$next[6:0]$9003 \alu_op__insn_type
+ assign $1\alu_op__invert_in$next[0:0]$9004 \alu_op__invert_in
+ assign $1\alu_op__invert_out$next[0:0]$9005 \alu_op__invert_out
+ assign $1\alu_op__is_32bit$next[0:0]$9006 \alu_op__is_32bit
+ assign $1\alu_op__is_signed$next[0:0]$9007 \alu_op__is_signed
+ assign $1\alu_op__oe__oe$next[0:0]$9008 \alu_op__oe__oe
+ assign $1\alu_op__oe__ok$next[0:0]$9009 \alu_op__oe__ok
+ assign $1\alu_op__output_carry$next[0:0]$9010 \alu_op__output_carry
+ assign $1\alu_op__rc__ok$next[0:0]$9011 \alu_op__rc__ok
+ assign $1\alu_op__rc__rc$next[0:0]$9012 \alu_op__rc__rc
+ assign $1\alu_op__write_cr0$next[0:0]$9013 \alu_op__write_cr0
+ assign $1\alu_op__zero_a$next[0:0]$9014 \alu_op__zero_a
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_op__imm_data__data$next[63:0]$9101 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_op__imm_data__ok$next[0:0]$9102 1'0
- assign $2\alu_op__rc__rc$next[0:0]$9106 1'0
- assign $2\alu_op__rc__ok$next[0:0]$9105 1'0
- assign $2\alu_op__oe__oe$next[0:0]$9103 1'0
- assign $2\alu_op__oe__ok$next[0:0]$9104 1'0
+ assign $2\alu_op__imm_data__data$next[63:0]$9015 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_op__imm_data__ok$next[0:0]$9016 1'0
+ assign $2\alu_op__rc__rc$next[0:0]$9020 1'0
+ assign $2\alu_op__rc__ok$next[0:0]$9019 1'0
+ assign $2\alu_op__oe__oe$next[0:0]$9017 1'0
+ assign $2\alu_op__oe__ok$next[0:0]$9018 1'0
case
- assign $2\alu_op__imm_data__data$next[63:0]$9101 $1\alu_op__imm_data__data$next[63:0]$9085
- assign $2\alu_op__imm_data__ok$next[0:0]$9102 $1\alu_op__imm_data__ok$next[0:0]$9086
- assign $2\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__oe__oe$next[0:0]$9094
- assign $2\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__ok$next[0:0]$9095
- assign $2\alu_op__rc__ok$next[0:0]$9105 $1\alu_op__rc__ok$next[0:0]$9097
- assign $2\alu_op__rc__rc$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9098
+ assign $2\alu_op__imm_data__data$next[63:0]$9015 $1\alu_op__imm_data__data$next[63:0]$8999
+ assign $2\alu_op__imm_data__ok$next[0:0]$9016 $1\alu_op__imm_data__ok$next[0:0]$9000
+ assign $2\alu_op__oe__oe$next[0:0]$9017 $1\alu_op__oe__oe$next[0:0]$9008
+ assign $2\alu_op__oe__ok$next[0:0]$9018 $1\alu_op__oe__ok$next[0:0]$9009
+ assign $2\alu_op__rc__ok$next[0:0]$9019 $1\alu_op__rc__ok$next[0:0]$9011
+ assign $2\alu_op__rc__rc$next[0:0]$9020 $1\alu_op__rc__rc$next[0:0]$9012
end
sync always
- update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9065
- update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$9066
- update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9067
- update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9068
- update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9069
- update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9070
- update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9071
- update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9072
- update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9073
- update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9074
- update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9075
- update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9076
- update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9077
- update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9078
- update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9079
- update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9080
- update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9081
- update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9082
+ update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8979
+ update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$8980
+ update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8981
+ update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8982
+ update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8983
+ update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8984
+ update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8985
+ update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8986
+ update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8987
+ update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8988
+ update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8989
+ update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8990
+ update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8991
+ update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8992
+ update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8993
+ update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8994
+ update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8995
+ update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8996
end
- attribute \src "libresoc.v:164332.3-164350.6"
- process $proc$libresoc.v:164332$9107
+ attribute \src "libresoc.v:162133.3-162151.6"
+ process $proc$libresoc.v:162133$9021
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9108 $1\o$next[63:0]$9110
+ assign $0\o$next[63:0]$9022 $1\o$next[63:0]$9024
assign { } { }
- assign $0\o_ok$next[0:0]$9109 $2\o_ok$next[0:0]$9112
- attribute \src "libresoc.v:164333.5-164333.29"
+ assign $0\o_ok$next[0:0]$9023 $2\o_ok$next[0:0]$9026
+ attribute \src "libresoc.v:162134.5-162134.29"
switch \initial
- attribute \src "libresoc.v:164333.9-164333.17"
+ attribute \src "libresoc.v:162134.9-162134.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9111 $1\o$next[63:0]$9110 } { \o_ok$89 \o$88 }
+ assign { $1\o_ok$next[0:0]$9025 $1\o$next[63:0]$9024 } { \o_ok$89 \o$88 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9111 $1\o$next[63:0]$9110 } { \o_ok$89 \o$88 }
+ assign { $1\o_ok$next[0:0]$9025 $1\o$next[63:0]$9024 } { \o_ok$89 \o$88 }
case
- assign $1\o$next[63:0]$9110 \o
- assign $1\o_ok$next[0:0]$9111 \o_ok
+ assign $1\o$next[63:0]$9024 \o
+ assign $1\o_ok$next[0:0]$9025 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9112 1'0
+ assign $2\o_ok$next[0:0]$9026 1'0
case
- assign $2\o_ok$next[0:0]$9112 $1\o_ok$next[0:0]$9111
+ assign $2\o_ok$next[0:0]$9026 $1\o_ok$next[0:0]$9025
end
sync always
- update \o$next $0\o$next[63:0]$9108
- update \o_ok$next $0\o_ok$next[0:0]$9109
+ update \o$next $0\o$next[63:0]$9022
+ update \o_ok$next $0\o_ok$next[0:0]$9023
end
- connect \$67 $and$libresoc.v:164013$9002_Y
+ connect \$67 $and$libresoc.v:161814$8916_Y
connect \xer_so_ok$98 1'0
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:164380.1-165802.10"
+attribute \src "libresoc.v:162181.1-163603.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1"
attribute \generator "nMigen"
module \pipe1$110
- attribute \src "libresoc.v:165735.3-165753.6"
- wire width 4 $0\cr_a$next[3:0]$9233
- attribute \src "libresoc.v:165477.3-165478.25"
+ attribute \src "libresoc.v:163536.3-163554.6"
+ wire width 4 $0\cr_a$next[3:0]$9147
+ attribute \src "libresoc.v:163278.3-163279.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:165735.3-165753.6"
- wire $0\cr_a_ok$next[0:0]$9234
- attribute \src "libresoc.v:165479.3-165480.31"
+ attribute \src "libresoc.v:163536.3-163554.6"
+ wire $0\cr_a_ok$next[0:0]$9148
+ attribute \src "libresoc.v:163280.3-163281.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:164381.7-164381.20"
+ attribute \src "libresoc.v:162182.7-162182.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:165662.3-165674.6"
- wire width 2 $0\muxid$next[1:0]$9183
- attribute \src "libresoc.v:165519.3-165520.27"
+ attribute \src "libresoc.v:163463.3-163475.6"
+ wire width 2 $0\muxid$next[1:0]$9097
+ attribute \src "libresoc.v:163320.3-163321.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:165716.3-165734.6"
- wire width 64 $0\o$next[63:0]$9227
- attribute \src "libresoc.v:165481.3-165482.19"
+ attribute \src "libresoc.v:163517.3-163535.6"
+ wire width 64 $0\o$next[63:0]$9141
+ attribute \src "libresoc.v:163282.3-163283.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:165716.3-165734.6"
- wire $0\o_ok$next[0:0]$9228
- attribute \src "libresoc.v:165483.3-165484.25"
+ attribute \src "libresoc.v:163517.3-163535.6"
+ wire $0\o_ok$next[0:0]$9142
+ attribute \src "libresoc.v:163284.3-163285.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:165644.3-165661.6"
- wire $0\r_busy$next[0:0]$9179
- attribute \src "libresoc.v:165521.3-165522.29"
+ attribute \src "libresoc.v:163445.3-163462.6"
+ wire $0\r_busy$next[0:0]$9093
+ attribute \src "libresoc.v:163322.3-163323.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 13 $0\sr_op__fn_unit$next[12:0]$9186
- attribute \src "libresoc.v:165487.3-165488.45"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 13 $0\sr_op__fn_unit$next[12:0]$9100
+ attribute \src "libresoc.v:163288.3-163289.45"
wire width 13 $0\sr_op__fn_unit[12:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 64 $0\sr_op__imm_data__data$next[63:0]$9187
- attribute \src "libresoc.v:165489.3-165490.59"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 64 $0\sr_op__imm_data__data$next[63:0]$9101
+ attribute \src "libresoc.v:163290.3-163291.59"
wire width 64 $0\sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__imm_data__ok$next[0:0]$9188
- attribute \src "libresoc.v:165491.3-165492.55"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__imm_data__ok$next[0:0]$9102
+ attribute \src "libresoc.v:163292.3-163293.55"
wire $0\sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 2 $0\sr_op__input_carry$next[1:0]$9189
- attribute \src "libresoc.v:165505.3-165506.53"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 2 $0\sr_op__input_carry$next[1:0]$9103
+ attribute \src "libresoc.v:163306.3-163307.53"
wire width 2 $0\sr_op__input_carry[1:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__input_cr$next[0:0]$9190
- attribute \src "libresoc.v:165509.3-165510.47"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__input_cr$next[0:0]$9104
+ attribute \src "libresoc.v:163310.3-163311.47"
wire $0\sr_op__input_cr[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 32 $0\sr_op__insn$next[31:0]$9191
- attribute \src "libresoc.v:165517.3-165518.39"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 32 $0\sr_op__insn$next[31:0]$9105
+ attribute \src "libresoc.v:163318.3-163319.39"
wire width 32 $0\sr_op__insn[31:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 7 $0\sr_op__insn_type$next[6:0]$9192
- attribute \src "libresoc.v:165485.3-165486.49"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 7 $0\sr_op__insn_type$next[6:0]$9106
+ attribute \src "libresoc.v:163286.3-163287.49"
wire width 7 $0\sr_op__insn_type[6:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__invert_in$next[0:0]$9193
- attribute \src "libresoc.v:165503.3-165504.49"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__invert_in$next[0:0]$9107
+ attribute \src "libresoc.v:163304.3-163305.49"
wire $0\sr_op__invert_in[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__is_32bit$next[0:0]$9194
- attribute \src "libresoc.v:165513.3-165514.47"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__is_32bit$next[0:0]$9108
+ attribute \src "libresoc.v:163314.3-163315.47"
wire $0\sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__is_signed$next[0:0]$9195
- attribute \src "libresoc.v:165515.3-165516.49"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__is_signed$next[0:0]$9109
+ attribute \src "libresoc.v:163316.3-163317.49"
wire $0\sr_op__is_signed[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__oe__oe$next[0:0]$9196
- attribute \src "libresoc.v:165497.3-165498.43"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__oe__oe$next[0:0]$9110
+ attribute \src "libresoc.v:163298.3-163299.43"
wire $0\sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__oe__ok$next[0:0]$9197
- attribute \src "libresoc.v:165499.3-165500.43"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__oe__ok$next[0:0]$9111
+ attribute \src "libresoc.v:163300.3-163301.43"
wire $0\sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__output_carry$next[0:0]$9198
- attribute \src "libresoc.v:165507.3-165508.55"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__output_carry$next[0:0]$9112
+ attribute \src "libresoc.v:163308.3-163309.55"
wire $0\sr_op__output_carry[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__output_cr$next[0:0]$9199
- attribute \src "libresoc.v:165511.3-165512.49"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__output_cr$next[0:0]$9113
+ attribute \src "libresoc.v:163312.3-163313.49"
wire $0\sr_op__output_cr[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__rc__ok$next[0:0]$9200
- attribute \src "libresoc.v:165495.3-165496.43"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__rc__ok$next[0:0]$9114
+ attribute \src "libresoc.v:163296.3-163297.43"
wire $0\sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__rc__rc$next[0:0]$9201
- attribute \src "libresoc.v:165493.3-165494.43"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__rc__rc$next[0:0]$9115
+ attribute \src "libresoc.v:163294.3-163295.43"
wire $0\sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $0\sr_op__write_cr0$next[0:0]$9202
- attribute \src "libresoc.v:165501.3-165502.49"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $0\sr_op__write_cr0$next[0:0]$9116
+ attribute \src "libresoc.v:163302.3-163303.49"
wire $0\sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:165625.3-165643.6"
- wire width 2 $0\xer_ca$next[1:0]$9174
- attribute \src "libresoc.v:165469.3-165470.29"
+ attribute \src "libresoc.v:163426.3-163444.6"
+ wire width 2 $0\xer_ca$next[1:0]$9088
+ attribute \src "libresoc.v:163270.3-163271.29"
wire width 2 $0\xer_ca[1:0]
- attribute \src "libresoc.v:165625.3-165643.6"
- wire $0\xer_ca_ok$next[0:0]$9173
- attribute \src "libresoc.v:165471.3-165472.35"
+ attribute \src "libresoc.v:163426.3-163444.6"
+ wire $0\xer_ca_ok$next[0:0]$9087
+ attribute \src "libresoc.v:163272.3-163273.35"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:165754.3-165772.6"
- wire $0\xer_so$next[0:0]$9239
- attribute \src "libresoc.v:165473.3-165474.29"
+ attribute \src "libresoc.v:163555.3-163573.6"
+ wire $0\xer_so$next[0:0]$9153
+ attribute \src "libresoc.v:163274.3-163275.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:165754.3-165772.6"
- wire $0\xer_so_ok$next[0:0]$9240
- attribute \src "libresoc.v:165475.3-165476.35"
+ attribute \src "libresoc.v:163555.3-163573.6"
+ wire $0\xer_so_ok$next[0:0]$9154
+ attribute \src "libresoc.v:163276.3-163277.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:165735.3-165753.6"
- wire width 4 $1\cr_a$next[3:0]$9235
- attribute \src "libresoc.v:164390.13-164390.24"
+ attribute \src "libresoc.v:163536.3-163554.6"
+ wire width 4 $1\cr_a$next[3:0]$9149
+ attribute \src "libresoc.v:162191.13-162191.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:165735.3-165753.6"
- wire $1\cr_a_ok$next[0:0]$9236
- attribute \src "libresoc.v:164399.7-164399.21"
+ attribute \src "libresoc.v:163536.3-163554.6"
+ wire $1\cr_a_ok$next[0:0]$9150
+ attribute \src "libresoc.v:162200.7-162200.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:165662.3-165674.6"
- wire width 2 $1\muxid$next[1:0]$9184
- attribute \src "libresoc.v:164956.13-164956.25"
+ attribute \src "libresoc.v:163463.3-163475.6"
+ wire width 2 $1\muxid$next[1:0]$9098
+ attribute \src "libresoc.v:162757.13-162757.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:165716.3-165734.6"
- wire width 64 $1\o$next[63:0]$9229
- attribute \src "libresoc.v:164971.14-164971.38"
+ attribute \src "libresoc.v:163517.3-163535.6"
+ wire width 64 $1\o$next[63:0]$9143
+ attribute \src "libresoc.v:162772.14-162772.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:165716.3-165734.6"
- wire $1\o_ok$next[0:0]$9230
- attribute \src "libresoc.v:164978.7-164978.18"
+ attribute \src "libresoc.v:163517.3-163535.6"
+ wire $1\o_ok$next[0:0]$9144
+ attribute \src "libresoc.v:162779.7-162779.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:165644.3-165661.6"
- wire $1\r_busy$next[0:0]$9180
- attribute \src "libresoc.v:164992.7-164992.20"
+ attribute \src "libresoc.v:163445.3-163462.6"
+ wire $1\r_busy$next[0:0]$9094
+ attribute \src "libresoc.v:162793.7-162793.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 13 $1\sr_op__fn_unit$next[12:0]$9203
- attribute \src "libresoc.v:165017.14-165017.39"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 13 $1\sr_op__fn_unit$next[12:0]$9117
+ attribute \src "libresoc.v:162818.14-162818.39"
wire width 13 $1\sr_op__fn_unit[12:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 64 $1\sr_op__imm_data__data$next[63:0]$9204
- attribute \src "libresoc.v:165054.14-165054.58"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 64 $1\sr_op__imm_data__data$next[63:0]$9118
+ attribute \src "libresoc.v:162855.14-162855.58"
wire width 64 $1\sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__imm_data__ok$next[0:0]$9205
- attribute \src "libresoc.v:165063.7-165063.33"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__imm_data__ok$next[0:0]$9119
+ attribute \src "libresoc.v:162864.7-162864.33"
wire $1\sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 2 $1\sr_op__input_carry$next[1:0]$9206
- attribute \src "libresoc.v:165076.13-165076.38"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 2 $1\sr_op__input_carry$next[1:0]$9120
+ attribute \src "libresoc.v:162877.13-162877.38"
wire width 2 $1\sr_op__input_carry[1:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__input_cr$next[0:0]$9207
- attribute \src "libresoc.v:165093.7-165093.29"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__input_cr$next[0:0]$9121
+ attribute \src "libresoc.v:162894.7-162894.29"
wire $1\sr_op__input_cr[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 32 $1\sr_op__insn$next[31:0]$9208
- attribute \src "libresoc.v:165102.14-165102.33"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 32 $1\sr_op__insn$next[31:0]$9122
+ attribute \src "libresoc.v:162903.14-162903.33"
wire width 32 $1\sr_op__insn[31:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 7 $1\sr_op__insn_type$next[6:0]$9209
- attribute \src "libresoc.v:165185.13-165185.37"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 7 $1\sr_op__insn_type$next[6:0]$9123
+ attribute \src "libresoc.v:162986.13-162986.37"
wire width 7 $1\sr_op__insn_type[6:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__invert_in$next[0:0]$9210
- attribute \src "libresoc.v:165342.7-165342.30"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__invert_in$next[0:0]$9124
+ attribute \src "libresoc.v:163143.7-163143.30"
wire $1\sr_op__invert_in[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__is_32bit$next[0:0]$9211
- attribute \src "libresoc.v:165351.7-165351.29"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__is_32bit$next[0:0]$9125
+ attribute \src "libresoc.v:163152.7-163152.29"
wire $1\sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__is_signed$next[0:0]$9212
- attribute \src "libresoc.v:165360.7-165360.30"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__is_signed$next[0:0]$9126
+ attribute \src "libresoc.v:163161.7-163161.30"
wire $1\sr_op__is_signed[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__oe__oe$next[0:0]$9213
- attribute \src "libresoc.v:165369.7-165369.27"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__oe__oe$next[0:0]$9127
+ attribute \src "libresoc.v:163170.7-163170.27"
wire $1\sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__oe__ok$next[0:0]$9214
- attribute \src "libresoc.v:165378.7-165378.27"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__oe__ok$next[0:0]$9128
+ attribute \src "libresoc.v:163179.7-163179.27"
wire $1\sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__output_carry$next[0:0]$9215
- attribute \src "libresoc.v:165387.7-165387.33"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__output_carry$next[0:0]$9129
+ attribute \src "libresoc.v:163188.7-163188.33"
wire $1\sr_op__output_carry[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__output_cr$next[0:0]$9216
- attribute \src "libresoc.v:165396.7-165396.30"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__output_cr$next[0:0]$9130
+ attribute \src "libresoc.v:163197.7-163197.30"
wire $1\sr_op__output_cr[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__rc__ok$next[0:0]$9217
- attribute \src "libresoc.v:165405.7-165405.27"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__rc__ok$next[0:0]$9131
+ attribute \src "libresoc.v:163206.7-163206.27"
wire $1\sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__rc__rc$next[0:0]$9218
- attribute \src "libresoc.v:165414.7-165414.27"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__rc__rc$next[0:0]$9132
+ attribute \src "libresoc.v:163215.7-163215.27"
wire $1\sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $1\sr_op__write_cr0$next[0:0]$9219
- attribute \src "libresoc.v:165423.7-165423.30"
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $1\sr_op__write_cr0$next[0:0]$9133
+ attribute \src "libresoc.v:163224.7-163224.30"
wire $1\sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:165625.3-165643.6"
- wire width 2 $1\xer_ca$next[1:0]$9176
- attribute \src "libresoc.v:165432.13-165432.26"
+ attribute \src "libresoc.v:163426.3-163444.6"
+ wire width 2 $1\xer_ca$next[1:0]$9090
+ attribute \src "libresoc.v:163233.13-163233.26"
wire width 2 $1\xer_ca[1:0]
- attribute \src "libresoc.v:165625.3-165643.6"
- wire $1\xer_ca_ok$next[0:0]$9175
- attribute \src "libresoc.v:165443.7-165443.23"
+ attribute \src "libresoc.v:163426.3-163444.6"
+ wire $1\xer_ca_ok$next[0:0]$9089
+ attribute \src "libresoc.v:163244.7-163244.23"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:165754.3-165772.6"
- wire $1\xer_so$next[0:0]$9241
- attribute \src "libresoc.v:165452.7-165452.20"
+ attribute \src "libresoc.v:163555.3-163573.6"
+ wire $1\xer_so$next[0:0]$9155
+ attribute \src "libresoc.v:163253.7-163253.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:165754.3-165772.6"
- wire $1\xer_so_ok$next[0:0]$9242
- attribute \src "libresoc.v:165461.7-165461.23"
+ attribute \src "libresoc.v:163555.3-163573.6"
+ wire $1\xer_so_ok$next[0:0]$9156
+ attribute \src "libresoc.v:163262.7-163262.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:165735.3-165753.6"
- wire $2\cr_a_ok$next[0:0]$9237
- attribute \src "libresoc.v:165716.3-165734.6"
- wire $2\o_ok$next[0:0]$9231
- attribute \src "libresoc.v:165644.3-165661.6"
- wire $2\r_busy$next[0:0]$9181
- attribute \src "libresoc.v:165675.3-165715.6"
- wire width 64 $2\sr_op__imm_data__data$next[63:0]$9220
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $2\sr_op__imm_data__ok$next[0:0]$9221
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $2\sr_op__oe__oe$next[0:0]$9222
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $2\sr_op__oe__ok$next[0:0]$9223
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $2\sr_op__rc__ok$next[0:0]$9224
- attribute \src "libresoc.v:165675.3-165715.6"
- wire $2\sr_op__rc__rc$next[0:0]$9225
- attribute \src "libresoc.v:165625.3-165643.6"
- wire $2\xer_ca_ok$next[0:0]$9177
- attribute \src "libresoc.v:165754.3-165772.6"
- wire $2\xer_so_ok$next[0:0]$9243
- attribute \src "libresoc.v:165468.18-165468.118"
- wire $and$libresoc.v:165468$9144_Y
+ attribute \src "libresoc.v:163536.3-163554.6"
+ wire $2\cr_a_ok$next[0:0]$9151
+ attribute \src "libresoc.v:163517.3-163535.6"
+ wire $2\o_ok$next[0:0]$9145
+ attribute \src "libresoc.v:163445.3-163462.6"
+ wire $2\r_busy$next[0:0]$9095
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire width 64 $2\sr_op__imm_data__data$next[63:0]$9134
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $2\sr_op__imm_data__ok$next[0:0]$9135
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $2\sr_op__oe__oe$next[0:0]$9136
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $2\sr_op__oe__ok$next[0:0]$9137
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $2\sr_op__rc__ok$next[0:0]$9138
+ attribute \src "libresoc.v:163476.3-163516.6"
+ wire $2\sr_op__rc__rc$next[0:0]$9139
+ attribute \src "libresoc.v:163426.3-163444.6"
+ wire $2\xer_ca_ok$next[0:0]$9091
+ attribute \src "libresoc.v:163555.3-163573.6"
+ wire $2\xer_so_ok$next[0:0]$9157
+ attribute \src "libresoc.v:163269.18-163269.118"
+ wire $and$libresoc.v:163269$9058_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 55 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 24 \cr_a
wire \cr_a_ok$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$next
- attribute \src "libresoc.v:164381.7-164381.15"
+ attribute \src "libresoc.v:162182.7-162182.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \input_muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:165468$9144
+ cell $and $and$libresoc.v:163269$9058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$64
connect \B \p_ready_o
- connect \Y $and$libresoc.v:165468$9144_Y
+ connect \Y $and$libresoc.v:163269$9058_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165523.15-165570.4"
+ attribute \src "libresoc.v:163324.15-163371.4"
cell \input$113 \input
connect \muxid \input_muxid
connect \muxid$1 \input_muxid$21
connect \xer_so$22 \input_xer_so$42
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165571.14-165616.4"
+ attribute \src "libresoc.v:163372.14-163417.4"
cell \main$114 \main
connect \muxid \main_muxid
connect \muxid$1 \main_muxid$44
connect \xer_so$19 \main_xer_so$62
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165617.11-165620.4"
+ attribute \src "libresoc.v:163418.11-163421.4"
cell \n$112 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:165621.11-165624.4"
+ attribute \src "libresoc.v:163422.11-163425.4"
cell \p$111 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:164381.7-164381.20"
- process $proc$libresoc.v:164381$9244
+ attribute \src "libresoc.v:162182.7-162182.20"
+ process $proc$libresoc.v:162182$9158
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:164390.13-164390.24"
- process $proc$libresoc.v:164390$9245
+ attribute \src "libresoc.v:162191.13-162191.24"
+ process $proc$libresoc.v:162191$9159
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:164399.7-164399.21"
- process $proc$libresoc.v:164399$9246
+ attribute \src "libresoc.v:162200.7-162200.21"
+ process $proc$libresoc.v:162200$9160
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:164956.13-164956.25"
- process $proc$libresoc.v:164956$9247
+ attribute \src "libresoc.v:162757.13-162757.25"
+ process $proc$libresoc.v:162757$9161
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:164971.14-164971.38"
- process $proc$libresoc.v:164971$9248
+ attribute \src "libresoc.v:162772.14-162772.38"
+ process $proc$libresoc.v:162772$9162
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:164978.7-164978.18"
- process $proc$libresoc.v:164978$9249
+ attribute \src "libresoc.v:162779.7-162779.18"
+ process $proc$libresoc.v:162779$9163
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:164992.7-164992.20"
- process $proc$libresoc.v:164992$9250
+ attribute \src "libresoc.v:162793.7-162793.20"
+ process $proc$libresoc.v:162793$9164
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:165017.14-165017.39"
- process $proc$libresoc.v:165017$9251
+ attribute \src "libresoc.v:162818.14-162818.39"
+ process $proc$libresoc.v:162818$9165
assign { } { }
assign $1\sr_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \sr_op__fn_unit $1\sr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:165054.14-165054.58"
- process $proc$libresoc.v:165054$9252
+ attribute \src "libresoc.v:162855.14-162855.58"
+ process $proc$libresoc.v:162855$9166
assign { } { }
assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:165063.7-165063.33"
- process $proc$libresoc.v:165063$9253
+ attribute \src "libresoc.v:162864.7-162864.33"
+ process $proc$libresoc.v:162864$9167
assign { } { }
assign $1\sr_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:165076.13-165076.38"
- process $proc$libresoc.v:165076$9254
+ attribute \src "libresoc.v:162877.13-162877.38"
+ process $proc$libresoc.v:162877$9168
assign { } { }
assign $1\sr_op__input_carry[1:0] 2'00
sync always
sync init
update \sr_op__input_carry $1\sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:165093.7-165093.29"
- process $proc$libresoc.v:165093$9255
+ attribute \src "libresoc.v:162894.7-162894.29"
+ process $proc$libresoc.v:162894$9169
assign { } { }
assign $1\sr_op__input_cr[0:0] 1'0
sync always
sync init
update \sr_op__input_cr $1\sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:165102.14-165102.33"
- process $proc$libresoc.v:165102$9256
+ attribute \src "libresoc.v:162903.14-162903.33"
+ process $proc$libresoc.v:162903$9170
assign { } { }
assign $1\sr_op__insn[31:0] 0
sync always
sync init
update \sr_op__insn $1\sr_op__insn[31:0]
end
- attribute \src "libresoc.v:165185.13-165185.37"
- process $proc$libresoc.v:165185$9257
+ attribute \src "libresoc.v:162986.13-162986.37"
+ process $proc$libresoc.v:162986$9171
assign { } { }
assign $1\sr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \sr_op__insn_type $1\sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:165342.7-165342.30"
- process $proc$libresoc.v:165342$9258
+ attribute \src "libresoc.v:163143.7-163143.30"
+ process $proc$libresoc.v:163143$9172
assign { } { }
assign $1\sr_op__invert_in[0:0] 1'0
sync always
sync init
update \sr_op__invert_in $1\sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:165351.7-165351.29"
- process $proc$libresoc.v:165351$9259
+ attribute \src "libresoc.v:163152.7-163152.29"
+ process $proc$libresoc.v:163152$9173
assign { } { }
assign $1\sr_op__is_32bit[0:0] 1'0
sync always
sync init
update \sr_op__is_32bit $1\sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:165360.7-165360.30"
- process $proc$libresoc.v:165360$9260
+ attribute \src "libresoc.v:163161.7-163161.30"
+ process $proc$libresoc.v:163161$9174
assign { } { }
assign $1\sr_op__is_signed[0:0] 1'0
sync always
sync init
update \sr_op__is_signed $1\sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:165369.7-165369.27"
- process $proc$libresoc.v:165369$9261
+ attribute \src "libresoc.v:163170.7-163170.27"
+ process $proc$libresoc.v:163170$9175
assign { } { }
assign $1\sr_op__oe__oe[0:0] 1'0
sync always
sync init
update \sr_op__oe__oe $1\sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:165378.7-165378.27"
- process $proc$libresoc.v:165378$9262
+ attribute \src "libresoc.v:163179.7-163179.27"
+ process $proc$libresoc.v:163179$9176
assign { } { }
assign $1\sr_op__oe__ok[0:0] 1'0
sync always
sync init
update \sr_op__oe__ok $1\sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:165387.7-165387.33"
- process $proc$libresoc.v:165387$9263
+ attribute \src "libresoc.v:163188.7-163188.33"
+ process $proc$libresoc.v:163188$9177
assign { } { }
assign $1\sr_op__output_carry[0:0] 1'0
sync always
sync init
update \sr_op__output_carry $1\sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:165396.7-165396.30"
- process $proc$libresoc.v:165396$9264
+ attribute \src "libresoc.v:163197.7-163197.30"
+ process $proc$libresoc.v:163197$9178
assign { } { }
assign $1\sr_op__output_cr[0:0] 1'0
sync always
sync init
update \sr_op__output_cr $1\sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:165405.7-165405.27"
- process $proc$libresoc.v:165405$9265
+ attribute \src "libresoc.v:163206.7-163206.27"
+ process $proc$libresoc.v:163206$9179
assign { } { }
assign $1\sr_op__rc__ok[0:0] 1'0
sync always
sync init
update \sr_op__rc__ok $1\sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:165414.7-165414.27"
- process $proc$libresoc.v:165414$9266
+ attribute \src "libresoc.v:163215.7-163215.27"
+ process $proc$libresoc.v:163215$9180
assign { } { }
assign $1\sr_op__rc__rc[0:0] 1'0
sync always
sync init
update \sr_op__rc__rc $1\sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:165423.7-165423.30"
- process $proc$libresoc.v:165423$9267
+ attribute \src "libresoc.v:163224.7-163224.30"
+ process $proc$libresoc.v:163224$9181
assign { } { }
assign $1\sr_op__write_cr0[0:0] 1'0
sync always
sync init
update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:165432.13-165432.26"
- process $proc$libresoc.v:165432$9268
+ attribute \src "libresoc.v:163233.13-163233.26"
+ process $proc$libresoc.v:163233$9182
assign { } { }
assign $1\xer_ca[1:0] 2'00
sync always
sync init
update \xer_ca $1\xer_ca[1:0]
end
- attribute \src "libresoc.v:165443.7-165443.23"
- process $proc$libresoc.v:165443$9269
+ attribute \src "libresoc.v:163244.7-163244.23"
+ process $proc$libresoc.v:163244$9183
assign { } { }
assign $1\xer_ca_ok[0:0] 1'0
sync always
sync init
update \xer_ca_ok $1\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:165452.7-165452.20"
- process $proc$libresoc.v:165452$9270
+ attribute \src "libresoc.v:163253.7-163253.20"
+ process $proc$libresoc.v:163253$9184
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:165461.7-165461.23"
- process $proc$libresoc.v:165461$9271
+ attribute \src "libresoc.v:163262.7-163262.23"
+ process $proc$libresoc.v:163262$9185
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:165469.3-165470.29"
- process $proc$libresoc.v:165469$9145
+ attribute \src "libresoc.v:163270.3-163271.29"
+ process $proc$libresoc.v:163270$9059
assign { } { }
assign $0\xer_ca[1:0] \xer_ca$next
sync posedge \coresync_clk
update \xer_ca $0\xer_ca[1:0]
end
- attribute \src "libresoc.v:165471.3-165472.35"
- process $proc$libresoc.v:165471$9146
+ attribute \src "libresoc.v:163272.3-163273.35"
+ process $proc$libresoc.v:163272$9060
assign { } { }
assign $0\xer_ca_ok[0:0] \xer_ca_ok$next
sync posedge \coresync_clk
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:165473.3-165474.29"
- process $proc$libresoc.v:165473$9147
+ attribute \src "libresoc.v:163274.3-163275.29"
+ process $proc$libresoc.v:163274$9061
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:165475.3-165476.35"
- process $proc$libresoc.v:165475$9148
+ attribute \src "libresoc.v:163276.3-163277.35"
+ process $proc$libresoc.v:163276$9062
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:165477.3-165478.25"
- process $proc$libresoc.v:165477$9149
+ attribute \src "libresoc.v:163278.3-163279.25"
+ process $proc$libresoc.v:163278$9063
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:165479.3-165480.31"
- process $proc$libresoc.v:165479$9150
+ attribute \src "libresoc.v:163280.3-163281.31"
+ process $proc$libresoc.v:163280$9064
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:165481.3-165482.19"
- process $proc$libresoc.v:165481$9151
+ attribute \src "libresoc.v:163282.3-163283.19"
+ process $proc$libresoc.v:163282$9065
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:165483.3-165484.25"
- process $proc$libresoc.v:165483$9152
+ attribute \src "libresoc.v:163284.3-163285.25"
+ process $proc$libresoc.v:163284$9066
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:165485.3-165486.49"
- process $proc$libresoc.v:165485$9153
+ attribute \src "libresoc.v:163286.3-163287.49"
+ process $proc$libresoc.v:163286$9067
assign { } { }
assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next
sync posedge \coresync_clk
update \sr_op__insn_type $0\sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:165487.3-165488.45"
- process $proc$libresoc.v:165487$9154
+ attribute \src "libresoc.v:163288.3-163289.45"
+ process $proc$libresoc.v:163288$9068
assign { } { }
assign $0\sr_op__fn_unit[12:0] \sr_op__fn_unit$next
sync posedge \coresync_clk
update \sr_op__fn_unit $0\sr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:165489.3-165490.59"
- process $proc$libresoc.v:165489$9155
+ attribute \src "libresoc.v:163290.3-163291.59"
+ process $proc$libresoc.v:163290$9069
assign { } { }
assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next
sync posedge \coresync_clk
update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:165491.3-165492.55"
- process $proc$libresoc.v:165491$9156
+ attribute \src "libresoc.v:163292.3-163293.55"
+ process $proc$libresoc.v:163292$9070
assign { } { }
assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next
sync posedge \coresync_clk
update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:165493.3-165494.43"
- process $proc$libresoc.v:165493$9157
+ attribute \src "libresoc.v:163294.3-163295.43"
+ process $proc$libresoc.v:163294$9071
assign { } { }
assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next
sync posedge \coresync_clk
update \sr_op__rc__rc $0\sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:165495.3-165496.43"
- process $proc$libresoc.v:165495$9158
+ attribute \src "libresoc.v:163296.3-163297.43"
+ process $proc$libresoc.v:163296$9072
assign { } { }
assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next
sync posedge \coresync_clk
update \sr_op__rc__ok $0\sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:165497.3-165498.43"
- process $proc$libresoc.v:165497$9159
+ attribute \src "libresoc.v:163298.3-163299.43"
+ process $proc$libresoc.v:163298$9073
assign { } { }
assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next
sync posedge \coresync_clk
update \sr_op__oe__oe $0\sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:165499.3-165500.43"
- process $proc$libresoc.v:165499$9160
+ attribute \src "libresoc.v:163300.3-163301.43"
+ process $proc$libresoc.v:163300$9074
assign { } { }
assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next
sync posedge \coresync_clk
update \sr_op__oe__ok $0\sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:165501.3-165502.49"
- process $proc$libresoc.v:165501$9161
+ attribute \src "libresoc.v:163302.3-163303.49"
+ process $proc$libresoc.v:163302$9075
assign { } { }
assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next
sync posedge \coresync_clk
update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:165503.3-165504.49"
- process $proc$libresoc.v:165503$9162
+ attribute \src "libresoc.v:163304.3-163305.49"
+ process $proc$libresoc.v:163304$9076
assign { } { }
assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next
sync posedge \coresync_clk
update \sr_op__invert_in $0\sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:165505.3-165506.53"
- process $proc$libresoc.v:165505$9163
+ attribute \src "libresoc.v:163306.3-163307.53"
+ process $proc$libresoc.v:163306$9077
assign { } { }
assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next
sync posedge \coresync_clk
update \sr_op__input_carry $0\sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:165507.3-165508.55"
- process $proc$libresoc.v:165507$9164
+ attribute \src "libresoc.v:163308.3-163309.55"
+ process $proc$libresoc.v:163308$9078
assign { } { }
assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next
sync posedge \coresync_clk
update \sr_op__output_carry $0\sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:165509.3-165510.47"
- process $proc$libresoc.v:165509$9165
+ attribute \src "libresoc.v:163310.3-163311.47"
+ process $proc$libresoc.v:163310$9079
assign { } { }
assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next
sync posedge \coresync_clk
update \sr_op__input_cr $0\sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:165511.3-165512.49"
- process $proc$libresoc.v:165511$9166
+ attribute \src "libresoc.v:163312.3-163313.49"
+ process $proc$libresoc.v:163312$9080
assign { } { }
assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next
sync posedge \coresync_clk
update \sr_op__output_cr $0\sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:165513.3-165514.47"
- process $proc$libresoc.v:165513$9167
+ attribute \src "libresoc.v:163314.3-163315.47"
+ process $proc$libresoc.v:163314$9081
assign { } { }
assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next
sync posedge \coresync_clk
update \sr_op__is_32bit $0\sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:165515.3-165516.49"
- process $proc$libresoc.v:165515$9168
+ attribute \src "libresoc.v:163316.3-163317.49"
+ process $proc$libresoc.v:163316$9082
assign { } { }
assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next
sync posedge \coresync_clk
update \sr_op__is_signed $0\sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:165517.3-165518.39"
- process $proc$libresoc.v:165517$9169
+ attribute \src "libresoc.v:163318.3-163319.39"
+ process $proc$libresoc.v:163318$9083
assign { } { }
assign $0\sr_op__insn[31:0] \sr_op__insn$next
sync posedge \coresync_clk
update \sr_op__insn $0\sr_op__insn[31:0]
end
- attribute \src "libresoc.v:165519.3-165520.27"
- process $proc$libresoc.v:165519$9170
+ attribute \src "libresoc.v:163320.3-163321.27"
+ process $proc$libresoc.v:163320$9084
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:165521.3-165522.29"
- process $proc$libresoc.v:165521$9171
+ attribute \src "libresoc.v:163322.3-163323.29"
+ process $proc$libresoc.v:163322$9085
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:165625.3-165643.6"
- process $proc$libresoc.v:165625$9172
+ attribute \src "libresoc.v:163426.3-163444.6"
+ process $proc$libresoc.v:163426$9086
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$next[1:0]$9174 $1\xer_ca$next[1:0]$9176
- assign $0\xer_ca_ok$next[0:0]$9173 $2\xer_ca_ok$next[0:0]$9177
- attribute \src "libresoc.v:165626.5-165626.29"
+ assign $0\xer_ca$next[1:0]$9088 $1\xer_ca$next[1:0]$9090
+ assign $0\xer_ca_ok$next[0:0]$9087 $2\xer_ca_ok$next[0:0]$9091
+ attribute \src "libresoc.v:163427.5-163427.29"
switch \initial
- attribute \src "libresoc.v:165626.9-165626.17"
+ attribute \src "libresoc.v:163427.9-163427.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9175 $1\xer_ca$next[1:0]$9176 } { \xer_ca_ok$95 \xer_ca$94 }
+ assign { $1\xer_ca_ok$next[0:0]$9089 $1\xer_ca$next[1:0]$9090 } { \xer_ca_ok$95 \xer_ca$94 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$next[0:0]$9175 $1\xer_ca$next[1:0]$9176 } { \xer_ca_ok$95 \xer_ca$94 }
+ assign { $1\xer_ca_ok$next[0:0]$9089 $1\xer_ca$next[1:0]$9090 } { \xer_ca_ok$95 \xer_ca$94 }
case
- assign $1\xer_ca_ok$next[0:0]$9175 \xer_ca_ok
- assign $1\xer_ca$next[1:0]$9176 \xer_ca
+ assign $1\xer_ca_ok$next[0:0]$9089 \xer_ca_ok
+ assign $1\xer_ca$next[1:0]$9090 \xer_ca
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$next[0:0]$9177 1'0
+ assign $2\xer_ca_ok$next[0:0]$9091 1'0
case
- assign $2\xer_ca_ok$next[0:0]$9177 $1\xer_ca_ok$next[0:0]$9175
+ assign $2\xer_ca_ok$next[0:0]$9091 $1\xer_ca_ok$next[0:0]$9089
end
sync always
- update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9173
- update \xer_ca$next $0\xer_ca$next[1:0]$9174
+ update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9087
+ update \xer_ca$next $0\xer_ca$next[1:0]$9088
end
- attribute \src "libresoc.v:165644.3-165661.6"
- process $proc$libresoc.v:165644$9178
+ attribute \src "libresoc.v:163445.3-163462.6"
+ process $proc$libresoc.v:163445$9092
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9179 $2\r_busy$next[0:0]$9181
- attribute \src "libresoc.v:165645.5-165645.29"
+ assign $0\r_busy$next[0:0]$9093 $2\r_busy$next[0:0]$9095
+ attribute \src "libresoc.v:163446.5-163446.29"
switch \initial
- attribute \src "libresoc.v:165645.9-165645.17"
+ attribute \src "libresoc.v:163446.9-163446.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9180 1'1
+ assign $1\r_busy$next[0:0]$9094 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9180 1'0
+ assign $1\r_busy$next[0:0]$9094 1'0
case
- assign $1\r_busy$next[0:0]$9180 \r_busy
+ assign $1\r_busy$next[0:0]$9094 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9181 1'0
+ assign $2\r_busy$next[0:0]$9095 1'0
case
- assign $2\r_busy$next[0:0]$9181 $1\r_busy$next[0:0]$9180
+ assign $2\r_busy$next[0:0]$9095 $1\r_busy$next[0:0]$9094
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9179
+ update \r_busy$next $0\r_busy$next[0:0]$9093
end
- attribute \src "libresoc.v:165662.3-165674.6"
- process $proc$libresoc.v:165662$9182
+ attribute \src "libresoc.v:163463.3-163475.6"
+ process $proc$libresoc.v:163463$9096
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9183 $1\muxid$next[1:0]$9184
- attribute \src "libresoc.v:165663.5-165663.29"
+ assign $0\muxid$next[1:0]$9097 $1\muxid$next[1:0]$9098
+ attribute \src "libresoc.v:163464.5-163464.29"
switch \initial
- attribute \src "libresoc.v:165663.9-165663.17"
+ attribute \src "libresoc.v:163464.9-163464.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9184 \muxid$67
+ assign $1\muxid$next[1:0]$9098 \muxid$67
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9184 \muxid$67
+ assign $1\muxid$next[1:0]$9098 \muxid$67
case
- assign $1\muxid$next[1:0]$9184 \muxid
+ assign $1\muxid$next[1:0]$9098 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9183
+ update \muxid$next $0\muxid$next[1:0]$9097
end
- attribute \src "libresoc.v:165675.3-165715.6"
- process $proc$libresoc.v:165675$9185
+ attribute \src "libresoc.v:163476.3-163516.6"
+ process $proc$libresoc.v:163476$9099
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr_op__fn_unit$next[12:0]$9186 $1\sr_op__fn_unit$next[12:0]$9203
+ assign $0\sr_op__fn_unit$next[12:0]$9100 $1\sr_op__fn_unit$next[12:0]$9117
assign { } { }
assign { } { }
- assign $0\sr_op__input_carry$next[1:0]$9189 $1\sr_op__input_carry$next[1:0]$9206
- assign $0\sr_op__input_cr$next[0:0]$9190 $1\sr_op__input_cr$next[0:0]$9207
- assign $0\sr_op__insn$next[31:0]$9191 $1\sr_op__insn$next[31:0]$9208
- assign $0\sr_op__insn_type$next[6:0]$9192 $1\sr_op__insn_type$next[6:0]$9209
- assign $0\sr_op__invert_in$next[0:0]$9193 $1\sr_op__invert_in$next[0:0]$9210
- assign $0\sr_op__is_32bit$next[0:0]$9194 $1\sr_op__is_32bit$next[0:0]$9211
- assign $0\sr_op__is_signed$next[0:0]$9195 $1\sr_op__is_signed$next[0:0]$9212
+ assign $0\sr_op__input_carry$next[1:0]$9103 $1\sr_op__input_carry$next[1:0]$9120
+ assign $0\sr_op__input_cr$next[0:0]$9104 $1\sr_op__input_cr$next[0:0]$9121
+ assign $0\sr_op__insn$next[31:0]$9105 $1\sr_op__insn$next[31:0]$9122
+ assign $0\sr_op__insn_type$next[6:0]$9106 $1\sr_op__insn_type$next[6:0]$9123
+ assign $0\sr_op__invert_in$next[0:0]$9107 $1\sr_op__invert_in$next[0:0]$9124
+ assign $0\sr_op__is_32bit$next[0:0]$9108 $1\sr_op__is_32bit$next[0:0]$9125
+ assign $0\sr_op__is_signed$next[0:0]$9109 $1\sr_op__is_signed$next[0:0]$9126
assign { } { }
assign { } { }
- assign $0\sr_op__output_carry$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9215
- assign $0\sr_op__output_cr$next[0:0]$9199 $1\sr_op__output_cr$next[0:0]$9216
+ assign $0\sr_op__output_carry$next[0:0]$9112 $1\sr_op__output_carry$next[0:0]$9129
+ assign $0\sr_op__output_cr$next[0:0]$9113 $1\sr_op__output_cr$next[0:0]$9130
assign { } { }
assign { } { }
- assign $0\sr_op__write_cr0$next[0:0]$9202 $1\sr_op__write_cr0$next[0:0]$9219
- assign $0\sr_op__imm_data__data$next[63:0]$9187 $2\sr_op__imm_data__data$next[63:0]$9220
- assign $0\sr_op__imm_data__ok$next[0:0]$9188 $2\sr_op__imm_data__ok$next[0:0]$9221
- assign $0\sr_op__oe__oe$next[0:0]$9196 $2\sr_op__oe__oe$next[0:0]$9222
- assign $0\sr_op__oe__ok$next[0:0]$9197 $2\sr_op__oe__ok$next[0:0]$9223
- assign $0\sr_op__rc__ok$next[0:0]$9200 $2\sr_op__rc__ok$next[0:0]$9224
- assign $0\sr_op__rc__rc$next[0:0]$9201 $2\sr_op__rc__rc$next[0:0]$9225
- attribute \src "libresoc.v:165676.5-165676.29"
+ assign $0\sr_op__write_cr0$next[0:0]$9116 $1\sr_op__write_cr0$next[0:0]$9133
+ assign $0\sr_op__imm_data__data$next[63:0]$9101 $2\sr_op__imm_data__data$next[63:0]$9134
+ assign $0\sr_op__imm_data__ok$next[0:0]$9102 $2\sr_op__imm_data__ok$next[0:0]$9135
+ assign $0\sr_op__oe__oe$next[0:0]$9110 $2\sr_op__oe__oe$next[0:0]$9136
+ assign $0\sr_op__oe__ok$next[0:0]$9111 $2\sr_op__oe__ok$next[0:0]$9137
+ assign $0\sr_op__rc__ok$next[0:0]$9114 $2\sr_op__rc__ok$next[0:0]$9138
+ assign $0\sr_op__rc__rc$next[0:0]$9115 $2\sr_op__rc__rc$next[0:0]$9139
+ attribute \src "libresoc.v:163477.5-163477.29"
switch \initial
- attribute \src "libresoc.v:165676.9-165676.17"
+ attribute \src "libresoc.v:163477.9-163477.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$next[31:0]$9208 $1\sr_op__is_signed$next[0:0]$9212 $1\sr_op__is_32bit$next[0:0]$9211 $1\sr_op__output_cr$next[0:0]$9216 $1\sr_op__input_cr$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9215 $1\sr_op__input_carry$next[1:0]$9206 $1\sr_op__invert_in$next[0:0]$9210 $1\sr_op__write_cr0$next[0:0]$9219 $1\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__rc__ok$next[0:0]$9217 $1\sr_op__rc__rc$next[0:0]$9218 $1\sr_op__imm_data__ok$next[0:0]$9205 $1\sr_op__imm_data__data$next[63:0]$9204 $1\sr_op__fn_unit$next[12:0]$9203 $1\sr_op__insn_type$next[6:0]$9209 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
+ assign { $1\sr_op__insn$next[31:0]$9122 $1\sr_op__is_signed$next[0:0]$9126 $1\sr_op__is_32bit$next[0:0]$9125 $1\sr_op__output_cr$next[0:0]$9130 $1\sr_op__input_cr$next[0:0]$9121 $1\sr_op__output_carry$next[0:0]$9129 $1\sr_op__input_carry$next[1:0]$9120 $1\sr_op__invert_in$next[0:0]$9124 $1\sr_op__write_cr0$next[0:0]$9133 $1\sr_op__oe__ok$next[0:0]$9128 $1\sr_op__oe__oe$next[0:0]$9127 $1\sr_op__rc__ok$next[0:0]$9131 $1\sr_op__rc__rc$next[0:0]$9132 $1\sr_op__imm_data__ok$next[0:0]$9119 $1\sr_op__imm_data__data$next[63:0]$9118 $1\sr_op__fn_unit$next[12:0]$9117 $1\sr_op__insn_type$next[6:0]$9123 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$next[31:0]$9208 $1\sr_op__is_signed$next[0:0]$9212 $1\sr_op__is_32bit$next[0:0]$9211 $1\sr_op__output_cr$next[0:0]$9216 $1\sr_op__input_cr$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9215 $1\sr_op__input_carry$next[1:0]$9206 $1\sr_op__invert_in$next[0:0]$9210 $1\sr_op__write_cr0$next[0:0]$9219 $1\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__rc__ok$next[0:0]$9217 $1\sr_op__rc__rc$next[0:0]$9218 $1\sr_op__imm_data__ok$next[0:0]$9205 $1\sr_op__imm_data__data$next[63:0]$9204 $1\sr_op__fn_unit$next[12:0]$9203 $1\sr_op__insn_type$next[6:0]$9209 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
+ assign { $1\sr_op__insn$next[31:0]$9122 $1\sr_op__is_signed$next[0:0]$9126 $1\sr_op__is_32bit$next[0:0]$9125 $1\sr_op__output_cr$next[0:0]$9130 $1\sr_op__input_cr$next[0:0]$9121 $1\sr_op__output_carry$next[0:0]$9129 $1\sr_op__input_carry$next[1:0]$9120 $1\sr_op__invert_in$next[0:0]$9124 $1\sr_op__write_cr0$next[0:0]$9133 $1\sr_op__oe__ok$next[0:0]$9128 $1\sr_op__oe__oe$next[0:0]$9127 $1\sr_op__rc__ok$next[0:0]$9131 $1\sr_op__rc__rc$next[0:0]$9132 $1\sr_op__imm_data__ok$next[0:0]$9119 $1\sr_op__imm_data__data$next[63:0]$9118 $1\sr_op__fn_unit$next[12:0]$9117 $1\sr_op__insn_type$next[6:0]$9123 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 }
case
- assign $1\sr_op__fn_unit$next[12:0]$9203 \sr_op__fn_unit
- assign $1\sr_op__imm_data__data$next[63:0]$9204 \sr_op__imm_data__data
- assign $1\sr_op__imm_data__ok$next[0:0]$9205 \sr_op__imm_data__ok
- assign $1\sr_op__input_carry$next[1:0]$9206 \sr_op__input_carry
- assign $1\sr_op__input_cr$next[0:0]$9207 \sr_op__input_cr
- assign $1\sr_op__insn$next[31:0]$9208 \sr_op__insn
- assign $1\sr_op__insn_type$next[6:0]$9209 \sr_op__insn_type
- assign $1\sr_op__invert_in$next[0:0]$9210 \sr_op__invert_in
- assign $1\sr_op__is_32bit$next[0:0]$9211 \sr_op__is_32bit
- assign $1\sr_op__is_signed$next[0:0]$9212 \sr_op__is_signed
- assign $1\sr_op__oe__oe$next[0:0]$9213 \sr_op__oe__oe
- assign $1\sr_op__oe__ok$next[0:0]$9214 \sr_op__oe__ok
- assign $1\sr_op__output_carry$next[0:0]$9215 \sr_op__output_carry
- assign $1\sr_op__output_cr$next[0:0]$9216 \sr_op__output_cr
- assign $1\sr_op__rc__ok$next[0:0]$9217 \sr_op__rc__ok
- assign $1\sr_op__rc__rc$next[0:0]$9218 \sr_op__rc__rc
- assign $1\sr_op__write_cr0$next[0:0]$9219 \sr_op__write_cr0
+ assign $1\sr_op__fn_unit$next[12:0]$9117 \sr_op__fn_unit
+ assign $1\sr_op__imm_data__data$next[63:0]$9118 \sr_op__imm_data__data
+ assign $1\sr_op__imm_data__ok$next[0:0]$9119 \sr_op__imm_data__ok
+ assign $1\sr_op__input_carry$next[1:0]$9120 \sr_op__input_carry
+ assign $1\sr_op__input_cr$next[0:0]$9121 \sr_op__input_cr
+ assign $1\sr_op__insn$next[31:0]$9122 \sr_op__insn
+ assign $1\sr_op__insn_type$next[6:0]$9123 \sr_op__insn_type
+ assign $1\sr_op__invert_in$next[0:0]$9124 \sr_op__invert_in
+ assign $1\sr_op__is_32bit$next[0:0]$9125 \sr_op__is_32bit
+ assign $1\sr_op__is_signed$next[0:0]$9126 \sr_op__is_signed
+ assign $1\sr_op__oe__oe$next[0:0]$9127 \sr_op__oe__oe
+ assign $1\sr_op__oe__ok$next[0:0]$9128 \sr_op__oe__ok
+ assign $1\sr_op__output_carry$next[0:0]$9129 \sr_op__output_carry
+ assign $1\sr_op__output_cr$next[0:0]$9130 \sr_op__output_cr
+ assign $1\sr_op__rc__ok$next[0:0]$9131 \sr_op__rc__ok
+ assign $1\sr_op__rc__rc$next[0:0]$9132 \sr_op__rc__rc
+ assign $1\sr_op__write_cr0$next[0:0]$9133 \sr_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\sr_op__imm_data__data$next[63:0]$9220 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\sr_op__imm_data__ok$next[0:0]$9221 1'0
- assign $2\sr_op__rc__rc$next[0:0]$9225 1'0
- assign $2\sr_op__rc__ok$next[0:0]$9224 1'0
- assign $2\sr_op__oe__oe$next[0:0]$9222 1'0
- assign $2\sr_op__oe__ok$next[0:0]$9223 1'0
+ assign $2\sr_op__imm_data__data$next[63:0]$9134 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sr_op__imm_data__ok$next[0:0]$9135 1'0
+ assign $2\sr_op__rc__rc$next[0:0]$9139 1'0
+ assign $2\sr_op__rc__ok$next[0:0]$9138 1'0
+ assign $2\sr_op__oe__oe$next[0:0]$9136 1'0
+ assign $2\sr_op__oe__ok$next[0:0]$9137 1'0
case
- assign $2\sr_op__imm_data__data$next[63:0]$9220 $1\sr_op__imm_data__data$next[63:0]$9204
- assign $2\sr_op__imm_data__ok$next[0:0]$9221 $1\sr_op__imm_data__ok$next[0:0]$9205
- assign $2\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__oe__oe$next[0:0]$9213
- assign $2\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__ok$next[0:0]$9214
- assign $2\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__ok$next[0:0]$9217
- assign $2\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__rc__rc$next[0:0]$9218
+ assign $2\sr_op__imm_data__data$next[63:0]$9134 $1\sr_op__imm_data__data$next[63:0]$9118
+ assign $2\sr_op__imm_data__ok$next[0:0]$9135 $1\sr_op__imm_data__ok$next[0:0]$9119
+ assign $2\sr_op__oe__oe$next[0:0]$9136 $1\sr_op__oe__oe$next[0:0]$9127
+ assign $2\sr_op__oe__ok$next[0:0]$9137 $1\sr_op__oe__ok$next[0:0]$9128
+ assign $2\sr_op__rc__ok$next[0:0]$9138 $1\sr_op__rc__ok$next[0:0]$9131
+ assign $2\sr_op__rc__rc$next[0:0]$9139 $1\sr_op__rc__rc$next[0:0]$9132
end
sync always
- update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9186
- update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9187
- update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9188
- update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9189
- update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9190
- update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9191
- update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9192
- update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9193
- update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9194
- update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9195
- update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9196
- update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9197
- update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9198
- update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9199
- update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9200
- update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9201
- update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9202
+ update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9100
+ update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9101
+ update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9102
+ update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9103
+ update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9104
+ update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9105
+ update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9106
+ update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9107
+ update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9108
+ update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9109
+ update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9110
+ update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9111
+ update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9112
+ update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9113
+ update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9114
+ update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9115
+ update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9116
end
- attribute \src "libresoc.v:165716.3-165734.6"
- process $proc$libresoc.v:165716$9226
+ attribute \src "libresoc.v:163517.3-163535.6"
+ process $proc$libresoc.v:163517$9140
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9227 $1\o$next[63:0]$9229
+ assign $0\o$next[63:0]$9141 $1\o$next[63:0]$9143
assign { } { }
- assign $0\o_ok$next[0:0]$9228 $2\o_ok$next[0:0]$9231
- attribute \src "libresoc.v:165717.5-165717.29"
+ assign $0\o_ok$next[0:0]$9142 $2\o_ok$next[0:0]$9145
+ attribute \src "libresoc.v:163518.5-163518.29"
switch \initial
- attribute \src "libresoc.v:165717.9-165717.17"
+ attribute \src "libresoc.v:163518.9-163518.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9230 $1\o$next[63:0]$9229 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$9144 $1\o$next[63:0]$9143 } { \o_ok$86 \o$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9230 $1\o$next[63:0]$9229 } { \o_ok$86 \o$85 }
+ assign { $1\o_ok$next[0:0]$9144 $1\o$next[63:0]$9143 } { \o_ok$86 \o$85 }
case
- assign $1\o$next[63:0]$9229 \o
- assign $1\o_ok$next[0:0]$9230 \o_ok
+ assign $1\o$next[63:0]$9143 \o
+ assign $1\o_ok$next[0:0]$9144 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9231 1'0
+ assign $2\o_ok$next[0:0]$9145 1'0
case
- assign $2\o_ok$next[0:0]$9231 $1\o_ok$next[0:0]$9230
+ assign $2\o_ok$next[0:0]$9145 $1\o_ok$next[0:0]$9144
end
sync always
- update \o$next $0\o$next[63:0]$9227
- update \o_ok$next $0\o_ok$next[0:0]$9228
+ update \o$next $0\o$next[63:0]$9141
+ update \o_ok$next $0\o_ok$next[0:0]$9142
end
- attribute \src "libresoc.v:165735.3-165753.6"
- process $proc$libresoc.v:165735$9232
+ attribute \src "libresoc.v:163536.3-163554.6"
+ process $proc$libresoc.v:163536$9146
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9233 $1\cr_a$next[3:0]$9235
+ assign $0\cr_a$next[3:0]$9147 $1\cr_a$next[3:0]$9149
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9234 $2\cr_a_ok$next[0:0]$9237
- attribute \src "libresoc.v:165736.5-165736.29"
+ assign $0\cr_a_ok$next[0:0]$9148 $2\cr_a_ok$next[0:0]$9151
+ attribute \src "libresoc.v:163537.5-163537.29"
switch \initial
- attribute \src "libresoc.v:165736.9-165736.17"
+ attribute \src "libresoc.v:163537.9-163537.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9236 $1\cr_a$next[3:0]$9235 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$9150 $1\cr_a$next[3:0]$9149 } { \cr_a_ok$88 \cr_a$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9236 $1\cr_a$next[3:0]$9235 } { \cr_a_ok$88 \cr_a$87 }
+ assign { $1\cr_a_ok$next[0:0]$9150 $1\cr_a$next[3:0]$9149 } { \cr_a_ok$88 \cr_a$87 }
case
- assign $1\cr_a$next[3:0]$9235 \cr_a
- assign $1\cr_a_ok$next[0:0]$9236 \cr_a_ok
+ assign $1\cr_a$next[3:0]$9149 \cr_a
+ assign $1\cr_a_ok$next[0:0]$9150 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9237 1'0
+ assign $2\cr_a_ok$next[0:0]$9151 1'0
case
- assign $2\cr_a_ok$next[0:0]$9237 $1\cr_a_ok$next[0:0]$9236
+ assign $2\cr_a_ok$next[0:0]$9151 $1\cr_a_ok$next[0:0]$9150
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9233
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9234
+ update \cr_a$next $0\cr_a$next[3:0]$9147
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9148
end
- attribute \src "libresoc.v:165754.3-165772.6"
- process $proc$libresoc.v:165754$9238
+ attribute \src "libresoc.v:163555.3-163573.6"
+ process $proc$libresoc.v:163555$9152
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$9239 $1\xer_so$next[0:0]$9241
+ assign $0\xer_so$next[0:0]$9153 $1\xer_so$next[0:0]$9155
assign { } { }
- assign $0\xer_so_ok$next[0:0]$9240 $2\xer_so_ok$next[0:0]$9243
- attribute \src "libresoc.v:165755.5-165755.29"
+ assign $0\xer_so_ok$next[0:0]$9154 $2\xer_so_ok$next[0:0]$9157
+ attribute \src "libresoc.v:163556.5-163556.29"
switch \initial
- attribute \src "libresoc.v:165755.9-165755.17"
+ attribute \src "libresoc.v:163556.9-163556.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9242 $1\xer_so$next[0:0]$9241 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$9156 $1\xer_so$next[0:0]$9155 } { \xer_so_ok$92 \xer_so$91 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9242 $1\xer_so$next[0:0]$9241 } { \xer_so_ok$92 \xer_so$91 }
+ assign { $1\xer_so_ok$next[0:0]$9156 $1\xer_so$next[0:0]$9155 } { \xer_so_ok$92 \xer_so$91 }
case
- assign $1\xer_so$next[0:0]$9241 \xer_so
- assign $1\xer_so_ok$next[0:0]$9242 \xer_so_ok
+ assign $1\xer_so$next[0:0]$9155 \xer_so
+ assign $1\xer_so_ok$next[0:0]$9156 \xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9243 1'0
+ assign $2\xer_so_ok$next[0:0]$9157 1'0
case
- assign $2\xer_so_ok$next[0:0]$9243 $1\xer_so_ok$next[0:0]$9242
+ assign $2\xer_so_ok$next[0:0]$9157 $1\xer_so_ok$next[0:0]$9156
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$9239
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9240
+ update \xer_so$next $0\xer_so$next[0:0]$9153
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9154
end
- connect \$65 $and$libresoc.v:165468$9144_Y
+ connect \$65 $and$libresoc.v:163269$9058_Y
connect \cr_a$89 4'0000
connect \cr_a_ok$90 1'0
connect \xer_so_ok$93 1'0
connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 }
connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:165806.1-166644.10"
+attribute \src "libresoc.v:163607.1-164445.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1"
attribute \generator "nMigen"
module \pipe1$32
- attribute \src "libresoc.v:166601.3-166613.6"
- wire width 64 $0\fast1$next[63:0]$9321
- attribute \src "libresoc.v:166457.3-166458.27"
+ attribute \src "libresoc.v:164402.3-164414.6"
+ wire width 64 $0\fast1$next[63:0]$9235
+ attribute \src "libresoc.v:164258.3-164259.27"
wire width 64 $0\fast1[63:0]
- attribute \src "libresoc.v:166614.3-166626.6"
- wire width 64 $0\fast2$next[63:0]$9324
- attribute \src "libresoc.v:166455.3-166456.27"
+ attribute \src "libresoc.v:164415.3-164427.6"
+ wire width 64 $0\fast2$next[63:0]$9238
+ attribute \src "libresoc.v:164256.3-164257.27"
wire width 64 $0\fast2[63:0]
- attribute \src "libresoc.v:165807.7-165807.20"
+ attribute \src "libresoc.v:163608.7-163608.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:166541.3-166553.6"
- wire width 2 $0\muxid$next[1:0]$9293
- attribute \src "libresoc.v:166481.3-166482.27"
+ attribute \src "libresoc.v:164342.3-164354.6"
+ wire width 2 $0\muxid$next[1:0]$9207
+ attribute \src "libresoc.v:164282.3-164283.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:166523.3-166540.6"
- wire $0\r_busy$next[0:0]$9289
- attribute \src "libresoc.v:166483.3-166484.29"
+ attribute \src "libresoc.v:164324.3-164341.6"
+ wire $0\r_busy$next[0:0]$9203
+ attribute \src "libresoc.v:164284.3-164285.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:166575.3-166587.6"
- wire width 64 $0\ra$next[63:0]$9315
- attribute \src "libresoc.v:166461.3-166462.21"
+ attribute \src "libresoc.v:164376.3-164388.6"
+ wire width 64 $0\ra$next[63:0]$9229
+ attribute \src "libresoc.v:164262.3-164263.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:166588.3-166600.6"
- wire width 64 $0\rb$next[63:0]$9318
- attribute \src "libresoc.v:166459.3-166460.21"
+ attribute \src "libresoc.v:164389.3-164401.6"
+ wire width 64 $0\rb$next[63:0]$9232
+ attribute \src "libresoc.v:164260.3-164261.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 64 $0\trap_op__cia$next[63:0]$9296
- attribute \src "libresoc.v:166471.3-166472.41"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 64 $0\trap_op__cia$next[63:0]$9210
+ attribute \src "libresoc.v:164272.3-164273.41"
wire width 64 $0\trap_op__cia[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 13 $0\trap_op__fn_unit$next[12:0]$9297
- attribute \src "libresoc.v:166465.3-166466.49"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 13 $0\trap_op__fn_unit$next[12:0]$9211
+ attribute \src "libresoc.v:164266.3-164267.49"
wire width 13 $0\trap_op__fn_unit[12:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 32 $0\trap_op__insn$next[31:0]$9298
- attribute \src "libresoc.v:166467.3-166468.43"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 32 $0\trap_op__insn$next[31:0]$9212
+ attribute \src "libresoc.v:164268.3-164269.43"
wire width 32 $0\trap_op__insn[31:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 7 $0\trap_op__insn_type$next[6:0]$9299
- attribute \src "libresoc.v:166463.3-166464.53"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 7 $0\trap_op__insn_type$next[6:0]$9213
+ attribute \src "libresoc.v:164264.3-164265.53"
wire width 7 $0\trap_op__insn_type[6:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire $0\trap_op__is_32bit$next[0:0]$9300
- attribute \src "libresoc.v:166473.3-166474.51"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire $0\trap_op__is_32bit$next[0:0]$9214
+ attribute \src "libresoc.v:164274.3-164275.51"
wire $0\trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 8 $0\trap_op__ldst_exc$next[7:0]$9301
- attribute \src "libresoc.v:166479.3-166480.51"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 8 $0\trap_op__ldst_exc$next[7:0]$9215
+ attribute \src "libresoc.v:164280.3-164281.51"
wire width 8 $0\trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 64 $0\trap_op__msr$next[63:0]$9302
- attribute \src "libresoc.v:166469.3-166470.41"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 64 $0\trap_op__msr$next[63:0]$9216
+ attribute \src "libresoc.v:164270.3-164271.41"
wire width 64 $0\trap_op__msr[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 13 $0\trap_op__trapaddr$next[12:0]$9303
- attribute \src "libresoc.v:166477.3-166478.51"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 13 $0\trap_op__trapaddr$next[12:0]$9217
+ attribute \src "libresoc.v:164278.3-164279.51"
wire width 13 $0\trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 8 $0\trap_op__traptype$next[7:0]$9304
- attribute \src "libresoc.v:166475.3-166476.51"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 8 $0\trap_op__traptype$next[7:0]$9218
+ attribute \src "libresoc.v:164276.3-164277.51"
wire width 8 $0\trap_op__traptype[7:0]
- attribute \src "libresoc.v:166601.3-166613.6"
- wire width 64 $1\fast1$next[63:0]$9322
- attribute \src "libresoc.v:166048.14-166048.42"
+ attribute \src "libresoc.v:164402.3-164414.6"
+ wire width 64 $1\fast1$next[63:0]$9236
+ attribute \src "libresoc.v:163849.14-163849.42"
wire width 64 $1\fast1[63:0]
- attribute \src "libresoc.v:166614.3-166626.6"
- wire width 64 $1\fast2$next[63:0]$9325
- attribute \src "libresoc.v:166057.14-166057.42"
+ attribute \src "libresoc.v:164415.3-164427.6"
+ wire width 64 $1\fast2$next[63:0]$9239
+ attribute \src "libresoc.v:163858.14-163858.42"
wire width 64 $1\fast2[63:0]
- attribute \src "libresoc.v:166541.3-166553.6"
- wire width 2 $1\muxid$next[1:0]$9294
- attribute \src "libresoc.v:166066.13-166066.25"
+ attribute \src "libresoc.v:164342.3-164354.6"
+ wire width 2 $1\muxid$next[1:0]$9208
+ attribute \src "libresoc.v:163867.13-163867.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:166523.3-166540.6"
- wire $1\r_busy$next[0:0]$9290
- attribute \src "libresoc.v:166088.7-166088.20"
+ attribute \src "libresoc.v:164324.3-164341.6"
+ wire $1\r_busy$next[0:0]$9204
+ attribute \src "libresoc.v:163889.7-163889.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:166575.3-166587.6"
- wire width 64 $1\ra$next[63:0]$9316
- attribute \src "libresoc.v:166093.14-166093.39"
+ attribute \src "libresoc.v:164376.3-164388.6"
+ wire width 64 $1\ra$next[63:0]$9230
+ attribute \src "libresoc.v:163894.14-163894.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:166588.3-166600.6"
- wire width 64 $1\rb$next[63:0]$9319
- attribute \src "libresoc.v:166102.14-166102.39"
+ attribute \src "libresoc.v:164389.3-164401.6"
+ wire width 64 $1\rb$next[63:0]$9233
+ attribute \src "libresoc.v:163903.14-163903.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 64 $1\trap_op__cia$next[63:0]$9305
- attribute \src "libresoc.v:166111.14-166111.49"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 64 $1\trap_op__cia$next[63:0]$9219
+ attribute \src "libresoc.v:163912.14-163912.49"
wire width 64 $1\trap_op__cia[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 13 $1\trap_op__fn_unit$next[12:0]$9306
- attribute \src "libresoc.v:166134.14-166134.41"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 13 $1\trap_op__fn_unit$next[12:0]$9220
+ attribute \src "libresoc.v:163935.14-163935.41"
wire width 13 $1\trap_op__fn_unit[12:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 32 $1\trap_op__insn$next[31:0]$9307
- attribute \src "libresoc.v:166171.14-166171.35"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 32 $1\trap_op__insn$next[31:0]$9221
+ attribute \src "libresoc.v:163972.14-163972.35"
wire width 32 $1\trap_op__insn[31:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 7 $1\trap_op__insn_type$next[6:0]$9308
- attribute \src "libresoc.v:166254.13-166254.39"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 7 $1\trap_op__insn_type$next[6:0]$9222
+ attribute \src "libresoc.v:164055.13-164055.39"
wire width 7 $1\trap_op__insn_type[6:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire $1\trap_op__is_32bit$next[0:0]$9309
- attribute \src "libresoc.v:166411.7-166411.31"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire $1\trap_op__is_32bit$next[0:0]$9223
+ attribute \src "libresoc.v:164212.7-164212.31"
wire $1\trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 8 $1\trap_op__ldst_exc$next[7:0]$9310
- attribute \src "libresoc.v:166420.13-166420.38"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 8 $1\trap_op__ldst_exc$next[7:0]$9224
+ attribute \src "libresoc.v:164221.13-164221.38"
wire width 8 $1\trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 64 $1\trap_op__msr$next[63:0]$9311
- attribute \src "libresoc.v:166429.14-166429.49"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 64 $1\trap_op__msr$next[63:0]$9225
+ attribute \src "libresoc.v:164230.14-164230.49"
wire width 64 $1\trap_op__msr[63:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 13 $1\trap_op__trapaddr$next[12:0]$9312
- attribute \src "libresoc.v:166438.14-166438.42"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 13 $1\trap_op__trapaddr$next[12:0]$9226
+ attribute \src "libresoc.v:164239.14-164239.42"
wire width 13 $1\trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:166554.3-166574.6"
- wire width 8 $1\trap_op__traptype$next[7:0]$9313
- attribute \src "libresoc.v:166447.13-166447.38"
+ attribute \src "libresoc.v:164355.3-164375.6"
+ wire width 8 $1\trap_op__traptype$next[7:0]$9227
+ attribute \src "libresoc.v:164248.13-164248.38"
wire width 8 $1\trap_op__traptype[7:0]
- attribute \src "libresoc.v:166523.3-166540.6"
- wire $2\r_busy$next[0:0]$9291
- attribute \src "libresoc.v:166454.18-166454.118"
- wire $and$libresoc.v:166454$9272_Y
+ attribute \src "libresoc.v:164324.3-164341.6"
+ wire $2\r_busy$next[0:0]$9205
+ attribute \src "libresoc.v:164255.18-164255.118"
+ wire $and$libresoc.v:164255$9186_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \dummy_fast1
wire width 64 \fast2$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \fast2$next
- attribute \src "libresoc.v:165807.7-165807.15"
+ attribute \src "libresoc.v:163608.7-163608.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 8 \trap_op__traptype$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:166454$9272
+ cell $and $and$libresoc.v:164255$9186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$29
connect \B \p_ready_o
- connect \Y $and$libresoc.v:166454$9272_Y
+ connect \Y $and$libresoc.v:164255$9186_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166485.9-166514.4"
+ attribute \src "libresoc.v:164286.9-164315.4"
cell \dummy \dummy
connect \fast1 \dummy_fast1
connect \fast1$13 \dummy_fast1$27
connect \trap_op__traptype$8 \dummy_trap_op__traptype$22
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166515.10-166518.4"
+ attribute \src "libresoc.v:164316.10-164319.4"
cell \n$34 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:166519.10-166522.4"
+ attribute \src "libresoc.v:164320.10-164323.4"
cell \p$33 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:165807.7-165807.20"
- process $proc$libresoc.v:165807$9326
+ attribute \src "libresoc.v:163608.7-163608.20"
+ process $proc$libresoc.v:163608$9240
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:166048.14-166048.42"
- process $proc$libresoc.v:166048$9327
+ attribute \src "libresoc.v:163849.14-163849.42"
+ process $proc$libresoc.v:163849$9241
assign { } { }
assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \fast1 $1\fast1[63:0]
end
- attribute \src "libresoc.v:166057.14-166057.42"
- process $proc$libresoc.v:166057$9328
+ attribute \src "libresoc.v:163858.14-163858.42"
+ process $proc$libresoc.v:163858$9242
assign { } { }
assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \fast2 $1\fast2[63:0]
end
- attribute \src "libresoc.v:166066.13-166066.25"
- process $proc$libresoc.v:166066$9329
+ attribute \src "libresoc.v:163867.13-163867.25"
+ process $proc$libresoc.v:163867$9243
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:166088.7-166088.20"
- process $proc$libresoc.v:166088$9330
+ attribute \src "libresoc.v:163889.7-163889.20"
+ process $proc$libresoc.v:163889$9244
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:166093.14-166093.39"
- process $proc$libresoc.v:166093$9331
+ attribute \src "libresoc.v:163894.14-163894.39"
+ process $proc$libresoc.v:163894$9245
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:166102.14-166102.39"
- process $proc$libresoc.v:166102$9332
+ attribute \src "libresoc.v:163903.14-163903.39"
+ process $proc$libresoc.v:163903$9246
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:166111.14-166111.49"
- process $proc$libresoc.v:166111$9333
+ attribute \src "libresoc.v:163912.14-163912.49"
+ process $proc$libresoc.v:163912$9247
assign { } { }
assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \trap_op__cia $1\trap_op__cia[63:0]
end
- attribute \src "libresoc.v:166134.14-166134.41"
- process $proc$libresoc.v:166134$9334
+ attribute \src "libresoc.v:163935.14-163935.41"
+ process $proc$libresoc.v:163935$9248
assign { } { }
assign $1\trap_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \trap_op__fn_unit $1\trap_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:166171.14-166171.35"
- process $proc$libresoc.v:166171$9335
+ attribute \src "libresoc.v:163972.14-163972.35"
+ process $proc$libresoc.v:163972$9249
assign { } { }
assign $1\trap_op__insn[31:0] 0
sync always
sync init
update \trap_op__insn $1\trap_op__insn[31:0]
end
- attribute \src "libresoc.v:166254.13-166254.39"
- process $proc$libresoc.v:166254$9336
+ attribute \src "libresoc.v:164055.13-164055.39"
+ process $proc$libresoc.v:164055$9250
assign { } { }
assign $1\trap_op__insn_type[6:0] 7'0000000
sync always
sync init
update \trap_op__insn_type $1\trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:166411.7-166411.31"
- process $proc$libresoc.v:166411$9337
+ attribute \src "libresoc.v:164212.7-164212.31"
+ process $proc$libresoc.v:164212$9251
assign { } { }
assign $1\trap_op__is_32bit[0:0] 1'0
sync always
sync init
update \trap_op__is_32bit $1\trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:166420.13-166420.38"
- process $proc$libresoc.v:166420$9338
+ attribute \src "libresoc.v:164221.13-164221.38"
+ process $proc$libresoc.v:164221$9252
assign { } { }
assign $1\trap_op__ldst_exc[7:0] 8'00000000
sync always
sync init
update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:166429.14-166429.49"
- process $proc$libresoc.v:166429$9339
+ attribute \src "libresoc.v:164230.14-164230.49"
+ process $proc$libresoc.v:164230$9253
assign { } { }
assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \trap_op__msr $1\trap_op__msr[63:0]
end
- attribute \src "libresoc.v:166438.14-166438.42"
- process $proc$libresoc.v:166438$9340
+ attribute \src "libresoc.v:164239.14-164239.42"
+ process $proc$libresoc.v:164239$9254
assign { } { }
assign $1\trap_op__trapaddr[12:0] 13'0000000000000
sync always
sync init
update \trap_op__trapaddr $1\trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:166447.13-166447.38"
- process $proc$libresoc.v:166447$9341
+ attribute \src "libresoc.v:164248.13-164248.38"
+ process $proc$libresoc.v:164248$9255
assign { } { }
assign $1\trap_op__traptype[7:0] 8'00000000
sync always
sync init
update \trap_op__traptype $1\trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:166455.3-166456.27"
- process $proc$libresoc.v:166455$9273
+ attribute \src "libresoc.v:164256.3-164257.27"
+ process $proc$libresoc.v:164256$9187
assign { } { }
assign $0\fast2[63:0] \fast2$next
sync posedge \coresync_clk
update \fast2 $0\fast2[63:0]
end
- attribute \src "libresoc.v:166457.3-166458.27"
- process $proc$libresoc.v:166457$9274
+ attribute \src "libresoc.v:164258.3-164259.27"
+ process $proc$libresoc.v:164258$9188
assign { } { }
assign $0\fast1[63:0] \fast1$next
sync posedge \coresync_clk
update \fast1 $0\fast1[63:0]
end
- attribute \src "libresoc.v:166459.3-166460.21"
- process $proc$libresoc.v:166459$9275
+ attribute \src "libresoc.v:164260.3-164261.21"
+ process $proc$libresoc.v:164260$9189
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:166461.3-166462.21"
- process $proc$libresoc.v:166461$9276
+ attribute \src "libresoc.v:164262.3-164263.21"
+ process $proc$libresoc.v:164262$9190
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:166463.3-166464.53"
- process $proc$libresoc.v:166463$9277
+ attribute \src "libresoc.v:164264.3-164265.53"
+ process $proc$libresoc.v:164264$9191
assign { } { }
assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next
sync posedge \coresync_clk
update \trap_op__insn_type $0\trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:166465.3-166466.49"
- process $proc$libresoc.v:166465$9278
+ attribute \src "libresoc.v:164266.3-164267.49"
+ process $proc$libresoc.v:164266$9192
assign { } { }
assign $0\trap_op__fn_unit[12:0] \trap_op__fn_unit$next
sync posedge \coresync_clk
update \trap_op__fn_unit $0\trap_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:166467.3-166468.43"
- process $proc$libresoc.v:166467$9279
+ attribute \src "libresoc.v:164268.3-164269.43"
+ process $proc$libresoc.v:164268$9193
assign { } { }
assign $0\trap_op__insn[31:0] \trap_op__insn$next
sync posedge \coresync_clk
update \trap_op__insn $0\trap_op__insn[31:0]
end
- attribute \src "libresoc.v:166469.3-166470.41"
- process $proc$libresoc.v:166469$9280
+ attribute \src "libresoc.v:164270.3-164271.41"
+ process $proc$libresoc.v:164270$9194
assign { } { }
assign $0\trap_op__msr[63:0] \trap_op__msr$next
sync posedge \coresync_clk
update \trap_op__msr $0\trap_op__msr[63:0]
end
- attribute \src "libresoc.v:166471.3-166472.41"
- process $proc$libresoc.v:166471$9281
+ attribute \src "libresoc.v:164272.3-164273.41"
+ process $proc$libresoc.v:164272$9195
assign { } { }
assign $0\trap_op__cia[63:0] \trap_op__cia$next
sync posedge \coresync_clk
update \trap_op__cia $0\trap_op__cia[63:0]
end
- attribute \src "libresoc.v:166473.3-166474.51"
- process $proc$libresoc.v:166473$9282
+ attribute \src "libresoc.v:164274.3-164275.51"
+ process $proc$libresoc.v:164274$9196
assign { } { }
assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next
sync posedge \coresync_clk
update \trap_op__is_32bit $0\trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:166475.3-166476.51"
- process $proc$libresoc.v:166475$9283
+ attribute \src "libresoc.v:164276.3-164277.51"
+ process $proc$libresoc.v:164276$9197
assign { } { }
assign $0\trap_op__traptype[7:0] \trap_op__traptype$next
sync posedge \coresync_clk
update \trap_op__traptype $0\trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:166477.3-166478.51"
- process $proc$libresoc.v:166477$9284
+ attribute \src "libresoc.v:164278.3-164279.51"
+ process $proc$libresoc.v:164278$9198
assign { } { }
assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next
sync posedge \coresync_clk
update \trap_op__trapaddr $0\trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:166479.3-166480.51"
- process $proc$libresoc.v:166479$9285
+ attribute \src "libresoc.v:164280.3-164281.51"
+ process $proc$libresoc.v:164280$9199
assign { } { }
assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next
sync posedge \coresync_clk
update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:166481.3-166482.27"
- process $proc$libresoc.v:166481$9286
+ attribute \src "libresoc.v:164282.3-164283.27"
+ process $proc$libresoc.v:164282$9200
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:166483.3-166484.29"
- process $proc$libresoc.v:166483$9287
+ attribute \src "libresoc.v:164284.3-164285.29"
+ process $proc$libresoc.v:164284$9201
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:166523.3-166540.6"
- process $proc$libresoc.v:166523$9288
+ attribute \src "libresoc.v:164324.3-164341.6"
+ process $proc$libresoc.v:164324$9202
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9289 $2\r_busy$next[0:0]$9291
- attribute \src "libresoc.v:166524.5-166524.29"
+ assign $0\r_busy$next[0:0]$9203 $2\r_busy$next[0:0]$9205
+ attribute \src "libresoc.v:164325.5-164325.29"
switch \initial
- attribute \src "libresoc.v:166524.9-166524.17"
+ attribute \src "libresoc.v:164325.9-164325.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9290 1'1
+ assign $1\r_busy$next[0:0]$9204 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9290 1'0
+ assign $1\r_busy$next[0:0]$9204 1'0
case
- assign $1\r_busy$next[0:0]$9290 \r_busy
+ assign $1\r_busy$next[0:0]$9204 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9291 1'0
+ assign $2\r_busy$next[0:0]$9205 1'0
case
- assign $2\r_busy$next[0:0]$9291 $1\r_busy$next[0:0]$9290
+ assign $2\r_busy$next[0:0]$9205 $1\r_busy$next[0:0]$9204
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9289
+ update \r_busy$next $0\r_busy$next[0:0]$9203
end
- attribute \src "libresoc.v:166541.3-166553.6"
- process $proc$libresoc.v:166541$9292
+ attribute \src "libresoc.v:164342.3-164354.6"
+ process $proc$libresoc.v:164342$9206
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$9293 $1\muxid$next[1:0]$9294
- attribute \src "libresoc.v:166542.5-166542.29"
+ assign $0\muxid$next[1:0]$9207 $1\muxid$next[1:0]$9208
+ attribute \src "libresoc.v:164343.5-164343.29"
switch \initial
- attribute \src "libresoc.v:166542.9-166542.17"
+ attribute \src "libresoc.v:164343.9-164343.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$9294 \muxid$32
+ assign $1\muxid$next[1:0]$9208 \muxid$32
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$9294 \muxid$32
+ assign $1\muxid$next[1:0]$9208 \muxid$32
case
- assign $1\muxid$next[1:0]$9294 \muxid
+ assign $1\muxid$next[1:0]$9208 \muxid
end
sync always
- update \muxid$next $0\muxid$next[1:0]$9293
+ update \muxid$next $0\muxid$next[1:0]$9207
end
- attribute \src "libresoc.v:166554.3-166574.6"
- process $proc$libresoc.v:166554$9295
+ attribute \src "libresoc.v:164355.3-164375.6"
+ process $proc$libresoc.v:164355$9209
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trap_op__cia$next[63:0]$9296 $1\trap_op__cia$next[63:0]$9305
- assign $0\trap_op__fn_unit$next[12:0]$9297 $1\trap_op__fn_unit$next[12:0]$9306
- assign $0\trap_op__insn$next[31:0]$9298 $1\trap_op__insn$next[31:0]$9307
- assign $0\trap_op__insn_type$next[6:0]$9299 $1\trap_op__insn_type$next[6:0]$9308
- assign $0\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__is_32bit$next[0:0]$9309
- assign $0\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__ldst_exc$next[7:0]$9310
- assign $0\trap_op__msr$next[63:0]$9302 $1\trap_op__msr$next[63:0]$9311
- assign $0\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__trapaddr$next[12:0]$9312
- assign $0\trap_op__traptype$next[7:0]$9304 $1\trap_op__traptype$next[7:0]$9313
- attribute \src "libresoc.v:166555.5-166555.29"
+ assign $0\trap_op__cia$next[63:0]$9210 $1\trap_op__cia$next[63:0]$9219
+ assign $0\trap_op__fn_unit$next[12:0]$9211 $1\trap_op__fn_unit$next[12:0]$9220
+ assign $0\trap_op__insn$next[31:0]$9212 $1\trap_op__insn$next[31:0]$9221
+ assign $0\trap_op__insn_type$next[6:0]$9213 $1\trap_op__insn_type$next[6:0]$9222
+ assign $0\trap_op__is_32bit$next[0:0]$9214 $1\trap_op__is_32bit$next[0:0]$9223
+ assign $0\trap_op__ldst_exc$next[7:0]$9215 $1\trap_op__ldst_exc$next[7:0]$9224
+ assign $0\trap_op__msr$next[63:0]$9216 $1\trap_op__msr$next[63:0]$9225
+ assign $0\trap_op__trapaddr$next[12:0]$9217 $1\trap_op__trapaddr$next[12:0]$9226
+ assign $0\trap_op__traptype$next[7:0]$9218 $1\trap_op__traptype$next[7:0]$9227
+ attribute \src "libresoc.v:164356.5-164356.29"
switch \initial
- attribute \src "libresoc.v:166555.9-166555.17"
+ attribute \src "libresoc.v:164356.9-164356.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__traptype$next[7:0]$9313 $1\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__cia$next[63:0]$9305 $1\trap_op__msr$next[63:0]$9311 $1\trap_op__insn$next[31:0]$9307 $1\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__insn_type$next[6:0]$9308 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
+ assign { $1\trap_op__ldst_exc$next[7:0]$9224 $1\trap_op__trapaddr$next[12:0]$9226 $1\trap_op__traptype$next[7:0]$9227 $1\trap_op__is_32bit$next[0:0]$9223 $1\trap_op__cia$next[63:0]$9219 $1\trap_op__msr$next[63:0]$9225 $1\trap_op__insn$next[31:0]$9221 $1\trap_op__fn_unit$next[12:0]$9220 $1\trap_op__insn_type$next[6:0]$9222 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__traptype$next[7:0]$9313 $1\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__cia$next[63:0]$9305 $1\trap_op__msr$next[63:0]$9311 $1\trap_op__insn$next[31:0]$9307 $1\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__insn_type$next[6:0]$9308 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
+ assign { $1\trap_op__ldst_exc$next[7:0]$9224 $1\trap_op__trapaddr$next[12:0]$9226 $1\trap_op__traptype$next[7:0]$9227 $1\trap_op__is_32bit$next[0:0]$9223 $1\trap_op__cia$next[63:0]$9219 $1\trap_op__msr$next[63:0]$9225 $1\trap_op__insn$next[31:0]$9221 $1\trap_op__fn_unit$next[12:0]$9220 $1\trap_op__insn_type$next[6:0]$9222 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 }
case
- assign $1\trap_op__cia$next[63:0]$9305 \trap_op__cia
- assign $1\trap_op__fn_unit$next[12:0]$9306 \trap_op__fn_unit
- assign $1\trap_op__insn$next[31:0]$9307 \trap_op__insn
- assign $1\trap_op__insn_type$next[6:0]$9308 \trap_op__insn_type
- assign $1\trap_op__is_32bit$next[0:0]$9309 \trap_op__is_32bit
- assign $1\trap_op__ldst_exc$next[7:0]$9310 \trap_op__ldst_exc
- assign $1\trap_op__msr$next[63:0]$9311 \trap_op__msr
- assign $1\trap_op__trapaddr$next[12:0]$9312 \trap_op__trapaddr
- assign $1\trap_op__traptype$next[7:0]$9313 \trap_op__traptype
+ assign $1\trap_op__cia$next[63:0]$9219 \trap_op__cia
+ assign $1\trap_op__fn_unit$next[12:0]$9220 \trap_op__fn_unit
+ assign $1\trap_op__insn$next[31:0]$9221 \trap_op__insn
+ assign $1\trap_op__insn_type$next[6:0]$9222 \trap_op__insn_type
+ assign $1\trap_op__is_32bit$next[0:0]$9223 \trap_op__is_32bit
+ assign $1\trap_op__ldst_exc$next[7:0]$9224 \trap_op__ldst_exc
+ assign $1\trap_op__msr$next[63:0]$9225 \trap_op__msr
+ assign $1\trap_op__trapaddr$next[12:0]$9226 \trap_op__trapaddr
+ assign $1\trap_op__traptype$next[7:0]$9227 \trap_op__traptype
end
sync always
- update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9296
- update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9297
- update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9298
- update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9299
- update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9300
- update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9301
- update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9302
- update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9303
- update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9304
+ update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9210
+ update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9211
+ update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9212
+ update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9213
+ update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9214
+ update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9215
+ update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9216
+ update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9217
+ update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9218
end
- attribute \src "libresoc.v:166575.3-166587.6"
- process $proc$libresoc.v:166575$9314
+ attribute \src "libresoc.v:164376.3-164388.6"
+ process $proc$libresoc.v:164376$9228
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$9315 $1\ra$next[63:0]$9316
- attribute \src "libresoc.v:166576.5-166576.29"
+ assign $0\ra$next[63:0]$9229 $1\ra$next[63:0]$9230
+ attribute \src "libresoc.v:164377.5-164377.29"
switch \initial
- attribute \src "libresoc.v:166576.9-166576.17"
+ attribute \src "libresoc.v:164377.9-164377.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$9316 \ra$42
+ assign $1\ra$next[63:0]$9230 \ra$42
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$9316 \ra$42
+ assign $1\ra$next[63:0]$9230 \ra$42
case
- assign $1\ra$next[63:0]$9316 \ra
+ assign $1\ra$next[63:0]$9230 \ra
end
sync always
- update \ra$next $0\ra$next[63:0]$9315
+ update \ra$next $0\ra$next[63:0]$9229
end
- attribute \src "libresoc.v:166588.3-166600.6"
- process $proc$libresoc.v:166588$9317
+ attribute \src "libresoc.v:164389.3-164401.6"
+ process $proc$libresoc.v:164389$9231
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$9318 $1\rb$next[63:0]$9319
- attribute \src "libresoc.v:166589.5-166589.29"
+ assign $0\rb$next[63:0]$9232 $1\rb$next[63:0]$9233
+ attribute \src "libresoc.v:164390.5-164390.29"
switch \initial
- attribute \src "libresoc.v:166589.9-166589.17"
+ attribute \src "libresoc.v:164390.9-164390.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$9319 \rb$43
+ assign $1\rb$next[63:0]$9233 \rb$43
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$9319 \rb$43
+ assign $1\rb$next[63:0]$9233 \rb$43
case
- assign $1\rb$next[63:0]$9319 \rb
+ assign $1\rb$next[63:0]$9233 \rb
end
sync always
- update \rb$next $0\rb$next[63:0]$9318
+ update \rb$next $0\rb$next[63:0]$9232
end
- attribute \src "libresoc.v:166601.3-166613.6"
- process $proc$libresoc.v:166601$9320
+ attribute \src "libresoc.v:164402.3-164414.6"
+ process $proc$libresoc.v:164402$9234
assign { } { }
assign { } { }
- assign $0\fast1$next[63:0]$9321 $1\fast1$next[63:0]$9322
- attribute \src "libresoc.v:166602.5-166602.29"
+ assign $0\fast1$next[63:0]$9235 $1\fast1$next[63:0]$9236
+ attribute \src "libresoc.v:164403.5-164403.29"
switch \initial
- attribute \src "libresoc.v:166602.9-166602.17"
+ attribute \src "libresoc.v:164403.9-164403.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\fast1$next[63:0]$9322 \fast1$44
+ assign $1\fast1$next[63:0]$9236 \fast1$44
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\fast1$next[63:0]$9322 \fast1$44
+ assign $1\fast1$next[63:0]$9236 \fast1$44
case
- assign $1\fast1$next[63:0]$9322 \fast1
+ assign $1\fast1$next[63:0]$9236 \fast1
end
sync always
- update \fast1$next $0\fast1$next[63:0]$9321
+ update \fast1$next $0\fast1$next[63:0]$9235
end
- attribute \src "libresoc.v:166614.3-166626.6"
- process $proc$libresoc.v:166614$9323
+ attribute \src "libresoc.v:164415.3-164427.6"
+ process $proc$libresoc.v:164415$9237
assign { } { }
assign { } { }
- assign $0\fast2$next[63:0]$9324 $1\fast2$next[63:0]$9325
- attribute \src "libresoc.v:166615.5-166615.29"
+ assign $0\fast2$next[63:0]$9238 $1\fast2$next[63:0]$9239
+ attribute \src "libresoc.v:164416.5-164416.29"
switch \initial
- attribute \src "libresoc.v:166615.9-166615.17"
+ attribute \src "libresoc.v:164416.9-164416.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\fast2$next[63:0]$9325 \fast2$45
+ assign $1\fast2$next[63:0]$9239 \fast2$45
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\fast2$next[63:0]$9325 \fast2$45
+ assign $1\fast2$next[63:0]$9239 \fast2$45
case
- assign $1\fast2$next[63:0]$9325 \fast2
+ assign $1\fast2$next[63:0]$9239 \fast2
end
sync always
- update \fast2$next $0\fast2$next[63:0]$9324
+ update \fast2$next $0\fast2$next[63:0]$9238
end
- connect \$30 $and$libresoc.v:166454$9272_Y
+ connect \$30 $and$libresoc.v:164255$9186_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect \fast2$45 \dummy_fast2$28
connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 }
connect \dummy_muxid \muxid$1
end
-attribute \src "libresoc.v:166648.1-167823.10"
+attribute \src "libresoc.v:164449.1-165624.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2"
attribute \generator "nMigen"
module \pipe2
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 4 $0\alu_op__data_len$18$next[3:0]$9410
- attribute \src "libresoc.v:167564.3-167565.57"
- wire width 4 $0\alu_op__data_len$18[3:0]$9396
- attribute \src "libresoc.v:166656.13-166656.41"
- wire width 4 $0\alu_op__data_len$18[3:0]$9484
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9411
- attribute \src "libresoc.v:167534.3-167535.53"
- wire width 13 $0\alu_op__fn_unit$3[12:0]$9366
- attribute \src "libresoc.v:166693.14-166693.44"
- wire width 13 $0\alu_op__fn_unit$3[12:0]$9486
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9412
- attribute \src "libresoc.v:167536.3-167537.67"
- wire width 64 $0\alu_op__imm_data__data$4[63:0]$9368
- attribute \src "libresoc.v:166716.14-166716.63"
- wire width 64 $0\alu_op__imm_data__data$4[63:0]$9488
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__imm_data__ok$5$next[0:0]$9413
- attribute \src "libresoc.v:167538.3-167539.63"
- wire $0\alu_op__imm_data__ok$5[0:0]$9370
- attribute \src "libresoc.v:166725.7-166725.38"
- wire $0\alu_op__imm_data__ok$5[0:0]$9490
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 2 $0\alu_op__input_carry$14$next[1:0]$9414
- attribute \src "libresoc.v:167556.3-167557.63"
- wire width 2 $0\alu_op__input_carry$14[1:0]$9388
- attribute \src "libresoc.v:166742.13-166742.44"
- wire width 2 $0\alu_op__input_carry$14[1:0]$9492
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 32 $0\alu_op__insn$19$next[31:0]$9415
- attribute \src "libresoc.v:167566.3-167567.49"
- wire width 32 $0\alu_op__insn$19[31:0]$9398
- attribute \src "libresoc.v:166755.14-166755.39"
- wire width 32 $0\alu_op__insn$19[31:0]$9494
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 7 $0\alu_op__insn_type$2$next[6:0]$9416
- attribute \src "libresoc.v:167532.3-167533.57"
- wire width 7 $0\alu_op__insn_type$2[6:0]$9364
- attribute \src "libresoc.v:166912.13-166912.42"
- wire width 7 $0\alu_op__insn_type$2[6:0]$9496
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__invert_in$10$next[0:0]$9417
- attribute \src "libresoc.v:167548.3-167549.59"
- wire $0\alu_op__invert_in$10[0:0]$9380
- attribute \src "libresoc.v:166995.7-166995.36"
- wire $0\alu_op__invert_in$10[0:0]$9498
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__invert_out$12$next[0:0]$9418
- attribute \src "libresoc.v:167552.3-167553.61"
- wire $0\alu_op__invert_out$12[0:0]$9384
- attribute \src "libresoc.v:167004.7-167004.37"
- wire $0\alu_op__invert_out$12[0:0]$9500
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__is_32bit$16$next[0:0]$9419
- attribute \src "libresoc.v:167560.3-167561.57"
- wire $0\alu_op__is_32bit$16[0:0]$9392
- attribute \src "libresoc.v:167013.7-167013.35"
- wire $0\alu_op__is_32bit$16[0:0]$9502
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__is_signed$17$next[0:0]$9420
- attribute \src "libresoc.v:167562.3-167563.59"
- wire $0\alu_op__is_signed$17[0:0]$9394
- attribute \src "libresoc.v:167022.7-167022.36"
- wire $0\alu_op__is_signed$17[0:0]$9504
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__oe__oe$8$next[0:0]$9421
- attribute \src "libresoc.v:167544.3-167545.51"
- wire $0\alu_op__oe__oe$8[0:0]$9376
- attribute \src "libresoc.v:167033.7-167033.32"
- wire $0\alu_op__oe__oe$8[0:0]$9506
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__oe__ok$9$next[0:0]$9422
- attribute \src "libresoc.v:167546.3-167547.51"
- wire $0\alu_op__oe__ok$9[0:0]$9378
- attribute \src "libresoc.v:167042.7-167042.32"
- wire $0\alu_op__oe__ok$9[0:0]$9508
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__output_carry$15$next[0:0]$9423
- attribute \src "libresoc.v:167558.3-167559.65"
- wire $0\alu_op__output_carry$15[0:0]$9390
- attribute \src "libresoc.v:167049.7-167049.39"
- wire $0\alu_op__output_carry$15[0:0]$9510
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__rc__ok$7$next[0:0]$9424
- attribute \src "libresoc.v:167542.3-167543.51"
- wire $0\alu_op__rc__ok$7[0:0]$9374
- attribute \src "libresoc.v:167060.7-167060.32"
- wire $0\alu_op__rc__ok$7[0:0]$9512
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__rc__rc$6$next[0:0]$9425
- attribute \src "libresoc.v:167540.3-167541.51"
- wire $0\alu_op__rc__rc$6[0:0]$9372
- attribute \src "libresoc.v:167067.7-167067.32"
- wire $0\alu_op__rc__rc$6[0:0]$9514
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__write_cr0$13$next[0:0]$9426
- attribute \src "libresoc.v:167554.3-167555.59"
- wire $0\alu_op__write_cr0$13[0:0]$9386
- attribute \src "libresoc.v:167076.7-167076.36"
- wire $0\alu_op__write_cr0$13[0:0]$9516
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $0\alu_op__zero_a$11$next[0:0]$9427
- attribute \src "libresoc.v:167550.3-167551.53"
- wire $0\alu_op__zero_a$11[0:0]$9382
- attribute \src "libresoc.v:167085.7-167085.33"
- wire $0\alu_op__zero_a$11[0:0]$9518
- attribute \src "libresoc.v:167728.3-167746.6"
- wire width 4 $0\cr_a$22$next[3:0]$9459
- attribute \src "libresoc.v:167524.3-167525.33"
- wire width 4 $0\cr_a$22[3:0]$9356
- attribute \src "libresoc.v:167098.13-167098.29"
- wire width 4 $0\cr_a$22[3:0]$9520
- attribute \src "libresoc.v:167728.3-167746.6"
- wire $0\cr_a_ok$23$next[0:0]$9460
- attribute \src "libresoc.v:167526.3-167527.39"
- wire $0\cr_a_ok$23[0:0]$9358
- attribute \src "libresoc.v:167107.7-167107.26"
- wire $0\cr_a_ok$23[0:0]$9522
- attribute \src "libresoc.v:166649.7-166649.20"
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 4 $0\alu_op__data_len$18$next[3:0]$9324
+ attribute \src "libresoc.v:165365.3-165366.57"
+ wire width 4 $0\alu_op__data_len$18[3:0]$9310
+ attribute \src "libresoc.v:164457.13-164457.41"
+ wire width 4 $0\alu_op__data_len$18[3:0]$9398
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9325
+ attribute \src "libresoc.v:165335.3-165336.53"
+ wire width 13 $0\alu_op__fn_unit$3[12:0]$9280
+ attribute \src "libresoc.v:164494.14-164494.44"
+ wire width 13 $0\alu_op__fn_unit$3[12:0]$9400
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9326
+ attribute \src "libresoc.v:165337.3-165338.67"
+ wire width 64 $0\alu_op__imm_data__data$4[63:0]$9282
+ attribute \src "libresoc.v:164517.14-164517.63"
+ wire width 64 $0\alu_op__imm_data__data$4[63:0]$9402
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__imm_data__ok$5$next[0:0]$9327
+ attribute \src "libresoc.v:165339.3-165340.63"
+ wire $0\alu_op__imm_data__ok$5[0:0]$9284
+ attribute \src "libresoc.v:164526.7-164526.38"
+ wire $0\alu_op__imm_data__ok$5[0:0]$9404
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 2 $0\alu_op__input_carry$14$next[1:0]$9328
+ attribute \src "libresoc.v:165357.3-165358.63"
+ wire width 2 $0\alu_op__input_carry$14[1:0]$9302
+ attribute \src "libresoc.v:164543.13-164543.44"
+ wire width 2 $0\alu_op__input_carry$14[1:0]$9406
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 32 $0\alu_op__insn$19$next[31:0]$9329
+ attribute \src "libresoc.v:165367.3-165368.49"
+ wire width 32 $0\alu_op__insn$19[31:0]$9312
+ attribute \src "libresoc.v:164556.14-164556.39"
+ wire width 32 $0\alu_op__insn$19[31:0]$9408
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 7 $0\alu_op__insn_type$2$next[6:0]$9330
+ attribute \src "libresoc.v:165333.3-165334.57"
+ wire width 7 $0\alu_op__insn_type$2[6:0]$9278
+ attribute \src "libresoc.v:164713.13-164713.42"
+ wire width 7 $0\alu_op__insn_type$2[6:0]$9410
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__invert_in$10$next[0:0]$9331
+ attribute \src "libresoc.v:165349.3-165350.59"
+ wire $0\alu_op__invert_in$10[0:0]$9294
+ attribute \src "libresoc.v:164796.7-164796.36"
+ wire $0\alu_op__invert_in$10[0:0]$9412
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__invert_out$12$next[0:0]$9332
+ attribute \src "libresoc.v:165353.3-165354.61"
+ wire $0\alu_op__invert_out$12[0:0]$9298
+ attribute \src "libresoc.v:164805.7-164805.37"
+ wire $0\alu_op__invert_out$12[0:0]$9414
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__is_32bit$16$next[0:0]$9333
+ attribute \src "libresoc.v:165361.3-165362.57"
+ wire $0\alu_op__is_32bit$16[0:0]$9306
+ attribute \src "libresoc.v:164814.7-164814.35"
+ wire $0\alu_op__is_32bit$16[0:0]$9416
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__is_signed$17$next[0:0]$9334
+ attribute \src "libresoc.v:165363.3-165364.59"
+ wire $0\alu_op__is_signed$17[0:0]$9308
+ attribute \src "libresoc.v:164823.7-164823.36"
+ wire $0\alu_op__is_signed$17[0:0]$9418
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__oe__oe$8$next[0:0]$9335
+ attribute \src "libresoc.v:165345.3-165346.51"
+ wire $0\alu_op__oe__oe$8[0:0]$9290
+ attribute \src "libresoc.v:164834.7-164834.32"
+ wire $0\alu_op__oe__oe$8[0:0]$9420
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__oe__ok$9$next[0:0]$9336
+ attribute \src "libresoc.v:165347.3-165348.51"
+ wire $0\alu_op__oe__ok$9[0:0]$9292
+ attribute \src "libresoc.v:164843.7-164843.32"
+ wire $0\alu_op__oe__ok$9[0:0]$9422
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__output_carry$15$next[0:0]$9337
+ attribute \src "libresoc.v:165359.3-165360.65"
+ wire $0\alu_op__output_carry$15[0:0]$9304
+ attribute \src "libresoc.v:164850.7-164850.39"
+ wire $0\alu_op__output_carry$15[0:0]$9424
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__rc__ok$7$next[0:0]$9338
+ attribute \src "libresoc.v:165343.3-165344.51"
+ wire $0\alu_op__rc__ok$7[0:0]$9288
+ attribute \src "libresoc.v:164861.7-164861.32"
+ wire $0\alu_op__rc__ok$7[0:0]$9426
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__rc__rc$6$next[0:0]$9339
+ attribute \src "libresoc.v:165341.3-165342.51"
+ wire $0\alu_op__rc__rc$6[0:0]$9286
+ attribute \src "libresoc.v:164868.7-164868.32"
+ wire $0\alu_op__rc__rc$6[0:0]$9428
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__write_cr0$13$next[0:0]$9340
+ attribute \src "libresoc.v:165355.3-165356.59"
+ wire $0\alu_op__write_cr0$13[0:0]$9300
+ attribute \src "libresoc.v:164877.7-164877.36"
+ wire $0\alu_op__write_cr0$13[0:0]$9430
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $0\alu_op__zero_a$11$next[0:0]$9341
+ attribute \src "libresoc.v:165351.3-165352.53"
+ wire $0\alu_op__zero_a$11[0:0]$9296
+ attribute \src "libresoc.v:164886.7-164886.33"
+ wire $0\alu_op__zero_a$11[0:0]$9432
+ attribute \src "libresoc.v:165529.3-165547.6"
+ wire width 4 $0\cr_a$22$next[3:0]$9373
+ attribute \src "libresoc.v:165325.3-165326.33"
+ wire width 4 $0\cr_a$22[3:0]$9270
+ attribute \src "libresoc.v:164899.13-164899.29"
+ wire width 4 $0\cr_a$22[3:0]$9434
+ attribute \src "libresoc.v:165529.3-165547.6"
+ wire $0\cr_a_ok$23$next[0:0]$9374
+ attribute \src "libresoc.v:165327.3-165328.39"
+ wire $0\cr_a_ok$23[0:0]$9272
+ attribute \src "libresoc.v:164908.7-164908.26"
+ wire $0\cr_a_ok$23[0:0]$9436
+ attribute \src "libresoc.v:164450.7-164450.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:167654.3-167666.6"
- wire width 2 $0\muxid$1$next[1:0]$9407
- attribute \src "libresoc.v:167568.3-167569.33"
- wire width 2 $0\muxid$1[1:0]$9400
- attribute \src "libresoc.v:167118.13-167118.29"
- wire width 2 $0\muxid$1[1:0]$9524
- attribute \src "libresoc.v:167709.3-167727.6"
- wire width 64 $0\o$20$next[63:0]$9453
- attribute \src "libresoc.v:167528.3-167529.27"
- wire width 64 $0\o$20[63:0]$9360
- attribute \src "libresoc.v:167133.14-167133.43"
- wire width 64 $0\o$20[63:0]$9526
- attribute \src "libresoc.v:167709.3-167727.6"
- wire $0\o_ok$21$next[0:0]$9454
- attribute \src "libresoc.v:167530.3-167531.33"
- wire $0\o_ok$21[0:0]$9362
- attribute \src "libresoc.v:167142.7-167142.23"
- wire $0\o_ok$21[0:0]$9528
- attribute \src "libresoc.v:167636.3-167653.6"
- wire $0\r_busy$next[0:0]$9403
- attribute \src "libresoc.v:167570.3-167571.29"
+ attribute \src "libresoc.v:165455.3-165467.6"
+ wire width 2 $0\muxid$1$next[1:0]$9321
+ attribute \src "libresoc.v:165369.3-165370.33"
+ wire width 2 $0\muxid$1[1:0]$9314
+ attribute \src "libresoc.v:164919.13-164919.29"
+ wire width 2 $0\muxid$1[1:0]$9438
+ attribute \src "libresoc.v:165510.3-165528.6"
+ wire width 64 $0\o$20$next[63:0]$9367
+ attribute \src "libresoc.v:165329.3-165330.27"
+ wire width 64 $0\o$20[63:0]$9274
+ attribute \src "libresoc.v:164934.14-164934.43"
+ wire width 64 $0\o$20[63:0]$9440
+ attribute \src "libresoc.v:165510.3-165528.6"
+ wire $0\o_ok$21$next[0:0]$9368
+ attribute \src "libresoc.v:165331.3-165332.33"
+ wire $0\o_ok$21[0:0]$9276
+ attribute \src "libresoc.v:164943.7-164943.23"
+ wire $0\o_ok$21[0:0]$9442
+ attribute \src "libresoc.v:165437.3-165454.6"
+ wire $0\r_busy$next[0:0]$9317
+ attribute \src "libresoc.v:165371.3-165372.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:167747.3-167765.6"
- wire width 2 $0\xer_ca$24$next[1:0]$9465
- attribute \src "libresoc.v:167520.3-167521.37"
- wire width 2 $0\xer_ca$24[1:0]$9352
- attribute \src "libresoc.v:167455.13-167455.31"
- wire width 2 $0\xer_ca$24[1:0]$9531
- attribute \src "libresoc.v:167747.3-167765.6"
- wire $0\xer_ca_ok$25$next[0:0]$9466
- attribute \src "libresoc.v:167522.3-167523.43"
- wire $0\xer_ca_ok$25[0:0]$9354
- attribute \src "libresoc.v:167464.7-167464.28"
- wire $0\xer_ca_ok$25[0:0]$9533
- attribute \src "libresoc.v:167766.3-167784.6"
- wire width 2 $0\xer_ov$26$next[1:0]$9471
- attribute \src "libresoc.v:167516.3-167517.37"
- wire width 2 $0\xer_ov$26[1:0]$9348
- attribute \src "libresoc.v:167475.13-167475.31"
- wire width 2 $0\xer_ov$26[1:0]$9535
- attribute \src "libresoc.v:167766.3-167784.6"
- wire $0\xer_ov_ok$27$next[0:0]$9472
- attribute \src "libresoc.v:167518.3-167519.43"
- wire $0\xer_ov_ok$27[0:0]$9350
- attribute \src "libresoc.v:167484.7-167484.28"
- wire $0\xer_ov_ok$27[0:0]$9537
- attribute \src "libresoc.v:167785.3-167803.6"
- wire $0\xer_so$28$next[0:0]$9477
- attribute \src "libresoc.v:167512.3-167513.37"
- wire $0\xer_so$28[0:0]$9344
- attribute \src "libresoc.v:167495.7-167495.25"
- wire $0\xer_so$28[0:0]$9539
- attribute \src "libresoc.v:167785.3-167803.6"
- wire $0\xer_so_ok$29$next[0:0]$9478
- attribute \src "libresoc.v:167514.3-167515.43"
- wire $0\xer_so_ok$29[0:0]$9346
- attribute \src "libresoc.v:167504.7-167504.28"
- wire $0\xer_so_ok$29[0:0]$9541
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 4 $1\alu_op__data_len$18$next[3:0]$9428
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 13 $1\alu_op__fn_unit$3$next[12:0]$9429
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9430
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__imm_data__ok$5$next[0:0]$9431
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 2 $1\alu_op__input_carry$14$next[1:0]$9432
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 32 $1\alu_op__insn$19$next[31:0]$9433
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 7 $1\alu_op__insn_type$2$next[6:0]$9434
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__invert_in$10$next[0:0]$9435
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__invert_out$12$next[0:0]$9436
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__is_32bit$16$next[0:0]$9437
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__is_signed$17$next[0:0]$9438
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__oe__oe$8$next[0:0]$9439
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__oe__ok$9$next[0:0]$9440
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__output_carry$15$next[0:0]$9441
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__rc__ok$7$next[0:0]$9442
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__rc__rc$6$next[0:0]$9443
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__write_cr0$13$next[0:0]$9444
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $1\alu_op__zero_a$11$next[0:0]$9445
- attribute \src "libresoc.v:167728.3-167746.6"
- wire width 4 $1\cr_a$22$next[3:0]$9461
- attribute \src "libresoc.v:167728.3-167746.6"
- wire $1\cr_a_ok$23$next[0:0]$9462
- attribute \src "libresoc.v:167654.3-167666.6"
- wire width 2 $1\muxid$1$next[1:0]$9408
- attribute \src "libresoc.v:167709.3-167727.6"
- wire width 64 $1\o$20$next[63:0]$9455
- attribute \src "libresoc.v:167709.3-167727.6"
- wire $1\o_ok$21$next[0:0]$9456
- attribute \src "libresoc.v:167636.3-167653.6"
- wire $1\r_busy$next[0:0]$9404
- attribute \src "libresoc.v:167448.7-167448.20"
+ attribute \src "libresoc.v:165548.3-165566.6"
+ wire width 2 $0\xer_ca$24$next[1:0]$9379
+ attribute \src "libresoc.v:165321.3-165322.37"
+ wire width 2 $0\xer_ca$24[1:0]$9266
+ attribute \src "libresoc.v:165256.13-165256.31"
+ wire width 2 $0\xer_ca$24[1:0]$9445
+ attribute \src "libresoc.v:165548.3-165566.6"
+ wire $0\xer_ca_ok$25$next[0:0]$9380
+ attribute \src "libresoc.v:165323.3-165324.43"
+ wire $0\xer_ca_ok$25[0:0]$9268
+ attribute \src "libresoc.v:165265.7-165265.28"
+ wire $0\xer_ca_ok$25[0:0]$9447
+ attribute \src "libresoc.v:165567.3-165585.6"
+ wire width 2 $0\xer_ov$26$next[1:0]$9385
+ attribute \src "libresoc.v:165317.3-165318.37"
+ wire width 2 $0\xer_ov$26[1:0]$9262
+ attribute \src "libresoc.v:165276.13-165276.31"
+ wire width 2 $0\xer_ov$26[1:0]$9449
+ attribute \src "libresoc.v:165567.3-165585.6"
+ wire $0\xer_ov_ok$27$next[0:0]$9386
+ attribute \src "libresoc.v:165319.3-165320.43"
+ wire $0\xer_ov_ok$27[0:0]$9264
+ attribute \src "libresoc.v:165285.7-165285.28"
+ wire $0\xer_ov_ok$27[0:0]$9451
+ attribute \src "libresoc.v:165586.3-165604.6"
+ wire $0\xer_so$28$next[0:0]$9391
+ attribute \src "libresoc.v:165313.3-165314.37"
+ wire $0\xer_so$28[0:0]$9258
+ attribute \src "libresoc.v:165296.7-165296.25"
+ wire $0\xer_so$28[0:0]$9453
+ attribute \src "libresoc.v:165586.3-165604.6"
+ wire $0\xer_so_ok$29$next[0:0]$9392
+ attribute \src "libresoc.v:165315.3-165316.43"
+ wire $0\xer_so_ok$29[0:0]$9260
+ attribute \src "libresoc.v:165305.7-165305.28"
+ wire $0\xer_so_ok$29[0:0]$9455
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 4 $1\alu_op__data_len$18$next[3:0]$9342
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 13 $1\alu_op__fn_unit$3$next[12:0]$9343
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9344
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__imm_data__ok$5$next[0:0]$9345
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 2 $1\alu_op__input_carry$14$next[1:0]$9346
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 32 $1\alu_op__insn$19$next[31:0]$9347
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 7 $1\alu_op__insn_type$2$next[6:0]$9348
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__invert_in$10$next[0:0]$9349
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__invert_out$12$next[0:0]$9350
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__is_32bit$16$next[0:0]$9351
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__is_signed$17$next[0:0]$9352
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__oe__oe$8$next[0:0]$9353
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__oe__ok$9$next[0:0]$9354
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__output_carry$15$next[0:0]$9355
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__rc__ok$7$next[0:0]$9356
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__rc__rc$6$next[0:0]$9357
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__write_cr0$13$next[0:0]$9358
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $1\alu_op__zero_a$11$next[0:0]$9359
+ attribute \src "libresoc.v:165529.3-165547.6"
+ wire width 4 $1\cr_a$22$next[3:0]$9375
+ attribute \src "libresoc.v:165529.3-165547.6"
+ wire $1\cr_a_ok$23$next[0:0]$9376
+ attribute \src "libresoc.v:165455.3-165467.6"
+ wire width 2 $1\muxid$1$next[1:0]$9322
+ attribute \src "libresoc.v:165510.3-165528.6"
+ wire width 64 $1\o$20$next[63:0]$9369
+ attribute \src "libresoc.v:165510.3-165528.6"
+ wire $1\o_ok$21$next[0:0]$9370
+ attribute \src "libresoc.v:165437.3-165454.6"
+ wire $1\r_busy$next[0:0]$9318
+ attribute \src "libresoc.v:165249.7-165249.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:167747.3-167765.6"
- wire width 2 $1\xer_ca$24$next[1:0]$9467
- attribute \src "libresoc.v:167747.3-167765.6"
- wire $1\xer_ca_ok$25$next[0:0]$9468
- attribute \src "libresoc.v:167766.3-167784.6"
- wire width 2 $1\xer_ov$26$next[1:0]$9473
- attribute \src "libresoc.v:167766.3-167784.6"
- wire $1\xer_ov_ok$27$next[0:0]$9474
- attribute \src "libresoc.v:167785.3-167803.6"
- wire $1\xer_so$28$next[0:0]$9479
- attribute \src "libresoc.v:167785.3-167803.6"
- wire $1\xer_so_ok$29$next[0:0]$9480
- attribute \src "libresoc.v:167667.3-167708.6"
- wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9446
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $2\alu_op__imm_data__ok$5$next[0:0]$9447
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $2\alu_op__oe__oe$8$next[0:0]$9448
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $2\alu_op__oe__ok$9$next[0:0]$9449
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $2\alu_op__rc__ok$7$next[0:0]$9450
- attribute \src "libresoc.v:167667.3-167708.6"
- wire $2\alu_op__rc__rc$6$next[0:0]$9451
- attribute \src "libresoc.v:167728.3-167746.6"
- wire $2\cr_a_ok$23$next[0:0]$9463
- attribute \src "libresoc.v:167709.3-167727.6"
- wire $2\o_ok$21$next[0:0]$9457
- attribute \src "libresoc.v:167636.3-167653.6"
- wire $2\r_busy$next[0:0]$9405
- attribute \src "libresoc.v:167747.3-167765.6"
- wire $2\xer_ca_ok$25$next[0:0]$9469
- attribute \src "libresoc.v:167766.3-167784.6"
- wire $2\xer_ov_ok$27$next[0:0]$9475
- attribute \src "libresoc.v:167785.3-167803.6"
- wire $2\xer_so_ok$29$next[0:0]$9481
- attribute \src "libresoc.v:167511.18-167511.118"
- wire $and$libresoc.v:167511$9342_Y
+ attribute \src "libresoc.v:165548.3-165566.6"
+ wire width 2 $1\xer_ca$24$next[1:0]$9381
+ attribute \src "libresoc.v:165548.3-165566.6"
+ wire $1\xer_ca_ok$25$next[0:0]$9382
+ attribute \src "libresoc.v:165567.3-165585.6"
+ wire width 2 $1\xer_ov$26$next[1:0]$9387
+ attribute \src "libresoc.v:165567.3-165585.6"
+ wire $1\xer_ov_ok$27$next[0:0]$9388
+ attribute \src "libresoc.v:165586.3-165604.6"
+ wire $1\xer_so$28$next[0:0]$9393
+ attribute \src "libresoc.v:165586.3-165604.6"
+ wire $1\xer_so_ok$29$next[0:0]$9394
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9360
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $2\alu_op__imm_data__ok$5$next[0:0]$9361
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $2\alu_op__oe__oe$8$next[0:0]$9362
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $2\alu_op__oe__ok$9$next[0:0]$9363
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $2\alu_op__rc__ok$7$next[0:0]$9364
+ attribute \src "libresoc.v:165468.3-165509.6"
+ wire $2\alu_op__rc__rc$6$next[0:0]$9365
+ attribute \src "libresoc.v:165529.3-165547.6"
+ wire $2\cr_a_ok$23$next[0:0]$9377
+ attribute \src "libresoc.v:165510.3-165528.6"
+ wire $2\o_ok$21$next[0:0]$9371
+ attribute \src "libresoc.v:165437.3-165454.6"
+ wire $2\r_busy$next[0:0]$9319
+ attribute \src "libresoc.v:165548.3-165566.6"
+ wire $2\xer_ca_ok$25$next[0:0]$9383
+ attribute \src "libresoc.v:165567.3-165585.6"
+ wire $2\xer_ov_ok$27$next[0:0]$9389
+ attribute \src "libresoc.v:165586.3-165604.6"
+ wire $2\xer_so_ok$29$next[0:0]$9395
+ attribute \src "libresoc.v:165312.18-165312.118"
+ wire $and$libresoc.v:165312$9256_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$11$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 64 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 25 \cr_a
wire \cr_a_ok$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$84
- attribute \src "libresoc.v:166649.7-166649.15"
+ attribute \src "libresoc.v:164450.7-164450.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$90
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:167511$9342
+ cell $and $and$libresoc.v:165312$9256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$59
connect \B \p_ready_o
- connect \Y $and$libresoc.v:167511$9342_Y
+ connect \Y $and$libresoc.v:165312$9256_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:167572.9-167575.4"
+ attribute \src "libresoc.v:165373.9-165376.4"
cell \n$4 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:167576.12-167631.4"
+ attribute \src "libresoc.v:165377.12-165432.4"
cell \output \output
connect \alu_op__data_len \output_alu_op__data_len
connect \alu_op__data_len$18 \output_alu_op__data_len$47
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:167632.9-167635.4"
+ attribute \src "libresoc.v:165433.9-165436.4"
cell \p$3 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:166649.7-166649.20"
- process $proc$libresoc.v:166649$9482
+ attribute \src "libresoc.v:164450.7-164450.20"
+ process $proc$libresoc.v:164450$9396
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:166656.13-166656.41"
- process $proc$libresoc.v:166656$9483
+ attribute \src "libresoc.v:164457.13-164457.41"
+ process $proc$libresoc.v:164457$9397
assign { } { }
- assign $0\alu_op__data_len$18[3:0]$9484 4'0000
+ assign $0\alu_op__data_len$18[3:0]$9398 4'0000
sync always
sync init
- update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9484
+ update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9398
end
- attribute \src "libresoc.v:166693.14-166693.44"
- process $proc$libresoc.v:166693$9485
+ attribute \src "libresoc.v:164494.14-164494.44"
+ process $proc$libresoc.v:164494$9399
assign { } { }
- assign $0\alu_op__fn_unit$3[12:0]$9486 13'0000000000000
+ assign $0\alu_op__fn_unit$3[12:0]$9400 13'0000000000000
sync always
sync init
- update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9486
+ update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9400
end
- attribute \src "libresoc.v:166716.14-166716.63"
- process $proc$libresoc.v:166716$9487
+ attribute \src "libresoc.v:164517.14-164517.63"
+ process $proc$libresoc.v:164517$9401
assign { } { }
- assign $0\alu_op__imm_data__data$4[63:0]$9488 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\alu_op__imm_data__data$4[63:0]$9402 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9488
+ update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9402
end
- attribute \src "libresoc.v:166725.7-166725.38"
- process $proc$libresoc.v:166725$9489
+ attribute \src "libresoc.v:164526.7-164526.38"
+ process $proc$libresoc.v:164526$9403
assign { } { }
- assign $0\alu_op__imm_data__ok$5[0:0]$9490 1'0
+ assign $0\alu_op__imm_data__ok$5[0:0]$9404 1'0
sync always
sync init
- update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9490
+ update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9404
end
- attribute \src "libresoc.v:166742.13-166742.44"
- process $proc$libresoc.v:166742$9491
+ attribute \src "libresoc.v:164543.13-164543.44"
+ process $proc$libresoc.v:164543$9405
assign { } { }
- assign $0\alu_op__input_carry$14[1:0]$9492 2'00
+ assign $0\alu_op__input_carry$14[1:0]$9406 2'00
sync always
sync init
- update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9492
+ update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9406
end
- attribute \src "libresoc.v:166755.14-166755.39"
- process $proc$libresoc.v:166755$9493
+ attribute \src "libresoc.v:164556.14-164556.39"
+ process $proc$libresoc.v:164556$9407
assign { } { }
- assign $0\alu_op__insn$19[31:0]$9494 0
+ assign $0\alu_op__insn$19[31:0]$9408 0
sync always
sync init
- update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9494
+ update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9408
end
- attribute \src "libresoc.v:166912.13-166912.42"
- process $proc$libresoc.v:166912$9495
+ attribute \src "libresoc.v:164713.13-164713.42"
+ process $proc$libresoc.v:164713$9409
assign { } { }
- assign $0\alu_op__insn_type$2[6:0]$9496 7'0000000
+ assign $0\alu_op__insn_type$2[6:0]$9410 7'0000000
sync always
sync init
- update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9496
+ update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9410
end
- attribute \src "libresoc.v:166995.7-166995.36"
- process $proc$libresoc.v:166995$9497
+ attribute \src "libresoc.v:164796.7-164796.36"
+ process $proc$libresoc.v:164796$9411
assign { } { }
- assign $0\alu_op__invert_in$10[0:0]$9498 1'0
+ assign $0\alu_op__invert_in$10[0:0]$9412 1'0
sync always
sync init
- update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9498
+ update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9412
end
- attribute \src "libresoc.v:167004.7-167004.37"
- process $proc$libresoc.v:167004$9499
+ attribute \src "libresoc.v:164805.7-164805.37"
+ process $proc$libresoc.v:164805$9413
assign { } { }
- assign $0\alu_op__invert_out$12[0:0]$9500 1'0
+ assign $0\alu_op__invert_out$12[0:0]$9414 1'0
sync always
sync init
- update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9500
+ update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9414
end
- attribute \src "libresoc.v:167013.7-167013.35"
- process $proc$libresoc.v:167013$9501
+ attribute \src "libresoc.v:164814.7-164814.35"
+ process $proc$libresoc.v:164814$9415
assign { } { }
- assign $0\alu_op__is_32bit$16[0:0]$9502 1'0
+ assign $0\alu_op__is_32bit$16[0:0]$9416 1'0
sync always
sync init
- update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9502
+ update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9416
end
- attribute \src "libresoc.v:167022.7-167022.36"
- process $proc$libresoc.v:167022$9503
+ attribute \src "libresoc.v:164823.7-164823.36"
+ process $proc$libresoc.v:164823$9417
assign { } { }
- assign $0\alu_op__is_signed$17[0:0]$9504 1'0
+ assign $0\alu_op__is_signed$17[0:0]$9418 1'0
sync always
sync init
- update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9504
+ update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9418
end
- attribute \src "libresoc.v:167033.7-167033.32"
- process $proc$libresoc.v:167033$9505
+ attribute \src "libresoc.v:164834.7-164834.32"
+ process $proc$libresoc.v:164834$9419
assign { } { }
- assign $0\alu_op__oe__oe$8[0:0]$9506 1'0
+ assign $0\alu_op__oe__oe$8[0:0]$9420 1'0
sync always
sync init
- update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9506
+ update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9420
end
- attribute \src "libresoc.v:167042.7-167042.32"
- process $proc$libresoc.v:167042$9507
+ attribute \src "libresoc.v:164843.7-164843.32"
+ process $proc$libresoc.v:164843$9421
assign { } { }
- assign $0\alu_op__oe__ok$9[0:0]$9508 1'0
+ assign $0\alu_op__oe__ok$9[0:0]$9422 1'0
sync always
sync init
- update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9508
+ update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9422
end
- attribute \src "libresoc.v:167049.7-167049.39"
- process $proc$libresoc.v:167049$9509
+ attribute \src "libresoc.v:164850.7-164850.39"
+ process $proc$libresoc.v:164850$9423
assign { } { }
- assign $0\alu_op__output_carry$15[0:0]$9510 1'0
+ assign $0\alu_op__output_carry$15[0:0]$9424 1'0
sync always
sync init
- update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9510
+ update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9424
end
- attribute \src "libresoc.v:167060.7-167060.32"
- process $proc$libresoc.v:167060$9511
+ attribute \src "libresoc.v:164861.7-164861.32"
+ process $proc$libresoc.v:164861$9425
assign { } { }
- assign $0\alu_op__rc__ok$7[0:0]$9512 1'0
+ assign $0\alu_op__rc__ok$7[0:0]$9426 1'0
sync always
sync init
- update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9512
+ update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9426
end
- attribute \src "libresoc.v:167067.7-167067.32"
- process $proc$libresoc.v:167067$9513
+ attribute \src "libresoc.v:164868.7-164868.32"
+ process $proc$libresoc.v:164868$9427
assign { } { }
- assign $0\alu_op__rc__rc$6[0:0]$9514 1'0
+ assign $0\alu_op__rc__rc$6[0:0]$9428 1'0
sync always
sync init
- update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9514
+ update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9428
end
- attribute \src "libresoc.v:167076.7-167076.36"
- process $proc$libresoc.v:167076$9515
+ attribute \src "libresoc.v:164877.7-164877.36"
+ process $proc$libresoc.v:164877$9429
assign { } { }
- assign $0\alu_op__write_cr0$13[0:0]$9516 1'0
+ assign $0\alu_op__write_cr0$13[0:0]$9430 1'0
sync always
sync init
- update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9516
+ update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9430
end
- attribute \src "libresoc.v:167085.7-167085.33"
- process $proc$libresoc.v:167085$9517
+ attribute \src "libresoc.v:164886.7-164886.33"
+ process $proc$libresoc.v:164886$9431
assign { } { }
- assign $0\alu_op__zero_a$11[0:0]$9518 1'0
+ assign $0\alu_op__zero_a$11[0:0]$9432 1'0
sync always
sync init
- update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9518
+ update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9432
end
- attribute \src "libresoc.v:167098.13-167098.29"
- process $proc$libresoc.v:167098$9519
+ attribute \src "libresoc.v:164899.13-164899.29"
+ process $proc$libresoc.v:164899$9433
assign { } { }
- assign $0\cr_a$22[3:0]$9520 4'0000
+ assign $0\cr_a$22[3:0]$9434 4'0000
sync always
sync init
- update \cr_a$22 $0\cr_a$22[3:0]$9520
+ update \cr_a$22 $0\cr_a$22[3:0]$9434
end
- attribute \src "libresoc.v:167107.7-167107.26"
- process $proc$libresoc.v:167107$9521
+ attribute \src "libresoc.v:164908.7-164908.26"
+ process $proc$libresoc.v:164908$9435
assign { } { }
- assign $0\cr_a_ok$23[0:0]$9522 1'0
+ assign $0\cr_a_ok$23[0:0]$9436 1'0
sync always
sync init
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9522
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9436
end
- attribute \src "libresoc.v:167118.13-167118.29"
- process $proc$libresoc.v:167118$9523
+ attribute \src "libresoc.v:164919.13-164919.29"
+ process $proc$libresoc.v:164919$9437
assign { } { }
- assign $0\muxid$1[1:0]$9524 2'00
+ assign $0\muxid$1[1:0]$9438 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9524
+ update \muxid$1 $0\muxid$1[1:0]$9438
end
- attribute \src "libresoc.v:167133.14-167133.43"
- process $proc$libresoc.v:167133$9525
+ attribute \src "libresoc.v:164934.14-164934.43"
+ process $proc$libresoc.v:164934$9439
assign { } { }
- assign $0\o$20[63:0]$9526 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$20[63:0]$9440 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$20 $0\o$20[63:0]$9526
+ update \o$20 $0\o$20[63:0]$9440
end
- attribute \src "libresoc.v:167142.7-167142.23"
- process $proc$libresoc.v:167142$9527
+ attribute \src "libresoc.v:164943.7-164943.23"
+ process $proc$libresoc.v:164943$9441
assign { } { }
- assign $0\o_ok$21[0:0]$9528 1'0
+ assign $0\o_ok$21[0:0]$9442 1'0
sync always
sync init
- update \o_ok$21 $0\o_ok$21[0:0]$9528
+ update \o_ok$21 $0\o_ok$21[0:0]$9442
end
- attribute \src "libresoc.v:167448.7-167448.20"
- process $proc$libresoc.v:167448$9529
+ attribute \src "libresoc.v:165249.7-165249.20"
+ process $proc$libresoc.v:165249$9443
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:167455.13-167455.31"
- process $proc$libresoc.v:167455$9530
+ attribute \src "libresoc.v:165256.13-165256.31"
+ process $proc$libresoc.v:165256$9444
assign { } { }
- assign $0\xer_ca$24[1:0]$9531 2'00
+ assign $0\xer_ca$24[1:0]$9445 2'00
sync always
sync init
- update \xer_ca$24 $0\xer_ca$24[1:0]$9531
+ update \xer_ca$24 $0\xer_ca$24[1:0]$9445
end
- attribute \src "libresoc.v:167464.7-167464.28"
- process $proc$libresoc.v:167464$9532
+ attribute \src "libresoc.v:165265.7-165265.28"
+ process $proc$libresoc.v:165265$9446
assign { } { }
- assign $0\xer_ca_ok$25[0:0]$9533 1'0
+ assign $0\xer_ca_ok$25[0:0]$9447 1'0
sync always
sync init
- update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9533
+ update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9447
end
- attribute \src "libresoc.v:167475.13-167475.31"
- process $proc$libresoc.v:167475$9534
+ attribute \src "libresoc.v:165276.13-165276.31"
+ process $proc$libresoc.v:165276$9448
assign { } { }
- assign $0\xer_ov$26[1:0]$9535 2'00
+ assign $0\xer_ov$26[1:0]$9449 2'00
sync always
sync init
- update \xer_ov$26 $0\xer_ov$26[1:0]$9535
+ update \xer_ov$26 $0\xer_ov$26[1:0]$9449
end
- attribute \src "libresoc.v:167484.7-167484.28"
- process $proc$libresoc.v:167484$9536
+ attribute \src "libresoc.v:165285.7-165285.28"
+ process $proc$libresoc.v:165285$9450
assign { } { }
- assign $0\xer_ov_ok$27[0:0]$9537 1'0
+ assign $0\xer_ov_ok$27[0:0]$9451 1'0
sync always
sync init
- update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9537
+ update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9451
end
- attribute \src "libresoc.v:167495.7-167495.25"
- process $proc$libresoc.v:167495$9538
+ attribute \src "libresoc.v:165296.7-165296.25"
+ process $proc$libresoc.v:165296$9452
assign { } { }
- assign $0\xer_so$28[0:0]$9539 1'0
+ assign $0\xer_so$28[0:0]$9453 1'0
sync always
sync init
- update \xer_so$28 $0\xer_so$28[0:0]$9539
+ update \xer_so$28 $0\xer_so$28[0:0]$9453
end
- attribute \src "libresoc.v:167504.7-167504.28"
- process $proc$libresoc.v:167504$9540
+ attribute \src "libresoc.v:165305.7-165305.28"
+ process $proc$libresoc.v:165305$9454
assign { } { }
- assign $0\xer_so_ok$29[0:0]$9541 1'0
+ assign $0\xer_so_ok$29[0:0]$9455 1'0
sync always
sync init
- update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9541
+ update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9455
end
- attribute \src "libresoc.v:167512.3-167513.37"
- process $proc$libresoc.v:167512$9343
+ attribute \src "libresoc.v:165313.3-165314.37"
+ process $proc$libresoc.v:165313$9257
assign { } { }
- assign $0\xer_so$28[0:0]$9344 \xer_so$28$next
+ assign $0\xer_so$28[0:0]$9258 \xer_so$28$next
sync posedge \coresync_clk
- update \xer_so$28 $0\xer_so$28[0:0]$9344
+ update \xer_so$28 $0\xer_so$28[0:0]$9258
end
- attribute \src "libresoc.v:167514.3-167515.43"
- process $proc$libresoc.v:167514$9345
+ attribute \src "libresoc.v:165315.3-165316.43"
+ process $proc$libresoc.v:165315$9259
assign { } { }
- assign $0\xer_so_ok$29[0:0]$9346 \xer_so_ok$29$next
+ assign $0\xer_so_ok$29[0:0]$9260 \xer_so_ok$29$next
sync posedge \coresync_clk
- update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9346
+ update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9260
end
- attribute \src "libresoc.v:167516.3-167517.37"
- process $proc$libresoc.v:167516$9347
+ attribute \src "libresoc.v:165317.3-165318.37"
+ process $proc$libresoc.v:165317$9261
assign { } { }
- assign $0\xer_ov$26[1:0]$9348 \xer_ov$26$next
+ assign $0\xer_ov$26[1:0]$9262 \xer_ov$26$next
sync posedge \coresync_clk
- update \xer_ov$26 $0\xer_ov$26[1:0]$9348
+ update \xer_ov$26 $0\xer_ov$26[1:0]$9262
end
- attribute \src "libresoc.v:167518.3-167519.43"
- process $proc$libresoc.v:167518$9349
+ attribute \src "libresoc.v:165319.3-165320.43"
+ process $proc$libresoc.v:165319$9263
assign { } { }
- assign $0\xer_ov_ok$27[0:0]$9350 \xer_ov_ok$27$next
+ assign $0\xer_ov_ok$27[0:0]$9264 \xer_ov_ok$27$next
sync posedge \coresync_clk
- update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9350
+ update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9264
end
- attribute \src "libresoc.v:167520.3-167521.37"
- process $proc$libresoc.v:167520$9351
+ attribute \src "libresoc.v:165321.3-165322.37"
+ process $proc$libresoc.v:165321$9265
assign { } { }
- assign $0\xer_ca$24[1:0]$9352 \xer_ca$24$next
+ assign $0\xer_ca$24[1:0]$9266 \xer_ca$24$next
sync posedge \coresync_clk
- update \xer_ca$24 $0\xer_ca$24[1:0]$9352
+ update \xer_ca$24 $0\xer_ca$24[1:0]$9266
end
- attribute \src "libresoc.v:167522.3-167523.43"
- process $proc$libresoc.v:167522$9353
+ attribute \src "libresoc.v:165323.3-165324.43"
+ process $proc$libresoc.v:165323$9267
assign { } { }
- assign $0\xer_ca_ok$25[0:0]$9354 \xer_ca_ok$25$next
+ assign $0\xer_ca_ok$25[0:0]$9268 \xer_ca_ok$25$next
sync posedge \coresync_clk
- update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9354
+ update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9268
end
- attribute \src "libresoc.v:167524.3-167525.33"
- process $proc$libresoc.v:167524$9355
+ attribute \src "libresoc.v:165325.3-165326.33"
+ process $proc$libresoc.v:165325$9269
assign { } { }
- assign $0\cr_a$22[3:0]$9356 \cr_a$22$next
+ assign $0\cr_a$22[3:0]$9270 \cr_a$22$next
sync posedge \coresync_clk
- update \cr_a$22 $0\cr_a$22[3:0]$9356
+ update \cr_a$22 $0\cr_a$22[3:0]$9270
end
- attribute \src "libresoc.v:167526.3-167527.39"
- process $proc$libresoc.v:167526$9357
+ attribute \src "libresoc.v:165327.3-165328.39"
+ process $proc$libresoc.v:165327$9271
assign { } { }
- assign $0\cr_a_ok$23[0:0]$9358 \cr_a_ok$23$next
+ assign $0\cr_a_ok$23[0:0]$9272 \cr_a_ok$23$next
sync posedge \coresync_clk
- update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9358
+ update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9272
end
- attribute \src "libresoc.v:167528.3-167529.27"
- process $proc$libresoc.v:167528$9359
+ attribute \src "libresoc.v:165329.3-165330.27"
+ process $proc$libresoc.v:165329$9273
assign { } { }
- assign $0\o$20[63:0]$9360 \o$20$next
+ assign $0\o$20[63:0]$9274 \o$20$next
sync posedge \coresync_clk
- update \o$20 $0\o$20[63:0]$9360
+ update \o$20 $0\o$20[63:0]$9274
end
- attribute \src "libresoc.v:167530.3-167531.33"
- process $proc$libresoc.v:167530$9361
+ attribute \src "libresoc.v:165331.3-165332.33"
+ process $proc$libresoc.v:165331$9275
assign { } { }
- assign $0\o_ok$21[0:0]$9362 \o_ok$21$next
+ assign $0\o_ok$21[0:0]$9276 \o_ok$21$next
sync posedge \coresync_clk
- update \o_ok$21 $0\o_ok$21[0:0]$9362
+ update \o_ok$21 $0\o_ok$21[0:0]$9276
end
- attribute \src "libresoc.v:167532.3-167533.57"
- process $proc$libresoc.v:167532$9363
+ attribute \src "libresoc.v:165333.3-165334.57"
+ process $proc$libresoc.v:165333$9277
assign { } { }
- assign $0\alu_op__insn_type$2[6:0]$9364 \alu_op__insn_type$2$next
+ assign $0\alu_op__insn_type$2[6:0]$9278 \alu_op__insn_type$2$next
sync posedge \coresync_clk
- update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9364
+ update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9278
end
- attribute \src "libresoc.v:167534.3-167535.53"
- process $proc$libresoc.v:167534$9365
+ attribute \src "libresoc.v:165335.3-165336.53"
+ process $proc$libresoc.v:165335$9279
assign { } { }
- assign $0\alu_op__fn_unit$3[12:0]$9366 \alu_op__fn_unit$3$next
+ assign $0\alu_op__fn_unit$3[12:0]$9280 \alu_op__fn_unit$3$next
sync posedge \coresync_clk
- update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9366
+ update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9280
end
- attribute \src "libresoc.v:167536.3-167537.67"
- process $proc$libresoc.v:167536$9367
+ attribute \src "libresoc.v:165337.3-165338.67"
+ process $proc$libresoc.v:165337$9281
assign { } { }
- assign $0\alu_op__imm_data__data$4[63:0]$9368 \alu_op__imm_data__data$4$next
+ assign $0\alu_op__imm_data__data$4[63:0]$9282 \alu_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9368
+ update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9282
end
- attribute \src "libresoc.v:167538.3-167539.63"
- process $proc$libresoc.v:167538$9369
+ attribute \src "libresoc.v:165339.3-165340.63"
+ process $proc$libresoc.v:165339$9283
assign { } { }
- assign $0\alu_op__imm_data__ok$5[0:0]$9370 \alu_op__imm_data__ok$5$next
+ assign $0\alu_op__imm_data__ok$5[0:0]$9284 \alu_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9370
+ update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9284
end
- attribute \src "libresoc.v:167540.3-167541.51"
- process $proc$libresoc.v:167540$9371
+ attribute \src "libresoc.v:165341.3-165342.51"
+ process $proc$libresoc.v:165341$9285
assign { } { }
- assign $0\alu_op__rc__rc$6[0:0]$9372 \alu_op__rc__rc$6$next
+ assign $0\alu_op__rc__rc$6[0:0]$9286 \alu_op__rc__rc$6$next
sync posedge \coresync_clk
- update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9372
+ update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9286
end
- attribute \src "libresoc.v:167542.3-167543.51"
- process $proc$libresoc.v:167542$9373
+ attribute \src "libresoc.v:165343.3-165344.51"
+ process $proc$libresoc.v:165343$9287
assign { } { }
- assign $0\alu_op__rc__ok$7[0:0]$9374 \alu_op__rc__ok$7$next
+ assign $0\alu_op__rc__ok$7[0:0]$9288 \alu_op__rc__ok$7$next
sync posedge \coresync_clk
- update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9374
+ update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9288
end
- attribute \src "libresoc.v:167544.3-167545.51"
- process $proc$libresoc.v:167544$9375
+ attribute \src "libresoc.v:165345.3-165346.51"
+ process $proc$libresoc.v:165345$9289
assign { } { }
- assign $0\alu_op__oe__oe$8[0:0]$9376 \alu_op__oe__oe$8$next
+ assign $0\alu_op__oe__oe$8[0:0]$9290 \alu_op__oe__oe$8$next
sync posedge \coresync_clk
- update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9376
+ update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9290
end
- attribute \src "libresoc.v:167546.3-167547.51"
- process $proc$libresoc.v:167546$9377
+ attribute \src "libresoc.v:165347.3-165348.51"
+ process $proc$libresoc.v:165347$9291
assign { } { }
- assign $0\alu_op__oe__ok$9[0:0]$9378 \alu_op__oe__ok$9$next
+ assign $0\alu_op__oe__ok$9[0:0]$9292 \alu_op__oe__ok$9$next
sync posedge \coresync_clk
- update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9378
+ update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9292
end
- attribute \src "libresoc.v:167548.3-167549.59"
- process $proc$libresoc.v:167548$9379
+ attribute \src "libresoc.v:165349.3-165350.59"
+ process $proc$libresoc.v:165349$9293
assign { } { }
- assign $0\alu_op__invert_in$10[0:0]$9380 \alu_op__invert_in$10$next
+ assign $0\alu_op__invert_in$10[0:0]$9294 \alu_op__invert_in$10$next
sync posedge \coresync_clk
- update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9380
+ update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9294
end
- attribute \src "libresoc.v:167550.3-167551.53"
- process $proc$libresoc.v:167550$9381
+ attribute \src "libresoc.v:165351.3-165352.53"
+ process $proc$libresoc.v:165351$9295
assign { } { }
- assign $0\alu_op__zero_a$11[0:0]$9382 \alu_op__zero_a$11$next
+ assign $0\alu_op__zero_a$11[0:0]$9296 \alu_op__zero_a$11$next
sync posedge \coresync_clk
- update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9382
+ update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9296
end
- attribute \src "libresoc.v:167552.3-167553.61"
- process $proc$libresoc.v:167552$9383
+ attribute \src "libresoc.v:165353.3-165354.61"
+ process $proc$libresoc.v:165353$9297
assign { } { }
- assign $0\alu_op__invert_out$12[0:0]$9384 \alu_op__invert_out$12$next
+ assign $0\alu_op__invert_out$12[0:0]$9298 \alu_op__invert_out$12$next
sync posedge \coresync_clk
- update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9384
+ update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9298
end
- attribute \src "libresoc.v:167554.3-167555.59"
- process $proc$libresoc.v:167554$9385
+ attribute \src "libresoc.v:165355.3-165356.59"
+ process $proc$libresoc.v:165355$9299
assign { } { }
- assign $0\alu_op__write_cr0$13[0:0]$9386 \alu_op__write_cr0$13$next
+ assign $0\alu_op__write_cr0$13[0:0]$9300 \alu_op__write_cr0$13$next
sync posedge \coresync_clk
- update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9386
+ update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9300
end
- attribute \src "libresoc.v:167556.3-167557.63"
- process $proc$libresoc.v:167556$9387
+ attribute \src "libresoc.v:165357.3-165358.63"
+ process $proc$libresoc.v:165357$9301
assign { } { }
- assign $0\alu_op__input_carry$14[1:0]$9388 \alu_op__input_carry$14$next
+ assign $0\alu_op__input_carry$14[1:0]$9302 \alu_op__input_carry$14$next
sync posedge \coresync_clk
- update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9388
+ update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9302
end
- attribute \src "libresoc.v:167558.3-167559.65"
- process $proc$libresoc.v:167558$9389
+ attribute \src "libresoc.v:165359.3-165360.65"
+ process $proc$libresoc.v:165359$9303
assign { } { }
- assign $0\alu_op__output_carry$15[0:0]$9390 \alu_op__output_carry$15$next
+ assign $0\alu_op__output_carry$15[0:0]$9304 \alu_op__output_carry$15$next
sync posedge \coresync_clk
- update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9390
+ update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9304
end
- attribute \src "libresoc.v:167560.3-167561.57"
- process $proc$libresoc.v:167560$9391
+ attribute \src "libresoc.v:165361.3-165362.57"
+ process $proc$libresoc.v:165361$9305
assign { } { }
- assign $0\alu_op__is_32bit$16[0:0]$9392 \alu_op__is_32bit$16$next
+ assign $0\alu_op__is_32bit$16[0:0]$9306 \alu_op__is_32bit$16$next
sync posedge \coresync_clk
- update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9392
+ update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9306
end
- attribute \src "libresoc.v:167562.3-167563.59"
- process $proc$libresoc.v:167562$9393
+ attribute \src "libresoc.v:165363.3-165364.59"
+ process $proc$libresoc.v:165363$9307
assign { } { }
- assign $0\alu_op__is_signed$17[0:0]$9394 \alu_op__is_signed$17$next
+ assign $0\alu_op__is_signed$17[0:0]$9308 \alu_op__is_signed$17$next
sync posedge \coresync_clk
- update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9394
+ update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9308
end
- attribute \src "libresoc.v:167564.3-167565.57"
- process $proc$libresoc.v:167564$9395
+ attribute \src "libresoc.v:165365.3-165366.57"
+ process $proc$libresoc.v:165365$9309
assign { } { }
- assign $0\alu_op__data_len$18[3:0]$9396 \alu_op__data_len$18$next
+ assign $0\alu_op__data_len$18[3:0]$9310 \alu_op__data_len$18$next
sync posedge \coresync_clk
- update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9396
+ update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9310
end
- attribute \src "libresoc.v:167566.3-167567.49"
- process $proc$libresoc.v:167566$9397
+ attribute \src "libresoc.v:165367.3-165368.49"
+ process $proc$libresoc.v:165367$9311
assign { } { }
- assign $0\alu_op__insn$19[31:0]$9398 \alu_op__insn$19$next
+ assign $0\alu_op__insn$19[31:0]$9312 \alu_op__insn$19$next
sync posedge \coresync_clk
- update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9398
+ update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9312
end
- attribute \src "libresoc.v:167568.3-167569.33"
- process $proc$libresoc.v:167568$9399
+ attribute \src "libresoc.v:165369.3-165370.33"
+ process $proc$libresoc.v:165369$9313
assign { } { }
- assign $0\muxid$1[1:0]$9400 \muxid$1$next
+ assign $0\muxid$1[1:0]$9314 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9400
+ update \muxid$1 $0\muxid$1[1:0]$9314
end
- attribute \src "libresoc.v:167570.3-167571.29"
- process $proc$libresoc.v:167570$9401
+ attribute \src "libresoc.v:165371.3-165372.29"
+ process $proc$libresoc.v:165371$9315
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:167636.3-167653.6"
- process $proc$libresoc.v:167636$9402
+ attribute \src "libresoc.v:165437.3-165454.6"
+ process $proc$libresoc.v:165437$9316
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9403 $2\r_busy$next[0:0]$9405
- attribute \src "libresoc.v:167637.5-167637.29"
+ assign $0\r_busy$next[0:0]$9317 $2\r_busy$next[0:0]$9319
+ attribute \src "libresoc.v:165438.5-165438.29"
switch \initial
- attribute \src "libresoc.v:167637.9-167637.17"
+ attribute \src "libresoc.v:165438.9-165438.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9404 1'1
+ assign $1\r_busy$next[0:0]$9318 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9404 1'0
+ assign $1\r_busy$next[0:0]$9318 1'0
case
- assign $1\r_busy$next[0:0]$9404 \r_busy
+ assign $1\r_busy$next[0:0]$9318 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9405 1'0
+ assign $2\r_busy$next[0:0]$9319 1'0
case
- assign $2\r_busy$next[0:0]$9405 $1\r_busy$next[0:0]$9404
+ assign $2\r_busy$next[0:0]$9319 $1\r_busy$next[0:0]$9318
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9403
+ update \r_busy$next $0\r_busy$next[0:0]$9317
end
- attribute \src "libresoc.v:167654.3-167666.6"
- process $proc$libresoc.v:167654$9406
+ attribute \src "libresoc.v:165455.3-165467.6"
+ process $proc$libresoc.v:165455$9320
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9407 $1\muxid$1$next[1:0]$9408
- attribute \src "libresoc.v:167655.5-167655.29"
+ assign $0\muxid$1$next[1:0]$9321 $1\muxid$1$next[1:0]$9322
+ attribute \src "libresoc.v:165456.5-165456.29"
switch \initial
- attribute \src "libresoc.v:167655.9-167655.17"
+ attribute \src "libresoc.v:165456.9-165456.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9408 \muxid$62
+ assign $1\muxid$1$next[1:0]$9322 \muxid$62
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9408 \muxid$62
+ assign $1\muxid$1$next[1:0]$9322 \muxid$62
case
- assign $1\muxid$1$next[1:0]$9408 \muxid$1
+ assign $1\muxid$1$next[1:0]$9322 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9407
+ update \muxid$1$next $0\muxid$1$next[1:0]$9321
end
- attribute \src "libresoc.v:167667.3-167708.6"
- process $proc$libresoc.v:167667$9409
+ attribute \src "libresoc.v:165468.3-165509.6"
+ process $proc$libresoc.v:165468$9323
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_op__data_len$18$next[3:0]$9410 $1\alu_op__data_len$18$next[3:0]$9428
- assign $0\alu_op__fn_unit$3$next[12:0]$9411 $1\alu_op__fn_unit$3$next[12:0]$9429
+ assign $0\alu_op__data_len$18$next[3:0]$9324 $1\alu_op__data_len$18$next[3:0]$9342
+ assign $0\alu_op__fn_unit$3$next[12:0]$9325 $1\alu_op__fn_unit$3$next[12:0]$9343
assign { } { }
assign { } { }
- assign $0\alu_op__input_carry$14$next[1:0]$9414 $1\alu_op__input_carry$14$next[1:0]$9432
- assign $0\alu_op__insn$19$next[31:0]$9415 $1\alu_op__insn$19$next[31:0]$9433
- assign $0\alu_op__insn_type$2$next[6:0]$9416 $1\alu_op__insn_type$2$next[6:0]$9434
- assign $0\alu_op__invert_in$10$next[0:0]$9417 $1\alu_op__invert_in$10$next[0:0]$9435
- assign $0\alu_op__invert_out$12$next[0:0]$9418 $1\alu_op__invert_out$12$next[0:0]$9436
- assign $0\alu_op__is_32bit$16$next[0:0]$9419 $1\alu_op__is_32bit$16$next[0:0]$9437
- assign $0\alu_op__is_signed$17$next[0:0]$9420 $1\alu_op__is_signed$17$next[0:0]$9438
+ assign $0\alu_op__input_carry$14$next[1:0]$9328 $1\alu_op__input_carry$14$next[1:0]$9346
+ assign $0\alu_op__insn$19$next[31:0]$9329 $1\alu_op__insn$19$next[31:0]$9347
+ assign $0\alu_op__insn_type$2$next[6:0]$9330 $1\alu_op__insn_type$2$next[6:0]$9348
+ assign $0\alu_op__invert_in$10$next[0:0]$9331 $1\alu_op__invert_in$10$next[0:0]$9349
+ assign $0\alu_op__invert_out$12$next[0:0]$9332 $1\alu_op__invert_out$12$next[0:0]$9350
+ assign $0\alu_op__is_32bit$16$next[0:0]$9333 $1\alu_op__is_32bit$16$next[0:0]$9351
+ assign $0\alu_op__is_signed$17$next[0:0]$9334 $1\alu_op__is_signed$17$next[0:0]$9352
assign { } { }
assign { } { }
- assign $0\alu_op__output_carry$15$next[0:0]$9423 $1\alu_op__output_carry$15$next[0:0]$9441
+ assign $0\alu_op__output_carry$15$next[0:0]$9337 $1\alu_op__output_carry$15$next[0:0]$9355
assign { } { }
assign { } { }
- assign $0\alu_op__write_cr0$13$next[0:0]$9426 $1\alu_op__write_cr0$13$next[0:0]$9444
- assign $0\alu_op__zero_a$11$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9445
- assign $0\alu_op__imm_data__data$4$next[63:0]$9412 $2\alu_op__imm_data__data$4$next[63:0]$9446
- assign $0\alu_op__imm_data__ok$5$next[0:0]$9413 $2\alu_op__imm_data__ok$5$next[0:0]$9447
- assign $0\alu_op__oe__oe$8$next[0:0]$9421 $2\alu_op__oe__oe$8$next[0:0]$9448
- assign $0\alu_op__oe__ok$9$next[0:0]$9422 $2\alu_op__oe__ok$9$next[0:0]$9449
- assign $0\alu_op__rc__ok$7$next[0:0]$9424 $2\alu_op__rc__ok$7$next[0:0]$9450
- assign $0\alu_op__rc__rc$6$next[0:0]$9425 $2\alu_op__rc__rc$6$next[0:0]$9451
- attribute \src "libresoc.v:167668.5-167668.29"
+ assign $0\alu_op__write_cr0$13$next[0:0]$9340 $1\alu_op__write_cr0$13$next[0:0]$9358
+ assign $0\alu_op__zero_a$11$next[0:0]$9341 $1\alu_op__zero_a$11$next[0:0]$9359
+ assign $0\alu_op__imm_data__data$4$next[63:0]$9326 $2\alu_op__imm_data__data$4$next[63:0]$9360
+ assign $0\alu_op__imm_data__ok$5$next[0:0]$9327 $2\alu_op__imm_data__ok$5$next[0:0]$9361
+ assign $0\alu_op__oe__oe$8$next[0:0]$9335 $2\alu_op__oe__oe$8$next[0:0]$9362
+ assign $0\alu_op__oe__ok$9$next[0:0]$9336 $2\alu_op__oe__ok$9$next[0:0]$9363
+ assign $0\alu_op__rc__ok$7$next[0:0]$9338 $2\alu_op__rc__ok$7$next[0:0]$9364
+ assign $0\alu_op__rc__rc$6$next[0:0]$9339 $2\alu_op__rc__rc$6$next[0:0]$9365
+ attribute \src "libresoc.v:165469.5-165469.29"
switch \initial
- attribute \src "libresoc.v:167668.9-167668.17"
+ attribute \src "libresoc.v:165469.9-165469.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$19$next[31:0]$9433 $1\alu_op__data_len$18$next[3:0]$9428 $1\alu_op__is_signed$17$next[0:0]$9438 $1\alu_op__is_32bit$16$next[0:0]$9437 $1\alu_op__output_carry$15$next[0:0]$9441 $1\alu_op__input_carry$14$next[1:0]$9432 $1\alu_op__write_cr0$13$next[0:0]$9444 $1\alu_op__invert_out$12$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9445 $1\alu_op__invert_in$10$next[0:0]$9435 $1\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__rc__ok$7$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9443 $1\alu_op__imm_data__ok$5$next[0:0]$9431 $1\alu_op__imm_data__data$4$next[63:0]$9430 $1\alu_op__fn_unit$3$next[12:0]$9429 $1\alu_op__insn_type$2$next[6:0]$9434 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
+ assign { $1\alu_op__insn$19$next[31:0]$9347 $1\alu_op__data_len$18$next[3:0]$9342 $1\alu_op__is_signed$17$next[0:0]$9352 $1\alu_op__is_32bit$16$next[0:0]$9351 $1\alu_op__output_carry$15$next[0:0]$9355 $1\alu_op__input_carry$14$next[1:0]$9346 $1\alu_op__write_cr0$13$next[0:0]$9358 $1\alu_op__invert_out$12$next[0:0]$9350 $1\alu_op__zero_a$11$next[0:0]$9359 $1\alu_op__invert_in$10$next[0:0]$9349 $1\alu_op__oe__ok$9$next[0:0]$9354 $1\alu_op__oe__oe$8$next[0:0]$9353 $1\alu_op__rc__ok$7$next[0:0]$9356 $1\alu_op__rc__rc$6$next[0:0]$9357 $1\alu_op__imm_data__ok$5$next[0:0]$9345 $1\alu_op__imm_data__data$4$next[63:0]$9344 $1\alu_op__fn_unit$3$next[12:0]$9343 $1\alu_op__insn_type$2$next[6:0]$9348 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_op__insn$19$next[31:0]$9433 $1\alu_op__data_len$18$next[3:0]$9428 $1\alu_op__is_signed$17$next[0:0]$9438 $1\alu_op__is_32bit$16$next[0:0]$9437 $1\alu_op__output_carry$15$next[0:0]$9441 $1\alu_op__input_carry$14$next[1:0]$9432 $1\alu_op__write_cr0$13$next[0:0]$9444 $1\alu_op__invert_out$12$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9445 $1\alu_op__invert_in$10$next[0:0]$9435 $1\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__rc__ok$7$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9443 $1\alu_op__imm_data__ok$5$next[0:0]$9431 $1\alu_op__imm_data__data$4$next[63:0]$9430 $1\alu_op__fn_unit$3$next[12:0]$9429 $1\alu_op__insn_type$2$next[6:0]$9434 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
+ assign { $1\alu_op__insn$19$next[31:0]$9347 $1\alu_op__data_len$18$next[3:0]$9342 $1\alu_op__is_signed$17$next[0:0]$9352 $1\alu_op__is_32bit$16$next[0:0]$9351 $1\alu_op__output_carry$15$next[0:0]$9355 $1\alu_op__input_carry$14$next[1:0]$9346 $1\alu_op__write_cr0$13$next[0:0]$9358 $1\alu_op__invert_out$12$next[0:0]$9350 $1\alu_op__zero_a$11$next[0:0]$9359 $1\alu_op__invert_in$10$next[0:0]$9349 $1\alu_op__oe__ok$9$next[0:0]$9354 $1\alu_op__oe__oe$8$next[0:0]$9353 $1\alu_op__rc__ok$7$next[0:0]$9356 $1\alu_op__rc__rc$6$next[0:0]$9357 $1\alu_op__imm_data__ok$5$next[0:0]$9345 $1\alu_op__imm_data__data$4$next[63:0]$9344 $1\alu_op__fn_unit$3$next[12:0]$9343 $1\alu_op__insn_type$2$next[6:0]$9348 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 }
case
- assign $1\alu_op__data_len$18$next[3:0]$9428 \alu_op__data_len$18
- assign $1\alu_op__fn_unit$3$next[12:0]$9429 \alu_op__fn_unit$3
- assign $1\alu_op__imm_data__data$4$next[63:0]$9430 \alu_op__imm_data__data$4
- assign $1\alu_op__imm_data__ok$5$next[0:0]$9431 \alu_op__imm_data__ok$5
- assign $1\alu_op__input_carry$14$next[1:0]$9432 \alu_op__input_carry$14
- assign $1\alu_op__insn$19$next[31:0]$9433 \alu_op__insn$19
- assign $1\alu_op__insn_type$2$next[6:0]$9434 \alu_op__insn_type$2
- assign $1\alu_op__invert_in$10$next[0:0]$9435 \alu_op__invert_in$10
- assign $1\alu_op__invert_out$12$next[0:0]$9436 \alu_op__invert_out$12
- assign $1\alu_op__is_32bit$16$next[0:0]$9437 \alu_op__is_32bit$16
- assign $1\alu_op__is_signed$17$next[0:0]$9438 \alu_op__is_signed$17
- assign $1\alu_op__oe__oe$8$next[0:0]$9439 \alu_op__oe__oe$8
- assign $1\alu_op__oe__ok$9$next[0:0]$9440 \alu_op__oe__ok$9
- assign $1\alu_op__output_carry$15$next[0:0]$9441 \alu_op__output_carry$15
- assign $1\alu_op__rc__ok$7$next[0:0]$9442 \alu_op__rc__ok$7
- assign $1\alu_op__rc__rc$6$next[0:0]$9443 \alu_op__rc__rc$6
- assign $1\alu_op__write_cr0$13$next[0:0]$9444 \alu_op__write_cr0$13
- assign $1\alu_op__zero_a$11$next[0:0]$9445 \alu_op__zero_a$11
+ assign $1\alu_op__data_len$18$next[3:0]$9342 \alu_op__data_len$18
+ assign $1\alu_op__fn_unit$3$next[12:0]$9343 \alu_op__fn_unit$3
+ assign $1\alu_op__imm_data__data$4$next[63:0]$9344 \alu_op__imm_data__data$4
+ assign $1\alu_op__imm_data__ok$5$next[0:0]$9345 \alu_op__imm_data__ok$5
+ assign $1\alu_op__input_carry$14$next[1:0]$9346 \alu_op__input_carry$14
+ assign $1\alu_op__insn$19$next[31:0]$9347 \alu_op__insn$19
+ assign $1\alu_op__insn_type$2$next[6:0]$9348 \alu_op__insn_type$2
+ assign $1\alu_op__invert_in$10$next[0:0]$9349 \alu_op__invert_in$10
+ assign $1\alu_op__invert_out$12$next[0:0]$9350 \alu_op__invert_out$12
+ assign $1\alu_op__is_32bit$16$next[0:0]$9351 \alu_op__is_32bit$16
+ assign $1\alu_op__is_signed$17$next[0:0]$9352 \alu_op__is_signed$17
+ assign $1\alu_op__oe__oe$8$next[0:0]$9353 \alu_op__oe__oe$8
+ assign $1\alu_op__oe__ok$9$next[0:0]$9354 \alu_op__oe__ok$9
+ assign $1\alu_op__output_carry$15$next[0:0]$9355 \alu_op__output_carry$15
+ assign $1\alu_op__rc__ok$7$next[0:0]$9356 \alu_op__rc__ok$7
+ assign $1\alu_op__rc__rc$6$next[0:0]$9357 \alu_op__rc__rc$6
+ assign $1\alu_op__write_cr0$13$next[0:0]$9358 \alu_op__write_cr0$13
+ assign $1\alu_op__zero_a$11$next[0:0]$9359 \alu_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_op__imm_data__data$4$next[63:0]$9446 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_op__imm_data__ok$5$next[0:0]$9447 1'0
- assign $2\alu_op__rc__rc$6$next[0:0]$9451 1'0
- assign $2\alu_op__rc__ok$7$next[0:0]$9450 1'0
- assign $2\alu_op__oe__oe$8$next[0:0]$9448 1'0
- assign $2\alu_op__oe__ok$9$next[0:0]$9449 1'0
+ assign $2\alu_op__imm_data__data$4$next[63:0]$9360 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_op__imm_data__ok$5$next[0:0]$9361 1'0
+ assign $2\alu_op__rc__rc$6$next[0:0]$9365 1'0
+ assign $2\alu_op__rc__ok$7$next[0:0]$9364 1'0
+ assign $2\alu_op__oe__oe$8$next[0:0]$9362 1'0
+ assign $2\alu_op__oe__ok$9$next[0:0]$9363 1'0
case
- assign $2\alu_op__imm_data__data$4$next[63:0]$9446 $1\alu_op__imm_data__data$4$next[63:0]$9430
- assign $2\alu_op__imm_data__ok$5$next[0:0]$9447 $1\alu_op__imm_data__ok$5$next[0:0]$9431
- assign $2\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__oe__oe$8$next[0:0]$9439
- assign $2\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__ok$9$next[0:0]$9440
- assign $2\alu_op__rc__ok$7$next[0:0]$9450 $1\alu_op__rc__ok$7$next[0:0]$9442
- assign $2\alu_op__rc__rc$6$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9443
+ assign $2\alu_op__imm_data__data$4$next[63:0]$9360 $1\alu_op__imm_data__data$4$next[63:0]$9344
+ assign $2\alu_op__imm_data__ok$5$next[0:0]$9361 $1\alu_op__imm_data__ok$5$next[0:0]$9345
+ assign $2\alu_op__oe__oe$8$next[0:0]$9362 $1\alu_op__oe__oe$8$next[0:0]$9353
+ assign $2\alu_op__oe__ok$9$next[0:0]$9363 $1\alu_op__oe__ok$9$next[0:0]$9354
+ assign $2\alu_op__rc__ok$7$next[0:0]$9364 $1\alu_op__rc__ok$7$next[0:0]$9356
+ assign $2\alu_op__rc__rc$6$next[0:0]$9365 $1\alu_op__rc__rc$6$next[0:0]$9357
end
sync always
- update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9410
- update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9411
- update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9412
- update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9413
- update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9414
- update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9415
- update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9416
- update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9417
- update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9418
- update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9419
- update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9420
- update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9421
- update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9422
- update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9423
- update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9424
- update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9425
- update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9426
- update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9427
+ update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9324
+ update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9325
+ update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9326
+ update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9327
+ update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9328
+ update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9329
+ update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9330
+ update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9331
+ update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9332
+ update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9333
+ update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9334
+ update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9335
+ update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9336
+ update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9337
+ update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9338
+ update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9339
+ update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9340
+ update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9341
end
- attribute \src "libresoc.v:167709.3-167727.6"
- process $proc$libresoc.v:167709$9452
+ attribute \src "libresoc.v:165510.3-165528.6"
+ process $proc$libresoc.v:165510$9366
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$20$next[63:0]$9453 $1\o$20$next[63:0]$9455
+ assign $0\o$20$next[63:0]$9367 $1\o$20$next[63:0]$9369
assign { } { }
- assign $0\o_ok$21$next[0:0]$9454 $2\o_ok$21$next[0:0]$9457
- attribute \src "libresoc.v:167710.5-167710.29"
+ assign $0\o_ok$21$next[0:0]$9368 $2\o_ok$21$next[0:0]$9371
+ attribute \src "libresoc.v:165511.5-165511.29"
switch \initial
- attribute \src "libresoc.v:167710.9-167710.17"
+ attribute \src "libresoc.v:165511.9-165511.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$9456 $1\o$20$next[63:0]$9455 } { \o_ok$82 \o$81 }
+ assign { $1\o_ok$21$next[0:0]$9370 $1\o$20$next[63:0]$9369 } { \o_ok$82 \o$81 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$21$next[0:0]$9456 $1\o$20$next[63:0]$9455 } { \o_ok$82 \o$81 }
+ assign { $1\o_ok$21$next[0:0]$9370 $1\o$20$next[63:0]$9369 } { \o_ok$82 \o$81 }
case
- assign $1\o$20$next[63:0]$9455 \o$20
- assign $1\o_ok$21$next[0:0]$9456 \o_ok$21
+ assign $1\o$20$next[63:0]$9369 \o$20
+ assign $1\o_ok$21$next[0:0]$9370 \o_ok$21
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$21$next[0:0]$9457 1'0
+ assign $2\o_ok$21$next[0:0]$9371 1'0
case
- assign $2\o_ok$21$next[0:0]$9457 $1\o_ok$21$next[0:0]$9456
+ assign $2\o_ok$21$next[0:0]$9371 $1\o_ok$21$next[0:0]$9370
end
sync always
- update \o$20$next $0\o$20$next[63:0]$9453
- update \o_ok$21$next $0\o_ok$21$next[0:0]$9454
+ update \o$20$next $0\o$20$next[63:0]$9367
+ update \o_ok$21$next $0\o_ok$21$next[0:0]$9368
end
- attribute \src "libresoc.v:167728.3-167746.6"
- process $proc$libresoc.v:167728$9458
+ attribute \src "libresoc.v:165529.3-165547.6"
+ process $proc$libresoc.v:165529$9372
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$22$next[3:0]$9459 $1\cr_a$22$next[3:0]$9461
+ assign $0\cr_a$22$next[3:0]$9373 $1\cr_a$22$next[3:0]$9375
assign { } { }
- assign $0\cr_a_ok$23$next[0:0]$9460 $2\cr_a_ok$23$next[0:0]$9463
- attribute \src "libresoc.v:167729.5-167729.29"
+ assign $0\cr_a_ok$23$next[0:0]$9374 $2\cr_a_ok$23$next[0:0]$9377
+ attribute \src "libresoc.v:165530.5-165530.29"
switch \initial
- attribute \src "libresoc.v:167729.9-167729.17"
+ attribute \src "libresoc.v:165530.9-165530.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$9462 $1\cr_a$22$next[3:0]$9461 } { \cr_a_ok$84 \cr_a$83 }
+ assign { $1\cr_a_ok$23$next[0:0]$9376 $1\cr_a$22$next[3:0]$9375 } { \cr_a_ok$84 \cr_a$83 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$23$next[0:0]$9462 $1\cr_a$22$next[3:0]$9461 } { \cr_a_ok$84 \cr_a$83 }
+ assign { $1\cr_a_ok$23$next[0:0]$9376 $1\cr_a$22$next[3:0]$9375 } { \cr_a_ok$84 \cr_a$83 }
case
- assign $1\cr_a$22$next[3:0]$9461 \cr_a$22
- assign $1\cr_a_ok$23$next[0:0]$9462 \cr_a_ok$23
+ assign $1\cr_a$22$next[3:0]$9375 \cr_a$22
+ assign $1\cr_a_ok$23$next[0:0]$9376 \cr_a_ok$23
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$23$next[0:0]$9463 1'0
+ assign $2\cr_a_ok$23$next[0:0]$9377 1'0
case
- assign $2\cr_a_ok$23$next[0:0]$9463 $1\cr_a_ok$23$next[0:0]$9462
+ assign $2\cr_a_ok$23$next[0:0]$9377 $1\cr_a_ok$23$next[0:0]$9376
end
sync always
- update \cr_a$22$next $0\cr_a$22$next[3:0]$9459
- update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9460
+ update \cr_a$22$next $0\cr_a$22$next[3:0]$9373
+ update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9374
end
- attribute \src "libresoc.v:167747.3-167765.6"
- process $proc$libresoc.v:167747$9464
+ attribute \src "libresoc.v:165548.3-165566.6"
+ process $proc$libresoc.v:165548$9378
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$24$next[1:0]$9465 $1\xer_ca$24$next[1:0]$9467
+ assign $0\xer_ca$24$next[1:0]$9379 $1\xer_ca$24$next[1:0]$9381
assign { } { }
- assign $0\xer_ca_ok$25$next[0:0]$9466 $2\xer_ca_ok$25$next[0:0]$9469
- attribute \src "libresoc.v:167748.5-167748.29"
+ assign $0\xer_ca_ok$25$next[0:0]$9380 $2\xer_ca_ok$25$next[0:0]$9383
+ attribute \src "libresoc.v:165549.5-165549.29"
switch \initial
- attribute \src "libresoc.v:167748.9-167748.17"
+ attribute \src "libresoc.v:165549.9-165549.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$25$next[0:0]$9468 $1\xer_ca$24$next[1:0]$9467 } { \xer_ca_ok$86 \xer_ca$85 }
+ assign { $1\xer_ca_ok$25$next[0:0]$9382 $1\xer_ca$24$next[1:0]$9381 } { \xer_ca_ok$86 \xer_ca$85 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$25$next[0:0]$9468 $1\xer_ca$24$next[1:0]$9467 } { \xer_ca_ok$86 \xer_ca$85 }
+ assign { $1\xer_ca_ok$25$next[0:0]$9382 $1\xer_ca$24$next[1:0]$9381 } { \xer_ca_ok$86 \xer_ca$85 }
case
- assign $1\xer_ca$24$next[1:0]$9467 \xer_ca$24
- assign $1\xer_ca_ok$25$next[0:0]$9468 \xer_ca_ok$25
+ assign $1\xer_ca$24$next[1:0]$9381 \xer_ca$24
+ assign $1\xer_ca_ok$25$next[0:0]$9382 \xer_ca_ok$25
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$25$next[0:0]$9469 1'0
+ assign $2\xer_ca_ok$25$next[0:0]$9383 1'0
case
- assign $2\xer_ca_ok$25$next[0:0]$9469 $1\xer_ca_ok$25$next[0:0]$9468
+ assign $2\xer_ca_ok$25$next[0:0]$9383 $1\xer_ca_ok$25$next[0:0]$9382
end
sync always
- update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9465
- update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9466
+ update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9379
+ update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9380
end
- attribute \src "libresoc.v:167766.3-167784.6"
- process $proc$libresoc.v:167766$9470
+ attribute \src "libresoc.v:165567.3-165585.6"
+ process $proc$libresoc.v:165567$9384
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$26$next[1:0]$9471 $1\xer_ov$26$next[1:0]$9473
+ assign $0\xer_ov$26$next[1:0]$9385 $1\xer_ov$26$next[1:0]$9387
assign { } { }
- assign $0\xer_ov_ok$27$next[0:0]$9472 $2\xer_ov_ok$27$next[0:0]$9475
- attribute \src "libresoc.v:167767.5-167767.29"
+ assign $0\xer_ov_ok$27$next[0:0]$9386 $2\xer_ov_ok$27$next[0:0]$9389
+ attribute \src "libresoc.v:165568.5-165568.29"
switch \initial
- attribute \src "libresoc.v:167767.9-167767.17"
+ attribute \src "libresoc.v:165568.9-165568.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$27$next[0:0]$9474 $1\xer_ov$26$next[1:0]$9473 } { \xer_ov_ok$88 \xer_ov$87 }
+ assign { $1\xer_ov_ok$27$next[0:0]$9388 $1\xer_ov$26$next[1:0]$9387 } { \xer_ov_ok$88 \xer_ov$87 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$27$next[0:0]$9474 $1\xer_ov$26$next[1:0]$9473 } { \xer_ov_ok$88 \xer_ov$87 }
+ assign { $1\xer_ov_ok$27$next[0:0]$9388 $1\xer_ov$26$next[1:0]$9387 } { \xer_ov_ok$88 \xer_ov$87 }
case
- assign $1\xer_ov$26$next[1:0]$9473 \xer_ov$26
- assign $1\xer_ov_ok$27$next[0:0]$9474 \xer_ov_ok$27
+ assign $1\xer_ov$26$next[1:0]$9387 \xer_ov$26
+ assign $1\xer_ov_ok$27$next[0:0]$9388 \xer_ov_ok$27
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$27$next[0:0]$9475 1'0
+ assign $2\xer_ov_ok$27$next[0:0]$9389 1'0
case
- assign $2\xer_ov_ok$27$next[0:0]$9475 $1\xer_ov_ok$27$next[0:0]$9474
+ assign $2\xer_ov_ok$27$next[0:0]$9389 $1\xer_ov_ok$27$next[0:0]$9388
end
sync always
- update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9471
- update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9472
+ update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9385
+ update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9386
end
- attribute \src "libresoc.v:167785.3-167803.6"
- process $proc$libresoc.v:167785$9476
+ attribute \src "libresoc.v:165586.3-165604.6"
+ process $proc$libresoc.v:165586$9390
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$28$next[0:0]$9477 $1\xer_so$28$next[0:0]$9479
+ assign $0\xer_so$28$next[0:0]$9391 $1\xer_so$28$next[0:0]$9393
assign { } { }
- assign $0\xer_so_ok$29$next[0:0]$9478 $2\xer_so_ok$29$next[0:0]$9481
- attribute \src "libresoc.v:167786.5-167786.29"
+ assign $0\xer_so_ok$29$next[0:0]$9392 $2\xer_so_ok$29$next[0:0]$9395
+ attribute \src "libresoc.v:165587.5-165587.29"
switch \initial
- attribute \src "libresoc.v:167786.9-167786.17"
+ attribute \src "libresoc.v:165587.9-165587.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$29$next[0:0]$9480 $1\xer_so$28$next[0:0]$9479 } { \xer_so_ok$90 \xer_so$89 }
+ assign { $1\xer_so_ok$29$next[0:0]$9394 $1\xer_so$28$next[0:0]$9393 } { \xer_so_ok$90 \xer_so$89 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$29$next[0:0]$9480 $1\xer_so$28$next[0:0]$9479 } { \xer_so_ok$90 \xer_so$89 }
+ assign { $1\xer_so_ok$29$next[0:0]$9394 $1\xer_so$28$next[0:0]$9393 } { \xer_so_ok$90 \xer_so$89 }
case
- assign $1\xer_so$28$next[0:0]$9479 \xer_so$28
- assign $1\xer_so_ok$29$next[0:0]$9480 \xer_so_ok$29
+ assign $1\xer_so$28$next[0:0]$9393 \xer_so$28
+ assign $1\xer_so_ok$29$next[0:0]$9394 \xer_so_ok$29
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$29$next[0:0]$9481 1'0
+ assign $2\xer_so_ok$29$next[0:0]$9395 1'0
case
- assign $2\xer_so_ok$29$next[0:0]$9481 $1\xer_so_ok$29$next[0:0]$9480
+ assign $2\xer_so_ok$29$next[0:0]$9395 $1\xer_so_ok$29$next[0:0]$9394
end
sync always
- update \xer_so$28$next $0\xer_so$28$next[0:0]$9477
- update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9478
+ update \xer_so$28$next $0\xer_so$28$next[0:0]$9391
+ update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9392
end
- connect \$60 $and$libresoc.v:167511$9342_Y
+ connect \$60 $and$libresoc.v:165312$9256_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 }
connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type }
connect \output_muxid \muxid
end
-attribute \src "libresoc.v:167827.1-168886.10"
+attribute \src "libresoc.v:165628.1-166687.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2"
attribute \generator "nMigen"
module \pipe2$115
- attribute \src "libresoc.v:168832.3-168850.6"
- wire width 4 $0\cr_a$21$next[3:0]$9647
- attribute \src "libresoc.v:168638.3-168639.33"
- wire width 4 $0\cr_a$21[3:0]$9548
- attribute \src "libresoc.v:167839.13-167839.29"
- wire width 4 $0\cr_a$21[3:0]$9660
- attribute \src "libresoc.v:168832.3-168850.6"
- wire $0\cr_a_ok$22$next[0:0]$9648
- attribute \src "libresoc.v:168640.3-168641.39"
- wire $0\cr_a_ok$22[0:0]$9550
- attribute \src "libresoc.v:167848.7-167848.26"
- wire $0\cr_a_ok$22[0:0]$9662
- attribute \src "libresoc.v:167828.7-167828.20"
+ attribute \src "libresoc.v:166633.3-166651.6"
+ wire width 4 $0\cr_a$21$next[3:0]$9561
+ attribute \src "libresoc.v:166439.3-166440.33"
+ wire width 4 $0\cr_a$21[3:0]$9462
+ attribute \src "libresoc.v:165640.13-165640.29"
+ wire width 4 $0\cr_a$21[3:0]$9574
+ attribute \src "libresoc.v:166633.3-166651.6"
+ wire $0\cr_a_ok$22$next[0:0]$9562
+ attribute \src "libresoc.v:166441.3-166442.39"
+ wire $0\cr_a_ok$22[0:0]$9464
+ attribute \src "libresoc.v:165649.7-165649.26"
+ wire $0\cr_a_ok$22[0:0]$9576
+ attribute \src "libresoc.v:165629.7-165629.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:168759.3-168771.6"
- wire width 2 $0\muxid$1$next[1:0]$9597
- attribute \src "libresoc.v:168680.3-168681.33"
- wire width 2 $0\muxid$1[1:0]$9590
- attribute \src "libresoc.v:167859.13-167859.29"
- wire width 2 $0\muxid$1[1:0]$9664
- attribute \src "libresoc.v:168813.3-168831.6"
- wire width 64 $0\o$19$next[63:0]$9641
- attribute \src "libresoc.v:168642.3-168643.27"
- wire width 64 $0\o$19[63:0]$9552
- attribute \src "libresoc.v:167874.14-167874.43"
- wire width 64 $0\o$19[63:0]$9666
- attribute \src "libresoc.v:168813.3-168831.6"
- wire $0\o_ok$20$next[0:0]$9642
- attribute \src "libresoc.v:168644.3-168645.33"
- wire $0\o_ok$20[0:0]$9554
- attribute \src "libresoc.v:167883.7-167883.23"
- wire $0\o_ok$20[0:0]$9668
- attribute \src "libresoc.v:168741.3-168758.6"
- wire $0\r_busy$next[0:0]$9593
- attribute \src "libresoc.v:168682.3-168683.29"
+ attribute \src "libresoc.v:166560.3-166572.6"
+ wire width 2 $0\muxid$1$next[1:0]$9511
+ attribute \src "libresoc.v:166481.3-166482.33"
+ wire width 2 $0\muxid$1[1:0]$9504
+ attribute \src "libresoc.v:165660.13-165660.29"
+ wire width 2 $0\muxid$1[1:0]$9578
+ attribute \src "libresoc.v:166614.3-166632.6"
+ wire width 64 $0\o$19$next[63:0]$9555
+ attribute \src "libresoc.v:166443.3-166444.27"
+ wire width 64 $0\o$19[63:0]$9466
+ attribute \src "libresoc.v:165675.14-165675.43"
+ wire width 64 $0\o$19[63:0]$9580
+ attribute \src "libresoc.v:166614.3-166632.6"
+ wire $0\o_ok$20$next[0:0]$9556
+ attribute \src "libresoc.v:166445.3-166446.33"
+ wire $0\o_ok$20[0:0]$9468
+ attribute \src "libresoc.v:165684.7-165684.23"
+ wire $0\o_ok$20[0:0]$9582
+ attribute \src "libresoc.v:166542.3-166559.6"
+ wire $0\r_busy$next[0:0]$9507
+ attribute \src "libresoc.v:166483.3-166484.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 13 $0\sr_op__fn_unit$3$next[12:0]$9600
- attribute \src "libresoc.v:168648.3-168649.51"
- wire width 13 $0\sr_op__fn_unit$3[12:0]$9558
- attribute \src "libresoc.v:168210.14-168210.43"
- wire width 13 $0\sr_op__fn_unit$3[12:0]$9671
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9601
- attribute \src "libresoc.v:168650.3-168651.65"
- wire width 64 $0\sr_op__imm_data__data$4[63:0]$9560
- attribute \src "libresoc.v:168233.14-168233.62"
- wire width 64 $0\sr_op__imm_data__data$4[63:0]$9673
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__imm_data__ok$5$next[0:0]$9602
- attribute \src "libresoc.v:168652.3-168653.61"
- wire $0\sr_op__imm_data__ok$5[0:0]$9562
- attribute \src "libresoc.v:168242.7-168242.37"
- wire $0\sr_op__imm_data__ok$5[0:0]$9675
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 2 $0\sr_op__input_carry$12$next[1:0]$9603
- attribute \src "libresoc.v:168666.3-168667.61"
- wire width 2 $0\sr_op__input_carry$12[1:0]$9576
- attribute \src "libresoc.v:168259.13-168259.43"
- wire width 2 $0\sr_op__input_carry$12[1:0]$9677
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__input_cr$14$next[0:0]$9604
- attribute \src "libresoc.v:168670.3-168671.55"
- wire $0\sr_op__input_cr$14[0:0]$9580
- attribute \src "libresoc.v:168272.7-168272.34"
- wire $0\sr_op__input_cr$14[0:0]$9679
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 32 $0\sr_op__insn$18$next[31:0]$9605
- attribute \src "libresoc.v:168678.3-168679.47"
- wire width 32 $0\sr_op__insn$18[31:0]$9588
- attribute \src "libresoc.v:168281.14-168281.38"
- wire width 32 $0\sr_op__insn$18[31:0]$9681
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 7 $0\sr_op__insn_type$2$next[6:0]$9606
- attribute \src "libresoc.v:168646.3-168647.55"
- wire width 7 $0\sr_op__insn_type$2[6:0]$9556
- attribute \src "libresoc.v:168438.13-168438.41"
- wire width 7 $0\sr_op__insn_type$2[6:0]$9683
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__invert_in$11$next[0:0]$9607
- attribute \src "libresoc.v:168664.3-168665.57"
- wire $0\sr_op__invert_in$11[0:0]$9574
- attribute \src "libresoc.v:168521.7-168521.35"
- wire $0\sr_op__invert_in$11[0:0]$9685
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__is_32bit$16$next[0:0]$9608
- attribute \src "libresoc.v:168674.3-168675.55"
- wire $0\sr_op__is_32bit$16[0:0]$9584
- attribute \src "libresoc.v:168530.7-168530.34"
- wire $0\sr_op__is_32bit$16[0:0]$9687
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__is_signed$17$next[0:0]$9609
- attribute \src "libresoc.v:168676.3-168677.57"
- wire $0\sr_op__is_signed$17[0:0]$9586
- attribute \src "libresoc.v:168539.7-168539.35"
- wire $0\sr_op__is_signed$17[0:0]$9689
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__oe__oe$8$next[0:0]$9610
- attribute \src "libresoc.v:168658.3-168659.49"
- wire $0\sr_op__oe__oe$8[0:0]$9568
- attribute \src "libresoc.v:168550.7-168550.31"
- wire $0\sr_op__oe__oe$8[0:0]$9691
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__oe__ok$9$next[0:0]$9611
- attribute \src "libresoc.v:168660.3-168661.49"
- wire $0\sr_op__oe__ok$9[0:0]$9570
- attribute \src "libresoc.v:168559.7-168559.31"
- wire $0\sr_op__oe__ok$9[0:0]$9693
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__output_carry$13$next[0:0]$9612
- attribute \src "libresoc.v:168668.3-168669.63"
- wire $0\sr_op__output_carry$13[0:0]$9578
- attribute \src "libresoc.v:168566.7-168566.38"
- wire $0\sr_op__output_carry$13[0:0]$9695
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__output_cr$15$next[0:0]$9613
- attribute \src "libresoc.v:168672.3-168673.57"
- wire $0\sr_op__output_cr$15[0:0]$9582
- attribute \src "libresoc.v:168575.7-168575.35"
- wire $0\sr_op__output_cr$15[0:0]$9697
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__rc__ok$7$next[0:0]$9614
- attribute \src "libresoc.v:168656.3-168657.49"
- wire $0\sr_op__rc__ok$7[0:0]$9566
- attribute \src "libresoc.v:168586.7-168586.31"
- wire $0\sr_op__rc__ok$7[0:0]$9699
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__rc__rc$6$next[0:0]$9615
- attribute \src "libresoc.v:168654.3-168655.49"
- wire $0\sr_op__rc__rc$6[0:0]$9564
- attribute \src "libresoc.v:168595.7-168595.31"
- wire $0\sr_op__rc__rc$6[0:0]$9701
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $0\sr_op__write_cr0$10$next[0:0]$9616
- attribute \src "libresoc.v:168662.3-168663.57"
- wire $0\sr_op__write_cr0$10[0:0]$9572
- attribute \src "libresoc.v:168602.7-168602.35"
- wire $0\sr_op__write_cr0$10[0:0]$9703
- attribute \src "libresoc.v:168851.3-168869.6"
- wire width 2 $0\xer_ca$23$next[1:0]$9653
- attribute \src "libresoc.v:168634.3-168635.37"
- wire width 2 $0\xer_ca$23[1:0]$9544
- attribute \src "libresoc.v:168611.13-168611.31"
- wire width 2 $0\xer_ca$23[1:0]$9705
- attribute \src "libresoc.v:168851.3-168869.6"
- wire $0\xer_ca_ok$24$next[0:0]$9654
- attribute \src "libresoc.v:168636.3-168637.43"
- wire $0\xer_ca_ok$24[0:0]$9546
- attribute \src "libresoc.v:168620.7-168620.28"
- wire $0\xer_ca_ok$24[0:0]$9707
- attribute \src "libresoc.v:168832.3-168850.6"
- wire width 4 $1\cr_a$21$next[3:0]$9649
- attribute \src "libresoc.v:168832.3-168850.6"
- wire $1\cr_a_ok$22$next[0:0]$9650
- attribute \src "libresoc.v:168759.3-168771.6"
- wire width 2 $1\muxid$1$next[1:0]$9598
- attribute \src "libresoc.v:168813.3-168831.6"
- wire width 64 $1\o$19$next[63:0]$9643
- attribute \src "libresoc.v:168813.3-168831.6"
- wire $1\o_ok$20$next[0:0]$9644
- attribute \src "libresoc.v:168741.3-168758.6"
- wire $1\r_busy$next[0:0]$9594
- attribute \src "libresoc.v:168175.7-168175.20"
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 13 $0\sr_op__fn_unit$3$next[12:0]$9514
+ attribute \src "libresoc.v:166449.3-166450.51"
+ wire width 13 $0\sr_op__fn_unit$3[12:0]$9472
+ attribute \src "libresoc.v:166011.14-166011.43"
+ wire width 13 $0\sr_op__fn_unit$3[12:0]$9585
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9515
+ attribute \src "libresoc.v:166451.3-166452.65"
+ wire width 64 $0\sr_op__imm_data__data$4[63:0]$9474
+ attribute \src "libresoc.v:166034.14-166034.62"
+ wire width 64 $0\sr_op__imm_data__data$4[63:0]$9587
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__imm_data__ok$5$next[0:0]$9516
+ attribute \src "libresoc.v:166453.3-166454.61"
+ wire $0\sr_op__imm_data__ok$5[0:0]$9476
+ attribute \src "libresoc.v:166043.7-166043.37"
+ wire $0\sr_op__imm_data__ok$5[0:0]$9589
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 2 $0\sr_op__input_carry$12$next[1:0]$9517
+ attribute \src "libresoc.v:166467.3-166468.61"
+ wire width 2 $0\sr_op__input_carry$12[1:0]$9490
+ attribute \src "libresoc.v:166060.13-166060.43"
+ wire width 2 $0\sr_op__input_carry$12[1:0]$9591
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__input_cr$14$next[0:0]$9518
+ attribute \src "libresoc.v:166471.3-166472.55"
+ wire $0\sr_op__input_cr$14[0:0]$9494
+ attribute \src "libresoc.v:166073.7-166073.34"
+ wire $0\sr_op__input_cr$14[0:0]$9593
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 32 $0\sr_op__insn$18$next[31:0]$9519
+ attribute \src "libresoc.v:166479.3-166480.47"
+ wire width 32 $0\sr_op__insn$18[31:0]$9502
+ attribute \src "libresoc.v:166082.14-166082.38"
+ wire width 32 $0\sr_op__insn$18[31:0]$9595
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 7 $0\sr_op__insn_type$2$next[6:0]$9520
+ attribute \src "libresoc.v:166447.3-166448.55"
+ wire width 7 $0\sr_op__insn_type$2[6:0]$9470
+ attribute \src "libresoc.v:166239.13-166239.41"
+ wire width 7 $0\sr_op__insn_type$2[6:0]$9597
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__invert_in$11$next[0:0]$9521
+ attribute \src "libresoc.v:166465.3-166466.57"
+ wire $0\sr_op__invert_in$11[0:0]$9488
+ attribute \src "libresoc.v:166322.7-166322.35"
+ wire $0\sr_op__invert_in$11[0:0]$9599
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__is_32bit$16$next[0:0]$9522
+ attribute \src "libresoc.v:166475.3-166476.55"
+ wire $0\sr_op__is_32bit$16[0:0]$9498
+ attribute \src "libresoc.v:166331.7-166331.34"
+ wire $0\sr_op__is_32bit$16[0:0]$9601
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__is_signed$17$next[0:0]$9523
+ attribute \src "libresoc.v:166477.3-166478.57"
+ wire $0\sr_op__is_signed$17[0:0]$9500
+ attribute \src "libresoc.v:166340.7-166340.35"
+ wire $0\sr_op__is_signed$17[0:0]$9603
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__oe__oe$8$next[0:0]$9524
+ attribute \src "libresoc.v:166459.3-166460.49"
+ wire $0\sr_op__oe__oe$8[0:0]$9482
+ attribute \src "libresoc.v:166351.7-166351.31"
+ wire $0\sr_op__oe__oe$8[0:0]$9605
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__oe__ok$9$next[0:0]$9525
+ attribute \src "libresoc.v:166461.3-166462.49"
+ wire $0\sr_op__oe__ok$9[0:0]$9484
+ attribute \src "libresoc.v:166360.7-166360.31"
+ wire $0\sr_op__oe__ok$9[0:0]$9607
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__output_carry$13$next[0:0]$9526
+ attribute \src "libresoc.v:166469.3-166470.63"
+ wire $0\sr_op__output_carry$13[0:0]$9492
+ attribute \src "libresoc.v:166367.7-166367.38"
+ wire $0\sr_op__output_carry$13[0:0]$9609
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__output_cr$15$next[0:0]$9527
+ attribute \src "libresoc.v:166473.3-166474.57"
+ wire $0\sr_op__output_cr$15[0:0]$9496
+ attribute \src "libresoc.v:166376.7-166376.35"
+ wire $0\sr_op__output_cr$15[0:0]$9611
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__rc__ok$7$next[0:0]$9528
+ attribute \src "libresoc.v:166457.3-166458.49"
+ wire $0\sr_op__rc__ok$7[0:0]$9480
+ attribute \src "libresoc.v:166387.7-166387.31"
+ wire $0\sr_op__rc__ok$7[0:0]$9613
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__rc__rc$6$next[0:0]$9529
+ attribute \src "libresoc.v:166455.3-166456.49"
+ wire $0\sr_op__rc__rc$6[0:0]$9478
+ attribute \src "libresoc.v:166396.7-166396.31"
+ wire $0\sr_op__rc__rc$6[0:0]$9615
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $0\sr_op__write_cr0$10$next[0:0]$9530
+ attribute \src "libresoc.v:166463.3-166464.57"
+ wire $0\sr_op__write_cr0$10[0:0]$9486
+ attribute \src "libresoc.v:166403.7-166403.35"
+ wire $0\sr_op__write_cr0$10[0:0]$9617
+ attribute \src "libresoc.v:166652.3-166670.6"
+ wire width 2 $0\xer_ca$23$next[1:0]$9567
+ attribute \src "libresoc.v:166435.3-166436.37"
+ wire width 2 $0\xer_ca$23[1:0]$9458
+ attribute \src "libresoc.v:166412.13-166412.31"
+ wire width 2 $0\xer_ca$23[1:0]$9619
+ attribute \src "libresoc.v:166652.3-166670.6"
+ wire $0\xer_ca_ok$24$next[0:0]$9568
+ attribute \src "libresoc.v:166437.3-166438.43"
+ wire $0\xer_ca_ok$24[0:0]$9460
+ attribute \src "libresoc.v:166421.7-166421.28"
+ wire $0\xer_ca_ok$24[0:0]$9621
+ attribute \src "libresoc.v:166633.3-166651.6"
+ wire width 4 $1\cr_a$21$next[3:0]$9563
+ attribute \src "libresoc.v:166633.3-166651.6"
+ wire $1\cr_a_ok$22$next[0:0]$9564
+ attribute \src "libresoc.v:166560.3-166572.6"
+ wire width 2 $1\muxid$1$next[1:0]$9512
+ attribute \src "libresoc.v:166614.3-166632.6"
+ wire width 64 $1\o$19$next[63:0]$9557
+ attribute \src "libresoc.v:166614.3-166632.6"
+ wire $1\o_ok$20$next[0:0]$9558
+ attribute \src "libresoc.v:166542.3-166559.6"
+ wire $1\r_busy$next[0:0]$9508
+ attribute \src "libresoc.v:165976.7-165976.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9617
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9618
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__imm_data__ok$5$next[0:0]$9619
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 2 $1\sr_op__input_carry$12$next[1:0]$9620
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__input_cr$14$next[0:0]$9621
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 32 $1\sr_op__insn$18$next[31:0]$9622
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 7 $1\sr_op__insn_type$2$next[6:0]$9623
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__invert_in$11$next[0:0]$9624
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__is_32bit$16$next[0:0]$9625
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__is_signed$17$next[0:0]$9626
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__oe__oe$8$next[0:0]$9627
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__oe__ok$9$next[0:0]$9628
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__output_carry$13$next[0:0]$9629
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__output_cr$15$next[0:0]$9630
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__rc__ok$7$next[0:0]$9631
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__rc__rc$6$next[0:0]$9632
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $1\sr_op__write_cr0$10$next[0:0]$9633
- attribute \src "libresoc.v:168851.3-168869.6"
- wire width 2 $1\xer_ca$23$next[1:0]$9655
- attribute \src "libresoc.v:168851.3-168869.6"
- wire $1\xer_ca_ok$24$next[0:0]$9656
- attribute \src "libresoc.v:168832.3-168850.6"
- wire $2\cr_a_ok$22$next[0:0]$9651
- attribute \src "libresoc.v:168813.3-168831.6"
- wire $2\o_ok$20$next[0:0]$9645
- attribute \src "libresoc.v:168741.3-168758.6"
- wire $2\r_busy$next[0:0]$9595
- attribute \src "libresoc.v:168772.3-168812.6"
- wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9634
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $2\sr_op__imm_data__ok$5$next[0:0]$9635
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $2\sr_op__oe__oe$8$next[0:0]$9636
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $2\sr_op__oe__ok$9$next[0:0]$9637
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $2\sr_op__rc__ok$7$next[0:0]$9638
- attribute \src "libresoc.v:168772.3-168812.6"
- wire $2\sr_op__rc__rc$6$next[0:0]$9639
- attribute \src "libresoc.v:168851.3-168869.6"
- wire $2\xer_ca_ok$24$next[0:0]$9657
- attribute \src "libresoc.v:168633.18-168633.118"
- wire $and$libresoc.v:168633$9542_Y
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9531
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9532
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__imm_data__ok$5$next[0:0]$9533
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 2 $1\sr_op__input_carry$12$next[1:0]$9534
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__input_cr$14$next[0:0]$9535
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 32 $1\sr_op__insn$18$next[31:0]$9536
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 7 $1\sr_op__insn_type$2$next[6:0]$9537
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__invert_in$11$next[0:0]$9538
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__is_32bit$16$next[0:0]$9539
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__is_signed$17$next[0:0]$9540
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__oe__oe$8$next[0:0]$9541
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__oe__ok$9$next[0:0]$9542
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__output_carry$13$next[0:0]$9543
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__output_cr$15$next[0:0]$9544
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__rc__ok$7$next[0:0]$9545
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__rc__rc$6$next[0:0]$9546
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $1\sr_op__write_cr0$10$next[0:0]$9547
+ attribute \src "libresoc.v:166652.3-166670.6"
+ wire width 2 $1\xer_ca$23$next[1:0]$9569
+ attribute \src "libresoc.v:166652.3-166670.6"
+ wire $1\xer_ca_ok$24$next[0:0]$9570
+ attribute \src "libresoc.v:166633.3-166651.6"
+ wire $2\cr_a_ok$22$next[0:0]$9565
+ attribute \src "libresoc.v:166614.3-166632.6"
+ wire $2\o_ok$20$next[0:0]$9559
+ attribute \src "libresoc.v:166542.3-166559.6"
+ wire $2\r_busy$next[0:0]$9509
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9548
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $2\sr_op__imm_data__ok$5$next[0:0]$9549
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $2\sr_op__oe__oe$8$next[0:0]$9550
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $2\sr_op__oe__ok$9$next[0:0]$9551
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $2\sr_op__rc__ok$7$next[0:0]$9552
+ attribute \src "libresoc.v:166573.3-166613.6"
+ wire $2\sr_op__rc__rc$6$next[0:0]$9553
+ attribute \src "libresoc.v:166652.3-166670.6"
+ wire $2\xer_ca_ok$24$next[0:0]$9571
+ attribute \src "libresoc.v:166434.18-166434.118"
+ wire $and$libresoc.v:166434$9456_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 56 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 input 24 \cr_a
wire \cr_a_ok$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \cr_a_ok$74
- attribute \src "libresoc.v:167828.7-167828.15"
+ attribute \src "libresoc.v:165629.7-165629.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$48
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:168633$9542
+ cell $and $and$libresoc.v:166434$9456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$50
connect \B \p_ready_o
- connect \Y $and$libresoc.v:168633$9542_Y
+ connect \Y $and$libresoc.v:166434$9456_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168684.11-168687.4"
+ attribute \src "libresoc.v:166485.11-166488.4"
cell \n$117 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168688.16-168736.4"
+ attribute \src "libresoc.v:166489.16-166537.4"
cell \output$118 \output
connect \cr_a \output_cr_a
connect \cr_a$21 \output_cr_a$45
connect \xer_so \output_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:168737.11-168740.4"
+ attribute \src "libresoc.v:166538.11-166541.4"
cell \p$116 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:167828.7-167828.20"
- process $proc$libresoc.v:167828$9658
+ attribute \src "libresoc.v:165629.7-165629.20"
+ process $proc$libresoc.v:165629$9572
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:167839.13-167839.29"
- process $proc$libresoc.v:167839$9659
+ attribute \src "libresoc.v:165640.13-165640.29"
+ process $proc$libresoc.v:165640$9573
assign { } { }
- assign $0\cr_a$21[3:0]$9660 4'0000
+ assign $0\cr_a$21[3:0]$9574 4'0000
sync always
sync init
- update \cr_a$21 $0\cr_a$21[3:0]$9660
+ update \cr_a$21 $0\cr_a$21[3:0]$9574
end
- attribute \src "libresoc.v:167848.7-167848.26"
- process $proc$libresoc.v:167848$9661
+ attribute \src "libresoc.v:165649.7-165649.26"
+ process $proc$libresoc.v:165649$9575
assign { } { }
- assign $0\cr_a_ok$22[0:0]$9662 1'0
+ assign $0\cr_a_ok$22[0:0]$9576 1'0
sync always
sync init
- update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9662
+ update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9576
end
- attribute \src "libresoc.v:167859.13-167859.29"
- process $proc$libresoc.v:167859$9663
+ attribute \src "libresoc.v:165660.13-165660.29"
+ process $proc$libresoc.v:165660$9577
assign { } { }
- assign $0\muxid$1[1:0]$9664 2'00
+ assign $0\muxid$1[1:0]$9578 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9664
+ update \muxid$1 $0\muxid$1[1:0]$9578
end
- attribute \src "libresoc.v:167874.14-167874.43"
- process $proc$libresoc.v:167874$9665
+ attribute \src "libresoc.v:165675.14-165675.43"
+ process $proc$libresoc.v:165675$9579
assign { } { }
- assign $0\o$19[63:0]$9666 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\o$19[63:0]$9580 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \o$19 $0\o$19[63:0]$9666
+ update \o$19 $0\o$19[63:0]$9580
end
- attribute \src "libresoc.v:167883.7-167883.23"
- process $proc$libresoc.v:167883$9667
+ attribute \src "libresoc.v:165684.7-165684.23"
+ process $proc$libresoc.v:165684$9581
assign { } { }
- assign $0\o_ok$20[0:0]$9668 1'0
+ assign $0\o_ok$20[0:0]$9582 1'0
sync always
sync init
- update \o_ok$20 $0\o_ok$20[0:0]$9668
+ update \o_ok$20 $0\o_ok$20[0:0]$9582
end
- attribute \src "libresoc.v:168175.7-168175.20"
- process $proc$libresoc.v:168175$9669
+ attribute \src "libresoc.v:165976.7-165976.20"
+ process $proc$libresoc.v:165976$9583
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:168210.14-168210.43"
- process $proc$libresoc.v:168210$9670
+ attribute \src "libresoc.v:166011.14-166011.43"
+ process $proc$libresoc.v:166011$9584
assign { } { }
- assign $0\sr_op__fn_unit$3[12:0]$9671 13'0000000000000
+ assign $0\sr_op__fn_unit$3[12:0]$9585 13'0000000000000
sync always
sync init
- update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9671
+ update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9585
end
- attribute \src "libresoc.v:168233.14-168233.62"
- process $proc$libresoc.v:168233$9672
+ attribute \src "libresoc.v:166034.14-166034.62"
+ process $proc$libresoc.v:166034$9586
assign { } { }
- assign $0\sr_op__imm_data__data$4[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\sr_op__imm_data__data$4[63:0]$9587 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9673
+ update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9587
end
- attribute \src "libresoc.v:168242.7-168242.37"
- process $proc$libresoc.v:168242$9674
+ attribute \src "libresoc.v:166043.7-166043.37"
+ process $proc$libresoc.v:166043$9588
assign { } { }
- assign $0\sr_op__imm_data__ok$5[0:0]$9675 1'0
+ assign $0\sr_op__imm_data__ok$5[0:0]$9589 1'0
sync always
sync init
- update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9675
+ update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9589
end
- attribute \src "libresoc.v:168259.13-168259.43"
- process $proc$libresoc.v:168259$9676
+ attribute \src "libresoc.v:166060.13-166060.43"
+ process $proc$libresoc.v:166060$9590
assign { } { }
- assign $0\sr_op__input_carry$12[1:0]$9677 2'00
+ assign $0\sr_op__input_carry$12[1:0]$9591 2'00
sync always
sync init
- update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9677
+ update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9591
end
- attribute \src "libresoc.v:168272.7-168272.34"
- process $proc$libresoc.v:168272$9678
+ attribute \src "libresoc.v:166073.7-166073.34"
+ process $proc$libresoc.v:166073$9592
assign { } { }
- assign $0\sr_op__input_cr$14[0:0]$9679 1'0
+ assign $0\sr_op__input_cr$14[0:0]$9593 1'0
sync always
sync init
- update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9679
+ update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9593
end
- attribute \src "libresoc.v:168281.14-168281.38"
- process $proc$libresoc.v:168281$9680
+ attribute \src "libresoc.v:166082.14-166082.38"
+ process $proc$libresoc.v:166082$9594
assign { } { }
- assign $0\sr_op__insn$18[31:0]$9681 0
+ assign $0\sr_op__insn$18[31:0]$9595 0
sync always
sync init
- update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9681
+ update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595
end
- attribute \src "libresoc.v:168438.13-168438.41"
- process $proc$libresoc.v:168438$9682
+ attribute \src "libresoc.v:166239.13-166239.41"
+ process $proc$libresoc.v:166239$9596
assign { } { }
- assign $0\sr_op__insn_type$2[6:0]$9683 7'0000000
+ assign $0\sr_op__insn_type$2[6:0]$9597 7'0000000
sync always
sync init
- update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9683
+ update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9597
end
- attribute \src "libresoc.v:168521.7-168521.35"
- process $proc$libresoc.v:168521$9684
+ attribute \src "libresoc.v:166322.7-166322.35"
+ process $proc$libresoc.v:166322$9598
assign { } { }
- assign $0\sr_op__invert_in$11[0:0]$9685 1'0
+ assign $0\sr_op__invert_in$11[0:0]$9599 1'0
sync always
sync init
- update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9685
+ update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9599
end
- attribute \src "libresoc.v:168530.7-168530.34"
- process $proc$libresoc.v:168530$9686
+ attribute \src "libresoc.v:166331.7-166331.34"
+ process $proc$libresoc.v:166331$9600
assign { } { }
- assign $0\sr_op__is_32bit$16[0:0]$9687 1'0
+ assign $0\sr_op__is_32bit$16[0:0]$9601 1'0
sync always
sync init
- update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9687
+ update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9601
end
- attribute \src "libresoc.v:168539.7-168539.35"
- process $proc$libresoc.v:168539$9688
+ attribute \src "libresoc.v:166340.7-166340.35"
+ process $proc$libresoc.v:166340$9602
assign { } { }
- assign $0\sr_op__is_signed$17[0:0]$9689 1'0
+ assign $0\sr_op__is_signed$17[0:0]$9603 1'0
sync always
sync init
- update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9689
+ update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9603
end
- attribute \src "libresoc.v:168550.7-168550.31"
- process $proc$libresoc.v:168550$9690
+ attribute \src "libresoc.v:166351.7-166351.31"
+ process $proc$libresoc.v:166351$9604
assign { } { }
- assign $0\sr_op__oe__oe$8[0:0]$9691 1'0
+ assign $0\sr_op__oe__oe$8[0:0]$9605 1'0
sync always
sync init
- update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9691
+ update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9605
end
- attribute \src "libresoc.v:168559.7-168559.31"
- process $proc$libresoc.v:168559$9692
+ attribute \src "libresoc.v:166360.7-166360.31"
+ process $proc$libresoc.v:166360$9606
assign { } { }
- assign $0\sr_op__oe__ok$9[0:0]$9693 1'0
+ assign $0\sr_op__oe__ok$9[0:0]$9607 1'0
sync always
sync init
- update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9693
+ update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9607
end
- attribute \src "libresoc.v:168566.7-168566.38"
- process $proc$libresoc.v:168566$9694
+ attribute \src "libresoc.v:166367.7-166367.38"
+ process $proc$libresoc.v:166367$9608
assign { } { }
- assign $0\sr_op__output_carry$13[0:0]$9695 1'0
+ assign $0\sr_op__output_carry$13[0:0]$9609 1'0
sync always
sync init
- update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9695
+ update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9609
end
- attribute \src "libresoc.v:168575.7-168575.35"
- process $proc$libresoc.v:168575$9696
+ attribute \src "libresoc.v:166376.7-166376.35"
+ process $proc$libresoc.v:166376$9610
assign { } { }
- assign $0\sr_op__output_cr$15[0:0]$9697 1'0
+ assign $0\sr_op__output_cr$15[0:0]$9611 1'0
sync always
sync init
- update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9697
+ update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9611
end
- attribute \src "libresoc.v:168586.7-168586.31"
- process $proc$libresoc.v:168586$9698
+ attribute \src "libresoc.v:166387.7-166387.31"
+ process $proc$libresoc.v:166387$9612
assign { } { }
- assign $0\sr_op__rc__ok$7[0:0]$9699 1'0
+ assign $0\sr_op__rc__ok$7[0:0]$9613 1'0
sync always
sync init
- update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9699
+ update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9613
end
- attribute \src "libresoc.v:168595.7-168595.31"
- process $proc$libresoc.v:168595$9700
+ attribute \src "libresoc.v:166396.7-166396.31"
+ process $proc$libresoc.v:166396$9614
assign { } { }
- assign $0\sr_op__rc__rc$6[0:0]$9701 1'0
+ assign $0\sr_op__rc__rc$6[0:0]$9615 1'0
sync always
sync init
- update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9701
+ update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9615
end
- attribute \src "libresoc.v:168602.7-168602.35"
- process $proc$libresoc.v:168602$9702
+ attribute \src "libresoc.v:166403.7-166403.35"
+ process $proc$libresoc.v:166403$9616
assign { } { }
- assign $0\sr_op__write_cr0$10[0:0]$9703 1'0
+ assign $0\sr_op__write_cr0$10[0:0]$9617 1'0
sync always
sync init
- update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9703
+ update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9617
end
- attribute \src "libresoc.v:168611.13-168611.31"
- process $proc$libresoc.v:168611$9704
+ attribute \src "libresoc.v:166412.13-166412.31"
+ process $proc$libresoc.v:166412$9618
assign { } { }
- assign $0\xer_ca$23[1:0]$9705 2'00
+ assign $0\xer_ca$23[1:0]$9619 2'00
sync always
sync init
- update \xer_ca$23 $0\xer_ca$23[1:0]$9705
+ update \xer_ca$23 $0\xer_ca$23[1:0]$9619
end
- attribute \src "libresoc.v:168620.7-168620.28"
- process $proc$libresoc.v:168620$9706
+ attribute \src "libresoc.v:166421.7-166421.28"
+ process $proc$libresoc.v:166421$9620
assign { } { }
- assign $0\xer_ca_ok$24[0:0]$9707 1'0
+ assign $0\xer_ca_ok$24[0:0]$9621 1'0
sync always
sync init
- update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9707
+ update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9621
end
- attribute \src "libresoc.v:168634.3-168635.37"
- process $proc$libresoc.v:168634$9543
+ attribute \src "libresoc.v:166435.3-166436.37"
+ process $proc$libresoc.v:166435$9457
assign { } { }
- assign $0\xer_ca$23[1:0]$9544 \xer_ca$23$next
+ assign $0\xer_ca$23[1:0]$9458 \xer_ca$23$next
sync posedge \coresync_clk
- update \xer_ca$23 $0\xer_ca$23[1:0]$9544
+ update \xer_ca$23 $0\xer_ca$23[1:0]$9458
end
- attribute \src "libresoc.v:168636.3-168637.43"
- process $proc$libresoc.v:168636$9545
+ attribute \src "libresoc.v:166437.3-166438.43"
+ process $proc$libresoc.v:166437$9459
assign { } { }
- assign $0\xer_ca_ok$24[0:0]$9546 \xer_ca_ok$24$next
+ assign $0\xer_ca_ok$24[0:0]$9460 \xer_ca_ok$24$next
sync posedge \coresync_clk
- update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9546
+ update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9460
end
- attribute \src "libresoc.v:168638.3-168639.33"
- process $proc$libresoc.v:168638$9547
+ attribute \src "libresoc.v:166439.3-166440.33"
+ process $proc$libresoc.v:166439$9461
assign { } { }
- assign $0\cr_a$21[3:0]$9548 \cr_a$21$next
+ assign $0\cr_a$21[3:0]$9462 \cr_a$21$next
sync posedge \coresync_clk
- update \cr_a$21 $0\cr_a$21[3:0]$9548
+ update \cr_a$21 $0\cr_a$21[3:0]$9462
end
- attribute \src "libresoc.v:168640.3-168641.39"
- process $proc$libresoc.v:168640$9549
+ attribute \src "libresoc.v:166441.3-166442.39"
+ process $proc$libresoc.v:166441$9463
assign { } { }
- assign $0\cr_a_ok$22[0:0]$9550 \cr_a_ok$22$next
+ assign $0\cr_a_ok$22[0:0]$9464 \cr_a_ok$22$next
sync posedge \coresync_clk
- update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9550
+ update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9464
end
- attribute \src "libresoc.v:168642.3-168643.27"
- process $proc$libresoc.v:168642$9551
+ attribute \src "libresoc.v:166443.3-166444.27"
+ process $proc$libresoc.v:166443$9465
assign { } { }
- assign $0\o$19[63:0]$9552 \o$19$next
+ assign $0\o$19[63:0]$9466 \o$19$next
sync posedge \coresync_clk
- update \o$19 $0\o$19[63:0]$9552
+ update \o$19 $0\o$19[63:0]$9466
end
- attribute \src "libresoc.v:168644.3-168645.33"
- process $proc$libresoc.v:168644$9553
+ attribute \src "libresoc.v:166445.3-166446.33"
+ process $proc$libresoc.v:166445$9467
assign { } { }
- assign $0\o_ok$20[0:0]$9554 \o_ok$20$next
+ assign $0\o_ok$20[0:0]$9468 \o_ok$20$next
sync posedge \coresync_clk
- update \o_ok$20 $0\o_ok$20[0:0]$9554
+ update \o_ok$20 $0\o_ok$20[0:0]$9468
end
- attribute \src "libresoc.v:168646.3-168647.55"
- process $proc$libresoc.v:168646$9555
+ attribute \src "libresoc.v:166447.3-166448.55"
+ process $proc$libresoc.v:166447$9469
assign { } { }
- assign $0\sr_op__insn_type$2[6:0]$9556 \sr_op__insn_type$2$next
+ assign $0\sr_op__insn_type$2[6:0]$9470 \sr_op__insn_type$2$next
sync posedge \coresync_clk
- update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9556
+ update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9470
end
- attribute \src "libresoc.v:168648.3-168649.51"
- process $proc$libresoc.v:168648$9557
+ attribute \src "libresoc.v:166449.3-166450.51"
+ process $proc$libresoc.v:166449$9471
assign { } { }
- assign $0\sr_op__fn_unit$3[12:0]$9558 \sr_op__fn_unit$3$next
+ assign $0\sr_op__fn_unit$3[12:0]$9472 \sr_op__fn_unit$3$next
sync posedge \coresync_clk
- update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9558
+ update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9472
end
- attribute \src "libresoc.v:168650.3-168651.65"
- process $proc$libresoc.v:168650$9559
+ attribute \src "libresoc.v:166451.3-166452.65"
+ process $proc$libresoc.v:166451$9473
assign { } { }
- assign $0\sr_op__imm_data__data$4[63:0]$9560 \sr_op__imm_data__data$4$next
+ assign $0\sr_op__imm_data__data$4[63:0]$9474 \sr_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9560
+ update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9474
end
- attribute \src "libresoc.v:168652.3-168653.61"
- process $proc$libresoc.v:168652$9561
+ attribute \src "libresoc.v:166453.3-166454.61"
+ process $proc$libresoc.v:166453$9475
assign { } { }
- assign $0\sr_op__imm_data__ok$5[0:0]$9562 \sr_op__imm_data__ok$5$next
+ assign $0\sr_op__imm_data__ok$5[0:0]$9476 \sr_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9562
+ update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9476
end
- attribute \src "libresoc.v:168654.3-168655.49"
- process $proc$libresoc.v:168654$9563
+ attribute \src "libresoc.v:166455.3-166456.49"
+ process $proc$libresoc.v:166455$9477
assign { } { }
- assign $0\sr_op__rc__rc$6[0:0]$9564 \sr_op__rc__rc$6$next
+ assign $0\sr_op__rc__rc$6[0:0]$9478 \sr_op__rc__rc$6$next
sync posedge \coresync_clk
- update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9564
+ update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9478
end
- attribute \src "libresoc.v:168656.3-168657.49"
- process $proc$libresoc.v:168656$9565
+ attribute \src "libresoc.v:166457.3-166458.49"
+ process $proc$libresoc.v:166457$9479
assign { } { }
- assign $0\sr_op__rc__ok$7[0:0]$9566 \sr_op__rc__ok$7$next
+ assign $0\sr_op__rc__ok$7[0:0]$9480 \sr_op__rc__ok$7$next
sync posedge \coresync_clk
- update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9566
+ update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9480
end
- attribute \src "libresoc.v:168658.3-168659.49"
- process $proc$libresoc.v:168658$9567
+ attribute \src "libresoc.v:166459.3-166460.49"
+ process $proc$libresoc.v:166459$9481
assign { } { }
- assign $0\sr_op__oe__oe$8[0:0]$9568 \sr_op__oe__oe$8$next
+ assign $0\sr_op__oe__oe$8[0:0]$9482 \sr_op__oe__oe$8$next
sync posedge \coresync_clk
- update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9568
+ update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9482
end
- attribute \src "libresoc.v:168660.3-168661.49"
- process $proc$libresoc.v:168660$9569
+ attribute \src "libresoc.v:166461.3-166462.49"
+ process $proc$libresoc.v:166461$9483
assign { } { }
- assign $0\sr_op__oe__ok$9[0:0]$9570 \sr_op__oe__ok$9$next
+ assign $0\sr_op__oe__ok$9[0:0]$9484 \sr_op__oe__ok$9$next
sync posedge \coresync_clk
- update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9570
+ update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9484
end
- attribute \src "libresoc.v:168662.3-168663.57"
- process $proc$libresoc.v:168662$9571
+ attribute \src "libresoc.v:166463.3-166464.57"
+ process $proc$libresoc.v:166463$9485
assign { } { }
- assign $0\sr_op__write_cr0$10[0:0]$9572 \sr_op__write_cr0$10$next
+ assign $0\sr_op__write_cr0$10[0:0]$9486 \sr_op__write_cr0$10$next
sync posedge \coresync_clk
- update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9572
+ update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9486
end
- attribute \src "libresoc.v:168664.3-168665.57"
- process $proc$libresoc.v:168664$9573
+ attribute \src "libresoc.v:166465.3-166466.57"
+ process $proc$libresoc.v:166465$9487
assign { } { }
- assign $0\sr_op__invert_in$11[0:0]$9574 \sr_op__invert_in$11$next
+ assign $0\sr_op__invert_in$11[0:0]$9488 \sr_op__invert_in$11$next
sync posedge \coresync_clk
- update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9574
+ update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9488
end
- attribute \src "libresoc.v:168666.3-168667.61"
- process $proc$libresoc.v:168666$9575
+ attribute \src "libresoc.v:166467.3-166468.61"
+ process $proc$libresoc.v:166467$9489
assign { } { }
- assign $0\sr_op__input_carry$12[1:0]$9576 \sr_op__input_carry$12$next
+ assign $0\sr_op__input_carry$12[1:0]$9490 \sr_op__input_carry$12$next
sync posedge \coresync_clk
- update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9576
+ update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9490
end
- attribute \src "libresoc.v:168668.3-168669.63"
- process $proc$libresoc.v:168668$9577
+ attribute \src "libresoc.v:166469.3-166470.63"
+ process $proc$libresoc.v:166469$9491
assign { } { }
- assign $0\sr_op__output_carry$13[0:0]$9578 \sr_op__output_carry$13$next
+ assign $0\sr_op__output_carry$13[0:0]$9492 \sr_op__output_carry$13$next
sync posedge \coresync_clk
- update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9578
+ update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9492
end
- attribute \src "libresoc.v:168670.3-168671.55"
- process $proc$libresoc.v:168670$9579
+ attribute \src "libresoc.v:166471.3-166472.55"
+ process $proc$libresoc.v:166471$9493
assign { } { }
- assign $0\sr_op__input_cr$14[0:0]$9580 \sr_op__input_cr$14$next
+ assign $0\sr_op__input_cr$14[0:0]$9494 \sr_op__input_cr$14$next
sync posedge \coresync_clk
- update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9580
+ update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9494
end
- attribute \src "libresoc.v:168672.3-168673.57"
- process $proc$libresoc.v:168672$9581
+ attribute \src "libresoc.v:166473.3-166474.57"
+ process $proc$libresoc.v:166473$9495
assign { } { }
- assign $0\sr_op__output_cr$15[0:0]$9582 \sr_op__output_cr$15$next
+ assign $0\sr_op__output_cr$15[0:0]$9496 \sr_op__output_cr$15$next
sync posedge \coresync_clk
- update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9582
+ update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9496
end
- attribute \src "libresoc.v:168674.3-168675.55"
- process $proc$libresoc.v:168674$9583
+ attribute \src "libresoc.v:166475.3-166476.55"
+ process $proc$libresoc.v:166475$9497
assign { } { }
- assign $0\sr_op__is_32bit$16[0:0]$9584 \sr_op__is_32bit$16$next
+ assign $0\sr_op__is_32bit$16[0:0]$9498 \sr_op__is_32bit$16$next
sync posedge \coresync_clk
- update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9584
+ update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9498
end
- attribute \src "libresoc.v:168676.3-168677.57"
- process $proc$libresoc.v:168676$9585
+ attribute \src "libresoc.v:166477.3-166478.57"
+ process $proc$libresoc.v:166477$9499
assign { } { }
- assign $0\sr_op__is_signed$17[0:0]$9586 \sr_op__is_signed$17$next
+ assign $0\sr_op__is_signed$17[0:0]$9500 \sr_op__is_signed$17$next
sync posedge \coresync_clk
- update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9586
+ update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9500
end
- attribute \src "libresoc.v:168678.3-168679.47"
- process $proc$libresoc.v:168678$9587
+ attribute \src "libresoc.v:166479.3-166480.47"
+ process $proc$libresoc.v:166479$9501
assign { } { }
- assign $0\sr_op__insn$18[31:0]$9588 \sr_op__insn$18$next
+ assign $0\sr_op__insn$18[31:0]$9502 \sr_op__insn$18$next
sync posedge \coresync_clk
- update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9588
+ update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9502
end
- attribute \src "libresoc.v:168680.3-168681.33"
- process $proc$libresoc.v:168680$9589
+ attribute \src "libresoc.v:166481.3-166482.33"
+ process $proc$libresoc.v:166481$9503
assign { } { }
- assign $0\muxid$1[1:0]$9590 \muxid$1$next
+ assign $0\muxid$1[1:0]$9504 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9590
+ update \muxid$1 $0\muxid$1[1:0]$9504
end
- attribute \src "libresoc.v:168682.3-168683.29"
- process $proc$libresoc.v:168682$9591
+ attribute \src "libresoc.v:166483.3-166484.29"
+ process $proc$libresoc.v:166483$9505
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:168741.3-168758.6"
- process $proc$libresoc.v:168741$9592
+ attribute \src "libresoc.v:166542.3-166559.6"
+ process $proc$libresoc.v:166542$9506
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9593 $2\r_busy$next[0:0]$9595
- attribute \src "libresoc.v:168742.5-168742.29"
+ assign $0\r_busy$next[0:0]$9507 $2\r_busy$next[0:0]$9509
+ attribute \src "libresoc.v:166543.5-166543.29"
switch \initial
- attribute \src "libresoc.v:168742.9-168742.17"
+ attribute \src "libresoc.v:166543.9-166543.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9594 1'1
+ assign $1\r_busy$next[0:0]$9508 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9594 1'0
+ assign $1\r_busy$next[0:0]$9508 1'0
case
- assign $1\r_busy$next[0:0]$9594 \r_busy
+ assign $1\r_busy$next[0:0]$9508 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9595 1'0
+ assign $2\r_busy$next[0:0]$9509 1'0
case
- assign $2\r_busy$next[0:0]$9595 $1\r_busy$next[0:0]$9594
+ assign $2\r_busy$next[0:0]$9509 $1\r_busy$next[0:0]$9508
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9593
+ update \r_busy$next $0\r_busy$next[0:0]$9507
end
- attribute \src "libresoc.v:168759.3-168771.6"
- process $proc$libresoc.v:168759$9596
+ attribute \src "libresoc.v:166560.3-166572.6"
+ process $proc$libresoc.v:166560$9510
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9597 $1\muxid$1$next[1:0]$9598
- attribute \src "libresoc.v:168760.5-168760.29"
+ assign $0\muxid$1$next[1:0]$9511 $1\muxid$1$next[1:0]$9512
+ attribute \src "libresoc.v:166561.5-166561.29"
switch \initial
- attribute \src "libresoc.v:168760.9-168760.17"
+ attribute \src "libresoc.v:166561.9-166561.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9598 \muxid$53
+ assign $1\muxid$1$next[1:0]$9512 \muxid$53
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9598 \muxid$53
+ assign $1\muxid$1$next[1:0]$9512 \muxid$53
case
- assign $1\muxid$1$next[1:0]$9598 \muxid$1
+ assign $1\muxid$1$next[1:0]$9512 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9597
+ update \muxid$1$next $0\muxid$1$next[1:0]$9511
end
- attribute \src "libresoc.v:168772.3-168812.6"
- process $proc$libresoc.v:168772$9599
+ attribute \src "libresoc.v:166573.3-166613.6"
+ process $proc$libresoc.v:166573$9513
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr_op__fn_unit$3$next[12:0]$9600 $1\sr_op__fn_unit$3$next[12:0]$9617
+ assign $0\sr_op__fn_unit$3$next[12:0]$9514 $1\sr_op__fn_unit$3$next[12:0]$9531
assign { } { }
assign { } { }
- assign $0\sr_op__input_carry$12$next[1:0]$9603 $1\sr_op__input_carry$12$next[1:0]$9620
- assign $0\sr_op__input_cr$14$next[0:0]$9604 $1\sr_op__input_cr$14$next[0:0]$9621
- assign $0\sr_op__insn$18$next[31:0]$9605 $1\sr_op__insn$18$next[31:0]$9622
- assign $0\sr_op__insn_type$2$next[6:0]$9606 $1\sr_op__insn_type$2$next[6:0]$9623
- assign $0\sr_op__invert_in$11$next[0:0]$9607 $1\sr_op__invert_in$11$next[0:0]$9624
- assign $0\sr_op__is_32bit$16$next[0:0]$9608 $1\sr_op__is_32bit$16$next[0:0]$9625
- assign $0\sr_op__is_signed$17$next[0:0]$9609 $1\sr_op__is_signed$17$next[0:0]$9626
+ assign $0\sr_op__input_carry$12$next[1:0]$9517 $1\sr_op__input_carry$12$next[1:0]$9534
+ assign $0\sr_op__input_cr$14$next[0:0]$9518 $1\sr_op__input_cr$14$next[0:0]$9535
+ assign $0\sr_op__insn$18$next[31:0]$9519 $1\sr_op__insn$18$next[31:0]$9536
+ assign $0\sr_op__insn_type$2$next[6:0]$9520 $1\sr_op__insn_type$2$next[6:0]$9537
+ assign $0\sr_op__invert_in$11$next[0:0]$9521 $1\sr_op__invert_in$11$next[0:0]$9538
+ assign $0\sr_op__is_32bit$16$next[0:0]$9522 $1\sr_op__is_32bit$16$next[0:0]$9539
+ assign $0\sr_op__is_signed$17$next[0:0]$9523 $1\sr_op__is_signed$17$next[0:0]$9540
assign { } { }
assign { } { }
- assign $0\sr_op__output_carry$13$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9629
- assign $0\sr_op__output_cr$15$next[0:0]$9613 $1\sr_op__output_cr$15$next[0:0]$9630
+ assign $0\sr_op__output_carry$13$next[0:0]$9526 $1\sr_op__output_carry$13$next[0:0]$9543
+ assign $0\sr_op__output_cr$15$next[0:0]$9527 $1\sr_op__output_cr$15$next[0:0]$9544
assign { } { }
assign { } { }
- assign $0\sr_op__write_cr0$10$next[0:0]$9616 $1\sr_op__write_cr0$10$next[0:0]$9633
- assign $0\sr_op__imm_data__data$4$next[63:0]$9601 $2\sr_op__imm_data__data$4$next[63:0]$9634
- assign $0\sr_op__imm_data__ok$5$next[0:0]$9602 $2\sr_op__imm_data__ok$5$next[0:0]$9635
- assign $0\sr_op__oe__oe$8$next[0:0]$9610 $2\sr_op__oe__oe$8$next[0:0]$9636
- assign $0\sr_op__oe__ok$9$next[0:0]$9611 $2\sr_op__oe__ok$9$next[0:0]$9637
- assign $0\sr_op__rc__ok$7$next[0:0]$9614 $2\sr_op__rc__ok$7$next[0:0]$9638
- assign $0\sr_op__rc__rc$6$next[0:0]$9615 $2\sr_op__rc__rc$6$next[0:0]$9639
- attribute \src "libresoc.v:168773.5-168773.29"
+ assign $0\sr_op__write_cr0$10$next[0:0]$9530 $1\sr_op__write_cr0$10$next[0:0]$9547
+ assign $0\sr_op__imm_data__data$4$next[63:0]$9515 $2\sr_op__imm_data__data$4$next[63:0]$9548
+ assign $0\sr_op__imm_data__ok$5$next[0:0]$9516 $2\sr_op__imm_data__ok$5$next[0:0]$9549
+ assign $0\sr_op__oe__oe$8$next[0:0]$9524 $2\sr_op__oe__oe$8$next[0:0]$9550
+ assign $0\sr_op__oe__ok$9$next[0:0]$9525 $2\sr_op__oe__ok$9$next[0:0]$9551
+ assign $0\sr_op__rc__ok$7$next[0:0]$9528 $2\sr_op__rc__ok$7$next[0:0]$9552
+ assign $0\sr_op__rc__rc$6$next[0:0]$9529 $2\sr_op__rc__rc$6$next[0:0]$9553
+ attribute \src "libresoc.v:166574.5-166574.29"
switch \initial
- attribute \src "libresoc.v:168773.9-168773.17"
+ attribute \src "libresoc.v:166574.9-166574.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$18$next[31:0]$9622 $1\sr_op__is_signed$17$next[0:0]$9626 $1\sr_op__is_32bit$16$next[0:0]$9625 $1\sr_op__output_cr$15$next[0:0]$9630 $1\sr_op__input_cr$14$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9629 $1\sr_op__input_carry$12$next[1:0]$9620 $1\sr_op__invert_in$11$next[0:0]$9624 $1\sr_op__write_cr0$10$next[0:0]$9633 $1\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__rc__ok$7$next[0:0]$9631 $1\sr_op__rc__rc$6$next[0:0]$9632 $1\sr_op__imm_data__ok$5$next[0:0]$9619 $1\sr_op__imm_data__data$4$next[63:0]$9618 $1\sr_op__fn_unit$3$next[12:0]$9617 $1\sr_op__insn_type$2$next[6:0]$9623 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
+ assign { $1\sr_op__insn$18$next[31:0]$9536 $1\sr_op__is_signed$17$next[0:0]$9540 $1\sr_op__is_32bit$16$next[0:0]$9539 $1\sr_op__output_cr$15$next[0:0]$9544 $1\sr_op__input_cr$14$next[0:0]$9535 $1\sr_op__output_carry$13$next[0:0]$9543 $1\sr_op__input_carry$12$next[1:0]$9534 $1\sr_op__invert_in$11$next[0:0]$9538 $1\sr_op__write_cr0$10$next[0:0]$9547 $1\sr_op__oe__ok$9$next[0:0]$9542 $1\sr_op__oe__oe$8$next[0:0]$9541 $1\sr_op__rc__ok$7$next[0:0]$9545 $1\sr_op__rc__rc$6$next[0:0]$9546 $1\sr_op__imm_data__ok$5$next[0:0]$9533 $1\sr_op__imm_data__data$4$next[63:0]$9532 $1\sr_op__fn_unit$3$next[12:0]$9531 $1\sr_op__insn_type$2$next[6:0]$9537 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\sr_op__insn$18$next[31:0]$9622 $1\sr_op__is_signed$17$next[0:0]$9626 $1\sr_op__is_32bit$16$next[0:0]$9625 $1\sr_op__output_cr$15$next[0:0]$9630 $1\sr_op__input_cr$14$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9629 $1\sr_op__input_carry$12$next[1:0]$9620 $1\sr_op__invert_in$11$next[0:0]$9624 $1\sr_op__write_cr0$10$next[0:0]$9633 $1\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__rc__ok$7$next[0:0]$9631 $1\sr_op__rc__rc$6$next[0:0]$9632 $1\sr_op__imm_data__ok$5$next[0:0]$9619 $1\sr_op__imm_data__data$4$next[63:0]$9618 $1\sr_op__fn_unit$3$next[12:0]$9617 $1\sr_op__insn_type$2$next[6:0]$9623 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
+ assign { $1\sr_op__insn$18$next[31:0]$9536 $1\sr_op__is_signed$17$next[0:0]$9540 $1\sr_op__is_32bit$16$next[0:0]$9539 $1\sr_op__output_cr$15$next[0:0]$9544 $1\sr_op__input_cr$14$next[0:0]$9535 $1\sr_op__output_carry$13$next[0:0]$9543 $1\sr_op__input_carry$12$next[1:0]$9534 $1\sr_op__invert_in$11$next[0:0]$9538 $1\sr_op__write_cr0$10$next[0:0]$9547 $1\sr_op__oe__ok$9$next[0:0]$9542 $1\sr_op__oe__oe$8$next[0:0]$9541 $1\sr_op__rc__ok$7$next[0:0]$9545 $1\sr_op__rc__rc$6$next[0:0]$9546 $1\sr_op__imm_data__ok$5$next[0:0]$9533 $1\sr_op__imm_data__data$4$next[63:0]$9532 $1\sr_op__fn_unit$3$next[12:0]$9531 $1\sr_op__insn_type$2$next[6:0]$9537 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 }
case
- assign $1\sr_op__fn_unit$3$next[12:0]$9617 \sr_op__fn_unit$3
- assign $1\sr_op__imm_data__data$4$next[63:0]$9618 \sr_op__imm_data__data$4
- assign $1\sr_op__imm_data__ok$5$next[0:0]$9619 \sr_op__imm_data__ok$5
- assign $1\sr_op__input_carry$12$next[1:0]$9620 \sr_op__input_carry$12
- assign $1\sr_op__input_cr$14$next[0:0]$9621 \sr_op__input_cr$14
- assign $1\sr_op__insn$18$next[31:0]$9622 \sr_op__insn$18
- assign $1\sr_op__insn_type$2$next[6:0]$9623 \sr_op__insn_type$2
- assign $1\sr_op__invert_in$11$next[0:0]$9624 \sr_op__invert_in$11
- assign $1\sr_op__is_32bit$16$next[0:0]$9625 \sr_op__is_32bit$16
- assign $1\sr_op__is_signed$17$next[0:0]$9626 \sr_op__is_signed$17
- assign $1\sr_op__oe__oe$8$next[0:0]$9627 \sr_op__oe__oe$8
- assign $1\sr_op__oe__ok$9$next[0:0]$9628 \sr_op__oe__ok$9
- assign $1\sr_op__output_carry$13$next[0:0]$9629 \sr_op__output_carry$13
- assign $1\sr_op__output_cr$15$next[0:0]$9630 \sr_op__output_cr$15
- assign $1\sr_op__rc__ok$7$next[0:0]$9631 \sr_op__rc__ok$7
- assign $1\sr_op__rc__rc$6$next[0:0]$9632 \sr_op__rc__rc$6
- assign $1\sr_op__write_cr0$10$next[0:0]$9633 \sr_op__write_cr0$10
+ assign $1\sr_op__fn_unit$3$next[12:0]$9531 \sr_op__fn_unit$3
+ assign $1\sr_op__imm_data__data$4$next[63:0]$9532 \sr_op__imm_data__data$4
+ assign $1\sr_op__imm_data__ok$5$next[0:0]$9533 \sr_op__imm_data__ok$5
+ assign $1\sr_op__input_carry$12$next[1:0]$9534 \sr_op__input_carry$12
+ assign $1\sr_op__input_cr$14$next[0:0]$9535 \sr_op__input_cr$14
+ assign $1\sr_op__insn$18$next[31:0]$9536 \sr_op__insn$18
+ assign $1\sr_op__insn_type$2$next[6:0]$9537 \sr_op__insn_type$2
+ assign $1\sr_op__invert_in$11$next[0:0]$9538 \sr_op__invert_in$11
+ assign $1\sr_op__is_32bit$16$next[0:0]$9539 \sr_op__is_32bit$16
+ assign $1\sr_op__is_signed$17$next[0:0]$9540 \sr_op__is_signed$17
+ assign $1\sr_op__oe__oe$8$next[0:0]$9541 \sr_op__oe__oe$8
+ assign $1\sr_op__oe__ok$9$next[0:0]$9542 \sr_op__oe__ok$9
+ assign $1\sr_op__output_carry$13$next[0:0]$9543 \sr_op__output_carry$13
+ assign $1\sr_op__output_cr$15$next[0:0]$9544 \sr_op__output_cr$15
+ assign $1\sr_op__rc__ok$7$next[0:0]$9545 \sr_op__rc__ok$7
+ assign $1\sr_op__rc__rc$6$next[0:0]$9546 \sr_op__rc__rc$6
+ assign $1\sr_op__write_cr0$10$next[0:0]$9547 \sr_op__write_cr0$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\sr_op__imm_data__data$4$next[63:0]$9634 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\sr_op__imm_data__ok$5$next[0:0]$9635 1'0
- assign $2\sr_op__rc__rc$6$next[0:0]$9639 1'0
- assign $2\sr_op__rc__ok$7$next[0:0]$9638 1'0
- assign $2\sr_op__oe__oe$8$next[0:0]$9636 1'0
- assign $2\sr_op__oe__ok$9$next[0:0]$9637 1'0
+ assign $2\sr_op__imm_data__data$4$next[63:0]$9548 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sr_op__imm_data__ok$5$next[0:0]$9549 1'0
+ assign $2\sr_op__rc__rc$6$next[0:0]$9553 1'0
+ assign $2\sr_op__rc__ok$7$next[0:0]$9552 1'0
+ assign $2\sr_op__oe__oe$8$next[0:0]$9550 1'0
+ assign $2\sr_op__oe__ok$9$next[0:0]$9551 1'0
case
- assign $2\sr_op__imm_data__data$4$next[63:0]$9634 $1\sr_op__imm_data__data$4$next[63:0]$9618
- assign $2\sr_op__imm_data__ok$5$next[0:0]$9635 $1\sr_op__imm_data__ok$5$next[0:0]$9619
- assign $2\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__oe__oe$8$next[0:0]$9627
- assign $2\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__ok$9$next[0:0]$9628
- assign $2\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__ok$7$next[0:0]$9631
- assign $2\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__rc__rc$6$next[0:0]$9632
+ assign $2\sr_op__imm_data__data$4$next[63:0]$9548 $1\sr_op__imm_data__data$4$next[63:0]$9532
+ assign $2\sr_op__imm_data__ok$5$next[0:0]$9549 $1\sr_op__imm_data__ok$5$next[0:0]$9533
+ assign $2\sr_op__oe__oe$8$next[0:0]$9550 $1\sr_op__oe__oe$8$next[0:0]$9541
+ assign $2\sr_op__oe__ok$9$next[0:0]$9551 $1\sr_op__oe__ok$9$next[0:0]$9542
+ assign $2\sr_op__rc__ok$7$next[0:0]$9552 $1\sr_op__rc__ok$7$next[0:0]$9545
+ assign $2\sr_op__rc__rc$6$next[0:0]$9553 $1\sr_op__rc__rc$6$next[0:0]$9546
end
sync always
- update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9600
- update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9601
- update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9602
- update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9603
- update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9604
- update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9605
- update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9606
- update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9607
- update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9608
- update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9609
- update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9610
- update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9611
- update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9612
- update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9613
- update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9614
- update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9615
- update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9616
+ update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9514
+ update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9515
+ update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9516
+ update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9517
+ update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9518
+ update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9519
+ update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9520
+ update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9521
+ update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9522
+ update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9523
+ update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9524
+ update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9525
+ update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9526
+ update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9527
+ update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9528
+ update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9529
+ update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9530
end
- attribute \src "libresoc.v:168813.3-168831.6"
- process $proc$libresoc.v:168813$9640
+ attribute \src "libresoc.v:166614.3-166632.6"
+ process $proc$libresoc.v:166614$9554
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$19$next[63:0]$9641 $1\o$19$next[63:0]$9643
+ assign $0\o$19$next[63:0]$9555 $1\o$19$next[63:0]$9557
assign { } { }
- assign $0\o_ok$20$next[0:0]$9642 $2\o_ok$20$next[0:0]$9645
- attribute \src "libresoc.v:168814.5-168814.29"
+ assign $0\o_ok$20$next[0:0]$9556 $2\o_ok$20$next[0:0]$9559
+ attribute \src "libresoc.v:166615.5-166615.29"
switch \initial
- attribute \src "libresoc.v:168814.9-168814.17"
+ attribute \src "libresoc.v:166615.9-166615.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$20$next[0:0]$9644 $1\o$19$next[63:0]$9643 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$20$next[0:0]$9558 $1\o$19$next[63:0]$9557 } { \o_ok$72 \o$71 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$20$next[0:0]$9644 $1\o$19$next[63:0]$9643 } { \o_ok$72 \o$71 }
+ assign { $1\o_ok$20$next[0:0]$9558 $1\o$19$next[63:0]$9557 } { \o_ok$72 \o$71 }
case
- assign $1\o$19$next[63:0]$9643 \o$19
- assign $1\o_ok$20$next[0:0]$9644 \o_ok$20
+ assign $1\o$19$next[63:0]$9557 \o$19
+ assign $1\o_ok$20$next[0:0]$9558 \o_ok$20
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$20$next[0:0]$9645 1'0
+ assign $2\o_ok$20$next[0:0]$9559 1'0
case
- assign $2\o_ok$20$next[0:0]$9645 $1\o_ok$20$next[0:0]$9644
+ assign $2\o_ok$20$next[0:0]$9559 $1\o_ok$20$next[0:0]$9558
end
sync always
- update \o$19$next $0\o$19$next[63:0]$9641
- update \o_ok$20$next $0\o_ok$20$next[0:0]$9642
+ update \o$19$next $0\o$19$next[63:0]$9555
+ update \o_ok$20$next $0\o_ok$20$next[0:0]$9556
end
- attribute \src "libresoc.v:168832.3-168850.6"
- process $proc$libresoc.v:168832$9646
+ attribute \src "libresoc.v:166633.3-166651.6"
+ process $proc$libresoc.v:166633$9560
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$21$next[3:0]$9647 $1\cr_a$21$next[3:0]$9649
+ assign $0\cr_a$21$next[3:0]$9561 $1\cr_a$21$next[3:0]$9563
assign { } { }
- assign $0\cr_a_ok$22$next[0:0]$9648 $2\cr_a_ok$22$next[0:0]$9651
- attribute \src "libresoc.v:168833.5-168833.29"
+ assign $0\cr_a_ok$22$next[0:0]$9562 $2\cr_a_ok$22$next[0:0]$9565
+ attribute \src "libresoc.v:166634.5-166634.29"
switch \initial
- attribute \src "libresoc.v:168833.9-168833.17"
+ attribute \src "libresoc.v:166634.9-166634.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$22$next[0:0]$9650 $1\cr_a$21$next[3:0]$9649 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$22$next[0:0]$9564 $1\cr_a$21$next[3:0]$9563 } { \cr_a_ok$74 \cr_a$73 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$22$next[0:0]$9650 $1\cr_a$21$next[3:0]$9649 } { \cr_a_ok$74 \cr_a$73 }
+ assign { $1\cr_a_ok$22$next[0:0]$9564 $1\cr_a$21$next[3:0]$9563 } { \cr_a_ok$74 \cr_a$73 }
case
- assign $1\cr_a$21$next[3:0]$9649 \cr_a$21
- assign $1\cr_a_ok$22$next[0:0]$9650 \cr_a_ok$22
+ assign $1\cr_a$21$next[3:0]$9563 \cr_a$21
+ assign $1\cr_a_ok$22$next[0:0]$9564 \cr_a_ok$22
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$22$next[0:0]$9651 1'0
+ assign $2\cr_a_ok$22$next[0:0]$9565 1'0
case
- assign $2\cr_a_ok$22$next[0:0]$9651 $1\cr_a_ok$22$next[0:0]$9650
+ assign $2\cr_a_ok$22$next[0:0]$9565 $1\cr_a_ok$22$next[0:0]$9564
end
sync always
- update \cr_a$21$next $0\cr_a$21$next[3:0]$9647
- update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9648
+ update \cr_a$21$next $0\cr_a$21$next[3:0]$9561
+ update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9562
end
- attribute \src "libresoc.v:168851.3-168869.6"
- process $proc$libresoc.v:168851$9652
+ attribute \src "libresoc.v:166652.3-166670.6"
+ process $proc$libresoc.v:166652$9566
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ca$23$next[1:0]$9653 $1\xer_ca$23$next[1:0]$9655
+ assign $0\xer_ca$23$next[1:0]$9567 $1\xer_ca$23$next[1:0]$9569
assign { } { }
- assign $0\xer_ca_ok$24$next[0:0]$9654 $2\xer_ca_ok$24$next[0:0]$9657
- attribute \src "libresoc.v:168852.5-168852.29"
+ assign $0\xer_ca_ok$24$next[0:0]$9568 $2\xer_ca_ok$24$next[0:0]$9571
+ attribute \src "libresoc.v:166653.5-166653.29"
switch \initial
- attribute \src "libresoc.v:168852.9-168852.17"
+ attribute \src "libresoc.v:166653.9-166653.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$24$next[0:0]$9656 $1\xer_ca$23$next[1:0]$9655 } { \xer_ca_ok$76 \xer_ca$75 }
+ assign { $1\xer_ca_ok$24$next[0:0]$9570 $1\xer_ca$23$next[1:0]$9569 } { \xer_ca_ok$76 \xer_ca$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ca_ok$24$next[0:0]$9656 $1\xer_ca$23$next[1:0]$9655 } { \xer_ca_ok$76 \xer_ca$75 }
+ assign { $1\xer_ca_ok$24$next[0:0]$9570 $1\xer_ca$23$next[1:0]$9569 } { \xer_ca_ok$76 \xer_ca$75 }
case
- assign $1\xer_ca$23$next[1:0]$9655 \xer_ca$23
- assign $1\xer_ca_ok$24$next[0:0]$9656 \xer_ca_ok$24
+ assign $1\xer_ca$23$next[1:0]$9569 \xer_ca$23
+ assign $1\xer_ca_ok$24$next[0:0]$9570 \xer_ca_ok$24
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ca_ok$24$next[0:0]$9657 1'0
+ assign $2\xer_ca_ok$24$next[0:0]$9571 1'0
case
- assign $2\xer_ca_ok$24$next[0:0]$9657 $1\xer_ca_ok$24$next[0:0]$9656
+ assign $2\xer_ca_ok$24$next[0:0]$9571 $1\xer_ca_ok$24$next[0:0]$9570
end
sync always
- update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9653
- update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9654
+ update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9567
+ update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9568
end
- connect \$51 $and$libresoc.v:168633$9542_Y
+ connect \$51 $and$libresoc.v:166434$9456_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 }
connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type }
connect \output_muxid \muxid
end
-attribute \src "libresoc.v:168890.1-169844.10"
+attribute \src "libresoc.v:166691.1-167645.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2"
attribute \generator "nMigen"
module \pipe2$35
- attribute \src "libresoc.v:169750.3-169768.6"
- wire width 64 $0\fast1$11$next[63:0]$9776
- attribute \src "libresoc.v:169605.3-169606.35"
- wire width 64 $0\fast1$11[63:0]$9717
- attribute \src "libresoc.v:168902.14-168902.47"
- wire width 64 $0\fast1$11[63:0]$9800
- attribute \src "libresoc.v:169750.3-169768.6"
- wire $0\fast1_ok$next[0:0]$9775
- attribute \src "libresoc.v:169607.3-169608.33"
+ attribute \src "libresoc.v:167551.3-167569.6"
+ wire width 64 $0\fast1$11$next[63:0]$9690
+ attribute \src "libresoc.v:167432.3-167433.35"
+ wire width 64 $0\fast1$11[63:0]$9654
+ attribute \src "libresoc.v:166703.14-166703.47"
+ wire width 64 $0\fast1$11[63:0]$9714
+ attribute \src "libresoc.v:167551.3-167569.6"
+ wire $0\fast1_ok$next[0:0]$9689
+ attribute \src "libresoc.v:167434.3-167435.33"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:169769.3-169787.6"
- wire width 64 $0\fast2$12$next[63:0]$9782
- attribute \src "libresoc.v:169601.3-169602.35"
- wire width 64 $0\fast2$12[63:0]$9714
- attribute \src "libresoc.v:168918.14-168918.47"
- wire width 64 $0\fast2$12[63:0]$9803
- attribute \src "libresoc.v:169769.3-169787.6"
- wire $0\fast2_ok$next[0:0]$9781
- attribute \src "libresoc.v:169603.3-169604.33"
+ attribute \src "libresoc.v:167570.3-167588.6"
+ wire width 64 $0\fast2$12$next[63:0]$9696
+ attribute \src "libresoc.v:167428.3-167429.35"
+ wire width 64 $0\fast2$12[63:0]$9651
+ attribute \src "libresoc.v:166719.14-166719.47"
+ wire width 64 $0\fast2$12[63:0]$9717
+ attribute \src "libresoc.v:167570.3-167588.6"
+ wire $0\fast2_ok$next[0:0]$9695
+ attribute \src "libresoc.v:167430.3-167431.33"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:168891.7-168891.20"
+ attribute \src "libresoc.v:166692.7-166692.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:169807.3-169825.6"
- wire width 64 $0\msr$next[63:0]$9793
- attribute \src "libresoc.v:169593.3-169594.23"
+ attribute \src "libresoc.v:167608.3-167626.6"
+ wire width 64 $0\msr$next[63:0]$9707
+ attribute \src "libresoc.v:167420.3-167421.23"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:169807.3-169825.6"
- wire $0\msr_ok$next[0:0]$9794
- attribute \src "libresoc.v:169595.3-169596.29"
+ attribute \src "libresoc.v:167608.3-167626.6"
+ wire $0\msr_ok$next[0:0]$9708
+ attribute \src "libresoc.v:167422.3-167423.29"
wire $0\msr_ok[0:0]
- attribute \src "libresoc.v:169697.3-169709.6"
- wire width 2 $0\muxid$1$next[1:0]$9747
- attribute \src "libresoc.v:169631.3-169632.33"
- wire width 2 $0\muxid$1[1:0]$9740
- attribute \src "libresoc.v:169192.13-169192.29"
- wire width 2 $0\muxid$1[1:0]$9808
- attribute \src "libresoc.v:169788.3-169806.6"
- wire width 64 $0\nia$next[63:0]$9787
- attribute \src "libresoc.v:169597.3-169598.23"
+ attribute \src "libresoc.v:167498.3-167510.6"
+ wire width 2 $0\muxid$1$next[1:0]$9661
+ attribute \src "libresoc.v:167416.3-167417.33"
+ wire width 2 $0\muxid$1[1:0]$9644
+ attribute \src "libresoc.v:166993.13-166993.29"
+ wire width 2 $0\muxid$1[1:0]$9722
+ attribute \src "libresoc.v:167589.3-167607.6"
+ wire width 64 $0\nia$next[63:0]$9701
+ attribute \src "libresoc.v:167424.3-167425.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:169788.3-169806.6"
- wire $0\nia_ok$next[0:0]$9788
- attribute \src "libresoc.v:169599.3-169600.29"
+ attribute \src "libresoc.v:167589.3-167607.6"
+ wire $0\nia_ok$next[0:0]$9702
+ attribute \src "libresoc.v:167426.3-167427.29"
wire $0\nia_ok[0:0]
- attribute \src "libresoc.v:169731.3-169749.6"
- wire width 64 $0\o$next[63:0]$9769
- attribute \src "libresoc.v:169609.3-169610.19"
+ attribute \src "libresoc.v:167532.3-167550.6"
+ wire width 64 $0\o$next[63:0]$9683
+ attribute \src "libresoc.v:167394.3-167395.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:169731.3-169749.6"
- wire $0\o_ok$next[0:0]$9770
- attribute \src "libresoc.v:169611.3-169612.25"
+ attribute \src "libresoc.v:167532.3-167550.6"
+ wire $0\o_ok$next[0:0]$9684
+ attribute \src "libresoc.v:167396.3-167397.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:169679.3-169696.6"
- wire $0\r_busy$next[0:0]$9743
- attribute \src "libresoc.v:169633.3-169634.29"
+ attribute \src "libresoc.v:167480.3-167497.6"
+ wire $0\r_busy$next[0:0]$9657
+ attribute \src "libresoc.v:167418.3-167419.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 64 $0\trap_op__cia$6$next[63:0]$9750
- attribute \src "libresoc.v:169621.3-169622.47"
- wire width 64 $0\trap_op__cia$6[63:0]$9730
- attribute \src "libresoc.v:169253.14-169253.53"
- wire width 64 $0\trap_op__cia$6[63:0]$9815
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 13 $0\trap_op__fn_unit$3$next[12:0]$9751
- attribute \src "libresoc.v:169615.3-169616.55"
- wire width 13 $0\trap_op__fn_unit$3[12:0]$9724
- attribute \src "libresoc.v:169288.14-169288.45"
- wire width 13 $0\trap_op__fn_unit$3[12:0]$9817
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 32 $0\trap_op__insn$4$next[31:0]$9752
- attribute \src "libresoc.v:169617.3-169618.49"
- wire width 32 $0\trap_op__insn$4[31:0]$9726
- attribute \src "libresoc.v:169313.14-169313.39"
- wire width 32 $0\trap_op__insn$4[31:0]$9819
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 7 $0\trap_op__insn_type$2$next[6:0]$9753
- attribute \src "libresoc.v:169613.3-169614.59"
- wire width 7 $0\trap_op__insn_type$2[6:0]$9722
- attribute \src "libresoc.v:169468.13-169468.43"
- wire width 7 $0\trap_op__insn_type$2[6:0]$9821
- attribute \src "libresoc.v:169710.3-169730.6"
- wire $0\trap_op__is_32bit$7$next[0:0]$9754
- attribute \src "libresoc.v:169623.3-169624.57"
- wire $0\trap_op__is_32bit$7[0:0]$9732
- attribute \src "libresoc.v:169553.7-169553.35"
- wire $0\trap_op__is_32bit$7[0:0]$9823
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9755
- attribute \src "libresoc.v:169629.3-169630.59"
- wire width 8 $0\trap_op__ldst_exc$10[7:0]$9738
- attribute \src "libresoc.v:169560.13-169560.43"
- wire width 8 $0\trap_op__ldst_exc$10[7:0]$9825
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 64 $0\trap_op__msr$5$next[63:0]$9756
- attribute \src "libresoc.v:169619.3-169620.47"
- wire width 64 $0\trap_op__msr$5[63:0]$9728
- attribute \src "libresoc.v:169571.14-169571.53"
- wire width 64 $0\trap_op__msr$5[63:0]$9827
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9757
- attribute \src "libresoc.v:169627.3-169628.57"
- wire width 13 $0\trap_op__trapaddr$9[12:0]$9736
- attribute \src "libresoc.v:169580.14-169580.46"
- wire width 13 $0\trap_op__trapaddr$9[12:0]$9829
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 8 $0\trap_op__traptype$8$next[7:0]$9758
- attribute \src "libresoc.v:169625.3-169626.57"
- wire width 8 $0\trap_op__traptype$8[7:0]$9734
- attribute \src "libresoc.v:169589.13-169589.42"
- wire width 8 $0\trap_op__traptype$8[7:0]$9831
- attribute \src "libresoc.v:169750.3-169768.6"
- wire width 64 $1\fast1$11$next[63:0]$9778
- attribute \src "libresoc.v:169750.3-169768.6"
- wire $1\fast1_ok$next[0:0]$9777
- attribute \src "libresoc.v:168909.7-168909.22"
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 64 $0\trap_op__cia$6$next[63:0]$9664
+ attribute \src "libresoc.v:167406.3-167407.47"
+ wire width 64 $0\trap_op__cia$6[63:0]$9634
+ attribute \src "libresoc.v:167054.14-167054.53"
+ wire width 64 $0\trap_op__cia$6[63:0]$9729
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 13 $0\trap_op__fn_unit$3$next[12:0]$9665
+ attribute \src "libresoc.v:167400.3-167401.55"
+ wire width 13 $0\trap_op__fn_unit$3[12:0]$9628
+ attribute \src "libresoc.v:167089.14-167089.45"
+ wire width 13 $0\trap_op__fn_unit$3[12:0]$9731
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 32 $0\trap_op__insn$4$next[31:0]$9666
+ attribute \src "libresoc.v:167402.3-167403.49"
+ wire width 32 $0\trap_op__insn$4[31:0]$9630
+ attribute \src "libresoc.v:167114.14-167114.39"
+ wire width 32 $0\trap_op__insn$4[31:0]$9733
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 7 $0\trap_op__insn_type$2$next[6:0]$9667
+ attribute \src "libresoc.v:167398.3-167399.59"
+ wire width 7 $0\trap_op__insn_type$2[6:0]$9626
+ attribute \src "libresoc.v:167269.13-167269.43"
+ wire width 7 $0\trap_op__insn_type$2[6:0]$9735
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire $0\trap_op__is_32bit$7$next[0:0]$9668
+ attribute \src "libresoc.v:167408.3-167409.57"
+ wire $0\trap_op__is_32bit$7[0:0]$9636
+ attribute \src "libresoc.v:167354.7-167354.35"
+ wire $0\trap_op__is_32bit$7[0:0]$9737
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9669
+ attribute \src "libresoc.v:167414.3-167415.59"
+ wire width 8 $0\trap_op__ldst_exc$10[7:0]$9642
+ attribute \src "libresoc.v:167361.13-167361.43"
+ wire width 8 $0\trap_op__ldst_exc$10[7:0]$9739
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 64 $0\trap_op__msr$5$next[63:0]$9670
+ attribute \src "libresoc.v:167404.3-167405.47"
+ wire width 64 $0\trap_op__msr$5[63:0]$9632
+ attribute \src "libresoc.v:167372.14-167372.53"
+ wire width 64 $0\trap_op__msr$5[63:0]$9741
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9671
+ attribute \src "libresoc.v:167412.3-167413.57"
+ wire width 13 $0\trap_op__trapaddr$9[12:0]$9640
+ attribute \src "libresoc.v:167381.14-167381.46"
+ wire width 13 $0\trap_op__trapaddr$9[12:0]$9743
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 8 $0\trap_op__traptype$8$next[7:0]$9672
+ attribute \src "libresoc.v:167410.3-167411.57"
+ wire width 8 $0\trap_op__traptype$8[7:0]$9638
+ attribute \src "libresoc.v:167390.13-167390.42"
+ wire width 8 $0\trap_op__traptype$8[7:0]$9745
+ attribute \src "libresoc.v:167551.3-167569.6"
+ wire width 64 $1\fast1$11$next[63:0]$9692
+ attribute \src "libresoc.v:167551.3-167569.6"
+ wire $1\fast1_ok$next[0:0]$9691
+ attribute \src "libresoc.v:166710.7-166710.22"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:169769.3-169787.6"
- wire width 64 $1\fast2$12$next[63:0]$9784
- attribute \src "libresoc.v:169769.3-169787.6"
- wire $1\fast2_ok$next[0:0]$9783
- attribute \src "libresoc.v:168925.7-168925.22"
+ attribute \src "libresoc.v:167570.3-167588.6"
+ wire width 64 $1\fast2$12$next[63:0]$9698
+ attribute \src "libresoc.v:167570.3-167588.6"
+ wire $1\fast2_ok$next[0:0]$9697
+ attribute \src "libresoc.v:166726.7-166726.22"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:169807.3-169825.6"
- wire width 64 $1\msr$next[63:0]$9795
- attribute \src "libresoc.v:169176.14-169176.40"
+ attribute \src "libresoc.v:167608.3-167626.6"
+ wire width 64 $1\msr$next[63:0]$9709
+ attribute \src "libresoc.v:166977.14-166977.40"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:169807.3-169825.6"
- wire $1\msr_ok$next[0:0]$9796
- attribute \src "libresoc.v:169183.7-169183.20"
+ attribute \src "libresoc.v:167608.3-167626.6"
+ wire $1\msr_ok$next[0:0]$9710
+ attribute \src "libresoc.v:166984.7-166984.20"
wire $1\msr_ok[0:0]
- attribute \src "libresoc.v:169697.3-169709.6"
- wire width 2 $1\muxid$1$next[1:0]$9748
- attribute \src "libresoc.v:169788.3-169806.6"
- wire width 64 $1\nia$next[63:0]$9789
- attribute \src "libresoc.v:169205.14-169205.40"
+ attribute \src "libresoc.v:167498.3-167510.6"
+ wire width 2 $1\muxid$1$next[1:0]$9662
+ attribute \src "libresoc.v:167589.3-167607.6"
+ wire width 64 $1\nia$next[63:0]$9703
+ attribute \src "libresoc.v:167006.14-167006.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:169788.3-169806.6"
- wire $1\nia_ok$next[0:0]$9790
- attribute \src "libresoc.v:169212.7-169212.20"
+ attribute \src "libresoc.v:167589.3-167607.6"
+ wire $1\nia_ok$next[0:0]$9704
+ attribute \src "libresoc.v:167013.7-167013.20"
wire $1\nia_ok[0:0]
- attribute \src "libresoc.v:169731.3-169749.6"
- wire width 64 $1\o$next[63:0]$9771
- attribute \src "libresoc.v:169219.14-169219.38"
+ attribute \src "libresoc.v:167532.3-167550.6"
+ wire width 64 $1\o$next[63:0]$9685
+ attribute \src "libresoc.v:167020.14-167020.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:169731.3-169749.6"
- wire $1\o_ok$next[0:0]$9772
- attribute \src "libresoc.v:169226.7-169226.18"
+ attribute \src "libresoc.v:167532.3-167550.6"
+ wire $1\o_ok$next[0:0]$9686
+ attribute \src "libresoc.v:167027.7-167027.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:169679.3-169696.6"
- wire $1\r_busy$next[0:0]$9744
- attribute \src "libresoc.v:169240.7-169240.20"
+ attribute \src "libresoc.v:167480.3-167497.6"
+ wire $1\r_busy$next[0:0]$9658
+ attribute \src "libresoc.v:167041.7-167041.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 64 $1\trap_op__cia$6$next[63:0]$9759
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 13 $1\trap_op__fn_unit$3$next[12:0]$9760
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 32 $1\trap_op__insn$4$next[31:0]$9761
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 7 $1\trap_op__insn_type$2$next[6:0]$9762
- attribute \src "libresoc.v:169710.3-169730.6"
- wire $1\trap_op__is_32bit$7$next[0:0]$9763
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9764
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 64 $1\trap_op__msr$5$next[63:0]$9765
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9766
- attribute \src "libresoc.v:169710.3-169730.6"
- wire width 8 $1\trap_op__traptype$8$next[7:0]$9767
- attribute \src "libresoc.v:169750.3-169768.6"
- wire $2\fast1_ok$next[0:0]$9779
- attribute \src "libresoc.v:169769.3-169787.6"
- wire $2\fast2_ok$next[0:0]$9785
- attribute \src "libresoc.v:169807.3-169825.6"
- wire $2\msr_ok$next[0:0]$9797
- attribute \src "libresoc.v:169788.3-169806.6"
- wire $2\nia_ok$next[0:0]$9791
- attribute \src "libresoc.v:169731.3-169749.6"
- wire $2\o_ok$next[0:0]$9773
- attribute \src "libresoc.v:169679.3-169696.6"
- wire $2\r_busy$next[0:0]$9745
- attribute \src "libresoc.v:169592.18-169592.118"
- wire $and$libresoc.v:169592$9708_Y
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 64 $1\trap_op__cia$6$next[63:0]$9673
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 13 $1\trap_op__fn_unit$3$next[12:0]$9674
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 32 $1\trap_op__insn$4$next[31:0]$9675
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 7 $1\trap_op__insn_type$2$next[6:0]$9676
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire $1\trap_op__is_32bit$7$next[0:0]$9677
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9678
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 64 $1\trap_op__msr$5$next[63:0]$9679
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9680
+ attribute \src "libresoc.v:167511.3-167531.6"
+ wire width 8 $1\trap_op__traptype$8$next[7:0]$9681
+ attribute \src "libresoc.v:167551.3-167569.6"
+ wire $2\fast1_ok$next[0:0]$9693
+ attribute \src "libresoc.v:167570.3-167588.6"
+ wire $2\fast2_ok$next[0:0]$9699
+ attribute \src "libresoc.v:167608.3-167626.6"
+ wire $2\msr_ok$next[0:0]$9711
+ attribute \src "libresoc.v:167589.3-167607.6"
+ wire $2\nia_ok$next[0:0]$9705
+ attribute \src "libresoc.v:167532.3-167550.6"
+ wire $2\o_ok$next[0:0]$9687
+ attribute \src "libresoc.v:167480.3-167497.6"
+ wire $2\r_busy$next[0:0]$9659
+ attribute \src "libresoc.v:167393.18-167393.118"
+ wire $and$libresoc.v:167393$9622_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 16 \fast1
wire \fast2_ok$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \fast2_ok$next
- attribute \src "libresoc.v:168891.7-168891.15"
+ attribute \src "libresoc.v:166692.7-166692.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 8 \trap_op__traptype$8$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:169592$9708
+ cell $and $and$libresoc.v:167393$9622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$25
connect \B \p_ready_o
- connect \Y $and$libresoc.v:169592$9708_Y
+ connect \Y $and$libresoc.v:167393$9622_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169635.13-169670.4"
+ attribute \src "libresoc.v:167436.13-167471.4"
cell \main$38 \main
connect \fast1 \main_fast1
connect \fast1$11 \main_fast1$23
connect \trap_op__traptype$8 \main_trap_op__traptype$20
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169671.10-169674.4"
+ attribute \src "libresoc.v:167472.10-167475.4"
cell \n$37 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:169675.10-169678.4"
+ attribute \src "libresoc.v:167476.10-167479.4"
cell \p$36 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:168891.7-168891.20"
- process $proc$libresoc.v:168891$9798
+ attribute \src "libresoc.v:166692.7-166692.20"
+ process $proc$libresoc.v:166692$9712
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:168902.14-168902.47"
- process $proc$libresoc.v:168902$9799
+ attribute \src "libresoc.v:166703.14-166703.47"
+ process $proc$libresoc.v:166703$9713
assign { } { }
- assign $0\fast1$11[63:0]$9800 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast1$11[63:0]$9714 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast1$11 $0\fast1$11[63:0]$9800
+ update \fast1$11 $0\fast1$11[63:0]$9714
end
- attribute \src "libresoc.v:168909.7-168909.22"
- process $proc$libresoc.v:168909$9801
+ attribute \src "libresoc.v:166710.7-166710.22"
+ process $proc$libresoc.v:166710$9715
assign { } { }
assign $1\fast1_ok[0:0] 1'0
sync always
sync init
update \fast1_ok $1\fast1_ok[0:0]
end
- attribute \src "libresoc.v:168918.14-168918.47"
- process $proc$libresoc.v:168918$9802
+ attribute \src "libresoc.v:166719.14-166719.47"
+ process $proc$libresoc.v:166719$9716
assign { } { }
- assign $0\fast2$12[63:0]$9803 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\fast2$12[63:0]$9717 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \fast2$12 $0\fast2$12[63:0]$9803
+ update \fast2$12 $0\fast2$12[63:0]$9717
end
- attribute \src "libresoc.v:168925.7-168925.22"
- process $proc$libresoc.v:168925$9804
+ attribute \src "libresoc.v:166726.7-166726.22"
+ process $proc$libresoc.v:166726$9718
assign { } { }
assign $1\fast2_ok[0:0] 1'0
sync always
sync init
update \fast2_ok $1\fast2_ok[0:0]
end
- attribute \src "libresoc.v:169176.14-169176.40"
- process $proc$libresoc.v:169176$9805
+ attribute \src "libresoc.v:166977.14-166977.40"
+ process $proc$libresoc.v:166977$9719
assign { } { }
assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr $1\msr[63:0]
end
- attribute \src "libresoc.v:169183.7-169183.20"
- process $proc$libresoc.v:169183$9806
+ attribute \src "libresoc.v:166984.7-166984.20"
+ process $proc$libresoc.v:166984$9720
assign { } { }
assign $1\msr_ok[0:0] 1'0
sync always
sync init
update \msr_ok $1\msr_ok[0:0]
end
- attribute \src "libresoc.v:169192.13-169192.29"
- process $proc$libresoc.v:169192$9807
+ attribute \src "libresoc.v:166993.13-166993.29"
+ process $proc$libresoc.v:166993$9721
assign { } { }
- assign $0\muxid$1[1:0]$9808 2'00
+ assign $0\muxid$1[1:0]$9722 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9808
+ update \muxid$1 $0\muxid$1[1:0]$9722
end
- attribute \src "libresoc.v:169205.14-169205.40"
- process $proc$libresoc.v:169205$9809
+ attribute \src "libresoc.v:167006.14-167006.40"
+ process $proc$libresoc.v:167006$9723
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:169212.7-169212.20"
- process $proc$libresoc.v:169212$9810
+ attribute \src "libresoc.v:167013.7-167013.20"
+ process $proc$libresoc.v:167013$9724
assign { } { }
assign $1\nia_ok[0:0] 1'0
sync always
sync init
update \nia_ok $1\nia_ok[0:0]
end
- attribute \src "libresoc.v:169219.14-169219.38"
- process $proc$libresoc.v:169219$9811
+ attribute \src "libresoc.v:167020.14-167020.38"
+ process $proc$libresoc.v:167020$9725
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:169226.7-169226.18"
- process $proc$libresoc.v:169226$9812
+ attribute \src "libresoc.v:167027.7-167027.18"
+ process $proc$libresoc.v:167027$9726
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:169240.7-169240.20"
- process $proc$libresoc.v:169240$9813
+ attribute \src "libresoc.v:167041.7-167041.20"
+ process $proc$libresoc.v:167041$9727
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:169253.14-169253.53"
- process $proc$libresoc.v:169253$9814
+ attribute \src "libresoc.v:167054.14-167054.53"
+ process $proc$libresoc.v:167054$9728
assign { } { }
- assign $0\trap_op__cia$6[63:0]$9815 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\trap_op__cia$6[63:0]$9729 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9815
+ update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9729
end
- attribute \src "libresoc.v:169288.14-169288.45"
- process $proc$libresoc.v:169288$9816
+ attribute \src "libresoc.v:167089.14-167089.45"
+ process $proc$libresoc.v:167089$9730
assign { } { }
- assign $0\trap_op__fn_unit$3[12:0]$9817 13'0000000000000
+ assign $0\trap_op__fn_unit$3[12:0]$9731 13'0000000000000
sync always
sync init
- update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9817
+ update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9731
end
- attribute \src "libresoc.v:169313.14-169313.39"
- process $proc$libresoc.v:169313$9818
+ attribute \src "libresoc.v:167114.14-167114.39"
+ process $proc$libresoc.v:167114$9732
assign { } { }
- assign $0\trap_op__insn$4[31:0]$9819 0
+ assign $0\trap_op__insn$4[31:0]$9733 0
sync always
sync init
- update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9819
+ update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733
end
- attribute \src "libresoc.v:169468.13-169468.43"
- process $proc$libresoc.v:169468$9820
+ attribute \src "libresoc.v:167269.13-167269.43"
+ process $proc$libresoc.v:167269$9734
assign { } { }
- assign $0\trap_op__insn_type$2[6:0]$9821 7'0000000
+ assign $0\trap_op__insn_type$2[6:0]$9735 7'0000000
sync always
sync init
- update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9821
+ update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9735
end
- attribute \src "libresoc.v:169553.7-169553.35"
- process $proc$libresoc.v:169553$9822
+ attribute \src "libresoc.v:167354.7-167354.35"
+ process $proc$libresoc.v:167354$9736
assign { } { }
- assign $0\trap_op__is_32bit$7[0:0]$9823 1'0
+ assign $0\trap_op__is_32bit$7[0:0]$9737 1'0
sync always
sync init
- update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9823
+ update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9737
end
- attribute \src "libresoc.v:169560.13-169560.43"
- process $proc$libresoc.v:169560$9824
+ attribute \src "libresoc.v:167361.13-167361.43"
+ process $proc$libresoc.v:167361$9738
assign { } { }
- assign $0\trap_op__ldst_exc$10[7:0]$9825 8'00000000
+ assign $0\trap_op__ldst_exc$10[7:0]$9739 8'00000000
sync always
sync init
- update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9825
+ update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9739
end
- attribute \src "libresoc.v:169571.14-169571.53"
- process $proc$libresoc.v:169571$9826
+ attribute \src "libresoc.v:167372.14-167372.53"
+ process $proc$libresoc.v:167372$9740
assign { } { }
- assign $0\trap_op__msr$5[63:0]$9827 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\trap_op__msr$5[63:0]$9741 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9827
+ update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9741
end
- attribute \src "libresoc.v:169580.14-169580.46"
- process $proc$libresoc.v:169580$9828
+ attribute \src "libresoc.v:167381.14-167381.46"
+ process $proc$libresoc.v:167381$9742
assign { } { }
- assign $0\trap_op__trapaddr$9[12:0]$9829 13'0000000000000
+ assign $0\trap_op__trapaddr$9[12:0]$9743 13'0000000000000
sync always
sync init
- update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9829
+ update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743
end
- attribute \src "libresoc.v:169589.13-169589.42"
- process $proc$libresoc.v:169589$9830
+ attribute \src "libresoc.v:167390.13-167390.42"
+ process $proc$libresoc.v:167390$9744
assign { } { }
- assign $0\trap_op__traptype$8[7:0]$9831 8'00000000
+ assign $0\trap_op__traptype$8[7:0]$9745 8'00000000
sync always
sync init
- update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9831
+ update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9745
end
- attribute \src "libresoc.v:169593.3-169594.23"
- process $proc$libresoc.v:169593$9709
+ attribute \src "libresoc.v:167394.3-167395.19"
+ process $proc$libresoc.v:167394$9623
assign { } { }
- assign $0\msr[63:0] \msr$next
+ assign $0\o[63:0] \o$next
sync posedge \coresync_clk
- update \msr $0\msr[63:0]
+ update \o $0\o[63:0]
end
- attribute \src "libresoc.v:169595.3-169596.29"
- process $proc$libresoc.v:169595$9710
+ attribute \src "libresoc.v:167396.3-167397.25"
+ process $proc$libresoc.v:167396$9624
assign { } { }
- assign $0\msr_ok[0:0] \msr_ok$next
+ assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
- update \msr_ok $0\msr_ok[0:0]
+ update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:169597.3-169598.23"
- process $proc$libresoc.v:169597$9711
+ attribute \src "libresoc.v:167398.3-167399.59"
+ process $proc$libresoc.v:167398$9625
assign { } { }
- assign $0\nia[63:0] \nia$next
+ assign $0\trap_op__insn_type$2[6:0]$9626 \trap_op__insn_type$2$next
sync posedge \coresync_clk
- update \nia $0\nia[63:0]
+ update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9626
end
- attribute \src "libresoc.v:169599.3-169600.29"
- process $proc$libresoc.v:169599$9712
+ attribute \src "libresoc.v:167400.3-167401.55"
+ process $proc$libresoc.v:167400$9627
assign { } { }
- assign $0\nia_ok[0:0] \nia_ok$next
+ assign $0\trap_op__fn_unit$3[12:0]$9628 \trap_op__fn_unit$3$next
sync posedge \coresync_clk
- update \nia_ok $0\nia_ok[0:0]
+ update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9628
end
- attribute \src "libresoc.v:169601.3-169602.35"
- process $proc$libresoc.v:169601$9713
+ attribute \src "libresoc.v:167402.3-167403.49"
+ process $proc$libresoc.v:167402$9629
assign { } { }
- assign $0\fast2$12[63:0]$9714 \fast2$12$next
+ assign $0\trap_op__insn$4[31:0]$9630 \trap_op__insn$4$next
sync posedge \coresync_clk
- update \fast2$12 $0\fast2$12[63:0]$9714
+ update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9630
end
- attribute \src "libresoc.v:169603.3-169604.33"
- process $proc$libresoc.v:169603$9715
+ attribute \src "libresoc.v:167404.3-167405.47"
+ process $proc$libresoc.v:167404$9631
assign { } { }
- assign $0\fast2_ok[0:0] \fast2_ok$next
+ assign $0\trap_op__msr$5[63:0]$9632 \trap_op__msr$5$next
sync posedge \coresync_clk
- update \fast2_ok $0\fast2_ok[0:0]
+ update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9632
end
- attribute \src "libresoc.v:169605.3-169606.35"
- process $proc$libresoc.v:169605$9716
+ attribute \src "libresoc.v:167406.3-167407.47"
+ process $proc$libresoc.v:167406$9633
assign { } { }
- assign $0\fast1$11[63:0]$9717 \fast1$11$next
+ assign $0\trap_op__cia$6[63:0]$9634 \trap_op__cia$6$next
sync posedge \coresync_clk
- update \fast1$11 $0\fast1$11[63:0]$9717
+ update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9634
end
- attribute \src "libresoc.v:169607.3-169608.33"
- process $proc$libresoc.v:169607$9718
+ attribute \src "libresoc.v:167408.3-167409.57"
+ process $proc$libresoc.v:167408$9635
assign { } { }
- assign $0\fast1_ok[0:0] \fast1_ok$next
+ assign $0\trap_op__is_32bit$7[0:0]$9636 \trap_op__is_32bit$7$next
sync posedge \coresync_clk
- update \fast1_ok $0\fast1_ok[0:0]
+ update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9636
end
- attribute \src "libresoc.v:169609.3-169610.19"
- process $proc$libresoc.v:169609$9719
+ attribute \src "libresoc.v:167410.3-167411.57"
+ process $proc$libresoc.v:167410$9637
assign { } { }
- assign $0\o[63:0] \o$next
+ assign $0\trap_op__traptype$8[7:0]$9638 \trap_op__traptype$8$next
sync posedge \coresync_clk
- update \o $0\o[63:0]
+ update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9638
end
- attribute \src "libresoc.v:169611.3-169612.25"
- process $proc$libresoc.v:169611$9720
+ attribute \src "libresoc.v:167412.3-167413.57"
+ process $proc$libresoc.v:167412$9639
assign { } { }
- assign $0\o_ok[0:0] \o_ok$next
+ assign $0\trap_op__trapaddr$9[12:0]$9640 \trap_op__trapaddr$9$next
sync posedge \coresync_clk
- update \o_ok $0\o_ok[0:0]
+ update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9640
end
- attribute \src "libresoc.v:169613.3-169614.59"
- process $proc$libresoc.v:169613$9721
+ attribute \src "libresoc.v:167414.3-167415.59"
+ process $proc$libresoc.v:167414$9641
assign { } { }
- assign $0\trap_op__insn_type$2[6:0]$9722 \trap_op__insn_type$2$next
+ assign $0\trap_op__ldst_exc$10[7:0]$9642 \trap_op__ldst_exc$10$next
sync posedge \coresync_clk
- update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9722
+ update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9642
end
- attribute \src "libresoc.v:169615.3-169616.55"
- process $proc$libresoc.v:169615$9723
+ attribute \src "libresoc.v:167416.3-167417.33"
+ process $proc$libresoc.v:167416$9643
assign { } { }
- assign $0\trap_op__fn_unit$3[12:0]$9724 \trap_op__fn_unit$3$next
+ assign $0\muxid$1[1:0]$9644 \muxid$1$next
sync posedge \coresync_clk
- update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9724
+ update \muxid$1 $0\muxid$1[1:0]$9644
end
- attribute \src "libresoc.v:169617.3-169618.49"
- process $proc$libresoc.v:169617$9725
+ attribute \src "libresoc.v:167418.3-167419.29"
+ process $proc$libresoc.v:167418$9645
assign { } { }
- assign $0\trap_op__insn$4[31:0]$9726 \trap_op__insn$4$next
+ assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
- update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9726
+ update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:169619.3-169620.47"
- process $proc$libresoc.v:169619$9727
+ attribute \src "libresoc.v:167420.3-167421.23"
+ process $proc$libresoc.v:167420$9646
assign { } { }
- assign $0\trap_op__msr$5[63:0]$9728 \trap_op__msr$5$next
+ assign $0\msr[63:0] \msr$next
sync posedge \coresync_clk
- update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9728
+ update \msr $0\msr[63:0]
end
- attribute \src "libresoc.v:169621.3-169622.47"
- process $proc$libresoc.v:169621$9729
+ attribute \src "libresoc.v:167422.3-167423.29"
+ process $proc$libresoc.v:167422$9647
assign { } { }
- assign $0\trap_op__cia$6[63:0]$9730 \trap_op__cia$6$next
+ assign $0\msr_ok[0:0] \msr_ok$next
sync posedge \coresync_clk
- update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9730
+ update \msr_ok $0\msr_ok[0:0]
end
- attribute \src "libresoc.v:169623.3-169624.57"
- process $proc$libresoc.v:169623$9731
+ attribute \src "libresoc.v:167424.3-167425.23"
+ process $proc$libresoc.v:167424$9648
assign { } { }
- assign $0\trap_op__is_32bit$7[0:0]$9732 \trap_op__is_32bit$7$next
+ assign $0\nia[63:0] \nia$next
sync posedge \coresync_clk
- update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9732
+ update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:169625.3-169626.57"
- process $proc$libresoc.v:169625$9733
+ attribute \src "libresoc.v:167426.3-167427.29"
+ process $proc$libresoc.v:167426$9649
assign { } { }
- assign $0\trap_op__traptype$8[7:0]$9734 \trap_op__traptype$8$next
+ assign $0\nia_ok[0:0] \nia_ok$next
sync posedge \coresync_clk
- update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9734
+ update \nia_ok $0\nia_ok[0:0]
end
- attribute \src "libresoc.v:169627.3-169628.57"
- process $proc$libresoc.v:169627$9735
+ attribute \src "libresoc.v:167428.3-167429.35"
+ process $proc$libresoc.v:167428$9650
assign { } { }
- assign $0\trap_op__trapaddr$9[12:0]$9736 \trap_op__trapaddr$9$next
+ assign $0\fast2$12[63:0]$9651 \fast2$12$next
sync posedge \coresync_clk
- update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9736
+ update \fast2$12 $0\fast2$12[63:0]$9651
end
- attribute \src "libresoc.v:169629.3-169630.59"
- process $proc$libresoc.v:169629$9737
+ attribute \src "libresoc.v:167430.3-167431.33"
+ process $proc$libresoc.v:167430$9652
assign { } { }
- assign $0\trap_op__ldst_exc$10[7:0]$9738 \trap_op__ldst_exc$10$next
+ assign $0\fast2_ok[0:0] \fast2_ok$next
sync posedge \coresync_clk
- update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9738
+ update \fast2_ok $0\fast2_ok[0:0]
end
- attribute \src "libresoc.v:169631.3-169632.33"
- process $proc$libresoc.v:169631$9739
+ attribute \src "libresoc.v:167432.3-167433.35"
+ process $proc$libresoc.v:167432$9653
assign { } { }
- assign $0\muxid$1[1:0]$9740 \muxid$1$next
+ assign $0\fast1$11[63:0]$9654 \fast1$11$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9740
+ update \fast1$11 $0\fast1$11[63:0]$9654
end
- attribute \src "libresoc.v:169633.3-169634.29"
- process $proc$libresoc.v:169633$9741
+ attribute \src "libresoc.v:167434.3-167435.33"
+ process $proc$libresoc.v:167434$9655
assign { } { }
- assign $0\r_busy[0:0] \r_busy$next
+ assign $0\fast1_ok[0:0] \fast1_ok$next
sync posedge \coresync_clk
- update \r_busy $0\r_busy[0:0]
+ update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:169679.3-169696.6"
- process $proc$libresoc.v:169679$9742
+ attribute \src "libresoc.v:167480.3-167497.6"
+ process $proc$libresoc.v:167480$9656
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9743 $2\r_busy$next[0:0]$9745
- attribute \src "libresoc.v:169680.5-169680.29"
+ assign $0\r_busy$next[0:0]$9657 $2\r_busy$next[0:0]$9659
+ attribute \src "libresoc.v:167481.5-167481.29"
switch \initial
- attribute \src "libresoc.v:169680.9-169680.17"
+ attribute \src "libresoc.v:167481.9-167481.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9744 1'1
+ assign $1\r_busy$next[0:0]$9658 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9744 1'0
+ assign $1\r_busy$next[0:0]$9658 1'0
case
- assign $1\r_busy$next[0:0]$9744 \r_busy
+ assign $1\r_busy$next[0:0]$9658 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9745 1'0
+ assign $2\r_busy$next[0:0]$9659 1'0
case
- assign $2\r_busy$next[0:0]$9745 $1\r_busy$next[0:0]$9744
+ assign $2\r_busy$next[0:0]$9659 $1\r_busy$next[0:0]$9658
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9743
+ update \r_busy$next $0\r_busy$next[0:0]$9657
end
- attribute \src "libresoc.v:169697.3-169709.6"
- process $proc$libresoc.v:169697$9746
+ attribute \src "libresoc.v:167498.3-167510.6"
+ process $proc$libresoc.v:167498$9660
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9747 $1\muxid$1$next[1:0]$9748
- attribute \src "libresoc.v:169698.5-169698.29"
+ assign $0\muxid$1$next[1:0]$9661 $1\muxid$1$next[1:0]$9662
+ attribute \src "libresoc.v:167499.5-167499.29"
switch \initial
- attribute \src "libresoc.v:169698.9-169698.17"
+ attribute \src "libresoc.v:167499.9-167499.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9748 \muxid$28
+ assign $1\muxid$1$next[1:0]$9662 \muxid$28
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9748 \muxid$28
+ assign $1\muxid$1$next[1:0]$9662 \muxid$28
case
- assign $1\muxid$1$next[1:0]$9748 \muxid$1
+ assign $1\muxid$1$next[1:0]$9662 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9747
+ update \muxid$1$next $0\muxid$1$next[1:0]$9661
end
- attribute \src "libresoc.v:169710.3-169730.6"
- process $proc$libresoc.v:169710$9749
+ attribute \src "libresoc.v:167511.3-167531.6"
+ process $proc$libresoc.v:167511$9663
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\trap_op__cia$6$next[63:0]$9750 $1\trap_op__cia$6$next[63:0]$9759
- assign $0\trap_op__fn_unit$3$next[12:0]$9751 $1\trap_op__fn_unit$3$next[12:0]$9760
- assign $0\trap_op__insn$4$next[31:0]$9752 $1\trap_op__insn$4$next[31:0]$9761
- assign $0\trap_op__insn_type$2$next[6:0]$9753 $1\trap_op__insn_type$2$next[6:0]$9762
- assign $0\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__is_32bit$7$next[0:0]$9763
- assign $0\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__ldst_exc$10$next[7:0]$9764
- assign $0\trap_op__msr$5$next[63:0]$9756 $1\trap_op__msr$5$next[63:0]$9765
- assign $0\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__trapaddr$9$next[12:0]$9766
- assign $0\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__traptype$8$next[7:0]$9767
- attribute \src "libresoc.v:169711.5-169711.29"
+ assign $0\trap_op__cia$6$next[63:0]$9664 $1\trap_op__cia$6$next[63:0]$9673
+ assign $0\trap_op__fn_unit$3$next[12:0]$9665 $1\trap_op__fn_unit$3$next[12:0]$9674
+ assign $0\trap_op__insn$4$next[31:0]$9666 $1\trap_op__insn$4$next[31:0]$9675
+ assign $0\trap_op__insn_type$2$next[6:0]$9667 $1\trap_op__insn_type$2$next[6:0]$9676
+ assign $0\trap_op__is_32bit$7$next[0:0]$9668 $1\trap_op__is_32bit$7$next[0:0]$9677
+ assign $0\trap_op__ldst_exc$10$next[7:0]$9669 $1\trap_op__ldst_exc$10$next[7:0]$9678
+ assign $0\trap_op__msr$5$next[63:0]$9670 $1\trap_op__msr$5$next[63:0]$9679
+ assign $0\trap_op__trapaddr$9$next[12:0]$9671 $1\trap_op__trapaddr$9$next[12:0]$9680
+ assign $0\trap_op__traptype$8$next[7:0]$9672 $1\trap_op__traptype$8$next[7:0]$9681
+ attribute \src "libresoc.v:167512.5-167512.29"
switch \initial
- attribute \src "libresoc.v:169711.9-169711.17"
+ attribute \src "libresoc.v:167512.9-167512.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__cia$6$next[63:0]$9759 $1\trap_op__msr$5$next[63:0]$9765 $1\trap_op__insn$4$next[31:0]$9761 $1\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9762 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
+ assign { $1\trap_op__ldst_exc$10$next[7:0]$9678 $1\trap_op__trapaddr$9$next[12:0]$9680 $1\trap_op__traptype$8$next[7:0]$9681 $1\trap_op__is_32bit$7$next[0:0]$9677 $1\trap_op__cia$6$next[63:0]$9673 $1\trap_op__msr$5$next[63:0]$9679 $1\trap_op__insn$4$next[31:0]$9675 $1\trap_op__fn_unit$3$next[12:0]$9674 $1\trap_op__insn_type$2$next[6:0]$9676 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__cia$6$next[63:0]$9759 $1\trap_op__msr$5$next[63:0]$9765 $1\trap_op__insn$4$next[31:0]$9761 $1\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9762 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
+ assign { $1\trap_op__ldst_exc$10$next[7:0]$9678 $1\trap_op__trapaddr$9$next[12:0]$9680 $1\trap_op__traptype$8$next[7:0]$9681 $1\trap_op__is_32bit$7$next[0:0]$9677 $1\trap_op__cia$6$next[63:0]$9673 $1\trap_op__msr$5$next[63:0]$9679 $1\trap_op__insn$4$next[31:0]$9675 $1\trap_op__fn_unit$3$next[12:0]$9674 $1\trap_op__insn_type$2$next[6:0]$9676 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 }
case
- assign $1\trap_op__cia$6$next[63:0]$9759 \trap_op__cia$6
- assign $1\trap_op__fn_unit$3$next[12:0]$9760 \trap_op__fn_unit$3
- assign $1\trap_op__insn$4$next[31:0]$9761 \trap_op__insn$4
- assign $1\trap_op__insn_type$2$next[6:0]$9762 \trap_op__insn_type$2
- assign $1\trap_op__is_32bit$7$next[0:0]$9763 \trap_op__is_32bit$7
- assign $1\trap_op__ldst_exc$10$next[7:0]$9764 \trap_op__ldst_exc$10
- assign $1\trap_op__msr$5$next[63:0]$9765 \trap_op__msr$5
- assign $1\trap_op__trapaddr$9$next[12:0]$9766 \trap_op__trapaddr$9
- assign $1\trap_op__traptype$8$next[7:0]$9767 \trap_op__traptype$8
+ assign $1\trap_op__cia$6$next[63:0]$9673 \trap_op__cia$6
+ assign $1\trap_op__fn_unit$3$next[12:0]$9674 \trap_op__fn_unit$3
+ assign $1\trap_op__insn$4$next[31:0]$9675 \trap_op__insn$4
+ assign $1\trap_op__insn_type$2$next[6:0]$9676 \trap_op__insn_type$2
+ assign $1\trap_op__is_32bit$7$next[0:0]$9677 \trap_op__is_32bit$7
+ assign $1\trap_op__ldst_exc$10$next[7:0]$9678 \trap_op__ldst_exc$10
+ assign $1\trap_op__msr$5$next[63:0]$9679 \trap_op__msr$5
+ assign $1\trap_op__trapaddr$9$next[12:0]$9680 \trap_op__trapaddr$9
+ assign $1\trap_op__traptype$8$next[7:0]$9681 \trap_op__traptype$8
end
sync always
- update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9750
- update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9751
- update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9752
- update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9753
- update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9754
- update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9755
- update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9756
- update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9757
- update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9758
+ update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9664
+ update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9665
+ update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9666
+ update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9667
+ update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9668
+ update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9669
+ update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9670
+ update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9671
+ update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9672
end
- attribute \src "libresoc.v:169731.3-169749.6"
- process $proc$libresoc.v:169731$9768
+ attribute \src "libresoc.v:167532.3-167550.6"
+ process $proc$libresoc.v:167532$9682
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9769 $1\o$next[63:0]$9771
+ assign $0\o$next[63:0]$9683 $1\o$next[63:0]$9685
assign { } { }
- assign $0\o_ok$next[0:0]$9770 $2\o_ok$next[0:0]$9773
- attribute \src "libresoc.v:169732.5-169732.29"
+ assign $0\o_ok$next[0:0]$9684 $2\o_ok$next[0:0]$9687
+ attribute \src "libresoc.v:167533.5-167533.29"
switch \initial
- attribute \src "libresoc.v:169732.9-169732.17"
+ attribute \src "libresoc.v:167533.9-167533.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9772 $1\o$next[63:0]$9771 } { \o_ok$39 \o$38 }
+ assign { $1\o_ok$next[0:0]$9686 $1\o$next[63:0]$9685 } { \o_ok$39 \o$38 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9772 $1\o$next[63:0]$9771 } { \o_ok$39 \o$38 }
+ assign { $1\o_ok$next[0:0]$9686 $1\o$next[63:0]$9685 } { \o_ok$39 \o$38 }
case
- assign $1\o$next[63:0]$9771 \o
- assign $1\o_ok$next[0:0]$9772 \o_ok
+ assign $1\o$next[63:0]$9685 \o
+ assign $1\o_ok$next[0:0]$9686 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9773 1'0
+ assign $2\o_ok$next[0:0]$9687 1'0
case
- assign $2\o_ok$next[0:0]$9773 $1\o_ok$next[0:0]$9772
+ assign $2\o_ok$next[0:0]$9687 $1\o_ok$next[0:0]$9686
end
sync always
- update \o$next $0\o$next[63:0]$9769
- update \o_ok$next $0\o_ok$next[0:0]$9770
+ update \o$next $0\o$next[63:0]$9683
+ update \o_ok$next $0\o_ok$next[0:0]$9684
end
- attribute \src "libresoc.v:169750.3-169768.6"
- process $proc$libresoc.v:169750$9774
+ attribute \src "libresoc.v:167551.3-167569.6"
+ process $proc$libresoc.v:167551$9688
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast1$11$next[63:0]$9776 $1\fast1$11$next[63:0]$9778
- assign $0\fast1_ok$next[0:0]$9775 $2\fast1_ok$next[0:0]$9779
- attribute \src "libresoc.v:169751.5-169751.29"
+ assign $0\fast1$11$next[63:0]$9690 $1\fast1$11$next[63:0]$9692
+ assign $0\fast1_ok$next[0:0]$9689 $2\fast1_ok$next[0:0]$9693
+ attribute \src "libresoc.v:167552.5-167552.29"
switch \initial
- attribute \src "libresoc.v:169751.9-169751.17"
+ attribute \src "libresoc.v:167552.9-167552.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$9777 $1\fast1$11$next[63:0]$9778 } { \fast1_ok$41 \fast1$40 }
+ assign { $1\fast1_ok$next[0:0]$9691 $1\fast1$11$next[63:0]$9692 } { \fast1_ok$41 \fast1$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast1_ok$next[0:0]$9777 $1\fast1$11$next[63:0]$9778 } { \fast1_ok$41 \fast1$40 }
+ assign { $1\fast1_ok$next[0:0]$9691 $1\fast1$11$next[63:0]$9692 } { \fast1_ok$41 \fast1$40 }
case
- assign $1\fast1_ok$next[0:0]$9777 \fast1_ok
- assign $1\fast1$11$next[63:0]$9778 \fast1$11
+ assign $1\fast1_ok$next[0:0]$9691 \fast1_ok
+ assign $1\fast1$11$next[63:0]$9692 \fast1$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast1_ok$next[0:0]$9779 1'0
+ assign $2\fast1_ok$next[0:0]$9693 1'0
case
- assign $2\fast1_ok$next[0:0]$9779 $1\fast1_ok$next[0:0]$9777
+ assign $2\fast1_ok$next[0:0]$9693 $1\fast1_ok$next[0:0]$9691
end
sync always
- update \fast1_ok$next $0\fast1_ok$next[0:0]$9775
- update \fast1$11$next $0\fast1$11$next[63:0]$9776
+ update \fast1_ok$next $0\fast1_ok$next[0:0]$9689
+ update \fast1$11$next $0\fast1$11$next[63:0]$9690
end
- attribute \src "libresoc.v:169769.3-169787.6"
- process $proc$libresoc.v:169769$9780
+ attribute \src "libresoc.v:167570.3-167588.6"
+ process $proc$libresoc.v:167570$9694
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\fast2$12$next[63:0]$9782 $1\fast2$12$next[63:0]$9784
- assign $0\fast2_ok$next[0:0]$9781 $2\fast2_ok$next[0:0]$9785
- attribute \src "libresoc.v:169770.5-169770.29"
+ assign $0\fast2$12$next[63:0]$9696 $1\fast2$12$next[63:0]$9698
+ assign $0\fast2_ok$next[0:0]$9695 $2\fast2_ok$next[0:0]$9699
+ attribute \src "libresoc.v:167571.5-167571.29"
switch \initial
- attribute \src "libresoc.v:169770.9-169770.17"
+ attribute \src "libresoc.v:167571.9-167571.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$9783 $1\fast2$12$next[63:0]$9784 } { \fast2_ok$43 \fast2$42 }
+ assign { $1\fast2_ok$next[0:0]$9697 $1\fast2$12$next[63:0]$9698 } { \fast2_ok$43 \fast2$42 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\fast2_ok$next[0:0]$9783 $1\fast2$12$next[63:0]$9784 } { \fast2_ok$43 \fast2$42 }
+ assign { $1\fast2_ok$next[0:0]$9697 $1\fast2$12$next[63:0]$9698 } { \fast2_ok$43 \fast2$42 }
case
- assign $1\fast2_ok$next[0:0]$9783 \fast2_ok
- assign $1\fast2$12$next[63:0]$9784 \fast2$12
+ assign $1\fast2_ok$next[0:0]$9697 \fast2_ok
+ assign $1\fast2$12$next[63:0]$9698 \fast2$12
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fast2_ok$next[0:0]$9785 1'0
+ assign $2\fast2_ok$next[0:0]$9699 1'0
case
- assign $2\fast2_ok$next[0:0]$9785 $1\fast2_ok$next[0:0]$9783
+ assign $2\fast2_ok$next[0:0]$9699 $1\fast2_ok$next[0:0]$9697
end
sync always
- update \fast2_ok$next $0\fast2_ok$next[0:0]$9781
- update \fast2$12$next $0\fast2$12$next[63:0]$9782
+ update \fast2_ok$next $0\fast2_ok$next[0:0]$9695
+ update \fast2$12$next $0\fast2$12$next[63:0]$9696
end
- attribute \src "libresoc.v:169788.3-169806.6"
- process $proc$libresoc.v:169788$9786
+ attribute \src "libresoc.v:167589.3-167607.6"
+ process $proc$libresoc.v:167589$9700
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$9787 $1\nia$next[63:0]$9789
+ assign $0\nia$next[63:0]$9701 $1\nia$next[63:0]$9703
assign { } { }
- assign $0\nia_ok$next[0:0]$9788 $2\nia_ok$next[0:0]$9791
- attribute \src "libresoc.v:169789.5-169789.29"
+ assign $0\nia_ok$next[0:0]$9702 $2\nia_ok$next[0:0]$9705
+ attribute \src "libresoc.v:167590.5-167590.29"
switch \initial
- attribute \src "libresoc.v:169789.9-169789.17"
+ attribute \src "libresoc.v:167590.9-167590.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$9790 $1\nia$next[63:0]$9789 } { \nia_ok$45 \nia$44 }
+ assign { $1\nia_ok$next[0:0]$9704 $1\nia$next[63:0]$9703 } { \nia_ok$45 \nia$44 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\nia_ok$next[0:0]$9790 $1\nia$next[63:0]$9789 } { \nia_ok$45 \nia$44 }
+ assign { $1\nia_ok$next[0:0]$9704 $1\nia$next[63:0]$9703 } { \nia_ok$45 \nia$44 }
case
- assign $1\nia$next[63:0]$9789 \nia
- assign $1\nia_ok$next[0:0]$9790 \nia_ok
+ assign $1\nia$next[63:0]$9703 \nia
+ assign $1\nia_ok$next[0:0]$9704 \nia_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\nia_ok$next[0:0]$9791 1'0
+ assign $2\nia_ok$next[0:0]$9705 1'0
case
- assign $2\nia_ok$next[0:0]$9791 $1\nia_ok$next[0:0]$9790
+ assign $2\nia_ok$next[0:0]$9705 $1\nia_ok$next[0:0]$9704
end
sync always
- update \nia$next $0\nia$next[63:0]$9787
- update \nia_ok$next $0\nia_ok$next[0:0]$9788
+ update \nia$next $0\nia$next[63:0]$9701
+ update \nia_ok$next $0\nia_ok$next[0:0]$9702
end
- attribute \src "libresoc.v:169807.3-169825.6"
- process $proc$libresoc.v:169807$9792
+ attribute \src "libresoc.v:167608.3-167626.6"
+ process $proc$libresoc.v:167608$9706
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr$next[63:0]$9793 $1\msr$next[63:0]$9795
+ assign $0\msr$next[63:0]$9707 $1\msr$next[63:0]$9709
assign { } { }
- assign $0\msr_ok$next[0:0]$9794 $2\msr_ok$next[0:0]$9797
- attribute \src "libresoc.v:169808.5-169808.29"
+ assign $0\msr_ok$next[0:0]$9708 $2\msr_ok$next[0:0]$9711
+ attribute \src "libresoc.v:167609.5-167609.29"
switch \initial
- attribute \src "libresoc.v:169808.9-169808.17"
+ attribute \src "libresoc.v:167609.9-167609.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\msr_ok$next[0:0]$9796 $1\msr$next[63:0]$9795 } { \msr_ok$47 \msr$46 }
+ assign { $1\msr_ok$next[0:0]$9710 $1\msr$next[63:0]$9709 } { \msr_ok$47 \msr$46 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\msr_ok$next[0:0]$9796 $1\msr$next[63:0]$9795 } { \msr_ok$47 \msr$46 }
+ assign { $1\msr_ok$next[0:0]$9710 $1\msr$next[63:0]$9709 } { \msr_ok$47 \msr$46 }
case
- assign $1\msr$next[63:0]$9795 \msr
- assign $1\msr_ok$next[0:0]$9796 \msr_ok
+ assign $1\msr$next[63:0]$9709 \msr
+ assign $1\msr_ok$next[0:0]$9710 \msr_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_ok$next[0:0]$9797 1'0
+ assign $2\msr_ok$next[0:0]$9711 1'0
case
- assign $2\msr_ok$next[0:0]$9797 $1\msr_ok$next[0:0]$9796
+ assign $2\msr_ok$next[0:0]$9711 $1\msr_ok$next[0:0]$9710
end
sync always
- update \msr$next $0\msr$next[63:0]$9793
- update \msr_ok$next $0\msr_ok$next[0:0]$9794
+ update \msr$next $0\msr$next[63:0]$9707
+ update \msr_ok$next $0\msr_ok$next[0:0]$9708
end
- connect \$26 $and$libresoc.v:169592$9708_Y
+ connect \$26 $and$libresoc.v:167393$9622_Y
connect \p_ready_o \n_i_rdy_data
connect \n_valid_o \r_busy
connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr }
connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
connect \main_muxid \muxid
end
-attribute \src "libresoc.v:169848.1-171337.10"
+attribute \src "libresoc.v:167649.1-169138.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end"
attribute \generator "nMigen"
module \pipe_end
- attribute \src "libresoc.v:171175.3-171193.6"
- wire width 4 $0\cr_a$next[3:0]$9888
- attribute \src "libresoc.v:170994.3-170995.25"
+ attribute \src "libresoc.v:168976.3-168994.6"
+ wire width 4 $0\cr_a$next[3:0]$9802
+ attribute \src "libresoc.v:168795.3-168796.25"
wire width 4 $0\cr_a[3:0]
- attribute \src "libresoc.v:171175.3-171193.6"
- wire $0\cr_a_ok$next[0:0]$9889
- attribute \src "libresoc.v:170996.3-170997.31"
+ attribute \src "libresoc.v:168976.3-168994.6"
+ wire $0\cr_a_ok$next[0:0]$9803
+ attribute \src "libresoc.v:168797.3-168798.31"
wire $0\cr_a_ok[0:0]
- attribute \src "libresoc.v:169849.7-169849.20"
+ attribute \src "libresoc.v:167650.7-167650.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 4 $0\logical_op__data_len$18$next[3:0]$9913
- attribute \src "libresoc.v:171034.3-171035.65"
- wire width 4 $0\logical_op__data_len$18[3:0]$9875
- attribute \src "libresoc.v:169890.13-169890.45"
- wire width 4 $0\logical_op__data_len$18[3:0]$9959
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9914
- attribute \src "libresoc.v:171004.3-171005.61"
- wire width 13 $0\logical_op__fn_unit$3[12:0]$9845
- attribute \src "libresoc.v:169927.14-169927.48"
- wire width 13 $0\logical_op__fn_unit$3[12:0]$9961
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9915
- attribute \src "libresoc.v:171006.3-171007.75"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$9847
- attribute \src "libresoc.v:169950.14-169950.67"
- wire width 64 $0\logical_op__imm_data__data$4[63:0]$9963
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__imm_data__ok$5$next[0:0]$9916
- attribute \src "libresoc.v:171008.3-171009.71"
- wire $0\logical_op__imm_data__ok$5[0:0]$9849
- attribute \src "libresoc.v:169959.7-169959.42"
- wire $0\logical_op__imm_data__ok$5[0:0]$9965
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 2 $0\logical_op__input_carry$12$next[1:0]$9917
- attribute \src "libresoc.v:171022.3-171023.71"
- wire width 2 $0\logical_op__input_carry$12[1:0]$9863
- attribute \src "libresoc.v:169976.13-169976.48"
- wire width 2 $0\logical_op__input_carry$12[1:0]$9967
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 32 $0\logical_op__insn$19$next[31:0]$9918
- attribute \src "libresoc.v:171036.3-171037.57"
- wire width 32 $0\logical_op__insn$19[31:0]$9877
- attribute \src "libresoc.v:169989.14-169989.43"
- wire width 32 $0\logical_op__insn$19[31:0]$9969
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 7 $0\logical_op__insn_type$2$next[6:0]$9919
- attribute \src "libresoc.v:171002.3-171003.65"
- wire width 7 $0\logical_op__insn_type$2[6:0]$9843
- attribute \src "libresoc.v:170146.13-170146.46"
- wire width 7 $0\logical_op__insn_type$2[6:0]$9971
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__invert_in$10$next[0:0]$9920
- attribute \src "libresoc.v:171018.3-171019.67"
- wire $0\logical_op__invert_in$10[0:0]$9859
- attribute \src "libresoc.v:170229.7-170229.40"
- wire $0\logical_op__invert_in$10[0:0]$9973
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__invert_out$13$next[0:0]$9921
- attribute \src "libresoc.v:171024.3-171025.69"
- wire $0\logical_op__invert_out$13[0:0]$9865
- attribute \src "libresoc.v:170238.7-170238.41"
- wire $0\logical_op__invert_out$13[0:0]$9975
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__is_32bit$16$next[0:0]$9922
- attribute \src "libresoc.v:171030.3-171031.65"
- wire $0\logical_op__is_32bit$16[0:0]$9871
- attribute \src "libresoc.v:170247.7-170247.39"
- wire $0\logical_op__is_32bit$16[0:0]$9977
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__is_signed$17$next[0:0]$9923
- attribute \src "libresoc.v:171032.3-171033.67"
- wire $0\logical_op__is_signed$17[0:0]$9873
- attribute \src "libresoc.v:170256.7-170256.40"
- wire $0\logical_op__is_signed$17[0:0]$9979
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__oe__oe$8$next[0:0]$9924
- attribute \src "libresoc.v:171014.3-171015.59"
- wire $0\logical_op__oe__oe$8[0:0]$9855
- attribute \src "libresoc.v:170265.7-170265.36"
- wire $0\logical_op__oe__oe$8[0:0]$9981
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__oe__ok$9$next[0:0]$9925
- attribute \src "libresoc.v:171016.3-171017.59"
- wire $0\logical_op__oe__ok$9[0:0]$9857
- attribute \src "libresoc.v:170276.7-170276.36"
- wire $0\logical_op__oe__ok$9[0:0]$9983
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__output_carry$15$next[0:0]$9926
- attribute \src "libresoc.v:171028.3-171029.73"
- wire $0\logical_op__output_carry$15[0:0]$9869
- attribute \src "libresoc.v:170283.7-170283.43"
- wire $0\logical_op__output_carry$15[0:0]$9985
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__rc__ok$7$next[0:0]$9927
- attribute \src "libresoc.v:171012.3-171013.59"
- wire $0\logical_op__rc__ok$7[0:0]$9853
- attribute \src "libresoc.v:170292.7-170292.36"
- wire $0\logical_op__rc__ok$7[0:0]$9987
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__rc__rc$6$next[0:0]$9928
- attribute \src "libresoc.v:171010.3-171011.59"
- wire $0\logical_op__rc__rc$6[0:0]$9851
- attribute \src "libresoc.v:170301.7-170301.36"
- wire $0\logical_op__rc__rc$6[0:0]$9989
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__write_cr0$14$next[0:0]$9929
- attribute \src "libresoc.v:171026.3-171027.67"
- wire $0\logical_op__write_cr0$14[0:0]$9867
- attribute \src "libresoc.v:170310.7-170310.40"
- wire $0\logical_op__write_cr0$14[0:0]$9991
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $0\logical_op__zero_a$11$next[0:0]$9930
- attribute \src "libresoc.v:171020.3-171021.61"
- wire $0\logical_op__zero_a$11[0:0]$9861
- attribute \src "libresoc.v:170319.7-170319.37"
- wire $0\logical_op__zero_a$11[0:0]$9993
- attribute \src "libresoc.v:171250.3-171262.6"
- wire width 2 $0\muxid$1$next[1:0]$9910
- attribute \src "libresoc.v:171038.3-171039.33"
- wire width 2 $0\muxid$1[1:0]$9879
- attribute \src "libresoc.v:170328.13-170328.29"
- wire width 2 $0\muxid$1[1:0]$9995
- attribute \src "libresoc.v:171156.3-171174.6"
- wire width 64 $0\o$next[63:0]$9882
- attribute \src "libresoc.v:170998.3-170999.19"
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 4 $0\logical_op__data_len$18$next[3:0]$9827
+ attribute \src "libresoc.v:168835.3-168836.65"
+ wire width 4 $0\logical_op__data_len$18[3:0]$9789
+ attribute \src "libresoc.v:167691.13-167691.45"
+ wire width 4 $0\logical_op__data_len$18[3:0]$9873
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9828
+ attribute \src "libresoc.v:168805.3-168806.61"
+ wire width 13 $0\logical_op__fn_unit$3[12:0]$9759
+ attribute \src "libresoc.v:167728.14-167728.48"
+ wire width 13 $0\logical_op__fn_unit$3[12:0]$9875
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9829
+ attribute \src "libresoc.v:168807.3-168808.75"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$9761
+ attribute \src "libresoc.v:167751.14-167751.67"
+ wire width 64 $0\logical_op__imm_data__data$4[63:0]$9877
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__imm_data__ok$5$next[0:0]$9830
+ attribute \src "libresoc.v:168809.3-168810.71"
+ wire $0\logical_op__imm_data__ok$5[0:0]$9763
+ attribute \src "libresoc.v:167760.7-167760.42"
+ wire $0\logical_op__imm_data__ok$5[0:0]$9879
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 2 $0\logical_op__input_carry$12$next[1:0]$9831
+ attribute \src "libresoc.v:168823.3-168824.71"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$9777
+ attribute \src "libresoc.v:167777.13-167777.48"
+ wire width 2 $0\logical_op__input_carry$12[1:0]$9881
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 32 $0\logical_op__insn$19$next[31:0]$9832
+ attribute \src "libresoc.v:168837.3-168838.57"
+ wire width 32 $0\logical_op__insn$19[31:0]$9791
+ attribute \src "libresoc.v:167790.14-167790.43"
+ wire width 32 $0\logical_op__insn$19[31:0]$9883
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 7 $0\logical_op__insn_type$2$next[6:0]$9833
+ attribute \src "libresoc.v:168803.3-168804.65"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$9757
+ attribute \src "libresoc.v:167947.13-167947.46"
+ wire width 7 $0\logical_op__insn_type$2[6:0]$9885
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__invert_in$10$next[0:0]$9834
+ attribute \src "libresoc.v:168819.3-168820.67"
+ wire $0\logical_op__invert_in$10[0:0]$9773
+ attribute \src "libresoc.v:168030.7-168030.40"
+ wire $0\logical_op__invert_in$10[0:0]$9887
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__invert_out$13$next[0:0]$9835
+ attribute \src "libresoc.v:168825.3-168826.69"
+ wire $0\logical_op__invert_out$13[0:0]$9779
+ attribute \src "libresoc.v:168039.7-168039.41"
+ wire $0\logical_op__invert_out$13[0:0]$9889
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__is_32bit$16$next[0:0]$9836
+ attribute \src "libresoc.v:168831.3-168832.65"
+ wire $0\logical_op__is_32bit$16[0:0]$9785
+ attribute \src "libresoc.v:168048.7-168048.39"
+ wire $0\logical_op__is_32bit$16[0:0]$9891
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__is_signed$17$next[0:0]$9837
+ attribute \src "libresoc.v:168833.3-168834.67"
+ wire $0\logical_op__is_signed$17[0:0]$9787
+ attribute \src "libresoc.v:168057.7-168057.40"
+ wire $0\logical_op__is_signed$17[0:0]$9893
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__oe__oe$8$next[0:0]$9838
+ attribute \src "libresoc.v:168815.3-168816.59"
+ wire $0\logical_op__oe__oe$8[0:0]$9769
+ attribute \src "libresoc.v:168066.7-168066.36"
+ wire $0\logical_op__oe__oe$8[0:0]$9895
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__oe__ok$9$next[0:0]$9839
+ attribute \src "libresoc.v:168817.3-168818.59"
+ wire $0\logical_op__oe__ok$9[0:0]$9771
+ attribute \src "libresoc.v:168077.7-168077.36"
+ wire $0\logical_op__oe__ok$9[0:0]$9897
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__output_carry$15$next[0:0]$9840
+ attribute \src "libresoc.v:168829.3-168830.73"
+ wire $0\logical_op__output_carry$15[0:0]$9783
+ attribute \src "libresoc.v:168084.7-168084.43"
+ wire $0\logical_op__output_carry$15[0:0]$9899
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__rc__ok$7$next[0:0]$9841
+ attribute \src "libresoc.v:168813.3-168814.59"
+ wire $0\logical_op__rc__ok$7[0:0]$9767
+ attribute \src "libresoc.v:168093.7-168093.36"
+ wire $0\logical_op__rc__ok$7[0:0]$9901
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__rc__rc$6$next[0:0]$9842
+ attribute \src "libresoc.v:168811.3-168812.59"
+ wire $0\logical_op__rc__rc$6[0:0]$9765
+ attribute \src "libresoc.v:168102.7-168102.36"
+ wire $0\logical_op__rc__rc$6[0:0]$9903
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__write_cr0$14$next[0:0]$9843
+ attribute \src "libresoc.v:168827.3-168828.67"
+ wire $0\logical_op__write_cr0$14[0:0]$9781
+ attribute \src "libresoc.v:168111.7-168111.40"
+ wire $0\logical_op__write_cr0$14[0:0]$9905
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $0\logical_op__zero_a$11$next[0:0]$9844
+ attribute \src "libresoc.v:168821.3-168822.61"
+ wire $0\logical_op__zero_a$11[0:0]$9775
+ attribute \src "libresoc.v:168120.7-168120.37"
+ wire $0\logical_op__zero_a$11[0:0]$9907
+ attribute \src "libresoc.v:169051.3-169063.6"
+ wire width 2 $0\muxid$1$next[1:0]$9824
+ attribute \src "libresoc.v:168839.3-168840.33"
+ wire width 2 $0\muxid$1[1:0]$9793
+ attribute \src "libresoc.v:168129.13-168129.29"
+ wire width 2 $0\muxid$1[1:0]$9909
+ attribute \src "libresoc.v:168957.3-168975.6"
+ wire width 64 $0\o$next[63:0]$9796
+ attribute \src "libresoc.v:168799.3-168800.19"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:171156.3-171174.6"
- wire $0\o_ok$next[0:0]$9883
- attribute \src "libresoc.v:171000.3-171001.25"
+ attribute \src "libresoc.v:168957.3-168975.6"
+ wire $0\o_ok$next[0:0]$9797
+ attribute \src "libresoc.v:168801.3-168802.25"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:171232.3-171249.6"
- wire $0\r_busy$next[0:0]$9906
- attribute \src "libresoc.v:171040.3-171041.29"
+ attribute \src "libresoc.v:169033.3-169050.6"
+ wire $0\r_busy$next[0:0]$9820
+ attribute \src "libresoc.v:168841.3-168842.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:171194.3-171212.6"
- wire width 2 $0\xer_ov$next[1:0]$9894
- attribute \src "libresoc.v:170990.3-170991.29"
+ attribute \src "libresoc.v:168995.3-169013.6"
+ wire width 2 $0\xer_ov$next[1:0]$9808
+ attribute \src "libresoc.v:168791.3-168792.29"
wire width 2 $0\xer_ov[1:0]
- attribute \src "libresoc.v:171194.3-171212.6"
- wire $0\xer_ov_ok$next[0:0]$9895
- attribute \src "libresoc.v:170992.3-170993.35"
+ attribute \src "libresoc.v:168995.3-169013.6"
+ wire $0\xer_ov_ok$next[0:0]$9809
+ attribute \src "libresoc.v:168793.3-168794.35"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:171213.3-171231.6"
- wire $0\xer_so$20$next[0:0]$9901
- attribute \src "libresoc.v:170971.7-170971.25"
- wire $0\xer_so$20[0:0]$10002
- attribute \src "libresoc.v:170986.3-170987.37"
- wire $0\xer_so$20[0:0]$9834
- attribute \src "libresoc.v:171213.3-171231.6"
- wire $0\xer_so_ok$next[0:0]$9900
- attribute \src "libresoc.v:170988.3-170989.35"
+ attribute \src "libresoc.v:169014.3-169032.6"
+ wire $0\xer_so$20$next[0:0]$9815
+ attribute \src "libresoc.v:168787.3-168788.37"
+ wire $0\xer_so$20[0:0]$9748
+ attribute \src "libresoc.v:168772.7-168772.25"
+ wire $0\xer_so$20[0:0]$9916
+ attribute \src "libresoc.v:169014.3-169032.6"
+ wire $0\xer_so_ok$next[0:0]$9814
+ attribute \src "libresoc.v:168789.3-168790.35"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:171175.3-171193.6"
- wire width 4 $1\cr_a$next[3:0]$9890
- attribute \src "libresoc.v:169858.13-169858.24"
+ attribute \src "libresoc.v:168976.3-168994.6"
+ wire width 4 $1\cr_a$next[3:0]$9804
+ attribute \src "libresoc.v:167659.13-167659.24"
wire width 4 $1\cr_a[3:0]
- attribute \src "libresoc.v:171175.3-171193.6"
- wire $1\cr_a_ok$next[0:0]$9891
- attribute \src "libresoc.v:169867.7-169867.21"
+ attribute \src "libresoc.v:168976.3-168994.6"
+ wire $1\cr_a_ok$next[0:0]$9805
+ attribute \src "libresoc.v:167668.7-167668.21"
wire $1\cr_a_ok[0:0]
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 4 $1\logical_op__data_len$18$next[3:0]$9931
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 13 $1\logical_op__fn_unit$3$next[12:0]$9932
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9933
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__imm_data__ok$5$next[0:0]$9934
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 2 $1\logical_op__input_carry$12$next[1:0]$9935
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 32 $1\logical_op__insn$19$next[31:0]$9936
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 7 $1\logical_op__insn_type$2$next[6:0]$9937
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__invert_in$10$next[0:0]$9938
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__invert_out$13$next[0:0]$9939
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__is_32bit$16$next[0:0]$9940
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__is_signed$17$next[0:0]$9941
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__oe__oe$8$next[0:0]$9942
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__oe__ok$9$next[0:0]$9943
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__output_carry$15$next[0:0]$9944
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__rc__ok$7$next[0:0]$9945
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__rc__rc$6$next[0:0]$9946
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__write_cr0$14$next[0:0]$9947
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $1\logical_op__zero_a$11$next[0:0]$9948
- attribute \src "libresoc.v:171250.3-171262.6"
- wire width 2 $1\muxid$1$next[1:0]$9911
- attribute \src "libresoc.v:171156.3-171174.6"
- wire width 64 $1\o$next[63:0]$9884
- attribute \src "libresoc.v:170341.14-170341.38"
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 4 $1\logical_op__data_len$18$next[3:0]$9845
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 13 $1\logical_op__fn_unit$3$next[12:0]$9846
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9847
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__imm_data__ok$5$next[0:0]$9848
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 2 $1\logical_op__input_carry$12$next[1:0]$9849
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 32 $1\logical_op__insn$19$next[31:0]$9850
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 7 $1\logical_op__insn_type$2$next[6:0]$9851
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__invert_in$10$next[0:0]$9852
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__invert_out$13$next[0:0]$9853
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__is_32bit$16$next[0:0]$9854
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__is_signed$17$next[0:0]$9855
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__oe__oe$8$next[0:0]$9856
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__oe__ok$9$next[0:0]$9857
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__output_carry$15$next[0:0]$9858
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__rc__ok$7$next[0:0]$9859
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__rc__rc$6$next[0:0]$9860
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__write_cr0$14$next[0:0]$9861
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $1\logical_op__zero_a$11$next[0:0]$9862
+ attribute \src "libresoc.v:169051.3-169063.6"
+ wire width 2 $1\muxid$1$next[1:0]$9825
+ attribute \src "libresoc.v:168957.3-168975.6"
+ wire width 64 $1\o$next[63:0]$9798
+ attribute \src "libresoc.v:168142.14-168142.38"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:171156.3-171174.6"
- wire $1\o_ok$next[0:0]$9885
- attribute \src "libresoc.v:170348.7-170348.18"
+ attribute \src "libresoc.v:168957.3-168975.6"
+ wire $1\o_ok$next[0:0]$9799
+ attribute \src "libresoc.v:168149.7-168149.18"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:171232.3-171249.6"
- wire $1\r_busy$next[0:0]$9907
- attribute \src "libresoc.v:170936.7-170936.20"
+ attribute \src "libresoc.v:169033.3-169050.6"
+ wire $1\r_busy$next[0:0]$9821
+ attribute \src "libresoc.v:168737.7-168737.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:171194.3-171212.6"
- wire width 2 $1\xer_ov$next[1:0]$9896
- attribute \src "libresoc.v:170951.13-170951.26"
+ attribute \src "libresoc.v:168995.3-169013.6"
+ wire width 2 $1\xer_ov$next[1:0]$9810
+ attribute \src "libresoc.v:168752.13-168752.26"
wire width 2 $1\xer_ov[1:0]
- attribute \src "libresoc.v:171194.3-171212.6"
- wire $1\xer_ov_ok$next[0:0]$9897
- attribute \src "libresoc.v:170958.7-170958.23"
+ attribute \src "libresoc.v:168995.3-169013.6"
+ wire $1\xer_ov_ok$next[0:0]$9811
+ attribute \src "libresoc.v:168759.7-168759.23"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:171213.3-171231.6"
- wire $1\xer_so$20$next[0:0]$9903
- attribute \src "libresoc.v:171213.3-171231.6"
- wire $1\xer_so_ok$next[0:0]$9902
- attribute \src "libresoc.v:170976.7-170976.23"
+ attribute \src "libresoc.v:169014.3-169032.6"
+ wire $1\xer_so$20$next[0:0]$9817
+ attribute \src "libresoc.v:169014.3-169032.6"
+ wire $1\xer_so_ok$next[0:0]$9816
+ attribute \src "libresoc.v:168777.7-168777.23"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:171175.3-171193.6"
- wire $2\cr_a_ok$next[0:0]$9892
- attribute \src "libresoc.v:171263.3-171304.6"
- wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9949
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $2\logical_op__imm_data__ok$5$next[0:0]$9950
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $2\logical_op__oe__oe$8$next[0:0]$9951
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $2\logical_op__oe__ok$9$next[0:0]$9952
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $2\logical_op__rc__ok$7$next[0:0]$9953
- attribute \src "libresoc.v:171263.3-171304.6"
- wire $2\logical_op__rc__rc$6$next[0:0]$9954
- attribute \src "libresoc.v:171156.3-171174.6"
- wire $2\o_ok$next[0:0]$9886
- attribute \src "libresoc.v:171232.3-171249.6"
- wire $2\r_busy$next[0:0]$9908
- attribute \src "libresoc.v:171194.3-171212.6"
- wire $2\xer_ov_ok$next[0:0]$9898
- attribute \src "libresoc.v:171213.3-171231.6"
- wire $2\xer_so_ok$next[0:0]$9904
- attribute \src "libresoc.v:170985.18-170985.118"
- wire $and$libresoc.v:170985$9832_Y
+ attribute \src "libresoc.v:168976.3-168994.6"
+ wire $2\cr_a_ok$next[0:0]$9806
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9863
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $2\logical_op__imm_data__ok$5$next[0:0]$9864
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $2\logical_op__oe__oe$8$next[0:0]$9865
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $2\logical_op__oe__ok$9$next[0:0]$9866
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $2\logical_op__rc__ok$7$next[0:0]$9867
+ attribute \src "libresoc.v:169064.3-169105.6"
+ wire $2\logical_op__rc__rc$6$next[0:0]$9868
+ attribute \src "libresoc.v:168957.3-168975.6"
+ wire $2\o_ok$next[0:0]$9800
+ attribute \src "libresoc.v:169033.3-169050.6"
+ wire $2\r_busy$next[0:0]$9822
+ attribute \src "libresoc.v:168995.3-169013.6"
+ wire $2\xer_ov_ok$next[0:0]$9812
+ attribute \src "libresoc.v:169014.3-169032.6"
+ wire $2\xer_so_ok$next[0:0]$9818
+ attribute \src "libresoc.v:168786.18-168786.118"
+ wire $and$libresoc.v:168786$9746_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 62 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 4 output 56 \cr_a
wire input 27 \dividend_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
wire input 26 \divisor_neg
- attribute \src "libresoc.v:169849.7-169849.15"
+ attribute \src "libresoc.v:167650.7-167650.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:170985$9832
+ cell $and $and$libresoc.v:168786$9746
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$73
connect \B \p_ready_o
- connect \Y $and$libresoc.v:170985$9832_Y
+ connect \Y $and$libresoc.v:168786$9746_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171042.10-171045.4"
+ attribute \src "libresoc.v:168843.10-168846.4"
cell \n$82 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171046.15-171098.4"
+ attribute \src "libresoc.v:168847.15-168899.4"
cell \output$83 \output
connect \cr_a \output_cr_a
connect \cr_a$22 \output_cr_a$62
connect \xer_so_ok \output_xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171099.16-171151.4"
+ attribute \src "libresoc.v:168900.16-168952.4"
cell \output_stage \output_stage
connect \div_by_zero \output_stage_div_by_zero
connect \dive_abs_ov32 \output_stage_dive_abs_ov32
connect \xer_so$20 \output_stage_xer_so$40
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171152.10-171155.4"
+ attribute \src "libresoc.v:168953.10-168956.4"
cell \p$81 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:169849.7-169849.20"
- process $proc$libresoc.v:169849$9955
+ attribute \src "libresoc.v:167650.7-167650.20"
+ process $proc$libresoc.v:167650$9869
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:169858.13-169858.24"
- process $proc$libresoc.v:169858$9956
+ attribute \src "libresoc.v:167659.13-167659.24"
+ process $proc$libresoc.v:167659$9870
assign { } { }
assign $1\cr_a[3:0] 4'0000
sync always
sync init
update \cr_a $1\cr_a[3:0]
end
- attribute \src "libresoc.v:169867.7-169867.21"
- process $proc$libresoc.v:169867$9957
+ attribute \src "libresoc.v:167668.7-167668.21"
+ process $proc$libresoc.v:167668$9871
assign { } { }
assign $1\cr_a_ok[0:0] 1'0
sync always
sync init
update \cr_a_ok $1\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:169890.13-169890.45"
- process $proc$libresoc.v:169890$9958
+ attribute \src "libresoc.v:167691.13-167691.45"
+ process $proc$libresoc.v:167691$9872
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$9959 4'0000
+ assign $0\logical_op__data_len$18[3:0]$9873 4'0000
sync always
sync init
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9959
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9873
end
- attribute \src "libresoc.v:169927.14-169927.48"
- process $proc$libresoc.v:169927$9960
+ attribute \src "libresoc.v:167728.14-167728.48"
+ process $proc$libresoc.v:167728$9874
assign { } { }
- assign $0\logical_op__fn_unit$3[12:0]$9961 13'0000000000000
+ assign $0\logical_op__fn_unit$3[12:0]$9875 13'0000000000000
sync always
sync init
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9961
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9875
end
- attribute \src "libresoc.v:169950.14-169950.67"
- process $proc$libresoc.v:169950$9962
+ attribute \src "libresoc.v:167751.14-167751.67"
+ process $proc$libresoc.v:167751$9876
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$9963 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$4[63:0]$9877 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9963
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9877
end
- attribute \src "libresoc.v:169959.7-169959.42"
- process $proc$libresoc.v:169959$9964
+ attribute \src "libresoc.v:167760.7-167760.42"
+ process $proc$libresoc.v:167760$9878
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$9965 1'0
+ assign $0\logical_op__imm_data__ok$5[0:0]$9879 1'0
sync always
sync init
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9965
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9879
end
- attribute \src "libresoc.v:169976.13-169976.48"
- process $proc$libresoc.v:169976$9966
+ attribute \src "libresoc.v:167777.13-167777.48"
+ process $proc$libresoc.v:167777$9880
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$9967 2'00
+ assign $0\logical_op__input_carry$12[1:0]$9881 2'00
sync always
sync init
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9967
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9881
end
- attribute \src "libresoc.v:169989.14-169989.43"
- process $proc$libresoc.v:169989$9968
+ attribute \src "libresoc.v:167790.14-167790.43"
+ process $proc$libresoc.v:167790$9882
assign { } { }
- assign $0\logical_op__insn$19[31:0]$9969 0
+ assign $0\logical_op__insn$19[31:0]$9883 0
sync always
sync init
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9969
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9883
end
- attribute \src "libresoc.v:170146.13-170146.46"
- process $proc$libresoc.v:170146$9970
+ attribute \src "libresoc.v:167947.13-167947.46"
+ process $proc$libresoc.v:167947$9884
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$9971 7'0000000
+ assign $0\logical_op__insn_type$2[6:0]$9885 7'0000000
sync always
sync init
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9971
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9885
end
- attribute \src "libresoc.v:170229.7-170229.40"
- process $proc$libresoc.v:170229$9972
+ attribute \src "libresoc.v:168030.7-168030.40"
+ process $proc$libresoc.v:168030$9886
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$9973 1'0
+ assign $0\logical_op__invert_in$10[0:0]$9887 1'0
sync always
sync init
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9973
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9887
end
- attribute \src "libresoc.v:170238.7-170238.41"
- process $proc$libresoc.v:170238$9974
+ attribute \src "libresoc.v:168039.7-168039.41"
+ process $proc$libresoc.v:168039$9888
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$9975 1'0
+ assign $0\logical_op__invert_out$13[0:0]$9889 1'0
sync always
sync init
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9975
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9889
end
- attribute \src "libresoc.v:170247.7-170247.39"
- process $proc$libresoc.v:170247$9976
+ attribute \src "libresoc.v:168048.7-168048.39"
+ process $proc$libresoc.v:168048$9890
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$9977 1'0
+ assign $0\logical_op__is_32bit$16[0:0]$9891 1'0
sync always
sync init
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9977
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9891
end
- attribute \src "libresoc.v:170256.7-170256.40"
- process $proc$libresoc.v:170256$9978
+ attribute \src "libresoc.v:168057.7-168057.40"
+ process $proc$libresoc.v:168057$9892
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$9979 1'0
+ assign $0\logical_op__is_signed$17[0:0]$9893 1'0
sync always
sync init
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9979
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9893
end
- attribute \src "libresoc.v:170265.7-170265.36"
- process $proc$libresoc.v:170265$9980
+ attribute \src "libresoc.v:168066.7-168066.36"
+ process $proc$libresoc.v:168066$9894
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$9981 1'0
+ assign $0\logical_op__oe__oe$8[0:0]$9895 1'0
sync always
sync init
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9981
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9895
end
- attribute \src "libresoc.v:170276.7-170276.36"
- process $proc$libresoc.v:170276$9982
+ attribute \src "libresoc.v:168077.7-168077.36"
+ process $proc$libresoc.v:168077$9896
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$9983 1'0
+ assign $0\logical_op__oe__ok$9[0:0]$9897 1'0
sync always
sync init
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9983
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9897
end
- attribute \src "libresoc.v:170283.7-170283.43"
- process $proc$libresoc.v:170283$9984
+ attribute \src "libresoc.v:168084.7-168084.43"
+ process $proc$libresoc.v:168084$9898
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$9985 1'0
+ assign $0\logical_op__output_carry$15[0:0]$9899 1'0
sync always
sync init
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9985
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9899
end
- attribute \src "libresoc.v:170292.7-170292.36"
- process $proc$libresoc.v:170292$9986
+ attribute \src "libresoc.v:168093.7-168093.36"
+ process $proc$libresoc.v:168093$9900
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$9987 1'0
+ assign $0\logical_op__rc__ok$7[0:0]$9901 1'0
sync always
sync init
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9987
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9901
end
- attribute \src "libresoc.v:170301.7-170301.36"
- process $proc$libresoc.v:170301$9988
+ attribute \src "libresoc.v:168102.7-168102.36"
+ process $proc$libresoc.v:168102$9902
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$9989 1'0
+ assign $0\logical_op__rc__rc$6[0:0]$9903 1'0
sync always
sync init
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9989
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9903
end
- attribute \src "libresoc.v:170310.7-170310.40"
- process $proc$libresoc.v:170310$9990
+ attribute \src "libresoc.v:168111.7-168111.40"
+ process $proc$libresoc.v:168111$9904
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$9991 1'0
+ assign $0\logical_op__write_cr0$14[0:0]$9905 1'0
sync always
sync init
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9991
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9905
end
- attribute \src "libresoc.v:170319.7-170319.37"
- process $proc$libresoc.v:170319$9992
+ attribute \src "libresoc.v:168120.7-168120.37"
+ process $proc$libresoc.v:168120$9906
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$9993 1'0
+ assign $0\logical_op__zero_a$11[0:0]$9907 1'0
sync always
sync init
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9993
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9907
end
- attribute \src "libresoc.v:170328.13-170328.29"
- process $proc$libresoc.v:170328$9994
+ attribute \src "libresoc.v:168129.13-168129.29"
+ process $proc$libresoc.v:168129$9908
assign { } { }
- assign $0\muxid$1[1:0]$9995 2'00
+ assign $0\muxid$1[1:0]$9909 2'00
sync always
sync init
- update \muxid$1 $0\muxid$1[1:0]$9995
+ update \muxid$1 $0\muxid$1[1:0]$9909
end
- attribute \src "libresoc.v:170341.14-170341.38"
- process $proc$libresoc.v:170341$9996
+ attribute \src "libresoc.v:168142.14-168142.38"
+ process $proc$libresoc.v:168142$9910
assign { } { }
assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \o $1\o[63:0]
end
- attribute \src "libresoc.v:170348.7-170348.18"
- process $proc$libresoc.v:170348$9997
+ attribute \src "libresoc.v:168149.7-168149.18"
+ process $proc$libresoc.v:168149$9911
assign { } { }
assign $1\o_ok[0:0] 1'0
sync always
sync init
update \o_ok $1\o_ok[0:0]
end
- attribute \src "libresoc.v:170936.7-170936.20"
- process $proc$libresoc.v:170936$9998
+ attribute \src "libresoc.v:168737.7-168737.20"
+ process $proc$libresoc.v:168737$9912
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:170951.13-170951.26"
- process $proc$libresoc.v:170951$9999
+ attribute \src "libresoc.v:168752.13-168752.26"
+ process $proc$libresoc.v:168752$9913
assign { } { }
assign $1\xer_ov[1:0] 2'00
sync always
sync init
update \xer_ov $1\xer_ov[1:0]
end
- attribute \src "libresoc.v:170958.7-170958.23"
- process $proc$libresoc.v:170958$10000
+ attribute \src "libresoc.v:168759.7-168759.23"
+ process $proc$libresoc.v:168759$9914
assign { } { }
assign $1\xer_ov_ok[0:0] 1'0
sync always
sync init
update \xer_ov_ok $1\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:170971.7-170971.25"
- process $proc$libresoc.v:170971$10001
+ attribute \src "libresoc.v:168772.7-168772.25"
+ process $proc$libresoc.v:168772$9915
assign { } { }
- assign $0\xer_so$20[0:0]$10002 1'0
+ assign $0\xer_so$20[0:0]$9916 1'0
sync always
sync init
- update \xer_so$20 $0\xer_so$20[0:0]$10002
+ update \xer_so$20 $0\xer_so$20[0:0]$9916
end
- attribute \src "libresoc.v:170976.7-170976.23"
- process $proc$libresoc.v:170976$10003
+ attribute \src "libresoc.v:168777.7-168777.23"
+ process $proc$libresoc.v:168777$9917
assign { } { }
assign $1\xer_so_ok[0:0] 1'0
sync always
sync init
update \xer_so_ok $1\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:170986.3-170987.37"
- process $proc$libresoc.v:170986$9833
+ attribute \src "libresoc.v:168787.3-168788.37"
+ process $proc$libresoc.v:168787$9747
assign { } { }
- assign $0\xer_so$20[0:0]$9834 \xer_so$20$next
+ assign $0\xer_so$20[0:0]$9748 \xer_so$20$next
sync posedge \coresync_clk
- update \xer_so$20 $0\xer_so$20[0:0]$9834
+ update \xer_so$20 $0\xer_so$20[0:0]$9748
end
- attribute \src "libresoc.v:170988.3-170989.35"
- process $proc$libresoc.v:170988$9835
+ attribute \src "libresoc.v:168789.3-168790.35"
+ process $proc$libresoc.v:168789$9749
assign { } { }
assign $0\xer_so_ok[0:0] \xer_so_ok$next
sync posedge \coresync_clk
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:170990.3-170991.29"
- process $proc$libresoc.v:170990$9836
+ attribute \src "libresoc.v:168791.3-168792.29"
+ process $proc$libresoc.v:168791$9750
assign { } { }
assign $0\xer_ov[1:0] \xer_ov$next
sync posedge \coresync_clk
update \xer_ov $0\xer_ov[1:0]
end
- attribute \src "libresoc.v:170992.3-170993.35"
- process $proc$libresoc.v:170992$9837
+ attribute \src "libresoc.v:168793.3-168794.35"
+ process $proc$libresoc.v:168793$9751
assign { } { }
assign $0\xer_ov_ok[0:0] \xer_ov_ok$next
sync posedge \coresync_clk
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:170994.3-170995.25"
- process $proc$libresoc.v:170994$9838
+ attribute \src "libresoc.v:168795.3-168796.25"
+ process $proc$libresoc.v:168795$9752
assign { } { }
assign $0\cr_a[3:0] \cr_a$next
sync posedge \coresync_clk
update \cr_a $0\cr_a[3:0]
end
- attribute \src "libresoc.v:170996.3-170997.31"
- process $proc$libresoc.v:170996$9839
+ attribute \src "libresoc.v:168797.3-168798.31"
+ process $proc$libresoc.v:168797$9753
assign { } { }
assign $0\cr_a_ok[0:0] \cr_a_ok$next
sync posedge \coresync_clk
update \cr_a_ok $0\cr_a_ok[0:0]
end
- attribute \src "libresoc.v:170998.3-170999.19"
- process $proc$libresoc.v:170998$9840
+ attribute \src "libresoc.v:168799.3-168800.19"
+ process $proc$libresoc.v:168799$9754
assign { } { }
assign $0\o[63:0] \o$next
sync posedge \coresync_clk
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:171000.3-171001.25"
- process $proc$libresoc.v:171000$9841
+ attribute \src "libresoc.v:168801.3-168802.25"
+ process $proc$libresoc.v:168801$9755
assign { } { }
assign $0\o_ok[0:0] \o_ok$next
sync posedge \coresync_clk
update \o_ok $0\o_ok[0:0]
end
- attribute \src "libresoc.v:171002.3-171003.65"
- process $proc$libresoc.v:171002$9842
+ attribute \src "libresoc.v:168803.3-168804.65"
+ process $proc$libresoc.v:168803$9756
assign { } { }
- assign $0\logical_op__insn_type$2[6:0]$9843 \logical_op__insn_type$2$next
+ assign $0\logical_op__insn_type$2[6:0]$9757 \logical_op__insn_type$2$next
sync posedge \coresync_clk
- update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9843
+ update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9757
end
- attribute \src "libresoc.v:171004.3-171005.61"
- process $proc$libresoc.v:171004$9844
+ attribute \src "libresoc.v:168805.3-168806.61"
+ process $proc$libresoc.v:168805$9758
assign { } { }
- assign $0\logical_op__fn_unit$3[12:0]$9845 \logical_op__fn_unit$3$next
+ assign $0\logical_op__fn_unit$3[12:0]$9759 \logical_op__fn_unit$3$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9845
+ update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9759
end
- attribute \src "libresoc.v:171006.3-171007.75"
- process $proc$libresoc.v:171006$9846
+ attribute \src "libresoc.v:168807.3-168808.75"
+ process $proc$libresoc.v:168807$9760
assign { } { }
- assign $0\logical_op__imm_data__data$4[63:0]$9847 \logical_op__imm_data__data$4$next
+ assign $0\logical_op__imm_data__data$4[63:0]$9761 \logical_op__imm_data__data$4$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9847
+ update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9761
end
- attribute \src "libresoc.v:171008.3-171009.71"
- process $proc$libresoc.v:171008$9848
+ attribute \src "libresoc.v:168809.3-168810.71"
+ process $proc$libresoc.v:168809$9762
assign { } { }
- assign $0\logical_op__imm_data__ok$5[0:0]$9849 \logical_op__imm_data__ok$5$next
+ assign $0\logical_op__imm_data__ok$5[0:0]$9763 \logical_op__imm_data__ok$5$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9849
+ update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9763
end
- attribute \src "libresoc.v:171010.3-171011.59"
- process $proc$libresoc.v:171010$9850
+ attribute \src "libresoc.v:168811.3-168812.59"
+ process $proc$libresoc.v:168811$9764
assign { } { }
- assign $0\logical_op__rc__rc$6[0:0]$9851 \logical_op__rc__rc$6$next
+ assign $0\logical_op__rc__rc$6[0:0]$9765 \logical_op__rc__rc$6$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9851
+ update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9765
end
- attribute \src "libresoc.v:171012.3-171013.59"
- process $proc$libresoc.v:171012$9852
+ attribute \src "libresoc.v:168813.3-168814.59"
+ process $proc$libresoc.v:168813$9766
assign { } { }
- assign $0\logical_op__rc__ok$7[0:0]$9853 \logical_op__rc__ok$7$next
+ assign $0\logical_op__rc__ok$7[0:0]$9767 \logical_op__rc__ok$7$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9853
+ update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9767
end
- attribute \src "libresoc.v:171014.3-171015.59"
- process $proc$libresoc.v:171014$9854
+ attribute \src "libresoc.v:168815.3-168816.59"
+ process $proc$libresoc.v:168815$9768
assign { } { }
- assign $0\logical_op__oe__oe$8[0:0]$9855 \logical_op__oe__oe$8$next
+ assign $0\logical_op__oe__oe$8[0:0]$9769 \logical_op__oe__oe$8$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9855
+ update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9769
end
- attribute \src "libresoc.v:171016.3-171017.59"
- process $proc$libresoc.v:171016$9856
+ attribute \src "libresoc.v:168817.3-168818.59"
+ process $proc$libresoc.v:168817$9770
assign { } { }
- assign $0\logical_op__oe__ok$9[0:0]$9857 \logical_op__oe__ok$9$next
+ assign $0\logical_op__oe__ok$9[0:0]$9771 \logical_op__oe__ok$9$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9857
+ update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9771
end
- attribute \src "libresoc.v:171018.3-171019.67"
- process $proc$libresoc.v:171018$9858
+ attribute \src "libresoc.v:168819.3-168820.67"
+ process $proc$libresoc.v:168819$9772
assign { } { }
- assign $0\logical_op__invert_in$10[0:0]$9859 \logical_op__invert_in$10$next
+ assign $0\logical_op__invert_in$10[0:0]$9773 \logical_op__invert_in$10$next
sync posedge \coresync_clk
- update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9859
+ update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9773
end
- attribute \src "libresoc.v:171020.3-171021.61"
- process $proc$libresoc.v:171020$9860
+ attribute \src "libresoc.v:168821.3-168822.61"
+ process $proc$libresoc.v:168821$9774
assign { } { }
- assign $0\logical_op__zero_a$11[0:0]$9861 \logical_op__zero_a$11$next
+ assign $0\logical_op__zero_a$11[0:0]$9775 \logical_op__zero_a$11$next
sync posedge \coresync_clk
- update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9861
+ update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9775
end
- attribute \src "libresoc.v:171022.3-171023.71"
- process $proc$libresoc.v:171022$9862
+ attribute \src "libresoc.v:168823.3-168824.71"
+ process $proc$libresoc.v:168823$9776
assign { } { }
- assign $0\logical_op__input_carry$12[1:0]$9863 \logical_op__input_carry$12$next
+ assign $0\logical_op__input_carry$12[1:0]$9777 \logical_op__input_carry$12$next
sync posedge \coresync_clk
- update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9863
+ update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9777
end
- attribute \src "libresoc.v:171024.3-171025.69"
- process $proc$libresoc.v:171024$9864
+ attribute \src "libresoc.v:168825.3-168826.69"
+ process $proc$libresoc.v:168825$9778
assign { } { }
- assign $0\logical_op__invert_out$13[0:0]$9865 \logical_op__invert_out$13$next
+ assign $0\logical_op__invert_out$13[0:0]$9779 \logical_op__invert_out$13$next
sync posedge \coresync_clk
- update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9865
+ update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9779
end
- attribute \src "libresoc.v:171026.3-171027.67"
- process $proc$libresoc.v:171026$9866
+ attribute \src "libresoc.v:168827.3-168828.67"
+ process $proc$libresoc.v:168827$9780
assign { } { }
- assign $0\logical_op__write_cr0$14[0:0]$9867 \logical_op__write_cr0$14$next
+ assign $0\logical_op__write_cr0$14[0:0]$9781 \logical_op__write_cr0$14$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9867
+ update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9781
end
- attribute \src "libresoc.v:171028.3-171029.73"
- process $proc$libresoc.v:171028$9868
+ attribute \src "libresoc.v:168829.3-168830.73"
+ process $proc$libresoc.v:168829$9782
assign { } { }
- assign $0\logical_op__output_carry$15[0:0]$9869 \logical_op__output_carry$15$next
+ assign $0\logical_op__output_carry$15[0:0]$9783 \logical_op__output_carry$15$next
sync posedge \coresync_clk
- update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9869
+ update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9783
end
- attribute \src "libresoc.v:171030.3-171031.65"
- process $proc$libresoc.v:171030$9870
+ attribute \src "libresoc.v:168831.3-168832.65"
+ process $proc$libresoc.v:168831$9784
assign { } { }
- assign $0\logical_op__is_32bit$16[0:0]$9871 \logical_op__is_32bit$16$next
+ assign $0\logical_op__is_32bit$16[0:0]$9785 \logical_op__is_32bit$16$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9871
+ update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9785
end
- attribute \src "libresoc.v:171032.3-171033.67"
- process $proc$libresoc.v:171032$9872
+ attribute \src "libresoc.v:168833.3-168834.67"
+ process $proc$libresoc.v:168833$9786
assign { } { }
- assign $0\logical_op__is_signed$17[0:0]$9873 \logical_op__is_signed$17$next
+ assign $0\logical_op__is_signed$17[0:0]$9787 \logical_op__is_signed$17$next
sync posedge \coresync_clk
- update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9873
+ update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9787
end
- attribute \src "libresoc.v:171034.3-171035.65"
- process $proc$libresoc.v:171034$9874
+ attribute \src "libresoc.v:168835.3-168836.65"
+ process $proc$libresoc.v:168835$9788
assign { } { }
- assign $0\logical_op__data_len$18[3:0]$9875 \logical_op__data_len$18$next
+ assign $0\logical_op__data_len$18[3:0]$9789 \logical_op__data_len$18$next
sync posedge \coresync_clk
- update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9875
+ update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9789
end
- attribute \src "libresoc.v:171036.3-171037.57"
- process $proc$libresoc.v:171036$9876
+ attribute \src "libresoc.v:168837.3-168838.57"
+ process $proc$libresoc.v:168837$9790
assign { } { }
- assign $0\logical_op__insn$19[31:0]$9877 \logical_op__insn$19$next
+ assign $0\logical_op__insn$19[31:0]$9791 \logical_op__insn$19$next
sync posedge \coresync_clk
- update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9877
+ update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9791
end
- attribute \src "libresoc.v:171038.3-171039.33"
- process $proc$libresoc.v:171038$9878
+ attribute \src "libresoc.v:168839.3-168840.33"
+ process $proc$libresoc.v:168839$9792
assign { } { }
- assign $0\muxid$1[1:0]$9879 \muxid$1$next
+ assign $0\muxid$1[1:0]$9793 \muxid$1$next
sync posedge \coresync_clk
- update \muxid$1 $0\muxid$1[1:0]$9879
+ update \muxid$1 $0\muxid$1[1:0]$9793
end
- attribute \src "libresoc.v:171040.3-171041.29"
- process $proc$libresoc.v:171040$9880
+ attribute \src "libresoc.v:168841.3-168842.29"
+ process $proc$libresoc.v:168841$9794
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:171156.3-171174.6"
- process $proc$libresoc.v:171156$9881
+ attribute \src "libresoc.v:168957.3-168975.6"
+ process $proc$libresoc.v:168957$9795
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\o$next[63:0]$9882 $1\o$next[63:0]$9884
+ assign $0\o$next[63:0]$9796 $1\o$next[63:0]$9798
assign { } { }
- assign $0\o_ok$next[0:0]$9883 $2\o_ok$next[0:0]$9886
- attribute \src "libresoc.v:171157.5-171157.29"
+ assign $0\o_ok$next[0:0]$9797 $2\o_ok$next[0:0]$9800
+ attribute \src "libresoc.v:168958.5-168958.29"
switch \initial
- attribute \src "libresoc.v:171157.9-171157.17"
+ attribute \src "libresoc.v:168958.9-168958.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9885 $1\o$next[63:0]$9884 } { \o_ok$96 \o$95 }
+ assign { $1\o_ok$next[0:0]$9799 $1\o$next[63:0]$9798 } { \o_ok$96 \o$95 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\o_ok$next[0:0]$9885 $1\o$next[63:0]$9884 } { \o_ok$96 \o$95 }
+ assign { $1\o_ok$next[0:0]$9799 $1\o$next[63:0]$9798 } { \o_ok$96 \o$95 }
case
- assign $1\o$next[63:0]$9884 \o
- assign $1\o_ok$next[0:0]$9885 \o_ok
+ assign $1\o$next[63:0]$9798 \o
+ assign $1\o_ok$next[0:0]$9799 \o_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\o_ok$next[0:0]$9886 1'0
+ assign $2\o_ok$next[0:0]$9800 1'0
case
- assign $2\o_ok$next[0:0]$9886 $1\o_ok$next[0:0]$9885
+ assign $2\o_ok$next[0:0]$9800 $1\o_ok$next[0:0]$9799
end
sync always
- update \o$next $0\o$next[63:0]$9882
- update \o_ok$next $0\o_ok$next[0:0]$9883
+ update \o$next $0\o$next[63:0]$9796
+ update \o_ok$next $0\o_ok$next[0:0]$9797
end
- attribute \src "libresoc.v:171175.3-171193.6"
- process $proc$libresoc.v:171175$9887
+ attribute \src "libresoc.v:168976.3-168994.6"
+ process $proc$libresoc.v:168976$9801
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cr_a$next[3:0]$9888 $1\cr_a$next[3:0]$9890
+ assign $0\cr_a$next[3:0]$9802 $1\cr_a$next[3:0]$9804
assign { } { }
- assign $0\cr_a_ok$next[0:0]$9889 $2\cr_a_ok$next[0:0]$9892
- attribute \src "libresoc.v:171176.5-171176.29"
+ assign $0\cr_a_ok$next[0:0]$9803 $2\cr_a_ok$next[0:0]$9806
+ attribute \src "libresoc.v:168977.5-168977.29"
switch \initial
- attribute \src "libresoc.v:171176.9-171176.17"
+ attribute \src "libresoc.v:168977.9-168977.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9891 $1\cr_a$next[3:0]$9890 } { \cr_a_ok$98 \cr_a$97 }
+ assign { $1\cr_a_ok$next[0:0]$9805 $1\cr_a$next[3:0]$9804 } { \cr_a_ok$98 \cr_a$97 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\cr_a_ok$next[0:0]$9891 $1\cr_a$next[3:0]$9890 } { \cr_a_ok$98 \cr_a$97 }
+ assign { $1\cr_a_ok$next[0:0]$9805 $1\cr_a$next[3:0]$9804 } { \cr_a_ok$98 \cr_a$97 }
case
- assign $1\cr_a$next[3:0]$9890 \cr_a
- assign $1\cr_a_ok$next[0:0]$9891 \cr_a_ok
+ assign $1\cr_a$next[3:0]$9804 \cr_a
+ assign $1\cr_a_ok$next[0:0]$9805 \cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cr_a_ok$next[0:0]$9892 1'0
+ assign $2\cr_a_ok$next[0:0]$9806 1'0
case
- assign $2\cr_a_ok$next[0:0]$9892 $1\cr_a_ok$next[0:0]$9891
+ assign $2\cr_a_ok$next[0:0]$9806 $1\cr_a_ok$next[0:0]$9805
end
sync always
- update \cr_a$next $0\cr_a$next[3:0]$9888
- update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9889
+ update \cr_a$next $0\cr_a$next[3:0]$9802
+ update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9803
end
- attribute \src "libresoc.v:171194.3-171212.6"
- process $proc$libresoc.v:171194$9893
+ attribute \src "libresoc.v:168995.3-169013.6"
+ process $proc$libresoc.v:168995$9807
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_ov$next[1:0]$9894 $1\xer_ov$next[1:0]$9896
+ assign $0\xer_ov$next[1:0]$9808 $1\xer_ov$next[1:0]$9810
assign { } { }
- assign $0\xer_ov_ok$next[0:0]$9895 $2\xer_ov_ok$next[0:0]$9898
- attribute \src "libresoc.v:171195.5-171195.29"
+ assign $0\xer_ov_ok$next[0:0]$9809 $2\xer_ov_ok$next[0:0]$9812
+ attribute \src "libresoc.v:168996.5-168996.29"
switch \initial
- attribute \src "libresoc.v:171195.9-171195.17"
+ attribute \src "libresoc.v:168996.9-168996.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9897 $1\xer_ov$next[1:0]$9896 } { \xer_ov_ok$100 \xer_ov$99 }
+ assign { $1\xer_ov_ok$next[0:0]$9811 $1\xer_ov$next[1:0]$9810 } { \xer_ov_ok$100 \xer_ov$99 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_ov_ok$next[0:0]$9897 $1\xer_ov$next[1:0]$9896 } { \xer_ov_ok$100 \xer_ov$99 }
+ assign { $1\xer_ov_ok$next[0:0]$9811 $1\xer_ov$next[1:0]$9810 } { \xer_ov_ok$100 \xer_ov$99 }
case
- assign $1\xer_ov$next[1:0]$9896 \xer_ov
- assign $1\xer_ov_ok$next[0:0]$9897 \xer_ov_ok
+ assign $1\xer_ov$next[1:0]$9810 \xer_ov
+ assign $1\xer_ov_ok$next[0:0]$9811 \xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_ov_ok$next[0:0]$9898 1'0
+ assign $2\xer_ov_ok$next[0:0]$9812 1'0
case
- assign $2\xer_ov_ok$next[0:0]$9898 $1\xer_ov_ok$next[0:0]$9897
+ assign $2\xer_ov_ok$next[0:0]$9812 $1\xer_ov_ok$next[0:0]$9811
end
sync always
- update \xer_ov$next $0\xer_ov$next[1:0]$9894
- update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9895
+ update \xer_ov$next $0\xer_ov$next[1:0]$9808
+ update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9809
end
- attribute \src "libresoc.v:171213.3-171231.6"
- process $proc$libresoc.v:171213$9899
+ attribute \src "libresoc.v:169014.3-169032.6"
+ process $proc$libresoc.v:169014$9813
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xer_so$20$next[0:0]$9901 $1\xer_so$20$next[0:0]$9903
- assign $0\xer_so_ok$next[0:0]$9900 $2\xer_so_ok$next[0:0]$9904
- attribute \src "libresoc.v:171214.5-171214.29"
+ assign $0\xer_so$20$next[0:0]$9815 $1\xer_so$20$next[0:0]$9817
+ assign $0\xer_so_ok$next[0:0]$9814 $2\xer_so_ok$next[0:0]$9818
+ attribute \src "libresoc.v:169015.5-169015.29"
switch \initial
- attribute \src "libresoc.v:171214.9-171214.17"
+ attribute \src "libresoc.v:169015.9-169015.17"
case 1'1
case
end
case 2'-1
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9902 $1\xer_so$20$next[0:0]$9903 } { \xer_so_ok$102 \xer_so$101 }
+ assign { $1\xer_so_ok$next[0:0]$9816 $1\xer_so$20$next[0:0]$9817 } { \xer_so_ok$102 \xer_so$101 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
- assign { $1\xer_so_ok$next[0:0]$9902 $1\xer_so$20$next[0:0]$9903 } { \xer_so_ok$102 \xer_so$101 }
+ assign { $1\xer_so_ok$next[0:0]$9816 $1\xer_so$20$next[0:0]$9817 } { \xer_so_ok$102 \xer_so$101 }
case
- assign $1\xer_so_ok$next[0:0]$9902 \xer_so_ok
- assign $1\xer_so$20$next[0:0]$9903 \xer_so$20
+ assign $1\xer_so_ok$next[0:0]$9816 \xer_so_ok
+ assign $1\xer_so$20$next[0:0]$9817 \xer_so$20
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so_ok$next[0:0]$9904 1'0
+ assign $2\xer_so_ok$next[0:0]$9818 1'0
case
- assign $2\xer_so_ok$next[0:0]$9904 $1\xer_so_ok$next[0:0]$9902
+ assign $2\xer_so_ok$next[0:0]$9818 $1\xer_so_ok$next[0:0]$9816
end
sync always
- update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9900
- update \xer_so$20$next $0\xer_so$20$next[0:0]$9901
+ update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9814
+ update \xer_so$20$next $0\xer_so$20$next[0:0]$9815
end
- attribute \src "libresoc.v:171232.3-171249.6"
- process $proc$libresoc.v:171232$9905
+ attribute \src "libresoc.v:169033.3-169050.6"
+ process $proc$libresoc.v:169033$9819
assign { } { }
assign { } { }
assign { } { }
- assign $0\r_busy$next[0:0]$9906 $2\r_busy$next[0:0]$9908
- attribute \src "libresoc.v:171233.5-171233.29"
+ assign $0\r_busy$next[0:0]$9820 $2\r_busy$next[0:0]$9822
+ attribute \src "libresoc.v:169034.5-169034.29"
switch \initial
- attribute \src "libresoc.v:171233.9-171233.17"
+ attribute \src "libresoc.v:169034.9-169034.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$9907 1'1
+ assign $1\r_busy$next[0:0]$9821 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$9907 1'0
+ assign $1\r_busy$next[0:0]$9821 1'0
case
- assign $1\r_busy$next[0:0]$9907 \r_busy
+ assign $1\r_busy$next[0:0]$9821 \r_busy
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r_busy$next[0:0]$9908 1'0
+ assign $2\r_busy$next[0:0]$9822 1'0
case
- assign $2\r_busy$next[0:0]$9908 $1\r_busy$next[0:0]$9907
+ assign $2\r_busy$next[0:0]$9822 $1\r_busy$next[0:0]$9821
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$9906
+ update \r_busy$next $0\r_busy$next[0:0]$9820
end
- attribute \src "libresoc.v:171250.3-171262.6"
- process $proc$libresoc.v:171250$9909
+ attribute \src "libresoc.v:169051.3-169063.6"
+ process $proc$libresoc.v:169051$9823
assign { } { }
assign { } { }
- assign $0\muxid$1$next[1:0]$9910 $1\muxid$1$next[1:0]$9911
- attribute \src "libresoc.v:171251.5-171251.29"
+ assign $0\muxid$1$next[1:0]$9824 $1\muxid$1$next[1:0]$9825
+ attribute \src "libresoc.v:169052.5-169052.29"
switch \initial
- attribute \src "libresoc.v:171251.9-171251.17"
+ attribute \src "libresoc.v:169052.9-169052.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$1$next[1:0]$9911 \muxid$76
+ assign $1\muxid$1$next[1:0]$9825 \muxid$76
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$1$next[1:0]$9911 \muxid$76
+ assign $1\muxid$1$next[1:0]$9825 \muxid$76
case
- assign $1\muxid$1$next[1:0]$9911 \muxid$1
+ assign $1\muxid$1$next[1:0]$9825 \muxid$1
end
sync always
- update \muxid$1$next $0\muxid$1$next[1:0]$9910
+ update \muxid$1$next $0\muxid$1$next[1:0]$9824
end
- attribute \src "libresoc.v:171263.3-171304.6"
- process $proc$libresoc.v:171263$9912
+ attribute \src "libresoc.v:169064.3-169105.6"
+ process $proc$libresoc.v:169064$9826
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$18$next[3:0]$9913 $1\logical_op__data_len$18$next[3:0]$9931
- assign $0\logical_op__fn_unit$3$next[12:0]$9914 $1\logical_op__fn_unit$3$next[12:0]$9932
+ assign $0\logical_op__data_len$18$next[3:0]$9827 $1\logical_op__data_len$18$next[3:0]$9845
+ assign $0\logical_op__fn_unit$3$next[12:0]$9828 $1\logical_op__fn_unit$3$next[12:0]$9846
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$12$next[1:0]$9917 $1\logical_op__input_carry$12$next[1:0]$9935
- assign $0\logical_op__insn$19$next[31:0]$9918 $1\logical_op__insn$19$next[31:0]$9936
- assign $0\logical_op__insn_type$2$next[6:0]$9919 $1\logical_op__insn_type$2$next[6:0]$9937
- assign $0\logical_op__invert_in$10$next[0:0]$9920 $1\logical_op__invert_in$10$next[0:0]$9938
- assign $0\logical_op__invert_out$13$next[0:0]$9921 $1\logical_op__invert_out$13$next[0:0]$9939
- assign $0\logical_op__is_32bit$16$next[0:0]$9922 $1\logical_op__is_32bit$16$next[0:0]$9940
- assign $0\logical_op__is_signed$17$next[0:0]$9923 $1\logical_op__is_signed$17$next[0:0]$9941
+ assign $0\logical_op__input_carry$12$next[1:0]$9831 $1\logical_op__input_carry$12$next[1:0]$9849
+ assign $0\logical_op__insn$19$next[31:0]$9832 $1\logical_op__insn$19$next[31:0]$9850
+ assign $0\logical_op__insn_type$2$next[6:0]$9833 $1\logical_op__insn_type$2$next[6:0]$9851
+ assign $0\logical_op__invert_in$10$next[0:0]$9834 $1\logical_op__invert_in$10$next[0:0]$9852
+ assign $0\logical_op__invert_out$13$next[0:0]$9835 $1\logical_op__invert_out$13$next[0:0]$9853
+ assign $0\logical_op__is_32bit$16$next[0:0]$9836 $1\logical_op__is_32bit$16$next[0:0]$9854
+ assign $0\logical_op__is_signed$17$next[0:0]$9837 $1\logical_op__is_signed$17$next[0:0]$9855
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$15$next[0:0]$9926 $1\logical_op__output_carry$15$next[0:0]$9944
+ assign $0\logical_op__output_carry$15$next[0:0]$9840 $1\logical_op__output_carry$15$next[0:0]$9858
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$14$next[0:0]$9929 $1\logical_op__write_cr0$14$next[0:0]$9947
- assign $0\logical_op__zero_a$11$next[0:0]$9930 $1\logical_op__zero_a$11$next[0:0]$9948
- assign $0\logical_op__imm_data__data$4$next[63:0]$9915 $2\logical_op__imm_data__data$4$next[63:0]$9949
- assign $0\logical_op__imm_data__ok$5$next[0:0]$9916 $2\logical_op__imm_data__ok$5$next[0:0]$9950
- assign $0\logical_op__oe__oe$8$next[0:0]$9924 $2\logical_op__oe__oe$8$next[0:0]$9951
- assign $0\logical_op__oe__ok$9$next[0:0]$9925 $2\logical_op__oe__ok$9$next[0:0]$9952
- assign $0\logical_op__rc__ok$7$next[0:0]$9927 $2\logical_op__rc__ok$7$next[0:0]$9953
- assign $0\logical_op__rc__rc$6$next[0:0]$9928 $2\logical_op__rc__rc$6$next[0:0]$9954
- attribute \src "libresoc.v:171264.5-171264.29"
+ assign $0\logical_op__write_cr0$14$next[0:0]$9843 $1\logical_op__write_cr0$14$next[0:0]$9861
+ assign $0\logical_op__zero_a$11$next[0:0]$9844 $1\logical_op__zero_a$11$next[0:0]$9862
+ assign $0\logical_op__imm_data__data$4$next[63:0]$9829 $2\logical_op__imm_data__data$4$next[63:0]$9863
+ assign $0\logical_op__imm_data__ok$5$next[0:0]$9830 $2\logical_op__imm_data__ok$5$next[0:0]$9864
+ assign $0\logical_op__oe__oe$8$next[0:0]$9838 $2\logical_op__oe__oe$8$next[0:0]$9865
+ assign $0\logical_op__oe__ok$9$next[0:0]$9839 $2\logical_op__oe__ok$9$next[0:0]$9866
+ assign $0\logical_op__rc__ok$7$next[0:0]$9841 $2\logical_op__rc__ok$7$next[0:0]$9867
+ assign $0\logical_op__rc__rc$6$next[0:0]$9842 $2\logical_op__rc__rc$6$next[0:0]$9868
+ attribute \src "libresoc.v:169065.5-169065.29"
switch \initial
- attribute \src "libresoc.v:171264.9-171264.17"
+ attribute \src "libresoc.v:169065.9-169065.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$9936 $1\logical_op__data_len$18$next[3:0]$9931 $1\logical_op__is_signed$17$next[0:0]$9941 $1\logical_op__is_32bit$16$next[0:0]$9940 $1\logical_op__output_carry$15$next[0:0]$9944 $1\logical_op__write_cr0$14$next[0:0]$9947 $1\logical_op__invert_out$13$next[0:0]$9939 $1\logical_op__input_carry$12$next[1:0]$9935 $1\logical_op__zero_a$11$next[0:0]$9948 $1\logical_op__invert_in$10$next[0:0]$9938 $1\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__rc__ok$7$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9946 $1\logical_op__imm_data__ok$5$next[0:0]$9934 $1\logical_op__imm_data__data$4$next[63:0]$9933 $1\logical_op__fn_unit$3$next[12:0]$9932 $1\logical_op__insn_type$2$next[6:0]$9937 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+ assign { $1\logical_op__insn$19$next[31:0]$9850 $1\logical_op__data_len$18$next[3:0]$9845 $1\logical_op__is_signed$17$next[0:0]$9855 $1\logical_op__is_32bit$16$next[0:0]$9854 $1\logical_op__output_carry$15$next[0:0]$9858 $1\logical_op__write_cr0$14$next[0:0]$9861 $1\logical_op__invert_out$13$next[0:0]$9853 $1\logical_op__input_carry$12$next[1:0]$9849 $1\logical_op__zero_a$11$next[0:0]$9862 $1\logical_op__invert_in$10$next[0:0]$9852 $1\logical_op__oe__ok$9$next[0:0]$9857 $1\logical_op__oe__oe$8$next[0:0]$9856 $1\logical_op__rc__ok$7$next[0:0]$9859 $1\logical_op__rc__rc$6$next[0:0]$9860 $1\logical_op__imm_data__ok$5$next[0:0]$9848 $1\logical_op__imm_data__data$4$next[63:0]$9847 $1\logical_op__fn_unit$3$next[12:0]$9846 $1\logical_op__insn_type$2$next[6:0]$9851 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\logical_op__insn$19$next[31:0]$9936 $1\logical_op__data_len$18$next[3:0]$9931 $1\logical_op__is_signed$17$next[0:0]$9941 $1\logical_op__is_32bit$16$next[0:0]$9940 $1\logical_op__output_carry$15$next[0:0]$9944 $1\logical_op__write_cr0$14$next[0:0]$9947 $1\logical_op__invert_out$13$next[0:0]$9939 $1\logical_op__input_carry$12$next[1:0]$9935 $1\logical_op__zero_a$11$next[0:0]$9948 $1\logical_op__invert_in$10$next[0:0]$9938 $1\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__rc__ok$7$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9946 $1\logical_op__imm_data__ok$5$next[0:0]$9934 $1\logical_op__imm_data__data$4$next[63:0]$9933 $1\logical_op__fn_unit$3$next[12:0]$9932 $1\logical_op__insn_type$2$next[6:0]$9937 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+ assign { $1\logical_op__insn$19$next[31:0]$9850 $1\logical_op__data_len$18$next[3:0]$9845 $1\logical_op__is_signed$17$next[0:0]$9855 $1\logical_op__is_32bit$16$next[0:0]$9854 $1\logical_op__output_carry$15$next[0:0]$9858 $1\logical_op__write_cr0$14$next[0:0]$9861 $1\logical_op__invert_out$13$next[0:0]$9853 $1\logical_op__input_carry$12$next[1:0]$9849 $1\logical_op__zero_a$11$next[0:0]$9862 $1\logical_op__invert_in$10$next[0:0]$9852 $1\logical_op__oe__ok$9$next[0:0]$9857 $1\logical_op__oe__oe$8$next[0:0]$9856 $1\logical_op__rc__ok$7$next[0:0]$9859 $1\logical_op__rc__rc$6$next[0:0]$9860 $1\logical_op__imm_data__ok$5$next[0:0]$9848 $1\logical_op__imm_data__data$4$next[63:0]$9847 $1\logical_op__fn_unit$3$next[12:0]$9846 $1\logical_op__insn_type$2$next[6:0]$9851 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 }
case
- assign $1\logical_op__data_len$18$next[3:0]$9931 \logical_op__data_len$18
- assign $1\logical_op__fn_unit$3$next[12:0]$9932 \logical_op__fn_unit$3
- assign $1\logical_op__imm_data__data$4$next[63:0]$9933 \logical_op__imm_data__data$4
- assign $1\logical_op__imm_data__ok$5$next[0:0]$9934 \logical_op__imm_data__ok$5
- assign $1\logical_op__input_carry$12$next[1:0]$9935 \logical_op__input_carry$12
- assign $1\logical_op__insn$19$next[31:0]$9936 \logical_op__insn$19
- assign $1\logical_op__insn_type$2$next[6:0]$9937 \logical_op__insn_type$2
- assign $1\logical_op__invert_in$10$next[0:0]$9938 \logical_op__invert_in$10
- assign $1\logical_op__invert_out$13$next[0:0]$9939 \logical_op__invert_out$13
- assign $1\logical_op__is_32bit$16$next[0:0]$9940 \logical_op__is_32bit$16
- assign $1\logical_op__is_signed$17$next[0:0]$9941 \logical_op__is_signed$17
- assign $1\logical_op__oe__oe$8$next[0:0]$9942 \logical_op__oe__oe$8
- assign $1\logical_op__oe__ok$9$next[0:0]$9943 \logical_op__oe__ok$9
- assign $1\logical_op__output_carry$15$next[0:0]$9944 \logical_op__output_carry$15
- assign $1\logical_op__rc__ok$7$next[0:0]$9945 \logical_op__rc__ok$7
- assign $1\logical_op__rc__rc$6$next[0:0]$9946 \logical_op__rc__rc$6
- assign $1\logical_op__write_cr0$14$next[0:0]$9947 \logical_op__write_cr0$14
- assign $1\logical_op__zero_a$11$next[0:0]$9948 \logical_op__zero_a$11
+ assign $1\logical_op__data_len$18$next[3:0]$9845 \logical_op__data_len$18
+ assign $1\logical_op__fn_unit$3$next[12:0]$9846 \logical_op__fn_unit$3
+ assign $1\logical_op__imm_data__data$4$next[63:0]$9847 \logical_op__imm_data__data$4
+ assign $1\logical_op__imm_data__ok$5$next[0:0]$9848 \logical_op__imm_data__ok$5
+ assign $1\logical_op__input_carry$12$next[1:0]$9849 \logical_op__input_carry$12
+ assign $1\logical_op__insn$19$next[31:0]$9850 \logical_op__insn$19
+ assign $1\logical_op__insn_type$2$next[6:0]$9851 \logical_op__insn_type$2
+ assign $1\logical_op__invert_in$10$next[0:0]$9852 \logical_op__invert_in$10
+ assign $1\logical_op__invert_out$13$next[0:0]$9853 \logical_op__invert_out$13
+ assign $1\logical_op__is_32bit$16$next[0:0]$9854 \logical_op__is_32bit$16
+ assign $1\logical_op__is_signed$17$next[0:0]$9855 \logical_op__is_signed$17
+ assign $1\logical_op__oe__oe$8$next[0:0]$9856 \logical_op__oe__oe$8
+ assign $1\logical_op__oe__ok$9$next[0:0]$9857 \logical_op__oe__ok$9
+ assign $1\logical_op__output_carry$15$next[0:0]$9858 \logical_op__output_carry$15
+ assign $1\logical_op__rc__ok$7$next[0:0]$9859 \logical_op__rc__ok$7
+ assign $1\logical_op__rc__rc$6$next[0:0]$9860 \logical_op__rc__rc$6
+ assign $1\logical_op__write_cr0$14$next[0:0]$9861 \logical_op__write_cr0$14
+ assign $1\logical_op__zero_a$11$next[0:0]$9862 \logical_op__zero_a$11
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\logical_op__imm_data__data$4$next[63:0]$9949 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$5$next[0:0]$9950 1'0
- assign $2\logical_op__rc__rc$6$next[0:0]$9954 1'0
- assign $2\logical_op__rc__ok$7$next[0:0]$9953 1'0
- assign $2\logical_op__oe__oe$8$next[0:0]$9951 1'0
- assign $2\logical_op__oe__ok$9$next[0:0]$9952 1'0
+ assign $2\logical_op__imm_data__data$4$next[63:0]$9863 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$9864 1'0
+ assign $2\logical_op__rc__rc$6$next[0:0]$9868 1'0
+ assign $2\logical_op__rc__ok$7$next[0:0]$9867 1'0
+ assign $2\logical_op__oe__oe$8$next[0:0]$9865 1'0
+ assign $2\logical_op__oe__ok$9$next[0:0]$9866 1'0
case
- assign $2\logical_op__imm_data__data$4$next[63:0]$9949 $1\logical_op__imm_data__data$4$next[63:0]$9933
- assign $2\logical_op__imm_data__ok$5$next[0:0]$9950 $1\logical_op__imm_data__ok$5$next[0:0]$9934
- assign $2\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__oe__oe$8$next[0:0]$9942
- assign $2\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__ok$9$next[0:0]$9943
- assign $2\logical_op__rc__ok$7$next[0:0]$9953 $1\logical_op__rc__ok$7$next[0:0]$9945
- assign $2\logical_op__rc__rc$6$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9946
+ assign $2\logical_op__imm_data__data$4$next[63:0]$9863 $1\logical_op__imm_data__data$4$next[63:0]$9847
+ assign $2\logical_op__imm_data__ok$5$next[0:0]$9864 $1\logical_op__imm_data__ok$5$next[0:0]$9848
+ assign $2\logical_op__oe__oe$8$next[0:0]$9865 $1\logical_op__oe__oe$8$next[0:0]$9856
+ assign $2\logical_op__oe__ok$9$next[0:0]$9866 $1\logical_op__oe__ok$9$next[0:0]$9857
+ assign $2\logical_op__rc__ok$7$next[0:0]$9867 $1\logical_op__rc__ok$7$next[0:0]$9859
+ assign $2\logical_op__rc__rc$6$next[0:0]$9868 $1\logical_op__rc__rc$6$next[0:0]$9860
end
sync always
- update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9913
- update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9914
- update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9915
- update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9916
- update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9917
- update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9918
- update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9919
- update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9920
- update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9921
- update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9922
- update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9923
- update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9924
- update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9925
- update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9926
- update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9927
- update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9928
- update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9929
- update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9930
+ update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9827
+ update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9828
+ update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9829
+ update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9830
+ update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9831
+ update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9832
+ update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9833
+ update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9834
+ update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9835
+ update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9836
+ update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9837
+ update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9838
+ update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9839
+ update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9840
+ update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9841
+ update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9842
+ update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9843
+ update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9844
end
- connect \$74 $and$libresoc.v:170985$9832_Y
+ connect \$74 $and$libresoc.v:168786$9746_Y
connect \cr_a$68 4'0000
connect \cr_a_ok$69 1'0
connect \xer_so_ok$72 1'0
connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \output_stage_muxid \muxid
end
-attribute \src "libresoc.v:171341.1-172322.10"
+attribute \src "libresoc.v:169142.1-170123.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0"
attribute \generator "nMigen"
module \pipe_middle_0
- attribute \src "libresoc.v:172247.3-172261.6"
- wire $0\div_by_zero$54$next[0:0]$10183
- attribute \src "libresoc.v:171921.3-171922.47"
- wire $0\div_by_zero$54[0:0]$10018
- attribute \src "libresoc.v:171364.7-171364.30"
- wire $0\div_by_zero$54[0:0]$10200
- attribute \src "libresoc.v:172043.3-172054.6"
+ attribute \src "libresoc.v:170048.3-170062.6"
+ wire $0\div_by_zero$54$next[0:0]$10097
+ attribute \src "libresoc.v:169165.7-169165.30"
+ wire $0\div_by_zero$54[0:0]$10114
+ attribute \src "libresoc.v:169722.3-169723.47"
+ wire $0\div_by_zero$54[0:0]$9932
+ attribute \src "libresoc.v:169844.3-169855.6"
wire width 64 $0\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:172031.3-172042.6"
+ attribute \src "libresoc.v:169832.3-169843.6"
wire width 128 $0\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:172019.3-172030.6"
+ attribute \src "libresoc.v:169820.3-169831.6"
wire width 7 $0\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:172217.3-172231.6"
- wire $0\dive_abs_ov32$52$next[0:0]$10175
- attribute \src "libresoc.v:171925.3-171926.51"
- wire $0\dive_abs_ov32$52[0:0]$10022
- attribute \src "libresoc.v:171388.7-171388.32"
- wire $0\dive_abs_ov32$52[0:0]$10202
- attribute \src "libresoc.v:172232.3-172246.6"
- wire $0\dive_abs_ov64$53$next[0:0]$10179
- attribute \src "libresoc.v:171923.3-171924.51"
- wire $0\dive_abs_ov64$53[0:0]$10020
- attribute \src "libresoc.v:171396.7-171396.32"
- wire $0\dive_abs_ov64$53[0:0]$10204
- attribute \src "libresoc.v:172262.3-172276.6"
- wire width 128 $0\dividend$68$next[127:0]$10187
- attribute \src "libresoc.v:171919.3-171920.41"
- wire width 128 $0\dividend$68[127:0]$10016
- attribute \src "libresoc.v:171402.15-171402.68"
- wire width 128 $0\dividend$68[127:0]$10206
- attribute \src "libresoc.v:172202.3-172216.6"
- wire $0\dividend_neg$51$next[0:0]$10171
- attribute \src "libresoc.v:171927.3-171928.49"
- wire $0\dividend_neg$51[0:0]$10024
- attribute \src "libresoc.v:171410.7-171410.31"
- wire $0\dividend_neg$51[0:0]$10208
- attribute \src "libresoc.v:172187.3-172201.6"
- wire $0\divisor_neg$50$next[0:0]$10167
- attribute \src "libresoc.v:171929.3-171930.47"
- wire $0\divisor_neg$50[0:0]$10026
- attribute \src "libresoc.v:171418.7-171418.30"
- wire $0\divisor_neg$50[0:0]$10210
- attribute \src "libresoc.v:172277.3-172291.6"
- wire width 64 $0\divisor_radicand$65$next[63:0]$10191
- attribute \src "libresoc.v:171917.3-171918.57"
- wire width 64 $0\divisor_radicand$65[63:0]$10014
- attribute \src "libresoc.v:171424.14-171424.58"
- wire width 64 $0\divisor_radicand$65[63:0]$10212
- attribute \src "libresoc.v:172055.3-172082.6"
- wire $0\empty$next[0:0]$10084
- attribute \src "libresoc.v:171975.3-171976.27"
+ attribute \src "libresoc.v:170018.3-170032.6"
+ wire $0\dive_abs_ov32$52$next[0:0]$10089
+ attribute \src "libresoc.v:169189.7-169189.32"
+ wire $0\dive_abs_ov32$52[0:0]$10116
+ attribute \src "libresoc.v:169726.3-169727.51"
+ wire $0\dive_abs_ov32$52[0:0]$9936
+ attribute \src "libresoc.v:170033.3-170047.6"
+ wire $0\dive_abs_ov64$53$next[0:0]$10093
+ attribute \src "libresoc.v:169197.7-169197.32"
+ wire $0\dive_abs_ov64$53[0:0]$10118
+ attribute \src "libresoc.v:169724.3-169725.51"
+ wire $0\dive_abs_ov64$53[0:0]$9934
+ attribute \src "libresoc.v:170063.3-170077.6"
+ wire width 128 $0\dividend$68$next[127:0]$10101
+ attribute \src "libresoc.v:169203.15-169203.68"
+ wire width 128 $0\dividend$68[127:0]$10120
+ attribute \src "libresoc.v:169720.3-169721.41"
+ wire width 128 $0\dividend$68[127:0]$9930
+ attribute \src "libresoc.v:170003.3-170017.6"
+ wire $0\dividend_neg$51$next[0:0]$10085
+ attribute \src "libresoc.v:169211.7-169211.31"
+ wire $0\dividend_neg$51[0:0]$10122
+ attribute \src "libresoc.v:169728.3-169729.49"
+ wire $0\dividend_neg$51[0:0]$9938
+ attribute \src "libresoc.v:169988.3-170002.6"
+ wire $0\divisor_neg$50$next[0:0]$10081
+ attribute \src "libresoc.v:169219.7-169219.30"
+ wire $0\divisor_neg$50[0:0]$10124
+ attribute \src "libresoc.v:169730.3-169731.47"
+ wire $0\divisor_neg$50[0:0]$9940
+ attribute \src "libresoc.v:170078.3-170092.6"
+ wire width 64 $0\divisor_radicand$65$next[63:0]$10105
+ attribute \src "libresoc.v:169225.14-169225.58"
+ wire width 64 $0\divisor_radicand$65[63:0]$10126
+ attribute \src "libresoc.v:169718.3-169719.57"
+ wire width 64 $0\divisor_radicand$65[63:0]$9928
+ attribute \src "libresoc.v:169856.3-169883.6"
+ wire $0\empty$next[0:0]$9998
+ attribute \src "libresoc.v:169776.3-169777.27"
wire $0\empty[0:0]
- attribute \src "libresoc.v:171342.7-171342.20"
+ attribute \src "libresoc.v:169143.7-169143.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 4 $0\logical_op__data_len$45$next[3:0]$10094
- attribute \src "libresoc.v:171969.3-171970.65"
- wire width 4 $0\logical_op__data_len$45[3:0]$10066
- attribute \src "libresoc.v:171436.13-171436.45"
- wire width 4 $0\logical_op__data_len$45[3:0]$10215
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10095
- attribute \src "libresoc.v:171939.3-171940.63"
- wire width 13 $0\logical_op__fn_unit$30[12:0]$10036
- attribute \src "libresoc.v:171486.14-171486.49"
- wire width 13 $0\logical_op__fn_unit$30[12:0]$10217
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10096
- attribute \src "libresoc.v:171941.3-171942.77"
- wire width 64 $0\logical_op__imm_data__data$31[63:0]$10038
- attribute \src "libresoc.v:171492.14-171492.68"
- wire width 64 $0\logical_op__imm_data__data$31[63:0]$10219
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__imm_data__ok$32$next[0:0]$10097
- attribute \src "libresoc.v:171943.3-171944.73"
- wire $0\logical_op__imm_data__ok$32[0:0]$10040
- attribute \src "libresoc.v:171500.7-171500.43"
- wire $0\logical_op__imm_data__ok$32[0:0]$10221
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 2 $0\logical_op__input_carry$39$next[1:0]$10098
- attribute \src "libresoc.v:171957.3-171958.71"
- wire width 2 $0\logical_op__input_carry$39[1:0]$10054
- attribute \src "libresoc.v:171522.13-171522.48"
- wire width 2 $0\logical_op__input_carry$39[1:0]$10223
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 32 $0\logical_op__insn$46$next[31:0]$10099
- attribute \src "libresoc.v:171971.3-171972.57"
- wire width 32 $0\logical_op__insn$46[31:0]$10068
- attribute \src "libresoc.v:171530.14-171530.43"
- wire width 32 $0\logical_op__insn$46[31:0]$10225
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 7 $0\logical_op__insn_type$29$next[6:0]$10100
- attribute \src "libresoc.v:171937.3-171938.67"
- wire width 7 $0\logical_op__insn_type$29[6:0]$10034
- attribute \src "libresoc.v:171760.13-171760.47"
- wire width 7 $0\logical_op__insn_type$29[6:0]$10227
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__invert_in$37$next[0:0]$10101
- attribute \src "libresoc.v:171953.3-171954.67"
- wire $0\logical_op__invert_in$37[0:0]$10050
- attribute \src "libresoc.v:171768.7-171768.40"
- wire $0\logical_op__invert_in$37[0:0]$10229
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__invert_out$40$next[0:0]$10102
- attribute \src "libresoc.v:171959.3-171960.69"
- wire $0\logical_op__invert_out$40[0:0]$10056
- attribute \src "libresoc.v:171776.7-171776.41"
- wire $0\logical_op__invert_out$40[0:0]$10231
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__is_32bit$43$next[0:0]$10103
- attribute \src "libresoc.v:171965.3-171966.65"
- wire $0\logical_op__is_32bit$43[0:0]$10062
- attribute \src "libresoc.v:171784.7-171784.39"
- wire $0\logical_op__is_32bit$43[0:0]$10233
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__is_signed$44$next[0:0]$10104
- attribute \src "libresoc.v:171967.3-171968.67"
- wire $0\logical_op__is_signed$44[0:0]$10064
- attribute \src "libresoc.v:171792.7-171792.40"
- wire $0\logical_op__is_signed$44[0:0]$10235
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__oe__oe$35$next[0:0]$10105
- attribute \src "libresoc.v:171949.3-171950.61"
- wire $0\logical_op__oe__oe$35[0:0]$10046
- attribute \src "libresoc.v:171798.7-171798.37"
- wire $0\logical_op__oe__oe$35[0:0]$10237
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__oe__ok$36$next[0:0]$10106
- attribute \src "libresoc.v:171951.3-171952.61"
- wire $0\logical_op__oe__ok$36[0:0]$10048
- attribute \src "libresoc.v:171806.7-171806.37"
- wire $0\logical_op__oe__ok$36[0:0]$10239
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__output_carry$42$next[0:0]$10107
- attribute \src "libresoc.v:171963.3-171964.73"
- wire $0\logical_op__output_carry$42[0:0]$10060
- attribute \src "libresoc.v:171816.7-171816.43"
- wire $0\logical_op__output_carry$42[0:0]$10241
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__rc__ok$34$next[0:0]$10108
- attribute \src "libresoc.v:171947.3-171948.61"
- wire $0\logical_op__rc__ok$34[0:0]$10044
- attribute \src "libresoc.v:171822.7-171822.37"
- wire $0\logical_op__rc__ok$34[0:0]$10243
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__rc__rc$33$next[0:0]$10109
- attribute \src "libresoc.v:171945.3-171946.61"
- wire $0\logical_op__rc__rc$33[0:0]$10042
- attribute \src "libresoc.v:171830.7-171830.37"
- wire $0\logical_op__rc__rc$33[0:0]$10245
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__write_cr0$41$next[0:0]$10110
- attribute \src "libresoc.v:171961.3-171962.67"
- wire $0\logical_op__write_cr0$41[0:0]$10058
- attribute \src "libresoc.v:171840.7-171840.40"
- wire $0\logical_op__write_cr0$41[0:0]$10247
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $0\logical_op__zero_a$38$next[0:0]$10111
- attribute \src "libresoc.v:171955.3-171956.61"
- wire $0\logical_op__zero_a$38[0:0]$10052
- attribute \src "libresoc.v:171848.7-171848.37"
- wire $0\logical_op__zero_a$38[0:0]$10249
- attribute \src "libresoc.v:172083.3-172097.6"
- wire width 2 $0\muxid$28$next[1:0]$10090
- attribute \src "libresoc.v:171973.3-171974.35"
- wire width 2 $0\muxid$28[1:0]$10070
- attribute \src "libresoc.v:171856.13-171856.30"
- wire width 2 $0\muxid$28[1:0]$10251
- attribute \src "libresoc.v:172292.3-172306.6"
- wire width 2 $0\operation$69$next[1:0]$10195
- attribute \src "libresoc.v:171915.3-171916.43"
- wire width 2 $0\operation$69[1:0]$10012
- attribute \src "libresoc.v:171866.13-171866.34"
- wire width 2 $0\operation$69[1:0]$10253
- attribute \src "libresoc.v:172142.3-172156.6"
- wire width 64 $0\ra$47$next[63:0]$10155
- attribute \src "libresoc.v:171935.3-171936.29"
- wire width 64 $0\ra$47[63:0]$10032
- attribute \src "libresoc.v:171880.14-171880.44"
- wire width 64 $0\ra$47[63:0]$10255
- attribute \src "libresoc.v:172157.3-172171.6"
- wire width 64 $0\rb$48$next[63:0]$10159
- attribute \src "libresoc.v:171933.3-171934.29"
- wire width 64 $0\rb$48[63:0]$10030
- attribute \src "libresoc.v:171888.14-171888.44"
- wire width 64 $0\rb$48[63:0]$10257
- attribute \src "libresoc.v:172010.3-172018.6"
- wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10078
- attribute \src "libresoc.v:171977.3-171978.75"
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 4 $0\logical_op__data_len$45$next[3:0]$10008
+ attribute \src "libresoc.v:169237.13-169237.45"
+ wire width 4 $0\logical_op__data_len$45[3:0]$10129
+ attribute \src "libresoc.v:169770.3-169771.65"
+ wire width 4 $0\logical_op__data_len$45[3:0]$9980
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10009
+ attribute \src "libresoc.v:169287.14-169287.49"
+ wire width 13 $0\logical_op__fn_unit$30[12:0]$10131
+ attribute \src "libresoc.v:169740.3-169741.63"
+ wire width 13 $0\logical_op__fn_unit$30[12:0]$9950
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10010
+ attribute \src "libresoc.v:169293.14-169293.68"
+ wire width 64 $0\logical_op__imm_data__data$31[63:0]$10133
+ attribute \src "libresoc.v:169742.3-169743.77"
+ wire width 64 $0\logical_op__imm_data__data$31[63:0]$9952
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__imm_data__ok$32$next[0:0]$10011
+ attribute \src "libresoc.v:169301.7-169301.43"
+ wire $0\logical_op__imm_data__ok$32[0:0]$10135
+ attribute \src "libresoc.v:169744.3-169745.73"
+ wire $0\logical_op__imm_data__ok$32[0:0]$9954
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 2 $0\logical_op__input_carry$39$next[1:0]$10012
+ attribute \src "libresoc.v:169323.13-169323.48"
+ wire width 2 $0\logical_op__input_carry$39[1:0]$10137
+ attribute \src "libresoc.v:169758.3-169759.71"
+ wire width 2 $0\logical_op__input_carry$39[1:0]$9968
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 32 $0\logical_op__insn$46$next[31:0]$10013
+ attribute \src "libresoc.v:169331.14-169331.43"
+ wire width 32 $0\logical_op__insn$46[31:0]$10139
+ attribute \src "libresoc.v:169772.3-169773.57"
+ wire width 32 $0\logical_op__insn$46[31:0]$9982
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 7 $0\logical_op__insn_type$29$next[6:0]$10014
+ attribute \src "libresoc.v:169561.13-169561.47"
+ wire width 7 $0\logical_op__insn_type$29[6:0]$10141
+ attribute \src "libresoc.v:169738.3-169739.67"
+ wire width 7 $0\logical_op__insn_type$29[6:0]$9948
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__invert_in$37$next[0:0]$10015
+ attribute \src "libresoc.v:169569.7-169569.40"
+ wire $0\logical_op__invert_in$37[0:0]$10143
+ attribute \src "libresoc.v:169754.3-169755.67"
+ wire $0\logical_op__invert_in$37[0:0]$9964
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__invert_out$40$next[0:0]$10016
+ attribute \src "libresoc.v:169577.7-169577.41"
+ wire $0\logical_op__invert_out$40[0:0]$10145
+ attribute \src "libresoc.v:169760.3-169761.69"
+ wire $0\logical_op__invert_out$40[0:0]$9970
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__is_32bit$43$next[0:0]$10017
+ attribute \src "libresoc.v:169585.7-169585.39"
+ wire $0\logical_op__is_32bit$43[0:0]$10147
+ attribute \src "libresoc.v:169766.3-169767.65"
+ wire $0\logical_op__is_32bit$43[0:0]$9976
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__is_signed$44$next[0:0]$10018
+ attribute \src "libresoc.v:169593.7-169593.40"
+ wire $0\logical_op__is_signed$44[0:0]$10149
+ attribute \src "libresoc.v:169768.3-169769.67"
+ wire $0\logical_op__is_signed$44[0:0]$9978
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__oe__oe$35$next[0:0]$10019
+ attribute \src "libresoc.v:169599.7-169599.37"
+ wire $0\logical_op__oe__oe$35[0:0]$10151
+ attribute \src "libresoc.v:169750.3-169751.61"
+ wire $0\logical_op__oe__oe$35[0:0]$9960
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__oe__ok$36$next[0:0]$10020
+ attribute \src "libresoc.v:169607.7-169607.37"
+ wire $0\logical_op__oe__ok$36[0:0]$10153
+ attribute \src "libresoc.v:169752.3-169753.61"
+ wire $0\logical_op__oe__ok$36[0:0]$9962
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__output_carry$42$next[0:0]$10021
+ attribute \src "libresoc.v:169617.7-169617.43"
+ wire $0\logical_op__output_carry$42[0:0]$10155
+ attribute \src "libresoc.v:169764.3-169765.73"
+ wire $0\logical_op__output_carry$42[0:0]$9974
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__rc__ok$34$next[0:0]$10022
+ attribute \src "libresoc.v:169623.7-169623.37"
+ wire $0\logical_op__rc__ok$34[0:0]$10157
+ attribute \src "libresoc.v:169748.3-169749.61"
+ wire $0\logical_op__rc__ok$34[0:0]$9958
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__rc__rc$33$next[0:0]$10023
+ attribute \src "libresoc.v:169631.7-169631.37"
+ wire $0\logical_op__rc__rc$33[0:0]$10159
+ attribute \src "libresoc.v:169746.3-169747.61"
+ wire $0\logical_op__rc__rc$33[0:0]$9956
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__write_cr0$41$next[0:0]$10024
+ attribute \src "libresoc.v:169641.7-169641.40"
+ wire $0\logical_op__write_cr0$41[0:0]$10161
+ attribute \src "libresoc.v:169762.3-169763.67"
+ wire $0\logical_op__write_cr0$41[0:0]$9972
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $0\logical_op__zero_a$38$next[0:0]$10025
+ attribute \src "libresoc.v:169649.7-169649.37"
+ wire $0\logical_op__zero_a$38[0:0]$10163
+ attribute \src "libresoc.v:169756.3-169757.61"
+ wire $0\logical_op__zero_a$38[0:0]$9966
+ attribute \src "libresoc.v:169884.3-169898.6"
+ wire width 2 $0\muxid$28$next[1:0]$10004
+ attribute \src "libresoc.v:169657.13-169657.30"
+ wire width 2 $0\muxid$28[1:0]$10165
+ attribute \src "libresoc.v:169774.3-169775.35"
+ wire width 2 $0\muxid$28[1:0]$9984
+ attribute \src "libresoc.v:170093.3-170107.6"
+ wire width 2 $0\operation$69$next[1:0]$10109
+ attribute \src "libresoc.v:169667.13-169667.34"
+ wire width 2 $0\operation$69[1:0]$10167
+ attribute \src "libresoc.v:169716.3-169717.43"
+ wire width 2 $0\operation$69[1:0]$9926
+ attribute \src "libresoc.v:169943.3-169957.6"
+ wire width 64 $0\ra$47$next[63:0]$10069
+ attribute \src "libresoc.v:169681.14-169681.44"
+ wire width 64 $0\ra$47[63:0]$10169
+ attribute \src "libresoc.v:169736.3-169737.29"
+ wire width 64 $0\ra$47[63:0]$9946
+ attribute \src "libresoc.v:169958.3-169972.6"
+ wire width 64 $0\rb$48$next[63:0]$10073
+ attribute \src "libresoc.v:169689.14-169689.44"
+ wire width 64 $0\rb$48[63:0]$10171
+ attribute \src "libresoc.v:169734.3-169735.29"
+ wire width 64 $0\rb$48[63:0]$9944
+ attribute \src "libresoc.v:169811.3-169819.6"
+ wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9992
+ attribute \src "libresoc.v:169778.3-169779.75"
wire width 128 $0\saved_state_dividend_quotient[127:0]
- attribute \src "libresoc.v:172001.3-172009.6"
- wire width 7 $0\saved_state_q_bits_known$next[6:0]$10075
- attribute \src "libresoc.v:171979.3-171980.65"
+ attribute \src "libresoc.v:169802.3-169810.6"
+ wire width 7 $0\saved_state_q_bits_known$next[6:0]$9989
+ attribute \src "libresoc.v:169780.3-169781.65"
wire width 7 $0\saved_state_q_bits_known[6:0]
- attribute \src "libresoc.v:172172.3-172186.6"
- wire $0\xer_so$49$next[0:0]$10163
- attribute \src "libresoc.v:171931.3-171932.37"
- wire $0\xer_so$49[0:0]$10028
- attribute \src "libresoc.v:171906.7-171906.25"
- wire $0\xer_so$49[0:0]$10261
- attribute \src "libresoc.v:172247.3-172261.6"
- wire $1\div_by_zero$54$next[0:0]$10184
- attribute \src "libresoc.v:172043.3-172054.6"
+ attribute \src "libresoc.v:169973.3-169987.6"
+ wire $0\xer_so$49$next[0:0]$10077
+ attribute \src "libresoc.v:169707.7-169707.25"
+ wire $0\xer_so$49[0:0]$10175
+ attribute \src "libresoc.v:169732.3-169733.37"
+ wire $0\xer_so$49[0:0]$9942
+ attribute \src "libresoc.v:170048.3-170062.6"
+ wire $1\div_by_zero$54$next[0:0]$10098
+ attribute \src "libresoc.v:169844.3-169855.6"
wire width 64 $1\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:172031.3-172042.6"
+ attribute \src "libresoc.v:169832.3-169843.6"
wire width 128 $1\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:172019.3-172030.6"
+ attribute \src "libresoc.v:169820.3-169831.6"
wire width 7 $1\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:172217.3-172231.6"
- wire $1\dive_abs_ov32$52$next[0:0]$10176
- attribute \src "libresoc.v:172232.3-172246.6"
- wire $1\dive_abs_ov64$53$next[0:0]$10180
- attribute \src "libresoc.v:172262.3-172276.6"
- wire width 128 $1\dividend$68$next[127:0]$10188
- attribute \src "libresoc.v:172202.3-172216.6"
- wire $1\dividend_neg$51$next[0:0]$10172
- attribute \src "libresoc.v:172187.3-172201.6"
- wire $1\divisor_neg$50$next[0:0]$10168
- attribute \src "libresoc.v:172277.3-172291.6"
- wire width 64 $1\divisor_radicand$65$next[63:0]$10192
- attribute \src "libresoc.v:172055.3-172082.6"
- wire $1\empty$next[0:0]$10085
- attribute \src "libresoc.v:171428.7-171428.19"
+ attribute \src "libresoc.v:170018.3-170032.6"
+ wire $1\dive_abs_ov32$52$next[0:0]$10090
+ attribute \src "libresoc.v:170033.3-170047.6"
+ wire $1\dive_abs_ov64$53$next[0:0]$10094
+ attribute \src "libresoc.v:170063.3-170077.6"
+ wire width 128 $1\dividend$68$next[127:0]$10102
+ attribute \src "libresoc.v:170003.3-170017.6"
+ wire $1\dividend_neg$51$next[0:0]$10086
+ attribute \src "libresoc.v:169988.3-170002.6"
+ wire $1\divisor_neg$50$next[0:0]$10082
+ attribute \src "libresoc.v:170078.3-170092.6"
+ wire width 64 $1\divisor_radicand$65$next[63:0]$10106
+ attribute \src "libresoc.v:169856.3-169883.6"
+ wire $1\empty$next[0:0]$9999
+ attribute \src "libresoc.v:169229.7-169229.19"
wire $1\empty[0:0]
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 4 $1\logical_op__data_len$45$next[3:0]$10112
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10113
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10114
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__imm_data__ok$32$next[0:0]$10115
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 2 $1\logical_op__input_carry$39$next[1:0]$10116
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 32 $1\logical_op__insn$46$next[31:0]$10117
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 7 $1\logical_op__insn_type$29$next[6:0]$10118
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__invert_in$37$next[0:0]$10119
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__invert_out$40$next[0:0]$10120
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__is_32bit$43$next[0:0]$10121
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__is_signed$44$next[0:0]$10122
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__oe__oe$35$next[0:0]$10123
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__oe__ok$36$next[0:0]$10124
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__output_carry$42$next[0:0]$10125
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__rc__ok$34$next[0:0]$10126
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__rc__rc$33$next[0:0]$10127
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__write_cr0$41$next[0:0]$10128
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $1\logical_op__zero_a$38$next[0:0]$10129
- attribute \src "libresoc.v:172083.3-172097.6"
- wire width 2 $1\muxid$28$next[1:0]$10091
- attribute \src "libresoc.v:172292.3-172306.6"
- wire width 2 $1\operation$69$next[1:0]$10196
- attribute \src "libresoc.v:172142.3-172156.6"
- wire width 64 $1\ra$47$next[63:0]$10156
- attribute \src "libresoc.v:172157.3-172171.6"
- wire width 64 $1\rb$48$next[63:0]$10160
- attribute \src "libresoc.v:172010.3-172018.6"
- wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10079
- attribute \src "libresoc.v:171894.15-171894.84"
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 4 $1\logical_op__data_len$45$next[3:0]$10026
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10027
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10028
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__imm_data__ok$32$next[0:0]$10029
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 2 $1\logical_op__input_carry$39$next[1:0]$10030
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 32 $1\logical_op__insn$46$next[31:0]$10031
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 7 $1\logical_op__insn_type$29$next[6:0]$10032
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__invert_in$37$next[0:0]$10033
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__invert_out$40$next[0:0]$10034
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__is_32bit$43$next[0:0]$10035
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__is_signed$44$next[0:0]$10036
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__oe__oe$35$next[0:0]$10037
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__oe__ok$36$next[0:0]$10038
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__output_carry$42$next[0:0]$10039
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__rc__ok$34$next[0:0]$10040
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__rc__rc$33$next[0:0]$10041
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__write_cr0$41$next[0:0]$10042
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $1\logical_op__zero_a$38$next[0:0]$10043
+ attribute \src "libresoc.v:169884.3-169898.6"
+ wire width 2 $1\muxid$28$next[1:0]$10005
+ attribute \src "libresoc.v:170093.3-170107.6"
+ wire width 2 $1\operation$69$next[1:0]$10110
+ attribute \src "libresoc.v:169943.3-169957.6"
+ wire width 64 $1\ra$47$next[63:0]$10070
+ attribute \src "libresoc.v:169958.3-169972.6"
+ wire width 64 $1\rb$48$next[63:0]$10074
+ attribute \src "libresoc.v:169811.3-169819.6"
+ wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9993
+ attribute \src "libresoc.v:169695.15-169695.84"
wire width 128 $1\saved_state_dividend_quotient[127:0]
- attribute \src "libresoc.v:172001.3-172009.6"
- wire width 7 $1\saved_state_q_bits_known$next[6:0]$10076
- attribute \src "libresoc.v:171898.13-171898.45"
+ attribute \src "libresoc.v:169802.3-169810.6"
+ wire width 7 $1\saved_state_q_bits_known$next[6:0]$9990
+ attribute \src "libresoc.v:169699.13-169699.45"
wire width 7 $1\saved_state_q_bits_known[6:0]
- attribute \src "libresoc.v:172172.3-172186.6"
- wire $1\xer_so$49$next[0:0]$10164
- attribute \src "libresoc.v:172247.3-172261.6"
- wire $2\div_by_zero$54$next[0:0]$10185
- attribute \src "libresoc.v:172217.3-172231.6"
- wire $2\dive_abs_ov32$52$next[0:0]$10177
- attribute \src "libresoc.v:172232.3-172246.6"
- wire $2\dive_abs_ov64$53$next[0:0]$10181
- attribute \src "libresoc.v:172262.3-172276.6"
- wire width 128 $2\dividend$68$next[127:0]$10189
- attribute \src "libresoc.v:172202.3-172216.6"
- wire $2\dividend_neg$51$next[0:0]$10173
- attribute \src "libresoc.v:172187.3-172201.6"
- wire $2\divisor_neg$50$next[0:0]$10169
- attribute \src "libresoc.v:172277.3-172291.6"
- wire width 64 $2\divisor_radicand$65$next[63:0]$10193
- attribute \src "libresoc.v:172055.3-172082.6"
- wire $2\empty$next[0:0]$10086
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 4 $2\logical_op__data_len$45$next[3:0]$10130
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10131
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10132
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__imm_data__ok$32$next[0:0]$10133
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 2 $2\logical_op__input_carry$39$next[1:0]$10134
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 32 $2\logical_op__insn$46$next[31:0]$10135
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 7 $2\logical_op__insn_type$29$next[6:0]$10136
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__invert_in$37$next[0:0]$10137
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__invert_out$40$next[0:0]$10138
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__is_32bit$43$next[0:0]$10139
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__is_signed$44$next[0:0]$10140
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__oe__oe$35$next[0:0]$10141
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__oe__ok$36$next[0:0]$10142
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__output_carry$42$next[0:0]$10143
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__rc__ok$34$next[0:0]$10144
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__rc__rc$33$next[0:0]$10145
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__write_cr0$41$next[0:0]$10146
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $2\logical_op__zero_a$38$next[0:0]$10147
- attribute \src "libresoc.v:172083.3-172097.6"
- wire width 2 $2\muxid$28$next[1:0]$10092
- attribute \src "libresoc.v:172292.3-172306.6"
- wire width 2 $2\operation$69$next[1:0]$10197
- attribute \src "libresoc.v:172142.3-172156.6"
- wire width 64 $2\ra$47$next[63:0]$10157
- attribute \src "libresoc.v:172157.3-172171.6"
- wire width 64 $2\rb$48$next[63:0]$10161
- attribute \src "libresoc.v:172172.3-172186.6"
- wire $2\xer_so$49$next[0:0]$10165
- attribute \src "libresoc.v:172055.3-172082.6"
- wire $3\empty$next[0:0]$10087
- attribute \src "libresoc.v:172098.3-172141.6"
- wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10148
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $3\logical_op__imm_data__ok$32$next[0:0]$10149
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $3\logical_op__oe__oe$35$next[0:0]$10150
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $3\logical_op__oe__ok$36$next[0:0]$10151
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $3\logical_op__rc__ok$34$next[0:0]$10152
- attribute \src "libresoc.v:172098.3-172141.6"
- wire $3\logical_op__rc__rc$33$next[0:0]$10153
- attribute \src "libresoc.v:172055.3-172082.6"
- wire $4\empty$next[0:0]$10088
- attribute \src "libresoc.v:171913.18-171913.98"
- wire $and$libresoc.v:171913$10009_Y
- attribute \src "libresoc.v:171914.18-171914.107"
- wire $and$libresoc.v:171914$10010_Y
- attribute \src "libresoc.v:171910.18-171910.92"
- wire width 192 $extend$libresoc.v:171910$10005_Y
- attribute \src "libresoc.v:171912.18-171912.119"
- wire $ge$libresoc.v:171912$10008_Y
- attribute \src "libresoc.v:171911.18-171911.93"
- wire $not$libresoc.v:171911$10007_Y
- attribute \src "libresoc.v:171910.18-171910.92"
- wire width 192 $pos$libresoc.v:171910$10006_Y
- attribute \src "libresoc.v:171909.18-171909.138"
- wire width 191 $sshl$libresoc.v:171909$10004_Y
+ attribute \src "libresoc.v:169973.3-169987.6"
+ wire $1\xer_so$49$next[0:0]$10078
+ attribute \src "libresoc.v:170048.3-170062.6"
+ wire $2\div_by_zero$54$next[0:0]$10099
+ attribute \src "libresoc.v:170018.3-170032.6"
+ wire $2\dive_abs_ov32$52$next[0:0]$10091
+ attribute \src "libresoc.v:170033.3-170047.6"
+ wire $2\dive_abs_ov64$53$next[0:0]$10095
+ attribute \src "libresoc.v:170063.3-170077.6"
+ wire width 128 $2\dividend$68$next[127:0]$10103
+ attribute \src "libresoc.v:170003.3-170017.6"
+ wire $2\dividend_neg$51$next[0:0]$10087
+ attribute \src "libresoc.v:169988.3-170002.6"
+ wire $2\divisor_neg$50$next[0:0]$10083
+ attribute \src "libresoc.v:170078.3-170092.6"
+ wire width 64 $2\divisor_radicand$65$next[63:0]$10107
+ attribute \src "libresoc.v:169856.3-169883.6"
+ wire $2\empty$next[0:0]$10000
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 4 $2\logical_op__data_len$45$next[3:0]$10044
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10045
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10046
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__imm_data__ok$32$next[0:0]$10047
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 2 $2\logical_op__input_carry$39$next[1:0]$10048
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 32 $2\logical_op__insn$46$next[31:0]$10049
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 7 $2\logical_op__insn_type$29$next[6:0]$10050
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__invert_in$37$next[0:0]$10051
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__invert_out$40$next[0:0]$10052
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__is_32bit$43$next[0:0]$10053
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__is_signed$44$next[0:0]$10054
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__oe__oe$35$next[0:0]$10055
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__oe__ok$36$next[0:0]$10056
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__output_carry$42$next[0:0]$10057
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__rc__ok$34$next[0:0]$10058
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__rc__rc$33$next[0:0]$10059
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__write_cr0$41$next[0:0]$10060
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $2\logical_op__zero_a$38$next[0:0]$10061
+ attribute \src "libresoc.v:169884.3-169898.6"
+ wire width 2 $2\muxid$28$next[1:0]$10006
+ attribute \src "libresoc.v:170093.3-170107.6"
+ wire width 2 $2\operation$69$next[1:0]$10111
+ attribute \src "libresoc.v:169943.3-169957.6"
+ wire width 64 $2\ra$47$next[63:0]$10071
+ attribute \src "libresoc.v:169958.3-169972.6"
+ wire width 64 $2\rb$48$next[63:0]$10075
+ attribute \src "libresoc.v:169973.3-169987.6"
+ wire $2\xer_so$49$next[0:0]$10079
+ attribute \src "libresoc.v:169856.3-169883.6"
+ wire $3\empty$next[0:0]$10001
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10062
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $3\logical_op__imm_data__ok$32$next[0:0]$10063
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $3\logical_op__oe__oe$35$next[0:0]$10064
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $3\logical_op__oe__ok$36$next[0:0]$10065
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $3\logical_op__rc__ok$34$next[0:0]$10066
+ attribute \src "libresoc.v:169899.3-169942.6"
+ wire $3\logical_op__rc__rc$33$next[0:0]$10067
+ attribute \src "libresoc.v:169856.3-169883.6"
+ wire $4\empty$next[0:0]$10002
+ attribute \src "libresoc.v:169714.18-169714.98"
+ wire $and$libresoc.v:169714$9923_Y
+ attribute \src "libresoc.v:169715.18-169715.107"
+ wire $and$libresoc.v:169715$9924_Y
+ attribute \src "libresoc.v:169711.18-169711.92"
+ wire width 192 $extend$libresoc.v:169711$9919_Y
+ attribute \src "libresoc.v:169713.18-169713.119"
+ wire $ge$libresoc.v:169713$9922_Y
+ attribute \src "libresoc.v:169712.18-169712.93"
+ wire $not$libresoc.v:169712$9921_Y
+ attribute \src "libresoc.v:169711.18-169711.92"
+ wire width 192 $pos$libresoc.v:169711$9920_Y
+ attribute \src "libresoc.v:169710.18-169710.138"
+ wire width 191 $sshl$libresoc.v:169710$9918_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
wire width 192 \$55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
wire \$63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 65 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire input 30 \div_by_zero
wire \empty
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140"
wire \empty$next
- attribute \src "libresoc.v:171342.7-171342.15"
+ attribute \src "libresoc.v:169143.7-169143.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 21 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$49$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171"
- cell $and $and$libresoc.v:171913$10009
+ cell $and $and$libresoc.v:169714$9923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$59
connect \B \$61
- connect \Y $and$libresoc.v:171913$10009_Y
+ connect \Y $and$libresoc.v:169714$9923_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
- cell $and $and$libresoc.v:171914$10010
+ cell $and $and$libresoc.v:169715$9924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \n_ready_i
connect \B \n_valid_o
- connect \Y $and$libresoc.v:171914$10010_Y
+ connect \Y $and$libresoc.v:169715$9924_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $pos $extend$libresoc.v:171910$10005
+ cell $pos $extend$libresoc.v:169711$9919
parameter \A_SIGNED 0
parameter \A_WIDTH 191
parameter \Y_WIDTH 192
connect \A \$56
- connect \Y $extend$libresoc.v:171910$10005_Y
+ connect \Y $extend$libresoc.v:169711$9919_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116"
- cell $ge $ge$libresoc.v:171912$10008
+ cell $ge $ge$libresoc.v:169713$9922
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \saved_state_q_bits_known
connect \B 6'111111
- connect \Y $ge$libresoc.v:171912$10008_Y
+ connect \Y $ge$libresoc.v:169713$9922_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171"
- cell $not $not$libresoc.v:171911$10007
+ cell $not $not$libresoc.v:169712$9921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \empty
- connect \Y $not$libresoc.v:171911$10007_Y
+ connect \Y $not$libresoc.v:169712$9921_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $pos $pos$libresoc.v:171910$10006
+ cell $pos $pos$libresoc.v:169711$9920
parameter \A_SIGNED 0
parameter \A_WIDTH 192
parameter \Y_WIDTH 192
- connect \A $extend$libresoc.v:171910$10005_Y
- connect \Y $pos$libresoc.v:171910$10006_Y
+ connect \A $extend$libresoc.v:169711$9919_Y
+ connect \Y $pos$libresoc.v:169711$9920_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169"
- cell $sshl $sshl$libresoc.v:171909$10004
+ cell $sshl $sshl$libresoc.v:169710$9918
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 191
connect \A \div_state_next_o_dividend_quotient [127:64]
connect \B 7'1000000
- connect \Y $sshl$libresoc.v:171909$10004_Y
+ connect \Y $sshl$libresoc.v:169710$9918_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171981.18-171985.4"
+ attribute \src "libresoc.v:169782.18-169786.4"
cell \div_state_init \div_state_init
connect \dividend \div_state_init_dividend
connect \o_dividend_quotient \div_state_init_o_dividend_quotient
connect \o_q_bits_known \div_state_init_o_q_bits_known
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171986.18-171992.4"
+ attribute \src "libresoc.v:169787.18-169793.4"
cell \div_state_next \div_state_next
connect \divisor \div_state_next_divisor
connect \i_dividend_quotient \div_state_next_i_dividend_quotient
connect \o_q_bits_known \div_state_next_o_q_bits_known
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171993.10-171996.4"
+ attribute \src "libresoc.v:169794.10-169797.4"
cell \n$80 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:171997.10-172000.4"
+ attribute \src "libresoc.v:169798.10-169801.4"
cell \p$79 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
- attribute \src "libresoc.v:171342.7-171342.20"
- process $proc$libresoc.v:171342$10198
+ attribute \src "libresoc.v:169143.7-169143.20"
+ process $proc$libresoc.v:169143$10112
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:171364.7-171364.30"
- process $proc$libresoc.v:171364$10199
+ attribute \src "libresoc.v:169165.7-169165.30"
+ process $proc$libresoc.v:169165$10113
assign { } { }
- assign $0\div_by_zero$54[0:0]$10200 1'0
+ assign $0\div_by_zero$54[0:0]$10114 1'0
sync always
sync init
- update \div_by_zero$54 $0\div_by_zero$54[0:0]$10200
+ update \div_by_zero$54 $0\div_by_zero$54[0:0]$10114
end
- attribute \src "libresoc.v:171388.7-171388.32"
- process $proc$libresoc.v:171388$10201
+ attribute \src "libresoc.v:169189.7-169189.32"
+ process $proc$libresoc.v:169189$10115
assign { } { }
- assign $0\dive_abs_ov32$52[0:0]$10202 1'0
+ assign $0\dive_abs_ov32$52[0:0]$10116 1'0
sync always
sync init
- update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10202
+ update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10116
end
- attribute \src "libresoc.v:171396.7-171396.32"
- process $proc$libresoc.v:171396$10203
+ attribute \src "libresoc.v:169197.7-169197.32"
+ process $proc$libresoc.v:169197$10117
assign { } { }
- assign $0\dive_abs_ov64$53[0:0]$10204 1'0
+ assign $0\dive_abs_ov64$53[0:0]$10118 1'0
sync always
sync init
- update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10204
+ update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10118
end
- attribute \src "libresoc.v:171402.15-171402.68"
- process $proc$libresoc.v:171402$10205
+ attribute \src "libresoc.v:169203.15-169203.68"
+ process $proc$libresoc.v:169203$10119
assign { } { }
- assign $0\dividend$68[127:0]$10206 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $0\dividend$68[127:0]$10120 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \dividend$68 $0\dividend$68[127:0]$10206
+ update \dividend$68 $0\dividend$68[127:0]$10120
end
- attribute \src "libresoc.v:171410.7-171410.31"
- process $proc$libresoc.v:171410$10207
+ attribute \src "libresoc.v:169211.7-169211.31"
+ process $proc$libresoc.v:169211$10121
assign { } { }
- assign $0\dividend_neg$51[0:0]$10208 1'0
+ assign $0\dividend_neg$51[0:0]$10122 1'0
sync always
sync init
- update \dividend_neg$51 $0\dividend_neg$51[0:0]$10208
+ update \dividend_neg$51 $0\dividend_neg$51[0:0]$10122
end
- attribute \src "libresoc.v:171418.7-171418.30"
- process $proc$libresoc.v:171418$10209
+ attribute \src "libresoc.v:169219.7-169219.30"
+ process $proc$libresoc.v:169219$10123
assign { } { }
- assign $0\divisor_neg$50[0:0]$10210 1'0
+ assign $0\divisor_neg$50[0:0]$10124 1'0
sync always
sync init
- update \divisor_neg$50 $0\divisor_neg$50[0:0]$10210
+ update \divisor_neg$50 $0\divisor_neg$50[0:0]$10124
end
- attribute \src "libresoc.v:171424.14-171424.58"
- process $proc$libresoc.v:171424$10211
+ attribute \src "libresoc.v:169225.14-169225.58"
+ process $proc$libresoc.v:169225$10125
assign { } { }
- assign $0\divisor_radicand$65[63:0]$10212 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\divisor_radicand$65[63:0]$10126 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10212
+ update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10126
end
- attribute \src "libresoc.v:171428.7-171428.19"
- process $proc$libresoc.v:171428$10213
+ attribute \src "libresoc.v:169229.7-169229.19"
+ process $proc$libresoc.v:169229$10127
assign { } { }
assign $1\empty[0:0] 1'1
sync always
sync init
update \empty $1\empty[0:0]
end
- attribute \src "libresoc.v:171436.13-171436.45"
- process $proc$libresoc.v:171436$10214
+ attribute \src "libresoc.v:169237.13-169237.45"
+ process $proc$libresoc.v:169237$10128
assign { } { }
- assign $0\logical_op__data_len$45[3:0]$10215 4'0000
+ assign $0\logical_op__data_len$45[3:0]$10129 4'0000
sync always
sync init
- update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10215
+ update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10129
end
- attribute \src "libresoc.v:171486.14-171486.49"
- process $proc$libresoc.v:171486$10216
+ attribute \src "libresoc.v:169287.14-169287.49"
+ process $proc$libresoc.v:169287$10130
assign { } { }
- assign $0\logical_op__fn_unit$30[12:0]$10217 13'0000000000000
+ assign $0\logical_op__fn_unit$30[12:0]$10131 13'0000000000000
sync always
sync init
- update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10217
+ update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10131
end
- attribute \src "libresoc.v:171492.14-171492.68"
- process $proc$libresoc.v:171492$10218
+ attribute \src "libresoc.v:169293.14-169293.68"
+ process $proc$libresoc.v:169293$10132
assign { } { }
- assign $0\logical_op__imm_data__data$31[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\logical_op__imm_data__data$31[63:0]$10133 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10219
+ update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10133
end
- attribute \src "libresoc.v:171500.7-171500.43"
- process $proc$libresoc.v:171500$10220
+ attribute \src "libresoc.v:169301.7-169301.43"
+ process $proc$libresoc.v:169301$10134
assign { } { }
- assign $0\logical_op__imm_data__ok$32[0:0]$10221 1'0
+ assign $0\logical_op__imm_data__ok$32[0:0]$10135 1'0
sync always
sync init
- update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10221
+ update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10135
end
- attribute \src "libresoc.v:171522.13-171522.48"
- process $proc$libresoc.v:171522$10222
+ attribute \src "libresoc.v:169323.13-169323.48"
+ process $proc$libresoc.v:169323$10136
assign { } { }
- assign $0\logical_op__input_carry$39[1:0]$10223 2'00
+ assign $0\logical_op__input_carry$39[1:0]$10137 2'00
sync always
sync init
- update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10223
+ update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10137
end
- attribute \src "libresoc.v:171530.14-171530.43"
- process $proc$libresoc.v:171530$10224
+ attribute \src "libresoc.v:169331.14-169331.43"
+ process $proc$libresoc.v:169331$10138
assign { } { }
- assign $0\logical_op__insn$46[31:0]$10225 0
+ assign $0\logical_op__insn$46[31:0]$10139 0
sync always
sync init
- update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10225
+ update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10139
end
- attribute \src "libresoc.v:171760.13-171760.47"
- process $proc$libresoc.v:171760$10226
+ attribute \src "libresoc.v:169561.13-169561.47"
+ process $proc$libresoc.v:169561$10140
assign { } { }
- assign $0\logical_op__insn_type$29[6:0]$10227 7'0000000
+ assign $0\logical_op__insn_type$29[6:0]$10141 7'0000000
sync always
sync init
- update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10227
+ update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10141
end
- attribute \src "libresoc.v:171768.7-171768.40"
- process $proc$libresoc.v:171768$10228
+ attribute \src "libresoc.v:169569.7-169569.40"
+ process $proc$libresoc.v:169569$10142
assign { } { }
- assign $0\logical_op__invert_in$37[0:0]$10229 1'0
+ assign $0\logical_op__invert_in$37[0:0]$10143 1'0
sync always
sync init
- update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10229
+ update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10143
end
- attribute \src "libresoc.v:171776.7-171776.41"
- process $proc$libresoc.v:171776$10230
+ attribute \src "libresoc.v:169577.7-169577.41"
+ process $proc$libresoc.v:169577$10144
assign { } { }
- assign $0\logical_op__invert_out$40[0:0]$10231 1'0
+ assign $0\logical_op__invert_out$40[0:0]$10145 1'0
sync always
sync init
- update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10231
+ update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10145
end
- attribute \src "libresoc.v:171784.7-171784.39"
- process $proc$libresoc.v:171784$10232
+ attribute \src "libresoc.v:169585.7-169585.39"
+ process $proc$libresoc.v:169585$10146
assign { } { }
- assign $0\logical_op__is_32bit$43[0:0]$10233 1'0
+ assign $0\logical_op__is_32bit$43[0:0]$10147 1'0
sync always
sync init
- update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10233
+ update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10147
end
- attribute \src "libresoc.v:171792.7-171792.40"
- process $proc$libresoc.v:171792$10234
+ attribute \src "libresoc.v:169593.7-169593.40"
+ process $proc$libresoc.v:169593$10148
assign { } { }
- assign $0\logical_op__is_signed$44[0:0]$10235 1'0
+ assign $0\logical_op__is_signed$44[0:0]$10149 1'0
sync always
sync init
- update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10235
+ update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10149
end
- attribute \src "libresoc.v:171798.7-171798.37"
- process $proc$libresoc.v:171798$10236
+ attribute \src "libresoc.v:169599.7-169599.37"
+ process $proc$libresoc.v:169599$10150
assign { } { }
- assign $0\logical_op__oe__oe$35[0:0]$10237 1'0
+ assign $0\logical_op__oe__oe$35[0:0]$10151 1'0
sync always
sync init
- update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10237
+ update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10151
end
- attribute \src "libresoc.v:171806.7-171806.37"
- process $proc$libresoc.v:171806$10238
+ attribute \src "libresoc.v:169607.7-169607.37"
+ process $proc$libresoc.v:169607$10152
assign { } { }
- assign $0\logical_op__oe__ok$36[0:0]$10239 1'0
+ assign $0\logical_op__oe__ok$36[0:0]$10153 1'0
sync always
sync init
- update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10239
+ update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10153
end
- attribute \src "libresoc.v:171816.7-171816.43"
- process $proc$libresoc.v:171816$10240
+ attribute \src "libresoc.v:169617.7-169617.43"
+ process $proc$libresoc.v:169617$10154
assign { } { }
- assign $0\logical_op__output_carry$42[0:0]$10241 1'0
+ assign $0\logical_op__output_carry$42[0:0]$10155 1'0
sync always
sync init
- update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10241
+ update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10155
end
- attribute \src "libresoc.v:171822.7-171822.37"
- process $proc$libresoc.v:171822$10242
+ attribute \src "libresoc.v:169623.7-169623.37"
+ process $proc$libresoc.v:169623$10156
assign { } { }
- assign $0\logical_op__rc__ok$34[0:0]$10243 1'0
+ assign $0\logical_op__rc__ok$34[0:0]$10157 1'0
sync always
sync init
- update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10243
+ update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10157
end
- attribute \src "libresoc.v:171830.7-171830.37"
- process $proc$libresoc.v:171830$10244
+ attribute \src "libresoc.v:169631.7-169631.37"
+ process $proc$libresoc.v:169631$10158
assign { } { }
- assign $0\logical_op__rc__rc$33[0:0]$10245 1'0
+ assign $0\logical_op__rc__rc$33[0:0]$10159 1'0
sync always
sync init
- update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10245
+ update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10159
end
- attribute \src "libresoc.v:171840.7-171840.40"
- process $proc$libresoc.v:171840$10246
+ attribute \src "libresoc.v:169641.7-169641.40"
+ process $proc$libresoc.v:169641$10160
assign { } { }
- assign $0\logical_op__write_cr0$41[0:0]$10247 1'0
+ assign $0\logical_op__write_cr0$41[0:0]$10161 1'0
sync always
sync init
- update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10247
+ update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10161
end
- attribute \src "libresoc.v:171848.7-171848.37"
- process $proc$libresoc.v:171848$10248
+ attribute \src "libresoc.v:169649.7-169649.37"
+ process $proc$libresoc.v:169649$10162
assign { } { }
- assign $0\logical_op__zero_a$38[0:0]$10249 1'0
+ assign $0\logical_op__zero_a$38[0:0]$10163 1'0
sync always
sync init
- update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10249
+ update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10163
end
- attribute \src "libresoc.v:171856.13-171856.30"
- process $proc$libresoc.v:171856$10250
+ attribute \src "libresoc.v:169657.13-169657.30"
+ process $proc$libresoc.v:169657$10164
assign { } { }
- assign $0\muxid$28[1:0]$10251 2'00
+ assign $0\muxid$28[1:0]$10165 2'00
sync always
sync init
- update \muxid$28 $0\muxid$28[1:0]$10251
+ update \muxid$28 $0\muxid$28[1:0]$10165
end
- attribute \src "libresoc.v:171866.13-171866.34"
- process $proc$libresoc.v:171866$10252
+ attribute \src "libresoc.v:169667.13-169667.34"
+ process $proc$libresoc.v:169667$10166
assign { } { }
- assign $0\operation$69[1:0]$10253 2'00
+ assign $0\operation$69[1:0]$10167 2'00
sync always
sync init
- update \operation$69 $0\operation$69[1:0]$10253
+ update \operation$69 $0\operation$69[1:0]$10167
end
- attribute \src "libresoc.v:171880.14-171880.44"
- process $proc$libresoc.v:171880$10254
+ attribute \src "libresoc.v:169681.14-169681.44"
+ process $proc$libresoc.v:169681$10168
assign { } { }
- assign $0\ra$47[63:0]$10255 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\ra$47[63:0]$10169 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \ra$47 $0\ra$47[63:0]$10255
+ update \ra$47 $0\ra$47[63:0]$10169
end
- attribute \src "libresoc.v:171888.14-171888.44"
- process $proc$libresoc.v:171888$10256
+ attribute \src "libresoc.v:169689.14-169689.44"
+ process $proc$libresoc.v:169689$10170
assign { } { }
- assign $0\rb$48[63:0]$10257 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\rb$48[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \rb$48 $0\rb$48[63:0]$10257
+ update \rb$48 $0\rb$48[63:0]$10171
end
- attribute \src "libresoc.v:171894.15-171894.84"
- process $proc$libresoc.v:171894$10258
+ attribute \src "libresoc.v:169695.15-169695.84"
+ process $proc$libresoc.v:169695$10172
assign { } { }
assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:171898.13-171898.45"
- process $proc$libresoc.v:171898$10259
+ attribute \src "libresoc.v:169699.13-169699.45"
+ process $proc$libresoc.v:169699$10173
assign { } { }
assign $1\saved_state_q_bits_known[6:0] 7'0000000
sync always
sync init
update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0]
end
- attribute \src "libresoc.v:171906.7-171906.25"
- process $proc$libresoc.v:171906$10260
+ attribute \src "libresoc.v:169707.7-169707.25"
+ process $proc$libresoc.v:169707$10174
assign { } { }
- assign $0\xer_so$49[0:0]$10261 1'0
+ assign $0\xer_so$49[0:0]$10175 1'0
sync always
sync init
- update \xer_so$49 $0\xer_so$49[0:0]$10261
+ update \xer_so$49 $0\xer_so$49[0:0]$10175
end
- attribute \src "libresoc.v:171915.3-171916.43"
- process $proc$libresoc.v:171915$10011
+ attribute \src "libresoc.v:169716.3-169717.43"
+ process $proc$libresoc.v:169716$9925
assign { } { }
- assign $0\operation$69[1:0]$10012 \operation$69$next
+ assign $0\operation$69[1:0]$9926 \operation$69$next
sync posedge \coresync_clk
- update \operation$69 $0\operation$69[1:0]$10012
+ update \operation$69 $0\operation$69[1:0]$9926
end
- attribute \src "libresoc.v:171917.3-171918.57"
- process $proc$libresoc.v:171917$10013
+ attribute \src "libresoc.v:169718.3-169719.57"
+ process $proc$libresoc.v:169718$9927
assign { } { }
- assign $0\divisor_radicand$65[63:0]$10014 \divisor_radicand$65$next
+ assign $0\divisor_radicand$65[63:0]$9928 \divisor_radicand$65$next
sync posedge \coresync_clk
- update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10014
+ update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9928
end
- attribute \src "libresoc.v:171919.3-171920.41"
- process $proc$libresoc.v:171919$10015
+ attribute \src "libresoc.v:169720.3-169721.41"
+ process $proc$libresoc.v:169720$9929
assign { } { }
- assign $0\dividend$68[127:0]$10016 \dividend$68$next
+ assign $0\dividend$68[127:0]$9930 \dividend$68$next
sync posedge \coresync_clk
- update \dividend$68 $0\dividend$68[127:0]$10016
+ update \dividend$68 $0\dividend$68[127:0]$9930
end
- attribute \src "libresoc.v:171921.3-171922.47"
- process $proc$libresoc.v:171921$10017
+ attribute \src "libresoc.v:169722.3-169723.47"
+ process $proc$libresoc.v:169722$9931
assign { } { }
- assign $0\div_by_zero$54[0:0]$10018 \div_by_zero$54$next
+ assign $0\div_by_zero$54[0:0]$9932 \div_by_zero$54$next
sync posedge \coresync_clk
- update \div_by_zero$54 $0\div_by_zero$54[0:0]$10018
+ update \div_by_zero$54 $0\div_by_zero$54[0:0]$9932
end
- attribute \src "libresoc.v:171923.3-171924.51"
- process $proc$libresoc.v:171923$10019
+ attribute \src "libresoc.v:169724.3-169725.51"
+ process $proc$libresoc.v:169724$9933
assign { } { }
- assign $0\dive_abs_ov64$53[0:0]$10020 \dive_abs_ov64$53$next
+ assign $0\dive_abs_ov64$53[0:0]$9934 \dive_abs_ov64$53$next
sync posedge \coresync_clk
- update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10020
+ update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9934
end
- attribute \src "libresoc.v:171925.3-171926.51"
- process $proc$libresoc.v:171925$10021
+ attribute \src "libresoc.v:169726.3-169727.51"
+ process $proc$libresoc.v:169726$9935
assign { } { }
- assign $0\dive_abs_ov32$52[0:0]$10022 \dive_abs_ov32$52$next
+ assign $0\dive_abs_ov32$52[0:0]$9936 \dive_abs_ov32$52$next
sync posedge \coresync_clk
- update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10022
+ update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9936
end
- attribute \src "libresoc.v:171927.3-171928.49"
- process $proc$libresoc.v:171927$10023
+ attribute \src "libresoc.v:169728.3-169729.49"
+ process $proc$libresoc.v:169728$9937
assign { } { }
- assign $0\dividend_neg$51[0:0]$10024 \dividend_neg$51$next
+ assign $0\dividend_neg$51[0:0]$9938 \dividend_neg$51$next
sync posedge \coresync_clk
- update \dividend_neg$51 $0\dividend_neg$51[0:0]$10024
+ update \dividend_neg$51 $0\dividend_neg$51[0:0]$9938
end
- attribute \src "libresoc.v:171929.3-171930.47"
- process $proc$libresoc.v:171929$10025
+ attribute \src "libresoc.v:169730.3-169731.47"
+ process $proc$libresoc.v:169730$9939
assign { } { }
- assign $0\divisor_neg$50[0:0]$10026 \divisor_neg$50$next
+ assign $0\divisor_neg$50[0:0]$9940 \divisor_neg$50$next
sync posedge \coresync_clk
- update \divisor_neg$50 $0\divisor_neg$50[0:0]$10026
+ update \divisor_neg$50 $0\divisor_neg$50[0:0]$9940
end
- attribute \src "libresoc.v:171931.3-171932.37"
- process $proc$libresoc.v:171931$10027
+ attribute \src "libresoc.v:169732.3-169733.37"
+ process $proc$libresoc.v:169732$9941
assign { } { }
- assign $0\xer_so$49[0:0]$10028 \xer_so$49$next
+ assign $0\xer_so$49[0:0]$9942 \xer_so$49$next
sync posedge \coresync_clk
- update \xer_so$49 $0\xer_so$49[0:0]$10028
+ update \xer_so$49 $0\xer_so$49[0:0]$9942
end
- attribute \src "libresoc.v:171933.3-171934.29"
- process $proc$libresoc.v:171933$10029
+ attribute \src "libresoc.v:169734.3-169735.29"
+ process $proc$libresoc.v:169734$9943
assign { } { }
- assign $0\rb$48[63:0]$10030 \rb$48$next
+ assign $0\rb$48[63:0]$9944 \rb$48$next
sync posedge \coresync_clk
- update \rb$48 $0\rb$48[63:0]$10030
+ update \rb$48 $0\rb$48[63:0]$9944
end
- attribute \src "libresoc.v:171935.3-171936.29"
- process $proc$libresoc.v:171935$10031
+ attribute \src "libresoc.v:169736.3-169737.29"
+ process $proc$libresoc.v:169736$9945
assign { } { }
- assign $0\ra$47[63:0]$10032 \ra$47$next
+ assign $0\ra$47[63:0]$9946 \ra$47$next
sync posedge \coresync_clk
- update \ra$47 $0\ra$47[63:0]$10032
+ update \ra$47 $0\ra$47[63:0]$9946
end
- attribute \src "libresoc.v:171937.3-171938.67"
- process $proc$libresoc.v:171937$10033
+ attribute \src "libresoc.v:169738.3-169739.67"
+ process $proc$libresoc.v:169738$9947
assign { } { }
- assign $0\logical_op__insn_type$29[6:0]$10034 \logical_op__insn_type$29$next
+ assign $0\logical_op__insn_type$29[6:0]$9948 \logical_op__insn_type$29$next
sync posedge \coresync_clk
- update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10034
+ update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9948
end
- attribute \src "libresoc.v:171939.3-171940.63"
- process $proc$libresoc.v:171939$10035
+ attribute \src "libresoc.v:169740.3-169741.63"
+ process $proc$libresoc.v:169740$9949
assign { } { }
- assign $0\logical_op__fn_unit$30[12:0]$10036 \logical_op__fn_unit$30$next
+ assign $0\logical_op__fn_unit$30[12:0]$9950 \logical_op__fn_unit$30$next
sync posedge \coresync_clk
- update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10036
+ update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$9950
end
- attribute \src "libresoc.v:171941.3-171942.77"
- process $proc$libresoc.v:171941$10037
+ attribute \src "libresoc.v:169742.3-169743.77"
+ process $proc$libresoc.v:169742$9951
assign { } { }
- assign $0\logical_op__imm_data__data$31[63:0]$10038 \logical_op__imm_data__data$31$next
+ assign $0\logical_op__imm_data__data$31[63:0]$9952 \logical_op__imm_data__data$31$next
sync posedge \coresync_clk
- update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10038
+ update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9952
end
- attribute \src "libresoc.v:171943.3-171944.73"
- process $proc$libresoc.v:171943$10039
+ attribute \src "libresoc.v:169744.3-169745.73"
+ process $proc$libresoc.v:169744$9953
assign { } { }
- assign $0\logical_op__imm_data__ok$32[0:0]$10040 \logical_op__imm_data__ok$32$next
+ assign $0\logical_op__imm_data__ok$32[0:0]$9954 \logical_op__imm_data__ok$32$next
sync posedge \coresync_clk
- update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10040
+ update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9954
end
- attribute \src "libresoc.v:171945.3-171946.61"
- process $proc$libresoc.v:171945$10041
+ attribute \src "libresoc.v:169746.3-169747.61"
+ process $proc$libresoc.v:169746$9955
assign { } { }
- assign $0\logical_op__rc__rc$33[0:0]$10042 \logical_op__rc__rc$33$next
+ assign $0\logical_op__rc__rc$33[0:0]$9956 \logical_op__rc__rc$33$next
sync posedge \coresync_clk
- update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10042
+ update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9956
end
- attribute \src "libresoc.v:171947.3-171948.61"
- process $proc$libresoc.v:171947$10043
+ attribute \src "libresoc.v:169748.3-169749.61"
+ process $proc$libresoc.v:169748$9957
assign { } { }
- assign $0\logical_op__rc__ok$34[0:0]$10044 \logical_op__rc__ok$34$next
+ assign $0\logical_op__rc__ok$34[0:0]$9958 \logical_op__rc__ok$34$next
sync posedge \coresync_clk
- update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10044
+ update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9958
end
- attribute \src "libresoc.v:171949.3-171950.61"
- process $proc$libresoc.v:171949$10045
+ attribute \src "libresoc.v:169750.3-169751.61"
+ process $proc$libresoc.v:169750$9959
assign { } { }
- assign $0\logical_op__oe__oe$35[0:0]$10046 \logical_op__oe__oe$35$next
+ assign $0\logical_op__oe__oe$35[0:0]$9960 \logical_op__oe__oe$35$next
sync posedge \coresync_clk
- update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10046
+ update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9960
end
- attribute \src "libresoc.v:171951.3-171952.61"
- process $proc$libresoc.v:171951$10047
+ attribute \src "libresoc.v:169752.3-169753.61"
+ process $proc$libresoc.v:169752$9961
assign { } { }
- assign $0\logical_op__oe__ok$36[0:0]$10048 \logical_op__oe__ok$36$next
+ assign $0\logical_op__oe__ok$36[0:0]$9962 \logical_op__oe__ok$36$next
sync posedge \coresync_clk
- update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10048
+ update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9962
end
- attribute \src "libresoc.v:171953.3-171954.67"
- process $proc$libresoc.v:171953$10049
+ attribute \src "libresoc.v:169754.3-169755.67"
+ process $proc$libresoc.v:169754$9963
assign { } { }
- assign $0\logical_op__invert_in$37[0:0]$10050 \logical_op__invert_in$37$next
+ assign $0\logical_op__invert_in$37[0:0]$9964 \logical_op__invert_in$37$next
sync posedge \coresync_clk
- update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10050
+ update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9964
end
- attribute \src "libresoc.v:171955.3-171956.61"
- process $proc$libresoc.v:171955$10051
+ attribute \src "libresoc.v:169756.3-169757.61"
+ process $proc$libresoc.v:169756$9965
assign { } { }
- assign $0\logical_op__zero_a$38[0:0]$10052 \logical_op__zero_a$38$next
+ assign $0\logical_op__zero_a$38[0:0]$9966 \logical_op__zero_a$38$next
sync posedge \coresync_clk
- update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10052
+ update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9966
end
- attribute \src "libresoc.v:171957.3-171958.71"
- process $proc$libresoc.v:171957$10053
+ attribute \src "libresoc.v:169758.3-169759.71"
+ process $proc$libresoc.v:169758$9967
assign { } { }
- assign $0\logical_op__input_carry$39[1:0]$10054 \logical_op__input_carry$39$next
+ assign $0\logical_op__input_carry$39[1:0]$9968 \logical_op__input_carry$39$next
sync posedge \coresync_clk
- update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10054
+ update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9968
end
- attribute \src "libresoc.v:171959.3-171960.69"
- process $proc$libresoc.v:171959$10055
+ attribute \src "libresoc.v:169760.3-169761.69"
+ process $proc$libresoc.v:169760$9969
assign { } { }
- assign $0\logical_op__invert_out$40[0:0]$10056 \logical_op__invert_out$40$next
+ assign $0\logical_op__invert_out$40[0:0]$9970 \logical_op__invert_out$40$next
sync posedge \coresync_clk
- update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10056
+ update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9970
end
- attribute \src "libresoc.v:171961.3-171962.67"
- process $proc$libresoc.v:171961$10057
+ attribute \src "libresoc.v:169762.3-169763.67"
+ process $proc$libresoc.v:169762$9971
assign { } { }
- assign $0\logical_op__write_cr0$41[0:0]$10058 \logical_op__write_cr0$41$next
+ assign $0\logical_op__write_cr0$41[0:0]$9972 \logical_op__write_cr0$41$next
sync posedge \coresync_clk
- update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10058
+ update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9972
end
- attribute \src "libresoc.v:171963.3-171964.73"
- process $proc$libresoc.v:171963$10059
+ attribute \src "libresoc.v:169764.3-169765.73"
+ process $proc$libresoc.v:169764$9973
assign { } { }
- assign $0\logical_op__output_carry$42[0:0]$10060 \logical_op__output_carry$42$next
+ assign $0\logical_op__output_carry$42[0:0]$9974 \logical_op__output_carry$42$next
sync posedge \coresync_clk
- update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10060
+ update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9974
end
- attribute \src "libresoc.v:171965.3-171966.65"
- process $proc$libresoc.v:171965$10061
+ attribute \src "libresoc.v:169766.3-169767.65"
+ process $proc$libresoc.v:169766$9975
assign { } { }
- assign $0\logical_op__is_32bit$43[0:0]$10062 \logical_op__is_32bit$43$next
+ assign $0\logical_op__is_32bit$43[0:0]$9976 \logical_op__is_32bit$43$next
sync posedge \coresync_clk
- update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10062
+ update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9976
end
- attribute \src "libresoc.v:171967.3-171968.67"
- process $proc$libresoc.v:171967$10063
+ attribute \src "libresoc.v:169768.3-169769.67"
+ process $proc$libresoc.v:169768$9977
assign { } { }
- assign $0\logical_op__is_signed$44[0:0]$10064 \logical_op__is_signed$44$next
+ assign $0\logical_op__is_signed$44[0:0]$9978 \logical_op__is_signed$44$next
sync posedge \coresync_clk
- update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10064
+ update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9978
end
- attribute \src "libresoc.v:171969.3-171970.65"
- process $proc$libresoc.v:171969$10065
+ attribute \src "libresoc.v:169770.3-169771.65"
+ process $proc$libresoc.v:169770$9979
assign { } { }
- assign $0\logical_op__data_len$45[3:0]$10066 \logical_op__data_len$45$next
+ assign $0\logical_op__data_len$45[3:0]$9980 \logical_op__data_len$45$next
sync posedge \coresync_clk
- update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10066
+ update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9980
end
- attribute \src "libresoc.v:171971.3-171972.57"
- process $proc$libresoc.v:171971$10067
+ attribute \src "libresoc.v:169772.3-169773.57"
+ process $proc$libresoc.v:169772$9981
assign { } { }
- assign $0\logical_op__insn$46[31:0]$10068 \logical_op__insn$46$next
+ assign $0\logical_op__insn$46[31:0]$9982 \logical_op__insn$46$next
sync posedge \coresync_clk
- update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10068
+ update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9982
end
- attribute \src "libresoc.v:171973.3-171974.35"
- process $proc$libresoc.v:171973$10069
+ attribute \src "libresoc.v:169774.3-169775.35"
+ process $proc$libresoc.v:169774$9983
assign { } { }
- assign $0\muxid$28[1:0]$10070 \muxid$28$next
+ assign $0\muxid$28[1:0]$9984 \muxid$28$next
sync posedge \coresync_clk
- update \muxid$28 $0\muxid$28[1:0]$10070
+ update \muxid$28 $0\muxid$28[1:0]$9984
end
- attribute \src "libresoc.v:171975.3-171976.27"
- process $proc$libresoc.v:171975$10071
+ attribute \src "libresoc.v:169776.3-169777.27"
+ process $proc$libresoc.v:169776$9985
assign { } { }
assign $0\empty[0:0] \empty$next
sync posedge \coresync_clk
update \empty $0\empty[0:0]
end
- attribute \src "libresoc.v:171977.3-171978.75"
- process $proc$libresoc.v:171977$10072
+ attribute \src "libresoc.v:169778.3-169779.75"
+ process $proc$libresoc.v:169778$9986
assign { } { }
assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next
sync posedge \coresync_clk
update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:171979.3-171980.65"
- process $proc$libresoc.v:171979$10073
+ attribute \src "libresoc.v:169780.3-169781.65"
+ process $proc$libresoc.v:169780$9987
assign { } { }
assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next
sync posedge \coresync_clk
update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0]
end
- attribute \src "libresoc.v:172001.3-172009.6"
- process $proc$libresoc.v:172001$10074
+ attribute \src "libresoc.v:169802.3-169810.6"
+ process $proc$libresoc.v:169802$9988
assign { } { }
assign { } { }
- assign $0\saved_state_q_bits_known$next[6:0]$10075 $1\saved_state_q_bits_known$next[6:0]$10076
- attribute \src "libresoc.v:172002.5-172002.29"
+ assign $0\saved_state_q_bits_known$next[6:0]$9989 $1\saved_state_q_bits_known$next[6:0]$9990
+ attribute \src "libresoc.v:169803.5-169803.29"
switch \initial
- attribute \src "libresoc.v:172002.9-172002.17"
+ attribute \src "libresoc.v:169803.9-169803.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\saved_state_q_bits_known$next[6:0]$10076 7'0000000
+ assign $1\saved_state_q_bits_known$next[6:0]$9990 7'0000000
case
- assign $1\saved_state_q_bits_known$next[6:0]$10076 \div_state_next_o_q_bits_known
+ assign $1\saved_state_q_bits_known$next[6:0]$9990 \div_state_next_o_q_bits_known
end
sync always
- update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10075
+ update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9989
end
- attribute \src "libresoc.v:172010.3-172018.6"
- process $proc$libresoc.v:172010$10077
+ attribute \src "libresoc.v:169811.3-169819.6"
+ process $proc$libresoc.v:169811$9991
assign { } { }
assign { } { }
- assign $0\saved_state_dividend_quotient$next[127:0]$10078 $1\saved_state_dividend_quotient$next[127:0]$10079
- attribute \src "libresoc.v:172011.5-172011.29"
+ assign $0\saved_state_dividend_quotient$next[127:0]$9992 $1\saved_state_dividend_quotient$next[127:0]$9993
+ attribute \src "libresoc.v:169812.5-169812.29"
switch \initial
- attribute \src "libresoc.v:172011.9-172011.17"
+ attribute \src "libresoc.v:169812.9-169812.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\saved_state_dividend_quotient$next[127:0]$10079 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign $1\saved_state_dividend_quotient$next[127:0]$9993 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\saved_state_dividend_quotient$next[127:0]$10079 \div_state_next_o_dividend_quotient
+ assign $1\saved_state_dividend_quotient$next[127:0]$9993 \div_state_next_o_dividend_quotient
end
sync always
- update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10078
+ update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9992
end
- attribute \src "libresoc.v:172019.3-172030.6"
- process $proc$libresoc.v:172019$10080
+ attribute \src "libresoc.v:169820.3-169831.6"
+ process $proc$libresoc.v:169820$9994
assign { } { }
assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0]
- attribute \src "libresoc.v:172020.5-172020.29"
+ attribute \src "libresoc.v:169821.5-169821.29"
switch \initial
- attribute \src "libresoc.v:172020.9-172020.17"
+ attribute \src "libresoc.v:169821.9-169821.17"
case 1'1
case
end
sync always
update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0]
end
- attribute \src "libresoc.v:172031.3-172042.6"
- process $proc$libresoc.v:172031$10081
+ attribute \src "libresoc.v:169832.3-169843.6"
+ process $proc$libresoc.v:169832$9995
assign { } { }
assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0]
- attribute \src "libresoc.v:172032.5-172032.29"
+ attribute \src "libresoc.v:169833.5-169833.29"
switch \initial
- attribute \src "libresoc.v:172032.9-172032.17"
+ attribute \src "libresoc.v:169833.9-169833.17"
case 1'1
case
end
sync always
update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0]
end
- attribute \src "libresoc.v:172043.3-172054.6"
- process $proc$libresoc.v:172043$10082
+ attribute \src "libresoc.v:169844.3-169855.6"
+ process $proc$libresoc.v:169844$9996
assign { } { }
assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0]
- attribute \src "libresoc.v:172044.5-172044.29"
+ attribute \src "libresoc.v:169845.5-169845.29"
switch \initial
- attribute \src "libresoc.v:172044.9-172044.17"
+ attribute \src "libresoc.v:169845.9-169845.17"
case 1'1
case
end
sync always
update \div_state_next_divisor $0\div_state_next_divisor[63:0]
end
- attribute \src "libresoc.v:172055.3-172082.6"
- process $proc$libresoc.v:172055$10083
+ attribute \src "libresoc.v:169856.3-169883.6"
+ process $proc$libresoc.v:169856$9997
assign { } { }
assign { } { }
assign { } { }
- assign $0\empty$next[0:0]$10084 $4\empty$next[0:0]$10088
- attribute \src "libresoc.v:172056.5-172056.29"
+ assign $0\empty$next[0:0]$9998 $4\empty$next[0:0]$10002
+ attribute \src "libresoc.v:169857.5-169857.29"
switch \initial
- attribute \src "libresoc.v:172056.9-172056.17"
+ attribute \src "libresoc.v:169857.9-169857.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\empty$next[0:0]$10085 $2\empty$next[0:0]$10086
+ assign $1\empty$next[0:0]$9999 $2\empty$next[0:0]$10000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\empty$next[0:0]$10086 1'0
+ assign $2\empty$next[0:0]$10000 1'0
case
- assign $2\empty$next[0:0]$10086 \empty
+ assign $2\empty$next[0:0]$10000 \empty
end
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\empty$next[0:0]$10085 $3\empty$next[0:0]$10087
+ assign $1\empty$next[0:0]$9999 $3\empty$next[0:0]$10001
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
switch \$66
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\empty$next[0:0]$10087 1'1
+ assign $3\empty$next[0:0]$10001 1'1
case
- assign $3\empty$next[0:0]$10087 \empty
+ assign $3\empty$next[0:0]$10001 \empty
end
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\empty$next[0:0]$10088 1'1
+ assign $4\empty$next[0:0]$10002 1'1
case
- assign $4\empty$next[0:0]$10088 $1\empty$next[0:0]$10085
+ assign $4\empty$next[0:0]$10002 $1\empty$next[0:0]$9999
end
sync always
- update \empty$next $0\empty$next[0:0]$10084
+ update \empty$next $0\empty$next[0:0]$9998
end
- attribute \src "libresoc.v:172083.3-172097.6"
- process $proc$libresoc.v:172083$10089
+ attribute \src "libresoc.v:169884.3-169898.6"
+ process $proc$libresoc.v:169884$10003
assign { } { }
assign { } { }
- assign $0\muxid$28$next[1:0]$10090 $1\muxid$28$next[1:0]$10091
- attribute \src "libresoc.v:172084.5-172084.29"
+ assign $0\muxid$28$next[1:0]$10004 $1\muxid$28$next[1:0]$10005
+ attribute \src "libresoc.v:169885.5-169885.29"
switch \initial
- attribute \src "libresoc.v:172084.9-172084.17"
+ attribute \src "libresoc.v:169885.9-169885.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\muxid$28$next[1:0]$10091 $2\muxid$28$next[1:0]$10092
+ assign $1\muxid$28$next[1:0]$10005 $2\muxid$28$next[1:0]$10006
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\muxid$28$next[1:0]$10092 \muxid
+ assign $2\muxid$28$next[1:0]$10006 \muxid
case
- assign $2\muxid$28$next[1:0]$10092 \muxid$28
+ assign $2\muxid$28$next[1:0]$10006 \muxid$28
end
case
- assign $1\muxid$28$next[1:0]$10091 \muxid$28
+ assign $1\muxid$28$next[1:0]$10005 \muxid$28
end
sync always
- update \muxid$28$next $0\muxid$28$next[1:0]$10090
+ update \muxid$28$next $0\muxid$28$next[1:0]$10004
end
- attribute \src "libresoc.v:172098.3-172141.6"
- process $proc$libresoc.v:172098$10093
+ attribute \src "libresoc.v:169899.3-169942.6"
+ process $proc$libresoc.v:169899$10007
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\logical_op__data_len$45$next[3:0]$10094 $1\logical_op__data_len$45$next[3:0]$10112
- assign $0\logical_op__fn_unit$30$next[12:0]$10095 $1\logical_op__fn_unit$30$next[12:0]$10113
+ assign $0\logical_op__data_len$45$next[3:0]$10008 $1\logical_op__data_len$45$next[3:0]$10026
+ assign $0\logical_op__fn_unit$30$next[12:0]$10009 $1\logical_op__fn_unit$30$next[12:0]$10027
assign { } { }
assign { } { }
- assign $0\logical_op__input_carry$39$next[1:0]$10098 $1\logical_op__input_carry$39$next[1:0]$10116
- assign $0\logical_op__insn$46$next[31:0]$10099 $1\logical_op__insn$46$next[31:0]$10117
- assign $0\logical_op__insn_type$29$next[6:0]$10100 $1\logical_op__insn_type$29$next[6:0]$10118
- assign $0\logical_op__invert_in$37$next[0:0]$10101 $1\logical_op__invert_in$37$next[0:0]$10119
- assign $0\logical_op__invert_out$40$next[0:0]$10102 $1\logical_op__invert_out$40$next[0:0]$10120
- assign $0\logical_op__is_32bit$43$next[0:0]$10103 $1\logical_op__is_32bit$43$next[0:0]$10121
- assign $0\logical_op__is_signed$44$next[0:0]$10104 $1\logical_op__is_signed$44$next[0:0]$10122
+ assign $0\logical_op__input_carry$39$next[1:0]$10012 $1\logical_op__input_carry$39$next[1:0]$10030
+ assign $0\logical_op__insn$46$next[31:0]$10013 $1\logical_op__insn$46$next[31:0]$10031
+ assign $0\logical_op__insn_type$29$next[6:0]$10014 $1\logical_op__insn_type$29$next[6:0]$10032
+ assign $0\logical_op__invert_in$37$next[0:0]$10015 $1\logical_op__invert_in$37$next[0:0]$10033
+ assign $0\logical_op__invert_out$40$next[0:0]$10016 $1\logical_op__invert_out$40$next[0:0]$10034
+ assign $0\logical_op__is_32bit$43$next[0:0]$10017 $1\logical_op__is_32bit$43$next[0:0]$10035
+ assign $0\logical_op__is_signed$44$next[0:0]$10018 $1\logical_op__is_signed$44$next[0:0]$10036
assign { } { }
assign { } { }
- assign $0\logical_op__output_carry$42$next[0:0]$10107 $1\logical_op__output_carry$42$next[0:0]$10125
+ assign $0\logical_op__output_carry$42$next[0:0]$10021 $1\logical_op__output_carry$42$next[0:0]$10039
assign { } { }
assign { } { }
- assign $0\logical_op__write_cr0$41$next[0:0]$10110 $1\logical_op__write_cr0$41$next[0:0]$10128
- assign $0\logical_op__zero_a$38$next[0:0]$10111 $1\logical_op__zero_a$38$next[0:0]$10129
- assign $0\logical_op__imm_data__data$31$next[63:0]$10096 $3\logical_op__imm_data__data$31$next[63:0]$10148
- assign $0\logical_op__imm_data__ok$32$next[0:0]$10097 $3\logical_op__imm_data__ok$32$next[0:0]$10149
- assign $0\logical_op__oe__oe$35$next[0:0]$10105 $3\logical_op__oe__oe$35$next[0:0]$10150
- assign $0\logical_op__oe__ok$36$next[0:0]$10106 $3\logical_op__oe__ok$36$next[0:0]$10151
- assign $0\logical_op__rc__ok$34$next[0:0]$10108 $3\logical_op__rc__ok$34$next[0:0]$10152
- assign $0\logical_op__rc__rc$33$next[0:0]$10109 $3\logical_op__rc__rc$33$next[0:0]$10153
- attribute \src "libresoc.v:172099.5-172099.29"
+ assign $0\logical_op__write_cr0$41$next[0:0]$10024 $1\logical_op__write_cr0$41$next[0:0]$10042
+ assign $0\logical_op__zero_a$38$next[0:0]$10025 $1\logical_op__zero_a$38$next[0:0]$10043
+ assign $0\logical_op__imm_data__data$31$next[63:0]$10010 $3\logical_op__imm_data__data$31$next[63:0]$10062
+ assign $0\logical_op__imm_data__ok$32$next[0:0]$10011 $3\logical_op__imm_data__ok$32$next[0:0]$10063
+ assign $0\logical_op__oe__oe$35$next[0:0]$10019 $3\logical_op__oe__oe$35$next[0:0]$10064
+ assign $0\logical_op__oe__ok$36$next[0:0]$10020 $3\logical_op__oe__ok$36$next[0:0]$10065
+ assign $0\logical_op__rc__ok$34$next[0:0]$10022 $3\logical_op__rc__ok$34$next[0:0]$10066
+ assign $0\logical_op__rc__rc$33$next[0:0]$10023 $3\logical_op__rc__rc$33$next[0:0]$10067
+ attribute \src "libresoc.v:169900.5-169900.29"
switch \initial
- attribute \src "libresoc.v:172099.9-172099.17"
+ attribute \src "libresoc.v:169900.9-169900.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\logical_op__data_len$45$next[3:0]$10112 $2\logical_op__data_len$45$next[3:0]$10130
- assign $1\logical_op__fn_unit$30$next[12:0]$10113 $2\logical_op__fn_unit$30$next[12:0]$10131
- assign $1\logical_op__imm_data__data$31$next[63:0]$10114 $2\logical_op__imm_data__data$31$next[63:0]$10132
- assign $1\logical_op__imm_data__ok$32$next[0:0]$10115 $2\logical_op__imm_data__ok$32$next[0:0]$10133
- assign $1\logical_op__input_carry$39$next[1:0]$10116 $2\logical_op__input_carry$39$next[1:0]$10134
- assign $1\logical_op__insn$46$next[31:0]$10117 $2\logical_op__insn$46$next[31:0]$10135
- assign $1\logical_op__insn_type$29$next[6:0]$10118 $2\logical_op__insn_type$29$next[6:0]$10136
- assign $1\logical_op__invert_in$37$next[0:0]$10119 $2\logical_op__invert_in$37$next[0:0]$10137
- assign $1\logical_op__invert_out$40$next[0:0]$10120 $2\logical_op__invert_out$40$next[0:0]$10138
- assign $1\logical_op__is_32bit$43$next[0:0]$10121 $2\logical_op__is_32bit$43$next[0:0]$10139
- assign $1\logical_op__is_signed$44$next[0:0]$10122 $2\logical_op__is_signed$44$next[0:0]$10140
- assign $1\logical_op__oe__oe$35$next[0:0]$10123 $2\logical_op__oe__oe$35$next[0:0]$10141
- assign $1\logical_op__oe__ok$36$next[0:0]$10124 $2\logical_op__oe__ok$36$next[0:0]$10142
- assign $1\logical_op__output_carry$42$next[0:0]$10125 $2\logical_op__output_carry$42$next[0:0]$10143
- assign $1\logical_op__rc__ok$34$next[0:0]$10126 $2\logical_op__rc__ok$34$next[0:0]$10144
- assign $1\logical_op__rc__rc$33$next[0:0]$10127 $2\logical_op__rc__rc$33$next[0:0]$10145
- assign $1\logical_op__write_cr0$41$next[0:0]$10128 $2\logical_op__write_cr0$41$next[0:0]$10146
- assign $1\logical_op__zero_a$38$next[0:0]$10129 $2\logical_op__zero_a$38$next[0:0]$10147
+ assign $1\logical_op__data_len$45$next[3:0]$10026 $2\logical_op__data_len$45$next[3:0]$10044
+ assign $1\logical_op__fn_unit$30$next[12:0]$10027 $2\logical_op__fn_unit$30$next[12:0]$10045
+ assign $1\logical_op__imm_data__data$31$next[63:0]$10028 $2\logical_op__imm_data__data$31$next[63:0]$10046
+ assign $1\logical_op__imm_data__ok$32$next[0:0]$10029 $2\logical_op__imm_data__ok$32$next[0:0]$10047
+ assign $1\logical_op__input_carry$39$next[1:0]$10030 $2\logical_op__input_carry$39$next[1:0]$10048
+ assign $1\logical_op__insn$46$next[31:0]$10031 $2\logical_op__insn$46$next[31:0]$10049
+ assign $1\logical_op__insn_type$29$next[6:0]$10032 $2\logical_op__insn_type$29$next[6:0]$10050
+ assign $1\logical_op__invert_in$37$next[0:0]$10033 $2\logical_op__invert_in$37$next[0:0]$10051
+ assign $1\logical_op__invert_out$40$next[0:0]$10034 $2\logical_op__invert_out$40$next[0:0]$10052
+ assign $1\logical_op__is_32bit$43$next[0:0]$10035 $2\logical_op__is_32bit$43$next[0:0]$10053
+ assign $1\logical_op__is_signed$44$next[0:0]$10036 $2\logical_op__is_signed$44$next[0:0]$10054
+ assign $1\logical_op__oe__oe$35$next[0:0]$10037 $2\logical_op__oe__oe$35$next[0:0]$10055
+ assign $1\logical_op__oe__ok$36$next[0:0]$10038 $2\logical_op__oe__ok$36$next[0:0]$10056
+ assign $1\logical_op__output_carry$42$next[0:0]$10039 $2\logical_op__output_carry$42$next[0:0]$10057
+ assign $1\logical_op__rc__ok$34$next[0:0]$10040 $2\logical_op__rc__ok$34$next[0:0]$10058
+ assign $1\logical_op__rc__rc$33$next[0:0]$10041 $2\logical_op__rc__rc$33$next[0:0]$10059
+ assign $1\logical_op__write_cr0$41$next[0:0]$10042 $2\logical_op__write_cr0$41$next[0:0]$10060
+ assign $1\logical_op__zero_a$38$next[0:0]$10043 $2\logical_op__zero_a$38$next[0:0]$10061
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $2\logical_op__insn$46$next[31:0]$10135 $2\logical_op__data_len$45$next[3:0]$10130 $2\logical_op__is_signed$44$next[0:0]$10140 $2\logical_op__is_32bit$43$next[0:0]$10139 $2\logical_op__output_carry$42$next[0:0]$10143 $2\logical_op__write_cr0$41$next[0:0]$10146 $2\logical_op__invert_out$40$next[0:0]$10138 $2\logical_op__input_carry$39$next[1:0]$10134 $2\logical_op__zero_a$38$next[0:0]$10147 $2\logical_op__invert_in$37$next[0:0]$10137 $2\logical_op__oe__ok$36$next[0:0]$10142 $2\logical_op__oe__oe$35$next[0:0]$10141 $2\logical_op__rc__ok$34$next[0:0]$10144 $2\logical_op__rc__rc$33$next[0:0]$10145 $2\logical_op__imm_data__ok$32$next[0:0]$10133 $2\logical_op__imm_data__data$31$next[63:0]$10132 $2\logical_op__fn_unit$30$next[12:0]$10131 $2\logical_op__insn_type$29$next[6:0]$10136 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
+ assign { $2\logical_op__insn$46$next[31:0]$10049 $2\logical_op__data_len$45$next[3:0]$10044 $2\logical_op__is_signed$44$next[0:0]$10054 $2\logical_op__is_32bit$43$next[0:0]$10053 $2\logical_op__output_carry$42$next[0:0]$10057 $2\logical_op__write_cr0$41$next[0:0]$10060 $2\logical_op__invert_out$40$next[0:0]$10052 $2\logical_op__input_carry$39$next[1:0]$10048 $2\logical_op__zero_a$38$next[0:0]$10061 $2\logical_op__invert_in$37$next[0:0]$10051 $2\logical_op__oe__ok$36$next[0:0]$10056 $2\logical_op__oe__oe$35$next[0:0]$10055 $2\logical_op__rc__ok$34$next[0:0]$10058 $2\logical_op__rc__rc$33$next[0:0]$10059 $2\logical_op__imm_data__ok$32$next[0:0]$10047 $2\logical_op__imm_data__data$31$next[63:0]$10046 $2\logical_op__fn_unit$30$next[12:0]$10045 $2\logical_op__insn_type$29$next[6:0]$10050 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
case
- assign $2\logical_op__data_len$45$next[3:0]$10130 \logical_op__data_len$45
- assign $2\logical_op__fn_unit$30$next[12:0]$10131 \logical_op__fn_unit$30
- assign $2\logical_op__imm_data__data$31$next[63:0]$10132 \logical_op__imm_data__data$31
- assign $2\logical_op__imm_data__ok$32$next[0:0]$10133 \logical_op__imm_data__ok$32
- assign $2\logical_op__input_carry$39$next[1:0]$10134 \logical_op__input_carry$39
- assign $2\logical_op__insn$46$next[31:0]$10135 \logical_op__insn$46
- assign $2\logical_op__insn_type$29$next[6:0]$10136 \logical_op__insn_type$29
- assign $2\logical_op__invert_in$37$next[0:0]$10137 \logical_op__invert_in$37
- assign $2\logical_op__invert_out$40$next[0:0]$10138 \logical_op__invert_out$40
- assign $2\logical_op__is_32bit$43$next[0:0]$10139 \logical_op__is_32bit$43
- assign $2\logical_op__is_signed$44$next[0:0]$10140 \logical_op__is_signed$44
- assign $2\logical_op__oe__oe$35$next[0:0]$10141 \logical_op__oe__oe$35
- assign $2\logical_op__oe__ok$36$next[0:0]$10142 \logical_op__oe__ok$36
- assign $2\logical_op__output_carry$42$next[0:0]$10143 \logical_op__output_carry$42
- assign $2\logical_op__rc__ok$34$next[0:0]$10144 \logical_op__rc__ok$34
- assign $2\logical_op__rc__rc$33$next[0:0]$10145 \logical_op__rc__rc$33
- assign $2\logical_op__write_cr0$41$next[0:0]$10146 \logical_op__write_cr0$41
- assign $2\logical_op__zero_a$38$next[0:0]$10147 \logical_op__zero_a$38
+ assign $2\logical_op__data_len$45$next[3:0]$10044 \logical_op__data_len$45
+ assign $2\logical_op__fn_unit$30$next[12:0]$10045 \logical_op__fn_unit$30
+ assign $2\logical_op__imm_data__data$31$next[63:0]$10046 \logical_op__imm_data__data$31
+ assign $2\logical_op__imm_data__ok$32$next[0:0]$10047 \logical_op__imm_data__ok$32
+ assign $2\logical_op__input_carry$39$next[1:0]$10048 \logical_op__input_carry$39
+ assign $2\logical_op__insn$46$next[31:0]$10049 \logical_op__insn$46
+ assign $2\logical_op__insn_type$29$next[6:0]$10050 \logical_op__insn_type$29
+ assign $2\logical_op__invert_in$37$next[0:0]$10051 \logical_op__invert_in$37
+ assign $2\logical_op__invert_out$40$next[0:0]$10052 \logical_op__invert_out$40
+ assign $2\logical_op__is_32bit$43$next[0:0]$10053 \logical_op__is_32bit$43
+ assign $2\logical_op__is_signed$44$next[0:0]$10054 \logical_op__is_signed$44
+ assign $2\logical_op__oe__oe$35$next[0:0]$10055 \logical_op__oe__oe$35
+ assign $2\logical_op__oe__ok$36$next[0:0]$10056 \logical_op__oe__ok$36
+ assign $2\logical_op__output_carry$42$next[0:0]$10057 \logical_op__output_carry$42
+ assign $2\logical_op__rc__ok$34$next[0:0]$10058 \logical_op__rc__ok$34
+ assign $2\logical_op__rc__rc$33$next[0:0]$10059 \logical_op__rc__rc$33
+ assign $2\logical_op__write_cr0$41$next[0:0]$10060 \logical_op__write_cr0$41
+ assign $2\logical_op__zero_a$38$next[0:0]$10061 \logical_op__zero_a$38
end
case
- assign $1\logical_op__data_len$45$next[3:0]$10112 \logical_op__data_len$45
- assign $1\logical_op__fn_unit$30$next[12:0]$10113 \logical_op__fn_unit$30
- assign $1\logical_op__imm_data__data$31$next[63:0]$10114 \logical_op__imm_data__data$31
- assign $1\logical_op__imm_data__ok$32$next[0:0]$10115 \logical_op__imm_data__ok$32
- assign $1\logical_op__input_carry$39$next[1:0]$10116 \logical_op__input_carry$39
- assign $1\logical_op__insn$46$next[31:0]$10117 \logical_op__insn$46
- assign $1\logical_op__insn_type$29$next[6:0]$10118 \logical_op__insn_type$29
- assign $1\logical_op__invert_in$37$next[0:0]$10119 \logical_op__invert_in$37
- assign $1\logical_op__invert_out$40$next[0:0]$10120 \logical_op__invert_out$40
- assign $1\logical_op__is_32bit$43$next[0:0]$10121 \logical_op__is_32bit$43
- assign $1\logical_op__is_signed$44$next[0:0]$10122 \logical_op__is_signed$44
- assign $1\logical_op__oe__oe$35$next[0:0]$10123 \logical_op__oe__oe$35
- assign $1\logical_op__oe__ok$36$next[0:0]$10124 \logical_op__oe__ok$36
- assign $1\logical_op__output_carry$42$next[0:0]$10125 \logical_op__output_carry$42
- assign $1\logical_op__rc__ok$34$next[0:0]$10126 \logical_op__rc__ok$34
- assign $1\logical_op__rc__rc$33$next[0:0]$10127 \logical_op__rc__rc$33
- assign $1\logical_op__write_cr0$41$next[0:0]$10128 \logical_op__write_cr0$41
- assign $1\logical_op__zero_a$38$next[0:0]$10129 \logical_op__zero_a$38
+ assign $1\logical_op__data_len$45$next[3:0]$10026 \logical_op__data_len$45
+ assign $1\logical_op__fn_unit$30$next[12:0]$10027 \logical_op__fn_unit$30
+ assign $1\logical_op__imm_data__data$31$next[63:0]$10028 \logical_op__imm_data__data$31
+ assign $1\logical_op__imm_data__ok$32$next[0:0]$10029 \logical_op__imm_data__ok$32
+ assign $1\logical_op__input_carry$39$next[1:0]$10030 \logical_op__input_carry$39
+ assign $1\logical_op__insn$46$next[31:0]$10031 \logical_op__insn$46
+ assign $1\logical_op__insn_type$29$next[6:0]$10032 \logical_op__insn_type$29
+ assign $1\logical_op__invert_in$37$next[0:0]$10033 \logical_op__invert_in$37
+ assign $1\logical_op__invert_out$40$next[0:0]$10034 \logical_op__invert_out$40
+ assign $1\logical_op__is_32bit$43$next[0:0]$10035 \logical_op__is_32bit$43
+ assign $1\logical_op__is_signed$44$next[0:0]$10036 \logical_op__is_signed$44
+ assign $1\logical_op__oe__oe$35$next[0:0]$10037 \logical_op__oe__oe$35
+ assign $1\logical_op__oe__ok$36$next[0:0]$10038 \logical_op__oe__ok$36
+ assign $1\logical_op__output_carry$42$next[0:0]$10039 \logical_op__output_carry$42
+ assign $1\logical_op__rc__ok$34$next[0:0]$10040 \logical_op__rc__ok$34
+ assign $1\logical_op__rc__rc$33$next[0:0]$10041 \logical_op__rc__rc$33
+ assign $1\logical_op__write_cr0$41$next[0:0]$10042 \logical_op__write_cr0$41
+ assign $1\logical_op__zero_a$38$next[0:0]$10043 \logical_op__zero_a$38
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\logical_op__imm_data__data$31$next[63:0]$10148 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\logical_op__imm_data__ok$32$next[0:0]$10149 1'0
- assign $3\logical_op__rc__rc$33$next[0:0]$10153 1'0
- assign $3\logical_op__rc__ok$34$next[0:0]$10152 1'0
- assign $3\logical_op__oe__oe$35$next[0:0]$10150 1'0
- assign $3\logical_op__oe__ok$36$next[0:0]$10151 1'0
+ assign $3\logical_op__imm_data__data$31$next[63:0]$10062 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\logical_op__imm_data__ok$32$next[0:0]$10063 1'0
+ assign $3\logical_op__rc__rc$33$next[0:0]$10067 1'0
+ assign $3\logical_op__rc__ok$34$next[0:0]$10066 1'0
+ assign $3\logical_op__oe__oe$35$next[0:0]$10064 1'0
+ assign $3\logical_op__oe__ok$36$next[0:0]$10065 1'0
case
- assign $3\logical_op__imm_data__data$31$next[63:0]$10148 $1\logical_op__imm_data__data$31$next[63:0]$10114
- assign $3\logical_op__imm_data__ok$32$next[0:0]$10149 $1\logical_op__imm_data__ok$32$next[0:0]$10115
- assign $3\logical_op__oe__oe$35$next[0:0]$10150 $1\logical_op__oe__oe$35$next[0:0]$10123
- assign $3\logical_op__oe__ok$36$next[0:0]$10151 $1\logical_op__oe__ok$36$next[0:0]$10124
- assign $3\logical_op__rc__ok$34$next[0:0]$10152 $1\logical_op__rc__ok$34$next[0:0]$10126
- assign $3\logical_op__rc__rc$33$next[0:0]$10153 $1\logical_op__rc__rc$33$next[0:0]$10127
+ assign $3\logical_op__imm_data__data$31$next[63:0]$10062 $1\logical_op__imm_data__data$31$next[63:0]$10028
+ assign $3\logical_op__imm_data__ok$32$next[0:0]$10063 $1\logical_op__imm_data__ok$32$next[0:0]$10029
+ assign $3\logical_op__oe__oe$35$next[0:0]$10064 $1\logical_op__oe__oe$35$next[0:0]$10037
+ assign $3\logical_op__oe__ok$36$next[0:0]$10065 $1\logical_op__oe__ok$36$next[0:0]$10038
+ assign $3\logical_op__rc__ok$34$next[0:0]$10066 $1\logical_op__rc__ok$34$next[0:0]$10040
+ assign $3\logical_op__rc__rc$33$next[0:0]$10067 $1\logical_op__rc__rc$33$next[0:0]$10041
end
sync always
- update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10094
- update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10095
- update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10096
- update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10097
- update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10098
- update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10099
- update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10100
- update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10101
- update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10102
- update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10103
- update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10104
- update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10105
- update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10106
- update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10107
- update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10108
- update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10109
- update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10110
- update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10111
+ update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10008
+ update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10009
+ update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10010
+ update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10011
+ update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10012
+ update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10013
+ update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10014
+ update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10015
+ update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10016
+ update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10017
+ update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10018
+ update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10019
+ update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10020
+ update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10021
+ update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10022
+ update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10023
+ update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10024
+ update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10025
end
- attribute \src "libresoc.v:172142.3-172156.6"
- process $proc$libresoc.v:172142$10154
+ attribute \src "libresoc.v:169943.3-169957.6"
+ process $proc$libresoc.v:169943$10068
assign { } { }
assign { } { }
- assign $0\ra$47$next[63:0]$10155 $1\ra$47$next[63:0]$10156
- attribute \src "libresoc.v:172143.5-172143.29"
+ assign $0\ra$47$next[63:0]$10069 $1\ra$47$next[63:0]$10070
+ attribute \src "libresoc.v:169944.5-169944.29"
switch \initial
- attribute \src "libresoc.v:172143.9-172143.17"
+ attribute \src "libresoc.v:169944.9-169944.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ra$47$next[63:0]$10156 $2\ra$47$next[63:0]$10157
+ assign $1\ra$47$next[63:0]$10070 $2\ra$47$next[63:0]$10071
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ra$47$next[63:0]$10157 \ra
+ assign $2\ra$47$next[63:0]$10071 \ra
case
- assign $2\ra$47$next[63:0]$10157 \ra$47
+ assign $2\ra$47$next[63:0]$10071 \ra$47
end
case
- assign $1\ra$47$next[63:0]$10156 \ra$47
+ assign $1\ra$47$next[63:0]$10070 \ra$47
end
sync always
- update \ra$47$next $0\ra$47$next[63:0]$10155
+ update \ra$47$next $0\ra$47$next[63:0]$10069
end
- attribute \src "libresoc.v:172157.3-172171.6"
- process $proc$libresoc.v:172157$10158
+ attribute \src "libresoc.v:169958.3-169972.6"
+ process $proc$libresoc.v:169958$10072
assign { } { }
assign { } { }
- assign $0\rb$48$next[63:0]$10159 $1\rb$48$next[63:0]$10160
- attribute \src "libresoc.v:172158.5-172158.29"
+ assign $0\rb$48$next[63:0]$10073 $1\rb$48$next[63:0]$10074
+ attribute \src "libresoc.v:169959.5-169959.29"
switch \initial
- attribute \src "libresoc.v:172158.9-172158.17"
+ attribute \src "libresoc.v:169959.9-169959.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rb$48$next[63:0]$10160 $2\rb$48$next[63:0]$10161
+ assign $1\rb$48$next[63:0]$10074 $2\rb$48$next[63:0]$10075
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\rb$48$next[63:0]$10161 \rb
+ assign $2\rb$48$next[63:0]$10075 \rb
case
- assign $2\rb$48$next[63:0]$10161 \rb$48
+ assign $2\rb$48$next[63:0]$10075 \rb$48
end
case
- assign $1\rb$48$next[63:0]$10160 \rb$48
+ assign $1\rb$48$next[63:0]$10074 \rb$48
end
sync always
- update \rb$48$next $0\rb$48$next[63:0]$10159
+ update \rb$48$next $0\rb$48$next[63:0]$10073
end
- attribute \src "libresoc.v:172172.3-172186.6"
- process $proc$libresoc.v:172172$10162
+ attribute \src "libresoc.v:169973.3-169987.6"
+ process $proc$libresoc.v:169973$10076
assign { } { }
assign { } { }
- assign $0\xer_so$49$next[0:0]$10163 $1\xer_so$49$next[0:0]$10164
- attribute \src "libresoc.v:172173.5-172173.29"
+ assign $0\xer_so$49$next[0:0]$10077 $1\xer_so$49$next[0:0]$10078
+ attribute \src "libresoc.v:169974.5-169974.29"
switch \initial
- attribute \src "libresoc.v:172173.9-172173.17"
+ attribute \src "libresoc.v:169974.9-169974.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xer_so$49$next[0:0]$10164 $2\xer_so$49$next[0:0]$10165
+ assign $1\xer_so$49$next[0:0]$10078 $2\xer_so$49$next[0:0]$10079
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xer_so$49$next[0:0]$10165 \xer_so
+ assign $2\xer_so$49$next[0:0]$10079 \xer_so
case
- assign $2\xer_so$49$next[0:0]$10165 \xer_so$49
+ assign $2\xer_so$49$next[0:0]$10079 \xer_so$49
end
case
- assign $1\xer_so$49$next[0:0]$10164 \xer_so$49
+ assign $1\xer_so$49$next[0:0]$10078 \xer_so$49
end
sync always
- update \xer_so$49$next $0\xer_so$49$next[0:0]$10163
+ update \xer_so$49$next $0\xer_so$49$next[0:0]$10077
end
- attribute \src "libresoc.v:172187.3-172201.6"
- process $proc$libresoc.v:172187$10166
+ attribute \src "libresoc.v:169988.3-170002.6"
+ process $proc$libresoc.v:169988$10080
assign { } { }
assign { } { }
- assign $0\divisor_neg$50$next[0:0]$10167 $1\divisor_neg$50$next[0:0]$10168
- attribute \src "libresoc.v:172188.5-172188.29"
+ assign $0\divisor_neg$50$next[0:0]$10081 $1\divisor_neg$50$next[0:0]$10082
+ attribute \src "libresoc.v:169989.5-169989.29"
switch \initial
- attribute \src "libresoc.v:172188.9-172188.17"
+ attribute \src "libresoc.v:169989.9-169989.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\divisor_neg$50$next[0:0]$10168 $2\divisor_neg$50$next[0:0]$10169
+ assign $1\divisor_neg$50$next[0:0]$10082 $2\divisor_neg$50$next[0:0]$10083
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\divisor_neg$50$next[0:0]$10169 \divisor_neg
+ assign $2\divisor_neg$50$next[0:0]$10083 \divisor_neg
case
- assign $2\divisor_neg$50$next[0:0]$10169 \divisor_neg$50
+ assign $2\divisor_neg$50$next[0:0]$10083 \divisor_neg$50
end
case
- assign $1\divisor_neg$50$next[0:0]$10168 \divisor_neg$50
+ assign $1\divisor_neg$50$next[0:0]$10082 \divisor_neg$50
end
sync always
- update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10167
+ update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10081
end
- attribute \src "libresoc.v:172202.3-172216.6"
- process $proc$libresoc.v:172202$10170
+ attribute \src "libresoc.v:170003.3-170017.6"
+ process $proc$libresoc.v:170003$10084
assign { } { }
assign { } { }
- assign $0\dividend_neg$51$next[0:0]$10171 $1\dividend_neg$51$next[0:0]$10172
- attribute \src "libresoc.v:172203.5-172203.29"
+ assign $0\dividend_neg$51$next[0:0]$10085 $1\dividend_neg$51$next[0:0]$10086
+ attribute \src "libresoc.v:170004.5-170004.29"
switch \initial
- attribute \src "libresoc.v:172203.9-172203.17"
+ attribute \src "libresoc.v:170004.9-170004.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dividend_neg$51$next[0:0]$10172 $2\dividend_neg$51$next[0:0]$10173
+ assign $1\dividend_neg$51$next[0:0]$10086 $2\dividend_neg$51$next[0:0]$10087
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dividend_neg$51$next[0:0]$10173 \dividend_neg
+ assign $2\dividend_neg$51$next[0:0]$10087 \dividend_neg
case
- assign $2\dividend_neg$51$next[0:0]$10173 \dividend_neg$51
+ assign $2\dividend_neg$51$next[0:0]$10087 \dividend_neg$51
end
case
- assign $1\dividend_neg$51$next[0:0]$10172 \dividend_neg$51
+ assign $1\dividend_neg$51$next[0:0]$10086 \dividend_neg$51
end
sync always
- update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10171
+ update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10085
end
- attribute \src "libresoc.v:172217.3-172231.6"
- process $proc$libresoc.v:172217$10174
+ attribute \src "libresoc.v:170018.3-170032.6"
+ process $proc$libresoc.v:170018$10088
assign { } { }
assign { } { }
- assign $0\dive_abs_ov32$52$next[0:0]$10175 $1\dive_abs_ov32$52$next[0:0]$10176
- attribute \src "libresoc.v:172218.5-172218.29"
+ assign $0\dive_abs_ov32$52$next[0:0]$10089 $1\dive_abs_ov32$52$next[0:0]$10090
+ attribute \src "libresoc.v:170019.5-170019.29"
switch \initial
- attribute \src "libresoc.v:172218.9-172218.17"
+ attribute \src "libresoc.v:170019.9-170019.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dive_abs_ov32$52$next[0:0]$10176 $2\dive_abs_ov32$52$next[0:0]$10177
+ assign $1\dive_abs_ov32$52$next[0:0]$10090 $2\dive_abs_ov32$52$next[0:0]$10091
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dive_abs_ov32$52$next[0:0]$10177 \dive_abs_ov32
+ assign $2\dive_abs_ov32$52$next[0:0]$10091 \dive_abs_ov32
case
- assign $2\dive_abs_ov32$52$next[0:0]$10177 \dive_abs_ov32$52
+ assign $2\dive_abs_ov32$52$next[0:0]$10091 \dive_abs_ov32$52
end
case
- assign $1\dive_abs_ov32$52$next[0:0]$10176 \dive_abs_ov32$52
+ assign $1\dive_abs_ov32$52$next[0:0]$10090 \dive_abs_ov32$52
end
sync always
- update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10175
+ update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10089
end
- attribute \src "libresoc.v:172232.3-172246.6"
- process $proc$libresoc.v:172232$10178
+ attribute \src "libresoc.v:170033.3-170047.6"
+ process $proc$libresoc.v:170033$10092
assign { } { }
assign { } { }
- assign $0\dive_abs_ov64$53$next[0:0]$10179 $1\dive_abs_ov64$53$next[0:0]$10180
- attribute \src "libresoc.v:172233.5-172233.29"
+ assign $0\dive_abs_ov64$53$next[0:0]$10093 $1\dive_abs_ov64$53$next[0:0]$10094
+ attribute \src "libresoc.v:170034.5-170034.29"
switch \initial
- attribute \src "libresoc.v:172233.9-172233.17"
+ attribute \src "libresoc.v:170034.9-170034.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dive_abs_ov64$53$next[0:0]$10180 $2\dive_abs_ov64$53$next[0:0]$10181
+ assign $1\dive_abs_ov64$53$next[0:0]$10094 $2\dive_abs_ov64$53$next[0:0]$10095
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dive_abs_ov64$53$next[0:0]$10181 \dive_abs_ov64
+ assign $2\dive_abs_ov64$53$next[0:0]$10095 \dive_abs_ov64
case
- assign $2\dive_abs_ov64$53$next[0:0]$10181 \dive_abs_ov64$53
+ assign $2\dive_abs_ov64$53$next[0:0]$10095 \dive_abs_ov64$53
end
case
- assign $1\dive_abs_ov64$53$next[0:0]$10180 \dive_abs_ov64$53
+ assign $1\dive_abs_ov64$53$next[0:0]$10094 \dive_abs_ov64$53
end
sync always
- update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10179
+ update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10093
end
- attribute \src "libresoc.v:172247.3-172261.6"
- process $proc$libresoc.v:172247$10182
+ attribute \src "libresoc.v:170048.3-170062.6"
+ process $proc$libresoc.v:170048$10096
assign { } { }
assign { } { }
- assign $0\div_by_zero$54$next[0:0]$10183 $1\div_by_zero$54$next[0:0]$10184
- attribute \src "libresoc.v:172248.5-172248.29"
+ assign $0\div_by_zero$54$next[0:0]$10097 $1\div_by_zero$54$next[0:0]$10098
+ attribute \src "libresoc.v:170049.5-170049.29"
switch \initial
- attribute \src "libresoc.v:172248.9-172248.17"
+ attribute \src "libresoc.v:170049.9-170049.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\div_by_zero$54$next[0:0]$10184 $2\div_by_zero$54$next[0:0]$10185
+ assign $1\div_by_zero$54$next[0:0]$10098 $2\div_by_zero$54$next[0:0]$10099
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\div_by_zero$54$next[0:0]$10185 \div_by_zero
+ assign $2\div_by_zero$54$next[0:0]$10099 \div_by_zero
case
- assign $2\div_by_zero$54$next[0:0]$10185 \div_by_zero$54
+ assign $2\div_by_zero$54$next[0:0]$10099 \div_by_zero$54
end
case
- assign $1\div_by_zero$54$next[0:0]$10184 \div_by_zero$54
+ assign $1\div_by_zero$54$next[0:0]$10098 \div_by_zero$54
end
sync always
- update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10183
+ update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10097
end
- attribute \src "libresoc.v:172262.3-172276.6"
- process $proc$libresoc.v:172262$10186
+ attribute \src "libresoc.v:170063.3-170077.6"
+ process $proc$libresoc.v:170063$10100
assign { } { }
assign { } { }
- assign $0\dividend$68$next[127:0]$10187 $1\dividend$68$next[127:0]$10188
- attribute \src "libresoc.v:172263.5-172263.29"
+ assign $0\dividend$68$next[127:0]$10101 $1\dividend$68$next[127:0]$10102
+ attribute \src "libresoc.v:170064.5-170064.29"
switch \initial
- attribute \src "libresoc.v:172263.9-172263.17"
+ attribute \src "libresoc.v:170064.9-170064.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dividend$68$next[127:0]$10188 $2\dividend$68$next[127:0]$10189
+ assign $1\dividend$68$next[127:0]$10102 $2\dividend$68$next[127:0]$10103
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dividend$68$next[127:0]$10189 \dividend
+ assign $2\dividend$68$next[127:0]$10103 \dividend
case
- assign $2\dividend$68$next[127:0]$10189 \dividend$68
+ assign $2\dividend$68$next[127:0]$10103 \dividend$68
end
case
- assign $1\dividend$68$next[127:0]$10188 \dividend$68
+ assign $1\dividend$68$next[127:0]$10102 \dividend$68
end
sync always
- update \dividend$68$next $0\dividend$68$next[127:0]$10187
+ update \dividend$68$next $0\dividend$68$next[127:0]$10101
end
- attribute \src "libresoc.v:172277.3-172291.6"
- process $proc$libresoc.v:172277$10190
+ attribute \src "libresoc.v:170078.3-170092.6"
+ process $proc$libresoc.v:170078$10104
assign { } { }
assign { } { }
- assign $0\divisor_radicand$65$next[63:0]$10191 $1\divisor_radicand$65$next[63:0]$10192
- attribute \src "libresoc.v:172278.5-172278.29"
+ assign $0\divisor_radicand$65$next[63:0]$10105 $1\divisor_radicand$65$next[63:0]$10106
+ attribute \src "libresoc.v:170079.5-170079.29"
switch \initial
- attribute \src "libresoc.v:172278.9-172278.17"
+ attribute \src "libresoc.v:170079.9-170079.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\divisor_radicand$65$next[63:0]$10192 $2\divisor_radicand$65$next[63:0]$10193
+ assign $1\divisor_radicand$65$next[63:0]$10106 $2\divisor_radicand$65$next[63:0]$10107
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\divisor_radicand$65$next[63:0]$10193 \divisor_radicand
+ assign $2\divisor_radicand$65$next[63:0]$10107 \divisor_radicand
case
- assign $2\divisor_radicand$65$next[63:0]$10193 \divisor_radicand$65
+ assign $2\divisor_radicand$65$next[63:0]$10107 \divisor_radicand$65
end
case
- assign $1\divisor_radicand$65$next[63:0]$10192 \divisor_radicand$65
+ assign $1\divisor_radicand$65$next[63:0]$10106 \divisor_radicand$65
end
sync always
- update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10191
+ update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10105
end
- attribute \src "libresoc.v:172292.3-172306.6"
- process $proc$libresoc.v:172292$10194
+ attribute \src "libresoc.v:170093.3-170107.6"
+ process $proc$libresoc.v:170093$10108
assign { } { }
assign { } { }
- assign $0\operation$69$next[1:0]$10195 $1\operation$69$next[1:0]$10196
- attribute \src "libresoc.v:172293.5-172293.29"
+ assign $0\operation$69$next[1:0]$10109 $1\operation$69$next[1:0]$10110
+ attribute \src "libresoc.v:170094.5-170094.29"
switch \initial
- attribute \src "libresoc.v:172293.9-172293.17"
+ attribute \src "libresoc.v:170094.9-170094.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\operation$69$next[1:0]$10196 $2\operation$69$next[1:0]$10197
+ assign $1\operation$69$next[1:0]$10110 $2\operation$69$next[1:0]$10111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178"
switch \p_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\operation$69$next[1:0]$10197 \operation
+ assign $2\operation$69$next[1:0]$10111 \operation
case
- assign $2\operation$69$next[1:0]$10197 \operation$69
+ assign $2\operation$69$next[1:0]$10111 \operation$69
end
case
- assign $1\operation$69$next[1:0]$10196 \operation$69
+ assign $1\operation$69$next[1:0]$10110 \operation$69
end
sync always
- update \operation$69$next $0\operation$69$next[1:0]$10195
+ update \operation$69$next $0\operation$69$next[1:0]$10109
end
- connect \$56 $sshl$libresoc.v:171909$10004_Y
- connect \$55 $pos$libresoc.v:171910$10006_Y
- connect \$59 $not$libresoc.v:171911$10007_Y
- connect \$61 $ge$libresoc.v:171912$10008_Y
- connect \$63 $and$libresoc.v:171913$10009_Y
- connect \$66 $and$libresoc.v:171914$10010_Y
+ connect \$56 $sshl$libresoc.v:169710$9918_Y
+ connect \$55 $pos$libresoc.v:169711$9920_Y
+ connect \$59 $not$libresoc.v:169712$9921_Y
+ connect \$61 $ge$libresoc.v:169713$9922_Y
+ connect \$63 $and$libresoc.v:169714$9923_Y
+ connect \$66 $and$libresoc.v:169715$9924_Y
connect \p_ready_o \empty
connect \n_valid_o \$63
connect \remainder \$55
connect \muxid$1 \muxid$28
connect \div_state_init_dividend \dividend
end
-attribute \src "libresoc.v:172326.1-173857.10"
+attribute \src "libresoc.v:170127.1-171658.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start"
attribute \generator "nMigen"
module \pipe_start
- attribute \src "libresoc.v:173663.3-173675.6"
- wire $0\div_by_zero$next[0:0]$10307
- attribute \src "libresoc.v:173449.3-173450.39"
+ attribute \src "libresoc.v:171464.3-171476.6"
+ wire $0\div_by_zero$next[0:0]$10221
+ attribute \src "libresoc.v:171250.3-171251.39"
wire $0\div_by_zero[0:0]
- attribute \src "libresoc.v:173637.3-173649.6"
- wire $0\dive_abs_ov32$next[0:0]$10301
- attribute \src "libresoc.v:173453.3-173454.43"
+ attribute \src "libresoc.v:171438.3-171450.6"
+ wire $0\dive_abs_ov32$next[0:0]$10215
+ attribute \src "libresoc.v:171254.3-171255.43"
wire $0\dive_abs_ov32[0:0]
- attribute \src "libresoc.v:173650.3-173662.6"
- wire $0\dive_abs_ov64$next[0:0]$10304
- attribute \src "libresoc.v:173451.3-173452.43"
+ attribute \src "libresoc.v:171451.3-171463.6"
+ wire $0\dive_abs_ov64$next[0:0]$10218
+ attribute \src "libresoc.v:171252.3-171253.43"
wire $0\dive_abs_ov64[0:0]
- attribute \src "libresoc.v:173676.3-173688.6"
- wire width 128 $0\dividend$next[127:0]$10310
- attribute \src "libresoc.v:173447.3-173448.33"
+ attribute \src "libresoc.v:171477.3-171489.6"
+ wire width 128 $0\dividend$next[127:0]$10224
+ attribute \src "libresoc.v:171248.3-171249.33"
wire width 128 $0\dividend[127:0]
- attribute \src "libresoc.v:173624.3-173636.6"
- wire $0\dividend_neg$next[0:0]$10298
- attribute \src "libresoc.v:173455.3-173456.41"
+ attribute \src "libresoc.v:171425.3-171437.6"
+ wire $0\dividend_neg$next[0:0]$10212
+ attribute \src "libresoc.v:171256.3-171257.41"
wire $0\dividend_neg[0:0]
- attribute \src "libresoc.v:173611.3-173623.6"
- wire $0\divisor_neg$next[0:0]$10295
- attribute \src "libresoc.v:173457.3-173458.39"
+ attribute \src "libresoc.v:171412.3-171424.6"
+ wire $0\divisor_neg$next[0:0]$10209
+ attribute \src "libresoc.v:171258.3-171259.39"
wire $0\divisor_neg[0:0]
- attribute \src "libresoc.v:173689.3-173701.6"
- wire width 64 $0\divisor_radicand$next[63:0]$10313
- attribute \src "libresoc.v:173445.3-173446.49"
+ attribute \src "libresoc.v:171490.3-171502.6"
+ wire width 64 $0\divisor_radicand$next[63:0]$10227
+ attribute \src "libresoc.v:171246.3-171247.49"
wire width 64 $0\divisor_radicand[63:0]
- attribute \src "libresoc.v:172327.7-172327.20"
+ attribute \src "libresoc.v:170128.7-170128.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 4 $0\logical_op__data_len$next[3:0]$10326
- attribute \src "libresoc.v:173497.3-173498.57"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 4 $0\logical_op__data_len$next[3:0]$10240
+ attribute \src "libresoc.v:171298.3-171299.57"
wire width 4 $0\logical_op__data_len[3:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 13 $0\logical_op__fn_unit$next[12:0]$10327
- attribute \src "libresoc.v:173467.3-173468.55"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 13 $0\logical_op__fn_unit$next[12:0]$10241
+ attribute \src "libresoc.v:171268.3-171269.55"
wire width 13 $0\logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 64 $0\logical_op__imm_data__data$next[63:0]$10328
- attribute \src "libresoc.v:173469.3-173470.69"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 64 $0\logical_op__imm_data__data$next[63:0]$10242
+ attribute \src "libresoc.v:171270.3-171271.69"
wire width 64 $0\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__imm_data__ok$next[0:0]$10329
- attribute \src "libresoc.v:173471.3-173472.65"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__imm_data__ok$next[0:0]$10243
+ attribute \src "libresoc.v:171272.3-171273.65"
wire $0\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 2 $0\logical_op__input_carry$next[1:0]$10330
- attribute \src "libresoc.v:173485.3-173486.63"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 2 $0\logical_op__input_carry$next[1:0]$10244
+ attribute \src "libresoc.v:171286.3-171287.63"
wire width 2 $0\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 32 $0\logical_op__insn$next[31:0]$10331
- attribute \src "libresoc.v:173499.3-173500.49"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 32 $0\logical_op__insn$next[31:0]$10245
+ attribute \src "libresoc.v:171300.3-171301.49"
wire width 32 $0\logical_op__insn[31:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 7 $0\logical_op__insn_type$next[6:0]$10332
- attribute \src "libresoc.v:173465.3-173466.59"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 7 $0\logical_op__insn_type$next[6:0]$10246
+ attribute \src "libresoc.v:171266.3-171267.59"
wire width 7 $0\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__invert_in$next[0:0]$10333
- attribute \src "libresoc.v:173481.3-173482.59"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__invert_in$next[0:0]$10247
+ attribute \src "libresoc.v:171282.3-171283.59"
wire $0\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__invert_out$next[0:0]$10334
- attribute \src "libresoc.v:173487.3-173488.61"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__invert_out$next[0:0]$10248
+ attribute \src "libresoc.v:171288.3-171289.61"
wire $0\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__is_32bit$next[0:0]$10335
- attribute \src "libresoc.v:173493.3-173494.57"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__is_32bit$next[0:0]$10249
+ attribute \src "libresoc.v:171294.3-171295.57"
wire $0\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__is_signed$next[0:0]$10336
- attribute \src "libresoc.v:173495.3-173496.59"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__is_signed$next[0:0]$10250
+ attribute \src "libresoc.v:171296.3-171297.59"
wire $0\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__oe__oe$next[0:0]$10337
- attribute \src "libresoc.v:173477.3-173478.53"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__oe__oe$next[0:0]$10251
+ attribute \src "libresoc.v:171278.3-171279.53"
wire $0\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__oe__ok$next[0:0]$10338
- attribute \src "libresoc.v:173479.3-173480.53"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__oe__ok$next[0:0]$10252
+ attribute \src "libresoc.v:171280.3-171281.53"
wire $0\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__output_carry$next[0:0]$10339
- attribute \src "libresoc.v:173491.3-173492.65"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__output_carry$next[0:0]$10253
+ attribute \src "libresoc.v:171292.3-171293.65"
wire $0\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__rc__ok$next[0:0]$10340
- attribute \src "libresoc.v:173475.3-173476.53"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__rc__ok$next[0:0]$10254
+ attribute \src "libresoc.v:171276.3-171277.53"
wire $0\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__rc__rc$next[0:0]$10341
- attribute \src "libresoc.v:173473.3-173474.53"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__rc__rc$next[0:0]$10255
+ attribute \src "libresoc.v:171274.3-171275.53"
wire $0\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__write_cr0$next[0:0]$10342
- attribute \src "libresoc.v:173489.3-173490.59"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__write_cr0$next[0:0]$10256
+ attribute \src "libresoc.v:171290.3-171291.59"
wire $0\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $0\logical_op__zero_a$next[0:0]$10343
- attribute \src "libresoc.v:173483.3-173484.53"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $0\logical_op__zero_a$next[0:0]$10257
+ attribute \src "libresoc.v:171284.3-171285.53"
wire $0\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:173733.3-173745.6"
- wire width 2 $0\muxid$next[1:0]$10323
- attribute \src "libresoc.v:173501.3-173502.27"
+ attribute \src "libresoc.v:171534.3-171546.6"
+ wire width 2 $0\muxid$next[1:0]$10237
+ attribute \src "libresoc.v:171302.3-171303.27"
wire width 2 $0\muxid[1:0]
- attribute \src "libresoc.v:173702.3-173714.6"
- wire width 2 $0\operation$next[1:0]$10316
- attribute \src "libresoc.v:173443.3-173444.35"
+ attribute \src "libresoc.v:171503.3-171515.6"
+ wire width 2 $0\operation$next[1:0]$10230
+ attribute \src "libresoc.v:171244.3-171245.35"
wire width 2 $0\operation[1:0]
- attribute \src "libresoc.v:173715.3-173732.6"
- wire $0\r_busy$next[0:0]$10319
- attribute \src "libresoc.v:173503.3-173504.29"
+ attribute \src "libresoc.v:171516.3-171533.6"
+ wire $0\r_busy$next[0:0]$10233
+ attribute \src "libresoc.v:171304.3-171305.29"
wire $0\r_busy[0:0]
- attribute \src "libresoc.v:173788.3-173800.6"
- wire width 64 $0\ra$next[63:0]$10369
- attribute \src "libresoc.v:173463.3-173464.21"
+ attribute \src "libresoc.v:171589.3-171601.6"
+ wire width 64 $0\ra$next[63:0]$10283
+ attribute \src "libresoc.v:171264.3-171265.21"
wire width 64 $0\ra[63:0]
- attribute \src "libresoc.v:173801.3-173813.6"
- wire width 64 $0\rb$next[63:0]$10372
- attribute \src "libresoc.v:173461.3-173462.21"
+ attribute \src "libresoc.v:171602.3-171614.6"
+ wire width 64 $0\rb$next[63:0]$10286
+ attribute \src "libresoc.v:171262.3-171263.21"
wire width 64 $0\rb[63:0]
- attribute \src "libresoc.v:173814.3-173826.6"
- wire $0\xer_so$next[0:0]$10375
- attribute \src "libresoc.v:173459.3-173460.29"
+ attribute \src "libresoc.v:171615.3-171627.6"
+ wire $0\xer_so$next[0:0]$10289
+ attribute \src "libresoc.v:171260.3-171261.29"
wire $0\xer_so[0:0]
- attribute \src "libresoc.v:173663.3-173675.6"
- wire $1\div_by_zero$next[0:0]$10308
- attribute \src "libresoc.v:172336.7-172336.25"
+ attribute \src "libresoc.v:171464.3-171476.6"
+ wire $1\div_by_zero$next[0:0]$10222
+ attribute \src "libresoc.v:170137.7-170137.25"
wire $1\div_by_zero[0:0]
- attribute \src "libresoc.v:173637.3-173649.6"
- wire $1\dive_abs_ov32$next[0:0]$10302
- attribute \src "libresoc.v:172343.7-172343.27"
+ attribute \src "libresoc.v:171438.3-171450.6"
+ wire $1\dive_abs_ov32$next[0:0]$10216
+ attribute \src "libresoc.v:170144.7-170144.27"
wire $1\dive_abs_ov32[0:0]
- attribute \src "libresoc.v:173650.3-173662.6"
- wire $1\dive_abs_ov64$next[0:0]$10305
- attribute \src "libresoc.v:172350.7-172350.27"
+ attribute \src "libresoc.v:171451.3-171463.6"
+ wire $1\dive_abs_ov64$next[0:0]$10219
+ attribute \src "libresoc.v:170151.7-170151.27"
wire $1\dive_abs_ov64[0:0]
- attribute \src "libresoc.v:173676.3-173688.6"
- wire width 128 $1\dividend$next[127:0]$10311
- attribute \src "libresoc.v:172357.15-172357.63"
+ attribute \src "libresoc.v:171477.3-171489.6"
+ wire width 128 $1\dividend$next[127:0]$10225
+ attribute \src "libresoc.v:170158.15-170158.63"
wire width 128 $1\dividend[127:0]
- attribute \src "libresoc.v:173624.3-173636.6"
- wire $1\dividend_neg$next[0:0]$10299
- attribute \src "libresoc.v:172364.7-172364.26"
+ attribute \src "libresoc.v:171425.3-171437.6"
+ wire $1\dividend_neg$next[0:0]$10213
+ attribute \src "libresoc.v:170165.7-170165.26"
wire $1\dividend_neg[0:0]
- attribute \src "libresoc.v:173611.3-173623.6"
- wire $1\divisor_neg$next[0:0]$10296
- attribute \src "libresoc.v:172371.7-172371.25"
+ attribute \src "libresoc.v:171412.3-171424.6"
+ wire $1\divisor_neg$next[0:0]$10210
+ attribute \src "libresoc.v:170172.7-170172.25"
wire $1\divisor_neg[0:0]
- attribute \src "libresoc.v:173689.3-173701.6"
- wire width 64 $1\divisor_radicand$next[63:0]$10314
- attribute \src "libresoc.v:172378.14-172378.53"
+ attribute \src "libresoc.v:171490.3-171502.6"
+ wire width 64 $1\divisor_radicand$next[63:0]$10228
+ attribute \src "libresoc.v:170179.14-170179.53"
wire width 64 $1\divisor_radicand[63:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 4 $1\logical_op__data_len$next[3:0]$10344
- attribute \src "libresoc.v:172657.13-172657.40"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 4 $1\logical_op__data_len$next[3:0]$10258
+ attribute \src "libresoc.v:170458.13-170458.40"
wire width 4 $1\logical_op__data_len[3:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 13 $1\logical_op__fn_unit$next[12:0]$10345
- attribute \src "libresoc.v:172680.14-172680.44"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 13 $1\logical_op__fn_unit$next[12:0]$10259
+ attribute \src "libresoc.v:170481.14-170481.44"
wire width 13 $1\logical_op__fn_unit[12:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 64 $1\logical_op__imm_data__data$next[63:0]$10346
- attribute \src "libresoc.v:172717.14-172717.63"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 64 $1\logical_op__imm_data__data$next[63:0]$10260
+ attribute \src "libresoc.v:170518.14-170518.63"
wire width 64 $1\logical_op__imm_data__data[63:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__imm_data__ok$next[0:0]$10347
- attribute \src "libresoc.v:172726.7-172726.38"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__imm_data__ok$next[0:0]$10261
+ attribute \src "libresoc.v:170527.7-170527.38"
wire $1\logical_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 2 $1\logical_op__input_carry$next[1:0]$10348
- attribute \src "libresoc.v:172739.13-172739.43"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 2 $1\logical_op__input_carry$next[1:0]$10262
+ attribute \src "libresoc.v:170540.13-170540.43"
wire width 2 $1\logical_op__input_carry[1:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 32 $1\logical_op__insn$next[31:0]$10349
- attribute \src "libresoc.v:172756.14-172756.38"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 32 $1\logical_op__insn$next[31:0]$10263
+ attribute \src "libresoc.v:170557.14-170557.38"
wire width 32 $1\logical_op__insn[31:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 7 $1\logical_op__insn_type$next[6:0]$10350
- attribute \src "libresoc.v:172839.13-172839.42"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 7 $1\logical_op__insn_type$next[6:0]$10264
+ attribute \src "libresoc.v:170640.13-170640.42"
wire width 7 $1\logical_op__insn_type[6:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__invert_in$next[0:0]$10351
- attribute \src "libresoc.v:172996.7-172996.35"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__invert_in$next[0:0]$10265
+ attribute \src "libresoc.v:170797.7-170797.35"
wire $1\logical_op__invert_in[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__invert_out$next[0:0]$10352
- attribute \src "libresoc.v:173005.7-173005.36"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__invert_out$next[0:0]$10266
+ attribute \src "libresoc.v:170806.7-170806.36"
wire $1\logical_op__invert_out[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__is_32bit$next[0:0]$10353
- attribute \src "libresoc.v:173014.7-173014.34"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__is_32bit$next[0:0]$10267
+ attribute \src "libresoc.v:170815.7-170815.34"
wire $1\logical_op__is_32bit[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__is_signed$next[0:0]$10354
- attribute \src "libresoc.v:173023.7-173023.35"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__is_signed$next[0:0]$10268
+ attribute \src "libresoc.v:170824.7-170824.35"
wire $1\logical_op__is_signed[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__oe__oe$next[0:0]$10355
- attribute \src "libresoc.v:173032.7-173032.32"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__oe__oe$next[0:0]$10269
+ attribute \src "libresoc.v:170833.7-170833.32"
wire $1\logical_op__oe__oe[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__oe__ok$next[0:0]$10356
- attribute \src "libresoc.v:173041.7-173041.32"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__oe__ok$next[0:0]$10270
+ attribute \src "libresoc.v:170842.7-170842.32"
wire $1\logical_op__oe__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__output_carry$next[0:0]$10357
- attribute \src "libresoc.v:173050.7-173050.38"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__output_carry$next[0:0]$10271
+ attribute \src "libresoc.v:170851.7-170851.38"
wire $1\logical_op__output_carry[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__rc__ok$next[0:0]$10358
- attribute \src "libresoc.v:173059.7-173059.32"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__rc__ok$next[0:0]$10272
+ attribute \src "libresoc.v:170860.7-170860.32"
wire $1\logical_op__rc__ok[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__rc__rc$next[0:0]$10359
- attribute \src "libresoc.v:173068.7-173068.32"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__rc__rc$next[0:0]$10273
+ attribute \src "libresoc.v:170869.7-170869.32"
wire $1\logical_op__rc__rc[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__write_cr0$next[0:0]$10360
- attribute \src "libresoc.v:173077.7-173077.35"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__write_cr0$next[0:0]$10274
+ attribute \src "libresoc.v:170878.7-170878.35"
wire $1\logical_op__write_cr0[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $1\logical_op__zero_a$next[0:0]$10361
- attribute \src "libresoc.v:173086.7-173086.32"
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $1\logical_op__zero_a$next[0:0]$10275
+ attribute \src "libresoc.v:170887.7-170887.32"
wire $1\logical_op__zero_a[0:0]
- attribute \src "libresoc.v:173733.3-173745.6"
- wire width 2 $1\muxid$next[1:0]$10324
- attribute \src "libresoc.v:173095.13-173095.25"
+ attribute \src "libresoc.v:171534.3-171546.6"
+ wire width 2 $1\muxid$next[1:0]$10238
+ attribute \src "libresoc.v:170896.13-170896.25"
wire width 2 $1\muxid[1:0]
- attribute \src "libresoc.v:173702.3-173714.6"
- wire width 2 $1\operation$next[1:0]$10317
- attribute \src "libresoc.v:173110.13-173110.29"
+ attribute \src "libresoc.v:171503.3-171515.6"
+ wire width 2 $1\operation$next[1:0]$10231
+ attribute \src "libresoc.v:170911.13-170911.29"
wire width 2 $1\operation[1:0]
- attribute \src "libresoc.v:173715.3-173732.6"
- wire $1\r_busy$next[0:0]$10320
- attribute \src "libresoc.v:173124.7-173124.20"
+ attribute \src "libresoc.v:171516.3-171533.6"
+ wire $1\r_busy$next[0:0]$10234
+ attribute \src "libresoc.v:170925.7-170925.20"
wire $1\r_busy[0:0]
- attribute \src "libresoc.v:173788.3-173800.6"
- wire width 64 $1\ra$next[63:0]$10370
- attribute \src "libresoc.v:173129.14-173129.39"
+ attribute \src "libresoc.v:171589.3-171601.6"
+ wire width 64 $1\ra$next[63:0]$10284
+ attribute \src "libresoc.v:170930.14-170930.39"
wire width 64 $1\ra[63:0]
- attribute \src "libresoc.v:173801.3-173813.6"
- wire width 64 $1\rb$next[63:0]$10373
- attribute \src "libresoc.v:173140.14-173140.39"
+ attribute \src "libresoc.v:171602.3-171614.6"
+ wire width 64 $1\rb$next[63:0]$10287
+ attribute \src "libresoc.v:170941.14-170941.39"
wire width 64 $1\rb[63:0]
- attribute \src "libresoc.v:173814.3-173826.6"
- wire $1\xer_so$next[0:0]$10376
- attribute \src "libresoc.v:173435.7-173435.20"
+ attribute \src "libresoc.v:171615.3-171627.6"
+ wire $1\xer_so$next[0:0]$10290
+ attribute \src "libresoc.v:171236.7-171236.20"
wire $1\xer_so[0:0]
- attribute \src "libresoc.v:173746.3-173787.6"
- wire width 64 $2\logical_op__imm_data__data$next[63:0]$10362
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $2\logical_op__imm_data__ok$next[0:0]$10363
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $2\logical_op__oe__oe$next[0:0]$10364
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $2\logical_op__oe__ok$next[0:0]$10365
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $2\logical_op__rc__ok$next[0:0]$10366
- attribute \src "libresoc.v:173746.3-173787.6"
- wire $2\logical_op__rc__rc$next[0:0]$10367
- attribute \src "libresoc.v:173715.3-173732.6"
- wire $2\r_busy$next[0:0]$10321
- attribute \src "libresoc.v:173442.18-173442.118"
- wire $and$libresoc.v:173442$10262_Y
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire width 64 $2\logical_op__imm_data__data$next[63:0]$10276
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $2\logical_op__imm_data__ok$next[0:0]$10277
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $2\logical_op__oe__oe$next[0:0]$10278
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $2\logical_op__oe__ok$next[0:0]$10279
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $2\logical_op__rc__ok$next[0:0]$10280
+ attribute \src "libresoc.v:171547.3-171588.6"
+ wire $2\logical_op__rc__rc$next[0:0]$10281
+ attribute \src "libresoc.v:171516.3-171533.6"
+ wire $2\r_busy$next[0:0]$10235
+ attribute \src "libresoc.v:171243.18-171243.118"
+ wire $and$libresoc.v:171243$10176_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire output 30 \div_by_zero
wire width 64 \divisor_radicand$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
wire width 64 \divisor_radicand$next
- attribute \src "libresoc.v:172327.7-172327.15"
+ attribute \src "libresoc.v:170128.7-170128.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \input_logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \xer_so$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
- cell $and $and$libresoc.v:173442$10262
+ cell $and $and$libresoc.v:171243$10176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \p_valid_i$65
connect \B \p_ready_o
- connect \Y $and$libresoc.v:173442$10262_Y
+ connect \Y $and$libresoc.v:171243$10176_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173505.14-173550.4"
+ attribute \src "libresoc.v:171306.14-171351.4"
cell \input$78 \input
connect \logical_op__data_len \input_logical_op__data_len
connect \logical_op__data_len$18 \input_logical_op__data_len$40
connect \xer_so$22 \input_xer_so$44
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173551.10-173554.4"
+ attribute \src "libresoc.v:171352.10-171355.4"
cell \n$77 \n
connect \n_ready_i \n_ready_i
connect \n_valid_o \n_valid_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173555.10-173558.4"
+ attribute \src "libresoc.v:171356.10-171359.4"
cell \p$76 \p
connect \p_ready_o \p_ready_o
connect \p_valid_i \p_valid_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:173559.15-173610.4"
+ attribute \src "libresoc.v:171360.15-171411.4"
cell \setup_stage \setup_stage
connect \div_by_zero \setup_stage_div_by_zero
connect \dive_abs_ov32 \setup_stage_dive_abs_ov32
connect \xer_so \setup_stage_xer_so
connect \xer_so$20 \setup_stage_xer_so$64
end
- attribute \src "libresoc.v:172327.7-172327.20"
- process $proc$libresoc.v:172327$10377
+ attribute \src "libresoc.v:170128.7-170128.20"
+ process $proc$libresoc.v:170128$10291
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:172336.7-172336.25"
- process $proc$libresoc.v:172336$10378
+ attribute \src "libresoc.v:170137.7-170137.25"
+ process $proc$libresoc.v:170137$10292
assign { } { }
assign $1\div_by_zero[0:0] 1'0
sync always
sync init
update \div_by_zero $1\div_by_zero[0:0]
end
- attribute \src "libresoc.v:172343.7-172343.27"
- process $proc$libresoc.v:172343$10379
+ attribute \src "libresoc.v:170144.7-170144.27"
+ process $proc$libresoc.v:170144$10293
assign { } { }
assign $1\dive_abs_ov32[0:0] 1'0
sync always
sync init
update \dive_abs_ov32 $1\dive_abs_ov32[0:0]
end
- attribute \src "libresoc.v:172350.7-172350.27"
- process $proc$libresoc.v:172350$10380
+ attribute \src "libresoc.v:170151.7-170151.27"
+ process $proc$libresoc.v:170151$10294
assign { } { }
assign $1\dive_abs_ov64[0:0] 1'0
sync always
sync init
update \dive_abs_ov64 $1\dive_abs_ov64[0:0]
end
- attribute \src "libresoc.v:172357.15-172357.63"
- process $proc$libresoc.v:172357$10381
+ attribute \src "libresoc.v:170158.15-170158.63"
+ process $proc$libresoc.v:170158$10295
assign { } { }
assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dividend $1\dividend[127:0]
end
- attribute \src "libresoc.v:172364.7-172364.26"
- process $proc$libresoc.v:172364$10382
+ attribute \src "libresoc.v:170165.7-170165.26"
+ process $proc$libresoc.v:170165$10296
assign { } { }
assign $1\dividend_neg[0:0] 1'0
sync always
sync init
update \dividend_neg $1\dividend_neg[0:0]
end
- attribute \src "libresoc.v:172371.7-172371.25"
- process $proc$libresoc.v:172371$10383
+ attribute \src "libresoc.v:170172.7-170172.25"
+ process $proc$libresoc.v:170172$10297
assign { } { }
assign $1\divisor_neg[0:0] 1'0
sync always
sync init
update \divisor_neg $1\divisor_neg[0:0]
end
- attribute \src "libresoc.v:172378.14-172378.53"
- process $proc$libresoc.v:172378$10384
+ attribute \src "libresoc.v:170179.14-170179.53"
+ process $proc$libresoc.v:170179$10298
assign { } { }
assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \divisor_radicand $1\divisor_radicand[63:0]
end
- attribute \src "libresoc.v:172657.13-172657.40"
- process $proc$libresoc.v:172657$10385
+ attribute \src "libresoc.v:170458.13-170458.40"
+ process $proc$libresoc.v:170458$10299
assign { } { }
assign $1\logical_op__data_len[3:0] 4'0000
sync always
sync init
update \logical_op__data_len $1\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:172680.14-172680.44"
- process $proc$libresoc.v:172680$10386
+ attribute \src "libresoc.v:170481.14-170481.44"
+ process $proc$libresoc.v:170481$10300
assign { } { }
assign $1\logical_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \logical_op__fn_unit $1\logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:172717.14-172717.63"
- process $proc$libresoc.v:172717$10387
+ attribute \src "libresoc.v:170518.14-170518.63"
+ process $proc$libresoc.v:170518$10301
assign { } { }
assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:172726.7-172726.38"
- process $proc$libresoc.v:172726$10388
+ attribute \src "libresoc.v:170527.7-170527.38"
+ process $proc$libresoc.v:170527$10302
assign { } { }
assign $1\logical_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:172739.13-172739.43"
- process $proc$libresoc.v:172739$10389
+ attribute \src "libresoc.v:170540.13-170540.43"
+ process $proc$libresoc.v:170540$10303
assign { } { }
assign $1\logical_op__input_carry[1:0] 2'00
sync always
sync init
update \logical_op__input_carry $1\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:172756.14-172756.38"
- process $proc$libresoc.v:172756$10390
+ attribute \src "libresoc.v:170557.14-170557.38"
+ process $proc$libresoc.v:170557$10304
assign { } { }
assign $1\logical_op__insn[31:0] 0
sync always
sync init
update \logical_op__insn $1\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:172839.13-172839.42"
- process $proc$libresoc.v:172839$10391
+ attribute \src "libresoc.v:170640.13-170640.42"
+ process $proc$libresoc.v:170640$10305
assign { } { }
assign $1\logical_op__insn_type[6:0] 7'0000000
sync always
sync init
update \logical_op__insn_type $1\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:172996.7-172996.35"
- process $proc$libresoc.v:172996$10392
+ attribute \src "libresoc.v:170797.7-170797.35"
+ process $proc$libresoc.v:170797$10306
assign { } { }
assign $1\logical_op__invert_in[0:0] 1'0
sync always
sync init
update \logical_op__invert_in $1\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:173005.7-173005.36"
- process $proc$libresoc.v:173005$10393
+ attribute \src "libresoc.v:170806.7-170806.36"
+ process $proc$libresoc.v:170806$10307
assign { } { }
assign $1\logical_op__invert_out[0:0] 1'0
sync always
sync init
update \logical_op__invert_out $1\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:173014.7-173014.34"
- process $proc$libresoc.v:173014$10394
+ attribute \src "libresoc.v:170815.7-170815.34"
+ process $proc$libresoc.v:170815$10308
assign { } { }
assign $1\logical_op__is_32bit[0:0] 1'0
sync always
sync init
update \logical_op__is_32bit $1\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:173023.7-173023.35"
- process $proc$libresoc.v:173023$10395
+ attribute \src "libresoc.v:170824.7-170824.35"
+ process $proc$libresoc.v:170824$10309
assign { } { }
assign $1\logical_op__is_signed[0:0] 1'0
sync always
sync init
update \logical_op__is_signed $1\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:173032.7-173032.32"
- process $proc$libresoc.v:173032$10396
+ attribute \src "libresoc.v:170833.7-170833.32"
+ process $proc$libresoc.v:170833$10310
assign { } { }
assign $1\logical_op__oe__oe[0:0] 1'0
sync always
sync init
update \logical_op__oe__oe $1\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:173041.7-173041.32"
- process $proc$libresoc.v:173041$10397
+ attribute \src "libresoc.v:170842.7-170842.32"
+ process $proc$libresoc.v:170842$10311
assign { } { }
assign $1\logical_op__oe__ok[0:0] 1'0
sync always
sync init
update \logical_op__oe__ok $1\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:173050.7-173050.38"
- process $proc$libresoc.v:173050$10398
+ attribute \src "libresoc.v:170851.7-170851.38"
+ process $proc$libresoc.v:170851$10312
assign { } { }
assign $1\logical_op__output_carry[0:0] 1'0
sync always
sync init
update \logical_op__output_carry $1\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:173059.7-173059.32"
- process $proc$libresoc.v:173059$10399
+ attribute \src "libresoc.v:170860.7-170860.32"
+ process $proc$libresoc.v:170860$10313
assign { } { }
assign $1\logical_op__rc__ok[0:0] 1'0
sync always
sync init
update \logical_op__rc__ok $1\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:173068.7-173068.32"
- process $proc$libresoc.v:173068$10400
+ attribute \src "libresoc.v:170869.7-170869.32"
+ process $proc$libresoc.v:170869$10314
assign { } { }
assign $1\logical_op__rc__rc[0:0] 1'0
sync always
sync init
update \logical_op__rc__rc $1\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:173077.7-173077.35"
- process $proc$libresoc.v:173077$10401
+ attribute \src "libresoc.v:170878.7-170878.35"
+ process $proc$libresoc.v:170878$10315
assign { } { }
assign $1\logical_op__write_cr0[0:0] 1'0
sync always
sync init
update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:173086.7-173086.32"
- process $proc$libresoc.v:173086$10402
+ attribute \src "libresoc.v:170887.7-170887.32"
+ process $proc$libresoc.v:170887$10316
assign { } { }
assign $1\logical_op__zero_a[0:0] 1'0
sync always
sync init
update \logical_op__zero_a $1\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:173095.13-173095.25"
- process $proc$libresoc.v:173095$10403
+ attribute \src "libresoc.v:170896.13-170896.25"
+ process $proc$libresoc.v:170896$10317
assign { } { }
assign $1\muxid[1:0] 2'00
sync always
sync init
update \muxid $1\muxid[1:0]
end
- attribute \src "libresoc.v:173110.13-173110.29"
- process $proc$libresoc.v:173110$10404
+ attribute \src "libresoc.v:170911.13-170911.29"
+ process $proc$libresoc.v:170911$10318
assign { } { }
assign $1\operation[1:0] 2'00
sync always
sync init
update \operation $1\operation[1:0]
end
- attribute \src "libresoc.v:173124.7-173124.20"
- process $proc$libresoc.v:173124$10405
+ attribute \src "libresoc.v:170925.7-170925.20"
+ process $proc$libresoc.v:170925$10319
assign { } { }
assign $1\r_busy[0:0] 1'0
sync always
sync init
update \r_busy $1\r_busy[0:0]
end
- attribute \src "libresoc.v:173129.14-173129.39"
- process $proc$libresoc.v:173129$10406
+ attribute \src "libresoc.v:170930.14-170930.39"
+ process $proc$libresoc.v:170930$10320
assign { } { }
assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ra $1\ra[63:0]
end
- attribute \src "libresoc.v:173140.14-173140.39"
- process $proc$libresoc.v:173140$10407
+ attribute \src "libresoc.v:170941.14-170941.39"
+ process $proc$libresoc.v:170941$10321
assign { } { }
assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rb $1\rb[63:0]
end
- attribute \src "libresoc.v:173435.7-173435.20"
- process $proc$libresoc.v:173435$10408
+ attribute \src "libresoc.v:171236.7-171236.20"
+ process $proc$libresoc.v:171236$10322
assign { } { }
assign $1\xer_so[0:0] 1'0
sync always
sync init
update \xer_so $1\xer_so[0:0]
end
- attribute \src "libresoc.v:173443.3-173444.35"
- process $proc$libresoc.v:173443$10263
+ attribute \src "libresoc.v:171244.3-171245.35"
+ process $proc$libresoc.v:171244$10177
assign { } { }
assign $0\operation[1:0] \operation$next
sync posedge \coresync_clk
update \operation $0\operation[1:0]
end
- attribute \src "libresoc.v:173445.3-173446.49"
- process $proc$libresoc.v:173445$10264
+ attribute \src "libresoc.v:171246.3-171247.49"
+ process $proc$libresoc.v:171246$10178
assign { } { }
assign $0\divisor_radicand[63:0] \divisor_radicand$next
sync posedge \coresync_clk
update \divisor_radicand $0\divisor_radicand[63:0]
end
- attribute \src "libresoc.v:173447.3-173448.33"
- process $proc$libresoc.v:173447$10265
+ attribute \src "libresoc.v:171248.3-171249.33"
+ process $proc$libresoc.v:171248$10179
assign { } { }
assign $0\dividend[127:0] \dividend$next
sync posedge \coresync_clk
update \dividend $0\dividend[127:0]
end
- attribute \src "libresoc.v:173449.3-173450.39"
- process $proc$libresoc.v:173449$10266
+ attribute \src "libresoc.v:171250.3-171251.39"
+ process $proc$libresoc.v:171250$10180
assign { } { }
assign $0\div_by_zero[0:0] \div_by_zero$next
sync posedge \coresync_clk
update \div_by_zero $0\div_by_zero[0:0]
end
- attribute \src "libresoc.v:173451.3-173452.43"
- process $proc$libresoc.v:173451$10267
+ attribute \src "libresoc.v:171252.3-171253.43"
+ process $proc$libresoc.v:171252$10181
assign { } { }
assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next
sync posedge \coresync_clk
update \dive_abs_ov64 $0\dive_abs_ov64[0:0]
end
- attribute \src "libresoc.v:173453.3-173454.43"
- process $proc$libresoc.v:173453$10268
+ attribute \src "libresoc.v:171254.3-171255.43"
+ process $proc$libresoc.v:171254$10182
assign { } { }
assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next
sync posedge \coresync_clk
update \dive_abs_ov32 $0\dive_abs_ov32[0:0]
end
- attribute \src "libresoc.v:173455.3-173456.41"
- process $proc$libresoc.v:173455$10269
+ attribute \src "libresoc.v:171256.3-171257.41"
+ process $proc$libresoc.v:171256$10183
assign { } { }
assign $0\dividend_neg[0:0] \dividend_neg$next
sync posedge \coresync_clk
update \dividend_neg $0\dividend_neg[0:0]
end
- attribute \src "libresoc.v:173457.3-173458.39"
- process $proc$libresoc.v:173457$10270
+ attribute \src "libresoc.v:171258.3-171259.39"
+ process $proc$libresoc.v:171258$10184
assign { } { }
assign $0\divisor_neg[0:0] \divisor_neg$next
sync posedge \coresync_clk
update \divisor_neg $0\divisor_neg[0:0]
end
- attribute \src "libresoc.v:173459.3-173460.29"
- process $proc$libresoc.v:173459$10271
+ attribute \src "libresoc.v:171260.3-171261.29"
+ process $proc$libresoc.v:171260$10185
assign { } { }
assign $0\xer_so[0:0] \xer_so$next
sync posedge \coresync_clk
update \xer_so $0\xer_so[0:0]
end
- attribute \src "libresoc.v:173461.3-173462.21"
- process $proc$libresoc.v:173461$10272
+ attribute \src "libresoc.v:171262.3-171263.21"
+ process $proc$libresoc.v:171262$10186
assign { } { }
assign $0\rb[63:0] \rb$next
sync posedge \coresync_clk
update \rb $0\rb[63:0]
end
- attribute \src "libresoc.v:173463.3-173464.21"
- process $proc$libresoc.v:173463$10273
+ attribute \src "libresoc.v:171264.3-171265.21"
+ process $proc$libresoc.v:171264$10187
assign { } { }
assign $0\ra[63:0] \ra$next
sync posedge \coresync_clk
update \ra $0\ra[63:0]
end
- attribute \src "libresoc.v:173465.3-173466.59"
- process $proc$libresoc.v:173465$10274
+ attribute \src "libresoc.v:171266.3-171267.59"
+ process $proc$libresoc.v:171266$10188
assign { } { }
assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next
sync posedge \coresync_clk
update \logical_op__insn_type $0\logical_op__insn_type[6:0]
end
- attribute \src "libresoc.v:173467.3-173468.55"
- process $proc$libresoc.v:173467$10275
+ attribute \src "libresoc.v:171268.3-171269.55"
+ process $proc$libresoc.v:171268$10189
assign { } { }
assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next
sync posedge \coresync_clk
update \logical_op__fn_unit $0\logical_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:173469.3-173470.69"
- process $proc$libresoc.v:173469$10276
+ attribute \src "libresoc.v:171270.3-171271.69"
+ process $proc$libresoc.v:171270$10190
assign { } { }
assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next
sync posedge \coresync_clk
update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:173471.3-173472.65"
- process $proc$libresoc.v:173471$10277
+ attribute \src "libresoc.v:171272.3-171273.65"
+ process $proc$libresoc.v:171272$10191
assign { } { }
assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next
sync posedge \coresync_clk
update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:173473.3-173474.53"
- process $proc$libresoc.v:173473$10278
+ attribute \src "libresoc.v:171274.3-171275.53"
+ process $proc$libresoc.v:171274$10192
assign { } { }
assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next
sync posedge \coresync_clk
update \logical_op__rc__rc $0\logical_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:173475.3-173476.53"
- process $proc$libresoc.v:173475$10279
+ attribute \src "libresoc.v:171276.3-171277.53"
+ process $proc$libresoc.v:171276$10193
assign { } { }
assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next
sync posedge \coresync_clk
update \logical_op__rc__ok $0\logical_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:173477.3-173478.53"
- process $proc$libresoc.v:173477$10280
+ attribute \src "libresoc.v:171278.3-171279.53"
+ process $proc$libresoc.v:171278$10194
assign { } { }
assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next
sync posedge \coresync_clk
update \logical_op__oe__oe $0\logical_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:173479.3-173480.53"
- process $proc$libresoc.v:173479$10281
+ attribute \src "libresoc.v:171280.3-171281.53"
+ process $proc$libresoc.v:171280$10195
assign { } { }
assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next
sync posedge \coresync_clk
update \logical_op__oe__ok $0\logical_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:173481.3-173482.59"
- process $proc$libresoc.v:173481$10282
+ attribute \src "libresoc.v:171282.3-171283.59"
+ process $proc$libresoc.v:171282$10196
assign { } { }
assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next
sync posedge \coresync_clk
update \logical_op__invert_in $0\logical_op__invert_in[0:0]
end
- attribute \src "libresoc.v:173483.3-173484.53"
- process $proc$libresoc.v:173483$10283
+ attribute \src "libresoc.v:171284.3-171285.53"
+ process $proc$libresoc.v:171284$10197
assign { } { }
assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next
sync posedge \coresync_clk
update \logical_op__zero_a $0\logical_op__zero_a[0:0]
end
- attribute \src "libresoc.v:173485.3-173486.63"
- process $proc$libresoc.v:173485$10284
+ attribute \src "libresoc.v:171286.3-171287.63"
+ process $proc$libresoc.v:171286$10198
assign { } { }
assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next
sync posedge \coresync_clk
update \logical_op__input_carry $0\logical_op__input_carry[1:0]
end
- attribute \src "libresoc.v:173487.3-173488.61"
- process $proc$libresoc.v:173487$10285
+ attribute \src "libresoc.v:171288.3-171289.61"
+ process $proc$libresoc.v:171288$10199
assign { } { }
assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next
sync posedge \coresync_clk
update \logical_op__invert_out $0\logical_op__invert_out[0:0]
end
- attribute \src "libresoc.v:173489.3-173490.59"
- process $proc$libresoc.v:173489$10286
+ attribute \src "libresoc.v:171290.3-171291.59"
+ process $proc$libresoc.v:171290$10200
assign { } { }
assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next
sync posedge \coresync_clk
update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:173491.3-173492.65"
- process $proc$libresoc.v:173491$10287
+ attribute \src "libresoc.v:171292.3-171293.65"
+ process $proc$libresoc.v:171292$10201
assign { } { }
assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next
sync posedge \coresync_clk
update \logical_op__output_carry $0\logical_op__output_carry[0:0]
end
- attribute \src "libresoc.v:173493.3-173494.57"
- process $proc$libresoc.v:173493$10288
+ attribute \src "libresoc.v:171294.3-171295.57"
+ process $proc$libresoc.v:171294$10202
assign { } { }
assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next
sync posedge \coresync_clk
update \logical_op__is_32bit $0\logical_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:173495.3-173496.59"
- process $proc$libresoc.v:173495$10289
+ attribute \src "libresoc.v:171296.3-171297.59"
+ process $proc$libresoc.v:171296$10203
assign { } { }
assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next
sync posedge \coresync_clk
update \logical_op__is_signed $0\logical_op__is_signed[0:0]
end
- attribute \src "libresoc.v:173497.3-173498.57"
- process $proc$libresoc.v:173497$10290
+ attribute \src "libresoc.v:171298.3-171299.57"
+ process $proc$libresoc.v:171298$10204
assign { } { }
assign $0\logical_op__data_len[3:0] \logical_op__data_len$next
sync posedge \coresync_clk
update \logical_op__data_len $0\logical_op__data_len[3:0]
end
- attribute \src "libresoc.v:173499.3-173500.49"
- process $proc$libresoc.v:173499$10291
+ attribute \src "libresoc.v:171300.3-171301.49"
+ process $proc$libresoc.v:171300$10205
assign { } { }
assign $0\logical_op__insn[31:0] \logical_op__insn$next
sync posedge \coresync_clk
update \logical_op__insn $0\logical_op__insn[31:0]
end
- attribute \src "libresoc.v:173501.3-173502.27"
- process $proc$libresoc.v:173501$10292
+ attribute \src "libresoc.v:171302.3-171303.27"
+ process $proc$libresoc.v:171302$10206
assign { } { }
assign $0\muxid[1:0] \muxid$next
sync posedge \coresync_clk
update \muxid $0\muxid[1:0]
end
- attribute \src "libresoc.v:173503.3-173504.29"
- process $proc$libresoc.v:173503$10293
+ attribute \src "libresoc.v:171304.3-171305.29"
+ process $proc$libresoc.v:171304$10207
assign { } { }
assign $0\r_busy[0:0] \r_busy$next
sync posedge \coresync_clk
update \r_busy $0\r_busy[0:0]
end
- attribute \src "libresoc.v:173611.3-173623.6"
- process $proc$libresoc.v:173611$10294
- assign { } { }
- assign { } { }
- assign $0\divisor_neg$next[0:0]$10295 $1\divisor_neg$next[0:0]$10296
- attribute \src "libresoc.v:173612.5-173612.29"
- switch \initial
- attribute \src "libresoc.v:173612.9-173612.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\divisor_neg$next[0:0]$10296 \divisor_neg$92
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\divisor_neg$next[0:0]$10296 \divisor_neg$92
- case
- assign $1\divisor_neg$next[0:0]$10296 \divisor_neg
- end
- sync always
- update \divisor_neg$next $0\divisor_neg$next[0:0]$10295
- end
- attribute \src "libresoc.v:173624.3-173636.6"
- process $proc$libresoc.v:173624$10297
- assign { } { }
- assign { } { }
- assign $0\dividend_neg$next[0:0]$10298 $1\dividend_neg$next[0:0]$10299
- attribute \src "libresoc.v:173625.5-173625.29"
- switch \initial
- attribute \src "libresoc.v:173625.9-173625.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\dividend_neg$next[0:0]$10299 \dividend_neg$93
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\dividend_neg$next[0:0]$10299 \dividend_neg$93
- case
- assign $1\dividend_neg$next[0:0]$10299 \dividend_neg
- end
- sync always
- update \dividend_neg$next $0\dividend_neg$next[0:0]$10298
- end
- attribute \src "libresoc.v:173637.3-173649.6"
- process $proc$libresoc.v:173637$10300
- assign { } { }
- assign { } { }
- assign $0\dive_abs_ov32$next[0:0]$10301 $1\dive_abs_ov32$next[0:0]$10302
- attribute \src "libresoc.v:173638.5-173638.29"
- switch \initial
- attribute \src "libresoc.v:173638.9-173638.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32$94
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32$94
- case
- assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32
- end
- sync always
- update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10301
- end
- attribute \src "libresoc.v:173650.3-173662.6"
- process $proc$libresoc.v:173650$10303
- assign { } { }
- assign { } { }
- assign $0\dive_abs_ov64$next[0:0]$10304 $1\dive_abs_ov64$next[0:0]$10305
- attribute \src "libresoc.v:173651.5-173651.29"
- switch \initial
- attribute \src "libresoc.v:173651.9-173651.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64$95
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64$95
- case
- assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64
- end
- sync always
- update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10304
- end
- attribute \src "libresoc.v:173663.3-173675.6"
- process $proc$libresoc.v:173663$10306
- assign { } { }
- assign { } { }
- assign $0\div_by_zero$next[0:0]$10307 $1\div_by_zero$next[0:0]$10308
- attribute \src "libresoc.v:173664.5-173664.29"
- switch \initial
- attribute \src "libresoc.v:173664.9-173664.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\div_by_zero$next[0:0]$10308 \div_by_zero$96
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\div_by_zero$next[0:0]$10308 \div_by_zero$96
- case
- assign $1\div_by_zero$next[0:0]$10308 \div_by_zero
- end
- sync always
- update \div_by_zero$next $0\div_by_zero$next[0:0]$10307
- end
- attribute \src "libresoc.v:173676.3-173688.6"
- process $proc$libresoc.v:173676$10309
- assign { } { }
- assign { } { }
- assign $0\dividend$next[127:0]$10310 $1\dividend$next[127:0]$10311
- attribute \src "libresoc.v:173677.5-173677.29"
- switch \initial
- attribute \src "libresoc.v:173677.9-173677.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\dividend$next[127:0]$10311 \dividend$97
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\dividend$next[127:0]$10311 \dividend$97
- case
- assign $1\dividend$next[127:0]$10311 \dividend
- end
- sync always
- update \dividend$next $0\dividend$next[127:0]$10310
- end
- attribute \src "libresoc.v:173689.3-173701.6"
- process $proc$libresoc.v:173689$10312
- assign { } { }
- assign { } { }
- assign $0\divisor_radicand$next[63:0]$10313 $1\divisor_radicand$next[63:0]$10314
- attribute \src "libresoc.v:173690.5-173690.29"
- switch \initial
- attribute \src "libresoc.v:173690.9-173690.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
- switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "libresoc.v:0.0-0.0"
- case 2'-1
- assign { } { }
- assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand$98
- attribute \src "libresoc.v:0.0-0.0"
- case 2'1-
- assign { } { }
- assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand$98
- case
- assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand
- end
- sync always
- update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10313
- end
- attribute \src "libresoc.v:173702.3-173714.6"
- process $proc$libresoc.v:173702$10315
+ attribute \src "libresoc.v:171412.3-171424.6"
+ process $proc$libresoc.v:171412$10208
assign { } { }
assign { } { }
- assign $0\operation$next[1:0]$10316 $1\operation$next[1:0]$10317
- attribute \src "libresoc.v:173703.5-173703.29"
+ assign $0\divisor_neg$next[0:0]$10209 $1\divisor_neg$next[0:0]$10210
+ attribute \src "libresoc.v:171413.5-171413.29"
switch \initial
- attribute \src "libresoc.v:173703.9-173703.17"
+ attribute \src "libresoc.v:171413.9-171413.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\operation$next[1:0]$10317 \operation$99
+ assign $1\divisor_neg$next[0:0]$10210 \divisor_neg$92
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\operation$next[1:0]$10317 \operation$99
+ assign $1\divisor_neg$next[0:0]$10210 \divisor_neg$92
case
- assign $1\operation$next[1:0]$10317 \operation
+ assign $1\divisor_neg$next[0:0]$10210 \divisor_neg
end
sync always
- update \operation$next $0\operation$next[1:0]$10316
+ update \divisor_neg$next $0\divisor_neg$next[0:0]$10209
end
- attribute \src "libresoc.v:173715.3-173732.6"
- process $proc$libresoc.v:173715$10318
+ attribute \src "libresoc.v:171425.3-171437.6"
+ process $proc$libresoc.v:171425$10211
assign { } { }
assign { } { }
- assign { } { }
- assign $0\r_busy$next[0:0]$10319 $2\r_busy$next[0:0]$10321
- attribute \src "libresoc.v:173716.5-173716.29"
+ assign $0\dividend_neg$next[0:0]$10212 $1\dividend_neg$next[0:0]$10213
+ attribute \src "libresoc.v:171426.5-171426.29"
switch \initial
- attribute \src "libresoc.v:173716.9-173716.17"
+ attribute \src "libresoc.v:171426.9-171426.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\r_busy$next[0:0]$10320 1'1
+ assign $1\dividend_neg$next[0:0]$10213 \dividend_neg$93
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\r_busy$next[0:0]$10320 1'0
+ assign $1\dividend_neg$next[0:0]$10213 \dividend_neg$93
case
- assign $1\r_busy$next[0:0]$10320 \r_busy
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\r_busy$next[0:0]$10321 1'0
- case
- assign $2\r_busy$next[0:0]$10321 $1\r_busy$next[0:0]$10320
+ assign $1\dividend_neg$next[0:0]$10213 \dividend_neg
end
sync always
- update \r_busy$next $0\r_busy$next[0:0]$10319
+ update \dividend_neg$next $0\dividend_neg$next[0:0]$10212
end
- attribute \src "libresoc.v:173733.3-173745.6"
- process $proc$libresoc.v:173733$10322
+ attribute \src "libresoc.v:171438.3-171450.6"
+ process $proc$libresoc.v:171438$10214
assign { } { }
assign { } { }
- assign $0\muxid$next[1:0]$10323 $1\muxid$next[1:0]$10324
- attribute \src "libresoc.v:173734.5-173734.29"
+ assign $0\dive_abs_ov32$next[0:0]$10215 $1\dive_abs_ov32$next[0:0]$10216
+ attribute \src "libresoc.v:171439.5-171439.29"
switch \initial
- attribute \src "libresoc.v:173734.9-173734.17"
+ attribute \src "libresoc.v:171439.9-171439.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\muxid$next[1:0]$10324 \muxid$68
+ assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32$94
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\muxid$next[1:0]$10324 \muxid$68
+ assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32$94
case
- assign $1\muxid$next[1:0]$10324 \muxid
+ assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32
end
sync always
- update \muxid$next $0\muxid$next[1:0]$10323
+ update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10215
end
- attribute \src "libresoc.v:173746.3-173787.6"
- process $proc$libresoc.v:173746$10325
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
+ attribute \src "libresoc.v:171451.3-171463.6"
+ process $proc$libresoc.v:171451$10217
assign { } { }
assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\logical_op__data_len$next[3:0]$10326 $1\logical_op__data_len$next[3:0]$10344
- assign $0\logical_op__fn_unit$next[12:0]$10327 $1\logical_op__fn_unit$next[12:0]$10345
- assign { } { }
- assign { } { }
- assign $0\logical_op__input_carry$next[1:0]$10330 $1\logical_op__input_carry$next[1:0]$10348
- assign $0\logical_op__insn$next[31:0]$10331 $1\logical_op__insn$next[31:0]$10349
- assign $0\logical_op__insn_type$next[6:0]$10332 $1\logical_op__insn_type$next[6:0]$10350
- assign $0\logical_op__invert_in$next[0:0]$10333 $1\logical_op__invert_in$next[0:0]$10351
- assign $0\logical_op__invert_out$next[0:0]$10334 $1\logical_op__invert_out$next[0:0]$10352
- assign $0\logical_op__is_32bit$next[0:0]$10335 $1\logical_op__is_32bit$next[0:0]$10353
- assign $0\logical_op__is_signed$next[0:0]$10336 $1\logical_op__is_signed$next[0:0]$10354
- assign { } { }
- assign { } { }
- assign $0\logical_op__output_carry$next[0:0]$10339 $1\logical_op__output_carry$next[0:0]$10357
- assign { } { }
- assign { } { }
- assign $0\logical_op__write_cr0$next[0:0]$10342 $1\logical_op__write_cr0$next[0:0]$10360
- assign $0\logical_op__zero_a$next[0:0]$10343 $1\logical_op__zero_a$next[0:0]$10361
- assign $0\logical_op__imm_data__data$next[63:0]$10328 $2\logical_op__imm_data__data$next[63:0]$10362
- assign $0\logical_op__imm_data__ok$next[0:0]$10329 $2\logical_op__imm_data__ok$next[0:0]$10363
- assign $0\logical_op__oe__oe$next[0:0]$10337 $2\logical_op__oe__oe$next[0:0]$10364
- assign $0\logical_op__oe__ok$next[0:0]$10338 $2\logical_op__oe__ok$next[0:0]$10365
- assign $0\logical_op__rc__ok$next[0:0]$10340 $2\logical_op__rc__ok$next[0:0]$10366
- assign $0\logical_op__rc__rc$next[0:0]$10341 $2\logical_op__rc__rc$next[0:0]$10367
- attribute \src "libresoc.v:173747.5-173747.29"
+ assign $0\dive_abs_ov64$next[0:0]$10218 $1\dive_abs_ov64$next[0:0]$10219
+ attribute \src "libresoc.v:171452.5-171452.29"
switch \initial
- attribute \src "libresoc.v:173747.9-173747.17"
+ attribute \src "libresoc.v:171452.9-171452.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { $1\logical_op__insn$next[31:0]$10349 $1\logical_op__data_len$next[3:0]$10344 $1\logical_op__is_signed$next[0:0]$10354 $1\logical_op__is_32bit$next[0:0]$10353 $1\logical_op__output_carry$next[0:0]$10357 $1\logical_op__write_cr0$next[0:0]$10360 $1\logical_op__invert_out$next[0:0]$10352 $1\logical_op__input_carry$next[1:0]$10348 $1\logical_op__zero_a$next[0:0]$10361 $1\logical_op__invert_in$next[0:0]$10351 $1\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__rc__ok$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10359 $1\logical_op__imm_data__ok$next[0:0]$10347 $1\logical_op__imm_data__data$next[63:0]$10346 $1\logical_op__fn_unit$next[12:0]$10345 $1\logical_op__insn_type$next[6:0]$10350 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
+ assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64$95
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { $1\logical_op__insn$next[31:0]$10349 $1\logical_op__data_len$next[3:0]$10344 $1\logical_op__is_signed$next[0:0]$10354 $1\logical_op__is_32bit$next[0:0]$10353 $1\logical_op__output_carry$next[0:0]$10357 $1\logical_op__write_cr0$next[0:0]$10360 $1\logical_op__invert_out$next[0:0]$10352 $1\logical_op__input_carry$next[1:0]$10348 $1\logical_op__zero_a$next[0:0]$10361 $1\logical_op__invert_in$next[0:0]$10351 $1\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__rc__ok$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10359 $1\logical_op__imm_data__ok$next[0:0]$10347 $1\logical_op__imm_data__data$next[63:0]$10346 $1\logical_op__fn_unit$next[12:0]$10345 $1\logical_op__insn_type$next[6:0]$10350 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
- case
- assign $1\logical_op__data_len$next[3:0]$10344 \logical_op__data_len
- assign $1\logical_op__fn_unit$next[12:0]$10345 \logical_op__fn_unit
- assign $1\logical_op__imm_data__data$next[63:0]$10346 \logical_op__imm_data__data
- assign $1\logical_op__imm_data__ok$next[0:0]$10347 \logical_op__imm_data__ok
- assign $1\logical_op__input_carry$next[1:0]$10348 \logical_op__input_carry
- assign $1\logical_op__insn$next[31:0]$10349 \logical_op__insn
- assign $1\logical_op__insn_type$next[6:0]$10350 \logical_op__insn_type
- assign $1\logical_op__invert_in$next[0:0]$10351 \logical_op__invert_in
- assign $1\logical_op__invert_out$next[0:0]$10352 \logical_op__invert_out
- assign $1\logical_op__is_32bit$next[0:0]$10353 \logical_op__is_32bit
- assign $1\logical_op__is_signed$next[0:0]$10354 \logical_op__is_signed
- assign $1\logical_op__oe__oe$next[0:0]$10355 \logical_op__oe__oe
- assign $1\logical_op__oe__ok$next[0:0]$10356 \logical_op__oe__ok
- assign $1\logical_op__output_carry$next[0:0]$10357 \logical_op__output_carry
- assign $1\logical_op__rc__ok$next[0:0]$10358 \logical_op__rc__ok
- assign $1\logical_op__rc__rc$next[0:0]$10359 \logical_op__rc__rc
- assign $1\logical_op__write_cr0$next[0:0]$10360 \logical_op__write_cr0
- assign $1\logical_op__zero_a$next[0:0]$10361 \logical_op__zero_a
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \coresync_rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $2\logical_op__imm_data__data$next[63:0]$10362 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\logical_op__imm_data__ok$next[0:0]$10363 1'0
- assign $2\logical_op__rc__rc$next[0:0]$10367 1'0
- assign $2\logical_op__rc__ok$next[0:0]$10366 1'0
- assign $2\logical_op__oe__oe$next[0:0]$10364 1'0
- assign $2\logical_op__oe__ok$next[0:0]$10365 1'0
+ assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64$95
case
- assign $2\logical_op__imm_data__data$next[63:0]$10362 $1\logical_op__imm_data__data$next[63:0]$10346
- assign $2\logical_op__imm_data__ok$next[0:0]$10363 $1\logical_op__imm_data__ok$next[0:0]$10347
- assign $2\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__oe__oe$next[0:0]$10355
- assign $2\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__ok$next[0:0]$10356
- assign $2\logical_op__rc__ok$next[0:0]$10366 $1\logical_op__rc__ok$next[0:0]$10358
- assign $2\logical_op__rc__rc$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10359
+ assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64
end
sync always
- update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10326
- update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10327
- update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10328
- update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10329
- update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10330
- update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10331
- update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10332
- update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10333
- update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10334
- update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10335
- update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10336
- update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10337
- update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10338
- update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10339
- update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10340
- update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10341
- update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10342
- update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10343
+ update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10218
end
- attribute \src "libresoc.v:173788.3-173800.6"
- process $proc$libresoc.v:173788$10368
+ attribute \src "libresoc.v:171464.3-171476.6"
+ process $proc$libresoc.v:171464$10220
assign { } { }
assign { } { }
- assign $0\ra$next[63:0]$10369 $1\ra$next[63:0]$10370
- attribute \src "libresoc.v:173789.5-173789.29"
+ assign $0\div_by_zero$next[0:0]$10221 $1\div_by_zero$next[0:0]$10222
+ attribute \src "libresoc.v:171465.5-171465.29"
switch \initial
- attribute \src "libresoc.v:173789.9-173789.17"
+ attribute \src "libresoc.v:171465.9-171465.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ra$next[63:0]$10370 \ra$87
+ assign $1\div_by_zero$next[0:0]$10222 \div_by_zero$96
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ra$next[63:0]$10370 \ra$87
+ assign $1\div_by_zero$next[0:0]$10222 \div_by_zero$96
case
- assign $1\ra$next[63:0]$10370 \ra
+ assign $1\div_by_zero$next[0:0]$10222 \div_by_zero
end
sync always
- update \ra$next $0\ra$next[63:0]$10369
+ update \div_by_zero$next $0\div_by_zero$next[0:0]$10221
end
- attribute \src "libresoc.v:173801.3-173813.6"
- process $proc$libresoc.v:173801$10371
+ attribute \src "libresoc.v:171477.3-171489.6"
+ process $proc$libresoc.v:171477$10223
assign { } { }
assign { } { }
- assign $0\rb$next[63:0]$10372 $1\rb$next[63:0]$10373
- attribute \src "libresoc.v:173802.5-173802.29"
+ assign $0\dividend$next[127:0]$10224 $1\dividend$next[127:0]$10225
+ attribute \src "libresoc.v:171478.5-171478.29"
switch \initial
- attribute \src "libresoc.v:173802.9-173802.17"
+ attribute \src "libresoc.v:171478.9-171478.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\rb$next[63:0]$10373 \rb$89
+ assign $1\dividend$next[127:0]$10225 \dividend$97
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\rb$next[63:0]$10373 \rb$89
+ assign $1\dividend$next[127:0]$10225 \dividend$97
case
- assign $1\rb$next[63:0]$10373 \rb
+ assign $1\dividend$next[127:0]$10225 \dividend
end
sync always
- update \rb$next $0\rb$next[63:0]$10372
+ update \dividend$next $0\dividend$next[127:0]$10224
end
- attribute \src "libresoc.v:173814.3-173826.6"
- process $proc$libresoc.v:173814$10374
+ attribute \src "libresoc.v:171490.3-171502.6"
+ process $proc$libresoc.v:171490$10226
assign { } { }
assign { } { }
- assign $0\xer_so$next[0:0]$10375 $1\xer_so$next[0:0]$10376
- attribute \src "libresoc.v:173815.5-173815.29"
+ assign $0\divisor_radicand$next[63:0]$10227 $1\divisor_radicand$next[63:0]$10228
+ attribute \src "libresoc.v:171491.5-171491.29"
switch \initial
- attribute \src "libresoc.v:173815.9-173815.17"
+ attribute \src "libresoc.v:171491.9-171491.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\xer_so$next[0:0]$10376 \xer_so$91
+ assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand$98
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\xer_so$next[0:0]$10376 \xer_so$91
+ assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand$98
case
- assign $1\xer_so$next[0:0]$10376 \xer_so
+ assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand
end
sync always
- update \xer_so$next $0\xer_so$next[0:0]$10375
+ update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10227
end
- connect \$66 $and$libresoc.v:173442$10262_Y
- connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000
- connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000
- connect \p_ready_o \n_i_rdy_data
- connect \n_valid_o \r_busy
- connect \operation$99 \setup_stage_operation
- connect \divisor_radicand$98 \setup_stage_divisor_radicand
- connect \dividend$97 \setup_stage_dividend
- connect \div_by_zero$96 \setup_stage_div_by_zero
- connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64
- connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32
- connect \dividend_neg$93 \setup_stage_dividend_neg
- connect \divisor_neg$92 \setup_stage_divisor_neg
- connect \xer_so$91 \setup_stage_xer_so$64
- connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000
- connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000
- connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 }
- connect \muxid$68 \setup_stage_muxid$45
- connect \p_valid_i_p_ready_o \$66
- connect \n_i_rdy_data \n_ready_i
- connect \p_valid_i$65 \p_valid_i
- connect \setup_stage_xer_so \input_xer_so$44
- connect \setup_stage_rb \input_rb$43
- connect \setup_stage_ra \input_ra$42
- connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 }
- connect \setup_stage_muxid \input_muxid$23
- connect \input_xer_so \xer_so$22
- connect \input_rb \rb$21
- connect \input_ra \ra$20
- connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 }
- connect \input_muxid \muxid$1
-end
-attribute \src "libresoc.v:173861.1-173905.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.pll"
-attribute \generator "nMigen"
-module \pll
- attribute \src "libresoc.v:173862.7-173862.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:173894.3-173903.6"
- wire $0\pll_18_o[0:0]
- attribute \src "libresoc.v:173884.3-173893.6"
- wire $0\pll_lck_o[0:0]
- attribute \src "libresoc.v:173894.3-173903.6"
- wire $1\pll_18_o[0:0]
- attribute \src "libresoc.v:173884.3-173893.6"
- wire $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:173881.17-173881.105"
- wire $eq$libresoc.v:173881$10409_Y
- attribute \src "libresoc.v:173882.17-173882.105"
- wire $eq$libresoc.v:173882$10410_Y
- attribute \src "libresoc.v:173883.17-173883.98"
- wire $not$libresoc.v:173883$10411_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21"
- wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
- wire input 1 \clk_24_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
- wire output 5 \clk_pll_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
- wire width 2 input 3 \clk_sel_i
- attribute \src "libresoc.v:173862.7-173862.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
- wire output 2 \pll_18_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
- wire output 4 \pll_lck_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:173881$10409
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \clk_sel_i
- connect \B 2'00
- connect \Y $eq$libresoc.v:173881$10409_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:173882$10410
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \clk_sel_i
- connect \B 2'00
- connect \Y $eq$libresoc.v:173882$10410_Y
+ attribute \src "libresoc.v:171503.3-171515.6"
+ process $proc$libresoc.v:171503$10229
+ assign { } { }
+ assign { } { }
+ assign $0\operation$next[1:0]$10230 $1\operation$next[1:0]$10231
+ attribute \src "libresoc.v:171504.5-171504.29"
+ switch \initial
+ attribute \src "libresoc.v:171504.9-171504.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $1\operation$next[1:0]$10231 \operation$99
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\operation$next[1:0]$10231 \operation$99
+ case
+ assign $1\operation$next[1:0]$10231 \operation
+ end
+ sync always
+ update \operation$next $0\operation$next[1:0]$10230
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21"
- cell $not $not$libresoc.v:173883$10411
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \clk_24_i
- connect \Y $not$libresoc.v:173883$10411_Y
+ attribute \src "libresoc.v:171516.3-171533.6"
+ process $proc$libresoc.v:171516$10232
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\r_busy$next[0:0]$10233 $2\r_busy$next[0:0]$10235
+ attribute \src "libresoc.v:171517.5-171517.29"
+ switch \initial
+ attribute \src "libresoc.v:171517.9-171517.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $1\r_busy$next[0:0]$10234 1'1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\r_busy$next[0:0]$10234 1'0
+ case
+ assign $1\r_busy$next[0:0]$10234 \r_busy
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\r_busy$next[0:0]$10235 1'0
+ case
+ assign $2\r_busy$next[0:0]$10235 $1\r_busy$next[0:0]$10234
+ end
+ sync always
+ update \r_busy$next $0\r_busy$next[0:0]$10233
end
- attribute \src "libresoc.v:173862.7-173862.20"
- process $proc$libresoc.v:173862$10414
+ attribute \src "libresoc.v:171534.3-171546.6"
+ process $proc$libresoc.v:171534$10236
assign { } { }
- assign $0\initial[0:0] 1'0
+ assign { } { }
+ assign $0\muxid$next[1:0]$10237 $1\muxid$next[1:0]$10238
+ attribute \src "libresoc.v:171535.5-171535.29"
+ switch \initial
+ attribute \src "libresoc.v:171535.9-171535.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $1\muxid$next[1:0]$10238 \muxid$68
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\muxid$next[1:0]$10238 \muxid$68
+ case
+ assign $1\muxid$next[1:0]$10238 \muxid
+ end
sync always
- update \initial $0\initial[0:0]
- sync init
+ update \muxid$next $0\muxid$next[1:0]$10237
end
- attribute \src "libresoc.v:173884.3-173893.6"
- process $proc$libresoc.v:173884$10412
+ attribute \src "libresoc.v:171547.3-171588.6"
+ process $proc$libresoc.v:171547$10239
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\logical_op__data_len$next[3:0]$10240 $1\logical_op__data_len$next[3:0]$10258
+ assign $0\logical_op__fn_unit$next[12:0]$10241 $1\logical_op__fn_unit$next[12:0]$10259
+ assign { } { }
+ assign { } { }
+ assign $0\logical_op__input_carry$next[1:0]$10244 $1\logical_op__input_carry$next[1:0]$10262
+ assign $0\logical_op__insn$next[31:0]$10245 $1\logical_op__insn$next[31:0]$10263
+ assign $0\logical_op__insn_type$next[6:0]$10246 $1\logical_op__insn_type$next[6:0]$10264
+ assign $0\logical_op__invert_in$next[0:0]$10247 $1\logical_op__invert_in$next[0:0]$10265
+ assign $0\logical_op__invert_out$next[0:0]$10248 $1\logical_op__invert_out$next[0:0]$10266
+ assign $0\logical_op__is_32bit$next[0:0]$10249 $1\logical_op__is_32bit$next[0:0]$10267
+ assign $0\logical_op__is_signed$next[0:0]$10250 $1\logical_op__is_signed$next[0:0]$10268
+ assign { } { }
assign { } { }
+ assign $0\logical_op__output_carry$next[0:0]$10253 $1\logical_op__output_carry$next[0:0]$10271
assign { } { }
- assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:173885.5-173885.29"
+ assign { } { }
+ assign $0\logical_op__write_cr0$next[0:0]$10256 $1\logical_op__write_cr0$next[0:0]$10274
+ assign $0\logical_op__zero_a$next[0:0]$10257 $1\logical_op__zero_a$next[0:0]$10275
+ assign $0\logical_op__imm_data__data$next[63:0]$10242 $2\logical_op__imm_data__data$next[63:0]$10276
+ assign $0\logical_op__imm_data__ok$next[0:0]$10243 $2\logical_op__imm_data__ok$next[0:0]$10277
+ assign $0\logical_op__oe__oe$next[0:0]$10251 $2\logical_op__oe__oe$next[0:0]$10278
+ assign $0\logical_op__oe__ok$next[0:0]$10252 $2\logical_op__oe__ok$next[0:0]$10279
+ assign $0\logical_op__rc__ok$next[0:0]$10254 $2\logical_op__rc__ok$next[0:0]$10280
+ assign $0\logical_op__rc__rc$next[0:0]$10255 $2\logical_op__rc__rc$next[0:0]$10281
+ attribute \src "libresoc.v:171548.5-171548.29"
switch \initial
- attribute \src "libresoc.v:173885.9-173885.17"
+ attribute \src "libresoc.v:171548.9-171548.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- switch \$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { $1\logical_op__insn$next[31:0]$10263 $1\logical_op__data_len$next[3:0]$10258 $1\logical_op__is_signed$next[0:0]$10268 $1\logical_op__is_32bit$next[0:0]$10267 $1\logical_op__output_carry$next[0:0]$10271 $1\logical_op__write_cr0$next[0:0]$10274 $1\logical_op__invert_out$next[0:0]$10266 $1\logical_op__input_carry$next[1:0]$10262 $1\logical_op__zero_a$next[0:0]$10275 $1\logical_op__invert_in$next[0:0]$10265 $1\logical_op__oe__ok$next[0:0]$10270 $1\logical_op__oe__oe$next[0:0]$10269 $1\logical_op__rc__ok$next[0:0]$10272 $1\logical_op__rc__rc$next[0:0]$10273 $1\logical_op__imm_data__ok$next[0:0]$10261 $1\logical_op__imm_data__data$next[63:0]$10260 $1\logical_op__fn_unit$next[12:0]$10259 $1\logical_op__insn_type$next[6:0]$10264 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { $1\logical_op__insn$next[31:0]$10263 $1\logical_op__data_len$next[3:0]$10258 $1\logical_op__is_signed$next[0:0]$10268 $1\logical_op__is_32bit$next[0:0]$10267 $1\logical_op__output_carry$next[0:0]$10271 $1\logical_op__write_cr0$next[0:0]$10274 $1\logical_op__invert_out$next[0:0]$10266 $1\logical_op__input_carry$next[1:0]$10262 $1\logical_op__zero_a$next[0:0]$10275 $1\logical_op__invert_in$next[0:0]$10265 $1\logical_op__oe__ok$next[0:0]$10270 $1\logical_op__oe__oe$next[0:0]$10269 $1\logical_op__rc__ok$next[0:0]$10272 $1\logical_op__rc__rc$next[0:0]$10273 $1\logical_op__imm_data__ok$next[0:0]$10261 $1\logical_op__imm_data__data$next[63:0]$10260 $1\logical_op__fn_unit$next[12:0]$10259 $1\logical_op__insn_type$next[6:0]$10264 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 }
+ case
+ assign $1\logical_op__data_len$next[3:0]$10258 \logical_op__data_len
+ assign $1\logical_op__fn_unit$next[12:0]$10259 \logical_op__fn_unit
+ assign $1\logical_op__imm_data__data$next[63:0]$10260 \logical_op__imm_data__data
+ assign $1\logical_op__imm_data__ok$next[0:0]$10261 \logical_op__imm_data__ok
+ assign $1\logical_op__input_carry$next[1:0]$10262 \logical_op__input_carry
+ assign $1\logical_op__insn$next[31:0]$10263 \logical_op__insn
+ assign $1\logical_op__insn_type$next[6:0]$10264 \logical_op__insn_type
+ assign $1\logical_op__invert_in$next[0:0]$10265 \logical_op__invert_in
+ assign $1\logical_op__invert_out$next[0:0]$10266 \logical_op__invert_out
+ assign $1\logical_op__is_32bit$next[0:0]$10267 \logical_op__is_32bit
+ assign $1\logical_op__is_signed$next[0:0]$10268 \logical_op__is_signed
+ assign $1\logical_op__oe__oe$next[0:0]$10269 \logical_op__oe__oe
+ assign $1\logical_op__oe__ok$next[0:0]$10270 \logical_op__oe__ok
+ assign $1\logical_op__output_carry$next[0:0]$10271 \logical_op__output_carry
+ assign $1\logical_op__rc__ok$next[0:0]$10272 \logical_op__rc__ok
+ assign $1\logical_op__rc__rc$next[0:0]$10273 \logical_op__rc__rc
+ assign $1\logical_op__write_cr0$next[0:0]$10274 \logical_op__write_cr0
+ assign $1\logical_op__zero_a$next[0:0]$10275 \logical_op__zero_a
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pll_lck_o[0:0] \clk_24_i
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $2\logical_op__imm_data__data$next[63:0]$10276 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\logical_op__imm_data__ok$next[0:0]$10277 1'0
+ assign $2\logical_op__rc__rc$next[0:0]$10281 1'0
+ assign $2\logical_op__rc__ok$next[0:0]$10280 1'0
+ assign $2\logical_op__oe__oe$next[0:0]$10278 1'0
+ assign $2\logical_op__oe__ok$next[0:0]$10279 1'0
case
- assign $1\pll_lck_o[0:0] 1'0
+ assign $2\logical_op__imm_data__data$next[63:0]$10276 $1\logical_op__imm_data__data$next[63:0]$10260
+ assign $2\logical_op__imm_data__ok$next[0:0]$10277 $1\logical_op__imm_data__ok$next[0:0]$10261
+ assign $2\logical_op__oe__oe$next[0:0]$10278 $1\logical_op__oe__oe$next[0:0]$10269
+ assign $2\logical_op__oe__ok$next[0:0]$10279 $1\logical_op__oe__ok$next[0:0]$10270
+ assign $2\logical_op__rc__ok$next[0:0]$10280 $1\logical_op__rc__ok$next[0:0]$10272
+ assign $2\logical_op__rc__rc$next[0:0]$10281 $1\logical_op__rc__rc$next[0:0]$10273
end
sync always
- update \pll_lck_o $0\pll_lck_o[0:0]
+ update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10240
+ update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10241
+ update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10242
+ update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10243
+ update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10244
+ update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10245
+ update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10246
+ update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10247
+ update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10248
+ update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10249
+ update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10250
+ update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10251
+ update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10252
+ update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10253
+ update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10254
+ update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10255
+ update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10256
+ update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10257
end
- attribute \src "libresoc.v:173894.3-173903.6"
- process $proc$libresoc.v:173894$10413
+ attribute \src "libresoc.v:171589.3-171601.6"
+ process $proc$libresoc.v:171589$10282
assign { } { }
assign { } { }
- assign $0\pll_18_o[0:0] $1\pll_18_o[0:0]
- attribute \src "libresoc.v:173895.5-173895.29"
+ assign $0\ra$next[63:0]$10283 $1\ra$next[63:0]$10284
+ attribute \src "libresoc.v:171590.5-171590.29"
switch \initial
- attribute \src "libresoc.v:173895.9-173895.17"
+ attribute \src "libresoc.v:171590.9-171590.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- switch \$3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $1\ra$next[63:0]$10284 \ra$87
attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\ra$next[63:0]$10284 \ra$87
+ case
+ assign $1\ra$next[63:0]$10284 \ra
+ end
+ sync always
+ update \ra$next $0\ra$next[63:0]$10283
+ end
+ attribute \src "libresoc.v:171602.3-171614.6"
+ process $proc$libresoc.v:171602$10285
+ assign { } { }
+ assign { } { }
+ assign $0\rb$next[63:0]$10286 $1\rb$next[63:0]$10287
+ attribute \src "libresoc.v:171603.5-171603.29"
+ switch \initial
+ attribute \src "libresoc.v:171603.9-171603.17"
case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
assign { } { }
- assign $1\pll_18_o[0:0] \$5
+ assign $1\rb$next[63:0]$10287 \rb$89
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\rb$next[63:0]$10287 \rb$89
+ case
+ assign $1\rb$next[63:0]$10287 \rb
+ end
+ sync always
+ update \rb$next $0\rb$next[63:0]$10286
+ end
+ attribute \src "libresoc.v:171615.3-171627.6"
+ process $proc$libresoc.v:171615$10288
+ assign { } { }
+ assign { } { }
+ assign $0\xer_so$next[0:0]$10289 $1\xer_so$next[0:0]$10290
+ attribute \src "libresoc.v:171616.5-171616.29"
+ switch \initial
+ attribute \src "libresoc.v:171616.9-171616.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $1\xer_so$next[0:0]$10290 \xer_so$91
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $1\xer_so$next[0:0]$10290 \xer_so$91
case
- assign $1\pll_18_o[0:0] 1'0
+ assign $1\xer_so$next[0:0]$10290 \xer_so
end
sync always
- update \pll_18_o $0\pll_18_o[0:0]
+ update \xer_so$next $0\xer_so$next[0:0]$10289
end
- connect \$1 $eq$libresoc.v:173881$10409_Y
- connect \$3 $eq$libresoc.v:173882$10410_Y
- connect \$5 $not$libresoc.v:173883$10411_Y
- connect \clk_pll_o \clk_24_i
+ connect \$66 $and$libresoc.v:171243$10176_Y
+ connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000
+ connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000
+ connect \p_ready_o \n_i_rdy_data
+ connect \n_valid_o \r_busy
+ connect \operation$99 \setup_stage_operation
+ connect \divisor_radicand$98 \setup_stage_divisor_radicand
+ connect \dividend$97 \setup_stage_dividend
+ connect \div_by_zero$96 \setup_stage_div_by_zero
+ connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64
+ connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32
+ connect \dividend_neg$93 \setup_stage_dividend_neg
+ connect \divisor_neg$92 \setup_stage_divisor_neg
+ connect \xer_so$91 \setup_stage_xer_so$64
+ connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000
+ connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000
+ connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 }
+ connect \muxid$68 \setup_stage_muxid$45
+ connect \p_valid_i_p_ready_o \$66
+ connect \n_i_rdy_data \n_ready_i
+ connect \p_valid_i$65 \p_valid_i
+ connect \setup_stage_xer_so \input_xer_so$44
+ connect \setup_stage_rb \input_rb$43
+ connect \setup_stage_ra \input_ra$42
+ connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 }
+ connect \setup_stage_muxid \input_muxid$23
+ connect \input_xer_so \xer_so$22
+ connect \input_rb \rb$21
+ connect \input_ra \ra$20
+ connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 }
+ connect \input_muxid \muxid$1
end
-attribute \src "libresoc.v:173909.1-174551.10"
+attribute \src "libresoc.v:171662.1-172304.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount"
attribute \generator "nMigen"
module \popcount
- attribute \src "libresoc.v:173910.7-173910.20"
+ attribute \src "libresoc.v:171663.7-171663.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:174398.3-174424.6"
+ attribute \src "libresoc.v:172151.3-172177.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:174398.3-174424.6"
+ attribute \src "libresoc.v:172151.3-172177.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:174322.19-174322.132"
- wire width 4 $add$libresoc.v:174322$10415_Y
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- wire width 4 $add$libresoc.v:174323$10416_Y
- attribute \src "libresoc.v:174324.19-174324.132"
- wire width 4 $add$libresoc.v:174324$10417_Y
- attribute \src "libresoc.v:174325.19-174325.132"
- wire width 4 $add$libresoc.v:174325$10418_Y
- attribute \src "libresoc.v:174326.19-174326.134"
- wire width 4 $add$libresoc.v:174326$10419_Y
- attribute \src "libresoc.v:174327.19-174327.134"
- wire width 4 $add$libresoc.v:174327$10420_Y
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- wire width 3 $add$libresoc.v:174328$10421_Y
- attribute \src "libresoc.v:174329.19-174329.134"
- wire width 4 $add$libresoc.v:174329$10422_Y
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- wire width 4 $add$libresoc.v:174330$10423_Y
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- wire width 4 $add$libresoc.v:174331$10424_Y
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- wire width 4 $add$libresoc.v:174332$10425_Y
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- wire width 4 $add$libresoc.v:174333$10426_Y
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- wire width 4 $add$libresoc.v:174334$10427_Y
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- wire width 4 $add$libresoc.v:174335$10428_Y
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- wire width 4 $add$libresoc.v:174336$10429_Y
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- wire width 4 $add$libresoc.v:174337$10430_Y
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- wire width 5 $add$libresoc.v:174338$10431_Y
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- wire width 3 $add$libresoc.v:174339$10432_Y
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- wire width 5 $add$libresoc.v:174340$10433_Y
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- wire width 5 $add$libresoc.v:174341$10434_Y
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- wire width 5 $add$libresoc.v:174342$10435_Y
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- wire width 5 $add$libresoc.v:174343$10436_Y
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- wire width 5 $add$libresoc.v:174344$10437_Y
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- wire width 5 $add$libresoc.v:174346$10439_Y
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- wire width 6 $add$libresoc.v:174349$10442_Y
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- wire width 6 $add$libresoc.v:174351$10444_Y
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- wire width 7 $add$libresoc.v:174352$10445_Y
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- wire width 7 $add$libresoc.v:174353$10446_Y
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- wire width 8 $add$libresoc.v:174354$10447_Y
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- wire width 3 $add$libresoc.v:174365$10466_Y
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- wire width 3 $add$libresoc.v:174369$10473_Y
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- wire width 3 $add$libresoc.v:174370$10474_Y
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- wire width 3 $add$libresoc.v:174371$10475_Y
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- wire width 3 $add$libresoc.v:174372$10476_Y
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- wire width 3 $add$libresoc.v:174373$10477_Y
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- wire width 3 $add$libresoc.v:174374$10478_Y
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- wire width 3 $add$libresoc.v:174375$10479_Y
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- wire width 3 $add$libresoc.v:174376$10480_Y
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- wire width 3 $add$libresoc.v:174377$10481_Y
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- wire width 3 $add$libresoc.v:174381$10485_Y
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- wire width 3 $add$libresoc.v:174382$10486_Y
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- wire width 3 $add$libresoc.v:174383$10487_Y
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- wire width 3 $add$libresoc.v:174384$10488_Y
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- wire width 3 $add$libresoc.v:174385$10489_Y
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- wire width 3 $add$libresoc.v:174386$10490_Y
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- wire width 3 $add$libresoc.v:174387$10491_Y
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- wire width 3 $add$libresoc.v:174388$10492_Y
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- wire width 3 $add$libresoc.v:174389$10493_Y
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- wire width 3 $add$libresoc.v:174390$10494_Y
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- wire width 3 $add$libresoc.v:174391$10495_Y
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- wire width 3 $add$libresoc.v:174392$10496_Y
- attribute \src "libresoc.v:174393.17-174393.124"
- wire width 3 $add$libresoc.v:174393$10497_Y
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- wire width 3 $add$libresoc.v:174394$10498_Y
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- wire width 3 $add$libresoc.v:174395$10499_Y
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- wire width 3 $add$libresoc.v:174396$10500_Y
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- wire width 4 $add$libresoc.v:174397$10501_Y
- attribute \src "libresoc.v:174355.19-174355.111"
- wire $eq$libresoc.v:174355$10448_Y
- attribute \src "libresoc.v:174356.19-174356.111"
- wire $eq$libresoc.v:174356$10449_Y
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- wire width 8 $extend$libresoc.v:174357$10450_Y
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- wire width 8 $extend$libresoc.v:174361$10458_Y
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- wire width 8 $extend$libresoc.v:174362$10460_Y
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- wire width 8 $extend$libresoc.v:174363$10462_Y
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- wire width 8 $extend$libresoc.v:174364$10464_Y
- attribute \src "libresoc.v:174366.19-174366.104"
- wire width 32 $extend$libresoc.v:174366$10467_Y
- attribute \src "libresoc.v:174367.19-174367.104"
- wire width 32 $extend$libresoc.v:174367$10469_Y
- attribute \src "libresoc.v:174368.19-174368.104"
- wire width 64 $extend$libresoc.v:174368$10471_Y
- attribute \src "libresoc.v:174357.19-174357.104"
- wire width 8 $pos$libresoc.v:174357$10451_Y
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- wire width 8 $pos$libresoc.v:174358$10453_Y
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- wire width 8 $pos$libresoc.v:174359$10455_Y
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- wire width 64 $pos$libresoc.v:174368$10472_Y
+ attribute \src "libresoc.v:172075.19-172075.132"
+ wire width 4 $add$libresoc.v:172075$10323_Y
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+ wire width 4 $add$libresoc.v:172077$10325_Y
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+ wire width 3 $add$libresoc.v:172081$10329_Y
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+ wire width 4 $add$libresoc.v:172085$10333_Y
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+ wire width 4 $add$libresoc.v:172087$10335_Y
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+ wire width 5 $add$libresoc.v:172091$10339_Y
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+ wire width 3 $add$libresoc.v:172092$10340_Y
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+ wire width 5 $add$libresoc.v:172093$10341_Y
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+ wire width 5 $add$libresoc.v:172094$10342_Y
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+ wire width 5 $add$libresoc.v:172095$10343_Y
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+ wire width 5 $add$libresoc.v:172096$10344_Y
+ attribute \src "libresoc.v:172097.19-172097.134"
+ wire width 5 $add$libresoc.v:172097$10345_Y
+ attribute \src "libresoc.v:172098.19-172098.134"
+ wire width 5 $add$libresoc.v:172098$10346_Y
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+ wire width 5 $add$libresoc.v:172099$10347_Y
+ attribute \src "libresoc.v:172100.19-172100.132"
+ wire width 6 $add$libresoc.v:172100$10348_Y
+ attribute \src "libresoc.v:172101.19-172101.132"
+ wire width 6 $add$libresoc.v:172101$10349_Y
+ attribute \src "libresoc.v:172102.19-172102.132"
+ wire width 6 $add$libresoc.v:172102$10350_Y
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+ wire width 3 $add$libresoc.v:172103$10351_Y
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+ wire width 6 $add$libresoc.v:172104$10352_Y
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+ wire width 7 $add$libresoc.v:172105$10353_Y
+ attribute \src "libresoc.v:172106.19-172106.132"
+ wire width 7 $add$libresoc.v:172106$10354_Y
+ attribute \src "libresoc.v:172107.19-172107.132"
+ wire width 8 $add$libresoc.v:172107$10355_Y
+ attribute \src "libresoc.v:172118.18-172118.127"
+ wire width 3 $add$libresoc.v:172118$10374_Y
+ attribute \src "libresoc.v:172122.18-172122.127"
+ wire width 3 $add$libresoc.v:172122$10381_Y
+ attribute \src "libresoc.v:172123.18-172123.127"
+ wire width 3 $add$libresoc.v:172123$10382_Y
+ attribute \src "libresoc.v:172124.17-172124.124"
+ wire width 3 $add$libresoc.v:172124$10383_Y
+ attribute \src "libresoc.v:172125.18-172125.127"
+ wire width 3 $add$libresoc.v:172125$10384_Y
+ attribute \src "libresoc.v:172126.18-172126.127"
+ wire width 3 $add$libresoc.v:172126$10385_Y
+ attribute \src "libresoc.v:172127.18-172127.127"
+ wire width 3 $add$libresoc.v:172127$10386_Y
+ attribute \src "libresoc.v:172128.18-172128.127"
+ wire width 3 $add$libresoc.v:172128$10387_Y
+ attribute \src "libresoc.v:172129.18-172129.127"
+ wire width 3 $add$libresoc.v:172129$10388_Y
+ attribute \src "libresoc.v:172130.18-172130.127"
+ wire width 3 $add$libresoc.v:172130$10389_Y
+ attribute \src "libresoc.v:172131.18-172131.127"
+ wire width 3 $add$libresoc.v:172131$10390_Y
+ attribute \src "libresoc.v:172132.18-172132.127"
+ wire width 3 $add$libresoc.v:172132$10391_Y
+ attribute \src "libresoc.v:172133.18-172133.127"
+ wire width 3 $add$libresoc.v:172133$10392_Y
+ attribute \src "libresoc.v:172134.18-172134.127"
+ wire width 3 $add$libresoc.v:172134$10393_Y
+ attribute \src "libresoc.v:172135.17-172135.124"
+ wire width 3 $add$libresoc.v:172135$10394_Y
+ attribute \src "libresoc.v:172136.18-172136.127"
+ wire width 3 $add$libresoc.v:172136$10395_Y
+ attribute \src "libresoc.v:172137.18-172137.127"
+ wire width 3 $add$libresoc.v:172137$10396_Y
+ attribute \src "libresoc.v:172138.18-172138.127"
+ wire width 3 $add$libresoc.v:172138$10397_Y
+ attribute \src "libresoc.v:172139.18-172139.127"
+ wire width 3 $add$libresoc.v:172139$10398_Y
+ attribute \src "libresoc.v:172140.18-172140.127"
+ wire width 3 $add$libresoc.v:172140$10399_Y
+ attribute \src "libresoc.v:172141.18-172141.127"
+ wire width 3 $add$libresoc.v:172141$10400_Y
+ attribute \src "libresoc.v:172142.18-172142.127"
+ wire width 3 $add$libresoc.v:172142$10401_Y
+ attribute \src "libresoc.v:172143.18-172143.127"
+ wire width 3 $add$libresoc.v:172143$10402_Y
+ attribute \src "libresoc.v:172144.18-172144.127"
+ wire width 3 $add$libresoc.v:172144$10403_Y
+ attribute \src "libresoc.v:172145.18-172145.127"
+ wire width 3 $add$libresoc.v:172145$10404_Y
+ attribute \src "libresoc.v:172146.17-172146.124"
+ wire width 3 $add$libresoc.v:172146$10405_Y
+ attribute \src "libresoc.v:172147.18-172147.127"
+ wire width 3 $add$libresoc.v:172147$10406_Y
+ attribute \src "libresoc.v:172148.18-172148.127"
+ wire width 3 $add$libresoc.v:172148$10407_Y
+ attribute \src "libresoc.v:172149.18-172149.127"
+ wire width 3 $add$libresoc.v:172149$10408_Y
+ attribute \src "libresoc.v:172150.18-172150.131"
+ wire width 4 $add$libresoc.v:172150$10409_Y
+ attribute \src "libresoc.v:172108.19-172108.111"
+ wire $eq$libresoc.v:172108$10356_Y
+ attribute \src "libresoc.v:172109.19-172109.111"
+ wire $eq$libresoc.v:172109$10357_Y
+ attribute \src "libresoc.v:172110.19-172110.104"
+ wire width 8 $extend$libresoc.v:172110$10358_Y
+ attribute \src "libresoc.v:172111.19-172111.104"
+ wire width 8 $extend$libresoc.v:172111$10360_Y
+ attribute \src "libresoc.v:172112.19-172112.104"
+ wire width 8 $extend$libresoc.v:172112$10362_Y
+ attribute \src "libresoc.v:172113.19-172113.104"
+ wire width 8 $extend$libresoc.v:172113$10364_Y
+ attribute \src "libresoc.v:172114.19-172114.104"
+ wire width 8 $extend$libresoc.v:172114$10366_Y
+ attribute \src "libresoc.v:172115.19-172115.104"
+ wire width 8 $extend$libresoc.v:172115$10368_Y
+ attribute \src "libresoc.v:172116.19-172116.104"
+ wire width 8 $extend$libresoc.v:172116$10370_Y
+ attribute \src "libresoc.v:172117.19-172117.104"
+ wire width 8 $extend$libresoc.v:172117$10372_Y
+ attribute \src "libresoc.v:172119.19-172119.104"
+ wire width 32 $extend$libresoc.v:172119$10375_Y
+ attribute \src "libresoc.v:172120.19-172120.104"
+ wire width 32 $extend$libresoc.v:172120$10377_Y
+ attribute \src "libresoc.v:172121.19-172121.104"
+ wire width 64 $extend$libresoc.v:172121$10379_Y
+ attribute \src "libresoc.v:172110.19-172110.104"
+ wire width 8 $pos$libresoc.v:172110$10359_Y
+ attribute \src "libresoc.v:172111.19-172111.104"
+ wire width 8 $pos$libresoc.v:172111$10361_Y
+ attribute \src "libresoc.v:172112.19-172112.104"
+ wire width 8 $pos$libresoc.v:172112$10363_Y
+ attribute \src "libresoc.v:172113.19-172113.104"
+ wire width 8 $pos$libresoc.v:172113$10365_Y
+ attribute \src "libresoc.v:172114.19-172114.104"
+ wire width 8 $pos$libresoc.v:172114$10367_Y
+ attribute \src "libresoc.v:172115.19-172115.104"
+ wire width 8 $pos$libresoc.v:172115$10369_Y
+ attribute \src "libresoc.v:172116.19-172116.104"
+ wire width 8 $pos$libresoc.v:172116$10371_Y
+ attribute \src "libresoc.v:172117.19-172117.104"
+ wire width 8 $pos$libresoc.v:172117$10373_Y
+ attribute \src "libresoc.v:172119.19-172119.104"
+ wire width 32 $pos$libresoc.v:172119$10376_Y
+ attribute \src "libresoc.v:172120.19-172120.104"
+ wire width 32 $pos$libresoc.v:172120$10378_Y
+ attribute \src "libresoc.v:172121.19-172121.104"
+ wire width 64 $pos$libresoc.v:172121$10380_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 64 input 3 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29"
wire width 64 input 1 \data_len
- attribute \src "libresoc.v:173910.7-173910.15"
+ attribute \src "libresoc.v:171663.7-171663.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30"
wire width 64 output 2 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 7 \pop_7_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174322$10415
+ cell $add $add$libresoc.v:172075$10323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_2 }
connect \B { 2'00 \pop_2_3 }
- connect \Y $add$libresoc.v:174322$10415_Y
+ connect \Y $add$libresoc.v:172075$10323_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174323$10416
+ cell $add $add$libresoc.v:172076$10324
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_4 }
connect \B { 2'00 \pop_2_5 }
- connect \Y $add$libresoc.v:174323$10416_Y
+ connect \Y $add$libresoc.v:172076$10324_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174324$10417
+ cell $add $add$libresoc.v:172077$10325
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_6 }
connect \B { 2'00 \pop_2_7 }
- connect \Y $add$libresoc.v:174324$10417_Y
+ connect \Y $add$libresoc.v:172077$10325_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174325$10418
+ cell $add $add$libresoc.v:172078$10326
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_8 }
connect \B { 2'00 \pop_2_9 }
- connect \Y $add$libresoc.v:174325$10418_Y
+ connect \Y $add$libresoc.v:172078$10326_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174326$10419
+ cell $add $add$libresoc.v:172079$10327
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_10 }
connect \B { 2'00 \pop_2_11 }
- connect \Y $add$libresoc.v:174326$10419_Y
+ connect \Y $add$libresoc.v:172079$10327_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174327$10420
+ cell $add $add$libresoc.v:172080$10328
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_12 }
connect \B { 2'00 \pop_2_13 }
- connect \Y $add$libresoc.v:174327$10420_Y
+ connect \Y $add$libresoc.v:172080$10328_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174328$10421
+ cell $add $add$libresoc.v:172081$10329
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [6] }
connect \B { 2'00 \a [7] }
- connect \Y $add$libresoc.v:174328$10421_Y
+ connect \Y $add$libresoc.v:172081$10329_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174329$10422
+ cell $add $add$libresoc.v:172082$10330
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_14 }
connect \B { 2'00 \pop_2_15 }
- connect \Y $add$libresoc.v:174329$10422_Y
+ connect \Y $add$libresoc.v:172082$10330_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174330$10423
+ cell $add $add$libresoc.v:172083$10331
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_16 }
connect \B { 2'00 \pop_2_17 }
- connect \Y $add$libresoc.v:174330$10423_Y
+ connect \Y $add$libresoc.v:172083$10331_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174331$10424
+ cell $add $add$libresoc.v:172084$10332
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_18 }
connect \B { 2'00 \pop_2_19 }
- connect \Y $add$libresoc.v:174331$10424_Y
+ connect \Y $add$libresoc.v:172084$10332_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174332$10425
+ cell $add $add$libresoc.v:172085$10333
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_20 }
connect \B { 2'00 \pop_2_21 }
- connect \Y $add$libresoc.v:174332$10425_Y
+ connect \Y $add$libresoc.v:172085$10333_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174333$10426
+ cell $add $add$libresoc.v:172086$10334
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_22 }
connect \B { 2'00 \pop_2_23 }
- connect \Y $add$libresoc.v:174333$10426_Y
+ connect \Y $add$libresoc.v:172086$10334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174334$10427
+ cell $add $add$libresoc.v:172087$10335
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_24 }
connect \B { 2'00 \pop_2_25 }
- connect \Y $add$libresoc.v:174334$10427_Y
+ connect \Y $add$libresoc.v:172087$10335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174335$10428
+ cell $add $add$libresoc.v:172088$10336
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_26 }
connect \B { 2'00 \pop_2_27 }
- connect \Y $add$libresoc.v:174335$10428_Y
+ connect \Y $add$libresoc.v:172088$10336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174336$10429
+ cell $add $add$libresoc.v:172089$10337
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_28 }
connect \B { 2'00 \pop_2_29 }
- connect \Y $add$libresoc.v:174336$10429_Y
+ connect \Y $add$libresoc.v:172089$10337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174337$10430
+ cell $add $add$libresoc.v:172090$10338
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_30 }
connect \B { 2'00 \pop_2_31 }
- connect \Y $add$libresoc.v:174337$10430_Y
+ connect \Y $add$libresoc.v:172090$10338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174338$10431
+ cell $add $add$libresoc.v:172091$10339
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_0 }
connect \B { 2'00 \pop_3_1 }
- connect \Y $add$libresoc.v:174338$10431_Y
+ connect \Y $add$libresoc.v:172091$10339_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174339$10432
+ cell $add $add$libresoc.v:172092$10340
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [8] }
connect \B { 2'00 \a [9] }
- connect \Y $add$libresoc.v:174339$10432_Y
+ connect \Y $add$libresoc.v:172092$10340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174340$10433
+ cell $add $add$libresoc.v:172093$10341
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_2 }
connect \B { 2'00 \pop_3_3 }
- connect \Y $add$libresoc.v:174340$10433_Y
+ connect \Y $add$libresoc.v:172093$10341_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174341$10434
+ cell $add $add$libresoc.v:172094$10342
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_4 }
connect \B { 2'00 \pop_3_5 }
- connect \Y $add$libresoc.v:174341$10434_Y
+ connect \Y $add$libresoc.v:172094$10342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174342$10435
+ cell $add $add$libresoc.v:172095$10343
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_6 }
connect \B { 2'00 \pop_3_7 }
- connect \Y $add$libresoc.v:174342$10435_Y
+ connect \Y $add$libresoc.v:172095$10343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174343$10436
+ cell $add $add$libresoc.v:172096$10344
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_8 }
connect \B { 2'00 \pop_3_9 }
- connect \Y $add$libresoc.v:174343$10436_Y
+ connect \Y $add$libresoc.v:172096$10344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174344$10437
+ cell $add $add$libresoc.v:172097$10345
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_10 }
connect \B { 2'00 \pop_3_11 }
- connect \Y $add$libresoc.v:174344$10437_Y
+ connect \Y $add$libresoc.v:172097$10345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174345$10438
+ cell $add $add$libresoc.v:172098$10346
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_12 }
connect \B { 2'00 \pop_3_13 }
- connect \Y $add$libresoc.v:174345$10438_Y
+ connect \Y $add$libresoc.v:172098$10346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174346$10439
+ cell $add $add$libresoc.v:172099$10347
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A { 2'00 \pop_3_14 }
connect \B { 2'00 \pop_3_15 }
- connect \Y $add$libresoc.v:174346$10439_Y
+ connect \Y $add$libresoc.v:172099$10347_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174347$10440
+ cell $add $add$libresoc.v:172100$10348
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_0 }
connect \B { 2'00 \pop_4_1 }
- connect \Y $add$libresoc.v:174347$10440_Y
+ connect \Y $add$libresoc.v:172100$10348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174348$10441
+ cell $add $add$libresoc.v:172101$10349
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_2 }
connect \B { 2'00 \pop_4_3 }
- connect \Y $add$libresoc.v:174348$10441_Y
+ connect \Y $add$libresoc.v:172101$10349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174349$10442
+ cell $add $add$libresoc.v:172102$10350
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_4 }
connect \B { 2'00 \pop_4_5 }
- connect \Y $add$libresoc.v:174349$10442_Y
+ connect \Y $add$libresoc.v:172102$10350_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174350$10443
+ cell $add $add$libresoc.v:172103$10351
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [10] }
connect \B { 2'00 \a [11] }
- connect \Y $add$libresoc.v:174350$10443_Y
+ connect \Y $add$libresoc.v:172103$10351_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174351$10444
+ cell $add $add$libresoc.v:172104$10352
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A { 2'00 \pop_4_6 }
connect \B { 2'00 \pop_4_7 }
- connect \Y $add$libresoc.v:174351$10444_Y
+ connect \Y $add$libresoc.v:172104$10352_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174352$10445
+ cell $add $add$libresoc.v:172105$10353
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A { 2'00 \pop_5_0 }
connect \B { 2'00 \pop_5_1 }
- connect \Y $add$libresoc.v:174352$10445_Y
+ connect \Y $add$libresoc.v:172105$10353_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174353$10446
+ cell $add $add$libresoc.v:172106$10354
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A { 2'00 \pop_5_2 }
connect \B { 2'00 \pop_5_3 }
- connect \Y $add$libresoc.v:174353$10446_Y
+ connect \Y $add$libresoc.v:172106$10354_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174354$10447
+ cell $add $add$libresoc.v:172107$10355
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A { 2'00 \pop_6_0 }
connect \B { 2'00 \pop_6_1 }
- connect \Y $add$libresoc.v:174354$10447_Y
+ connect \Y $add$libresoc.v:172107$10355_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174365$10466
+ cell $add $add$libresoc.v:172118$10374
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [12] }
connect \B { 2'00 \a [13] }
- connect \Y $add$libresoc.v:174365$10466_Y
+ connect \Y $add$libresoc.v:172118$10374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174369$10473
+ cell $add $add$libresoc.v:172122$10381
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [14] }
connect \B { 2'00 \a [15] }
- connect \Y $add$libresoc.v:174369$10473_Y
+ connect \Y $add$libresoc.v:172122$10381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174370$10474
+ cell $add $add$libresoc.v:172123$10382
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [16] }
connect \B { 2'00 \a [17] }
- connect \Y $add$libresoc.v:174370$10474_Y
+ connect \Y $add$libresoc.v:172123$10382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174371$10475
+ cell $add $add$libresoc.v:172124$10383
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [0] }
connect \B { 2'00 \a [1] }
- connect \Y $add$libresoc.v:174371$10475_Y
+ connect \Y $add$libresoc.v:172124$10383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174372$10476
+ cell $add $add$libresoc.v:172125$10384
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [18] }
connect \B { 2'00 \a [19] }
- connect \Y $add$libresoc.v:174372$10476_Y
+ connect \Y $add$libresoc.v:172125$10384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174373$10477
+ cell $add $add$libresoc.v:172126$10385
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [20] }
connect \B { 2'00 \a [21] }
- connect \Y $add$libresoc.v:174373$10477_Y
+ connect \Y $add$libresoc.v:172126$10385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174374$10478
+ cell $add $add$libresoc.v:172127$10386
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [22] }
connect \B { 2'00 \a [23] }
- connect \Y $add$libresoc.v:174374$10478_Y
+ connect \Y $add$libresoc.v:172127$10386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174375$10479
+ cell $add $add$libresoc.v:172128$10387
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [24] }
connect \B { 2'00 \a [25] }
- connect \Y $add$libresoc.v:174375$10479_Y
+ connect \Y $add$libresoc.v:172128$10387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174376$10480
+ cell $add $add$libresoc.v:172129$10388
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [26] }
connect \B { 2'00 \a [27] }
- connect \Y $add$libresoc.v:174376$10480_Y
+ connect \Y $add$libresoc.v:172129$10388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174377$10481
+ cell $add $add$libresoc.v:172130$10389
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [28] }
connect \B { 2'00 \a [29] }
- connect \Y $add$libresoc.v:174377$10481_Y
+ connect \Y $add$libresoc.v:172130$10389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174378$10482
+ cell $add $add$libresoc.v:172131$10390
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [30] }
connect \B { 2'00 \a [31] }
- connect \Y $add$libresoc.v:174378$10482_Y
+ connect \Y $add$libresoc.v:172131$10390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174379$10483
+ cell $add $add$libresoc.v:172132$10391
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [32] }
connect \B { 2'00 \a [33] }
- connect \Y $add$libresoc.v:174379$10483_Y
+ connect \Y $add$libresoc.v:172132$10391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174380$10484
+ cell $add $add$libresoc.v:172133$10392
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [34] }
connect \B { 2'00 \a [35] }
- connect \Y $add$libresoc.v:174380$10484_Y
+ connect \Y $add$libresoc.v:172133$10392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174381$10485
+ cell $add $add$libresoc.v:172134$10393
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [36] }
connect \B { 2'00 \a [37] }
- connect \Y $add$libresoc.v:174381$10485_Y
+ connect \Y $add$libresoc.v:172134$10393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174382$10486
+ cell $add $add$libresoc.v:172135$10394
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [2] }
connect \B { 2'00 \a [3] }
- connect \Y $add$libresoc.v:174382$10486_Y
+ connect \Y $add$libresoc.v:172135$10394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174383$10487
+ cell $add $add$libresoc.v:172136$10395
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [38] }
connect \B { 2'00 \a [39] }
- connect \Y $add$libresoc.v:174383$10487_Y
+ connect \Y $add$libresoc.v:172136$10395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174384$10488
+ cell $add $add$libresoc.v:172137$10396
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [40] }
connect \B { 2'00 \a [41] }
- connect \Y $add$libresoc.v:174384$10488_Y
+ connect \Y $add$libresoc.v:172137$10396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174385$10489
+ cell $add $add$libresoc.v:172138$10397
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [42] }
connect \B { 2'00 \a [43] }
- connect \Y $add$libresoc.v:174385$10489_Y
+ connect \Y $add$libresoc.v:172138$10397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174386$10490
+ cell $add $add$libresoc.v:172139$10398
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [44] }
connect \B { 2'00 \a [45] }
- connect \Y $add$libresoc.v:174386$10490_Y
+ connect \Y $add$libresoc.v:172139$10398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174387$10491
+ cell $add $add$libresoc.v:172140$10399
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [46] }
connect \B { 2'00 \a [47] }
- connect \Y $add$libresoc.v:174387$10491_Y
+ connect \Y $add$libresoc.v:172140$10399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174388$10492
+ cell $add $add$libresoc.v:172141$10400
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [48] }
connect \B { 2'00 \a [49] }
- connect \Y $add$libresoc.v:174388$10492_Y
+ connect \Y $add$libresoc.v:172141$10400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174389$10493
+ cell $add $add$libresoc.v:172142$10401
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [50] }
connect \B { 2'00 \a [51] }
- connect \Y $add$libresoc.v:174389$10493_Y
+ connect \Y $add$libresoc.v:172142$10401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174390$10494
+ cell $add $add$libresoc.v:172143$10402
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [52] }
connect \B { 2'00 \a [53] }
- connect \Y $add$libresoc.v:174390$10494_Y
+ connect \Y $add$libresoc.v:172143$10402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174391$10495
+ cell $add $add$libresoc.v:172144$10403
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [54] }
connect \B { 2'00 \a [55] }
- connect \Y $add$libresoc.v:174391$10495_Y
+ connect \Y $add$libresoc.v:172144$10403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174392$10496
+ cell $add $add$libresoc.v:172145$10404
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [56] }
connect \B { 2'00 \a [57] }
- connect \Y $add$libresoc.v:174392$10496_Y
+ connect \Y $add$libresoc.v:172145$10404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174393$10497
+ cell $add $add$libresoc.v:172146$10405
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [4] }
connect \B { 2'00 \a [5] }
- connect \Y $add$libresoc.v:174393$10497_Y
+ connect \Y $add$libresoc.v:172146$10405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174394$10498
+ cell $add $add$libresoc.v:172147$10406
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [58] }
connect \B { 2'00 \a [59] }
- connect \Y $add$libresoc.v:174394$10498_Y
+ connect \Y $add$libresoc.v:172147$10406_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174395$10499
+ cell $add $add$libresoc.v:172148$10407
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [60] }
connect \B { 2'00 \a [61] }
- connect \Y $add$libresoc.v:174395$10499_Y
+ connect \Y $add$libresoc.v:172148$10407_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174396$10500
+ cell $add $add$libresoc.v:172149$10408
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A { 2'00 \a [62] }
connect \B { 2'00 \a [63] }
- connect \Y $add$libresoc.v:174396$10500_Y
+ connect \Y $add$libresoc.v:172149$10408_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
- cell $add $add$libresoc.v:174397$10501
+ cell $add $add$libresoc.v:172150$10409
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A { 2'00 \pop_2_0 }
connect \B { 2'00 \pop_2_1 }
- connect \Y $add$libresoc.v:174397$10501_Y
+ connect \Y $add$libresoc.v:172150$10409_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55"
- cell $eq $eq$libresoc.v:174355$10448
+ cell $eq $eq$libresoc.v:172108$10356
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \data_len
connect \B 1'1
- connect \Y $eq$libresoc.v:174355$10448_Y
+ connect \Y $eq$libresoc.v:172108$10356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59"
- cell $eq $eq$libresoc.v:174356$10449
+ cell $eq $eq$libresoc.v:172109$10357
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \data_len
connect \B 3'100
- connect \Y $eq$libresoc.v:174356$10449_Y
+ connect \Y $eq$libresoc.v:172109$10357_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174357$10450
+ cell $pos $extend$libresoc.v:172110$10358
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_0
- connect \Y $extend$libresoc.v:174357$10450_Y
+ connect \Y $extend$libresoc.v:172110$10358_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174358$10452
+ cell $pos $extend$libresoc.v:172111$10360
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_1
- connect \Y $extend$libresoc.v:174358$10452_Y
+ connect \Y $extend$libresoc.v:172111$10360_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174359$10454
+ cell $pos $extend$libresoc.v:172112$10362
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_2
- connect \Y $extend$libresoc.v:174359$10454_Y
+ connect \Y $extend$libresoc.v:172112$10362_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174360$10456
+ cell $pos $extend$libresoc.v:172113$10364
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_3
- connect \Y $extend$libresoc.v:174360$10456_Y
+ connect \Y $extend$libresoc.v:172113$10364_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174361$10458
+ cell $pos $extend$libresoc.v:172114$10366
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_4
- connect \Y $extend$libresoc.v:174361$10458_Y
+ connect \Y $extend$libresoc.v:172114$10366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174362$10460
+ cell $pos $extend$libresoc.v:172115$10368
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_5
- connect \Y $extend$libresoc.v:174362$10460_Y
+ connect \Y $extend$libresoc.v:172115$10368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174363$10462
+ cell $pos $extend$libresoc.v:172116$10370
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_6
- connect \Y $extend$libresoc.v:174363$10462_Y
+ connect \Y $extend$libresoc.v:172116$10370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174364$10464
+ cell $pos $extend$libresoc.v:172117$10372
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \pop_4_7
- connect \Y $extend$libresoc.v:174364$10464_Y
+ connect \Y $extend$libresoc.v:172117$10372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174366$10467
+ cell $pos $extend$libresoc.v:172119$10375
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 32
connect \A \pop_6_0
- connect \Y $extend$libresoc.v:174366$10467_Y
+ connect \Y $extend$libresoc.v:172119$10375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174367$10469
+ cell $pos $extend$libresoc.v:172120$10377
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 32
connect \A \pop_6_1
- connect \Y $extend$libresoc.v:174367$10469_Y
+ connect \Y $extend$libresoc.v:172120$10377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $extend$libresoc.v:174368$10471
+ cell $pos $extend$libresoc.v:172121$10379
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 64
connect \A \pop_7_0
- connect \Y $extend$libresoc.v:174368$10471_Y
+ connect \Y $extend$libresoc.v:172121$10379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174357$10451
+ cell $pos $pos$libresoc.v:172110$10359
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174357$10450_Y
- connect \Y $pos$libresoc.v:174357$10451_Y
+ connect \A $extend$libresoc.v:172110$10358_Y
+ connect \Y $pos$libresoc.v:172110$10359_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174358$10453
+ cell $pos $pos$libresoc.v:172111$10361
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174358$10452_Y
- connect \Y $pos$libresoc.v:174358$10453_Y
+ connect \A $extend$libresoc.v:172111$10360_Y
+ connect \Y $pos$libresoc.v:172111$10361_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174359$10455
+ cell $pos $pos$libresoc.v:172112$10363
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174359$10454_Y
- connect \Y $pos$libresoc.v:174359$10455_Y
+ connect \A $extend$libresoc.v:172112$10362_Y
+ connect \Y $pos$libresoc.v:172112$10363_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174360$10457
+ cell $pos $pos$libresoc.v:172113$10365
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174360$10456_Y
- connect \Y $pos$libresoc.v:174360$10457_Y
+ connect \A $extend$libresoc.v:172113$10364_Y
+ connect \Y $pos$libresoc.v:172113$10365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174361$10459
+ cell $pos $pos$libresoc.v:172114$10367
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174361$10458_Y
- connect \Y $pos$libresoc.v:174361$10459_Y
+ connect \A $extend$libresoc.v:172114$10366_Y
+ connect \Y $pos$libresoc.v:172114$10367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174362$10461
+ cell $pos $pos$libresoc.v:172115$10369
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174362$10460_Y
- connect \Y $pos$libresoc.v:174362$10461_Y
+ connect \A $extend$libresoc.v:172115$10368_Y
+ connect \Y $pos$libresoc.v:172115$10369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174363$10463
+ cell $pos $pos$libresoc.v:172116$10371
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174363$10462_Y
- connect \Y $pos$libresoc.v:174363$10463_Y
+ connect \A $extend$libresoc.v:172116$10370_Y
+ connect \Y $pos$libresoc.v:172116$10371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174364$10465
+ cell $pos $pos$libresoc.v:172117$10373
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:174364$10464_Y
- connect \Y $pos$libresoc.v:174364$10465_Y
+ connect \A $extend$libresoc.v:172117$10372_Y
+ connect \Y $pos$libresoc.v:172117$10373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174366$10468
+ cell $pos $pos$libresoc.v:172119$10376
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $extend$libresoc.v:174366$10467_Y
- connect \Y $pos$libresoc.v:174366$10468_Y
+ connect \A $extend$libresoc.v:172119$10375_Y
+ connect \Y $pos$libresoc.v:172119$10376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174367$10470
+ cell $pos $pos$libresoc.v:172120$10378
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $extend$libresoc.v:174367$10469_Y
- connect \Y $pos$libresoc.v:174367$10470_Y
+ connect \A $extend$libresoc.v:172120$10377_Y
+ connect \Y $pos$libresoc.v:172120$10378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
- cell $pos $pos$libresoc.v:174368$10472
+ cell $pos $pos$libresoc.v:172121$10380
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:174368$10471_Y
- connect \Y $pos$libresoc.v:174368$10472_Y
+ connect \A $extend$libresoc.v:172121$10379_Y
+ connect \Y $pos$libresoc.v:172121$10380_Y
end
- attribute \src "libresoc.v:173910.7-173910.20"
- process $proc$libresoc.v:173910$10503
+ attribute \src "libresoc.v:171663.7-171663.20"
+ process $proc$libresoc.v:171663$10411
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:174398.3-174424.6"
- process $proc$libresoc.v:174398$10502
+ attribute \src "libresoc.v:172151.3-172177.6"
+ process $proc$libresoc.v:172151$10410
assign { } { }
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:174399.5-174399.29"
+ attribute \src "libresoc.v:172152.5-172152.29"
switch \initial
- attribute \src "libresoc.v:174399.9-174399.17"
+ attribute \src "libresoc.v:172152.9-172152.17"
case 1'1
case
end
sync always
update \o $0\o[63:0]
end
- connect \$101 $add$libresoc.v:174322$10415_Y
- connect \$104 $add$libresoc.v:174323$10416_Y
- connect \$107 $add$libresoc.v:174324$10417_Y
- connect \$110 $add$libresoc.v:174325$10418_Y
- connect \$113 $add$libresoc.v:174326$10419_Y
- connect \$116 $add$libresoc.v:174327$10420_Y
- connect \$11 $add$libresoc.v:174328$10421_Y
- connect \$119 $add$libresoc.v:174329$10422_Y
- connect \$122 $add$libresoc.v:174330$10423_Y
- connect \$125 $add$libresoc.v:174331$10424_Y
- connect \$128 $add$libresoc.v:174332$10425_Y
- connect \$131 $add$libresoc.v:174333$10426_Y
- connect \$134 $add$libresoc.v:174334$10427_Y
- connect \$137 $add$libresoc.v:174335$10428_Y
- connect \$140 $add$libresoc.v:174336$10429_Y
- connect \$143 $add$libresoc.v:174337$10430_Y
- connect \$146 $add$libresoc.v:174338$10431_Y
- connect \$14 $add$libresoc.v:174339$10432_Y
- connect \$149 $add$libresoc.v:174340$10433_Y
- connect \$152 $add$libresoc.v:174341$10434_Y
- connect \$155 $add$libresoc.v:174342$10435_Y
- connect \$158 $add$libresoc.v:174343$10436_Y
- connect \$161 $add$libresoc.v:174344$10437_Y
- connect \$164 $add$libresoc.v:174345$10438_Y
- connect \$167 $add$libresoc.v:174346$10439_Y
- connect \$170 $add$libresoc.v:174347$10440_Y
- connect \$173 $add$libresoc.v:174348$10441_Y
- connect \$176 $add$libresoc.v:174349$10442_Y
- connect \$17 $add$libresoc.v:174350$10443_Y
- connect \$179 $add$libresoc.v:174351$10444_Y
- connect \$182 $add$libresoc.v:174352$10445_Y
- connect \$185 $add$libresoc.v:174353$10446_Y
- connect \$188 $add$libresoc.v:174354$10447_Y
- connect \$190 $eq$libresoc.v:174355$10448_Y
- connect \$192 $eq$libresoc.v:174356$10449_Y
- connect \$194 $pos$libresoc.v:174357$10451_Y
- connect \$196 $pos$libresoc.v:174358$10453_Y
- connect \$198 $pos$libresoc.v:174359$10455_Y
- connect \$200 $pos$libresoc.v:174360$10457_Y
- connect \$202 $pos$libresoc.v:174361$10459_Y
- connect \$204 $pos$libresoc.v:174362$10461_Y
- connect \$206 $pos$libresoc.v:174363$10463_Y
- connect \$208 $pos$libresoc.v:174364$10465_Y
- connect \$20 $add$libresoc.v:174365$10466_Y
- connect \$210 $pos$libresoc.v:174366$10468_Y
- connect \$212 $pos$libresoc.v:174367$10470_Y
- connect \$214 $pos$libresoc.v:174368$10472_Y
- connect \$23 $add$libresoc.v:174369$10473_Y
- connect \$26 $add$libresoc.v:174370$10474_Y
- connect \$2 $add$libresoc.v:174371$10475_Y
- connect \$29 $add$libresoc.v:174372$10476_Y
- connect \$32 $add$libresoc.v:174373$10477_Y
- connect \$35 $add$libresoc.v:174374$10478_Y
- connect \$38 $add$libresoc.v:174375$10479_Y
- connect \$41 $add$libresoc.v:174376$10480_Y
- connect \$44 $add$libresoc.v:174377$10481_Y
- connect \$47 $add$libresoc.v:174378$10482_Y
- connect \$50 $add$libresoc.v:174379$10483_Y
- connect \$53 $add$libresoc.v:174380$10484_Y
- connect \$56 $add$libresoc.v:174381$10485_Y
- connect \$5 $add$libresoc.v:174382$10486_Y
- connect \$59 $add$libresoc.v:174383$10487_Y
- connect \$62 $add$libresoc.v:174384$10488_Y
- connect \$65 $add$libresoc.v:174385$10489_Y
- connect \$68 $add$libresoc.v:174386$10490_Y
- connect \$71 $add$libresoc.v:174387$10491_Y
- connect \$74 $add$libresoc.v:174388$10492_Y
- connect \$77 $add$libresoc.v:174389$10493_Y
- connect \$80 $add$libresoc.v:174390$10494_Y
- connect \$83 $add$libresoc.v:174391$10495_Y
- connect \$86 $add$libresoc.v:174392$10496_Y
- connect \$8 $add$libresoc.v:174393$10497_Y
- connect \$89 $add$libresoc.v:174394$10498_Y
- connect \$92 $add$libresoc.v:174395$10499_Y
- connect \$95 $add$libresoc.v:174396$10500_Y
- connect \$98 $add$libresoc.v:174397$10501_Y
+ connect \$101 $add$libresoc.v:172075$10323_Y
+ connect \$104 $add$libresoc.v:172076$10324_Y
+ connect \$107 $add$libresoc.v:172077$10325_Y
+ connect \$110 $add$libresoc.v:172078$10326_Y
+ connect \$113 $add$libresoc.v:172079$10327_Y
+ connect \$116 $add$libresoc.v:172080$10328_Y
+ connect \$11 $add$libresoc.v:172081$10329_Y
+ connect \$119 $add$libresoc.v:172082$10330_Y
+ connect \$122 $add$libresoc.v:172083$10331_Y
+ connect \$125 $add$libresoc.v:172084$10332_Y
+ connect \$128 $add$libresoc.v:172085$10333_Y
+ connect \$131 $add$libresoc.v:172086$10334_Y
+ connect \$134 $add$libresoc.v:172087$10335_Y
+ connect \$137 $add$libresoc.v:172088$10336_Y
+ connect \$140 $add$libresoc.v:172089$10337_Y
+ connect \$143 $add$libresoc.v:172090$10338_Y
+ connect \$146 $add$libresoc.v:172091$10339_Y
+ connect \$14 $add$libresoc.v:172092$10340_Y
+ connect \$149 $add$libresoc.v:172093$10341_Y
+ connect \$152 $add$libresoc.v:172094$10342_Y
+ connect \$155 $add$libresoc.v:172095$10343_Y
+ connect \$158 $add$libresoc.v:172096$10344_Y
+ connect \$161 $add$libresoc.v:172097$10345_Y
+ connect \$164 $add$libresoc.v:172098$10346_Y
+ connect \$167 $add$libresoc.v:172099$10347_Y
+ connect \$170 $add$libresoc.v:172100$10348_Y
+ connect \$173 $add$libresoc.v:172101$10349_Y
+ connect \$176 $add$libresoc.v:172102$10350_Y
+ connect \$17 $add$libresoc.v:172103$10351_Y
+ connect \$179 $add$libresoc.v:172104$10352_Y
+ connect \$182 $add$libresoc.v:172105$10353_Y
+ connect \$185 $add$libresoc.v:172106$10354_Y
+ connect \$188 $add$libresoc.v:172107$10355_Y
+ connect \$190 $eq$libresoc.v:172108$10356_Y
+ connect \$192 $eq$libresoc.v:172109$10357_Y
+ connect \$194 $pos$libresoc.v:172110$10359_Y
+ connect \$196 $pos$libresoc.v:172111$10361_Y
+ connect \$198 $pos$libresoc.v:172112$10363_Y
+ connect \$200 $pos$libresoc.v:172113$10365_Y
+ connect \$202 $pos$libresoc.v:172114$10367_Y
+ connect \$204 $pos$libresoc.v:172115$10369_Y
+ connect \$206 $pos$libresoc.v:172116$10371_Y
+ connect \$208 $pos$libresoc.v:172117$10373_Y
+ connect \$20 $add$libresoc.v:172118$10374_Y
+ connect \$210 $pos$libresoc.v:172119$10376_Y
+ connect \$212 $pos$libresoc.v:172120$10378_Y
+ connect \$214 $pos$libresoc.v:172121$10380_Y
+ connect \$23 $add$libresoc.v:172122$10381_Y
+ connect \$26 $add$libresoc.v:172123$10382_Y
+ connect \$2 $add$libresoc.v:172124$10383_Y
+ connect \$29 $add$libresoc.v:172125$10384_Y
+ connect \$32 $add$libresoc.v:172126$10385_Y
+ connect \$35 $add$libresoc.v:172127$10386_Y
+ connect \$38 $add$libresoc.v:172128$10387_Y
+ connect \$41 $add$libresoc.v:172129$10388_Y
+ connect \$44 $add$libresoc.v:172130$10389_Y
+ connect \$47 $add$libresoc.v:172131$10390_Y
+ connect \$50 $add$libresoc.v:172132$10391_Y
+ connect \$53 $add$libresoc.v:172133$10392_Y
+ connect \$56 $add$libresoc.v:172134$10393_Y
+ connect \$5 $add$libresoc.v:172135$10394_Y
+ connect \$59 $add$libresoc.v:172136$10395_Y
+ connect \$62 $add$libresoc.v:172137$10396_Y
+ connect \$65 $add$libresoc.v:172138$10397_Y
+ connect \$68 $add$libresoc.v:172139$10398_Y
+ connect \$71 $add$libresoc.v:172140$10399_Y
+ connect \$74 $add$libresoc.v:172141$10400_Y
+ connect \$77 $add$libresoc.v:172142$10401_Y
+ connect \$80 $add$libresoc.v:172143$10402_Y
+ connect \$83 $add$libresoc.v:172144$10403_Y
+ connect \$86 $add$libresoc.v:172145$10404_Y
+ connect \$8 $add$libresoc.v:172146$10405_Y
+ connect \$89 $add$libresoc.v:172147$10406_Y
+ connect \$92 $add$libresoc.v:172148$10407_Y
+ connect \$95 $add$libresoc.v:172149$10408_Y
+ connect \$98 $add$libresoc.v:172150$10409_Y
connect \$1 \$2
connect \$4 \$5
connect \$7 \$8
connect \pop_2_1 \$5 [1:0]
connect \pop_2_0 \$2 [1:0]
end
-attribute \src "libresoc.v:174555.1-174639.10"
+attribute \src "libresoc.v:172308.1-172392.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick"
attribute \generator "nMigen"
module \ppick
- attribute \src "libresoc.v:174612.17-174612.91"
- wire $not$libresoc.v:174612$10504_Y
- attribute \src "libresoc.v:174614.18-174614.93"
- wire $not$libresoc.v:174614$10506_Y
- attribute \src "libresoc.v:174616.18-174616.93"
- wire $not$libresoc.v:174616$10508_Y
- attribute \src "libresoc.v:174617.17-174617.138"
- wire width 8 $not$libresoc.v:174617$10509_Y
- attribute \src "libresoc.v:174619.18-174619.93"
- wire $not$libresoc.v:174619$10511_Y
- attribute \src "libresoc.v:174621.18-174621.93"
- wire $not$libresoc.v:174621$10513_Y
- attribute \src "libresoc.v:174623.18-174623.93"
- wire $not$libresoc.v:174623$10515_Y
- attribute \src "libresoc.v:174626.17-174626.91"
- wire $not$libresoc.v:174626$10518_Y
- attribute \src "libresoc.v:174613.18-174613.116"
- wire $reduce_or$libresoc.v:174613$10505_Y
- attribute \src "libresoc.v:174615.18-174615.122"
- wire $reduce_or$libresoc.v:174615$10507_Y
- attribute \src "libresoc.v:174618.18-174618.128"
- wire $reduce_or$libresoc.v:174618$10510_Y
- attribute \src "libresoc.v:174620.18-174620.134"
- wire $reduce_or$libresoc.v:174620$10512_Y
- attribute \src "libresoc.v:174622.18-174622.140"
- wire $reduce_or$libresoc.v:174622$10514_Y
- attribute \src "libresoc.v:174624.18-174624.90"
- wire $reduce_or$libresoc.v:174624$10516_Y
- attribute \src "libresoc.v:174625.17-174625.103"
- wire $reduce_or$libresoc.v:174625$10517_Y
- attribute \src "libresoc.v:174627.17-174627.109"
- wire $reduce_or$libresoc.v:174627$10519_Y
+ attribute \src "libresoc.v:172365.17-172365.91"
+ wire $not$libresoc.v:172365$10412_Y
+ attribute \src "libresoc.v:172367.18-172367.93"
+ wire $not$libresoc.v:172367$10414_Y
+ attribute \src "libresoc.v:172369.18-172369.93"
+ wire $not$libresoc.v:172369$10416_Y
+ attribute \src "libresoc.v:172370.17-172370.138"
+ wire width 8 $not$libresoc.v:172370$10417_Y
+ attribute \src "libresoc.v:172372.18-172372.93"
+ wire $not$libresoc.v:172372$10419_Y
+ attribute \src "libresoc.v:172374.18-172374.93"
+ wire $not$libresoc.v:172374$10421_Y
+ attribute \src "libresoc.v:172376.18-172376.93"
+ wire $not$libresoc.v:172376$10423_Y
+ attribute \src "libresoc.v:172379.17-172379.91"
+ wire $not$libresoc.v:172379$10426_Y
+ attribute \src "libresoc.v:172366.18-172366.116"
+ wire $reduce_or$libresoc.v:172366$10413_Y
+ attribute \src "libresoc.v:172368.18-172368.122"
+ wire $reduce_or$libresoc.v:172368$10415_Y
+ attribute \src "libresoc.v:172371.18-172371.128"
+ wire $reduce_or$libresoc.v:172371$10418_Y
+ attribute \src "libresoc.v:172373.18-172373.134"
+ wire $reduce_or$libresoc.v:172373$10420_Y
+ attribute \src "libresoc.v:172375.18-172375.140"
+ wire $reduce_or$libresoc.v:172375$10422_Y
+ attribute \src "libresoc.v:172377.18-172377.90"
+ wire $reduce_or$libresoc.v:172377$10424_Y
+ attribute \src "libresoc.v:172378.17-172378.103"
+ wire $reduce_or$libresoc.v:172378$10425_Y
+ attribute \src "libresoc.v:172380.17-172380.109"
+ wire $reduce_or$libresoc.v:172380$10427_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174612$10504
+ cell $not $not$libresoc.v:172365$10412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:174612$10504_Y
+ connect \Y $not$libresoc.v:172365$10412_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174614$10506
+ cell $not $not$libresoc.v:172367$10414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:174614$10506_Y
+ connect \Y $not$libresoc.v:172367$10414_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174616$10508
+ cell $not $not$libresoc.v:172369$10416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:174616$10508_Y
+ connect \Y $not$libresoc.v:172369$10416_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174617$10509
+ cell $not $not$libresoc.v:172370$10417
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:174617$10509_Y
+ connect \Y $not$libresoc.v:172370$10417_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174619$10511
+ cell $not $not$libresoc.v:172372$10419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:174619$10511_Y
+ connect \Y $not$libresoc.v:172372$10419_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174621$10513
+ cell $not $not$libresoc.v:172374$10421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:174621$10513_Y
+ connect \Y $not$libresoc.v:172374$10421_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174623$10515
+ cell $not $not$libresoc.v:172376$10423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:174623$10515_Y
+ connect \Y $not$libresoc.v:172376$10423_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174626$10518
+ cell $not $not$libresoc.v:172379$10426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174626$10518_Y
+ connect \Y $not$libresoc.v:172379$10426_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174613$10505
+ cell $reduce_or $reduce_or$libresoc.v:172366$10413
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:174613$10505_Y
+ connect \Y $reduce_or$libresoc.v:172366$10413_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174615$10507
+ cell $reduce_or $reduce_or$libresoc.v:172368$10415
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:174615$10507_Y
+ connect \Y $reduce_or$libresoc.v:172368$10415_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174618$10510
+ cell $reduce_or $reduce_or$libresoc.v:172371$10418
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:174618$10510_Y
+ connect \Y $reduce_or$libresoc.v:172371$10418_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174620$10512
+ cell $reduce_or $reduce_or$libresoc.v:172373$10420
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:174620$10512_Y
+ connect \Y $reduce_or$libresoc.v:172373$10420_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174622$10514
+ cell $reduce_or $reduce_or$libresoc.v:172375$10422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:174622$10514_Y
+ connect \Y $reduce_or$libresoc.v:172375$10422_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174624$10516
+ cell $reduce_or $reduce_or$libresoc.v:172377$10424
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174624$10516_Y
+ connect \Y $reduce_or$libresoc.v:172377$10424_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174625$10517
+ cell $reduce_or $reduce_or$libresoc.v:172378$10425
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174625$10517_Y
+ connect \Y $reduce_or$libresoc.v:172378$10425_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174627$10519
+ cell $reduce_or $reduce_or$libresoc.v:172380$10427
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:174627$10519_Y
- end
- connect \$7 $not$libresoc.v:174612$10504_Y
- connect \$12 $reduce_or$libresoc.v:174613$10505_Y
- connect \$11 $not$libresoc.v:174614$10506_Y
- connect \$16 $reduce_or$libresoc.v:174615$10507_Y
- connect \$15 $not$libresoc.v:174616$10508_Y
- connect \$1 $not$libresoc.v:174617$10509_Y
- connect \$20 $reduce_or$libresoc.v:174618$10510_Y
- connect \$19 $not$libresoc.v:174619$10511_Y
- connect \$24 $reduce_or$libresoc.v:174620$10512_Y
- connect \$23 $not$libresoc.v:174621$10513_Y
- connect \$28 $reduce_or$libresoc.v:174622$10514_Y
- connect \$27 $not$libresoc.v:174623$10515_Y
- connect \$31 $reduce_or$libresoc.v:174624$10516_Y
- connect \$4 $reduce_or$libresoc.v:174625$10517_Y
- connect \$3 $not$libresoc.v:174626$10518_Y
- connect \$8 $reduce_or$libresoc.v:174627$10519_Y
+ connect \Y $reduce_or$libresoc.v:172380$10427_Y
+ end
+ connect \$7 $not$libresoc.v:172365$10412_Y
+ connect \$12 $reduce_or$libresoc.v:172366$10413_Y
+ connect \$11 $not$libresoc.v:172367$10414_Y
+ connect \$16 $reduce_or$libresoc.v:172368$10415_Y
+ connect \$15 $not$libresoc.v:172369$10416_Y
+ connect \$1 $not$libresoc.v:172370$10417_Y
+ connect \$20 $reduce_or$libresoc.v:172371$10418_Y
+ connect \$19 $not$libresoc.v:172372$10419_Y
+ connect \$24 $reduce_or$libresoc.v:172373$10420_Y
+ connect \$23 $not$libresoc.v:172374$10421_Y
+ connect \$28 $reduce_or$libresoc.v:172375$10422_Y
+ connect \$27 $not$libresoc.v:172376$10423_Y
+ connect \$31 $reduce_or$libresoc.v:172377$10424_Y
+ connect \$4 $reduce_or$libresoc.v:172378$10425_Y
+ connect \$3 $not$libresoc.v:172379$10426_Y
+ connect \$8 $reduce_or$libresoc.v:172380$10427_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:174643.1-174727.10"
+attribute \src "libresoc.v:172396.1-172480.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick"
attribute \generator "nMigen"
module \ppick$175
- attribute \src "libresoc.v:174700.17-174700.91"
- wire $not$libresoc.v:174700$10520_Y
- attribute \src "libresoc.v:174702.18-174702.93"
- wire $not$libresoc.v:174702$10522_Y
- attribute \src "libresoc.v:174704.18-174704.93"
- wire $not$libresoc.v:174704$10524_Y
- attribute \src "libresoc.v:174705.17-174705.138"
- wire width 8 $not$libresoc.v:174705$10525_Y
- attribute \src "libresoc.v:174707.18-174707.93"
- wire $not$libresoc.v:174707$10527_Y
- attribute \src "libresoc.v:174709.18-174709.93"
- wire $not$libresoc.v:174709$10529_Y
- attribute \src "libresoc.v:174711.18-174711.93"
- wire $not$libresoc.v:174711$10531_Y
- attribute \src "libresoc.v:174714.17-174714.91"
- wire $not$libresoc.v:174714$10534_Y
- attribute \src "libresoc.v:174701.18-174701.116"
- wire $reduce_or$libresoc.v:174701$10521_Y
- attribute \src "libresoc.v:174703.18-174703.122"
- wire $reduce_or$libresoc.v:174703$10523_Y
- attribute \src "libresoc.v:174706.18-174706.128"
- wire $reduce_or$libresoc.v:174706$10526_Y
- attribute \src "libresoc.v:174708.18-174708.134"
- wire $reduce_or$libresoc.v:174708$10528_Y
- attribute \src "libresoc.v:174710.18-174710.140"
- wire $reduce_or$libresoc.v:174710$10530_Y
- attribute \src "libresoc.v:174712.18-174712.90"
- wire $reduce_or$libresoc.v:174712$10532_Y
- attribute \src "libresoc.v:174713.17-174713.103"
- wire $reduce_or$libresoc.v:174713$10533_Y
- attribute \src "libresoc.v:174715.17-174715.109"
- wire $reduce_or$libresoc.v:174715$10535_Y
+ attribute \src "libresoc.v:172453.17-172453.91"
+ wire $not$libresoc.v:172453$10428_Y
+ attribute \src "libresoc.v:172455.18-172455.93"
+ wire $not$libresoc.v:172455$10430_Y
+ attribute \src "libresoc.v:172457.18-172457.93"
+ wire $not$libresoc.v:172457$10432_Y
+ attribute \src "libresoc.v:172458.17-172458.138"
+ wire width 8 $not$libresoc.v:172458$10433_Y
+ attribute \src "libresoc.v:172460.18-172460.93"
+ wire $not$libresoc.v:172460$10435_Y
+ attribute \src "libresoc.v:172462.18-172462.93"
+ wire $not$libresoc.v:172462$10437_Y
+ attribute \src "libresoc.v:172464.18-172464.93"
+ wire $not$libresoc.v:172464$10439_Y
+ attribute \src "libresoc.v:172467.17-172467.91"
+ wire $not$libresoc.v:172467$10442_Y
+ attribute \src "libresoc.v:172454.18-172454.116"
+ wire $reduce_or$libresoc.v:172454$10429_Y
+ attribute \src "libresoc.v:172456.18-172456.122"
+ wire $reduce_or$libresoc.v:172456$10431_Y
+ attribute \src "libresoc.v:172459.18-172459.128"
+ wire $reduce_or$libresoc.v:172459$10434_Y
+ attribute \src "libresoc.v:172461.18-172461.134"
+ wire $reduce_or$libresoc.v:172461$10436_Y
+ attribute \src "libresoc.v:172463.18-172463.140"
+ wire $reduce_or$libresoc.v:172463$10438_Y
+ attribute \src "libresoc.v:172465.18-172465.90"
+ wire $reduce_or$libresoc.v:172465$10440_Y
+ attribute \src "libresoc.v:172466.17-172466.103"
+ wire $reduce_or$libresoc.v:172466$10441_Y
+ attribute \src "libresoc.v:172468.17-172468.109"
+ wire $reduce_or$libresoc.v:172468$10443_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174700$10520
+ cell $not $not$libresoc.v:172453$10428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:174700$10520_Y
+ connect \Y $not$libresoc.v:172453$10428_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174702$10522
+ cell $not $not$libresoc.v:172455$10430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:174702$10522_Y
+ connect \Y $not$libresoc.v:172455$10430_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174704$10524
+ cell $not $not$libresoc.v:172457$10432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:174704$10524_Y
+ connect \Y $not$libresoc.v:172457$10432_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174705$10525
+ cell $not $not$libresoc.v:172458$10433
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:174705$10525_Y
+ connect \Y $not$libresoc.v:172458$10433_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174707$10527
+ cell $not $not$libresoc.v:172460$10435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:174707$10527_Y
+ connect \Y $not$libresoc.v:172460$10435_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174709$10529
+ cell $not $not$libresoc.v:172462$10437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:174709$10529_Y
+ connect \Y $not$libresoc.v:172462$10437_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174711$10531
+ cell $not $not$libresoc.v:172464$10439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:174711$10531_Y
+ connect \Y $not$libresoc.v:172464$10439_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174714$10534
+ cell $not $not$libresoc.v:172467$10442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174714$10534_Y
+ connect \Y $not$libresoc.v:172467$10442_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174701$10521
+ cell $reduce_or $reduce_or$libresoc.v:172454$10429
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:174701$10521_Y
+ connect \Y $reduce_or$libresoc.v:172454$10429_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174703$10523
+ cell $reduce_or $reduce_or$libresoc.v:172456$10431
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:174703$10523_Y
+ connect \Y $reduce_or$libresoc.v:172456$10431_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174706$10526
+ cell $reduce_or $reduce_or$libresoc.v:172459$10434
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:174706$10526_Y
+ connect \Y $reduce_or$libresoc.v:172459$10434_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174708$10528
+ cell $reduce_or $reduce_or$libresoc.v:172461$10436
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:174708$10528_Y
+ connect \Y $reduce_or$libresoc.v:172461$10436_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174710$10530
+ cell $reduce_or $reduce_or$libresoc.v:172463$10438
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:174710$10530_Y
+ connect \Y $reduce_or$libresoc.v:172463$10438_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174712$10532
+ cell $reduce_or $reduce_or$libresoc.v:172465$10440
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174712$10532_Y
+ connect \Y $reduce_or$libresoc.v:172465$10440_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174713$10533
+ cell $reduce_or $reduce_or$libresoc.v:172466$10441
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174713$10533_Y
+ connect \Y $reduce_or$libresoc.v:172466$10441_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174715$10535
+ cell $reduce_or $reduce_or$libresoc.v:172468$10443
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:174715$10535_Y
- end
- connect \$7 $not$libresoc.v:174700$10520_Y
- connect \$12 $reduce_or$libresoc.v:174701$10521_Y
- connect \$11 $not$libresoc.v:174702$10522_Y
- connect \$16 $reduce_or$libresoc.v:174703$10523_Y
- connect \$15 $not$libresoc.v:174704$10524_Y
- connect \$1 $not$libresoc.v:174705$10525_Y
- connect \$20 $reduce_or$libresoc.v:174706$10526_Y
- connect \$19 $not$libresoc.v:174707$10527_Y
- connect \$24 $reduce_or$libresoc.v:174708$10528_Y
- connect \$23 $not$libresoc.v:174709$10529_Y
- connect \$28 $reduce_or$libresoc.v:174710$10530_Y
- connect \$27 $not$libresoc.v:174711$10531_Y
- connect \$31 $reduce_or$libresoc.v:174712$10532_Y
- connect \$4 $reduce_or$libresoc.v:174713$10533_Y
- connect \$3 $not$libresoc.v:174714$10534_Y
- connect \$8 $reduce_or$libresoc.v:174715$10535_Y
+ connect \Y $reduce_or$libresoc.v:172468$10443_Y
+ end
+ connect \$7 $not$libresoc.v:172453$10428_Y
+ connect \$12 $reduce_or$libresoc.v:172454$10429_Y
+ connect \$11 $not$libresoc.v:172455$10430_Y
+ connect \$16 $reduce_or$libresoc.v:172456$10431_Y
+ connect \$15 $not$libresoc.v:172457$10432_Y
+ connect \$1 $not$libresoc.v:172458$10433_Y
+ connect \$20 $reduce_or$libresoc.v:172459$10434_Y
+ connect \$19 $not$libresoc.v:172460$10435_Y
+ connect \$24 $reduce_or$libresoc.v:172461$10436_Y
+ connect \$23 $not$libresoc.v:172462$10437_Y
+ connect \$28 $reduce_or$libresoc.v:172463$10438_Y
+ connect \$27 $not$libresoc.v:172464$10439_Y
+ connect \$31 $reduce_or$libresoc.v:172465$10440_Y
+ connect \$4 $reduce_or$libresoc.v:172466$10441_Y
+ connect \$3 $not$libresoc.v:172467$10442_Y
+ connect \$8 $reduce_or$libresoc.v:172468$10443_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:174731.1-174761.10"
+attribute \src "libresoc.v:172484.1-172514.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a"
attribute \generator "nMigen"
module \rdpick_CR_cr_a
- attribute \src "libresoc.v:174752.17-174752.89"
- wire width 2 $not$libresoc.v:174752$10536_Y
- attribute \src "libresoc.v:174754.17-174754.91"
- wire $not$libresoc.v:174754$10538_Y
- attribute \src "libresoc.v:174753.17-174753.103"
- wire $reduce_or$libresoc.v:174753$10537_Y
- attribute \src "libresoc.v:174755.17-174755.89"
- wire $reduce_or$libresoc.v:174755$10539_Y
+ attribute \src "libresoc.v:172505.17-172505.89"
+ wire width 2 $not$libresoc.v:172505$10444_Y
+ attribute \src "libresoc.v:172507.17-172507.91"
+ wire $not$libresoc.v:172507$10446_Y
+ attribute \src "libresoc.v:172506.17-172506.103"
+ wire $reduce_or$libresoc.v:172506$10445_Y
+ attribute \src "libresoc.v:172508.17-172508.89"
+ wire $reduce_or$libresoc.v:172508$10447_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174752$10536
+ cell $not $not$libresoc.v:172505$10444
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:174752$10536_Y
+ connect \Y $not$libresoc.v:172505$10444_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174754$10538
+ cell $not $not$libresoc.v:172507$10446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174754$10538_Y
+ connect \Y $not$libresoc.v:172507$10446_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174753$10537
+ cell $reduce_or $reduce_or$libresoc.v:172506$10445
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174753$10537_Y
+ connect \Y $reduce_or$libresoc.v:172506$10445_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174755$10539
+ cell $reduce_or $reduce_or$libresoc.v:172508$10447
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174755$10539_Y
+ connect \Y $reduce_or$libresoc.v:172508$10447_Y
end
- connect \$1 $not$libresoc.v:174752$10536_Y
- connect \$4 $reduce_or$libresoc.v:174753$10537_Y
- connect \$3 $not$libresoc.v:174754$10538_Y
- connect \$7 $reduce_or$libresoc.v:174755$10539_Y
+ connect \$1 $not$libresoc.v:172505$10444_Y
+ connect \$4 $reduce_or$libresoc.v:172506$10445_Y
+ connect \$3 $not$libresoc.v:172507$10446_Y
+ connect \$7 $reduce_or$libresoc.v:172508$10447_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:174765.1-174786.10"
+attribute \src "libresoc.v:172518.1-172539.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b"
attribute \generator "nMigen"
module \rdpick_CR_cr_b
- attribute \src "libresoc.v:174780.17-174780.89"
- wire $not$libresoc.v:174780$10540_Y
- attribute \src "libresoc.v:174781.17-174781.89"
- wire $reduce_or$libresoc.v:174781$10541_Y
+ attribute \src "libresoc.v:172533.17-172533.89"
+ wire $not$libresoc.v:172533$10448_Y
+ attribute \src "libresoc.v:172534.17-172534.89"
+ wire $reduce_or$libresoc.v:172534$10449_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174780$10540
+ cell $not $not$libresoc.v:172533$10448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:174780$10540_Y
+ connect \Y $not$libresoc.v:172533$10448_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174781$10541
+ cell $reduce_or $reduce_or$libresoc.v:172534$10449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174781$10541_Y
+ connect \Y $reduce_or$libresoc.v:172534$10449_Y
end
- connect \$1 $not$libresoc.v:174780$10540_Y
- connect \$3 $reduce_or$libresoc.v:174781$10541_Y
+ connect \$1 $not$libresoc.v:172533$10448_Y
+ connect \$3 $reduce_or$libresoc.v:172534$10449_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:174790.1-174811.10"
+attribute \src "libresoc.v:172543.1-172564.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c"
attribute \generator "nMigen"
module \rdpick_CR_cr_c
- attribute \src "libresoc.v:174805.17-174805.89"
- wire $not$libresoc.v:174805$10542_Y
- attribute \src "libresoc.v:174806.17-174806.89"
- wire $reduce_or$libresoc.v:174806$10543_Y
+ attribute \src "libresoc.v:172558.17-172558.89"
+ wire $not$libresoc.v:172558$10450_Y
+ attribute \src "libresoc.v:172559.17-172559.89"
+ wire $reduce_or$libresoc.v:172559$10451_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174805$10542
+ cell $not $not$libresoc.v:172558$10450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:174805$10542_Y
+ connect \Y $not$libresoc.v:172558$10450_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174806$10543
+ cell $reduce_or $reduce_or$libresoc.v:172559$10451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174806$10543_Y
+ connect \Y $reduce_or$libresoc.v:172559$10451_Y
end
- connect \$1 $not$libresoc.v:174805$10542_Y
- connect \$3 $reduce_or$libresoc.v:174806$10543_Y
+ connect \$1 $not$libresoc.v:172558$10450_Y
+ connect \$3 $reduce_or$libresoc.v:172559$10451_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:174815.1-174836.10"
+attribute \src "libresoc.v:172568.1-172589.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr"
attribute \generator "nMigen"
module \rdpick_CR_full_cr
- attribute \src "libresoc.v:174830.17-174830.89"
- wire $not$libresoc.v:174830$10544_Y
- attribute \src "libresoc.v:174831.17-174831.89"
- wire $reduce_or$libresoc.v:174831$10545_Y
+ attribute \src "libresoc.v:172583.17-172583.89"
+ wire $not$libresoc.v:172583$10452_Y
+ attribute \src "libresoc.v:172584.17-172584.89"
+ wire $reduce_or$libresoc.v:172584$10453_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174830$10544
+ cell $not $not$libresoc.v:172583$10452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:174830$10544_Y
+ connect \Y $not$libresoc.v:172583$10452_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174831$10545
+ cell $reduce_or $reduce_or$libresoc.v:172584$10453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174831$10545_Y
+ connect \Y $reduce_or$libresoc.v:172584$10453_Y
end
- connect \$1 $not$libresoc.v:174830$10544_Y
- connect \$3 $reduce_or$libresoc.v:174831$10545_Y
+ connect \$1 $not$libresoc.v:172583$10452_Y
+ connect \$3 $reduce_or$libresoc.v:172584$10453_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:174840.1-174879.10"
+attribute \src "libresoc.v:172593.1-172632.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1"
attribute \generator "nMigen"
module \rdpick_FAST_fast1
- attribute \src "libresoc.v:174867.17-174867.91"
- wire $not$libresoc.v:174867$10546_Y
- attribute \src "libresoc.v:174869.17-174869.89"
- wire width 3 $not$libresoc.v:174869$10548_Y
- attribute \src "libresoc.v:174871.17-174871.91"
- wire $not$libresoc.v:174871$10550_Y
- attribute \src "libresoc.v:174868.18-174868.90"
- wire $reduce_or$libresoc.v:174868$10547_Y
- attribute \src "libresoc.v:174870.17-174870.103"
- wire $reduce_or$libresoc.v:174870$10549_Y
- attribute \src "libresoc.v:174872.17-174872.105"
- wire $reduce_or$libresoc.v:174872$10551_Y
+ attribute \src "libresoc.v:172620.17-172620.91"
+ wire $not$libresoc.v:172620$10454_Y
+ attribute \src "libresoc.v:172622.17-172622.89"
+ wire width 3 $not$libresoc.v:172622$10456_Y
+ attribute \src "libresoc.v:172624.17-172624.91"
+ wire $not$libresoc.v:172624$10458_Y
+ attribute \src "libresoc.v:172621.18-172621.90"
+ wire $reduce_or$libresoc.v:172621$10455_Y
+ attribute \src "libresoc.v:172623.17-172623.103"
+ wire $reduce_or$libresoc.v:172623$10457_Y
+ attribute \src "libresoc.v:172625.17-172625.105"
+ wire $reduce_or$libresoc.v:172625$10459_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174867$10546
+ cell $not $not$libresoc.v:172620$10454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:174867$10546_Y
+ connect \Y $not$libresoc.v:172620$10454_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174869$10548
+ cell $not $not$libresoc.v:172622$10456
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:174869$10548_Y
+ connect \Y $not$libresoc.v:172622$10456_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174871$10550
+ cell $not $not$libresoc.v:172624$10458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174871$10550_Y
+ connect \Y $not$libresoc.v:172624$10458_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174868$10547
+ cell $reduce_or $reduce_or$libresoc.v:172621$10455
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174868$10547_Y
+ connect \Y $reduce_or$libresoc.v:172621$10455_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174870$10549
+ cell $reduce_or $reduce_or$libresoc.v:172623$10457
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174870$10549_Y
+ connect \Y $reduce_or$libresoc.v:172623$10457_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174872$10551
+ cell $reduce_or $reduce_or$libresoc.v:172625$10459
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:174872$10551_Y
- end
- connect \$7 $not$libresoc.v:174867$10546_Y
- connect \$11 $reduce_or$libresoc.v:174868$10547_Y
- connect \$1 $not$libresoc.v:174869$10548_Y
- connect \$4 $reduce_or$libresoc.v:174870$10549_Y
- connect \$3 $not$libresoc.v:174871$10550_Y
- connect \$8 $reduce_or$libresoc.v:174872$10551_Y
+ connect \Y $reduce_or$libresoc.v:172625$10459_Y
+ end
+ connect \$7 $not$libresoc.v:172620$10454_Y
+ connect \$11 $reduce_or$libresoc.v:172621$10455_Y
+ connect \$1 $not$libresoc.v:172622$10456_Y
+ connect \$4 $reduce_or$libresoc.v:172623$10457_Y
+ connect \$3 $not$libresoc.v:172624$10458_Y
+ connect \$8 $reduce_or$libresoc.v:172625$10459_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:174883.1-174913.10"
+attribute \src "libresoc.v:172636.1-172666.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2"
attribute \generator "nMigen"
module \rdpick_FAST_fast2
- attribute \src "libresoc.v:174904.17-174904.89"
- wire width 2 $not$libresoc.v:174904$10552_Y
- attribute \src "libresoc.v:174906.17-174906.91"
- wire $not$libresoc.v:174906$10554_Y
- attribute \src "libresoc.v:174905.17-174905.103"
- wire $reduce_or$libresoc.v:174905$10553_Y
- attribute \src "libresoc.v:174907.17-174907.89"
- wire $reduce_or$libresoc.v:174907$10555_Y
+ attribute \src "libresoc.v:172657.17-172657.89"
+ wire width 2 $not$libresoc.v:172657$10460_Y
+ attribute \src "libresoc.v:172659.17-172659.91"
+ wire $not$libresoc.v:172659$10462_Y
+ attribute \src "libresoc.v:172658.17-172658.103"
+ wire $reduce_or$libresoc.v:172658$10461_Y
+ attribute \src "libresoc.v:172660.17-172660.89"
+ wire $reduce_or$libresoc.v:172660$10463_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174904$10552
+ cell $not $not$libresoc.v:172657$10460
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:174904$10552_Y
+ connect \Y $not$libresoc.v:172657$10460_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174906$10554
+ cell $not $not$libresoc.v:172659$10462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174906$10554_Y
+ connect \Y $not$libresoc.v:172659$10462_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174905$10553
+ cell $reduce_or $reduce_or$libresoc.v:172658$10461
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174905$10553_Y
+ connect \Y $reduce_or$libresoc.v:172658$10461_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174907$10555
+ cell $reduce_or $reduce_or$libresoc.v:172660$10463
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174907$10555_Y
+ connect \Y $reduce_or$libresoc.v:172660$10463_Y
end
- connect \$1 $not$libresoc.v:174904$10552_Y
- connect \$4 $reduce_or$libresoc.v:174905$10553_Y
- connect \$3 $not$libresoc.v:174906$10554_Y
- connect \$7 $reduce_or$libresoc.v:174907$10555_Y
+ connect \$1 $not$libresoc.v:172657$10460_Y
+ connect \$4 $reduce_or$libresoc.v:172658$10461_Y
+ connect \$3 $not$libresoc.v:172659$10462_Y
+ connect \$7 $reduce_or$libresoc.v:172660$10463_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:174917.1-175010.10"
+attribute \src "libresoc.v:172670.1-172763.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra"
attribute \generator "nMigen"
module \rdpick_INT_ra
- attribute \src "libresoc.v:174980.17-174980.91"
- wire $not$libresoc.v:174980$10556_Y
- attribute \src "libresoc.v:174982.18-174982.93"
- wire $not$libresoc.v:174982$10558_Y
- attribute \src "libresoc.v:174984.18-174984.93"
- wire $not$libresoc.v:174984$10560_Y
- attribute \src "libresoc.v:174985.17-174985.89"
- wire width 9 $not$libresoc.v:174985$10561_Y
- attribute \src "libresoc.v:174987.18-174987.93"
- wire $not$libresoc.v:174987$10563_Y
- attribute \src "libresoc.v:174989.18-174989.93"
- wire $not$libresoc.v:174989$10565_Y
- attribute \src "libresoc.v:174991.18-174991.93"
- wire $not$libresoc.v:174991$10567_Y
- attribute \src "libresoc.v:174993.18-174993.93"
- wire $not$libresoc.v:174993$10569_Y
- attribute \src "libresoc.v:174996.17-174996.91"
- wire $not$libresoc.v:174996$10572_Y
- attribute \src "libresoc.v:174981.18-174981.106"
- wire $reduce_or$libresoc.v:174981$10557_Y
- attribute \src "libresoc.v:174983.18-174983.106"
- wire $reduce_or$libresoc.v:174983$10559_Y
- attribute \src "libresoc.v:174986.18-174986.106"
- wire $reduce_or$libresoc.v:174986$10562_Y
- attribute \src "libresoc.v:174988.18-174988.106"
- wire $reduce_or$libresoc.v:174988$10564_Y
- attribute \src "libresoc.v:174990.18-174990.106"
- wire $reduce_or$libresoc.v:174990$10566_Y
- attribute \src "libresoc.v:174992.18-174992.106"
- wire $reduce_or$libresoc.v:174992$10568_Y
- attribute \src "libresoc.v:174994.18-174994.90"
- wire $reduce_or$libresoc.v:174994$10570_Y
- attribute \src "libresoc.v:174995.17-174995.103"
- wire $reduce_or$libresoc.v:174995$10571_Y
- attribute \src "libresoc.v:174997.17-174997.105"
- wire $reduce_or$libresoc.v:174997$10573_Y
+ attribute \src "libresoc.v:172733.17-172733.91"
+ wire $not$libresoc.v:172733$10464_Y
+ attribute \src "libresoc.v:172735.18-172735.93"
+ wire $not$libresoc.v:172735$10466_Y
+ attribute \src "libresoc.v:172737.18-172737.93"
+ wire $not$libresoc.v:172737$10468_Y
+ attribute \src "libresoc.v:172738.17-172738.89"
+ wire width 9 $not$libresoc.v:172738$10469_Y
+ attribute \src "libresoc.v:172740.18-172740.93"
+ wire $not$libresoc.v:172740$10471_Y
+ attribute \src "libresoc.v:172742.18-172742.93"
+ wire $not$libresoc.v:172742$10473_Y
+ attribute \src "libresoc.v:172744.18-172744.93"
+ wire $not$libresoc.v:172744$10475_Y
+ attribute \src "libresoc.v:172746.18-172746.93"
+ wire $not$libresoc.v:172746$10477_Y
+ attribute \src "libresoc.v:172749.17-172749.91"
+ wire $not$libresoc.v:172749$10480_Y
+ attribute \src "libresoc.v:172734.18-172734.106"
+ wire $reduce_or$libresoc.v:172734$10465_Y
+ attribute \src "libresoc.v:172736.18-172736.106"
+ wire $reduce_or$libresoc.v:172736$10467_Y
+ attribute \src "libresoc.v:172739.18-172739.106"
+ wire $reduce_or$libresoc.v:172739$10470_Y
+ attribute \src "libresoc.v:172741.18-172741.106"
+ wire $reduce_or$libresoc.v:172741$10472_Y
+ attribute \src "libresoc.v:172743.18-172743.106"
+ wire $reduce_or$libresoc.v:172743$10474_Y
+ attribute \src "libresoc.v:172745.18-172745.106"
+ wire $reduce_or$libresoc.v:172745$10476_Y
+ attribute \src "libresoc.v:172747.18-172747.90"
+ wire $reduce_or$libresoc.v:172747$10478_Y
+ attribute \src "libresoc.v:172748.17-172748.103"
+ wire $reduce_or$libresoc.v:172748$10479_Y
+ attribute \src "libresoc.v:172750.17-172750.105"
+ wire $reduce_or$libresoc.v:172750$10481_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 9 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t8
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174980$10556
+ cell $not $not$libresoc.v:172733$10464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:174980$10556_Y
+ connect \Y $not$libresoc.v:172733$10464_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174982$10558
+ cell $not $not$libresoc.v:172735$10466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:174982$10558_Y
+ connect \Y $not$libresoc.v:172735$10466_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174984$10560
+ cell $not $not$libresoc.v:172737$10468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:174984$10560_Y
+ connect \Y $not$libresoc.v:172737$10468_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:174985$10561
+ cell $not $not$libresoc.v:172738$10469
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 9
connect \A \i
- connect \Y $not$libresoc.v:174985$10561_Y
+ connect \Y $not$libresoc.v:172738$10469_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174987$10563
+ cell $not $not$libresoc.v:172740$10471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:174987$10563_Y
+ connect \Y $not$libresoc.v:172740$10471_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174989$10565
+ cell $not $not$libresoc.v:172742$10473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:174989$10565_Y
+ connect \Y $not$libresoc.v:172742$10473_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174991$10567
+ cell $not $not$libresoc.v:172744$10475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:174991$10567_Y
+ connect \Y $not$libresoc.v:172744$10475_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174993$10569
+ cell $not $not$libresoc.v:172746$10477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$32
- connect \Y $not$libresoc.v:174993$10569_Y
+ connect \Y $not$libresoc.v:172746$10477_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:174996$10572
+ cell $not $not$libresoc.v:172749$10480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:174996$10572_Y
+ connect \Y $not$libresoc.v:172749$10480_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174981$10557
+ cell $reduce_or $reduce_or$libresoc.v:172734$10465
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:174981$10557_Y
+ connect \Y $reduce_or$libresoc.v:172734$10465_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174983$10559
+ cell $reduce_or $reduce_or$libresoc.v:172736$10467
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:174983$10559_Y
+ connect \Y $reduce_or$libresoc.v:172736$10467_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174986$10562
+ cell $reduce_or $reduce_or$libresoc.v:172739$10470
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:174986$10562_Y
+ connect \Y $reduce_or$libresoc.v:172739$10470_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174988$10564
+ cell $reduce_or $reduce_or$libresoc.v:172741$10472
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:174988$10564_Y
+ connect \Y $reduce_or$libresoc.v:172741$10472_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174990$10566
+ cell $reduce_or $reduce_or$libresoc.v:172743$10474
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:174990$10566_Y
+ connect \Y $reduce_or$libresoc.v:172743$10474_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174992$10568
+ cell $reduce_or $reduce_or$libresoc.v:172745$10476
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 1
connect \A { \i [7:0] \ni [8] }
- connect \Y $reduce_or$libresoc.v:174992$10568_Y
+ connect \Y $reduce_or$libresoc.v:172745$10476_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:174994$10570
+ cell $reduce_or $reduce_or$libresoc.v:172747$10478
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:174994$10570_Y
+ connect \Y $reduce_or$libresoc.v:172747$10478_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174995$10571
+ cell $reduce_or $reduce_or$libresoc.v:172748$10479
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:174995$10571_Y
+ connect \Y $reduce_or$libresoc.v:172748$10479_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:174997$10573
+ cell $reduce_or $reduce_or$libresoc.v:172750$10481
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:174997$10573_Y
- end
- connect \$7 $not$libresoc.v:174980$10556_Y
- connect \$12 $reduce_or$libresoc.v:174981$10557_Y
- connect \$11 $not$libresoc.v:174982$10558_Y
- connect \$16 $reduce_or$libresoc.v:174983$10559_Y
- connect \$15 $not$libresoc.v:174984$10560_Y
- connect \$1 $not$libresoc.v:174985$10561_Y
- connect \$20 $reduce_or$libresoc.v:174986$10562_Y
- connect \$19 $not$libresoc.v:174987$10563_Y
- connect \$24 $reduce_or$libresoc.v:174988$10564_Y
- connect \$23 $not$libresoc.v:174989$10565_Y
- connect \$28 $reduce_or$libresoc.v:174990$10566_Y
- connect \$27 $not$libresoc.v:174991$10567_Y
- connect \$32 $reduce_or$libresoc.v:174992$10568_Y
- connect \$31 $not$libresoc.v:174993$10569_Y
- connect \$35 $reduce_or$libresoc.v:174994$10570_Y
- connect \$4 $reduce_or$libresoc.v:174995$10571_Y
- connect \$3 $not$libresoc.v:174996$10572_Y
- connect \$8 $reduce_or$libresoc.v:174997$10573_Y
+ connect \Y $reduce_or$libresoc.v:172750$10481_Y
+ end
+ connect \$7 $not$libresoc.v:172733$10464_Y
+ connect \$12 $reduce_or$libresoc.v:172734$10465_Y
+ connect \$11 $not$libresoc.v:172735$10466_Y
+ connect \$16 $reduce_or$libresoc.v:172736$10467_Y
+ connect \$15 $not$libresoc.v:172737$10468_Y
+ connect \$1 $not$libresoc.v:172738$10469_Y
+ connect \$20 $reduce_or$libresoc.v:172739$10470_Y
+ connect \$19 $not$libresoc.v:172740$10471_Y
+ connect \$24 $reduce_or$libresoc.v:172741$10472_Y
+ connect \$23 $not$libresoc.v:172742$10473_Y
+ connect \$28 $reduce_or$libresoc.v:172743$10474_Y
+ connect \$27 $not$libresoc.v:172744$10475_Y
+ connect \$32 $reduce_or$libresoc.v:172745$10476_Y
+ connect \$31 $not$libresoc.v:172746$10477_Y
+ connect \$35 $reduce_or$libresoc.v:172747$10478_Y
+ connect \$4 $reduce_or$libresoc.v:172748$10479_Y
+ connect \$3 $not$libresoc.v:172749$10480_Y
+ connect \$8 $reduce_or$libresoc.v:172750$10481_Y
connect \en_o \$35
connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t8 \$31
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:175014.1-175098.10"
+attribute \src "libresoc.v:172767.1-172851.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb"
attribute \generator "nMigen"
module \rdpick_INT_rb
- attribute \src "libresoc.v:175071.17-175071.91"
- wire $not$libresoc.v:175071$10574_Y
- attribute \src "libresoc.v:175073.18-175073.93"
- wire $not$libresoc.v:175073$10576_Y
- attribute \src "libresoc.v:175075.18-175075.93"
- wire $not$libresoc.v:175075$10578_Y
- attribute \src "libresoc.v:175076.17-175076.89"
- wire width 8 $not$libresoc.v:175076$10579_Y
- attribute \src "libresoc.v:175078.18-175078.93"
- wire $not$libresoc.v:175078$10581_Y
- attribute \src "libresoc.v:175080.18-175080.93"
- wire $not$libresoc.v:175080$10583_Y
- attribute \src "libresoc.v:175082.18-175082.93"
- wire $not$libresoc.v:175082$10585_Y
- attribute \src "libresoc.v:175085.17-175085.91"
- wire $not$libresoc.v:175085$10588_Y
- attribute \src "libresoc.v:175072.18-175072.106"
- wire $reduce_or$libresoc.v:175072$10575_Y
- attribute \src "libresoc.v:175074.18-175074.106"
- wire $reduce_or$libresoc.v:175074$10577_Y
- attribute \src "libresoc.v:175077.18-175077.106"
- wire $reduce_or$libresoc.v:175077$10580_Y
- attribute \src "libresoc.v:175079.18-175079.106"
- wire $reduce_or$libresoc.v:175079$10582_Y
- attribute \src "libresoc.v:175081.18-175081.106"
- wire $reduce_or$libresoc.v:175081$10584_Y
- attribute \src "libresoc.v:175083.18-175083.90"
- wire $reduce_or$libresoc.v:175083$10586_Y
- attribute \src "libresoc.v:175084.17-175084.103"
- wire $reduce_or$libresoc.v:175084$10587_Y
- attribute \src "libresoc.v:175086.17-175086.105"
- wire $reduce_or$libresoc.v:175086$10589_Y
+ attribute \src "libresoc.v:172824.17-172824.91"
+ wire $not$libresoc.v:172824$10482_Y
+ attribute \src "libresoc.v:172826.18-172826.93"
+ wire $not$libresoc.v:172826$10484_Y
+ attribute \src "libresoc.v:172828.18-172828.93"
+ wire $not$libresoc.v:172828$10486_Y
+ attribute \src "libresoc.v:172829.17-172829.89"
+ wire width 8 $not$libresoc.v:172829$10487_Y
+ attribute \src "libresoc.v:172831.18-172831.93"
+ wire $not$libresoc.v:172831$10489_Y
+ attribute \src "libresoc.v:172833.18-172833.93"
+ wire $not$libresoc.v:172833$10491_Y
+ attribute \src "libresoc.v:172835.18-172835.93"
+ wire $not$libresoc.v:172835$10493_Y
+ attribute \src "libresoc.v:172838.17-172838.91"
+ wire $not$libresoc.v:172838$10496_Y
+ attribute \src "libresoc.v:172825.18-172825.106"
+ wire $reduce_or$libresoc.v:172825$10483_Y
+ attribute \src "libresoc.v:172827.18-172827.106"
+ wire $reduce_or$libresoc.v:172827$10485_Y
+ attribute \src "libresoc.v:172830.18-172830.106"
+ wire $reduce_or$libresoc.v:172830$10488_Y
+ attribute \src "libresoc.v:172832.18-172832.106"
+ wire $reduce_or$libresoc.v:172832$10490_Y
+ attribute \src "libresoc.v:172834.18-172834.106"
+ wire $reduce_or$libresoc.v:172834$10492_Y
+ attribute \src "libresoc.v:172836.18-172836.90"
+ wire $reduce_or$libresoc.v:172836$10494_Y
+ attribute \src "libresoc.v:172837.17-172837.103"
+ wire $reduce_or$libresoc.v:172837$10495_Y
+ attribute \src "libresoc.v:172839.17-172839.105"
+ wire $reduce_or$libresoc.v:172839$10497_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175071$10574
+ cell $not $not$libresoc.v:172824$10482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:175071$10574_Y
+ connect \Y $not$libresoc.v:172824$10482_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175073$10576
+ cell $not $not$libresoc.v:172826$10484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:175073$10576_Y
+ connect \Y $not$libresoc.v:172826$10484_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175075$10578
+ cell $not $not$libresoc.v:172828$10486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:175075$10578_Y
+ connect \Y $not$libresoc.v:172828$10486_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175076$10579
+ cell $not $not$libresoc.v:172829$10487
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A \i
- connect \Y $not$libresoc.v:175076$10579_Y
+ connect \Y $not$libresoc.v:172829$10487_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175078$10581
+ cell $not $not$libresoc.v:172831$10489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:175078$10581_Y
+ connect \Y $not$libresoc.v:172831$10489_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175080$10583
+ cell $not $not$libresoc.v:172833$10491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:175080$10583_Y
+ connect \Y $not$libresoc.v:172833$10491_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175082$10585
+ cell $not $not$libresoc.v:172835$10493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:175082$10585_Y
+ connect \Y $not$libresoc.v:172835$10493_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175085$10588
+ cell $not $not$libresoc.v:172838$10496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:175085$10588_Y
+ connect \Y $not$libresoc.v:172838$10496_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175072$10575
+ cell $reduce_or $reduce_or$libresoc.v:172825$10483
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:175072$10575_Y
+ connect \Y $reduce_or$libresoc.v:172825$10483_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175074$10577
+ cell $reduce_or $reduce_or$libresoc.v:172827$10485
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:175074$10577_Y
+ connect \Y $reduce_or$libresoc.v:172827$10485_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175077$10580
+ cell $reduce_or $reduce_or$libresoc.v:172830$10488
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:175077$10580_Y
+ connect \Y $reduce_or$libresoc.v:172830$10488_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175079$10582
+ cell $reduce_or $reduce_or$libresoc.v:172832$10490
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:175079$10582_Y
+ connect \Y $reduce_or$libresoc.v:172832$10490_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175081$10584
+ cell $reduce_or $reduce_or$libresoc.v:172834$10492
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:175081$10584_Y
+ connect \Y $reduce_or$libresoc.v:172834$10492_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175083$10586
+ cell $reduce_or $reduce_or$libresoc.v:172836$10494
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175083$10586_Y
+ connect \Y $reduce_or$libresoc.v:172836$10494_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175084$10587
+ cell $reduce_or $reduce_or$libresoc.v:172837$10495
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:175084$10587_Y
+ connect \Y $reduce_or$libresoc.v:172837$10495_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175086$10589
+ cell $reduce_or $reduce_or$libresoc.v:172839$10497
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:175086$10589_Y
- end
- connect \$7 $not$libresoc.v:175071$10574_Y
- connect \$12 $reduce_or$libresoc.v:175072$10575_Y
- connect \$11 $not$libresoc.v:175073$10576_Y
- connect \$16 $reduce_or$libresoc.v:175074$10577_Y
- connect \$15 $not$libresoc.v:175075$10578_Y
- connect \$1 $not$libresoc.v:175076$10579_Y
- connect \$20 $reduce_or$libresoc.v:175077$10580_Y
- connect \$19 $not$libresoc.v:175078$10581_Y
- connect \$24 $reduce_or$libresoc.v:175079$10582_Y
- connect \$23 $not$libresoc.v:175080$10583_Y
- connect \$28 $reduce_or$libresoc.v:175081$10584_Y
- connect \$27 $not$libresoc.v:175082$10585_Y
- connect \$31 $reduce_or$libresoc.v:175083$10586_Y
- connect \$4 $reduce_or$libresoc.v:175084$10587_Y
- connect \$3 $not$libresoc.v:175085$10588_Y
- connect \$8 $reduce_or$libresoc.v:175086$10589_Y
+ connect \Y $reduce_or$libresoc.v:172839$10497_Y
+ end
+ connect \$7 $not$libresoc.v:172824$10482_Y
+ connect \$12 $reduce_or$libresoc.v:172825$10483_Y
+ connect \$11 $not$libresoc.v:172826$10484_Y
+ connect \$16 $reduce_or$libresoc.v:172827$10485_Y
+ connect \$15 $not$libresoc.v:172828$10486_Y
+ connect \$1 $not$libresoc.v:172829$10487_Y
+ connect \$20 $reduce_or$libresoc.v:172830$10488_Y
+ connect \$19 $not$libresoc.v:172831$10489_Y
+ connect \$24 $reduce_or$libresoc.v:172832$10490_Y
+ connect \$23 $not$libresoc.v:172833$10491_Y
+ connect \$28 $reduce_or$libresoc.v:172834$10492_Y
+ connect \$27 $not$libresoc.v:172835$10493_Y
+ connect \$31 $reduce_or$libresoc.v:172836$10494_Y
+ connect \$4 $reduce_or$libresoc.v:172837$10495_Y
+ connect \$3 $not$libresoc.v:172838$10496_Y
+ connect \$8 $reduce_or$libresoc.v:172839$10497_Y
connect \en_o \$31
connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t7 \$27
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:175102.1-175132.10"
+attribute \src "libresoc.v:172855.1-172885.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc"
attribute \generator "nMigen"
module \rdpick_INT_rc
- attribute \src "libresoc.v:175123.17-175123.89"
- wire width 2 $not$libresoc.v:175123$10590_Y
- attribute \src "libresoc.v:175125.17-175125.91"
- wire $not$libresoc.v:175125$10592_Y
- attribute \src "libresoc.v:175124.17-175124.103"
- wire $reduce_or$libresoc.v:175124$10591_Y
- attribute \src "libresoc.v:175126.17-175126.89"
- wire $reduce_or$libresoc.v:175126$10593_Y
+ attribute \src "libresoc.v:172876.17-172876.89"
+ wire width 2 $not$libresoc.v:172876$10498_Y
+ attribute \src "libresoc.v:172878.17-172878.91"
+ wire $not$libresoc.v:172878$10500_Y
+ attribute \src "libresoc.v:172877.17-172877.103"
+ wire $reduce_or$libresoc.v:172877$10499_Y
+ attribute \src "libresoc.v:172879.17-172879.89"
+ wire $reduce_or$libresoc.v:172879$10501_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175123$10590
+ cell $not $not$libresoc.v:172876$10498
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:175123$10590_Y
+ connect \Y $not$libresoc.v:172876$10498_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175125$10592
+ cell $not $not$libresoc.v:172878$10500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:175125$10592_Y
+ connect \Y $not$libresoc.v:172878$10500_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175124$10591
+ cell $reduce_or $reduce_or$libresoc.v:172877$10499
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:175124$10591_Y
+ connect \Y $reduce_or$libresoc.v:172877$10499_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175126$10593
+ cell $reduce_or $reduce_or$libresoc.v:172879$10501
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175126$10593_Y
+ connect \Y $reduce_or$libresoc.v:172879$10501_Y
end
- connect \$1 $not$libresoc.v:175123$10590_Y
- connect \$4 $reduce_or$libresoc.v:175124$10591_Y
- connect \$3 $not$libresoc.v:175125$10592_Y
- connect \$7 $reduce_or$libresoc.v:175126$10593_Y
+ connect \$1 $not$libresoc.v:172876$10498_Y
+ connect \$4 $reduce_or$libresoc.v:172877$10499_Y
+ connect \$3 $not$libresoc.v:172878$10500_Y
+ connect \$7 $reduce_or$libresoc.v:172879$10501_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:175136.1-175157.10"
+attribute \src "libresoc.v:172889.1-172910.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1"
attribute \generator "nMigen"
module \rdpick_SPR_spr1
- attribute \src "libresoc.v:175151.17-175151.89"
- wire $not$libresoc.v:175151$10594_Y
- attribute \src "libresoc.v:175152.17-175152.89"
- wire $reduce_or$libresoc.v:175152$10595_Y
+ attribute \src "libresoc.v:172904.17-172904.89"
+ wire $not$libresoc.v:172904$10502_Y
+ attribute \src "libresoc.v:172905.17-172905.89"
+ wire $reduce_or$libresoc.v:172905$10503_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175151$10594
+ cell $not $not$libresoc.v:172904$10502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:175151$10594_Y
+ connect \Y $not$libresoc.v:172904$10502_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175152$10595
+ cell $reduce_or $reduce_or$libresoc.v:172905$10503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175152$10595_Y
+ connect \Y $reduce_or$libresoc.v:172905$10503_Y
end
- connect \$1 $not$libresoc.v:175151$10594_Y
- connect \$3 $reduce_or$libresoc.v:175152$10595_Y
+ connect \$1 $not$libresoc.v:172904$10502_Y
+ connect \$3 $reduce_or$libresoc.v:172905$10503_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:175161.1-175200.10"
+attribute \src "libresoc.v:172914.1-172953.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca"
attribute \generator "nMigen"
module \rdpick_XER_xer_ca
- attribute \src "libresoc.v:175188.17-175188.91"
- wire $not$libresoc.v:175188$10596_Y
- attribute \src "libresoc.v:175190.17-175190.89"
- wire width 3 $not$libresoc.v:175190$10598_Y
- attribute \src "libresoc.v:175192.17-175192.91"
- wire $not$libresoc.v:175192$10600_Y
- attribute \src "libresoc.v:175189.18-175189.90"
- wire $reduce_or$libresoc.v:175189$10597_Y
- attribute \src "libresoc.v:175191.17-175191.103"
- wire $reduce_or$libresoc.v:175191$10599_Y
- attribute \src "libresoc.v:175193.17-175193.105"
- wire $reduce_or$libresoc.v:175193$10601_Y
+ attribute \src "libresoc.v:172941.17-172941.91"
+ wire $not$libresoc.v:172941$10504_Y
+ attribute \src "libresoc.v:172943.17-172943.89"
+ wire width 3 $not$libresoc.v:172943$10506_Y
+ attribute \src "libresoc.v:172945.17-172945.91"
+ wire $not$libresoc.v:172945$10508_Y
+ attribute \src "libresoc.v:172942.18-172942.90"
+ wire $reduce_or$libresoc.v:172942$10505_Y
+ attribute \src "libresoc.v:172944.17-172944.103"
+ wire $reduce_or$libresoc.v:172944$10507_Y
+ attribute \src "libresoc.v:172946.17-172946.105"
+ wire $reduce_or$libresoc.v:172946$10509_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175188$10596
+ cell $not $not$libresoc.v:172941$10504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:175188$10596_Y
+ connect \Y $not$libresoc.v:172941$10504_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175190$10598
+ cell $not $not$libresoc.v:172943$10506
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:175190$10598_Y
+ connect \Y $not$libresoc.v:172943$10506_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175192$10600
+ cell $not $not$libresoc.v:172945$10508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:175192$10600_Y
+ connect \Y $not$libresoc.v:172945$10508_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175189$10597
+ cell $reduce_or $reduce_or$libresoc.v:172942$10505
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175189$10597_Y
+ connect \Y $reduce_or$libresoc.v:172942$10505_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175191$10599
+ cell $reduce_or $reduce_or$libresoc.v:172944$10507
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:175191$10599_Y
+ connect \Y $reduce_or$libresoc.v:172944$10507_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175193$10601
+ cell $reduce_or $reduce_or$libresoc.v:172946$10509
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:175193$10601_Y
- end
- connect \$7 $not$libresoc.v:175188$10596_Y
- connect \$11 $reduce_or$libresoc.v:175189$10597_Y
- connect \$1 $not$libresoc.v:175190$10598_Y
- connect \$4 $reduce_or$libresoc.v:175191$10599_Y
- connect \$3 $not$libresoc.v:175192$10600_Y
- connect \$8 $reduce_or$libresoc.v:175193$10601_Y
+ connect \Y $reduce_or$libresoc.v:172946$10509_Y
+ end
+ connect \$7 $not$libresoc.v:172941$10504_Y
+ connect \$11 $reduce_or$libresoc.v:172942$10505_Y
+ connect \$1 $not$libresoc.v:172943$10506_Y
+ connect \$4 $reduce_or$libresoc.v:172944$10507_Y
+ connect \$3 $not$libresoc.v:172945$10508_Y
+ connect \$8 $reduce_or$libresoc.v:172946$10509_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:175204.1-175225.10"
+attribute \src "libresoc.v:172957.1-172978.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov"
attribute \generator "nMigen"
module \rdpick_XER_xer_ov
- attribute \src "libresoc.v:175219.17-175219.89"
- wire $not$libresoc.v:175219$10602_Y
- attribute \src "libresoc.v:175220.17-175220.89"
- wire $reduce_or$libresoc.v:175220$10603_Y
+ attribute \src "libresoc.v:172972.17-172972.89"
+ wire $not$libresoc.v:172972$10510_Y
+ attribute \src "libresoc.v:172973.17-172973.89"
+ wire $reduce_or$libresoc.v:172973$10511_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175219$10602
+ cell $not $not$libresoc.v:172972$10510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:175219$10602_Y
+ connect \Y $not$libresoc.v:172972$10510_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175220$10603
+ cell $reduce_or $reduce_or$libresoc.v:172973$10511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175220$10603_Y
+ connect \Y $reduce_or$libresoc.v:172973$10511_Y
end
- connect \$1 $not$libresoc.v:175219$10602_Y
- connect \$3 $reduce_or$libresoc.v:175220$10603_Y
+ connect \$1 $not$libresoc.v:172972$10510_Y
+ connect \$3 $reduce_or$libresoc.v:172973$10511_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:175229.1-175295.10"
+attribute \src "libresoc.v:172982.1-173048.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so"
attribute \generator "nMigen"
module \rdpick_XER_xer_so
- attribute \src "libresoc.v:175274.17-175274.91"
- wire $not$libresoc.v:175274$10604_Y
- attribute \src "libresoc.v:175276.18-175276.93"
- wire $not$libresoc.v:175276$10606_Y
- attribute \src "libresoc.v:175278.18-175278.93"
- wire $not$libresoc.v:175278$10608_Y
- attribute \src "libresoc.v:175279.17-175279.89"
- wire width 6 $not$libresoc.v:175279$10609_Y
- attribute \src "libresoc.v:175281.18-175281.93"
- wire $not$libresoc.v:175281$10611_Y
- attribute \src "libresoc.v:175284.17-175284.91"
- wire $not$libresoc.v:175284$10614_Y
- attribute \src "libresoc.v:175275.18-175275.106"
- wire $reduce_or$libresoc.v:175275$10605_Y
- attribute \src "libresoc.v:175277.18-175277.106"
- wire $reduce_or$libresoc.v:175277$10607_Y
- attribute \src "libresoc.v:175280.18-175280.106"
- wire $reduce_or$libresoc.v:175280$10610_Y
- attribute \src "libresoc.v:175282.18-175282.90"
- wire $reduce_or$libresoc.v:175282$10612_Y
- attribute \src "libresoc.v:175283.17-175283.103"
- wire $reduce_or$libresoc.v:175283$10613_Y
- attribute \src "libresoc.v:175285.17-175285.105"
- wire $reduce_or$libresoc.v:175285$10615_Y
+ attribute \src "libresoc.v:173027.17-173027.91"
+ wire $not$libresoc.v:173027$10512_Y
+ attribute \src "libresoc.v:173029.18-173029.93"
+ wire $not$libresoc.v:173029$10514_Y
+ attribute \src "libresoc.v:173031.18-173031.93"
+ wire $not$libresoc.v:173031$10516_Y
+ attribute \src "libresoc.v:173032.17-173032.89"
+ wire width 6 $not$libresoc.v:173032$10517_Y
+ attribute \src "libresoc.v:173034.18-173034.93"
+ wire $not$libresoc.v:173034$10519_Y
+ attribute \src "libresoc.v:173037.17-173037.91"
+ wire $not$libresoc.v:173037$10522_Y
+ attribute \src "libresoc.v:173028.18-173028.106"
+ wire $reduce_or$libresoc.v:173028$10513_Y
+ attribute \src "libresoc.v:173030.18-173030.106"
+ wire $reduce_or$libresoc.v:173030$10515_Y
+ attribute \src "libresoc.v:173033.18-173033.106"
+ wire $reduce_or$libresoc.v:173033$10518_Y
+ attribute \src "libresoc.v:173035.18-173035.90"
+ wire $reduce_or$libresoc.v:173035$10520_Y
+ attribute \src "libresoc.v:173036.17-173036.103"
+ wire $reduce_or$libresoc.v:173036$10521_Y
+ attribute \src "libresoc.v:173038.17-173038.105"
+ wire $reduce_or$libresoc.v:173038$10523_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175274$10604
+ cell $not $not$libresoc.v:173027$10512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:175274$10604_Y
+ connect \Y $not$libresoc.v:173027$10512_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175276$10606
+ cell $not $not$libresoc.v:173029$10514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:175276$10606_Y
+ connect \Y $not$libresoc.v:173029$10514_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175278$10608
+ cell $not $not$libresoc.v:173031$10516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:175278$10608_Y
+ connect \Y $not$libresoc.v:173031$10516_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:175279$10609
+ cell $not $not$libresoc.v:173032$10517
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \i
- connect \Y $not$libresoc.v:175279$10609_Y
+ connect \Y $not$libresoc.v:173032$10517_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175281$10611
+ cell $not $not$libresoc.v:173034$10519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:175281$10611_Y
+ connect \Y $not$libresoc.v:173034$10519_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:175284$10614
+ cell $not $not$libresoc.v:173037$10522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:175284$10614_Y
+ connect \Y $not$libresoc.v:173037$10522_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175275$10605
+ cell $reduce_or $reduce_or$libresoc.v:173028$10513
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:175275$10605_Y
+ connect \Y $reduce_or$libresoc.v:173028$10513_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175277$10607
+ cell $reduce_or $reduce_or$libresoc.v:173030$10515
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:175277$10607_Y
+ connect \Y $reduce_or$libresoc.v:173030$10515_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175280$10610
+ cell $reduce_or $reduce_or$libresoc.v:173033$10518
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:175280$10610_Y
+ connect \Y $reduce_or$libresoc.v:173033$10518_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:175282$10612
+ cell $reduce_or $reduce_or$libresoc.v:173035$10520
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:175282$10612_Y
+ connect \Y $reduce_or$libresoc.v:173035$10520_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175283$10613
+ cell $reduce_or $reduce_or$libresoc.v:173036$10521
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:175283$10613_Y
+ connect \Y $reduce_or$libresoc.v:173036$10521_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:175285$10615
+ cell $reduce_or $reduce_or$libresoc.v:173038$10523
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:175285$10615_Y
- end
- connect \$7 $not$libresoc.v:175274$10604_Y
- connect \$12 $reduce_or$libresoc.v:175275$10605_Y
- connect \$11 $not$libresoc.v:175276$10606_Y
- connect \$16 $reduce_or$libresoc.v:175277$10607_Y
- connect \$15 $not$libresoc.v:175278$10608_Y
- connect \$1 $not$libresoc.v:175279$10609_Y
- connect \$20 $reduce_or$libresoc.v:175280$10610_Y
- connect \$19 $not$libresoc.v:175281$10611_Y
- connect \$23 $reduce_or$libresoc.v:175282$10612_Y
- connect \$4 $reduce_or$libresoc.v:175283$10613_Y
- connect \$3 $not$libresoc.v:175284$10614_Y
- connect \$8 $reduce_or$libresoc.v:175285$10615_Y
+ connect \Y $reduce_or$libresoc.v:173038$10523_Y
+ end
+ connect \$7 $not$libresoc.v:173027$10512_Y
+ connect \$12 $reduce_or$libresoc.v:173028$10513_Y
+ connect \$11 $not$libresoc.v:173029$10514_Y
+ connect \$16 $reduce_or$libresoc.v:173030$10515_Y
+ connect \$15 $not$libresoc.v:173031$10516_Y
+ connect \$1 $not$libresoc.v:173032$10517_Y
+ connect \$20 $reduce_or$libresoc.v:173033$10518_Y
+ connect \$19 $not$libresoc.v:173034$10519_Y
+ connect \$23 $reduce_or$libresoc.v:173035$10520_Y
+ connect \$4 $reduce_or$libresoc.v:173036$10521_Y
+ connect \$3 $not$libresoc.v:173037$10522_Y
+ connect \$8 $reduce_or$libresoc.v:173038$10523_Y
connect \en_o \$23
connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t5 \$19
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:175299.1-175770.10"
+attribute \src "libresoc.v:173052.1-173523.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0"
attribute \generator "nMigen"
module \reg_0
- attribute \src "libresoc.v:175300.7-175300.20"
+ attribute \src "libresoc.v:173053.7-173053.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $0\r0__data_o$next[3:0]$10671
- attribute \src "libresoc.v:175385.3-175386.37"
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $0\r0__data_o$next[3:0]$10579
+ attribute \src "libresoc.v:173138.3-173139.37"
wire width 4 $0\r0__data_o[3:0]
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $0\r20__data_o$next[3:0]$10685
- attribute \src "libresoc.v:175383.3-175384.39"
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $0\r20__data_o$next[3:0]$10593
+ attribute \src "libresoc.v:173136.3-173137.39"
wire width 4 $0\r20__data_o[3:0]
- attribute \src "libresoc.v:175463.3-175489.6"
- wire width 4 $0\reg$next[3:0]$10637
- attribute \src "libresoc.v:175381.3-175382.25"
+ attribute \src "libresoc.v:173216.3-173242.6"
+ wire width 4 $0\reg$next[3:0]$10545
+ attribute \src "libresoc.v:173134.3-173135.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $0\src10__data_o$next[3:0]$10628
- attribute \src "libresoc.v:175391.3-175392.43"
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $0\src10__data_o$next[3:0]$10536
+ attribute \src "libresoc.v:173144.3-173145.43"
wire width 4 $0\src10__data_o[3:0]
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $0\src20__data_o$next[3:0]$10643
- attribute \src "libresoc.v:175389.3-175390.43"
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $0\src20__data_o$next[3:0]$10551
+ attribute \src "libresoc.v:173142.3-173143.43"
wire width 4 $0\src20__data_o[3:0]
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $0\src30__data_o$next[3:0]$10657
- attribute \src "libresoc.v:175387.3-175388.43"
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $0\src30__data_o$next[3:0]$10565
+ attribute \src "libresoc.v:173140.3-173141.43"
wire width 4 $0\src30__data_o[3:0]
- attribute \src "libresoc.v:175670.3-175699.6"
- wire $0\wr_detect$10[0:0]$10679
- attribute \src "libresoc.v:175740.3-175769.6"
- wire $0\wr_detect$13[0:0]$10693
- attribute \src "libresoc.v:175530.3-175559.6"
- wire $0\wr_detect$4[0:0]$10651
- attribute \src "libresoc.v:175600.3-175629.6"
- wire $0\wr_detect$7[0:0]$10665
- attribute \src "libresoc.v:175433.3-175462.6"
+ attribute \src "libresoc.v:173423.3-173452.6"
+ wire $0\wr_detect$10[0:0]$10587
+ attribute \src "libresoc.v:173493.3-173522.6"
+ wire $0\wr_detect$13[0:0]$10601
+ attribute \src "libresoc.v:173283.3-173312.6"
+ wire $0\wr_detect$4[0:0]$10559
+ attribute \src "libresoc.v:173353.3-173382.6"
+ wire $0\wr_detect$7[0:0]$10573
+ attribute \src "libresoc.v:173186.3-173215.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $1\r0__data_o$next[3:0]$10672
- attribute \src "libresoc.v:175325.13-175325.30"
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $1\r0__data_o$next[3:0]$10580
+ attribute \src "libresoc.v:173078.13-173078.30"
wire width 4 $1\r0__data_o[3:0]
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $1\r20__data_o$next[3:0]$10686
- attribute \src "libresoc.v:175332.13-175332.31"
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $1\r20__data_o$next[3:0]$10594
+ attribute \src "libresoc.v:173085.13-173085.31"
wire width 4 $1\r20__data_o[3:0]
- attribute \src "libresoc.v:175463.3-175489.6"
- wire width 4 $1\reg$next[3:0]$10638
- attribute \src "libresoc.v:175338.13-175338.25"
+ attribute \src "libresoc.v:173216.3-173242.6"
+ wire width 4 $1\reg$next[3:0]$10546
+ attribute \src "libresoc.v:173091.13-173091.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $1\src10__data_o$next[3:0]$10629
- attribute \src "libresoc.v:175343.13-175343.33"
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $1\src10__data_o$next[3:0]$10537
+ attribute \src "libresoc.v:173096.13-173096.33"
wire width 4 $1\src10__data_o[3:0]
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $1\src20__data_o$next[3:0]$10644
- attribute \src "libresoc.v:175350.13-175350.33"
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $1\src20__data_o$next[3:0]$10552
+ attribute \src "libresoc.v:173103.13-173103.33"
wire width 4 $1\src20__data_o[3:0]
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $1\src30__data_o$next[3:0]$10658
- attribute \src "libresoc.v:175357.13-175357.33"
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $1\src30__data_o$next[3:0]$10566
+ attribute \src "libresoc.v:173110.13-173110.33"
wire width 4 $1\src30__data_o[3:0]
- attribute \src "libresoc.v:175670.3-175699.6"
- wire $1\wr_detect$10[0:0]$10680
- attribute \src "libresoc.v:175740.3-175769.6"
- wire $1\wr_detect$13[0:0]$10694
- attribute \src "libresoc.v:175530.3-175559.6"
- wire $1\wr_detect$4[0:0]$10652
- attribute \src "libresoc.v:175600.3-175629.6"
- wire $1\wr_detect$7[0:0]$10666
- attribute \src "libresoc.v:175433.3-175462.6"
+ attribute \src "libresoc.v:173423.3-173452.6"
+ wire $1\wr_detect$10[0:0]$10588
+ attribute \src "libresoc.v:173493.3-173522.6"
+ wire $1\wr_detect$13[0:0]$10602
+ attribute \src "libresoc.v:173283.3-173312.6"
+ wire $1\wr_detect$4[0:0]$10560
+ attribute \src "libresoc.v:173353.3-173382.6"
+ wire $1\wr_detect$7[0:0]$10574
+ attribute \src "libresoc.v:173186.3-173215.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $2\r0__data_o$next[3:0]$10673
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $2\r20__data_o$next[3:0]$10687
- attribute \src "libresoc.v:175463.3-175489.6"
- wire width 4 $2\reg$next[3:0]$10639
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $2\src10__data_o$next[3:0]$10630
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $2\src20__data_o$next[3:0]$10645
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $2\src30__data_o$next[3:0]$10659
- attribute \src "libresoc.v:175670.3-175699.6"
- wire $2\wr_detect$10[0:0]$10681
- attribute \src "libresoc.v:175740.3-175769.6"
- wire $2\wr_detect$13[0:0]$10695
- attribute \src "libresoc.v:175530.3-175559.6"
- wire $2\wr_detect$4[0:0]$10653
- attribute \src "libresoc.v:175600.3-175629.6"
- wire $2\wr_detect$7[0:0]$10667
- attribute \src "libresoc.v:175433.3-175462.6"
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $2\r0__data_o$next[3:0]$10581
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $2\r20__data_o$next[3:0]$10595
+ attribute \src "libresoc.v:173216.3-173242.6"
+ wire width 4 $2\reg$next[3:0]$10547
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $2\src10__data_o$next[3:0]$10538
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $2\src20__data_o$next[3:0]$10553
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $2\src30__data_o$next[3:0]$10567
+ attribute \src "libresoc.v:173423.3-173452.6"
+ wire $2\wr_detect$10[0:0]$10589
+ attribute \src "libresoc.v:173493.3-173522.6"
+ wire $2\wr_detect$13[0:0]$10603
+ attribute \src "libresoc.v:173283.3-173312.6"
+ wire $2\wr_detect$4[0:0]$10561
+ attribute \src "libresoc.v:173353.3-173382.6"
+ wire $2\wr_detect$7[0:0]$10575
+ attribute \src "libresoc.v:173186.3-173215.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $3\r0__data_o$next[3:0]$10674
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $3\r20__data_o$next[3:0]$10688
- attribute \src "libresoc.v:175463.3-175489.6"
- wire width 4 $3\reg$next[3:0]$10640
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $3\src10__data_o$next[3:0]$10631
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $3\src20__data_o$next[3:0]$10646
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $3\src30__data_o$next[3:0]$10660
- attribute \src "libresoc.v:175670.3-175699.6"
- wire $3\wr_detect$10[0:0]$10682
- attribute \src "libresoc.v:175740.3-175769.6"
- wire $3\wr_detect$13[0:0]$10696
- attribute \src "libresoc.v:175530.3-175559.6"
- wire $3\wr_detect$4[0:0]$10654
- attribute \src "libresoc.v:175600.3-175629.6"
- wire $3\wr_detect$7[0:0]$10668
- attribute \src "libresoc.v:175433.3-175462.6"
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $3\r0__data_o$next[3:0]$10582
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $3\r20__data_o$next[3:0]$10596
+ attribute \src "libresoc.v:173216.3-173242.6"
+ wire width 4 $3\reg$next[3:0]$10548
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $3\src10__data_o$next[3:0]$10539
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $3\src20__data_o$next[3:0]$10554
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $3\src30__data_o$next[3:0]$10568
+ attribute \src "libresoc.v:173423.3-173452.6"
+ wire $3\wr_detect$10[0:0]$10590
+ attribute \src "libresoc.v:173493.3-173522.6"
+ wire $3\wr_detect$13[0:0]$10604
+ attribute \src "libresoc.v:173283.3-173312.6"
+ wire $3\wr_detect$4[0:0]$10562
+ attribute \src "libresoc.v:173353.3-173382.6"
+ wire $3\wr_detect$7[0:0]$10576
+ attribute \src "libresoc.v:173186.3-173215.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $4\r0__data_o$next[3:0]$10675
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $4\r20__data_o$next[3:0]$10689
- attribute \src "libresoc.v:175463.3-175489.6"
- wire width 4 $4\reg$next[3:0]$10641
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $4\src10__data_o$next[3:0]$10632
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $4\src20__data_o$next[3:0]$10647
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $4\src30__data_o$next[3:0]$10661
- attribute \src "libresoc.v:175670.3-175699.6"
- wire $4\wr_detect$10[0:0]$10683
- attribute \src "libresoc.v:175740.3-175769.6"
- wire $4\wr_detect$13[0:0]$10697
- attribute \src "libresoc.v:175530.3-175559.6"
- wire $4\wr_detect$4[0:0]$10655
- attribute \src "libresoc.v:175600.3-175629.6"
- wire $4\wr_detect$7[0:0]$10669
- attribute \src "libresoc.v:175433.3-175462.6"
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $4\r0__data_o$next[3:0]$10583
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $4\r20__data_o$next[3:0]$10597
+ attribute \src "libresoc.v:173216.3-173242.6"
+ wire width 4 $4\reg$next[3:0]$10549
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $4\src10__data_o$next[3:0]$10540
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $4\src20__data_o$next[3:0]$10555
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $4\src30__data_o$next[3:0]$10569
+ attribute \src "libresoc.v:173423.3-173452.6"
+ wire $4\wr_detect$10[0:0]$10591
+ attribute \src "libresoc.v:173493.3-173522.6"
+ wire $4\wr_detect$13[0:0]$10605
+ attribute \src "libresoc.v:173283.3-173312.6"
+ wire $4\wr_detect$4[0:0]$10563
+ attribute \src "libresoc.v:173353.3-173382.6"
+ wire $4\wr_detect$7[0:0]$10577
+ attribute \src "libresoc.v:173186.3-173215.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $5\r0__data_o$next[3:0]$10676
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $5\r20__data_o$next[3:0]$10690
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $5\src10__data_o$next[3:0]$10633
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $5\src20__data_o$next[3:0]$10648
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $5\src30__data_o$next[3:0]$10662
- attribute \src "libresoc.v:175630.3-175669.6"
- wire width 4 $6\r0__data_o$next[3:0]$10677
- attribute \src "libresoc.v:175700.3-175739.6"
- wire width 4 $6\r20__data_o$next[3:0]$10691
- attribute \src "libresoc.v:175393.3-175432.6"
- wire width 4 $6\src10__data_o$next[3:0]$10634
- attribute \src "libresoc.v:175490.3-175529.6"
- wire width 4 $6\src20__data_o$next[3:0]$10649
- attribute \src "libresoc.v:175560.3-175599.6"
- wire width 4 $6\src30__data_o$next[3:0]$10663
- attribute \src "libresoc.v:175376.17-175376.104"
- wire $not$libresoc.v:175376$10616_Y
- attribute \src "libresoc.v:175377.18-175377.105"
- wire $not$libresoc.v:175377$10617_Y
- attribute \src "libresoc.v:175378.17-175378.100"
- wire $not$libresoc.v:175378$10618_Y
- attribute \src "libresoc.v:175379.17-175379.103"
- wire $not$libresoc.v:175379$10619_Y
- attribute \src "libresoc.v:175380.17-175380.103"
- wire $not$libresoc.v:175380$10620_Y
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $5\r0__data_o$next[3:0]$10584
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $5\r20__data_o$next[3:0]$10598
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $5\src10__data_o$next[3:0]$10541
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $5\src20__data_o$next[3:0]$10556
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $5\src30__data_o$next[3:0]$10570
+ attribute \src "libresoc.v:173383.3-173422.6"
+ wire width 4 $6\r0__data_o$next[3:0]$10585
+ attribute \src "libresoc.v:173453.3-173492.6"
+ wire width 4 $6\r20__data_o$next[3:0]$10599
+ attribute \src "libresoc.v:173146.3-173185.6"
+ wire width 4 $6\src10__data_o$next[3:0]$10542
+ attribute \src "libresoc.v:173243.3-173282.6"
+ wire width 4 $6\src20__data_o$next[3:0]$10557
+ attribute \src "libresoc.v:173313.3-173352.6"
+ wire width 4 $6\src30__data_o$next[3:0]$10571
+ attribute \src "libresoc.v:173129.17-173129.104"
+ wire $not$libresoc.v:173129$10524_Y
+ attribute \src "libresoc.v:173130.18-173130.105"
+ wire $not$libresoc.v:173130$10525_Y
+ attribute \src "libresoc.v:173131.17-173131.100"
+ wire $not$libresoc.v:173131$10526_Y
+ attribute \src "libresoc.v:173132.17-173132.103"
+ wire $not$libresoc.v:173132$10527_Y
+ attribute \src "libresoc.v:173133.17-173133.103"
+ wire $not$libresoc.v:173133$10528_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest10__data_i
wire width 4 input 11 \dest20__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest20__wen
- attribute \src "libresoc.v:175300.7-175300.15"
+ attribute \src "libresoc.v:173053.7-173053.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 12 \r0__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175376$10616
+ cell $not $not$libresoc.v:173129$10524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:175376$10616_Y
+ connect \Y $not$libresoc.v:173129$10524_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175377$10617
+ cell $not $not$libresoc.v:173130$10525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:175377$10617_Y
+ connect \Y $not$libresoc.v:173130$10525_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175378$10618
+ cell $not $not$libresoc.v:173131$10526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:175378$10618_Y
+ connect \Y $not$libresoc.v:173131$10526_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175379$10619
+ cell $not $not$libresoc.v:173132$10527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:175379$10619_Y
+ connect \Y $not$libresoc.v:173132$10527_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175380$10620
+ cell $not $not$libresoc.v:173133$10528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:175380$10620_Y
+ connect \Y $not$libresoc.v:173133$10528_Y
end
- attribute \src "libresoc.v:175300.7-175300.20"
- process $proc$libresoc.v:175300$10698
+ attribute \src "libresoc.v:173053.7-173053.20"
+ process $proc$libresoc.v:173053$10606
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:175325.13-175325.30"
- process $proc$libresoc.v:175325$10699
+ attribute \src "libresoc.v:173078.13-173078.30"
+ process $proc$libresoc.v:173078$10607
assign { } { }
assign $1\r0__data_o[3:0] 4'0000
sync always
sync init
update \r0__data_o $1\r0__data_o[3:0]
end
- attribute \src "libresoc.v:175332.13-175332.31"
- process $proc$libresoc.v:175332$10700
+ attribute \src "libresoc.v:173085.13-173085.31"
+ process $proc$libresoc.v:173085$10608
assign { } { }
assign $1\r20__data_o[3:0] 4'0000
sync always
sync init
update \r20__data_o $1\r20__data_o[3:0]
end
- attribute \src "libresoc.v:175338.13-175338.25"
- process $proc$libresoc.v:175338$10701
+ attribute \src "libresoc.v:173091.13-173091.25"
+ process $proc$libresoc.v:173091$10609
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:175343.13-175343.33"
- process $proc$libresoc.v:175343$10702
+ attribute \src "libresoc.v:173096.13-173096.33"
+ process $proc$libresoc.v:173096$10610
assign { } { }
assign $1\src10__data_o[3:0] 4'0000
sync always
sync init
update \src10__data_o $1\src10__data_o[3:0]
end
- attribute \src "libresoc.v:175350.13-175350.33"
- process $proc$libresoc.v:175350$10703
+ attribute \src "libresoc.v:173103.13-173103.33"
+ process $proc$libresoc.v:173103$10611
assign { } { }
assign $1\src20__data_o[3:0] 4'0000
sync always
sync init
update \src20__data_o $1\src20__data_o[3:0]
end
- attribute \src "libresoc.v:175357.13-175357.33"
- process $proc$libresoc.v:175357$10704
+ attribute \src "libresoc.v:173110.13-173110.33"
+ process $proc$libresoc.v:173110$10612
assign { } { }
assign $1\src30__data_o[3:0] 4'0000
sync always
sync init
update \src30__data_o $1\src30__data_o[3:0]
end
- attribute \src "libresoc.v:175381.3-175382.25"
- process $proc$libresoc.v:175381$10621
+ attribute \src "libresoc.v:173134.3-173135.25"
+ process $proc$libresoc.v:173134$10529
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:175383.3-175384.39"
- process $proc$libresoc.v:175383$10622
+ attribute \src "libresoc.v:173136.3-173137.39"
+ process $proc$libresoc.v:173136$10530
assign { } { }
assign $0\r20__data_o[3:0] \r20__data_o$next
sync posedge \coresync_clk
update \r20__data_o $0\r20__data_o[3:0]
end
- attribute \src "libresoc.v:175385.3-175386.37"
- process $proc$libresoc.v:175385$10623
+ attribute \src "libresoc.v:173138.3-173139.37"
+ process $proc$libresoc.v:173138$10531
assign { } { }
assign $0\r0__data_o[3:0] \r0__data_o$next
sync posedge \coresync_clk
update \r0__data_o $0\r0__data_o[3:0]
end
- attribute \src "libresoc.v:175387.3-175388.43"
- process $proc$libresoc.v:175387$10624
+ attribute \src "libresoc.v:173140.3-173141.43"
+ process $proc$libresoc.v:173140$10532
assign { } { }
assign $0\src30__data_o[3:0] \src30__data_o$next
sync posedge \coresync_clk
update \src30__data_o $0\src30__data_o[3:0]
end
- attribute \src "libresoc.v:175389.3-175390.43"
- process $proc$libresoc.v:175389$10625
+ attribute \src "libresoc.v:173142.3-173143.43"
+ process $proc$libresoc.v:173142$10533
assign { } { }
assign $0\src20__data_o[3:0] \src20__data_o$next
sync posedge \coresync_clk
update \src20__data_o $0\src20__data_o[3:0]
end
- attribute \src "libresoc.v:175391.3-175392.43"
- process $proc$libresoc.v:175391$10626
+ attribute \src "libresoc.v:173144.3-173145.43"
+ process $proc$libresoc.v:173144$10534
assign { } { }
assign $0\src10__data_o[3:0] \src10__data_o$next
sync posedge \coresync_clk
update \src10__data_o $0\src10__data_o[3:0]
end
- attribute \src "libresoc.v:175393.3-175432.6"
- process $proc$libresoc.v:175393$10627
+ attribute \src "libresoc.v:173146.3-173185.6"
+ process $proc$libresoc.v:173146$10535
assign { } { }
assign { } { }
assign { } { }
- assign $0\src10__data_o$next[3:0]$10628 $6\src10__data_o$next[3:0]$10634
- attribute \src "libresoc.v:175394.5-175394.29"
+ assign $0\src10__data_o$next[3:0]$10536 $6\src10__data_o$next[3:0]$10542
+ attribute \src "libresoc.v:173147.5-173147.29"
switch \initial
- attribute \src "libresoc.v:175394.9-175394.17"
+ attribute \src "libresoc.v:173147.9-173147.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src10__data_o$next[3:0]$10629 $5\src10__data_o$next[3:0]$10633
+ assign $1\src10__data_o$next[3:0]$10537 $5\src10__data_o$next[3:0]$10541
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src10__data_o$next[3:0]$10630 \dest10__data_i
+ assign $2\src10__data_o$next[3:0]$10538 \dest10__data_i
case
- assign $2\src10__data_o$next[3:0]$10630 4'0000
+ assign $2\src10__data_o$next[3:0]$10538 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src10__data_o$next[3:0]$10631 \dest20__data_i
+ assign $3\src10__data_o$next[3:0]$10539 \dest20__data_i
case
- assign $3\src10__data_o$next[3:0]$10631 $2\src10__data_o$next[3:0]$10630
+ assign $3\src10__data_o$next[3:0]$10539 $2\src10__data_o$next[3:0]$10538
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src10__data_o$next[3:0]$10632 \w0__data_i
+ assign $4\src10__data_o$next[3:0]$10540 \w0__data_i
case
- assign $4\src10__data_o$next[3:0]$10632 $3\src10__data_o$next[3:0]$10631
+ assign $4\src10__data_o$next[3:0]$10540 $3\src10__data_o$next[3:0]$10539
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src10__data_o$next[3:0]$10633 \reg
+ assign $5\src10__data_o$next[3:0]$10541 \reg
case
- assign $5\src10__data_o$next[3:0]$10633 $4\src10__data_o$next[3:0]$10632
+ assign $5\src10__data_o$next[3:0]$10541 $4\src10__data_o$next[3:0]$10540
end
case
- assign $1\src10__data_o$next[3:0]$10629 4'0000
+ assign $1\src10__data_o$next[3:0]$10537 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src10__data_o$next[3:0]$10634 4'0000
+ assign $6\src10__data_o$next[3:0]$10542 4'0000
case
- assign $6\src10__data_o$next[3:0]$10634 $1\src10__data_o$next[3:0]$10629
+ assign $6\src10__data_o$next[3:0]$10542 $1\src10__data_o$next[3:0]$10537
end
sync always
- update \src10__data_o$next $0\src10__data_o$next[3:0]$10628
+ update \src10__data_o$next $0\src10__data_o$next[3:0]$10536
end
- attribute \src "libresoc.v:175433.3-175462.6"
- process $proc$libresoc.v:175433$10635
+ attribute \src "libresoc.v:173186.3-173215.6"
+ process $proc$libresoc.v:173186$10543
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:175434.5-175434.29"
+ attribute \src "libresoc.v:173187.5-173187.29"
switch \initial
- attribute \src "libresoc.v:175434.9-175434.17"
+ attribute \src "libresoc.v:173187.9-173187.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:175463.3-175489.6"
- process $proc$libresoc.v:175463$10636
+ attribute \src "libresoc.v:173216.3-173242.6"
+ process $proc$libresoc.v:173216$10544
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$10637 $4\reg$next[3:0]$10641
- attribute \src "libresoc.v:175464.5-175464.29"
+ assign $0\reg$next[3:0]$10545 $4\reg$next[3:0]$10549
+ attribute \src "libresoc.v:173217.5-173217.29"
switch \initial
- attribute \src "libresoc.v:175464.9-175464.17"
+ attribute \src "libresoc.v:173217.9-173217.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$10638 \dest10__data_i
+ assign $1\reg$next[3:0]$10546 \dest10__data_i
case
- assign $1\reg$next[3:0]$10638 \reg
+ assign $1\reg$next[3:0]$10546 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$10639 \dest20__data_i
+ assign $2\reg$next[3:0]$10547 \dest20__data_i
case
- assign $2\reg$next[3:0]$10639 $1\reg$next[3:0]$10638
+ assign $2\reg$next[3:0]$10547 $1\reg$next[3:0]$10546
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$10640 \w0__data_i
+ assign $3\reg$next[3:0]$10548 \w0__data_i
case
- assign $3\reg$next[3:0]$10640 $2\reg$next[3:0]$10639
+ assign $3\reg$next[3:0]$10548 $2\reg$next[3:0]$10547
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$10641 4'0000
+ assign $4\reg$next[3:0]$10549 4'0000
case
- assign $4\reg$next[3:0]$10641 $3\reg$next[3:0]$10640
+ assign $4\reg$next[3:0]$10549 $3\reg$next[3:0]$10548
end
sync always
- update \reg$next $0\reg$next[3:0]$10637
+ update \reg$next $0\reg$next[3:0]$10545
end
- attribute \src "libresoc.v:175490.3-175529.6"
- process $proc$libresoc.v:175490$10642
+ attribute \src "libresoc.v:173243.3-173282.6"
+ process $proc$libresoc.v:173243$10550
assign { } { }
assign { } { }
assign { } { }
- assign $0\src20__data_o$next[3:0]$10643 $6\src20__data_o$next[3:0]$10649
- attribute \src "libresoc.v:175491.5-175491.29"
+ assign $0\src20__data_o$next[3:0]$10551 $6\src20__data_o$next[3:0]$10557
+ attribute \src "libresoc.v:173244.5-173244.29"
switch \initial
- attribute \src "libresoc.v:175491.9-175491.17"
+ attribute \src "libresoc.v:173244.9-173244.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src20__data_o$next[3:0]$10644 $5\src20__data_o$next[3:0]$10648
+ assign $1\src20__data_o$next[3:0]$10552 $5\src20__data_o$next[3:0]$10556
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src20__data_o$next[3:0]$10645 \dest10__data_i
+ assign $2\src20__data_o$next[3:0]$10553 \dest10__data_i
case
- assign $2\src20__data_o$next[3:0]$10645 4'0000
+ assign $2\src20__data_o$next[3:0]$10553 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src20__data_o$next[3:0]$10646 \dest20__data_i
+ assign $3\src20__data_o$next[3:0]$10554 \dest20__data_i
case
- assign $3\src20__data_o$next[3:0]$10646 $2\src20__data_o$next[3:0]$10645
+ assign $3\src20__data_o$next[3:0]$10554 $2\src20__data_o$next[3:0]$10553
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src20__data_o$next[3:0]$10647 \w0__data_i
+ assign $4\src20__data_o$next[3:0]$10555 \w0__data_i
case
- assign $4\src20__data_o$next[3:0]$10647 $3\src20__data_o$next[3:0]$10646
+ assign $4\src20__data_o$next[3:0]$10555 $3\src20__data_o$next[3:0]$10554
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src20__data_o$next[3:0]$10648 \reg
+ assign $5\src20__data_o$next[3:0]$10556 \reg
case
- assign $5\src20__data_o$next[3:0]$10648 $4\src20__data_o$next[3:0]$10647
+ assign $5\src20__data_o$next[3:0]$10556 $4\src20__data_o$next[3:0]$10555
end
case
- assign $1\src20__data_o$next[3:0]$10644 4'0000
+ assign $1\src20__data_o$next[3:0]$10552 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src20__data_o$next[3:0]$10649 4'0000
+ assign $6\src20__data_o$next[3:0]$10557 4'0000
case
- assign $6\src20__data_o$next[3:0]$10649 $1\src20__data_o$next[3:0]$10644
+ assign $6\src20__data_o$next[3:0]$10557 $1\src20__data_o$next[3:0]$10552
end
sync always
- update \src20__data_o$next $0\src20__data_o$next[3:0]$10643
+ update \src20__data_o$next $0\src20__data_o$next[3:0]$10551
end
- attribute \src "libresoc.v:175530.3-175559.6"
- process $proc$libresoc.v:175530$10650
+ attribute \src "libresoc.v:173283.3-173312.6"
+ process $proc$libresoc.v:173283$10558
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10651 $1\wr_detect$4[0:0]$10652
- attribute \src "libresoc.v:175531.5-175531.29"
+ assign $0\wr_detect$4[0:0]$10559 $1\wr_detect$4[0:0]$10560
+ attribute \src "libresoc.v:173284.5-173284.29"
switch \initial
- attribute \src "libresoc.v:175531.9-175531.17"
+ attribute \src "libresoc.v:173284.9-173284.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10652 $4\wr_detect$4[0:0]$10655
+ assign $1\wr_detect$4[0:0]$10560 $4\wr_detect$4[0:0]$10563
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10653 1'1
+ assign $2\wr_detect$4[0:0]$10561 1'1
case
- assign $2\wr_detect$4[0:0]$10653 1'0
+ assign $2\wr_detect$4[0:0]$10561 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10654 1'1
+ assign $3\wr_detect$4[0:0]$10562 1'1
case
- assign $3\wr_detect$4[0:0]$10654 $2\wr_detect$4[0:0]$10653
+ assign $3\wr_detect$4[0:0]$10562 $2\wr_detect$4[0:0]$10561
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10655 1'1
+ assign $4\wr_detect$4[0:0]$10563 1'1
case
- assign $4\wr_detect$4[0:0]$10655 $3\wr_detect$4[0:0]$10654
+ assign $4\wr_detect$4[0:0]$10563 $3\wr_detect$4[0:0]$10562
end
case
- assign $1\wr_detect$4[0:0]$10652 1'0
+ assign $1\wr_detect$4[0:0]$10560 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10651
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10559
end
- attribute \src "libresoc.v:175560.3-175599.6"
- process $proc$libresoc.v:175560$10656
+ attribute \src "libresoc.v:173313.3-173352.6"
+ process $proc$libresoc.v:173313$10564
assign { } { }
assign { } { }
assign { } { }
- assign $0\src30__data_o$next[3:0]$10657 $6\src30__data_o$next[3:0]$10663
- attribute \src "libresoc.v:175561.5-175561.29"
+ assign $0\src30__data_o$next[3:0]$10565 $6\src30__data_o$next[3:0]$10571
+ attribute \src "libresoc.v:173314.5-173314.29"
switch \initial
- attribute \src "libresoc.v:175561.9-175561.17"
+ attribute \src "libresoc.v:173314.9-173314.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src30__data_o$next[3:0]$10658 $5\src30__data_o$next[3:0]$10662
+ assign $1\src30__data_o$next[3:0]$10566 $5\src30__data_o$next[3:0]$10570
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src30__data_o$next[3:0]$10659 \dest10__data_i
+ assign $2\src30__data_o$next[3:0]$10567 \dest10__data_i
case
- assign $2\src30__data_o$next[3:0]$10659 4'0000
+ assign $2\src30__data_o$next[3:0]$10567 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src30__data_o$next[3:0]$10660 \dest20__data_i
+ assign $3\src30__data_o$next[3:0]$10568 \dest20__data_i
case
- assign $3\src30__data_o$next[3:0]$10660 $2\src30__data_o$next[3:0]$10659
+ assign $3\src30__data_o$next[3:0]$10568 $2\src30__data_o$next[3:0]$10567
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src30__data_o$next[3:0]$10661 \w0__data_i
+ assign $4\src30__data_o$next[3:0]$10569 \w0__data_i
case
- assign $4\src30__data_o$next[3:0]$10661 $3\src30__data_o$next[3:0]$10660
+ assign $4\src30__data_o$next[3:0]$10569 $3\src30__data_o$next[3:0]$10568
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src30__data_o$next[3:0]$10662 \reg
+ assign $5\src30__data_o$next[3:0]$10570 \reg
case
- assign $5\src30__data_o$next[3:0]$10662 $4\src30__data_o$next[3:0]$10661
+ assign $5\src30__data_o$next[3:0]$10570 $4\src30__data_o$next[3:0]$10569
end
case
- assign $1\src30__data_o$next[3:0]$10658 4'0000
+ assign $1\src30__data_o$next[3:0]$10566 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src30__data_o$next[3:0]$10663 4'0000
+ assign $6\src30__data_o$next[3:0]$10571 4'0000
case
- assign $6\src30__data_o$next[3:0]$10663 $1\src30__data_o$next[3:0]$10658
+ assign $6\src30__data_o$next[3:0]$10571 $1\src30__data_o$next[3:0]$10566
end
sync always
- update \src30__data_o$next $0\src30__data_o$next[3:0]$10657
+ update \src30__data_o$next $0\src30__data_o$next[3:0]$10565
end
- attribute \src "libresoc.v:175600.3-175629.6"
- process $proc$libresoc.v:175600$10664
+ attribute \src "libresoc.v:173353.3-173382.6"
+ process $proc$libresoc.v:173353$10572
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10665 $1\wr_detect$7[0:0]$10666
- attribute \src "libresoc.v:175601.5-175601.29"
+ assign $0\wr_detect$7[0:0]$10573 $1\wr_detect$7[0:0]$10574
+ attribute \src "libresoc.v:173354.5-173354.29"
switch \initial
- attribute \src "libresoc.v:175601.9-175601.17"
+ attribute \src "libresoc.v:173354.9-173354.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10666 $4\wr_detect$7[0:0]$10669
+ assign $1\wr_detect$7[0:0]$10574 $4\wr_detect$7[0:0]$10577
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10667 1'1
+ assign $2\wr_detect$7[0:0]$10575 1'1
case
- assign $2\wr_detect$7[0:0]$10667 1'0
+ assign $2\wr_detect$7[0:0]$10575 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10668 1'1
+ assign $3\wr_detect$7[0:0]$10576 1'1
case
- assign $3\wr_detect$7[0:0]$10668 $2\wr_detect$7[0:0]$10667
+ assign $3\wr_detect$7[0:0]$10576 $2\wr_detect$7[0:0]$10575
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10669 1'1
+ assign $4\wr_detect$7[0:0]$10577 1'1
case
- assign $4\wr_detect$7[0:0]$10669 $3\wr_detect$7[0:0]$10668
+ assign $4\wr_detect$7[0:0]$10577 $3\wr_detect$7[0:0]$10576
end
case
- assign $1\wr_detect$7[0:0]$10666 1'0
+ assign $1\wr_detect$7[0:0]$10574 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10665
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10573
end
- attribute \src "libresoc.v:175630.3-175669.6"
- process $proc$libresoc.v:175630$10670
+ attribute \src "libresoc.v:173383.3-173422.6"
+ process $proc$libresoc.v:173383$10578
assign { } { }
assign { } { }
assign { } { }
- assign $0\r0__data_o$next[3:0]$10671 $6\r0__data_o$next[3:0]$10677
- attribute \src "libresoc.v:175631.5-175631.29"
+ assign $0\r0__data_o$next[3:0]$10579 $6\r0__data_o$next[3:0]$10585
+ attribute \src "libresoc.v:173384.5-173384.29"
switch \initial
- attribute \src "libresoc.v:175631.9-175631.17"
+ attribute \src "libresoc.v:173384.9-173384.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r0__data_o$next[3:0]$10672 $5\r0__data_o$next[3:0]$10676
+ assign $1\r0__data_o$next[3:0]$10580 $5\r0__data_o$next[3:0]$10584
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r0__data_o$next[3:0]$10673 \dest10__data_i
+ assign $2\r0__data_o$next[3:0]$10581 \dest10__data_i
case
- assign $2\r0__data_o$next[3:0]$10673 4'0000
+ assign $2\r0__data_o$next[3:0]$10581 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r0__data_o$next[3:0]$10674 \dest20__data_i
+ assign $3\r0__data_o$next[3:0]$10582 \dest20__data_i
case
- assign $3\r0__data_o$next[3:0]$10674 $2\r0__data_o$next[3:0]$10673
+ assign $3\r0__data_o$next[3:0]$10582 $2\r0__data_o$next[3:0]$10581
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r0__data_o$next[3:0]$10675 \w0__data_i
+ assign $4\r0__data_o$next[3:0]$10583 \w0__data_i
case
- assign $4\r0__data_o$next[3:0]$10675 $3\r0__data_o$next[3:0]$10674
+ assign $4\r0__data_o$next[3:0]$10583 $3\r0__data_o$next[3:0]$10582
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r0__data_o$next[3:0]$10676 \reg
+ assign $5\r0__data_o$next[3:0]$10584 \reg
case
- assign $5\r0__data_o$next[3:0]$10676 $4\r0__data_o$next[3:0]$10675
+ assign $5\r0__data_o$next[3:0]$10584 $4\r0__data_o$next[3:0]$10583
end
case
- assign $1\r0__data_o$next[3:0]$10672 4'0000
+ assign $1\r0__data_o$next[3:0]$10580 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r0__data_o$next[3:0]$10677 4'0000
+ assign $6\r0__data_o$next[3:0]$10585 4'0000
case
- assign $6\r0__data_o$next[3:0]$10677 $1\r0__data_o$next[3:0]$10672
+ assign $6\r0__data_o$next[3:0]$10585 $1\r0__data_o$next[3:0]$10580
end
sync always
- update \r0__data_o$next $0\r0__data_o$next[3:0]$10671
+ update \r0__data_o$next $0\r0__data_o$next[3:0]$10579
end
- attribute \src "libresoc.v:175670.3-175699.6"
- process $proc$libresoc.v:175670$10678
+ attribute \src "libresoc.v:173423.3-173452.6"
+ process $proc$libresoc.v:173423$10586
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10679 $1\wr_detect$10[0:0]$10680
- attribute \src "libresoc.v:175671.5-175671.29"
+ assign $0\wr_detect$10[0:0]$10587 $1\wr_detect$10[0:0]$10588
+ attribute \src "libresoc.v:173424.5-173424.29"
switch \initial
- attribute \src "libresoc.v:175671.9-175671.17"
+ attribute \src "libresoc.v:173424.9-173424.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10680 $4\wr_detect$10[0:0]$10683
+ assign $1\wr_detect$10[0:0]$10588 $4\wr_detect$10[0:0]$10591
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10681 1'1
+ assign $2\wr_detect$10[0:0]$10589 1'1
case
- assign $2\wr_detect$10[0:0]$10681 1'0
+ assign $2\wr_detect$10[0:0]$10589 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10682 1'1
+ assign $3\wr_detect$10[0:0]$10590 1'1
case
- assign $3\wr_detect$10[0:0]$10682 $2\wr_detect$10[0:0]$10681
+ assign $3\wr_detect$10[0:0]$10590 $2\wr_detect$10[0:0]$10589
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10683 1'1
+ assign $4\wr_detect$10[0:0]$10591 1'1
case
- assign $4\wr_detect$10[0:0]$10683 $3\wr_detect$10[0:0]$10682
+ assign $4\wr_detect$10[0:0]$10591 $3\wr_detect$10[0:0]$10590
end
case
- assign $1\wr_detect$10[0:0]$10680 1'0
+ assign $1\wr_detect$10[0:0]$10588 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10679
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10587
end
- attribute \src "libresoc.v:175700.3-175739.6"
- process $proc$libresoc.v:175700$10684
+ attribute \src "libresoc.v:173453.3-173492.6"
+ process $proc$libresoc.v:173453$10592
assign { } { }
assign { } { }
assign { } { }
- assign $0\r20__data_o$next[3:0]$10685 $6\r20__data_o$next[3:0]$10691
- attribute \src "libresoc.v:175701.5-175701.29"
+ assign $0\r20__data_o$next[3:0]$10593 $6\r20__data_o$next[3:0]$10599
+ attribute \src "libresoc.v:173454.5-173454.29"
switch \initial
- attribute \src "libresoc.v:175701.9-175701.17"
+ attribute \src "libresoc.v:173454.9-173454.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r20__data_o$next[3:0]$10686 $5\r20__data_o$next[3:0]$10690
+ assign $1\r20__data_o$next[3:0]$10594 $5\r20__data_o$next[3:0]$10598
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r20__data_o$next[3:0]$10687 \dest10__data_i
+ assign $2\r20__data_o$next[3:0]$10595 \dest10__data_i
case
- assign $2\r20__data_o$next[3:0]$10687 4'0000
+ assign $2\r20__data_o$next[3:0]$10595 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r20__data_o$next[3:0]$10688 \dest20__data_i
+ assign $3\r20__data_o$next[3:0]$10596 \dest20__data_i
case
- assign $3\r20__data_o$next[3:0]$10688 $2\r20__data_o$next[3:0]$10687
+ assign $3\r20__data_o$next[3:0]$10596 $2\r20__data_o$next[3:0]$10595
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r20__data_o$next[3:0]$10689 \w0__data_i
+ assign $4\r20__data_o$next[3:0]$10597 \w0__data_i
case
- assign $4\r20__data_o$next[3:0]$10689 $3\r20__data_o$next[3:0]$10688
+ assign $4\r20__data_o$next[3:0]$10597 $3\r20__data_o$next[3:0]$10596
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r20__data_o$next[3:0]$10690 \reg
+ assign $5\r20__data_o$next[3:0]$10598 \reg
case
- assign $5\r20__data_o$next[3:0]$10690 $4\r20__data_o$next[3:0]$10689
+ assign $5\r20__data_o$next[3:0]$10598 $4\r20__data_o$next[3:0]$10597
end
case
- assign $1\r20__data_o$next[3:0]$10686 4'0000
+ assign $1\r20__data_o$next[3:0]$10594 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r20__data_o$next[3:0]$10691 4'0000
+ assign $6\r20__data_o$next[3:0]$10599 4'0000
case
- assign $6\r20__data_o$next[3:0]$10691 $1\r20__data_o$next[3:0]$10686
+ assign $6\r20__data_o$next[3:0]$10599 $1\r20__data_o$next[3:0]$10594
end
sync always
- update \r20__data_o$next $0\r20__data_o$next[3:0]$10685
+ update \r20__data_o$next $0\r20__data_o$next[3:0]$10593
end
- attribute \src "libresoc.v:175740.3-175769.6"
- process $proc$libresoc.v:175740$10692
+ attribute \src "libresoc.v:173493.3-173522.6"
+ process $proc$libresoc.v:173493$10600
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$10693 $1\wr_detect$13[0:0]$10694
- attribute \src "libresoc.v:175741.5-175741.29"
+ assign $0\wr_detect$13[0:0]$10601 $1\wr_detect$13[0:0]$10602
+ attribute \src "libresoc.v:173494.5-173494.29"
switch \initial
- attribute \src "libresoc.v:175741.9-175741.17"
+ attribute \src "libresoc.v:173494.9-173494.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$10694 $4\wr_detect$13[0:0]$10697
+ assign $1\wr_detect$13[0:0]$10602 $4\wr_detect$13[0:0]$10605
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$10695 1'1
+ assign $2\wr_detect$13[0:0]$10603 1'1
case
- assign $2\wr_detect$13[0:0]$10695 1'0
+ assign $2\wr_detect$13[0:0]$10603 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$10696 1'1
+ assign $3\wr_detect$13[0:0]$10604 1'1
case
- assign $3\wr_detect$13[0:0]$10696 $2\wr_detect$13[0:0]$10695
+ assign $3\wr_detect$13[0:0]$10604 $2\wr_detect$13[0:0]$10603
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$10697 1'1
+ assign $4\wr_detect$13[0:0]$10605 1'1
case
- assign $4\wr_detect$13[0:0]$10697 $3\wr_detect$13[0:0]$10696
+ assign $4\wr_detect$13[0:0]$10605 $3\wr_detect$13[0:0]$10604
end
case
- assign $1\wr_detect$13[0:0]$10694 1'0
+ assign $1\wr_detect$13[0:0]$10602 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$10693
+ update \wr_detect$13 $0\wr_detect$13[0:0]$10601
end
- connect \$9 $not$libresoc.v:175376$10616_Y
- connect \$12 $not$libresoc.v:175377$10617_Y
- connect \$1 $not$libresoc.v:175378$10618_Y
- connect \$3 $not$libresoc.v:175379$10619_Y
- connect \$6 $not$libresoc.v:175380$10620_Y
+ connect \$9 $not$libresoc.v:173129$10524_Y
+ connect \$12 $not$libresoc.v:173130$10525_Y
+ connect \$1 $not$libresoc.v:173131$10526_Y
+ connect \$3 $not$libresoc.v:173132$10527_Y
+ connect \$6 $not$libresoc.v:173133$10528_Y
end
-attribute \src "libresoc.v:175774.1-176219.10"
+attribute \src "libresoc.v:173527.1-173972.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0"
attribute \generator "nMigen"
module \reg_0$132
- attribute \src "libresoc.v:175775.7-175775.20"
+ attribute \src "libresoc.v:173528.7-173528.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $0\r0__data_o$next[1:0]$10757
- attribute \src "libresoc.v:175850.3-175851.37"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $0\r0__data_o$next[1:0]$10665
+ attribute \src "libresoc.v:173603.3-173604.37"
wire width 2 $0\r0__data_o[1:0]
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $0\reg$next[1:0]$10773
- attribute \src "libresoc.v:175848.3-175849.25"
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $0\reg$next[1:0]$10681
+ attribute \src "libresoc.v:173601.3-173602.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $0\src10__data_o$next[1:0]$10715
- attribute \src "libresoc.v:175856.3-175857.43"
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $0\src10__data_o$next[1:0]$10623
+ attribute \src "libresoc.v:173609.3-173610.43"
wire width 2 $0\src10__data_o[1:0]
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $0\src20__data_o$next[1:0]$10725
- attribute \src "libresoc.v:175854.3-175855.43"
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $0\src20__data_o$next[1:0]$10633
+ attribute \src "libresoc.v:173607.3-173608.43"
wire width 2 $0\src20__data_o[1:0]
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $0\src30__data_o$next[1:0]$10741
- attribute \src "libresoc.v:175852.3-175853.43"
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $0\src30__data_o$next[1:0]$10649
+ attribute \src "libresoc.v:173605.3-173606.43"
wire width 2 $0\src30__data_o[1:0]
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $0\wr_detect$10[0:0]$10766
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $0\wr_detect$4[0:0]$10734
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $0\wr_detect$7[0:0]$10750
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $0\wr_detect$10[0:0]$10674
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $0\wr_detect$4[0:0]$10642
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $0\wr_detect$7[0:0]$10658
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $1\r0__data_o$next[1:0]$10758
- attribute \src "libresoc.v:175802.13-175802.30"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $1\r0__data_o$next[1:0]$10666
+ attribute \src "libresoc.v:173555.13-173555.30"
wire width 2 $1\r0__data_o[1:0]
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $1\reg$next[1:0]$10774
- attribute \src "libresoc.v:175808.13-175808.25"
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $1\reg$next[1:0]$10682
+ attribute \src "libresoc.v:173561.13-173561.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $1\src10__data_o$next[1:0]$10716
- attribute \src "libresoc.v:175813.13-175813.33"
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $1\src10__data_o$next[1:0]$10624
+ attribute \src "libresoc.v:173566.13-173566.33"
wire width 2 $1\src10__data_o[1:0]
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $1\src20__data_o$next[1:0]$10726
- attribute \src "libresoc.v:175820.13-175820.33"
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $1\src20__data_o$next[1:0]$10634
+ attribute \src "libresoc.v:173573.13-173573.33"
wire width 2 $1\src20__data_o[1:0]
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $1\src30__data_o$next[1:0]$10742
- attribute \src "libresoc.v:175827.13-175827.33"
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $1\src30__data_o$next[1:0]$10650
+ attribute \src "libresoc.v:173580.13-173580.33"
wire width 2 $1\src30__data_o[1:0]
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $1\wr_detect$10[0:0]$10767
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $1\wr_detect$4[0:0]$10735
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $1\wr_detect$7[0:0]$10751
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $1\wr_detect$10[0:0]$10675
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $1\wr_detect$4[0:0]$10643
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $1\wr_detect$7[0:0]$10659
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $2\r0__data_o$next[1:0]$10759
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $2\reg$next[1:0]$10775
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $2\src10__data_o$next[1:0]$10717
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $2\src20__data_o$next[1:0]$10727
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $2\src30__data_o$next[1:0]$10743
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $2\wr_detect$10[0:0]$10768
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $2\wr_detect$4[0:0]$10736
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $2\wr_detect$7[0:0]$10752
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $2\r0__data_o$next[1:0]$10667
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $2\reg$next[1:0]$10683
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $2\src10__data_o$next[1:0]$10625
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $2\src20__data_o$next[1:0]$10635
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $2\src30__data_o$next[1:0]$10651
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $2\wr_detect$10[0:0]$10676
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $2\wr_detect$4[0:0]$10644
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $2\wr_detect$7[0:0]$10660
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $3\r0__data_o$next[1:0]$10760
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $3\reg$next[1:0]$10776
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $3\src10__data_o$next[1:0]$10718
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $3\src20__data_o$next[1:0]$10728
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $3\src30__data_o$next[1:0]$10744
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $3\wr_detect$10[0:0]$10769
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $3\wr_detect$4[0:0]$10737
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $3\wr_detect$7[0:0]$10753
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $3\r0__data_o$next[1:0]$10668
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $3\reg$next[1:0]$10684
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $3\src10__data_o$next[1:0]$10626
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $3\src20__data_o$next[1:0]$10636
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $3\src30__data_o$next[1:0]$10652
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $3\wr_detect$10[0:0]$10677
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $3\wr_detect$4[0:0]$10645
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $3\wr_detect$7[0:0]$10661
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $4\r0__data_o$next[1:0]$10761
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $4\reg$next[1:0]$10777
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $4\src10__data_o$next[1:0]$10719
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $4\src20__data_o$next[1:0]$10729
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $4\src30__data_o$next[1:0]$10745
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $4\wr_detect$10[0:0]$10770
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $4\wr_detect$4[0:0]$10738
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $4\wr_detect$7[0:0]$10754
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $4\r0__data_o$next[1:0]$10669
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $4\reg$next[1:0]$10685
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $4\src10__data_o$next[1:0]$10627
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $4\src20__data_o$next[1:0]$10637
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $4\src30__data_o$next[1:0]$10653
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $4\wr_detect$10[0:0]$10678
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $4\wr_detect$4[0:0]$10646
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $4\wr_detect$7[0:0]$10662
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $5\r0__data_o$next[1:0]$10762
- attribute \src "libresoc.v:176186.3-176218.6"
- wire width 2 $5\reg$next[1:0]$10778
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $5\src10__data_o$next[1:0]$10720
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $5\src20__data_o$next[1:0]$10730
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $5\src30__data_o$next[1:0]$10746
- attribute \src "libresoc.v:176150.3-176185.6"
- wire $5\wr_detect$10[0:0]$10771
- attribute \src "libresoc.v:175986.3-176021.6"
- wire $5\wr_detect$4[0:0]$10739
- attribute \src "libresoc.v:176068.3-176103.6"
- wire $5\wr_detect$7[0:0]$10755
- attribute \src "libresoc.v:175904.3-175939.6"
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $5\r0__data_o$next[1:0]$10670
+ attribute \src "libresoc.v:173939.3-173971.6"
+ wire width 2 $5\reg$next[1:0]$10686
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $5\src10__data_o$next[1:0]$10628
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $5\src20__data_o$next[1:0]$10638
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $5\src30__data_o$next[1:0]$10654
+ attribute \src "libresoc.v:173903.3-173938.6"
+ wire $5\wr_detect$10[0:0]$10679
+ attribute \src "libresoc.v:173739.3-173774.6"
+ wire $5\wr_detect$4[0:0]$10647
+ attribute \src "libresoc.v:173821.3-173856.6"
+ wire $5\wr_detect$7[0:0]$10663
+ attribute \src "libresoc.v:173657.3-173692.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $6\r0__data_o$next[1:0]$10763
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $6\src10__data_o$next[1:0]$10721
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $6\src20__data_o$next[1:0]$10731
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $6\src30__data_o$next[1:0]$10747
- attribute \src "libresoc.v:176104.3-176149.6"
- wire width 2 $7\r0__data_o$next[1:0]$10764
- attribute \src "libresoc.v:175858.3-175903.6"
- wire width 2 $7\src10__data_o$next[1:0]$10722
- attribute \src "libresoc.v:175940.3-175985.6"
- wire width 2 $7\src20__data_o$next[1:0]$10732
- attribute \src "libresoc.v:176022.3-176067.6"
- wire width 2 $7\src30__data_o$next[1:0]$10748
- attribute \src "libresoc.v:175844.17-175844.104"
- wire $not$libresoc.v:175844$10705_Y
- attribute \src "libresoc.v:175845.17-175845.100"
- wire $not$libresoc.v:175845$10706_Y
- attribute \src "libresoc.v:175846.17-175846.103"
- wire $not$libresoc.v:175846$10707_Y
- attribute \src "libresoc.v:175847.17-175847.103"
- wire $not$libresoc.v:175847$10708_Y
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $6\r0__data_o$next[1:0]$10671
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $6\src10__data_o$next[1:0]$10629
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $6\src20__data_o$next[1:0]$10639
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $6\src30__data_o$next[1:0]$10655
+ attribute \src "libresoc.v:173857.3-173902.6"
+ wire width 2 $7\r0__data_o$next[1:0]$10672
+ attribute \src "libresoc.v:173611.3-173656.6"
+ wire width 2 $7\src10__data_o$next[1:0]$10630
+ attribute \src "libresoc.v:173693.3-173738.6"
+ wire width 2 $7\src20__data_o$next[1:0]$10640
+ attribute \src "libresoc.v:173775.3-173820.6"
+ wire width 2 $7\src30__data_o$next[1:0]$10656
+ attribute \src "libresoc.v:173597.17-173597.104"
+ wire $not$libresoc.v:173597$10613_Y
+ attribute \src "libresoc.v:173598.17-173598.100"
+ wire $not$libresoc.v:173598$10614_Y
+ attribute \src "libresoc.v:173599.17-173599.103"
+ wire $not$libresoc.v:173599$10615_Y
+ attribute \src "libresoc.v:173600.17-173600.103"
+ wire $not$libresoc.v:173600$10616_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest10__data_i
wire width 2 input 13 \dest30__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest30__wen
- attribute \src "libresoc.v:175775.7-175775.15"
+ attribute \src "libresoc.v:173528.7-173528.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r0__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175844$10705
+ cell $not $not$libresoc.v:173597$10613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:175844$10705_Y
+ connect \Y $not$libresoc.v:173597$10613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175845$10706
+ cell $not $not$libresoc.v:173598$10614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:175845$10706_Y
+ connect \Y $not$libresoc.v:173598$10614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175846$10707
+ cell $not $not$libresoc.v:173599$10615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:175846$10707_Y
+ connect \Y $not$libresoc.v:173599$10615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:175847$10708
+ cell $not $not$libresoc.v:173600$10616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:175847$10708_Y
+ connect \Y $not$libresoc.v:173600$10616_Y
end
- attribute \src "libresoc.v:175775.7-175775.20"
- process $proc$libresoc.v:175775$10779
+ attribute \src "libresoc.v:173528.7-173528.20"
+ process $proc$libresoc.v:173528$10687
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:175802.13-175802.30"
- process $proc$libresoc.v:175802$10780
+ attribute \src "libresoc.v:173555.13-173555.30"
+ process $proc$libresoc.v:173555$10688
assign { } { }
assign $1\r0__data_o[1:0] 2'00
sync always
sync init
update \r0__data_o $1\r0__data_o[1:0]
end
- attribute \src "libresoc.v:175808.13-175808.25"
- process $proc$libresoc.v:175808$10781
+ attribute \src "libresoc.v:173561.13-173561.25"
+ process $proc$libresoc.v:173561$10689
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:175813.13-175813.33"
- process $proc$libresoc.v:175813$10782
+ attribute \src "libresoc.v:173566.13-173566.33"
+ process $proc$libresoc.v:173566$10690
assign { } { }
assign $1\src10__data_o[1:0] 2'00
sync always
sync init
update \src10__data_o $1\src10__data_o[1:0]
end
- attribute \src "libresoc.v:175820.13-175820.33"
- process $proc$libresoc.v:175820$10783
+ attribute \src "libresoc.v:173573.13-173573.33"
+ process $proc$libresoc.v:173573$10691
assign { } { }
assign $1\src20__data_o[1:0] 2'00
sync always
sync init
update \src20__data_o $1\src20__data_o[1:0]
end
- attribute \src "libresoc.v:175827.13-175827.33"
- process $proc$libresoc.v:175827$10784
+ attribute \src "libresoc.v:173580.13-173580.33"
+ process $proc$libresoc.v:173580$10692
assign { } { }
assign $1\src30__data_o[1:0] 2'00
sync always
sync init
update \src30__data_o $1\src30__data_o[1:0]
end
- attribute \src "libresoc.v:175848.3-175849.25"
- process $proc$libresoc.v:175848$10709
+ attribute \src "libresoc.v:173601.3-173602.25"
+ process $proc$libresoc.v:173601$10617
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:175850.3-175851.37"
- process $proc$libresoc.v:175850$10710
+ attribute \src "libresoc.v:173603.3-173604.37"
+ process $proc$libresoc.v:173603$10618
assign { } { }
assign $0\r0__data_o[1:0] \r0__data_o$next
sync posedge \coresync_clk
update \r0__data_o $0\r0__data_o[1:0]
end
- attribute \src "libresoc.v:175852.3-175853.43"
- process $proc$libresoc.v:175852$10711
+ attribute \src "libresoc.v:173605.3-173606.43"
+ process $proc$libresoc.v:173605$10619
assign { } { }
assign $0\src30__data_o[1:0] \src30__data_o$next
sync posedge \coresync_clk
update \src30__data_o $0\src30__data_o[1:0]
end
- attribute \src "libresoc.v:175854.3-175855.43"
- process $proc$libresoc.v:175854$10712
+ attribute \src "libresoc.v:173607.3-173608.43"
+ process $proc$libresoc.v:173607$10620
assign { } { }
assign $0\src20__data_o[1:0] \src20__data_o$next
sync posedge \coresync_clk
update \src20__data_o $0\src20__data_o[1:0]
end
- attribute \src "libresoc.v:175856.3-175857.43"
- process $proc$libresoc.v:175856$10713
+ attribute \src "libresoc.v:173609.3-173610.43"
+ process $proc$libresoc.v:173609$10621
assign { } { }
assign $0\src10__data_o[1:0] \src10__data_o$next
sync posedge \coresync_clk
update \src10__data_o $0\src10__data_o[1:0]
end
- attribute \src "libresoc.v:175858.3-175903.6"
- process $proc$libresoc.v:175858$10714
+ attribute \src "libresoc.v:173611.3-173656.6"
+ process $proc$libresoc.v:173611$10622
assign { } { }
assign { } { }
assign { } { }
- assign $0\src10__data_o$next[1:0]$10715 $7\src10__data_o$next[1:0]$10722
- attribute \src "libresoc.v:175859.5-175859.29"
+ assign $0\src10__data_o$next[1:0]$10623 $7\src10__data_o$next[1:0]$10630
+ attribute \src "libresoc.v:173612.5-173612.29"
switch \initial
- attribute \src "libresoc.v:175859.9-175859.17"
+ attribute \src "libresoc.v:173612.9-173612.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src10__data_o$next[1:0]$10716 $6\src10__data_o$next[1:0]$10721
+ assign $1\src10__data_o$next[1:0]$10624 $6\src10__data_o$next[1:0]$10629
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src10__data_o$next[1:0]$10717 \dest10__data_i
+ assign $2\src10__data_o$next[1:0]$10625 \dest10__data_i
case
- assign $2\src10__data_o$next[1:0]$10717 2'00
+ assign $2\src10__data_o$next[1:0]$10625 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src10__data_o$next[1:0]$10718 \dest20__data_i
+ assign $3\src10__data_o$next[1:0]$10626 \dest20__data_i
case
- assign $3\src10__data_o$next[1:0]$10718 $2\src10__data_o$next[1:0]$10717
+ assign $3\src10__data_o$next[1:0]$10626 $2\src10__data_o$next[1:0]$10625
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src10__data_o$next[1:0]$10719 \dest30__data_i
+ assign $4\src10__data_o$next[1:0]$10627 \dest30__data_i
case
- assign $4\src10__data_o$next[1:0]$10719 $3\src10__data_o$next[1:0]$10718
+ assign $4\src10__data_o$next[1:0]$10627 $3\src10__data_o$next[1:0]$10626
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src10__data_o$next[1:0]$10720 \w0__data_i
+ assign $5\src10__data_o$next[1:0]$10628 \w0__data_i
case
- assign $5\src10__data_o$next[1:0]$10720 $4\src10__data_o$next[1:0]$10719
+ assign $5\src10__data_o$next[1:0]$10628 $4\src10__data_o$next[1:0]$10627
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src10__data_o$next[1:0]$10721 \reg
+ assign $6\src10__data_o$next[1:0]$10629 \reg
case
- assign $6\src10__data_o$next[1:0]$10721 $5\src10__data_o$next[1:0]$10720
+ assign $6\src10__data_o$next[1:0]$10629 $5\src10__data_o$next[1:0]$10628
end
case
- assign $1\src10__data_o$next[1:0]$10716 2'00
+ assign $1\src10__data_o$next[1:0]$10624 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src10__data_o$next[1:0]$10722 2'00
+ assign $7\src10__data_o$next[1:0]$10630 2'00
case
- assign $7\src10__data_o$next[1:0]$10722 $1\src10__data_o$next[1:0]$10716
+ assign $7\src10__data_o$next[1:0]$10630 $1\src10__data_o$next[1:0]$10624
end
sync always
- update \src10__data_o$next $0\src10__data_o$next[1:0]$10715
+ update \src10__data_o$next $0\src10__data_o$next[1:0]$10623
end
- attribute \src "libresoc.v:175904.3-175939.6"
- process $proc$libresoc.v:175904$10723
+ attribute \src "libresoc.v:173657.3-173692.6"
+ process $proc$libresoc.v:173657$10631
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:175905.5-175905.29"
+ attribute \src "libresoc.v:173658.5-173658.29"
switch \initial
- attribute \src "libresoc.v:175905.9-175905.17"
+ attribute \src "libresoc.v:173658.9-173658.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:175940.3-175985.6"
- process $proc$libresoc.v:175940$10724
+ attribute \src "libresoc.v:173693.3-173738.6"
+ process $proc$libresoc.v:173693$10632
assign { } { }
assign { } { }
assign { } { }
- assign $0\src20__data_o$next[1:0]$10725 $7\src20__data_o$next[1:0]$10732
- attribute \src "libresoc.v:175941.5-175941.29"
+ assign $0\src20__data_o$next[1:0]$10633 $7\src20__data_o$next[1:0]$10640
+ attribute \src "libresoc.v:173694.5-173694.29"
switch \initial
- attribute \src "libresoc.v:175941.9-175941.17"
+ attribute \src "libresoc.v:173694.9-173694.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src20__data_o$next[1:0]$10726 $6\src20__data_o$next[1:0]$10731
+ assign $1\src20__data_o$next[1:0]$10634 $6\src20__data_o$next[1:0]$10639
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src20__data_o$next[1:0]$10727 \dest10__data_i
+ assign $2\src20__data_o$next[1:0]$10635 \dest10__data_i
case
- assign $2\src20__data_o$next[1:0]$10727 2'00
+ assign $2\src20__data_o$next[1:0]$10635 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src20__data_o$next[1:0]$10728 \dest20__data_i
+ assign $3\src20__data_o$next[1:0]$10636 \dest20__data_i
case
- assign $3\src20__data_o$next[1:0]$10728 $2\src20__data_o$next[1:0]$10727
+ assign $3\src20__data_o$next[1:0]$10636 $2\src20__data_o$next[1:0]$10635
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src20__data_o$next[1:0]$10729 \dest30__data_i
+ assign $4\src20__data_o$next[1:0]$10637 \dest30__data_i
case
- assign $4\src20__data_o$next[1:0]$10729 $3\src20__data_o$next[1:0]$10728
+ assign $4\src20__data_o$next[1:0]$10637 $3\src20__data_o$next[1:0]$10636
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src20__data_o$next[1:0]$10730 \w0__data_i
+ assign $5\src20__data_o$next[1:0]$10638 \w0__data_i
case
- assign $5\src20__data_o$next[1:0]$10730 $4\src20__data_o$next[1:0]$10729
+ assign $5\src20__data_o$next[1:0]$10638 $4\src20__data_o$next[1:0]$10637
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src20__data_o$next[1:0]$10731 \reg
+ assign $6\src20__data_o$next[1:0]$10639 \reg
case
- assign $6\src20__data_o$next[1:0]$10731 $5\src20__data_o$next[1:0]$10730
+ assign $6\src20__data_o$next[1:0]$10639 $5\src20__data_o$next[1:0]$10638
end
case
- assign $1\src20__data_o$next[1:0]$10726 2'00
+ assign $1\src20__data_o$next[1:0]$10634 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src20__data_o$next[1:0]$10732 2'00
+ assign $7\src20__data_o$next[1:0]$10640 2'00
case
- assign $7\src20__data_o$next[1:0]$10732 $1\src20__data_o$next[1:0]$10726
+ assign $7\src20__data_o$next[1:0]$10640 $1\src20__data_o$next[1:0]$10634
end
sync always
- update \src20__data_o$next $0\src20__data_o$next[1:0]$10725
+ update \src20__data_o$next $0\src20__data_o$next[1:0]$10633
end
- attribute \src "libresoc.v:175986.3-176021.6"
- process $proc$libresoc.v:175986$10733
+ attribute \src "libresoc.v:173739.3-173774.6"
+ process $proc$libresoc.v:173739$10641
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10734 $1\wr_detect$4[0:0]$10735
- attribute \src "libresoc.v:175987.5-175987.29"
+ assign $0\wr_detect$4[0:0]$10642 $1\wr_detect$4[0:0]$10643
+ attribute \src "libresoc.v:173740.5-173740.29"
switch \initial
- attribute \src "libresoc.v:175987.9-175987.17"
+ attribute \src "libresoc.v:173740.9-173740.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10735 $5\wr_detect$4[0:0]$10739
+ assign $1\wr_detect$4[0:0]$10643 $5\wr_detect$4[0:0]$10647
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10736 1'1
+ assign $2\wr_detect$4[0:0]$10644 1'1
case
- assign $2\wr_detect$4[0:0]$10736 1'0
+ assign $2\wr_detect$4[0:0]$10644 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10737 1'1
+ assign $3\wr_detect$4[0:0]$10645 1'1
case
- assign $3\wr_detect$4[0:0]$10737 $2\wr_detect$4[0:0]$10736
+ assign $3\wr_detect$4[0:0]$10645 $2\wr_detect$4[0:0]$10644
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10738 1'1
+ assign $4\wr_detect$4[0:0]$10646 1'1
case
- assign $4\wr_detect$4[0:0]$10738 $3\wr_detect$4[0:0]$10737
+ assign $4\wr_detect$4[0:0]$10646 $3\wr_detect$4[0:0]$10645
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10739 1'1
+ assign $5\wr_detect$4[0:0]$10647 1'1
case
- assign $5\wr_detect$4[0:0]$10739 $4\wr_detect$4[0:0]$10738
+ assign $5\wr_detect$4[0:0]$10647 $4\wr_detect$4[0:0]$10646
end
case
- assign $1\wr_detect$4[0:0]$10735 1'0
+ assign $1\wr_detect$4[0:0]$10643 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10734
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10642
end
- attribute \src "libresoc.v:176022.3-176067.6"
- process $proc$libresoc.v:176022$10740
+ attribute \src "libresoc.v:173775.3-173820.6"
+ process $proc$libresoc.v:173775$10648
assign { } { }
assign { } { }
assign { } { }
- assign $0\src30__data_o$next[1:0]$10741 $7\src30__data_o$next[1:0]$10748
- attribute \src "libresoc.v:176023.5-176023.29"
+ assign $0\src30__data_o$next[1:0]$10649 $7\src30__data_o$next[1:0]$10656
+ attribute \src "libresoc.v:173776.5-173776.29"
switch \initial
- attribute \src "libresoc.v:176023.9-176023.17"
+ attribute \src "libresoc.v:173776.9-173776.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src30__data_o$next[1:0]$10742 $6\src30__data_o$next[1:0]$10747
+ assign $1\src30__data_o$next[1:0]$10650 $6\src30__data_o$next[1:0]$10655
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src30__data_o$next[1:0]$10743 \dest10__data_i
+ assign $2\src30__data_o$next[1:0]$10651 \dest10__data_i
case
- assign $2\src30__data_o$next[1:0]$10743 2'00
+ assign $2\src30__data_o$next[1:0]$10651 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src30__data_o$next[1:0]$10744 \dest20__data_i
+ assign $3\src30__data_o$next[1:0]$10652 \dest20__data_i
case
- assign $3\src30__data_o$next[1:0]$10744 $2\src30__data_o$next[1:0]$10743
+ assign $3\src30__data_o$next[1:0]$10652 $2\src30__data_o$next[1:0]$10651
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src30__data_o$next[1:0]$10745 \dest30__data_i
+ assign $4\src30__data_o$next[1:0]$10653 \dest30__data_i
case
- assign $4\src30__data_o$next[1:0]$10745 $3\src30__data_o$next[1:0]$10744
+ assign $4\src30__data_o$next[1:0]$10653 $3\src30__data_o$next[1:0]$10652
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src30__data_o$next[1:0]$10746 \w0__data_i
+ assign $5\src30__data_o$next[1:0]$10654 \w0__data_i
case
- assign $5\src30__data_o$next[1:0]$10746 $4\src30__data_o$next[1:0]$10745
+ assign $5\src30__data_o$next[1:0]$10654 $4\src30__data_o$next[1:0]$10653
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src30__data_o$next[1:0]$10747 \reg
+ assign $6\src30__data_o$next[1:0]$10655 \reg
case
- assign $6\src30__data_o$next[1:0]$10747 $5\src30__data_o$next[1:0]$10746
+ assign $6\src30__data_o$next[1:0]$10655 $5\src30__data_o$next[1:0]$10654
end
case
- assign $1\src30__data_o$next[1:0]$10742 2'00
+ assign $1\src30__data_o$next[1:0]$10650 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src30__data_o$next[1:0]$10748 2'00
+ assign $7\src30__data_o$next[1:0]$10656 2'00
case
- assign $7\src30__data_o$next[1:0]$10748 $1\src30__data_o$next[1:0]$10742
+ assign $7\src30__data_o$next[1:0]$10656 $1\src30__data_o$next[1:0]$10650
end
sync always
- update \src30__data_o$next $0\src30__data_o$next[1:0]$10741
+ update \src30__data_o$next $0\src30__data_o$next[1:0]$10649
end
- attribute \src "libresoc.v:176068.3-176103.6"
- process $proc$libresoc.v:176068$10749
+ attribute \src "libresoc.v:173821.3-173856.6"
+ process $proc$libresoc.v:173821$10657
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10750 $1\wr_detect$7[0:0]$10751
- attribute \src "libresoc.v:176069.5-176069.29"
+ assign $0\wr_detect$7[0:0]$10658 $1\wr_detect$7[0:0]$10659
+ attribute \src "libresoc.v:173822.5-173822.29"
switch \initial
- attribute \src "libresoc.v:176069.9-176069.17"
+ attribute \src "libresoc.v:173822.9-173822.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10751 $5\wr_detect$7[0:0]$10755
+ assign $1\wr_detect$7[0:0]$10659 $5\wr_detect$7[0:0]$10663
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10752 1'1
+ assign $2\wr_detect$7[0:0]$10660 1'1
case
- assign $2\wr_detect$7[0:0]$10752 1'0
+ assign $2\wr_detect$7[0:0]$10660 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10753 1'1
+ assign $3\wr_detect$7[0:0]$10661 1'1
case
- assign $3\wr_detect$7[0:0]$10753 $2\wr_detect$7[0:0]$10752
+ assign $3\wr_detect$7[0:0]$10661 $2\wr_detect$7[0:0]$10660
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10754 1'1
+ assign $4\wr_detect$7[0:0]$10662 1'1
case
- assign $4\wr_detect$7[0:0]$10754 $3\wr_detect$7[0:0]$10753
+ assign $4\wr_detect$7[0:0]$10662 $3\wr_detect$7[0:0]$10661
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$10755 1'1
+ assign $5\wr_detect$7[0:0]$10663 1'1
case
- assign $5\wr_detect$7[0:0]$10755 $4\wr_detect$7[0:0]$10754
+ assign $5\wr_detect$7[0:0]$10663 $4\wr_detect$7[0:0]$10662
end
case
- assign $1\wr_detect$7[0:0]$10751 1'0
+ assign $1\wr_detect$7[0:0]$10659 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10750
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10658
end
- attribute \src "libresoc.v:176104.3-176149.6"
- process $proc$libresoc.v:176104$10756
+ attribute \src "libresoc.v:173857.3-173902.6"
+ process $proc$libresoc.v:173857$10664
assign { } { }
assign { } { }
assign { } { }
- assign $0\r0__data_o$next[1:0]$10757 $7\r0__data_o$next[1:0]$10764
- attribute \src "libresoc.v:176105.5-176105.29"
+ assign $0\r0__data_o$next[1:0]$10665 $7\r0__data_o$next[1:0]$10672
+ attribute \src "libresoc.v:173858.5-173858.29"
switch \initial
- attribute \src "libresoc.v:176105.9-176105.17"
+ attribute \src "libresoc.v:173858.9-173858.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r0__data_o$next[1:0]$10758 $6\r0__data_o$next[1:0]$10763
+ assign $1\r0__data_o$next[1:0]$10666 $6\r0__data_o$next[1:0]$10671
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r0__data_o$next[1:0]$10759 \dest10__data_i
+ assign $2\r0__data_o$next[1:0]$10667 \dest10__data_i
case
- assign $2\r0__data_o$next[1:0]$10759 2'00
+ assign $2\r0__data_o$next[1:0]$10667 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r0__data_o$next[1:0]$10760 \dest20__data_i
+ assign $3\r0__data_o$next[1:0]$10668 \dest20__data_i
case
- assign $3\r0__data_o$next[1:0]$10760 $2\r0__data_o$next[1:0]$10759
+ assign $3\r0__data_o$next[1:0]$10668 $2\r0__data_o$next[1:0]$10667
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r0__data_o$next[1:0]$10761 \dest30__data_i
+ assign $4\r0__data_o$next[1:0]$10669 \dest30__data_i
case
- assign $4\r0__data_o$next[1:0]$10761 $3\r0__data_o$next[1:0]$10760
+ assign $4\r0__data_o$next[1:0]$10669 $3\r0__data_o$next[1:0]$10668
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r0__data_o$next[1:0]$10762 \w0__data_i
+ assign $5\r0__data_o$next[1:0]$10670 \w0__data_i
case
- assign $5\r0__data_o$next[1:0]$10762 $4\r0__data_o$next[1:0]$10761
+ assign $5\r0__data_o$next[1:0]$10670 $4\r0__data_o$next[1:0]$10669
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r0__data_o$next[1:0]$10763 \reg
+ assign $6\r0__data_o$next[1:0]$10671 \reg
case
- assign $6\r0__data_o$next[1:0]$10763 $5\r0__data_o$next[1:0]$10762
+ assign $6\r0__data_o$next[1:0]$10671 $5\r0__data_o$next[1:0]$10670
end
case
- assign $1\r0__data_o$next[1:0]$10758 2'00
+ assign $1\r0__data_o$next[1:0]$10666 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r0__data_o$next[1:0]$10764 2'00
+ assign $7\r0__data_o$next[1:0]$10672 2'00
case
- assign $7\r0__data_o$next[1:0]$10764 $1\r0__data_o$next[1:0]$10758
+ assign $7\r0__data_o$next[1:0]$10672 $1\r0__data_o$next[1:0]$10666
end
sync always
- update \r0__data_o$next $0\r0__data_o$next[1:0]$10757
+ update \r0__data_o$next $0\r0__data_o$next[1:0]$10665
end
- attribute \src "libresoc.v:176150.3-176185.6"
- process $proc$libresoc.v:176150$10765
+ attribute \src "libresoc.v:173903.3-173938.6"
+ process $proc$libresoc.v:173903$10673
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10766 $1\wr_detect$10[0:0]$10767
- attribute \src "libresoc.v:176151.5-176151.29"
+ assign $0\wr_detect$10[0:0]$10674 $1\wr_detect$10[0:0]$10675
+ attribute \src "libresoc.v:173904.5-173904.29"
switch \initial
- attribute \src "libresoc.v:176151.9-176151.17"
+ attribute \src "libresoc.v:173904.9-173904.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10767 $5\wr_detect$10[0:0]$10771
+ assign $1\wr_detect$10[0:0]$10675 $5\wr_detect$10[0:0]$10679
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10768 1'1
+ assign $2\wr_detect$10[0:0]$10676 1'1
case
- assign $2\wr_detect$10[0:0]$10768 1'0
+ assign $2\wr_detect$10[0:0]$10676 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10769 1'1
+ assign $3\wr_detect$10[0:0]$10677 1'1
case
- assign $3\wr_detect$10[0:0]$10769 $2\wr_detect$10[0:0]$10768
+ assign $3\wr_detect$10[0:0]$10677 $2\wr_detect$10[0:0]$10676
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10770 1'1
+ assign $4\wr_detect$10[0:0]$10678 1'1
case
- assign $4\wr_detect$10[0:0]$10770 $3\wr_detect$10[0:0]$10769
+ assign $4\wr_detect$10[0:0]$10678 $3\wr_detect$10[0:0]$10677
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$10771 1'1
+ assign $5\wr_detect$10[0:0]$10679 1'1
case
- assign $5\wr_detect$10[0:0]$10771 $4\wr_detect$10[0:0]$10770
+ assign $5\wr_detect$10[0:0]$10679 $4\wr_detect$10[0:0]$10678
end
case
- assign $1\wr_detect$10[0:0]$10767 1'0
+ assign $1\wr_detect$10[0:0]$10675 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10766
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10674
end
- attribute \src "libresoc.v:176186.3-176218.6"
- process $proc$libresoc.v:176186$10772
+ attribute \src "libresoc.v:173939.3-173971.6"
+ process $proc$libresoc.v:173939$10680
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$10773 $5\reg$next[1:0]$10778
- attribute \src "libresoc.v:176187.5-176187.29"
+ assign $0\reg$next[1:0]$10681 $5\reg$next[1:0]$10686
+ attribute \src "libresoc.v:173940.5-173940.29"
switch \initial
- attribute \src "libresoc.v:176187.9-176187.17"
+ attribute \src "libresoc.v:173940.9-173940.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$10774 \dest10__data_i
+ assign $1\reg$next[1:0]$10682 \dest10__data_i
case
- assign $1\reg$next[1:0]$10774 \reg
+ assign $1\reg$next[1:0]$10682 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest20__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$10775 \dest20__data_i
+ assign $2\reg$next[1:0]$10683 \dest20__data_i
case
- assign $2\reg$next[1:0]$10775 $1\reg$next[1:0]$10774
+ assign $2\reg$next[1:0]$10683 $1\reg$next[1:0]$10682
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest30__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$10776 \dest30__data_i
+ assign $3\reg$next[1:0]$10684 \dest30__data_i
case
- assign $3\reg$next[1:0]$10776 $2\reg$next[1:0]$10775
+ assign $3\reg$next[1:0]$10684 $2\reg$next[1:0]$10683
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$10777 \w0__data_i
+ assign $4\reg$next[1:0]$10685 \w0__data_i
case
- assign $4\reg$next[1:0]$10777 $3\reg$next[1:0]$10776
+ assign $4\reg$next[1:0]$10685 $3\reg$next[1:0]$10684
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$10778 2'00
+ assign $5\reg$next[1:0]$10686 2'00
case
- assign $5\reg$next[1:0]$10778 $4\reg$next[1:0]$10777
+ assign $5\reg$next[1:0]$10686 $4\reg$next[1:0]$10685
end
sync always
- update \reg$next $0\reg$next[1:0]$10773
+ update \reg$next $0\reg$next[1:0]$10681
end
- connect \$9 $not$libresoc.v:175844$10705_Y
- connect \$1 $not$libresoc.v:175845$10706_Y
- connect \$3 $not$libresoc.v:175846$10707_Y
- connect \$6 $not$libresoc.v:175847$10708_Y
+ connect \$9 $not$libresoc.v:173597$10613_Y
+ connect \$1 $not$libresoc.v:173598$10614_Y
+ connect \$3 $not$libresoc.v:173599$10615_Y
+ connect \$6 $not$libresoc.v:173600$10616_Y
end
-attribute \src "libresoc.v:176223.1-176572.10"
+attribute \src "libresoc.v:173976.1-174325.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0"
attribute \generator "nMigen"
module \reg_0$135
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $0\cia0__data_o$next[63:0]$10793
- attribute \src "libresoc.v:176291.3-176292.41"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $0\cia0__data_o$next[63:0]$10701
+ attribute \src "libresoc.v:174044.3-174045.41"
wire width 64 $0\cia0__data_o[63:0]
- attribute \src "libresoc.v:176224.7-176224.20"
+ attribute \src "libresoc.v:173977.7-173977.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $0\msr0__data_o$next[63:0]$10803
- attribute \src "libresoc.v:176289.3-176290.41"
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $0\msr0__data_o$next[63:0]$10711
+ attribute \src "libresoc.v:174042.3-174043.41"
wire width 64 $0\msr0__data_o[63:0]
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $0\reg$next[63:0]$10835
- attribute \src "libresoc.v:176285.3-176286.25"
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $0\reg$next[63:0]$10743
+ attribute \src "libresoc.v:174038.3-174039.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $0\sv0__data_o$next[63:0]$10819
- attribute \src "libresoc.v:176287.3-176288.39"
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $0\sv0__data_o$next[63:0]$10727
+ attribute \src "libresoc.v:174040.3-174041.39"
wire width 64 $0\sv0__data_o[63:0]
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $0\wr_detect$4[0:0]$10812
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $0\wr_detect$7[0:0]$10828
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $0\wr_detect$4[0:0]$10720
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $0\wr_detect$7[0:0]$10736
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $1\cia0__data_o$next[63:0]$10794
- attribute \src "libresoc.v:176233.14-176233.49"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $1\cia0__data_o$next[63:0]$10702
+ attribute \src "libresoc.v:173986.14-173986.49"
wire width 64 $1\cia0__data_o[63:0]
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $1\msr0__data_o$next[63:0]$10804
- attribute \src "libresoc.v:176250.14-176250.49"
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $1\msr0__data_o$next[63:0]$10712
+ attribute \src "libresoc.v:174003.14-174003.49"
wire width 64 $1\msr0__data_o[63:0]
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $1\reg$next[63:0]$10836
- attribute \src "libresoc.v:176262.14-176262.42"
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $1\reg$next[63:0]$10744
+ attribute \src "libresoc.v:174015.14-174015.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $1\sv0__data_o$next[63:0]$10820
- attribute \src "libresoc.v:176269.14-176269.48"
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $1\sv0__data_o$next[63:0]$10728
+ attribute \src "libresoc.v:174022.14-174022.48"
wire width 64 $1\sv0__data_o[63:0]
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $1\wr_detect$4[0:0]$10813
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $1\wr_detect$7[0:0]$10829
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $1\wr_detect$4[0:0]$10721
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $1\wr_detect$7[0:0]$10737
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $2\cia0__data_o$next[63:0]$10795
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $2\msr0__data_o$next[63:0]$10805
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $2\reg$next[63:0]$10837
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $2\sv0__data_o$next[63:0]$10821
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $2\wr_detect$4[0:0]$10814
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $2\wr_detect$7[0:0]$10830
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $2\cia0__data_o$next[63:0]$10703
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $2\msr0__data_o$next[63:0]$10713
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $2\reg$next[63:0]$10745
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $2\sv0__data_o$next[63:0]$10729
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $2\wr_detect$4[0:0]$10722
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $2\wr_detect$7[0:0]$10738
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $3\cia0__data_o$next[63:0]$10796
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $3\msr0__data_o$next[63:0]$10806
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $3\reg$next[63:0]$10838
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $3\sv0__data_o$next[63:0]$10822
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $3\wr_detect$4[0:0]$10815
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $3\wr_detect$7[0:0]$10831
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $3\cia0__data_o$next[63:0]$10704
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $3\msr0__data_o$next[63:0]$10714
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $3\reg$next[63:0]$10746
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $3\sv0__data_o$next[63:0]$10730
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $3\wr_detect$4[0:0]$10723
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $3\wr_detect$7[0:0]$10739
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $4\cia0__data_o$next[63:0]$10797
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $4\msr0__data_o$next[63:0]$10807
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $4\reg$next[63:0]$10839
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $4\sv0__data_o$next[63:0]$10823
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $4\wr_detect$4[0:0]$10816
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $4\wr_detect$7[0:0]$10832
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $4\cia0__data_o$next[63:0]$10705
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $4\msr0__data_o$next[63:0]$10715
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $4\reg$next[63:0]$10747
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $4\sv0__data_o$next[63:0]$10731
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $4\wr_detect$4[0:0]$10724
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $4\wr_detect$7[0:0]$10740
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $5\cia0__data_o$next[63:0]$10798
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $5\msr0__data_o$next[63:0]$10808
- attribute \src "libresoc.v:176539.3-176571.6"
- wire width 64 $5\reg$next[63:0]$10840
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $5\sv0__data_o$next[63:0]$10824
- attribute \src "libresoc.v:176421.3-176456.6"
- wire $5\wr_detect$4[0:0]$10817
- attribute \src "libresoc.v:176503.3-176538.6"
- wire $5\wr_detect$7[0:0]$10833
- attribute \src "libresoc.v:176339.3-176374.6"
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $5\cia0__data_o$next[63:0]$10706
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $5\msr0__data_o$next[63:0]$10716
+ attribute \src "libresoc.v:174292.3-174324.6"
+ wire width 64 $5\reg$next[63:0]$10748
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $5\sv0__data_o$next[63:0]$10732
+ attribute \src "libresoc.v:174174.3-174209.6"
+ wire $5\wr_detect$4[0:0]$10725
+ attribute \src "libresoc.v:174256.3-174291.6"
+ wire $5\wr_detect$7[0:0]$10741
+ attribute \src "libresoc.v:174092.3-174127.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $6\cia0__data_o$next[63:0]$10799
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $6\msr0__data_o$next[63:0]$10809
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $6\sv0__data_o$next[63:0]$10825
- attribute \src "libresoc.v:176293.3-176338.6"
- wire width 64 $7\cia0__data_o$next[63:0]$10800
- attribute \src "libresoc.v:176375.3-176420.6"
- wire width 64 $7\msr0__data_o$next[63:0]$10810
- attribute \src "libresoc.v:176457.3-176502.6"
- wire width 64 $7\sv0__data_o$next[63:0]$10826
- attribute \src "libresoc.v:176282.17-176282.100"
- wire $not$libresoc.v:176282$10785_Y
- attribute \src "libresoc.v:176283.17-176283.103"
- wire $not$libresoc.v:176283$10786_Y
- attribute \src "libresoc.v:176284.17-176284.103"
- wire $not$libresoc.v:176284$10787_Y
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $6\cia0__data_o$next[63:0]$10707
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $6\msr0__data_o$next[63:0]$10717
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $6\sv0__data_o$next[63:0]$10733
+ attribute \src "libresoc.v:174046.3-174091.6"
+ wire width 64 $7\cia0__data_o$next[63:0]$10708
+ attribute \src "libresoc.v:174128.3-174173.6"
+ wire width 64 $7\msr0__data_o$next[63:0]$10718
+ attribute \src "libresoc.v:174210.3-174255.6"
+ wire width 64 $7\sv0__data_o$next[63:0]$10734
+ attribute \src "libresoc.v:174035.17-174035.100"
+ wire $not$libresoc.v:174035$10693_Y
+ attribute \src "libresoc.v:174036.17-174036.103"
+ wire $not$libresoc.v:174036$10694_Y
+ attribute \src "libresoc.v:174037.17-174037.103"
+ wire $not$libresoc.v:174037$10695_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia0__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia0__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr10__wen
- attribute \src "libresoc.v:176224.7-176224.15"
+ attribute \src "libresoc.v:173977.7-173977.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr0__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176282$10785
+ cell $not $not$libresoc.v:174035$10693
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:176282$10785_Y
+ connect \Y $not$libresoc.v:174035$10693_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176283$10786
+ cell $not $not$libresoc.v:174036$10694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:176283$10786_Y
+ connect \Y $not$libresoc.v:174036$10694_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176284$10787
+ cell $not $not$libresoc.v:174037$10695
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:176284$10787_Y
+ connect \Y $not$libresoc.v:174037$10695_Y
end
- attribute \src "libresoc.v:176224.7-176224.20"
- process $proc$libresoc.v:176224$10841
+ attribute \src "libresoc.v:173977.7-173977.20"
+ process $proc$libresoc.v:173977$10749
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:176233.14-176233.49"
- process $proc$libresoc.v:176233$10842
+ attribute \src "libresoc.v:173986.14-173986.49"
+ process $proc$libresoc.v:173986$10750
assign { } { }
assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia0__data_o $1\cia0__data_o[63:0]
end
- attribute \src "libresoc.v:176250.14-176250.49"
- process $proc$libresoc.v:176250$10843
+ attribute \src "libresoc.v:174003.14-174003.49"
+ process $proc$libresoc.v:174003$10751
assign { } { }
assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr0__data_o $1\msr0__data_o[63:0]
end
- attribute \src "libresoc.v:176262.14-176262.42"
- process $proc$libresoc.v:176262$10844
+ attribute \src "libresoc.v:174015.14-174015.42"
+ process $proc$libresoc.v:174015$10752
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:176269.14-176269.48"
- process $proc$libresoc.v:176269$10845
+ attribute \src "libresoc.v:174022.14-174022.48"
+ process $proc$libresoc.v:174022$10753
assign { } { }
assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv0__data_o $1\sv0__data_o[63:0]
end
- attribute \src "libresoc.v:176285.3-176286.25"
- process $proc$libresoc.v:176285$10788
+ attribute \src "libresoc.v:174038.3-174039.25"
+ process $proc$libresoc.v:174038$10696
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:176287.3-176288.39"
- process $proc$libresoc.v:176287$10789
+ attribute \src "libresoc.v:174040.3-174041.39"
+ process $proc$libresoc.v:174040$10697
assign { } { }
assign $0\sv0__data_o[63:0] \sv0__data_o$next
sync posedge \coresync_clk
update \sv0__data_o $0\sv0__data_o[63:0]
end
- attribute \src "libresoc.v:176289.3-176290.41"
- process $proc$libresoc.v:176289$10790
+ attribute \src "libresoc.v:174042.3-174043.41"
+ process $proc$libresoc.v:174042$10698
assign { } { }
assign $0\msr0__data_o[63:0] \msr0__data_o$next
sync posedge \coresync_clk
update \msr0__data_o $0\msr0__data_o[63:0]
end
- attribute \src "libresoc.v:176291.3-176292.41"
- process $proc$libresoc.v:176291$10791
+ attribute \src "libresoc.v:174044.3-174045.41"
+ process $proc$libresoc.v:174044$10699
assign { } { }
assign $0\cia0__data_o[63:0] \cia0__data_o$next
sync posedge \coresync_clk
update \cia0__data_o $0\cia0__data_o[63:0]
end
- attribute \src "libresoc.v:176293.3-176338.6"
- process $proc$libresoc.v:176293$10792
+ attribute \src "libresoc.v:174046.3-174091.6"
+ process $proc$libresoc.v:174046$10700
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia0__data_o$next[63:0]$10793 $7\cia0__data_o$next[63:0]$10800
- attribute \src "libresoc.v:176294.5-176294.29"
+ assign $0\cia0__data_o$next[63:0]$10701 $7\cia0__data_o$next[63:0]$10708
+ attribute \src "libresoc.v:174047.5-174047.29"
switch \initial
- attribute \src "libresoc.v:176294.9-176294.17"
+ attribute \src "libresoc.v:174047.9-174047.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia0__data_o$next[63:0]$10794 $6\cia0__data_o$next[63:0]$10799
+ assign $1\cia0__data_o$next[63:0]$10702 $6\cia0__data_o$next[63:0]$10707
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia0__data_o$next[63:0]$10795 \nia0__data_i
+ assign $2\cia0__data_o$next[63:0]$10703 \nia0__data_i
case
- assign $2\cia0__data_o$next[63:0]$10795 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia0__data_o$next[63:0]$10703 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia0__data_o$next[63:0]$10796 \msr0__data_i
+ assign $3\cia0__data_o$next[63:0]$10704 \msr0__data_i
case
- assign $3\cia0__data_o$next[63:0]$10796 $2\cia0__data_o$next[63:0]$10795
+ assign $3\cia0__data_o$next[63:0]$10704 $2\cia0__data_o$next[63:0]$10703
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia0__data_o$next[63:0]$10797 \sv0__data_i
+ assign $4\cia0__data_o$next[63:0]$10705 \sv0__data_i
case
- assign $4\cia0__data_o$next[63:0]$10797 $3\cia0__data_o$next[63:0]$10796
+ assign $4\cia0__data_o$next[63:0]$10705 $3\cia0__data_o$next[63:0]$10704
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia0__data_o$next[63:0]$10798 \d_wr10__data_i
+ assign $5\cia0__data_o$next[63:0]$10706 \d_wr10__data_i
case
- assign $5\cia0__data_o$next[63:0]$10798 $4\cia0__data_o$next[63:0]$10797
+ assign $5\cia0__data_o$next[63:0]$10706 $4\cia0__data_o$next[63:0]$10705
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia0__data_o$next[63:0]$10799 \reg
+ assign $6\cia0__data_o$next[63:0]$10707 \reg
case
- assign $6\cia0__data_o$next[63:0]$10799 $5\cia0__data_o$next[63:0]$10798
+ assign $6\cia0__data_o$next[63:0]$10707 $5\cia0__data_o$next[63:0]$10706
end
case
- assign $1\cia0__data_o$next[63:0]$10794 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia0__data_o$next[63:0]$10702 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia0__data_o$next[63:0]$10800 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia0__data_o$next[63:0]$10708 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia0__data_o$next[63:0]$10800 $1\cia0__data_o$next[63:0]$10794
+ assign $7\cia0__data_o$next[63:0]$10708 $1\cia0__data_o$next[63:0]$10702
end
sync always
- update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10793
+ update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10701
end
- attribute \src "libresoc.v:176339.3-176374.6"
- process $proc$libresoc.v:176339$10801
+ attribute \src "libresoc.v:174092.3-174127.6"
+ process $proc$libresoc.v:174092$10709
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:176340.5-176340.29"
+ attribute \src "libresoc.v:174093.5-174093.29"
switch \initial
- attribute \src "libresoc.v:176340.9-176340.17"
+ attribute \src "libresoc.v:174093.9-174093.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:176375.3-176420.6"
- process $proc$libresoc.v:176375$10802
+ attribute \src "libresoc.v:174128.3-174173.6"
+ process $proc$libresoc.v:174128$10710
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr0__data_o$next[63:0]$10803 $7\msr0__data_o$next[63:0]$10810
- attribute \src "libresoc.v:176376.5-176376.29"
+ assign $0\msr0__data_o$next[63:0]$10711 $7\msr0__data_o$next[63:0]$10718
+ attribute \src "libresoc.v:174129.5-174129.29"
switch \initial
- attribute \src "libresoc.v:176376.9-176376.17"
+ attribute \src "libresoc.v:174129.9-174129.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr0__data_o$next[63:0]$10804 $6\msr0__data_o$next[63:0]$10809
+ assign $1\msr0__data_o$next[63:0]$10712 $6\msr0__data_o$next[63:0]$10717
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr0__data_o$next[63:0]$10805 \nia0__data_i
+ assign $2\msr0__data_o$next[63:0]$10713 \nia0__data_i
case
- assign $2\msr0__data_o$next[63:0]$10805 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr0__data_o$next[63:0]$10713 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr0__data_o$next[63:0]$10806 \msr0__data_i
+ assign $3\msr0__data_o$next[63:0]$10714 \msr0__data_i
case
- assign $3\msr0__data_o$next[63:0]$10806 $2\msr0__data_o$next[63:0]$10805
+ assign $3\msr0__data_o$next[63:0]$10714 $2\msr0__data_o$next[63:0]$10713
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr0__data_o$next[63:0]$10807 \sv0__data_i
+ assign $4\msr0__data_o$next[63:0]$10715 \sv0__data_i
case
- assign $4\msr0__data_o$next[63:0]$10807 $3\msr0__data_o$next[63:0]$10806
+ assign $4\msr0__data_o$next[63:0]$10715 $3\msr0__data_o$next[63:0]$10714
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr0__data_o$next[63:0]$10808 \d_wr10__data_i
+ assign $5\msr0__data_o$next[63:0]$10716 \d_wr10__data_i
case
- assign $5\msr0__data_o$next[63:0]$10808 $4\msr0__data_o$next[63:0]$10807
+ assign $5\msr0__data_o$next[63:0]$10716 $4\msr0__data_o$next[63:0]$10715
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr0__data_o$next[63:0]$10809 \reg
+ assign $6\msr0__data_o$next[63:0]$10717 \reg
case
- assign $6\msr0__data_o$next[63:0]$10809 $5\msr0__data_o$next[63:0]$10808
+ assign $6\msr0__data_o$next[63:0]$10717 $5\msr0__data_o$next[63:0]$10716
end
case
- assign $1\msr0__data_o$next[63:0]$10804 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr0__data_o$next[63:0]$10712 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr0__data_o$next[63:0]$10810 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr0__data_o$next[63:0]$10718 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr0__data_o$next[63:0]$10810 $1\msr0__data_o$next[63:0]$10804
+ assign $7\msr0__data_o$next[63:0]$10718 $1\msr0__data_o$next[63:0]$10712
end
sync always
- update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10803
+ update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10711
end
- attribute \src "libresoc.v:176421.3-176456.6"
- process $proc$libresoc.v:176421$10811
+ attribute \src "libresoc.v:174174.3-174209.6"
+ process $proc$libresoc.v:174174$10719
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10812 $1\wr_detect$4[0:0]$10813
- attribute \src "libresoc.v:176422.5-176422.29"
+ assign $0\wr_detect$4[0:0]$10720 $1\wr_detect$4[0:0]$10721
+ attribute \src "libresoc.v:174175.5-174175.29"
switch \initial
- attribute \src "libresoc.v:176422.9-176422.17"
+ attribute \src "libresoc.v:174175.9-174175.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10813 $5\wr_detect$4[0:0]$10817
+ assign $1\wr_detect$4[0:0]$10721 $5\wr_detect$4[0:0]$10725
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10814 1'1
+ assign $2\wr_detect$4[0:0]$10722 1'1
case
- assign $2\wr_detect$4[0:0]$10814 1'0
+ assign $2\wr_detect$4[0:0]$10722 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10815 1'1
+ assign $3\wr_detect$4[0:0]$10723 1'1
case
- assign $3\wr_detect$4[0:0]$10815 $2\wr_detect$4[0:0]$10814
+ assign $3\wr_detect$4[0:0]$10723 $2\wr_detect$4[0:0]$10722
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10816 1'1
+ assign $4\wr_detect$4[0:0]$10724 1'1
case
- assign $4\wr_detect$4[0:0]$10816 $3\wr_detect$4[0:0]$10815
+ assign $4\wr_detect$4[0:0]$10724 $3\wr_detect$4[0:0]$10723
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10817 1'1
+ assign $5\wr_detect$4[0:0]$10725 1'1
case
- assign $5\wr_detect$4[0:0]$10817 $4\wr_detect$4[0:0]$10816
+ assign $5\wr_detect$4[0:0]$10725 $4\wr_detect$4[0:0]$10724
end
case
- assign $1\wr_detect$4[0:0]$10813 1'0
+ assign $1\wr_detect$4[0:0]$10721 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10812
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10720
end
- attribute \src "libresoc.v:176457.3-176502.6"
- process $proc$libresoc.v:176457$10818
+ attribute \src "libresoc.v:174210.3-174255.6"
+ process $proc$libresoc.v:174210$10726
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv0__data_o$next[63:0]$10819 $7\sv0__data_o$next[63:0]$10826
- attribute \src "libresoc.v:176458.5-176458.29"
+ assign $0\sv0__data_o$next[63:0]$10727 $7\sv0__data_o$next[63:0]$10734
+ attribute \src "libresoc.v:174211.5-174211.29"
switch \initial
- attribute \src "libresoc.v:176458.9-176458.17"
+ attribute \src "libresoc.v:174211.9-174211.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv0__data_o$next[63:0]$10820 $6\sv0__data_o$next[63:0]$10825
+ assign $1\sv0__data_o$next[63:0]$10728 $6\sv0__data_o$next[63:0]$10733
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv0__data_o$next[63:0]$10821 \nia0__data_i
+ assign $2\sv0__data_o$next[63:0]$10729 \nia0__data_i
case
- assign $2\sv0__data_o$next[63:0]$10821 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv0__data_o$next[63:0]$10729 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv0__data_o$next[63:0]$10822 \msr0__data_i
+ assign $3\sv0__data_o$next[63:0]$10730 \msr0__data_i
case
- assign $3\sv0__data_o$next[63:0]$10822 $2\sv0__data_o$next[63:0]$10821
+ assign $3\sv0__data_o$next[63:0]$10730 $2\sv0__data_o$next[63:0]$10729
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv0__data_o$next[63:0]$10823 \sv0__data_i
+ assign $4\sv0__data_o$next[63:0]$10731 \sv0__data_i
case
- assign $4\sv0__data_o$next[63:0]$10823 $3\sv0__data_o$next[63:0]$10822
+ assign $4\sv0__data_o$next[63:0]$10731 $3\sv0__data_o$next[63:0]$10730
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv0__data_o$next[63:0]$10824 \d_wr10__data_i
+ assign $5\sv0__data_o$next[63:0]$10732 \d_wr10__data_i
case
- assign $5\sv0__data_o$next[63:0]$10824 $4\sv0__data_o$next[63:0]$10823
+ assign $5\sv0__data_o$next[63:0]$10732 $4\sv0__data_o$next[63:0]$10731
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv0__data_o$next[63:0]$10825 \reg
+ assign $6\sv0__data_o$next[63:0]$10733 \reg
case
- assign $6\sv0__data_o$next[63:0]$10825 $5\sv0__data_o$next[63:0]$10824
+ assign $6\sv0__data_o$next[63:0]$10733 $5\sv0__data_o$next[63:0]$10732
end
case
- assign $1\sv0__data_o$next[63:0]$10820 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv0__data_o$next[63:0]$10728 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv0__data_o$next[63:0]$10826 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv0__data_o$next[63:0]$10734 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv0__data_o$next[63:0]$10826 $1\sv0__data_o$next[63:0]$10820
+ assign $7\sv0__data_o$next[63:0]$10734 $1\sv0__data_o$next[63:0]$10728
end
sync always
- update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10819
+ update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10727
end
- attribute \src "libresoc.v:176503.3-176538.6"
- process $proc$libresoc.v:176503$10827
+ attribute \src "libresoc.v:174256.3-174291.6"
+ process $proc$libresoc.v:174256$10735
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10828 $1\wr_detect$7[0:0]$10829
- attribute \src "libresoc.v:176504.5-176504.29"
+ assign $0\wr_detect$7[0:0]$10736 $1\wr_detect$7[0:0]$10737
+ attribute \src "libresoc.v:174257.5-174257.29"
switch \initial
- attribute \src "libresoc.v:176504.9-176504.17"
+ attribute \src "libresoc.v:174257.9-174257.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10829 $5\wr_detect$7[0:0]$10833
+ assign $1\wr_detect$7[0:0]$10737 $5\wr_detect$7[0:0]$10741
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10830 1'1
+ assign $2\wr_detect$7[0:0]$10738 1'1
case
- assign $2\wr_detect$7[0:0]$10830 1'0
+ assign $2\wr_detect$7[0:0]$10738 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10831 1'1
+ assign $3\wr_detect$7[0:0]$10739 1'1
case
- assign $3\wr_detect$7[0:0]$10831 $2\wr_detect$7[0:0]$10830
+ assign $3\wr_detect$7[0:0]$10739 $2\wr_detect$7[0:0]$10738
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10832 1'1
+ assign $4\wr_detect$7[0:0]$10740 1'1
case
- assign $4\wr_detect$7[0:0]$10832 $3\wr_detect$7[0:0]$10831
+ assign $4\wr_detect$7[0:0]$10740 $3\wr_detect$7[0:0]$10739
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$10833 1'1
+ assign $5\wr_detect$7[0:0]$10741 1'1
case
- assign $5\wr_detect$7[0:0]$10833 $4\wr_detect$7[0:0]$10832
+ assign $5\wr_detect$7[0:0]$10741 $4\wr_detect$7[0:0]$10740
end
case
- assign $1\wr_detect$7[0:0]$10829 1'0
+ assign $1\wr_detect$7[0:0]$10737 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10828
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10736
end
- attribute \src "libresoc.v:176539.3-176571.6"
- process $proc$libresoc.v:176539$10834
+ attribute \src "libresoc.v:174292.3-174324.6"
+ process $proc$libresoc.v:174292$10742
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$10835 $5\reg$next[63:0]$10840
- attribute \src "libresoc.v:176540.5-176540.29"
+ assign $0\reg$next[63:0]$10743 $5\reg$next[63:0]$10748
+ attribute \src "libresoc.v:174293.5-174293.29"
switch \initial
- attribute \src "libresoc.v:176540.9-176540.17"
+ attribute \src "libresoc.v:174293.9-174293.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$10836 \nia0__data_i
+ assign $1\reg$next[63:0]$10744 \nia0__data_i
case
- assign $1\reg$next[63:0]$10836 \reg
+ assign $1\reg$next[63:0]$10744 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$10837 \msr0__data_i
+ assign $2\reg$next[63:0]$10745 \msr0__data_i
case
- assign $2\reg$next[63:0]$10837 $1\reg$next[63:0]$10836
+ assign $2\reg$next[63:0]$10745 $1\reg$next[63:0]$10744
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv0__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$10838 \sv0__data_i
+ assign $3\reg$next[63:0]$10746 \sv0__data_i
case
- assign $3\reg$next[63:0]$10838 $2\reg$next[63:0]$10837
+ assign $3\reg$next[63:0]$10746 $2\reg$next[63:0]$10745
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr10__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$10839 \d_wr10__data_i
+ assign $4\reg$next[63:0]$10747 \d_wr10__data_i
case
- assign $4\reg$next[63:0]$10839 $3\reg$next[63:0]$10838
+ assign $4\reg$next[63:0]$10747 $3\reg$next[63:0]$10746
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$10840 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$10748 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$10840 $4\reg$next[63:0]$10839
+ assign $5\reg$next[63:0]$10748 $4\reg$next[63:0]$10747
end
sync always
- update \reg$next $0\reg$next[63:0]$10835
+ update \reg$next $0\reg$next[63:0]$10743
end
- connect \$1 $not$libresoc.v:176282$10785_Y
- connect \$3 $not$libresoc.v:176283$10786_Y
- connect \$6 $not$libresoc.v:176284$10787_Y
+ connect \$1 $not$libresoc.v:174035$10693_Y
+ connect \$3 $not$libresoc.v:174036$10694_Y
+ connect \$6 $not$libresoc.v:174037$10695_Y
end
-attribute \src "libresoc.v:176576.1-177047.10"
+attribute \src "libresoc.v:174329.1-174800.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1"
attribute \generator "nMigen"
module \reg_1
- attribute \src "libresoc.v:176577.7-176577.20"
+ attribute \src "libresoc.v:174330.7-174330.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $0\r1__data_o$next[3:0]$10901
- attribute \src "libresoc.v:176662.3-176663.37"
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $0\r1__data_o$next[3:0]$10809
+ attribute \src "libresoc.v:174415.3-174416.37"
wire width 4 $0\r1__data_o[3:0]
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $0\r21__data_o$next[3:0]$10915
- attribute \src "libresoc.v:176660.3-176661.39"
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $0\r21__data_o$next[3:0]$10823
+ attribute \src "libresoc.v:174413.3-174414.39"
wire width 4 $0\r21__data_o[3:0]
- attribute \src "libresoc.v:176740.3-176766.6"
- wire width 4 $0\reg$next[3:0]$10867
- attribute \src "libresoc.v:176658.3-176659.25"
+ attribute \src "libresoc.v:174493.3-174519.6"
+ wire width 4 $0\reg$next[3:0]$10775
+ attribute \src "libresoc.v:174411.3-174412.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $0\src11__data_o$next[3:0]$10858
- attribute \src "libresoc.v:176668.3-176669.43"
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $0\src11__data_o$next[3:0]$10766
+ attribute \src "libresoc.v:174421.3-174422.43"
wire width 4 $0\src11__data_o[3:0]
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $0\src21__data_o$next[3:0]$10873
- attribute \src "libresoc.v:176666.3-176667.43"
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $0\src21__data_o$next[3:0]$10781
+ attribute \src "libresoc.v:174419.3-174420.43"
wire width 4 $0\src21__data_o[3:0]
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $0\src31__data_o$next[3:0]$10887
- attribute \src "libresoc.v:176664.3-176665.43"
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $0\src31__data_o$next[3:0]$10795
+ attribute \src "libresoc.v:174417.3-174418.43"
wire width 4 $0\src31__data_o[3:0]
- attribute \src "libresoc.v:176947.3-176976.6"
- wire $0\wr_detect$10[0:0]$10909
- attribute \src "libresoc.v:177017.3-177046.6"
- wire $0\wr_detect$13[0:0]$10923
- attribute \src "libresoc.v:176807.3-176836.6"
- wire $0\wr_detect$4[0:0]$10881
- attribute \src "libresoc.v:176877.3-176906.6"
- wire $0\wr_detect$7[0:0]$10895
- attribute \src "libresoc.v:176710.3-176739.6"
+ attribute \src "libresoc.v:174700.3-174729.6"
+ wire $0\wr_detect$10[0:0]$10817
+ attribute \src "libresoc.v:174770.3-174799.6"
+ wire $0\wr_detect$13[0:0]$10831
+ attribute \src "libresoc.v:174560.3-174589.6"
+ wire $0\wr_detect$4[0:0]$10789
+ attribute \src "libresoc.v:174630.3-174659.6"
+ wire $0\wr_detect$7[0:0]$10803
+ attribute \src "libresoc.v:174463.3-174492.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $1\r1__data_o$next[3:0]$10902
- attribute \src "libresoc.v:176602.13-176602.30"
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $1\r1__data_o$next[3:0]$10810
+ attribute \src "libresoc.v:174355.13-174355.30"
wire width 4 $1\r1__data_o[3:0]
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $1\r21__data_o$next[3:0]$10916
- attribute \src "libresoc.v:176609.13-176609.31"
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $1\r21__data_o$next[3:0]$10824
+ attribute \src "libresoc.v:174362.13-174362.31"
wire width 4 $1\r21__data_o[3:0]
- attribute \src "libresoc.v:176740.3-176766.6"
- wire width 4 $1\reg$next[3:0]$10868
- attribute \src "libresoc.v:176615.13-176615.25"
+ attribute \src "libresoc.v:174493.3-174519.6"
+ wire width 4 $1\reg$next[3:0]$10776
+ attribute \src "libresoc.v:174368.13-174368.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $1\src11__data_o$next[3:0]$10859
- attribute \src "libresoc.v:176620.13-176620.33"
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $1\src11__data_o$next[3:0]$10767
+ attribute \src "libresoc.v:174373.13-174373.33"
wire width 4 $1\src11__data_o[3:0]
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $1\src21__data_o$next[3:0]$10874
- attribute \src "libresoc.v:176627.13-176627.33"
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $1\src21__data_o$next[3:0]$10782
+ attribute \src "libresoc.v:174380.13-174380.33"
wire width 4 $1\src21__data_o[3:0]
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $1\src31__data_o$next[3:0]$10888
- attribute \src "libresoc.v:176634.13-176634.33"
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $1\src31__data_o$next[3:0]$10796
+ attribute \src "libresoc.v:174387.13-174387.33"
wire width 4 $1\src31__data_o[3:0]
- attribute \src "libresoc.v:176947.3-176976.6"
- wire $1\wr_detect$10[0:0]$10910
- attribute \src "libresoc.v:177017.3-177046.6"
- wire $1\wr_detect$13[0:0]$10924
- attribute \src "libresoc.v:176807.3-176836.6"
- wire $1\wr_detect$4[0:0]$10882
- attribute \src "libresoc.v:176877.3-176906.6"
- wire $1\wr_detect$7[0:0]$10896
- attribute \src "libresoc.v:176710.3-176739.6"
+ attribute \src "libresoc.v:174700.3-174729.6"
+ wire $1\wr_detect$10[0:0]$10818
+ attribute \src "libresoc.v:174770.3-174799.6"
+ wire $1\wr_detect$13[0:0]$10832
+ attribute \src "libresoc.v:174560.3-174589.6"
+ wire $1\wr_detect$4[0:0]$10790
+ attribute \src "libresoc.v:174630.3-174659.6"
+ wire $1\wr_detect$7[0:0]$10804
+ attribute \src "libresoc.v:174463.3-174492.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $2\r1__data_o$next[3:0]$10903
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $2\r21__data_o$next[3:0]$10917
- attribute \src "libresoc.v:176740.3-176766.6"
- wire width 4 $2\reg$next[3:0]$10869
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $2\src11__data_o$next[3:0]$10860
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $2\src21__data_o$next[3:0]$10875
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $2\src31__data_o$next[3:0]$10889
- attribute \src "libresoc.v:176947.3-176976.6"
- wire $2\wr_detect$10[0:0]$10911
- attribute \src "libresoc.v:177017.3-177046.6"
- wire $2\wr_detect$13[0:0]$10925
- attribute \src "libresoc.v:176807.3-176836.6"
- wire $2\wr_detect$4[0:0]$10883
- attribute \src "libresoc.v:176877.3-176906.6"
- wire $2\wr_detect$7[0:0]$10897
- attribute \src "libresoc.v:176710.3-176739.6"
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $2\r1__data_o$next[3:0]$10811
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $2\r21__data_o$next[3:0]$10825
+ attribute \src "libresoc.v:174493.3-174519.6"
+ wire width 4 $2\reg$next[3:0]$10777
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $2\src11__data_o$next[3:0]$10768
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $2\src21__data_o$next[3:0]$10783
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $2\src31__data_o$next[3:0]$10797
+ attribute \src "libresoc.v:174700.3-174729.6"
+ wire $2\wr_detect$10[0:0]$10819
+ attribute \src "libresoc.v:174770.3-174799.6"
+ wire $2\wr_detect$13[0:0]$10833
+ attribute \src "libresoc.v:174560.3-174589.6"
+ wire $2\wr_detect$4[0:0]$10791
+ attribute \src "libresoc.v:174630.3-174659.6"
+ wire $2\wr_detect$7[0:0]$10805
+ attribute \src "libresoc.v:174463.3-174492.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $3\r1__data_o$next[3:0]$10904
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $3\r21__data_o$next[3:0]$10918
- attribute \src "libresoc.v:176740.3-176766.6"
- wire width 4 $3\reg$next[3:0]$10870
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $3\src11__data_o$next[3:0]$10861
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $3\src21__data_o$next[3:0]$10876
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $3\src31__data_o$next[3:0]$10890
- attribute \src "libresoc.v:176947.3-176976.6"
- wire $3\wr_detect$10[0:0]$10912
- attribute \src "libresoc.v:177017.3-177046.6"
- wire $3\wr_detect$13[0:0]$10926
- attribute \src "libresoc.v:176807.3-176836.6"
- wire $3\wr_detect$4[0:0]$10884
- attribute \src "libresoc.v:176877.3-176906.6"
- wire $3\wr_detect$7[0:0]$10898
- attribute \src "libresoc.v:176710.3-176739.6"
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $3\r1__data_o$next[3:0]$10812
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $3\r21__data_o$next[3:0]$10826
+ attribute \src "libresoc.v:174493.3-174519.6"
+ wire width 4 $3\reg$next[3:0]$10778
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $3\src11__data_o$next[3:0]$10769
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $3\src21__data_o$next[3:0]$10784
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $3\src31__data_o$next[3:0]$10798
+ attribute \src "libresoc.v:174700.3-174729.6"
+ wire $3\wr_detect$10[0:0]$10820
+ attribute \src "libresoc.v:174770.3-174799.6"
+ wire $3\wr_detect$13[0:0]$10834
+ attribute \src "libresoc.v:174560.3-174589.6"
+ wire $3\wr_detect$4[0:0]$10792
+ attribute \src "libresoc.v:174630.3-174659.6"
+ wire $3\wr_detect$7[0:0]$10806
+ attribute \src "libresoc.v:174463.3-174492.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $4\r1__data_o$next[3:0]$10905
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $4\r21__data_o$next[3:0]$10919
- attribute \src "libresoc.v:176740.3-176766.6"
- wire width 4 $4\reg$next[3:0]$10871
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $4\src11__data_o$next[3:0]$10862
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $4\src21__data_o$next[3:0]$10877
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $4\src31__data_o$next[3:0]$10891
- attribute \src "libresoc.v:176947.3-176976.6"
- wire $4\wr_detect$10[0:0]$10913
- attribute \src "libresoc.v:177017.3-177046.6"
- wire $4\wr_detect$13[0:0]$10927
- attribute \src "libresoc.v:176807.3-176836.6"
- wire $4\wr_detect$4[0:0]$10885
- attribute \src "libresoc.v:176877.3-176906.6"
- wire $4\wr_detect$7[0:0]$10899
- attribute \src "libresoc.v:176710.3-176739.6"
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $4\r1__data_o$next[3:0]$10813
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $4\r21__data_o$next[3:0]$10827
+ attribute \src "libresoc.v:174493.3-174519.6"
+ wire width 4 $4\reg$next[3:0]$10779
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $4\src11__data_o$next[3:0]$10770
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $4\src21__data_o$next[3:0]$10785
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $4\src31__data_o$next[3:0]$10799
+ attribute \src "libresoc.v:174700.3-174729.6"
+ wire $4\wr_detect$10[0:0]$10821
+ attribute \src "libresoc.v:174770.3-174799.6"
+ wire $4\wr_detect$13[0:0]$10835
+ attribute \src "libresoc.v:174560.3-174589.6"
+ wire $4\wr_detect$4[0:0]$10793
+ attribute \src "libresoc.v:174630.3-174659.6"
+ wire $4\wr_detect$7[0:0]$10807
+ attribute \src "libresoc.v:174463.3-174492.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $5\r1__data_o$next[3:0]$10906
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $5\r21__data_o$next[3:0]$10920
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $5\src11__data_o$next[3:0]$10863
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $5\src21__data_o$next[3:0]$10878
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $5\src31__data_o$next[3:0]$10892
- attribute \src "libresoc.v:176907.3-176946.6"
- wire width 4 $6\r1__data_o$next[3:0]$10907
- attribute \src "libresoc.v:176977.3-177016.6"
- wire width 4 $6\r21__data_o$next[3:0]$10921
- attribute \src "libresoc.v:176670.3-176709.6"
- wire width 4 $6\src11__data_o$next[3:0]$10864
- attribute \src "libresoc.v:176767.3-176806.6"
- wire width 4 $6\src21__data_o$next[3:0]$10879
- attribute \src "libresoc.v:176837.3-176876.6"
- wire width 4 $6\src31__data_o$next[3:0]$10893
- attribute \src "libresoc.v:176653.17-176653.104"
- wire $not$libresoc.v:176653$10846_Y
- attribute \src "libresoc.v:176654.18-176654.105"
- wire $not$libresoc.v:176654$10847_Y
- attribute \src "libresoc.v:176655.17-176655.100"
- wire $not$libresoc.v:176655$10848_Y
- attribute \src "libresoc.v:176656.17-176656.103"
- wire $not$libresoc.v:176656$10849_Y
- attribute \src "libresoc.v:176657.17-176657.103"
- wire $not$libresoc.v:176657$10850_Y
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $5\r1__data_o$next[3:0]$10814
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $5\r21__data_o$next[3:0]$10828
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $5\src11__data_o$next[3:0]$10771
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $5\src21__data_o$next[3:0]$10786
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $5\src31__data_o$next[3:0]$10800
+ attribute \src "libresoc.v:174660.3-174699.6"
+ wire width 4 $6\r1__data_o$next[3:0]$10815
+ attribute \src "libresoc.v:174730.3-174769.6"
+ wire width 4 $6\r21__data_o$next[3:0]$10829
+ attribute \src "libresoc.v:174423.3-174462.6"
+ wire width 4 $6\src11__data_o$next[3:0]$10772
+ attribute \src "libresoc.v:174520.3-174559.6"
+ wire width 4 $6\src21__data_o$next[3:0]$10787
+ attribute \src "libresoc.v:174590.3-174629.6"
+ wire width 4 $6\src31__data_o$next[3:0]$10801
+ attribute \src "libresoc.v:174406.17-174406.104"
+ wire $not$libresoc.v:174406$10754_Y
+ attribute \src "libresoc.v:174407.18-174407.105"
+ wire $not$libresoc.v:174407$10755_Y
+ attribute \src "libresoc.v:174408.17-174408.100"
+ wire $not$libresoc.v:174408$10756_Y
+ attribute \src "libresoc.v:174409.17-174409.103"
+ wire $not$libresoc.v:174409$10757_Y
+ attribute \src "libresoc.v:174410.17-174410.103"
+ wire $not$libresoc.v:174410$10758_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest11__data_i
wire width 4 input 11 \dest21__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest21__wen
- attribute \src "libresoc.v:176577.7-176577.15"
+ attribute \src "libresoc.v:174330.7-174330.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 12 \r1__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176653$10846
+ cell $not $not$libresoc.v:174406$10754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:176653$10846_Y
+ connect \Y $not$libresoc.v:174406$10754_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176654$10847
+ cell $not $not$libresoc.v:174407$10755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:176654$10847_Y
+ connect \Y $not$libresoc.v:174407$10755_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176655$10848
+ cell $not $not$libresoc.v:174408$10756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:176655$10848_Y
+ connect \Y $not$libresoc.v:174408$10756_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176656$10849
+ cell $not $not$libresoc.v:174409$10757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:176656$10849_Y
+ connect \Y $not$libresoc.v:174409$10757_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:176657$10850
+ cell $not $not$libresoc.v:174410$10758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:176657$10850_Y
+ connect \Y $not$libresoc.v:174410$10758_Y
end
- attribute \src "libresoc.v:176577.7-176577.20"
- process $proc$libresoc.v:176577$10928
+ attribute \src "libresoc.v:174330.7-174330.20"
+ process $proc$libresoc.v:174330$10836
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:176602.13-176602.30"
- process $proc$libresoc.v:176602$10929
+ attribute \src "libresoc.v:174355.13-174355.30"
+ process $proc$libresoc.v:174355$10837
assign { } { }
assign $1\r1__data_o[3:0] 4'0000
sync always
sync init
update \r1__data_o $1\r1__data_o[3:0]
end
- attribute \src "libresoc.v:176609.13-176609.31"
- process $proc$libresoc.v:176609$10930
+ attribute \src "libresoc.v:174362.13-174362.31"
+ process $proc$libresoc.v:174362$10838
assign { } { }
assign $1\r21__data_o[3:0] 4'0000
sync always
sync init
update \r21__data_o $1\r21__data_o[3:0]
end
- attribute \src "libresoc.v:176615.13-176615.25"
- process $proc$libresoc.v:176615$10931
+ attribute \src "libresoc.v:174368.13-174368.25"
+ process $proc$libresoc.v:174368$10839
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:176620.13-176620.33"
- process $proc$libresoc.v:176620$10932
+ attribute \src "libresoc.v:174373.13-174373.33"
+ process $proc$libresoc.v:174373$10840
assign { } { }
assign $1\src11__data_o[3:0] 4'0000
sync always
sync init
update \src11__data_o $1\src11__data_o[3:0]
end
- attribute \src "libresoc.v:176627.13-176627.33"
- process $proc$libresoc.v:176627$10933
+ attribute \src "libresoc.v:174380.13-174380.33"
+ process $proc$libresoc.v:174380$10841
assign { } { }
assign $1\src21__data_o[3:0] 4'0000
sync always
sync init
update \src21__data_o $1\src21__data_o[3:0]
end
- attribute \src "libresoc.v:176634.13-176634.33"
- process $proc$libresoc.v:176634$10934
+ attribute \src "libresoc.v:174387.13-174387.33"
+ process $proc$libresoc.v:174387$10842
assign { } { }
assign $1\src31__data_o[3:0] 4'0000
sync always
sync init
update \src31__data_o $1\src31__data_o[3:0]
end
- attribute \src "libresoc.v:176658.3-176659.25"
- process $proc$libresoc.v:176658$10851
+ attribute \src "libresoc.v:174411.3-174412.25"
+ process $proc$libresoc.v:174411$10759
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:176660.3-176661.39"
- process $proc$libresoc.v:176660$10852
+ attribute \src "libresoc.v:174413.3-174414.39"
+ process $proc$libresoc.v:174413$10760
assign { } { }
assign $0\r21__data_o[3:0] \r21__data_o$next
sync posedge \coresync_clk
update \r21__data_o $0\r21__data_o[3:0]
end
- attribute \src "libresoc.v:176662.3-176663.37"
- process $proc$libresoc.v:176662$10853
+ attribute \src "libresoc.v:174415.3-174416.37"
+ process $proc$libresoc.v:174415$10761
assign { } { }
assign $0\r1__data_o[3:0] \r1__data_o$next
sync posedge \coresync_clk
update \r1__data_o $0\r1__data_o[3:0]
end
- attribute \src "libresoc.v:176664.3-176665.43"
- process $proc$libresoc.v:176664$10854
+ attribute \src "libresoc.v:174417.3-174418.43"
+ process $proc$libresoc.v:174417$10762
assign { } { }
assign $0\src31__data_o[3:0] \src31__data_o$next
sync posedge \coresync_clk
update \src31__data_o $0\src31__data_o[3:0]
end
- attribute \src "libresoc.v:176666.3-176667.43"
- process $proc$libresoc.v:176666$10855
+ attribute \src "libresoc.v:174419.3-174420.43"
+ process $proc$libresoc.v:174419$10763
assign { } { }
assign $0\src21__data_o[3:0] \src21__data_o$next
sync posedge \coresync_clk
update \src21__data_o $0\src21__data_o[3:0]
end
- attribute \src "libresoc.v:176668.3-176669.43"
- process $proc$libresoc.v:176668$10856
+ attribute \src "libresoc.v:174421.3-174422.43"
+ process $proc$libresoc.v:174421$10764
assign { } { }
assign $0\src11__data_o[3:0] \src11__data_o$next
sync posedge \coresync_clk
update \src11__data_o $0\src11__data_o[3:0]
end
- attribute \src "libresoc.v:176670.3-176709.6"
- process $proc$libresoc.v:176670$10857
+ attribute \src "libresoc.v:174423.3-174462.6"
+ process $proc$libresoc.v:174423$10765
assign { } { }
assign { } { }
assign { } { }
- assign $0\src11__data_o$next[3:0]$10858 $6\src11__data_o$next[3:0]$10864
- attribute \src "libresoc.v:176671.5-176671.29"
+ assign $0\src11__data_o$next[3:0]$10766 $6\src11__data_o$next[3:0]$10772
+ attribute \src "libresoc.v:174424.5-174424.29"
switch \initial
- attribute \src "libresoc.v:176671.9-176671.17"
+ attribute \src "libresoc.v:174424.9-174424.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src11__data_o$next[3:0]$10859 $5\src11__data_o$next[3:0]$10863
+ assign $1\src11__data_o$next[3:0]$10767 $5\src11__data_o$next[3:0]$10771
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src11__data_o$next[3:0]$10860 \dest11__data_i
+ assign $2\src11__data_o$next[3:0]$10768 \dest11__data_i
case
- assign $2\src11__data_o$next[3:0]$10860 4'0000
+ assign $2\src11__data_o$next[3:0]$10768 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src11__data_o$next[3:0]$10861 \dest21__data_i
+ assign $3\src11__data_o$next[3:0]$10769 \dest21__data_i
case
- assign $3\src11__data_o$next[3:0]$10861 $2\src11__data_o$next[3:0]$10860
+ assign $3\src11__data_o$next[3:0]$10769 $2\src11__data_o$next[3:0]$10768
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src11__data_o$next[3:0]$10862 \w1__data_i
+ assign $4\src11__data_o$next[3:0]$10770 \w1__data_i
case
- assign $4\src11__data_o$next[3:0]$10862 $3\src11__data_o$next[3:0]$10861
+ assign $4\src11__data_o$next[3:0]$10770 $3\src11__data_o$next[3:0]$10769
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src11__data_o$next[3:0]$10863 \reg
+ assign $5\src11__data_o$next[3:0]$10771 \reg
case
- assign $5\src11__data_o$next[3:0]$10863 $4\src11__data_o$next[3:0]$10862
+ assign $5\src11__data_o$next[3:0]$10771 $4\src11__data_o$next[3:0]$10770
end
case
- assign $1\src11__data_o$next[3:0]$10859 4'0000
+ assign $1\src11__data_o$next[3:0]$10767 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src11__data_o$next[3:0]$10864 4'0000
+ assign $6\src11__data_o$next[3:0]$10772 4'0000
case
- assign $6\src11__data_o$next[3:0]$10864 $1\src11__data_o$next[3:0]$10859
+ assign $6\src11__data_o$next[3:0]$10772 $1\src11__data_o$next[3:0]$10767
end
sync always
- update \src11__data_o$next $0\src11__data_o$next[3:0]$10858
+ update \src11__data_o$next $0\src11__data_o$next[3:0]$10766
end
- attribute \src "libresoc.v:176710.3-176739.6"
- process $proc$libresoc.v:176710$10865
+ attribute \src "libresoc.v:174463.3-174492.6"
+ process $proc$libresoc.v:174463$10773
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:176711.5-176711.29"
+ attribute \src "libresoc.v:174464.5-174464.29"
switch \initial
- attribute \src "libresoc.v:176711.9-176711.17"
+ attribute \src "libresoc.v:174464.9-174464.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:176740.3-176766.6"
- process $proc$libresoc.v:176740$10866
+ attribute \src "libresoc.v:174493.3-174519.6"
+ process $proc$libresoc.v:174493$10774
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$10867 $4\reg$next[3:0]$10871
- attribute \src "libresoc.v:176741.5-176741.29"
+ assign $0\reg$next[3:0]$10775 $4\reg$next[3:0]$10779
+ attribute \src "libresoc.v:174494.5-174494.29"
switch \initial
- attribute \src "libresoc.v:176741.9-176741.17"
+ attribute \src "libresoc.v:174494.9-174494.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$10868 \dest11__data_i
+ assign $1\reg$next[3:0]$10776 \dest11__data_i
case
- assign $1\reg$next[3:0]$10868 \reg
+ assign $1\reg$next[3:0]$10776 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$10869 \dest21__data_i
+ assign $2\reg$next[3:0]$10777 \dest21__data_i
case
- assign $2\reg$next[3:0]$10869 $1\reg$next[3:0]$10868
+ assign $2\reg$next[3:0]$10777 $1\reg$next[3:0]$10776
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$10870 \w1__data_i
+ assign $3\reg$next[3:0]$10778 \w1__data_i
case
- assign $3\reg$next[3:0]$10870 $2\reg$next[3:0]$10869
+ assign $3\reg$next[3:0]$10778 $2\reg$next[3:0]$10777
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$10871 4'0000
+ assign $4\reg$next[3:0]$10779 4'0000
case
- assign $4\reg$next[3:0]$10871 $3\reg$next[3:0]$10870
+ assign $4\reg$next[3:0]$10779 $3\reg$next[3:0]$10778
end
sync always
- update \reg$next $0\reg$next[3:0]$10867
+ update \reg$next $0\reg$next[3:0]$10775
end
- attribute \src "libresoc.v:176767.3-176806.6"
- process $proc$libresoc.v:176767$10872
+ attribute \src "libresoc.v:174520.3-174559.6"
+ process $proc$libresoc.v:174520$10780
assign { } { }
assign { } { }
assign { } { }
- assign $0\src21__data_o$next[3:0]$10873 $6\src21__data_o$next[3:0]$10879
- attribute \src "libresoc.v:176768.5-176768.29"
+ assign $0\src21__data_o$next[3:0]$10781 $6\src21__data_o$next[3:0]$10787
+ attribute \src "libresoc.v:174521.5-174521.29"
switch \initial
- attribute \src "libresoc.v:176768.9-176768.17"
+ attribute \src "libresoc.v:174521.9-174521.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src21__data_o$next[3:0]$10874 $5\src21__data_o$next[3:0]$10878
+ assign $1\src21__data_o$next[3:0]$10782 $5\src21__data_o$next[3:0]$10786
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src21__data_o$next[3:0]$10875 \dest11__data_i
+ assign $2\src21__data_o$next[3:0]$10783 \dest11__data_i
case
- assign $2\src21__data_o$next[3:0]$10875 4'0000
+ assign $2\src21__data_o$next[3:0]$10783 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src21__data_o$next[3:0]$10876 \dest21__data_i
+ assign $3\src21__data_o$next[3:0]$10784 \dest21__data_i
case
- assign $3\src21__data_o$next[3:0]$10876 $2\src21__data_o$next[3:0]$10875
+ assign $3\src21__data_o$next[3:0]$10784 $2\src21__data_o$next[3:0]$10783
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src21__data_o$next[3:0]$10877 \w1__data_i
+ assign $4\src21__data_o$next[3:0]$10785 \w1__data_i
case
- assign $4\src21__data_o$next[3:0]$10877 $3\src21__data_o$next[3:0]$10876
+ assign $4\src21__data_o$next[3:0]$10785 $3\src21__data_o$next[3:0]$10784
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src21__data_o$next[3:0]$10878 \reg
+ assign $5\src21__data_o$next[3:0]$10786 \reg
case
- assign $5\src21__data_o$next[3:0]$10878 $4\src21__data_o$next[3:0]$10877
+ assign $5\src21__data_o$next[3:0]$10786 $4\src21__data_o$next[3:0]$10785
end
case
- assign $1\src21__data_o$next[3:0]$10874 4'0000
+ assign $1\src21__data_o$next[3:0]$10782 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src21__data_o$next[3:0]$10879 4'0000
+ assign $6\src21__data_o$next[3:0]$10787 4'0000
case
- assign $6\src21__data_o$next[3:0]$10879 $1\src21__data_o$next[3:0]$10874
+ assign $6\src21__data_o$next[3:0]$10787 $1\src21__data_o$next[3:0]$10782
end
sync always
- update \src21__data_o$next $0\src21__data_o$next[3:0]$10873
+ update \src21__data_o$next $0\src21__data_o$next[3:0]$10781
end
- attribute \src "libresoc.v:176807.3-176836.6"
- process $proc$libresoc.v:176807$10880
+ attribute \src "libresoc.v:174560.3-174589.6"
+ process $proc$libresoc.v:174560$10788
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10881 $1\wr_detect$4[0:0]$10882
- attribute \src "libresoc.v:176808.5-176808.29"
+ assign $0\wr_detect$4[0:0]$10789 $1\wr_detect$4[0:0]$10790
+ attribute \src "libresoc.v:174561.5-174561.29"
switch \initial
- attribute \src "libresoc.v:176808.9-176808.17"
+ attribute \src "libresoc.v:174561.9-174561.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10882 $4\wr_detect$4[0:0]$10885
+ assign $1\wr_detect$4[0:0]$10790 $4\wr_detect$4[0:0]$10793
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10883 1'1
+ assign $2\wr_detect$4[0:0]$10791 1'1
case
- assign $2\wr_detect$4[0:0]$10883 1'0
+ assign $2\wr_detect$4[0:0]$10791 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10884 1'1
+ assign $3\wr_detect$4[0:0]$10792 1'1
case
- assign $3\wr_detect$4[0:0]$10884 $2\wr_detect$4[0:0]$10883
+ assign $3\wr_detect$4[0:0]$10792 $2\wr_detect$4[0:0]$10791
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10885 1'1
+ assign $4\wr_detect$4[0:0]$10793 1'1
case
- assign $4\wr_detect$4[0:0]$10885 $3\wr_detect$4[0:0]$10884
+ assign $4\wr_detect$4[0:0]$10793 $3\wr_detect$4[0:0]$10792
end
case
- assign $1\wr_detect$4[0:0]$10882 1'0
+ assign $1\wr_detect$4[0:0]$10790 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10881
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10789
end
- attribute \src "libresoc.v:176837.3-176876.6"
- process $proc$libresoc.v:176837$10886
+ attribute \src "libresoc.v:174590.3-174629.6"
+ process $proc$libresoc.v:174590$10794
assign { } { }
assign { } { }
assign { } { }
- assign $0\src31__data_o$next[3:0]$10887 $6\src31__data_o$next[3:0]$10893
- attribute \src "libresoc.v:176838.5-176838.29"
+ assign $0\src31__data_o$next[3:0]$10795 $6\src31__data_o$next[3:0]$10801
+ attribute \src "libresoc.v:174591.5-174591.29"
switch \initial
- attribute \src "libresoc.v:176838.9-176838.17"
+ attribute \src "libresoc.v:174591.9-174591.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src31__data_o$next[3:0]$10888 $5\src31__data_o$next[3:0]$10892
+ assign $1\src31__data_o$next[3:0]$10796 $5\src31__data_o$next[3:0]$10800
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src31__data_o$next[3:0]$10889 \dest11__data_i
+ assign $2\src31__data_o$next[3:0]$10797 \dest11__data_i
case
- assign $2\src31__data_o$next[3:0]$10889 4'0000
+ assign $2\src31__data_o$next[3:0]$10797 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src31__data_o$next[3:0]$10890 \dest21__data_i
+ assign $3\src31__data_o$next[3:0]$10798 \dest21__data_i
case
- assign $3\src31__data_o$next[3:0]$10890 $2\src31__data_o$next[3:0]$10889
+ assign $3\src31__data_o$next[3:0]$10798 $2\src31__data_o$next[3:0]$10797
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src31__data_o$next[3:0]$10891 \w1__data_i
+ assign $4\src31__data_o$next[3:0]$10799 \w1__data_i
case
- assign $4\src31__data_o$next[3:0]$10891 $3\src31__data_o$next[3:0]$10890
+ assign $4\src31__data_o$next[3:0]$10799 $3\src31__data_o$next[3:0]$10798
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src31__data_o$next[3:0]$10892 \reg
+ assign $5\src31__data_o$next[3:0]$10800 \reg
case
- assign $5\src31__data_o$next[3:0]$10892 $4\src31__data_o$next[3:0]$10891
+ assign $5\src31__data_o$next[3:0]$10800 $4\src31__data_o$next[3:0]$10799
end
case
- assign $1\src31__data_o$next[3:0]$10888 4'0000
+ assign $1\src31__data_o$next[3:0]$10796 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src31__data_o$next[3:0]$10893 4'0000
+ assign $6\src31__data_o$next[3:0]$10801 4'0000
case
- assign $6\src31__data_o$next[3:0]$10893 $1\src31__data_o$next[3:0]$10888
+ assign $6\src31__data_o$next[3:0]$10801 $1\src31__data_o$next[3:0]$10796
end
sync always
- update \src31__data_o$next $0\src31__data_o$next[3:0]$10887
+ update \src31__data_o$next $0\src31__data_o$next[3:0]$10795
end
- attribute \src "libresoc.v:176877.3-176906.6"
- process $proc$libresoc.v:176877$10894
+ attribute \src "libresoc.v:174630.3-174659.6"
+ process $proc$libresoc.v:174630$10802
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10895 $1\wr_detect$7[0:0]$10896
- attribute \src "libresoc.v:176878.5-176878.29"
+ assign $0\wr_detect$7[0:0]$10803 $1\wr_detect$7[0:0]$10804
+ attribute \src "libresoc.v:174631.5-174631.29"
switch \initial
- attribute \src "libresoc.v:176878.9-176878.17"
+ attribute \src "libresoc.v:174631.9-174631.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10896 $4\wr_detect$7[0:0]$10899
+ assign $1\wr_detect$7[0:0]$10804 $4\wr_detect$7[0:0]$10807
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10897 1'1
+ assign $2\wr_detect$7[0:0]$10805 1'1
case
- assign $2\wr_detect$7[0:0]$10897 1'0
+ assign $2\wr_detect$7[0:0]$10805 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10898 1'1
+ assign $3\wr_detect$7[0:0]$10806 1'1
case
- assign $3\wr_detect$7[0:0]$10898 $2\wr_detect$7[0:0]$10897
+ assign $3\wr_detect$7[0:0]$10806 $2\wr_detect$7[0:0]$10805
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10899 1'1
+ assign $4\wr_detect$7[0:0]$10807 1'1
case
- assign $4\wr_detect$7[0:0]$10899 $3\wr_detect$7[0:0]$10898
+ assign $4\wr_detect$7[0:0]$10807 $3\wr_detect$7[0:0]$10806
end
case
- assign $1\wr_detect$7[0:0]$10896 1'0
+ assign $1\wr_detect$7[0:0]$10804 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10895
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10803
end
- attribute \src "libresoc.v:176907.3-176946.6"
- process $proc$libresoc.v:176907$10900
+ attribute \src "libresoc.v:174660.3-174699.6"
+ process $proc$libresoc.v:174660$10808
assign { } { }
assign { } { }
assign { } { }
- assign $0\r1__data_o$next[3:0]$10901 $6\r1__data_o$next[3:0]$10907
- attribute \src "libresoc.v:176908.5-176908.29"
+ assign $0\r1__data_o$next[3:0]$10809 $6\r1__data_o$next[3:0]$10815
+ attribute \src "libresoc.v:174661.5-174661.29"
switch \initial
- attribute \src "libresoc.v:176908.9-176908.17"
+ attribute \src "libresoc.v:174661.9-174661.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r1__data_o$next[3:0]$10902 $5\r1__data_o$next[3:0]$10906
+ assign $1\r1__data_o$next[3:0]$10810 $5\r1__data_o$next[3:0]$10814
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r1__data_o$next[3:0]$10903 \dest11__data_i
+ assign $2\r1__data_o$next[3:0]$10811 \dest11__data_i
case
- assign $2\r1__data_o$next[3:0]$10903 4'0000
+ assign $2\r1__data_o$next[3:0]$10811 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r1__data_o$next[3:0]$10904 \dest21__data_i
+ assign $3\r1__data_o$next[3:0]$10812 \dest21__data_i
case
- assign $3\r1__data_o$next[3:0]$10904 $2\r1__data_o$next[3:0]$10903
+ assign $3\r1__data_o$next[3:0]$10812 $2\r1__data_o$next[3:0]$10811
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r1__data_o$next[3:0]$10905 \w1__data_i
+ assign $4\r1__data_o$next[3:0]$10813 \w1__data_i
case
- assign $4\r1__data_o$next[3:0]$10905 $3\r1__data_o$next[3:0]$10904
+ assign $4\r1__data_o$next[3:0]$10813 $3\r1__data_o$next[3:0]$10812
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r1__data_o$next[3:0]$10906 \reg
+ assign $5\r1__data_o$next[3:0]$10814 \reg
case
- assign $5\r1__data_o$next[3:0]$10906 $4\r1__data_o$next[3:0]$10905
+ assign $5\r1__data_o$next[3:0]$10814 $4\r1__data_o$next[3:0]$10813
end
case
- assign $1\r1__data_o$next[3:0]$10902 4'0000
+ assign $1\r1__data_o$next[3:0]$10810 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r1__data_o$next[3:0]$10907 4'0000
+ assign $6\r1__data_o$next[3:0]$10815 4'0000
case
- assign $6\r1__data_o$next[3:0]$10907 $1\r1__data_o$next[3:0]$10902
+ assign $6\r1__data_o$next[3:0]$10815 $1\r1__data_o$next[3:0]$10810
end
sync always
- update \r1__data_o$next $0\r1__data_o$next[3:0]$10901
+ update \r1__data_o$next $0\r1__data_o$next[3:0]$10809
end
- attribute \src "libresoc.v:176947.3-176976.6"
- process $proc$libresoc.v:176947$10908
+ attribute \src "libresoc.v:174700.3-174729.6"
+ process $proc$libresoc.v:174700$10816
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10909 $1\wr_detect$10[0:0]$10910
- attribute \src "libresoc.v:176948.5-176948.29"
+ assign $0\wr_detect$10[0:0]$10817 $1\wr_detect$10[0:0]$10818
+ attribute \src "libresoc.v:174701.5-174701.29"
switch \initial
- attribute \src "libresoc.v:176948.9-176948.17"
+ attribute \src "libresoc.v:174701.9-174701.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10910 $4\wr_detect$10[0:0]$10913
+ assign $1\wr_detect$10[0:0]$10818 $4\wr_detect$10[0:0]$10821
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10911 1'1
+ assign $2\wr_detect$10[0:0]$10819 1'1
case
- assign $2\wr_detect$10[0:0]$10911 1'0
+ assign $2\wr_detect$10[0:0]$10819 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10912 1'1
+ assign $3\wr_detect$10[0:0]$10820 1'1
case
- assign $3\wr_detect$10[0:0]$10912 $2\wr_detect$10[0:0]$10911
+ assign $3\wr_detect$10[0:0]$10820 $2\wr_detect$10[0:0]$10819
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$10913 1'1
+ assign $4\wr_detect$10[0:0]$10821 1'1
case
- assign $4\wr_detect$10[0:0]$10913 $3\wr_detect$10[0:0]$10912
+ assign $4\wr_detect$10[0:0]$10821 $3\wr_detect$10[0:0]$10820
end
case
- assign $1\wr_detect$10[0:0]$10910 1'0
+ assign $1\wr_detect$10[0:0]$10818 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10909
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10817
end
- attribute \src "libresoc.v:176977.3-177016.6"
- process $proc$libresoc.v:176977$10914
+ attribute \src "libresoc.v:174730.3-174769.6"
+ process $proc$libresoc.v:174730$10822
assign { } { }
assign { } { }
assign { } { }
- assign $0\r21__data_o$next[3:0]$10915 $6\r21__data_o$next[3:0]$10921
- attribute \src "libresoc.v:176978.5-176978.29"
+ assign $0\r21__data_o$next[3:0]$10823 $6\r21__data_o$next[3:0]$10829
+ attribute \src "libresoc.v:174731.5-174731.29"
switch \initial
- attribute \src "libresoc.v:176978.9-176978.17"
+ attribute \src "libresoc.v:174731.9-174731.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r21__data_o$next[3:0]$10916 $5\r21__data_o$next[3:0]$10920
+ assign $1\r21__data_o$next[3:0]$10824 $5\r21__data_o$next[3:0]$10828
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r21__data_o$next[3:0]$10917 \dest11__data_i
+ assign $2\r21__data_o$next[3:0]$10825 \dest11__data_i
case
- assign $2\r21__data_o$next[3:0]$10917 4'0000
+ assign $2\r21__data_o$next[3:0]$10825 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r21__data_o$next[3:0]$10918 \dest21__data_i
+ assign $3\r21__data_o$next[3:0]$10826 \dest21__data_i
case
- assign $3\r21__data_o$next[3:0]$10918 $2\r21__data_o$next[3:0]$10917
+ assign $3\r21__data_o$next[3:0]$10826 $2\r21__data_o$next[3:0]$10825
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r21__data_o$next[3:0]$10919 \w1__data_i
+ assign $4\r21__data_o$next[3:0]$10827 \w1__data_i
case
- assign $4\r21__data_o$next[3:0]$10919 $3\r21__data_o$next[3:0]$10918
+ assign $4\r21__data_o$next[3:0]$10827 $3\r21__data_o$next[3:0]$10826
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r21__data_o$next[3:0]$10920 \reg
+ assign $5\r21__data_o$next[3:0]$10828 \reg
case
- assign $5\r21__data_o$next[3:0]$10920 $4\r21__data_o$next[3:0]$10919
+ assign $5\r21__data_o$next[3:0]$10828 $4\r21__data_o$next[3:0]$10827
end
case
- assign $1\r21__data_o$next[3:0]$10916 4'0000
+ assign $1\r21__data_o$next[3:0]$10824 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r21__data_o$next[3:0]$10921 4'0000
+ assign $6\r21__data_o$next[3:0]$10829 4'0000
case
- assign $6\r21__data_o$next[3:0]$10921 $1\r21__data_o$next[3:0]$10916
+ assign $6\r21__data_o$next[3:0]$10829 $1\r21__data_o$next[3:0]$10824
end
sync always
- update \r21__data_o$next $0\r21__data_o$next[3:0]$10915
+ update \r21__data_o$next $0\r21__data_o$next[3:0]$10823
end
- attribute \src "libresoc.v:177017.3-177046.6"
- process $proc$libresoc.v:177017$10922
+ attribute \src "libresoc.v:174770.3-174799.6"
+ process $proc$libresoc.v:174770$10830
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$10923 $1\wr_detect$13[0:0]$10924
- attribute \src "libresoc.v:177018.5-177018.29"
+ assign $0\wr_detect$13[0:0]$10831 $1\wr_detect$13[0:0]$10832
+ attribute \src "libresoc.v:174771.5-174771.29"
switch \initial
- attribute \src "libresoc.v:177018.9-177018.17"
+ attribute \src "libresoc.v:174771.9-174771.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$10924 $4\wr_detect$13[0:0]$10927
+ assign $1\wr_detect$13[0:0]$10832 $4\wr_detect$13[0:0]$10835
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$10925 1'1
+ assign $2\wr_detect$13[0:0]$10833 1'1
case
- assign $2\wr_detect$13[0:0]$10925 1'0
+ assign $2\wr_detect$13[0:0]$10833 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$10926 1'1
+ assign $3\wr_detect$13[0:0]$10834 1'1
case
- assign $3\wr_detect$13[0:0]$10926 $2\wr_detect$13[0:0]$10925
+ assign $3\wr_detect$13[0:0]$10834 $2\wr_detect$13[0:0]$10833
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$10927 1'1
+ assign $4\wr_detect$13[0:0]$10835 1'1
case
- assign $4\wr_detect$13[0:0]$10927 $3\wr_detect$13[0:0]$10926
+ assign $4\wr_detect$13[0:0]$10835 $3\wr_detect$13[0:0]$10834
end
case
- assign $1\wr_detect$13[0:0]$10924 1'0
+ assign $1\wr_detect$13[0:0]$10832 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$10923
+ update \wr_detect$13 $0\wr_detect$13[0:0]$10831
end
- connect \$9 $not$libresoc.v:176653$10846_Y
- connect \$12 $not$libresoc.v:176654$10847_Y
- connect \$1 $not$libresoc.v:176655$10848_Y
- connect \$3 $not$libresoc.v:176656$10849_Y
- connect \$6 $not$libresoc.v:176657$10850_Y
+ connect \$9 $not$libresoc.v:174406$10754_Y
+ connect \$12 $not$libresoc.v:174407$10755_Y
+ connect \$1 $not$libresoc.v:174408$10756_Y
+ connect \$3 $not$libresoc.v:174409$10757_Y
+ connect \$6 $not$libresoc.v:174410$10758_Y
end
-attribute \src "libresoc.v:177051.1-177496.10"
+attribute \src "libresoc.v:174804.1-175249.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1"
attribute \generator "nMigen"
module \reg_1$133
- attribute \src "libresoc.v:177052.7-177052.20"
+ attribute \src "libresoc.v:174805.7-174805.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $0\r1__data_o$next[1:0]$10987
- attribute \src "libresoc.v:177127.3-177128.37"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $0\r1__data_o$next[1:0]$10895
+ attribute \src "libresoc.v:174880.3-174881.37"
wire width 2 $0\r1__data_o[1:0]
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $0\reg$next[1:0]$11003
- attribute \src "libresoc.v:177125.3-177126.25"
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $0\reg$next[1:0]$10911
+ attribute \src "libresoc.v:174878.3-174879.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $0\src11__data_o$next[1:0]$10945
- attribute \src "libresoc.v:177133.3-177134.43"
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $0\src11__data_o$next[1:0]$10853
+ attribute \src "libresoc.v:174886.3-174887.43"
wire width 2 $0\src11__data_o[1:0]
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $0\src21__data_o$next[1:0]$10955
- attribute \src "libresoc.v:177131.3-177132.43"
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $0\src21__data_o$next[1:0]$10863
+ attribute \src "libresoc.v:174884.3-174885.43"
wire width 2 $0\src21__data_o[1:0]
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $0\src31__data_o$next[1:0]$10971
- attribute \src "libresoc.v:177129.3-177130.43"
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $0\src31__data_o$next[1:0]$10879
+ attribute \src "libresoc.v:174882.3-174883.43"
wire width 2 $0\src31__data_o[1:0]
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $0\wr_detect$10[0:0]$10996
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $0\wr_detect$4[0:0]$10964
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $0\wr_detect$7[0:0]$10980
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $0\wr_detect$10[0:0]$10904
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $0\wr_detect$4[0:0]$10872
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $0\wr_detect$7[0:0]$10888
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $1\r1__data_o$next[1:0]$10988
- attribute \src "libresoc.v:177079.13-177079.30"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $1\r1__data_o$next[1:0]$10896
+ attribute \src "libresoc.v:174832.13-174832.30"
wire width 2 $1\r1__data_o[1:0]
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $1\reg$next[1:0]$11004
- attribute \src "libresoc.v:177085.13-177085.25"
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $1\reg$next[1:0]$10912
+ attribute \src "libresoc.v:174838.13-174838.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $1\src11__data_o$next[1:0]$10946
- attribute \src "libresoc.v:177090.13-177090.33"
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $1\src11__data_o$next[1:0]$10854
+ attribute \src "libresoc.v:174843.13-174843.33"
wire width 2 $1\src11__data_o[1:0]
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $1\src21__data_o$next[1:0]$10956
- attribute \src "libresoc.v:177097.13-177097.33"
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $1\src21__data_o$next[1:0]$10864
+ attribute \src "libresoc.v:174850.13-174850.33"
wire width 2 $1\src21__data_o[1:0]
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $1\src31__data_o$next[1:0]$10972
- attribute \src "libresoc.v:177104.13-177104.33"
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $1\src31__data_o$next[1:0]$10880
+ attribute \src "libresoc.v:174857.13-174857.33"
wire width 2 $1\src31__data_o[1:0]
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $1\wr_detect$10[0:0]$10997
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $1\wr_detect$4[0:0]$10965
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $1\wr_detect$7[0:0]$10981
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $1\wr_detect$10[0:0]$10905
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $1\wr_detect$4[0:0]$10873
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $1\wr_detect$7[0:0]$10889
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $2\r1__data_o$next[1:0]$10989
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $2\reg$next[1:0]$11005
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $2\src11__data_o$next[1:0]$10947
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $2\src21__data_o$next[1:0]$10957
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $2\src31__data_o$next[1:0]$10973
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $2\wr_detect$10[0:0]$10998
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $2\wr_detect$4[0:0]$10966
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $2\wr_detect$7[0:0]$10982
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $2\r1__data_o$next[1:0]$10897
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $2\reg$next[1:0]$10913
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $2\src11__data_o$next[1:0]$10855
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $2\src21__data_o$next[1:0]$10865
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $2\src31__data_o$next[1:0]$10881
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $2\wr_detect$10[0:0]$10906
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $2\wr_detect$4[0:0]$10874
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $2\wr_detect$7[0:0]$10890
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $3\r1__data_o$next[1:0]$10990
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $3\reg$next[1:0]$11006
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $3\src11__data_o$next[1:0]$10948
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $3\src21__data_o$next[1:0]$10958
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $3\src31__data_o$next[1:0]$10974
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $3\wr_detect$10[0:0]$10999
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $3\wr_detect$4[0:0]$10967
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $3\wr_detect$7[0:0]$10983
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $3\r1__data_o$next[1:0]$10898
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $3\reg$next[1:0]$10914
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $3\src11__data_o$next[1:0]$10856
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $3\src21__data_o$next[1:0]$10866
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $3\src31__data_o$next[1:0]$10882
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $3\wr_detect$10[0:0]$10907
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $3\wr_detect$4[0:0]$10875
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $3\wr_detect$7[0:0]$10891
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $4\r1__data_o$next[1:0]$10991
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $4\reg$next[1:0]$11007
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $4\src11__data_o$next[1:0]$10949
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $4\src21__data_o$next[1:0]$10959
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $4\src31__data_o$next[1:0]$10975
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $4\wr_detect$10[0:0]$11000
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $4\wr_detect$4[0:0]$10968
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $4\wr_detect$7[0:0]$10984
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $4\r1__data_o$next[1:0]$10899
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $4\reg$next[1:0]$10915
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $4\src11__data_o$next[1:0]$10857
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $4\src21__data_o$next[1:0]$10867
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $4\src31__data_o$next[1:0]$10883
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $4\wr_detect$10[0:0]$10908
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $4\wr_detect$4[0:0]$10876
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $4\wr_detect$7[0:0]$10892
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $5\r1__data_o$next[1:0]$10992
- attribute \src "libresoc.v:177463.3-177495.6"
- wire width 2 $5\reg$next[1:0]$11008
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $5\src11__data_o$next[1:0]$10950
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $5\src21__data_o$next[1:0]$10960
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $5\src31__data_o$next[1:0]$10976
- attribute \src "libresoc.v:177427.3-177462.6"
- wire $5\wr_detect$10[0:0]$11001
- attribute \src "libresoc.v:177263.3-177298.6"
- wire $5\wr_detect$4[0:0]$10969
- attribute \src "libresoc.v:177345.3-177380.6"
- wire $5\wr_detect$7[0:0]$10985
- attribute \src "libresoc.v:177181.3-177216.6"
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $5\r1__data_o$next[1:0]$10900
+ attribute \src "libresoc.v:175216.3-175248.6"
+ wire width 2 $5\reg$next[1:0]$10916
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $5\src11__data_o$next[1:0]$10858
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $5\src21__data_o$next[1:0]$10868
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $5\src31__data_o$next[1:0]$10884
+ attribute \src "libresoc.v:175180.3-175215.6"
+ wire $5\wr_detect$10[0:0]$10909
+ attribute \src "libresoc.v:175016.3-175051.6"
+ wire $5\wr_detect$4[0:0]$10877
+ attribute \src "libresoc.v:175098.3-175133.6"
+ wire $5\wr_detect$7[0:0]$10893
+ attribute \src "libresoc.v:174934.3-174969.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $6\r1__data_o$next[1:0]$10993
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $6\src11__data_o$next[1:0]$10951
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $6\src21__data_o$next[1:0]$10961
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $6\src31__data_o$next[1:0]$10977
- attribute \src "libresoc.v:177381.3-177426.6"
- wire width 2 $7\r1__data_o$next[1:0]$10994
- attribute \src "libresoc.v:177135.3-177180.6"
- wire width 2 $7\src11__data_o$next[1:0]$10952
- attribute \src "libresoc.v:177217.3-177262.6"
- wire width 2 $7\src21__data_o$next[1:0]$10962
- attribute \src "libresoc.v:177299.3-177344.6"
- wire width 2 $7\src31__data_o$next[1:0]$10978
- attribute \src "libresoc.v:177121.17-177121.104"
- wire $not$libresoc.v:177121$10935_Y
- attribute \src "libresoc.v:177122.17-177122.100"
- wire $not$libresoc.v:177122$10936_Y
- attribute \src "libresoc.v:177123.17-177123.103"
- wire $not$libresoc.v:177123$10937_Y
- attribute \src "libresoc.v:177124.17-177124.103"
- wire $not$libresoc.v:177124$10938_Y
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $6\r1__data_o$next[1:0]$10901
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $6\src11__data_o$next[1:0]$10859
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $6\src21__data_o$next[1:0]$10869
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $6\src31__data_o$next[1:0]$10885
+ attribute \src "libresoc.v:175134.3-175179.6"
+ wire width 2 $7\r1__data_o$next[1:0]$10902
+ attribute \src "libresoc.v:174888.3-174933.6"
+ wire width 2 $7\src11__data_o$next[1:0]$10860
+ attribute \src "libresoc.v:174970.3-175015.6"
+ wire width 2 $7\src21__data_o$next[1:0]$10870
+ attribute \src "libresoc.v:175052.3-175097.6"
+ wire width 2 $7\src31__data_o$next[1:0]$10886
+ attribute \src "libresoc.v:174874.17-174874.104"
+ wire $not$libresoc.v:174874$10843_Y
+ attribute \src "libresoc.v:174875.17-174875.100"
+ wire $not$libresoc.v:174875$10844_Y
+ attribute \src "libresoc.v:174876.17-174876.103"
+ wire $not$libresoc.v:174876$10845_Y
+ attribute \src "libresoc.v:174877.17-174877.103"
+ wire $not$libresoc.v:174877$10846_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest11__data_i
wire width 2 input 13 \dest31__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest31__wen
- attribute \src "libresoc.v:177052.7-177052.15"
+ attribute \src "libresoc.v:174805.7-174805.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r1__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177121$10935
+ cell $not $not$libresoc.v:174874$10843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:177121$10935_Y
+ connect \Y $not$libresoc.v:174874$10843_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177122$10936
+ cell $not $not$libresoc.v:174875$10844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:177122$10936_Y
+ connect \Y $not$libresoc.v:174875$10844_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177123$10937
+ cell $not $not$libresoc.v:174876$10845
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:177123$10937_Y
+ connect \Y $not$libresoc.v:174876$10845_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177124$10938
+ cell $not $not$libresoc.v:174877$10846
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:177124$10938_Y
+ connect \Y $not$libresoc.v:174877$10846_Y
end
- attribute \src "libresoc.v:177052.7-177052.20"
- process $proc$libresoc.v:177052$11009
+ attribute \src "libresoc.v:174805.7-174805.20"
+ process $proc$libresoc.v:174805$10917
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:177079.13-177079.30"
- process $proc$libresoc.v:177079$11010
+ attribute \src "libresoc.v:174832.13-174832.30"
+ process $proc$libresoc.v:174832$10918
assign { } { }
assign $1\r1__data_o[1:0] 2'00
sync always
sync init
update \r1__data_o $1\r1__data_o[1:0]
end
- attribute \src "libresoc.v:177085.13-177085.25"
- process $proc$libresoc.v:177085$11011
+ attribute \src "libresoc.v:174838.13-174838.25"
+ process $proc$libresoc.v:174838$10919
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:177090.13-177090.33"
- process $proc$libresoc.v:177090$11012
+ attribute \src "libresoc.v:174843.13-174843.33"
+ process $proc$libresoc.v:174843$10920
assign { } { }
assign $1\src11__data_o[1:0] 2'00
sync always
sync init
update \src11__data_o $1\src11__data_o[1:0]
end
- attribute \src "libresoc.v:177097.13-177097.33"
- process $proc$libresoc.v:177097$11013
+ attribute \src "libresoc.v:174850.13-174850.33"
+ process $proc$libresoc.v:174850$10921
assign { } { }
assign $1\src21__data_o[1:0] 2'00
sync always
sync init
update \src21__data_o $1\src21__data_o[1:0]
end
- attribute \src "libresoc.v:177104.13-177104.33"
- process $proc$libresoc.v:177104$11014
+ attribute \src "libresoc.v:174857.13-174857.33"
+ process $proc$libresoc.v:174857$10922
assign { } { }
assign $1\src31__data_o[1:0] 2'00
sync always
sync init
update \src31__data_o $1\src31__data_o[1:0]
end
- attribute \src "libresoc.v:177125.3-177126.25"
- process $proc$libresoc.v:177125$10939
+ attribute \src "libresoc.v:174878.3-174879.25"
+ process $proc$libresoc.v:174878$10847
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:177127.3-177128.37"
- process $proc$libresoc.v:177127$10940
+ attribute \src "libresoc.v:174880.3-174881.37"
+ process $proc$libresoc.v:174880$10848
assign { } { }
assign $0\r1__data_o[1:0] \r1__data_o$next
sync posedge \coresync_clk
update \r1__data_o $0\r1__data_o[1:0]
end
- attribute \src "libresoc.v:177129.3-177130.43"
- process $proc$libresoc.v:177129$10941
+ attribute \src "libresoc.v:174882.3-174883.43"
+ process $proc$libresoc.v:174882$10849
assign { } { }
assign $0\src31__data_o[1:0] \src31__data_o$next
sync posedge \coresync_clk
update \src31__data_o $0\src31__data_o[1:0]
end
- attribute \src "libresoc.v:177131.3-177132.43"
- process $proc$libresoc.v:177131$10942
+ attribute \src "libresoc.v:174884.3-174885.43"
+ process $proc$libresoc.v:174884$10850
assign { } { }
assign $0\src21__data_o[1:0] \src21__data_o$next
sync posedge \coresync_clk
update \src21__data_o $0\src21__data_o[1:0]
end
- attribute \src "libresoc.v:177133.3-177134.43"
- process $proc$libresoc.v:177133$10943
+ attribute \src "libresoc.v:174886.3-174887.43"
+ process $proc$libresoc.v:174886$10851
assign { } { }
assign $0\src11__data_o[1:0] \src11__data_o$next
sync posedge \coresync_clk
update \src11__data_o $0\src11__data_o[1:0]
end
- attribute \src "libresoc.v:177135.3-177180.6"
- process $proc$libresoc.v:177135$10944
+ attribute \src "libresoc.v:174888.3-174933.6"
+ process $proc$libresoc.v:174888$10852
assign { } { }
assign { } { }
assign { } { }
- assign $0\src11__data_o$next[1:0]$10945 $7\src11__data_o$next[1:0]$10952
- attribute \src "libresoc.v:177136.5-177136.29"
+ assign $0\src11__data_o$next[1:0]$10853 $7\src11__data_o$next[1:0]$10860
+ attribute \src "libresoc.v:174889.5-174889.29"
switch \initial
- attribute \src "libresoc.v:177136.9-177136.17"
+ attribute \src "libresoc.v:174889.9-174889.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src11__data_o$next[1:0]$10946 $6\src11__data_o$next[1:0]$10951
+ assign $1\src11__data_o$next[1:0]$10854 $6\src11__data_o$next[1:0]$10859
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src11__data_o$next[1:0]$10947 \dest11__data_i
+ assign $2\src11__data_o$next[1:0]$10855 \dest11__data_i
case
- assign $2\src11__data_o$next[1:0]$10947 2'00
+ assign $2\src11__data_o$next[1:0]$10855 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src11__data_o$next[1:0]$10948 \dest21__data_i
+ assign $3\src11__data_o$next[1:0]$10856 \dest21__data_i
case
- assign $3\src11__data_o$next[1:0]$10948 $2\src11__data_o$next[1:0]$10947
+ assign $3\src11__data_o$next[1:0]$10856 $2\src11__data_o$next[1:0]$10855
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src11__data_o$next[1:0]$10949 \dest31__data_i
+ assign $4\src11__data_o$next[1:0]$10857 \dest31__data_i
case
- assign $4\src11__data_o$next[1:0]$10949 $3\src11__data_o$next[1:0]$10948
+ assign $4\src11__data_o$next[1:0]$10857 $3\src11__data_o$next[1:0]$10856
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src11__data_o$next[1:0]$10950 \w1__data_i
+ assign $5\src11__data_o$next[1:0]$10858 \w1__data_i
case
- assign $5\src11__data_o$next[1:0]$10950 $4\src11__data_o$next[1:0]$10949
+ assign $5\src11__data_o$next[1:0]$10858 $4\src11__data_o$next[1:0]$10857
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src11__data_o$next[1:0]$10951 \reg
+ assign $6\src11__data_o$next[1:0]$10859 \reg
case
- assign $6\src11__data_o$next[1:0]$10951 $5\src11__data_o$next[1:0]$10950
+ assign $6\src11__data_o$next[1:0]$10859 $5\src11__data_o$next[1:0]$10858
end
case
- assign $1\src11__data_o$next[1:0]$10946 2'00
+ assign $1\src11__data_o$next[1:0]$10854 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src11__data_o$next[1:0]$10952 2'00
+ assign $7\src11__data_o$next[1:0]$10860 2'00
case
- assign $7\src11__data_o$next[1:0]$10952 $1\src11__data_o$next[1:0]$10946
+ assign $7\src11__data_o$next[1:0]$10860 $1\src11__data_o$next[1:0]$10854
end
sync always
- update \src11__data_o$next $0\src11__data_o$next[1:0]$10945
+ update \src11__data_o$next $0\src11__data_o$next[1:0]$10853
end
- attribute \src "libresoc.v:177181.3-177216.6"
- process $proc$libresoc.v:177181$10953
+ attribute \src "libresoc.v:174934.3-174969.6"
+ process $proc$libresoc.v:174934$10861
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:177182.5-177182.29"
+ attribute \src "libresoc.v:174935.5-174935.29"
switch \initial
- attribute \src "libresoc.v:177182.9-177182.17"
+ attribute \src "libresoc.v:174935.9-174935.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:177217.3-177262.6"
- process $proc$libresoc.v:177217$10954
+ attribute \src "libresoc.v:174970.3-175015.6"
+ process $proc$libresoc.v:174970$10862
assign { } { }
assign { } { }
assign { } { }
- assign $0\src21__data_o$next[1:0]$10955 $7\src21__data_o$next[1:0]$10962
- attribute \src "libresoc.v:177218.5-177218.29"
+ assign $0\src21__data_o$next[1:0]$10863 $7\src21__data_o$next[1:0]$10870
+ attribute \src "libresoc.v:174971.5-174971.29"
switch \initial
- attribute \src "libresoc.v:177218.9-177218.17"
+ attribute \src "libresoc.v:174971.9-174971.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src21__data_o$next[1:0]$10956 $6\src21__data_o$next[1:0]$10961
+ assign $1\src21__data_o$next[1:0]$10864 $6\src21__data_o$next[1:0]$10869
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src21__data_o$next[1:0]$10957 \dest11__data_i
+ assign $2\src21__data_o$next[1:0]$10865 \dest11__data_i
case
- assign $2\src21__data_o$next[1:0]$10957 2'00
+ assign $2\src21__data_o$next[1:0]$10865 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src21__data_o$next[1:0]$10958 \dest21__data_i
+ assign $3\src21__data_o$next[1:0]$10866 \dest21__data_i
case
- assign $3\src21__data_o$next[1:0]$10958 $2\src21__data_o$next[1:0]$10957
+ assign $3\src21__data_o$next[1:0]$10866 $2\src21__data_o$next[1:0]$10865
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src21__data_o$next[1:0]$10959 \dest31__data_i
+ assign $4\src21__data_o$next[1:0]$10867 \dest31__data_i
case
- assign $4\src21__data_o$next[1:0]$10959 $3\src21__data_o$next[1:0]$10958
+ assign $4\src21__data_o$next[1:0]$10867 $3\src21__data_o$next[1:0]$10866
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src21__data_o$next[1:0]$10960 \w1__data_i
+ assign $5\src21__data_o$next[1:0]$10868 \w1__data_i
case
- assign $5\src21__data_o$next[1:0]$10960 $4\src21__data_o$next[1:0]$10959
+ assign $5\src21__data_o$next[1:0]$10868 $4\src21__data_o$next[1:0]$10867
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src21__data_o$next[1:0]$10961 \reg
+ assign $6\src21__data_o$next[1:0]$10869 \reg
case
- assign $6\src21__data_o$next[1:0]$10961 $5\src21__data_o$next[1:0]$10960
+ assign $6\src21__data_o$next[1:0]$10869 $5\src21__data_o$next[1:0]$10868
end
case
- assign $1\src21__data_o$next[1:0]$10956 2'00
+ assign $1\src21__data_o$next[1:0]$10864 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src21__data_o$next[1:0]$10962 2'00
+ assign $7\src21__data_o$next[1:0]$10870 2'00
case
- assign $7\src21__data_o$next[1:0]$10962 $1\src21__data_o$next[1:0]$10956
+ assign $7\src21__data_o$next[1:0]$10870 $1\src21__data_o$next[1:0]$10864
end
sync always
- update \src21__data_o$next $0\src21__data_o$next[1:0]$10955
+ update \src21__data_o$next $0\src21__data_o$next[1:0]$10863
end
- attribute \src "libresoc.v:177263.3-177298.6"
- process $proc$libresoc.v:177263$10963
+ attribute \src "libresoc.v:175016.3-175051.6"
+ process $proc$libresoc.v:175016$10871
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$10964 $1\wr_detect$4[0:0]$10965
- attribute \src "libresoc.v:177264.5-177264.29"
+ assign $0\wr_detect$4[0:0]$10872 $1\wr_detect$4[0:0]$10873
+ attribute \src "libresoc.v:175017.5-175017.29"
switch \initial
- attribute \src "libresoc.v:177264.9-177264.17"
+ attribute \src "libresoc.v:175017.9-175017.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$10965 $5\wr_detect$4[0:0]$10969
+ assign $1\wr_detect$4[0:0]$10873 $5\wr_detect$4[0:0]$10877
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$10966 1'1
+ assign $2\wr_detect$4[0:0]$10874 1'1
case
- assign $2\wr_detect$4[0:0]$10966 1'0
+ assign $2\wr_detect$4[0:0]$10874 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$10967 1'1
+ assign $3\wr_detect$4[0:0]$10875 1'1
case
- assign $3\wr_detect$4[0:0]$10967 $2\wr_detect$4[0:0]$10966
+ assign $3\wr_detect$4[0:0]$10875 $2\wr_detect$4[0:0]$10874
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$10968 1'1
+ assign $4\wr_detect$4[0:0]$10876 1'1
case
- assign $4\wr_detect$4[0:0]$10968 $3\wr_detect$4[0:0]$10967
+ assign $4\wr_detect$4[0:0]$10876 $3\wr_detect$4[0:0]$10875
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$10969 1'1
+ assign $5\wr_detect$4[0:0]$10877 1'1
case
- assign $5\wr_detect$4[0:0]$10969 $4\wr_detect$4[0:0]$10968
+ assign $5\wr_detect$4[0:0]$10877 $4\wr_detect$4[0:0]$10876
end
case
- assign $1\wr_detect$4[0:0]$10965 1'0
+ assign $1\wr_detect$4[0:0]$10873 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$10964
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10872
end
- attribute \src "libresoc.v:177299.3-177344.6"
- process $proc$libresoc.v:177299$10970
+ attribute \src "libresoc.v:175052.3-175097.6"
+ process $proc$libresoc.v:175052$10878
assign { } { }
assign { } { }
assign { } { }
- assign $0\src31__data_o$next[1:0]$10971 $7\src31__data_o$next[1:0]$10978
- attribute \src "libresoc.v:177300.5-177300.29"
+ assign $0\src31__data_o$next[1:0]$10879 $7\src31__data_o$next[1:0]$10886
+ attribute \src "libresoc.v:175053.5-175053.29"
switch \initial
- attribute \src "libresoc.v:177300.9-177300.17"
+ attribute \src "libresoc.v:175053.9-175053.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src31__data_o$next[1:0]$10972 $6\src31__data_o$next[1:0]$10977
+ assign $1\src31__data_o$next[1:0]$10880 $6\src31__data_o$next[1:0]$10885
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src31__data_o$next[1:0]$10973 \dest11__data_i
+ assign $2\src31__data_o$next[1:0]$10881 \dest11__data_i
case
- assign $2\src31__data_o$next[1:0]$10973 2'00
+ assign $2\src31__data_o$next[1:0]$10881 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src31__data_o$next[1:0]$10974 \dest21__data_i
+ assign $3\src31__data_o$next[1:0]$10882 \dest21__data_i
case
- assign $3\src31__data_o$next[1:0]$10974 $2\src31__data_o$next[1:0]$10973
+ assign $3\src31__data_o$next[1:0]$10882 $2\src31__data_o$next[1:0]$10881
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src31__data_o$next[1:0]$10975 \dest31__data_i
+ assign $4\src31__data_o$next[1:0]$10883 \dest31__data_i
case
- assign $4\src31__data_o$next[1:0]$10975 $3\src31__data_o$next[1:0]$10974
+ assign $4\src31__data_o$next[1:0]$10883 $3\src31__data_o$next[1:0]$10882
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src31__data_o$next[1:0]$10976 \w1__data_i
+ assign $5\src31__data_o$next[1:0]$10884 \w1__data_i
case
- assign $5\src31__data_o$next[1:0]$10976 $4\src31__data_o$next[1:0]$10975
+ assign $5\src31__data_o$next[1:0]$10884 $4\src31__data_o$next[1:0]$10883
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src31__data_o$next[1:0]$10977 \reg
+ assign $6\src31__data_o$next[1:0]$10885 \reg
case
- assign $6\src31__data_o$next[1:0]$10977 $5\src31__data_o$next[1:0]$10976
+ assign $6\src31__data_o$next[1:0]$10885 $5\src31__data_o$next[1:0]$10884
end
case
- assign $1\src31__data_o$next[1:0]$10972 2'00
+ assign $1\src31__data_o$next[1:0]$10880 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src31__data_o$next[1:0]$10978 2'00
+ assign $7\src31__data_o$next[1:0]$10886 2'00
case
- assign $7\src31__data_o$next[1:0]$10978 $1\src31__data_o$next[1:0]$10972
+ assign $7\src31__data_o$next[1:0]$10886 $1\src31__data_o$next[1:0]$10880
end
sync always
- update \src31__data_o$next $0\src31__data_o$next[1:0]$10971
+ update \src31__data_o$next $0\src31__data_o$next[1:0]$10879
end
- attribute \src "libresoc.v:177345.3-177380.6"
- process $proc$libresoc.v:177345$10979
+ attribute \src "libresoc.v:175098.3-175133.6"
+ process $proc$libresoc.v:175098$10887
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$10980 $1\wr_detect$7[0:0]$10981
- attribute \src "libresoc.v:177346.5-177346.29"
+ assign $0\wr_detect$7[0:0]$10888 $1\wr_detect$7[0:0]$10889
+ attribute \src "libresoc.v:175099.5-175099.29"
switch \initial
- attribute \src "libresoc.v:177346.9-177346.17"
+ attribute \src "libresoc.v:175099.9-175099.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$10981 $5\wr_detect$7[0:0]$10985
+ assign $1\wr_detect$7[0:0]$10889 $5\wr_detect$7[0:0]$10893
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$10982 1'1
+ assign $2\wr_detect$7[0:0]$10890 1'1
case
- assign $2\wr_detect$7[0:0]$10982 1'0
+ assign $2\wr_detect$7[0:0]$10890 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$10983 1'1
+ assign $3\wr_detect$7[0:0]$10891 1'1
case
- assign $3\wr_detect$7[0:0]$10983 $2\wr_detect$7[0:0]$10982
+ assign $3\wr_detect$7[0:0]$10891 $2\wr_detect$7[0:0]$10890
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$10984 1'1
+ assign $4\wr_detect$7[0:0]$10892 1'1
case
- assign $4\wr_detect$7[0:0]$10984 $3\wr_detect$7[0:0]$10983
+ assign $4\wr_detect$7[0:0]$10892 $3\wr_detect$7[0:0]$10891
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$10985 1'1
+ assign $5\wr_detect$7[0:0]$10893 1'1
case
- assign $5\wr_detect$7[0:0]$10985 $4\wr_detect$7[0:0]$10984
+ assign $5\wr_detect$7[0:0]$10893 $4\wr_detect$7[0:0]$10892
end
case
- assign $1\wr_detect$7[0:0]$10981 1'0
+ assign $1\wr_detect$7[0:0]$10889 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$10980
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10888
end
- attribute \src "libresoc.v:177381.3-177426.6"
- process $proc$libresoc.v:177381$10986
+ attribute \src "libresoc.v:175134.3-175179.6"
+ process $proc$libresoc.v:175134$10894
assign { } { }
assign { } { }
assign { } { }
- assign $0\r1__data_o$next[1:0]$10987 $7\r1__data_o$next[1:0]$10994
- attribute \src "libresoc.v:177382.5-177382.29"
+ assign $0\r1__data_o$next[1:0]$10895 $7\r1__data_o$next[1:0]$10902
+ attribute \src "libresoc.v:175135.5-175135.29"
switch \initial
- attribute \src "libresoc.v:177382.9-177382.17"
+ attribute \src "libresoc.v:175135.9-175135.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r1__data_o$next[1:0]$10988 $6\r1__data_o$next[1:0]$10993
+ assign $1\r1__data_o$next[1:0]$10896 $6\r1__data_o$next[1:0]$10901
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r1__data_o$next[1:0]$10989 \dest11__data_i
+ assign $2\r1__data_o$next[1:0]$10897 \dest11__data_i
case
- assign $2\r1__data_o$next[1:0]$10989 2'00
+ assign $2\r1__data_o$next[1:0]$10897 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r1__data_o$next[1:0]$10990 \dest21__data_i
+ assign $3\r1__data_o$next[1:0]$10898 \dest21__data_i
case
- assign $3\r1__data_o$next[1:0]$10990 $2\r1__data_o$next[1:0]$10989
+ assign $3\r1__data_o$next[1:0]$10898 $2\r1__data_o$next[1:0]$10897
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r1__data_o$next[1:0]$10991 \dest31__data_i
+ assign $4\r1__data_o$next[1:0]$10899 \dest31__data_i
case
- assign $4\r1__data_o$next[1:0]$10991 $3\r1__data_o$next[1:0]$10990
+ assign $4\r1__data_o$next[1:0]$10899 $3\r1__data_o$next[1:0]$10898
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r1__data_o$next[1:0]$10992 \w1__data_i
+ assign $5\r1__data_o$next[1:0]$10900 \w1__data_i
case
- assign $5\r1__data_o$next[1:0]$10992 $4\r1__data_o$next[1:0]$10991
+ assign $5\r1__data_o$next[1:0]$10900 $4\r1__data_o$next[1:0]$10899
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r1__data_o$next[1:0]$10993 \reg
+ assign $6\r1__data_o$next[1:0]$10901 \reg
case
- assign $6\r1__data_o$next[1:0]$10993 $5\r1__data_o$next[1:0]$10992
+ assign $6\r1__data_o$next[1:0]$10901 $5\r1__data_o$next[1:0]$10900
end
case
- assign $1\r1__data_o$next[1:0]$10988 2'00
+ assign $1\r1__data_o$next[1:0]$10896 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r1__data_o$next[1:0]$10994 2'00
+ assign $7\r1__data_o$next[1:0]$10902 2'00
case
- assign $7\r1__data_o$next[1:0]$10994 $1\r1__data_o$next[1:0]$10988
+ assign $7\r1__data_o$next[1:0]$10902 $1\r1__data_o$next[1:0]$10896
end
sync always
- update \r1__data_o$next $0\r1__data_o$next[1:0]$10987
+ update \r1__data_o$next $0\r1__data_o$next[1:0]$10895
end
- attribute \src "libresoc.v:177427.3-177462.6"
- process $proc$libresoc.v:177427$10995
+ attribute \src "libresoc.v:175180.3-175215.6"
+ process $proc$libresoc.v:175180$10903
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$10996 $1\wr_detect$10[0:0]$10997
- attribute \src "libresoc.v:177428.5-177428.29"
+ assign $0\wr_detect$10[0:0]$10904 $1\wr_detect$10[0:0]$10905
+ attribute \src "libresoc.v:175181.5-175181.29"
switch \initial
- attribute \src "libresoc.v:177428.9-177428.17"
+ attribute \src "libresoc.v:175181.9-175181.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$10997 $5\wr_detect$10[0:0]$11001
+ assign $1\wr_detect$10[0:0]$10905 $5\wr_detect$10[0:0]$10909
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$10998 1'1
+ assign $2\wr_detect$10[0:0]$10906 1'1
case
- assign $2\wr_detect$10[0:0]$10998 1'0
+ assign $2\wr_detect$10[0:0]$10906 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$10999 1'1
+ assign $3\wr_detect$10[0:0]$10907 1'1
case
- assign $3\wr_detect$10[0:0]$10999 $2\wr_detect$10[0:0]$10998
+ assign $3\wr_detect$10[0:0]$10907 $2\wr_detect$10[0:0]$10906
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11000 1'1
+ assign $4\wr_detect$10[0:0]$10908 1'1
case
- assign $4\wr_detect$10[0:0]$11000 $3\wr_detect$10[0:0]$10999
+ assign $4\wr_detect$10[0:0]$10908 $3\wr_detect$10[0:0]$10907
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$11001 1'1
+ assign $5\wr_detect$10[0:0]$10909 1'1
case
- assign $5\wr_detect$10[0:0]$11001 $4\wr_detect$10[0:0]$11000
+ assign $5\wr_detect$10[0:0]$10909 $4\wr_detect$10[0:0]$10908
end
case
- assign $1\wr_detect$10[0:0]$10997 1'0
+ assign $1\wr_detect$10[0:0]$10905 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$10996
+ update \wr_detect$10 $0\wr_detect$10[0:0]$10904
end
- attribute \src "libresoc.v:177463.3-177495.6"
- process $proc$libresoc.v:177463$11002
+ attribute \src "libresoc.v:175216.3-175248.6"
+ process $proc$libresoc.v:175216$10910
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$11003 $5\reg$next[1:0]$11008
- attribute \src "libresoc.v:177464.5-177464.29"
+ assign $0\reg$next[1:0]$10911 $5\reg$next[1:0]$10916
+ attribute \src "libresoc.v:175217.5-175217.29"
switch \initial
- attribute \src "libresoc.v:177464.9-177464.17"
+ attribute \src "libresoc.v:175217.9-175217.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$11004 \dest11__data_i
+ assign $1\reg$next[1:0]$10912 \dest11__data_i
case
- assign $1\reg$next[1:0]$11004 \reg
+ assign $1\reg$next[1:0]$10912 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest21__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$11005 \dest21__data_i
+ assign $2\reg$next[1:0]$10913 \dest21__data_i
case
- assign $2\reg$next[1:0]$11005 $1\reg$next[1:0]$11004
+ assign $2\reg$next[1:0]$10913 $1\reg$next[1:0]$10912
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest31__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$11006 \dest31__data_i
+ assign $3\reg$next[1:0]$10914 \dest31__data_i
case
- assign $3\reg$next[1:0]$11006 $2\reg$next[1:0]$11005
+ assign $3\reg$next[1:0]$10914 $2\reg$next[1:0]$10913
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$11007 \w1__data_i
+ assign $4\reg$next[1:0]$10915 \w1__data_i
case
- assign $4\reg$next[1:0]$11007 $3\reg$next[1:0]$11006
+ assign $4\reg$next[1:0]$10915 $3\reg$next[1:0]$10914
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$11008 2'00
+ assign $5\reg$next[1:0]$10916 2'00
case
- assign $5\reg$next[1:0]$11008 $4\reg$next[1:0]$11007
+ assign $5\reg$next[1:0]$10916 $4\reg$next[1:0]$10915
end
sync always
- update \reg$next $0\reg$next[1:0]$11003
+ update \reg$next $0\reg$next[1:0]$10911
end
- connect \$9 $not$libresoc.v:177121$10935_Y
- connect \$1 $not$libresoc.v:177122$10936_Y
- connect \$3 $not$libresoc.v:177123$10937_Y
- connect \$6 $not$libresoc.v:177124$10938_Y
+ connect \$9 $not$libresoc.v:174874$10843_Y
+ connect \$1 $not$libresoc.v:174875$10844_Y
+ connect \$3 $not$libresoc.v:174876$10845_Y
+ connect \$6 $not$libresoc.v:174877$10846_Y
end
-attribute \src "libresoc.v:177500.1-177849.10"
+attribute \src "libresoc.v:175253.1-175602.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1"
attribute \generator "nMigen"
module \reg_1$136
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $0\cia1__data_o$next[63:0]$11023
- attribute \src "libresoc.v:177568.3-177569.41"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $0\cia1__data_o$next[63:0]$10931
+ attribute \src "libresoc.v:175321.3-175322.41"
wire width 64 $0\cia1__data_o[63:0]
- attribute \src "libresoc.v:177501.7-177501.20"
+ attribute \src "libresoc.v:175254.7-175254.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $0\msr1__data_o$next[63:0]$11033
- attribute \src "libresoc.v:177566.3-177567.41"
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $0\msr1__data_o$next[63:0]$10941
+ attribute \src "libresoc.v:175319.3-175320.41"
wire width 64 $0\msr1__data_o[63:0]
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $0\reg$next[63:0]$11065
- attribute \src "libresoc.v:177562.3-177563.25"
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $0\reg$next[63:0]$10973
+ attribute \src "libresoc.v:175315.3-175316.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $0\sv1__data_o$next[63:0]$11049
- attribute \src "libresoc.v:177564.3-177565.39"
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $0\sv1__data_o$next[63:0]$10957
+ attribute \src "libresoc.v:175317.3-175318.39"
wire width 64 $0\sv1__data_o[63:0]
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $0\wr_detect$4[0:0]$11042
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $0\wr_detect$7[0:0]$11058
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $0\wr_detect$4[0:0]$10950
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $0\wr_detect$7[0:0]$10966
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $1\cia1__data_o$next[63:0]$11024
- attribute \src "libresoc.v:177510.14-177510.49"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $1\cia1__data_o$next[63:0]$10932
+ attribute \src "libresoc.v:175263.14-175263.49"
wire width 64 $1\cia1__data_o[63:0]
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $1\msr1__data_o$next[63:0]$11034
- attribute \src "libresoc.v:177527.14-177527.49"
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $1\msr1__data_o$next[63:0]$10942
+ attribute \src "libresoc.v:175280.14-175280.49"
wire width 64 $1\msr1__data_o[63:0]
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $1\reg$next[63:0]$11066
- attribute \src "libresoc.v:177539.14-177539.42"
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $1\reg$next[63:0]$10974
+ attribute \src "libresoc.v:175292.14-175292.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $1\sv1__data_o$next[63:0]$11050
- attribute \src "libresoc.v:177546.14-177546.48"
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $1\sv1__data_o$next[63:0]$10958
+ attribute \src "libresoc.v:175299.14-175299.48"
wire width 64 $1\sv1__data_o[63:0]
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $1\wr_detect$4[0:0]$11043
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $1\wr_detect$7[0:0]$11059
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $1\wr_detect$4[0:0]$10951
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $1\wr_detect$7[0:0]$10967
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $2\cia1__data_o$next[63:0]$11025
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $2\msr1__data_o$next[63:0]$11035
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $2\reg$next[63:0]$11067
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $2\sv1__data_o$next[63:0]$11051
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $2\wr_detect$4[0:0]$11044
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $2\wr_detect$7[0:0]$11060
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $2\cia1__data_o$next[63:0]$10933
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $2\msr1__data_o$next[63:0]$10943
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $2\reg$next[63:0]$10975
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $2\sv1__data_o$next[63:0]$10959
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $2\wr_detect$4[0:0]$10952
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $2\wr_detect$7[0:0]$10968
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $3\cia1__data_o$next[63:0]$11026
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $3\msr1__data_o$next[63:0]$11036
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $3\reg$next[63:0]$11068
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $3\sv1__data_o$next[63:0]$11052
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $3\wr_detect$4[0:0]$11045
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $3\wr_detect$7[0:0]$11061
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $3\cia1__data_o$next[63:0]$10934
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $3\msr1__data_o$next[63:0]$10944
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $3\reg$next[63:0]$10976
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $3\sv1__data_o$next[63:0]$10960
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $3\wr_detect$4[0:0]$10953
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $3\wr_detect$7[0:0]$10969
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $4\cia1__data_o$next[63:0]$11027
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $4\msr1__data_o$next[63:0]$11037
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $4\reg$next[63:0]$11069
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $4\sv1__data_o$next[63:0]$11053
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $4\wr_detect$4[0:0]$11046
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $4\wr_detect$7[0:0]$11062
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $4\cia1__data_o$next[63:0]$10935
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $4\msr1__data_o$next[63:0]$10945
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $4\reg$next[63:0]$10977
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $4\sv1__data_o$next[63:0]$10961
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $4\wr_detect$4[0:0]$10954
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $4\wr_detect$7[0:0]$10970
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $5\cia1__data_o$next[63:0]$11028
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $5\msr1__data_o$next[63:0]$11038
- attribute \src "libresoc.v:177816.3-177848.6"
- wire width 64 $5\reg$next[63:0]$11070
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $5\sv1__data_o$next[63:0]$11054
- attribute \src "libresoc.v:177698.3-177733.6"
- wire $5\wr_detect$4[0:0]$11047
- attribute \src "libresoc.v:177780.3-177815.6"
- wire $5\wr_detect$7[0:0]$11063
- attribute \src "libresoc.v:177616.3-177651.6"
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $5\cia1__data_o$next[63:0]$10936
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $5\msr1__data_o$next[63:0]$10946
+ attribute \src "libresoc.v:175569.3-175601.6"
+ wire width 64 $5\reg$next[63:0]$10978
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $5\sv1__data_o$next[63:0]$10962
+ attribute \src "libresoc.v:175451.3-175486.6"
+ wire $5\wr_detect$4[0:0]$10955
+ attribute \src "libresoc.v:175533.3-175568.6"
+ wire $5\wr_detect$7[0:0]$10971
+ attribute \src "libresoc.v:175369.3-175404.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $6\cia1__data_o$next[63:0]$11029
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $6\msr1__data_o$next[63:0]$11039
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $6\sv1__data_o$next[63:0]$11055
- attribute \src "libresoc.v:177570.3-177615.6"
- wire width 64 $7\cia1__data_o$next[63:0]$11030
- attribute \src "libresoc.v:177652.3-177697.6"
- wire width 64 $7\msr1__data_o$next[63:0]$11040
- attribute \src "libresoc.v:177734.3-177779.6"
- wire width 64 $7\sv1__data_o$next[63:0]$11056
- attribute \src "libresoc.v:177559.17-177559.100"
- wire $not$libresoc.v:177559$11015_Y
- attribute \src "libresoc.v:177560.17-177560.103"
- wire $not$libresoc.v:177560$11016_Y
- attribute \src "libresoc.v:177561.17-177561.103"
- wire $not$libresoc.v:177561$11017_Y
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $6\cia1__data_o$next[63:0]$10937
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $6\msr1__data_o$next[63:0]$10947
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $6\sv1__data_o$next[63:0]$10963
+ attribute \src "libresoc.v:175323.3-175368.6"
+ wire width 64 $7\cia1__data_o$next[63:0]$10938
+ attribute \src "libresoc.v:175405.3-175450.6"
+ wire width 64 $7\msr1__data_o$next[63:0]$10948
+ attribute \src "libresoc.v:175487.3-175532.6"
+ wire width 64 $7\sv1__data_o$next[63:0]$10964
+ attribute \src "libresoc.v:175312.17-175312.100"
+ wire $not$libresoc.v:175312$10923_Y
+ attribute \src "libresoc.v:175313.17-175313.103"
+ wire $not$libresoc.v:175313$10924_Y
+ attribute \src "libresoc.v:175314.17-175314.103"
+ wire $not$libresoc.v:175314$10925_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia1__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia1__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr11__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr11__wen
- attribute \src "libresoc.v:177501.7-177501.15"
+ attribute \src "libresoc.v:175254.7-175254.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr1__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177559$11015
+ cell $not $not$libresoc.v:175312$10923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:177559$11015_Y
+ connect \Y $not$libresoc.v:175312$10923_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177560$11016
+ cell $not $not$libresoc.v:175313$10924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:177560$11016_Y
+ connect \Y $not$libresoc.v:175313$10924_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177561$11017
+ cell $not $not$libresoc.v:175314$10925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:177561$11017_Y
+ connect \Y $not$libresoc.v:175314$10925_Y
end
- attribute \src "libresoc.v:177501.7-177501.20"
- process $proc$libresoc.v:177501$11071
+ attribute \src "libresoc.v:175254.7-175254.20"
+ process $proc$libresoc.v:175254$10979
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:177510.14-177510.49"
- process $proc$libresoc.v:177510$11072
+ attribute \src "libresoc.v:175263.14-175263.49"
+ process $proc$libresoc.v:175263$10980
assign { } { }
assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia1__data_o $1\cia1__data_o[63:0]
end
- attribute \src "libresoc.v:177527.14-177527.49"
- process $proc$libresoc.v:177527$11073
+ attribute \src "libresoc.v:175280.14-175280.49"
+ process $proc$libresoc.v:175280$10981
assign { } { }
assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr1__data_o $1\msr1__data_o[63:0]
end
- attribute \src "libresoc.v:177539.14-177539.42"
- process $proc$libresoc.v:177539$11074
+ attribute \src "libresoc.v:175292.14-175292.42"
+ process $proc$libresoc.v:175292$10982
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:177546.14-177546.48"
- process $proc$libresoc.v:177546$11075
+ attribute \src "libresoc.v:175299.14-175299.48"
+ process $proc$libresoc.v:175299$10983
assign { } { }
assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv1__data_o $1\sv1__data_o[63:0]
end
- attribute \src "libresoc.v:177562.3-177563.25"
- process $proc$libresoc.v:177562$11018
+ attribute \src "libresoc.v:175315.3-175316.25"
+ process $proc$libresoc.v:175315$10926
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:177564.3-177565.39"
- process $proc$libresoc.v:177564$11019
+ attribute \src "libresoc.v:175317.3-175318.39"
+ process $proc$libresoc.v:175317$10927
assign { } { }
assign $0\sv1__data_o[63:0] \sv1__data_o$next
sync posedge \coresync_clk
update \sv1__data_o $0\sv1__data_o[63:0]
end
- attribute \src "libresoc.v:177566.3-177567.41"
- process $proc$libresoc.v:177566$11020
+ attribute \src "libresoc.v:175319.3-175320.41"
+ process $proc$libresoc.v:175319$10928
assign { } { }
assign $0\msr1__data_o[63:0] \msr1__data_o$next
sync posedge \coresync_clk
update \msr1__data_o $0\msr1__data_o[63:0]
end
- attribute \src "libresoc.v:177568.3-177569.41"
- process $proc$libresoc.v:177568$11021
+ attribute \src "libresoc.v:175321.3-175322.41"
+ process $proc$libresoc.v:175321$10929
assign { } { }
assign $0\cia1__data_o[63:0] \cia1__data_o$next
sync posedge \coresync_clk
update \cia1__data_o $0\cia1__data_o[63:0]
end
- attribute \src "libresoc.v:177570.3-177615.6"
- process $proc$libresoc.v:177570$11022
+ attribute \src "libresoc.v:175323.3-175368.6"
+ process $proc$libresoc.v:175323$10930
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia1__data_o$next[63:0]$11023 $7\cia1__data_o$next[63:0]$11030
- attribute \src "libresoc.v:177571.5-177571.29"
+ assign $0\cia1__data_o$next[63:0]$10931 $7\cia1__data_o$next[63:0]$10938
+ attribute \src "libresoc.v:175324.5-175324.29"
switch \initial
- attribute \src "libresoc.v:177571.9-177571.17"
+ attribute \src "libresoc.v:175324.9-175324.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia1__data_o$next[63:0]$11024 $6\cia1__data_o$next[63:0]$11029
+ assign $1\cia1__data_o$next[63:0]$10932 $6\cia1__data_o$next[63:0]$10937
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia1__data_o$next[63:0]$11025 \nia1__data_i
+ assign $2\cia1__data_o$next[63:0]$10933 \nia1__data_i
case
- assign $2\cia1__data_o$next[63:0]$11025 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia1__data_o$next[63:0]$10933 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia1__data_o$next[63:0]$11026 \msr1__data_i
+ assign $3\cia1__data_o$next[63:0]$10934 \msr1__data_i
case
- assign $3\cia1__data_o$next[63:0]$11026 $2\cia1__data_o$next[63:0]$11025
+ assign $3\cia1__data_o$next[63:0]$10934 $2\cia1__data_o$next[63:0]$10933
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia1__data_o$next[63:0]$11027 \sv1__data_i
+ assign $4\cia1__data_o$next[63:0]$10935 \sv1__data_i
case
- assign $4\cia1__data_o$next[63:0]$11027 $3\cia1__data_o$next[63:0]$11026
+ assign $4\cia1__data_o$next[63:0]$10935 $3\cia1__data_o$next[63:0]$10934
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia1__data_o$next[63:0]$11028 \d_wr11__data_i
+ assign $5\cia1__data_o$next[63:0]$10936 \d_wr11__data_i
case
- assign $5\cia1__data_o$next[63:0]$11028 $4\cia1__data_o$next[63:0]$11027
+ assign $5\cia1__data_o$next[63:0]$10936 $4\cia1__data_o$next[63:0]$10935
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia1__data_o$next[63:0]$11029 \reg
+ assign $6\cia1__data_o$next[63:0]$10937 \reg
case
- assign $6\cia1__data_o$next[63:0]$11029 $5\cia1__data_o$next[63:0]$11028
+ assign $6\cia1__data_o$next[63:0]$10937 $5\cia1__data_o$next[63:0]$10936
end
case
- assign $1\cia1__data_o$next[63:0]$11024 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia1__data_o$next[63:0]$10932 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia1__data_o$next[63:0]$11030 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia1__data_o$next[63:0]$10938 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia1__data_o$next[63:0]$11030 $1\cia1__data_o$next[63:0]$11024
+ assign $7\cia1__data_o$next[63:0]$10938 $1\cia1__data_o$next[63:0]$10932
end
sync always
- update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11023
+ update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10931
end
- attribute \src "libresoc.v:177616.3-177651.6"
- process $proc$libresoc.v:177616$11031
+ attribute \src "libresoc.v:175369.3-175404.6"
+ process $proc$libresoc.v:175369$10939
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:177617.5-177617.29"
+ attribute \src "libresoc.v:175370.5-175370.29"
switch \initial
- attribute \src "libresoc.v:177617.9-177617.17"
+ attribute \src "libresoc.v:175370.9-175370.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:177652.3-177697.6"
- process $proc$libresoc.v:177652$11032
+ attribute \src "libresoc.v:175405.3-175450.6"
+ process $proc$libresoc.v:175405$10940
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr1__data_o$next[63:0]$11033 $7\msr1__data_o$next[63:0]$11040
- attribute \src "libresoc.v:177653.5-177653.29"
+ assign $0\msr1__data_o$next[63:0]$10941 $7\msr1__data_o$next[63:0]$10948
+ attribute \src "libresoc.v:175406.5-175406.29"
switch \initial
- attribute \src "libresoc.v:177653.9-177653.17"
+ attribute \src "libresoc.v:175406.9-175406.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr1__data_o$next[63:0]$11034 $6\msr1__data_o$next[63:0]$11039
+ assign $1\msr1__data_o$next[63:0]$10942 $6\msr1__data_o$next[63:0]$10947
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr1__data_o$next[63:0]$11035 \nia1__data_i
+ assign $2\msr1__data_o$next[63:0]$10943 \nia1__data_i
case
- assign $2\msr1__data_o$next[63:0]$11035 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr1__data_o$next[63:0]$10943 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr1__data_o$next[63:0]$11036 \msr1__data_i
+ assign $3\msr1__data_o$next[63:0]$10944 \msr1__data_i
case
- assign $3\msr1__data_o$next[63:0]$11036 $2\msr1__data_o$next[63:0]$11035
+ assign $3\msr1__data_o$next[63:0]$10944 $2\msr1__data_o$next[63:0]$10943
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr1__data_o$next[63:0]$11037 \sv1__data_i
+ assign $4\msr1__data_o$next[63:0]$10945 \sv1__data_i
case
- assign $4\msr1__data_o$next[63:0]$11037 $3\msr1__data_o$next[63:0]$11036
+ assign $4\msr1__data_o$next[63:0]$10945 $3\msr1__data_o$next[63:0]$10944
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr1__data_o$next[63:0]$11038 \d_wr11__data_i
+ assign $5\msr1__data_o$next[63:0]$10946 \d_wr11__data_i
case
- assign $5\msr1__data_o$next[63:0]$11038 $4\msr1__data_o$next[63:0]$11037
+ assign $5\msr1__data_o$next[63:0]$10946 $4\msr1__data_o$next[63:0]$10945
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr1__data_o$next[63:0]$11039 \reg
+ assign $6\msr1__data_o$next[63:0]$10947 \reg
case
- assign $6\msr1__data_o$next[63:0]$11039 $5\msr1__data_o$next[63:0]$11038
+ assign $6\msr1__data_o$next[63:0]$10947 $5\msr1__data_o$next[63:0]$10946
end
case
- assign $1\msr1__data_o$next[63:0]$11034 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr1__data_o$next[63:0]$10942 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr1__data_o$next[63:0]$11040 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr1__data_o$next[63:0]$10948 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr1__data_o$next[63:0]$11040 $1\msr1__data_o$next[63:0]$11034
+ assign $7\msr1__data_o$next[63:0]$10948 $1\msr1__data_o$next[63:0]$10942
end
sync always
- update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11033
+ update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10941
end
- attribute \src "libresoc.v:177698.3-177733.6"
- process $proc$libresoc.v:177698$11041
+ attribute \src "libresoc.v:175451.3-175486.6"
+ process $proc$libresoc.v:175451$10949
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11042 $1\wr_detect$4[0:0]$11043
- attribute \src "libresoc.v:177699.5-177699.29"
+ assign $0\wr_detect$4[0:0]$10950 $1\wr_detect$4[0:0]$10951
+ attribute \src "libresoc.v:175452.5-175452.29"
switch \initial
- attribute \src "libresoc.v:177699.9-177699.17"
+ attribute \src "libresoc.v:175452.9-175452.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11043 $5\wr_detect$4[0:0]$11047
+ assign $1\wr_detect$4[0:0]$10951 $5\wr_detect$4[0:0]$10955
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11044 1'1
+ assign $2\wr_detect$4[0:0]$10952 1'1
case
- assign $2\wr_detect$4[0:0]$11044 1'0
+ assign $2\wr_detect$4[0:0]$10952 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11045 1'1
+ assign $3\wr_detect$4[0:0]$10953 1'1
case
- assign $3\wr_detect$4[0:0]$11045 $2\wr_detect$4[0:0]$11044
+ assign $3\wr_detect$4[0:0]$10953 $2\wr_detect$4[0:0]$10952
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11046 1'1
+ assign $4\wr_detect$4[0:0]$10954 1'1
case
- assign $4\wr_detect$4[0:0]$11046 $3\wr_detect$4[0:0]$11045
+ assign $4\wr_detect$4[0:0]$10954 $3\wr_detect$4[0:0]$10953
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11047 1'1
+ assign $5\wr_detect$4[0:0]$10955 1'1
case
- assign $5\wr_detect$4[0:0]$11047 $4\wr_detect$4[0:0]$11046
+ assign $5\wr_detect$4[0:0]$10955 $4\wr_detect$4[0:0]$10954
end
case
- assign $1\wr_detect$4[0:0]$11043 1'0
+ assign $1\wr_detect$4[0:0]$10951 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11042
+ update \wr_detect$4 $0\wr_detect$4[0:0]$10950
end
- attribute \src "libresoc.v:177734.3-177779.6"
- process $proc$libresoc.v:177734$11048
+ attribute \src "libresoc.v:175487.3-175532.6"
+ process $proc$libresoc.v:175487$10956
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv1__data_o$next[63:0]$11049 $7\sv1__data_o$next[63:0]$11056
- attribute \src "libresoc.v:177735.5-177735.29"
+ assign $0\sv1__data_o$next[63:0]$10957 $7\sv1__data_o$next[63:0]$10964
+ attribute \src "libresoc.v:175488.5-175488.29"
switch \initial
- attribute \src "libresoc.v:177735.9-177735.17"
+ attribute \src "libresoc.v:175488.9-175488.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv1__data_o$next[63:0]$11050 $6\sv1__data_o$next[63:0]$11055
+ assign $1\sv1__data_o$next[63:0]$10958 $6\sv1__data_o$next[63:0]$10963
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv1__data_o$next[63:0]$11051 \nia1__data_i
+ assign $2\sv1__data_o$next[63:0]$10959 \nia1__data_i
case
- assign $2\sv1__data_o$next[63:0]$11051 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv1__data_o$next[63:0]$10959 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv1__data_o$next[63:0]$11052 \msr1__data_i
+ assign $3\sv1__data_o$next[63:0]$10960 \msr1__data_i
case
- assign $3\sv1__data_o$next[63:0]$11052 $2\sv1__data_o$next[63:0]$11051
+ assign $3\sv1__data_o$next[63:0]$10960 $2\sv1__data_o$next[63:0]$10959
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv1__data_o$next[63:0]$11053 \sv1__data_i
+ assign $4\sv1__data_o$next[63:0]$10961 \sv1__data_i
case
- assign $4\sv1__data_o$next[63:0]$11053 $3\sv1__data_o$next[63:0]$11052
+ assign $4\sv1__data_o$next[63:0]$10961 $3\sv1__data_o$next[63:0]$10960
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv1__data_o$next[63:0]$11054 \d_wr11__data_i
+ assign $5\sv1__data_o$next[63:0]$10962 \d_wr11__data_i
case
- assign $5\sv1__data_o$next[63:0]$11054 $4\sv1__data_o$next[63:0]$11053
+ assign $5\sv1__data_o$next[63:0]$10962 $4\sv1__data_o$next[63:0]$10961
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv1__data_o$next[63:0]$11055 \reg
+ assign $6\sv1__data_o$next[63:0]$10963 \reg
case
- assign $6\sv1__data_o$next[63:0]$11055 $5\sv1__data_o$next[63:0]$11054
+ assign $6\sv1__data_o$next[63:0]$10963 $5\sv1__data_o$next[63:0]$10962
end
case
- assign $1\sv1__data_o$next[63:0]$11050 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv1__data_o$next[63:0]$11056 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv1__data_o$next[63:0]$10964 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv1__data_o$next[63:0]$11056 $1\sv1__data_o$next[63:0]$11050
+ assign $7\sv1__data_o$next[63:0]$10964 $1\sv1__data_o$next[63:0]$10958
end
sync always
- update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11049
+ update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10957
end
- attribute \src "libresoc.v:177780.3-177815.6"
- process $proc$libresoc.v:177780$11057
+ attribute \src "libresoc.v:175533.3-175568.6"
+ process $proc$libresoc.v:175533$10965
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11058 $1\wr_detect$7[0:0]$11059
- attribute \src "libresoc.v:177781.5-177781.29"
+ assign $0\wr_detect$7[0:0]$10966 $1\wr_detect$7[0:0]$10967
+ attribute \src "libresoc.v:175534.5-175534.29"
switch \initial
- attribute \src "libresoc.v:177781.9-177781.17"
+ attribute \src "libresoc.v:175534.9-175534.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11059 $5\wr_detect$7[0:0]$11063
+ assign $1\wr_detect$7[0:0]$10967 $5\wr_detect$7[0:0]$10971
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11060 1'1
+ assign $2\wr_detect$7[0:0]$10968 1'1
case
- assign $2\wr_detect$7[0:0]$11060 1'0
+ assign $2\wr_detect$7[0:0]$10968 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11061 1'1
+ assign $3\wr_detect$7[0:0]$10969 1'1
case
- assign $3\wr_detect$7[0:0]$11061 $2\wr_detect$7[0:0]$11060
+ assign $3\wr_detect$7[0:0]$10969 $2\wr_detect$7[0:0]$10968
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11062 1'1
+ assign $4\wr_detect$7[0:0]$10970 1'1
case
- assign $4\wr_detect$7[0:0]$11062 $3\wr_detect$7[0:0]$11061
+ assign $4\wr_detect$7[0:0]$10970 $3\wr_detect$7[0:0]$10969
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11063 1'1
+ assign $5\wr_detect$7[0:0]$10971 1'1
case
- assign $5\wr_detect$7[0:0]$11063 $4\wr_detect$7[0:0]$11062
+ assign $5\wr_detect$7[0:0]$10971 $4\wr_detect$7[0:0]$10970
end
case
- assign $1\wr_detect$7[0:0]$11059 1'0
+ assign $1\wr_detect$7[0:0]$10967 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11058
+ update \wr_detect$7 $0\wr_detect$7[0:0]$10966
end
- attribute \src "libresoc.v:177816.3-177848.6"
- process $proc$libresoc.v:177816$11064
+ attribute \src "libresoc.v:175569.3-175601.6"
+ process $proc$libresoc.v:175569$10972
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$11065 $5\reg$next[63:0]$11070
- attribute \src "libresoc.v:177817.5-177817.29"
+ assign $0\reg$next[63:0]$10973 $5\reg$next[63:0]$10978
+ attribute \src "libresoc.v:175570.5-175570.29"
switch \initial
- attribute \src "libresoc.v:177817.9-177817.17"
+ attribute \src "libresoc.v:175570.9-175570.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$11066 \nia1__data_i
+ assign $1\reg$next[63:0]$10974 \nia1__data_i
case
- assign $1\reg$next[63:0]$11066 \reg
+ assign $1\reg$next[63:0]$10974 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$11067 \msr1__data_i
+ assign $2\reg$next[63:0]$10975 \msr1__data_i
case
- assign $2\reg$next[63:0]$11067 $1\reg$next[63:0]$11066
+ assign $2\reg$next[63:0]$10975 $1\reg$next[63:0]$10974
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv1__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$11068 \sv1__data_i
+ assign $3\reg$next[63:0]$10976 \sv1__data_i
case
- assign $3\reg$next[63:0]$11068 $2\reg$next[63:0]$11067
+ assign $3\reg$next[63:0]$10976 $2\reg$next[63:0]$10975
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr11__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$11069 \d_wr11__data_i
+ assign $4\reg$next[63:0]$10977 \d_wr11__data_i
case
- assign $4\reg$next[63:0]$11069 $3\reg$next[63:0]$11068
+ assign $4\reg$next[63:0]$10977 $3\reg$next[63:0]$10976
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$11070 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$10978 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$11070 $4\reg$next[63:0]$11069
+ assign $5\reg$next[63:0]$10978 $4\reg$next[63:0]$10977
end
sync always
- update \reg$next $0\reg$next[63:0]$11065
+ update \reg$next $0\reg$next[63:0]$10973
end
- connect \$1 $not$libresoc.v:177559$11015_Y
- connect \$3 $not$libresoc.v:177560$11016_Y
- connect \$6 $not$libresoc.v:177561$11017_Y
+ connect \$1 $not$libresoc.v:175312$10923_Y
+ connect \$3 $not$libresoc.v:175313$10924_Y
+ connect \$6 $not$libresoc.v:175314$10925_Y
end
-attribute \src "libresoc.v:177853.1-178324.10"
+attribute \src "libresoc.v:175606.1-176077.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2"
attribute \generator "nMigen"
module \reg_2
- attribute \src "libresoc.v:177854.7-177854.20"
+ attribute \src "libresoc.v:175607.7-175607.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $0\r22__data_o$next[3:0]$11145
- attribute \src "libresoc.v:177937.3-177938.39"
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $0\r22__data_o$next[3:0]$11053
+ attribute \src "libresoc.v:175690.3-175691.39"
wire width 4 $0\r22__data_o[3:0]
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $0\r2__data_o$next[3:0]$11131
- attribute \src "libresoc.v:177939.3-177940.37"
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $0\r2__data_o$next[3:0]$11039
+ attribute \src "libresoc.v:175692.3-175693.37"
wire width 4 $0\r2__data_o[3:0]
- attribute \src "libresoc.v:178017.3-178043.6"
- wire width 4 $0\reg$next[3:0]$11097
- attribute \src "libresoc.v:177935.3-177936.25"
+ attribute \src "libresoc.v:175770.3-175796.6"
+ wire width 4 $0\reg$next[3:0]$11005
+ attribute \src "libresoc.v:175688.3-175689.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $0\src12__data_o$next[3:0]$11088
- attribute \src "libresoc.v:177945.3-177946.43"
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $0\src12__data_o$next[3:0]$10996
+ attribute \src "libresoc.v:175698.3-175699.43"
wire width 4 $0\src12__data_o[3:0]
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $0\src22__data_o$next[3:0]$11103
- attribute \src "libresoc.v:177943.3-177944.43"
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $0\src22__data_o$next[3:0]$11011
+ attribute \src "libresoc.v:175696.3-175697.43"
wire width 4 $0\src22__data_o[3:0]
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $0\src32__data_o$next[3:0]$11117
- attribute \src "libresoc.v:177941.3-177942.43"
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $0\src32__data_o$next[3:0]$11025
+ attribute \src "libresoc.v:175694.3-175695.43"
wire width 4 $0\src32__data_o[3:0]
- attribute \src "libresoc.v:178224.3-178253.6"
- wire $0\wr_detect$10[0:0]$11139
- attribute \src "libresoc.v:178294.3-178323.6"
- wire $0\wr_detect$13[0:0]$11153
- attribute \src "libresoc.v:178084.3-178113.6"
- wire $0\wr_detect$4[0:0]$11111
- attribute \src "libresoc.v:178154.3-178183.6"
- wire $0\wr_detect$7[0:0]$11125
- attribute \src "libresoc.v:177987.3-178016.6"
+ attribute \src "libresoc.v:175977.3-176006.6"
+ wire $0\wr_detect$10[0:0]$11047
+ attribute \src "libresoc.v:176047.3-176076.6"
+ wire $0\wr_detect$13[0:0]$11061
+ attribute \src "libresoc.v:175837.3-175866.6"
+ wire $0\wr_detect$4[0:0]$11019
+ attribute \src "libresoc.v:175907.3-175936.6"
+ wire $0\wr_detect$7[0:0]$11033
+ attribute \src "libresoc.v:175740.3-175769.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $1\r22__data_o$next[3:0]$11146
- attribute \src "libresoc.v:177879.13-177879.31"
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $1\r22__data_o$next[3:0]$11054
+ attribute \src "libresoc.v:175632.13-175632.31"
wire width 4 $1\r22__data_o[3:0]
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $1\r2__data_o$next[3:0]$11132
- attribute \src "libresoc.v:177886.13-177886.30"
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $1\r2__data_o$next[3:0]$11040
+ attribute \src "libresoc.v:175639.13-175639.30"
wire width 4 $1\r2__data_o[3:0]
- attribute \src "libresoc.v:178017.3-178043.6"
- wire width 4 $1\reg$next[3:0]$11098
- attribute \src "libresoc.v:177892.13-177892.25"
+ attribute \src "libresoc.v:175770.3-175796.6"
+ wire width 4 $1\reg$next[3:0]$11006
+ attribute \src "libresoc.v:175645.13-175645.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $1\src12__data_o$next[3:0]$11089
- attribute \src "libresoc.v:177897.13-177897.33"
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $1\src12__data_o$next[3:0]$10997
+ attribute \src "libresoc.v:175650.13-175650.33"
wire width 4 $1\src12__data_o[3:0]
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $1\src22__data_o$next[3:0]$11104
- attribute \src "libresoc.v:177904.13-177904.33"
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $1\src22__data_o$next[3:0]$11012
+ attribute \src "libresoc.v:175657.13-175657.33"
wire width 4 $1\src22__data_o[3:0]
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $1\src32__data_o$next[3:0]$11118
- attribute \src "libresoc.v:177911.13-177911.33"
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $1\src32__data_o$next[3:0]$11026
+ attribute \src "libresoc.v:175664.13-175664.33"
wire width 4 $1\src32__data_o[3:0]
- attribute \src "libresoc.v:178224.3-178253.6"
- wire $1\wr_detect$10[0:0]$11140
- attribute \src "libresoc.v:178294.3-178323.6"
- wire $1\wr_detect$13[0:0]$11154
- attribute \src "libresoc.v:178084.3-178113.6"
- wire $1\wr_detect$4[0:0]$11112
- attribute \src "libresoc.v:178154.3-178183.6"
- wire $1\wr_detect$7[0:0]$11126
- attribute \src "libresoc.v:177987.3-178016.6"
+ attribute \src "libresoc.v:175977.3-176006.6"
+ wire $1\wr_detect$10[0:0]$11048
+ attribute \src "libresoc.v:176047.3-176076.6"
+ wire $1\wr_detect$13[0:0]$11062
+ attribute \src "libresoc.v:175837.3-175866.6"
+ wire $1\wr_detect$4[0:0]$11020
+ attribute \src "libresoc.v:175907.3-175936.6"
+ wire $1\wr_detect$7[0:0]$11034
+ attribute \src "libresoc.v:175740.3-175769.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $2\r22__data_o$next[3:0]$11147
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $2\r2__data_o$next[3:0]$11133
- attribute \src "libresoc.v:178017.3-178043.6"
- wire width 4 $2\reg$next[3:0]$11099
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $2\src12__data_o$next[3:0]$11090
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $2\src22__data_o$next[3:0]$11105
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $2\src32__data_o$next[3:0]$11119
- attribute \src "libresoc.v:178224.3-178253.6"
- wire $2\wr_detect$10[0:0]$11141
- attribute \src "libresoc.v:178294.3-178323.6"
- wire $2\wr_detect$13[0:0]$11155
- attribute \src "libresoc.v:178084.3-178113.6"
- wire $2\wr_detect$4[0:0]$11113
- attribute \src "libresoc.v:178154.3-178183.6"
- wire $2\wr_detect$7[0:0]$11127
- attribute \src "libresoc.v:177987.3-178016.6"
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $2\r22__data_o$next[3:0]$11055
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $2\r2__data_o$next[3:0]$11041
+ attribute \src "libresoc.v:175770.3-175796.6"
+ wire width 4 $2\reg$next[3:0]$11007
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $2\src12__data_o$next[3:0]$10998
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $2\src22__data_o$next[3:0]$11013
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $2\src32__data_o$next[3:0]$11027
+ attribute \src "libresoc.v:175977.3-176006.6"
+ wire $2\wr_detect$10[0:0]$11049
+ attribute \src "libresoc.v:176047.3-176076.6"
+ wire $2\wr_detect$13[0:0]$11063
+ attribute \src "libresoc.v:175837.3-175866.6"
+ wire $2\wr_detect$4[0:0]$11021
+ attribute \src "libresoc.v:175907.3-175936.6"
+ wire $2\wr_detect$7[0:0]$11035
+ attribute \src "libresoc.v:175740.3-175769.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $3\r22__data_o$next[3:0]$11148
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $3\r2__data_o$next[3:0]$11134
- attribute \src "libresoc.v:178017.3-178043.6"
- wire width 4 $3\reg$next[3:0]$11100
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $3\src12__data_o$next[3:0]$11091
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $3\src22__data_o$next[3:0]$11106
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $3\src32__data_o$next[3:0]$11120
- attribute \src "libresoc.v:178224.3-178253.6"
- wire $3\wr_detect$10[0:0]$11142
- attribute \src "libresoc.v:178294.3-178323.6"
- wire $3\wr_detect$13[0:0]$11156
- attribute \src "libresoc.v:178084.3-178113.6"
- wire $3\wr_detect$4[0:0]$11114
- attribute \src "libresoc.v:178154.3-178183.6"
- wire $3\wr_detect$7[0:0]$11128
- attribute \src "libresoc.v:177987.3-178016.6"
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $3\r22__data_o$next[3:0]$11056
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $3\r2__data_o$next[3:0]$11042
+ attribute \src "libresoc.v:175770.3-175796.6"
+ wire width 4 $3\reg$next[3:0]$11008
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $3\src12__data_o$next[3:0]$10999
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $3\src22__data_o$next[3:0]$11014
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $3\src32__data_o$next[3:0]$11028
+ attribute \src "libresoc.v:175977.3-176006.6"
+ wire $3\wr_detect$10[0:0]$11050
+ attribute \src "libresoc.v:176047.3-176076.6"
+ wire $3\wr_detect$13[0:0]$11064
+ attribute \src "libresoc.v:175837.3-175866.6"
+ wire $3\wr_detect$4[0:0]$11022
+ attribute \src "libresoc.v:175907.3-175936.6"
+ wire $3\wr_detect$7[0:0]$11036
+ attribute \src "libresoc.v:175740.3-175769.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $4\r22__data_o$next[3:0]$11149
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $4\r2__data_o$next[3:0]$11135
- attribute \src "libresoc.v:178017.3-178043.6"
- wire width 4 $4\reg$next[3:0]$11101
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $4\src12__data_o$next[3:0]$11092
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $4\src22__data_o$next[3:0]$11107
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $4\src32__data_o$next[3:0]$11121
- attribute \src "libresoc.v:178224.3-178253.6"
- wire $4\wr_detect$10[0:0]$11143
- attribute \src "libresoc.v:178294.3-178323.6"
- wire $4\wr_detect$13[0:0]$11157
- attribute \src "libresoc.v:178084.3-178113.6"
- wire $4\wr_detect$4[0:0]$11115
- attribute \src "libresoc.v:178154.3-178183.6"
- wire $4\wr_detect$7[0:0]$11129
- attribute \src "libresoc.v:177987.3-178016.6"
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $4\r22__data_o$next[3:0]$11057
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $4\r2__data_o$next[3:0]$11043
+ attribute \src "libresoc.v:175770.3-175796.6"
+ wire width 4 $4\reg$next[3:0]$11009
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $4\src12__data_o$next[3:0]$11000
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $4\src22__data_o$next[3:0]$11015
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $4\src32__data_o$next[3:0]$11029
+ attribute \src "libresoc.v:175977.3-176006.6"
+ wire $4\wr_detect$10[0:0]$11051
+ attribute \src "libresoc.v:176047.3-176076.6"
+ wire $4\wr_detect$13[0:0]$11065
+ attribute \src "libresoc.v:175837.3-175866.6"
+ wire $4\wr_detect$4[0:0]$11023
+ attribute \src "libresoc.v:175907.3-175936.6"
+ wire $4\wr_detect$7[0:0]$11037
+ attribute \src "libresoc.v:175740.3-175769.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $5\r22__data_o$next[3:0]$11150
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $5\r2__data_o$next[3:0]$11136
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $5\src12__data_o$next[3:0]$11093
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $5\src22__data_o$next[3:0]$11108
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $5\src32__data_o$next[3:0]$11122
- attribute \src "libresoc.v:178254.3-178293.6"
- wire width 4 $6\r22__data_o$next[3:0]$11151
- attribute \src "libresoc.v:178184.3-178223.6"
- wire width 4 $6\r2__data_o$next[3:0]$11137
- attribute \src "libresoc.v:177947.3-177986.6"
- wire width 4 $6\src12__data_o$next[3:0]$11094
- attribute \src "libresoc.v:178044.3-178083.6"
- wire width 4 $6\src22__data_o$next[3:0]$11109
- attribute \src "libresoc.v:178114.3-178153.6"
- wire width 4 $6\src32__data_o$next[3:0]$11123
- attribute \src "libresoc.v:177930.17-177930.104"
- wire $not$libresoc.v:177930$11076_Y
- attribute \src "libresoc.v:177931.18-177931.105"
- wire $not$libresoc.v:177931$11077_Y
- attribute \src "libresoc.v:177932.17-177932.100"
- wire $not$libresoc.v:177932$11078_Y
- attribute \src "libresoc.v:177933.17-177933.103"
- wire $not$libresoc.v:177933$11079_Y
- attribute \src "libresoc.v:177934.17-177934.103"
- wire $not$libresoc.v:177934$11080_Y
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $5\r22__data_o$next[3:0]$11058
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $5\r2__data_o$next[3:0]$11044
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $5\src12__data_o$next[3:0]$11001
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $5\src22__data_o$next[3:0]$11016
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $5\src32__data_o$next[3:0]$11030
+ attribute \src "libresoc.v:176007.3-176046.6"
+ wire width 4 $6\r22__data_o$next[3:0]$11059
+ attribute \src "libresoc.v:175937.3-175976.6"
+ wire width 4 $6\r2__data_o$next[3:0]$11045
+ attribute \src "libresoc.v:175700.3-175739.6"
+ wire width 4 $6\src12__data_o$next[3:0]$11002
+ attribute \src "libresoc.v:175797.3-175836.6"
+ wire width 4 $6\src22__data_o$next[3:0]$11017
+ attribute \src "libresoc.v:175867.3-175906.6"
+ wire width 4 $6\src32__data_o$next[3:0]$11031
+ attribute \src "libresoc.v:175683.17-175683.104"
+ wire $not$libresoc.v:175683$10984_Y
+ attribute \src "libresoc.v:175684.18-175684.105"
+ wire $not$libresoc.v:175684$10985_Y
+ attribute \src "libresoc.v:175685.17-175685.100"
+ wire $not$libresoc.v:175685$10986_Y
+ attribute \src "libresoc.v:175686.17-175686.103"
+ wire $not$libresoc.v:175686$10987_Y
+ attribute \src "libresoc.v:175687.17-175687.103"
+ wire $not$libresoc.v:175687$10988_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest12__data_i
wire width 4 input 11 \dest22__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest22__wen
- attribute \src "libresoc.v:177854.7-177854.15"
+ attribute \src "libresoc.v:175607.7-175607.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r22__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177930$11076
+ cell $not $not$libresoc.v:175683$10984
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:177930$11076_Y
+ connect \Y $not$libresoc.v:175683$10984_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177931$11077
+ cell $not $not$libresoc.v:175684$10985
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:177931$11077_Y
+ connect \Y $not$libresoc.v:175684$10985_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177932$11078
+ cell $not $not$libresoc.v:175685$10986
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:177932$11078_Y
+ connect \Y $not$libresoc.v:175685$10986_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177933$11079
+ cell $not $not$libresoc.v:175686$10987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:177933$11079_Y
+ connect \Y $not$libresoc.v:175686$10987_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:177934$11080
+ cell $not $not$libresoc.v:175687$10988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:177934$11080_Y
+ connect \Y $not$libresoc.v:175687$10988_Y
end
- attribute \src "libresoc.v:177854.7-177854.20"
- process $proc$libresoc.v:177854$11158
+ attribute \src "libresoc.v:175607.7-175607.20"
+ process $proc$libresoc.v:175607$11066
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:177879.13-177879.31"
- process $proc$libresoc.v:177879$11159
+ attribute \src "libresoc.v:175632.13-175632.31"
+ process $proc$libresoc.v:175632$11067
assign { } { }
assign $1\r22__data_o[3:0] 4'0000
sync always
sync init
update \r22__data_o $1\r22__data_o[3:0]
end
- attribute \src "libresoc.v:177886.13-177886.30"
- process $proc$libresoc.v:177886$11160
+ attribute \src "libresoc.v:175639.13-175639.30"
+ process $proc$libresoc.v:175639$11068
assign { } { }
assign $1\r2__data_o[3:0] 4'0000
sync always
sync init
update \r2__data_o $1\r2__data_o[3:0]
end
- attribute \src "libresoc.v:177892.13-177892.25"
- process $proc$libresoc.v:177892$11161
+ attribute \src "libresoc.v:175645.13-175645.25"
+ process $proc$libresoc.v:175645$11069
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:177897.13-177897.33"
- process $proc$libresoc.v:177897$11162
+ attribute \src "libresoc.v:175650.13-175650.33"
+ process $proc$libresoc.v:175650$11070
assign { } { }
assign $1\src12__data_o[3:0] 4'0000
sync always
sync init
update \src12__data_o $1\src12__data_o[3:0]
end
- attribute \src "libresoc.v:177904.13-177904.33"
- process $proc$libresoc.v:177904$11163
+ attribute \src "libresoc.v:175657.13-175657.33"
+ process $proc$libresoc.v:175657$11071
assign { } { }
assign $1\src22__data_o[3:0] 4'0000
sync always
sync init
update \src22__data_o $1\src22__data_o[3:0]
end
- attribute \src "libresoc.v:177911.13-177911.33"
- process $proc$libresoc.v:177911$11164
+ attribute \src "libresoc.v:175664.13-175664.33"
+ process $proc$libresoc.v:175664$11072
assign { } { }
assign $1\src32__data_o[3:0] 4'0000
sync always
sync init
update \src32__data_o $1\src32__data_o[3:0]
end
- attribute \src "libresoc.v:177935.3-177936.25"
- process $proc$libresoc.v:177935$11081
+ attribute \src "libresoc.v:175688.3-175689.25"
+ process $proc$libresoc.v:175688$10989
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:177937.3-177938.39"
- process $proc$libresoc.v:177937$11082
+ attribute \src "libresoc.v:175690.3-175691.39"
+ process $proc$libresoc.v:175690$10990
assign { } { }
assign $0\r22__data_o[3:0] \r22__data_o$next
sync posedge \coresync_clk
update \r22__data_o $0\r22__data_o[3:0]
end
- attribute \src "libresoc.v:177939.3-177940.37"
- process $proc$libresoc.v:177939$11083
+ attribute \src "libresoc.v:175692.3-175693.37"
+ process $proc$libresoc.v:175692$10991
assign { } { }
assign $0\r2__data_o[3:0] \r2__data_o$next
sync posedge \coresync_clk
update \r2__data_o $0\r2__data_o[3:0]
end
- attribute \src "libresoc.v:177941.3-177942.43"
- process $proc$libresoc.v:177941$11084
+ attribute \src "libresoc.v:175694.3-175695.43"
+ process $proc$libresoc.v:175694$10992
assign { } { }
assign $0\src32__data_o[3:0] \src32__data_o$next
sync posedge \coresync_clk
update \src32__data_o $0\src32__data_o[3:0]
end
- attribute \src "libresoc.v:177943.3-177944.43"
- process $proc$libresoc.v:177943$11085
+ attribute \src "libresoc.v:175696.3-175697.43"
+ process $proc$libresoc.v:175696$10993
assign { } { }
assign $0\src22__data_o[3:0] \src22__data_o$next
sync posedge \coresync_clk
update \src22__data_o $0\src22__data_o[3:0]
end
- attribute \src "libresoc.v:177945.3-177946.43"
- process $proc$libresoc.v:177945$11086
+ attribute \src "libresoc.v:175698.3-175699.43"
+ process $proc$libresoc.v:175698$10994
assign { } { }
assign $0\src12__data_o[3:0] \src12__data_o$next
sync posedge \coresync_clk
update \src12__data_o $0\src12__data_o[3:0]
end
- attribute \src "libresoc.v:177947.3-177986.6"
- process $proc$libresoc.v:177947$11087
+ attribute \src "libresoc.v:175700.3-175739.6"
+ process $proc$libresoc.v:175700$10995
assign { } { }
assign { } { }
assign { } { }
- assign $0\src12__data_o$next[3:0]$11088 $6\src12__data_o$next[3:0]$11094
- attribute \src "libresoc.v:177948.5-177948.29"
+ assign $0\src12__data_o$next[3:0]$10996 $6\src12__data_o$next[3:0]$11002
+ attribute \src "libresoc.v:175701.5-175701.29"
switch \initial
- attribute \src "libresoc.v:177948.9-177948.17"
+ attribute \src "libresoc.v:175701.9-175701.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src12__data_o$next[3:0]$11089 $5\src12__data_o$next[3:0]$11093
+ assign $1\src12__data_o$next[3:0]$10997 $5\src12__data_o$next[3:0]$11001
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src12__data_o$next[3:0]$11090 \dest12__data_i
+ assign $2\src12__data_o$next[3:0]$10998 \dest12__data_i
case
- assign $2\src12__data_o$next[3:0]$11090 4'0000
+ assign $2\src12__data_o$next[3:0]$10998 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src12__data_o$next[3:0]$11091 \dest22__data_i
+ assign $3\src12__data_o$next[3:0]$10999 \dest22__data_i
case
- assign $3\src12__data_o$next[3:0]$11091 $2\src12__data_o$next[3:0]$11090
+ assign $3\src12__data_o$next[3:0]$10999 $2\src12__data_o$next[3:0]$10998
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src12__data_o$next[3:0]$11092 \w2__data_i
+ assign $4\src12__data_o$next[3:0]$11000 \w2__data_i
case
- assign $4\src12__data_o$next[3:0]$11092 $3\src12__data_o$next[3:0]$11091
+ assign $4\src12__data_o$next[3:0]$11000 $3\src12__data_o$next[3:0]$10999
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src12__data_o$next[3:0]$11093 \reg
+ assign $5\src12__data_o$next[3:0]$11001 \reg
case
- assign $5\src12__data_o$next[3:0]$11093 $4\src12__data_o$next[3:0]$11092
+ assign $5\src12__data_o$next[3:0]$11001 $4\src12__data_o$next[3:0]$11000
end
case
- assign $1\src12__data_o$next[3:0]$11089 4'0000
+ assign $1\src12__data_o$next[3:0]$10997 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src12__data_o$next[3:0]$11094 4'0000
+ assign $6\src12__data_o$next[3:0]$11002 4'0000
case
- assign $6\src12__data_o$next[3:0]$11094 $1\src12__data_o$next[3:0]$11089
+ assign $6\src12__data_o$next[3:0]$11002 $1\src12__data_o$next[3:0]$10997
end
sync always
- update \src12__data_o$next $0\src12__data_o$next[3:0]$11088
+ update \src12__data_o$next $0\src12__data_o$next[3:0]$10996
end
- attribute \src "libresoc.v:177987.3-178016.6"
- process $proc$libresoc.v:177987$11095
+ attribute \src "libresoc.v:175740.3-175769.6"
+ process $proc$libresoc.v:175740$11003
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:177988.5-177988.29"
+ attribute \src "libresoc.v:175741.5-175741.29"
switch \initial
- attribute \src "libresoc.v:177988.9-177988.17"
+ attribute \src "libresoc.v:175741.9-175741.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:178017.3-178043.6"
- process $proc$libresoc.v:178017$11096
+ attribute \src "libresoc.v:175770.3-175796.6"
+ process $proc$libresoc.v:175770$11004
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11097 $4\reg$next[3:0]$11101
- attribute \src "libresoc.v:178018.5-178018.29"
+ assign $0\reg$next[3:0]$11005 $4\reg$next[3:0]$11009
+ attribute \src "libresoc.v:175771.5-175771.29"
switch \initial
- attribute \src "libresoc.v:178018.9-178018.17"
+ attribute \src "libresoc.v:175771.9-175771.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11098 \dest12__data_i
+ assign $1\reg$next[3:0]$11006 \dest12__data_i
case
- assign $1\reg$next[3:0]$11098 \reg
+ assign $1\reg$next[3:0]$11006 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11099 \dest22__data_i
+ assign $2\reg$next[3:0]$11007 \dest22__data_i
case
- assign $2\reg$next[3:0]$11099 $1\reg$next[3:0]$11098
+ assign $2\reg$next[3:0]$11007 $1\reg$next[3:0]$11006
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11100 \w2__data_i
+ assign $3\reg$next[3:0]$11008 \w2__data_i
case
- assign $3\reg$next[3:0]$11100 $2\reg$next[3:0]$11099
+ assign $3\reg$next[3:0]$11008 $2\reg$next[3:0]$11007
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11101 4'0000
+ assign $4\reg$next[3:0]$11009 4'0000
case
- assign $4\reg$next[3:0]$11101 $3\reg$next[3:0]$11100
+ assign $4\reg$next[3:0]$11009 $3\reg$next[3:0]$11008
end
sync always
- update \reg$next $0\reg$next[3:0]$11097
+ update \reg$next $0\reg$next[3:0]$11005
end
- attribute \src "libresoc.v:178044.3-178083.6"
- process $proc$libresoc.v:178044$11102
+ attribute \src "libresoc.v:175797.3-175836.6"
+ process $proc$libresoc.v:175797$11010
assign { } { }
assign { } { }
assign { } { }
- assign $0\src22__data_o$next[3:0]$11103 $6\src22__data_o$next[3:0]$11109
- attribute \src "libresoc.v:178045.5-178045.29"
+ assign $0\src22__data_o$next[3:0]$11011 $6\src22__data_o$next[3:0]$11017
+ attribute \src "libresoc.v:175798.5-175798.29"
switch \initial
- attribute \src "libresoc.v:178045.9-178045.17"
+ attribute \src "libresoc.v:175798.9-175798.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src22__data_o$next[3:0]$11104 $5\src22__data_o$next[3:0]$11108
+ assign $1\src22__data_o$next[3:0]$11012 $5\src22__data_o$next[3:0]$11016
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src22__data_o$next[3:0]$11105 \dest12__data_i
+ assign $2\src22__data_o$next[3:0]$11013 \dest12__data_i
case
- assign $2\src22__data_o$next[3:0]$11105 4'0000
+ assign $2\src22__data_o$next[3:0]$11013 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src22__data_o$next[3:0]$11106 \dest22__data_i
+ assign $3\src22__data_o$next[3:0]$11014 \dest22__data_i
case
- assign $3\src22__data_o$next[3:0]$11106 $2\src22__data_o$next[3:0]$11105
+ assign $3\src22__data_o$next[3:0]$11014 $2\src22__data_o$next[3:0]$11013
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src22__data_o$next[3:0]$11107 \w2__data_i
+ assign $4\src22__data_o$next[3:0]$11015 \w2__data_i
case
- assign $4\src22__data_o$next[3:0]$11107 $3\src22__data_o$next[3:0]$11106
+ assign $4\src22__data_o$next[3:0]$11015 $3\src22__data_o$next[3:0]$11014
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src22__data_o$next[3:0]$11108 \reg
+ assign $5\src22__data_o$next[3:0]$11016 \reg
case
- assign $5\src22__data_o$next[3:0]$11108 $4\src22__data_o$next[3:0]$11107
+ assign $5\src22__data_o$next[3:0]$11016 $4\src22__data_o$next[3:0]$11015
end
case
- assign $1\src22__data_o$next[3:0]$11104 4'0000
+ assign $1\src22__data_o$next[3:0]$11012 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src22__data_o$next[3:0]$11109 4'0000
+ assign $6\src22__data_o$next[3:0]$11017 4'0000
case
- assign $6\src22__data_o$next[3:0]$11109 $1\src22__data_o$next[3:0]$11104
+ assign $6\src22__data_o$next[3:0]$11017 $1\src22__data_o$next[3:0]$11012
end
sync always
- update \src22__data_o$next $0\src22__data_o$next[3:0]$11103
+ update \src22__data_o$next $0\src22__data_o$next[3:0]$11011
end
- attribute \src "libresoc.v:178084.3-178113.6"
- process $proc$libresoc.v:178084$11110
+ attribute \src "libresoc.v:175837.3-175866.6"
+ process $proc$libresoc.v:175837$11018
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11111 $1\wr_detect$4[0:0]$11112
- attribute \src "libresoc.v:178085.5-178085.29"
+ assign $0\wr_detect$4[0:0]$11019 $1\wr_detect$4[0:0]$11020
+ attribute \src "libresoc.v:175838.5-175838.29"
switch \initial
- attribute \src "libresoc.v:178085.9-178085.17"
+ attribute \src "libresoc.v:175838.9-175838.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11112 $4\wr_detect$4[0:0]$11115
+ assign $1\wr_detect$4[0:0]$11020 $4\wr_detect$4[0:0]$11023
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11113 1'1
+ assign $2\wr_detect$4[0:0]$11021 1'1
case
- assign $2\wr_detect$4[0:0]$11113 1'0
+ assign $2\wr_detect$4[0:0]$11021 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11114 1'1
+ assign $3\wr_detect$4[0:0]$11022 1'1
case
- assign $3\wr_detect$4[0:0]$11114 $2\wr_detect$4[0:0]$11113
+ assign $3\wr_detect$4[0:0]$11022 $2\wr_detect$4[0:0]$11021
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11115 1'1
+ assign $4\wr_detect$4[0:0]$11023 1'1
case
- assign $4\wr_detect$4[0:0]$11115 $3\wr_detect$4[0:0]$11114
+ assign $4\wr_detect$4[0:0]$11023 $3\wr_detect$4[0:0]$11022
end
case
- assign $1\wr_detect$4[0:0]$11112 1'0
+ assign $1\wr_detect$4[0:0]$11020 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11111
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11019
end
- attribute \src "libresoc.v:178114.3-178153.6"
- process $proc$libresoc.v:178114$11116
+ attribute \src "libresoc.v:175867.3-175906.6"
+ process $proc$libresoc.v:175867$11024
assign { } { }
assign { } { }
assign { } { }
- assign $0\src32__data_o$next[3:0]$11117 $6\src32__data_o$next[3:0]$11123
- attribute \src "libresoc.v:178115.5-178115.29"
+ assign $0\src32__data_o$next[3:0]$11025 $6\src32__data_o$next[3:0]$11031
+ attribute \src "libresoc.v:175868.5-175868.29"
switch \initial
- attribute \src "libresoc.v:178115.9-178115.17"
+ attribute \src "libresoc.v:175868.9-175868.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src32__data_o$next[3:0]$11118 $5\src32__data_o$next[3:0]$11122
+ assign $1\src32__data_o$next[3:0]$11026 $5\src32__data_o$next[3:0]$11030
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src32__data_o$next[3:0]$11119 \dest12__data_i
+ assign $2\src32__data_o$next[3:0]$11027 \dest12__data_i
case
- assign $2\src32__data_o$next[3:0]$11119 4'0000
+ assign $2\src32__data_o$next[3:0]$11027 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src32__data_o$next[3:0]$11120 \dest22__data_i
+ assign $3\src32__data_o$next[3:0]$11028 \dest22__data_i
case
- assign $3\src32__data_o$next[3:0]$11120 $2\src32__data_o$next[3:0]$11119
+ assign $3\src32__data_o$next[3:0]$11028 $2\src32__data_o$next[3:0]$11027
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src32__data_o$next[3:0]$11121 \w2__data_i
+ assign $4\src32__data_o$next[3:0]$11029 \w2__data_i
case
- assign $4\src32__data_o$next[3:0]$11121 $3\src32__data_o$next[3:0]$11120
+ assign $4\src32__data_o$next[3:0]$11029 $3\src32__data_o$next[3:0]$11028
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src32__data_o$next[3:0]$11122 \reg
+ assign $5\src32__data_o$next[3:0]$11030 \reg
case
- assign $5\src32__data_o$next[3:0]$11122 $4\src32__data_o$next[3:0]$11121
+ assign $5\src32__data_o$next[3:0]$11030 $4\src32__data_o$next[3:0]$11029
end
case
- assign $1\src32__data_o$next[3:0]$11118 4'0000
+ assign $1\src32__data_o$next[3:0]$11026 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src32__data_o$next[3:0]$11123 4'0000
+ assign $6\src32__data_o$next[3:0]$11031 4'0000
case
- assign $6\src32__data_o$next[3:0]$11123 $1\src32__data_o$next[3:0]$11118
+ assign $6\src32__data_o$next[3:0]$11031 $1\src32__data_o$next[3:0]$11026
end
sync always
- update \src32__data_o$next $0\src32__data_o$next[3:0]$11117
+ update \src32__data_o$next $0\src32__data_o$next[3:0]$11025
end
- attribute \src "libresoc.v:178154.3-178183.6"
- process $proc$libresoc.v:178154$11124
+ attribute \src "libresoc.v:175907.3-175936.6"
+ process $proc$libresoc.v:175907$11032
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11125 $1\wr_detect$7[0:0]$11126
- attribute \src "libresoc.v:178155.5-178155.29"
+ assign $0\wr_detect$7[0:0]$11033 $1\wr_detect$7[0:0]$11034
+ attribute \src "libresoc.v:175908.5-175908.29"
switch \initial
- attribute \src "libresoc.v:178155.9-178155.17"
+ attribute \src "libresoc.v:175908.9-175908.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11126 $4\wr_detect$7[0:0]$11129
+ assign $1\wr_detect$7[0:0]$11034 $4\wr_detect$7[0:0]$11037
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11127 1'1
+ assign $2\wr_detect$7[0:0]$11035 1'1
case
- assign $2\wr_detect$7[0:0]$11127 1'0
+ assign $2\wr_detect$7[0:0]$11035 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11128 1'1
+ assign $3\wr_detect$7[0:0]$11036 1'1
case
- assign $3\wr_detect$7[0:0]$11128 $2\wr_detect$7[0:0]$11127
+ assign $3\wr_detect$7[0:0]$11036 $2\wr_detect$7[0:0]$11035
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11129 1'1
+ assign $4\wr_detect$7[0:0]$11037 1'1
case
- assign $4\wr_detect$7[0:0]$11129 $3\wr_detect$7[0:0]$11128
+ assign $4\wr_detect$7[0:0]$11037 $3\wr_detect$7[0:0]$11036
end
case
- assign $1\wr_detect$7[0:0]$11126 1'0
+ assign $1\wr_detect$7[0:0]$11034 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11125
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11033
end
- attribute \src "libresoc.v:178184.3-178223.6"
- process $proc$libresoc.v:178184$11130
+ attribute \src "libresoc.v:175937.3-175976.6"
+ process $proc$libresoc.v:175937$11038
assign { } { }
assign { } { }
assign { } { }
- assign $0\r2__data_o$next[3:0]$11131 $6\r2__data_o$next[3:0]$11137
- attribute \src "libresoc.v:178185.5-178185.29"
+ assign $0\r2__data_o$next[3:0]$11039 $6\r2__data_o$next[3:0]$11045
+ attribute \src "libresoc.v:175938.5-175938.29"
switch \initial
- attribute \src "libresoc.v:178185.9-178185.17"
+ attribute \src "libresoc.v:175938.9-175938.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r2__data_o$next[3:0]$11132 $5\r2__data_o$next[3:0]$11136
+ assign $1\r2__data_o$next[3:0]$11040 $5\r2__data_o$next[3:0]$11044
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r2__data_o$next[3:0]$11133 \dest12__data_i
+ assign $2\r2__data_o$next[3:0]$11041 \dest12__data_i
case
- assign $2\r2__data_o$next[3:0]$11133 4'0000
+ assign $2\r2__data_o$next[3:0]$11041 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r2__data_o$next[3:0]$11134 \dest22__data_i
+ assign $3\r2__data_o$next[3:0]$11042 \dest22__data_i
case
- assign $3\r2__data_o$next[3:0]$11134 $2\r2__data_o$next[3:0]$11133
+ assign $3\r2__data_o$next[3:0]$11042 $2\r2__data_o$next[3:0]$11041
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r2__data_o$next[3:0]$11135 \w2__data_i
+ assign $4\r2__data_o$next[3:0]$11043 \w2__data_i
case
- assign $4\r2__data_o$next[3:0]$11135 $3\r2__data_o$next[3:0]$11134
+ assign $4\r2__data_o$next[3:0]$11043 $3\r2__data_o$next[3:0]$11042
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r2__data_o$next[3:0]$11136 \reg
+ assign $5\r2__data_o$next[3:0]$11044 \reg
case
- assign $5\r2__data_o$next[3:0]$11136 $4\r2__data_o$next[3:0]$11135
+ assign $5\r2__data_o$next[3:0]$11044 $4\r2__data_o$next[3:0]$11043
end
case
- assign $1\r2__data_o$next[3:0]$11132 4'0000
+ assign $1\r2__data_o$next[3:0]$11040 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r2__data_o$next[3:0]$11137 4'0000
+ assign $6\r2__data_o$next[3:0]$11045 4'0000
case
- assign $6\r2__data_o$next[3:0]$11137 $1\r2__data_o$next[3:0]$11132
+ assign $6\r2__data_o$next[3:0]$11045 $1\r2__data_o$next[3:0]$11040
end
sync always
- update \r2__data_o$next $0\r2__data_o$next[3:0]$11131
+ update \r2__data_o$next $0\r2__data_o$next[3:0]$11039
end
- attribute \src "libresoc.v:178224.3-178253.6"
- process $proc$libresoc.v:178224$11138
+ attribute \src "libresoc.v:175977.3-176006.6"
+ process $proc$libresoc.v:175977$11046
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11139 $1\wr_detect$10[0:0]$11140
- attribute \src "libresoc.v:178225.5-178225.29"
+ assign $0\wr_detect$10[0:0]$11047 $1\wr_detect$10[0:0]$11048
+ attribute \src "libresoc.v:175978.5-175978.29"
switch \initial
- attribute \src "libresoc.v:178225.9-178225.17"
+ attribute \src "libresoc.v:175978.9-175978.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11140 $4\wr_detect$10[0:0]$11143
+ assign $1\wr_detect$10[0:0]$11048 $4\wr_detect$10[0:0]$11051
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11141 1'1
+ assign $2\wr_detect$10[0:0]$11049 1'1
case
- assign $2\wr_detect$10[0:0]$11141 1'0
+ assign $2\wr_detect$10[0:0]$11049 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11142 1'1
+ assign $3\wr_detect$10[0:0]$11050 1'1
case
- assign $3\wr_detect$10[0:0]$11142 $2\wr_detect$10[0:0]$11141
+ assign $3\wr_detect$10[0:0]$11050 $2\wr_detect$10[0:0]$11049
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11143 1'1
+ assign $4\wr_detect$10[0:0]$11051 1'1
case
- assign $4\wr_detect$10[0:0]$11143 $3\wr_detect$10[0:0]$11142
+ assign $4\wr_detect$10[0:0]$11051 $3\wr_detect$10[0:0]$11050
end
case
- assign $1\wr_detect$10[0:0]$11140 1'0
+ assign $1\wr_detect$10[0:0]$11048 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11139
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11047
end
- attribute \src "libresoc.v:178254.3-178293.6"
- process $proc$libresoc.v:178254$11144
+ attribute \src "libresoc.v:176007.3-176046.6"
+ process $proc$libresoc.v:176007$11052
assign { } { }
assign { } { }
assign { } { }
- assign $0\r22__data_o$next[3:0]$11145 $6\r22__data_o$next[3:0]$11151
- attribute \src "libresoc.v:178255.5-178255.29"
+ assign $0\r22__data_o$next[3:0]$11053 $6\r22__data_o$next[3:0]$11059
+ attribute \src "libresoc.v:176008.5-176008.29"
switch \initial
- attribute \src "libresoc.v:178255.9-178255.17"
+ attribute \src "libresoc.v:176008.9-176008.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r22__data_o$next[3:0]$11146 $5\r22__data_o$next[3:0]$11150
+ assign $1\r22__data_o$next[3:0]$11054 $5\r22__data_o$next[3:0]$11058
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r22__data_o$next[3:0]$11147 \dest12__data_i
+ assign $2\r22__data_o$next[3:0]$11055 \dest12__data_i
case
- assign $2\r22__data_o$next[3:0]$11147 4'0000
+ assign $2\r22__data_o$next[3:0]$11055 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r22__data_o$next[3:0]$11148 \dest22__data_i
+ assign $3\r22__data_o$next[3:0]$11056 \dest22__data_i
case
- assign $3\r22__data_o$next[3:0]$11148 $2\r22__data_o$next[3:0]$11147
+ assign $3\r22__data_o$next[3:0]$11056 $2\r22__data_o$next[3:0]$11055
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r22__data_o$next[3:0]$11149 \w2__data_i
+ assign $4\r22__data_o$next[3:0]$11057 \w2__data_i
case
- assign $4\r22__data_o$next[3:0]$11149 $3\r22__data_o$next[3:0]$11148
+ assign $4\r22__data_o$next[3:0]$11057 $3\r22__data_o$next[3:0]$11056
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r22__data_o$next[3:0]$11150 \reg
+ assign $5\r22__data_o$next[3:0]$11058 \reg
case
- assign $5\r22__data_o$next[3:0]$11150 $4\r22__data_o$next[3:0]$11149
+ assign $5\r22__data_o$next[3:0]$11058 $4\r22__data_o$next[3:0]$11057
end
case
- assign $1\r22__data_o$next[3:0]$11146 4'0000
+ assign $1\r22__data_o$next[3:0]$11054 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r22__data_o$next[3:0]$11151 4'0000
+ assign $6\r22__data_o$next[3:0]$11059 4'0000
case
- assign $6\r22__data_o$next[3:0]$11151 $1\r22__data_o$next[3:0]$11146
+ assign $6\r22__data_o$next[3:0]$11059 $1\r22__data_o$next[3:0]$11054
end
sync always
- update \r22__data_o$next $0\r22__data_o$next[3:0]$11145
+ update \r22__data_o$next $0\r22__data_o$next[3:0]$11053
end
- attribute \src "libresoc.v:178294.3-178323.6"
- process $proc$libresoc.v:178294$11152
+ attribute \src "libresoc.v:176047.3-176076.6"
+ process $proc$libresoc.v:176047$11060
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11153 $1\wr_detect$13[0:0]$11154
- attribute \src "libresoc.v:178295.5-178295.29"
+ assign $0\wr_detect$13[0:0]$11061 $1\wr_detect$13[0:0]$11062
+ attribute \src "libresoc.v:176048.5-176048.29"
switch \initial
- attribute \src "libresoc.v:178295.9-178295.17"
+ attribute \src "libresoc.v:176048.9-176048.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11154 $4\wr_detect$13[0:0]$11157
+ assign $1\wr_detect$13[0:0]$11062 $4\wr_detect$13[0:0]$11065
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11155 1'1
+ assign $2\wr_detect$13[0:0]$11063 1'1
case
- assign $2\wr_detect$13[0:0]$11155 1'0
+ assign $2\wr_detect$13[0:0]$11063 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11156 1'1
+ assign $3\wr_detect$13[0:0]$11064 1'1
case
- assign $3\wr_detect$13[0:0]$11156 $2\wr_detect$13[0:0]$11155
+ assign $3\wr_detect$13[0:0]$11064 $2\wr_detect$13[0:0]$11063
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11157 1'1
+ assign $4\wr_detect$13[0:0]$11065 1'1
case
- assign $4\wr_detect$13[0:0]$11157 $3\wr_detect$13[0:0]$11156
+ assign $4\wr_detect$13[0:0]$11065 $3\wr_detect$13[0:0]$11064
end
case
- assign $1\wr_detect$13[0:0]$11154 1'0
+ assign $1\wr_detect$13[0:0]$11062 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11153
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11061
end
- connect \$9 $not$libresoc.v:177930$11076_Y
- connect \$12 $not$libresoc.v:177931$11077_Y
- connect \$1 $not$libresoc.v:177932$11078_Y
- connect \$3 $not$libresoc.v:177933$11079_Y
- connect \$6 $not$libresoc.v:177934$11080_Y
+ connect \$9 $not$libresoc.v:175683$10984_Y
+ connect \$12 $not$libresoc.v:175684$10985_Y
+ connect \$1 $not$libresoc.v:175685$10986_Y
+ connect \$3 $not$libresoc.v:175686$10987_Y
+ connect \$6 $not$libresoc.v:175687$10988_Y
end
-attribute \src "libresoc.v:178328.1-178773.10"
+attribute \src "libresoc.v:176081.1-176526.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2"
attribute \generator "nMigen"
module \reg_2$134
- attribute \src "libresoc.v:178329.7-178329.20"
+ attribute \src "libresoc.v:176082.7-176082.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $0\r2__data_o$next[1:0]$11217
- attribute \src "libresoc.v:178404.3-178405.37"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $0\r2__data_o$next[1:0]$11125
+ attribute \src "libresoc.v:176157.3-176158.37"
wire width 2 $0\r2__data_o[1:0]
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $0\reg$next[1:0]$11233
- attribute \src "libresoc.v:178402.3-178403.25"
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $0\reg$next[1:0]$11141
+ attribute \src "libresoc.v:176155.3-176156.25"
wire width 2 $0\reg[1:0]
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $0\src12__data_o$next[1:0]$11175
- attribute \src "libresoc.v:178410.3-178411.43"
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $0\src12__data_o$next[1:0]$11083
+ attribute \src "libresoc.v:176163.3-176164.43"
wire width 2 $0\src12__data_o[1:0]
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $0\src22__data_o$next[1:0]$11185
- attribute \src "libresoc.v:178408.3-178409.43"
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $0\src22__data_o$next[1:0]$11093
+ attribute \src "libresoc.v:176161.3-176162.43"
wire width 2 $0\src22__data_o[1:0]
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $0\src32__data_o$next[1:0]$11201
- attribute \src "libresoc.v:178406.3-178407.43"
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $0\src32__data_o$next[1:0]$11109
+ attribute \src "libresoc.v:176159.3-176160.43"
wire width 2 $0\src32__data_o[1:0]
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $0\wr_detect$10[0:0]$11226
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $0\wr_detect$4[0:0]$11194
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $0\wr_detect$7[0:0]$11210
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $0\wr_detect$10[0:0]$11134
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $0\wr_detect$4[0:0]$11102
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $0\wr_detect$7[0:0]$11118
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $1\r2__data_o$next[1:0]$11218
- attribute \src "libresoc.v:178356.13-178356.30"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $1\r2__data_o$next[1:0]$11126
+ attribute \src "libresoc.v:176109.13-176109.30"
wire width 2 $1\r2__data_o[1:0]
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $1\reg$next[1:0]$11234
- attribute \src "libresoc.v:178362.13-178362.25"
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $1\reg$next[1:0]$11142
+ attribute \src "libresoc.v:176115.13-176115.25"
wire width 2 $1\reg[1:0]
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $1\src12__data_o$next[1:0]$11176
- attribute \src "libresoc.v:178367.13-178367.33"
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $1\src12__data_o$next[1:0]$11084
+ attribute \src "libresoc.v:176120.13-176120.33"
wire width 2 $1\src12__data_o[1:0]
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $1\src22__data_o$next[1:0]$11186
- attribute \src "libresoc.v:178374.13-178374.33"
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $1\src22__data_o$next[1:0]$11094
+ attribute \src "libresoc.v:176127.13-176127.33"
wire width 2 $1\src22__data_o[1:0]
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $1\src32__data_o$next[1:0]$11202
- attribute \src "libresoc.v:178381.13-178381.33"
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $1\src32__data_o$next[1:0]$11110
+ attribute \src "libresoc.v:176134.13-176134.33"
wire width 2 $1\src32__data_o[1:0]
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $1\wr_detect$10[0:0]$11227
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $1\wr_detect$4[0:0]$11195
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $1\wr_detect$7[0:0]$11211
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $1\wr_detect$10[0:0]$11135
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $1\wr_detect$4[0:0]$11103
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $1\wr_detect$7[0:0]$11119
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $2\r2__data_o$next[1:0]$11219
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $2\reg$next[1:0]$11235
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $2\src12__data_o$next[1:0]$11177
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $2\src22__data_o$next[1:0]$11187
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $2\src32__data_o$next[1:0]$11203
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $2\wr_detect$10[0:0]$11228
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $2\wr_detect$4[0:0]$11196
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $2\wr_detect$7[0:0]$11212
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $2\r2__data_o$next[1:0]$11127
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $2\reg$next[1:0]$11143
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $2\src12__data_o$next[1:0]$11085
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $2\src22__data_o$next[1:0]$11095
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $2\src32__data_o$next[1:0]$11111
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $2\wr_detect$10[0:0]$11136
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $2\wr_detect$4[0:0]$11104
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $2\wr_detect$7[0:0]$11120
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $3\r2__data_o$next[1:0]$11220
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $3\reg$next[1:0]$11236
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $3\src12__data_o$next[1:0]$11178
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $3\src22__data_o$next[1:0]$11188
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $3\src32__data_o$next[1:0]$11204
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $3\wr_detect$10[0:0]$11229
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $3\wr_detect$4[0:0]$11197
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $3\wr_detect$7[0:0]$11213
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $3\r2__data_o$next[1:0]$11128
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $3\reg$next[1:0]$11144
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $3\src12__data_o$next[1:0]$11086
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $3\src22__data_o$next[1:0]$11096
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $3\src32__data_o$next[1:0]$11112
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $3\wr_detect$10[0:0]$11137
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $3\wr_detect$4[0:0]$11105
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $3\wr_detect$7[0:0]$11121
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $4\r2__data_o$next[1:0]$11221
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $4\reg$next[1:0]$11237
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $4\src12__data_o$next[1:0]$11179
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $4\src22__data_o$next[1:0]$11189
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $4\src32__data_o$next[1:0]$11205
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $4\wr_detect$10[0:0]$11230
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $4\wr_detect$4[0:0]$11198
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $4\wr_detect$7[0:0]$11214
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $4\r2__data_o$next[1:0]$11129
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $4\reg$next[1:0]$11145
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $4\src12__data_o$next[1:0]$11087
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $4\src22__data_o$next[1:0]$11097
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $4\src32__data_o$next[1:0]$11113
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $4\wr_detect$10[0:0]$11138
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $4\wr_detect$4[0:0]$11106
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $4\wr_detect$7[0:0]$11122
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $5\r2__data_o$next[1:0]$11222
- attribute \src "libresoc.v:178740.3-178772.6"
- wire width 2 $5\reg$next[1:0]$11238
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $5\src12__data_o$next[1:0]$11180
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $5\src22__data_o$next[1:0]$11190
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $5\src32__data_o$next[1:0]$11206
- attribute \src "libresoc.v:178704.3-178739.6"
- wire $5\wr_detect$10[0:0]$11231
- attribute \src "libresoc.v:178540.3-178575.6"
- wire $5\wr_detect$4[0:0]$11199
- attribute \src "libresoc.v:178622.3-178657.6"
- wire $5\wr_detect$7[0:0]$11215
- attribute \src "libresoc.v:178458.3-178493.6"
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $5\r2__data_o$next[1:0]$11130
+ attribute \src "libresoc.v:176493.3-176525.6"
+ wire width 2 $5\reg$next[1:0]$11146
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $5\src12__data_o$next[1:0]$11088
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $5\src22__data_o$next[1:0]$11098
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $5\src32__data_o$next[1:0]$11114
+ attribute \src "libresoc.v:176457.3-176492.6"
+ wire $5\wr_detect$10[0:0]$11139
+ attribute \src "libresoc.v:176293.3-176328.6"
+ wire $5\wr_detect$4[0:0]$11107
+ attribute \src "libresoc.v:176375.3-176410.6"
+ wire $5\wr_detect$7[0:0]$11123
+ attribute \src "libresoc.v:176211.3-176246.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $6\r2__data_o$next[1:0]$11223
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $6\src12__data_o$next[1:0]$11181
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $6\src22__data_o$next[1:0]$11191
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $6\src32__data_o$next[1:0]$11207
- attribute \src "libresoc.v:178658.3-178703.6"
- wire width 2 $7\r2__data_o$next[1:0]$11224
- attribute \src "libresoc.v:178412.3-178457.6"
- wire width 2 $7\src12__data_o$next[1:0]$11182
- attribute \src "libresoc.v:178494.3-178539.6"
- wire width 2 $7\src22__data_o$next[1:0]$11192
- attribute \src "libresoc.v:178576.3-178621.6"
- wire width 2 $7\src32__data_o$next[1:0]$11208
- attribute \src "libresoc.v:178398.17-178398.104"
- wire $not$libresoc.v:178398$11165_Y
- attribute \src "libresoc.v:178399.17-178399.100"
- wire $not$libresoc.v:178399$11166_Y
- attribute \src "libresoc.v:178400.17-178400.103"
- wire $not$libresoc.v:178400$11167_Y
- attribute \src "libresoc.v:178401.17-178401.103"
- wire $not$libresoc.v:178401$11168_Y
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $6\r2__data_o$next[1:0]$11131
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $6\src12__data_o$next[1:0]$11089
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $6\src22__data_o$next[1:0]$11099
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $6\src32__data_o$next[1:0]$11115
+ attribute \src "libresoc.v:176411.3-176456.6"
+ wire width 2 $7\r2__data_o$next[1:0]$11132
+ attribute \src "libresoc.v:176165.3-176210.6"
+ wire width 2 $7\src12__data_o$next[1:0]$11090
+ attribute \src "libresoc.v:176247.3-176292.6"
+ wire width 2 $7\src22__data_o$next[1:0]$11100
+ attribute \src "libresoc.v:176329.3-176374.6"
+ wire width 2 $7\src32__data_o$next[1:0]$11116
+ attribute \src "libresoc.v:176151.17-176151.104"
+ wire $not$libresoc.v:176151$11073_Y
+ attribute \src "libresoc.v:176152.17-176152.100"
+ wire $not$libresoc.v:176152$11074_Y
+ attribute \src "libresoc.v:176153.17-176153.103"
+ wire $not$libresoc.v:176153$11075_Y
+ attribute \src "libresoc.v:176154.17-176154.103"
+ wire $not$libresoc.v:176154$11076_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest12__data_i
wire width 2 input 13 \dest32__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 12 \dest32__wen
- attribute \src "libresoc.v:178329.7-178329.15"
+ attribute \src "libresoc.v:176082.7-176082.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 output 14 \r2__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178398$11165
+ cell $not $not$libresoc.v:176151$11073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:178398$11165_Y
+ connect \Y $not$libresoc.v:176151$11073_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178399$11166
+ cell $not $not$libresoc.v:176152$11074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:178399$11166_Y
+ connect \Y $not$libresoc.v:176152$11074_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178400$11167
+ cell $not $not$libresoc.v:176153$11075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:178400$11167_Y
+ connect \Y $not$libresoc.v:176153$11075_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178401$11168
+ cell $not $not$libresoc.v:176154$11076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:178401$11168_Y
+ connect \Y $not$libresoc.v:176154$11076_Y
end
- attribute \src "libresoc.v:178329.7-178329.20"
- process $proc$libresoc.v:178329$11239
+ attribute \src "libresoc.v:176082.7-176082.20"
+ process $proc$libresoc.v:176082$11147
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:178356.13-178356.30"
- process $proc$libresoc.v:178356$11240
+ attribute \src "libresoc.v:176109.13-176109.30"
+ process $proc$libresoc.v:176109$11148
assign { } { }
assign $1\r2__data_o[1:0] 2'00
sync always
sync init
update \r2__data_o $1\r2__data_o[1:0]
end
- attribute \src "libresoc.v:178362.13-178362.25"
- process $proc$libresoc.v:178362$11241
+ attribute \src "libresoc.v:176115.13-176115.25"
+ process $proc$libresoc.v:176115$11149
assign { } { }
assign $1\reg[1:0] 2'00
sync always
sync init
update \reg $1\reg[1:0]
end
- attribute \src "libresoc.v:178367.13-178367.33"
- process $proc$libresoc.v:178367$11242
+ attribute \src "libresoc.v:176120.13-176120.33"
+ process $proc$libresoc.v:176120$11150
assign { } { }
assign $1\src12__data_o[1:0] 2'00
sync always
sync init
update \src12__data_o $1\src12__data_o[1:0]
end
- attribute \src "libresoc.v:178374.13-178374.33"
- process $proc$libresoc.v:178374$11243
+ attribute \src "libresoc.v:176127.13-176127.33"
+ process $proc$libresoc.v:176127$11151
assign { } { }
assign $1\src22__data_o[1:0] 2'00
sync always
sync init
update \src22__data_o $1\src22__data_o[1:0]
end
- attribute \src "libresoc.v:178381.13-178381.33"
- process $proc$libresoc.v:178381$11244
+ attribute \src "libresoc.v:176134.13-176134.33"
+ process $proc$libresoc.v:176134$11152
assign { } { }
assign $1\src32__data_o[1:0] 2'00
sync always
sync init
update \src32__data_o $1\src32__data_o[1:0]
end
- attribute \src "libresoc.v:178402.3-178403.25"
- process $proc$libresoc.v:178402$11169
+ attribute \src "libresoc.v:176155.3-176156.25"
+ process $proc$libresoc.v:176155$11077
assign { } { }
assign $0\reg[1:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[1:0]
end
- attribute \src "libresoc.v:178404.3-178405.37"
- process $proc$libresoc.v:178404$11170
+ attribute \src "libresoc.v:176157.3-176158.37"
+ process $proc$libresoc.v:176157$11078
assign { } { }
assign $0\r2__data_o[1:0] \r2__data_o$next
sync posedge \coresync_clk
update \r2__data_o $0\r2__data_o[1:0]
end
- attribute \src "libresoc.v:178406.3-178407.43"
- process $proc$libresoc.v:178406$11171
+ attribute \src "libresoc.v:176159.3-176160.43"
+ process $proc$libresoc.v:176159$11079
assign { } { }
assign $0\src32__data_o[1:0] \src32__data_o$next
sync posedge \coresync_clk
update \src32__data_o $0\src32__data_o[1:0]
end
- attribute \src "libresoc.v:178408.3-178409.43"
- process $proc$libresoc.v:178408$11172
+ attribute \src "libresoc.v:176161.3-176162.43"
+ process $proc$libresoc.v:176161$11080
assign { } { }
assign $0\src22__data_o[1:0] \src22__data_o$next
sync posedge \coresync_clk
update \src22__data_o $0\src22__data_o[1:0]
end
- attribute \src "libresoc.v:178410.3-178411.43"
- process $proc$libresoc.v:178410$11173
+ attribute \src "libresoc.v:176163.3-176164.43"
+ process $proc$libresoc.v:176163$11081
assign { } { }
assign $0\src12__data_o[1:0] \src12__data_o$next
sync posedge \coresync_clk
update \src12__data_o $0\src12__data_o[1:0]
end
- attribute \src "libresoc.v:178412.3-178457.6"
- process $proc$libresoc.v:178412$11174
+ attribute \src "libresoc.v:176165.3-176210.6"
+ process $proc$libresoc.v:176165$11082
assign { } { }
assign { } { }
assign { } { }
- assign $0\src12__data_o$next[1:0]$11175 $7\src12__data_o$next[1:0]$11182
- attribute \src "libresoc.v:178413.5-178413.29"
+ assign $0\src12__data_o$next[1:0]$11083 $7\src12__data_o$next[1:0]$11090
+ attribute \src "libresoc.v:176166.5-176166.29"
switch \initial
- attribute \src "libresoc.v:178413.9-178413.17"
+ attribute \src "libresoc.v:176166.9-176166.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src12__data_o$next[1:0]$11176 $6\src12__data_o$next[1:0]$11181
+ assign $1\src12__data_o$next[1:0]$11084 $6\src12__data_o$next[1:0]$11089
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src12__data_o$next[1:0]$11177 \dest12__data_i
+ assign $2\src12__data_o$next[1:0]$11085 \dest12__data_i
case
- assign $2\src12__data_o$next[1:0]$11177 2'00
+ assign $2\src12__data_o$next[1:0]$11085 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src12__data_o$next[1:0]$11178 \dest22__data_i
+ assign $3\src12__data_o$next[1:0]$11086 \dest22__data_i
case
- assign $3\src12__data_o$next[1:0]$11178 $2\src12__data_o$next[1:0]$11177
+ assign $3\src12__data_o$next[1:0]$11086 $2\src12__data_o$next[1:0]$11085
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src12__data_o$next[1:0]$11179 \dest32__data_i
+ assign $4\src12__data_o$next[1:0]$11087 \dest32__data_i
case
- assign $4\src12__data_o$next[1:0]$11179 $3\src12__data_o$next[1:0]$11178
+ assign $4\src12__data_o$next[1:0]$11087 $3\src12__data_o$next[1:0]$11086
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src12__data_o$next[1:0]$11180 \w2__data_i
+ assign $5\src12__data_o$next[1:0]$11088 \w2__data_i
case
- assign $5\src12__data_o$next[1:0]$11180 $4\src12__data_o$next[1:0]$11179
+ assign $5\src12__data_o$next[1:0]$11088 $4\src12__data_o$next[1:0]$11087
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src12__data_o$next[1:0]$11181 \reg
+ assign $6\src12__data_o$next[1:0]$11089 \reg
case
- assign $6\src12__data_o$next[1:0]$11181 $5\src12__data_o$next[1:0]$11180
+ assign $6\src12__data_o$next[1:0]$11089 $5\src12__data_o$next[1:0]$11088
end
case
- assign $1\src12__data_o$next[1:0]$11176 2'00
+ assign $1\src12__data_o$next[1:0]$11084 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src12__data_o$next[1:0]$11182 2'00
+ assign $7\src12__data_o$next[1:0]$11090 2'00
case
- assign $7\src12__data_o$next[1:0]$11182 $1\src12__data_o$next[1:0]$11176
+ assign $7\src12__data_o$next[1:0]$11090 $1\src12__data_o$next[1:0]$11084
end
sync always
- update \src12__data_o$next $0\src12__data_o$next[1:0]$11175
+ update \src12__data_o$next $0\src12__data_o$next[1:0]$11083
end
- attribute \src "libresoc.v:178458.3-178493.6"
- process $proc$libresoc.v:178458$11183
+ attribute \src "libresoc.v:176211.3-176246.6"
+ process $proc$libresoc.v:176211$11091
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:178459.5-178459.29"
+ attribute \src "libresoc.v:176212.5-176212.29"
switch \initial
- attribute \src "libresoc.v:178459.9-178459.17"
+ attribute \src "libresoc.v:176212.9-176212.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:178494.3-178539.6"
- process $proc$libresoc.v:178494$11184
+ attribute \src "libresoc.v:176247.3-176292.6"
+ process $proc$libresoc.v:176247$11092
assign { } { }
assign { } { }
assign { } { }
- assign $0\src22__data_o$next[1:0]$11185 $7\src22__data_o$next[1:0]$11192
- attribute \src "libresoc.v:178495.5-178495.29"
+ assign $0\src22__data_o$next[1:0]$11093 $7\src22__data_o$next[1:0]$11100
+ attribute \src "libresoc.v:176248.5-176248.29"
switch \initial
- attribute \src "libresoc.v:178495.9-178495.17"
+ attribute \src "libresoc.v:176248.9-176248.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src22__data_o$next[1:0]$11186 $6\src22__data_o$next[1:0]$11191
+ assign $1\src22__data_o$next[1:0]$11094 $6\src22__data_o$next[1:0]$11099
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src22__data_o$next[1:0]$11187 \dest12__data_i
+ assign $2\src22__data_o$next[1:0]$11095 \dest12__data_i
case
- assign $2\src22__data_o$next[1:0]$11187 2'00
+ assign $2\src22__data_o$next[1:0]$11095 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src22__data_o$next[1:0]$11188 \dest22__data_i
+ assign $3\src22__data_o$next[1:0]$11096 \dest22__data_i
case
- assign $3\src22__data_o$next[1:0]$11188 $2\src22__data_o$next[1:0]$11187
+ assign $3\src22__data_o$next[1:0]$11096 $2\src22__data_o$next[1:0]$11095
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src22__data_o$next[1:0]$11189 \dest32__data_i
+ assign $4\src22__data_o$next[1:0]$11097 \dest32__data_i
case
- assign $4\src22__data_o$next[1:0]$11189 $3\src22__data_o$next[1:0]$11188
+ assign $4\src22__data_o$next[1:0]$11097 $3\src22__data_o$next[1:0]$11096
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src22__data_o$next[1:0]$11190 \w2__data_i
+ assign $5\src22__data_o$next[1:0]$11098 \w2__data_i
case
- assign $5\src22__data_o$next[1:0]$11190 $4\src22__data_o$next[1:0]$11189
+ assign $5\src22__data_o$next[1:0]$11098 $4\src22__data_o$next[1:0]$11097
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src22__data_o$next[1:0]$11191 \reg
+ assign $6\src22__data_o$next[1:0]$11099 \reg
case
- assign $6\src22__data_o$next[1:0]$11191 $5\src22__data_o$next[1:0]$11190
+ assign $6\src22__data_o$next[1:0]$11099 $5\src22__data_o$next[1:0]$11098
end
case
- assign $1\src22__data_o$next[1:0]$11186 2'00
+ assign $1\src22__data_o$next[1:0]$11094 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src22__data_o$next[1:0]$11192 2'00
+ assign $7\src22__data_o$next[1:0]$11100 2'00
case
- assign $7\src22__data_o$next[1:0]$11192 $1\src22__data_o$next[1:0]$11186
+ assign $7\src22__data_o$next[1:0]$11100 $1\src22__data_o$next[1:0]$11094
end
sync always
- update \src22__data_o$next $0\src22__data_o$next[1:0]$11185
+ update \src22__data_o$next $0\src22__data_o$next[1:0]$11093
end
- attribute \src "libresoc.v:178540.3-178575.6"
- process $proc$libresoc.v:178540$11193
+ attribute \src "libresoc.v:176293.3-176328.6"
+ process $proc$libresoc.v:176293$11101
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11194 $1\wr_detect$4[0:0]$11195
- attribute \src "libresoc.v:178541.5-178541.29"
+ assign $0\wr_detect$4[0:0]$11102 $1\wr_detect$4[0:0]$11103
+ attribute \src "libresoc.v:176294.5-176294.29"
switch \initial
- attribute \src "libresoc.v:178541.9-178541.17"
+ attribute \src "libresoc.v:176294.9-176294.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11195 $5\wr_detect$4[0:0]$11199
+ assign $1\wr_detect$4[0:0]$11103 $5\wr_detect$4[0:0]$11107
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11196 1'1
+ assign $2\wr_detect$4[0:0]$11104 1'1
case
- assign $2\wr_detect$4[0:0]$11196 1'0
+ assign $2\wr_detect$4[0:0]$11104 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11197 1'1
+ assign $3\wr_detect$4[0:0]$11105 1'1
case
- assign $3\wr_detect$4[0:0]$11197 $2\wr_detect$4[0:0]$11196
+ assign $3\wr_detect$4[0:0]$11105 $2\wr_detect$4[0:0]$11104
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11198 1'1
+ assign $4\wr_detect$4[0:0]$11106 1'1
case
- assign $4\wr_detect$4[0:0]$11198 $3\wr_detect$4[0:0]$11197
+ assign $4\wr_detect$4[0:0]$11106 $3\wr_detect$4[0:0]$11105
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11199 1'1
+ assign $5\wr_detect$4[0:0]$11107 1'1
case
- assign $5\wr_detect$4[0:0]$11199 $4\wr_detect$4[0:0]$11198
+ assign $5\wr_detect$4[0:0]$11107 $4\wr_detect$4[0:0]$11106
end
case
- assign $1\wr_detect$4[0:0]$11195 1'0
+ assign $1\wr_detect$4[0:0]$11103 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11194
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11102
end
- attribute \src "libresoc.v:178576.3-178621.6"
- process $proc$libresoc.v:178576$11200
+ attribute \src "libresoc.v:176329.3-176374.6"
+ process $proc$libresoc.v:176329$11108
assign { } { }
assign { } { }
assign { } { }
- assign $0\src32__data_o$next[1:0]$11201 $7\src32__data_o$next[1:0]$11208
- attribute \src "libresoc.v:178577.5-178577.29"
+ assign $0\src32__data_o$next[1:0]$11109 $7\src32__data_o$next[1:0]$11116
+ attribute \src "libresoc.v:176330.5-176330.29"
switch \initial
- attribute \src "libresoc.v:178577.9-178577.17"
+ attribute \src "libresoc.v:176330.9-176330.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src32__data_o$next[1:0]$11202 $6\src32__data_o$next[1:0]$11207
+ assign $1\src32__data_o$next[1:0]$11110 $6\src32__data_o$next[1:0]$11115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src32__data_o$next[1:0]$11203 \dest12__data_i
+ assign $2\src32__data_o$next[1:0]$11111 \dest12__data_i
case
- assign $2\src32__data_o$next[1:0]$11203 2'00
+ assign $2\src32__data_o$next[1:0]$11111 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src32__data_o$next[1:0]$11204 \dest22__data_i
+ assign $3\src32__data_o$next[1:0]$11112 \dest22__data_i
case
- assign $3\src32__data_o$next[1:0]$11204 $2\src32__data_o$next[1:0]$11203
+ assign $3\src32__data_o$next[1:0]$11112 $2\src32__data_o$next[1:0]$11111
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src32__data_o$next[1:0]$11205 \dest32__data_i
+ assign $4\src32__data_o$next[1:0]$11113 \dest32__data_i
case
- assign $4\src32__data_o$next[1:0]$11205 $3\src32__data_o$next[1:0]$11204
+ assign $4\src32__data_o$next[1:0]$11113 $3\src32__data_o$next[1:0]$11112
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src32__data_o$next[1:0]$11206 \w2__data_i
+ assign $5\src32__data_o$next[1:0]$11114 \w2__data_i
case
- assign $5\src32__data_o$next[1:0]$11206 $4\src32__data_o$next[1:0]$11205
+ assign $5\src32__data_o$next[1:0]$11114 $4\src32__data_o$next[1:0]$11113
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src32__data_o$next[1:0]$11207 \reg
+ assign $6\src32__data_o$next[1:0]$11115 \reg
case
- assign $6\src32__data_o$next[1:0]$11207 $5\src32__data_o$next[1:0]$11206
+ assign $6\src32__data_o$next[1:0]$11115 $5\src32__data_o$next[1:0]$11114
end
case
- assign $1\src32__data_o$next[1:0]$11202 2'00
+ assign $1\src32__data_o$next[1:0]$11110 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\src32__data_o$next[1:0]$11208 2'00
+ assign $7\src32__data_o$next[1:0]$11116 2'00
case
- assign $7\src32__data_o$next[1:0]$11208 $1\src32__data_o$next[1:0]$11202
+ assign $7\src32__data_o$next[1:0]$11116 $1\src32__data_o$next[1:0]$11110
end
sync always
- update \src32__data_o$next $0\src32__data_o$next[1:0]$11201
+ update \src32__data_o$next $0\src32__data_o$next[1:0]$11109
end
- attribute \src "libresoc.v:178622.3-178657.6"
- process $proc$libresoc.v:178622$11209
+ attribute \src "libresoc.v:176375.3-176410.6"
+ process $proc$libresoc.v:176375$11117
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11210 $1\wr_detect$7[0:0]$11211
- attribute \src "libresoc.v:178623.5-178623.29"
+ assign $0\wr_detect$7[0:0]$11118 $1\wr_detect$7[0:0]$11119
+ attribute \src "libresoc.v:176376.5-176376.29"
switch \initial
- attribute \src "libresoc.v:178623.9-178623.17"
+ attribute \src "libresoc.v:176376.9-176376.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11211 $5\wr_detect$7[0:0]$11215
+ assign $1\wr_detect$7[0:0]$11119 $5\wr_detect$7[0:0]$11123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11212 1'1
+ assign $2\wr_detect$7[0:0]$11120 1'1
case
- assign $2\wr_detect$7[0:0]$11212 1'0
+ assign $2\wr_detect$7[0:0]$11120 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11213 1'1
+ assign $3\wr_detect$7[0:0]$11121 1'1
case
- assign $3\wr_detect$7[0:0]$11213 $2\wr_detect$7[0:0]$11212
+ assign $3\wr_detect$7[0:0]$11121 $2\wr_detect$7[0:0]$11120
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11214 1'1
+ assign $4\wr_detect$7[0:0]$11122 1'1
case
- assign $4\wr_detect$7[0:0]$11214 $3\wr_detect$7[0:0]$11213
+ assign $4\wr_detect$7[0:0]$11122 $3\wr_detect$7[0:0]$11121
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11215 1'1
+ assign $5\wr_detect$7[0:0]$11123 1'1
case
- assign $5\wr_detect$7[0:0]$11215 $4\wr_detect$7[0:0]$11214
+ assign $5\wr_detect$7[0:0]$11123 $4\wr_detect$7[0:0]$11122
end
case
- assign $1\wr_detect$7[0:0]$11211 1'0
+ assign $1\wr_detect$7[0:0]$11119 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11210
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11118
end
- attribute \src "libresoc.v:178658.3-178703.6"
- process $proc$libresoc.v:178658$11216
+ attribute \src "libresoc.v:176411.3-176456.6"
+ process $proc$libresoc.v:176411$11124
assign { } { }
assign { } { }
assign { } { }
- assign $0\r2__data_o$next[1:0]$11217 $7\r2__data_o$next[1:0]$11224
- attribute \src "libresoc.v:178659.5-178659.29"
+ assign $0\r2__data_o$next[1:0]$11125 $7\r2__data_o$next[1:0]$11132
+ attribute \src "libresoc.v:176412.5-176412.29"
switch \initial
- attribute \src "libresoc.v:178659.9-178659.17"
+ attribute \src "libresoc.v:176412.9-176412.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r2__data_o$next[1:0]$11218 $6\r2__data_o$next[1:0]$11223
+ assign $1\r2__data_o$next[1:0]$11126 $6\r2__data_o$next[1:0]$11131
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r2__data_o$next[1:0]$11219 \dest12__data_i
+ assign $2\r2__data_o$next[1:0]$11127 \dest12__data_i
case
- assign $2\r2__data_o$next[1:0]$11219 2'00
+ assign $2\r2__data_o$next[1:0]$11127 2'00
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r2__data_o$next[1:0]$11220 \dest22__data_i
+ assign $3\r2__data_o$next[1:0]$11128 \dest22__data_i
case
- assign $3\r2__data_o$next[1:0]$11220 $2\r2__data_o$next[1:0]$11219
+ assign $3\r2__data_o$next[1:0]$11128 $2\r2__data_o$next[1:0]$11127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r2__data_o$next[1:0]$11221 \dest32__data_i
+ assign $4\r2__data_o$next[1:0]$11129 \dest32__data_i
case
- assign $4\r2__data_o$next[1:0]$11221 $3\r2__data_o$next[1:0]$11220
+ assign $4\r2__data_o$next[1:0]$11129 $3\r2__data_o$next[1:0]$11128
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r2__data_o$next[1:0]$11222 \w2__data_i
+ assign $5\r2__data_o$next[1:0]$11130 \w2__data_i
case
- assign $5\r2__data_o$next[1:0]$11222 $4\r2__data_o$next[1:0]$11221
+ assign $5\r2__data_o$next[1:0]$11130 $4\r2__data_o$next[1:0]$11129
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r2__data_o$next[1:0]$11223 \reg
+ assign $6\r2__data_o$next[1:0]$11131 \reg
case
- assign $6\r2__data_o$next[1:0]$11223 $5\r2__data_o$next[1:0]$11222
+ assign $6\r2__data_o$next[1:0]$11131 $5\r2__data_o$next[1:0]$11130
end
case
- assign $1\r2__data_o$next[1:0]$11218 2'00
+ assign $1\r2__data_o$next[1:0]$11126 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\r2__data_o$next[1:0]$11224 2'00
+ assign $7\r2__data_o$next[1:0]$11132 2'00
case
- assign $7\r2__data_o$next[1:0]$11224 $1\r2__data_o$next[1:0]$11218
+ assign $7\r2__data_o$next[1:0]$11132 $1\r2__data_o$next[1:0]$11126
end
sync always
- update \r2__data_o$next $0\r2__data_o$next[1:0]$11217
+ update \r2__data_o$next $0\r2__data_o$next[1:0]$11125
end
- attribute \src "libresoc.v:178704.3-178739.6"
- process $proc$libresoc.v:178704$11225
+ attribute \src "libresoc.v:176457.3-176492.6"
+ process $proc$libresoc.v:176457$11133
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11226 $1\wr_detect$10[0:0]$11227
- attribute \src "libresoc.v:178705.5-178705.29"
+ assign $0\wr_detect$10[0:0]$11134 $1\wr_detect$10[0:0]$11135
+ attribute \src "libresoc.v:176458.5-176458.29"
switch \initial
- attribute \src "libresoc.v:178705.9-178705.17"
+ attribute \src "libresoc.v:176458.9-176458.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11227 $5\wr_detect$10[0:0]$11231
+ assign $1\wr_detect$10[0:0]$11135 $5\wr_detect$10[0:0]$11139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11228 1'1
+ assign $2\wr_detect$10[0:0]$11136 1'1
case
- assign $2\wr_detect$10[0:0]$11228 1'0
+ assign $2\wr_detect$10[0:0]$11136 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11229 1'1
+ assign $3\wr_detect$10[0:0]$11137 1'1
case
- assign $3\wr_detect$10[0:0]$11229 $2\wr_detect$10[0:0]$11228
+ assign $3\wr_detect$10[0:0]$11137 $2\wr_detect$10[0:0]$11136
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11230 1'1
+ assign $4\wr_detect$10[0:0]$11138 1'1
case
- assign $4\wr_detect$10[0:0]$11230 $3\wr_detect$10[0:0]$11229
+ assign $4\wr_detect$10[0:0]$11138 $3\wr_detect$10[0:0]$11137
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$10[0:0]$11231 1'1
+ assign $5\wr_detect$10[0:0]$11139 1'1
case
- assign $5\wr_detect$10[0:0]$11231 $4\wr_detect$10[0:0]$11230
+ assign $5\wr_detect$10[0:0]$11139 $4\wr_detect$10[0:0]$11138
end
case
- assign $1\wr_detect$10[0:0]$11227 1'0
+ assign $1\wr_detect$10[0:0]$11135 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11226
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11134
end
- attribute \src "libresoc.v:178740.3-178772.6"
- process $proc$libresoc.v:178740$11232
+ attribute \src "libresoc.v:176493.3-176525.6"
+ process $proc$libresoc.v:176493$11140
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[1:0]$11233 $5\reg$next[1:0]$11238
- attribute \src "libresoc.v:178741.5-178741.29"
+ assign $0\reg$next[1:0]$11141 $5\reg$next[1:0]$11146
+ attribute \src "libresoc.v:176494.5-176494.29"
switch \initial
- attribute \src "libresoc.v:178741.9-178741.17"
+ attribute \src "libresoc.v:176494.9-176494.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[1:0]$11234 \dest12__data_i
+ assign $1\reg$next[1:0]$11142 \dest12__data_i
case
- assign $1\reg$next[1:0]$11234 \reg
+ assign $1\reg$next[1:0]$11142 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest22__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[1:0]$11235 \dest22__data_i
+ assign $2\reg$next[1:0]$11143 \dest22__data_i
case
- assign $2\reg$next[1:0]$11235 $1\reg$next[1:0]$11234
+ assign $2\reg$next[1:0]$11143 $1\reg$next[1:0]$11142
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest32__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[1:0]$11236 \dest32__data_i
+ assign $3\reg$next[1:0]$11144 \dest32__data_i
case
- assign $3\reg$next[1:0]$11236 $2\reg$next[1:0]$11235
+ assign $3\reg$next[1:0]$11144 $2\reg$next[1:0]$11143
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[1:0]$11237 \w2__data_i
+ assign $4\reg$next[1:0]$11145 \w2__data_i
case
- assign $4\reg$next[1:0]$11237 $3\reg$next[1:0]$11236
+ assign $4\reg$next[1:0]$11145 $3\reg$next[1:0]$11144
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[1:0]$11238 2'00
+ assign $5\reg$next[1:0]$11146 2'00
case
- assign $5\reg$next[1:0]$11238 $4\reg$next[1:0]$11237
+ assign $5\reg$next[1:0]$11146 $4\reg$next[1:0]$11145
end
sync always
- update \reg$next $0\reg$next[1:0]$11233
+ update \reg$next $0\reg$next[1:0]$11141
end
- connect \$9 $not$libresoc.v:178398$11165_Y
- connect \$1 $not$libresoc.v:178399$11166_Y
- connect \$3 $not$libresoc.v:178400$11167_Y
- connect \$6 $not$libresoc.v:178401$11168_Y
+ connect \$9 $not$libresoc.v:176151$11073_Y
+ connect \$1 $not$libresoc.v:176152$11074_Y
+ connect \$3 $not$libresoc.v:176153$11075_Y
+ connect \$6 $not$libresoc.v:176154$11076_Y
end
-attribute \src "libresoc.v:178777.1-179126.10"
+attribute \src "libresoc.v:176530.1-176879.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2"
attribute \generator "nMigen"
module \reg_2$137
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $0\cia2__data_o$next[63:0]$11253
- attribute \src "libresoc.v:178845.3-178846.41"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $0\cia2__data_o$next[63:0]$11161
+ attribute \src "libresoc.v:176598.3-176599.41"
wire width 64 $0\cia2__data_o[63:0]
- attribute \src "libresoc.v:178778.7-178778.20"
+ attribute \src "libresoc.v:176531.7-176531.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $0\msr2__data_o$next[63:0]$11263
- attribute \src "libresoc.v:178843.3-178844.41"
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $0\msr2__data_o$next[63:0]$11171
+ attribute \src "libresoc.v:176596.3-176597.41"
wire width 64 $0\msr2__data_o[63:0]
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $0\reg$next[63:0]$11295
- attribute \src "libresoc.v:178839.3-178840.25"
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $0\reg$next[63:0]$11203
+ attribute \src "libresoc.v:176592.3-176593.25"
wire width 64 $0\reg[63:0]
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $0\sv2__data_o$next[63:0]$11279
- attribute \src "libresoc.v:178841.3-178842.39"
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $0\sv2__data_o$next[63:0]$11187
+ attribute \src "libresoc.v:176594.3-176595.39"
wire width 64 $0\sv2__data_o[63:0]
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $0\wr_detect$4[0:0]$11272
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $0\wr_detect$7[0:0]$11288
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $0\wr_detect$4[0:0]$11180
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $0\wr_detect$7[0:0]$11196
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $1\cia2__data_o$next[63:0]$11254
- attribute \src "libresoc.v:178787.14-178787.49"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $1\cia2__data_o$next[63:0]$11162
+ attribute \src "libresoc.v:176540.14-176540.49"
wire width 64 $1\cia2__data_o[63:0]
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $1\msr2__data_o$next[63:0]$11264
- attribute \src "libresoc.v:178804.14-178804.49"
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $1\msr2__data_o$next[63:0]$11172
+ attribute \src "libresoc.v:176557.14-176557.49"
wire width 64 $1\msr2__data_o[63:0]
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $1\reg$next[63:0]$11296
- attribute \src "libresoc.v:178816.14-178816.42"
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $1\reg$next[63:0]$11204
+ attribute \src "libresoc.v:176569.14-176569.42"
wire width 64 $1\reg[63:0]
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $1\sv2__data_o$next[63:0]$11280
- attribute \src "libresoc.v:178823.14-178823.48"
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $1\sv2__data_o$next[63:0]$11188
+ attribute \src "libresoc.v:176576.14-176576.48"
wire width 64 $1\sv2__data_o[63:0]
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $1\wr_detect$4[0:0]$11273
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $1\wr_detect$7[0:0]$11289
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $1\wr_detect$4[0:0]$11181
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $1\wr_detect$7[0:0]$11197
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $2\cia2__data_o$next[63:0]$11255
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $2\msr2__data_o$next[63:0]$11265
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $2\reg$next[63:0]$11297
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $2\sv2__data_o$next[63:0]$11281
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $2\wr_detect$4[0:0]$11274
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $2\wr_detect$7[0:0]$11290
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $2\cia2__data_o$next[63:0]$11163
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $2\msr2__data_o$next[63:0]$11173
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $2\reg$next[63:0]$11205
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $2\sv2__data_o$next[63:0]$11189
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $2\wr_detect$4[0:0]$11182
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $2\wr_detect$7[0:0]$11198
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $3\cia2__data_o$next[63:0]$11256
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $3\msr2__data_o$next[63:0]$11266
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $3\reg$next[63:0]$11298
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $3\sv2__data_o$next[63:0]$11282
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $3\wr_detect$4[0:0]$11275
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $3\wr_detect$7[0:0]$11291
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $3\cia2__data_o$next[63:0]$11164
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $3\msr2__data_o$next[63:0]$11174
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $3\reg$next[63:0]$11206
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $3\sv2__data_o$next[63:0]$11190
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $3\wr_detect$4[0:0]$11183
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $3\wr_detect$7[0:0]$11199
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $4\cia2__data_o$next[63:0]$11257
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $4\msr2__data_o$next[63:0]$11267
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $4\reg$next[63:0]$11299
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $4\sv2__data_o$next[63:0]$11283
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $4\wr_detect$4[0:0]$11276
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $4\wr_detect$7[0:0]$11292
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $4\cia2__data_o$next[63:0]$11165
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $4\msr2__data_o$next[63:0]$11175
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $4\reg$next[63:0]$11207
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $4\sv2__data_o$next[63:0]$11191
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $4\wr_detect$4[0:0]$11184
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $4\wr_detect$7[0:0]$11200
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $5\cia2__data_o$next[63:0]$11258
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $5\msr2__data_o$next[63:0]$11268
- attribute \src "libresoc.v:179093.3-179125.6"
- wire width 64 $5\reg$next[63:0]$11300
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $5\sv2__data_o$next[63:0]$11284
- attribute \src "libresoc.v:178975.3-179010.6"
- wire $5\wr_detect$4[0:0]$11277
- attribute \src "libresoc.v:179057.3-179092.6"
- wire $5\wr_detect$7[0:0]$11293
- attribute \src "libresoc.v:178893.3-178928.6"
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $5\cia2__data_o$next[63:0]$11166
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $5\msr2__data_o$next[63:0]$11176
+ attribute \src "libresoc.v:176846.3-176878.6"
+ wire width 64 $5\reg$next[63:0]$11208
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $5\sv2__data_o$next[63:0]$11192
+ attribute \src "libresoc.v:176728.3-176763.6"
+ wire $5\wr_detect$4[0:0]$11185
+ attribute \src "libresoc.v:176810.3-176845.6"
+ wire $5\wr_detect$7[0:0]$11201
+ attribute \src "libresoc.v:176646.3-176681.6"
wire $5\wr_detect[0:0]
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $6\cia2__data_o$next[63:0]$11259
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $6\msr2__data_o$next[63:0]$11269
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $6\sv2__data_o$next[63:0]$11285
- attribute \src "libresoc.v:178847.3-178892.6"
- wire width 64 $7\cia2__data_o$next[63:0]$11260
- attribute \src "libresoc.v:178929.3-178974.6"
- wire width 64 $7\msr2__data_o$next[63:0]$11270
- attribute \src "libresoc.v:179011.3-179056.6"
- wire width 64 $7\sv2__data_o$next[63:0]$11286
- attribute \src "libresoc.v:178836.17-178836.100"
- wire $not$libresoc.v:178836$11245_Y
- attribute \src "libresoc.v:178837.17-178837.103"
- wire $not$libresoc.v:178837$11246_Y
- attribute \src "libresoc.v:178838.17-178838.103"
- wire $not$libresoc.v:178838$11247_Y
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $6\cia2__data_o$next[63:0]$11167
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $6\msr2__data_o$next[63:0]$11177
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $6\sv2__data_o$next[63:0]$11193
+ attribute \src "libresoc.v:176600.3-176645.6"
+ wire width 64 $7\cia2__data_o$next[63:0]$11168
+ attribute \src "libresoc.v:176682.3-176727.6"
+ wire width 64 $7\msr2__data_o$next[63:0]$11178
+ attribute \src "libresoc.v:176764.3-176809.6"
+ wire width 64 $7\sv2__data_o$next[63:0]$11194
+ attribute \src "libresoc.v:176589.17-176589.100"
+ wire $not$libresoc.v:176589$11153_Y
+ attribute \src "libresoc.v:176590.17-176590.103"
+ wire $not$libresoc.v:176590$11154_Y
+ attribute \src "libresoc.v:176591.17-176591.103"
+ wire $not$libresoc.v:176591$11155_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire width 64 \cia2__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia2__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr12__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 14 \d_wr12__wen
- attribute \src "libresoc.v:178778.7-178778.15"
+ attribute \src "libresoc.v:176531.7-176531.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 11 \msr2__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178836$11245
+ cell $not $not$libresoc.v:176589$11153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:178836$11245_Y
+ connect \Y $not$libresoc.v:176589$11153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178837$11246
+ cell $not $not$libresoc.v:176590$11154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:178837$11246_Y
+ connect \Y $not$libresoc.v:176590$11154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:178838$11247
+ cell $not $not$libresoc.v:176591$11155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:178838$11247_Y
+ connect \Y $not$libresoc.v:176591$11155_Y
end
- attribute \src "libresoc.v:178778.7-178778.20"
- process $proc$libresoc.v:178778$11301
+ attribute \src "libresoc.v:176531.7-176531.20"
+ process $proc$libresoc.v:176531$11209
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:178787.14-178787.49"
- process $proc$libresoc.v:178787$11302
+ attribute \src "libresoc.v:176540.14-176540.49"
+ process $proc$libresoc.v:176540$11210
assign { } { }
assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \cia2__data_o $1\cia2__data_o[63:0]
end
- attribute \src "libresoc.v:178804.14-178804.49"
- process $proc$libresoc.v:178804$11303
+ attribute \src "libresoc.v:176557.14-176557.49"
+ process $proc$libresoc.v:176557$11211
assign { } { }
assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \msr2__data_o $1\msr2__data_o[63:0]
end
- attribute \src "libresoc.v:178816.14-178816.42"
- process $proc$libresoc.v:178816$11304
+ attribute \src "libresoc.v:176569.14-176569.42"
+ process $proc$libresoc.v:176569$11212
assign { } { }
assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \reg $1\reg[63:0]
end
- attribute \src "libresoc.v:178823.14-178823.48"
- process $proc$libresoc.v:178823$11305
+ attribute \src "libresoc.v:176576.14-176576.48"
+ process $proc$libresoc.v:176576$11213
assign { } { }
assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \sv2__data_o $1\sv2__data_o[63:0]
end
- attribute \src "libresoc.v:178839.3-178840.25"
- process $proc$libresoc.v:178839$11248
+ attribute \src "libresoc.v:176592.3-176593.25"
+ process $proc$libresoc.v:176592$11156
assign { } { }
assign $0\reg[63:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[63:0]
end
- attribute \src "libresoc.v:178841.3-178842.39"
- process $proc$libresoc.v:178841$11249
+ attribute \src "libresoc.v:176594.3-176595.39"
+ process $proc$libresoc.v:176594$11157
assign { } { }
assign $0\sv2__data_o[63:0] \sv2__data_o$next
sync posedge \coresync_clk
update \sv2__data_o $0\sv2__data_o[63:0]
end
- attribute \src "libresoc.v:178843.3-178844.41"
- process $proc$libresoc.v:178843$11250
+ attribute \src "libresoc.v:176596.3-176597.41"
+ process $proc$libresoc.v:176596$11158
assign { } { }
assign $0\msr2__data_o[63:0] \msr2__data_o$next
sync posedge \coresync_clk
update \msr2__data_o $0\msr2__data_o[63:0]
end
- attribute \src "libresoc.v:178845.3-178846.41"
- process $proc$libresoc.v:178845$11251
+ attribute \src "libresoc.v:176598.3-176599.41"
+ process $proc$libresoc.v:176598$11159
assign { } { }
assign $0\cia2__data_o[63:0] \cia2__data_o$next
sync posedge \coresync_clk
update \cia2__data_o $0\cia2__data_o[63:0]
end
- attribute \src "libresoc.v:178847.3-178892.6"
- process $proc$libresoc.v:178847$11252
+ attribute \src "libresoc.v:176600.3-176645.6"
+ process $proc$libresoc.v:176600$11160
assign { } { }
assign { } { }
assign { } { }
- assign $0\cia2__data_o$next[63:0]$11253 $7\cia2__data_o$next[63:0]$11260
- attribute \src "libresoc.v:178848.5-178848.29"
+ assign $0\cia2__data_o$next[63:0]$11161 $7\cia2__data_o$next[63:0]$11168
+ attribute \src "libresoc.v:176601.5-176601.29"
switch \initial
- attribute \src "libresoc.v:178848.9-178848.17"
+ attribute \src "libresoc.v:176601.9-176601.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cia2__data_o$next[63:0]$11254 $6\cia2__data_o$next[63:0]$11259
+ assign $1\cia2__data_o$next[63:0]$11162 $6\cia2__data_o$next[63:0]$11167
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\cia2__data_o$next[63:0]$11255 \nia2__data_i
+ assign $2\cia2__data_o$next[63:0]$11163 \nia2__data_i
case
- assign $2\cia2__data_o$next[63:0]$11255 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\cia2__data_o$next[63:0]$11163 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\cia2__data_o$next[63:0]$11256 \msr2__data_i
+ assign $3\cia2__data_o$next[63:0]$11164 \msr2__data_i
case
- assign $3\cia2__data_o$next[63:0]$11256 $2\cia2__data_o$next[63:0]$11255
+ assign $3\cia2__data_o$next[63:0]$11164 $2\cia2__data_o$next[63:0]$11163
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cia2__data_o$next[63:0]$11257 \sv2__data_i
+ assign $4\cia2__data_o$next[63:0]$11165 \sv2__data_i
case
- assign $4\cia2__data_o$next[63:0]$11257 $3\cia2__data_o$next[63:0]$11256
+ assign $4\cia2__data_o$next[63:0]$11165 $3\cia2__data_o$next[63:0]$11164
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\cia2__data_o$next[63:0]$11258 \d_wr12__data_i
+ assign $5\cia2__data_o$next[63:0]$11166 \d_wr12__data_i
case
- assign $5\cia2__data_o$next[63:0]$11258 $4\cia2__data_o$next[63:0]$11257
+ assign $5\cia2__data_o$next[63:0]$11166 $4\cia2__data_o$next[63:0]$11165
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\cia2__data_o$next[63:0]$11259 \reg
+ assign $6\cia2__data_o$next[63:0]$11167 \reg
case
- assign $6\cia2__data_o$next[63:0]$11259 $5\cia2__data_o$next[63:0]$11258
+ assign $6\cia2__data_o$next[63:0]$11167 $5\cia2__data_o$next[63:0]$11166
end
case
- assign $1\cia2__data_o$next[63:0]$11254 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\cia2__data_o$next[63:0]$11162 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\cia2__data_o$next[63:0]$11260 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\cia2__data_o$next[63:0]$11168 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\cia2__data_o$next[63:0]$11260 $1\cia2__data_o$next[63:0]$11254
+ assign $7\cia2__data_o$next[63:0]$11168 $1\cia2__data_o$next[63:0]$11162
end
sync always
- update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11253
+ update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11161
end
- attribute \src "libresoc.v:178893.3-178928.6"
- process $proc$libresoc.v:178893$11261
+ attribute \src "libresoc.v:176646.3-176681.6"
+ process $proc$libresoc.v:176646$11169
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:178894.5-178894.29"
+ attribute \src "libresoc.v:176647.5-176647.29"
switch \initial
- attribute \src "libresoc.v:178894.9-178894.17"
+ attribute \src "libresoc.v:176647.9-176647.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:178929.3-178974.6"
- process $proc$libresoc.v:178929$11262
+ attribute \src "libresoc.v:176682.3-176727.6"
+ process $proc$libresoc.v:176682$11170
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr2__data_o$next[63:0]$11263 $7\msr2__data_o$next[63:0]$11270
- attribute \src "libresoc.v:178930.5-178930.29"
+ assign $0\msr2__data_o$next[63:0]$11171 $7\msr2__data_o$next[63:0]$11178
+ attribute \src "libresoc.v:176683.5-176683.29"
switch \initial
- attribute \src "libresoc.v:178930.9-178930.17"
+ attribute \src "libresoc.v:176683.9-176683.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\msr2__data_o$next[63:0]$11264 $6\msr2__data_o$next[63:0]$11269
+ assign $1\msr2__data_o$next[63:0]$11172 $6\msr2__data_o$next[63:0]$11177
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr2__data_o$next[63:0]$11265 \nia2__data_i
+ assign $2\msr2__data_o$next[63:0]$11173 \nia2__data_i
case
- assign $2\msr2__data_o$next[63:0]$11265 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\msr2__data_o$next[63:0]$11173 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr2__data_o$next[63:0]$11266 \msr2__data_i
+ assign $3\msr2__data_o$next[63:0]$11174 \msr2__data_i
case
- assign $3\msr2__data_o$next[63:0]$11266 $2\msr2__data_o$next[63:0]$11265
+ assign $3\msr2__data_o$next[63:0]$11174 $2\msr2__data_o$next[63:0]$11173
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr2__data_o$next[63:0]$11267 \sv2__data_i
+ assign $4\msr2__data_o$next[63:0]$11175 \sv2__data_i
case
- assign $4\msr2__data_o$next[63:0]$11267 $3\msr2__data_o$next[63:0]$11266
+ assign $4\msr2__data_o$next[63:0]$11175 $3\msr2__data_o$next[63:0]$11174
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\msr2__data_o$next[63:0]$11268 \d_wr12__data_i
+ assign $5\msr2__data_o$next[63:0]$11176 \d_wr12__data_i
case
- assign $5\msr2__data_o$next[63:0]$11268 $4\msr2__data_o$next[63:0]$11267
+ assign $5\msr2__data_o$next[63:0]$11176 $4\msr2__data_o$next[63:0]$11175
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\msr2__data_o$next[63:0]$11269 \reg
+ assign $6\msr2__data_o$next[63:0]$11177 \reg
case
- assign $6\msr2__data_o$next[63:0]$11269 $5\msr2__data_o$next[63:0]$11268
+ assign $6\msr2__data_o$next[63:0]$11177 $5\msr2__data_o$next[63:0]$11176
end
case
- assign $1\msr2__data_o$next[63:0]$11264 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\msr2__data_o$next[63:0]$11172 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\msr2__data_o$next[63:0]$11270 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\msr2__data_o$next[63:0]$11178 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\msr2__data_o$next[63:0]$11270 $1\msr2__data_o$next[63:0]$11264
+ assign $7\msr2__data_o$next[63:0]$11178 $1\msr2__data_o$next[63:0]$11172
end
sync always
- update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11263
+ update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11171
end
- attribute \src "libresoc.v:178975.3-179010.6"
- process $proc$libresoc.v:178975$11271
+ attribute \src "libresoc.v:176728.3-176763.6"
+ process $proc$libresoc.v:176728$11179
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11272 $1\wr_detect$4[0:0]$11273
- attribute \src "libresoc.v:178976.5-178976.29"
+ assign $0\wr_detect$4[0:0]$11180 $1\wr_detect$4[0:0]$11181
+ attribute \src "libresoc.v:176729.5-176729.29"
switch \initial
- attribute \src "libresoc.v:178976.9-178976.17"
+ attribute \src "libresoc.v:176729.9-176729.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11273 $5\wr_detect$4[0:0]$11277
+ assign $1\wr_detect$4[0:0]$11181 $5\wr_detect$4[0:0]$11185
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11274 1'1
+ assign $2\wr_detect$4[0:0]$11182 1'1
case
- assign $2\wr_detect$4[0:0]$11274 1'0
+ assign $2\wr_detect$4[0:0]$11182 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11275 1'1
+ assign $3\wr_detect$4[0:0]$11183 1'1
case
- assign $3\wr_detect$4[0:0]$11275 $2\wr_detect$4[0:0]$11274
+ assign $3\wr_detect$4[0:0]$11183 $2\wr_detect$4[0:0]$11182
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11276 1'1
+ assign $4\wr_detect$4[0:0]$11184 1'1
case
- assign $4\wr_detect$4[0:0]$11276 $3\wr_detect$4[0:0]$11275
+ assign $4\wr_detect$4[0:0]$11184 $3\wr_detect$4[0:0]$11183
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$4[0:0]$11277 1'1
+ assign $5\wr_detect$4[0:0]$11185 1'1
case
- assign $5\wr_detect$4[0:0]$11277 $4\wr_detect$4[0:0]$11276
+ assign $5\wr_detect$4[0:0]$11185 $4\wr_detect$4[0:0]$11184
end
case
- assign $1\wr_detect$4[0:0]$11273 1'0
+ assign $1\wr_detect$4[0:0]$11181 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11272
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11180
end
- attribute \src "libresoc.v:179011.3-179056.6"
- process $proc$libresoc.v:179011$11278
+ attribute \src "libresoc.v:176764.3-176809.6"
+ process $proc$libresoc.v:176764$11186
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv2__data_o$next[63:0]$11279 $7\sv2__data_o$next[63:0]$11286
- attribute \src "libresoc.v:179012.5-179012.29"
+ assign $0\sv2__data_o$next[63:0]$11187 $7\sv2__data_o$next[63:0]$11194
+ attribute \src "libresoc.v:176765.5-176765.29"
switch \initial
- attribute \src "libresoc.v:179012.9-179012.17"
+ attribute \src "libresoc.v:176765.9-176765.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\sv2__data_o$next[63:0]$11280 $6\sv2__data_o$next[63:0]$11285
+ assign $1\sv2__data_o$next[63:0]$11188 $6\sv2__data_o$next[63:0]$11193
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sv2__data_o$next[63:0]$11281 \nia2__data_i
+ assign $2\sv2__data_o$next[63:0]$11189 \nia2__data_i
case
- assign $2\sv2__data_o$next[63:0]$11281 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\sv2__data_o$next[63:0]$11189 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv2__data_o$next[63:0]$11282 \msr2__data_i
+ assign $3\sv2__data_o$next[63:0]$11190 \msr2__data_i
case
- assign $3\sv2__data_o$next[63:0]$11282 $2\sv2__data_o$next[63:0]$11281
+ assign $3\sv2__data_o$next[63:0]$11190 $2\sv2__data_o$next[63:0]$11189
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\sv2__data_o$next[63:0]$11283 \sv2__data_i
+ assign $4\sv2__data_o$next[63:0]$11191 \sv2__data_i
case
- assign $4\sv2__data_o$next[63:0]$11283 $3\sv2__data_o$next[63:0]$11282
+ assign $4\sv2__data_o$next[63:0]$11191 $3\sv2__data_o$next[63:0]$11190
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv2__data_o$next[63:0]$11284 \d_wr12__data_i
+ assign $5\sv2__data_o$next[63:0]$11192 \d_wr12__data_i
case
- assign $5\sv2__data_o$next[63:0]$11284 $4\sv2__data_o$next[63:0]$11283
+ assign $5\sv2__data_o$next[63:0]$11192 $4\sv2__data_o$next[63:0]$11191
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv2__data_o$next[63:0]$11285 \reg
+ assign $6\sv2__data_o$next[63:0]$11193 \reg
case
- assign $6\sv2__data_o$next[63:0]$11285 $5\sv2__data_o$next[63:0]$11284
+ assign $6\sv2__data_o$next[63:0]$11193 $5\sv2__data_o$next[63:0]$11192
end
case
- assign $1\sv2__data_o$next[63:0]$11280 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\sv2__data_o$next[63:0]$11188 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv2__data_o$next[63:0]$11286 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\sv2__data_o$next[63:0]$11194 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $7\sv2__data_o$next[63:0]$11286 $1\sv2__data_o$next[63:0]$11280
+ assign $7\sv2__data_o$next[63:0]$11194 $1\sv2__data_o$next[63:0]$11188
end
sync always
- update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11279
+ update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11187
end
- attribute \src "libresoc.v:179057.3-179092.6"
- process $proc$libresoc.v:179057$11287
+ attribute \src "libresoc.v:176810.3-176845.6"
+ process $proc$libresoc.v:176810$11195
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11288 $1\wr_detect$7[0:0]$11289
- attribute \src "libresoc.v:179058.5-179058.29"
+ assign $0\wr_detect$7[0:0]$11196 $1\wr_detect$7[0:0]$11197
+ attribute \src "libresoc.v:176811.5-176811.29"
switch \initial
- attribute \src "libresoc.v:179058.9-179058.17"
+ attribute \src "libresoc.v:176811.9-176811.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11289 $5\wr_detect$7[0:0]$11293
+ assign $1\wr_detect$7[0:0]$11197 $5\wr_detect$7[0:0]$11201
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \nia2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11290 1'1
+ assign $2\wr_detect$7[0:0]$11198 1'1
case
- assign $2\wr_detect$7[0:0]$11290 1'0
+ assign $2\wr_detect$7[0:0]$11198 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11291 1'1
+ assign $3\wr_detect$7[0:0]$11199 1'1
case
- assign $3\wr_detect$7[0:0]$11291 $2\wr_detect$7[0:0]$11290
+ assign $3\wr_detect$7[0:0]$11199 $2\wr_detect$7[0:0]$11198
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11292 1'1
+ assign $4\wr_detect$7[0:0]$11200 1'1
case
- assign $4\wr_detect$7[0:0]$11292 $3\wr_detect$7[0:0]$11291
+ assign $4\wr_detect$7[0:0]$11200 $3\wr_detect$7[0:0]$11199
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\wr_detect$7[0:0]$11293 1'1
+ assign $5\wr_detect$7[0:0]$11201 1'1
case
- assign $5\wr_detect$7[0:0]$11293 $4\wr_detect$7[0:0]$11292
+ assign $5\wr_detect$7[0:0]$11201 $4\wr_detect$7[0:0]$11200
end
case
- assign $1\wr_detect$7[0:0]$11289 1'0
+ assign $1\wr_detect$7[0:0]$11197 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11288
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11196
end
- attribute \src "libresoc.v:179093.3-179125.6"
- process $proc$libresoc.v:179093$11294
+ attribute \src "libresoc.v:176846.3-176878.6"
+ process $proc$libresoc.v:176846$11202
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[63:0]$11295 $5\reg$next[63:0]$11300
- attribute \src "libresoc.v:179094.5-179094.29"
+ assign $0\reg$next[63:0]$11203 $5\reg$next[63:0]$11208
+ attribute \src "libresoc.v:176847.5-176847.29"
switch \initial
- attribute \src "libresoc.v:179094.9-179094.17"
+ attribute \src "libresoc.v:176847.9-176847.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[63:0]$11296 \nia2__data_i
+ assign $1\reg$next[63:0]$11204 \nia2__data_i
case
- assign $1\reg$next[63:0]$11296 \reg
+ assign $1\reg$next[63:0]$11204 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \msr2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[63:0]$11297 \msr2__data_i
+ assign $2\reg$next[63:0]$11205 \msr2__data_i
case
- assign $2\reg$next[63:0]$11297 $1\reg$next[63:0]$11296
+ assign $2\reg$next[63:0]$11205 $1\reg$next[63:0]$11204
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \sv2__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[63:0]$11298 \sv2__data_i
+ assign $3\reg$next[63:0]$11206 \sv2__data_i
case
- assign $3\reg$next[63:0]$11298 $2\reg$next[63:0]$11297
+ assign $3\reg$next[63:0]$11206 $2\reg$next[63:0]$11205
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \d_wr12__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[63:0]$11299 \d_wr12__data_i
+ assign $4\reg$next[63:0]$11207 \d_wr12__data_i
case
- assign $4\reg$next[63:0]$11299 $3\reg$next[63:0]$11298
+ assign $4\reg$next[63:0]$11207 $3\reg$next[63:0]$11206
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\reg$next[63:0]$11300 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $5\reg$next[63:0]$11208 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $5\reg$next[63:0]$11300 $4\reg$next[63:0]$11299
+ assign $5\reg$next[63:0]$11208 $4\reg$next[63:0]$11207
end
sync always
- update \reg$next $0\reg$next[63:0]$11295
+ update \reg$next $0\reg$next[63:0]$11203
end
- connect \$1 $not$libresoc.v:178836$11245_Y
- connect \$3 $not$libresoc.v:178837$11246_Y
- connect \$6 $not$libresoc.v:178838$11247_Y
+ connect \$1 $not$libresoc.v:176589$11153_Y
+ connect \$3 $not$libresoc.v:176590$11154_Y
+ connect \$6 $not$libresoc.v:176591$11155_Y
end
-attribute \src "libresoc.v:179130.1-179601.10"
+attribute \src "libresoc.v:176883.1-177354.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3"
attribute \generator "nMigen"
module \reg_3
- attribute \src "libresoc.v:179131.7-179131.20"
+ attribute \src "libresoc.v:176884.7-176884.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $0\r23__data_o$next[3:0]$11375
- attribute \src "libresoc.v:179214.3-179215.39"
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $0\r23__data_o$next[3:0]$11283
+ attribute \src "libresoc.v:176967.3-176968.39"
wire width 4 $0\r23__data_o[3:0]
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $0\r3__data_o$next[3:0]$11361
- attribute \src "libresoc.v:179216.3-179217.37"
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $0\r3__data_o$next[3:0]$11269
+ attribute \src "libresoc.v:176969.3-176970.37"
wire width 4 $0\r3__data_o[3:0]
- attribute \src "libresoc.v:179294.3-179320.6"
- wire width 4 $0\reg$next[3:0]$11327
- attribute \src "libresoc.v:179212.3-179213.25"
+ attribute \src "libresoc.v:177047.3-177073.6"
+ wire width 4 $0\reg$next[3:0]$11235
+ attribute \src "libresoc.v:176965.3-176966.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $0\src13__data_o$next[3:0]$11318
- attribute \src "libresoc.v:179222.3-179223.43"
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $0\src13__data_o$next[3:0]$11226
+ attribute \src "libresoc.v:176975.3-176976.43"
wire width 4 $0\src13__data_o[3:0]
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $0\src23__data_o$next[3:0]$11333
- attribute \src "libresoc.v:179220.3-179221.43"
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $0\src23__data_o$next[3:0]$11241
+ attribute \src "libresoc.v:176973.3-176974.43"
wire width 4 $0\src23__data_o[3:0]
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $0\src33__data_o$next[3:0]$11347
- attribute \src "libresoc.v:179218.3-179219.43"
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $0\src33__data_o$next[3:0]$11255
+ attribute \src "libresoc.v:176971.3-176972.43"
wire width 4 $0\src33__data_o[3:0]
- attribute \src "libresoc.v:179501.3-179530.6"
- wire $0\wr_detect$10[0:0]$11369
- attribute \src "libresoc.v:179571.3-179600.6"
- wire $0\wr_detect$13[0:0]$11383
- attribute \src "libresoc.v:179361.3-179390.6"
- wire $0\wr_detect$4[0:0]$11341
- attribute \src "libresoc.v:179431.3-179460.6"
- wire $0\wr_detect$7[0:0]$11355
- attribute \src "libresoc.v:179264.3-179293.6"
+ attribute \src "libresoc.v:177254.3-177283.6"
+ wire $0\wr_detect$10[0:0]$11277
+ attribute \src "libresoc.v:177324.3-177353.6"
+ wire $0\wr_detect$13[0:0]$11291
+ attribute \src "libresoc.v:177114.3-177143.6"
+ wire $0\wr_detect$4[0:0]$11249
+ attribute \src "libresoc.v:177184.3-177213.6"
+ wire $0\wr_detect$7[0:0]$11263
+ attribute \src "libresoc.v:177017.3-177046.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $1\r23__data_o$next[3:0]$11376
- attribute \src "libresoc.v:179156.13-179156.31"
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $1\r23__data_o$next[3:0]$11284
+ attribute \src "libresoc.v:176909.13-176909.31"
wire width 4 $1\r23__data_o[3:0]
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $1\r3__data_o$next[3:0]$11362
- attribute \src "libresoc.v:179163.13-179163.30"
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $1\r3__data_o$next[3:0]$11270
+ attribute \src "libresoc.v:176916.13-176916.30"
wire width 4 $1\r3__data_o[3:0]
- attribute \src "libresoc.v:179294.3-179320.6"
- wire width 4 $1\reg$next[3:0]$11328
- attribute \src "libresoc.v:179169.13-179169.25"
+ attribute \src "libresoc.v:177047.3-177073.6"
+ wire width 4 $1\reg$next[3:0]$11236
+ attribute \src "libresoc.v:176922.13-176922.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $1\src13__data_o$next[3:0]$11319
- attribute \src "libresoc.v:179174.13-179174.33"
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $1\src13__data_o$next[3:0]$11227
+ attribute \src "libresoc.v:176927.13-176927.33"
wire width 4 $1\src13__data_o[3:0]
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $1\src23__data_o$next[3:0]$11334
- attribute \src "libresoc.v:179181.13-179181.33"
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $1\src23__data_o$next[3:0]$11242
+ attribute \src "libresoc.v:176934.13-176934.33"
wire width 4 $1\src23__data_o[3:0]
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $1\src33__data_o$next[3:0]$11348
- attribute \src "libresoc.v:179188.13-179188.33"
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $1\src33__data_o$next[3:0]$11256
+ attribute \src "libresoc.v:176941.13-176941.33"
wire width 4 $1\src33__data_o[3:0]
- attribute \src "libresoc.v:179501.3-179530.6"
- wire $1\wr_detect$10[0:0]$11370
- attribute \src "libresoc.v:179571.3-179600.6"
- wire $1\wr_detect$13[0:0]$11384
- attribute \src "libresoc.v:179361.3-179390.6"
- wire $1\wr_detect$4[0:0]$11342
- attribute \src "libresoc.v:179431.3-179460.6"
- wire $1\wr_detect$7[0:0]$11356
- attribute \src "libresoc.v:179264.3-179293.6"
+ attribute \src "libresoc.v:177254.3-177283.6"
+ wire $1\wr_detect$10[0:0]$11278
+ attribute \src "libresoc.v:177324.3-177353.6"
+ wire $1\wr_detect$13[0:0]$11292
+ attribute \src "libresoc.v:177114.3-177143.6"
+ wire $1\wr_detect$4[0:0]$11250
+ attribute \src "libresoc.v:177184.3-177213.6"
+ wire $1\wr_detect$7[0:0]$11264
+ attribute \src "libresoc.v:177017.3-177046.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $2\r23__data_o$next[3:0]$11377
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $2\r3__data_o$next[3:0]$11363
- attribute \src "libresoc.v:179294.3-179320.6"
- wire width 4 $2\reg$next[3:0]$11329
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $2\src13__data_o$next[3:0]$11320
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $2\src23__data_o$next[3:0]$11335
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $2\src33__data_o$next[3:0]$11349
- attribute \src "libresoc.v:179501.3-179530.6"
- wire $2\wr_detect$10[0:0]$11371
- attribute \src "libresoc.v:179571.3-179600.6"
- wire $2\wr_detect$13[0:0]$11385
- attribute \src "libresoc.v:179361.3-179390.6"
- wire $2\wr_detect$4[0:0]$11343
- attribute \src "libresoc.v:179431.3-179460.6"
- wire $2\wr_detect$7[0:0]$11357
- attribute \src "libresoc.v:179264.3-179293.6"
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $2\r23__data_o$next[3:0]$11285
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $2\r3__data_o$next[3:0]$11271
+ attribute \src "libresoc.v:177047.3-177073.6"
+ wire width 4 $2\reg$next[3:0]$11237
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $2\src13__data_o$next[3:0]$11228
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $2\src23__data_o$next[3:0]$11243
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $2\src33__data_o$next[3:0]$11257
+ attribute \src "libresoc.v:177254.3-177283.6"
+ wire $2\wr_detect$10[0:0]$11279
+ attribute \src "libresoc.v:177324.3-177353.6"
+ wire $2\wr_detect$13[0:0]$11293
+ attribute \src "libresoc.v:177114.3-177143.6"
+ wire $2\wr_detect$4[0:0]$11251
+ attribute \src "libresoc.v:177184.3-177213.6"
+ wire $2\wr_detect$7[0:0]$11265
+ attribute \src "libresoc.v:177017.3-177046.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $3\r23__data_o$next[3:0]$11378
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $3\r3__data_o$next[3:0]$11364
- attribute \src "libresoc.v:179294.3-179320.6"
- wire width 4 $3\reg$next[3:0]$11330
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $3\src13__data_o$next[3:0]$11321
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $3\src23__data_o$next[3:0]$11336
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $3\src33__data_o$next[3:0]$11350
- attribute \src "libresoc.v:179501.3-179530.6"
- wire $3\wr_detect$10[0:0]$11372
- attribute \src "libresoc.v:179571.3-179600.6"
- wire $3\wr_detect$13[0:0]$11386
- attribute \src "libresoc.v:179361.3-179390.6"
- wire $3\wr_detect$4[0:0]$11344
- attribute \src "libresoc.v:179431.3-179460.6"
- wire $3\wr_detect$7[0:0]$11358
- attribute \src "libresoc.v:179264.3-179293.6"
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $3\r23__data_o$next[3:0]$11286
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $3\r3__data_o$next[3:0]$11272
+ attribute \src "libresoc.v:177047.3-177073.6"
+ wire width 4 $3\reg$next[3:0]$11238
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $3\src13__data_o$next[3:0]$11229
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $3\src23__data_o$next[3:0]$11244
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $3\src33__data_o$next[3:0]$11258
+ attribute \src "libresoc.v:177254.3-177283.6"
+ wire $3\wr_detect$10[0:0]$11280
+ attribute \src "libresoc.v:177324.3-177353.6"
+ wire $3\wr_detect$13[0:0]$11294
+ attribute \src "libresoc.v:177114.3-177143.6"
+ wire $3\wr_detect$4[0:0]$11252
+ attribute \src "libresoc.v:177184.3-177213.6"
+ wire $3\wr_detect$7[0:0]$11266
+ attribute \src "libresoc.v:177017.3-177046.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $4\r23__data_o$next[3:0]$11379
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $4\r3__data_o$next[3:0]$11365
- attribute \src "libresoc.v:179294.3-179320.6"
- wire width 4 $4\reg$next[3:0]$11331
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $4\src13__data_o$next[3:0]$11322
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $4\src23__data_o$next[3:0]$11337
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $4\src33__data_o$next[3:0]$11351
- attribute \src "libresoc.v:179501.3-179530.6"
- wire $4\wr_detect$10[0:0]$11373
- attribute \src "libresoc.v:179571.3-179600.6"
- wire $4\wr_detect$13[0:0]$11387
- attribute \src "libresoc.v:179361.3-179390.6"
- wire $4\wr_detect$4[0:0]$11345
- attribute \src "libresoc.v:179431.3-179460.6"
- wire $4\wr_detect$7[0:0]$11359
- attribute \src "libresoc.v:179264.3-179293.6"
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $4\r23__data_o$next[3:0]$11287
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $4\r3__data_o$next[3:0]$11273
+ attribute \src "libresoc.v:177047.3-177073.6"
+ wire width 4 $4\reg$next[3:0]$11239
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $4\src13__data_o$next[3:0]$11230
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $4\src23__data_o$next[3:0]$11245
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $4\src33__data_o$next[3:0]$11259
+ attribute \src "libresoc.v:177254.3-177283.6"
+ wire $4\wr_detect$10[0:0]$11281
+ attribute \src "libresoc.v:177324.3-177353.6"
+ wire $4\wr_detect$13[0:0]$11295
+ attribute \src "libresoc.v:177114.3-177143.6"
+ wire $4\wr_detect$4[0:0]$11253
+ attribute \src "libresoc.v:177184.3-177213.6"
+ wire $4\wr_detect$7[0:0]$11267
+ attribute \src "libresoc.v:177017.3-177046.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $5\r23__data_o$next[3:0]$11380
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $5\r3__data_o$next[3:0]$11366
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $5\src13__data_o$next[3:0]$11323
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $5\src23__data_o$next[3:0]$11338
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $5\src33__data_o$next[3:0]$11352
- attribute \src "libresoc.v:179531.3-179570.6"
- wire width 4 $6\r23__data_o$next[3:0]$11381
- attribute \src "libresoc.v:179461.3-179500.6"
- wire width 4 $6\r3__data_o$next[3:0]$11367
- attribute \src "libresoc.v:179224.3-179263.6"
- wire width 4 $6\src13__data_o$next[3:0]$11324
- attribute \src "libresoc.v:179321.3-179360.6"
- wire width 4 $6\src23__data_o$next[3:0]$11339
- attribute \src "libresoc.v:179391.3-179430.6"
- wire width 4 $6\src33__data_o$next[3:0]$11353
- attribute \src "libresoc.v:179207.17-179207.104"
- wire $not$libresoc.v:179207$11306_Y
- attribute \src "libresoc.v:179208.18-179208.105"
- wire $not$libresoc.v:179208$11307_Y
- attribute \src "libresoc.v:179209.17-179209.100"
- wire $not$libresoc.v:179209$11308_Y
- attribute \src "libresoc.v:179210.17-179210.103"
- wire $not$libresoc.v:179210$11309_Y
- attribute \src "libresoc.v:179211.17-179211.103"
- wire $not$libresoc.v:179211$11310_Y
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $5\r23__data_o$next[3:0]$11288
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $5\r3__data_o$next[3:0]$11274
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $5\src13__data_o$next[3:0]$11231
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $5\src23__data_o$next[3:0]$11246
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $5\src33__data_o$next[3:0]$11260
+ attribute \src "libresoc.v:177284.3-177323.6"
+ wire width 4 $6\r23__data_o$next[3:0]$11289
+ attribute \src "libresoc.v:177214.3-177253.6"
+ wire width 4 $6\r3__data_o$next[3:0]$11275
+ attribute \src "libresoc.v:176977.3-177016.6"
+ wire width 4 $6\src13__data_o$next[3:0]$11232
+ attribute \src "libresoc.v:177074.3-177113.6"
+ wire width 4 $6\src23__data_o$next[3:0]$11247
+ attribute \src "libresoc.v:177144.3-177183.6"
+ wire width 4 $6\src33__data_o$next[3:0]$11261
+ attribute \src "libresoc.v:176960.17-176960.104"
+ wire $not$libresoc.v:176960$11214_Y
+ attribute \src "libresoc.v:176961.18-176961.105"
+ wire $not$libresoc.v:176961$11215_Y
+ attribute \src "libresoc.v:176962.17-176962.100"
+ wire $not$libresoc.v:176962$11216_Y
+ attribute \src "libresoc.v:176963.17-176963.103"
+ wire $not$libresoc.v:176963$11217_Y
+ attribute \src "libresoc.v:176964.17-176964.103"
+ wire $not$libresoc.v:176964$11218_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest13__data_i
wire width 4 input 11 \dest23__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest23__wen
- attribute \src "libresoc.v:179131.7-179131.15"
+ attribute \src "libresoc.v:176884.7-176884.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r23__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179207$11306
+ cell $not $not$libresoc.v:176960$11214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:179207$11306_Y
+ connect \Y $not$libresoc.v:176960$11214_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179208$11307
+ cell $not $not$libresoc.v:176961$11215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:179208$11307_Y
+ connect \Y $not$libresoc.v:176961$11215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179209$11308
+ cell $not $not$libresoc.v:176962$11216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:179209$11308_Y
+ connect \Y $not$libresoc.v:176962$11216_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179210$11309
+ cell $not $not$libresoc.v:176963$11217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:179210$11309_Y
+ connect \Y $not$libresoc.v:176963$11217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179211$11310
+ cell $not $not$libresoc.v:176964$11218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:179211$11310_Y
+ connect \Y $not$libresoc.v:176964$11218_Y
end
- attribute \src "libresoc.v:179131.7-179131.20"
- process $proc$libresoc.v:179131$11388
+ attribute \src "libresoc.v:176884.7-176884.20"
+ process $proc$libresoc.v:176884$11296
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:179156.13-179156.31"
- process $proc$libresoc.v:179156$11389
+ attribute \src "libresoc.v:176909.13-176909.31"
+ process $proc$libresoc.v:176909$11297
assign { } { }
assign $1\r23__data_o[3:0] 4'0000
sync always
sync init
update \r23__data_o $1\r23__data_o[3:0]
end
- attribute \src "libresoc.v:179163.13-179163.30"
- process $proc$libresoc.v:179163$11390
+ attribute \src "libresoc.v:176916.13-176916.30"
+ process $proc$libresoc.v:176916$11298
assign { } { }
assign $1\r3__data_o[3:0] 4'0000
sync always
sync init
update \r3__data_o $1\r3__data_o[3:0]
end
- attribute \src "libresoc.v:179169.13-179169.25"
- process $proc$libresoc.v:179169$11391
+ attribute \src "libresoc.v:176922.13-176922.25"
+ process $proc$libresoc.v:176922$11299
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:179174.13-179174.33"
- process $proc$libresoc.v:179174$11392
+ attribute \src "libresoc.v:176927.13-176927.33"
+ process $proc$libresoc.v:176927$11300
assign { } { }
assign $1\src13__data_o[3:0] 4'0000
sync always
sync init
update \src13__data_o $1\src13__data_o[3:0]
end
- attribute \src "libresoc.v:179181.13-179181.33"
- process $proc$libresoc.v:179181$11393
+ attribute \src "libresoc.v:176934.13-176934.33"
+ process $proc$libresoc.v:176934$11301
assign { } { }
assign $1\src23__data_o[3:0] 4'0000
sync always
sync init
update \src23__data_o $1\src23__data_o[3:0]
end
- attribute \src "libresoc.v:179188.13-179188.33"
- process $proc$libresoc.v:179188$11394
+ attribute \src "libresoc.v:176941.13-176941.33"
+ process $proc$libresoc.v:176941$11302
assign { } { }
assign $1\src33__data_o[3:0] 4'0000
sync always
sync init
update \src33__data_o $1\src33__data_o[3:0]
end
- attribute \src "libresoc.v:179212.3-179213.25"
- process $proc$libresoc.v:179212$11311
+ attribute \src "libresoc.v:176965.3-176966.25"
+ process $proc$libresoc.v:176965$11219
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:179214.3-179215.39"
- process $proc$libresoc.v:179214$11312
+ attribute \src "libresoc.v:176967.3-176968.39"
+ process $proc$libresoc.v:176967$11220
assign { } { }
assign $0\r23__data_o[3:0] \r23__data_o$next
sync posedge \coresync_clk
update \r23__data_o $0\r23__data_o[3:0]
end
- attribute \src "libresoc.v:179216.3-179217.37"
- process $proc$libresoc.v:179216$11313
+ attribute \src "libresoc.v:176969.3-176970.37"
+ process $proc$libresoc.v:176969$11221
assign { } { }
assign $0\r3__data_o[3:0] \r3__data_o$next
sync posedge \coresync_clk
update \r3__data_o $0\r3__data_o[3:0]
end
- attribute \src "libresoc.v:179218.3-179219.43"
- process $proc$libresoc.v:179218$11314
+ attribute \src "libresoc.v:176971.3-176972.43"
+ process $proc$libresoc.v:176971$11222
assign { } { }
assign $0\src33__data_o[3:0] \src33__data_o$next
sync posedge \coresync_clk
update \src33__data_o $0\src33__data_o[3:0]
end
- attribute \src "libresoc.v:179220.3-179221.43"
- process $proc$libresoc.v:179220$11315
+ attribute \src "libresoc.v:176973.3-176974.43"
+ process $proc$libresoc.v:176973$11223
assign { } { }
assign $0\src23__data_o[3:0] \src23__data_o$next
sync posedge \coresync_clk
update \src23__data_o $0\src23__data_o[3:0]
end
- attribute \src "libresoc.v:179222.3-179223.43"
- process $proc$libresoc.v:179222$11316
+ attribute \src "libresoc.v:176975.3-176976.43"
+ process $proc$libresoc.v:176975$11224
assign { } { }
assign $0\src13__data_o[3:0] \src13__data_o$next
sync posedge \coresync_clk
update \src13__data_o $0\src13__data_o[3:0]
end
- attribute \src "libresoc.v:179224.3-179263.6"
- process $proc$libresoc.v:179224$11317
+ attribute \src "libresoc.v:176977.3-177016.6"
+ process $proc$libresoc.v:176977$11225
assign { } { }
assign { } { }
assign { } { }
- assign $0\src13__data_o$next[3:0]$11318 $6\src13__data_o$next[3:0]$11324
- attribute \src "libresoc.v:179225.5-179225.29"
+ assign $0\src13__data_o$next[3:0]$11226 $6\src13__data_o$next[3:0]$11232
+ attribute \src "libresoc.v:176978.5-176978.29"
switch \initial
- attribute \src "libresoc.v:179225.9-179225.17"
+ attribute \src "libresoc.v:176978.9-176978.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src13__data_o$next[3:0]$11319 $5\src13__data_o$next[3:0]$11323
+ assign $1\src13__data_o$next[3:0]$11227 $5\src13__data_o$next[3:0]$11231
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src13__data_o$next[3:0]$11320 \dest13__data_i
+ assign $2\src13__data_o$next[3:0]$11228 \dest13__data_i
case
- assign $2\src13__data_o$next[3:0]$11320 4'0000
+ assign $2\src13__data_o$next[3:0]$11228 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src13__data_o$next[3:0]$11321 \dest23__data_i
+ assign $3\src13__data_o$next[3:0]$11229 \dest23__data_i
case
- assign $3\src13__data_o$next[3:0]$11321 $2\src13__data_o$next[3:0]$11320
+ assign $3\src13__data_o$next[3:0]$11229 $2\src13__data_o$next[3:0]$11228
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src13__data_o$next[3:0]$11322 \w3__data_i
+ assign $4\src13__data_o$next[3:0]$11230 \w3__data_i
case
- assign $4\src13__data_o$next[3:0]$11322 $3\src13__data_o$next[3:0]$11321
+ assign $4\src13__data_o$next[3:0]$11230 $3\src13__data_o$next[3:0]$11229
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src13__data_o$next[3:0]$11323 \reg
+ assign $5\src13__data_o$next[3:0]$11231 \reg
case
- assign $5\src13__data_o$next[3:0]$11323 $4\src13__data_o$next[3:0]$11322
+ assign $5\src13__data_o$next[3:0]$11231 $4\src13__data_o$next[3:0]$11230
end
case
- assign $1\src13__data_o$next[3:0]$11319 4'0000
+ assign $1\src13__data_o$next[3:0]$11227 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src13__data_o$next[3:0]$11324 4'0000
+ assign $6\src13__data_o$next[3:0]$11232 4'0000
case
- assign $6\src13__data_o$next[3:0]$11324 $1\src13__data_o$next[3:0]$11319
+ assign $6\src13__data_o$next[3:0]$11232 $1\src13__data_o$next[3:0]$11227
end
sync always
- update \src13__data_o$next $0\src13__data_o$next[3:0]$11318
+ update \src13__data_o$next $0\src13__data_o$next[3:0]$11226
end
- attribute \src "libresoc.v:179264.3-179293.6"
- process $proc$libresoc.v:179264$11325
+ attribute \src "libresoc.v:177017.3-177046.6"
+ process $proc$libresoc.v:177017$11233
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:179265.5-179265.29"
+ attribute \src "libresoc.v:177018.5-177018.29"
switch \initial
- attribute \src "libresoc.v:179265.9-179265.17"
+ attribute \src "libresoc.v:177018.9-177018.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:179294.3-179320.6"
- process $proc$libresoc.v:179294$11326
+ attribute \src "libresoc.v:177047.3-177073.6"
+ process $proc$libresoc.v:177047$11234
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11327 $4\reg$next[3:0]$11331
- attribute \src "libresoc.v:179295.5-179295.29"
+ assign $0\reg$next[3:0]$11235 $4\reg$next[3:0]$11239
+ attribute \src "libresoc.v:177048.5-177048.29"
switch \initial
- attribute \src "libresoc.v:179295.9-179295.17"
+ attribute \src "libresoc.v:177048.9-177048.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11328 \dest13__data_i
+ assign $1\reg$next[3:0]$11236 \dest13__data_i
case
- assign $1\reg$next[3:0]$11328 \reg
+ assign $1\reg$next[3:0]$11236 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11329 \dest23__data_i
+ assign $2\reg$next[3:0]$11237 \dest23__data_i
case
- assign $2\reg$next[3:0]$11329 $1\reg$next[3:0]$11328
+ assign $2\reg$next[3:0]$11237 $1\reg$next[3:0]$11236
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11330 \w3__data_i
+ assign $3\reg$next[3:0]$11238 \w3__data_i
case
- assign $3\reg$next[3:0]$11330 $2\reg$next[3:0]$11329
+ assign $3\reg$next[3:0]$11238 $2\reg$next[3:0]$11237
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11331 4'0000
+ assign $4\reg$next[3:0]$11239 4'0000
case
- assign $4\reg$next[3:0]$11331 $3\reg$next[3:0]$11330
+ assign $4\reg$next[3:0]$11239 $3\reg$next[3:0]$11238
end
sync always
- update \reg$next $0\reg$next[3:0]$11327
+ update \reg$next $0\reg$next[3:0]$11235
end
- attribute \src "libresoc.v:179321.3-179360.6"
- process $proc$libresoc.v:179321$11332
+ attribute \src "libresoc.v:177074.3-177113.6"
+ process $proc$libresoc.v:177074$11240
assign { } { }
assign { } { }
assign { } { }
- assign $0\src23__data_o$next[3:0]$11333 $6\src23__data_o$next[3:0]$11339
- attribute \src "libresoc.v:179322.5-179322.29"
+ assign $0\src23__data_o$next[3:0]$11241 $6\src23__data_o$next[3:0]$11247
+ attribute \src "libresoc.v:177075.5-177075.29"
switch \initial
- attribute \src "libresoc.v:179322.9-179322.17"
+ attribute \src "libresoc.v:177075.9-177075.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src23__data_o$next[3:0]$11334 $5\src23__data_o$next[3:0]$11338
+ assign $1\src23__data_o$next[3:0]$11242 $5\src23__data_o$next[3:0]$11246
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src23__data_o$next[3:0]$11335 \dest13__data_i
+ assign $2\src23__data_o$next[3:0]$11243 \dest13__data_i
case
- assign $2\src23__data_o$next[3:0]$11335 4'0000
+ assign $2\src23__data_o$next[3:0]$11243 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src23__data_o$next[3:0]$11336 \dest23__data_i
+ assign $3\src23__data_o$next[3:0]$11244 \dest23__data_i
case
- assign $3\src23__data_o$next[3:0]$11336 $2\src23__data_o$next[3:0]$11335
+ assign $3\src23__data_o$next[3:0]$11244 $2\src23__data_o$next[3:0]$11243
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src23__data_o$next[3:0]$11337 \w3__data_i
+ assign $4\src23__data_o$next[3:0]$11245 \w3__data_i
case
- assign $4\src23__data_o$next[3:0]$11337 $3\src23__data_o$next[3:0]$11336
+ assign $4\src23__data_o$next[3:0]$11245 $3\src23__data_o$next[3:0]$11244
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src23__data_o$next[3:0]$11338 \reg
+ assign $5\src23__data_o$next[3:0]$11246 \reg
case
- assign $5\src23__data_o$next[3:0]$11338 $4\src23__data_o$next[3:0]$11337
+ assign $5\src23__data_o$next[3:0]$11246 $4\src23__data_o$next[3:0]$11245
end
case
- assign $1\src23__data_o$next[3:0]$11334 4'0000
+ assign $1\src23__data_o$next[3:0]$11242 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src23__data_o$next[3:0]$11339 4'0000
+ assign $6\src23__data_o$next[3:0]$11247 4'0000
case
- assign $6\src23__data_o$next[3:0]$11339 $1\src23__data_o$next[3:0]$11334
+ assign $6\src23__data_o$next[3:0]$11247 $1\src23__data_o$next[3:0]$11242
end
sync always
- update \src23__data_o$next $0\src23__data_o$next[3:0]$11333
+ update \src23__data_o$next $0\src23__data_o$next[3:0]$11241
end
- attribute \src "libresoc.v:179361.3-179390.6"
- process $proc$libresoc.v:179361$11340
+ attribute \src "libresoc.v:177114.3-177143.6"
+ process $proc$libresoc.v:177114$11248
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11341 $1\wr_detect$4[0:0]$11342
- attribute \src "libresoc.v:179362.5-179362.29"
+ assign $0\wr_detect$4[0:0]$11249 $1\wr_detect$4[0:0]$11250
+ attribute \src "libresoc.v:177115.5-177115.29"
switch \initial
- attribute \src "libresoc.v:179362.9-179362.17"
+ attribute \src "libresoc.v:177115.9-177115.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11342 $4\wr_detect$4[0:0]$11345
+ assign $1\wr_detect$4[0:0]$11250 $4\wr_detect$4[0:0]$11253
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11343 1'1
+ assign $2\wr_detect$4[0:0]$11251 1'1
case
- assign $2\wr_detect$4[0:0]$11343 1'0
+ assign $2\wr_detect$4[0:0]$11251 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11344 1'1
+ assign $3\wr_detect$4[0:0]$11252 1'1
case
- assign $3\wr_detect$4[0:0]$11344 $2\wr_detect$4[0:0]$11343
+ assign $3\wr_detect$4[0:0]$11252 $2\wr_detect$4[0:0]$11251
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11345 1'1
+ assign $4\wr_detect$4[0:0]$11253 1'1
case
- assign $4\wr_detect$4[0:0]$11345 $3\wr_detect$4[0:0]$11344
+ assign $4\wr_detect$4[0:0]$11253 $3\wr_detect$4[0:0]$11252
end
case
- assign $1\wr_detect$4[0:0]$11342 1'0
+ assign $1\wr_detect$4[0:0]$11250 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11341
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11249
end
- attribute \src "libresoc.v:179391.3-179430.6"
- process $proc$libresoc.v:179391$11346
+ attribute \src "libresoc.v:177144.3-177183.6"
+ process $proc$libresoc.v:177144$11254
assign { } { }
assign { } { }
assign { } { }
- assign $0\src33__data_o$next[3:0]$11347 $6\src33__data_o$next[3:0]$11353
- attribute \src "libresoc.v:179392.5-179392.29"
+ assign $0\src33__data_o$next[3:0]$11255 $6\src33__data_o$next[3:0]$11261
+ attribute \src "libresoc.v:177145.5-177145.29"
switch \initial
- attribute \src "libresoc.v:179392.9-179392.17"
+ attribute \src "libresoc.v:177145.9-177145.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src33__data_o$next[3:0]$11348 $5\src33__data_o$next[3:0]$11352
+ assign $1\src33__data_o$next[3:0]$11256 $5\src33__data_o$next[3:0]$11260
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src33__data_o$next[3:0]$11349 \dest13__data_i
+ assign $2\src33__data_o$next[3:0]$11257 \dest13__data_i
case
- assign $2\src33__data_o$next[3:0]$11349 4'0000
+ assign $2\src33__data_o$next[3:0]$11257 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src33__data_o$next[3:0]$11350 \dest23__data_i
+ assign $3\src33__data_o$next[3:0]$11258 \dest23__data_i
case
- assign $3\src33__data_o$next[3:0]$11350 $2\src33__data_o$next[3:0]$11349
+ assign $3\src33__data_o$next[3:0]$11258 $2\src33__data_o$next[3:0]$11257
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src33__data_o$next[3:0]$11351 \w3__data_i
+ assign $4\src33__data_o$next[3:0]$11259 \w3__data_i
case
- assign $4\src33__data_o$next[3:0]$11351 $3\src33__data_o$next[3:0]$11350
+ assign $4\src33__data_o$next[3:0]$11259 $3\src33__data_o$next[3:0]$11258
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src33__data_o$next[3:0]$11352 \reg
+ assign $5\src33__data_o$next[3:0]$11260 \reg
case
- assign $5\src33__data_o$next[3:0]$11352 $4\src33__data_o$next[3:0]$11351
+ assign $5\src33__data_o$next[3:0]$11260 $4\src33__data_o$next[3:0]$11259
end
case
- assign $1\src33__data_o$next[3:0]$11348 4'0000
+ assign $1\src33__data_o$next[3:0]$11256 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src33__data_o$next[3:0]$11353 4'0000
+ assign $6\src33__data_o$next[3:0]$11261 4'0000
case
- assign $6\src33__data_o$next[3:0]$11353 $1\src33__data_o$next[3:0]$11348
+ assign $6\src33__data_o$next[3:0]$11261 $1\src33__data_o$next[3:0]$11256
end
sync always
- update \src33__data_o$next $0\src33__data_o$next[3:0]$11347
+ update \src33__data_o$next $0\src33__data_o$next[3:0]$11255
end
- attribute \src "libresoc.v:179431.3-179460.6"
- process $proc$libresoc.v:179431$11354
+ attribute \src "libresoc.v:177184.3-177213.6"
+ process $proc$libresoc.v:177184$11262
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11355 $1\wr_detect$7[0:0]$11356
- attribute \src "libresoc.v:179432.5-179432.29"
+ assign $0\wr_detect$7[0:0]$11263 $1\wr_detect$7[0:0]$11264
+ attribute \src "libresoc.v:177185.5-177185.29"
switch \initial
- attribute \src "libresoc.v:179432.9-179432.17"
+ attribute \src "libresoc.v:177185.9-177185.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11356 $4\wr_detect$7[0:0]$11359
+ assign $1\wr_detect$7[0:0]$11264 $4\wr_detect$7[0:0]$11267
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11357 1'1
+ assign $2\wr_detect$7[0:0]$11265 1'1
case
- assign $2\wr_detect$7[0:0]$11357 1'0
+ assign $2\wr_detect$7[0:0]$11265 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11358 1'1
+ assign $3\wr_detect$7[0:0]$11266 1'1
case
- assign $3\wr_detect$7[0:0]$11358 $2\wr_detect$7[0:0]$11357
+ assign $3\wr_detect$7[0:0]$11266 $2\wr_detect$7[0:0]$11265
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11359 1'1
+ assign $4\wr_detect$7[0:0]$11267 1'1
case
- assign $4\wr_detect$7[0:0]$11359 $3\wr_detect$7[0:0]$11358
+ assign $4\wr_detect$7[0:0]$11267 $3\wr_detect$7[0:0]$11266
end
case
- assign $1\wr_detect$7[0:0]$11356 1'0
+ assign $1\wr_detect$7[0:0]$11264 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11355
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11263
end
- attribute \src "libresoc.v:179461.3-179500.6"
- process $proc$libresoc.v:179461$11360
+ attribute \src "libresoc.v:177214.3-177253.6"
+ process $proc$libresoc.v:177214$11268
assign { } { }
assign { } { }
assign { } { }
- assign $0\r3__data_o$next[3:0]$11361 $6\r3__data_o$next[3:0]$11367
- attribute \src "libresoc.v:179462.5-179462.29"
+ assign $0\r3__data_o$next[3:0]$11269 $6\r3__data_o$next[3:0]$11275
+ attribute \src "libresoc.v:177215.5-177215.29"
switch \initial
- attribute \src "libresoc.v:179462.9-179462.17"
+ attribute \src "libresoc.v:177215.9-177215.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r3__data_o$next[3:0]$11362 $5\r3__data_o$next[3:0]$11366
+ assign $1\r3__data_o$next[3:0]$11270 $5\r3__data_o$next[3:0]$11274
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r3__data_o$next[3:0]$11363 \dest13__data_i
+ assign $2\r3__data_o$next[3:0]$11271 \dest13__data_i
case
- assign $2\r3__data_o$next[3:0]$11363 4'0000
+ assign $2\r3__data_o$next[3:0]$11271 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r3__data_o$next[3:0]$11364 \dest23__data_i
+ assign $3\r3__data_o$next[3:0]$11272 \dest23__data_i
case
- assign $3\r3__data_o$next[3:0]$11364 $2\r3__data_o$next[3:0]$11363
+ assign $3\r3__data_o$next[3:0]$11272 $2\r3__data_o$next[3:0]$11271
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r3__data_o$next[3:0]$11365 \w3__data_i
+ assign $4\r3__data_o$next[3:0]$11273 \w3__data_i
case
- assign $4\r3__data_o$next[3:0]$11365 $3\r3__data_o$next[3:0]$11364
+ assign $4\r3__data_o$next[3:0]$11273 $3\r3__data_o$next[3:0]$11272
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r3__data_o$next[3:0]$11366 \reg
+ assign $5\r3__data_o$next[3:0]$11274 \reg
case
- assign $5\r3__data_o$next[3:0]$11366 $4\r3__data_o$next[3:0]$11365
+ assign $5\r3__data_o$next[3:0]$11274 $4\r3__data_o$next[3:0]$11273
end
case
- assign $1\r3__data_o$next[3:0]$11362 4'0000
+ assign $1\r3__data_o$next[3:0]$11270 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r3__data_o$next[3:0]$11367 4'0000
+ assign $6\r3__data_o$next[3:0]$11275 4'0000
case
- assign $6\r3__data_o$next[3:0]$11367 $1\r3__data_o$next[3:0]$11362
+ assign $6\r3__data_o$next[3:0]$11275 $1\r3__data_o$next[3:0]$11270
end
sync always
- update \r3__data_o$next $0\r3__data_o$next[3:0]$11361
+ update \r3__data_o$next $0\r3__data_o$next[3:0]$11269
end
- attribute \src "libresoc.v:179501.3-179530.6"
- process $proc$libresoc.v:179501$11368
+ attribute \src "libresoc.v:177254.3-177283.6"
+ process $proc$libresoc.v:177254$11276
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11369 $1\wr_detect$10[0:0]$11370
- attribute \src "libresoc.v:179502.5-179502.29"
+ assign $0\wr_detect$10[0:0]$11277 $1\wr_detect$10[0:0]$11278
+ attribute \src "libresoc.v:177255.5-177255.29"
switch \initial
- attribute \src "libresoc.v:179502.9-179502.17"
+ attribute \src "libresoc.v:177255.9-177255.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11370 $4\wr_detect$10[0:0]$11373
+ assign $1\wr_detect$10[0:0]$11278 $4\wr_detect$10[0:0]$11281
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11371 1'1
+ assign $2\wr_detect$10[0:0]$11279 1'1
case
- assign $2\wr_detect$10[0:0]$11371 1'0
+ assign $2\wr_detect$10[0:0]$11279 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11372 1'1
+ assign $3\wr_detect$10[0:0]$11280 1'1
case
- assign $3\wr_detect$10[0:0]$11372 $2\wr_detect$10[0:0]$11371
+ assign $3\wr_detect$10[0:0]$11280 $2\wr_detect$10[0:0]$11279
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11373 1'1
+ assign $4\wr_detect$10[0:0]$11281 1'1
case
- assign $4\wr_detect$10[0:0]$11373 $3\wr_detect$10[0:0]$11372
+ assign $4\wr_detect$10[0:0]$11281 $3\wr_detect$10[0:0]$11280
end
case
- assign $1\wr_detect$10[0:0]$11370 1'0
+ assign $1\wr_detect$10[0:0]$11278 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11369
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11277
end
- attribute \src "libresoc.v:179531.3-179570.6"
- process $proc$libresoc.v:179531$11374
+ attribute \src "libresoc.v:177284.3-177323.6"
+ process $proc$libresoc.v:177284$11282
assign { } { }
assign { } { }
assign { } { }
- assign $0\r23__data_o$next[3:0]$11375 $6\r23__data_o$next[3:0]$11381
- attribute \src "libresoc.v:179532.5-179532.29"
+ assign $0\r23__data_o$next[3:0]$11283 $6\r23__data_o$next[3:0]$11289
+ attribute \src "libresoc.v:177285.5-177285.29"
switch \initial
- attribute \src "libresoc.v:179532.9-179532.17"
+ attribute \src "libresoc.v:177285.9-177285.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r23__data_o$next[3:0]$11376 $5\r23__data_o$next[3:0]$11380
+ assign $1\r23__data_o$next[3:0]$11284 $5\r23__data_o$next[3:0]$11288
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r23__data_o$next[3:0]$11377 \dest13__data_i
+ assign $2\r23__data_o$next[3:0]$11285 \dest13__data_i
case
- assign $2\r23__data_o$next[3:0]$11377 4'0000
+ assign $2\r23__data_o$next[3:0]$11285 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r23__data_o$next[3:0]$11378 \dest23__data_i
+ assign $3\r23__data_o$next[3:0]$11286 \dest23__data_i
case
- assign $3\r23__data_o$next[3:0]$11378 $2\r23__data_o$next[3:0]$11377
+ assign $3\r23__data_o$next[3:0]$11286 $2\r23__data_o$next[3:0]$11285
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r23__data_o$next[3:0]$11379 \w3__data_i
+ assign $4\r23__data_o$next[3:0]$11287 \w3__data_i
case
- assign $4\r23__data_o$next[3:0]$11379 $3\r23__data_o$next[3:0]$11378
+ assign $4\r23__data_o$next[3:0]$11287 $3\r23__data_o$next[3:0]$11286
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r23__data_o$next[3:0]$11380 \reg
+ assign $5\r23__data_o$next[3:0]$11288 \reg
case
- assign $5\r23__data_o$next[3:0]$11380 $4\r23__data_o$next[3:0]$11379
+ assign $5\r23__data_o$next[3:0]$11288 $4\r23__data_o$next[3:0]$11287
end
case
- assign $1\r23__data_o$next[3:0]$11376 4'0000
+ assign $1\r23__data_o$next[3:0]$11284 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r23__data_o$next[3:0]$11381 4'0000
+ assign $6\r23__data_o$next[3:0]$11289 4'0000
case
- assign $6\r23__data_o$next[3:0]$11381 $1\r23__data_o$next[3:0]$11376
+ assign $6\r23__data_o$next[3:0]$11289 $1\r23__data_o$next[3:0]$11284
end
sync always
- update \r23__data_o$next $0\r23__data_o$next[3:0]$11375
+ update \r23__data_o$next $0\r23__data_o$next[3:0]$11283
end
- attribute \src "libresoc.v:179571.3-179600.6"
- process $proc$libresoc.v:179571$11382
+ attribute \src "libresoc.v:177324.3-177353.6"
+ process $proc$libresoc.v:177324$11290
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11383 $1\wr_detect$13[0:0]$11384
- attribute \src "libresoc.v:179572.5-179572.29"
+ assign $0\wr_detect$13[0:0]$11291 $1\wr_detect$13[0:0]$11292
+ attribute \src "libresoc.v:177325.5-177325.29"
switch \initial
- attribute \src "libresoc.v:179572.9-179572.17"
+ attribute \src "libresoc.v:177325.9-177325.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11384 $4\wr_detect$13[0:0]$11387
+ assign $1\wr_detect$13[0:0]$11292 $4\wr_detect$13[0:0]$11295
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest13__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11385 1'1
+ assign $2\wr_detect$13[0:0]$11293 1'1
case
- assign $2\wr_detect$13[0:0]$11385 1'0
+ assign $2\wr_detect$13[0:0]$11293 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest23__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11386 1'1
+ assign $3\wr_detect$13[0:0]$11294 1'1
case
- assign $3\wr_detect$13[0:0]$11386 $2\wr_detect$13[0:0]$11385
+ assign $3\wr_detect$13[0:0]$11294 $2\wr_detect$13[0:0]$11293
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w3__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11387 1'1
+ assign $4\wr_detect$13[0:0]$11295 1'1
case
- assign $4\wr_detect$13[0:0]$11387 $3\wr_detect$13[0:0]$11386
+ assign $4\wr_detect$13[0:0]$11295 $3\wr_detect$13[0:0]$11294
end
case
- assign $1\wr_detect$13[0:0]$11384 1'0
+ assign $1\wr_detect$13[0:0]$11292 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11383
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11291
end
- connect \$9 $not$libresoc.v:179207$11306_Y
- connect \$12 $not$libresoc.v:179208$11307_Y
- connect \$1 $not$libresoc.v:179209$11308_Y
- connect \$3 $not$libresoc.v:179210$11309_Y
- connect \$6 $not$libresoc.v:179211$11310_Y
+ connect \$9 $not$libresoc.v:176960$11214_Y
+ connect \$12 $not$libresoc.v:176961$11215_Y
+ connect \$1 $not$libresoc.v:176962$11216_Y
+ connect \$3 $not$libresoc.v:176963$11217_Y
+ connect \$6 $not$libresoc.v:176964$11218_Y
end
-attribute \src "libresoc.v:179605.1-180076.10"
+attribute \src "libresoc.v:177358.1-177829.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4"
attribute \generator "nMigen"
module \reg_4
- attribute \src "libresoc.v:179606.7-179606.20"
+ attribute \src "libresoc.v:177359.7-177359.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $0\r24__data_o$next[3:0]$11464
- attribute \src "libresoc.v:179689.3-179690.39"
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $0\r24__data_o$next[3:0]$11372
+ attribute \src "libresoc.v:177442.3-177443.39"
wire width 4 $0\r24__data_o[3:0]
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $0\r4__data_o$next[3:0]$11450
- attribute \src "libresoc.v:179691.3-179692.37"
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $0\r4__data_o$next[3:0]$11358
+ attribute \src "libresoc.v:177444.3-177445.37"
wire width 4 $0\r4__data_o[3:0]
- attribute \src "libresoc.v:179769.3-179795.6"
- wire width 4 $0\reg$next[3:0]$11416
- attribute \src "libresoc.v:179687.3-179688.25"
+ attribute \src "libresoc.v:177522.3-177548.6"
+ wire width 4 $0\reg$next[3:0]$11324
+ attribute \src "libresoc.v:177440.3-177441.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $0\src14__data_o$next[3:0]$11407
- attribute \src "libresoc.v:179697.3-179698.43"
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $0\src14__data_o$next[3:0]$11315
+ attribute \src "libresoc.v:177450.3-177451.43"
wire width 4 $0\src14__data_o[3:0]
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $0\src24__data_o$next[3:0]$11422
- attribute \src "libresoc.v:179695.3-179696.43"
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $0\src24__data_o$next[3:0]$11330
+ attribute \src "libresoc.v:177448.3-177449.43"
wire width 4 $0\src24__data_o[3:0]
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $0\src34__data_o$next[3:0]$11436
- attribute \src "libresoc.v:179693.3-179694.43"
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $0\src34__data_o$next[3:0]$11344
+ attribute \src "libresoc.v:177446.3-177447.43"
wire width 4 $0\src34__data_o[3:0]
- attribute \src "libresoc.v:179976.3-180005.6"
- wire $0\wr_detect$10[0:0]$11458
- attribute \src "libresoc.v:180046.3-180075.6"
- wire $0\wr_detect$13[0:0]$11472
- attribute \src "libresoc.v:179836.3-179865.6"
- wire $0\wr_detect$4[0:0]$11430
- attribute \src "libresoc.v:179906.3-179935.6"
- wire $0\wr_detect$7[0:0]$11444
- attribute \src "libresoc.v:179739.3-179768.6"
+ attribute \src "libresoc.v:177729.3-177758.6"
+ wire $0\wr_detect$10[0:0]$11366
+ attribute \src "libresoc.v:177799.3-177828.6"
+ wire $0\wr_detect$13[0:0]$11380
+ attribute \src "libresoc.v:177589.3-177618.6"
+ wire $0\wr_detect$4[0:0]$11338
+ attribute \src "libresoc.v:177659.3-177688.6"
+ wire $0\wr_detect$7[0:0]$11352
+ attribute \src "libresoc.v:177492.3-177521.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $1\r24__data_o$next[3:0]$11465
- attribute \src "libresoc.v:179631.13-179631.31"
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $1\r24__data_o$next[3:0]$11373
+ attribute \src "libresoc.v:177384.13-177384.31"
wire width 4 $1\r24__data_o[3:0]
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $1\r4__data_o$next[3:0]$11451
- attribute \src "libresoc.v:179638.13-179638.30"
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $1\r4__data_o$next[3:0]$11359
+ attribute \src "libresoc.v:177391.13-177391.30"
wire width 4 $1\r4__data_o[3:0]
- attribute \src "libresoc.v:179769.3-179795.6"
- wire width 4 $1\reg$next[3:0]$11417
- attribute \src "libresoc.v:179644.13-179644.25"
+ attribute \src "libresoc.v:177522.3-177548.6"
+ wire width 4 $1\reg$next[3:0]$11325
+ attribute \src "libresoc.v:177397.13-177397.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $1\src14__data_o$next[3:0]$11408
- attribute \src "libresoc.v:179649.13-179649.33"
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $1\src14__data_o$next[3:0]$11316
+ attribute \src "libresoc.v:177402.13-177402.33"
wire width 4 $1\src14__data_o[3:0]
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $1\src24__data_o$next[3:0]$11423
- attribute \src "libresoc.v:179656.13-179656.33"
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $1\src24__data_o$next[3:0]$11331
+ attribute \src "libresoc.v:177409.13-177409.33"
wire width 4 $1\src24__data_o[3:0]
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $1\src34__data_o$next[3:0]$11437
- attribute \src "libresoc.v:179663.13-179663.33"
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $1\src34__data_o$next[3:0]$11345
+ attribute \src "libresoc.v:177416.13-177416.33"
wire width 4 $1\src34__data_o[3:0]
- attribute \src "libresoc.v:179976.3-180005.6"
- wire $1\wr_detect$10[0:0]$11459
- attribute \src "libresoc.v:180046.3-180075.6"
- wire $1\wr_detect$13[0:0]$11473
- attribute \src "libresoc.v:179836.3-179865.6"
- wire $1\wr_detect$4[0:0]$11431
- attribute \src "libresoc.v:179906.3-179935.6"
- wire $1\wr_detect$7[0:0]$11445
- attribute \src "libresoc.v:179739.3-179768.6"
+ attribute \src "libresoc.v:177729.3-177758.6"
+ wire $1\wr_detect$10[0:0]$11367
+ attribute \src "libresoc.v:177799.3-177828.6"
+ wire $1\wr_detect$13[0:0]$11381
+ attribute \src "libresoc.v:177589.3-177618.6"
+ wire $1\wr_detect$4[0:0]$11339
+ attribute \src "libresoc.v:177659.3-177688.6"
+ wire $1\wr_detect$7[0:0]$11353
+ attribute \src "libresoc.v:177492.3-177521.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $2\r24__data_o$next[3:0]$11466
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $2\r4__data_o$next[3:0]$11452
- attribute \src "libresoc.v:179769.3-179795.6"
- wire width 4 $2\reg$next[3:0]$11418
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $2\src14__data_o$next[3:0]$11409
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $2\src24__data_o$next[3:0]$11424
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $2\src34__data_o$next[3:0]$11438
- attribute \src "libresoc.v:179976.3-180005.6"
- wire $2\wr_detect$10[0:0]$11460
- attribute \src "libresoc.v:180046.3-180075.6"
- wire $2\wr_detect$13[0:0]$11474
- attribute \src "libresoc.v:179836.3-179865.6"
- wire $2\wr_detect$4[0:0]$11432
- attribute \src "libresoc.v:179906.3-179935.6"
- wire $2\wr_detect$7[0:0]$11446
- attribute \src "libresoc.v:179739.3-179768.6"
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $2\r24__data_o$next[3:0]$11374
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $2\r4__data_o$next[3:0]$11360
+ attribute \src "libresoc.v:177522.3-177548.6"
+ wire width 4 $2\reg$next[3:0]$11326
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $2\src14__data_o$next[3:0]$11317
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $2\src24__data_o$next[3:0]$11332
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $2\src34__data_o$next[3:0]$11346
+ attribute \src "libresoc.v:177729.3-177758.6"
+ wire $2\wr_detect$10[0:0]$11368
+ attribute \src "libresoc.v:177799.3-177828.6"
+ wire $2\wr_detect$13[0:0]$11382
+ attribute \src "libresoc.v:177589.3-177618.6"
+ wire $2\wr_detect$4[0:0]$11340
+ attribute \src "libresoc.v:177659.3-177688.6"
+ wire $2\wr_detect$7[0:0]$11354
+ attribute \src "libresoc.v:177492.3-177521.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $3\r24__data_o$next[3:0]$11467
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $3\r4__data_o$next[3:0]$11453
- attribute \src "libresoc.v:179769.3-179795.6"
- wire width 4 $3\reg$next[3:0]$11419
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $3\src14__data_o$next[3:0]$11410
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $3\src24__data_o$next[3:0]$11425
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $3\src34__data_o$next[3:0]$11439
- attribute \src "libresoc.v:179976.3-180005.6"
- wire $3\wr_detect$10[0:0]$11461
- attribute \src "libresoc.v:180046.3-180075.6"
- wire $3\wr_detect$13[0:0]$11475
- attribute \src "libresoc.v:179836.3-179865.6"
- wire $3\wr_detect$4[0:0]$11433
- attribute \src "libresoc.v:179906.3-179935.6"
- wire $3\wr_detect$7[0:0]$11447
- attribute \src "libresoc.v:179739.3-179768.6"
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $3\r24__data_o$next[3:0]$11375
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $3\r4__data_o$next[3:0]$11361
+ attribute \src "libresoc.v:177522.3-177548.6"
+ wire width 4 $3\reg$next[3:0]$11327
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $3\src14__data_o$next[3:0]$11318
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $3\src24__data_o$next[3:0]$11333
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $3\src34__data_o$next[3:0]$11347
+ attribute \src "libresoc.v:177729.3-177758.6"
+ wire $3\wr_detect$10[0:0]$11369
+ attribute \src "libresoc.v:177799.3-177828.6"
+ wire $3\wr_detect$13[0:0]$11383
+ attribute \src "libresoc.v:177589.3-177618.6"
+ wire $3\wr_detect$4[0:0]$11341
+ attribute \src "libresoc.v:177659.3-177688.6"
+ wire $3\wr_detect$7[0:0]$11355
+ attribute \src "libresoc.v:177492.3-177521.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $4\r24__data_o$next[3:0]$11468
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $4\r4__data_o$next[3:0]$11454
- attribute \src "libresoc.v:179769.3-179795.6"
- wire width 4 $4\reg$next[3:0]$11420
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $4\src14__data_o$next[3:0]$11411
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $4\src24__data_o$next[3:0]$11426
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $4\src34__data_o$next[3:0]$11440
- attribute \src "libresoc.v:179976.3-180005.6"
- wire $4\wr_detect$10[0:0]$11462
- attribute \src "libresoc.v:180046.3-180075.6"
- wire $4\wr_detect$13[0:0]$11476
- attribute \src "libresoc.v:179836.3-179865.6"
- wire $4\wr_detect$4[0:0]$11434
- attribute \src "libresoc.v:179906.3-179935.6"
- wire $4\wr_detect$7[0:0]$11448
- attribute \src "libresoc.v:179739.3-179768.6"
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $4\r24__data_o$next[3:0]$11376
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $4\r4__data_o$next[3:0]$11362
+ attribute \src "libresoc.v:177522.3-177548.6"
+ wire width 4 $4\reg$next[3:0]$11328
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $4\src14__data_o$next[3:0]$11319
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $4\src24__data_o$next[3:0]$11334
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $4\src34__data_o$next[3:0]$11348
+ attribute \src "libresoc.v:177729.3-177758.6"
+ wire $4\wr_detect$10[0:0]$11370
+ attribute \src "libresoc.v:177799.3-177828.6"
+ wire $4\wr_detect$13[0:0]$11384
+ attribute \src "libresoc.v:177589.3-177618.6"
+ wire $4\wr_detect$4[0:0]$11342
+ attribute \src "libresoc.v:177659.3-177688.6"
+ wire $4\wr_detect$7[0:0]$11356
+ attribute \src "libresoc.v:177492.3-177521.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $5\r24__data_o$next[3:0]$11469
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $5\r4__data_o$next[3:0]$11455
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $5\src14__data_o$next[3:0]$11412
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $5\src24__data_o$next[3:0]$11427
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $5\src34__data_o$next[3:0]$11441
- attribute \src "libresoc.v:180006.3-180045.6"
- wire width 4 $6\r24__data_o$next[3:0]$11470
- attribute \src "libresoc.v:179936.3-179975.6"
- wire width 4 $6\r4__data_o$next[3:0]$11456
- attribute \src "libresoc.v:179699.3-179738.6"
- wire width 4 $6\src14__data_o$next[3:0]$11413
- attribute \src "libresoc.v:179796.3-179835.6"
- wire width 4 $6\src24__data_o$next[3:0]$11428
- attribute \src "libresoc.v:179866.3-179905.6"
- wire width 4 $6\src34__data_o$next[3:0]$11442
- attribute \src "libresoc.v:179682.17-179682.104"
- wire $not$libresoc.v:179682$11395_Y
- attribute \src "libresoc.v:179683.18-179683.105"
- wire $not$libresoc.v:179683$11396_Y
- attribute \src "libresoc.v:179684.17-179684.100"
- wire $not$libresoc.v:179684$11397_Y
- attribute \src "libresoc.v:179685.17-179685.103"
- wire $not$libresoc.v:179685$11398_Y
- attribute \src "libresoc.v:179686.17-179686.103"
- wire $not$libresoc.v:179686$11399_Y
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $5\r24__data_o$next[3:0]$11377
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $5\r4__data_o$next[3:0]$11363
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $5\src14__data_o$next[3:0]$11320
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $5\src24__data_o$next[3:0]$11335
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $5\src34__data_o$next[3:0]$11349
+ attribute \src "libresoc.v:177759.3-177798.6"
+ wire width 4 $6\r24__data_o$next[3:0]$11378
+ attribute \src "libresoc.v:177689.3-177728.6"
+ wire width 4 $6\r4__data_o$next[3:0]$11364
+ attribute \src "libresoc.v:177452.3-177491.6"
+ wire width 4 $6\src14__data_o$next[3:0]$11321
+ attribute \src "libresoc.v:177549.3-177588.6"
+ wire width 4 $6\src24__data_o$next[3:0]$11336
+ attribute \src "libresoc.v:177619.3-177658.6"
+ wire width 4 $6\src34__data_o$next[3:0]$11350
+ attribute \src "libresoc.v:177435.17-177435.104"
+ wire $not$libresoc.v:177435$11303_Y
+ attribute \src "libresoc.v:177436.18-177436.105"
+ wire $not$libresoc.v:177436$11304_Y
+ attribute \src "libresoc.v:177437.17-177437.100"
+ wire $not$libresoc.v:177437$11305_Y
+ attribute \src "libresoc.v:177438.17-177438.103"
+ wire $not$libresoc.v:177438$11306_Y
+ attribute \src "libresoc.v:177439.17-177439.103"
+ wire $not$libresoc.v:177439$11307_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest14__data_i
wire width 4 input 11 \dest24__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest24__wen
- attribute \src "libresoc.v:179606.7-179606.15"
+ attribute \src "libresoc.v:177359.7-177359.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r24__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179682$11395
+ cell $not $not$libresoc.v:177435$11303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:179682$11395_Y
+ connect \Y $not$libresoc.v:177435$11303_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179683$11396
+ cell $not $not$libresoc.v:177436$11304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:179683$11396_Y
+ connect \Y $not$libresoc.v:177436$11304_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179684$11397
+ cell $not $not$libresoc.v:177437$11305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:179684$11397_Y
+ connect \Y $not$libresoc.v:177437$11305_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179685$11398
+ cell $not $not$libresoc.v:177438$11306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:179685$11398_Y
+ connect \Y $not$libresoc.v:177438$11306_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:179686$11399
+ cell $not $not$libresoc.v:177439$11307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:179686$11399_Y
+ connect \Y $not$libresoc.v:177439$11307_Y
end
- attribute \src "libresoc.v:179606.7-179606.20"
- process $proc$libresoc.v:179606$11477
+ attribute \src "libresoc.v:177359.7-177359.20"
+ process $proc$libresoc.v:177359$11385
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:179631.13-179631.31"
- process $proc$libresoc.v:179631$11478
+ attribute \src "libresoc.v:177384.13-177384.31"
+ process $proc$libresoc.v:177384$11386
assign { } { }
assign $1\r24__data_o[3:0] 4'0000
sync always
sync init
update \r24__data_o $1\r24__data_o[3:0]
end
- attribute \src "libresoc.v:179638.13-179638.30"
- process $proc$libresoc.v:179638$11479
+ attribute \src "libresoc.v:177391.13-177391.30"
+ process $proc$libresoc.v:177391$11387
assign { } { }
assign $1\r4__data_o[3:0] 4'0000
sync always
sync init
update \r4__data_o $1\r4__data_o[3:0]
end
- attribute \src "libresoc.v:179644.13-179644.25"
- process $proc$libresoc.v:179644$11480
+ attribute \src "libresoc.v:177397.13-177397.25"
+ process $proc$libresoc.v:177397$11388
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:179649.13-179649.33"
- process $proc$libresoc.v:179649$11481
+ attribute \src "libresoc.v:177402.13-177402.33"
+ process $proc$libresoc.v:177402$11389
assign { } { }
assign $1\src14__data_o[3:0] 4'0000
sync always
sync init
update \src14__data_o $1\src14__data_o[3:0]
end
- attribute \src "libresoc.v:179656.13-179656.33"
- process $proc$libresoc.v:179656$11482
+ attribute \src "libresoc.v:177409.13-177409.33"
+ process $proc$libresoc.v:177409$11390
assign { } { }
assign $1\src24__data_o[3:0] 4'0000
sync always
sync init
update \src24__data_o $1\src24__data_o[3:0]
end
- attribute \src "libresoc.v:179663.13-179663.33"
- process $proc$libresoc.v:179663$11483
+ attribute \src "libresoc.v:177416.13-177416.33"
+ process $proc$libresoc.v:177416$11391
assign { } { }
assign $1\src34__data_o[3:0] 4'0000
sync always
sync init
update \src34__data_o $1\src34__data_o[3:0]
end
- attribute \src "libresoc.v:179687.3-179688.25"
- process $proc$libresoc.v:179687$11400
+ attribute \src "libresoc.v:177440.3-177441.25"
+ process $proc$libresoc.v:177440$11308
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:179689.3-179690.39"
- process $proc$libresoc.v:179689$11401
+ attribute \src "libresoc.v:177442.3-177443.39"
+ process $proc$libresoc.v:177442$11309
assign { } { }
assign $0\r24__data_o[3:0] \r24__data_o$next
sync posedge \coresync_clk
update \r24__data_o $0\r24__data_o[3:0]
end
- attribute \src "libresoc.v:179691.3-179692.37"
- process $proc$libresoc.v:179691$11402
+ attribute \src "libresoc.v:177444.3-177445.37"
+ process $proc$libresoc.v:177444$11310
assign { } { }
assign $0\r4__data_o[3:0] \r4__data_o$next
sync posedge \coresync_clk
update \r4__data_o $0\r4__data_o[3:0]
end
- attribute \src "libresoc.v:179693.3-179694.43"
- process $proc$libresoc.v:179693$11403
+ attribute \src "libresoc.v:177446.3-177447.43"
+ process $proc$libresoc.v:177446$11311
assign { } { }
assign $0\src34__data_o[3:0] \src34__data_o$next
sync posedge \coresync_clk
update \src34__data_o $0\src34__data_o[3:0]
end
- attribute \src "libresoc.v:179695.3-179696.43"
- process $proc$libresoc.v:179695$11404
+ attribute \src "libresoc.v:177448.3-177449.43"
+ process $proc$libresoc.v:177448$11312
assign { } { }
assign $0\src24__data_o[3:0] \src24__data_o$next
sync posedge \coresync_clk
update \src24__data_o $0\src24__data_o[3:0]
end
- attribute \src "libresoc.v:179697.3-179698.43"
- process $proc$libresoc.v:179697$11405
+ attribute \src "libresoc.v:177450.3-177451.43"
+ process $proc$libresoc.v:177450$11313
assign { } { }
assign $0\src14__data_o[3:0] \src14__data_o$next
sync posedge \coresync_clk
update \src14__data_o $0\src14__data_o[3:0]
end
- attribute \src "libresoc.v:179699.3-179738.6"
- process $proc$libresoc.v:179699$11406
+ attribute \src "libresoc.v:177452.3-177491.6"
+ process $proc$libresoc.v:177452$11314
assign { } { }
assign { } { }
assign { } { }
- assign $0\src14__data_o$next[3:0]$11407 $6\src14__data_o$next[3:0]$11413
- attribute \src "libresoc.v:179700.5-179700.29"
+ assign $0\src14__data_o$next[3:0]$11315 $6\src14__data_o$next[3:0]$11321
+ attribute \src "libresoc.v:177453.5-177453.29"
switch \initial
- attribute \src "libresoc.v:179700.9-179700.17"
+ attribute \src "libresoc.v:177453.9-177453.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src14__data_o$next[3:0]$11408 $5\src14__data_o$next[3:0]$11412
+ assign $1\src14__data_o$next[3:0]$11316 $5\src14__data_o$next[3:0]$11320
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src14__data_o$next[3:0]$11409 \dest14__data_i
+ assign $2\src14__data_o$next[3:0]$11317 \dest14__data_i
case
- assign $2\src14__data_o$next[3:0]$11409 4'0000
+ assign $2\src14__data_o$next[3:0]$11317 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src14__data_o$next[3:0]$11410 \dest24__data_i
+ assign $3\src14__data_o$next[3:0]$11318 \dest24__data_i
case
- assign $3\src14__data_o$next[3:0]$11410 $2\src14__data_o$next[3:0]$11409
+ assign $3\src14__data_o$next[3:0]$11318 $2\src14__data_o$next[3:0]$11317
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src14__data_o$next[3:0]$11411 \w4__data_i
+ assign $4\src14__data_o$next[3:0]$11319 \w4__data_i
case
- assign $4\src14__data_o$next[3:0]$11411 $3\src14__data_o$next[3:0]$11410
+ assign $4\src14__data_o$next[3:0]$11319 $3\src14__data_o$next[3:0]$11318
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src14__data_o$next[3:0]$11412 \reg
+ assign $5\src14__data_o$next[3:0]$11320 \reg
case
- assign $5\src14__data_o$next[3:0]$11412 $4\src14__data_o$next[3:0]$11411
+ assign $5\src14__data_o$next[3:0]$11320 $4\src14__data_o$next[3:0]$11319
end
case
- assign $1\src14__data_o$next[3:0]$11408 4'0000
+ assign $1\src14__data_o$next[3:0]$11316 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src14__data_o$next[3:0]$11413 4'0000
+ assign $6\src14__data_o$next[3:0]$11321 4'0000
case
- assign $6\src14__data_o$next[3:0]$11413 $1\src14__data_o$next[3:0]$11408
+ assign $6\src14__data_o$next[3:0]$11321 $1\src14__data_o$next[3:0]$11316
end
sync always
- update \src14__data_o$next $0\src14__data_o$next[3:0]$11407
+ update \src14__data_o$next $0\src14__data_o$next[3:0]$11315
end
- attribute \src "libresoc.v:179739.3-179768.6"
- process $proc$libresoc.v:179739$11414
+ attribute \src "libresoc.v:177492.3-177521.6"
+ process $proc$libresoc.v:177492$11322
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:179740.5-179740.29"
+ attribute \src "libresoc.v:177493.5-177493.29"
switch \initial
- attribute \src "libresoc.v:179740.9-179740.17"
+ attribute \src "libresoc.v:177493.9-177493.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:179769.3-179795.6"
- process $proc$libresoc.v:179769$11415
+ attribute \src "libresoc.v:177522.3-177548.6"
+ process $proc$libresoc.v:177522$11323
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11416 $4\reg$next[3:0]$11420
- attribute \src "libresoc.v:179770.5-179770.29"
+ assign $0\reg$next[3:0]$11324 $4\reg$next[3:0]$11328
+ attribute \src "libresoc.v:177523.5-177523.29"
switch \initial
- attribute \src "libresoc.v:179770.9-179770.17"
+ attribute \src "libresoc.v:177523.9-177523.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11417 \dest14__data_i
+ assign $1\reg$next[3:0]$11325 \dest14__data_i
case
- assign $1\reg$next[3:0]$11417 \reg
+ assign $1\reg$next[3:0]$11325 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11418 \dest24__data_i
+ assign $2\reg$next[3:0]$11326 \dest24__data_i
case
- assign $2\reg$next[3:0]$11418 $1\reg$next[3:0]$11417
+ assign $2\reg$next[3:0]$11326 $1\reg$next[3:0]$11325
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11419 \w4__data_i
+ assign $3\reg$next[3:0]$11327 \w4__data_i
case
- assign $3\reg$next[3:0]$11419 $2\reg$next[3:0]$11418
+ assign $3\reg$next[3:0]$11327 $2\reg$next[3:0]$11326
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11420 4'0000
+ assign $4\reg$next[3:0]$11328 4'0000
case
- assign $4\reg$next[3:0]$11420 $3\reg$next[3:0]$11419
+ assign $4\reg$next[3:0]$11328 $3\reg$next[3:0]$11327
end
sync always
- update \reg$next $0\reg$next[3:0]$11416
+ update \reg$next $0\reg$next[3:0]$11324
end
- attribute \src "libresoc.v:179796.3-179835.6"
- process $proc$libresoc.v:179796$11421
+ attribute \src "libresoc.v:177549.3-177588.6"
+ process $proc$libresoc.v:177549$11329
assign { } { }
assign { } { }
assign { } { }
- assign $0\src24__data_o$next[3:0]$11422 $6\src24__data_o$next[3:0]$11428
- attribute \src "libresoc.v:179797.5-179797.29"
+ assign $0\src24__data_o$next[3:0]$11330 $6\src24__data_o$next[3:0]$11336
+ attribute \src "libresoc.v:177550.5-177550.29"
switch \initial
- attribute \src "libresoc.v:179797.9-179797.17"
+ attribute \src "libresoc.v:177550.9-177550.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src24__data_o$next[3:0]$11423 $5\src24__data_o$next[3:0]$11427
+ assign $1\src24__data_o$next[3:0]$11331 $5\src24__data_o$next[3:0]$11335
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src24__data_o$next[3:0]$11424 \dest14__data_i
+ assign $2\src24__data_o$next[3:0]$11332 \dest14__data_i
case
- assign $2\src24__data_o$next[3:0]$11424 4'0000
+ assign $2\src24__data_o$next[3:0]$11332 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src24__data_o$next[3:0]$11425 \dest24__data_i
+ assign $3\src24__data_o$next[3:0]$11333 \dest24__data_i
case
- assign $3\src24__data_o$next[3:0]$11425 $2\src24__data_o$next[3:0]$11424
+ assign $3\src24__data_o$next[3:0]$11333 $2\src24__data_o$next[3:0]$11332
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src24__data_o$next[3:0]$11426 \w4__data_i
+ assign $4\src24__data_o$next[3:0]$11334 \w4__data_i
case
- assign $4\src24__data_o$next[3:0]$11426 $3\src24__data_o$next[3:0]$11425
+ assign $4\src24__data_o$next[3:0]$11334 $3\src24__data_o$next[3:0]$11333
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src24__data_o$next[3:0]$11427 \reg
+ assign $5\src24__data_o$next[3:0]$11335 \reg
case
- assign $5\src24__data_o$next[3:0]$11427 $4\src24__data_o$next[3:0]$11426
+ assign $5\src24__data_o$next[3:0]$11335 $4\src24__data_o$next[3:0]$11334
end
case
- assign $1\src24__data_o$next[3:0]$11423 4'0000
+ assign $1\src24__data_o$next[3:0]$11331 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src24__data_o$next[3:0]$11428 4'0000
+ assign $6\src24__data_o$next[3:0]$11336 4'0000
case
- assign $6\src24__data_o$next[3:0]$11428 $1\src24__data_o$next[3:0]$11423
+ assign $6\src24__data_o$next[3:0]$11336 $1\src24__data_o$next[3:0]$11331
end
sync always
- update \src24__data_o$next $0\src24__data_o$next[3:0]$11422
+ update \src24__data_o$next $0\src24__data_o$next[3:0]$11330
end
- attribute \src "libresoc.v:179836.3-179865.6"
- process $proc$libresoc.v:179836$11429
+ attribute \src "libresoc.v:177589.3-177618.6"
+ process $proc$libresoc.v:177589$11337
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11430 $1\wr_detect$4[0:0]$11431
- attribute \src "libresoc.v:179837.5-179837.29"
+ assign $0\wr_detect$4[0:0]$11338 $1\wr_detect$4[0:0]$11339
+ attribute \src "libresoc.v:177590.5-177590.29"
switch \initial
- attribute \src "libresoc.v:179837.9-179837.17"
+ attribute \src "libresoc.v:177590.9-177590.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11431 $4\wr_detect$4[0:0]$11434
+ assign $1\wr_detect$4[0:0]$11339 $4\wr_detect$4[0:0]$11342
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11432 1'1
+ assign $2\wr_detect$4[0:0]$11340 1'1
case
- assign $2\wr_detect$4[0:0]$11432 1'0
+ assign $2\wr_detect$4[0:0]$11340 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11433 1'1
+ assign $3\wr_detect$4[0:0]$11341 1'1
case
- assign $3\wr_detect$4[0:0]$11433 $2\wr_detect$4[0:0]$11432
+ assign $3\wr_detect$4[0:0]$11341 $2\wr_detect$4[0:0]$11340
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11434 1'1
+ assign $4\wr_detect$4[0:0]$11342 1'1
case
- assign $4\wr_detect$4[0:0]$11434 $3\wr_detect$4[0:0]$11433
+ assign $4\wr_detect$4[0:0]$11342 $3\wr_detect$4[0:0]$11341
end
case
- assign $1\wr_detect$4[0:0]$11431 1'0
+ assign $1\wr_detect$4[0:0]$11339 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11430
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11338
end
- attribute \src "libresoc.v:179866.3-179905.6"
- process $proc$libresoc.v:179866$11435
+ attribute \src "libresoc.v:177619.3-177658.6"
+ process $proc$libresoc.v:177619$11343
assign { } { }
assign { } { }
assign { } { }
- assign $0\src34__data_o$next[3:0]$11436 $6\src34__data_o$next[3:0]$11442
- attribute \src "libresoc.v:179867.5-179867.29"
+ assign $0\src34__data_o$next[3:0]$11344 $6\src34__data_o$next[3:0]$11350
+ attribute \src "libresoc.v:177620.5-177620.29"
switch \initial
- attribute \src "libresoc.v:179867.9-179867.17"
+ attribute \src "libresoc.v:177620.9-177620.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src34__data_o$next[3:0]$11437 $5\src34__data_o$next[3:0]$11441
+ assign $1\src34__data_o$next[3:0]$11345 $5\src34__data_o$next[3:0]$11349
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src34__data_o$next[3:0]$11438 \dest14__data_i
+ assign $2\src34__data_o$next[3:0]$11346 \dest14__data_i
case
- assign $2\src34__data_o$next[3:0]$11438 4'0000
+ assign $2\src34__data_o$next[3:0]$11346 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src34__data_o$next[3:0]$11439 \dest24__data_i
+ assign $3\src34__data_o$next[3:0]$11347 \dest24__data_i
case
- assign $3\src34__data_o$next[3:0]$11439 $2\src34__data_o$next[3:0]$11438
+ assign $3\src34__data_o$next[3:0]$11347 $2\src34__data_o$next[3:0]$11346
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src34__data_o$next[3:0]$11440 \w4__data_i
+ assign $4\src34__data_o$next[3:0]$11348 \w4__data_i
case
- assign $4\src34__data_o$next[3:0]$11440 $3\src34__data_o$next[3:0]$11439
+ assign $4\src34__data_o$next[3:0]$11348 $3\src34__data_o$next[3:0]$11347
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src34__data_o$next[3:0]$11441 \reg
+ assign $5\src34__data_o$next[3:0]$11349 \reg
case
- assign $5\src34__data_o$next[3:0]$11441 $4\src34__data_o$next[3:0]$11440
+ assign $5\src34__data_o$next[3:0]$11349 $4\src34__data_o$next[3:0]$11348
end
case
- assign $1\src34__data_o$next[3:0]$11437 4'0000
+ assign $1\src34__data_o$next[3:0]$11345 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src34__data_o$next[3:0]$11442 4'0000
+ assign $6\src34__data_o$next[3:0]$11350 4'0000
case
- assign $6\src34__data_o$next[3:0]$11442 $1\src34__data_o$next[3:0]$11437
+ assign $6\src34__data_o$next[3:0]$11350 $1\src34__data_o$next[3:0]$11345
end
sync always
- update \src34__data_o$next $0\src34__data_o$next[3:0]$11436
+ update \src34__data_o$next $0\src34__data_o$next[3:0]$11344
end
- attribute \src "libresoc.v:179906.3-179935.6"
- process $proc$libresoc.v:179906$11443
+ attribute \src "libresoc.v:177659.3-177688.6"
+ process $proc$libresoc.v:177659$11351
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11444 $1\wr_detect$7[0:0]$11445
- attribute \src "libresoc.v:179907.5-179907.29"
+ assign $0\wr_detect$7[0:0]$11352 $1\wr_detect$7[0:0]$11353
+ attribute \src "libresoc.v:177660.5-177660.29"
switch \initial
- attribute \src "libresoc.v:179907.9-179907.17"
+ attribute \src "libresoc.v:177660.9-177660.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11445 $4\wr_detect$7[0:0]$11448
+ assign $1\wr_detect$7[0:0]$11353 $4\wr_detect$7[0:0]$11356
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11446 1'1
+ assign $2\wr_detect$7[0:0]$11354 1'1
case
- assign $2\wr_detect$7[0:0]$11446 1'0
+ assign $2\wr_detect$7[0:0]$11354 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11447 1'1
+ assign $3\wr_detect$7[0:0]$11355 1'1
case
- assign $3\wr_detect$7[0:0]$11447 $2\wr_detect$7[0:0]$11446
+ assign $3\wr_detect$7[0:0]$11355 $2\wr_detect$7[0:0]$11354
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11448 1'1
+ assign $4\wr_detect$7[0:0]$11356 1'1
case
- assign $4\wr_detect$7[0:0]$11448 $3\wr_detect$7[0:0]$11447
+ assign $4\wr_detect$7[0:0]$11356 $3\wr_detect$7[0:0]$11355
end
case
- assign $1\wr_detect$7[0:0]$11445 1'0
+ assign $1\wr_detect$7[0:0]$11353 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11444
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11352
end
- attribute \src "libresoc.v:179936.3-179975.6"
- process $proc$libresoc.v:179936$11449
+ attribute \src "libresoc.v:177689.3-177728.6"
+ process $proc$libresoc.v:177689$11357
assign { } { }
assign { } { }
assign { } { }
- assign $0\r4__data_o$next[3:0]$11450 $6\r4__data_o$next[3:0]$11456
- attribute \src "libresoc.v:179937.5-179937.29"
+ assign $0\r4__data_o$next[3:0]$11358 $6\r4__data_o$next[3:0]$11364
+ attribute \src "libresoc.v:177690.5-177690.29"
switch \initial
- attribute \src "libresoc.v:179937.9-179937.17"
+ attribute \src "libresoc.v:177690.9-177690.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r4__data_o$next[3:0]$11451 $5\r4__data_o$next[3:0]$11455
+ assign $1\r4__data_o$next[3:0]$11359 $5\r4__data_o$next[3:0]$11363
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r4__data_o$next[3:0]$11452 \dest14__data_i
+ assign $2\r4__data_o$next[3:0]$11360 \dest14__data_i
case
- assign $2\r4__data_o$next[3:0]$11452 4'0000
+ assign $2\r4__data_o$next[3:0]$11360 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r4__data_o$next[3:0]$11453 \dest24__data_i
+ assign $3\r4__data_o$next[3:0]$11361 \dest24__data_i
case
- assign $3\r4__data_o$next[3:0]$11453 $2\r4__data_o$next[3:0]$11452
+ assign $3\r4__data_o$next[3:0]$11361 $2\r4__data_o$next[3:0]$11360
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r4__data_o$next[3:0]$11454 \w4__data_i
+ assign $4\r4__data_o$next[3:0]$11362 \w4__data_i
case
- assign $4\r4__data_o$next[3:0]$11454 $3\r4__data_o$next[3:0]$11453
+ assign $4\r4__data_o$next[3:0]$11362 $3\r4__data_o$next[3:0]$11361
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r4__data_o$next[3:0]$11455 \reg
+ assign $5\r4__data_o$next[3:0]$11363 \reg
case
- assign $5\r4__data_o$next[3:0]$11455 $4\r4__data_o$next[3:0]$11454
+ assign $5\r4__data_o$next[3:0]$11363 $4\r4__data_o$next[3:0]$11362
end
case
- assign $1\r4__data_o$next[3:0]$11451 4'0000
+ assign $1\r4__data_o$next[3:0]$11359 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r4__data_o$next[3:0]$11456 4'0000
+ assign $6\r4__data_o$next[3:0]$11364 4'0000
case
- assign $6\r4__data_o$next[3:0]$11456 $1\r4__data_o$next[3:0]$11451
+ assign $6\r4__data_o$next[3:0]$11364 $1\r4__data_o$next[3:0]$11359
end
sync always
- update \r4__data_o$next $0\r4__data_o$next[3:0]$11450
+ update \r4__data_o$next $0\r4__data_o$next[3:0]$11358
end
- attribute \src "libresoc.v:179976.3-180005.6"
- process $proc$libresoc.v:179976$11457
+ attribute \src "libresoc.v:177729.3-177758.6"
+ process $proc$libresoc.v:177729$11365
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11458 $1\wr_detect$10[0:0]$11459
- attribute \src "libresoc.v:179977.5-179977.29"
+ assign $0\wr_detect$10[0:0]$11366 $1\wr_detect$10[0:0]$11367
+ attribute \src "libresoc.v:177730.5-177730.29"
switch \initial
- attribute \src "libresoc.v:179977.9-179977.17"
+ attribute \src "libresoc.v:177730.9-177730.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11459 $4\wr_detect$10[0:0]$11462
+ assign $1\wr_detect$10[0:0]$11367 $4\wr_detect$10[0:0]$11370
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11460 1'1
+ assign $2\wr_detect$10[0:0]$11368 1'1
case
- assign $2\wr_detect$10[0:0]$11460 1'0
+ assign $2\wr_detect$10[0:0]$11368 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11461 1'1
+ assign $3\wr_detect$10[0:0]$11369 1'1
case
- assign $3\wr_detect$10[0:0]$11461 $2\wr_detect$10[0:0]$11460
+ assign $3\wr_detect$10[0:0]$11369 $2\wr_detect$10[0:0]$11368
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11462 1'1
+ assign $4\wr_detect$10[0:0]$11370 1'1
case
- assign $4\wr_detect$10[0:0]$11462 $3\wr_detect$10[0:0]$11461
+ assign $4\wr_detect$10[0:0]$11370 $3\wr_detect$10[0:0]$11369
end
case
- assign $1\wr_detect$10[0:0]$11459 1'0
+ assign $1\wr_detect$10[0:0]$11367 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11458
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11366
end
- attribute \src "libresoc.v:180006.3-180045.6"
- process $proc$libresoc.v:180006$11463
+ attribute \src "libresoc.v:177759.3-177798.6"
+ process $proc$libresoc.v:177759$11371
assign { } { }
assign { } { }
assign { } { }
- assign $0\r24__data_o$next[3:0]$11464 $6\r24__data_o$next[3:0]$11470
- attribute \src "libresoc.v:180007.5-180007.29"
+ assign $0\r24__data_o$next[3:0]$11372 $6\r24__data_o$next[3:0]$11378
+ attribute \src "libresoc.v:177760.5-177760.29"
switch \initial
- attribute \src "libresoc.v:180007.9-180007.17"
+ attribute \src "libresoc.v:177760.9-177760.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r24__data_o$next[3:0]$11465 $5\r24__data_o$next[3:0]$11469
+ assign $1\r24__data_o$next[3:0]$11373 $5\r24__data_o$next[3:0]$11377
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r24__data_o$next[3:0]$11466 \dest14__data_i
+ assign $2\r24__data_o$next[3:0]$11374 \dest14__data_i
case
- assign $2\r24__data_o$next[3:0]$11466 4'0000
+ assign $2\r24__data_o$next[3:0]$11374 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r24__data_o$next[3:0]$11467 \dest24__data_i
+ assign $3\r24__data_o$next[3:0]$11375 \dest24__data_i
case
- assign $3\r24__data_o$next[3:0]$11467 $2\r24__data_o$next[3:0]$11466
+ assign $3\r24__data_o$next[3:0]$11375 $2\r24__data_o$next[3:0]$11374
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r24__data_o$next[3:0]$11468 \w4__data_i
+ assign $4\r24__data_o$next[3:0]$11376 \w4__data_i
case
- assign $4\r24__data_o$next[3:0]$11468 $3\r24__data_o$next[3:0]$11467
+ assign $4\r24__data_o$next[3:0]$11376 $3\r24__data_o$next[3:0]$11375
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r24__data_o$next[3:0]$11469 \reg
+ assign $5\r24__data_o$next[3:0]$11377 \reg
case
- assign $5\r24__data_o$next[3:0]$11469 $4\r24__data_o$next[3:0]$11468
+ assign $5\r24__data_o$next[3:0]$11377 $4\r24__data_o$next[3:0]$11376
end
case
- assign $1\r24__data_o$next[3:0]$11465 4'0000
+ assign $1\r24__data_o$next[3:0]$11373 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r24__data_o$next[3:0]$11470 4'0000
+ assign $6\r24__data_o$next[3:0]$11378 4'0000
case
- assign $6\r24__data_o$next[3:0]$11470 $1\r24__data_o$next[3:0]$11465
+ assign $6\r24__data_o$next[3:0]$11378 $1\r24__data_o$next[3:0]$11373
end
sync always
- update \r24__data_o$next $0\r24__data_o$next[3:0]$11464
+ update \r24__data_o$next $0\r24__data_o$next[3:0]$11372
end
- attribute \src "libresoc.v:180046.3-180075.6"
- process $proc$libresoc.v:180046$11471
+ attribute \src "libresoc.v:177799.3-177828.6"
+ process $proc$libresoc.v:177799$11379
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11472 $1\wr_detect$13[0:0]$11473
- attribute \src "libresoc.v:180047.5-180047.29"
+ assign $0\wr_detect$13[0:0]$11380 $1\wr_detect$13[0:0]$11381
+ attribute \src "libresoc.v:177800.5-177800.29"
switch \initial
- attribute \src "libresoc.v:180047.9-180047.17"
+ attribute \src "libresoc.v:177800.9-177800.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11473 $4\wr_detect$13[0:0]$11476
+ assign $1\wr_detect$13[0:0]$11381 $4\wr_detect$13[0:0]$11384
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest14__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11474 1'1
+ assign $2\wr_detect$13[0:0]$11382 1'1
case
- assign $2\wr_detect$13[0:0]$11474 1'0
+ assign $2\wr_detect$13[0:0]$11382 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest24__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11475 1'1
+ assign $3\wr_detect$13[0:0]$11383 1'1
case
- assign $3\wr_detect$13[0:0]$11475 $2\wr_detect$13[0:0]$11474
+ assign $3\wr_detect$13[0:0]$11383 $2\wr_detect$13[0:0]$11382
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w4__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11476 1'1
+ assign $4\wr_detect$13[0:0]$11384 1'1
case
- assign $4\wr_detect$13[0:0]$11476 $3\wr_detect$13[0:0]$11475
+ assign $4\wr_detect$13[0:0]$11384 $3\wr_detect$13[0:0]$11383
end
case
- assign $1\wr_detect$13[0:0]$11473 1'0
+ assign $1\wr_detect$13[0:0]$11381 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11472
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11380
end
- connect \$9 $not$libresoc.v:179682$11395_Y
- connect \$12 $not$libresoc.v:179683$11396_Y
- connect \$1 $not$libresoc.v:179684$11397_Y
- connect \$3 $not$libresoc.v:179685$11398_Y
- connect \$6 $not$libresoc.v:179686$11399_Y
+ connect \$9 $not$libresoc.v:177435$11303_Y
+ connect \$12 $not$libresoc.v:177436$11304_Y
+ connect \$1 $not$libresoc.v:177437$11305_Y
+ connect \$3 $not$libresoc.v:177438$11306_Y
+ connect \$6 $not$libresoc.v:177439$11307_Y
end
-attribute \src "libresoc.v:180080.1-180551.10"
+attribute \src "libresoc.v:177833.1-178304.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5"
attribute \generator "nMigen"
module \reg_5
- attribute \src "libresoc.v:180081.7-180081.20"
+ attribute \src "libresoc.v:177834.7-177834.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $0\r25__data_o$next[3:0]$11553
- attribute \src "libresoc.v:180164.3-180165.39"
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $0\r25__data_o$next[3:0]$11461
+ attribute \src "libresoc.v:177917.3-177918.39"
wire width 4 $0\r25__data_o[3:0]
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $0\r5__data_o$next[3:0]$11539
- attribute \src "libresoc.v:180166.3-180167.37"
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $0\r5__data_o$next[3:0]$11447
+ attribute \src "libresoc.v:177919.3-177920.37"
wire width 4 $0\r5__data_o[3:0]
- attribute \src "libresoc.v:180244.3-180270.6"
- wire width 4 $0\reg$next[3:0]$11505
- attribute \src "libresoc.v:180162.3-180163.25"
+ attribute \src "libresoc.v:177997.3-178023.6"
+ wire width 4 $0\reg$next[3:0]$11413
+ attribute \src "libresoc.v:177915.3-177916.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $0\src15__data_o$next[3:0]$11496
- attribute \src "libresoc.v:180172.3-180173.43"
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $0\src15__data_o$next[3:0]$11404
+ attribute \src "libresoc.v:177925.3-177926.43"
wire width 4 $0\src15__data_o[3:0]
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $0\src25__data_o$next[3:0]$11511
- attribute \src "libresoc.v:180170.3-180171.43"
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $0\src25__data_o$next[3:0]$11419
+ attribute \src "libresoc.v:177923.3-177924.43"
wire width 4 $0\src25__data_o[3:0]
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $0\src35__data_o$next[3:0]$11525
- attribute \src "libresoc.v:180168.3-180169.43"
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $0\src35__data_o$next[3:0]$11433
+ attribute \src "libresoc.v:177921.3-177922.43"
wire width 4 $0\src35__data_o[3:0]
- attribute \src "libresoc.v:180451.3-180480.6"
- wire $0\wr_detect$10[0:0]$11547
- attribute \src "libresoc.v:180521.3-180550.6"
- wire $0\wr_detect$13[0:0]$11561
- attribute \src "libresoc.v:180311.3-180340.6"
- wire $0\wr_detect$4[0:0]$11519
- attribute \src "libresoc.v:180381.3-180410.6"
- wire $0\wr_detect$7[0:0]$11533
- attribute \src "libresoc.v:180214.3-180243.6"
+ attribute \src "libresoc.v:178204.3-178233.6"
+ wire $0\wr_detect$10[0:0]$11455
+ attribute \src "libresoc.v:178274.3-178303.6"
+ wire $0\wr_detect$13[0:0]$11469
+ attribute \src "libresoc.v:178064.3-178093.6"
+ wire $0\wr_detect$4[0:0]$11427
+ attribute \src "libresoc.v:178134.3-178163.6"
+ wire $0\wr_detect$7[0:0]$11441
+ attribute \src "libresoc.v:177967.3-177996.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $1\r25__data_o$next[3:0]$11554
- attribute \src "libresoc.v:180106.13-180106.31"
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $1\r25__data_o$next[3:0]$11462
+ attribute \src "libresoc.v:177859.13-177859.31"
wire width 4 $1\r25__data_o[3:0]
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $1\r5__data_o$next[3:0]$11540
- attribute \src "libresoc.v:180113.13-180113.30"
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $1\r5__data_o$next[3:0]$11448
+ attribute \src "libresoc.v:177866.13-177866.30"
wire width 4 $1\r5__data_o[3:0]
- attribute \src "libresoc.v:180244.3-180270.6"
- wire width 4 $1\reg$next[3:0]$11506
- attribute \src "libresoc.v:180119.13-180119.25"
+ attribute \src "libresoc.v:177997.3-178023.6"
+ wire width 4 $1\reg$next[3:0]$11414
+ attribute \src "libresoc.v:177872.13-177872.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $1\src15__data_o$next[3:0]$11497
- attribute \src "libresoc.v:180124.13-180124.33"
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $1\src15__data_o$next[3:0]$11405
+ attribute \src "libresoc.v:177877.13-177877.33"
wire width 4 $1\src15__data_o[3:0]
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $1\src25__data_o$next[3:0]$11512
- attribute \src "libresoc.v:180131.13-180131.33"
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $1\src25__data_o$next[3:0]$11420
+ attribute \src "libresoc.v:177884.13-177884.33"
wire width 4 $1\src25__data_o[3:0]
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $1\src35__data_o$next[3:0]$11526
- attribute \src "libresoc.v:180138.13-180138.33"
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $1\src35__data_o$next[3:0]$11434
+ attribute \src "libresoc.v:177891.13-177891.33"
wire width 4 $1\src35__data_o[3:0]
- attribute \src "libresoc.v:180451.3-180480.6"
- wire $1\wr_detect$10[0:0]$11548
- attribute \src "libresoc.v:180521.3-180550.6"
- wire $1\wr_detect$13[0:0]$11562
- attribute \src "libresoc.v:180311.3-180340.6"
- wire $1\wr_detect$4[0:0]$11520
- attribute \src "libresoc.v:180381.3-180410.6"
- wire $1\wr_detect$7[0:0]$11534
- attribute \src "libresoc.v:180214.3-180243.6"
+ attribute \src "libresoc.v:178204.3-178233.6"
+ wire $1\wr_detect$10[0:0]$11456
+ attribute \src "libresoc.v:178274.3-178303.6"
+ wire $1\wr_detect$13[0:0]$11470
+ attribute \src "libresoc.v:178064.3-178093.6"
+ wire $1\wr_detect$4[0:0]$11428
+ attribute \src "libresoc.v:178134.3-178163.6"
+ wire $1\wr_detect$7[0:0]$11442
+ attribute \src "libresoc.v:177967.3-177996.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $2\r25__data_o$next[3:0]$11555
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $2\r5__data_o$next[3:0]$11541
- attribute \src "libresoc.v:180244.3-180270.6"
- wire width 4 $2\reg$next[3:0]$11507
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $2\src15__data_o$next[3:0]$11498
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $2\src25__data_o$next[3:0]$11513
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $2\src35__data_o$next[3:0]$11527
- attribute \src "libresoc.v:180451.3-180480.6"
- wire $2\wr_detect$10[0:0]$11549
- attribute \src "libresoc.v:180521.3-180550.6"
- wire $2\wr_detect$13[0:0]$11563
- attribute \src "libresoc.v:180311.3-180340.6"
- wire $2\wr_detect$4[0:0]$11521
- attribute \src "libresoc.v:180381.3-180410.6"
- wire $2\wr_detect$7[0:0]$11535
- attribute \src "libresoc.v:180214.3-180243.6"
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $2\r25__data_o$next[3:0]$11463
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $2\r5__data_o$next[3:0]$11449
+ attribute \src "libresoc.v:177997.3-178023.6"
+ wire width 4 $2\reg$next[3:0]$11415
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $2\src15__data_o$next[3:0]$11406
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $2\src25__data_o$next[3:0]$11421
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $2\src35__data_o$next[3:0]$11435
+ attribute \src "libresoc.v:178204.3-178233.6"
+ wire $2\wr_detect$10[0:0]$11457
+ attribute \src "libresoc.v:178274.3-178303.6"
+ wire $2\wr_detect$13[0:0]$11471
+ attribute \src "libresoc.v:178064.3-178093.6"
+ wire $2\wr_detect$4[0:0]$11429
+ attribute \src "libresoc.v:178134.3-178163.6"
+ wire $2\wr_detect$7[0:0]$11443
+ attribute \src "libresoc.v:177967.3-177996.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $3\r25__data_o$next[3:0]$11556
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $3\r5__data_o$next[3:0]$11542
- attribute \src "libresoc.v:180244.3-180270.6"
- wire width 4 $3\reg$next[3:0]$11508
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $3\src15__data_o$next[3:0]$11499
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $3\src25__data_o$next[3:0]$11514
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $3\src35__data_o$next[3:0]$11528
- attribute \src "libresoc.v:180451.3-180480.6"
- wire $3\wr_detect$10[0:0]$11550
- attribute \src "libresoc.v:180521.3-180550.6"
- wire $3\wr_detect$13[0:0]$11564
- attribute \src "libresoc.v:180311.3-180340.6"
- wire $3\wr_detect$4[0:0]$11522
- attribute \src "libresoc.v:180381.3-180410.6"
- wire $3\wr_detect$7[0:0]$11536
- attribute \src "libresoc.v:180214.3-180243.6"
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $3\r25__data_o$next[3:0]$11464
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $3\r5__data_o$next[3:0]$11450
+ attribute \src "libresoc.v:177997.3-178023.6"
+ wire width 4 $3\reg$next[3:0]$11416
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $3\src15__data_o$next[3:0]$11407
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $3\src25__data_o$next[3:0]$11422
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $3\src35__data_o$next[3:0]$11436
+ attribute \src "libresoc.v:178204.3-178233.6"
+ wire $3\wr_detect$10[0:0]$11458
+ attribute \src "libresoc.v:178274.3-178303.6"
+ wire $3\wr_detect$13[0:0]$11472
+ attribute \src "libresoc.v:178064.3-178093.6"
+ wire $3\wr_detect$4[0:0]$11430
+ attribute \src "libresoc.v:178134.3-178163.6"
+ wire $3\wr_detect$7[0:0]$11444
+ attribute \src "libresoc.v:177967.3-177996.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $4\r25__data_o$next[3:0]$11557
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $4\r5__data_o$next[3:0]$11543
- attribute \src "libresoc.v:180244.3-180270.6"
- wire width 4 $4\reg$next[3:0]$11509
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $4\src15__data_o$next[3:0]$11500
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $4\src25__data_o$next[3:0]$11515
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $4\src35__data_o$next[3:0]$11529
- attribute \src "libresoc.v:180451.3-180480.6"
- wire $4\wr_detect$10[0:0]$11551
- attribute \src "libresoc.v:180521.3-180550.6"
- wire $4\wr_detect$13[0:0]$11565
- attribute \src "libresoc.v:180311.3-180340.6"
- wire $4\wr_detect$4[0:0]$11523
- attribute \src "libresoc.v:180381.3-180410.6"
- wire $4\wr_detect$7[0:0]$11537
- attribute \src "libresoc.v:180214.3-180243.6"
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $4\r25__data_o$next[3:0]$11465
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $4\r5__data_o$next[3:0]$11451
+ attribute \src "libresoc.v:177997.3-178023.6"
+ wire width 4 $4\reg$next[3:0]$11417
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $4\src15__data_o$next[3:0]$11408
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $4\src25__data_o$next[3:0]$11423
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $4\src35__data_o$next[3:0]$11437
+ attribute \src "libresoc.v:178204.3-178233.6"
+ wire $4\wr_detect$10[0:0]$11459
+ attribute \src "libresoc.v:178274.3-178303.6"
+ wire $4\wr_detect$13[0:0]$11473
+ attribute \src "libresoc.v:178064.3-178093.6"
+ wire $4\wr_detect$4[0:0]$11431
+ attribute \src "libresoc.v:178134.3-178163.6"
+ wire $4\wr_detect$7[0:0]$11445
+ attribute \src "libresoc.v:177967.3-177996.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $5\r25__data_o$next[3:0]$11558
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $5\r5__data_o$next[3:0]$11544
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $5\src15__data_o$next[3:0]$11501
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $5\src25__data_o$next[3:0]$11516
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $5\src35__data_o$next[3:0]$11530
- attribute \src "libresoc.v:180481.3-180520.6"
- wire width 4 $6\r25__data_o$next[3:0]$11559
- attribute \src "libresoc.v:180411.3-180450.6"
- wire width 4 $6\r5__data_o$next[3:0]$11545
- attribute \src "libresoc.v:180174.3-180213.6"
- wire width 4 $6\src15__data_o$next[3:0]$11502
- attribute \src "libresoc.v:180271.3-180310.6"
- wire width 4 $6\src25__data_o$next[3:0]$11517
- attribute \src "libresoc.v:180341.3-180380.6"
- wire width 4 $6\src35__data_o$next[3:0]$11531
- attribute \src "libresoc.v:180157.17-180157.104"
- wire $not$libresoc.v:180157$11484_Y
- attribute \src "libresoc.v:180158.18-180158.105"
- wire $not$libresoc.v:180158$11485_Y
- attribute \src "libresoc.v:180159.17-180159.100"
- wire $not$libresoc.v:180159$11486_Y
- attribute \src "libresoc.v:180160.17-180160.103"
- wire $not$libresoc.v:180160$11487_Y
- attribute \src "libresoc.v:180161.17-180161.103"
- wire $not$libresoc.v:180161$11488_Y
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $5\r25__data_o$next[3:0]$11466
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $5\r5__data_o$next[3:0]$11452
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $5\src15__data_o$next[3:0]$11409
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $5\src25__data_o$next[3:0]$11424
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $5\src35__data_o$next[3:0]$11438
+ attribute \src "libresoc.v:178234.3-178273.6"
+ wire width 4 $6\r25__data_o$next[3:0]$11467
+ attribute \src "libresoc.v:178164.3-178203.6"
+ wire width 4 $6\r5__data_o$next[3:0]$11453
+ attribute \src "libresoc.v:177927.3-177966.6"
+ wire width 4 $6\src15__data_o$next[3:0]$11410
+ attribute \src "libresoc.v:178024.3-178063.6"
+ wire width 4 $6\src25__data_o$next[3:0]$11425
+ attribute \src "libresoc.v:178094.3-178133.6"
+ wire width 4 $6\src35__data_o$next[3:0]$11439
+ attribute \src "libresoc.v:177910.17-177910.104"
+ wire $not$libresoc.v:177910$11392_Y
+ attribute \src "libresoc.v:177911.18-177911.105"
+ wire $not$libresoc.v:177911$11393_Y
+ attribute \src "libresoc.v:177912.17-177912.100"
+ wire $not$libresoc.v:177912$11394_Y
+ attribute \src "libresoc.v:177913.17-177913.103"
+ wire $not$libresoc.v:177913$11395_Y
+ attribute \src "libresoc.v:177914.17-177914.103"
+ wire $not$libresoc.v:177914$11396_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest15__data_i
wire width 4 input 11 \dest25__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest25__wen
- attribute \src "libresoc.v:180081.7-180081.15"
+ attribute \src "libresoc.v:177834.7-177834.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r25__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180157$11484
+ cell $not $not$libresoc.v:177910$11392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:180157$11484_Y
+ connect \Y $not$libresoc.v:177910$11392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180158$11485
+ cell $not $not$libresoc.v:177911$11393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:180158$11485_Y
+ connect \Y $not$libresoc.v:177911$11393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180159$11486
+ cell $not $not$libresoc.v:177912$11394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:180159$11486_Y
+ connect \Y $not$libresoc.v:177912$11394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180160$11487
+ cell $not $not$libresoc.v:177913$11395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:180160$11487_Y
+ connect \Y $not$libresoc.v:177913$11395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180161$11488
+ cell $not $not$libresoc.v:177914$11396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:180161$11488_Y
+ connect \Y $not$libresoc.v:177914$11396_Y
end
- attribute \src "libresoc.v:180081.7-180081.20"
- process $proc$libresoc.v:180081$11566
+ attribute \src "libresoc.v:177834.7-177834.20"
+ process $proc$libresoc.v:177834$11474
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:180106.13-180106.31"
- process $proc$libresoc.v:180106$11567
+ attribute \src "libresoc.v:177859.13-177859.31"
+ process $proc$libresoc.v:177859$11475
assign { } { }
assign $1\r25__data_o[3:0] 4'0000
sync always
sync init
update \r25__data_o $1\r25__data_o[3:0]
end
- attribute \src "libresoc.v:180113.13-180113.30"
- process $proc$libresoc.v:180113$11568
+ attribute \src "libresoc.v:177866.13-177866.30"
+ process $proc$libresoc.v:177866$11476
assign { } { }
assign $1\r5__data_o[3:0] 4'0000
sync always
sync init
update \r5__data_o $1\r5__data_o[3:0]
end
- attribute \src "libresoc.v:180119.13-180119.25"
- process $proc$libresoc.v:180119$11569
+ attribute \src "libresoc.v:177872.13-177872.25"
+ process $proc$libresoc.v:177872$11477
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:180124.13-180124.33"
- process $proc$libresoc.v:180124$11570
+ attribute \src "libresoc.v:177877.13-177877.33"
+ process $proc$libresoc.v:177877$11478
assign { } { }
assign $1\src15__data_o[3:0] 4'0000
sync always
sync init
update \src15__data_o $1\src15__data_o[3:0]
end
- attribute \src "libresoc.v:180131.13-180131.33"
- process $proc$libresoc.v:180131$11571
+ attribute \src "libresoc.v:177884.13-177884.33"
+ process $proc$libresoc.v:177884$11479
assign { } { }
assign $1\src25__data_o[3:0] 4'0000
sync always
sync init
update \src25__data_o $1\src25__data_o[3:0]
end
- attribute \src "libresoc.v:180138.13-180138.33"
- process $proc$libresoc.v:180138$11572
+ attribute \src "libresoc.v:177891.13-177891.33"
+ process $proc$libresoc.v:177891$11480
assign { } { }
assign $1\src35__data_o[3:0] 4'0000
sync always
sync init
update \src35__data_o $1\src35__data_o[3:0]
end
- attribute \src "libresoc.v:180162.3-180163.25"
- process $proc$libresoc.v:180162$11489
+ attribute \src "libresoc.v:177915.3-177916.25"
+ process $proc$libresoc.v:177915$11397
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:180164.3-180165.39"
- process $proc$libresoc.v:180164$11490
+ attribute \src "libresoc.v:177917.3-177918.39"
+ process $proc$libresoc.v:177917$11398
assign { } { }
assign $0\r25__data_o[3:0] \r25__data_o$next
sync posedge \coresync_clk
update \r25__data_o $0\r25__data_o[3:0]
end
- attribute \src "libresoc.v:180166.3-180167.37"
- process $proc$libresoc.v:180166$11491
+ attribute \src "libresoc.v:177919.3-177920.37"
+ process $proc$libresoc.v:177919$11399
assign { } { }
assign $0\r5__data_o[3:0] \r5__data_o$next
sync posedge \coresync_clk
update \r5__data_o $0\r5__data_o[3:0]
end
- attribute \src "libresoc.v:180168.3-180169.43"
- process $proc$libresoc.v:180168$11492
+ attribute \src "libresoc.v:177921.3-177922.43"
+ process $proc$libresoc.v:177921$11400
assign { } { }
assign $0\src35__data_o[3:0] \src35__data_o$next
sync posedge \coresync_clk
update \src35__data_o $0\src35__data_o[3:0]
end
- attribute \src "libresoc.v:180170.3-180171.43"
- process $proc$libresoc.v:180170$11493
+ attribute \src "libresoc.v:177923.3-177924.43"
+ process $proc$libresoc.v:177923$11401
assign { } { }
assign $0\src25__data_o[3:0] \src25__data_o$next
sync posedge \coresync_clk
update \src25__data_o $0\src25__data_o[3:0]
end
- attribute \src "libresoc.v:180172.3-180173.43"
- process $proc$libresoc.v:180172$11494
+ attribute \src "libresoc.v:177925.3-177926.43"
+ process $proc$libresoc.v:177925$11402
assign { } { }
assign $0\src15__data_o[3:0] \src15__data_o$next
sync posedge \coresync_clk
update \src15__data_o $0\src15__data_o[3:0]
end
- attribute \src "libresoc.v:180174.3-180213.6"
- process $proc$libresoc.v:180174$11495
+ attribute \src "libresoc.v:177927.3-177966.6"
+ process $proc$libresoc.v:177927$11403
assign { } { }
assign { } { }
assign { } { }
- assign $0\src15__data_o$next[3:0]$11496 $6\src15__data_o$next[3:0]$11502
- attribute \src "libresoc.v:180175.5-180175.29"
+ assign $0\src15__data_o$next[3:0]$11404 $6\src15__data_o$next[3:0]$11410
+ attribute \src "libresoc.v:177928.5-177928.29"
switch \initial
- attribute \src "libresoc.v:180175.9-180175.17"
+ attribute \src "libresoc.v:177928.9-177928.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src15__data_o$next[3:0]$11497 $5\src15__data_o$next[3:0]$11501
+ assign $1\src15__data_o$next[3:0]$11405 $5\src15__data_o$next[3:0]$11409
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src15__data_o$next[3:0]$11498 \dest15__data_i
+ assign $2\src15__data_o$next[3:0]$11406 \dest15__data_i
case
- assign $2\src15__data_o$next[3:0]$11498 4'0000
+ assign $2\src15__data_o$next[3:0]$11406 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src15__data_o$next[3:0]$11499 \dest25__data_i
+ assign $3\src15__data_o$next[3:0]$11407 \dest25__data_i
case
- assign $3\src15__data_o$next[3:0]$11499 $2\src15__data_o$next[3:0]$11498
+ assign $3\src15__data_o$next[3:0]$11407 $2\src15__data_o$next[3:0]$11406
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src15__data_o$next[3:0]$11500 \w5__data_i
+ assign $4\src15__data_o$next[3:0]$11408 \w5__data_i
case
- assign $4\src15__data_o$next[3:0]$11500 $3\src15__data_o$next[3:0]$11499
+ assign $4\src15__data_o$next[3:0]$11408 $3\src15__data_o$next[3:0]$11407
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src15__data_o$next[3:0]$11501 \reg
+ assign $5\src15__data_o$next[3:0]$11409 \reg
case
- assign $5\src15__data_o$next[3:0]$11501 $4\src15__data_o$next[3:0]$11500
+ assign $5\src15__data_o$next[3:0]$11409 $4\src15__data_o$next[3:0]$11408
end
case
- assign $1\src15__data_o$next[3:0]$11497 4'0000
+ assign $1\src15__data_o$next[3:0]$11405 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src15__data_o$next[3:0]$11502 4'0000
+ assign $6\src15__data_o$next[3:0]$11410 4'0000
case
- assign $6\src15__data_o$next[3:0]$11502 $1\src15__data_o$next[3:0]$11497
+ assign $6\src15__data_o$next[3:0]$11410 $1\src15__data_o$next[3:0]$11405
end
sync always
- update \src15__data_o$next $0\src15__data_o$next[3:0]$11496
+ update \src15__data_o$next $0\src15__data_o$next[3:0]$11404
end
- attribute \src "libresoc.v:180214.3-180243.6"
- process $proc$libresoc.v:180214$11503
+ attribute \src "libresoc.v:177967.3-177996.6"
+ process $proc$libresoc.v:177967$11411
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:180215.5-180215.29"
+ attribute \src "libresoc.v:177968.5-177968.29"
switch \initial
- attribute \src "libresoc.v:180215.9-180215.17"
+ attribute \src "libresoc.v:177968.9-177968.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:180244.3-180270.6"
- process $proc$libresoc.v:180244$11504
+ attribute \src "libresoc.v:177997.3-178023.6"
+ process $proc$libresoc.v:177997$11412
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11505 $4\reg$next[3:0]$11509
- attribute \src "libresoc.v:180245.5-180245.29"
+ assign $0\reg$next[3:0]$11413 $4\reg$next[3:0]$11417
+ attribute \src "libresoc.v:177998.5-177998.29"
switch \initial
- attribute \src "libresoc.v:180245.9-180245.17"
+ attribute \src "libresoc.v:177998.9-177998.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11506 \dest15__data_i
+ assign $1\reg$next[3:0]$11414 \dest15__data_i
case
- assign $1\reg$next[3:0]$11506 \reg
+ assign $1\reg$next[3:0]$11414 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11507 \dest25__data_i
+ assign $2\reg$next[3:0]$11415 \dest25__data_i
case
- assign $2\reg$next[3:0]$11507 $1\reg$next[3:0]$11506
+ assign $2\reg$next[3:0]$11415 $1\reg$next[3:0]$11414
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11508 \w5__data_i
+ assign $3\reg$next[3:0]$11416 \w5__data_i
case
- assign $3\reg$next[3:0]$11508 $2\reg$next[3:0]$11507
+ assign $3\reg$next[3:0]$11416 $2\reg$next[3:0]$11415
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11509 4'0000
+ assign $4\reg$next[3:0]$11417 4'0000
case
- assign $4\reg$next[3:0]$11509 $3\reg$next[3:0]$11508
+ assign $4\reg$next[3:0]$11417 $3\reg$next[3:0]$11416
end
sync always
- update \reg$next $0\reg$next[3:0]$11505
+ update \reg$next $0\reg$next[3:0]$11413
end
- attribute \src "libresoc.v:180271.3-180310.6"
- process $proc$libresoc.v:180271$11510
+ attribute \src "libresoc.v:178024.3-178063.6"
+ process $proc$libresoc.v:178024$11418
assign { } { }
assign { } { }
assign { } { }
- assign $0\src25__data_o$next[3:0]$11511 $6\src25__data_o$next[3:0]$11517
- attribute \src "libresoc.v:180272.5-180272.29"
+ assign $0\src25__data_o$next[3:0]$11419 $6\src25__data_o$next[3:0]$11425
+ attribute \src "libresoc.v:178025.5-178025.29"
switch \initial
- attribute \src "libresoc.v:180272.9-180272.17"
+ attribute \src "libresoc.v:178025.9-178025.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src25__data_o$next[3:0]$11512 $5\src25__data_o$next[3:0]$11516
+ assign $1\src25__data_o$next[3:0]$11420 $5\src25__data_o$next[3:0]$11424
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src25__data_o$next[3:0]$11513 \dest15__data_i
+ assign $2\src25__data_o$next[3:0]$11421 \dest15__data_i
case
- assign $2\src25__data_o$next[3:0]$11513 4'0000
+ assign $2\src25__data_o$next[3:0]$11421 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src25__data_o$next[3:0]$11514 \dest25__data_i
+ assign $3\src25__data_o$next[3:0]$11422 \dest25__data_i
case
- assign $3\src25__data_o$next[3:0]$11514 $2\src25__data_o$next[3:0]$11513
+ assign $3\src25__data_o$next[3:0]$11422 $2\src25__data_o$next[3:0]$11421
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src25__data_o$next[3:0]$11515 \w5__data_i
+ assign $4\src25__data_o$next[3:0]$11423 \w5__data_i
case
- assign $4\src25__data_o$next[3:0]$11515 $3\src25__data_o$next[3:0]$11514
+ assign $4\src25__data_o$next[3:0]$11423 $3\src25__data_o$next[3:0]$11422
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src25__data_o$next[3:0]$11516 \reg
+ assign $5\src25__data_o$next[3:0]$11424 \reg
case
- assign $5\src25__data_o$next[3:0]$11516 $4\src25__data_o$next[3:0]$11515
+ assign $5\src25__data_o$next[3:0]$11424 $4\src25__data_o$next[3:0]$11423
end
case
- assign $1\src25__data_o$next[3:0]$11512 4'0000
+ assign $1\src25__data_o$next[3:0]$11420 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src25__data_o$next[3:0]$11517 4'0000
+ assign $6\src25__data_o$next[3:0]$11425 4'0000
case
- assign $6\src25__data_o$next[3:0]$11517 $1\src25__data_o$next[3:0]$11512
+ assign $6\src25__data_o$next[3:0]$11425 $1\src25__data_o$next[3:0]$11420
end
sync always
- update \src25__data_o$next $0\src25__data_o$next[3:0]$11511
+ update \src25__data_o$next $0\src25__data_o$next[3:0]$11419
end
- attribute \src "libresoc.v:180311.3-180340.6"
- process $proc$libresoc.v:180311$11518
+ attribute \src "libresoc.v:178064.3-178093.6"
+ process $proc$libresoc.v:178064$11426
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11519 $1\wr_detect$4[0:0]$11520
- attribute \src "libresoc.v:180312.5-180312.29"
+ assign $0\wr_detect$4[0:0]$11427 $1\wr_detect$4[0:0]$11428
+ attribute \src "libresoc.v:178065.5-178065.29"
switch \initial
- attribute \src "libresoc.v:180312.9-180312.17"
+ attribute \src "libresoc.v:178065.9-178065.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11520 $4\wr_detect$4[0:0]$11523
+ assign $1\wr_detect$4[0:0]$11428 $4\wr_detect$4[0:0]$11431
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11521 1'1
+ assign $2\wr_detect$4[0:0]$11429 1'1
case
- assign $2\wr_detect$4[0:0]$11521 1'0
+ assign $2\wr_detect$4[0:0]$11429 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11522 1'1
+ assign $3\wr_detect$4[0:0]$11430 1'1
case
- assign $3\wr_detect$4[0:0]$11522 $2\wr_detect$4[0:0]$11521
+ assign $3\wr_detect$4[0:0]$11430 $2\wr_detect$4[0:0]$11429
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11523 1'1
+ assign $4\wr_detect$4[0:0]$11431 1'1
case
- assign $4\wr_detect$4[0:0]$11523 $3\wr_detect$4[0:0]$11522
+ assign $4\wr_detect$4[0:0]$11431 $3\wr_detect$4[0:0]$11430
end
case
- assign $1\wr_detect$4[0:0]$11520 1'0
+ assign $1\wr_detect$4[0:0]$11428 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11519
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11427
end
- attribute \src "libresoc.v:180341.3-180380.6"
- process $proc$libresoc.v:180341$11524
+ attribute \src "libresoc.v:178094.3-178133.6"
+ process $proc$libresoc.v:178094$11432
assign { } { }
assign { } { }
assign { } { }
- assign $0\src35__data_o$next[3:0]$11525 $6\src35__data_o$next[3:0]$11531
- attribute \src "libresoc.v:180342.5-180342.29"
+ assign $0\src35__data_o$next[3:0]$11433 $6\src35__data_o$next[3:0]$11439
+ attribute \src "libresoc.v:178095.5-178095.29"
switch \initial
- attribute \src "libresoc.v:180342.9-180342.17"
+ attribute \src "libresoc.v:178095.9-178095.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src35__data_o$next[3:0]$11526 $5\src35__data_o$next[3:0]$11530
+ assign $1\src35__data_o$next[3:0]$11434 $5\src35__data_o$next[3:0]$11438
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src35__data_o$next[3:0]$11527 \dest15__data_i
+ assign $2\src35__data_o$next[3:0]$11435 \dest15__data_i
case
- assign $2\src35__data_o$next[3:0]$11527 4'0000
+ assign $2\src35__data_o$next[3:0]$11435 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src35__data_o$next[3:0]$11528 \dest25__data_i
+ assign $3\src35__data_o$next[3:0]$11436 \dest25__data_i
case
- assign $3\src35__data_o$next[3:0]$11528 $2\src35__data_o$next[3:0]$11527
+ assign $3\src35__data_o$next[3:0]$11436 $2\src35__data_o$next[3:0]$11435
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src35__data_o$next[3:0]$11529 \w5__data_i
+ assign $4\src35__data_o$next[3:0]$11437 \w5__data_i
case
- assign $4\src35__data_o$next[3:0]$11529 $3\src35__data_o$next[3:0]$11528
+ assign $4\src35__data_o$next[3:0]$11437 $3\src35__data_o$next[3:0]$11436
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src35__data_o$next[3:0]$11530 \reg
+ assign $5\src35__data_o$next[3:0]$11438 \reg
case
- assign $5\src35__data_o$next[3:0]$11530 $4\src35__data_o$next[3:0]$11529
+ assign $5\src35__data_o$next[3:0]$11438 $4\src35__data_o$next[3:0]$11437
end
case
- assign $1\src35__data_o$next[3:0]$11526 4'0000
+ assign $1\src35__data_o$next[3:0]$11434 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src35__data_o$next[3:0]$11531 4'0000
+ assign $6\src35__data_o$next[3:0]$11439 4'0000
case
- assign $6\src35__data_o$next[3:0]$11531 $1\src35__data_o$next[3:0]$11526
+ assign $6\src35__data_o$next[3:0]$11439 $1\src35__data_o$next[3:0]$11434
end
sync always
- update \src35__data_o$next $0\src35__data_o$next[3:0]$11525
+ update \src35__data_o$next $0\src35__data_o$next[3:0]$11433
end
- attribute \src "libresoc.v:180381.3-180410.6"
- process $proc$libresoc.v:180381$11532
+ attribute \src "libresoc.v:178134.3-178163.6"
+ process $proc$libresoc.v:178134$11440
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11533 $1\wr_detect$7[0:0]$11534
- attribute \src "libresoc.v:180382.5-180382.29"
+ assign $0\wr_detect$7[0:0]$11441 $1\wr_detect$7[0:0]$11442
+ attribute \src "libresoc.v:178135.5-178135.29"
switch \initial
- attribute \src "libresoc.v:180382.9-180382.17"
+ attribute \src "libresoc.v:178135.9-178135.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11534 $4\wr_detect$7[0:0]$11537
+ assign $1\wr_detect$7[0:0]$11442 $4\wr_detect$7[0:0]$11445
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11535 1'1
+ assign $2\wr_detect$7[0:0]$11443 1'1
case
- assign $2\wr_detect$7[0:0]$11535 1'0
+ assign $2\wr_detect$7[0:0]$11443 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11536 1'1
+ assign $3\wr_detect$7[0:0]$11444 1'1
case
- assign $3\wr_detect$7[0:0]$11536 $2\wr_detect$7[0:0]$11535
+ assign $3\wr_detect$7[0:0]$11444 $2\wr_detect$7[0:0]$11443
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11537 1'1
+ assign $4\wr_detect$7[0:0]$11445 1'1
case
- assign $4\wr_detect$7[0:0]$11537 $3\wr_detect$7[0:0]$11536
+ assign $4\wr_detect$7[0:0]$11445 $3\wr_detect$7[0:0]$11444
end
case
- assign $1\wr_detect$7[0:0]$11534 1'0
+ assign $1\wr_detect$7[0:0]$11442 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11533
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11441
end
- attribute \src "libresoc.v:180411.3-180450.6"
- process $proc$libresoc.v:180411$11538
+ attribute \src "libresoc.v:178164.3-178203.6"
+ process $proc$libresoc.v:178164$11446
assign { } { }
assign { } { }
assign { } { }
- assign $0\r5__data_o$next[3:0]$11539 $6\r5__data_o$next[3:0]$11545
- attribute \src "libresoc.v:180412.5-180412.29"
+ assign $0\r5__data_o$next[3:0]$11447 $6\r5__data_o$next[3:0]$11453
+ attribute \src "libresoc.v:178165.5-178165.29"
switch \initial
- attribute \src "libresoc.v:180412.9-180412.17"
+ attribute \src "libresoc.v:178165.9-178165.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r5__data_o$next[3:0]$11540 $5\r5__data_o$next[3:0]$11544
+ assign $1\r5__data_o$next[3:0]$11448 $5\r5__data_o$next[3:0]$11452
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r5__data_o$next[3:0]$11541 \dest15__data_i
+ assign $2\r5__data_o$next[3:0]$11449 \dest15__data_i
case
- assign $2\r5__data_o$next[3:0]$11541 4'0000
+ assign $2\r5__data_o$next[3:0]$11449 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r5__data_o$next[3:0]$11542 \dest25__data_i
+ assign $3\r5__data_o$next[3:0]$11450 \dest25__data_i
case
- assign $3\r5__data_o$next[3:0]$11542 $2\r5__data_o$next[3:0]$11541
+ assign $3\r5__data_o$next[3:0]$11450 $2\r5__data_o$next[3:0]$11449
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r5__data_o$next[3:0]$11543 \w5__data_i
+ assign $4\r5__data_o$next[3:0]$11451 \w5__data_i
case
- assign $4\r5__data_o$next[3:0]$11543 $3\r5__data_o$next[3:0]$11542
+ assign $4\r5__data_o$next[3:0]$11451 $3\r5__data_o$next[3:0]$11450
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r5__data_o$next[3:0]$11544 \reg
+ assign $5\r5__data_o$next[3:0]$11452 \reg
case
- assign $5\r5__data_o$next[3:0]$11544 $4\r5__data_o$next[3:0]$11543
+ assign $5\r5__data_o$next[3:0]$11452 $4\r5__data_o$next[3:0]$11451
end
case
- assign $1\r5__data_o$next[3:0]$11540 4'0000
+ assign $1\r5__data_o$next[3:0]$11448 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r5__data_o$next[3:0]$11545 4'0000
+ assign $6\r5__data_o$next[3:0]$11453 4'0000
case
- assign $6\r5__data_o$next[3:0]$11545 $1\r5__data_o$next[3:0]$11540
+ assign $6\r5__data_o$next[3:0]$11453 $1\r5__data_o$next[3:0]$11448
end
sync always
- update \r5__data_o$next $0\r5__data_o$next[3:0]$11539
+ update \r5__data_o$next $0\r5__data_o$next[3:0]$11447
end
- attribute \src "libresoc.v:180451.3-180480.6"
- process $proc$libresoc.v:180451$11546
+ attribute \src "libresoc.v:178204.3-178233.6"
+ process $proc$libresoc.v:178204$11454
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11547 $1\wr_detect$10[0:0]$11548
- attribute \src "libresoc.v:180452.5-180452.29"
+ assign $0\wr_detect$10[0:0]$11455 $1\wr_detect$10[0:0]$11456
+ attribute \src "libresoc.v:178205.5-178205.29"
switch \initial
- attribute \src "libresoc.v:180452.9-180452.17"
+ attribute \src "libresoc.v:178205.9-178205.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11548 $4\wr_detect$10[0:0]$11551
+ assign $1\wr_detect$10[0:0]$11456 $4\wr_detect$10[0:0]$11459
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11549 1'1
+ assign $2\wr_detect$10[0:0]$11457 1'1
case
- assign $2\wr_detect$10[0:0]$11549 1'0
+ assign $2\wr_detect$10[0:0]$11457 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11550 1'1
+ assign $3\wr_detect$10[0:0]$11458 1'1
case
- assign $3\wr_detect$10[0:0]$11550 $2\wr_detect$10[0:0]$11549
+ assign $3\wr_detect$10[0:0]$11458 $2\wr_detect$10[0:0]$11457
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11551 1'1
+ assign $4\wr_detect$10[0:0]$11459 1'1
case
- assign $4\wr_detect$10[0:0]$11551 $3\wr_detect$10[0:0]$11550
+ assign $4\wr_detect$10[0:0]$11459 $3\wr_detect$10[0:0]$11458
end
case
- assign $1\wr_detect$10[0:0]$11548 1'0
+ assign $1\wr_detect$10[0:0]$11456 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11547
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11455
end
- attribute \src "libresoc.v:180481.3-180520.6"
- process $proc$libresoc.v:180481$11552
+ attribute \src "libresoc.v:178234.3-178273.6"
+ process $proc$libresoc.v:178234$11460
assign { } { }
assign { } { }
assign { } { }
- assign $0\r25__data_o$next[3:0]$11553 $6\r25__data_o$next[3:0]$11559
- attribute \src "libresoc.v:180482.5-180482.29"
+ assign $0\r25__data_o$next[3:0]$11461 $6\r25__data_o$next[3:0]$11467
+ attribute \src "libresoc.v:178235.5-178235.29"
switch \initial
- attribute \src "libresoc.v:180482.9-180482.17"
+ attribute \src "libresoc.v:178235.9-178235.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r25__data_o$next[3:0]$11554 $5\r25__data_o$next[3:0]$11558
+ assign $1\r25__data_o$next[3:0]$11462 $5\r25__data_o$next[3:0]$11466
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r25__data_o$next[3:0]$11555 \dest15__data_i
+ assign $2\r25__data_o$next[3:0]$11463 \dest15__data_i
case
- assign $2\r25__data_o$next[3:0]$11555 4'0000
+ assign $2\r25__data_o$next[3:0]$11463 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r25__data_o$next[3:0]$11556 \dest25__data_i
+ assign $3\r25__data_o$next[3:0]$11464 \dest25__data_i
case
- assign $3\r25__data_o$next[3:0]$11556 $2\r25__data_o$next[3:0]$11555
+ assign $3\r25__data_o$next[3:0]$11464 $2\r25__data_o$next[3:0]$11463
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r25__data_o$next[3:0]$11557 \w5__data_i
+ assign $4\r25__data_o$next[3:0]$11465 \w5__data_i
case
- assign $4\r25__data_o$next[3:0]$11557 $3\r25__data_o$next[3:0]$11556
+ assign $4\r25__data_o$next[3:0]$11465 $3\r25__data_o$next[3:0]$11464
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r25__data_o$next[3:0]$11558 \reg
+ assign $5\r25__data_o$next[3:0]$11466 \reg
case
- assign $5\r25__data_o$next[3:0]$11558 $4\r25__data_o$next[3:0]$11557
+ assign $5\r25__data_o$next[3:0]$11466 $4\r25__data_o$next[3:0]$11465
end
case
- assign $1\r25__data_o$next[3:0]$11554 4'0000
+ assign $1\r25__data_o$next[3:0]$11462 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r25__data_o$next[3:0]$11559 4'0000
+ assign $6\r25__data_o$next[3:0]$11467 4'0000
case
- assign $6\r25__data_o$next[3:0]$11559 $1\r25__data_o$next[3:0]$11554
+ assign $6\r25__data_o$next[3:0]$11467 $1\r25__data_o$next[3:0]$11462
end
sync always
- update \r25__data_o$next $0\r25__data_o$next[3:0]$11553
+ update \r25__data_o$next $0\r25__data_o$next[3:0]$11461
end
- attribute \src "libresoc.v:180521.3-180550.6"
- process $proc$libresoc.v:180521$11560
+ attribute \src "libresoc.v:178274.3-178303.6"
+ process $proc$libresoc.v:178274$11468
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11561 $1\wr_detect$13[0:0]$11562
- attribute \src "libresoc.v:180522.5-180522.29"
+ assign $0\wr_detect$13[0:0]$11469 $1\wr_detect$13[0:0]$11470
+ attribute \src "libresoc.v:178275.5-178275.29"
switch \initial
- attribute \src "libresoc.v:180522.9-180522.17"
+ attribute \src "libresoc.v:178275.9-178275.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11562 $4\wr_detect$13[0:0]$11565
+ assign $1\wr_detect$13[0:0]$11470 $4\wr_detect$13[0:0]$11473
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest15__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11563 1'1
+ assign $2\wr_detect$13[0:0]$11471 1'1
case
- assign $2\wr_detect$13[0:0]$11563 1'0
+ assign $2\wr_detect$13[0:0]$11471 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest25__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11564 1'1
+ assign $3\wr_detect$13[0:0]$11472 1'1
case
- assign $3\wr_detect$13[0:0]$11564 $2\wr_detect$13[0:0]$11563
+ assign $3\wr_detect$13[0:0]$11472 $2\wr_detect$13[0:0]$11471
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w5__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11565 1'1
+ assign $4\wr_detect$13[0:0]$11473 1'1
case
- assign $4\wr_detect$13[0:0]$11565 $3\wr_detect$13[0:0]$11564
+ assign $4\wr_detect$13[0:0]$11473 $3\wr_detect$13[0:0]$11472
end
case
- assign $1\wr_detect$13[0:0]$11562 1'0
+ assign $1\wr_detect$13[0:0]$11470 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11561
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11469
end
- connect \$9 $not$libresoc.v:180157$11484_Y
- connect \$12 $not$libresoc.v:180158$11485_Y
- connect \$1 $not$libresoc.v:180159$11486_Y
- connect \$3 $not$libresoc.v:180160$11487_Y
- connect \$6 $not$libresoc.v:180161$11488_Y
+ connect \$9 $not$libresoc.v:177910$11392_Y
+ connect \$12 $not$libresoc.v:177911$11393_Y
+ connect \$1 $not$libresoc.v:177912$11394_Y
+ connect \$3 $not$libresoc.v:177913$11395_Y
+ connect \$6 $not$libresoc.v:177914$11396_Y
end
-attribute \src "libresoc.v:180555.1-181026.10"
+attribute \src "libresoc.v:178308.1-178779.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6"
attribute \generator "nMigen"
module \reg_6
- attribute \src "libresoc.v:180556.7-180556.20"
+ attribute \src "libresoc.v:178309.7-178309.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $0\r26__data_o$next[3:0]$11642
- attribute \src "libresoc.v:180639.3-180640.39"
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $0\r26__data_o$next[3:0]$11550
+ attribute \src "libresoc.v:178392.3-178393.39"
wire width 4 $0\r26__data_o[3:0]
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $0\r6__data_o$next[3:0]$11628
- attribute \src "libresoc.v:180641.3-180642.37"
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $0\r6__data_o$next[3:0]$11536
+ attribute \src "libresoc.v:178394.3-178395.37"
wire width 4 $0\r6__data_o[3:0]
- attribute \src "libresoc.v:180719.3-180745.6"
- wire width 4 $0\reg$next[3:0]$11594
- attribute \src "libresoc.v:180637.3-180638.25"
+ attribute \src "libresoc.v:178472.3-178498.6"
+ wire width 4 $0\reg$next[3:0]$11502
+ attribute \src "libresoc.v:178390.3-178391.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $0\src16__data_o$next[3:0]$11585
- attribute \src "libresoc.v:180647.3-180648.43"
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $0\src16__data_o$next[3:0]$11493
+ attribute \src "libresoc.v:178400.3-178401.43"
wire width 4 $0\src16__data_o[3:0]
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $0\src26__data_o$next[3:0]$11600
- attribute \src "libresoc.v:180645.3-180646.43"
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $0\src26__data_o$next[3:0]$11508
+ attribute \src "libresoc.v:178398.3-178399.43"
wire width 4 $0\src26__data_o[3:0]
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $0\src36__data_o$next[3:0]$11614
- attribute \src "libresoc.v:180643.3-180644.43"
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $0\src36__data_o$next[3:0]$11522
+ attribute \src "libresoc.v:178396.3-178397.43"
wire width 4 $0\src36__data_o[3:0]
- attribute \src "libresoc.v:180926.3-180955.6"
- wire $0\wr_detect$10[0:0]$11636
- attribute \src "libresoc.v:180996.3-181025.6"
- wire $0\wr_detect$13[0:0]$11650
- attribute \src "libresoc.v:180786.3-180815.6"
- wire $0\wr_detect$4[0:0]$11608
- attribute \src "libresoc.v:180856.3-180885.6"
- wire $0\wr_detect$7[0:0]$11622
- attribute \src "libresoc.v:180689.3-180718.6"
+ attribute \src "libresoc.v:178679.3-178708.6"
+ wire $0\wr_detect$10[0:0]$11544
+ attribute \src "libresoc.v:178749.3-178778.6"
+ wire $0\wr_detect$13[0:0]$11558
+ attribute \src "libresoc.v:178539.3-178568.6"
+ wire $0\wr_detect$4[0:0]$11516
+ attribute \src "libresoc.v:178609.3-178638.6"
+ wire $0\wr_detect$7[0:0]$11530
+ attribute \src "libresoc.v:178442.3-178471.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $1\r26__data_o$next[3:0]$11643
- attribute \src "libresoc.v:180581.13-180581.31"
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $1\r26__data_o$next[3:0]$11551
+ attribute \src "libresoc.v:178334.13-178334.31"
wire width 4 $1\r26__data_o[3:0]
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $1\r6__data_o$next[3:0]$11629
- attribute \src "libresoc.v:180588.13-180588.30"
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $1\r6__data_o$next[3:0]$11537
+ attribute \src "libresoc.v:178341.13-178341.30"
wire width 4 $1\r6__data_o[3:0]
- attribute \src "libresoc.v:180719.3-180745.6"
- wire width 4 $1\reg$next[3:0]$11595
- attribute \src "libresoc.v:180594.13-180594.25"
+ attribute \src "libresoc.v:178472.3-178498.6"
+ wire width 4 $1\reg$next[3:0]$11503
+ attribute \src "libresoc.v:178347.13-178347.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $1\src16__data_o$next[3:0]$11586
- attribute \src "libresoc.v:180599.13-180599.33"
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $1\src16__data_o$next[3:0]$11494
+ attribute \src "libresoc.v:178352.13-178352.33"
wire width 4 $1\src16__data_o[3:0]
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $1\src26__data_o$next[3:0]$11601
- attribute \src "libresoc.v:180606.13-180606.33"
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $1\src26__data_o$next[3:0]$11509
+ attribute \src "libresoc.v:178359.13-178359.33"
wire width 4 $1\src26__data_o[3:0]
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $1\src36__data_o$next[3:0]$11615
- attribute \src "libresoc.v:180613.13-180613.33"
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $1\src36__data_o$next[3:0]$11523
+ attribute \src "libresoc.v:178366.13-178366.33"
wire width 4 $1\src36__data_o[3:0]
- attribute \src "libresoc.v:180926.3-180955.6"
- wire $1\wr_detect$10[0:0]$11637
- attribute \src "libresoc.v:180996.3-181025.6"
- wire $1\wr_detect$13[0:0]$11651
- attribute \src "libresoc.v:180786.3-180815.6"
- wire $1\wr_detect$4[0:0]$11609
- attribute \src "libresoc.v:180856.3-180885.6"
- wire $1\wr_detect$7[0:0]$11623
- attribute \src "libresoc.v:180689.3-180718.6"
+ attribute \src "libresoc.v:178679.3-178708.6"
+ wire $1\wr_detect$10[0:0]$11545
+ attribute \src "libresoc.v:178749.3-178778.6"
+ wire $1\wr_detect$13[0:0]$11559
+ attribute \src "libresoc.v:178539.3-178568.6"
+ wire $1\wr_detect$4[0:0]$11517
+ attribute \src "libresoc.v:178609.3-178638.6"
+ wire $1\wr_detect$7[0:0]$11531
+ attribute \src "libresoc.v:178442.3-178471.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $2\r26__data_o$next[3:0]$11644
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $2\r6__data_o$next[3:0]$11630
- attribute \src "libresoc.v:180719.3-180745.6"
- wire width 4 $2\reg$next[3:0]$11596
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $2\src16__data_o$next[3:0]$11587
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $2\src26__data_o$next[3:0]$11602
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $2\src36__data_o$next[3:0]$11616
- attribute \src "libresoc.v:180926.3-180955.6"
- wire $2\wr_detect$10[0:0]$11638
- attribute \src "libresoc.v:180996.3-181025.6"
- wire $2\wr_detect$13[0:0]$11652
- attribute \src "libresoc.v:180786.3-180815.6"
- wire $2\wr_detect$4[0:0]$11610
- attribute \src "libresoc.v:180856.3-180885.6"
- wire $2\wr_detect$7[0:0]$11624
- attribute \src "libresoc.v:180689.3-180718.6"
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $2\r26__data_o$next[3:0]$11552
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $2\r6__data_o$next[3:0]$11538
+ attribute \src "libresoc.v:178472.3-178498.6"
+ wire width 4 $2\reg$next[3:0]$11504
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $2\src16__data_o$next[3:0]$11495
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $2\src26__data_o$next[3:0]$11510
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $2\src36__data_o$next[3:0]$11524
+ attribute \src "libresoc.v:178679.3-178708.6"
+ wire $2\wr_detect$10[0:0]$11546
+ attribute \src "libresoc.v:178749.3-178778.6"
+ wire $2\wr_detect$13[0:0]$11560
+ attribute \src "libresoc.v:178539.3-178568.6"
+ wire $2\wr_detect$4[0:0]$11518
+ attribute \src "libresoc.v:178609.3-178638.6"
+ wire $2\wr_detect$7[0:0]$11532
+ attribute \src "libresoc.v:178442.3-178471.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $3\r26__data_o$next[3:0]$11645
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $3\r6__data_o$next[3:0]$11631
- attribute \src "libresoc.v:180719.3-180745.6"
- wire width 4 $3\reg$next[3:0]$11597
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $3\src16__data_o$next[3:0]$11588
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $3\src26__data_o$next[3:0]$11603
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $3\src36__data_o$next[3:0]$11617
- attribute \src "libresoc.v:180926.3-180955.6"
- wire $3\wr_detect$10[0:0]$11639
- attribute \src "libresoc.v:180996.3-181025.6"
- wire $3\wr_detect$13[0:0]$11653
- attribute \src "libresoc.v:180786.3-180815.6"
- wire $3\wr_detect$4[0:0]$11611
- attribute \src "libresoc.v:180856.3-180885.6"
- wire $3\wr_detect$7[0:0]$11625
- attribute \src "libresoc.v:180689.3-180718.6"
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $3\r26__data_o$next[3:0]$11553
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $3\r6__data_o$next[3:0]$11539
+ attribute \src "libresoc.v:178472.3-178498.6"
+ wire width 4 $3\reg$next[3:0]$11505
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $3\src16__data_o$next[3:0]$11496
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $3\src26__data_o$next[3:0]$11511
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $3\src36__data_o$next[3:0]$11525
+ attribute \src "libresoc.v:178679.3-178708.6"
+ wire $3\wr_detect$10[0:0]$11547
+ attribute \src "libresoc.v:178749.3-178778.6"
+ wire $3\wr_detect$13[0:0]$11561
+ attribute \src "libresoc.v:178539.3-178568.6"
+ wire $3\wr_detect$4[0:0]$11519
+ attribute \src "libresoc.v:178609.3-178638.6"
+ wire $3\wr_detect$7[0:0]$11533
+ attribute \src "libresoc.v:178442.3-178471.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $4\r26__data_o$next[3:0]$11646
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $4\r6__data_o$next[3:0]$11632
- attribute \src "libresoc.v:180719.3-180745.6"
- wire width 4 $4\reg$next[3:0]$11598
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $4\src16__data_o$next[3:0]$11589
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $4\src26__data_o$next[3:0]$11604
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $4\src36__data_o$next[3:0]$11618
- attribute \src "libresoc.v:180926.3-180955.6"
- wire $4\wr_detect$10[0:0]$11640
- attribute \src "libresoc.v:180996.3-181025.6"
- wire $4\wr_detect$13[0:0]$11654
- attribute \src "libresoc.v:180786.3-180815.6"
- wire $4\wr_detect$4[0:0]$11612
- attribute \src "libresoc.v:180856.3-180885.6"
- wire $4\wr_detect$7[0:0]$11626
- attribute \src "libresoc.v:180689.3-180718.6"
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $4\r26__data_o$next[3:0]$11554
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $4\r6__data_o$next[3:0]$11540
+ attribute \src "libresoc.v:178472.3-178498.6"
+ wire width 4 $4\reg$next[3:0]$11506
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $4\src16__data_o$next[3:0]$11497
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $4\src26__data_o$next[3:0]$11512
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $4\src36__data_o$next[3:0]$11526
+ attribute \src "libresoc.v:178679.3-178708.6"
+ wire $4\wr_detect$10[0:0]$11548
+ attribute \src "libresoc.v:178749.3-178778.6"
+ wire $4\wr_detect$13[0:0]$11562
+ attribute \src "libresoc.v:178539.3-178568.6"
+ wire $4\wr_detect$4[0:0]$11520
+ attribute \src "libresoc.v:178609.3-178638.6"
+ wire $4\wr_detect$7[0:0]$11534
+ attribute \src "libresoc.v:178442.3-178471.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $5\r26__data_o$next[3:0]$11647
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $5\r6__data_o$next[3:0]$11633
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $5\src16__data_o$next[3:0]$11590
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $5\src26__data_o$next[3:0]$11605
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $5\src36__data_o$next[3:0]$11619
- attribute \src "libresoc.v:180956.3-180995.6"
- wire width 4 $6\r26__data_o$next[3:0]$11648
- attribute \src "libresoc.v:180886.3-180925.6"
- wire width 4 $6\r6__data_o$next[3:0]$11634
- attribute \src "libresoc.v:180649.3-180688.6"
- wire width 4 $6\src16__data_o$next[3:0]$11591
- attribute \src "libresoc.v:180746.3-180785.6"
- wire width 4 $6\src26__data_o$next[3:0]$11606
- attribute \src "libresoc.v:180816.3-180855.6"
- wire width 4 $6\src36__data_o$next[3:0]$11620
- attribute \src "libresoc.v:180632.17-180632.104"
- wire $not$libresoc.v:180632$11573_Y
- attribute \src "libresoc.v:180633.18-180633.105"
- wire $not$libresoc.v:180633$11574_Y
- attribute \src "libresoc.v:180634.17-180634.100"
- wire $not$libresoc.v:180634$11575_Y
- attribute \src "libresoc.v:180635.17-180635.103"
- wire $not$libresoc.v:180635$11576_Y
- attribute \src "libresoc.v:180636.17-180636.103"
- wire $not$libresoc.v:180636$11577_Y
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $5\r26__data_o$next[3:0]$11555
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $5\r6__data_o$next[3:0]$11541
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $5\src16__data_o$next[3:0]$11498
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $5\src26__data_o$next[3:0]$11513
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $5\src36__data_o$next[3:0]$11527
+ attribute \src "libresoc.v:178709.3-178748.6"
+ wire width 4 $6\r26__data_o$next[3:0]$11556
+ attribute \src "libresoc.v:178639.3-178678.6"
+ wire width 4 $6\r6__data_o$next[3:0]$11542
+ attribute \src "libresoc.v:178402.3-178441.6"
+ wire width 4 $6\src16__data_o$next[3:0]$11499
+ attribute \src "libresoc.v:178499.3-178538.6"
+ wire width 4 $6\src26__data_o$next[3:0]$11514
+ attribute \src "libresoc.v:178569.3-178608.6"
+ wire width 4 $6\src36__data_o$next[3:0]$11528
+ attribute \src "libresoc.v:178385.17-178385.104"
+ wire $not$libresoc.v:178385$11481_Y
+ attribute \src "libresoc.v:178386.18-178386.105"
+ wire $not$libresoc.v:178386$11482_Y
+ attribute \src "libresoc.v:178387.17-178387.100"
+ wire $not$libresoc.v:178387$11483_Y
+ attribute \src "libresoc.v:178388.17-178388.103"
+ wire $not$libresoc.v:178388$11484_Y
+ attribute \src "libresoc.v:178389.17-178389.103"
+ wire $not$libresoc.v:178389$11485_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest16__data_i
wire width 4 input 11 \dest26__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest26__wen
- attribute \src "libresoc.v:180556.7-180556.15"
+ attribute \src "libresoc.v:178309.7-178309.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r26__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180632$11573
+ cell $not $not$libresoc.v:178385$11481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:180632$11573_Y
+ connect \Y $not$libresoc.v:178385$11481_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180633$11574
+ cell $not $not$libresoc.v:178386$11482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:180633$11574_Y
+ connect \Y $not$libresoc.v:178386$11482_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180634$11575
+ cell $not $not$libresoc.v:178387$11483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:180634$11575_Y
+ connect \Y $not$libresoc.v:178387$11483_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180635$11576
+ cell $not $not$libresoc.v:178388$11484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:180635$11576_Y
+ connect \Y $not$libresoc.v:178388$11484_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:180636$11577
+ cell $not $not$libresoc.v:178389$11485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:180636$11577_Y
+ connect \Y $not$libresoc.v:178389$11485_Y
end
- attribute \src "libresoc.v:180556.7-180556.20"
- process $proc$libresoc.v:180556$11655
+ attribute \src "libresoc.v:178309.7-178309.20"
+ process $proc$libresoc.v:178309$11563
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:180581.13-180581.31"
- process $proc$libresoc.v:180581$11656
+ attribute \src "libresoc.v:178334.13-178334.31"
+ process $proc$libresoc.v:178334$11564
assign { } { }
assign $1\r26__data_o[3:0] 4'0000
sync always
sync init
update \r26__data_o $1\r26__data_o[3:0]
end
- attribute \src "libresoc.v:180588.13-180588.30"
- process $proc$libresoc.v:180588$11657
+ attribute \src "libresoc.v:178341.13-178341.30"
+ process $proc$libresoc.v:178341$11565
assign { } { }
assign $1\r6__data_o[3:0] 4'0000
sync always
sync init
update \r6__data_o $1\r6__data_o[3:0]
end
- attribute \src "libresoc.v:180594.13-180594.25"
- process $proc$libresoc.v:180594$11658
+ attribute \src "libresoc.v:178347.13-178347.25"
+ process $proc$libresoc.v:178347$11566
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:180599.13-180599.33"
- process $proc$libresoc.v:180599$11659
+ attribute \src "libresoc.v:178352.13-178352.33"
+ process $proc$libresoc.v:178352$11567
assign { } { }
assign $1\src16__data_o[3:0] 4'0000
sync always
sync init
update \src16__data_o $1\src16__data_o[3:0]
end
- attribute \src "libresoc.v:180606.13-180606.33"
- process $proc$libresoc.v:180606$11660
+ attribute \src "libresoc.v:178359.13-178359.33"
+ process $proc$libresoc.v:178359$11568
assign { } { }
assign $1\src26__data_o[3:0] 4'0000
sync always
sync init
update \src26__data_o $1\src26__data_o[3:0]
end
- attribute \src "libresoc.v:180613.13-180613.33"
- process $proc$libresoc.v:180613$11661
+ attribute \src "libresoc.v:178366.13-178366.33"
+ process $proc$libresoc.v:178366$11569
assign { } { }
assign $1\src36__data_o[3:0] 4'0000
sync always
sync init
update \src36__data_o $1\src36__data_o[3:0]
end
- attribute \src "libresoc.v:180637.3-180638.25"
- process $proc$libresoc.v:180637$11578
+ attribute \src "libresoc.v:178390.3-178391.25"
+ process $proc$libresoc.v:178390$11486
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:180639.3-180640.39"
- process $proc$libresoc.v:180639$11579
+ attribute \src "libresoc.v:178392.3-178393.39"
+ process $proc$libresoc.v:178392$11487
assign { } { }
assign $0\r26__data_o[3:0] \r26__data_o$next
sync posedge \coresync_clk
update \r26__data_o $0\r26__data_o[3:0]
end
- attribute \src "libresoc.v:180641.3-180642.37"
- process $proc$libresoc.v:180641$11580
+ attribute \src "libresoc.v:178394.3-178395.37"
+ process $proc$libresoc.v:178394$11488
assign { } { }
assign $0\r6__data_o[3:0] \r6__data_o$next
sync posedge \coresync_clk
update \r6__data_o $0\r6__data_o[3:0]
end
- attribute \src "libresoc.v:180643.3-180644.43"
- process $proc$libresoc.v:180643$11581
+ attribute \src "libresoc.v:178396.3-178397.43"
+ process $proc$libresoc.v:178396$11489
assign { } { }
assign $0\src36__data_o[3:0] \src36__data_o$next
sync posedge \coresync_clk
update \src36__data_o $0\src36__data_o[3:0]
end
- attribute \src "libresoc.v:180645.3-180646.43"
- process $proc$libresoc.v:180645$11582
+ attribute \src "libresoc.v:178398.3-178399.43"
+ process $proc$libresoc.v:178398$11490
assign { } { }
assign $0\src26__data_o[3:0] \src26__data_o$next
sync posedge \coresync_clk
update \src26__data_o $0\src26__data_o[3:0]
end
- attribute \src "libresoc.v:180647.3-180648.43"
- process $proc$libresoc.v:180647$11583
+ attribute \src "libresoc.v:178400.3-178401.43"
+ process $proc$libresoc.v:178400$11491
assign { } { }
assign $0\src16__data_o[3:0] \src16__data_o$next
sync posedge \coresync_clk
update \src16__data_o $0\src16__data_o[3:0]
end
- attribute \src "libresoc.v:180649.3-180688.6"
- process $proc$libresoc.v:180649$11584
+ attribute \src "libresoc.v:178402.3-178441.6"
+ process $proc$libresoc.v:178402$11492
assign { } { }
assign { } { }
assign { } { }
- assign $0\src16__data_o$next[3:0]$11585 $6\src16__data_o$next[3:0]$11591
- attribute \src "libresoc.v:180650.5-180650.29"
+ assign $0\src16__data_o$next[3:0]$11493 $6\src16__data_o$next[3:0]$11499
+ attribute \src "libresoc.v:178403.5-178403.29"
switch \initial
- attribute \src "libresoc.v:180650.9-180650.17"
+ attribute \src "libresoc.v:178403.9-178403.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src16__data_o$next[3:0]$11586 $5\src16__data_o$next[3:0]$11590
+ assign $1\src16__data_o$next[3:0]$11494 $5\src16__data_o$next[3:0]$11498
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src16__data_o$next[3:0]$11587 \dest16__data_i
+ assign $2\src16__data_o$next[3:0]$11495 \dest16__data_i
case
- assign $2\src16__data_o$next[3:0]$11587 4'0000
+ assign $2\src16__data_o$next[3:0]$11495 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src16__data_o$next[3:0]$11588 \dest26__data_i
+ assign $3\src16__data_o$next[3:0]$11496 \dest26__data_i
case
- assign $3\src16__data_o$next[3:0]$11588 $2\src16__data_o$next[3:0]$11587
+ assign $3\src16__data_o$next[3:0]$11496 $2\src16__data_o$next[3:0]$11495
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src16__data_o$next[3:0]$11589 \w6__data_i
+ assign $4\src16__data_o$next[3:0]$11497 \w6__data_i
case
- assign $4\src16__data_o$next[3:0]$11589 $3\src16__data_o$next[3:0]$11588
+ assign $4\src16__data_o$next[3:0]$11497 $3\src16__data_o$next[3:0]$11496
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src16__data_o$next[3:0]$11590 \reg
+ assign $5\src16__data_o$next[3:0]$11498 \reg
case
- assign $5\src16__data_o$next[3:0]$11590 $4\src16__data_o$next[3:0]$11589
+ assign $5\src16__data_o$next[3:0]$11498 $4\src16__data_o$next[3:0]$11497
end
case
- assign $1\src16__data_o$next[3:0]$11586 4'0000
+ assign $1\src16__data_o$next[3:0]$11494 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src16__data_o$next[3:0]$11591 4'0000
+ assign $6\src16__data_o$next[3:0]$11499 4'0000
case
- assign $6\src16__data_o$next[3:0]$11591 $1\src16__data_o$next[3:0]$11586
+ assign $6\src16__data_o$next[3:0]$11499 $1\src16__data_o$next[3:0]$11494
end
sync always
- update \src16__data_o$next $0\src16__data_o$next[3:0]$11585
+ update \src16__data_o$next $0\src16__data_o$next[3:0]$11493
end
- attribute \src "libresoc.v:180689.3-180718.6"
- process $proc$libresoc.v:180689$11592
+ attribute \src "libresoc.v:178442.3-178471.6"
+ process $proc$libresoc.v:178442$11500
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:180690.5-180690.29"
+ attribute \src "libresoc.v:178443.5-178443.29"
switch \initial
- attribute \src "libresoc.v:180690.9-180690.17"
+ attribute \src "libresoc.v:178443.9-178443.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:180719.3-180745.6"
- process $proc$libresoc.v:180719$11593
+ attribute \src "libresoc.v:178472.3-178498.6"
+ process $proc$libresoc.v:178472$11501
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11594 $4\reg$next[3:0]$11598
- attribute \src "libresoc.v:180720.5-180720.29"
+ assign $0\reg$next[3:0]$11502 $4\reg$next[3:0]$11506
+ attribute \src "libresoc.v:178473.5-178473.29"
switch \initial
- attribute \src "libresoc.v:180720.9-180720.17"
+ attribute \src "libresoc.v:178473.9-178473.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11595 \dest16__data_i
+ assign $1\reg$next[3:0]$11503 \dest16__data_i
case
- assign $1\reg$next[3:0]$11595 \reg
+ assign $1\reg$next[3:0]$11503 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11596 \dest26__data_i
+ assign $2\reg$next[3:0]$11504 \dest26__data_i
case
- assign $2\reg$next[3:0]$11596 $1\reg$next[3:0]$11595
+ assign $2\reg$next[3:0]$11504 $1\reg$next[3:0]$11503
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11597 \w6__data_i
+ assign $3\reg$next[3:0]$11505 \w6__data_i
case
- assign $3\reg$next[3:0]$11597 $2\reg$next[3:0]$11596
+ assign $3\reg$next[3:0]$11505 $2\reg$next[3:0]$11504
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11598 4'0000
+ assign $4\reg$next[3:0]$11506 4'0000
case
- assign $4\reg$next[3:0]$11598 $3\reg$next[3:0]$11597
+ assign $4\reg$next[3:0]$11506 $3\reg$next[3:0]$11505
end
sync always
- update \reg$next $0\reg$next[3:0]$11594
+ update \reg$next $0\reg$next[3:0]$11502
end
- attribute \src "libresoc.v:180746.3-180785.6"
- process $proc$libresoc.v:180746$11599
+ attribute \src "libresoc.v:178499.3-178538.6"
+ process $proc$libresoc.v:178499$11507
assign { } { }
assign { } { }
assign { } { }
- assign $0\src26__data_o$next[3:0]$11600 $6\src26__data_o$next[3:0]$11606
- attribute \src "libresoc.v:180747.5-180747.29"
+ assign $0\src26__data_o$next[3:0]$11508 $6\src26__data_o$next[3:0]$11514
+ attribute \src "libresoc.v:178500.5-178500.29"
switch \initial
- attribute \src "libresoc.v:180747.9-180747.17"
+ attribute \src "libresoc.v:178500.9-178500.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src26__data_o$next[3:0]$11601 $5\src26__data_o$next[3:0]$11605
+ assign $1\src26__data_o$next[3:0]$11509 $5\src26__data_o$next[3:0]$11513
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src26__data_o$next[3:0]$11602 \dest16__data_i
+ assign $2\src26__data_o$next[3:0]$11510 \dest16__data_i
case
- assign $2\src26__data_o$next[3:0]$11602 4'0000
+ assign $2\src26__data_o$next[3:0]$11510 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src26__data_o$next[3:0]$11603 \dest26__data_i
+ assign $3\src26__data_o$next[3:0]$11511 \dest26__data_i
case
- assign $3\src26__data_o$next[3:0]$11603 $2\src26__data_o$next[3:0]$11602
+ assign $3\src26__data_o$next[3:0]$11511 $2\src26__data_o$next[3:0]$11510
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src26__data_o$next[3:0]$11604 \w6__data_i
+ assign $4\src26__data_o$next[3:0]$11512 \w6__data_i
case
- assign $4\src26__data_o$next[3:0]$11604 $3\src26__data_o$next[3:0]$11603
+ assign $4\src26__data_o$next[3:0]$11512 $3\src26__data_o$next[3:0]$11511
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src26__data_o$next[3:0]$11605 \reg
+ assign $5\src26__data_o$next[3:0]$11513 \reg
case
- assign $5\src26__data_o$next[3:0]$11605 $4\src26__data_o$next[3:0]$11604
+ assign $5\src26__data_o$next[3:0]$11513 $4\src26__data_o$next[3:0]$11512
end
case
- assign $1\src26__data_o$next[3:0]$11601 4'0000
+ assign $1\src26__data_o$next[3:0]$11509 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src26__data_o$next[3:0]$11606 4'0000
+ assign $6\src26__data_o$next[3:0]$11514 4'0000
case
- assign $6\src26__data_o$next[3:0]$11606 $1\src26__data_o$next[3:0]$11601
+ assign $6\src26__data_o$next[3:0]$11514 $1\src26__data_o$next[3:0]$11509
end
sync always
- update \src26__data_o$next $0\src26__data_o$next[3:0]$11600
+ update \src26__data_o$next $0\src26__data_o$next[3:0]$11508
end
- attribute \src "libresoc.v:180786.3-180815.6"
- process $proc$libresoc.v:180786$11607
+ attribute \src "libresoc.v:178539.3-178568.6"
+ process $proc$libresoc.v:178539$11515
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11608 $1\wr_detect$4[0:0]$11609
- attribute \src "libresoc.v:180787.5-180787.29"
+ assign $0\wr_detect$4[0:0]$11516 $1\wr_detect$4[0:0]$11517
+ attribute \src "libresoc.v:178540.5-178540.29"
switch \initial
- attribute \src "libresoc.v:180787.9-180787.17"
+ attribute \src "libresoc.v:178540.9-178540.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11609 $4\wr_detect$4[0:0]$11612
+ assign $1\wr_detect$4[0:0]$11517 $4\wr_detect$4[0:0]$11520
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11610 1'1
+ assign $2\wr_detect$4[0:0]$11518 1'1
case
- assign $2\wr_detect$4[0:0]$11610 1'0
+ assign $2\wr_detect$4[0:0]$11518 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11611 1'1
+ assign $3\wr_detect$4[0:0]$11519 1'1
case
- assign $3\wr_detect$4[0:0]$11611 $2\wr_detect$4[0:0]$11610
+ assign $3\wr_detect$4[0:0]$11519 $2\wr_detect$4[0:0]$11518
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11612 1'1
+ assign $4\wr_detect$4[0:0]$11520 1'1
case
- assign $4\wr_detect$4[0:0]$11612 $3\wr_detect$4[0:0]$11611
+ assign $4\wr_detect$4[0:0]$11520 $3\wr_detect$4[0:0]$11519
end
case
- assign $1\wr_detect$4[0:0]$11609 1'0
+ assign $1\wr_detect$4[0:0]$11517 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11608
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11516
end
- attribute \src "libresoc.v:180816.3-180855.6"
- process $proc$libresoc.v:180816$11613
+ attribute \src "libresoc.v:178569.3-178608.6"
+ process $proc$libresoc.v:178569$11521
assign { } { }
assign { } { }
assign { } { }
- assign $0\src36__data_o$next[3:0]$11614 $6\src36__data_o$next[3:0]$11620
- attribute \src "libresoc.v:180817.5-180817.29"
+ assign $0\src36__data_o$next[3:0]$11522 $6\src36__data_o$next[3:0]$11528
+ attribute \src "libresoc.v:178570.5-178570.29"
switch \initial
- attribute \src "libresoc.v:180817.9-180817.17"
+ attribute \src "libresoc.v:178570.9-178570.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src36__data_o$next[3:0]$11615 $5\src36__data_o$next[3:0]$11619
+ assign $1\src36__data_o$next[3:0]$11523 $5\src36__data_o$next[3:0]$11527
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src36__data_o$next[3:0]$11616 \dest16__data_i
+ assign $2\src36__data_o$next[3:0]$11524 \dest16__data_i
case
- assign $2\src36__data_o$next[3:0]$11616 4'0000
+ assign $2\src36__data_o$next[3:0]$11524 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src36__data_o$next[3:0]$11617 \dest26__data_i
+ assign $3\src36__data_o$next[3:0]$11525 \dest26__data_i
case
- assign $3\src36__data_o$next[3:0]$11617 $2\src36__data_o$next[3:0]$11616
+ assign $3\src36__data_o$next[3:0]$11525 $2\src36__data_o$next[3:0]$11524
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src36__data_o$next[3:0]$11618 \w6__data_i
+ assign $4\src36__data_o$next[3:0]$11526 \w6__data_i
case
- assign $4\src36__data_o$next[3:0]$11618 $3\src36__data_o$next[3:0]$11617
+ assign $4\src36__data_o$next[3:0]$11526 $3\src36__data_o$next[3:0]$11525
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src36__data_o$next[3:0]$11619 \reg
+ assign $5\src36__data_o$next[3:0]$11527 \reg
case
- assign $5\src36__data_o$next[3:0]$11619 $4\src36__data_o$next[3:0]$11618
+ assign $5\src36__data_o$next[3:0]$11527 $4\src36__data_o$next[3:0]$11526
end
case
- assign $1\src36__data_o$next[3:0]$11615 4'0000
+ assign $1\src36__data_o$next[3:0]$11523 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src36__data_o$next[3:0]$11620 4'0000
+ assign $6\src36__data_o$next[3:0]$11528 4'0000
case
- assign $6\src36__data_o$next[3:0]$11620 $1\src36__data_o$next[3:0]$11615
+ assign $6\src36__data_o$next[3:0]$11528 $1\src36__data_o$next[3:0]$11523
end
sync always
- update \src36__data_o$next $0\src36__data_o$next[3:0]$11614
+ update \src36__data_o$next $0\src36__data_o$next[3:0]$11522
end
- attribute \src "libresoc.v:180856.3-180885.6"
- process $proc$libresoc.v:180856$11621
+ attribute \src "libresoc.v:178609.3-178638.6"
+ process $proc$libresoc.v:178609$11529
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11622 $1\wr_detect$7[0:0]$11623
- attribute \src "libresoc.v:180857.5-180857.29"
+ assign $0\wr_detect$7[0:0]$11530 $1\wr_detect$7[0:0]$11531
+ attribute \src "libresoc.v:178610.5-178610.29"
switch \initial
- attribute \src "libresoc.v:180857.9-180857.17"
+ attribute \src "libresoc.v:178610.9-178610.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11623 $4\wr_detect$7[0:0]$11626
+ assign $1\wr_detect$7[0:0]$11531 $4\wr_detect$7[0:0]$11534
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11624 1'1
+ assign $2\wr_detect$7[0:0]$11532 1'1
case
- assign $2\wr_detect$7[0:0]$11624 1'0
+ assign $2\wr_detect$7[0:0]$11532 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11625 1'1
+ assign $3\wr_detect$7[0:0]$11533 1'1
case
- assign $3\wr_detect$7[0:0]$11625 $2\wr_detect$7[0:0]$11624
+ assign $3\wr_detect$7[0:0]$11533 $2\wr_detect$7[0:0]$11532
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11626 1'1
+ assign $4\wr_detect$7[0:0]$11534 1'1
case
- assign $4\wr_detect$7[0:0]$11626 $3\wr_detect$7[0:0]$11625
+ assign $4\wr_detect$7[0:0]$11534 $3\wr_detect$7[0:0]$11533
end
case
- assign $1\wr_detect$7[0:0]$11623 1'0
+ assign $1\wr_detect$7[0:0]$11531 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11622
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11530
end
- attribute \src "libresoc.v:180886.3-180925.6"
- process $proc$libresoc.v:180886$11627
+ attribute \src "libresoc.v:178639.3-178678.6"
+ process $proc$libresoc.v:178639$11535
assign { } { }
assign { } { }
assign { } { }
- assign $0\r6__data_o$next[3:0]$11628 $6\r6__data_o$next[3:0]$11634
- attribute \src "libresoc.v:180887.5-180887.29"
+ assign $0\r6__data_o$next[3:0]$11536 $6\r6__data_o$next[3:0]$11542
+ attribute \src "libresoc.v:178640.5-178640.29"
switch \initial
- attribute \src "libresoc.v:180887.9-180887.17"
+ attribute \src "libresoc.v:178640.9-178640.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r6__data_o$next[3:0]$11629 $5\r6__data_o$next[3:0]$11633
+ assign $1\r6__data_o$next[3:0]$11537 $5\r6__data_o$next[3:0]$11541
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r6__data_o$next[3:0]$11630 \dest16__data_i
+ assign $2\r6__data_o$next[3:0]$11538 \dest16__data_i
case
- assign $2\r6__data_o$next[3:0]$11630 4'0000
+ assign $2\r6__data_o$next[3:0]$11538 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r6__data_o$next[3:0]$11631 \dest26__data_i
+ assign $3\r6__data_o$next[3:0]$11539 \dest26__data_i
case
- assign $3\r6__data_o$next[3:0]$11631 $2\r6__data_o$next[3:0]$11630
+ assign $3\r6__data_o$next[3:0]$11539 $2\r6__data_o$next[3:0]$11538
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r6__data_o$next[3:0]$11632 \w6__data_i
+ assign $4\r6__data_o$next[3:0]$11540 \w6__data_i
case
- assign $4\r6__data_o$next[3:0]$11632 $3\r6__data_o$next[3:0]$11631
+ assign $4\r6__data_o$next[3:0]$11540 $3\r6__data_o$next[3:0]$11539
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r6__data_o$next[3:0]$11633 \reg
+ assign $5\r6__data_o$next[3:0]$11541 \reg
case
- assign $5\r6__data_o$next[3:0]$11633 $4\r6__data_o$next[3:0]$11632
+ assign $5\r6__data_o$next[3:0]$11541 $4\r6__data_o$next[3:0]$11540
end
case
- assign $1\r6__data_o$next[3:0]$11629 4'0000
+ assign $1\r6__data_o$next[3:0]$11537 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r6__data_o$next[3:0]$11634 4'0000
+ assign $6\r6__data_o$next[3:0]$11542 4'0000
case
- assign $6\r6__data_o$next[3:0]$11634 $1\r6__data_o$next[3:0]$11629
+ assign $6\r6__data_o$next[3:0]$11542 $1\r6__data_o$next[3:0]$11537
end
sync always
- update \r6__data_o$next $0\r6__data_o$next[3:0]$11628
+ update \r6__data_o$next $0\r6__data_o$next[3:0]$11536
end
- attribute \src "libresoc.v:180926.3-180955.6"
- process $proc$libresoc.v:180926$11635
+ attribute \src "libresoc.v:178679.3-178708.6"
+ process $proc$libresoc.v:178679$11543
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11636 $1\wr_detect$10[0:0]$11637
- attribute \src "libresoc.v:180927.5-180927.29"
+ assign $0\wr_detect$10[0:0]$11544 $1\wr_detect$10[0:0]$11545
+ attribute \src "libresoc.v:178680.5-178680.29"
switch \initial
- attribute \src "libresoc.v:180927.9-180927.17"
+ attribute \src "libresoc.v:178680.9-178680.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11637 $4\wr_detect$10[0:0]$11640
+ assign $1\wr_detect$10[0:0]$11545 $4\wr_detect$10[0:0]$11548
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11638 1'1
+ assign $2\wr_detect$10[0:0]$11546 1'1
case
- assign $2\wr_detect$10[0:0]$11638 1'0
+ assign $2\wr_detect$10[0:0]$11546 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11639 1'1
+ assign $3\wr_detect$10[0:0]$11547 1'1
case
- assign $3\wr_detect$10[0:0]$11639 $2\wr_detect$10[0:0]$11638
+ assign $3\wr_detect$10[0:0]$11547 $2\wr_detect$10[0:0]$11546
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11640 1'1
+ assign $4\wr_detect$10[0:0]$11548 1'1
case
- assign $4\wr_detect$10[0:0]$11640 $3\wr_detect$10[0:0]$11639
+ assign $4\wr_detect$10[0:0]$11548 $3\wr_detect$10[0:0]$11547
end
case
- assign $1\wr_detect$10[0:0]$11637 1'0
+ assign $1\wr_detect$10[0:0]$11545 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11636
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11544
end
- attribute \src "libresoc.v:180956.3-180995.6"
- process $proc$libresoc.v:180956$11641
+ attribute \src "libresoc.v:178709.3-178748.6"
+ process $proc$libresoc.v:178709$11549
assign { } { }
assign { } { }
assign { } { }
- assign $0\r26__data_o$next[3:0]$11642 $6\r26__data_o$next[3:0]$11648
- attribute \src "libresoc.v:180957.5-180957.29"
+ assign $0\r26__data_o$next[3:0]$11550 $6\r26__data_o$next[3:0]$11556
+ attribute \src "libresoc.v:178710.5-178710.29"
switch \initial
- attribute \src "libresoc.v:180957.9-180957.17"
+ attribute \src "libresoc.v:178710.9-178710.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r26__data_o$next[3:0]$11643 $5\r26__data_o$next[3:0]$11647
+ assign $1\r26__data_o$next[3:0]$11551 $5\r26__data_o$next[3:0]$11555
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r26__data_o$next[3:0]$11644 \dest16__data_i
+ assign $2\r26__data_o$next[3:0]$11552 \dest16__data_i
case
- assign $2\r26__data_o$next[3:0]$11644 4'0000
+ assign $2\r26__data_o$next[3:0]$11552 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r26__data_o$next[3:0]$11645 \dest26__data_i
+ assign $3\r26__data_o$next[3:0]$11553 \dest26__data_i
case
- assign $3\r26__data_o$next[3:0]$11645 $2\r26__data_o$next[3:0]$11644
+ assign $3\r26__data_o$next[3:0]$11553 $2\r26__data_o$next[3:0]$11552
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r26__data_o$next[3:0]$11646 \w6__data_i
+ assign $4\r26__data_o$next[3:0]$11554 \w6__data_i
case
- assign $4\r26__data_o$next[3:0]$11646 $3\r26__data_o$next[3:0]$11645
+ assign $4\r26__data_o$next[3:0]$11554 $3\r26__data_o$next[3:0]$11553
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r26__data_o$next[3:0]$11647 \reg
+ assign $5\r26__data_o$next[3:0]$11555 \reg
case
- assign $5\r26__data_o$next[3:0]$11647 $4\r26__data_o$next[3:0]$11646
+ assign $5\r26__data_o$next[3:0]$11555 $4\r26__data_o$next[3:0]$11554
end
case
- assign $1\r26__data_o$next[3:0]$11643 4'0000
+ assign $1\r26__data_o$next[3:0]$11551 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r26__data_o$next[3:0]$11648 4'0000
+ assign $6\r26__data_o$next[3:0]$11556 4'0000
case
- assign $6\r26__data_o$next[3:0]$11648 $1\r26__data_o$next[3:0]$11643
+ assign $6\r26__data_o$next[3:0]$11556 $1\r26__data_o$next[3:0]$11551
end
sync always
- update \r26__data_o$next $0\r26__data_o$next[3:0]$11642
+ update \r26__data_o$next $0\r26__data_o$next[3:0]$11550
end
- attribute \src "libresoc.v:180996.3-181025.6"
- process $proc$libresoc.v:180996$11649
+ attribute \src "libresoc.v:178749.3-178778.6"
+ process $proc$libresoc.v:178749$11557
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11650 $1\wr_detect$13[0:0]$11651
- attribute \src "libresoc.v:180997.5-180997.29"
+ assign $0\wr_detect$13[0:0]$11558 $1\wr_detect$13[0:0]$11559
+ attribute \src "libresoc.v:178750.5-178750.29"
switch \initial
- attribute \src "libresoc.v:180997.9-180997.17"
+ attribute \src "libresoc.v:178750.9-178750.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11651 $4\wr_detect$13[0:0]$11654
+ assign $1\wr_detect$13[0:0]$11559 $4\wr_detect$13[0:0]$11562
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest16__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11652 1'1
+ assign $2\wr_detect$13[0:0]$11560 1'1
case
- assign $2\wr_detect$13[0:0]$11652 1'0
+ assign $2\wr_detect$13[0:0]$11560 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest26__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11653 1'1
+ assign $3\wr_detect$13[0:0]$11561 1'1
case
- assign $3\wr_detect$13[0:0]$11653 $2\wr_detect$13[0:0]$11652
+ assign $3\wr_detect$13[0:0]$11561 $2\wr_detect$13[0:0]$11560
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w6__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11654 1'1
+ assign $4\wr_detect$13[0:0]$11562 1'1
case
- assign $4\wr_detect$13[0:0]$11654 $3\wr_detect$13[0:0]$11653
+ assign $4\wr_detect$13[0:0]$11562 $3\wr_detect$13[0:0]$11561
end
case
- assign $1\wr_detect$13[0:0]$11651 1'0
+ assign $1\wr_detect$13[0:0]$11559 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11650
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11558
end
- connect \$9 $not$libresoc.v:180632$11573_Y
- connect \$12 $not$libresoc.v:180633$11574_Y
- connect \$1 $not$libresoc.v:180634$11575_Y
- connect \$3 $not$libresoc.v:180635$11576_Y
- connect \$6 $not$libresoc.v:180636$11577_Y
+ connect \$9 $not$libresoc.v:178385$11481_Y
+ connect \$12 $not$libresoc.v:178386$11482_Y
+ connect \$1 $not$libresoc.v:178387$11483_Y
+ connect \$3 $not$libresoc.v:178388$11484_Y
+ connect \$6 $not$libresoc.v:178389$11485_Y
end
-attribute \src "libresoc.v:181030.1-181501.10"
+attribute \src "libresoc.v:178783.1-179254.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7"
attribute \generator "nMigen"
module \reg_7
- attribute \src "libresoc.v:181031.7-181031.20"
+ attribute \src "libresoc.v:178784.7-178784.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $0\r27__data_o$next[3:0]$11731
- attribute \src "libresoc.v:181114.3-181115.39"
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $0\r27__data_o$next[3:0]$11639
+ attribute \src "libresoc.v:178867.3-178868.39"
wire width 4 $0\r27__data_o[3:0]
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $0\r7__data_o$next[3:0]$11717
- attribute \src "libresoc.v:181116.3-181117.37"
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $0\r7__data_o$next[3:0]$11625
+ attribute \src "libresoc.v:178869.3-178870.37"
wire width 4 $0\r7__data_o[3:0]
- attribute \src "libresoc.v:181194.3-181220.6"
- wire width 4 $0\reg$next[3:0]$11683
- attribute \src "libresoc.v:181112.3-181113.25"
+ attribute \src "libresoc.v:178947.3-178973.6"
+ wire width 4 $0\reg$next[3:0]$11591
+ attribute \src "libresoc.v:178865.3-178866.25"
wire width 4 $0\reg[3:0]
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $0\src17__data_o$next[3:0]$11674
- attribute \src "libresoc.v:181122.3-181123.43"
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $0\src17__data_o$next[3:0]$11582
+ attribute \src "libresoc.v:178875.3-178876.43"
wire width 4 $0\src17__data_o[3:0]
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $0\src27__data_o$next[3:0]$11689
- attribute \src "libresoc.v:181120.3-181121.43"
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $0\src27__data_o$next[3:0]$11597
+ attribute \src "libresoc.v:178873.3-178874.43"
wire width 4 $0\src27__data_o[3:0]
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $0\src37__data_o$next[3:0]$11703
- attribute \src "libresoc.v:181118.3-181119.43"
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $0\src37__data_o$next[3:0]$11611
+ attribute \src "libresoc.v:178871.3-178872.43"
wire width 4 $0\src37__data_o[3:0]
- attribute \src "libresoc.v:181401.3-181430.6"
- wire $0\wr_detect$10[0:0]$11725
- attribute \src "libresoc.v:181471.3-181500.6"
- wire $0\wr_detect$13[0:0]$11739
- attribute \src "libresoc.v:181261.3-181290.6"
- wire $0\wr_detect$4[0:0]$11697
- attribute \src "libresoc.v:181331.3-181360.6"
- wire $0\wr_detect$7[0:0]$11711
- attribute \src "libresoc.v:181164.3-181193.6"
+ attribute \src "libresoc.v:179154.3-179183.6"
+ wire $0\wr_detect$10[0:0]$11633
+ attribute \src "libresoc.v:179224.3-179253.6"
+ wire $0\wr_detect$13[0:0]$11647
+ attribute \src "libresoc.v:179014.3-179043.6"
+ wire $0\wr_detect$4[0:0]$11605
+ attribute \src "libresoc.v:179084.3-179113.6"
+ wire $0\wr_detect$7[0:0]$11619
+ attribute \src "libresoc.v:178917.3-178946.6"
wire $0\wr_detect[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $1\r27__data_o$next[3:0]$11732
- attribute \src "libresoc.v:181056.13-181056.31"
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $1\r27__data_o$next[3:0]$11640
+ attribute \src "libresoc.v:178809.13-178809.31"
wire width 4 $1\r27__data_o[3:0]
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $1\r7__data_o$next[3:0]$11718
- attribute \src "libresoc.v:181063.13-181063.30"
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $1\r7__data_o$next[3:0]$11626
+ attribute \src "libresoc.v:178816.13-178816.30"
wire width 4 $1\r7__data_o[3:0]
- attribute \src "libresoc.v:181194.3-181220.6"
- wire width 4 $1\reg$next[3:0]$11684
- attribute \src "libresoc.v:181069.13-181069.25"
+ attribute \src "libresoc.v:178947.3-178973.6"
+ wire width 4 $1\reg$next[3:0]$11592
+ attribute \src "libresoc.v:178822.13-178822.25"
wire width 4 $1\reg[3:0]
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $1\src17__data_o$next[3:0]$11675
- attribute \src "libresoc.v:181074.13-181074.33"
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $1\src17__data_o$next[3:0]$11583
+ attribute \src "libresoc.v:178827.13-178827.33"
wire width 4 $1\src17__data_o[3:0]
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $1\src27__data_o$next[3:0]$11690
- attribute \src "libresoc.v:181081.13-181081.33"
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $1\src27__data_o$next[3:0]$11598
+ attribute \src "libresoc.v:178834.13-178834.33"
wire width 4 $1\src27__data_o[3:0]
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $1\src37__data_o$next[3:0]$11704
- attribute \src "libresoc.v:181088.13-181088.33"
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $1\src37__data_o$next[3:0]$11612
+ attribute \src "libresoc.v:178841.13-178841.33"
wire width 4 $1\src37__data_o[3:0]
- attribute \src "libresoc.v:181401.3-181430.6"
- wire $1\wr_detect$10[0:0]$11726
- attribute \src "libresoc.v:181471.3-181500.6"
- wire $1\wr_detect$13[0:0]$11740
- attribute \src "libresoc.v:181261.3-181290.6"
- wire $1\wr_detect$4[0:0]$11698
- attribute \src "libresoc.v:181331.3-181360.6"
- wire $1\wr_detect$7[0:0]$11712
- attribute \src "libresoc.v:181164.3-181193.6"
+ attribute \src "libresoc.v:179154.3-179183.6"
+ wire $1\wr_detect$10[0:0]$11634
+ attribute \src "libresoc.v:179224.3-179253.6"
+ wire $1\wr_detect$13[0:0]$11648
+ attribute \src "libresoc.v:179014.3-179043.6"
+ wire $1\wr_detect$4[0:0]$11606
+ attribute \src "libresoc.v:179084.3-179113.6"
+ wire $1\wr_detect$7[0:0]$11620
+ attribute \src "libresoc.v:178917.3-178946.6"
wire $1\wr_detect[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $2\r27__data_o$next[3:0]$11733
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $2\r7__data_o$next[3:0]$11719
- attribute \src "libresoc.v:181194.3-181220.6"
- wire width 4 $2\reg$next[3:0]$11685
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $2\src17__data_o$next[3:0]$11676
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $2\src27__data_o$next[3:0]$11691
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $2\src37__data_o$next[3:0]$11705
- attribute \src "libresoc.v:181401.3-181430.6"
- wire $2\wr_detect$10[0:0]$11727
- attribute \src "libresoc.v:181471.3-181500.6"
- wire $2\wr_detect$13[0:0]$11741
- attribute \src "libresoc.v:181261.3-181290.6"
- wire $2\wr_detect$4[0:0]$11699
- attribute \src "libresoc.v:181331.3-181360.6"
- wire $2\wr_detect$7[0:0]$11713
- attribute \src "libresoc.v:181164.3-181193.6"
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $2\r27__data_o$next[3:0]$11641
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $2\r7__data_o$next[3:0]$11627
+ attribute \src "libresoc.v:178947.3-178973.6"
+ wire width 4 $2\reg$next[3:0]$11593
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $2\src17__data_o$next[3:0]$11584
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $2\src27__data_o$next[3:0]$11599
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $2\src37__data_o$next[3:0]$11613
+ attribute \src "libresoc.v:179154.3-179183.6"
+ wire $2\wr_detect$10[0:0]$11635
+ attribute \src "libresoc.v:179224.3-179253.6"
+ wire $2\wr_detect$13[0:0]$11649
+ attribute \src "libresoc.v:179014.3-179043.6"
+ wire $2\wr_detect$4[0:0]$11607
+ attribute \src "libresoc.v:179084.3-179113.6"
+ wire $2\wr_detect$7[0:0]$11621
+ attribute \src "libresoc.v:178917.3-178946.6"
wire $2\wr_detect[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $3\r27__data_o$next[3:0]$11734
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $3\r7__data_o$next[3:0]$11720
- attribute \src "libresoc.v:181194.3-181220.6"
- wire width 4 $3\reg$next[3:0]$11686
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $3\src17__data_o$next[3:0]$11677
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $3\src27__data_o$next[3:0]$11692
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $3\src37__data_o$next[3:0]$11706
- attribute \src "libresoc.v:181401.3-181430.6"
- wire $3\wr_detect$10[0:0]$11728
- attribute \src "libresoc.v:181471.3-181500.6"
- wire $3\wr_detect$13[0:0]$11742
- attribute \src "libresoc.v:181261.3-181290.6"
- wire $3\wr_detect$4[0:0]$11700
- attribute \src "libresoc.v:181331.3-181360.6"
- wire $3\wr_detect$7[0:0]$11714
- attribute \src "libresoc.v:181164.3-181193.6"
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $3\r27__data_o$next[3:0]$11642
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $3\r7__data_o$next[3:0]$11628
+ attribute \src "libresoc.v:178947.3-178973.6"
+ wire width 4 $3\reg$next[3:0]$11594
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $3\src17__data_o$next[3:0]$11585
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $3\src27__data_o$next[3:0]$11600
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $3\src37__data_o$next[3:0]$11614
+ attribute \src "libresoc.v:179154.3-179183.6"
+ wire $3\wr_detect$10[0:0]$11636
+ attribute \src "libresoc.v:179224.3-179253.6"
+ wire $3\wr_detect$13[0:0]$11650
+ attribute \src "libresoc.v:179014.3-179043.6"
+ wire $3\wr_detect$4[0:0]$11608
+ attribute \src "libresoc.v:179084.3-179113.6"
+ wire $3\wr_detect$7[0:0]$11622
+ attribute \src "libresoc.v:178917.3-178946.6"
wire $3\wr_detect[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $4\r27__data_o$next[3:0]$11735
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $4\r7__data_o$next[3:0]$11721
- attribute \src "libresoc.v:181194.3-181220.6"
- wire width 4 $4\reg$next[3:0]$11687
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $4\src17__data_o$next[3:0]$11678
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $4\src27__data_o$next[3:0]$11693
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $4\src37__data_o$next[3:0]$11707
- attribute \src "libresoc.v:181401.3-181430.6"
- wire $4\wr_detect$10[0:0]$11729
- attribute \src "libresoc.v:181471.3-181500.6"
- wire $4\wr_detect$13[0:0]$11743
- attribute \src "libresoc.v:181261.3-181290.6"
- wire $4\wr_detect$4[0:0]$11701
- attribute \src "libresoc.v:181331.3-181360.6"
- wire $4\wr_detect$7[0:0]$11715
- attribute \src "libresoc.v:181164.3-181193.6"
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $4\r27__data_o$next[3:0]$11643
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $4\r7__data_o$next[3:0]$11629
+ attribute \src "libresoc.v:178947.3-178973.6"
+ wire width 4 $4\reg$next[3:0]$11595
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $4\src17__data_o$next[3:0]$11586
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $4\src27__data_o$next[3:0]$11601
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $4\src37__data_o$next[3:0]$11615
+ attribute \src "libresoc.v:179154.3-179183.6"
+ wire $4\wr_detect$10[0:0]$11637
+ attribute \src "libresoc.v:179224.3-179253.6"
+ wire $4\wr_detect$13[0:0]$11651
+ attribute \src "libresoc.v:179014.3-179043.6"
+ wire $4\wr_detect$4[0:0]$11609
+ attribute \src "libresoc.v:179084.3-179113.6"
+ wire $4\wr_detect$7[0:0]$11623
+ attribute \src "libresoc.v:178917.3-178946.6"
wire $4\wr_detect[0:0]
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $5\r27__data_o$next[3:0]$11736
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $5\r7__data_o$next[3:0]$11722
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $5\src17__data_o$next[3:0]$11679
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $5\src27__data_o$next[3:0]$11694
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $5\src37__data_o$next[3:0]$11708
- attribute \src "libresoc.v:181431.3-181470.6"
- wire width 4 $6\r27__data_o$next[3:0]$11737
- attribute \src "libresoc.v:181361.3-181400.6"
- wire width 4 $6\r7__data_o$next[3:0]$11723
- attribute \src "libresoc.v:181124.3-181163.6"
- wire width 4 $6\src17__data_o$next[3:0]$11680
- attribute \src "libresoc.v:181221.3-181260.6"
- wire width 4 $6\src27__data_o$next[3:0]$11695
- attribute \src "libresoc.v:181291.3-181330.6"
- wire width 4 $6\src37__data_o$next[3:0]$11709
- attribute \src "libresoc.v:181107.17-181107.104"
- wire $not$libresoc.v:181107$11662_Y
- attribute \src "libresoc.v:181108.18-181108.105"
- wire $not$libresoc.v:181108$11663_Y
- attribute \src "libresoc.v:181109.17-181109.100"
- wire $not$libresoc.v:181109$11664_Y
- attribute \src "libresoc.v:181110.17-181110.103"
- wire $not$libresoc.v:181110$11665_Y
- attribute \src "libresoc.v:181111.17-181111.103"
- wire $not$libresoc.v:181111$11666_Y
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $5\r27__data_o$next[3:0]$11644
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $5\r7__data_o$next[3:0]$11630
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $5\src17__data_o$next[3:0]$11587
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $5\src27__data_o$next[3:0]$11602
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $5\src37__data_o$next[3:0]$11616
+ attribute \src "libresoc.v:179184.3-179223.6"
+ wire width 4 $6\r27__data_o$next[3:0]$11645
+ attribute \src "libresoc.v:179114.3-179153.6"
+ wire width 4 $6\r7__data_o$next[3:0]$11631
+ attribute \src "libresoc.v:178877.3-178916.6"
+ wire width 4 $6\src17__data_o$next[3:0]$11588
+ attribute \src "libresoc.v:178974.3-179013.6"
+ wire width 4 $6\src27__data_o$next[3:0]$11603
+ attribute \src "libresoc.v:179044.3-179083.6"
+ wire width 4 $6\src37__data_o$next[3:0]$11617
+ attribute \src "libresoc.v:178860.17-178860.104"
+ wire $not$libresoc.v:178860$11570_Y
+ attribute \src "libresoc.v:178861.18-178861.105"
+ wire $not$libresoc.v:178861$11571_Y
+ attribute \src "libresoc.v:178862.17-178862.100"
+ wire $not$libresoc.v:178862$11572_Y
+ attribute \src "libresoc.v:178863.17-178863.103"
+ wire $not$libresoc.v:178863$11573_Y
+ attribute \src "libresoc.v:178864.17-178864.103"
+ wire $not$libresoc.v:178864$11574_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest17__data_i
wire width 4 input 11 \dest27__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 10 \dest27__wen
- attribute \src "libresoc.v:181031.7-181031.15"
+ attribute \src "libresoc.v:178784.7-178784.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 output 14 \r27__data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
wire \wr_detect$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181107$11662
+ cell $not $not$libresoc.v:178860$11570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$10
- connect \Y $not$libresoc.v:181107$11662_Y
+ connect \Y $not$libresoc.v:178860$11570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181108$11663
+ cell $not $not$libresoc.v:178861$11571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$13
- connect \Y $not$libresoc.v:181108$11663_Y
+ connect \Y $not$libresoc.v:178861$11571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181109$11664
+ cell $not $not$libresoc.v:178862$11572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect
- connect \Y $not$libresoc.v:181109$11664_Y
+ connect \Y $not$libresoc.v:178862$11572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181110$11665
+ cell $not $not$libresoc.v:178863$11573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$4
- connect \Y $not$libresoc.v:181110$11665_Y
+ connect \Y $not$libresoc.v:178863$11573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
- cell $not $not$libresoc.v:181111$11666
+ cell $not $not$libresoc.v:178864$11574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_detect$7
- connect \Y $not$libresoc.v:181111$11666_Y
+ connect \Y $not$libresoc.v:178864$11574_Y
end
- attribute \src "libresoc.v:181031.7-181031.20"
- process $proc$libresoc.v:181031$11744
+ attribute \src "libresoc.v:178784.7-178784.20"
+ process $proc$libresoc.v:178784$11652
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181056.13-181056.31"
- process $proc$libresoc.v:181056$11745
+ attribute \src "libresoc.v:178809.13-178809.31"
+ process $proc$libresoc.v:178809$11653
assign { } { }
assign $1\r27__data_o[3:0] 4'0000
sync always
sync init
update \r27__data_o $1\r27__data_o[3:0]
end
- attribute \src "libresoc.v:181063.13-181063.30"
- process $proc$libresoc.v:181063$11746
+ attribute \src "libresoc.v:178816.13-178816.30"
+ process $proc$libresoc.v:178816$11654
assign { } { }
assign $1\r7__data_o[3:0] 4'0000
sync always
sync init
update \r7__data_o $1\r7__data_o[3:0]
end
- attribute \src "libresoc.v:181069.13-181069.25"
- process $proc$libresoc.v:181069$11747
+ attribute \src "libresoc.v:178822.13-178822.25"
+ process $proc$libresoc.v:178822$11655
assign { } { }
assign $1\reg[3:0] 4'0000
sync always
sync init
update \reg $1\reg[3:0]
end
- attribute \src "libresoc.v:181074.13-181074.33"
- process $proc$libresoc.v:181074$11748
+ attribute \src "libresoc.v:178827.13-178827.33"
+ process $proc$libresoc.v:178827$11656
assign { } { }
assign $1\src17__data_o[3:0] 4'0000
sync always
sync init
update \src17__data_o $1\src17__data_o[3:0]
end
- attribute \src "libresoc.v:181081.13-181081.33"
- process $proc$libresoc.v:181081$11749
+ attribute \src "libresoc.v:178834.13-178834.33"
+ process $proc$libresoc.v:178834$11657
assign { } { }
assign $1\src27__data_o[3:0] 4'0000
sync always
sync init
update \src27__data_o $1\src27__data_o[3:0]
end
- attribute \src "libresoc.v:181088.13-181088.33"
- process $proc$libresoc.v:181088$11750
+ attribute \src "libresoc.v:178841.13-178841.33"
+ process $proc$libresoc.v:178841$11658
assign { } { }
assign $1\src37__data_o[3:0] 4'0000
sync always
sync init
update \src37__data_o $1\src37__data_o[3:0]
end
- attribute \src "libresoc.v:181112.3-181113.25"
- process $proc$libresoc.v:181112$11667
+ attribute \src "libresoc.v:178865.3-178866.25"
+ process $proc$libresoc.v:178865$11575
assign { } { }
assign $0\reg[3:0] \reg$next
sync posedge \coresync_clk
update \reg $0\reg[3:0]
end
- attribute \src "libresoc.v:181114.3-181115.39"
- process $proc$libresoc.v:181114$11668
+ attribute \src "libresoc.v:178867.3-178868.39"
+ process $proc$libresoc.v:178867$11576
assign { } { }
assign $0\r27__data_o[3:0] \r27__data_o$next
sync posedge \coresync_clk
update \r27__data_o $0\r27__data_o[3:0]
end
- attribute \src "libresoc.v:181116.3-181117.37"
- process $proc$libresoc.v:181116$11669
+ attribute \src "libresoc.v:178869.3-178870.37"
+ process $proc$libresoc.v:178869$11577
assign { } { }
assign $0\r7__data_o[3:0] \r7__data_o$next
sync posedge \coresync_clk
update \r7__data_o $0\r7__data_o[3:0]
end
- attribute \src "libresoc.v:181118.3-181119.43"
- process $proc$libresoc.v:181118$11670
+ attribute \src "libresoc.v:178871.3-178872.43"
+ process $proc$libresoc.v:178871$11578
assign { } { }
assign $0\src37__data_o[3:0] \src37__data_o$next
sync posedge \coresync_clk
update \src37__data_o $0\src37__data_o[3:0]
end
- attribute \src "libresoc.v:181120.3-181121.43"
- process $proc$libresoc.v:181120$11671
+ attribute \src "libresoc.v:178873.3-178874.43"
+ process $proc$libresoc.v:178873$11579
assign { } { }
assign $0\src27__data_o[3:0] \src27__data_o$next
sync posedge \coresync_clk
update \src27__data_o $0\src27__data_o[3:0]
end
- attribute \src "libresoc.v:181122.3-181123.43"
- process $proc$libresoc.v:181122$11672
+ attribute \src "libresoc.v:178875.3-178876.43"
+ process $proc$libresoc.v:178875$11580
assign { } { }
assign $0\src17__data_o[3:0] \src17__data_o$next
sync posedge \coresync_clk
update \src17__data_o $0\src17__data_o[3:0]
end
- attribute \src "libresoc.v:181124.3-181163.6"
- process $proc$libresoc.v:181124$11673
+ attribute \src "libresoc.v:178877.3-178916.6"
+ process $proc$libresoc.v:178877$11581
assign { } { }
assign { } { }
assign { } { }
- assign $0\src17__data_o$next[3:0]$11674 $6\src17__data_o$next[3:0]$11680
- attribute \src "libresoc.v:181125.5-181125.29"
+ assign $0\src17__data_o$next[3:0]$11582 $6\src17__data_o$next[3:0]$11588
+ attribute \src "libresoc.v:178878.5-178878.29"
switch \initial
- attribute \src "libresoc.v:181125.9-181125.17"
+ attribute \src "libresoc.v:178878.9-178878.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src17__data_o$next[3:0]$11675 $5\src17__data_o$next[3:0]$11679
+ assign $1\src17__data_o$next[3:0]$11583 $5\src17__data_o$next[3:0]$11587
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src17__data_o$next[3:0]$11676 \dest17__data_i
+ assign $2\src17__data_o$next[3:0]$11584 \dest17__data_i
case
- assign $2\src17__data_o$next[3:0]$11676 4'0000
+ assign $2\src17__data_o$next[3:0]$11584 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src17__data_o$next[3:0]$11677 \dest27__data_i
+ assign $3\src17__data_o$next[3:0]$11585 \dest27__data_i
case
- assign $3\src17__data_o$next[3:0]$11677 $2\src17__data_o$next[3:0]$11676
+ assign $3\src17__data_o$next[3:0]$11585 $2\src17__data_o$next[3:0]$11584
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src17__data_o$next[3:0]$11678 \w7__data_i
+ assign $4\src17__data_o$next[3:0]$11586 \w7__data_i
case
- assign $4\src17__data_o$next[3:0]$11678 $3\src17__data_o$next[3:0]$11677
+ assign $4\src17__data_o$next[3:0]$11586 $3\src17__data_o$next[3:0]$11585
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src17__data_o$next[3:0]$11679 \reg
+ assign $5\src17__data_o$next[3:0]$11587 \reg
case
- assign $5\src17__data_o$next[3:0]$11679 $4\src17__data_o$next[3:0]$11678
+ assign $5\src17__data_o$next[3:0]$11587 $4\src17__data_o$next[3:0]$11586
end
case
- assign $1\src17__data_o$next[3:0]$11675 4'0000
+ assign $1\src17__data_o$next[3:0]$11583 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src17__data_o$next[3:0]$11680 4'0000
+ assign $6\src17__data_o$next[3:0]$11588 4'0000
case
- assign $6\src17__data_o$next[3:0]$11680 $1\src17__data_o$next[3:0]$11675
+ assign $6\src17__data_o$next[3:0]$11588 $1\src17__data_o$next[3:0]$11583
end
sync always
- update \src17__data_o$next $0\src17__data_o$next[3:0]$11674
+ update \src17__data_o$next $0\src17__data_o$next[3:0]$11582
end
- attribute \src "libresoc.v:181164.3-181193.6"
- process $proc$libresoc.v:181164$11681
+ attribute \src "libresoc.v:178917.3-178946.6"
+ process $proc$libresoc.v:178917$11589
assign { } { }
assign { } { }
assign $0\wr_detect[0:0] $1\wr_detect[0:0]
- attribute \src "libresoc.v:181165.5-181165.29"
+ attribute \src "libresoc.v:178918.5-178918.29"
switch \initial
- attribute \src "libresoc.v:181165.9-181165.17"
+ attribute \src "libresoc.v:178918.9-178918.17"
case 1'1
case
end
sync always
update \wr_detect $0\wr_detect[0:0]
end
- attribute \src "libresoc.v:181194.3-181220.6"
- process $proc$libresoc.v:181194$11682
+ attribute \src "libresoc.v:178947.3-178973.6"
+ process $proc$libresoc.v:178947$11590
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\reg$next[3:0]$11683 $4\reg$next[3:0]$11687
- attribute \src "libresoc.v:181195.5-181195.29"
+ assign $0\reg$next[3:0]$11591 $4\reg$next[3:0]$11595
+ attribute \src "libresoc.v:178948.5-178948.29"
switch \initial
- attribute \src "libresoc.v:181195.9-181195.17"
+ attribute \src "libresoc.v:178948.9-178948.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\reg$next[3:0]$11684 \dest17__data_i
+ assign $1\reg$next[3:0]$11592 \dest17__data_i
case
- assign $1\reg$next[3:0]$11684 \reg
+ assign $1\reg$next[3:0]$11592 \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\reg$next[3:0]$11685 \dest27__data_i
+ assign $2\reg$next[3:0]$11593 \dest27__data_i
case
- assign $2\reg$next[3:0]$11685 $1\reg$next[3:0]$11684
+ assign $2\reg$next[3:0]$11593 $1\reg$next[3:0]$11592
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\reg$next[3:0]$11686 \w7__data_i
+ assign $3\reg$next[3:0]$11594 \w7__data_i
case
- assign $3\reg$next[3:0]$11686 $2\reg$next[3:0]$11685
+ assign $3\reg$next[3:0]$11594 $2\reg$next[3:0]$11593
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\reg$next[3:0]$11687 4'0000
+ assign $4\reg$next[3:0]$11595 4'0000
case
- assign $4\reg$next[3:0]$11687 $3\reg$next[3:0]$11686
+ assign $4\reg$next[3:0]$11595 $3\reg$next[3:0]$11594
end
sync always
- update \reg$next $0\reg$next[3:0]$11683
+ update \reg$next $0\reg$next[3:0]$11591
end
- attribute \src "libresoc.v:181221.3-181260.6"
- process $proc$libresoc.v:181221$11688
+ attribute \src "libresoc.v:178974.3-179013.6"
+ process $proc$libresoc.v:178974$11596
assign { } { }
assign { } { }
assign { } { }
- assign $0\src27__data_o$next[3:0]$11689 $6\src27__data_o$next[3:0]$11695
- attribute \src "libresoc.v:181222.5-181222.29"
+ assign $0\src27__data_o$next[3:0]$11597 $6\src27__data_o$next[3:0]$11603
+ attribute \src "libresoc.v:178975.5-178975.29"
switch \initial
- attribute \src "libresoc.v:181222.9-181222.17"
+ attribute \src "libresoc.v:178975.9-178975.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src27__data_o$next[3:0]$11690 $5\src27__data_o$next[3:0]$11694
+ assign $1\src27__data_o$next[3:0]$11598 $5\src27__data_o$next[3:0]$11602
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src27__data_o$next[3:0]$11691 \dest17__data_i
+ assign $2\src27__data_o$next[3:0]$11599 \dest17__data_i
case
- assign $2\src27__data_o$next[3:0]$11691 4'0000
+ assign $2\src27__data_o$next[3:0]$11599 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src27__data_o$next[3:0]$11692 \dest27__data_i
+ assign $3\src27__data_o$next[3:0]$11600 \dest27__data_i
case
- assign $3\src27__data_o$next[3:0]$11692 $2\src27__data_o$next[3:0]$11691
+ assign $3\src27__data_o$next[3:0]$11600 $2\src27__data_o$next[3:0]$11599
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src27__data_o$next[3:0]$11693 \w7__data_i
+ assign $4\src27__data_o$next[3:0]$11601 \w7__data_i
case
- assign $4\src27__data_o$next[3:0]$11693 $3\src27__data_o$next[3:0]$11692
+ assign $4\src27__data_o$next[3:0]$11601 $3\src27__data_o$next[3:0]$11600
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src27__data_o$next[3:0]$11694 \reg
+ assign $5\src27__data_o$next[3:0]$11602 \reg
case
- assign $5\src27__data_o$next[3:0]$11694 $4\src27__data_o$next[3:0]$11693
+ assign $5\src27__data_o$next[3:0]$11602 $4\src27__data_o$next[3:0]$11601
end
case
- assign $1\src27__data_o$next[3:0]$11690 4'0000
+ assign $1\src27__data_o$next[3:0]$11598 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src27__data_o$next[3:0]$11695 4'0000
+ assign $6\src27__data_o$next[3:0]$11603 4'0000
case
- assign $6\src27__data_o$next[3:0]$11695 $1\src27__data_o$next[3:0]$11690
+ assign $6\src27__data_o$next[3:0]$11603 $1\src27__data_o$next[3:0]$11598
end
sync always
- update \src27__data_o$next $0\src27__data_o$next[3:0]$11689
+ update \src27__data_o$next $0\src27__data_o$next[3:0]$11597
end
- attribute \src "libresoc.v:181261.3-181290.6"
- process $proc$libresoc.v:181261$11696
+ attribute \src "libresoc.v:179014.3-179043.6"
+ process $proc$libresoc.v:179014$11604
assign { } { }
assign { } { }
- assign $0\wr_detect$4[0:0]$11697 $1\wr_detect$4[0:0]$11698
- attribute \src "libresoc.v:181262.5-181262.29"
+ assign $0\wr_detect$4[0:0]$11605 $1\wr_detect$4[0:0]$11606
+ attribute \src "libresoc.v:179015.5-179015.29"
switch \initial
- attribute \src "libresoc.v:181262.9-181262.17"
+ attribute \src "libresoc.v:179015.9-179015.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$4[0:0]$11698 $4\wr_detect$4[0:0]$11701
+ assign $1\wr_detect$4[0:0]$11606 $4\wr_detect$4[0:0]$11609
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$4[0:0]$11699 1'1
+ assign $2\wr_detect$4[0:0]$11607 1'1
case
- assign $2\wr_detect$4[0:0]$11699 1'0
+ assign $2\wr_detect$4[0:0]$11607 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$4[0:0]$11700 1'1
+ assign $3\wr_detect$4[0:0]$11608 1'1
case
- assign $3\wr_detect$4[0:0]$11700 $2\wr_detect$4[0:0]$11699
+ assign $3\wr_detect$4[0:0]$11608 $2\wr_detect$4[0:0]$11607
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$4[0:0]$11701 1'1
+ assign $4\wr_detect$4[0:0]$11609 1'1
case
- assign $4\wr_detect$4[0:0]$11701 $3\wr_detect$4[0:0]$11700
+ assign $4\wr_detect$4[0:0]$11609 $3\wr_detect$4[0:0]$11608
end
case
- assign $1\wr_detect$4[0:0]$11698 1'0
+ assign $1\wr_detect$4[0:0]$11606 1'0
end
sync always
- update \wr_detect$4 $0\wr_detect$4[0:0]$11697
+ update \wr_detect$4 $0\wr_detect$4[0:0]$11605
end
- attribute \src "libresoc.v:181291.3-181330.6"
- process $proc$libresoc.v:181291$11702
+ attribute \src "libresoc.v:179044.3-179083.6"
+ process $proc$libresoc.v:179044$11610
assign { } { }
assign { } { }
assign { } { }
- assign $0\src37__data_o$next[3:0]$11703 $6\src37__data_o$next[3:0]$11709
- attribute \src "libresoc.v:181292.5-181292.29"
+ assign $0\src37__data_o$next[3:0]$11611 $6\src37__data_o$next[3:0]$11617
+ attribute \src "libresoc.v:179045.5-179045.29"
switch \initial
- attribute \src "libresoc.v:181292.9-181292.17"
+ attribute \src "libresoc.v:179045.9-179045.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\src37__data_o$next[3:0]$11704 $5\src37__data_o$next[3:0]$11708
+ assign $1\src37__data_o$next[3:0]$11612 $5\src37__data_o$next[3:0]$11616
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\src37__data_o$next[3:0]$11705 \dest17__data_i
+ assign $2\src37__data_o$next[3:0]$11613 \dest17__data_i
case
- assign $2\src37__data_o$next[3:0]$11705 4'0000
+ assign $2\src37__data_o$next[3:0]$11613 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\src37__data_o$next[3:0]$11706 \dest27__data_i
+ assign $3\src37__data_o$next[3:0]$11614 \dest27__data_i
case
- assign $3\src37__data_o$next[3:0]$11706 $2\src37__data_o$next[3:0]$11705
+ assign $3\src37__data_o$next[3:0]$11614 $2\src37__data_o$next[3:0]$11613
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\src37__data_o$next[3:0]$11707 \w7__data_i
+ assign $4\src37__data_o$next[3:0]$11615 \w7__data_i
case
- assign $4\src37__data_o$next[3:0]$11707 $3\src37__data_o$next[3:0]$11706
+ assign $4\src37__data_o$next[3:0]$11615 $3\src37__data_o$next[3:0]$11614
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$6
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\src37__data_o$next[3:0]$11708 \reg
+ assign $5\src37__data_o$next[3:0]$11616 \reg
case
- assign $5\src37__data_o$next[3:0]$11708 $4\src37__data_o$next[3:0]$11707
+ assign $5\src37__data_o$next[3:0]$11616 $4\src37__data_o$next[3:0]$11615
end
case
- assign $1\src37__data_o$next[3:0]$11704 4'0000
+ assign $1\src37__data_o$next[3:0]$11612 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\src37__data_o$next[3:0]$11709 4'0000
+ assign $6\src37__data_o$next[3:0]$11617 4'0000
case
- assign $6\src37__data_o$next[3:0]$11709 $1\src37__data_o$next[3:0]$11704
+ assign $6\src37__data_o$next[3:0]$11617 $1\src37__data_o$next[3:0]$11612
end
sync always
- update \src37__data_o$next $0\src37__data_o$next[3:0]$11703
+ update \src37__data_o$next $0\src37__data_o$next[3:0]$11611
end
- attribute \src "libresoc.v:181331.3-181360.6"
- process $proc$libresoc.v:181331$11710
+ attribute \src "libresoc.v:179084.3-179113.6"
+ process $proc$libresoc.v:179084$11618
assign { } { }
assign { } { }
- assign $0\wr_detect$7[0:0]$11711 $1\wr_detect$7[0:0]$11712
- attribute \src "libresoc.v:181332.5-181332.29"
+ assign $0\wr_detect$7[0:0]$11619 $1\wr_detect$7[0:0]$11620
+ attribute \src "libresoc.v:179085.5-179085.29"
switch \initial
- attribute \src "libresoc.v:181332.9-181332.17"
+ attribute \src "libresoc.v:179085.9-179085.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$7[0:0]$11712 $4\wr_detect$7[0:0]$11715
+ assign $1\wr_detect$7[0:0]$11620 $4\wr_detect$7[0:0]$11623
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$7[0:0]$11713 1'1
+ assign $2\wr_detect$7[0:0]$11621 1'1
case
- assign $2\wr_detect$7[0:0]$11713 1'0
+ assign $2\wr_detect$7[0:0]$11621 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$7[0:0]$11714 1'1
+ assign $3\wr_detect$7[0:0]$11622 1'1
case
- assign $3\wr_detect$7[0:0]$11714 $2\wr_detect$7[0:0]$11713
+ assign $3\wr_detect$7[0:0]$11622 $2\wr_detect$7[0:0]$11621
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$7[0:0]$11715 1'1
+ assign $4\wr_detect$7[0:0]$11623 1'1
case
- assign $4\wr_detect$7[0:0]$11715 $3\wr_detect$7[0:0]$11714
+ assign $4\wr_detect$7[0:0]$11623 $3\wr_detect$7[0:0]$11622
end
case
- assign $1\wr_detect$7[0:0]$11712 1'0
+ assign $1\wr_detect$7[0:0]$11620 1'0
end
sync always
- update \wr_detect$7 $0\wr_detect$7[0:0]$11711
+ update \wr_detect$7 $0\wr_detect$7[0:0]$11619
end
- attribute \src "libresoc.v:181361.3-181400.6"
- process $proc$libresoc.v:181361$11716
+ attribute \src "libresoc.v:179114.3-179153.6"
+ process $proc$libresoc.v:179114$11624
assign { } { }
assign { } { }
assign { } { }
- assign $0\r7__data_o$next[3:0]$11717 $6\r7__data_o$next[3:0]$11723
- attribute \src "libresoc.v:181362.5-181362.29"
+ assign $0\r7__data_o$next[3:0]$11625 $6\r7__data_o$next[3:0]$11631
+ attribute \src "libresoc.v:179115.5-179115.29"
switch \initial
- attribute \src "libresoc.v:181362.9-181362.17"
+ attribute \src "libresoc.v:179115.9-179115.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r7__data_o$next[3:0]$11718 $5\r7__data_o$next[3:0]$11722
+ assign $1\r7__data_o$next[3:0]$11626 $5\r7__data_o$next[3:0]$11630
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r7__data_o$next[3:0]$11719 \dest17__data_i
+ assign $2\r7__data_o$next[3:0]$11627 \dest17__data_i
case
- assign $2\r7__data_o$next[3:0]$11719 4'0000
+ assign $2\r7__data_o$next[3:0]$11627 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r7__data_o$next[3:0]$11720 \dest27__data_i
+ assign $3\r7__data_o$next[3:0]$11628 \dest27__data_i
case
- assign $3\r7__data_o$next[3:0]$11720 $2\r7__data_o$next[3:0]$11719
+ assign $3\r7__data_o$next[3:0]$11628 $2\r7__data_o$next[3:0]$11627
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r7__data_o$next[3:0]$11721 \w7__data_i
+ assign $4\r7__data_o$next[3:0]$11629 \w7__data_i
case
- assign $4\r7__data_o$next[3:0]$11721 $3\r7__data_o$next[3:0]$11720
+ assign $4\r7__data_o$next[3:0]$11629 $3\r7__data_o$next[3:0]$11628
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r7__data_o$next[3:0]$11722 \reg
+ assign $5\r7__data_o$next[3:0]$11630 \reg
case
- assign $5\r7__data_o$next[3:0]$11722 $4\r7__data_o$next[3:0]$11721
+ assign $5\r7__data_o$next[3:0]$11630 $4\r7__data_o$next[3:0]$11629
end
case
- assign $1\r7__data_o$next[3:0]$11718 4'0000
+ assign $1\r7__data_o$next[3:0]$11626 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r7__data_o$next[3:0]$11723 4'0000
+ assign $6\r7__data_o$next[3:0]$11631 4'0000
case
- assign $6\r7__data_o$next[3:0]$11723 $1\r7__data_o$next[3:0]$11718
+ assign $6\r7__data_o$next[3:0]$11631 $1\r7__data_o$next[3:0]$11626
end
sync always
- update \r7__data_o$next $0\r7__data_o$next[3:0]$11717
+ update \r7__data_o$next $0\r7__data_o$next[3:0]$11625
end
- attribute \src "libresoc.v:181401.3-181430.6"
- process $proc$libresoc.v:181401$11724
+ attribute \src "libresoc.v:179154.3-179183.6"
+ process $proc$libresoc.v:179154$11632
assign { } { }
assign { } { }
- assign $0\wr_detect$10[0:0]$11725 $1\wr_detect$10[0:0]$11726
- attribute \src "libresoc.v:181402.5-181402.29"
+ assign $0\wr_detect$10[0:0]$11633 $1\wr_detect$10[0:0]$11634
+ attribute \src "libresoc.v:179155.5-179155.29"
switch \initial
- attribute \src "libresoc.v:181402.9-181402.17"
+ attribute \src "libresoc.v:179155.9-179155.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$10[0:0]$11726 $4\wr_detect$10[0:0]$11729
+ assign $1\wr_detect$10[0:0]$11634 $4\wr_detect$10[0:0]$11637
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$10[0:0]$11727 1'1
+ assign $2\wr_detect$10[0:0]$11635 1'1
case
- assign $2\wr_detect$10[0:0]$11727 1'0
+ assign $2\wr_detect$10[0:0]$11635 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$10[0:0]$11728 1'1
+ assign $3\wr_detect$10[0:0]$11636 1'1
case
- assign $3\wr_detect$10[0:0]$11728 $2\wr_detect$10[0:0]$11727
+ assign $3\wr_detect$10[0:0]$11636 $2\wr_detect$10[0:0]$11635
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$10[0:0]$11729 1'1
+ assign $4\wr_detect$10[0:0]$11637 1'1
case
- assign $4\wr_detect$10[0:0]$11729 $3\wr_detect$10[0:0]$11728
+ assign $4\wr_detect$10[0:0]$11637 $3\wr_detect$10[0:0]$11636
end
case
- assign $1\wr_detect$10[0:0]$11726 1'0
+ assign $1\wr_detect$10[0:0]$11634 1'0
end
sync always
- update \wr_detect$10 $0\wr_detect$10[0:0]$11725
+ update \wr_detect$10 $0\wr_detect$10[0:0]$11633
end
- attribute \src "libresoc.v:181431.3-181470.6"
- process $proc$libresoc.v:181431$11730
+ attribute \src "libresoc.v:179184.3-179223.6"
+ process $proc$libresoc.v:179184$11638
assign { } { }
assign { } { }
assign { } { }
- assign $0\r27__data_o$next[3:0]$11731 $6\r27__data_o$next[3:0]$11737
- attribute \src "libresoc.v:181432.5-181432.29"
+ assign $0\r27__data_o$next[3:0]$11639 $6\r27__data_o$next[3:0]$11645
+ attribute \src "libresoc.v:179185.5-179185.29"
switch \initial
- attribute \src "libresoc.v:181432.9-181432.17"
+ attribute \src "libresoc.v:179185.9-179185.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\r27__data_o$next[3:0]$11732 $5\r27__data_o$next[3:0]$11736
+ assign $1\r27__data_o$next[3:0]$11640 $5\r27__data_o$next[3:0]$11644
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\r27__data_o$next[3:0]$11733 \dest17__data_i
+ assign $2\r27__data_o$next[3:0]$11641 \dest17__data_i
case
- assign $2\r27__data_o$next[3:0]$11733 4'0000
+ assign $2\r27__data_o$next[3:0]$11641 4'0000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\r27__data_o$next[3:0]$11734 \dest27__data_i
+ assign $3\r27__data_o$next[3:0]$11642 \dest27__data_i
case
- assign $3\r27__data_o$next[3:0]$11734 $2\r27__data_o$next[3:0]$11733
+ assign $3\r27__data_o$next[3:0]$11642 $2\r27__data_o$next[3:0]$11641
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\r27__data_o$next[3:0]$11735 \w7__data_i
+ assign $4\r27__data_o$next[3:0]$11643 \w7__data_i
case
- assign $4\r27__data_o$next[3:0]$11735 $3\r27__data_o$next[3:0]$11734
+ assign $4\r27__data_o$next[3:0]$11643 $3\r27__data_o$next[3:0]$11642
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
switch \$12
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\r27__data_o$next[3:0]$11736 \reg
+ assign $5\r27__data_o$next[3:0]$11644 \reg
case
- assign $5\r27__data_o$next[3:0]$11736 $4\r27__data_o$next[3:0]$11735
+ assign $5\r27__data_o$next[3:0]$11644 $4\r27__data_o$next[3:0]$11643
end
case
- assign $1\r27__data_o$next[3:0]$11732 4'0000
+ assign $1\r27__data_o$next[3:0]$11640 4'0000
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\r27__data_o$next[3:0]$11737 4'0000
+ assign $6\r27__data_o$next[3:0]$11645 4'0000
case
- assign $6\r27__data_o$next[3:0]$11737 $1\r27__data_o$next[3:0]$11732
+ assign $6\r27__data_o$next[3:0]$11645 $1\r27__data_o$next[3:0]$11640
end
sync always
- update \r27__data_o$next $0\r27__data_o$next[3:0]$11731
+ update \r27__data_o$next $0\r27__data_o$next[3:0]$11639
end
- attribute \src "libresoc.v:181471.3-181500.6"
- process $proc$libresoc.v:181471$11738
+ attribute \src "libresoc.v:179224.3-179253.6"
+ process $proc$libresoc.v:179224$11646
assign { } { }
assign { } { }
- assign $0\wr_detect$13[0:0]$11739 $1\wr_detect$13[0:0]$11740
- attribute \src "libresoc.v:181472.5-181472.29"
+ assign $0\wr_detect$13[0:0]$11647 $1\wr_detect$13[0:0]$11648
+ attribute \src "libresoc.v:179225.5-179225.29"
switch \initial
- attribute \src "libresoc.v:181472.9-181472.17"
+ attribute \src "libresoc.v:179225.9-179225.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wr_detect$13[0:0]$11740 $4\wr_detect$13[0:0]$11743
+ assign $1\wr_detect$13[0:0]$11648 $4\wr_detect$13[0:0]$11651
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest17__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\wr_detect$13[0:0]$11741 1'1
+ assign $2\wr_detect$13[0:0]$11649 1'1
case
- assign $2\wr_detect$13[0:0]$11741 1'0
+ assign $2\wr_detect$13[0:0]$11649 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \dest27__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\wr_detect$13[0:0]$11742 1'1
+ assign $3\wr_detect$13[0:0]$11650 1'1
case
- assign $3\wr_detect$13[0:0]$11742 $2\wr_detect$13[0:0]$11741
+ assign $3\wr_detect$13[0:0]$11650 $2\wr_detect$13[0:0]$11649
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74"
switch \w7__wen
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\wr_detect$13[0:0]$11743 1'1
+ assign $4\wr_detect$13[0:0]$11651 1'1
case
- assign $4\wr_detect$13[0:0]$11743 $3\wr_detect$13[0:0]$11742
+ assign $4\wr_detect$13[0:0]$11651 $3\wr_detect$13[0:0]$11650
end
case
- assign $1\wr_detect$13[0:0]$11740 1'0
+ assign $1\wr_detect$13[0:0]$11648 1'0
end
sync always
- update \wr_detect$13 $0\wr_detect$13[0:0]$11739
+ update \wr_detect$13 $0\wr_detect$13[0:0]$11647
end
- connect \$9 $not$libresoc.v:181107$11662_Y
- connect \$12 $not$libresoc.v:181108$11663_Y
- connect \$1 $not$libresoc.v:181109$11664_Y
- connect \$3 $not$libresoc.v:181110$11665_Y
- connect \$6 $not$libresoc.v:181111$11666_Y
+ connect \$9 $not$libresoc.v:178860$11570_Y
+ connect \$12 $not$libresoc.v:178861$11571_Y
+ connect \$1 $not$libresoc.v:178862$11572_Y
+ connect \$3 $not$libresoc.v:178863$11573_Y
+ connect \$6 $not$libresoc.v:178864$11574_Y
end
-attribute \src "libresoc.v:181505.1-181563.10"
+attribute \src "libresoc.v:179258.1-179316.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l"
attribute \generator "nMigen"
module \req_l
- attribute \src "libresoc.v:181506.7-181506.20"
+ attribute \src "libresoc.v:179259.7-179259.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181551.3-181559.6"
- wire width 5 $0\q_int$next[4:0]$11761
- attribute \src "libresoc.v:181549.3-181550.27"
+ attribute \src "libresoc.v:179304.3-179312.6"
+ wire width 5 $0\q_int$next[4:0]$11669
+ attribute \src "libresoc.v:179302.3-179303.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:181551.3-181559.6"
- wire width 5 $1\q_int$next[4:0]$11762
- attribute \src "libresoc.v:181528.13-181528.26"
+ attribute \src "libresoc.v:179304.3-179312.6"
+ wire width 5 $1\q_int$next[4:0]$11670
+ attribute \src "libresoc.v:179281.13-179281.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:181541.17-181541.96"
- wire width 5 $and$libresoc.v:181541$11751_Y
- attribute \src "libresoc.v:181546.17-181546.96"
- wire width 5 $and$libresoc.v:181546$11756_Y
- attribute \src "libresoc.v:181543.18-181543.93"
- wire width 5 $not$libresoc.v:181543$11753_Y
- attribute \src "libresoc.v:181545.17-181545.92"
- wire width 5 $not$libresoc.v:181545$11755_Y
- attribute \src "libresoc.v:181548.17-181548.92"
- wire width 5 $not$libresoc.v:181548$11758_Y
- attribute \src "libresoc.v:181542.18-181542.98"
- wire width 5 $or$libresoc.v:181542$11752_Y
- attribute \src "libresoc.v:181544.18-181544.99"
- wire width 5 $or$libresoc.v:181544$11754_Y
- attribute \src "libresoc.v:181547.17-181547.97"
- wire width 5 $or$libresoc.v:181547$11757_Y
+ attribute \src "libresoc.v:179294.17-179294.96"
+ wire width 5 $and$libresoc.v:179294$11659_Y
+ attribute \src "libresoc.v:179299.17-179299.96"
+ wire width 5 $and$libresoc.v:179299$11664_Y
+ attribute \src "libresoc.v:179296.18-179296.93"
+ wire width 5 $not$libresoc.v:179296$11661_Y
+ attribute \src "libresoc.v:179298.17-179298.92"
+ wire width 5 $not$libresoc.v:179298$11663_Y
+ attribute \src "libresoc.v:179301.17-179301.92"
+ wire width 5 $not$libresoc.v:179301$11666_Y
+ attribute \src "libresoc.v:179295.18-179295.98"
+ wire width 5 $or$libresoc.v:179295$11660_Y
+ attribute \src "libresoc.v:179297.18-179297.99"
+ wire width 5 $or$libresoc.v:179297$11662_Y
+ attribute \src "libresoc.v:179300.17-179300.97"
+ wire width 5 $or$libresoc.v:179300$11665_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181506.7-181506.15"
+ attribute \src "libresoc.v:179259.7-179259.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181541$11751
+ cell $and $and$libresoc.v:179294$11659
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181541$11751_Y
+ connect \Y $and$libresoc.v:179294$11659_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181546$11756
+ cell $and $and$libresoc.v:179299$11664
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181546$11756_Y
+ connect \Y $and$libresoc.v:179299$11664_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181543$11753
+ cell $not $not$libresoc.v:179296$11661
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_req
- connect \Y $not$libresoc.v:181543$11753_Y
+ connect \Y $not$libresoc.v:179296$11661_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181545$11755
+ cell $not $not$libresoc.v:179298$11663
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:181545$11755_Y
+ connect \Y $not$libresoc.v:179298$11663_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181548$11758
+ cell $not $not$libresoc.v:179301$11666
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:181548$11758_Y
+ connect \Y $not$libresoc.v:179301$11666_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181542$11752
+ cell $or $or$libresoc.v:179295$11660
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181542$11752_Y
+ connect \Y $or$libresoc.v:179295$11660_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181544$11754
+ cell $or $or$libresoc.v:179297$11662
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181544$11754_Y
+ connect \Y $or$libresoc.v:179297$11662_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181547$11757
+ cell $or $or$libresoc.v:179300$11665
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181547$11757_Y
+ connect \Y $or$libresoc.v:179300$11665_Y
end
- attribute \src "libresoc.v:181506.7-181506.20"
- process $proc$libresoc.v:181506$11763
+ attribute \src "libresoc.v:179259.7-179259.20"
+ process $proc$libresoc.v:179259$11671
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181528.13-181528.26"
- process $proc$libresoc.v:181528$11764
+ attribute \src "libresoc.v:179281.13-179281.26"
+ process $proc$libresoc.v:179281$11672
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:181549.3-181550.27"
- process $proc$libresoc.v:181549$11759
+ attribute \src "libresoc.v:179302.3-179303.27"
+ process $proc$libresoc.v:179302$11667
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:181551.3-181559.6"
- process $proc$libresoc.v:181551$11760
+ attribute \src "libresoc.v:179304.3-179312.6"
+ process $proc$libresoc.v:179304$11668
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$11761 $1\q_int$next[4:0]$11762
- attribute \src "libresoc.v:181552.5-181552.29"
+ assign $0\q_int$next[4:0]$11669 $1\q_int$next[4:0]$11670
+ attribute \src "libresoc.v:179305.5-179305.29"
switch \initial
- attribute \src "libresoc.v:181552.9-181552.17"
+ attribute \src "libresoc.v:179305.9-179305.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$11762 5'00000
+ assign $1\q_int$next[4:0]$11670 5'00000
case
- assign $1\q_int$next[4:0]$11762 \$5
+ assign $1\q_int$next[4:0]$11670 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$11761
+ update \q_int$next $0\q_int$next[4:0]$11669
end
- connect \$9 $and$libresoc.v:181541$11751_Y
- connect \$11 $or$libresoc.v:181542$11752_Y
- connect \$13 $not$libresoc.v:181543$11753_Y
- connect \$15 $or$libresoc.v:181544$11754_Y
- connect \$1 $not$libresoc.v:181545$11755_Y
- connect \$3 $and$libresoc.v:181546$11756_Y
- connect \$5 $or$libresoc.v:181547$11757_Y
- connect \$7 $not$libresoc.v:181548$11758_Y
+ connect \$9 $and$libresoc.v:179294$11659_Y
+ connect \$11 $or$libresoc.v:179295$11660_Y
+ connect \$13 $not$libresoc.v:179296$11661_Y
+ connect \$15 $or$libresoc.v:179297$11662_Y
+ connect \$1 $not$libresoc.v:179298$11663_Y
+ connect \$3 $and$libresoc.v:179299$11664_Y
+ connect \$5 $or$libresoc.v:179300$11665_Y
+ connect \$7 $not$libresoc.v:179301$11666_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181567.1-181625.10"
+attribute \src "libresoc.v:179320.1-179378.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l"
attribute \generator "nMigen"
module \req_l$103
- attribute \src "libresoc.v:181568.7-181568.20"
+ attribute \src "libresoc.v:179321.7-179321.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181613.3-181621.6"
- wire width 4 $0\q_int$next[3:0]$11775
- attribute \src "libresoc.v:181611.3-181612.27"
+ attribute \src "libresoc.v:179366.3-179374.6"
+ wire width 4 $0\q_int$next[3:0]$11683
+ attribute \src "libresoc.v:179364.3-179365.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:181613.3-181621.6"
- wire width 4 $1\q_int$next[3:0]$11776
- attribute \src "libresoc.v:181590.13-181590.25"
+ attribute \src "libresoc.v:179366.3-179374.6"
+ wire width 4 $1\q_int$next[3:0]$11684
+ attribute \src "libresoc.v:179343.13-179343.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:181603.17-181603.96"
- wire width 4 $and$libresoc.v:181603$11765_Y
- attribute \src "libresoc.v:181608.17-181608.96"
- wire width 4 $and$libresoc.v:181608$11770_Y
- attribute \src "libresoc.v:181605.18-181605.93"
- wire width 4 $not$libresoc.v:181605$11767_Y
- attribute \src "libresoc.v:181607.17-181607.92"
- wire width 4 $not$libresoc.v:181607$11769_Y
- attribute \src "libresoc.v:181610.17-181610.92"
- wire width 4 $not$libresoc.v:181610$11772_Y
- attribute \src "libresoc.v:181604.18-181604.98"
- wire width 4 $or$libresoc.v:181604$11766_Y
- attribute \src "libresoc.v:181606.18-181606.99"
- wire width 4 $or$libresoc.v:181606$11768_Y
- attribute \src "libresoc.v:181609.17-181609.97"
- wire width 4 $or$libresoc.v:181609$11771_Y
+ attribute \src "libresoc.v:179356.17-179356.96"
+ wire width 4 $and$libresoc.v:179356$11673_Y
+ attribute \src "libresoc.v:179361.17-179361.96"
+ wire width 4 $and$libresoc.v:179361$11678_Y
+ attribute \src "libresoc.v:179358.18-179358.93"
+ wire width 4 $not$libresoc.v:179358$11675_Y
+ attribute \src "libresoc.v:179360.17-179360.92"
+ wire width 4 $not$libresoc.v:179360$11677_Y
+ attribute \src "libresoc.v:179363.17-179363.92"
+ wire width 4 $not$libresoc.v:179363$11680_Y
+ attribute \src "libresoc.v:179357.18-179357.98"
+ wire width 4 $or$libresoc.v:179357$11674_Y
+ attribute \src "libresoc.v:179359.18-179359.99"
+ wire width 4 $or$libresoc.v:179359$11676_Y
+ attribute \src "libresoc.v:179362.17-179362.97"
+ wire width 4 $or$libresoc.v:179362$11679_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181568.7-181568.15"
+ attribute \src "libresoc.v:179321.7-179321.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181603$11765
+ cell $and $and$libresoc.v:179356$11673
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181603$11765_Y
+ connect \Y $and$libresoc.v:179356$11673_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181608$11770
+ cell $and $and$libresoc.v:179361$11678
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181608$11770_Y
+ connect \Y $and$libresoc.v:179361$11678_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181605$11767
+ cell $not $not$libresoc.v:179358$11675
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_req
- connect \Y $not$libresoc.v:181605$11767_Y
+ connect \Y $not$libresoc.v:179358$11675_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181607$11769
+ cell $not $not$libresoc.v:179360$11677
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:181607$11769_Y
+ connect \Y $not$libresoc.v:179360$11677_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181610$11772
+ cell $not $not$libresoc.v:179363$11680
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:181610$11772_Y
+ connect \Y $not$libresoc.v:179363$11680_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181604$11766
+ cell $or $or$libresoc.v:179357$11674
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181604$11766_Y
+ connect \Y $or$libresoc.v:179357$11674_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181606$11768
+ cell $or $or$libresoc.v:179359$11676
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181606$11768_Y
+ connect \Y $or$libresoc.v:179359$11676_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181609$11771
+ cell $or $or$libresoc.v:179362$11679
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181609$11771_Y
+ connect \Y $or$libresoc.v:179362$11679_Y
end
- attribute \src "libresoc.v:181568.7-181568.20"
- process $proc$libresoc.v:181568$11777
+ attribute \src "libresoc.v:179321.7-179321.20"
+ process $proc$libresoc.v:179321$11685
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181590.13-181590.25"
- process $proc$libresoc.v:181590$11778
+ attribute \src "libresoc.v:179343.13-179343.25"
+ process $proc$libresoc.v:179343$11686
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:181611.3-181612.27"
- process $proc$libresoc.v:181611$11773
+ attribute \src "libresoc.v:179364.3-179365.27"
+ process $proc$libresoc.v:179364$11681
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:181613.3-181621.6"
- process $proc$libresoc.v:181613$11774
+ attribute \src "libresoc.v:179366.3-179374.6"
+ process $proc$libresoc.v:179366$11682
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$11775 $1\q_int$next[3:0]$11776
- attribute \src "libresoc.v:181614.5-181614.29"
+ assign $0\q_int$next[3:0]$11683 $1\q_int$next[3:0]$11684
+ attribute \src "libresoc.v:179367.5-179367.29"
switch \initial
- attribute \src "libresoc.v:181614.9-181614.17"
+ attribute \src "libresoc.v:179367.9-179367.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$11776 4'0000
+ assign $1\q_int$next[3:0]$11684 4'0000
case
- assign $1\q_int$next[3:0]$11776 \$5
+ assign $1\q_int$next[3:0]$11684 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$11775
+ update \q_int$next $0\q_int$next[3:0]$11683
end
- connect \$9 $and$libresoc.v:181603$11765_Y
- connect \$11 $or$libresoc.v:181604$11766_Y
- connect \$13 $not$libresoc.v:181605$11767_Y
- connect \$15 $or$libresoc.v:181606$11768_Y
- connect \$1 $not$libresoc.v:181607$11769_Y
- connect \$3 $and$libresoc.v:181608$11770_Y
- connect \$5 $or$libresoc.v:181609$11771_Y
- connect \$7 $not$libresoc.v:181610$11772_Y
+ connect \$9 $and$libresoc.v:179356$11673_Y
+ connect \$11 $or$libresoc.v:179357$11674_Y
+ connect \$13 $not$libresoc.v:179358$11675_Y
+ connect \$15 $or$libresoc.v:179359$11676_Y
+ connect \$1 $not$libresoc.v:179360$11677_Y
+ connect \$3 $and$libresoc.v:179361$11678_Y
+ connect \$5 $or$libresoc.v:179362$11679_Y
+ connect \$7 $not$libresoc.v:179363$11680_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181629.1-181687.10"
+attribute \src "libresoc.v:179382.1-179440.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l"
attribute \generator "nMigen"
module \req_l$12
- attribute \src "libresoc.v:181630.7-181630.20"
+ attribute \src "libresoc.v:179383.7-179383.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181675.3-181683.6"
- wire width 3 $0\q_int$next[2:0]$11789
- attribute \src "libresoc.v:181673.3-181674.27"
+ attribute \src "libresoc.v:179428.3-179436.6"
+ wire width 3 $0\q_int$next[2:0]$11697
+ attribute \src "libresoc.v:179426.3-179427.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:181675.3-181683.6"
- wire width 3 $1\q_int$next[2:0]$11790
- attribute \src "libresoc.v:181652.13-181652.25"
+ attribute \src "libresoc.v:179428.3-179436.6"
+ wire width 3 $1\q_int$next[2:0]$11698
+ attribute \src "libresoc.v:179405.13-179405.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:181665.17-181665.96"
- wire width 3 $and$libresoc.v:181665$11779_Y
- attribute \src "libresoc.v:181670.17-181670.96"
- wire width 3 $and$libresoc.v:181670$11784_Y
- attribute \src "libresoc.v:181667.18-181667.93"
- wire width 3 $not$libresoc.v:181667$11781_Y
- attribute \src "libresoc.v:181669.17-181669.92"
- wire width 3 $not$libresoc.v:181669$11783_Y
- attribute \src "libresoc.v:181672.17-181672.92"
- wire width 3 $not$libresoc.v:181672$11786_Y
- attribute \src "libresoc.v:181666.18-181666.98"
- wire width 3 $or$libresoc.v:181666$11780_Y
- attribute \src "libresoc.v:181668.18-181668.99"
- wire width 3 $or$libresoc.v:181668$11782_Y
- attribute \src "libresoc.v:181671.17-181671.97"
- wire width 3 $or$libresoc.v:181671$11785_Y
+ attribute \src "libresoc.v:179418.17-179418.96"
+ wire width 3 $and$libresoc.v:179418$11687_Y
+ attribute \src "libresoc.v:179423.17-179423.96"
+ wire width 3 $and$libresoc.v:179423$11692_Y
+ attribute \src "libresoc.v:179420.18-179420.93"
+ wire width 3 $not$libresoc.v:179420$11689_Y
+ attribute \src "libresoc.v:179422.17-179422.92"
+ wire width 3 $not$libresoc.v:179422$11691_Y
+ attribute \src "libresoc.v:179425.17-179425.92"
+ wire width 3 $not$libresoc.v:179425$11694_Y
+ attribute \src "libresoc.v:179419.18-179419.98"
+ wire width 3 $or$libresoc.v:179419$11688_Y
+ attribute \src "libresoc.v:179421.18-179421.99"
+ wire width 3 $or$libresoc.v:179421$11690_Y
+ attribute \src "libresoc.v:179424.17-179424.97"
+ wire width 3 $or$libresoc.v:179424$11693_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181630.7-181630.15"
+ attribute \src "libresoc.v:179383.7-179383.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181665$11779
+ cell $and $and$libresoc.v:179418$11687
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181665$11779_Y
+ connect \Y $and$libresoc.v:179418$11687_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181670$11784
+ cell $and $and$libresoc.v:179423$11692
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181670$11784_Y
+ connect \Y $and$libresoc.v:179423$11692_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181667$11781
+ cell $not $not$libresoc.v:179420$11689
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:181667$11781_Y
+ connect \Y $not$libresoc.v:179420$11689_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181669$11783
+ cell $not $not$libresoc.v:179422$11691
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181669$11783_Y
+ connect \Y $not$libresoc.v:179422$11691_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181672$11786
+ cell $not $not$libresoc.v:179425$11694
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181672$11786_Y
+ connect \Y $not$libresoc.v:179425$11694_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181666$11780
+ cell $or $or$libresoc.v:179419$11688
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181666$11780_Y
+ connect \Y $or$libresoc.v:179419$11688_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181668$11782
+ cell $or $or$libresoc.v:179421$11690
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181668$11782_Y
+ connect \Y $or$libresoc.v:179421$11690_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181671$11785
+ cell $or $or$libresoc.v:179424$11693
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181671$11785_Y
+ connect \Y $or$libresoc.v:179424$11693_Y
end
- attribute \src "libresoc.v:181630.7-181630.20"
- process $proc$libresoc.v:181630$11791
+ attribute \src "libresoc.v:179383.7-179383.20"
+ process $proc$libresoc.v:179383$11699
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181652.13-181652.25"
- process $proc$libresoc.v:181652$11792
+ attribute \src "libresoc.v:179405.13-179405.25"
+ process $proc$libresoc.v:179405$11700
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:181673.3-181674.27"
- process $proc$libresoc.v:181673$11787
+ attribute \src "libresoc.v:179426.3-179427.27"
+ process $proc$libresoc.v:179426$11695
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:181675.3-181683.6"
- process $proc$libresoc.v:181675$11788
+ attribute \src "libresoc.v:179428.3-179436.6"
+ process $proc$libresoc.v:179428$11696
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11789 $1\q_int$next[2:0]$11790
- attribute \src "libresoc.v:181676.5-181676.29"
+ assign $0\q_int$next[2:0]$11697 $1\q_int$next[2:0]$11698
+ attribute \src "libresoc.v:179429.5-179429.29"
switch \initial
- attribute \src "libresoc.v:181676.9-181676.17"
+ attribute \src "libresoc.v:179429.9-179429.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11790 3'000
+ assign $1\q_int$next[2:0]$11698 3'000
case
- assign $1\q_int$next[2:0]$11790 \$5
+ assign $1\q_int$next[2:0]$11698 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11789
+ update \q_int$next $0\q_int$next[2:0]$11697
end
- connect \$9 $and$libresoc.v:181665$11779_Y
- connect \$11 $or$libresoc.v:181666$11780_Y
- connect \$13 $not$libresoc.v:181667$11781_Y
- connect \$15 $or$libresoc.v:181668$11782_Y
- connect \$1 $not$libresoc.v:181669$11783_Y
- connect \$3 $and$libresoc.v:181670$11784_Y
- connect \$5 $or$libresoc.v:181671$11785_Y
- connect \$7 $not$libresoc.v:181672$11786_Y
+ connect \$9 $and$libresoc.v:179418$11687_Y
+ connect \$11 $or$libresoc.v:179419$11688_Y
+ connect \$13 $not$libresoc.v:179420$11689_Y
+ connect \$15 $or$libresoc.v:179421$11690_Y
+ connect \$1 $not$libresoc.v:179422$11691_Y
+ connect \$3 $and$libresoc.v:179423$11692_Y
+ connect \$5 $or$libresoc.v:179424$11693_Y
+ connect \$7 $not$libresoc.v:179425$11694_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181691.1-181749.10"
+attribute \src "libresoc.v:179444.1-179502.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l"
attribute \generator "nMigen"
module \req_l$121
- attribute \src "libresoc.v:181692.7-181692.20"
+ attribute \src "libresoc.v:179445.7-179445.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181737.3-181745.6"
- wire width 3 $0\q_int$next[2:0]$11803
- attribute \src "libresoc.v:181735.3-181736.27"
+ attribute \src "libresoc.v:179490.3-179498.6"
+ wire width 3 $0\q_int$next[2:0]$11711
+ attribute \src "libresoc.v:179488.3-179489.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:181737.3-181745.6"
- wire width 3 $1\q_int$next[2:0]$11804
- attribute \src "libresoc.v:181714.13-181714.25"
+ attribute \src "libresoc.v:179490.3-179498.6"
+ wire width 3 $1\q_int$next[2:0]$11712
+ attribute \src "libresoc.v:179467.13-179467.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:181727.17-181727.96"
- wire width 3 $and$libresoc.v:181727$11793_Y
- attribute \src "libresoc.v:181732.17-181732.96"
- wire width 3 $and$libresoc.v:181732$11798_Y
- attribute \src "libresoc.v:181729.18-181729.93"
- wire width 3 $not$libresoc.v:181729$11795_Y
- attribute \src "libresoc.v:181731.17-181731.92"
- wire width 3 $not$libresoc.v:181731$11797_Y
- attribute \src "libresoc.v:181734.17-181734.92"
- wire width 3 $not$libresoc.v:181734$11800_Y
- attribute \src "libresoc.v:181728.18-181728.98"
- wire width 3 $or$libresoc.v:181728$11794_Y
- attribute \src "libresoc.v:181730.18-181730.99"
- wire width 3 $or$libresoc.v:181730$11796_Y
- attribute \src "libresoc.v:181733.17-181733.97"
- wire width 3 $or$libresoc.v:181733$11799_Y
+ attribute \src "libresoc.v:179480.17-179480.96"
+ wire width 3 $and$libresoc.v:179480$11701_Y
+ attribute \src "libresoc.v:179485.17-179485.96"
+ wire width 3 $and$libresoc.v:179485$11706_Y
+ attribute \src "libresoc.v:179482.18-179482.93"
+ wire width 3 $not$libresoc.v:179482$11703_Y
+ attribute \src "libresoc.v:179484.17-179484.92"
+ wire width 3 $not$libresoc.v:179484$11705_Y
+ attribute \src "libresoc.v:179487.17-179487.92"
+ wire width 3 $not$libresoc.v:179487$11708_Y
+ attribute \src "libresoc.v:179481.18-179481.98"
+ wire width 3 $or$libresoc.v:179481$11702_Y
+ attribute \src "libresoc.v:179483.18-179483.99"
+ wire width 3 $or$libresoc.v:179483$11704_Y
+ attribute \src "libresoc.v:179486.17-179486.97"
+ wire width 3 $or$libresoc.v:179486$11707_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181692.7-181692.15"
+ attribute \src "libresoc.v:179445.7-179445.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181727$11793
+ cell $and $and$libresoc.v:179480$11701
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181727$11793_Y
+ connect \Y $and$libresoc.v:179480$11701_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181732$11798
+ cell $and $and$libresoc.v:179485$11706
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181732$11798_Y
+ connect \Y $and$libresoc.v:179485$11706_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181729$11795
+ cell $not $not$libresoc.v:179482$11703
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:181729$11795_Y
+ connect \Y $not$libresoc.v:179482$11703_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181731$11797
+ cell $not $not$libresoc.v:179484$11705
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181731$11797_Y
+ connect \Y $not$libresoc.v:179484$11705_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181734$11800
+ cell $not $not$libresoc.v:179487$11708
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181734$11800_Y
+ connect \Y $not$libresoc.v:179487$11708_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181728$11794
+ cell $or $or$libresoc.v:179481$11702
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181728$11794_Y
+ connect \Y $or$libresoc.v:179481$11702_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181730$11796
+ cell $or $or$libresoc.v:179483$11704
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181730$11796_Y
+ connect \Y $or$libresoc.v:179483$11704_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181733$11799
+ cell $or $or$libresoc.v:179486$11707
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181733$11799_Y
+ connect \Y $or$libresoc.v:179486$11707_Y
end
- attribute \src "libresoc.v:181692.7-181692.20"
- process $proc$libresoc.v:181692$11805
+ attribute \src "libresoc.v:179445.7-179445.20"
+ process $proc$libresoc.v:179445$11713
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181714.13-181714.25"
- process $proc$libresoc.v:181714$11806
+ attribute \src "libresoc.v:179467.13-179467.25"
+ process $proc$libresoc.v:179467$11714
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:181735.3-181736.27"
- process $proc$libresoc.v:181735$11801
+ attribute \src "libresoc.v:179488.3-179489.27"
+ process $proc$libresoc.v:179488$11709
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:181737.3-181745.6"
- process $proc$libresoc.v:181737$11802
+ attribute \src "libresoc.v:179490.3-179498.6"
+ process $proc$libresoc.v:179490$11710
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11803 $1\q_int$next[2:0]$11804
- attribute \src "libresoc.v:181738.5-181738.29"
+ assign $0\q_int$next[2:0]$11711 $1\q_int$next[2:0]$11712
+ attribute \src "libresoc.v:179491.5-179491.29"
switch \initial
- attribute \src "libresoc.v:181738.9-181738.17"
+ attribute \src "libresoc.v:179491.9-179491.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11804 3'000
+ assign $1\q_int$next[2:0]$11712 3'000
case
- assign $1\q_int$next[2:0]$11804 \$5
+ assign $1\q_int$next[2:0]$11712 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11803
+ update \q_int$next $0\q_int$next[2:0]$11711
end
- connect \$9 $and$libresoc.v:181727$11793_Y
- connect \$11 $or$libresoc.v:181728$11794_Y
- connect \$13 $not$libresoc.v:181729$11795_Y
- connect \$15 $or$libresoc.v:181730$11796_Y
- connect \$1 $not$libresoc.v:181731$11797_Y
- connect \$3 $and$libresoc.v:181732$11798_Y
- connect \$5 $or$libresoc.v:181733$11799_Y
- connect \$7 $not$libresoc.v:181734$11800_Y
+ connect \$9 $and$libresoc.v:179480$11701_Y
+ connect \$11 $or$libresoc.v:179481$11702_Y
+ connect \$13 $not$libresoc.v:179482$11703_Y
+ connect \$15 $or$libresoc.v:179483$11704_Y
+ connect \$1 $not$libresoc.v:179484$11705_Y
+ connect \$3 $and$libresoc.v:179485$11706_Y
+ connect \$5 $or$libresoc.v:179486$11707_Y
+ connect \$7 $not$libresoc.v:179487$11708_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181753.1-181811.10"
+attribute \src "libresoc.v:179506.1-179564.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l"
attribute \generator "nMigen"
module \req_l$25
- attribute \src "libresoc.v:181754.7-181754.20"
+ attribute \src "libresoc.v:179507.7-179507.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181799.3-181807.6"
- wire width 3 $0\q_int$next[2:0]$11817
- attribute \src "libresoc.v:181797.3-181798.27"
+ attribute \src "libresoc.v:179552.3-179560.6"
+ wire width 3 $0\q_int$next[2:0]$11725
+ attribute \src "libresoc.v:179550.3-179551.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:181799.3-181807.6"
- wire width 3 $1\q_int$next[2:0]$11818
- attribute \src "libresoc.v:181776.13-181776.25"
+ attribute \src "libresoc.v:179552.3-179560.6"
+ wire width 3 $1\q_int$next[2:0]$11726
+ attribute \src "libresoc.v:179529.13-179529.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:181789.17-181789.96"
- wire width 3 $and$libresoc.v:181789$11807_Y
- attribute \src "libresoc.v:181794.17-181794.96"
- wire width 3 $and$libresoc.v:181794$11812_Y
- attribute \src "libresoc.v:181791.18-181791.93"
- wire width 3 $not$libresoc.v:181791$11809_Y
- attribute \src "libresoc.v:181793.17-181793.92"
- wire width 3 $not$libresoc.v:181793$11811_Y
- attribute \src "libresoc.v:181796.17-181796.92"
- wire width 3 $not$libresoc.v:181796$11814_Y
- attribute \src "libresoc.v:181790.18-181790.98"
- wire width 3 $or$libresoc.v:181790$11808_Y
- attribute \src "libresoc.v:181792.18-181792.99"
- wire width 3 $or$libresoc.v:181792$11810_Y
- attribute \src "libresoc.v:181795.17-181795.97"
- wire width 3 $or$libresoc.v:181795$11813_Y
+ attribute \src "libresoc.v:179542.17-179542.96"
+ wire width 3 $and$libresoc.v:179542$11715_Y
+ attribute \src "libresoc.v:179547.17-179547.96"
+ wire width 3 $and$libresoc.v:179547$11720_Y
+ attribute \src "libresoc.v:179544.18-179544.93"
+ wire width 3 $not$libresoc.v:179544$11717_Y
+ attribute \src "libresoc.v:179546.17-179546.92"
+ wire width 3 $not$libresoc.v:179546$11719_Y
+ attribute \src "libresoc.v:179549.17-179549.92"
+ wire width 3 $not$libresoc.v:179549$11722_Y
+ attribute \src "libresoc.v:179543.18-179543.98"
+ wire width 3 $or$libresoc.v:179543$11716_Y
+ attribute \src "libresoc.v:179545.18-179545.99"
+ wire width 3 $or$libresoc.v:179545$11718_Y
+ attribute \src "libresoc.v:179548.17-179548.97"
+ wire width 3 $or$libresoc.v:179548$11721_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181754.7-181754.15"
+ attribute \src "libresoc.v:179507.7-179507.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181789$11807
+ cell $and $and$libresoc.v:179542$11715
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181789$11807_Y
+ connect \Y $and$libresoc.v:179542$11715_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181794$11812
+ cell $and $and$libresoc.v:179547$11720
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181794$11812_Y
+ connect \Y $and$libresoc.v:179547$11720_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181791$11809
+ cell $not $not$libresoc.v:179544$11717
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_req
- connect \Y $not$libresoc.v:181791$11809_Y
+ connect \Y $not$libresoc.v:179544$11717_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181793$11811
+ cell $not $not$libresoc.v:179546$11719
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181793$11811_Y
+ connect \Y $not$libresoc.v:179546$11719_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181796$11814
+ cell $not $not$libresoc.v:179549$11722
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_req
- connect \Y $not$libresoc.v:181796$11814_Y
+ connect \Y $not$libresoc.v:179549$11722_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181790$11808
+ cell $or $or$libresoc.v:179543$11716
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181790$11808_Y
+ connect \Y $or$libresoc.v:179543$11716_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181792$11810
+ cell $or $or$libresoc.v:179545$11718
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181792$11810_Y
+ connect \Y $or$libresoc.v:179545$11718_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181795$11813
+ cell $or $or$libresoc.v:179548$11721
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181795$11813_Y
+ connect \Y $or$libresoc.v:179548$11721_Y
end
- attribute \src "libresoc.v:181754.7-181754.20"
- process $proc$libresoc.v:181754$11819
+ attribute \src "libresoc.v:179507.7-179507.20"
+ process $proc$libresoc.v:179507$11727
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181776.13-181776.25"
- process $proc$libresoc.v:181776$11820
+ attribute \src "libresoc.v:179529.13-179529.25"
+ process $proc$libresoc.v:179529$11728
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:181797.3-181798.27"
- process $proc$libresoc.v:181797$11815
+ attribute \src "libresoc.v:179550.3-179551.27"
+ process $proc$libresoc.v:179550$11723
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:181799.3-181807.6"
- process $proc$libresoc.v:181799$11816
+ attribute \src "libresoc.v:179552.3-179560.6"
+ process $proc$libresoc.v:179552$11724
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$11817 $1\q_int$next[2:0]$11818
- attribute \src "libresoc.v:181800.5-181800.29"
+ assign $0\q_int$next[2:0]$11725 $1\q_int$next[2:0]$11726
+ attribute \src "libresoc.v:179553.5-179553.29"
switch \initial
- attribute \src "libresoc.v:181800.9-181800.17"
+ attribute \src "libresoc.v:179553.9-179553.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$11818 3'000
+ assign $1\q_int$next[2:0]$11726 3'000
case
- assign $1\q_int$next[2:0]$11818 \$5
+ assign $1\q_int$next[2:0]$11726 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$11817
+ update \q_int$next $0\q_int$next[2:0]$11725
end
- connect \$9 $and$libresoc.v:181789$11807_Y
- connect \$11 $or$libresoc.v:181790$11808_Y
- connect \$13 $not$libresoc.v:181791$11809_Y
- connect \$15 $or$libresoc.v:181792$11810_Y
- connect \$1 $not$libresoc.v:181793$11811_Y
- connect \$3 $and$libresoc.v:181794$11812_Y
- connect \$5 $or$libresoc.v:181795$11813_Y
- connect \$7 $not$libresoc.v:181796$11814_Y
+ connect \$9 $and$libresoc.v:179542$11715_Y
+ connect \$11 $or$libresoc.v:179543$11716_Y
+ connect \$13 $not$libresoc.v:179544$11717_Y
+ connect \$15 $or$libresoc.v:179545$11718_Y
+ connect \$1 $not$libresoc.v:179546$11719_Y
+ connect \$3 $and$libresoc.v:179547$11720_Y
+ connect \$5 $or$libresoc.v:179548$11721_Y
+ connect \$7 $not$libresoc.v:179549$11722_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181815.1-181873.10"
+attribute \src "libresoc.v:179568.1-179626.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l"
attribute \generator "nMigen"
module \req_l$41
- attribute \src "libresoc.v:181816.7-181816.20"
+ attribute \src "libresoc.v:179569.7-179569.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181861.3-181869.6"
- wire width 5 $0\q_int$next[4:0]$11831
- attribute \src "libresoc.v:181859.3-181860.27"
+ attribute \src "libresoc.v:179614.3-179622.6"
+ wire width 5 $0\q_int$next[4:0]$11739
+ attribute \src "libresoc.v:179612.3-179613.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:181861.3-181869.6"
- wire width 5 $1\q_int$next[4:0]$11832
- attribute \src "libresoc.v:181838.13-181838.26"
+ attribute \src "libresoc.v:179614.3-179622.6"
+ wire width 5 $1\q_int$next[4:0]$11740
+ attribute \src "libresoc.v:179591.13-179591.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:181851.17-181851.96"
- wire width 5 $and$libresoc.v:181851$11821_Y
- attribute \src "libresoc.v:181856.17-181856.96"
- wire width 5 $and$libresoc.v:181856$11826_Y
- attribute \src "libresoc.v:181853.18-181853.93"
- wire width 5 $not$libresoc.v:181853$11823_Y
- attribute \src "libresoc.v:181855.17-181855.92"
- wire width 5 $not$libresoc.v:181855$11825_Y
- attribute \src "libresoc.v:181858.17-181858.92"
- wire width 5 $not$libresoc.v:181858$11828_Y
- attribute \src "libresoc.v:181852.18-181852.98"
- wire width 5 $or$libresoc.v:181852$11822_Y
- attribute \src "libresoc.v:181854.18-181854.99"
- wire width 5 $or$libresoc.v:181854$11824_Y
- attribute \src "libresoc.v:181857.17-181857.97"
- wire width 5 $or$libresoc.v:181857$11827_Y
+ attribute \src "libresoc.v:179604.17-179604.96"
+ wire width 5 $and$libresoc.v:179604$11729_Y
+ attribute \src "libresoc.v:179609.17-179609.96"
+ wire width 5 $and$libresoc.v:179609$11734_Y
+ attribute \src "libresoc.v:179606.18-179606.93"
+ wire width 5 $not$libresoc.v:179606$11731_Y
+ attribute \src "libresoc.v:179608.17-179608.92"
+ wire width 5 $not$libresoc.v:179608$11733_Y
+ attribute \src "libresoc.v:179611.17-179611.92"
+ wire width 5 $not$libresoc.v:179611$11736_Y
+ attribute \src "libresoc.v:179605.18-179605.98"
+ wire width 5 $or$libresoc.v:179605$11730_Y
+ attribute \src "libresoc.v:179607.18-179607.99"
+ wire width 5 $or$libresoc.v:179607$11732_Y
+ attribute \src "libresoc.v:179610.17-179610.97"
+ wire width 5 $or$libresoc.v:179610$11735_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181816.7-181816.15"
+ attribute \src "libresoc.v:179569.7-179569.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181851$11821
+ cell $and $and$libresoc.v:179604$11729
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181851$11821_Y
+ connect \Y $and$libresoc.v:179604$11729_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181856$11826
+ cell $and $and$libresoc.v:179609$11734
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181856$11826_Y
+ connect \Y $and$libresoc.v:179609$11734_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181853$11823
+ cell $not $not$libresoc.v:179606$11731
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_req
- connect \Y $not$libresoc.v:181853$11823_Y
+ connect \Y $not$libresoc.v:179606$11731_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181855$11825
+ cell $not $not$libresoc.v:179608$11733
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:181855$11825_Y
+ connect \Y $not$libresoc.v:179608$11733_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181858$11828
+ cell $not $not$libresoc.v:179611$11736
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_req
- connect \Y $not$libresoc.v:181858$11828_Y
+ connect \Y $not$libresoc.v:179611$11736_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181852$11822
+ cell $or $or$libresoc.v:179605$11730
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181852$11822_Y
+ connect \Y $or$libresoc.v:179605$11730_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181854$11824
+ cell $or $or$libresoc.v:179607$11732
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181854$11824_Y
+ connect \Y $or$libresoc.v:179607$11732_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181857$11827
+ cell $or $or$libresoc.v:179610$11735
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181857$11827_Y
+ connect \Y $or$libresoc.v:179610$11735_Y
end
- attribute \src "libresoc.v:181816.7-181816.20"
- process $proc$libresoc.v:181816$11833
+ attribute \src "libresoc.v:179569.7-179569.20"
+ process $proc$libresoc.v:179569$11741
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181838.13-181838.26"
- process $proc$libresoc.v:181838$11834
+ attribute \src "libresoc.v:179591.13-179591.26"
+ process $proc$libresoc.v:179591$11742
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:181859.3-181860.27"
- process $proc$libresoc.v:181859$11829
+ attribute \src "libresoc.v:179612.3-179613.27"
+ process $proc$libresoc.v:179612$11737
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:181861.3-181869.6"
- process $proc$libresoc.v:181861$11830
+ attribute \src "libresoc.v:179614.3-179622.6"
+ process $proc$libresoc.v:179614$11738
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$11831 $1\q_int$next[4:0]$11832
- attribute \src "libresoc.v:181862.5-181862.29"
+ assign $0\q_int$next[4:0]$11739 $1\q_int$next[4:0]$11740
+ attribute \src "libresoc.v:179615.5-179615.29"
switch \initial
- attribute \src "libresoc.v:181862.9-181862.17"
+ attribute \src "libresoc.v:179615.9-179615.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$11832 5'00000
+ assign $1\q_int$next[4:0]$11740 5'00000
case
- assign $1\q_int$next[4:0]$11832 \$5
+ assign $1\q_int$next[4:0]$11740 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$11831
+ update \q_int$next $0\q_int$next[4:0]$11739
end
- connect \$9 $and$libresoc.v:181851$11821_Y
- connect \$11 $or$libresoc.v:181852$11822_Y
- connect \$13 $not$libresoc.v:181853$11823_Y
- connect \$15 $or$libresoc.v:181854$11824_Y
- connect \$1 $not$libresoc.v:181855$11825_Y
- connect \$3 $and$libresoc.v:181856$11826_Y
- connect \$5 $or$libresoc.v:181857$11827_Y
- connect \$7 $not$libresoc.v:181858$11828_Y
+ connect \$9 $and$libresoc.v:179604$11729_Y
+ connect \$11 $or$libresoc.v:179605$11730_Y
+ connect \$13 $not$libresoc.v:179606$11731_Y
+ connect \$15 $or$libresoc.v:179607$11732_Y
+ connect \$1 $not$libresoc.v:179608$11733_Y
+ connect \$3 $and$libresoc.v:179609$11734_Y
+ connect \$5 $or$libresoc.v:179610$11735_Y
+ connect \$7 $not$libresoc.v:179611$11736_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181877.1-181935.10"
+attribute \src "libresoc.v:179630.1-179688.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l"
attribute \generator "nMigen"
module \req_l$57
- attribute \src "libresoc.v:181878.7-181878.20"
+ attribute \src "libresoc.v:179631.7-179631.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181923.3-181931.6"
- wire width 2 $0\q_int$next[1:0]$11845
- attribute \src "libresoc.v:181921.3-181922.27"
+ attribute \src "libresoc.v:179676.3-179684.6"
+ wire width 2 $0\q_int$next[1:0]$11753
+ attribute \src "libresoc.v:179674.3-179675.27"
wire width 2 $0\q_int[1:0]
- attribute \src "libresoc.v:181923.3-181931.6"
- wire width 2 $1\q_int$next[1:0]$11846
- attribute \src "libresoc.v:181900.13-181900.25"
+ attribute \src "libresoc.v:179676.3-179684.6"
+ wire width 2 $1\q_int$next[1:0]$11754
+ attribute \src "libresoc.v:179653.13-179653.25"
wire width 2 $1\q_int[1:0]
- attribute \src "libresoc.v:181913.17-181913.96"
- wire width 2 $and$libresoc.v:181913$11835_Y
- attribute \src "libresoc.v:181918.17-181918.96"
- wire width 2 $and$libresoc.v:181918$11840_Y
- attribute \src "libresoc.v:181915.18-181915.93"
- wire width 2 $not$libresoc.v:181915$11837_Y
- attribute \src "libresoc.v:181917.17-181917.92"
- wire width 2 $not$libresoc.v:181917$11839_Y
- attribute \src "libresoc.v:181920.17-181920.92"
- wire width 2 $not$libresoc.v:181920$11842_Y
- attribute \src "libresoc.v:181914.18-181914.98"
- wire width 2 $or$libresoc.v:181914$11836_Y
- attribute \src "libresoc.v:181916.18-181916.99"
- wire width 2 $or$libresoc.v:181916$11838_Y
- attribute \src "libresoc.v:181919.17-181919.97"
- wire width 2 $or$libresoc.v:181919$11841_Y
+ attribute \src "libresoc.v:179666.17-179666.96"
+ wire width 2 $and$libresoc.v:179666$11743_Y
+ attribute \src "libresoc.v:179671.17-179671.96"
+ wire width 2 $and$libresoc.v:179671$11748_Y
+ attribute \src "libresoc.v:179668.18-179668.93"
+ wire width 2 $not$libresoc.v:179668$11745_Y
+ attribute \src "libresoc.v:179670.17-179670.92"
+ wire width 2 $not$libresoc.v:179670$11747_Y
+ attribute \src "libresoc.v:179673.17-179673.92"
+ wire width 2 $not$libresoc.v:179673$11750_Y
+ attribute \src "libresoc.v:179667.18-179667.98"
+ wire width 2 $or$libresoc.v:179667$11744_Y
+ attribute \src "libresoc.v:179669.18-179669.99"
+ wire width 2 $or$libresoc.v:179669$11746_Y
+ attribute \src "libresoc.v:179672.17-179672.97"
+ wire width 2 $or$libresoc.v:179672$11749_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181878.7-181878.15"
+ attribute \src "libresoc.v:179631.7-179631.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 2 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 2 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181913$11835
+ cell $and $and$libresoc.v:179666$11743
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181913$11835_Y
+ connect \Y $and$libresoc.v:179666$11743_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181918$11840
+ cell $and $and$libresoc.v:179671$11748
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181918$11840_Y
+ connect \Y $and$libresoc.v:179671$11748_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181915$11837
+ cell $not $not$libresoc.v:179668$11745
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \q_req
- connect \Y $not$libresoc.v:181915$11837_Y
+ connect \Y $not$libresoc.v:179668$11745_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181917$11839
+ cell $not $not$libresoc.v:179670$11747
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \r_req
- connect \Y $not$libresoc.v:181917$11839_Y
+ connect \Y $not$libresoc.v:179670$11747_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181920$11842
+ cell $not $not$libresoc.v:179673$11750
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \r_req
- connect \Y $not$libresoc.v:181920$11842_Y
+ connect \Y $not$libresoc.v:179673$11750_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181914$11836
+ cell $or $or$libresoc.v:179667$11744
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181914$11836_Y
+ connect \Y $or$libresoc.v:179667$11744_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181916$11838
+ cell $or $or$libresoc.v:179669$11746
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181916$11838_Y
+ connect \Y $or$libresoc.v:179669$11746_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181919$11841
+ cell $or $or$libresoc.v:179672$11749
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181919$11841_Y
+ connect \Y $or$libresoc.v:179672$11749_Y
end
- attribute \src "libresoc.v:181878.7-181878.20"
- process $proc$libresoc.v:181878$11847
+ attribute \src "libresoc.v:179631.7-179631.20"
+ process $proc$libresoc.v:179631$11755
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181900.13-181900.25"
- process $proc$libresoc.v:181900$11848
+ attribute \src "libresoc.v:179653.13-179653.25"
+ process $proc$libresoc.v:179653$11756
assign { } { }
assign $1\q_int[1:0] 2'00
sync always
sync init
update \q_int $1\q_int[1:0]
end
- attribute \src "libresoc.v:181921.3-181922.27"
- process $proc$libresoc.v:181921$11843
+ attribute \src "libresoc.v:179674.3-179675.27"
+ process $proc$libresoc.v:179674$11751
assign { } { }
assign $0\q_int[1:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[1:0]
end
- attribute \src "libresoc.v:181923.3-181931.6"
- process $proc$libresoc.v:181923$11844
+ attribute \src "libresoc.v:179676.3-179684.6"
+ process $proc$libresoc.v:179676$11752
assign { } { }
assign { } { }
- assign $0\q_int$next[1:0]$11845 $1\q_int$next[1:0]$11846
- attribute \src "libresoc.v:181924.5-181924.29"
+ assign $0\q_int$next[1:0]$11753 $1\q_int$next[1:0]$11754
+ attribute \src "libresoc.v:179677.5-179677.29"
switch \initial
- attribute \src "libresoc.v:181924.9-181924.17"
+ attribute \src "libresoc.v:179677.9-179677.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[1:0]$11846 2'00
+ assign $1\q_int$next[1:0]$11754 2'00
case
- assign $1\q_int$next[1:0]$11846 \$5
+ assign $1\q_int$next[1:0]$11754 \$5
end
sync always
- update \q_int$next $0\q_int$next[1:0]$11845
+ update \q_int$next $0\q_int$next[1:0]$11753
end
- connect \$9 $and$libresoc.v:181913$11835_Y
- connect \$11 $or$libresoc.v:181914$11836_Y
- connect \$13 $not$libresoc.v:181915$11837_Y
- connect \$15 $or$libresoc.v:181916$11838_Y
- connect \$1 $not$libresoc.v:181917$11839_Y
- connect \$3 $and$libresoc.v:181918$11840_Y
- connect \$5 $or$libresoc.v:181919$11841_Y
- connect \$7 $not$libresoc.v:181920$11842_Y
+ connect \$9 $and$libresoc.v:179666$11743_Y
+ connect \$11 $or$libresoc.v:179667$11744_Y
+ connect \$13 $not$libresoc.v:179668$11745_Y
+ connect \$15 $or$libresoc.v:179669$11746_Y
+ connect \$1 $not$libresoc.v:179670$11747_Y
+ connect \$3 $and$libresoc.v:179671$11748_Y
+ connect \$5 $or$libresoc.v:179672$11749_Y
+ connect \$7 $not$libresoc.v:179673$11750_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:181939.1-181997.10"
+attribute \src "libresoc.v:179692.1-179750.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l"
attribute \generator "nMigen"
module \req_l$69
- attribute \src "libresoc.v:181940.7-181940.20"
+ attribute \src "libresoc.v:179693.7-179693.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:181985.3-181993.6"
- wire width 6 $0\q_int$next[5:0]$11859
- attribute \src "libresoc.v:181983.3-181984.27"
+ attribute \src "libresoc.v:179738.3-179746.6"
+ wire width 6 $0\q_int$next[5:0]$11767
+ attribute \src "libresoc.v:179736.3-179737.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:181985.3-181993.6"
- wire width 6 $1\q_int$next[5:0]$11860
- attribute \src "libresoc.v:181962.13-181962.26"
+ attribute \src "libresoc.v:179738.3-179746.6"
+ wire width 6 $1\q_int$next[5:0]$11768
+ attribute \src "libresoc.v:179715.13-179715.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:181975.17-181975.96"
- wire width 6 $and$libresoc.v:181975$11849_Y
- attribute \src "libresoc.v:181980.17-181980.96"
- wire width 6 $and$libresoc.v:181980$11854_Y
- attribute \src "libresoc.v:181977.18-181977.93"
- wire width 6 $not$libresoc.v:181977$11851_Y
- attribute \src "libresoc.v:181979.17-181979.92"
- wire width 6 $not$libresoc.v:181979$11853_Y
- attribute \src "libresoc.v:181982.17-181982.92"
- wire width 6 $not$libresoc.v:181982$11856_Y
- attribute \src "libresoc.v:181976.18-181976.98"
- wire width 6 $or$libresoc.v:181976$11850_Y
- attribute \src "libresoc.v:181978.18-181978.99"
- wire width 6 $or$libresoc.v:181978$11852_Y
- attribute \src "libresoc.v:181981.17-181981.97"
- wire width 6 $or$libresoc.v:181981$11855_Y
+ attribute \src "libresoc.v:179728.17-179728.96"
+ wire width 6 $and$libresoc.v:179728$11757_Y
+ attribute \src "libresoc.v:179733.17-179733.96"
+ wire width 6 $and$libresoc.v:179733$11762_Y
+ attribute \src "libresoc.v:179730.18-179730.93"
+ wire width 6 $not$libresoc.v:179730$11759_Y
+ attribute \src "libresoc.v:179732.17-179732.92"
+ wire width 6 $not$libresoc.v:179732$11761_Y
+ attribute \src "libresoc.v:179735.17-179735.92"
+ wire width 6 $not$libresoc.v:179735$11764_Y
+ attribute \src "libresoc.v:179729.18-179729.98"
+ wire width 6 $or$libresoc.v:179729$11758_Y
+ attribute \src "libresoc.v:179731.18-179731.99"
+ wire width 6 $or$libresoc.v:179731$11760_Y
+ attribute \src "libresoc.v:179734.17-179734.97"
+ wire width 6 $or$libresoc.v:179734$11763_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:181940.7-181940.15"
+ attribute \src "libresoc.v:179693.7-179693.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:181975$11849
+ cell $and $and$libresoc.v:179728$11757
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:181975$11849_Y
+ connect \Y $and$libresoc.v:179728$11757_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:181980$11854
+ cell $and $and$libresoc.v:179733$11762
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:181980$11854_Y
+ connect \Y $and$libresoc.v:179733$11762_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:181977$11851
+ cell $not $not$libresoc.v:179730$11759
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_req
- connect \Y $not$libresoc.v:181977$11851_Y
+ connect \Y $not$libresoc.v:179730$11759_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:181979$11853
+ cell $not $not$libresoc.v:179732$11761
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_req
- connect \Y $not$libresoc.v:181979$11853_Y
+ connect \Y $not$libresoc.v:179732$11761_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:181982$11856
+ cell $not $not$libresoc.v:179735$11764
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_req
- connect \Y $not$libresoc.v:181982$11856_Y
+ connect \Y $not$libresoc.v:179735$11764_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:181976$11850
+ cell $or $or$libresoc.v:179729$11758
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:181976$11850_Y
+ connect \Y $or$libresoc.v:179729$11758_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:181978$11852
+ cell $or $or$libresoc.v:179731$11760
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:181978$11852_Y
+ connect \Y $or$libresoc.v:179731$11760_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:181981$11855
+ cell $or $or$libresoc.v:179734$11763
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:181981$11855_Y
+ connect \Y $or$libresoc.v:179734$11763_Y
end
- attribute \src "libresoc.v:181940.7-181940.20"
- process $proc$libresoc.v:181940$11861
+ attribute \src "libresoc.v:179693.7-179693.20"
+ process $proc$libresoc.v:179693$11769
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:181962.13-181962.26"
- process $proc$libresoc.v:181962$11862
+ attribute \src "libresoc.v:179715.13-179715.26"
+ process $proc$libresoc.v:179715$11770
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:181983.3-181984.27"
- process $proc$libresoc.v:181983$11857
+ attribute \src "libresoc.v:179736.3-179737.27"
+ process $proc$libresoc.v:179736$11765
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:181985.3-181993.6"
- process $proc$libresoc.v:181985$11858
+ attribute \src "libresoc.v:179738.3-179746.6"
+ process $proc$libresoc.v:179738$11766
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$11859 $1\q_int$next[5:0]$11860
- attribute \src "libresoc.v:181986.5-181986.29"
+ assign $0\q_int$next[5:0]$11767 $1\q_int$next[5:0]$11768
+ attribute \src "libresoc.v:179739.5-179739.29"
switch \initial
- attribute \src "libresoc.v:181986.9-181986.17"
+ attribute \src "libresoc.v:179739.9-179739.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$11860 6'000000
+ assign $1\q_int$next[5:0]$11768 6'000000
case
- assign $1\q_int$next[5:0]$11860 \$5
+ assign $1\q_int$next[5:0]$11768 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$11859
+ update \q_int$next $0\q_int$next[5:0]$11767
end
- connect \$9 $and$libresoc.v:181975$11849_Y
- connect \$11 $or$libresoc.v:181976$11850_Y
- connect \$13 $not$libresoc.v:181977$11851_Y
- connect \$15 $or$libresoc.v:181978$11852_Y
- connect \$1 $not$libresoc.v:181979$11853_Y
- connect \$3 $and$libresoc.v:181980$11854_Y
- connect \$5 $or$libresoc.v:181981$11855_Y
- connect \$7 $not$libresoc.v:181982$11856_Y
+ connect \$9 $and$libresoc.v:179728$11757_Y
+ connect \$11 $or$libresoc.v:179729$11758_Y
+ connect \$13 $not$libresoc.v:179730$11759_Y
+ connect \$15 $or$libresoc.v:179731$11760_Y
+ connect \$1 $not$libresoc.v:179732$11761_Y
+ connect \$3 $and$libresoc.v:179733$11762_Y
+ connect \$5 $or$libresoc.v:179734$11763_Y
+ connect \$7 $not$libresoc.v:179735$11764_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:182001.1-182059.10"
+attribute \src "libresoc.v:179754.1-179812.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l"
attribute \generator "nMigen"
module \req_l$86
- attribute \src "libresoc.v:182002.7-182002.20"
+ attribute \src "libresoc.v:179755.7-179755.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182047.3-182055.6"
- wire width 4 $0\q_int$next[3:0]$11873
- attribute \src "libresoc.v:182045.3-182046.27"
+ attribute \src "libresoc.v:179800.3-179808.6"
+ wire width 4 $0\q_int$next[3:0]$11781
+ attribute \src "libresoc.v:179798.3-179799.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:182047.3-182055.6"
- wire width 4 $1\q_int$next[3:0]$11874
- attribute \src "libresoc.v:182024.13-182024.25"
+ attribute \src "libresoc.v:179800.3-179808.6"
+ wire width 4 $1\q_int$next[3:0]$11782
+ attribute \src "libresoc.v:179777.13-179777.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:182037.17-182037.96"
- wire width 4 $and$libresoc.v:182037$11863_Y
- attribute \src "libresoc.v:182042.17-182042.96"
- wire width 4 $and$libresoc.v:182042$11868_Y
- attribute \src "libresoc.v:182039.18-182039.93"
- wire width 4 $not$libresoc.v:182039$11865_Y
- attribute \src "libresoc.v:182041.17-182041.92"
- wire width 4 $not$libresoc.v:182041$11867_Y
- attribute \src "libresoc.v:182044.17-182044.92"
- wire width 4 $not$libresoc.v:182044$11870_Y
- attribute \src "libresoc.v:182038.18-182038.98"
- wire width 4 $or$libresoc.v:182038$11864_Y
- attribute \src "libresoc.v:182040.18-182040.99"
- wire width 4 $or$libresoc.v:182040$11866_Y
- attribute \src "libresoc.v:182043.17-182043.97"
- wire width 4 $or$libresoc.v:182043$11869_Y
+ attribute \src "libresoc.v:179790.17-179790.96"
+ wire width 4 $and$libresoc.v:179790$11771_Y
+ attribute \src "libresoc.v:179795.17-179795.96"
+ wire width 4 $and$libresoc.v:179795$11776_Y
+ attribute \src "libresoc.v:179792.18-179792.93"
+ wire width 4 $not$libresoc.v:179792$11773_Y
+ attribute \src "libresoc.v:179794.17-179794.92"
+ wire width 4 $not$libresoc.v:179794$11775_Y
+ attribute \src "libresoc.v:179797.17-179797.92"
+ wire width 4 $not$libresoc.v:179797$11778_Y
+ attribute \src "libresoc.v:179791.18-179791.98"
+ wire width 4 $or$libresoc.v:179791$11772_Y
+ attribute \src "libresoc.v:179793.18-179793.99"
+ wire width 4 $or$libresoc.v:179793$11774_Y
+ attribute \src "libresoc.v:179796.17-179796.97"
+ wire width 4 $or$libresoc.v:179796$11777_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182002.7-182002.15"
+ attribute \src "libresoc.v:179755.7-179755.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 3 \s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:182037$11863
+ cell $and $and$libresoc.v:179790$11771
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:182037$11863_Y
+ connect \Y $and$libresoc.v:179790$11771_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182042$11868
+ cell $and $and$libresoc.v:179795$11776
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182042$11868_Y
+ connect \Y $and$libresoc.v:179795$11776_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182039$11865
+ cell $not $not$libresoc.v:179792$11773
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_req
- connect \Y $not$libresoc.v:182039$11865_Y
+ connect \Y $not$libresoc.v:179792$11773_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182041$11867
+ cell $not $not$libresoc.v:179794$11775
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:182041$11867_Y
+ connect \Y $not$libresoc.v:179794$11775_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:182044$11870
+ cell $not $not$libresoc.v:179797$11778
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_req
- connect \Y $not$libresoc.v:182044$11870_Y
+ connect \Y $not$libresoc.v:179797$11778_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:182038$11864
+ cell $or $or$libresoc.v:179791$11772
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_req
- connect \Y $or$libresoc.v:182038$11864_Y
+ connect \Y $or$libresoc.v:179791$11772_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182040$11866
+ cell $or $or$libresoc.v:179793$11774
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_req
connect \B \q_int
- connect \Y $or$libresoc.v:182040$11866_Y
+ connect \Y $or$libresoc.v:179793$11774_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182043$11869
+ cell $or $or$libresoc.v:179796$11777
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_req
- connect \Y $or$libresoc.v:182043$11869_Y
+ connect \Y $or$libresoc.v:179796$11777_Y
end
- attribute \src "libresoc.v:182002.7-182002.20"
- process $proc$libresoc.v:182002$11875
+ attribute \src "libresoc.v:179755.7-179755.20"
+ process $proc$libresoc.v:179755$11783
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182024.13-182024.25"
- process $proc$libresoc.v:182024$11876
+ attribute \src "libresoc.v:179777.13-179777.25"
+ process $proc$libresoc.v:179777$11784
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:182045.3-182046.27"
- process $proc$libresoc.v:182045$11871
+ attribute \src "libresoc.v:179798.3-179799.27"
+ process $proc$libresoc.v:179798$11779
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:182047.3-182055.6"
- process $proc$libresoc.v:182047$11872
+ attribute \src "libresoc.v:179800.3-179808.6"
+ process $proc$libresoc.v:179800$11780
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$11873 $1\q_int$next[3:0]$11874
- attribute \src "libresoc.v:182048.5-182048.29"
+ assign $0\q_int$next[3:0]$11781 $1\q_int$next[3:0]$11782
+ attribute \src "libresoc.v:179801.5-179801.29"
switch \initial
- attribute \src "libresoc.v:182048.9-182048.17"
+ attribute \src "libresoc.v:179801.9-179801.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$11874 4'0000
+ assign $1\q_int$next[3:0]$11782 4'0000
case
- assign $1\q_int$next[3:0]$11874 \$5
+ assign $1\q_int$next[3:0]$11782 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$11873
+ update \q_int$next $0\q_int$next[3:0]$11781
end
- connect \$9 $and$libresoc.v:182037$11863_Y
- connect \$11 $or$libresoc.v:182038$11864_Y
- connect \$13 $not$libresoc.v:182039$11865_Y
- connect \$15 $or$libresoc.v:182040$11866_Y
- connect \$1 $not$libresoc.v:182041$11867_Y
- connect \$3 $and$libresoc.v:182042$11868_Y
- connect \$5 $or$libresoc.v:182043$11869_Y
- connect \$7 $not$libresoc.v:182044$11870_Y
+ connect \$9 $and$libresoc.v:179790$11771_Y
+ connect \$11 $or$libresoc.v:179791$11772_Y
+ connect \$13 $not$libresoc.v:179792$11773_Y
+ connect \$15 $or$libresoc.v:179793$11774_Y
+ connect \$1 $not$libresoc.v:179794$11775_Y
+ connect \$3 $and$libresoc.v:179795$11776_Y
+ connect \$5 $or$libresoc.v:179796$11777_Y
+ connect \$7 $not$libresoc.v:179797$11778_Y
connect \qlq_req \$15
connect \qn_req \$13
connect \q_req \$11
end
-attribute \src "libresoc.v:182063.1-182112.10"
+attribute \src "libresoc.v:179816.1-179865.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l"
attribute \generator "nMigen"
module \reset_l
- attribute \src "libresoc.v:182064.7-182064.20"
+ attribute \src "libresoc.v:179817.7-179817.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182100.3-182108.6"
- wire $0\q_int$next[0:0]$11884
- attribute \src "libresoc.v:182098.3-182099.27"
+ attribute \src "libresoc.v:179853.3-179861.6"
+ wire $0\q_int$next[0:0]$11792
+ attribute \src "libresoc.v:179851.3-179852.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182100.3-182108.6"
- wire $1\q_int$next[0:0]$11885
- attribute \src "libresoc.v:182080.7-182080.19"
+ attribute \src "libresoc.v:179853.3-179861.6"
+ wire $1\q_int$next[0:0]$11793
+ attribute \src "libresoc.v:179833.7-179833.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182095.17-182095.96"
- wire $and$libresoc.v:182095$11879_Y
- attribute \src "libresoc.v:182094.17-182094.94"
- wire $not$libresoc.v:182094$11878_Y
- attribute \src "libresoc.v:182097.17-182097.94"
- wire $not$libresoc.v:182097$11881_Y
- attribute \src "libresoc.v:182093.17-182093.100"
- wire $or$libresoc.v:182093$11877_Y
- attribute \src "libresoc.v:182096.17-182096.99"
- wire $or$libresoc.v:182096$11880_Y
+ attribute \src "libresoc.v:179848.17-179848.96"
+ wire $and$libresoc.v:179848$11787_Y
+ attribute \src "libresoc.v:179847.17-179847.94"
+ wire $not$libresoc.v:179847$11786_Y
+ attribute \src "libresoc.v:179850.17-179850.94"
+ wire $not$libresoc.v:179850$11789_Y
+ attribute \src "libresoc.v:179846.17-179846.100"
+ wire $or$libresoc.v:179846$11785_Y
+ attribute \src "libresoc.v:179849.17-179849.99"
+ wire $or$libresoc.v:179849$11788_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182064.7-182064.15"
+ attribute \src "libresoc.v:179817.7-179817.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_reset
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182095$11879
+ cell $and $and$libresoc.v:179848$11787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182095$11879_Y
+ connect \Y $and$libresoc.v:179848$11787_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182094$11878
+ cell $not $not$libresoc.v:179847$11786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_reset
- connect \Y $not$libresoc.v:182094$11878_Y
+ connect \Y $not$libresoc.v:179847$11786_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182097$11881
+ cell $not $not$libresoc.v:179850$11789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_reset
- connect \Y $not$libresoc.v:182097$11881_Y
+ connect \Y $not$libresoc.v:179850$11789_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182093$11877
+ cell $or $or$libresoc.v:179846$11785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_reset
connect \B \q_int
- connect \Y $or$libresoc.v:182093$11877_Y
+ connect \Y $or$libresoc.v:179846$11785_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182096$11880
+ cell $or $or$libresoc.v:179849$11788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_reset
- connect \Y $or$libresoc.v:182096$11880_Y
+ connect \Y $or$libresoc.v:179849$11788_Y
end
- attribute \src "libresoc.v:182064.7-182064.20"
- process $proc$libresoc.v:182064$11886
+ attribute \src "libresoc.v:179817.7-179817.20"
+ process $proc$libresoc.v:179817$11794
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182080.7-182080.19"
- process $proc$libresoc.v:182080$11887
+ attribute \src "libresoc.v:179833.7-179833.19"
+ process $proc$libresoc.v:179833$11795
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182098.3-182099.27"
- process $proc$libresoc.v:182098$11882
+ attribute \src "libresoc.v:179851.3-179852.27"
+ process $proc$libresoc.v:179851$11790
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182100.3-182108.6"
- process $proc$libresoc.v:182100$11883
+ attribute \src "libresoc.v:179853.3-179861.6"
+ process $proc$libresoc.v:179853$11791
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$11884 $1\q_int$next[0:0]$11885
- attribute \src "libresoc.v:182101.5-182101.29"
+ assign $0\q_int$next[0:0]$11792 $1\q_int$next[0:0]$11793
+ attribute \src "libresoc.v:179854.5-179854.29"
switch \initial
- attribute \src "libresoc.v:182101.9-182101.17"
+ attribute \src "libresoc.v:179854.9-179854.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$11885 1'0
+ assign $1\q_int$next[0:0]$11793 1'0
case
- assign $1\q_int$next[0:0]$11885 \$5
+ assign $1\q_int$next[0:0]$11793 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$11884
+ update \q_int$next $0\q_int$next[0:0]$11792
end
- connect \$9 $or$libresoc.v:182093$11877_Y
- connect \$1 $not$libresoc.v:182094$11878_Y
- connect \$3 $and$libresoc.v:182095$11879_Y
- connect \$5 $or$libresoc.v:182096$11880_Y
- connect \$7 $not$libresoc.v:182097$11881_Y
+ connect \$9 $or$libresoc.v:179846$11785_Y
+ connect \$1 $not$libresoc.v:179847$11786_Y
+ connect \$3 $and$libresoc.v:179848$11787_Y
+ connect \$5 $or$libresoc.v:179849$11788_Y
+ connect \$7 $not$libresoc.v:179850$11789_Y
connect \qlq_reset \$9
connect \qn_reset \$7
connect \q_reset \q_int
end
-attribute \src "libresoc.v:182116.1-182165.10"
+attribute \src "libresoc.v:179869.1-179918.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l"
attribute \generator "nMigen"
module \reset_l$131
- attribute \src "libresoc.v:182117.7-182117.20"
+ attribute \src "libresoc.v:179870.7-179870.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182153.3-182161.6"
- wire $0\q_int$next[0:0]$11895
- attribute \src "libresoc.v:182151.3-182152.27"
+ attribute \src "libresoc.v:179906.3-179914.6"
+ wire $0\q_int$next[0:0]$11803
+ attribute \src "libresoc.v:179904.3-179905.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182153.3-182161.6"
- wire $1\q_int$next[0:0]$11896
- attribute \src "libresoc.v:182133.7-182133.19"
+ attribute \src "libresoc.v:179906.3-179914.6"
+ wire $1\q_int$next[0:0]$11804
+ attribute \src "libresoc.v:179886.7-179886.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182148.17-182148.96"
- wire $and$libresoc.v:182148$11890_Y
- attribute \src "libresoc.v:182147.17-182147.94"
- wire $not$libresoc.v:182147$11889_Y
- attribute \src "libresoc.v:182150.17-182150.94"
- wire $not$libresoc.v:182150$11892_Y
- attribute \src "libresoc.v:182146.17-182146.100"
- wire $or$libresoc.v:182146$11888_Y
- attribute \src "libresoc.v:182149.17-182149.99"
- wire $or$libresoc.v:182149$11891_Y
+ attribute \src "libresoc.v:179901.17-179901.96"
+ wire $and$libresoc.v:179901$11798_Y
+ attribute \src "libresoc.v:179900.17-179900.94"
+ wire $not$libresoc.v:179900$11797_Y
+ attribute \src "libresoc.v:179903.17-179903.94"
+ wire $not$libresoc.v:179903$11800_Y
+ attribute \src "libresoc.v:179899.17-179899.100"
+ wire $or$libresoc.v:179899$11796_Y
+ attribute \src "libresoc.v:179902.17-179902.99"
+ wire $or$libresoc.v:179902$11799_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182117.7-182117.15"
+ attribute \src "libresoc.v:179870.7-179870.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_reset
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182148$11890
+ cell $and $and$libresoc.v:179901$11798
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182148$11890_Y
+ connect \Y $and$libresoc.v:179901$11798_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182147$11889
+ cell $not $not$libresoc.v:179900$11797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_reset
- connect \Y $not$libresoc.v:182147$11889_Y
+ connect \Y $not$libresoc.v:179900$11797_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182150$11892
+ cell $not $not$libresoc.v:179903$11800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_reset
- connect \Y $not$libresoc.v:182150$11892_Y
+ connect \Y $not$libresoc.v:179903$11800_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182146$11888
+ cell $or $or$libresoc.v:179899$11796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_reset
connect \B \q_int
- connect \Y $or$libresoc.v:182146$11888_Y
+ connect \Y $or$libresoc.v:179899$11796_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182149$11891
+ cell $or $or$libresoc.v:179902$11799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_reset
- connect \Y $or$libresoc.v:182149$11891_Y
+ connect \Y $or$libresoc.v:179902$11799_Y
end
- attribute \src "libresoc.v:182117.7-182117.20"
- process $proc$libresoc.v:182117$11897
+ attribute \src "libresoc.v:179870.7-179870.20"
+ process $proc$libresoc.v:179870$11805
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182133.7-182133.19"
- process $proc$libresoc.v:182133$11898
+ attribute \src "libresoc.v:179886.7-179886.19"
+ process $proc$libresoc.v:179886$11806
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182151.3-182152.27"
- process $proc$libresoc.v:182151$11893
+ attribute \src "libresoc.v:179904.3-179905.27"
+ process $proc$libresoc.v:179904$11801
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182153.3-182161.6"
- process $proc$libresoc.v:182153$11894
+ attribute \src "libresoc.v:179906.3-179914.6"
+ process $proc$libresoc.v:179906$11802
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$11895 $1\q_int$next[0:0]$11896
- attribute \src "libresoc.v:182154.5-182154.29"
+ assign $0\q_int$next[0:0]$11803 $1\q_int$next[0:0]$11804
+ attribute \src "libresoc.v:179907.5-179907.29"
switch \initial
- attribute \src "libresoc.v:182154.9-182154.17"
+ attribute \src "libresoc.v:179907.9-179907.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$11896 1'0
+ assign $1\q_int$next[0:0]$11804 1'0
case
- assign $1\q_int$next[0:0]$11896 \$5
+ assign $1\q_int$next[0:0]$11804 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$11895
+ update \q_int$next $0\q_int$next[0:0]$11803
end
- connect \$9 $or$libresoc.v:182146$11888_Y
- connect \$1 $not$libresoc.v:182147$11889_Y
- connect \$3 $and$libresoc.v:182148$11890_Y
- connect \$5 $or$libresoc.v:182149$11891_Y
- connect \$7 $not$libresoc.v:182150$11892_Y
+ connect \$9 $or$libresoc.v:179899$11796_Y
+ connect \$1 $not$libresoc.v:179900$11797_Y
+ connect \$3 $and$libresoc.v:179901$11798_Y
+ connect \$5 $or$libresoc.v:179902$11799_Y
+ connect \$7 $not$libresoc.v:179903$11800_Y
connect \qlq_reset \$9
connect \qn_reset \$7
connect \q_reset \q_int
end
-attribute \src "libresoc.v:182169.1-182756.10"
+attribute \src "libresoc.v:179922.1-180509.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask"
attribute \generator "nMigen"
module \right_mask
- attribute \src "libresoc.v:182170.7-182170.20"
+ attribute \src "libresoc.v:179923.7-179923.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire width 64 $0\mask[63:0]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $10\mask[9:9]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $11\mask[10:10]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $12\mask[11:11]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $13\mask[12:12]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $14\mask[13:13]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $15\mask[14:14]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $16\mask[15:15]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $17\mask[16:16]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $18\mask[17:17]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $19\mask[18:18]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $1\mask[0:0]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $20\mask[19:19]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $21\mask[20:20]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $22\mask[21:21]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $23\mask[22:22]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $24\mask[23:23]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $25\mask[24:24]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $26\mask[25:25]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $27\mask[26:26]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $28\mask[27:27]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $29\mask[28:28]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $2\mask[1:1]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $30\mask[29:29]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $31\mask[30:30]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $32\mask[31:31]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $33\mask[32:32]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $34\mask[33:33]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $35\mask[34:34]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $36\mask[35:35]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $37\mask[36:36]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $38\mask[37:37]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $39\mask[38:38]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $3\mask[2:2]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $40\mask[39:39]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $41\mask[40:40]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $42\mask[41:41]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $43\mask[42:42]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $44\mask[43:43]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $45\mask[44:44]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $46\mask[45:45]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $47\mask[46:46]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $48\mask[47:47]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $49\mask[48:48]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $4\mask[3:3]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $50\mask[49:49]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $51\mask[50:50]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $52\mask[51:51]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $53\mask[52:52]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $54\mask[53:53]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $55\mask[54:54]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $56\mask[55:55]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $57\mask[56:56]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $58\mask[57:57]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $59\mask[58:58]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $5\mask[4:4]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $60\mask[59:59]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $61\mask[60:60]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $62\mask[61:61]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $63\mask[62:62]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $64\mask[63:63]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $6\mask[5:5]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $7\mask[6:6]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $8\mask[7:7]
- attribute \src "libresoc.v:182368.3-182755.6"
+ attribute \src "libresoc.v:180121.3-180508.6"
wire $9\mask[8:8]
- attribute \src "libresoc.v:182304.17-182304.96"
- wire $gt$libresoc.v:182304$11899_Y
- attribute \src "libresoc.v:182305.18-182305.98"
- wire $gt$libresoc.v:182305$11900_Y
- attribute \src "libresoc.v:182306.19-182306.99"
- wire $gt$libresoc.v:182306$11901_Y
- attribute \src "libresoc.v:182307.19-182307.99"
- wire $gt$libresoc.v:182307$11902_Y
- attribute \src "libresoc.v:182308.19-182308.99"
- wire $gt$libresoc.v:182308$11903_Y
- attribute \src "libresoc.v:182309.19-182309.99"
- wire $gt$libresoc.v:182309$11904_Y
- attribute \src "libresoc.v:182310.19-182310.99"
- wire $gt$libresoc.v:182310$11905_Y
- attribute \src "libresoc.v:182311.19-182311.99"
- wire $gt$libresoc.v:182311$11906_Y
- attribute \src "libresoc.v:182312.19-182312.99"
- wire $gt$libresoc.v:182312$11907_Y
- attribute \src "libresoc.v:182313.19-182313.99"
- wire $gt$libresoc.v:182313$11908_Y
- attribute \src "libresoc.v:182314.19-182314.99"
- wire $gt$libresoc.v:182314$11909_Y
- attribute \src "libresoc.v:182315.18-182315.97"
- wire $gt$libresoc.v:182315$11910_Y
- attribute \src "libresoc.v:182316.19-182316.99"
- wire $gt$libresoc.v:182316$11911_Y
- attribute \src "libresoc.v:182317.19-182317.99"
- wire $gt$libresoc.v:182317$11912_Y
- attribute \src "libresoc.v:182318.19-182318.99"
- wire $gt$libresoc.v:182318$11913_Y
- attribute \src "libresoc.v:182319.19-182319.99"
- wire $gt$libresoc.v:182319$11914_Y
- attribute \src "libresoc.v:182320.19-182320.99"
- wire $gt$libresoc.v:182320$11915_Y
- attribute \src "libresoc.v:182321.18-182321.97"
- wire $gt$libresoc.v:182321$11916_Y
- attribute \src "libresoc.v:182322.18-182322.97"
- wire $gt$libresoc.v:182322$11917_Y
- attribute \src "libresoc.v:182323.18-182323.97"
- wire $gt$libresoc.v:182323$11918_Y
- attribute \src "libresoc.v:182324.17-182324.96"
- wire $gt$libresoc.v:182324$11919_Y
- attribute \src "libresoc.v:182325.18-182325.97"
- wire $gt$libresoc.v:182325$11920_Y
- attribute \src "libresoc.v:182326.18-182326.97"
- wire $gt$libresoc.v:182326$11921_Y
- attribute \src "libresoc.v:182327.18-182327.97"
- wire $gt$libresoc.v:182327$11922_Y
- attribute \src "libresoc.v:182328.18-182328.97"
- wire $gt$libresoc.v:182328$11923_Y
- attribute \src "libresoc.v:182329.18-182329.97"
- wire $gt$libresoc.v:182329$11924_Y
- attribute \src "libresoc.v:182330.18-182330.97"
- wire $gt$libresoc.v:182330$11925_Y
- attribute \src "libresoc.v:182331.18-182331.97"
- wire $gt$libresoc.v:182331$11926_Y
- attribute \src "libresoc.v:182332.18-182332.98"
- wire $gt$libresoc.v:182332$11927_Y
- attribute \src "libresoc.v:182333.18-182333.98"
- wire $gt$libresoc.v:182333$11928_Y
- attribute \src "libresoc.v:182334.18-182334.98"
- wire $gt$libresoc.v:182334$11929_Y
- attribute \src "libresoc.v:182335.17-182335.96"
- wire $gt$libresoc.v:182335$11930_Y
- attribute \src "libresoc.v:182336.18-182336.98"
- wire $gt$libresoc.v:182336$11931_Y
- attribute \src "libresoc.v:182337.18-182337.98"
- wire $gt$libresoc.v:182337$11932_Y
- attribute \src "libresoc.v:182338.18-182338.98"
- wire $gt$libresoc.v:182338$11933_Y
- attribute \src "libresoc.v:182339.18-182339.98"
- wire $gt$libresoc.v:182339$11934_Y
- attribute \src "libresoc.v:182340.18-182340.98"
- wire $gt$libresoc.v:182340$11935_Y
- attribute \src "libresoc.v:182341.18-182341.98"
- wire $gt$libresoc.v:182341$11936_Y
- attribute \src "libresoc.v:182342.18-182342.98"
- wire $gt$libresoc.v:182342$11937_Y
- attribute \src "libresoc.v:182343.18-182343.98"
- wire $gt$libresoc.v:182343$11938_Y
- attribute \src "libresoc.v:182344.18-182344.98"
- wire $gt$libresoc.v:182344$11939_Y
- attribute \src "libresoc.v:182345.18-182345.98"
- wire $gt$libresoc.v:182345$11940_Y
- attribute \src "libresoc.v:182346.17-182346.96"
- wire $gt$libresoc.v:182346$11941_Y
- attribute \src "libresoc.v:182347.18-182347.98"
- wire $gt$libresoc.v:182347$11942_Y
- attribute \src "libresoc.v:182348.18-182348.98"
- wire $gt$libresoc.v:182348$11943_Y
- attribute \src "libresoc.v:182349.18-182349.98"
- wire $gt$libresoc.v:182349$11944_Y
- attribute \src "libresoc.v:182350.18-182350.98"
- wire $gt$libresoc.v:182350$11945_Y
- attribute \src "libresoc.v:182351.18-182351.98"
- wire $gt$libresoc.v:182351$11946_Y
- attribute \src "libresoc.v:182352.18-182352.98"
- wire $gt$libresoc.v:182352$11947_Y
- attribute \src "libresoc.v:182353.18-182353.98"
- wire $gt$libresoc.v:182353$11948_Y
- attribute \src "libresoc.v:182354.18-182354.98"
- wire $gt$libresoc.v:182354$11949_Y
- attribute \src "libresoc.v:182355.18-182355.98"
- wire $gt$libresoc.v:182355$11950_Y
- attribute \src "libresoc.v:182356.18-182356.98"
- wire $gt$libresoc.v:182356$11951_Y
- attribute \src "libresoc.v:182357.17-182357.96"
- wire $gt$libresoc.v:182357$11952_Y
- attribute \src "libresoc.v:182358.18-182358.98"
- wire $gt$libresoc.v:182358$11953_Y
- attribute \src "libresoc.v:182359.18-182359.98"
- wire $gt$libresoc.v:182359$11954_Y
- attribute \src "libresoc.v:182360.18-182360.98"
- wire $gt$libresoc.v:182360$11955_Y
- attribute \src "libresoc.v:182361.18-182361.98"
- wire $gt$libresoc.v:182361$11956_Y
- attribute \src "libresoc.v:182362.18-182362.98"
- wire $gt$libresoc.v:182362$11957_Y
- attribute \src "libresoc.v:182363.18-182363.98"
- wire $gt$libresoc.v:182363$11958_Y
- attribute \src "libresoc.v:182364.18-182364.98"
- wire $gt$libresoc.v:182364$11959_Y
- attribute \src "libresoc.v:182365.18-182365.98"
- wire $gt$libresoc.v:182365$11960_Y
- attribute \src "libresoc.v:182366.18-182366.98"
- wire $gt$libresoc.v:182366$11961_Y
- attribute \src "libresoc.v:182367.18-182367.98"
- wire $gt$libresoc.v:182367$11962_Y
+ attribute \src "libresoc.v:180057.17-180057.96"
+ wire $gt$libresoc.v:180057$11807_Y
+ attribute \src "libresoc.v:180058.18-180058.98"
+ wire $gt$libresoc.v:180058$11808_Y
+ attribute \src "libresoc.v:180059.19-180059.99"
+ wire $gt$libresoc.v:180059$11809_Y
+ attribute \src "libresoc.v:180060.19-180060.99"
+ wire $gt$libresoc.v:180060$11810_Y
+ attribute \src "libresoc.v:180061.19-180061.99"
+ wire $gt$libresoc.v:180061$11811_Y
+ attribute \src "libresoc.v:180062.19-180062.99"
+ wire $gt$libresoc.v:180062$11812_Y
+ attribute \src "libresoc.v:180063.19-180063.99"
+ wire $gt$libresoc.v:180063$11813_Y
+ attribute \src "libresoc.v:180064.19-180064.99"
+ wire $gt$libresoc.v:180064$11814_Y
+ attribute \src "libresoc.v:180065.19-180065.99"
+ wire $gt$libresoc.v:180065$11815_Y
+ attribute \src "libresoc.v:180066.19-180066.99"
+ wire $gt$libresoc.v:180066$11816_Y
+ attribute \src "libresoc.v:180067.19-180067.99"
+ wire $gt$libresoc.v:180067$11817_Y
+ attribute \src "libresoc.v:180068.18-180068.97"
+ wire $gt$libresoc.v:180068$11818_Y
+ attribute \src "libresoc.v:180069.19-180069.99"
+ wire $gt$libresoc.v:180069$11819_Y
+ attribute \src "libresoc.v:180070.19-180070.99"
+ wire $gt$libresoc.v:180070$11820_Y
+ attribute \src "libresoc.v:180071.19-180071.99"
+ wire $gt$libresoc.v:180071$11821_Y
+ attribute \src "libresoc.v:180072.19-180072.99"
+ wire $gt$libresoc.v:180072$11822_Y
+ attribute \src "libresoc.v:180073.19-180073.99"
+ wire $gt$libresoc.v:180073$11823_Y
+ attribute \src "libresoc.v:180074.18-180074.97"
+ wire $gt$libresoc.v:180074$11824_Y
+ attribute \src "libresoc.v:180075.18-180075.97"
+ wire $gt$libresoc.v:180075$11825_Y
+ attribute \src "libresoc.v:180076.18-180076.97"
+ wire $gt$libresoc.v:180076$11826_Y
+ attribute \src "libresoc.v:180077.17-180077.96"
+ wire $gt$libresoc.v:180077$11827_Y
+ attribute \src "libresoc.v:180078.18-180078.97"
+ wire $gt$libresoc.v:180078$11828_Y
+ attribute \src "libresoc.v:180079.18-180079.97"
+ wire $gt$libresoc.v:180079$11829_Y
+ attribute \src "libresoc.v:180080.18-180080.97"
+ wire $gt$libresoc.v:180080$11830_Y
+ attribute \src "libresoc.v:180081.18-180081.97"
+ wire $gt$libresoc.v:180081$11831_Y
+ attribute \src "libresoc.v:180082.18-180082.97"
+ wire $gt$libresoc.v:180082$11832_Y
+ attribute \src "libresoc.v:180083.18-180083.97"
+ wire $gt$libresoc.v:180083$11833_Y
+ attribute \src "libresoc.v:180084.18-180084.97"
+ wire $gt$libresoc.v:180084$11834_Y
+ attribute \src "libresoc.v:180085.18-180085.98"
+ wire $gt$libresoc.v:180085$11835_Y
+ attribute \src "libresoc.v:180086.18-180086.98"
+ wire $gt$libresoc.v:180086$11836_Y
+ attribute \src "libresoc.v:180087.18-180087.98"
+ wire $gt$libresoc.v:180087$11837_Y
+ attribute \src "libresoc.v:180088.17-180088.96"
+ wire $gt$libresoc.v:180088$11838_Y
+ attribute \src "libresoc.v:180089.18-180089.98"
+ wire $gt$libresoc.v:180089$11839_Y
+ attribute \src "libresoc.v:180090.18-180090.98"
+ wire $gt$libresoc.v:180090$11840_Y
+ attribute \src "libresoc.v:180091.18-180091.98"
+ wire $gt$libresoc.v:180091$11841_Y
+ attribute \src "libresoc.v:180092.18-180092.98"
+ wire $gt$libresoc.v:180092$11842_Y
+ attribute \src "libresoc.v:180093.18-180093.98"
+ wire $gt$libresoc.v:180093$11843_Y
+ attribute \src "libresoc.v:180094.18-180094.98"
+ wire $gt$libresoc.v:180094$11844_Y
+ attribute \src "libresoc.v:180095.18-180095.98"
+ wire $gt$libresoc.v:180095$11845_Y
+ attribute \src "libresoc.v:180096.18-180096.98"
+ wire $gt$libresoc.v:180096$11846_Y
+ attribute \src "libresoc.v:180097.18-180097.98"
+ wire $gt$libresoc.v:180097$11847_Y
+ attribute \src "libresoc.v:180098.18-180098.98"
+ wire $gt$libresoc.v:180098$11848_Y
+ attribute \src "libresoc.v:180099.17-180099.96"
+ wire $gt$libresoc.v:180099$11849_Y
+ attribute \src "libresoc.v:180100.18-180100.98"
+ wire $gt$libresoc.v:180100$11850_Y
+ attribute \src "libresoc.v:180101.18-180101.98"
+ wire $gt$libresoc.v:180101$11851_Y
+ attribute \src "libresoc.v:180102.18-180102.98"
+ wire $gt$libresoc.v:180102$11852_Y
+ attribute \src "libresoc.v:180103.18-180103.98"
+ wire $gt$libresoc.v:180103$11853_Y
+ attribute \src "libresoc.v:180104.18-180104.98"
+ wire $gt$libresoc.v:180104$11854_Y
+ attribute \src "libresoc.v:180105.18-180105.98"
+ wire $gt$libresoc.v:180105$11855_Y
+ attribute \src "libresoc.v:180106.18-180106.98"
+ wire $gt$libresoc.v:180106$11856_Y
+ attribute \src "libresoc.v:180107.18-180107.98"
+ wire $gt$libresoc.v:180107$11857_Y
+ attribute \src "libresoc.v:180108.18-180108.98"
+ wire $gt$libresoc.v:180108$11858_Y
+ attribute \src "libresoc.v:180109.18-180109.98"
+ wire $gt$libresoc.v:180109$11859_Y
+ attribute \src "libresoc.v:180110.17-180110.96"
+ wire $gt$libresoc.v:180110$11860_Y
+ attribute \src "libresoc.v:180111.18-180111.98"
+ wire $gt$libresoc.v:180111$11861_Y
+ attribute \src "libresoc.v:180112.18-180112.98"
+ wire $gt$libresoc.v:180112$11862_Y
+ attribute \src "libresoc.v:180113.18-180113.98"
+ wire $gt$libresoc.v:180113$11863_Y
+ attribute \src "libresoc.v:180114.18-180114.98"
+ wire $gt$libresoc.v:180114$11864_Y
+ attribute \src "libresoc.v:180115.18-180115.98"
+ wire $gt$libresoc.v:180115$11865_Y
+ attribute \src "libresoc.v:180116.18-180116.98"
+ wire $gt$libresoc.v:180116$11866_Y
+ attribute \src "libresoc.v:180117.18-180117.98"
+ wire $gt$libresoc.v:180117$11867_Y
+ attribute \src "libresoc.v:180118.18-180118.98"
+ wire $gt$libresoc.v:180118$11868_Y
+ attribute \src "libresoc.v:180119.18-180119.98"
+ wire $gt$libresoc.v:180119$11869_Y
+ attribute \src "libresoc.v:180120.18-180120.98"
+ wire $gt$libresoc.v:180120$11870_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
wire \$99
- attribute \src "libresoc.v:182170.7-182170.15"
+ attribute \src "libresoc.v:179923.7-179923.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20"
wire width 64 output 1 \mask
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19"
wire width 7 input 2 \shift
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182304$11899
+ cell $gt $gt$libresoc.v:180057$11807
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'100
- connect \Y $gt$libresoc.v:182304$11899_Y
+ connect \Y $gt$libresoc.v:180057$11807_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182305$11900
+ cell $gt $gt$libresoc.v:180058$11808
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110001
- connect \Y $gt$libresoc.v:182305$11900_Y
+ connect \Y $gt$libresoc.v:180058$11808_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182306$11901
+ cell $gt $gt$libresoc.v:180059$11809
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110010
- connect \Y $gt$libresoc.v:182306$11901_Y
+ connect \Y $gt$libresoc.v:180059$11809_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182307$11902
+ cell $gt $gt$libresoc.v:180060$11810
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110011
- connect \Y $gt$libresoc.v:182307$11902_Y
+ connect \Y $gt$libresoc.v:180060$11810_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182308$11903
+ cell $gt $gt$libresoc.v:180061$11811
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110100
- connect \Y $gt$libresoc.v:182308$11903_Y
+ connect \Y $gt$libresoc.v:180061$11811_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182309$11904
+ cell $gt $gt$libresoc.v:180062$11812
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110101
- connect \Y $gt$libresoc.v:182309$11904_Y
+ connect \Y $gt$libresoc.v:180062$11812_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182310$11905
+ cell $gt $gt$libresoc.v:180063$11813
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110110
- connect \Y $gt$libresoc.v:182310$11905_Y
+ connect \Y $gt$libresoc.v:180063$11813_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182311$11906
+ cell $gt $gt$libresoc.v:180064$11814
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110111
- connect \Y $gt$libresoc.v:182311$11906_Y
+ connect \Y $gt$libresoc.v:180064$11814_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182312$11907
+ cell $gt $gt$libresoc.v:180065$11815
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111000
- connect \Y $gt$libresoc.v:182312$11907_Y
+ connect \Y $gt$libresoc.v:180065$11815_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182313$11908
+ cell $gt $gt$libresoc.v:180066$11816
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111001
- connect \Y $gt$libresoc.v:182313$11908_Y
+ connect \Y $gt$libresoc.v:180066$11816_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182314$11909
+ cell $gt $gt$libresoc.v:180067$11817
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111010
- connect \Y $gt$libresoc.v:182314$11909_Y
+ connect \Y $gt$libresoc.v:180067$11817_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182315$11910
+ cell $gt $gt$libresoc.v:180068$11818
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'101
- connect \Y $gt$libresoc.v:182315$11910_Y
+ connect \Y $gt$libresoc.v:180068$11818_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182316$11911
+ cell $gt $gt$libresoc.v:180069$11819
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111011
- connect \Y $gt$libresoc.v:182316$11911_Y
+ connect \Y $gt$libresoc.v:180069$11819_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182317$11912
+ cell $gt $gt$libresoc.v:180070$11820
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111100
- connect \Y $gt$libresoc.v:182317$11912_Y
+ connect \Y $gt$libresoc.v:180070$11820_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182318$11913
+ cell $gt $gt$libresoc.v:180071$11821
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111101
- connect \Y $gt$libresoc.v:182318$11913_Y
+ connect \Y $gt$libresoc.v:180071$11821_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182319$11914
+ cell $gt $gt$libresoc.v:180072$11822
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111110
- connect \Y $gt$libresoc.v:182319$11914_Y
+ connect \Y $gt$libresoc.v:180072$11822_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182320$11915
+ cell $gt $gt$libresoc.v:180073$11823
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'111111
- connect \Y $gt$libresoc.v:182320$11915_Y
+ connect \Y $gt$libresoc.v:180073$11823_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182321$11916
+ cell $gt $gt$libresoc.v:180074$11824
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'110
- connect \Y $gt$libresoc.v:182321$11916_Y
+ connect \Y $gt$libresoc.v:180074$11824_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182322$11917
+ cell $gt $gt$libresoc.v:180075$11825
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 3'111
- connect \Y $gt$libresoc.v:182322$11917_Y
+ connect \Y $gt$libresoc.v:180075$11825_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182323$11918
+ cell $gt $gt$libresoc.v:180076$11826
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1000
- connect \Y $gt$libresoc.v:182323$11918_Y
+ connect \Y $gt$libresoc.v:180076$11826_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182324$11919
+ cell $gt $gt$libresoc.v:180077$11827
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'0
- connect \Y $gt$libresoc.v:182324$11919_Y
+ connect \Y $gt$libresoc.v:180077$11827_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182325$11920
+ cell $gt $gt$libresoc.v:180078$11828
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1001
- connect \Y $gt$libresoc.v:182325$11920_Y
+ connect \Y $gt$libresoc.v:180078$11828_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182326$11921
+ cell $gt $gt$libresoc.v:180079$11829
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1010
- connect \Y $gt$libresoc.v:182326$11921_Y
+ connect \Y $gt$libresoc.v:180079$11829_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182327$11922
+ cell $gt $gt$libresoc.v:180080$11830
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1011
- connect \Y $gt$libresoc.v:182327$11922_Y
+ connect \Y $gt$libresoc.v:180080$11830_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182328$11923
+ cell $gt $gt$libresoc.v:180081$11831
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1100
- connect \Y $gt$libresoc.v:182328$11923_Y
+ connect \Y $gt$libresoc.v:180081$11831_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182329$11924
+ cell $gt $gt$libresoc.v:180082$11832
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1101
- connect \Y $gt$libresoc.v:182329$11924_Y
+ connect \Y $gt$libresoc.v:180082$11832_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182330$11925
+ cell $gt $gt$libresoc.v:180083$11833
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1110
- connect \Y $gt$libresoc.v:182330$11925_Y
+ connect \Y $gt$libresoc.v:180083$11833_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182331$11926
+ cell $gt $gt$libresoc.v:180084$11834
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 4'1111
- connect \Y $gt$libresoc.v:182331$11926_Y
+ connect \Y $gt$libresoc.v:180084$11834_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182332$11927
+ cell $gt $gt$libresoc.v:180085$11835
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10000
- connect \Y $gt$libresoc.v:182332$11927_Y
+ connect \Y $gt$libresoc.v:180085$11835_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182333$11928
+ cell $gt $gt$libresoc.v:180086$11836
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10001
- connect \Y $gt$libresoc.v:182333$11928_Y
+ connect \Y $gt$libresoc.v:180086$11836_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182334$11929
+ cell $gt $gt$libresoc.v:180087$11837
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10010
- connect \Y $gt$libresoc.v:182334$11929_Y
+ connect \Y $gt$libresoc.v:180087$11837_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182335$11930
+ cell $gt $gt$libresoc.v:180088$11838
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 1'1
- connect \Y $gt$libresoc.v:182335$11930_Y
+ connect \Y $gt$libresoc.v:180088$11838_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182336$11931
+ cell $gt $gt$libresoc.v:180089$11839
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10011
- connect \Y $gt$libresoc.v:182336$11931_Y
+ connect \Y $gt$libresoc.v:180089$11839_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182337$11932
+ cell $gt $gt$libresoc.v:180090$11840
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10100
- connect \Y $gt$libresoc.v:182337$11932_Y
+ connect \Y $gt$libresoc.v:180090$11840_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182338$11933
+ cell $gt $gt$libresoc.v:180091$11841
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10101
- connect \Y $gt$libresoc.v:182338$11933_Y
+ connect \Y $gt$libresoc.v:180091$11841_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182339$11934
+ cell $gt $gt$libresoc.v:180092$11842
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10110
- connect \Y $gt$libresoc.v:182339$11934_Y
+ connect \Y $gt$libresoc.v:180092$11842_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182340$11935
+ cell $gt $gt$libresoc.v:180093$11843
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'10111
- connect \Y $gt$libresoc.v:182340$11935_Y
+ connect \Y $gt$libresoc.v:180093$11843_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182341$11936
+ cell $gt $gt$libresoc.v:180094$11844
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11000
- connect \Y $gt$libresoc.v:182341$11936_Y
+ connect \Y $gt$libresoc.v:180094$11844_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182342$11937
+ cell $gt $gt$libresoc.v:180095$11845
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11001
- connect \Y $gt$libresoc.v:182342$11937_Y
+ connect \Y $gt$libresoc.v:180095$11845_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182343$11938
+ cell $gt $gt$libresoc.v:180096$11846
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11010
- connect \Y $gt$libresoc.v:182343$11938_Y
+ connect \Y $gt$libresoc.v:180096$11846_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182344$11939
+ cell $gt $gt$libresoc.v:180097$11847
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11011
- connect \Y $gt$libresoc.v:182344$11939_Y
+ connect \Y $gt$libresoc.v:180097$11847_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182345$11940
+ cell $gt $gt$libresoc.v:180098$11848
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11100
- connect \Y $gt$libresoc.v:182345$11940_Y
+ connect \Y $gt$libresoc.v:180098$11848_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182346$11941
+ cell $gt $gt$libresoc.v:180099$11849
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'10
- connect \Y $gt$libresoc.v:182346$11941_Y
+ connect \Y $gt$libresoc.v:180099$11849_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182347$11942
+ cell $gt $gt$libresoc.v:180100$11850
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11101
- connect \Y $gt$libresoc.v:182347$11942_Y
+ connect \Y $gt$libresoc.v:180100$11850_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182348$11943
+ cell $gt $gt$libresoc.v:180101$11851
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11110
- connect \Y $gt$libresoc.v:182348$11943_Y
+ connect \Y $gt$libresoc.v:180101$11851_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182349$11944
+ cell $gt $gt$libresoc.v:180102$11852
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 5'11111
- connect \Y $gt$libresoc.v:182349$11944_Y
+ connect \Y $gt$libresoc.v:180102$11852_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182350$11945
+ cell $gt $gt$libresoc.v:180103$11853
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100000
- connect \Y $gt$libresoc.v:182350$11945_Y
+ connect \Y $gt$libresoc.v:180103$11853_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182351$11946
+ cell $gt $gt$libresoc.v:180104$11854
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100001
- connect \Y $gt$libresoc.v:182351$11946_Y
+ connect \Y $gt$libresoc.v:180104$11854_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182352$11947
+ cell $gt $gt$libresoc.v:180105$11855
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100010
- connect \Y $gt$libresoc.v:182352$11947_Y
+ connect \Y $gt$libresoc.v:180105$11855_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182353$11948
+ cell $gt $gt$libresoc.v:180106$11856
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100011
- connect \Y $gt$libresoc.v:182353$11948_Y
+ connect \Y $gt$libresoc.v:180106$11856_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182354$11949
+ cell $gt $gt$libresoc.v:180107$11857
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100100
- connect \Y $gt$libresoc.v:182354$11949_Y
+ connect \Y $gt$libresoc.v:180107$11857_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182355$11950
+ cell $gt $gt$libresoc.v:180108$11858
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100101
- connect \Y $gt$libresoc.v:182355$11950_Y
+ connect \Y $gt$libresoc.v:180108$11858_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182356$11951
+ cell $gt $gt$libresoc.v:180109$11859
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100110
- connect \Y $gt$libresoc.v:182356$11951_Y
+ connect \Y $gt$libresoc.v:180109$11859_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182357$11952
+ cell $gt $gt$libresoc.v:180110$11860
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 2'11
- connect \Y $gt$libresoc.v:182357$11952_Y
+ connect \Y $gt$libresoc.v:180110$11860_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182358$11953
+ cell $gt $gt$libresoc.v:180111$11861
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'100111
- connect \Y $gt$libresoc.v:182358$11953_Y
+ connect \Y $gt$libresoc.v:180111$11861_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182359$11954
+ cell $gt $gt$libresoc.v:180112$11862
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101000
- connect \Y $gt$libresoc.v:182359$11954_Y
+ connect \Y $gt$libresoc.v:180112$11862_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182360$11955
+ cell $gt $gt$libresoc.v:180113$11863
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101001
- connect \Y $gt$libresoc.v:182360$11955_Y
+ connect \Y $gt$libresoc.v:180113$11863_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182361$11956
+ cell $gt $gt$libresoc.v:180114$11864
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101010
- connect \Y $gt$libresoc.v:182361$11956_Y
+ connect \Y $gt$libresoc.v:180114$11864_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182362$11957
+ cell $gt $gt$libresoc.v:180115$11865
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101011
- connect \Y $gt$libresoc.v:182362$11957_Y
+ connect \Y $gt$libresoc.v:180115$11865_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182363$11958
+ cell $gt $gt$libresoc.v:180116$11866
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101100
- connect \Y $gt$libresoc.v:182363$11958_Y
+ connect \Y $gt$libresoc.v:180116$11866_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182364$11959
+ cell $gt $gt$libresoc.v:180117$11867
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101101
- connect \Y $gt$libresoc.v:182364$11959_Y
+ connect \Y $gt$libresoc.v:180117$11867_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182365$11960
+ cell $gt $gt$libresoc.v:180118$11868
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101110
- connect \Y $gt$libresoc.v:182365$11960_Y
+ connect \Y $gt$libresoc.v:180118$11868_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182366$11961
+ cell $gt $gt$libresoc.v:180119$11869
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'101111
- connect \Y $gt$libresoc.v:182366$11961_Y
+ connect \Y $gt$libresoc.v:180119$11869_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26"
- cell $gt $gt$libresoc.v:182367$11962
+ cell $gt $gt$libresoc.v:180120$11870
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift
connect \B 6'110000
- connect \Y $gt$libresoc.v:182367$11962_Y
+ connect \Y $gt$libresoc.v:180120$11870_Y
end
- attribute \src "libresoc.v:182170.7-182170.20"
- process $proc$libresoc.v:182170$11964
+ attribute \src "libresoc.v:179923.7-179923.20"
+ process $proc$libresoc.v:179923$11872
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182368.3-182755.6"
- process $proc$libresoc.v:182368$11963
+ attribute \src "libresoc.v:180121.3-180508.6"
+ process $proc$libresoc.v:180121$11871
assign { } { }
assign { } { }
assign $0\mask[63:0] [0] $1\mask[0:0]
assign $0\mask[63:0] [61] $62\mask[61:61]
assign $0\mask[63:0] [62] $63\mask[62:62]
assign $0\mask[63:0] [63] $64\mask[63:63]
- attribute \src "libresoc.v:182369.5-182369.29"
+ attribute \src "libresoc.v:180122.5-180122.29"
switch \initial
- attribute \src "libresoc.v:182369.9-182369.17"
+ attribute \src "libresoc.v:180122.9-180122.17"
case 1'1
case
end
sync always
update \mask $0\mask[63:0]
end
- connect \$9 $gt$libresoc.v:182304$11899_Y
- connect \$99 $gt$libresoc.v:182305$11900_Y
- connect \$101 $gt$libresoc.v:182306$11901_Y
- connect \$103 $gt$libresoc.v:182307$11902_Y
- connect \$105 $gt$libresoc.v:182308$11903_Y
- connect \$107 $gt$libresoc.v:182309$11904_Y
- connect \$109 $gt$libresoc.v:182310$11905_Y
- connect \$111 $gt$libresoc.v:182311$11906_Y
- connect \$113 $gt$libresoc.v:182312$11907_Y
- connect \$115 $gt$libresoc.v:182313$11908_Y
- connect \$117 $gt$libresoc.v:182314$11909_Y
- connect \$11 $gt$libresoc.v:182315$11910_Y
- connect \$119 $gt$libresoc.v:182316$11911_Y
- connect \$121 $gt$libresoc.v:182317$11912_Y
- connect \$123 $gt$libresoc.v:182318$11913_Y
- connect \$125 $gt$libresoc.v:182319$11914_Y
- connect \$127 $gt$libresoc.v:182320$11915_Y
- connect \$13 $gt$libresoc.v:182321$11916_Y
- connect \$15 $gt$libresoc.v:182322$11917_Y
- connect \$17 $gt$libresoc.v:182323$11918_Y
- connect \$1 $gt$libresoc.v:182324$11919_Y
- connect \$19 $gt$libresoc.v:182325$11920_Y
- connect \$21 $gt$libresoc.v:182326$11921_Y
- connect \$23 $gt$libresoc.v:182327$11922_Y
- connect \$25 $gt$libresoc.v:182328$11923_Y
- connect \$27 $gt$libresoc.v:182329$11924_Y
- connect \$29 $gt$libresoc.v:182330$11925_Y
- connect \$31 $gt$libresoc.v:182331$11926_Y
- connect \$33 $gt$libresoc.v:182332$11927_Y
- connect \$35 $gt$libresoc.v:182333$11928_Y
- connect \$37 $gt$libresoc.v:182334$11929_Y
- connect \$3 $gt$libresoc.v:182335$11930_Y
- connect \$39 $gt$libresoc.v:182336$11931_Y
- connect \$41 $gt$libresoc.v:182337$11932_Y
- connect \$43 $gt$libresoc.v:182338$11933_Y
- connect \$45 $gt$libresoc.v:182339$11934_Y
- connect \$47 $gt$libresoc.v:182340$11935_Y
- connect \$49 $gt$libresoc.v:182341$11936_Y
- connect \$51 $gt$libresoc.v:182342$11937_Y
- connect \$53 $gt$libresoc.v:182343$11938_Y
- connect \$55 $gt$libresoc.v:182344$11939_Y
- connect \$57 $gt$libresoc.v:182345$11940_Y
- connect \$5 $gt$libresoc.v:182346$11941_Y
- connect \$59 $gt$libresoc.v:182347$11942_Y
- connect \$61 $gt$libresoc.v:182348$11943_Y
- connect \$63 $gt$libresoc.v:182349$11944_Y
- connect \$65 $gt$libresoc.v:182350$11945_Y
- connect \$67 $gt$libresoc.v:182351$11946_Y
- connect \$69 $gt$libresoc.v:182352$11947_Y
- connect \$71 $gt$libresoc.v:182353$11948_Y
- connect \$73 $gt$libresoc.v:182354$11949_Y
- connect \$75 $gt$libresoc.v:182355$11950_Y
- connect \$77 $gt$libresoc.v:182356$11951_Y
- connect \$7 $gt$libresoc.v:182357$11952_Y
- connect \$79 $gt$libresoc.v:182358$11953_Y
- connect \$81 $gt$libresoc.v:182359$11954_Y
- connect \$83 $gt$libresoc.v:182360$11955_Y
- connect \$85 $gt$libresoc.v:182361$11956_Y
- connect \$87 $gt$libresoc.v:182362$11957_Y
- connect \$89 $gt$libresoc.v:182363$11958_Y
- connect \$91 $gt$libresoc.v:182364$11959_Y
- connect \$93 $gt$libresoc.v:182365$11960_Y
- connect \$95 $gt$libresoc.v:182366$11961_Y
- connect \$97 $gt$libresoc.v:182367$11962_Y
+ connect \$9 $gt$libresoc.v:180057$11807_Y
+ connect \$99 $gt$libresoc.v:180058$11808_Y
+ connect \$101 $gt$libresoc.v:180059$11809_Y
+ connect \$103 $gt$libresoc.v:180060$11810_Y
+ connect \$105 $gt$libresoc.v:180061$11811_Y
+ connect \$107 $gt$libresoc.v:180062$11812_Y
+ connect \$109 $gt$libresoc.v:180063$11813_Y
+ connect \$111 $gt$libresoc.v:180064$11814_Y
+ connect \$113 $gt$libresoc.v:180065$11815_Y
+ connect \$115 $gt$libresoc.v:180066$11816_Y
+ connect \$117 $gt$libresoc.v:180067$11817_Y
+ connect \$11 $gt$libresoc.v:180068$11818_Y
+ connect \$119 $gt$libresoc.v:180069$11819_Y
+ connect \$121 $gt$libresoc.v:180070$11820_Y
+ connect \$123 $gt$libresoc.v:180071$11821_Y
+ connect \$125 $gt$libresoc.v:180072$11822_Y
+ connect \$127 $gt$libresoc.v:180073$11823_Y
+ connect \$13 $gt$libresoc.v:180074$11824_Y
+ connect \$15 $gt$libresoc.v:180075$11825_Y
+ connect \$17 $gt$libresoc.v:180076$11826_Y
+ connect \$1 $gt$libresoc.v:180077$11827_Y
+ connect \$19 $gt$libresoc.v:180078$11828_Y
+ connect \$21 $gt$libresoc.v:180079$11829_Y
+ connect \$23 $gt$libresoc.v:180080$11830_Y
+ connect \$25 $gt$libresoc.v:180081$11831_Y
+ connect \$27 $gt$libresoc.v:180082$11832_Y
+ connect \$29 $gt$libresoc.v:180083$11833_Y
+ connect \$31 $gt$libresoc.v:180084$11834_Y
+ connect \$33 $gt$libresoc.v:180085$11835_Y
+ connect \$35 $gt$libresoc.v:180086$11836_Y
+ connect \$37 $gt$libresoc.v:180087$11837_Y
+ connect \$3 $gt$libresoc.v:180088$11838_Y
+ connect \$39 $gt$libresoc.v:180089$11839_Y
+ connect \$41 $gt$libresoc.v:180090$11840_Y
+ connect \$43 $gt$libresoc.v:180091$11841_Y
+ connect \$45 $gt$libresoc.v:180092$11842_Y
+ connect \$47 $gt$libresoc.v:180093$11843_Y
+ connect \$49 $gt$libresoc.v:180094$11844_Y
+ connect \$51 $gt$libresoc.v:180095$11845_Y
+ connect \$53 $gt$libresoc.v:180096$11846_Y
+ connect \$55 $gt$libresoc.v:180097$11847_Y
+ connect \$57 $gt$libresoc.v:180098$11848_Y
+ connect \$5 $gt$libresoc.v:180099$11849_Y
+ connect \$59 $gt$libresoc.v:180100$11850_Y
+ connect \$61 $gt$libresoc.v:180101$11851_Y
+ connect \$63 $gt$libresoc.v:180102$11852_Y
+ connect \$65 $gt$libresoc.v:180103$11853_Y
+ connect \$67 $gt$libresoc.v:180104$11854_Y
+ connect \$69 $gt$libresoc.v:180105$11855_Y
+ connect \$71 $gt$libresoc.v:180106$11856_Y
+ connect \$73 $gt$libresoc.v:180107$11857_Y
+ connect \$75 $gt$libresoc.v:180108$11858_Y
+ connect \$77 $gt$libresoc.v:180109$11859_Y
+ connect \$7 $gt$libresoc.v:180110$11860_Y
+ connect \$79 $gt$libresoc.v:180111$11861_Y
+ connect \$81 $gt$libresoc.v:180112$11862_Y
+ connect \$83 $gt$libresoc.v:180113$11863_Y
+ connect \$85 $gt$libresoc.v:180114$11864_Y
+ connect \$87 $gt$libresoc.v:180115$11865_Y
+ connect \$89 $gt$libresoc.v:180116$11866_Y
+ connect \$91 $gt$libresoc.v:180117$11867_Y
+ connect \$93 $gt$libresoc.v:180118$11868_Y
+ connect \$95 $gt$libresoc.v:180119$11869_Y
+ connect \$97 $gt$libresoc.v:180120$11870_Y
end
-attribute \src "libresoc.v:182760.1-182818.10"
+attribute \src "libresoc.v:180513.1-180571.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l"
attribute \generator "nMigen"
module \rok_l
- attribute \src "libresoc.v:182761.7-182761.20"
+ attribute \src "libresoc.v:180514.7-180514.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182806.3-182814.6"
- wire $0\q_int$next[0:0]$11975
- attribute \src "libresoc.v:182804.3-182805.27"
+ attribute \src "libresoc.v:180559.3-180567.6"
+ wire $0\q_int$next[0:0]$11883
+ attribute \src "libresoc.v:180557.3-180558.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182806.3-182814.6"
- wire $1\q_int$next[0:0]$11976
- attribute \src "libresoc.v:182783.7-182783.19"
+ attribute \src "libresoc.v:180559.3-180567.6"
+ wire $1\q_int$next[0:0]$11884
+ attribute \src "libresoc.v:180536.7-180536.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182796.17-182796.96"
- wire $and$libresoc.v:182796$11965_Y
- attribute \src "libresoc.v:182801.17-182801.96"
- wire $and$libresoc.v:182801$11970_Y
- attribute \src "libresoc.v:182798.18-182798.94"
- wire $not$libresoc.v:182798$11967_Y
- attribute \src "libresoc.v:182800.17-182800.93"
- wire $not$libresoc.v:182800$11969_Y
- attribute \src "libresoc.v:182803.17-182803.93"
- wire $not$libresoc.v:182803$11972_Y
- attribute \src "libresoc.v:182797.18-182797.99"
- wire $or$libresoc.v:182797$11966_Y
- attribute \src "libresoc.v:182799.18-182799.100"
- wire $or$libresoc.v:182799$11968_Y
- attribute \src "libresoc.v:182802.17-182802.98"
- wire $or$libresoc.v:182802$11971_Y
+ attribute \src "libresoc.v:180549.17-180549.96"
+ wire $and$libresoc.v:180549$11873_Y
+ attribute \src "libresoc.v:180554.17-180554.96"
+ wire $and$libresoc.v:180554$11878_Y
+ attribute \src "libresoc.v:180551.18-180551.94"
+ wire $not$libresoc.v:180551$11875_Y
+ attribute \src "libresoc.v:180553.17-180553.93"
+ wire $not$libresoc.v:180553$11877_Y
+ attribute \src "libresoc.v:180556.17-180556.93"
+ wire $not$libresoc.v:180556$11880_Y
+ attribute \src "libresoc.v:180550.18-180550.99"
+ wire $or$libresoc.v:180550$11874_Y
+ attribute \src "libresoc.v:180552.18-180552.100"
+ wire $or$libresoc.v:180552$11876_Y
+ attribute \src "libresoc.v:180555.17-180555.98"
+ wire $or$libresoc.v:180555$11879_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182761.7-182761.15"
+ attribute \src "libresoc.v:180514.7-180514.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:182796$11965
+ cell $and $and$libresoc.v:180549$11873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:182796$11965_Y
+ connect \Y $and$libresoc.v:180549$11873_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182801$11970
+ cell $and $and$libresoc.v:180554$11878
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182801$11970_Y
+ connect \Y $and$libresoc.v:180554$11878_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182798$11967
+ cell $not $not$libresoc.v:180551$11875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:182798$11967_Y
+ connect \Y $not$libresoc.v:180551$11875_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182800$11969
+ cell $not $not$libresoc.v:180553$11877
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182800$11969_Y
+ connect \Y $not$libresoc.v:180553$11877_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:182803$11972
+ cell $not $not$libresoc.v:180556$11880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182803$11972_Y
+ connect \Y $not$libresoc.v:180556$11880_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:182797$11966
+ cell $or $or$libresoc.v:180550$11874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:182797$11966_Y
+ connect \Y $or$libresoc.v:180550$11874_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182799$11968
+ cell $or $or$libresoc.v:180552$11876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:182799$11968_Y
+ connect \Y $or$libresoc.v:180552$11876_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182802$11971
+ cell $or $or$libresoc.v:180555$11879
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:182802$11971_Y
+ connect \Y $or$libresoc.v:180555$11879_Y
end
- attribute \src "libresoc.v:182761.7-182761.20"
- process $proc$libresoc.v:182761$11977
+ attribute \src "libresoc.v:180514.7-180514.20"
+ process $proc$libresoc.v:180514$11885
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182783.7-182783.19"
- process $proc$libresoc.v:182783$11978
+ attribute \src "libresoc.v:180536.7-180536.19"
+ process $proc$libresoc.v:180536$11886
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182804.3-182805.27"
- process $proc$libresoc.v:182804$11973
+ attribute \src "libresoc.v:180557.3-180558.27"
+ process $proc$libresoc.v:180557$11881
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182806.3-182814.6"
- process $proc$libresoc.v:182806$11974
+ attribute \src "libresoc.v:180559.3-180567.6"
+ process $proc$libresoc.v:180559$11882
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$11975 $1\q_int$next[0:0]$11976
- attribute \src "libresoc.v:182807.5-182807.29"
+ assign $0\q_int$next[0:0]$11883 $1\q_int$next[0:0]$11884
+ attribute \src "libresoc.v:180560.5-180560.29"
switch \initial
- attribute \src "libresoc.v:182807.9-182807.17"
+ attribute \src "libresoc.v:180560.9-180560.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$11976 1'0
+ assign $1\q_int$next[0:0]$11884 1'0
case
- assign $1\q_int$next[0:0]$11976 \$5
+ assign $1\q_int$next[0:0]$11884 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$11975
+ update \q_int$next $0\q_int$next[0:0]$11883
end
- connect \$9 $and$libresoc.v:182796$11965_Y
- connect \$11 $or$libresoc.v:182797$11966_Y
- connect \$13 $not$libresoc.v:182798$11967_Y
- connect \$15 $or$libresoc.v:182799$11968_Y
- connect \$1 $not$libresoc.v:182800$11969_Y
- connect \$3 $and$libresoc.v:182801$11970_Y
- connect \$5 $or$libresoc.v:182802$11971_Y
- connect \$7 $not$libresoc.v:182803$11972_Y
+ connect \$9 $and$libresoc.v:180549$11873_Y
+ connect \$11 $or$libresoc.v:180550$11874_Y
+ connect \$13 $not$libresoc.v:180551$11875_Y
+ connect \$15 $or$libresoc.v:180552$11876_Y
+ connect \$1 $not$libresoc.v:180553$11877_Y
+ connect \$3 $and$libresoc.v:180554$11878_Y
+ connect \$5 $or$libresoc.v:180555$11879_Y
+ connect \$7 $not$libresoc.v:180556$11880_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:182822.1-182880.10"
+attribute \src "libresoc.v:180575.1-180633.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l"
attribute \generator "nMigen"
module \rok_l$105
- attribute \src "libresoc.v:182823.7-182823.20"
+ attribute \src "libresoc.v:180576.7-180576.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182868.3-182876.6"
- wire $0\q_int$next[0:0]$11989
- attribute \src "libresoc.v:182866.3-182867.27"
+ attribute \src "libresoc.v:180621.3-180629.6"
+ wire $0\q_int$next[0:0]$11897
+ attribute \src "libresoc.v:180619.3-180620.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182868.3-182876.6"
- wire $1\q_int$next[0:0]$11990
- attribute \src "libresoc.v:182845.7-182845.19"
+ attribute \src "libresoc.v:180621.3-180629.6"
+ wire $1\q_int$next[0:0]$11898
+ attribute \src "libresoc.v:180598.7-180598.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182858.17-182858.96"
- wire $and$libresoc.v:182858$11979_Y
- attribute \src "libresoc.v:182863.17-182863.96"
- wire $and$libresoc.v:182863$11984_Y
- attribute \src "libresoc.v:182860.18-182860.94"
- wire $not$libresoc.v:182860$11981_Y
- attribute \src "libresoc.v:182862.17-182862.93"
- wire $not$libresoc.v:182862$11983_Y
- attribute \src "libresoc.v:182865.17-182865.93"
- wire $not$libresoc.v:182865$11986_Y
- attribute \src "libresoc.v:182859.18-182859.99"
- wire $or$libresoc.v:182859$11980_Y
- attribute \src "libresoc.v:182861.18-182861.100"
- wire $or$libresoc.v:182861$11982_Y
- attribute \src "libresoc.v:182864.17-182864.98"
- wire $or$libresoc.v:182864$11985_Y
+ attribute \src "libresoc.v:180611.17-180611.96"
+ wire $and$libresoc.v:180611$11887_Y
+ attribute \src "libresoc.v:180616.17-180616.96"
+ wire $and$libresoc.v:180616$11892_Y
+ attribute \src "libresoc.v:180613.18-180613.94"
+ wire $not$libresoc.v:180613$11889_Y
+ attribute \src "libresoc.v:180615.17-180615.93"
+ wire $not$libresoc.v:180615$11891_Y
+ attribute \src "libresoc.v:180618.17-180618.93"
+ wire $not$libresoc.v:180618$11894_Y
+ attribute \src "libresoc.v:180612.18-180612.99"
+ wire $or$libresoc.v:180612$11888_Y
+ attribute \src "libresoc.v:180614.18-180614.100"
+ wire $or$libresoc.v:180614$11890_Y
+ attribute \src "libresoc.v:180617.17-180617.98"
+ wire $or$libresoc.v:180617$11893_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182823.7-182823.15"
+ attribute \src "libresoc.v:180576.7-180576.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:182858$11979
+ cell $and $and$libresoc.v:180611$11887
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:182858$11979_Y
+ connect \Y $and$libresoc.v:180611$11887_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182863$11984
+ cell $and $and$libresoc.v:180616$11892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182863$11984_Y
+ connect \Y $and$libresoc.v:180616$11892_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182860$11981
+ cell $not $not$libresoc.v:180613$11889
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:182860$11981_Y
+ connect \Y $not$libresoc.v:180613$11889_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182862$11983
+ cell $not $not$libresoc.v:180615$11891
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182862$11983_Y
+ connect \Y $not$libresoc.v:180615$11891_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:182865$11986
+ cell $not $not$libresoc.v:180618$11894
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182865$11986_Y
+ connect \Y $not$libresoc.v:180618$11894_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:182859$11980
+ cell $or $or$libresoc.v:180612$11888
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:182859$11980_Y
+ connect \Y $or$libresoc.v:180612$11888_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182861$11982
+ cell $or $or$libresoc.v:180614$11890
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:182861$11982_Y
+ connect \Y $or$libresoc.v:180614$11890_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182864$11985
+ cell $or $or$libresoc.v:180617$11893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:182864$11985_Y
+ connect \Y $or$libresoc.v:180617$11893_Y
end
- attribute \src "libresoc.v:182823.7-182823.20"
- process $proc$libresoc.v:182823$11991
+ attribute \src "libresoc.v:180576.7-180576.20"
+ process $proc$libresoc.v:180576$11899
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182845.7-182845.19"
- process $proc$libresoc.v:182845$11992
+ attribute \src "libresoc.v:180598.7-180598.19"
+ process $proc$libresoc.v:180598$11900
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182866.3-182867.27"
- process $proc$libresoc.v:182866$11987
+ attribute \src "libresoc.v:180619.3-180620.27"
+ process $proc$libresoc.v:180619$11895
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182868.3-182876.6"
- process $proc$libresoc.v:182868$11988
+ attribute \src "libresoc.v:180621.3-180629.6"
+ process $proc$libresoc.v:180621$11896
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$11989 $1\q_int$next[0:0]$11990
- attribute \src "libresoc.v:182869.5-182869.29"
+ assign $0\q_int$next[0:0]$11897 $1\q_int$next[0:0]$11898
+ attribute \src "libresoc.v:180622.5-180622.29"
switch \initial
- attribute \src "libresoc.v:182869.9-182869.17"
+ attribute \src "libresoc.v:180622.9-180622.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$11990 1'0
+ assign $1\q_int$next[0:0]$11898 1'0
case
- assign $1\q_int$next[0:0]$11990 \$5
+ assign $1\q_int$next[0:0]$11898 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$11989
+ update \q_int$next $0\q_int$next[0:0]$11897
end
- connect \$9 $and$libresoc.v:182858$11979_Y
- connect \$11 $or$libresoc.v:182859$11980_Y
- connect \$13 $not$libresoc.v:182860$11981_Y
- connect \$15 $or$libresoc.v:182861$11982_Y
- connect \$1 $not$libresoc.v:182862$11983_Y
- connect \$3 $and$libresoc.v:182863$11984_Y
- connect \$5 $or$libresoc.v:182864$11985_Y
- connect \$7 $not$libresoc.v:182865$11986_Y
+ connect \$9 $and$libresoc.v:180611$11887_Y
+ connect \$11 $or$libresoc.v:180612$11888_Y
+ connect \$13 $not$libresoc.v:180613$11889_Y
+ connect \$15 $or$libresoc.v:180614$11890_Y
+ connect \$1 $not$libresoc.v:180615$11891_Y
+ connect \$3 $and$libresoc.v:180616$11892_Y
+ connect \$5 $or$libresoc.v:180617$11893_Y
+ connect \$7 $not$libresoc.v:180618$11894_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:182884.1-182942.10"
+attribute \src "libresoc.v:180637.1-180695.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l"
attribute \generator "nMigen"
module \rok_l$123
- attribute \src "libresoc.v:182885.7-182885.20"
+ attribute \src "libresoc.v:180638.7-180638.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182930.3-182938.6"
- wire $0\q_int$next[0:0]$12003
- attribute \src "libresoc.v:182928.3-182929.27"
+ attribute \src "libresoc.v:180683.3-180691.6"
+ wire $0\q_int$next[0:0]$11911
+ attribute \src "libresoc.v:180681.3-180682.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182930.3-182938.6"
- wire $1\q_int$next[0:0]$12004
- attribute \src "libresoc.v:182907.7-182907.19"
+ attribute \src "libresoc.v:180683.3-180691.6"
+ wire $1\q_int$next[0:0]$11912
+ attribute \src "libresoc.v:180660.7-180660.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182920.17-182920.96"
- wire $and$libresoc.v:182920$11993_Y
- attribute \src "libresoc.v:182925.17-182925.96"
- wire $and$libresoc.v:182925$11998_Y
- attribute \src "libresoc.v:182922.18-182922.94"
- wire $not$libresoc.v:182922$11995_Y
- attribute \src "libresoc.v:182924.17-182924.93"
- wire $not$libresoc.v:182924$11997_Y
- attribute \src "libresoc.v:182927.17-182927.93"
- wire $not$libresoc.v:182927$12000_Y
- attribute \src "libresoc.v:182921.18-182921.99"
- wire $or$libresoc.v:182921$11994_Y
- attribute \src "libresoc.v:182923.18-182923.100"
- wire $or$libresoc.v:182923$11996_Y
- attribute \src "libresoc.v:182926.17-182926.98"
- wire $or$libresoc.v:182926$11999_Y
+ attribute \src "libresoc.v:180673.17-180673.96"
+ wire $and$libresoc.v:180673$11901_Y
+ attribute \src "libresoc.v:180678.17-180678.96"
+ wire $and$libresoc.v:180678$11906_Y
+ attribute \src "libresoc.v:180675.18-180675.94"
+ wire $not$libresoc.v:180675$11903_Y
+ attribute \src "libresoc.v:180677.17-180677.93"
+ wire $not$libresoc.v:180677$11905_Y
+ attribute \src "libresoc.v:180680.17-180680.93"
+ wire $not$libresoc.v:180680$11908_Y
+ attribute \src "libresoc.v:180674.18-180674.99"
+ wire $or$libresoc.v:180674$11902_Y
+ attribute \src "libresoc.v:180676.18-180676.100"
+ wire $or$libresoc.v:180676$11904_Y
+ attribute \src "libresoc.v:180679.17-180679.98"
+ wire $or$libresoc.v:180679$11907_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182885.7-182885.15"
+ attribute \src "libresoc.v:180638.7-180638.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:182920$11993
+ cell $and $and$libresoc.v:180673$11901
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:182920$11993_Y
+ connect \Y $and$libresoc.v:180673$11901_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182925$11998
+ cell $and $and$libresoc.v:180678$11906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182925$11998_Y
+ connect \Y $and$libresoc.v:180678$11906_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182922$11995
+ cell $not $not$libresoc.v:180675$11903
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:182922$11995_Y
+ connect \Y $not$libresoc.v:180675$11903_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182924$11997
+ cell $not $not$libresoc.v:180677$11905
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182924$11997_Y
+ connect \Y $not$libresoc.v:180677$11905_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:182927$12000
+ cell $not $not$libresoc.v:180680$11908
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182927$12000_Y
+ connect \Y $not$libresoc.v:180680$11908_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:182921$11994
+ cell $or $or$libresoc.v:180674$11902
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:182921$11994_Y
+ connect \Y $or$libresoc.v:180674$11902_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182923$11996
+ cell $or $or$libresoc.v:180676$11904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:182923$11996_Y
+ connect \Y $or$libresoc.v:180676$11904_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182926$11999
+ cell $or $or$libresoc.v:180679$11907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:182926$11999_Y
+ connect \Y $or$libresoc.v:180679$11907_Y
end
- attribute \src "libresoc.v:182885.7-182885.20"
- process $proc$libresoc.v:182885$12005
+ attribute \src "libresoc.v:180638.7-180638.20"
+ process $proc$libresoc.v:180638$11913
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182907.7-182907.19"
- process $proc$libresoc.v:182907$12006
+ attribute \src "libresoc.v:180660.7-180660.19"
+ process $proc$libresoc.v:180660$11914
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182928.3-182929.27"
- process $proc$libresoc.v:182928$12001
+ attribute \src "libresoc.v:180681.3-180682.27"
+ process $proc$libresoc.v:180681$11909
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182930.3-182938.6"
- process $proc$libresoc.v:182930$12002
+ attribute \src "libresoc.v:180683.3-180691.6"
+ process $proc$libresoc.v:180683$11910
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12003 $1\q_int$next[0:0]$12004
- attribute \src "libresoc.v:182931.5-182931.29"
+ assign $0\q_int$next[0:0]$11911 $1\q_int$next[0:0]$11912
+ attribute \src "libresoc.v:180684.5-180684.29"
switch \initial
- attribute \src "libresoc.v:182931.9-182931.17"
+ attribute \src "libresoc.v:180684.9-180684.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12004 1'0
+ assign $1\q_int$next[0:0]$11912 1'0
case
- assign $1\q_int$next[0:0]$12004 \$5
+ assign $1\q_int$next[0:0]$11912 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12003
+ update \q_int$next $0\q_int$next[0:0]$11911
end
- connect \$9 $and$libresoc.v:182920$11993_Y
- connect \$11 $or$libresoc.v:182921$11994_Y
- connect \$13 $not$libresoc.v:182922$11995_Y
- connect \$15 $or$libresoc.v:182923$11996_Y
- connect \$1 $not$libresoc.v:182924$11997_Y
- connect \$3 $and$libresoc.v:182925$11998_Y
- connect \$5 $or$libresoc.v:182926$11999_Y
- connect \$7 $not$libresoc.v:182927$12000_Y
+ connect \$9 $and$libresoc.v:180673$11901_Y
+ connect \$11 $or$libresoc.v:180674$11902_Y
+ connect \$13 $not$libresoc.v:180675$11903_Y
+ connect \$15 $or$libresoc.v:180676$11904_Y
+ connect \$1 $not$libresoc.v:180677$11905_Y
+ connect \$3 $and$libresoc.v:180678$11906_Y
+ connect \$5 $or$libresoc.v:180679$11907_Y
+ connect \$7 $not$libresoc.v:180680$11908_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:182946.1-183004.10"
+attribute \src "libresoc.v:180699.1-180757.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l"
attribute \generator "nMigen"
module \rok_l$14
- attribute \src "libresoc.v:182947.7-182947.20"
+ attribute \src "libresoc.v:180700.7-180700.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:182992.3-183000.6"
- wire $0\q_int$next[0:0]$12017
- attribute \src "libresoc.v:182990.3-182991.27"
+ attribute \src "libresoc.v:180745.3-180753.6"
+ wire $0\q_int$next[0:0]$11925
+ attribute \src "libresoc.v:180743.3-180744.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:182992.3-183000.6"
- wire $1\q_int$next[0:0]$12018
- attribute \src "libresoc.v:182969.7-182969.19"
+ attribute \src "libresoc.v:180745.3-180753.6"
+ wire $1\q_int$next[0:0]$11926
+ attribute \src "libresoc.v:180722.7-180722.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:182982.17-182982.96"
- wire $and$libresoc.v:182982$12007_Y
- attribute \src "libresoc.v:182987.17-182987.96"
- wire $and$libresoc.v:182987$12012_Y
- attribute \src "libresoc.v:182984.18-182984.94"
- wire $not$libresoc.v:182984$12009_Y
- attribute \src "libresoc.v:182986.17-182986.93"
- wire $not$libresoc.v:182986$12011_Y
- attribute \src "libresoc.v:182989.17-182989.93"
- wire $not$libresoc.v:182989$12014_Y
- attribute \src "libresoc.v:182983.18-182983.99"
- wire $or$libresoc.v:182983$12008_Y
- attribute \src "libresoc.v:182985.18-182985.100"
- wire $or$libresoc.v:182985$12010_Y
- attribute \src "libresoc.v:182988.17-182988.98"
- wire $or$libresoc.v:182988$12013_Y
+ attribute \src "libresoc.v:180735.17-180735.96"
+ wire $and$libresoc.v:180735$11915_Y
+ attribute \src "libresoc.v:180740.17-180740.96"
+ wire $and$libresoc.v:180740$11920_Y
+ attribute \src "libresoc.v:180737.18-180737.94"
+ wire $not$libresoc.v:180737$11917_Y
+ attribute \src "libresoc.v:180739.17-180739.93"
+ wire $not$libresoc.v:180739$11919_Y
+ attribute \src "libresoc.v:180742.17-180742.93"
+ wire $not$libresoc.v:180742$11922_Y
+ attribute \src "libresoc.v:180736.18-180736.99"
+ wire $or$libresoc.v:180736$11916_Y
+ attribute \src "libresoc.v:180738.18-180738.100"
+ wire $or$libresoc.v:180738$11918_Y
+ attribute \src "libresoc.v:180741.17-180741.98"
+ wire $or$libresoc.v:180741$11921_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:182947.7-182947.15"
+ attribute \src "libresoc.v:180700.7-180700.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:182982$12007
+ cell $and $and$libresoc.v:180735$11915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:182982$12007_Y
+ connect \Y $and$libresoc.v:180735$11915_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:182987$12012
+ cell $and $and$libresoc.v:180740$11920
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:182987$12012_Y
+ connect \Y $and$libresoc.v:180740$11920_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:182984$12009
+ cell $not $not$libresoc.v:180737$11917
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:182984$12009_Y
+ connect \Y $not$libresoc.v:180737$11917_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:182986$12011
+ cell $not $not$libresoc.v:180739$11919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182986$12011_Y
+ connect \Y $not$libresoc.v:180739$11919_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:182989$12014
+ cell $not $not$libresoc.v:180742$11922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:182989$12014_Y
+ connect \Y $not$libresoc.v:180742$11922_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:182983$12008
+ cell $or $or$libresoc.v:180736$11916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:182983$12008_Y
+ connect \Y $or$libresoc.v:180736$11916_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:182985$12010
+ cell $or $or$libresoc.v:180738$11918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:182985$12010_Y
+ connect \Y $or$libresoc.v:180738$11918_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:182988$12013
+ cell $or $or$libresoc.v:180741$11921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:182988$12013_Y
+ connect \Y $or$libresoc.v:180741$11921_Y
end
- attribute \src "libresoc.v:182947.7-182947.20"
- process $proc$libresoc.v:182947$12019
+ attribute \src "libresoc.v:180700.7-180700.20"
+ process $proc$libresoc.v:180700$11927
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:182969.7-182969.19"
- process $proc$libresoc.v:182969$12020
+ attribute \src "libresoc.v:180722.7-180722.19"
+ process $proc$libresoc.v:180722$11928
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:182990.3-182991.27"
- process $proc$libresoc.v:182990$12015
+ attribute \src "libresoc.v:180743.3-180744.27"
+ process $proc$libresoc.v:180743$11923
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:182992.3-183000.6"
- process $proc$libresoc.v:182992$12016
+ attribute \src "libresoc.v:180745.3-180753.6"
+ process $proc$libresoc.v:180745$11924
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12017 $1\q_int$next[0:0]$12018
- attribute \src "libresoc.v:182993.5-182993.29"
+ assign $0\q_int$next[0:0]$11925 $1\q_int$next[0:0]$11926
+ attribute \src "libresoc.v:180746.5-180746.29"
switch \initial
- attribute \src "libresoc.v:182993.9-182993.17"
+ attribute \src "libresoc.v:180746.9-180746.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12018 1'0
+ assign $1\q_int$next[0:0]$11926 1'0
case
- assign $1\q_int$next[0:0]$12018 \$5
+ assign $1\q_int$next[0:0]$11926 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12017
+ update \q_int$next $0\q_int$next[0:0]$11925
end
- connect \$9 $and$libresoc.v:182982$12007_Y
- connect \$11 $or$libresoc.v:182983$12008_Y
- connect \$13 $not$libresoc.v:182984$12009_Y
- connect \$15 $or$libresoc.v:182985$12010_Y
- connect \$1 $not$libresoc.v:182986$12011_Y
- connect \$3 $and$libresoc.v:182987$12012_Y
- connect \$5 $or$libresoc.v:182988$12013_Y
- connect \$7 $not$libresoc.v:182989$12014_Y
+ connect \$9 $and$libresoc.v:180735$11915_Y
+ connect \$11 $or$libresoc.v:180736$11916_Y
+ connect \$13 $not$libresoc.v:180737$11917_Y
+ connect \$15 $or$libresoc.v:180738$11918_Y
+ connect \$1 $not$libresoc.v:180739$11919_Y
+ connect \$3 $and$libresoc.v:180740$11920_Y
+ connect \$5 $or$libresoc.v:180741$11921_Y
+ connect \$7 $not$libresoc.v:180742$11922_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183008.1-183066.10"
+attribute \src "libresoc.v:180761.1-180819.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l"
attribute \generator "nMigen"
module \rok_l$27
- attribute \src "libresoc.v:183009.7-183009.20"
+ attribute \src "libresoc.v:180762.7-180762.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183054.3-183062.6"
- wire $0\q_int$next[0:0]$12031
- attribute \src "libresoc.v:183052.3-183053.27"
+ attribute \src "libresoc.v:180807.3-180815.6"
+ wire $0\q_int$next[0:0]$11939
+ attribute \src "libresoc.v:180805.3-180806.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183054.3-183062.6"
- wire $1\q_int$next[0:0]$12032
- attribute \src "libresoc.v:183031.7-183031.19"
+ attribute \src "libresoc.v:180807.3-180815.6"
+ wire $1\q_int$next[0:0]$11940
+ attribute \src "libresoc.v:180784.7-180784.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183044.17-183044.96"
- wire $and$libresoc.v:183044$12021_Y
- attribute \src "libresoc.v:183049.17-183049.96"
- wire $and$libresoc.v:183049$12026_Y
- attribute \src "libresoc.v:183046.18-183046.94"
- wire $not$libresoc.v:183046$12023_Y
- attribute \src "libresoc.v:183048.17-183048.93"
- wire $not$libresoc.v:183048$12025_Y
- attribute \src "libresoc.v:183051.17-183051.93"
- wire $not$libresoc.v:183051$12028_Y
- attribute \src "libresoc.v:183045.18-183045.99"
- wire $or$libresoc.v:183045$12022_Y
- attribute \src "libresoc.v:183047.18-183047.100"
- wire $or$libresoc.v:183047$12024_Y
- attribute \src "libresoc.v:183050.17-183050.98"
- wire $or$libresoc.v:183050$12027_Y
+ attribute \src "libresoc.v:180797.17-180797.96"
+ wire $and$libresoc.v:180797$11929_Y
+ attribute \src "libresoc.v:180802.17-180802.96"
+ wire $and$libresoc.v:180802$11934_Y
+ attribute \src "libresoc.v:180799.18-180799.94"
+ wire $not$libresoc.v:180799$11931_Y
+ attribute \src "libresoc.v:180801.17-180801.93"
+ wire $not$libresoc.v:180801$11933_Y
+ attribute \src "libresoc.v:180804.17-180804.93"
+ wire $not$libresoc.v:180804$11936_Y
+ attribute \src "libresoc.v:180798.18-180798.99"
+ wire $or$libresoc.v:180798$11930_Y
+ attribute \src "libresoc.v:180800.18-180800.100"
+ wire $or$libresoc.v:180800$11932_Y
+ attribute \src "libresoc.v:180803.17-180803.98"
+ wire $or$libresoc.v:180803$11935_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183009.7-183009.15"
+ attribute \src "libresoc.v:180762.7-180762.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183044$12021
+ cell $and $and$libresoc.v:180797$11929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183044$12021_Y
+ connect \Y $and$libresoc.v:180797$11929_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183049$12026
+ cell $and $and$libresoc.v:180802$11934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183049$12026_Y
+ connect \Y $and$libresoc.v:180802$11934_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183046$12023
+ cell $not $not$libresoc.v:180799$11931
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:183046$12023_Y
+ connect \Y $not$libresoc.v:180799$11931_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183048$12025
+ cell $not $not$libresoc.v:180801$11933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183048$12025_Y
+ connect \Y $not$libresoc.v:180801$11933_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183051$12028
+ cell $not $not$libresoc.v:180804$11936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183051$12028_Y
+ connect \Y $not$libresoc.v:180804$11936_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183045$12022
+ cell $or $or$libresoc.v:180798$11930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:183045$12022_Y
+ connect \Y $or$libresoc.v:180798$11930_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183047$12024
+ cell $or $or$libresoc.v:180800$11932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:183047$12024_Y
+ connect \Y $or$libresoc.v:180800$11932_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183050$12027
+ cell $or $or$libresoc.v:180803$11935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:183050$12027_Y
+ connect \Y $or$libresoc.v:180803$11935_Y
end
- attribute \src "libresoc.v:183009.7-183009.20"
- process $proc$libresoc.v:183009$12033
+ attribute \src "libresoc.v:180762.7-180762.20"
+ process $proc$libresoc.v:180762$11941
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183031.7-183031.19"
- process $proc$libresoc.v:183031$12034
+ attribute \src "libresoc.v:180784.7-180784.19"
+ process $proc$libresoc.v:180784$11942
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183052.3-183053.27"
- process $proc$libresoc.v:183052$12029
+ attribute \src "libresoc.v:180805.3-180806.27"
+ process $proc$libresoc.v:180805$11937
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183054.3-183062.6"
- process $proc$libresoc.v:183054$12030
+ attribute \src "libresoc.v:180807.3-180815.6"
+ process $proc$libresoc.v:180807$11938
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12031 $1\q_int$next[0:0]$12032
- attribute \src "libresoc.v:183055.5-183055.29"
+ assign $0\q_int$next[0:0]$11939 $1\q_int$next[0:0]$11940
+ attribute \src "libresoc.v:180808.5-180808.29"
switch \initial
- attribute \src "libresoc.v:183055.9-183055.17"
+ attribute \src "libresoc.v:180808.9-180808.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12032 1'0
+ assign $1\q_int$next[0:0]$11940 1'0
case
- assign $1\q_int$next[0:0]$12032 \$5
+ assign $1\q_int$next[0:0]$11940 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12031
+ update \q_int$next $0\q_int$next[0:0]$11939
end
- connect \$9 $and$libresoc.v:183044$12021_Y
- connect \$11 $or$libresoc.v:183045$12022_Y
- connect \$13 $not$libresoc.v:183046$12023_Y
- connect \$15 $or$libresoc.v:183047$12024_Y
- connect \$1 $not$libresoc.v:183048$12025_Y
- connect \$3 $and$libresoc.v:183049$12026_Y
- connect \$5 $or$libresoc.v:183050$12027_Y
- connect \$7 $not$libresoc.v:183051$12028_Y
+ connect \$9 $and$libresoc.v:180797$11929_Y
+ connect \$11 $or$libresoc.v:180798$11930_Y
+ connect \$13 $not$libresoc.v:180799$11931_Y
+ connect \$15 $or$libresoc.v:180800$11932_Y
+ connect \$1 $not$libresoc.v:180801$11933_Y
+ connect \$3 $and$libresoc.v:180802$11934_Y
+ connect \$5 $or$libresoc.v:180803$11935_Y
+ connect \$7 $not$libresoc.v:180804$11936_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183070.1-183128.10"
+attribute \src "libresoc.v:180823.1-180881.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l"
attribute \generator "nMigen"
module \rok_l$43
- attribute \src "libresoc.v:183071.7-183071.20"
+ attribute \src "libresoc.v:180824.7-180824.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183116.3-183124.6"
- wire $0\q_int$next[0:0]$12045
- attribute \src "libresoc.v:183114.3-183115.27"
+ attribute \src "libresoc.v:180869.3-180877.6"
+ wire $0\q_int$next[0:0]$11953
+ attribute \src "libresoc.v:180867.3-180868.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183116.3-183124.6"
- wire $1\q_int$next[0:0]$12046
- attribute \src "libresoc.v:183093.7-183093.19"
+ attribute \src "libresoc.v:180869.3-180877.6"
+ wire $1\q_int$next[0:0]$11954
+ attribute \src "libresoc.v:180846.7-180846.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183106.17-183106.96"
- wire $and$libresoc.v:183106$12035_Y
- attribute \src "libresoc.v:183111.17-183111.96"
- wire $and$libresoc.v:183111$12040_Y
- attribute \src "libresoc.v:183108.18-183108.94"
- wire $not$libresoc.v:183108$12037_Y
- attribute \src "libresoc.v:183110.17-183110.93"
- wire $not$libresoc.v:183110$12039_Y
- attribute \src "libresoc.v:183113.17-183113.93"
- wire $not$libresoc.v:183113$12042_Y
- attribute \src "libresoc.v:183107.18-183107.99"
- wire $or$libresoc.v:183107$12036_Y
- attribute \src "libresoc.v:183109.18-183109.100"
- wire $or$libresoc.v:183109$12038_Y
- attribute \src "libresoc.v:183112.17-183112.98"
- wire $or$libresoc.v:183112$12041_Y
+ attribute \src "libresoc.v:180859.17-180859.96"
+ wire $and$libresoc.v:180859$11943_Y
+ attribute \src "libresoc.v:180864.17-180864.96"
+ wire $and$libresoc.v:180864$11948_Y
+ attribute \src "libresoc.v:180861.18-180861.94"
+ wire $not$libresoc.v:180861$11945_Y
+ attribute \src "libresoc.v:180863.17-180863.93"
+ wire $not$libresoc.v:180863$11947_Y
+ attribute \src "libresoc.v:180866.17-180866.93"
+ wire $not$libresoc.v:180866$11950_Y
+ attribute \src "libresoc.v:180860.18-180860.99"
+ wire $or$libresoc.v:180860$11944_Y
+ attribute \src "libresoc.v:180862.18-180862.100"
+ wire $or$libresoc.v:180862$11946_Y
+ attribute \src "libresoc.v:180865.17-180865.98"
+ wire $or$libresoc.v:180865$11949_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183071.7-183071.15"
+ attribute \src "libresoc.v:180824.7-180824.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183106$12035
+ cell $and $and$libresoc.v:180859$11943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183106$12035_Y
+ connect \Y $and$libresoc.v:180859$11943_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183111$12040
+ cell $and $and$libresoc.v:180864$11948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183111$12040_Y
+ connect \Y $and$libresoc.v:180864$11948_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183108$12037
+ cell $not $not$libresoc.v:180861$11945
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:183108$12037_Y
+ connect \Y $not$libresoc.v:180861$11945_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183110$12039
+ cell $not $not$libresoc.v:180863$11947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183110$12039_Y
+ connect \Y $not$libresoc.v:180863$11947_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183113$12042
+ cell $not $not$libresoc.v:180866$11950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183113$12042_Y
+ connect \Y $not$libresoc.v:180866$11950_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183107$12036
+ cell $or $or$libresoc.v:180860$11944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:183107$12036_Y
+ connect \Y $or$libresoc.v:180860$11944_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183109$12038
+ cell $or $or$libresoc.v:180862$11946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:183109$12038_Y
+ connect \Y $or$libresoc.v:180862$11946_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183112$12041
+ cell $or $or$libresoc.v:180865$11949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:183112$12041_Y
+ connect \Y $or$libresoc.v:180865$11949_Y
end
- attribute \src "libresoc.v:183071.7-183071.20"
- process $proc$libresoc.v:183071$12047
+ attribute \src "libresoc.v:180824.7-180824.20"
+ process $proc$libresoc.v:180824$11955
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183093.7-183093.19"
- process $proc$libresoc.v:183093$12048
+ attribute \src "libresoc.v:180846.7-180846.19"
+ process $proc$libresoc.v:180846$11956
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183114.3-183115.27"
- process $proc$libresoc.v:183114$12043
+ attribute \src "libresoc.v:180867.3-180868.27"
+ process $proc$libresoc.v:180867$11951
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183116.3-183124.6"
- process $proc$libresoc.v:183116$12044
+ attribute \src "libresoc.v:180869.3-180877.6"
+ process $proc$libresoc.v:180869$11952
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12045 $1\q_int$next[0:0]$12046
- attribute \src "libresoc.v:183117.5-183117.29"
+ assign $0\q_int$next[0:0]$11953 $1\q_int$next[0:0]$11954
+ attribute \src "libresoc.v:180870.5-180870.29"
switch \initial
- attribute \src "libresoc.v:183117.9-183117.17"
+ attribute \src "libresoc.v:180870.9-180870.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12046 1'0
+ assign $1\q_int$next[0:0]$11954 1'0
case
- assign $1\q_int$next[0:0]$12046 \$5
+ assign $1\q_int$next[0:0]$11954 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12045
+ update \q_int$next $0\q_int$next[0:0]$11953
end
- connect \$9 $and$libresoc.v:183106$12035_Y
- connect \$11 $or$libresoc.v:183107$12036_Y
- connect \$13 $not$libresoc.v:183108$12037_Y
- connect \$15 $or$libresoc.v:183109$12038_Y
- connect \$1 $not$libresoc.v:183110$12039_Y
- connect \$3 $and$libresoc.v:183111$12040_Y
- connect \$5 $or$libresoc.v:183112$12041_Y
- connect \$7 $not$libresoc.v:183113$12042_Y
+ connect \$9 $and$libresoc.v:180859$11943_Y
+ connect \$11 $or$libresoc.v:180860$11944_Y
+ connect \$13 $not$libresoc.v:180861$11945_Y
+ connect \$15 $or$libresoc.v:180862$11946_Y
+ connect \$1 $not$libresoc.v:180863$11947_Y
+ connect \$3 $and$libresoc.v:180864$11948_Y
+ connect \$5 $or$libresoc.v:180865$11949_Y
+ connect \$7 $not$libresoc.v:180866$11950_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183132.1-183190.10"
+attribute \src "libresoc.v:180885.1-180943.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l"
attribute \generator "nMigen"
module \rok_l$59
- attribute \src "libresoc.v:183133.7-183133.20"
+ attribute \src "libresoc.v:180886.7-180886.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183178.3-183186.6"
- wire $0\q_int$next[0:0]$12059
- attribute \src "libresoc.v:183176.3-183177.27"
+ attribute \src "libresoc.v:180931.3-180939.6"
+ wire $0\q_int$next[0:0]$11967
+ attribute \src "libresoc.v:180929.3-180930.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183178.3-183186.6"
- wire $1\q_int$next[0:0]$12060
- attribute \src "libresoc.v:183155.7-183155.19"
+ attribute \src "libresoc.v:180931.3-180939.6"
+ wire $1\q_int$next[0:0]$11968
+ attribute \src "libresoc.v:180908.7-180908.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183168.17-183168.96"
- wire $and$libresoc.v:183168$12049_Y
- attribute \src "libresoc.v:183173.17-183173.96"
- wire $and$libresoc.v:183173$12054_Y
- attribute \src "libresoc.v:183170.18-183170.94"
- wire $not$libresoc.v:183170$12051_Y
- attribute \src "libresoc.v:183172.17-183172.93"
- wire $not$libresoc.v:183172$12053_Y
- attribute \src "libresoc.v:183175.17-183175.93"
- wire $not$libresoc.v:183175$12056_Y
- attribute \src "libresoc.v:183169.18-183169.99"
- wire $or$libresoc.v:183169$12050_Y
- attribute \src "libresoc.v:183171.18-183171.100"
- wire $or$libresoc.v:183171$12052_Y
- attribute \src "libresoc.v:183174.17-183174.98"
- wire $or$libresoc.v:183174$12055_Y
+ attribute \src "libresoc.v:180921.17-180921.96"
+ wire $and$libresoc.v:180921$11957_Y
+ attribute \src "libresoc.v:180926.17-180926.96"
+ wire $and$libresoc.v:180926$11962_Y
+ attribute \src "libresoc.v:180923.18-180923.94"
+ wire $not$libresoc.v:180923$11959_Y
+ attribute \src "libresoc.v:180925.17-180925.93"
+ wire $not$libresoc.v:180925$11961_Y
+ attribute \src "libresoc.v:180928.17-180928.93"
+ wire $not$libresoc.v:180928$11964_Y
+ attribute \src "libresoc.v:180922.18-180922.99"
+ wire $or$libresoc.v:180922$11958_Y
+ attribute \src "libresoc.v:180924.18-180924.100"
+ wire $or$libresoc.v:180924$11960_Y
+ attribute \src "libresoc.v:180927.17-180927.98"
+ wire $or$libresoc.v:180927$11963_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183133.7-183133.15"
+ attribute \src "libresoc.v:180886.7-180886.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183168$12049
+ cell $and $and$libresoc.v:180921$11957
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183168$12049_Y
+ connect \Y $and$libresoc.v:180921$11957_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183173$12054
+ cell $and $and$libresoc.v:180926$11962
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183173$12054_Y
+ connect \Y $and$libresoc.v:180926$11962_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183170$12051
+ cell $not $not$libresoc.v:180923$11959
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:183170$12051_Y
+ connect \Y $not$libresoc.v:180923$11959_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183172$12053
+ cell $not $not$libresoc.v:180925$11961
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183172$12053_Y
+ connect \Y $not$libresoc.v:180925$11961_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183175$12056
+ cell $not $not$libresoc.v:180928$11964
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183175$12056_Y
+ connect \Y $not$libresoc.v:180928$11964_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183169$12050
+ cell $or $or$libresoc.v:180922$11958
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:183169$12050_Y
+ connect \Y $or$libresoc.v:180922$11958_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183171$12052
+ cell $or $or$libresoc.v:180924$11960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:183171$12052_Y
+ connect \Y $or$libresoc.v:180924$11960_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183174$12055
+ cell $or $or$libresoc.v:180927$11963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:183174$12055_Y
+ connect \Y $or$libresoc.v:180927$11963_Y
end
- attribute \src "libresoc.v:183133.7-183133.20"
- process $proc$libresoc.v:183133$12061
+ attribute \src "libresoc.v:180886.7-180886.20"
+ process $proc$libresoc.v:180886$11969
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183155.7-183155.19"
- process $proc$libresoc.v:183155$12062
+ attribute \src "libresoc.v:180908.7-180908.19"
+ process $proc$libresoc.v:180908$11970
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183176.3-183177.27"
- process $proc$libresoc.v:183176$12057
+ attribute \src "libresoc.v:180929.3-180930.27"
+ process $proc$libresoc.v:180929$11965
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183178.3-183186.6"
- process $proc$libresoc.v:183178$12058
+ attribute \src "libresoc.v:180931.3-180939.6"
+ process $proc$libresoc.v:180931$11966
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12059 $1\q_int$next[0:0]$12060
- attribute \src "libresoc.v:183179.5-183179.29"
+ assign $0\q_int$next[0:0]$11967 $1\q_int$next[0:0]$11968
+ attribute \src "libresoc.v:180932.5-180932.29"
switch \initial
- attribute \src "libresoc.v:183179.9-183179.17"
+ attribute \src "libresoc.v:180932.9-180932.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12060 1'0
+ assign $1\q_int$next[0:0]$11968 1'0
case
- assign $1\q_int$next[0:0]$12060 \$5
+ assign $1\q_int$next[0:0]$11968 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12059
+ update \q_int$next $0\q_int$next[0:0]$11967
end
- connect \$9 $and$libresoc.v:183168$12049_Y
- connect \$11 $or$libresoc.v:183169$12050_Y
- connect \$13 $not$libresoc.v:183170$12051_Y
- connect \$15 $or$libresoc.v:183171$12052_Y
- connect \$1 $not$libresoc.v:183172$12053_Y
- connect \$3 $and$libresoc.v:183173$12054_Y
- connect \$5 $or$libresoc.v:183174$12055_Y
- connect \$7 $not$libresoc.v:183175$12056_Y
+ connect \$9 $and$libresoc.v:180921$11957_Y
+ connect \$11 $or$libresoc.v:180922$11958_Y
+ connect \$13 $not$libresoc.v:180923$11959_Y
+ connect \$15 $or$libresoc.v:180924$11960_Y
+ connect \$1 $not$libresoc.v:180925$11961_Y
+ connect \$3 $and$libresoc.v:180926$11962_Y
+ connect \$5 $or$libresoc.v:180927$11963_Y
+ connect \$7 $not$libresoc.v:180928$11964_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183194.1-183252.10"
+attribute \src "libresoc.v:180947.1-181005.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l"
attribute \generator "nMigen"
module \rok_l$71
- attribute \src "libresoc.v:183195.7-183195.20"
+ attribute \src "libresoc.v:180948.7-180948.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183240.3-183248.6"
- wire $0\q_int$next[0:0]$12073
- attribute \src "libresoc.v:183238.3-183239.27"
+ attribute \src "libresoc.v:180993.3-181001.6"
+ wire $0\q_int$next[0:0]$11981
+ attribute \src "libresoc.v:180991.3-180992.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183240.3-183248.6"
- wire $1\q_int$next[0:0]$12074
- attribute \src "libresoc.v:183217.7-183217.19"
+ attribute \src "libresoc.v:180993.3-181001.6"
+ wire $1\q_int$next[0:0]$11982
+ attribute \src "libresoc.v:180970.7-180970.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183230.17-183230.96"
- wire $and$libresoc.v:183230$12063_Y
- attribute \src "libresoc.v:183235.17-183235.96"
- wire $and$libresoc.v:183235$12068_Y
- attribute \src "libresoc.v:183232.18-183232.94"
- wire $not$libresoc.v:183232$12065_Y
- attribute \src "libresoc.v:183234.17-183234.93"
- wire $not$libresoc.v:183234$12067_Y
- attribute \src "libresoc.v:183237.17-183237.93"
- wire $not$libresoc.v:183237$12070_Y
- attribute \src "libresoc.v:183231.18-183231.99"
- wire $or$libresoc.v:183231$12064_Y
- attribute \src "libresoc.v:183233.18-183233.100"
- wire $or$libresoc.v:183233$12066_Y
- attribute \src "libresoc.v:183236.17-183236.98"
- wire $or$libresoc.v:183236$12069_Y
+ attribute \src "libresoc.v:180983.17-180983.96"
+ wire $and$libresoc.v:180983$11971_Y
+ attribute \src "libresoc.v:180988.17-180988.96"
+ wire $and$libresoc.v:180988$11976_Y
+ attribute \src "libresoc.v:180985.18-180985.94"
+ wire $not$libresoc.v:180985$11973_Y
+ attribute \src "libresoc.v:180987.17-180987.93"
+ wire $not$libresoc.v:180987$11975_Y
+ attribute \src "libresoc.v:180990.17-180990.93"
+ wire $not$libresoc.v:180990$11978_Y
+ attribute \src "libresoc.v:180984.18-180984.99"
+ wire $or$libresoc.v:180984$11972_Y
+ attribute \src "libresoc.v:180986.18-180986.100"
+ wire $or$libresoc.v:180986$11974_Y
+ attribute \src "libresoc.v:180989.17-180989.98"
+ wire $or$libresoc.v:180989$11977_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183195.7-183195.15"
+ attribute \src "libresoc.v:180948.7-180948.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183230$12063
+ cell $and $and$libresoc.v:180983$11971
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183230$12063_Y
+ connect \Y $and$libresoc.v:180983$11971_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183235$12068
+ cell $and $and$libresoc.v:180988$11976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183235$12068_Y
+ connect \Y $and$libresoc.v:180988$11976_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183232$12065
+ cell $not $not$libresoc.v:180985$11973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:183232$12065_Y
+ connect \Y $not$libresoc.v:180985$11973_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183234$12067
+ cell $not $not$libresoc.v:180987$11975
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183234$12067_Y
+ connect \Y $not$libresoc.v:180987$11975_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183237$12070
+ cell $not $not$libresoc.v:180990$11978
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183237$12070_Y
+ connect \Y $not$libresoc.v:180990$11978_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183231$12064
+ cell $or $or$libresoc.v:180984$11972
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:183231$12064_Y
+ connect \Y $or$libresoc.v:180984$11972_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183233$12066
+ cell $or $or$libresoc.v:180986$11974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:183233$12066_Y
+ connect \Y $or$libresoc.v:180986$11974_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183236$12069
+ cell $or $or$libresoc.v:180989$11977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:183236$12069_Y
+ connect \Y $or$libresoc.v:180989$11977_Y
end
- attribute \src "libresoc.v:183195.7-183195.20"
- process $proc$libresoc.v:183195$12075
+ attribute \src "libresoc.v:180948.7-180948.20"
+ process $proc$libresoc.v:180948$11983
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183217.7-183217.19"
- process $proc$libresoc.v:183217$12076
+ attribute \src "libresoc.v:180970.7-180970.19"
+ process $proc$libresoc.v:180970$11984
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183238.3-183239.27"
- process $proc$libresoc.v:183238$12071
+ attribute \src "libresoc.v:180991.3-180992.27"
+ process $proc$libresoc.v:180991$11979
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183240.3-183248.6"
- process $proc$libresoc.v:183240$12072
+ attribute \src "libresoc.v:180993.3-181001.6"
+ process $proc$libresoc.v:180993$11980
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12073 $1\q_int$next[0:0]$12074
- attribute \src "libresoc.v:183241.5-183241.29"
+ assign $0\q_int$next[0:0]$11981 $1\q_int$next[0:0]$11982
+ attribute \src "libresoc.v:180994.5-180994.29"
switch \initial
- attribute \src "libresoc.v:183241.9-183241.17"
+ attribute \src "libresoc.v:180994.9-180994.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12074 1'0
+ assign $1\q_int$next[0:0]$11982 1'0
case
- assign $1\q_int$next[0:0]$12074 \$5
+ assign $1\q_int$next[0:0]$11982 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12073
+ update \q_int$next $0\q_int$next[0:0]$11981
end
- connect \$9 $and$libresoc.v:183230$12063_Y
- connect \$11 $or$libresoc.v:183231$12064_Y
- connect \$13 $not$libresoc.v:183232$12065_Y
- connect \$15 $or$libresoc.v:183233$12066_Y
- connect \$1 $not$libresoc.v:183234$12067_Y
- connect \$3 $and$libresoc.v:183235$12068_Y
- connect \$5 $or$libresoc.v:183236$12069_Y
- connect \$7 $not$libresoc.v:183237$12070_Y
+ connect \$9 $and$libresoc.v:180983$11971_Y
+ connect \$11 $or$libresoc.v:180984$11972_Y
+ connect \$13 $not$libresoc.v:180985$11973_Y
+ connect \$15 $or$libresoc.v:180986$11974_Y
+ connect \$1 $not$libresoc.v:180987$11975_Y
+ connect \$3 $and$libresoc.v:180988$11976_Y
+ connect \$5 $or$libresoc.v:180989$11977_Y
+ connect \$7 $not$libresoc.v:180990$11978_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183256.1-183314.10"
+attribute \src "libresoc.v:181009.1-181067.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l"
attribute \generator "nMigen"
module \rok_l$88
- attribute \src "libresoc.v:183257.7-183257.20"
+ attribute \src "libresoc.v:181010.7-181010.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183302.3-183310.6"
- wire $0\q_int$next[0:0]$12087
- attribute \src "libresoc.v:183300.3-183301.27"
+ attribute \src "libresoc.v:181055.3-181063.6"
+ wire $0\q_int$next[0:0]$11995
+ attribute \src "libresoc.v:181053.3-181054.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183302.3-183310.6"
- wire $1\q_int$next[0:0]$12088
- attribute \src "libresoc.v:183279.7-183279.19"
+ attribute \src "libresoc.v:181055.3-181063.6"
+ wire $1\q_int$next[0:0]$11996
+ attribute \src "libresoc.v:181032.7-181032.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183292.17-183292.96"
- wire $and$libresoc.v:183292$12077_Y
- attribute \src "libresoc.v:183297.17-183297.96"
- wire $and$libresoc.v:183297$12082_Y
- attribute \src "libresoc.v:183294.18-183294.94"
- wire $not$libresoc.v:183294$12079_Y
- attribute \src "libresoc.v:183296.17-183296.93"
- wire $not$libresoc.v:183296$12081_Y
- attribute \src "libresoc.v:183299.17-183299.93"
- wire $not$libresoc.v:183299$12084_Y
- attribute \src "libresoc.v:183293.18-183293.99"
- wire $or$libresoc.v:183293$12078_Y
- attribute \src "libresoc.v:183295.18-183295.100"
- wire $or$libresoc.v:183295$12080_Y
- attribute \src "libresoc.v:183298.17-183298.98"
- wire $or$libresoc.v:183298$12083_Y
+ attribute \src "libresoc.v:181045.17-181045.96"
+ wire $and$libresoc.v:181045$11985_Y
+ attribute \src "libresoc.v:181050.17-181050.96"
+ wire $and$libresoc.v:181050$11990_Y
+ attribute \src "libresoc.v:181047.18-181047.94"
+ wire $not$libresoc.v:181047$11987_Y
+ attribute \src "libresoc.v:181049.17-181049.93"
+ wire $not$libresoc.v:181049$11989_Y
+ attribute \src "libresoc.v:181052.17-181052.93"
+ wire $not$libresoc.v:181052$11992_Y
+ attribute \src "libresoc.v:181046.18-181046.99"
+ wire $or$libresoc.v:181046$11986_Y
+ attribute \src "libresoc.v:181048.18-181048.100"
+ wire $or$libresoc.v:181048$11988_Y
+ attribute \src "libresoc.v:181051.17-181051.98"
+ wire $or$libresoc.v:181051$11991_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183257.7-183257.15"
+ attribute \src "libresoc.v:181010.7-181010.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183292$12077
+ cell $and $and$libresoc.v:181045$11985
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183292$12077_Y
+ connect \Y $and$libresoc.v:181045$11985_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183297$12082
+ cell $and $and$libresoc.v:181050$11990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183297$12082_Y
+ connect \Y $and$libresoc.v:181050$11990_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183294$12079
+ cell $not $not$libresoc.v:181047$11987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rdok
- connect \Y $not$libresoc.v:183294$12079_Y
+ connect \Y $not$libresoc.v:181047$11987_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183296$12081
+ cell $not $not$libresoc.v:181049$11989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183296$12081_Y
+ connect \Y $not$libresoc.v:181049$11989_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183299$12084
+ cell $not $not$libresoc.v:181052$11992
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rdok
- connect \Y $not$libresoc.v:183299$12084_Y
+ connect \Y $not$libresoc.v:181052$11992_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183293$12078
+ cell $or $or$libresoc.v:181046$11986
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rdok
- connect \Y $or$libresoc.v:183293$12078_Y
+ connect \Y $or$libresoc.v:181046$11986_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183295$12080
+ cell $or $or$libresoc.v:181048$11988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rdok
connect \B \q_int
- connect \Y $or$libresoc.v:183295$12080_Y
+ connect \Y $or$libresoc.v:181048$11988_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183298$12083
+ cell $or $or$libresoc.v:181051$11991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rdok
- connect \Y $or$libresoc.v:183298$12083_Y
+ connect \Y $or$libresoc.v:181051$11991_Y
end
- attribute \src "libresoc.v:183257.7-183257.20"
- process $proc$libresoc.v:183257$12089
+ attribute \src "libresoc.v:181010.7-181010.20"
+ process $proc$libresoc.v:181010$11997
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183279.7-183279.19"
- process $proc$libresoc.v:183279$12090
+ attribute \src "libresoc.v:181032.7-181032.19"
+ process $proc$libresoc.v:181032$11998
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183300.3-183301.27"
- process $proc$libresoc.v:183300$12085
+ attribute \src "libresoc.v:181053.3-181054.27"
+ process $proc$libresoc.v:181053$11993
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183302.3-183310.6"
- process $proc$libresoc.v:183302$12086
+ attribute \src "libresoc.v:181055.3-181063.6"
+ process $proc$libresoc.v:181055$11994
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12087 $1\q_int$next[0:0]$12088
- attribute \src "libresoc.v:183303.5-183303.29"
+ assign $0\q_int$next[0:0]$11995 $1\q_int$next[0:0]$11996
+ attribute \src "libresoc.v:181056.5-181056.29"
switch \initial
- attribute \src "libresoc.v:183303.9-183303.17"
+ attribute \src "libresoc.v:181056.9-181056.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12088 1'0
+ assign $1\q_int$next[0:0]$11996 1'0
case
- assign $1\q_int$next[0:0]$12088 \$5
+ assign $1\q_int$next[0:0]$11996 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12087
+ update \q_int$next $0\q_int$next[0:0]$11995
end
- connect \$9 $and$libresoc.v:183292$12077_Y
- connect \$11 $or$libresoc.v:183293$12078_Y
- connect \$13 $not$libresoc.v:183294$12079_Y
- connect \$15 $or$libresoc.v:183295$12080_Y
- connect \$1 $not$libresoc.v:183296$12081_Y
- connect \$3 $and$libresoc.v:183297$12082_Y
- connect \$5 $or$libresoc.v:183298$12083_Y
- connect \$7 $not$libresoc.v:183299$12084_Y
+ connect \$9 $and$libresoc.v:181045$11985_Y
+ connect \$11 $or$libresoc.v:181046$11986_Y
+ connect \$13 $not$libresoc.v:181047$11987_Y
+ connect \$15 $or$libresoc.v:181048$11988_Y
+ connect \$1 $not$libresoc.v:181049$11989_Y
+ connect \$3 $and$libresoc.v:181050$11990_Y
+ connect \$5 $or$libresoc.v:181051$11991_Y
+ connect \$7 $not$libresoc.v:181052$11992_Y
connect \qlq_rdok \$15
connect \qn_rdok \$13
connect \q_rdok \$11
end
-attribute \src "libresoc.v:183318.1-183669.10"
+attribute \src "libresoc.v:181071.1-181422.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator"
attribute \generator "nMigen"
module \rotator
- attribute \src "libresoc.v:183587.3-183596.6"
+ attribute \src "libresoc.v:181340.3-181349.6"
wire $0\carry_out_o[0:0]
- attribute \src "libresoc.v:183519.3-183533.6"
+ attribute \src "libresoc.v:181272.3-181286.6"
wire width 32 $0\hi32[31:0]
- attribute \src "libresoc.v:183319.7-183319.20"
+ attribute \src "libresoc.v:181072.7-181072.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183609.3-183642.6"
- wire width 7 $0\mb$8[6:0]$12138
- attribute \src "libresoc.v:183643.3-183657.6"
- wire width 7 $0\me$13[6:0]$12143
- attribute \src "libresoc.v:183544.3-183555.6"
+ attribute \src "libresoc.v:181362.3-181395.6"
+ wire width 7 $0\mb$8[6:0]$12046
+ attribute \src "libresoc.v:181396.3-181410.6"
+ wire width 7 $0\me$13[6:0]$12051
+ attribute \src "libresoc.v:181297.3-181308.6"
wire width 64 $0\mr[63:0]
- attribute \src "libresoc.v:183556.3-183567.6"
+ attribute \src "libresoc.v:181309.3-181320.6"
wire width 2 $0\output_mode[1:0]
- attribute \src "libresoc.v:183568.3-183586.6"
+ attribute \src "libresoc.v:181321.3-181339.6"
wire width 64 $0\result_o[63:0]
- attribute \src "libresoc.v:183534.3-183543.6"
+ attribute \src "libresoc.v:181287.3-181296.6"
wire width 7 $0\right_mask_shift[6:0]
- attribute \src "libresoc.v:183597.3-183608.6"
+ attribute \src "libresoc.v:181350.3-181361.6"
wire width 6 $0\rot_count[5:0]
- attribute \src "libresoc.v:183587.3-183596.6"
+ attribute \src "libresoc.v:181340.3-181349.6"
wire $1\carry_out_o[0:0]
- attribute \src "libresoc.v:183519.3-183533.6"
+ attribute \src "libresoc.v:181272.3-181286.6"
wire width 32 $1\hi32[31:0]
- attribute \src "libresoc.v:183609.3-183642.6"
- wire width 7 $1\mb$8[6:0]$12139
- attribute \src "libresoc.v:183643.3-183657.6"
- wire width 7 $1\me$13[6:0]$12144
- attribute \src "libresoc.v:183544.3-183555.6"
+ attribute \src "libresoc.v:181362.3-181395.6"
+ wire width 7 $1\mb$8[6:0]$12047
+ attribute \src "libresoc.v:181396.3-181410.6"
+ wire width 7 $1\me$13[6:0]$12052
+ attribute \src "libresoc.v:181297.3-181308.6"
wire width 64 $1\mr[63:0]
- attribute \src "libresoc.v:183556.3-183567.6"
+ attribute \src "libresoc.v:181309.3-181320.6"
wire width 2 $1\output_mode[1:0]
- attribute \src "libresoc.v:183568.3-183586.6"
+ attribute \src "libresoc.v:181321.3-181339.6"
wire width 64 $1\result_o[63:0]
- attribute \src "libresoc.v:183534.3-183543.6"
+ attribute \src "libresoc.v:181287.3-181296.6"
wire width 7 $1\right_mask_shift[6:0]
- attribute \src "libresoc.v:183597.3-183608.6"
+ attribute \src "libresoc.v:181350.3-181361.6"
wire width 6 $1\rot_count[5:0]
- attribute \src "libresoc.v:183609.3-183642.6"
- wire width 2 $2\mb$8[6:5]$12140
- attribute \src "libresoc.v:183609.3-183642.6"
- wire width 2 $3\mb$8[6:5]$12141
- attribute \src "libresoc.v:183470.18-183470.118"
- wire $and$libresoc.v:183470$12094_Y
- attribute \src "libresoc.v:183472.18-183472.114"
- wire $and$libresoc.v:183472$12096_Y
- attribute \src "libresoc.v:183481.18-183481.113"
- wire $and$libresoc.v:183481$12105_Y
- attribute \src "libresoc.v:183483.18-183483.114"
- wire $and$libresoc.v:183483$12107_Y
- attribute \src "libresoc.v:183485.18-183485.114"
- wire $and$libresoc.v:183485$12109_Y
- attribute \src "libresoc.v:183486.18-183486.103"
- wire width 64 $and$libresoc.v:183486$12110_Y
- attribute \src "libresoc.v:183487.18-183487.106"
- wire width 64 $and$libresoc.v:183487$12111_Y
- attribute \src "libresoc.v:183489.18-183489.103"
- wire width 64 $and$libresoc.v:183489$12113_Y
- attribute \src "libresoc.v:183491.18-183491.105"
- wire width 64 $and$libresoc.v:183491$12115_Y
- attribute \src "libresoc.v:183494.18-183494.106"
- wire width 64 $and$libresoc.v:183494$12118_Y
- attribute \src "libresoc.v:183497.18-183497.105"
- wire width 64 $and$libresoc.v:183497$12121_Y
- attribute \src "libresoc.v:183499.17-183499.109"
- wire $and$libresoc.v:183499$12123_Y
- attribute \src "libresoc.v:183500.18-183500.104"
- wire width 64 $and$libresoc.v:183500$12124_Y
- attribute \src "libresoc.v:183504.18-183504.105"
- wire width 64 $and$libresoc.v:183504$12128_Y
- attribute \src "libresoc.v:183468.17-183468.98"
- wire width 7 $extend$libresoc.v:183468$12091_Y
- attribute \src "libresoc.v:183484.18-183484.122"
- wire $gt$libresoc.v:183484$12108_Y
- attribute \src "libresoc.v:183474.18-183474.111"
- wire $le$libresoc.v:183474$12098_Y
- attribute \src "libresoc.v:183476.18-183476.111"
- wire $le$libresoc.v:183476$12100_Y
- attribute \src "libresoc.v:183477.17-183477.117"
- wire width 7 $neg$libresoc.v:183477$12101_Y
- attribute \src "libresoc.v:183469.18-183469.103"
- wire $not$libresoc.v:183469$12093_Y
- attribute \src "libresoc.v:183471.18-183471.108"
- wire $not$libresoc.v:183471$12095_Y
- attribute \src "libresoc.v:183473.18-183473.105"
- wire width 6 $not$libresoc.v:183473$12097_Y
- attribute \src "libresoc.v:183479.18-183479.112"
- wire width 64 $not$libresoc.v:183479$12103_Y
- attribute \src "libresoc.v:183480.18-183480.109"
- wire $not$libresoc.v:183480$12104_Y
- attribute \src "libresoc.v:183488.17-183488.105"
- wire $not$libresoc.v:183488$12112_Y
- attribute \src "libresoc.v:183490.18-183490.102"
- wire width 64 $not$libresoc.v:183490$12114_Y
- attribute \src "libresoc.v:183496.18-183496.102"
- wire width 64 $not$libresoc.v:183496$12120_Y
- attribute \src "libresoc.v:183501.18-183501.100"
- wire width 64 $not$libresoc.v:183501$12125_Y
- attribute \src "libresoc.v:183503.18-183503.100"
- wire width 64 $not$libresoc.v:183503$12127_Y
- attribute \src "libresoc.v:183482.18-183482.115"
- wire $or$libresoc.v:183482$12106_Y
- attribute \src "libresoc.v:183492.18-183492.108"
- wire width 64 $or$libresoc.v:183492$12116_Y
- attribute \src "libresoc.v:183493.18-183493.103"
- wire width 64 $or$libresoc.v:183493$12117_Y
- attribute \src "libresoc.v:183495.18-183495.103"
- wire width 64 $or$libresoc.v:183495$12119_Y
- attribute \src "libresoc.v:183498.18-183498.108"
- wire width 64 $or$libresoc.v:183498$12122_Y
- attribute \src "libresoc.v:183502.18-183502.106"
- wire width 64 $or$libresoc.v:183502$12126_Y
- attribute \src "libresoc.v:183468.17-183468.98"
- wire width 7 $pos$libresoc.v:183468$12092_Y
- attribute \src "libresoc.v:183505.18-183505.102"
- wire $reduce_or$libresoc.v:183505$12129_Y
- attribute \src "libresoc.v:183475.18-183475.109"
- wire width 8 $sub$libresoc.v:183475$12099_Y
- attribute \src "libresoc.v:183478.18-183478.110"
- wire width 8 $sub$libresoc.v:183478$12102_Y
+ attribute \src "libresoc.v:181362.3-181395.6"
+ wire width 2 $2\mb$8[6:5]$12048
+ attribute \src "libresoc.v:181362.3-181395.6"
+ wire width 2 $3\mb$8[6:5]$12049
+ attribute \src "libresoc.v:181223.18-181223.118"
+ wire $and$libresoc.v:181223$12002_Y
+ attribute \src "libresoc.v:181225.18-181225.114"
+ wire $and$libresoc.v:181225$12004_Y
+ attribute \src "libresoc.v:181234.18-181234.113"
+ wire $and$libresoc.v:181234$12013_Y
+ attribute \src "libresoc.v:181236.18-181236.114"
+ wire $and$libresoc.v:181236$12015_Y
+ attribute \src "libresoc.v:181238.18-181238.114"
+ wire $and$libresoc.v:181238$12017_Y
+ attribute \src "libresoc.v:181239.18-181239.103"
+ wire width 64 $and$libresoc.v:181239$12018_Y
+ attribute \src "libresoc.v:181240.18-181240.106"
+ wire width 64 $and$libresoc.v:181240$12019_Y
+ attribute \src "libresoc.v:181242.18-181242.103"
+ wire width 64 $and$libresoc.v:181242$12021_Y
+ attribute \src "libresoc.v:181244.18-181244.105"
+ wire width 64 $and$libresoc.v:181244$12023_Y
+ attribute \src "libresoc.v:181247.18-181247.106"
+ wire width 64 $and$libresoc.v:181247$12026_Y
+ attribute \src "libresoc.v:181250.18-181250.105"
+ wire width 64 $and$libresoc.v:181250$12029_Y
+ attribute \src "libresoc.v:181252.17-181252.109"
+ wire $and$libresoc.v:181252$12031_Y
+ attribute \src "libresoc.v:181253.18-181253.104"
+ wire width 64 $and$libresoc.v:181253$12032_Y
+ attribute \src "libresoc.v:181257.18-181257.105"
+ wire width 64 $and$libresoc.v:181257$12036_Y
+ attribute \src "libresoc.v:181221.17-181221.98"
+ wire width 7 $extend$libresoc.v:181221$11999_Y
+ attribute \src "libresoc.v:181237.18-181237.122"
+ wire $gt$libresoc.v:181237$12016_Y
+ attribute \src "libresoc.v:181227.18-181227.111"
+ wire $le$libresoc.v:181227$12006_Y
+ attribute \src "libresoc.v:181229.18-181229.111"
+ wire $le$libresoc.v:181229$12008_Y
+ attribute \src "libresoc.v:181230.17-181230.117"
+ wire width 7 $neg$libresoc.v:181230$12009_Y
+ attribute \src "libresoc.v:181222.18-181222.103"
+ wire $not$libresoc.v:181222$12001_Y
+ attribute \src "libresoc.v:181224.18-181224.108"
+ wire $not$libresoc.v:181224$12003_Y
+ attribute \src "libresoc.v:181226.18-181226.105"
+ wire width 6 $not$libresoc.v:181226$12005_Y
+ attribute \src "libresoc.v:181232.18-181232.112"
+ wire width 64 $not$libresoc.v:181232$12011_Y
+ attribute \src "libresoc.v:181233.18-181233.109"
+ wire $not$libresoc.v:181233$12012_Y
+ attribute \src "libresoc.v:181241.17-181241.105"
+ wire $not$libresoc.v:181241$12020_Y
+ attribute \src "libresoc.v:181243.18-181243.102"
+ wire width 64 $not$libresoc.v:181243$12022_Y
+ attribute \src "libresoc.v:181249.18-181249.102"
+ wire width 64 $not$libresoc.v:181249$12028_Y
+ attribute \src "libresoc.v:181254.18-181254.100"
+ wire width 64 $not$libresoc.v:181254$12033_Y
+ attribute \src "libresoc.v:181256.18-181256.100"
+ wire width 64 $not$libresoc.v:181256$12035_Y
+ attribute \src "libresoc.v:181235.18-181235.115"
+ wire $or$libresoc.v:181235$12014_Y
+ attribute \src "libresoc.v:181245.18-181245.108"
+ wire width 64 $or$libresoc.v:181245$12024_Y
+ attribute \src "libresoc.v:181246.18-181246.103"
+ wire width 64 $or$libresoc.v:181246$12025_Y
+ attribute \src "libresoc.v:181248.18-181248.103"
+ wire width 64 $or$libresoc.v:181248$12027_Y
+ attribute \src "libresoc.v:181251.18-181251.108"
+ wire width 64 $or$libresoc.v:181251$12030_Y
+ attribute \src "libresoc.v:181255.18-181255.106"
+ wire width 64 $or$libresoc.v:181255$12034_Y
+ attribute \src "libresoc.v:181221.17-181221.98"
+ wire width 7 $pos$libresoc.v:181221$12000_Y
+ attribute \src "libresoc.v:181258.18-181258.102"
+ wire $reduce_or$libresoc.v:181258$12037_Y
+ attribute \src "libresoc.v:181228.18-181228.109"
+ wire width 8 $sub$libresoc.v:181228$12007_Y
+ attribute \src "libresoc.v:181231.18-181231.110"
+ wire width 8 $sub$libresoc.v:181231$12010_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99"
wire width 7 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
wire input 10 \clear_right
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81"
wire width 32 \hi32
- attribute \src "libresoc.v:183319.7-183319.15"
+ attribute \src "libresoc.v:181072.7-181072.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
wire input 6 \is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
wire input 11 \sign_ext_rs
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
- cell $and $and$libresoc.v:183470$12094
+ cell $and $and$libresoc.v:181223$12002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \is_32bit
- connect \Y $and$libresoc.v:183470$12094_Y
+ connect \Y $and$libresoc.v:181223$12002_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
- cell $and $and$libresoc.v:183472$12096
+ cell $and $and$libresoc.v:181225$12004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \$16
- connect \Y $and$libresoc.v:183472$12096_Y
+ connect \Y $and$libresoc.v:181225$12004_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $and $and$libresoc.v:183481$12105
+ cell $and $and$libresoc.v:181234$12013
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_left
connect \B \$34
- connect \Y $and$libresoc.v:183481$12105_Y
+ connect \Y $and$libresoc.v:181234$12013_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
- cell $and $and$libresoc.v:183483$12107
+ cell $and $and$libresoc.v:181236$12015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \arith
connect \B \repl32 [63]
- connect \Y $and$libresoc.v:183483$12107_Y
+ connect \Y $and$libresoc.v:181236$12015_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
- cell $and $and$libresoc.v:183485$12109
+ cell $and $and$libresoc.v:181238$12017
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clear_right
connect \B \$42
- connect \Y $and$libresoc.v:183485$12109_Y
+ connect \Y $and$libresoc.v:181238$12017_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:183486$12110
+ cell $and $and$libresoc.v:181239$12018
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $and$libresoc.v:183486$12110_Y
+ connect \Y $and$libresoc.v:181239$12018_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:183487$12111
+ cell $and $and$libresoc.v:181240$12019
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$46
- connect \Y $and$libresoc.v:183487$12111_Y
+ connect \Y $and$libresoc.v:181240$12019_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:183489$12113
+ cell $and $and$libresoc.v:181242$12021
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $and$libresoc.v:183489$12113_Y
+ connect \Y $and$libresoc.v:181242$12021_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $and $and$libresoc.v:183491$12115
+ cell $and $and$libresoc.v:181244$12023
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \$50
- connect \Y $and$libresoc.v:183491$12115_Y
+ connect \Y $and$libresoc.v:181244$12023_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $and $and$libresoc.v:183494$12118
+ cell $and $and$libresoc.v:181247$12026
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$58
- connect \Y $and$libresoc.v:183494$12118_Y
+ connect \Y $and$libresoc.v:181247$12026_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $and $and$libresoc.v:183497$12121
+ cell $and $and$libresoc.v:181250$12029
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \$62
- connect \Y $and$libresoc.v:183497$12121_Y
+ connect \Y $and$libresoc.v:181250$12029_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- cell $and $and$libresoc.v:183499$12123
+ cell $and $and$libresoc.v:181252$12031
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \shift [6]
connect \B \$4
- connect \Y $and$libresoc.v:183499$12123_Y
+ connect \Y $and$libresoc.v:181252$12031_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174"
- cell $and $and$libresoc.v:183500$12124
+ cell $and $and$libresoc.v:181253$12032
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \mr
- connect \Y $and$libresoc.v:183500$12124_Y
+ connect \Y $and$libresoc.v:181253$12032_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $and $and$libresoc.v:183504$12128
+ cell $and $and$libresoc.v:181257$12036
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rs
connect \B \$77
- connect \Y $and$libresoc.v:183504$12128_Y
+ connect \Y $and$libresoc.v:181257$12036_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- cell $pos $extend$libresoc.v:183468$12091
+ cell $pos $extend$libresoc.v:181221$11999
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 7
connect \A \mb
- connect \Y $extend$libresoc.v:183468$12091_Y
+ connect \Y $extend$libresoc.v:181221$11999_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
- cell $gt $gt$libresoc.v:183484$12108
+ cell $gt $gt$libresoc.v:181237$12016
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8 [5:0]
connect \B \me$13 [5:0]
- connect \Y $gt$libresoc.v:183484$12108_Y
+ connect \Y $gt$libresoc.v:181237$12016_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- cell $le $le$libresoc.v:183474$12098
+ cell $le $le$libresoc.v:181227$12006
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8
connect \B 7'1000000
- connect \Y $le$libresoc.v:183474$12098_Y
+ connect \Y $le$libresoc.v:181227$12006_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- cell $le $le$libresoc.v:183476$12100
+ cell $le $le$libresoc.v:181229$12008
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mb$8
connect \B 7'1000000
- connect \Y $le$libresoc.v:183476$12100_Y
+ connect \Y $le$libresoc.v:181229$12008_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99"
- cell $neg $neg$libresoc.v:183477$12101
+ cell $neg $neg$libresoc.v:181230$12009
parameter \A_SIGNED 1
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
connect \A { \shift_signed [5] \shift_signed }
- connect \Y $neg$libresoc.v:183477$12101_Y
+ connect \Y $neg$libresoc.v:181230$12009_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- cell $not $not$libresoc.v:183469$12093
+ cell $not $not$libresoc.v:181222$12001
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sh [5]
- connect \Y $not$libresoc.v:183469$12093_Y
+ connect \Y $not$libresoc.v:181222$12001_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
- cell $not $not$libresoc.v:183471$12095
+ cell $not $not$libresoc.v:181224$12003
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \clear_left
- connect \Y $not$libresoc.v:183471$12095_Y
+ connect \Y $not$libresoc.v:181224$12003_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139"
- cell $not $not$libresoc.v:183473$12097
+ cell $not $not$libresoc.v:181226$12005
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \sh [5:0]
- connect \Y $not$libresoc.v:183473$12097_Y
+ connect \Y $not$libresoc.v:181226$12005_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
- cell $not $not$libresoc.v:183479$12103
+ cell $not $not$libresoc.v:181232$12011
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \left_mask_mask
- connect \Y $not$libresoc.v:183479$12103_Y
+ connect \Y $not$libresoc.v:181232$12011_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $not $not$libresoc.v:183480$12104
+ cell $not $not$libresoc.v:181233$12012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \clear_right
- connect \Y $not$libresoc.v:183480$12104_Y
+ connect \Y $not$libresoc.v:181233$12012_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- cell $not $not$libresoc.v:183488$12112
+ cell $not $not$libresoc.v:181241$12020
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_32bit
- connect \Y $not$libresoc.v:183488$12112_Y
+ connect \Y $not$libresoc.v:181241$12020_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $not $not$libresoc.v:183490$12114
+ cell $not $not$libresoc.v:181243$12022
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \$51
- connect \Y $not$libresoc.v:183490$12114_Y
+ connect \Y $not$libresoc.v:181243$12022_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $not $not$libresoc.v:183496$12120
+ cell $not $not$libresoc.v:181249$12028
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \$63
- connect \Y $not$libresoc.v:183496$12120_Y
+ connect \Y $not$libresoc.v:181249$12028_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176"
- cell $not $not$libresoc.v:183501$12125
+ cell $not $not$libresoc.v:181254$12033
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \mr
- connect \Y $not$libresoc.v:183501$12125_Y
+ connect \Y $not$libresoc.v:181254$12033_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $not $not$libresoc.v:183503$12127
+ cell $not $not$libresoc.v:181256$12035
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ml
- connect \Y $not$libresoc.v:183503$12127_Y
+ connect \Y $not$libresoc.v:181256$12035_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
- cell $or $or$libresoc.v:183482$12106
+ cell $or $or$libresoc.v:181235$12014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \right_shift
- connect \Y $or$libresoc.v:183482$12106_Y
+ connect \Y $or$libresoc.v:181235$12014_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170"
- cell $or $or$libresoc.v:183492$12116
+ cell $or $or$libresoc.v:181245$12024
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \$48
connect \B \$54
- connect \Y $or$libresoc.v:183492$12116_Y
+ connect \Y $or$libresoc.v:181245$12024_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:183493$12117
+ cell $or $or$libresoc.v:181246$12025
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $or$libresoc.v:183493$12117_Y
+ connect \Y $or$libresoc.v:181246$12025_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:183495$12119
+ cell $or $or$libresoc.v:181248$12027
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \mr
connect \B \ml
- connect \Y $or$libresoc.v:183495$12119_Y
+ connect \Y $or$libresoc.v:181248$12027_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172"
- cell $or $or$libresoc.v:183498$12122
+ cell $or $or$libresoc.v:181251$12030
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \$60
connect \B \$66
- connect \Y $or$libresoc.v:183498$12122_Y
+ connect \Y $or$libresoc.v:181251$12030_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176"
- cell $or $or$libresoc.v:183502$12126
+ cell $or $or$libresoc.v:181255$12034
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \rot
connect \B \$72
- connect \Y $or$libresoc.v:183502$12126_Y
+ connect \Y $or$libresoc.v:181255$12034_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- cell $pos $pos$libresoc.v:183468$12092
+ cell $pos $pos$libresoc.v:181221$12000
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 7
- connect \A $extend$libresoc.v:183468$12091_Y
- connect \Y $pos$libresoc.v:183468$12092_Y
+ connect \A $extend$libresoc.v:181221$11999_Y
+ connect \Y $pos$libresoc.v:181221$12000_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178"
- cell $reduce_or $reduce_or$libresoc.v:183505$12129
+ cell $reduce_or $reduce_or$libresoc.v:181258$12037
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \$79
- connect \Y $reduce_or$libresoc.v:183505$12129_Y
+ connect \Y $reduce_or$libresoc.v:181258$12037_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
- cell $sub $sub$libresoc.v:183475$12099
+ cell $sub $sub$libresoc.v:181228$12007
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 7'1000000
connect \B \mb$8
- connect \Y $sub$libresoc.v:183475$12099_Y
+ connect \Y $sub$libresoc.v:181228$12007_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $sub $sub$libresoc.v:183478$12102
+ cell $sub $sub$libresoc.v:181231$12010
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 6'111111
connect \B \me$13
- connect \Y $sub$libresoc.v:183478$12102_Y
+ connect \Y $sub$libresoc.v:181231$12010_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:183506.13-183509.4"
+ attribute \src "libresoc.v:181259.13-181262.4"
cell \left_mask \left_mask
connect \mask \left_mask_mask
connect \shift \left_mask_shift
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:183510.14-183513.4"
+ attribute \src "libresoc.v:181263.14-181266.4"
cell \right_mask \right_mask
connect \mask \right_mask_mask
connect \shift \right_mask_shift
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:183514.8-183518.4"
+ attribute \src "libresoc.v:181267.8-181271.4"
cell \rotl \rotl
connect \a \rotl_a
connect \b \rotl_b
connect \o \rotl_o
end
- attribute \src "libresoc.v:183319.7-183319.20"
- process $proc$libresoc.v:183319$12145
+ attribute \src "libresoc.v:181072.7-181072.20"
+ process $proc$libresoc.v:181072$12053
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183519.3-183533.6"
- process $proc$libresoc.v:183519$12130
+ attribute \src "libresoc.v:181272.3-181286.6"
+ process $proc$libresoc.v:181272$12038
assign { } { }
assign $0\hi32[31:0] $1\hi32[31:0]
- attribute \src "libresoc.v:183520.5-183520.29"
+ attribute \src "libresoc.v:181273.5-181273.29"
switch \initial
- attribute \src "libresoc.v:183520.9-183520.17"
+ attribute \src "libresoc.v:181273.9-181273.17"
case 1'1
case
end
sync always
update \hi32 $0\hi32[31:0]
end
- attribute \src "libresoc.v:183534.3-183543.6"
- process $proc$libresoc.v:183534$12131
+ attribute \src "libresoc.v:181287.3-181296.6"
+ process $proc$libresoc.v:181287$12039
assign { } { }
assign { } { }
assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0]
- attribute \src "libresoc.v:183535.5-183535.29"
+ attribute \src "libresoc.v:181288.5-181288.29"
switch \initial
- attribute \src "libresoc.v:183535.9-183535.17"
+ attribute \src "libresoc.v:181288.9-181288.17"
case 1'1
case
end
sync always
update \right_mask_shift $0\right_mask_shift[6:0]
end
- attribute \src "libresoc.v:183544.3-183555.6"
- process $proc$libresoc.v:183544$12132
+ attribute \src "libresoc.v:181297.3-181308.6"
+ process $proc$libresoc.v:181297$12040
assign { } { }
assign $0\mr[63:0] $1\mr[63:0]
- attribute \src "libresoc.v:183545.5-183545.29"
+ attribute \src "libresoc.v:181298.5-181298.29"
switch \initial
- attribute \src "libresoc.v:183545.9-183545.17"
+ attribute \src "libresoc.v:181298.9-181298.17"
case 1'1
case
end
sync always
update \mr $0\mr[63:0]
end
- attribute \src "libresoc.v:183556.3-183567.6"
- process $proc$libresoc.v:183556$12133
+ attribute \src "libresoc.v:181309.3-181320.6"
+ process $proc$libresoc.v:181309$12041
assign { } { }
assign $0\output_mode[1:0] $1\output_mode[1:0]
- attribute \src "libresoc.v:183557.5-183557.29"
+ attribute \src "libresoc.v:181310.5-181310.29"
switch \initial
- attribute \src "libresoc.v:183557.9-183557.17"
+ attribute \src "libresoc.v:181310.9-181310.17"
case 1'1
case
end
sync always
update \output_mode $0\output_mode[1:0]
end
- attribute \src "libresoc.v:183568.3-183586.6"
- process $proc$libresoc.v:183568$12134
+ attribute \src "libresoc.v:181321.3-181339.6"
+ process $proc$libresoc.v:181321$12042
assign { } { }
assign { } { }
assign $0\result_o[63:0] $1\result_o[63:0]
- attribute \src "libresoc.v:183569.5-183569.29"
+ attribute \src "libresoc.v:181322.5-181322.29"
switch \initial
- attribute \src "libresoc.v:183569.9-183569.17"
+ attribute \src "libresoc.v:181322.9-181322.17"
case 1'1
case
end
sync always
update \result_o $0\result_o[63:0]
end
- attribute \src "libresoc.v:183587.3-183596.6"
- process $proc$libresoc.v:183587$12135
+ attribute \src "libresoc.v:181340.3-181349.6"
+ process $proc$libresoc.v:181340$12043
assign { } { }
assign { } { }
assign $0\carry_out_o[0:0] $1\carry_out_o[0:0]
- attribute \src "libresoc.v:183588.5-183588.29"
+ attribute \src "libresoc.v:181341.5-181341.29"
switch \initial
- attribute \src "libresoc.v:183588.9-183588.17"
+ attribute \src "libresoc.v:181341.9-181341.17"
case 1'1
case
end
sync always
update \carry_out_o $0\carry_out_o[0:0]
end
- attribute \src "libresoc.v:183597.3-183608.6"
- process $proc$libresoc.v:183597$12136
+ attribute \src "libresoc.v:181350.3-181361.6"
+ process $proc$libresoc.v:181350$12044
assign { } { }
assign $0\rot_count[5:0] $1\rot_count[5:0]
- attribute \src "libresoc.v:183598.5-183598.29"
+ attribute \src "libresoc.v:181351.5-181351.29"
switch \initial
- attribute \src "libresoc.v:183598.9-183598.17"
+ attribute \src "libresoc.v:181351.9-181351.17"
case 1'1
case
end
sync always
update \rot_count $0\rot_count[5:0]
end
- attribute \src "libresoc.v:183609.3-183642.6"
- process $proc$libresoc.v:183609$12137
+ attribute \src "libresoc.v:181362.3-181395.6"
+ process $proc$libresoc.v:181362$12045
assign { } { }
- assign $0\mb$8[6:0]$12138 $1\mb$8[6:0]$12139
- attribute \src "libresoc.v:183610.5-183610.29"
+ assign $0\mb$8[6:0]$12046 $1\mb$8[6:0]$12047
+ attribute \src "libresoc.v:181363.5-181363.29"
switch \initial
- attribute \src "libresoc.v:183610.9-183610.17"
+ attribute \src "libresoc.v:181363.9-181363.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\mb$8[6:0]$12139 [4:0] \$9 [4:0]
- assign $1\mb$8[6:0]$12139 [6:5] $2\mb$8[6:5]$12140
+ assign $1\mb$8[6:0]$12047 [4:0] \$9 [4:0]
+ assign $1\mb$8[6:0]$12047 [6:5] $2\mb$8[6:5]$12048
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
switch \is_32bit
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\mb$8[6:5]$12140 2'01
+ assign $2\mb$8[6:5]$12048 2'01
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\mb$8[6:5]$12140 { 1'0 \mb_extra }
+ assign $2\mb$8[6:5]$12048 { 1'0 \mb_extra }
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\mb$8[6:0]$12139 [4:0] \sh [4:0]
- assign $1\mb$8[6:0]$12139 [6:5] $3\mb$8[6:5]$12141
+ assign $1\mb$8[6:0]$12047 [4:0] \sh [4:0]
+ assign $1\mb$8[6:0]$12047 [6:5] $3\mb$8[6:5]$12049
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
switch \is_32bit
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\mb$8[6:5]$12141 { \sh [5] \$11 }
+ assign $3\mb$8[6:5]$12049 { \sh [5] \$11 }
case
- assign $3\mb$8[6:5]$12141 \sh [6:5]
+ assign $3\mb$8[6:5]$12049 \sh [6:5]
end
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\mb$8[6:0]$12139 { 1'0 \is_32bit 5'00000 }
+ assign $1\mb$8[6:0]$12047 { 1'0 \is_32bit 5'00000 }
end
sync always
- update \mb$8 $0\mb$8[6:0]$12138
+ update \mb$8 $0\mb$8[6:0]$12046
end
- attribute \src "libresoc.v:183643.3-183657.6"
- process $proc$libresoc.v:183643$12142
+ attribute \src "libresoc.v:181396.3-181410.6"
+ process $proc$libresoc.v:181396$12050
assign { } { }
- assign $0\me$13[6:0]$12143 $1\me$13[6:0]$12144
- attribute \src "libresoc.v:183644.5-183644.29"
+ assign $0\me$13[6:0]$12051 $1\me$13[6:0]$12052
+ attribute \src "libresoc.v:181397.5-181397.29"
switch \initial
- attribute \src "libresoc.v:183644.9-183644.17"
+ attribute \src "libresoc.v:181397.9-181397.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\me$13[6:0]$12144 { 2'01 \me }
+ assign $1\me$13[6:0]$12052 { 2'01 \me }
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\me$13[6:0]$12144 { 1'0 \mb_extra \mb }
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $1\me$13[6:0]$12144 { \sh [6] \$20 }
- end
- sync always
- update \me$13 $0\me$13[6:0]$12143
- end
- connect \$9 $pos$libresoc.v:183468$12092_Y
- connect \$11 $not$libresoc.v:183469$12093_Y
- connect \$14 $and$libresoc.v:183470$12094_Y
- connect \$16 $not$libresoc.v:183471$12095_Y
- connect \$18 $and$libresoc.v:183472$12096_Y
- connect \$20 $not$libresoc.v:183473$12097_Y
- connect \$22 $le$libresoc.v:183474$12098_Y
- connect \$25 $sub$libresoc.v:183475$12099_Y
- connect \$27 $le$libresoc.v:183476$12100_Y
- connect \$2 $neg$libresoc.v:183477$12101_Y
- connect \$30 $sub$libresoc.v:183478$12102_Y
- connect \$32 $not$libresoc.v:183479$12103_Y
- connect \$34 $not$libresoc.v:183480$12104_Y
- connect \$36 $and$libresoc.v:183481$12105_Y
- connect \$38 $or$libresoc.v:183482$12106_Y
- connect \$40 $and$libresoc.v:183483$12107_Y
- connect \$42 $gt$libresoc.v:183484$12108_Y
- connect \$44 $and$libresoc.v:183485$12109_Y
- connect \$46 $and$libresoc.v:183486$12110_Y
- connect \$48 $and$libresoc.v:183487$12111_Y
- connect \$4 $not$libresoc.v:183488$12112_Y
- connect \$51 $and$libresoc.v:183489$12113_Y
- connect \$50 $not$libresoc.v:183490$12114_Y
- connect \$54 $and$libresoc.v:183491$12115_Y
- connect \$56 $or$libresoc.v:183492$12116_Y
- connect \$58 $or$libresoc.v:183493$12117_Y
- connect \$60 $and$libresoc.v:183494$12118_Y
- connect \$63 $or$libresoc.v:183495$12119_Y
- connect \$62 $not$libresoc.v:183496$12120_Y
- connect \$66 $and$libresoc.v:183497$12121_Y
- connect \$68 $or$libresoc.v:183498$12122_Y
- connect \$6 $and$libresoc.v:183499$12123_Y
- connect \$70 $and$libresoc.v:183500$12124_Y
- connect \$72 $not$libresoc.v:183501$12125_Y
- connect \$74 $or$libresoc.v:183502$12126_Y
- connect \$77 $not$libresoc.v:183503$12127_Y
- connect \$79 $and$libresoc.v:183504$12128_Y
- connect \$76 $reduce_or$libresoc.v:183505$12129_Y
+ assign $1\me$13[6:0]$12052 { 1'0 \mb_extra \mb }
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $1\me$13[6:0]$12052 { \sh [6] \$20 }
+ end
+ sync always
+ update \me$13 $0\me$13[6:0]$12051
+ end
+ connect \$9 $pos$libresoc.v:181221$12000_Y
+ connect \$11 $not$libresoc.v:181222$12001_Y
+ connect \$14 $and$libresoc.v:181223$12002_Y
+ connect \$16 $not$libresoc.v:181224$12003_Y
+ connect \$18 $and$libresoc.v:181225$12004_Y
+ connect \$20 $not$libresoc.v:181226$12005_Y
+ connect \$22 $le$libresoc.v:181227$12006_Y
+ connect \$25 $sub$libresoc.v:181228$12007_Y
+ connect \$27 $le$libresoc.v:181229$12008_Y
+ connect \$2 $neg$libresoc.v:181230$12009_Y
+ connect \$30 $sub$libresoc.v:181231$12010_Y
+ connect \$32 $not$libresoc.v:181232$12011_Y
+ connect \$34 $not$libresoc.v:181233$12012_Y
+ connect \$36 $and$libresoc.v:181234$12013_Y
+ connect \$38 $or$libresoc.v:181235$12014_Y
+ connect \$40 $and$libresoc.v:181236$12015_Y
+ connect \$42 $gt$libresoc.v:181237$12016_Y
+ connect \$44 $and$libresoc.v:181238$12017_Y
+ connect \$46 $and$libresoc.v:181239$12018_Y
+ connect \$48 $and$libresoc.v:181240$12019_Y
+ connect \$4 $not$libresoc.v:181241$12020_Y
+ connect \$51 $and$libresoc.v:181242$12021_Y
+ connect \$50 $not$libresoc.v:181243$12022_Y
+ connect \$54 $and$libresoc.v:181244$12023_Y
+ connect \$56 $or$libresoc.v:181245$12024_Y
+ connect \$58 $or$libresoc.v:181246$12025_Y
+ connect \$60 $and$libresoc.v:181247$12026_Y
+ connect \$63 $or$libresoc.v:181248$12027_Y
+ connect \$62 $not$libresoc.v:181249$12028_Y
+ connect \$66 $and$libresoc.v:181250$12029_Y
+ connect \$68 $or$libresoc.v:181251$12030_Y
+ connect \$6 $and$libresoc.v:181252$12031_Y
+ connect \$70 $and$libresoc.v:181253$12032_Y
+ connect \$72 $not$libresoc.v:181254$12033_Y
+ connect \$74 $or$libresoc.v:181255$12034_Y
+ connect \$77 $not$libresoc.v:181256$12035_Y
+ connect \$79 $and$libresoc.v:181257$12036_Y
+ connect \$76 $reduce_or$libresoc.v:181258$12037_Y
connect \$1 \$2
connect \$24 \$25
connect \$29 \$30
connect \shift_signed \shift [5:0]
connect \repl32 { \hi32 \rs [31:0] }
end
-attribute \src "libresoc.v:183673.1-183687.10"
+attribute \src "libresoc.v:181426.1-181440.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl"
attribute \generator "nMigen"
module \rotl
- attribute \src "libresoc.v:183685.17-183685.32"
- wire width 128 $shr$libresoc.v:183685$12147_Y
- attribute \src "libresoc.v:183684.17-183684.100"
- wire width 8 $sub$libresoc.v:183684$12146_Y
+ attribute \src "libresoc.v:181438.17-181438.32"
+ wire width 128 $shr$libresoc.v:181438$12055_Y
+ attribute \src "libresoc.v:181437.17-181437.100"
+ wire width 8 $sub$libresoc.v:181437$12054_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
wire width 6 input 1 \b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
wire width 64 output 2 \o
- attribute \src "libresoc.v:183685.17-183685.32"
- cell $shr $shr$libresoc.v:183685$12147
+ attribute \src "libresoc.v:181438.17-181438.32"
+ cell $shr $shr$libresoc.v:181438$12055
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \B_SIGNED 0
parameter \Y_WIDTH 128
connect \A { \a \a }
connect \B \$2
- connect \Y $shr$libresoc.v:183685$12147_Y
+ connect \Y $shr$libresoc.v:181438$12055_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
- cell $sub $sub$libresoc.v:183684$12146
+ cell $sub $sub$libresoc.v:181437$12054
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 7'1000000
connect \B \b
- connect \Y $sub$libresoc.v:183684$12146_Y
+ connect \Y $sub$libresoc.v:181437$12054_Y
end
- connect \$2 $sub$libresoc.v:183684$12146_Y
- connect \$1 $shr$libresoc.v:183685$12147_Y [63:0]
+ connect \$2 $sub$libresoc.v:181437$12054_Y
+ connect \$1 $shr$libresoc.v:181438$12055_Y [63:0]
connect \o \$1
end
-attribute \src "libresoc.v:183691.1-183749.10"
+attribute \src "libresoc.v:181444.1-181502.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l"
attribute \generator "nMigen"
module \rst_l
- attribute \src "libresoc.v:183692.7-183692.20"
+ attribute \src "libresoc.v:181445.7-181445.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183737.3-183745.6"
- wire $0\q_int$next[0:0]$12158
- attribute \src "libresoc.v:183735.3-183736.27"
+ attribute \src "libresoc.v:181490.3-181498.6"
+ wire $0\q_int$next[0:0]$12066
+ attribute \src "libresoc.v:181488.3-181489.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183737.3-183745.6"
- wire $1\q_int$next[0:0]$12159
- attribute \src "libresoc.v:183714.7-183714.19"
+ attribute \src "libresoc.v:181490.3-181498.6"
+ wire $1\q_int$next[0:0]$12067
+ attribute \src "libresoc.v:181467.7-181467.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183727.17-183727.96"
- wire $and$libresoc.v:183727$12148_Y
- attribute \src "libresoc.v:183732.17-183732.96"
- wire $and$libresoc.v:183732$12153_Y
- attribute \src "libresoc.v:183729.18-183729.93"
- wire $not$libresoc.v:183729$12150_Y
- attribute \src "libresoc.v:183731.17-183731.92"
- wire $not$libresoc.v:183731$12152_Y
- attribute \src "libresoc.v:183734.17-183734.92"
- wire $not$libresoc.v:183734$12155_Y
- attribute \src "libresoc.v:183728.18-183728.98"
- wire $or$libresoc.v:183728$12149_Y
- attribute \src "libresoc.v:183730.18-183730.99"
- wire $or$libresoc.v:183730$12151_Y
- attribute \src "libresoc.v:183733.17-183733.97"
- wire $or$libresoc.v:183733$12154_Y
+ attribute \src "libresoc.v:181480.17-181480.96"
+ wire $and$libresoc.v:181480$12056_Y
+ attribute \src "libresoc.v:181485.17-181485.96"
+ wire $and$libresoc.v:181485$12061_Y
+ attribute \src "libresoc.v:181482.18-181482.93"
+ wire $not$libresoc.v:181482$12058_Y
+ attribute \src "libresoc.v:181484.17-181484.92"
+ wire $not$libresoc.v:181484$12060_Y
+ attribute \src "libresoc.v:181487.17-181487.92"
+ wire $not$libresoc.v:181487$12063_Y
+ attribute \src "libresoc.v:181481.18-181481.98"
+ wire $or$libresoc.v:181481$12057_Y
+ attribute \src "libresoc.v:181483.18-181483.99"
+ wire $or$libresoc.v:181483$12059_Y
+ attribute \src "libresoc.v:181486.17-181486.97"
+ wire $or$libresoc.v:181486$12062_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183692.7-183692.15"
+ attribute \src "libresoc.v:181445.7-181445.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183727$12148
+ cell $and $and$libresoc.v:181480$12056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183727$12148_Y
+ connect \Y $and$libresoc.v:181480$12056_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183732$12153
+ cell $and $and$libresoc.v:181485$12061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183732$12153_Y
+ connect \Y $and$libresoc.v:181485$12061_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183729$12150
+ cell $not $not$libresoc.v:181482$12058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:183729$12150_Y
+ connect \Y $not$libresoc.v:181482$12058_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183731$12152
+ cell $not $not$libresoc.v:181484$12060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183731$12152_Y
+ connect \Y $not$libresoc.v:181484$12060_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183734$12155
+ cell $not $not$libresoc.v:181487$12063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183734$12155_Y
+ connect \Y $not$libresoc.v:181487$12063_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183728$12149
+ cell $or $or$libresoc.v:181481$12057
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:183728$12149_Y
+ connect \Y $or$libresoc.v:181481$12057_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183730$12151
+ cell $or $or$libresoc.v:181483$12059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:183730$12151_Y
+ connect \Y $or$libresoc.v:181483$12059_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183733$12154
+ cell $or $or$libresoc.v:181486$12062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:183733$12154_Y
+ connect \Y $or$libresoc.v:181486$12062_Y
end
- attribute \src "libresoc.v:183692.7-183692.20"
- process $proc$libresoc.v:183692$12160
+ attribute \src "libresoc.v:181445.7-181445.20"
+ process $proc$libresoc.v:181445$12068
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183714.7-183714.19"
- process $proc$libresoc.v:183714$12161
+ attribute \src "libresoc.v:181467.7-181467.19"
+ process $proc$libresoc.v:181467$12069
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183735.3-183736.27"
- process $proc$libresoc.v:183735$12156
+ attribute \src "libresoc.v:181488.3-181489.27"
+ process $proc$libresoc.v:181488$12064
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183737.3-183745.6"
- process $proc$libresoc.v:183737$12157
+ attribute \src "libresoc.v:181490.3-181498.6"
+ process $proc$libresoc.v:181490$12065
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12158 $1\q_int$next[0:0]$12159
- attribute \src "libresoc.v:183738.5-183738.29"
+ assign $0\q_int$next[0:0]$12066 $1\q_int$next[0:0]$12067
+ attribute \src "libresoc.v:181491.5-181491.29"
switch \initial
- attribute \src "libresoc.v:183738.9-183738.17"
+ attribute \src "libresoc.v:181491.9-181491.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12159 1'0
+ assign $1\q_int$next[0:0]$12067 1'0
case
- assign $1\q_int$next[0:0]$12159 \$5
+ assign $1\q_int$next[0:0]$12067 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12158
+ update \q_int$next $0\q_int$next[0:0]$12066
end
- connect \$9 $and$libresoc.v:183727$12148_Y
- connect \$11 $or$libresoc.v:183728$12149_Y
- connect \$13 $not$libresoc.v:183729$12150_Y
- connect \$15 $or$libresoc.v:183730$12151_Y
- connect \$1 $not$libresoc.v:183731$12152_Y
- connect \$3 $and$libresoc.v:183732$12153_Y
- connect \$5 $or$libresoc.v:183733$12154_Y
- connect \$7 $not$libresoc.v:183734$12155_Y
+ connect \$9 $and$libresoc.v:181480$12056_Y
+ connect \$11 $or$libresoc.v:181481$12057_Y
+ connect \$13 $not$libresoc.v:181482$12058_Y
+ connect \$15 $or$libresoc.v:181483$12059_Y
+ connect \$1 $not$libresoc.v:181484$12060_Y
+ connect \$3 $and$libresoc.v:181485$12061_Y
+ connect \$5 $or$libresoc.v:181486$12062_Y
+ connect \$7 $not$libresoc.v:181487$12063_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:183753.1-183811.10"
+attribute \src "libresoc.v:181506.1-181564.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l"
attribute \generator "nMigen"
module \rst_l$104
- attribute \src "libresoc.v:183754.7-183754.20"
+ attribute \src "libresoc.v:181507.7-181507.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183799.3-183807.6"
- wire $0\q_int$next[0:0]$12172
- attribute \src "libresoc.v:183797.3-183798.27"
+ attribute \src "libresoc.v:181552.3-181560.6"
+ wire $0\q_int$next[0:0]$12080
+ attribute \src "libresoc.v:181550.3-181551.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183799.3-183807.6"
- wire $1\q_int$next[0:0]$12173
- attribute \src "libresoc.v:183776.7-183776.19"
+ attribute \src "libresoc.v:181552.3-181560.6"
+ wire $1\q_int$next[0:0]$12081
+ attribute \src "libresoc.v:181529.7-181529.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183789.17-183789.96"
- wire $and$libresoc.v:183789$12162_Y
- attribute \src "libresoc.v:183794.17-183794.96"
- wire $and$libresoc.v:183794$12167_Y
- attribute \src "libresoc.v:183791.18-183791.93"
- wire $not$libresoc.v:183791$12164_Y
- attribute \src "libresoc.v:183793.17-183793.92"
- wire $not$libresoc.v:183793$12166_Y
- attribute \src "libresoc.v:183796.17-183796.92"
- wire $not$libresoc.v:183796$12169_Y
- attribute \src "libresoc.v:183790.18-183790.98"
- wire $or$libresoc.v:183790$12163_Y
- attribute \src "libresoc.v:183792.18-183792.99"
- wire $or$libresoc.v:183792$12165_Y
- attribute \src "libresoc.v:183795.17-183795.97"
- wire $or$libresoc.v:183795$12168_Y
+ attribute \src "libresoc.v:181542.17-181542.96"
+ wire $and$libresoc.v:181542$12070_Y
+ attribute \src "libresoc.v:181547.17-181547.96"
+ wire $and$libresoc.v:181547$12075_Y
+ attribute \src "libresoc.v:181544.18-181544.93"
+ wire $not$libresoc.v:181544$12072_Y
+ attribute \src "libresoc.v:181546.17-181546.92"
+ wire $not$libresoc.v:181546$12074_Y
+ attribute \src "libresoc.v:181549.17-181549.92"
+ wire $not$libresoc.v:181549$12077_Y
+ attribute \src "libresoc.v:181543.18-181543.98"
+ wire $or$libresoc.v:181543$12071_Y
+ attribute \src "libresoc.v:181545.18-181545.99"
+ wire $or$libresoc.v:181545$12073_Y
+ attribute \src "libresoc.v:181548.17-181548.97"
+ wire $or$libresoc.v:181548$12076_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183754.7-183754.15"
+ attribute \src "libresoc.v:181507.7-181507.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183789$12162
+ cell $and $and$libresoc.v:181542$12070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183789$12162_Y
+ connect \Y $and$libresoc.v:181542$12070_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183794$12167
+ cell $and $and$libresoc.v:181547$12075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183794$12167_Y
+ connect \Y $and$libresoc.v:181547$12075_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183791$12164
+ cell $not $not$libresoc.v:181544$12072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:183791$12164_Y
+ connect \Y $not$libresoc.v:181544$12072_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183793$12166
+ cell $not $not$libresoc.v:181546$12074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183793$12166_Y
+ connect \Y $not$libresoc.v:181546$12074_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183796$12169
+ cell $not $not$libresoc.v:181549$12077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183796$12169_Y
+ connect \Y $not$libresoc.v:181549$12077_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183790$12163
+ cell $or $or$libresoc.v:181543$12071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:183790$12163_Y
+ connect \Y $or$libresoc.v:181543$12071_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183792$12165
+ cell $or $or$libresoc.v:181545$12073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:183792$12165_Y
+ connect \Y $or$libresoc.v:181545$12073_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183795$12168
+ cell $or $or$libresoc.v:181548$12076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:183795$12168_Y
+ connect \Y $or$libresoc.v:181548$12076_Y
end
- attribute \src "libresoc.v:183754.7-183754.20"
- process $proc$libresoc.v:183754$12174
+ attribute \src "libresoc.v:181507.7-181507.20"
+ process $proc$libresoc.v:181507$12082
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183776.7-183776.19"
- process $proc$libresoc.v:183776$12175
+ attribute \src "libresoc.v:181529.7-181529.19"
+ process $proc$libresoc.v:181529$12083
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183797.3-183798.27"
- process $proc$libresoc.v:183797$12170
+ attribute \src "libresoc.v:181550.3-181551.27"
+ process $proc$libresoc.v:181550$12078
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183799.3-183807.6"
- process $proc$libresoc.v:183799$12171
+ attribute \src "libresoc.v:181552.3-181560.6"
+ process $proc$libresoc.v:181552$12079
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12172 $1\q_int$next[0:0]$12173
- attribute \src "libresoc.v:183800.5-183800.29"
+ assign $0\q_int$next[0:0]$12080 $1\q_int$next[0:0]$12081
+ attribute \src "libresoc.v:181553.5-181553.29"
switch \initial
- attribute \src "libresoc.v:183800.9-183800.17"
+ attribute \src "libresoc.v:181553.9-181553.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12173 1'0
+ assign $1\q_int$next[0:0]$12081 1'0
case
- assign $1\q_int$next[0:0]$12173 \$5
+ assign $1\q_int$next[0:0]$12081 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12172
+ update \q_int$next $0\q_int$next[0:0]$12080
end
- connect \$9 $and$libresoc.v:183789$12162_Y
- connect \$11 $or$libresoc.v:183790$12163_Y
- connect \$13 $not$libresoc.v:183791$12164_Y
- connect \$15 $or$libresoc.v:183792$12165_Y
- connect \$1 $not$libresoc.v:183793$12166_Y
- connect \$3 $and$libresoc.v:183794$12167_Y
- connect \$5 $or$libresoc.v:183795$12168_Y
- connect \$7 $not$libresoc.v:183796$12169_Y
+ connect \$9 $and$libresoc.v:181542$12070_Y
+ connect \$11 $or$libresoc.v:181543$12071_Y
+ connect \$13 $not$libresoc.v:181544$12072_Y
+ connect \$15 $or$libresoc.v:181545$12073_Y
+ connect \$1 $not$libresoc.v:181546$12074_Y
+ connect \$3 $and$libresoc.v:181547$12075_Y
+ connect \$5 $or$libresoc.v:181548$12076_Y
+ connect \$7 $not$libresoc.v:181549$12077_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:183815.1-183873.10"
+attribute \src "libresoc.v:181568.1-181626.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l"
attribute \generator "nMigen"
module \rst_l$122
- attribute \src "libresoc.v:183816.7-183816.20"
+ attribute \src "libresoc.v:181569.7-181569.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183861.3-183869.6"
- wire $0\q_int$next[0:0]$12186
- attribute \src "libresoc.v:183859.3-183860.27"
+ attribute \src "libresoc.v:181614.3-181622.6"
+ wire $0\q_int$next[0:0]$12094
+ attribute \src "libresoc.v:181612.3-181613.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183861.3-183869.6"
- wire $1\q_int$next[0:0]$12187
- attribute \src "libresoc.v:183838.7-183838.19"
+ attribute \src "libresoc.v:181614.3-181622.6"
+ wire $1\q_int$next[0:0]$12095
+ attribute \src "libresoc.v:181591.7-181591.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183851.17-183851.96"
- wire $and$libresoc.v:183851$12176_Y
- attribute \src "libresoc.v:183856.17-183856.96"
- wire $and$libresoc.v:183856$12181_Y
- attribute \src "libresoc.v:183853.18-183853.93"
- wire $not$libresoc.v:183853$12178_Y
- attribute \src "libresoc.v:183855.17-183855.92"
- wire $not$libresoc.v:183855$12180_Y
- attribute \src "libresoc.v:183858.17-183858.92"
- wire $not$libresoc.v:183858$12183_Y
- attribute \src "libresoc.v:183852.18-183852.98"
- wire $or$libresoc.v:183852$12177_Y
- attribute \src "libresoc.v:183854.18-183854.99"
- wire $or$libresoc.v:183854$12179_Y
- attribute \src "libresoc.v:183857.17-183857.97"
- wire $or$libresoc.v:183857$12182_Y
+ attribute \src "libresoc.v:181604.17-181604.96"
+ wire $and$libresoc.v:181604$12084_Y
+ attribute \src "libresoc.v:181609.17-181609.96"
+ wire $and$libresoc.v:181609$12089_Y
+ attribute \src "libresoc.v:181606.18-181606.93"
+ wire $not$libresoc.v:181606$12086_Y
+ attribute \src "libresoc.v:181608.17-181608.92"
+ wire $not$libresoc.v:181608$12088_Y
+ attribute \src "libresoc.v:181611.17-181611.92"
+ wire $not$libresoc.v:181611$12091_Y
+ attribute \src "libresoc.v:181605.18-181605.98"
+ wire $or$libresoc.v:181605$12085_Y
+ attribute \src "libresoc.v:181607.18-181607.99"
+ wire $or$libresoc.v:181607$12087_Y
+ attribute \src "libresoc.v:181610.17-181610.97"
+ wire $or$libresoc.v:181610$12090_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183816.7-183816.15"
+ attribute \src "libresoc.v:181569.7-181569.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183851$12176
+ cell $and $and$libresoc.v:181604$12084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183851$12176_Y
+ connect \Y $and$libresoc.v:181604$12084_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183856$12181
+ cell $and $and$libresoc.v:181609$12089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183856$12181_Y
+ connect \Y $and$libresoc.v:181609$12089_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183853$12178
+ cell $not $not$libresoc.v:181606$12086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:183853$12178_Y
+ connect \Y $not$libresoc.v:181606$12086_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183855$12180
+ cell $not $not$libresoc.v:181608$12088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183855$12180_Y
+ connect \Y $not$libresoc.v:181608$12088_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183858$12183
+ cell $not $not$libresoc.v:181611$12091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183858$12183_Y
+ connect \Y $not$libresoc.v:181611$12091_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183852$12177
+ cell $or $or$libresoc.v:181605$12085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:183852$12177_Y
+ connect \Y $or$libresoc.v:181605$12085_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183854$12179
+ cell $or $or$libresoc.v:181607$12087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:183854$12179_Y
+ connect \Y $or$libresoc.v:181607$12087_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183857$12182
+ cell $or $or$libresoc.v:181610$12090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:183857$12182_Y
+ connect \Y $or$libresoc.v:181610$12090_Y
end
- attribute \src "libresoc.v:183816.7-183816.20"
- process $proc$libresoc.v:183816$12188
+ attribute \src "libresoc.v:181569.7-181569.20"
+ process $proc$libresoc.v:181569$12096
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183838.7-183838.19"
- process $proc$libresoc.v:183838$12189
+ attribute \src "libresoc.v:181591.7-181591.19"
+ process $proc$libresoc.v:181591$12097
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183859.3-183860.27"
- process $proc$libresoc.v:183859$12184
+ attribute \src "libresoc.v:181612.3-181613.27"
+ process $proc$libresoc.v:181612$12092
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183861.3-183869.6"
- process $proc$libresoc.v:183861$12185
+ attribute \src "libresoc.v:181614.3-181622.6"
+ process $proc$libresoc.v:181614$12093
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12186 $1\q_int$next[0:0]$12187
- attribute \src "libresoc.v:183862.5-183862.29"
+ assign $0\q_int$next[0:0]$12094 $1\q_int$next[0:0]$12095
+ attribute \src "libresoc.v:181615.5-181615.29"
switch \initial
- attribute \src "libresoc.v:183862.9-183862.17"
+ attribute \src "libresoc.v:181615.9-181615.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12187 1'0
+ assign $1\q_int$next[0:0]$12095 1'0
case
- assign $1\q_int$next[0:0]$12187 \$5
+ assign $1\q_int$next[0:0]$12095 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12186
+ update \q_int$next $0\q_int$next[0:0]$12094
end
- connect \$9 $and$libresoc.v:183851$12176_Y
- connect \$11 $or$libresoc.v:183852$12177_Y
- connect \$13 $not$libresoc.v:183853$12178_Y
- connect \$15 $or$libresoc.v:183854$12179_Y
- connect \$1 $not$libresoc.v:183855$12180_Y
- connect \$3 $and$libresoc.v:183856$12181_Y
- connect \$5 $or$libresoc.v:183857$12182_Y
- connect \$7 $not$libresoc.v:183858$12183_Y
+ connect \$9 $and$libresoc.v:181604$12084_Y
+ connect \$11 $or$libresoc.v:181605$12085_Y
+ connect \$13 $not$libresoc.v:181606$12086_Y
+ connect \$15 $or$libresoc.v:181607$12087_Y
+ connect \$1 $not$libresoc.v:181608$12088_Y
+ connect \$3 $and$libresoc.v:181609$12089_Y
+ connect \$5 $or$libresoc.v:181610$12090_Y
+ connect \$7 $not$libresoc.v:181611$12091_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:183877.1-183935.10"
+attribute \src "libresoc.v:181630.1-181688.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l"
attribute \generator "nMigen"
module \rst_l$129
- attribute \src "libresoc.v:183878.7-183878.20"
+ attribute \src "libresoc.v:181631.7-181631.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183923.3-183931.6"
- wire $0\q_int$next[0:0]$12200
- attribute \src "libresoc.v:183921.3-183922.27"
+ attribute \src "libresoc.v:181676.3-181684.6"
+ wire $0\q_int$next[0:0]$12108
+ attribute \src "libresoc.v:181674.3-181675.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183923.3-183931.6"
- wire $1\q_int$next[0:0]$12201
- attribute \src "libresoc.v:183900.7-183900.19"
+ attribute \src "libresoc.v:181676.3-181684.6"
+ wire $1\q_int$next[0:0]$12109
+ attribute \src "libresoc.v:181653.7-181653.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183913.17-183913.96"
- wire $and$libresoc.v:183913$12190_Y
- attribute \src "libresoc.v:183918.17-183918.96"
- wire $and$libresoc.v:183918$12195_Y
- attribute \src "libresoc.v:183915.18-183915.93"
- wire $not$libresoc.v:183915$12192_Y
- attribute \src "libresoc.v:183917.17-183917.92"
- wire $not$libresoc.v:183917$12194_Y
- attribute \src "libresoc.v:183920.17-183920.92"
- wire $not$libresoc.v:183920$12197_Y
- attribute \src "libresoc.v:183914.18-183914.98"
- wire $or$libresoc.v:183914$12191_Y
- attribute \src "libresoc.v:183916.18-183916.99"
- wire $or$libresoc.v:183916$12193_Y
- attribute \src "libresoc.v:183919.17-183919.97"
- wire $or$libresoc.v:183919$12196_Y
+ attribute \src "libresoc.v:181666.17-181666.96"
+ wire $and$libresoc.v:181666$12098_Y
+ attribute \src "libresoc.v:181671.17-181671.96"
+ wire $and$libresoc.v:181671$12103_Y
+ attribute \src "libresoc.v:181668.18-181668.93"
+ wire $not$libresoc.v:181668$12100_Y
+ attribute \src "libresoc.v:181670.17-181670.92"
+ wire $not$libresoc.v:181670$12102_Y
+ attribute \src "libresoc.v:181673.17-181673.92"
+ wire $not$libresoc.v:181673$12105_Y
+ attribute \src "libresoc.v:181667.18-181667.98"
+ wire $or$libresoc.v:181667$12099_Y
+ attribute \src "libresoc.v:181669.18-181669.99"
+ wire $or$libresoc.v:181669$12101_Y
+ attribute \src "libresoc.v:181672.17-181672.97"
+ wire $or$libresoc.v:181672$12104_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183878.7-183878.15"
+ attribute \src "libresoc.v:181631.7-181631.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183913$12190
+ cell $and $and$libresoc.v:181666$12098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183913$12190_Y
+ connect \Y $and$libresoc.v:181666$12098_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183918$12195
+ cell $and $and$libresoc.v:181671$12103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183918$12195_Y
+ connect \Y $and$libresoc.v:181671$12103_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183915$12192
+ cell $not $not$libresoc.v:181668$12100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:183915$12192_Y
+ connect \Y $not$libresoc.v:181668$12100_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183917$12194
+ cell $not $not$libresoc.v:181670$12102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183917$12194_Y
+ connect \Y $not$libresoc.v:181670$12102_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183920$12197
+ cell $not $not$libresoc.v:181673$12105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183920$12197_Y
+ connect \Y $not$libresoc.v:181673$12105_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183914$12191
+ cell $or $or$libresoc.v:181667$12099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:183914$12191_Y
+ connect \Y $or$libresoc.v:181667$12099_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183916$12193
+ cell $or $or$libresoc.v:181669$12101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:183916$12193_Y
+ connect \Y $or$libresoc.v:181669$12101_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183919$12196
+ cell $or $or$libresoc.v:181672$12104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:183919$12196_Y
+ connect \Y $or$libresoc.v:181672$12104_Y
end
- attribute \src "libresoc.v:183878.7-183878.20"
- process $proc$libresoc.v:183878$12202
+ attribute \src "libresoc.v:181631.7-181631.20"
+ process $proc$libresoc.v:181631$12110
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183900.7-183900.19"
- process $proc$libresoc.v:183900$12203
+ attribute \src "libresoc.v:181653.7-181653.19"
+ process $proc$libresoc.v:181653$12111
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183921.3-183922.27"
- process $proc$libresoc.v:183921$12198
+ attribute \src "libresoc.v:181674.3-181675.27"
+ process $proc$libresoc.v:181674$12106
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183923.3-183931.6"
- process $proc$libresoc.v:183923$12199
+ attribute \src "libresoc.v:181676.3-181684.6"
+ process $proc$libresoc.v:181676$12107
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12200 $1\q_int$next[0:0]$12201
- attribute \src "libresoc.v:183924.5-183924.29"
+ assign $0\q_int$next[0:0]$12108 $1\q_int$next[0:0]$12109
+ attribute \src "libresoc.v:181677.5-181677.29"
switch \initial
- attribute \src "libresoc.v:183924.9-183924.17"
+ attribute \src "libresoc.v:181677.9-181677.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12201 1'0
+ assign $1\q_int$next[0:0]$12109 1'0
case
- assign $1\q_int$next[0:0]$12201 \$5
+ assign $1\q_int$next[0:0]$12109 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12200
+ update \q_int$next $0\q_int$next[0:0]$12108
end
- connect \$9 $and$libresoc.v:183913$12190_Y
- connect \$11 $or$libresoc.v:183914$12191_Y
- connect \$13 $not$libresoc.v:183915$12192_Y
- connect \$15 $or$libresoc.v:183916$12193_Y
- connect \$1 $not$libresoc.v:183917$12194_Y
- connect \$3 $and$libresoc.v:183918$12195_Y
- connect \$5 $or$libresoc.v:183919$12196_Y
- connect \$7 $not$libresoc.v:183920$12197_Y
+ connect \$9 $and$libresoc.v:181666$12098_Y
+ connect \$11 $or$libresoc.v:181667$12099_Y
+ connect \$13 $not$libresoc.v:181668$12100_Y
+ connect \$15 $or$libresoc.v:181669$12101_Y
+ connect \$1 $not$libresoc.v:181670$12102_Y
+ connect \$3 $and$libresoc.v:181671$12103_Y
+ connect \$5 $or$libresoc.v:181672$12104_Y
+ connect \$7 $not$libresoc.v:181673$12105_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:183939.1-183997.10"
+attribute \src "libresoc.v:181692.1-181750.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l"
attribute \generator "nMigen"
module \rst_l$13
- attribute \src "libresoc.v:183940.7-183940.20"
+ attribute \src "libresoc.v:181693.7-181693.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:183985.3-183993.6"
- wire $0\q_int$next[0:0]$12214
- attribute \src "libresoc.v:183983.3-183984.27"
+ attribute \src "libresoc.v:181738.3-181746.6"
+ wire $0\q_int$next[0:0]$12122
+ attribute \src "libresoc.v:181736.3-181737.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:183985.3-183993.6"
- wire $1\q_int$next[0:0]$12215
- attribute \src "libresoc.v:183962.7-183962.19"
+ attribute \src "libresoc.v:181738.3-181746.6"
+ wire $1\q_int$next[0:0]$12123
+ attribute \src "libresoc.v:181715.7-181715.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:183975.17-183975.96"
- wire $and$libresoc.v:183975$12204_Y
- attribute \src "libresoc.v:183980.17-183980.96"
- wire $and$libresoc.v:183980$12209_Y
- attribute \src "libresoc.v:183977.18-183977.93"
- wire $not$libresoc.v:183977$12206_Y
- attribute \src "libresoc.v:183979.17-183979.92"
- wire $not$libresoc.v:183979$12208_Y
- attribute \src "libresoc.v:183982.17-183982.92"
- wire $not$libresoc.v:183982$12211_Y
- attribute \src "libresoc.v:183976.18-183976.98"
- wire $or$libresoc.v:183976$12205_Y
- attribute \src "libresoc.v:183978.18-183978.99"
- wire $or$libresoc.v:183978$12207_Y
- attribute \src "libresoc.v:183981.17-183981.97"
- wire $or$libresoc.v:183981$12210_Y
+ attribute \src "libresoc.v:181728.17-181728.96"
+ wire $and$libresoc.v:181728$12112_Y
+ attribute \src "libresoc.v:181733.17-181733.96"
+ wire $and$libresoc.v:181733$12117_Y
+ attribute \src "libresoc.v:181730.18-181730.93"
+ wire $not$libresoc.v:181730$12114_Y
+ attribute \src "libresoc.v:181732.17-181732.92"
+ wire $not$libresoc.v:181732$12116_Y
+ attribute \src "libresoc.v:181735.17-181735.92"
+ wire $not$libresoc.v:181735$12119_Y
+ attribute \src "libresoc.v:181729.18-181729.98"
+ wire $or$libresoc.v:181729$12113_Y
+ attribute \src "libresoc.v:181731.18-181731.99"
+ wire $or$libresoc.v:181731$12115_Y
+ attribute \src "libresoc.v:181734.17-181734.97"
+ wire $or$libresoc.v:181734$12118_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:183940.7-183940.15"
+ attribute \src "libresoc.v:181693.7-181693.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:183975$12204
+ cell $and $and$libresoc.v:181728$12112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:183975$12204_Y
+ connect \Y $and$libresoc.v:181728$12112_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:183980$12209
+ cell $and $and$libresoc.v:181733$12117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:183980$12209_Y
+ connect \Y $and$libresoc.v:181733$12117_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:183977$12206
+ cell $not $not$libresoc.v:181730$12114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:183977$12206_Y
+ connect \Y $not$libresoc.v:181730$12114_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:183979$12208
+ cell $not $not$libresoc.v:181732$12116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183979$12208_Y
+ connect \Y $not$libresoc.v:181732$12116_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:183982$12211
+ cell $not $not$libresoc.v:181735$12119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:183982$12211_Y
+ connect \Y $not$libresoc.v:181735$12119_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:183976$12205
+ cell $or $or$libresoc.v:181729$12113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:183976$12205_Y
+ connect \Y $or$libresoc.v:181729$12113_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:183978$12207
+ cell $or $or$libresoc.v:181731$12115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:183978$12207_Y
+ connect \Y $or$libresoc.v:181731$12115_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:183981$12210
+ cell $or $or$libresoc.v:181734$12118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:183981$12210_Y
+ connect \Y $or$libresoc.v:181734$12118_Y
end
- attribute \src "libresoc.v:183940.7-183940.20"
- process $proc$libresoc.v:183940$12216
+ attribute \src "libresoc.v:181693.7-181693.20"
+ process $proc$libresoc.v:181693$12124
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:183962.7-183962.19"
- process $proc$libresoc.v:183962$12217
+ attribute \src "libresoc.v:181715.7-181715.19"
+ process $proc$libresoc.v:181715$12125
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:183983.3-183984.27"
- process $proc$libresoc.v:183983$12212
+ attribute \src "libresoc.v:181736.3-181737.27"
+ process $proc$libresoc.v:181736$12120
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:183985.3-183993.6"
- process $proc$libresoc.v:183985$12213
+ attribute \src "libresoc.v:181738.3-181746.6"
+ process $proc$libresoc.v:181738$12121
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12214 $1\q_int$next[0:0]$12215
- attribute \src "libresoc.v:183986.5-183986.29"
+ assign $0\q_int$next[0:0]$12122 $1\q_int$next[0:0]$12123
+ attribute \src "libresoc.v:181739.5-181739.29"
switch \initial
- attribute \src "libresoc.v:183986.9-183986.17"
+ attribute \src "libresoc.v:181739.9-181739.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12215 1'0
+ assign $1\q_int$next[0:0]$12123 1'0
case
- assign $1\q_int$next[0:0]$12215 \$5
+ assign $1\q_int$next[0:0]$12123 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12214
+ update \q_int$next $0\q_int$next[0:0]$12122
end
- connect \$9 $and$libresoc.v:183975$12204_Y
- connect \$11 $or$libresoc.v:183976$12205_Y
- connect \$13 $not$libresoc.v:183977$12206_Y
- connect \$15 $or$libresoc.v:183978$12207_Y
- connect \$1 $not$libresoc.v:183979$12208_Y
- connect \$3 $and$libresoc.v:183980$12209_Y
- connect \$5 $or$libresoc.v:183981$12210_Y
- connect \$7 $not$libresoc.v:183982$12211_Y
+ connect \$9 $and$libresoc.v:181728$12112_Y
+ connect \$11 $or$libresoc.v:181729$12113_Y
+ connect \$13 $not$libresoc.v:181730$12114_Y
+ connect \$15 $or$libresoc.v:181731$12115_Y
+ connect \$1 $not$libresoc.v:181732$12116_Y
+ connect \$3 $and$libresoc.v:181733$12117_Y
+ connect \$5 $or$libresoc.v:181734$12118_Y
+ connect \$7 $not$libresoc.v:181735$12119_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184001.1-184059.10"
+attribute \src "libresoc.v:181754.1-181812.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l"
attribute \generator "nMigen"
module \rst_l$26
- attribute \src "libresoc.v:184002.7-184002.20"
+ attribute \src "libresoc.v:181755.7-181755.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184047.3-184055.6"
- wire $0\q_int$next[0:0]$12228
- attribute \src "libresoc.v:184045.3-184046.27"
+ attribute \src "libresoc.v:181800.3-181808.6"
+ wire $0\q_int$next[0:0]$12136
+ attribute \src "libresoc.v:181798.3-181799.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:184047.3-184055.6"
- wire $1\q_int$next[0:0]$12229
- attribute \src "libresoc.v:184024.7-184024.19"
+ attribute \src "libresoc.v:181800.3-181808.6"
+ wire $1\q_int$next[0:0]$12137
+ attribute \src "libresoc.v:181777.7-181777.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:184037.17-184037.96"
- wire $and$libresoc.v:184037$12218_Y
- attribute \src "libresoc.v:184042.17-184042.96"
- wire $and$libresoc.v:184042$12223_Y
- attribute \src "libresoc.v:184039.18-184039.93"
- wire $not$libresoc.v:184039$12220_Y
- attribute \src "libresoc.v:184041.17-184041.92"
- wire $not$libresoc.v:184041$12222_Y
- attribute \src "libresoc.v:184044.17-184044.92"
- wire $not$libresoc.v:184044$12225_Y
- attribute \src "libresoc.v:184038.18-184038.98"
- wire $or$libresoc.v:184038$12219_Y
- attribute \src "libresoc.v:184040.18-184040.99"
- wire $or$libresoc.v:184040$12221_Y
- attribute \src "libresoc.v:184043.17-184043.97"
- wire $or$libresoc.v:184043$12224_Y
+ attribute \src "libresoc.v:181790.17-181790.96"
+ wire $and$libresoc.v:181790$12126_Y
+ attribute \src "libresoc.v:181795.17-181795.96"
+ wire $and$libresoc.v:181795$12131_Y
+ attribute \src "libresoc.v:181792.18-181792.93"
+ wire $not$libresoc.v:181792$12128_Y
+ attribute \src "libresoc.v:181794.17-181794.92"
+ wire $not$libresoc.v:181794$12130_Y
+ attribute \src "libresoc.v:181797.17-181797.92"
+ wire $not$libresoc.v:181797$12133_Y
+ attribute \src "libresoc.v:181791.18-181791.98"
+ wire $or$libresoc.v:181791$12127_Y
+ attribute \src "libresoc.v:181793.18-181793.99"
+ wire $or$libresoc.v:181793$12129_Y
+ attribute \src "libresoc.v:181796.17-181796.97"
+ wire $or$libresoc.v:181796$12132_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184002.7-184002.15"
+ attribute \src "libresoc.v:181755.7-181755.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:184037$12218
+ cell $and $and$libresoc.v:181790$12126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:184037$12218_Y
+ connect \Y $and$libresoc.v:181790$12126_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:184042$12223
+ cell $and $and$libresoc.v:181795$12131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:184042$12223_Y
+ connect \Y $and$libresoc.v:181795$12131_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:184039$12220
+ cell $not $not$libresoc.v:181792$12128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:184039$12220_Y
+ connect \Y $not$libresoc.v:181792$12128_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:184041$12222
+ cell $not $not$libresoc.v:181794$12130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184041$12222_Y
+ connect \Y $not$libresoc.v:181794$12130_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:184044$12225
+ cell $not $not$libresoc.v:181797$12133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184044$12225_Y
+ connect \Y $not$libresoc.v:181797$12133_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:184038$12219
+ cell $or $or$libresoc.v:181791$12127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:184038$12219_Y
+ connect \Y $or$libresoc.v:181791$12127_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:184040$12221
+ cell $or $or$libresoc.v:181793$12129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:184040$12221_Y
+ connect \Y $or$libresoc.v:181793$12129_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:184043$12224
+ cell $or $or$libresoc.v:181796$12132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:184043$12224_Y
+ connect \Y $or$libresoc.v:181796$12132_Y
end
- attribute \src "libresoc.v:184002.7-184002.20"
- process $proc$libresoc.v:184002$12230
+ attribute \src "libresoc.v:181755.7-181755.20"
+ process $proc$libresoc.v:181755$12138
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184024.7-184024.19"
- process $proc$libresoc.v:184024$12231
+ attribute \src "libresoc.v:181777.7-181777.19"
+ process $proc$libresoc.v:181777$12139
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:184045.3-184046.27"
- process $proc$libresoc.v:184045$12226
+ attribute \src "libresoc.v:181798.3-181799.27"
+ process $proc$libresoc.v:181798$12134
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:184047.3-184055.6"
- process $proc$libresoc.v:184047$12227
+ attribute \src "libresoc.v:181800.3-181808.6"
+ process $proc$libresoc.v:181800$12135
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12228 $1\q_int$next[0:0]$12229
- attribute \src "libresoc.v:184048.5-184048.29"
+ assign $0\q_int$next[0:0]$12136 $1\q_int$next[0:0]$12137
+ attribute \src "libresoc.v:181801.5-181801.29"
switch \initial
- attribute \src "libresoc.v:184048.9-184048.17"
+ attribute \src "libresoc.v:181801.9-181801.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12229 1'0
+ assign $1\q_int$next[0:0]$12137 1'0
case
- assign $1\q_int$next[0:0]$12229 \$5
+ assign $1\q_int$next[0:0]$12137 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12228
+ update \q_int$next $0\q_int$next[0:0]$12136
end
- connect \$9 $and$libresoc.v:184037$12218_Y
- connect \$11 $or$libresoc.v:184038$12219_Y
- connect \$13 $not$libresoc.v:184039$12220_Y
- connect \$15 $or$libresoc.v:184040$12221_Y
- connect \$1 $not$libresoc.v:184041$12222_Y
- connect \$3 $and$libresoc.v:184042$12223_Y
- connect \$5 $or$libresoc.v:184043$12224_Y
- connect \$7 $not$libresoc.v:184044$12225_Y
+ connect \$9 $and$libresoc.v:181790$12126_Y
+ connect \$11 $or$libresoc.v:181791$12127_Y
+ connect \$13 $not$libresoc.v:181792$12128_Y
+ connect \$15 $or$libresoc.v:181793$12129_Y
+ connect \$1 $not$libresoc.v:181794$12130_Y
+ connect \$3 $and$libresoc.v:181795$12131_Y
+ connect \$5 $or$libresoc.v:181796$12132_Y
+ connect \$7 $not$libresoc.v:181797$12133_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184063.1-184121.10"
+attribute \src "libresoc.v:181816.1-181874.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l"
attribute \generator "nMigen"
module \rst_l$42
- attribute \src "libresoc.v:184064.7-184064.20"
+ attribute \src "libresoc.v:181817.7-181817.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184109.3-184117.6"
- wire $0\q_int$next[0:0]$12242
- attribute \src "libresoc.v:184107.3-184108.27"
+ attribute \src "libresoc.v:181862.3-181870.6"
+ wire $0\q_int$next[0:0]$12150
+ attribute \src "libresoc.v:181860.3-181861.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:184109.3-184117.6"
- wire $1\q_int$next[0:0]$12243
- attribute \src "libresoc.v:184086.7-184086.19"
+ attribute \src "libresoc.v:181862.3-181870.6"
+ wire $1\q_int$next[0:0]$12151
+ attribute \src "libresoc.v:181839.7-181839.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:184099.17-184099.96"
- wire $and$libresoc.v:184099$12232_Y
- attribute \src "libresoc.v:184104.17-184104.96"
- wire $and$libresoc.v:184104$12237_Y
- attribute \src "libresoc.v:184101.18-184101.93"
- wire $not$libresoc.v:184101$12234_Y
- attribute \src "libresoc.v:184103.17-184103.92"
- wire $not$libresoc.v:184103$12236_Y
- attribute \src "libresoc.v:184106.17-184106.92"
- wire $not$libresoc.v:184106$12239_Y
- attribute \src "libresoc.v:184100.18-184100.98"
- wire $or$libresoc.v:184100$12233_Y
- attribute \src "libresoc.v:184102.18-184102.99"
- wire $or$libresoc.v:184102$12235_Y
- attribute \src "libresoc.v:184105.17-184105.97"
- wire $or$libresoc.v:184105$12238_Y
+ attribute \src "libresoc.v:181852.17-181852.96"
+ wire $and$libresoc.v:181852$12140_Y
+ attribute \src "libresoc.v:181857.17-181857.96"
+ wire $and$libresoc.v:181857$12145_Y
+ attribute \src "libresoc.v:181854.18-181854.93"
+ wire $not$libresoc.v:181854$12142_Y
+ attribute \src "libresoc.v:181856.17-181856.92"
+ wire $not$libresoc.v:181856$12144_Y
+ attribute \src "libresoc.v:181859.17-181859.92"
+ wire $not$libresoc.v:181859$12147_Y
+ attribute \src "libresoc.v:181853.18-181853.98"
+ wire $or$libresoc.v:181853$12141_Y
+ attribute \src "libresoc.v:181855.18-181855.99"
+ wire $or$libresoc.v:181855$12143_Y
+ attribute \src "libresoc.v:181858.17-181858.97"
+ wire $or$libresoc.v:181858$12146_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184064.7-184064.15"
+ attribute \src "libresoc.v:181817.7-181817.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:184099$12232
+ cell $and $and$libresoc.v:181852$12140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:184099$12232_Y
+ connect \Y $and$libresoc.v:181852$12140_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:184104$12237
+ cell $and $and$libresoc.v:181857$12145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:184104$12237_Y
+ connect \Y $and$libresoc.v:181857$12145_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:184101$12234
+ cell $not $not$libresoc.v:181854$12142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:184101$12234_Y
+ connect \Y $not$libresoc.v:181854$12142_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:184103$12236
+ cell $not $not$libresoc.v:181856$12144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184103$12236_Y
+ connect \Y $not$libresoc.v:181856$12144_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:184106$12239
+ cell $not $not$libresoc.v:181859$12147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184106$12239_Y
+ connect \Y $not$libresoc.v:181859$12147_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:184100$12233
+ cell $or $or$libresoc.v:181853$12141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:184100$12233_Y
+ connect \Y $or$libresoc.v:181853$12141_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:184102$12235
+ cell $or $or$libresoc.v:181855$12143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:184102$12235_Y
+ connect \Y $or$libresoc.v:181855$12143_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:184105$12238
+ cell $or $or$libresoc.v:181858$12146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:184105$12238_Y
+ connect \Y $or$libresoc.v:181858$12146_Y
end
- attribute \src "libresoc.v:184064.7-184064.20"
- process $proc$libresoc.v:184064$12244
+ attribute \src "libresoc.v:181817.7-181817.20"
+ process $proc$libresoc.v:181817$12152
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184086.7-184086.19"
- process $proc$libresoc.v:184086$12245
+ attribute \src "libresoc.v:181839.7-181839.19"
+ process $proc$libresoc.v:181839$12153
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:184107.3-184108.27"
- process $proc$libresoc.v:184107$12240
+ attribute \src "libresoc.v:181860.3-181861.27"
+ process $proc$libresoc.v:181860$12148
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:184109.3-184117.6"
- process $proc$libresoc.v:184109$12241
+ attribute \src "libresoc.v:181862.3-181870.6"
+ process $proc$libresoc.v:181862$12149
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12242 $1\q_int$next[0:0]$12243
- attribute \src "libresoc.v:184110.5-184110.29"
+ assign $0\q_int$next[0:0]$12150 $1\q_int$next[0:0]$12151
+ attribute \src "libresoc.v:181863.5-181863.29"
switch \initial
- attribute \src "libresoc.v:184110.9-184110.17"
+ attribute \src "libresoc.v:181863.9-181863.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12243 1'0
+ assign $1\q_int$next[0:0]$12151 1'0
case
- assign $1\q_int$next[0:0]$12243 \$5
+ assign $1\q_int$next[0:0]$12151 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12242
+ update \q_int$next $0\q_int$next[0:0]$12150
end
- connect \$9 $and$libresoc.v:184099$12232_Y
- connect \$11 $or$libresoc.v:184100$12233_Y
- connect \$13 $not$libresoc.v:184101$12234_Y
- connect \$15 $or$libresoc.v:184102$12235_Y
- connect \$1 $not$libresoc.v:184103$12236_Y
- connect \$3 $and$libresoc.v:184104$12237_Y
- connect \$5 $or$libresoc.v:184105$12238_Y
- connect \$7 $not$libresoc.v:184106$12239_Y
+ connect \$9 $and$libresoc.v:181852$12140_Y
+ connect \$11 $or$libresoc.v:181853$12141_Y
+ connect \$13 $not$libresoc.v:181854$12142_Y
+ connect \$15 $or$libresoc.v:181855$12143_Y
+ connect \$1 $not$libresoc.v:181856$12144_Y
+ connect \$3 $and$libresoc.v:181857$12145_Y
+ connect \$5 $or$libresoc.v:181858$12146_Y
+ connect \$7 $not$libresoc.v:181859$12147_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184125.1-184183.10"
+attribute \src "libresoc.v:181878.1-181936.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l"
attribute \generator "nMigen"
module \rst_l$58
- attribute \src "libresoc.v:184126.7-184126.20"
+ attribute \src "libresoc.v:181879.7-181879.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184171.3-184179.6"
- wire $0\q_int$next[0:0]$12256
- attribute \src "libresoc.v:184169.3-184170.27"
+ attribute \src "libresoc.v:181924.3-181932.6"
+ wire $0\q_int$next[0:0]$12164
+ attribute \src "libresoc.v:181922.3-181923.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:184171.3-184179.6"
- wire $1\q_int$next[0:0]$12257
- attribute \src "libresoc.v:184148.7-184148.19"
+ attribute \src "libresoc.v:181924.3-181932.6"
+ wire $1\q_int$next[0:0]$12165
+ attribute \src "libresoc.v:181901.7-181901.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:184161.17-184161.96"
- wire $and$libresoc.v:184161$12246_Y
- attribute \src "libresoc.v:184166.17-184166.96"
- wire $and$libresoc.v:184166$12251_Y
- attribute \src "libresoc.v:184163.18-184163.93"
- wire $not$libresoc.v:184163$12248_Y
- attribute \src "libresoc.v:184165.17-184165.92"
- wire $not$libresoc.v:184165$12250_Y
- attribute \src "libresoc.v:184168.17-184168.92"
- wire $not$libresoc.v:184168$12253_Y
- attribute \src "libresoc.v:184162.18-184162.98"
- wire $or$libresoc.v:184162$12247_Y
- attribute \src "libresoc.v:184164.18-184164.99"
- wire $or$libresoc.v:184164$12249_Y
- attribute \src "libresoc.v:184167.17-184167.97"
- wire $or$libresoc.v:184167$12252_Y
+ attribute \src "libresoc.v:181914.17-181914.96"
+ wire $and$libresoc.v:181914$12154_Y
+ attribute \src "libresoc.v:181919.17-181919.96"
+ wire $and$libresoc.v:181919$12159_Y
+ attribute \src "libresoc.v:181916.18-181916.93"
+ wire $not$libresoc.v:181916$12156_Y
+ attribute \src "libresoc.v:181918.17-181918.92"
+ wire $not$libresoc.v:181918$12158_Y
+ attribute \src "libresoc.v:181921.17-181921.92"
+ wire $not$libresoc.v:181921$12161_Y
+ attribute \src "libresoc.v:181915.18-181915.98"
+ wire $or$libresoc.v:181915$12155_Y
+ attribute \src "libresoc.v:181917.18-181917.99"
+ wire $or$libresoc.v:181917$12157_Y
+ attribute \src "libresoc.v:181920.17-181920.97"
+ wire $or$libresoc.v:181920$12160_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184126.7-184126.15"
+ attribute \src "libresoc.v:181879.7-181879.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:184161$12246
+ cell $and $and$libresoc.v:181914$12154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:184161$12246_Y
+ connect \Y $and$libresoc.v:181914$12154_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:184166$12251
+ cell $and $and$libresoc.v:181919$12159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:184166$12251_Y
+ connect \Y $and$libresoc.v:181919$12159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:184163$12248
+ cell $not $not$libresoc.v:181916$12156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:184163$12248_Y
+ connect \Y $not$libresoc.v:181916$12156_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:184165$12250
+ cell $not $not$libresoc.v:181918$12158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184165$12250_Y
+ connect \Y $not$libresoc.v:181918$12158_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:184168$12253
+ cell $not $not$libresoc.v:181921$12161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184168$12253_Y
+ connect \Y $not$libresoc.v:181921$12161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:184162$12247
+ cell $or $or$libresoc.v:181915$12155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:184162$12247_Y
+ connect \Y $or$libresoc.v:181915$12155_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:184164$12249
+ cell $or $or$libresoc.v:181917$12157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:184164$12249_Y
+ connect \Y $or$libresoc.v:181917$12157_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:184167$12252
+ cell $or $or$libresoc.v:181920$12160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:184167$12252_Y
+ connect \Y $or$libresoc.v:181920$12160_Y
end
- attribute \src "libresoc.v:184126.7-184126.20"
- process $proc$libresoc.v:184126$12258
+ attribute \src "libresoc.v:181879.7-181879.20"
+ process $proc$libresoc.v:181879$12166
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184148.7-184148.19"
- process $proc$libresoc.v:184148$12259
+ attribute \src "libresoc.v:181901.7-181901.19"
+ process $proc$libresoc.v:181901$12167
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:184169.3-184170.27"
- process $proc$libresoc.v:184169$12254
+ attribute \src "libresoc.v:181922.3-181923.27"
+ process $proc$libresoc.v:181922$12162
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:184171.3-184179.6"
- process $proc$libresoc.v:184171$12255
+ attribute \src "libresoc.v:181924.3-181932.6"
+ process $proc$libresoc.v:181924$12163
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12256 $1\q_int$next[0:0]$12257
- attribute \src "libresoc.v:184172.5-184172.29"
+ assign $0\q_int$next[0:0]$12164 $1\q_int$next[0:0]$12165
+ attribute \src "libresoc.v:181925.5-181925.29"
switch \initial
- attribute \src "libresoc.v:184172.9-184172.17"
+ attribute \src "libresoc.v:181925.9-181925.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12257 1'0
+ assign $1\q_int$next[0:0]$12165 1'0
case
- assign $1\q_int$next[0:0]$12257 \$5
+ assign $1\q_int$next[0:0]$12165 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12256
+ update \q_int$next $0\q_int$next[0:0]$12164
end
- connect \$9 $and$libresoc.v:184161$12246_Y
- connect \$11 $or$libresoc.v:184162$12247_Y
- connect \$13 $not$libresoc.v:184163$12248_Y
- connect \$15 $or$libresoc.v:184164$12249_Y
- connect \$1 $not$libresoc.v:184165$12250_Y
- connect \$3 $and$libresoc.v:184166$12251_Y
- connect \$5 $or$libresoc.v:184167$12252_Y
- connect \$7 $not$libresoc.v:184168$12253_Y
+ connect \$9 $and$libresoc.v:181914$12154_Y
+ connect \$11 $or$libresoc.v:181915$12155_Y
+ connect \$13 $not$libresoc.v:181916$12156_Y
+ connect \$15 $or$libresoc.v:181917$12157_Y
+ connect \$1 $not$libresoc.v:181918$12158_Y
+ connect \$3 $and$libresoc.v:181919$12159_Y
+ connect \$5 $or$libresoc.v:181920$12160_Y
+ connect \$7 $not$libresoc.v:181921$12161_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184187.1-184245.10"
+attribute \src "libresoc.v:181940.1-181998.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l"
attribute \generator "nMigen"
module \rst_l$70
- attribute \src "libresoc.v:184188.7-184188.20"
+ attribute \src "libresoc.v:181941.7-181941.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184233.3-184241.6"
- wire $0\q_int$next[0:0]$12270
- attribute \src "libresoc.v:184231.3-184232.27"
+ attribute \src "libresoc.v:181986.3-181994.6"
+ wire $0\q_int$next[0:0]$12178
+ attribute \src "libresoc.v:181984.3-181985.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:184233.3-184241.6"
- wire $1\q_int$next[0:0]$12271
- attribute \src "libresoc.v:184210.7-184210.19"
+ attribute \src "libresoc.v:181986.3-181994.6"
+ wire $1\q_int$next[0:0]$12179
+ attribute \src "libresoc.v:181963.7-181963.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:184223.17-184223.96"
- wire $and$libresoc.v:184223$12260_Y
- attribute \src "libresoc.v:184228.17-184228.96"
- wire $and$libresoc.v:184228$12265_Y
- attribute \src "libresoc.v:184225.18-184225.93"
- wire $not$libresoc.v:184225$12262_Y
- attribute \src "libresoc.v:184227.17-184227.92"
- wire $not$libresoc.v:184227$12264_Y
- attribute \src "libresoc.v:184230.17-184230.92"
- wire $not$libresoc.v:184230$12267_Y
- attribute \src "libresoc.v:184224.18-184224.98"
- wire $or$libresoc.v:184224$12261_Y
- attribute \src "libresoc.v:184226.18-184226.99"
- wire $or$libresoc.v:184226$12263_Y
- attribute \src "libresoc.v:184229.17-184229.97"
- wire $or$libresoc.v:184229$12266_Y
+ attribute \src "libresoc.v:181976.17-181976.96"
+ wire $and$libresoc.v:181976$12168_Y
+ attribute \src "libresoc.v:181981.17-181981.96"
+ wire $and$libresoc.v:181981$12173_Y
+ attribute \src "libresoc.v:181978.18-181978.93"
+ wire $not$libresoc.v:181978$12170_Y
+ attribute \src "libresoc.v:181980.17-181980.92"
+ wire $not$libresoc.v:181980$12172_Y
+ attribute \src "libresoc.v:181983.17-181983.92"
+ wire $not$libresoc.v:181983$12175_Y
+ attribute \src "libresoc.v:181977.18-181977.98"
+ wire $or$libresoc.v:181977$12169_Y
+ attribute \src "libresoc.v:181979.18-181979.99"
+ wire $or$libresoc.v:181979$12171_Y
+ attribute \src "libresoc.v:181982.17-181982.97"
+ wire $or$libresoc.v:181982$12174_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184188.7-184188.15"
+ attribute \src "libresoc.v:181941.7-181941.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:184223$12260
+ cell $and $and$libresoc.v:181976$12168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:184223$12260_Y
+ connect \Y $and$libresoc.v:181976$12168_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:184228$12265
+ cell $and $and$libresoc.v:181981$12173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:184228$12265_Y
+ connect \Y $and$libresoc.v:181981$12173_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:184225$12262
+ cell $not $not$libresoc.v:181978$12170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:184225$12262_Y
+ connect \Y $not$libresoc.v:181978$12170_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:184227$12264
+ cell $not $not$libresoc.v:181980$12172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184227$12264_Y
+ connect \Y $not$libresoc.v:181980$12172_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:184230$12267
+ cell $not $not$libresoc.v:181983$12175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184230$12267_Y
+ connect \Y $not$libresoc.v:181983$12175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:184224$12261
+ cell $or $or$libresoc.v:181977$12169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:184224$12261_Y
+ connect \Y $or$libresoc.v:181977$12169_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:184226$12263
+ cell $or $or$libresoc.v:181979$12171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:184226$12263_Y
+ connect \Y $or$libresoc.v:181979$12171_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:184229$12266
+ cell $or $or$libresoc.v:181982$12174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:184229$12266_Y
+ connect \Y $or$libresoc.v:181982$12174_Y
end
- attribute \src "libresoc.v:184188.7-184188.20"
- process $proc$libresoc.v:184188$12272
+ attribute \src "libresoc.v:181941.7-181941.20"
+ process $proc$libresoc.v:181941$12180
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184210.7-184210.19"
- process $proc$libresoc.v:184210$12273
+ attribute \src "libresoc.v:181963.7-181963.19"
+ process $proc$libresoc.v:181963$12181
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:184231.3-184232.27"
- process $proc$libresoc.v:184231$12268
+ attribute \src "libresoc.v:181984.3-181985.27"
+ process $proc$libresoc.v:181984$12176
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:184233.3-184241.6"
- process $proc$libresoc.v:184233$12269
+ attribute \src "libresoc.v:181986.3-181994.6"
+ process $proc$libresoc.v:181986$12177
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12270 $1\q_int$next[0:0]$12271
- attribute \src "libresoc.v:184234.5-184234.29"
+ assign $0\q_int$next[0:0]$12178 $1\q_int$next[0:0]$12179
+ attribute \src "libresoc.v:181987.5-181987.29"
switch \initial
- attribute \src "libresoc.v:184234.9-184234.17"
+ attribute \src "libresoc.v:181987.9-181987.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12271 1'0
+ assign $1\q_int$next[0:0]$12179 1'0
case
- assign $1\q_int$next[0:0]$12271 \$5
+ assign $1\q_int$next[0:0]$12179 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12270
+ update \q_int$next $0\q_int$next[0:0]$12178
end
- connect \$9 $and$libresoc.v:184223$12260_Y
- connect \$11 $or$libresoc.v:184224$12261_Y
- connect \$13 $not$libresoc.v:184225$12262_Y
- connect \$15 $or$libresoc.v:184226$12263_Y
- connect \$1 $not$libresoc.v:184227$12264_Y
- connect \$3 $and$libresoc.v:184228$12265_Y
- connect \$5 $or$libresoc.v:184229$12266_Y
- connect \$7 $not$libresoc.v:184230$12267_Y
+ connect \$9 $and$libresoc.v:181976$12168_Y
+ connect \$11 $or$libresoc.v:181977$12169_Y
+ connect \$13 $not$libresoc.v:181978$12170_Y
+ connect \$15 $or$libresoc.v:181979$12171_Y
+ connect \$1 $not$libresoc.v:181980$12172_Y
+ connect \$3 $and$libresoc.v:181981$12173_Y
+ connect \$5 $or$libresoc.v:181982$12174_Y
+ connect \$7 $not$libresoc.v:181983$12175_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184249.1-184307.10"
+attribute \src "libresoc.v:182002.1-182060.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l"
attribute \generator "nMigen"
module \rst_l$87
- attribute \src "libresoc.v:184250.7-184250.20"
+ attribute \src "libresoc.v:182003.7-182003.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184295.3-184303.6"
- wire $0\q_int$next[0:0]$12284
- attribute \src "libresoc.v:184293.3-184294.27"
+ attribute \src "libresoc.v:182048.3-182056.6"
+ wire $0\q_int$next[0:0]$12192
+ attribute \src "libresoc.v:182046.3-182047.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:184295.3-184303.6"
- wire $1\q_int$next[0:0]$12285
- attribute \src "libresoc.v:184272.7-184272.19"
+ attribute \src "libresoc.v:182048.3-182056.6"
+ wire $1\q_int$next[0:0]$12193
+ attribute \src "libresoc.v:182025.7-182025.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:184285.17-184285.96"
- wire $and$libresoc.v:184285$12274_Y
- attribute \src "libresoc.v:184290.17-184290.96"
- wire $and$libresoc.v:184290$12279_Y
- attribute \src "libresoc.v:184287.18-184287.93"
- wire $not$libresoc.v:184287$12276_Y
- attribute \src "libresoc.v:184289.17-184289.92"
- wire $not$libresoc.v:184289$12278_Y
- attribute \src "libresoc.v:184292.17-184292.92"
- wire $not$libresoc.v:184292$12281_Y
- attribute \src "libresoc.v:184286.18-184286.98"
- wire $or$libresoc.v:184286$12275_Y
- attribute \src "libresoc.v:184288.18-184288.99"
- wire $or$libresoc.v:184288$12277_Y
- attribute \src "libresoc.v:184291.17-184291.97"
- wire $or$libresoc.v:184291$12280_Y
+ attribute \src "libresoc.v:182038.17-182038.96"
+ wire $and$libresoc.v:182038$12182_Y
+ attribute \src "libresoc.v:182043.17-182043.96"
+ wire $and$libresoc.v:182043$12187_Y
+ attribute \src "libresoc.v:182040.18-182040.93"
+ wire $not$libresoc.v:182040$12184_Y
+ attribute \src "libresoc.v:182042.17-182042.92"
+ wire $not$libresoc.v:182042$12186_Y
+ attribute \src "libresoc.v:182045.17-182045.92"
+ wire $not$libresoc.v:182045$12189_Y
+ attribute \src "libresoc.v:182039.18-182039.98"
+ wire $or$libresoc.v:182039$12183_Y
+ attribute \src "libresoc.v:182041.18-182041.99"
+ wire $or$libresoc.v:182041$12185_Y
+ attribute \src "libresoc.v:182044.17-182044.97"
+ wire $or$libresoc.v:182044$12188_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:184250.7-184250.15"
+ attribute \src "libresoc.v:182003.7-182003.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:184285$12274
+ cell $and $and$libresoc.v:182038$12182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:184285$12274_Y
+ connect \Y $and$libresoc.v:182038$12182_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:184290$12279
+ cell $and $and$libresoc.v:182043$12187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:184290$12279_Y
+ connect \Y $and$libresoc.v:182043$12187_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:184287$12276
+ cell $not $not$libresoc.v:182040$12184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_rst
- connect \Y $not$libresoc.v:184287$12276_Y
+ connect \Y $not$libresoc.v:182040$12184_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:184289$12278
+ cell $not $not$libresoc.v:182042$12186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184289$12278_Y
+ connect \Y $not$libresoc.v:182042$12186_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:184292$12281
+ cell $not $not$libresoc.v:182045$12189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_rst
- connect \Y $not$libresoc.v:184292$12281_Y
+ connect \Y $not$libresoc.v:182045$12189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:184286$12275
+ cell $or $or$libresoc.v:182039$12183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_rst
- connect \Y $or$libresoc.v:184286$12275_Y
+ connect \Y $or$libresoc.v:182039$12183_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:184288$12277
+ cell $or $or$libresoc.v:182041$12185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_rst
connect \B \q_int
- connect \Y $or$libresoc.v:184288$12277_Y
+ connect \Y $or$libresoc.v:182041$12185_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:184291$12280
+ cell $or $or$libresoc.v:182044$12188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_rst
- connect \Y $or$libresoc.v:184291$12280_Y
+ connect \Y $or$libresoc.v:182044$12188_Y
end
- attribute \src "libresoc.v:184250.7-184250.20"
- process $proc$libresoc.v:184250$12286
+ attribute \src "libresoc.v:182003.7-182003.20"
+ process $proc$libresoc.v:182003$12194
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184272.7-184272.19"
- process $proc$libresoc.v:184272$12287
+ attribute \src "libresoc.v:182025.7-182025.19"
+ process $proc$libresoc.v:182025$12195
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:184293.3-184294.27"
- process $proc$libresoc.v:184293$12282
+ attribute \src "libresoc.v:182046.3-182047.27"
+ process $proc$libresoc.v:182046$12190
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:184295.3-184303.6"
- process $proc$libresoc.v:184295$12283
+ attribute \src "libresoc.v:182048.3-182056.6"
+ process $proc$libresoc.v:182048$12191
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$12284 $1\q_int$next[0:0]$12285
- attribute \src "libresoc.v:184296.5-184296.29"
+ assign $0\q_int$next[0:0]$12192 $1\q_int$next[0:0]$12193
+ attribute \src "libresoc.v:182049.5-182049.29"
switch \initial
- attribute \src "libresoc.v:184296.9-184296.17"
+ attribute \src "libresoc.v:182049.9-182049.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$12285 1'0
+ assign $1\q_int$next[0:0]$12193 1'0
case
- assign $1\q_int$next[0:0]$12285 \$5
+ assign $1\q_int$next[0:0]$12193 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$12284
+ update \q_int$next $0\q_int$next[0:0]$12192
end
- connect \$9 $and$libresoc.v:184285$12274_Y
- connect \$11 $or$libresoc.v:184286$12275_Y
- connect \$13 $not$libresoc.v:184287$12276_Y
- connect \$15 $or$libresoc.v:184288$12277_Y
- connect \$1 $not$libresoc.v:184289$12278_Y
- connect \$3 $and$libresoc.v:184290$12279_Y
- connect \$5 $or$libresoc.v:184291$12280_Y
- connect \$7 $not$libresoc.v:184292$12281_Y
+ connect \$9 $and$libresoc.v:182038$12182_Y
+ connect \$11 $or$libresoc.v:182039$12183_Y
+ connect \$13 $not$libresoc.v:182040$12184_Y
+ connect \$15 $or$libresoc.v:182041$12185_Y
+ connect \$1 $not$libresoc.v:182042$12186_Y
+ connect \$3 $and$libresoc.v:182043$12187_Y
+ connect \$5 $or$libresoc.v:182044$12188_Y
+ connect \$7 $not$libresoc.v:182045$12189_Y
connect \qlq_rst \$15
connect \qn_rst \$13
connect \q_rst \$11
end
-attribute \src "libresoc.v:184311.1-184716.10"
+attribute \src "libresoc.v:182064.1-182469.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage"
attribute \generator "nMigen"
module \setup_stage
- attribute \src "libresoc.v:184674.3-184699.6"
+ attribute \src "libresoc.v:182427.3-182452.6"
wire width 128 $0\dividend[127:0]
- attribute \src "libresoc.v:184312.7-184312.20"
+ attribute \src "libresoc.v:182065.7-182065.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:184674.3-184699.6"
+ attribute \src "libresoc.v:182427.3-182452.6"
wire width 128 $1\dividend[127:0]
- attribute \src "libresoc.v:184674.3-184699.6"
+ attribute \src "libresoc.v:182427.3-182452.6"
wire width 128 $2\dividend[127:0]
- attribute \src "libresoc.v:184653.18-184653.122"
- wire $and$libresoc.v:184653$12289_Y
- attribute \src "libresoc.v:184655.18-184655.122"
- wire $and$libresoc.v:184655$12291_Y
- attribute \src "libresoc.v:184664.18-184664.105"
- wire $and$libresoc.v:184664$12304_Y
- attribute \src "libresoc.v:184667.18-184667.105"
- wire $and$libresoc.v:184667$12307_Y
- attribute \src "libresoc.v:184663.18-184663.123"
- wire $eq$libresoc.v:184663$12303_Y
- attribute \src "libresoc.v:184666.18-184666.123"
- wire $eq$libresoc.v:184666$12306_Y
- attribute \src "libresoc.v:184669.18-184669.117"
- wire $eq$libresoc.v:184669$12309_Y
- attribute \src "libresoc.v:184656.18-184656.97"
- wire width 65 $extend$libresoc.v:184656$12292_Y
- attribute \src "libresoc.v:184657.18-184657.91"
- wire width 65 $extend$libresoc.v:184657$12294_Y
- attribute \src "libresoc.v:184659.18-184659.97"
- wire width 65 $extend$libresoc.v:184659$12297_Y
- attribute \src "libresoc.v:184660.18-184660.91"
- wire width 65 $extend$libresoc.v:184660$12299_Y
- attribute \src "libresoc.v:184672.18-184672.99"
- wire width 128 $extend$libresoc.v:184672$12312_Y
- attribute \src "libresoc.v:184662.18-184662.112"
- wire $ge$libresoc.v:184662$12302_Y
- attribute \src "libresoc.v:184665.18-184665.124"
- wire $ge$libresoc.v:184665$12305_Y
- attribute \src "libresoc.v:184656.18-184656.97"
- wire width 65 $neg$libresoc.v:184656$12293_Y
- attribute \src "libresoc.v:184659.18-184659.97"
- wire width 65 $neg$libresoc.v:184659$12298_Y
- attribute \src "libresoc.v:184657.18-184657.91"
- wire width 65 $pos$libresoc.v:184657$12295_Y
- attribute \src "libresoc.v:184660.18-184660.91"
- wire width 65 $pos$libresoc.v:184660$12300_Y
- attribute \src "libresoc.v:184672.18-184672.99"
- wire width 128 $pos$libresoc.v:184672$12313_Y
- attribute \src "libresoc.v:184671.18-184671.117"
- wire width 95 $sshl$libresoc.v:184671$12311_Y
- attribute \src "libresoc.v:184673.18-184673.111"
- wire width 191 $sshl$libresoc.v:184673$12314_Y
- attribute \src "libresoc.v:184652.18-184652.131"
- wire $ternary$libresoc.v:184652$12288_Y
- attribute \src "libresoc.v:184654.18-184654.131"
- wire $ternary$libresoc.v:184654$12290_Y
- attribute \src "libresoc.v:184658.18-184658.119"
- wire width 65 $ternary$libresoc.v:184658$12296_Y
- attribute \src "libresoc.v:184661.18-184661.120"
- wire width 65 $ternary$libresoc.v:184661$12301_Y
- attribute \src "libresoc.v:184668.18-184668.130"
- wire width 32 $ternary$libresoc.v:184668$12308_Y
- attribute \src "libresoc.v:184670.18-184670.131"
- wire width 32 $ternary$libresoc.v:184670$12310_Y
+ attribute \src "libresoc.v:182406.18-182406.122"
+ wire $and$libresoc.v:182406$12197_Y
+ attribute \src "libresoc.v:182408.18-182408.122"
+ wire $and$libresoc.v:182408$12199_Y
+ attribute \src "libresoc.v:182417.18-182417.105"
+ wire $and$libresoc.v:182417$12212_Y
+ attribute \src "libresoc.v:182420.18-182420.105"
+ wire $and$libresoc.v:182420$12215_Y
+ attribute \src "libresoc.v:182416.18-182416.123"
+ wire $eq$libresoc.v:182416$12211_Y
+ attribute \src "libresoc.v:182419.18-182419.123"
+ wire $eq$libresoc.v:182419$12214_Y
+ attribute \src "libresoc.v:182422.18-182422.117"
+ wire $eq$libresoc.v:182422$12217_Y
+ attribute \src "libresoc.v:182409.18-182409.97"
+ wire width 65 $extend$libresoc.v:182409$12200_Y
+ attribute \src "libresoc.v:182410.18-182410.91"
+ wire width 65 $extend$libresoc.v:182410$12202_Y
+ attribute \src "libresoc.v:182412.18-182412.97"
+ wire width 65 $extend$libresoc.v:182412$12205_Y
+ attribute \src "libresoc.v:182413.18-182413.91"
+ wire width 65 $extend$libresoc.v:182413$12207_Y
+ attribute \src "libresoc.v:182425.18-182425.99"
+ wire width 128 $extend$libresoc.v:182425$12220_Y
+ attribute \src "libresoc.v:182415.18-182415.112"
+ wire $ge$libresoc.v:182415$12210_Y
+ attribute \src "libresoc.v:182418.18-182418.124"
+ wire $ge$libresoc.v:182418$12213_Y
+ attribute \src "libresoc.v:182409.18-182409.97"
+ wire width 65 $neg$libresoc.v:182409$12201_Y
+ attribute \src "libresoc.v:182412.18-182412.97"
+ wire width 65 $neg$libresoc.v:182412$12206_Y
+ attribute \src "libresoc.v:182410.18-182410.91"
+ wire width 65 $pos$libresoc.v:182410$12203_Y
+ attribute \src "libresoc.v:182413.18-182413.91"
+ wire width 65 $pos$libresoc.v:182413$12208_Y
+ attribute \src "libresoc.v:182425.18-182425.99"
+ wire width 128 $pos$libresoc.v:182425$12221_Y
+ attribute \src "libresoc.v:182424.18-182424.117"
+ wire width 95 $sshl$libresoc.v:182424$12219_Y
+ attribute \src "libresoc.v:182426.18-182426.111"
+ wire width 191 $sshl$libresoc.v:182426$12222_Y
+ attribute \src "libresoc.v:182405.18-182405.131"
+ wire $ternary$libresoc.v:182405$12196_Y
+ attribute \src "libresoc.v:182407.18-182407.131"
+ wire $ternary$libresoc.v:182407$12198_Y
+ attribute \src "libresoc.v:182411.18-182411.119"
+ wire width 65 $ternary$libresoc.v:182411$12204_Y
+ attribute \src "libresoc.v:182414.18-182414.120"
+ wire width 65 $ternary$libresoc.v:182414$12209_Y
+ attribute \src "libresoc.v:182421.18-182421.130"
+ wire width 32 $ternary$libresoc.v:182421$12216_Y
+ attribute \src "libresoc.v:182423.18-182423.131"
+ wire width 32 $ternary$libresoc.v:182423$12218_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
wire \$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
wire output 42 \divisor_neg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
wire width 64 output 48 \divisor_radicand
- attribute \src "libresoc.v:184312.7-184312.15"
+ attribute \src "libresoc.v:182065.7-182065.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 17 \logical_op__data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire output 41 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
- cell $and $and$libresoc.v:184653$12289
+ cell $and $and$libresoc.v:182406$12197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$21
connect \B \logical_op__is_signed
- connect \Y $and$libresoc.v:184653$12289_Y
+ connect \Y $and$libresoc.v:182406$12197_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
- cell $and $and$libresoc.v:184655$12291
+ cell $and $and$libresoc.v:182408$12199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$25
connect \B \logical_op__is_signed
- connect \Y $and$libresoc.v:184655$12291_Y
+ connect \Y $and$libresoc.v:182408$12199_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
- cell $and $and$libresoc.v:184664$12304
+ cell $and $and$libresoc.v:182417$12212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B \$45
- connect \Y $and$libresoc.v:184664$12304_Y
+ connect \Y $and$libresoc.v:182417$12212_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
- cell $and $and$libresoc.v:184667$12307
+ cell $and $and$libresoc.v:182420$12215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \$51
- connect \Y $and$libresoc.v:184667$12307_Y
+ connect \Y $and$libresoc.v:182420$12215_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
- cell $eq $eq$libresoc.v:184663$12303
+ cell $eq $eq$libresoc.v:182416$12211
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0011110
- connect \Y $eq$libresoc.v:184663$12303_Y
+ connect \Y $eq$libresoc.v:182416$12211_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
- cell $eq $eq$libresoc.v:184666$12306
+ cell $eq $eq$libresoc.v:182419$12214
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \logical_op__insn_type
connect \B 7'0011110
- connect \Y $eq$libresoc.v:184666$12306_Y
+ connect \Y $eq$libresoc.v:182419$12214_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67"
- cell $eq $eq$libresoc.v:184669$12309
+ cell $eq $eq$libresoc.v:182422$12217
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \divisor_radicand
connect \B 1'0
- connect \Y $eq$libresoc.v:184669$12309_Y
+ connect \Y $eq$libresoc.v:182422$12217_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $pos $extend$libresoc.v:184656$12292
+ cell $pos $extend$libresoc.v:182409$12200
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:184656$12292_Y
+ connect \Y $extend$libresoc.v:182409$12200_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:184657$12294
+ cell $pos $extend$libresoc.v:182410$12202
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \rb
- connect \Y $extend$libresoc.v:184657$12294_Y
+ connect \Y $extend$libresoc.v:182410$12202_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $pos $extend$libresoc.v:184659$12297
+ cell $pos $extend$libresoc.v:182412$12205
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:184659$12297_Y
+ connect \Y $extend$libresoc.v:182412$12205_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $extend$libresoc.v:184660$12299
+ cell $pos $extend$libresoc.v:182413$12207
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \ra
- connect \Y $extend$libresoc.v:184660$12299_Y
+ connect \Y $extend$libresoc.v:182413$12207_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $pos $extend$libresoc.v:184672$12312
+ cell $pos $extend$libresoc.v:182425$12220
parameter \A_SIGNED 0
parameter \A_WIDTH 95
parameter \Y_WIDTH 128
connect \A \$62
- connect \Y $extend$libresoc.v:184672$12312_Y
+ connect \Y $extend$libresoc.v:182425$12220_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57"
- cell $ge $ge$libresoc.v:184662$12302
+ cell $ge $ge$libresoc.v:182415$12210
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \abs_dend
connect \B \abs_dor
- connect \Y $ge$libresoc.v:184662$12302_Y
+ connect \Y $ge$libresoc.v:182415$12210_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60"
- cell $ge $ge$libresoc.v:184665$12305
+ cell $ge $ge$libresoc.v:182418$12213
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \abs_dend [31:0]
connect \B \abs_dor [31:0]
- connect \Y $ge$libresoc.v:184665$12305_Y
+ connect \Y $ge$libresoc.v:182418$12213_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $neg $neg$libresoc.v:184656$12293
+ cell $neg $neg$libresoc.v:182409$12201
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:184656$12292_Y
- connect \Y $neg$libresoc.v:184656$12293_Y
+ connect \A $extend$libresoc.v:182409$12200_Y
+ connect \Y $neg$libresoc.v:182409$12201_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $neg $neg$libresoc.v:184659$12298
+ cell $neg $neg$libresoc.v:182412$12206
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:184659$12297_Y
- connect \Y $neg$libresoc.v:184659$12298_Y
+ connect \A $extend$libresoc.v:182412$12205_Y
+ connect \Y $neg$libresoc.v:182412$12206_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:184657$12295
+ cell $pos $pos$libresoc.v:182410$12203
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:184657$12294_Y
- connect \Y $pos$libresoc.v:184657$12295_Y
+ connect \A $extend$libresoc.v:182410$12202_Y
+ connect \Y $pos$libresoc.v:182410$12203_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
- cell $pos $pos$libresoc.v:184660$12300
+ cell $pos $pos$libresoc.v:182413$12208
parameter \A_SIGNED 0
parameter \A_WIDTH 65
parameter \Y_WIDTH 65
- connect \A $extend$libresoc.v:184660$12299_Y
- connect \Y $pos$libresoc.v:184660$12300_Y
+ connect \A $extend$libresoc.v:182413$12207_Y
+ connect \Y $pos$libresoc.v:182413$12208_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $pos $pos$libresoc.v:184672$12313
+ cell $pos $pos$libresoc.v:182425$12221
parameter \A_SIGNED 0
parameter \A_WIDTH 128
parameter \Y_WIDTH 128
- connect \A $extend$libresoc.v:184672$12312_Y
- connect \Y $pos$libresoc.v:184672$12313_Y
+ connect \A $extend$libresoc.v:182425$12220_Y
+ connect \Y $pos$libresoc.v:182425$12221_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
- cell $sshl $sshl$libresoc.v:184671$12311
+ cell $sshl $sshl$libresoc.v:182424$12219
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 95
connect \A \abs_dend [31:0]
connect \B 6'100000
- connect \Y $sshl$libresoc.v:184671$12311_Y
+ connect \Y $sshl$libresoc.v:182424$12219_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81"
- cell $sshl $sshl$libresoc.v:184673$12314
+ cell $sshl $sshl$libresoc.v:182426$12222
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 191
connect \A \abs_dend
connect \B 7'1000000
- connect \Y $sshl$libresoc.v:184673$12314_Y
+ connect \Y $sshl$libresoc.v:182426$12222_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
- cell $mux $ternary$libresoc.v:184652$12288
+ cell $mux $ternary$libresoc.v:182405$12196
parameter \WIDTH 1
connect \A \ra [63]
connect \B \ra [31]
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:184652$12288_Y
+ connect \Y $ternary$libresoc.v:182405$12196_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
- cell $mux $ternary$libresoc.v:184654$12290
+ cell $mux $ternary$libresoc.v:182407$12198
parameter \WIDTH 1
connect \A \rb [63]
connect \B \rb [31]
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:184654$12290_Y
+ connect \Y $ternary$libresoc.v:182407$12198_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
- cell $mux $ternary$libresoc.v:184658$12296
+ cell $mux $ternary$libresoc.v:182411$12204
parameter \WIDTH 65
connect \A \$32
connect \B \$30
connect \S \divisor_neg
- connect \Y $ternary$libresoc.v:184658$12296_Y
+ connect \Y $ternary$libresoc.v:182411$12204_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
- cell $mux $ternary$libresoc.v:184661$12301
+ cell $mux $ternary$libresoc.v:182414$12209
parameter \WIDTH 65
connect \A \$39
connect \B \$37
connect \S \dividend_neg
- connect \Y $ternary$libresoc.v:184661$12301_Y
+ connect \Y $ternary$libresoc.v:182414$12209_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:184668$12308
+ cell $mux $ternary$libresoc.v:182421$12216
parameter \WIDTH 32
connect \A \abs_dor [63:32]
connect \B 0
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:184668$12308_Y
+ connect \Y $ternary$libresoc.v:182421$12216_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41"
- cell $mux $ternary$libresoc.v:184670$12310
+ cell $mux $ternary$libresoc.v:182423$12218
parameter \WIDTH 32
connect \A \abs_dend [63:32]
connect \B 0
connect \S \logical_op__is_32bit
- connect \Y $ternary$libresoc.v:184670$12310_Y
+ connect \Y $ternary$libresoc.v:182423$12218_Y
end
- attribute \src "libresoc.v:184312.7-184312.20"
- process $proc$libresoc.v:184312$12316
+ attribute \src "libresoc.v:182065.7-182065.20"
+ process $proc$libresoc.v:182065$12224
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184674.3-184699.6"
- process $proc$libresoc.v:184674$12315
+ attribute \src "libresoc.v:182427.3-182452.6"
+ process $proc$libresoc.v:182427$12223
assign { } { }
assign { } { }
assign $0\dividend[127:0] $1\dividend[127:0]
- attribute \src "libresoc.v:184675.5-184675.29"
+ attribute \src "libresoc.v:182428.5-182428.29"
switch \initial
- attribute \src "libresoc.v:184675.9-184675.17"
+ attribute \src "libresoc.v:182428.9-182428.17"
case 1'1
case
end
sync always
update \dividend $0\dividend[127:0]
end
- connect \$21 $ternary$libresoc.v:184652$12288_Y
- connect \$23 $and$libresoc.v:184653$12289_Y
- connect \$25 $ternary$libresoc.v:184654$12290_Y
- connect \$27 $and$libresoc.v:184655$12291_Y
- connect \$30 $neg$libresoc.v:184656$12293_Y
- connect \$32 $pos$libresoc.v:184657$12295_Y
- connect \$34 $ternary$libresoc.v:184658$12296_Y
- connect \$37 $neg$libresoc.v:184659$12298_Y
- connect \$39 $pos$libresoc.v:184660$12300_Y
- connect \$41 $ternary$libresoc.v:184661$12301_Y
- connect \$43 $ge$libresoc.v:184662$12302_Y
- connect \$45 $eq$libresoc.v:184663$12303_Y
- connect \$47 $and$libresoc.v:184664$12304_Y
- connect \$49 $ge$libresoc.v:184665$12305_Y
- connect \$51 $eq$libresoc.v:184666$12306_Y
- connect \$53 $and$libresoc.v:184667$12307_Y
- connect \$55 $ternary$libresoc.v:184668$12308_Y
- connect \$57 $eq$libresoc.v:184669$12309_Y
- connect \$59 $ternary$libresoc.v:184670$12310_Y
- connect \$62 $sshl$libresoc.v:184671$12311_Y
- connect \$61 $pos$libresoc.v:184672$12313_Y
- connect \$66 $sshl$libresoc.v:184673$12314_Y
+ connect \$21 $ternary$libresoc.v:182405$12196_Y
+ connect \$23 $and$libresoc.v:182406$12197_Y
+ connect \$25 $ternary$libresoc.v:182407$12198_Y
+ connect \$27 $and$libresoc.v:182408$12199_Y
+ connect \$30 $neg$libresoc.v:182409$12201_Y
+ connect \$32 $pos$libresoc.v:182410$12203_Y
+ connect \$34 $ternary$libresoc.v:182411$12204_Y
+ connect \$37 $neg$libresoc.v:182412$12206_Y
+ connect \$39 $pos$libresoc.v:182413$12208_Y
+ connect \$41 $ternary$libresoc.v:182414$12209_Y
+ connect \$43 $ge$libresoc.v:182415$12210_Y
+ connect \$45 $eq$libresoc.v:182416$12211_Y
+ connect \$47 $and$libresoc.v:182417$12212_Y
+ connect \$49 $ge$libresoc.v:182418$12213_Y
+ connect \$51 $eq$libresoc.v:182419$12214_Y
+ connect \$53 $and$libresoc.v:182420$12215_Y
+ connect \$55 $ternary$libresoc.v:182421$12216_Y
+ connect \$57 $eq$libresoc.v:182422$12217_Y
+ connect \$59 $ternary$libresoc.v:182423$12218_Y
+ connect \$62 $sshl$libresoc.v:182424$12219_Y
+ connect \$61 $pos$libresoc.v:182425$12221_Y
+ connect \$66 $sshl$libresoc.v:182426$12222_Y
connect \$29 \$34
connect \$36 \$41
connect \$65 \$66
connect \dividend_neg \$23
connect \operation 2'01
end
-attribute \src "libresoc.v:184720.1-185923.10"
+attribute \src "libresoc.v:182473.1-183676.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0"
attribute \generator "nMigen"
module \shiftrot0
- attribute \src "libresoc.v:185494.3-185495.25"
+ attribute \src "libresoc.v:183247.3-183248.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:185492.3-185493.46"
+ attribute \src "libresoc.v:183245.3-183246.46"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:185843.3-185851.6"
- wire $0\alu_l_r_alu$next[0:0]$12534
- attribute \src "libresoc.v:185410.3-185411.39"
+ attribute \src "libresoc.v:183596.3-183604.6"
+ wire $0\alu_l_r_alu$next[0:0]$12442
+ attribute \src "libresoc.v:183163.3-183164.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451
- attribute \src "libresoc.v:185438.3-185439.75"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359
+ attribute \src "libresoc.v:183191.3-183192.75"
wire width 13 $0\alu_shift_rot0_sr_op__fn_unit[12:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452
- attribute \src "libresoc.v:185440.3-185441.89"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360
+ attribute \src "libresoc.v:183193.3-183194.89"
wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453
- attribute \src "libresoc.v:185442.3-185443.85"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361
+ attribute \src "libresoc.v:183195.3-183196.85"
wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454
- attribute \src "libresoc.v:185456.3-185457.83"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362
+ attribute \src "libresoc.v:183209.3-183210.83"
wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455
- attribute \src "libresoc.v:185460.3-185461.77"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363
+ attribute \src "libresoc.v:183213.3-183214.77"
wire $0\alu_shift_rot0_sr_op__input_cr[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456
- attribute \src "libresoc.v:185468.3-185469.69"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364
+ attribute \src "libresoc.v:183221.3-183222.69"
wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457
- attribute \src "libresoc.v:185436.3-185437.79"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365
+ attribute \src "libresoc.v:183189.3-183190.79"
wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458
- attribute \src "libresoc.v:185454.3-185455.79"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366
+ attribute \src "libresoc.v:183207.3-183208.79"
wire $0\alu_shift_rot0_sr_op__invert_in[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459
- attribute \src "libresoc.v:185464.3-185465.77"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367
+ attribute \src "libresoc.v:183217.3-183218.77"
wire $0\alu_shift_rot0_sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460
- attribute \src "libresoc.v:185466.3-185467.79"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368
+ attribute \src "libresoc.v:183219.3-183220.79"
wire $0\alu_shift_rot0_sr_op__is_signed[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461
- attribute \src "libresoc.v:185448.3-185449.73"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369
+ attribute \src "libresoc.v:183201.3-183202.73"
wire $0\alu_shift_rot0_sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462
- attribute \src "libresoc.v:185450.3-185451.73"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370
+ attribute \src "libresoc.v:183203.3-183204.73"
wire $0\alu_shift_rot0_sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463
- attribute \src "libresoc.v:185458.3-185459.85"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371
+ attribute \src "libresoc.v:183211.3-183212.85"
wire $0\alu_shift_rot0_sr_op__output_carry[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464
- attribute \src "libresoc.v:185462.3-185463.79"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372
+ attribute \src "libresoc.v:183215.3-183216.79"
wire $0\alu_shift_rot0_sr_op__output_cr[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465
- attribute \src "libresoc.v:185446.3-185447.73"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373
+ attribute \src "libresoc.v:183199.3-183200.73"
wire $0\alu_shift_rot0_sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466
- attribute \src "libresoc.v:185444.3-185445.73"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374
+ attribute \src "libresoc.v:183197.3-183198.73"
wire $0\alu_shift_rot0_sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467
- attribute \src "libresoc.v:185452.3-185453.79"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375
+ attribute \src "libresoc.v:183205.3-183206.79"
wire $0\alu_shift_rot0_sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:185834.3-185842.6"
- wire $0\alui_l_r_alui$next[0:0]$12531
- attribute \src "libresoc.v:185412.3-185413.43"
+ attribute \src "libresoc.v:183587.3-183595.6"
+ wire $0\alui_l_r_alui$next[0:0]$12439
+ attribute \src "libresoc.v:183165.3-183166.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:185718.3-185739.6"
- wire width 64 $0\data_r0__o$next[63:0]$12492
- attribute \src "libresoc.v:185432.3-185433.37"
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire width 64 $0\data_r0__o$next[63:0]$12400
+ attribute \src "libresoc.v:183185.3-183186.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:185718.3-185739.6"
- wire $0\data_r0__o_ok$next[0:0]$12493
- attribute \src "libresoc.v:185434.3-185435.43"
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire $0\data_r0__o_ok$next[0:0]$12401
+ attribute \src "libresoc.v:183187.3-183188.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:185740.3-185761.6"
- wire width 4 $0\data_r1__cr_a$next[3:0]$12500
- attribute \src "libresoc.v:185428.3-185429.43"
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire width 4 $0\data_r1__cr_a$next[3:0]$12408
+ attribute \src "libresoc.v:183181.3-183182.43"
wire width 4 $0\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:185740.3-185761.6"
- wire $0\data_r1__cr_a_ok$next[0:0]$12501
- attribute \src "libresoc.v:185430.3-185431.49"
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire $0\data_r1__cr_a_ok$next[0:0]$12409
+ attribute \src "libresoc.v:183183.3-183184.49"
wire $0\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:185762.3-185783.6"
- wire width 2 $0\data_r2__xer_ca$next[1:0]$12508
- attribute \src "libresoc.v:185424.3-185425.47"
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire width 2 $0\data_r2__xer_ca$next[1:0]$12416
+ attribute \src "libresoc.v:183177.3-183178.47"
wire width 2 $0\data_r2__xer_ca[1:0]
- attribute \src "libresoc.v:185762.3-185783.6"
- wire $0\data_r2__xer_ca_ok$next[0:0]$12509
- attribute \src "libresoc.v:185426.3-185427.53"
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire $0\data_r2__xer_ca_ok$next[0:0]$12417
+ attribute \src "libresoc.v:183179.3-183180.53"
wire $0\data_r2__xer_ca_ok[0:0]
- attribute \src "libresoc.v:185852.3-185861.6"
+ attribute \src "libresoc.v:183605.3-183614.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:185862.3-185871.6"
+ attribute \src "libresoc.v:183615.3-183624.6"
wire width 4 $0\dest2_o[3:0]
- attribute \src "libresoc.v:185872.3-185881.6"
+ attribute \src "libresoc.v:183625.3-183634.6"
wire width 2 $0\dest3_o[1:0]
- attribute \src "libresoc.v:184721.7-184721.20"
+ attribute \src "libresoc.v:182474.7-182474.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:185635.3-185643.6"
- wire $0\opc_l_r_opc$next[0:0]$12436
- attribute \src "libresoc.v:185478.3-185479.39"
+ attribute \src "libresoc.v:183388.3-183396.6"
+ wire $0\opc_l_r_opc$next[0:0]$12344
+ attribute \src "libresoc.v:183231.3-183232.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:185626.3-185634.6"
- wire $0\opc_l_s_opc$next[0:0]$12433
- attribute \src "libresoc.v:185480.3-185481.39"
+ attribute \src "libresoc.v:183379.3-183387.6"
+ wire $0\opc_l_s_opc$next[0:0]$12341
+ attribute \src "libresoc.v:183233.3-183234.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:185882.3-185890.6"
- wire width 3 $0\prev_wr_go$next[2:0]$12540
- attribute \src "libresoc.v:185490.3-185491.37"
+ attribute \src "libresoc.v:183635.3-183643.6"
+ wire width 3 $0\prev_wr_go$next[2:0]$12448
+ attribute \src "libresoc.v:183243.3-183244.37"
wire width 3 $0\prev_wr_go[2:0]
- attribute \src "libresoc.v:185580.3-185589.6"
+ attribute \src "libresoc.v:183333.3-183342.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:185671.3-185679.6"
- wire width 3 $0\req_l_r_req$next[2:0]$12448
- attribute \src "libresoc.v:185470.3-185471.39"
+ attribute \src "libresoc.v:183424.3-183432.6"
+ wire width 3 $0\req_l_r_req$next[2:0]$12356
+ attribute \src "libresoc.v:183223.3-183224.39"
wire width 3 $0\req_l_r_req[2:0]
- attribute \src "libresoc.v:185662.3-185670.6"
- wire width 3 $0\req_l_s_req$next[2:0]$12445
- attribute \src "libresoc.v:185472.3-185473.39"
+ attribute \src "libresoc.v:183415.3-183423.6"
+ wire width 3 $0\req_l_s_req$next[2:0]$12353
+ attribute \src "libresoc.v:183225.3-183226.39"
wire width 3 $0\req_l_s_req[2:0]
- attribute \src "libresoc.v:185599.3-185607.6"
- wire $0\rok_l_r_rdok$next[0:0]$12424
- attribute \src "libresoc.v:185486.3-185487.41"
+ attribute \src "libresoc.v:183352.3-183360.6"
+ wire $0\rok_l_r_rdok$next[0:0]$12332
+ attribute \src "libresoc.v:183239.3-183240.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:185590.3-185598.6"
- wire $0\rok_l_s_rdok$next[0:0]$12421
- attribute \src "libresoc.v:185488.3-185489.41"
+ attribute \src "libresoc.v:183343.3-183351.6"
+ wire $0\rok_l_s_rdok$next[0:0]$12329
+ attribute \src "libresoc.v:183241.3-183242.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:185617.3-185625.6"
- wire $0\rst_l_r_rst$next[0:0]$12430
- attribute \src "libresoc.v:185482.3-185483.39"
+ attribute \src "libresoc.v:183370.3-183378.6"
+ wire $0\rst_l_r_rst$next[0:0]$12338
+ attribute \src "libresoc.v:183235.3-183236.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:185608.3-185616.6"
- wire $0\rst_l_s_rst$next[0:0]$12427
- attribute \src "libresoc.v:185484.3-185485.39"
+ attribute \src "libresoc.v:183361.3-183369.6"
+ wire $0\rst_l_s_rst$next[0:0]$12335
+ attribute \src "libresoc.v:183237.3-183238.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:185653.3-185661.6"
- wire width 5 $0\src_l_r_src$next[4:0]$12442
- attribute \src "libresoc.v:185474.3-185475.39"
+ attribute \src "libresoc.v:183406.3-183414.6"
+ wire width 5 $0\src_l_r_src$next[4:0]$12350
+ attribute \src "libresoc.v:183227.3-183228.39"
wire width 5 $0\src_l_r_src[4:0]
- attribute \src "libresoc.v:185644.3-185652.6"
- wire width 5 $0\src_l_s_src$next[4:0]$12439
- attribute \src "libresoc.v:185476.3-185477.39"
+ attribute \src "libresoc.v:183397.3-183405.6"
+ wire width 5 $0\src_l_s_src$next[4:0]$12347
+ attribute \src "libresoc.v:183229.3-183230.39"
wire width 5 $0\src_l_s_src[4:0]
- attribute \src "libresoc.v:185784.3-185793.6"
- wire width 64 $0\src_r0$next[63:0]$12516
- attribute \src "libresoc.v:185422.3-185423.29"
+ attribute \src "libresoc.v:183537.3-183546.6"
+ wire width 64 $0\src_r0$next[63:0]$12424
+ attribute \src "libresoc.v:183175.3-183176.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:185794.3-185803.6"
- wire width 64 $0\src_r1$next[63:0]$12519
- attribute \src "libresoc.v:185420.3-185421.29"
+ attribute \src "libresoc.v:183547.3-183556.6"
+ wire width 64 $0\src_r1$next[63:0]$12427
+ attribute \src "libresoc.v:183173.3-183174.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:185804.3-185813.6"
- wire width 64 $0\src_r2$next[63:0]$12522
- attribute \src "libresoc.v:185418.3-185419.29"
+ attribute \src "libresoc.v:183557.3-183566.6"
+ wire width 64 $0\src_r2$next[63:0]$12430
+ attribute \src "libresoc.v:183171.3-183172.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:185814.3-185823.6"
- wire $0\src_r3$next[0:0]$12525
- attribute \src "libresoc.v:185416.3-185417.29"
+ attribute \src "libresoc.v:183567.3-183576.6"
+ wire $0\src_r3$next[0:0]$12433
+ attribute \src "libresoc.v:183169.3-183170.29"
wire $0\src_r3[0:0]
- attribute \src "libresoc.v:185824.3-185833.6"
- wire width 2 $0\src_r4$next[1:0]$12528
- attribute \src "libresoc.v:185414.3-185415.29"
+ attribute \src "libresoc.v:183577.3-183586.6"
+ wire width 2 $0\src_r4$next[1:0]$12436
+ attribute \src "libresoc.v:183167.3-183168.29"
wire width 2 $0\src_r4[1:0]
- attribute \src "libresoc.v:184843.7-184843.24"
+ attribute \src "libresoc.v:182596.7-182596.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:184853.7-184853.26"
+ attribute \src "libresoc.v:182606.7-182606.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:185843.3-185851.6"
- wire $1\alu_l_r_alu$next[0:0]$12535
- attribute \src "libresoc.v:184861.7-184861.25"
+ attribute \src "libresoc.v:183596.3-183604.6"
+ wire $1\alu_l_r_alu$next[0:0]$12443
+ attribute \src "libresoc.v:182614.7-182614.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468
- attribute \src "libresoc.v:184903.14-184903.54"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376
+ attribute \src "libresoc.v:182656.14-182656.54"
wire width 13 $1\alu_shift_rot0_sr_op__fn_unit[12:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469
- attribute \src "libresoc.v:184907.14-184907.73"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377
+ attribute \src "libresoc.v:182660.14-182660.73"
wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470
- attribute \src "libresoc.v:184911.7-184911.48"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378
+ attribute \src "libresoc.v:182664.7-182664.48"
wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471
- attribute \src "libresoc.v:184919.13-184919.53"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379
+ attribute \src "libresoc.v:182672.13-182672.53"
wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472
- attribute \src "libresoc.v:184923.7-184923.44"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380
+ attribute \src "libresoc.v:182676.7-182676.44"
wire $1\alu_shift_rot0_sr_op__input_cr[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473
- attribute \src "libresoc.v:184927.14-184927.48"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381
+ attribute \src "libresoc.v:182680.14-182680.48"
wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474
- attribute \src "libresoc.v:185005.13-185005.52"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382
+ attribute \src "libresoc.v:182758.13-182758.52"
wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475
- attribute \src "libresoc.v:185009.7-185009.45"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383
+ attribute \src "libresoc.v:182762.7-182762.45"
wire $1\alu_shift_rot0_sr_op__invert_in[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476
- attribute \src "libresoc.v:185013.7-185013.44"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384
+ attribute \src "libresoc.v:182766.7-182766.44"
wire $1\alu_shift_rot0_sr_op__is_32bit[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477
- attribute \src "libresoc.v:185017.7-185017.45"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385
+ attribute \src "libresoc.v:182770.7-182770.45"
wire $1\alu_shift_rot0_sr_op__is_signed[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478
- attribute \src "libresoc.v:185021.7-185021.42"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386
+ attribute \src "libresoc.v:182774.7-182774.42"
wire $1\alu_shift_rot0_sr_op__oe__oe[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479
- attribute \src "libresoc.v:185025.7-185025.42"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387
+ attribute \src "libresoc.v:182778.7-182778.42"
wire $1\alu_shift_rot0_sr_op__oe__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480
- attribute \src "libresoc.v:185029.7-185029.48"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388
+ attribute \src "libresoc.v:182782.7-182782.48"
wire $1\alu_shift_rot0_sr_op__output_carry[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481
- attribute \src "libresoc.v:185033.7-185033.45"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389
+ attribute \src "libresoc.v:182786.7-182786.45"
wire $1\alu_shift_rot0_sr_op__output_cr[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482
- attribute \src "libresoc.v:185037.7-185037.42"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390
+ attribute \src "libresoc.v:182790.7-182790.42"
wire $1\alu_shift_rot0_sr_op__rc__ok[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483
- attribute \src "libresoc.v:185041.7-185041.42"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391
+ attribute \src "libresoc.v:182794.7-182794.42"
wire $1\alu_shift_rot0_sr_op__rc__rc[0:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484
- attribute \src "libresoc.v:185045.7-185045.45"
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392
+ attribute \src "libresoc.v:182798.7-182798.45"
wire $1\alu_shift_rot0_sr_op__write_cr0[0:0]
- attribute \src "libresoc.v:185834.3-185842.6"
- wire $1\alui_l_r_alui$next[0:0]$12532
- attribute \src "libresoc.v:185057.7-185057.27"
+ attribute \src "libresoc.v:183587.3-183595.6"
+ wire $1\alui_l_r_alui$next[0:0]$12440
+ attribute \src "libresoc.v:182810.7-182810.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:185718.3-185739.6"
- wire width 64 $1\data_r0__o$next[63:0]$12494
- attribute \src "libresoc.v:185091.14-185091.47"
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire width 64 $1\data_r0__o$next[63:0]$12402
+ attribute \src "libresoc.v:182844.14-182844.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:185718.3-185739.6"
- wire $1\data_r0__o_ok$next[0:0]$12495
- attribute \src "libresoc.v:185095.7-185095.27"
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire $1\data_r0__o_ok$next[0:0]$12403
+ attribute \src "libresoc.v:182848.7-182848.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:185740.3-185761.6"
- wire width 4 $1\data_r1__cr_a$next[3:0]$12502
- attribute \src "libresoc.v:185099.13-185099.33"
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire width 4 $1\data_r1__cr_a$next[3:0]$12410
+ attribute \src "libresoc.v:182852.13-182852.33"
wire width 4 $1\data_r1__cr_a[3:0]
- attribute \src "libresoc.v:185740.3-185761.6"
- wire $1\data_r1__cr_a_ok$next[0:0]$12503
- attribute \src "libresoc.v:185103.7-185103.30"
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire $1\data_r1__cr_a_ok$next[0:0]$12411
+ attribute \src "libresoc.v:182856.7-182856.30"
wire $1\data_r1__cr_a_ok[0:0]
- attribute \src "libresoc.v:185762.3-185783.6"
- wire width 2 $1\data_r2__xer_ca$next[1:0]$12510
- attribute \src "libresoc.v:185107.13-185107.35"
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire width 2 $1\data_r2__xer_ca$next[1:0]$12418
+ attribute \src "libresoc.v:182860.13-182860.35"
wire width 2 $1\data_r2__xer_ca[1:0]
- attribute \src "libresoc.v:185762.3-185783.6"
- wire $1\data_r2__xer_ca_ok$next[0:0]$12511
- attribute \src "libresoc.v:185111.7-185111.32"
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire $1\data_r2__xer_ca_ok$next[0:0]$12419
+ attribute \src "libresoc.v:182864.7-182864.32"
wire $1\data_r2__xer_ca_ok[0:0]
- attribute \src "libresoc.v:185852.3-185861.6"
+ attribute \src "libresoc.v:183605.3-183614.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:185862.3-185871.6"
+ attribute \src "libresoc.v:183615.3-183624.6"
wire width 4 $1\dest2_o[3:0]
- attribute \src "libresoc.v:185872.3-185881.6"
+ attribute \src "libresoc.v:183625.3-183634.6"
wire width 2 $1\dest3_o[1:0]
- attribute \src "libresoc.v:185635.3-185643.6"
- wire $1\opc_l_r_opc$next[0:0]$12437
- attribute \src "libresoc.v:185128.7-185128.25"
+ attribute \src "libresoc.v:183388.3-183396.6"
+ wire $1\opc_l_r_opc$next[0:0]$12345
+ attribute \src "libresoc.v:182881.7-182881.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:185626.3-185634.6"
- wire $1\opc_l_s_opc$next[0:0]$12434
- attribute \src "libresoc.v:185132.7-185132.25"
+ attribute \src "libresoc.v:183379.3-183387.6"
+ wire $1\opc_l_s_opc$next[0:0]$12342
+ attribute \src "libresoc.v:182885.7-182885.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:185882.3-185890.6"
- wire width 3 $1\prev_wr_go$next[2:0]$12541
- attribute \src "libresoc.v:185262.13-185262.30"
+ attribute \src "libresoc.v:183635.3-183643.6"
+ wire width 3 $1\prev_wr_go$next[2:0]$12449
+ attribute \src "libresoc.v:183015.13-183015.30"
wire width 3 $1\prev_wr_go[2:0]
- attribute \src "libresoc.v:185580.3-185589.6"
+ attribute \src "libresoc.v:183333.3-183342.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:185671.3-185679.6"
- wire width 3 $1\req_l_r_req$next[2:0]$12449
- attribute \src "libresoc.v:185270.13-185270.31"
+ attribute \src "libresoc.v:183424.3-183432.6"
+ wire width 3 $1\req_l_r_req$next[2:0]$12357
+ attribute \src "libresoc.v:183023.13-183023.31"
wire width 3 $1\req_l_r_req[2:0]
- attribute \src "libresoc.v:185662.3-185670.6"
- wire width 3 $1\req_l_s_req$next[2:0]$12446
- attribute \src "libresoc.v:185274.13-185274.31"
+ attribute \src "libresoc.v:183415.3-183423.6"
+ wire width 3 $1\req_l_s_req$next[2:0]$12354
+ attribute \src "libresoc.v:183027.13-183027.31"
wire width 3 $1\req_l_s_req[2:0]
- attribute \src "libresoc.v:185599.3-185607.6"
- wire $1\rok_l_r_rdok$next[0:0]$12425
- attribute \src "libresoc.v:185286.7-185286.26"
+ attribute \src "libresoc.v:183352.3-183360.6"
+ wire $1\rok_l_r_rdok$next[0:0]$12333
+ attribute \src "libresoc.v:183039.7-183039.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:185590.3-185598.6"
- wire $1\rok_l_s_rdok$next[0:0]$12422
- attribute \src "libresoc.v:185290.7-185290.26"
+ attribute \src "libresoc.v:183343.3-183351.6"
+ wire $1\rok_l_s_rdok$next[0:0]$12330
+ attribute \src "libresoc.v:183043.7-183043.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:185617.3-185625.6"
- wire $1\rst_l_r_rst$next[0:0]$12431
- attribute \src "libresoc.v:185294.7-185294.25"
+ attribute \src "libresoc.v:183370.3-183378.6"
+ wire $1\rst_l_r_rst$next[0:0]$12339
+ attribute \src "libresoc.v:183047.7-183047.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:185608.3-185616.6"
- wire $1\rst_l_s_rst$next[0:0]$12428
- attribute \src "libresoc.v:185298.7-185298.25"
+ attribute \src "libresoc.v:183361.3-183369.6"
+ wire $1\rst_l_s_rst$next[0:0]$12336
+ attribute \src "libresoc.v:183051.7-183051.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:185653.3-185661.6"
- wire width 5 $1\src_l_r_src$next[4:0]$12443
- attribute \src "libresoc.v:185316.13-185316.32"
+ attribute \src "libresoc.v:183406.3-183414.6"
+ wire width 5 $1\src_l_r_src$next[4:0]$12351
+ attribute \src "libresoc.v:183069.13-183069.32"
wire width 5 $1\src_l_r_src[4:0]
- attribute \src "libresoc.v:185644.3-185652.6"
- wire width 5 $1\src_l_s_src$next[4:0]$12440
- attribute \src "libresoc.v:185320.13-185320.32"
+ attribute \src "libresoc.v:183397.3-183405.6"
+ wire width 5 $1\src_l_s_src$next[4:0]$12348
+ attribute \src "libresoc.v:183073.13-183073.32"
wire width 5 $1\src_l_s_src[4:0]
- attribute \src "libresoc.v:185784.3-185793.6"
- wire width 64 $1\src_r0$next[63:0]$12517
- attribute \src "libresoc.v:185326.14-185326.43"
+ attribute \src "libresoc.v:183537.3-183546.6"
+ wire width 64 $1\src_r0$next[63:0]$12425
+ attribute \src "libresoc.v:183079.14-183079.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:185794.3-185803.6"
- wire width 64 $1\src_r1$next[63:0]$12520
- attribute \src "libresoc.v:185330.14-185330.43"
+ attribute \src "libresoc.v:183547.3-183556.6"
+ wire width 64 $1\src_r1$next[63:0]$12428
+ attribute \src "libresoc.v:183083.14-183083.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:185804.3-185813.6"
- wire width 64 $1\src_r2$next[63:0]$12523
- attribute \src "libresoc.v:185334.14-185334.43"
+ attribute \src "libresoc.v:183557.3-183566.6"
+ wire width 64 $1\src_r2$next[63:0]$12431
+ attribute \src "libresoc.v:183087.14-183087.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:185814.3-185823.6"
- wire $1\src_r3$next[0:0]$12526
- attribute \src "libresoc.v:185338.7-185338.20"
+ attribute \src "libresoc.v:183567.3-183576.6"
+ wire $1\src_r3$next[0:0]$12434
+ attribute \src "libresoc.v:183091.7-183091.20"
wire $1\src_r3[0:0]
- attribute \src "libresoc.v:185824.3-185833.6"
- wire width 2 $1\src_r4$next[1:0]$12529
- attribute \src "libresoc.v:185342.13-185342.26"
+ attribute \src "libresoc.v:183577.3-183586.6"
+ wire width 2 $1\src_r4$next[1:0]$12437
+ attribute \src "libresoc.v:183095.13-183095.26"
wire width 2 $1\src_r4[1:0]
- attribute \src "libresoc.v:185680.3-185717.6"
- wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489
- attribute \src "libresoc.v:185680.3-185717.6"
- wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490
- attribute \src "libresoc.v:185718.3-185739.6"
- wire width 64 $2\data_r0__o$next[63:0]$12496
- attribute \src "libresoc.v:185718.3-185739.6"
- wire $2\data_r0__o_ok$next[0:0]$12497
- attribute \src "libresoc.v:185740.3-185761.6"
- wire width 4 $2\data_r1__cr_a$next[3:0]$12504
- attribute \src "libresoc.v:185740.3-185761.6"
- wire $2\data_r1__cr_a_ok$next[0:0]$12505
- attribute \src "libresoc.v:185762.3-185783.6"
- wire width 2 $2\data_r2__xer_ca$next[1:0]$12512
- attribute \src "libresoc.v:185762.3-185783.6"
- wire $2\data_r2__xer_ca_ok$next[0:0]$12513
- attribute \src "libresoc.v:185718.3-185739.6"
- wire $3\data_r0__o_ok$next[0:0]$12498
- attribute \src "libresoc.v:185740.3-185761.6"
- wire $3\data_r1__cr_a_ok$next[0:0]$12506
- attribute \src "libresoc.v:185762.3-185783.6"
- wire $3\data_r2__xer_ca_ok$next[0:0]$12514
- attribute \src "libresoc.v:185352.19-185352.114"
- wire width 5 $and$libresoc.v:185352$12318_Y
- attribute \src "libresoc.v:185353.19-185353.125"
- wire $and$libresoc.v:185353$12319_Y
- attribute \src "libresoc.v:185354.19-185354.125"
- wire $and$libresoc.v:185354$12320_Y
- attribute \src "libresoc.v:185355.19-185355.125"
- wire $and$libresoc.v:185355$12321_Y
- attribute \src "libresoc.v:185356.18-185356.110"
- wire $and$libresoc.v:185356$12322_Y
- attribute \src "libresoc.v:185357.19-185357.141"
- wire width 3 $and$libresoc.v:185357$12323_Y
- attribute \src "libresoc.v:185358.19-185358.121"
- wire width 3 $and$libresoc.v:185358$12324_Y
- attribute \src "libresoc.v:185359.19-185359.127"
- wire $and$libresoc.v:185359$12325_Y
- attribute \src "libresoc.v:185360.19-185360.127"
- wire $and$libresoc.v:185360$12326_Y
- attribute \src "libresoc.v:185361.19-185361.127"
- wire $and$libresoc.v:185361$12327_Y
- attribute \src "libresoc.v:185363.18-185363.98"
- wire $and$libresoc.v:185363$12329_Y
- attribute \src "libresoc.v:185365.18-185365.100"
- wire $and$libresoc.v:185365$12331_Y
- attribute \src "libresoc.v:185366.18-185366.149"
- wire width 3 $and$libresoc.v:185366$12332_Y
- attribute \src "libresoc.v:185368.18-185368.119"
- wire width 3 $and$libresoc.v:185368$12334_Y
- attribute \src "libresoc.v:185371.17-185371.123"
- wire $and$libresoc.v:185371$12337_Y
- attribute \src "libresoc.v:185372.18-185372.116"
- wire $and$libresoc.v:185372$12338_Y
- attribute \src "libresoc.v:185377.18-185377.113"
- wire $and$libresoc.v:185377$12343_Y
- attribute \src "libresoc.v:185378.18-185378.125"
- wire width 3 $and$libresoc.v:185378$12344_Y
- attribute \src "libresoc.v:185380.18-185380.112"
- wire $and$libresoc.v:185380$12346_Y
- attribute \src "libresoc.v:185382.18-185382.132"
- wire $and$libresoc.v:185382$12348_Y
- attribute \src "libresoc.v:185383.18-185383.132"
- wire $and$libresoc.v:185383$12349_Y
- attribute \src "libresoc.v:185384.18-185384.117"
- wire $and$libresoc.v:185384$12350_Y
- attribute \src "libresoc.v:185390.18-185390.136"
- wire $and$libresoc.v:185390$12356_Y
- attribute \src "libresoc.v:185391.18-185391.124"
- wire width 3 $and$libresoc.v:185391$12357_Y
- attribute \src "libresoc.v:185393.18-185393.116"
- wire $and$libresoc.v:185393$12359_Y
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- wire $and$libresoc.v:185394$12360_Y
- attribute \src "libresoc.v:185395.18-185395.121"
- wire $and$libresoc.v:185395$12361_Y
- attribute \src "libresoc.v:185405.18-185405.140"
- wire $and$libresoc.v:185405$12371_Y
- attribute \src "libresoc.v:185406.18-185406.138"
- wire $and$libresoc.v:185406$12372_Y
- attribute \src "libresoc.v:185407.18-185407.171"
- wire width 5 $and$libresoc.v:185407$12373_Y
- attribute \src "libresoc.v:185409.18-185409.129"
- wire width 5 $and$libresoc.v:185409$12375_Y
- attribute \src "libresoc.v:185379.18-185379.113"
- wire $eq$libresoc.v:185379$12345_Y
- attribute \src "libresoc.v:185381.18-185381.119"
- wire $eq$libresoc.v:185381$12347_Y
- attribute \src "libresoc.v:185351.19-185351.115"
- wire width 5 $not$libresoc.v:185351$12317_Y
- attribute \src "libresoc.v:185362.18-185362.97"
- wire $not$libresoc.v:185362$12328_Y
- attribute \src "libresoc.v:185364.18-185364.99"
- wire $not$libresoc.v:185364$12330_Y
- attribute \src "libresoc.v:185367.18-185367.113"
- wire width 3 $not$libresoc.v:185367$12333_Y
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- wire $not$libresoc.v:185370$12336_Y
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- wire $not$libresoc.v:185376$12342_Y
- attribute \src "libresoc.v:185387.17-185387.113"
- wire width 5 $not$libresoc.v:185387$12353_Y
- attribute \src "libresoc.v:185408.18-185408.136"
- wire $not$libresoc.v:185408$12374_Y
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- wire $or$libresoc.v:185375$12341_Y
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- wire $or$libresoc.v:185385$12351_Y
- attribute \src "libresoc.v:185386.18-185386.124"
- wire $or$libresoc.v:185386$12352_Y
- attribute \src "libresoc.v:185388.18-185388.155"
- wire width 3 $or$libresoc.v:185388$12354_Y
- attribute \src "libresoc.v:185389.18-185389.181"
- wire width 5 $or$libresoc.v:185389$12355_Y
- attribute \src "libresoc.v:185392.18-185392.120"
- wire width 3 $or$libresoc.v:185392$12358_Y
- attribute \src "libresoc.v:185398.17-185398.117"
- wire width 5 $or$libresoc.v:185398$12364_Y
- attribute \src "libresoc.v:185404.17-185404.104"
- wire $reduce_and$libresoc.v:185404$12370_Y
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- wire $reduce_or$libresoc.v:185369$12335_Y
- attribute \src "libresoc.v:185373.18-185373.113"
- wire $reduce_or$libresoc.v:185373$12339_Y
- attribute \src "libresoc.v:185374.18-185374.112"
- wire $reduce_or$libresoc.v:185374$12340_Y
- attribute \src "libresoc.v:185396.18-185396.165"
- wire $ternary$libresoc.v:185396$12362_Y
- attribute \src "libresoc.v:185397.18-185397.182"
- wire width 64 $ternary$libresoc.v:185397$12363_Y
- attribute \src "libresoc.v:185399.18-185399.118"
- wire width 64 $ternary$libresoc.v:185399$12365_Y
- attribute \src "libresoc.v:185400.18-185400.115"
- wire width 64 $ternary$libresoc.v:185400$12366_Y
- attribute \src "libresoc.v:185401.18-185401.118"
- wire width 64 $ternary$libresoc.v:185401$12367_Y
- attribute \src "libresoc.v:185402.18-185402.118"
- wire $ternary$libresoc.v:185402$12368_Y
- attribute \src "libresoc.v:185403.18-185403.118"
- wire width 2 $ternary$libresoc.v:185403$12369_Y
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397
+ attribute \src "libresoc.v:183433.3-183470.6"
+ wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire width 64 $2\data_r0__o$next[63:0]$12404
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire $2\data_r0__o_ok$next[0:0]$12405
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire width 4 $2\data_r1__cr_a$next[3:0]$12412
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire $2\data_r1__cr_a_ok$next[0:0]$12413
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire width 2 $2\data_r2__xer_ca$next[1:0]$12420
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire $2\data_r2__xer_ca_ok$next[0:0]$12421
+ attribute \src "libresoc.v:183471.3-183492.6"
+ wire $3\data_r0__o_ok$next[0:0]$12406
+ attribute \src "libresoc.v:183493.3-183514.6"
+ wire $3\data_r1__cr_a_ok$next[0:0]$12414
+ attribute \src "libresoc.v:183515.3-183536.6"
+ wire $3\data_r2__xer_ca_ok$next[0:0]$12422
+ attribute \src "libresoc.v:183105.19-183105.114"
+ wire width 5 $and$libresoc.v:183105$12226_Y
+ attribute \src "libresoc.v:183106.19-183106.125"
+ wire $and$libresoc.v:183106$12227_Y
+ attribute \src "libresoc.v:183107.19-183107.125"
+ wire $and$libresoc.v:183107$12228_Y
+ attribute \src "libresoc.v:183108.19-183108.125"
+ wire $and$libresoc.v:183108$12229_Y
+ attribute \src "libresoc.v:183109.18-183109.110"
+ wire $and$libresoc.v:183109$12230_Y
+ attribute \src "libresoc.v:183110.19-183110.141"
+ wire width 3 $and$libresoc.v:183110$12231_Y
+ attribute \src "libresoc.v:183111.19-183111.121"
+ wire width 3 $and$libresoc.v:183111$12232_Y
+ attribute \src "libresoc.v:183112.19-183112.127"
+ wire $and$libresoc.v:183112$12233_Y
+ attribute \src "libresoc.v:183113.19-183113.127"
+ wire $and$libresoc.v:183113$12234_Y
+ attribute \src "libresoc.v:183114.19-183114.127"
+ wire $and$libresoc.v:183114$12235_Y
+ attribute \src "libresoc.v:183116.18-183116.98"
+ wire $and$libresoc.v:183116$12237_Y
+ attribute \src "libresoc.v:183118.18-183118.100"
+ wire $and$libresoc.v:183118$12239_Y
+ attribute \src "libresoc.v:183119.18-183119.149"
+ wire width 3 $and$libresoc.v:183119$12240_Y
+ attribute \src "libresoc.v:183121.18-183121.119"
+ wire width 3 $and$libresoc.v:183121$12242_Y
+ attribute \src "libresoc.v:183124.17-183124.123"
+ wire $and$libresoc.v:183124$12245_Y
+ attribute \src "libresoc.v:183125.18-183125.116"
+ wire $and$libresoc.v:183125$12246_Y
+ attribute \src "libresoc.v:183130.18-183130.113"
+ wire $and$libresoc.v:183130$12251_Y
+ attribute \src "libresoc.v:183131.18-183131.125"
+ wire width 3 $and$libresoc.v:183131$12252_Y
+ attribute \src "libresoc.v:183133.18-183133.112"
+ wire $and$libresoc.v:183133$12254_Y
+ attribute \src "libresoc.v:183135.18-183135.132"
+ wire $and$libresoc.v:183135$12256_Y
+ attribute \src "libresoc.v:183136.18-183136.132"
+ wire $and$libresoc.v:183136$12257_Y
+ attribute \src "libresoc.v:183137.18-183137.117"
+ wire $and$libresoc.v:183137$12258_Y
+ attribute \src "libresoc.v:183143.18-183143.136"
+ wire $and$libresoc.v:183143$12264_Y
+ attribute \src "libresoc.v:183144.18-183144.124"
+ wire width 3 $and$libresoc.v:183144$12265_Y
+ attribute \src "libresoc.v:183146.18-183146.116"
+ wire $and$libresoc.v:183146$12267_Y
+ attribute \src "libresoc.v:183147.18-183147.119"
+ wire $and$libresoc.v:183147$12268_Y
+ attribute \src "libresoc.v:183148.18-183148.121"
+ wire $and$libresoc.v:183148$12269_Y
+ attribute \src "libresoc.v:183158.18-183158.140"
+ wire $and$libresoc.v:183158$12279_Y
+ attribute \src "libresoc.v:183159.18-183159.138"
+ wire $and$libresoc.v:183159$12280_Y
+ attribute \src "libresoc.v:183160.18-183160.171"
+ wire width 5 $and$libresoc.v:183160$12281_Y
+ attribute \src "libresoc.v:183162.18-183162.129"
+ wire width 5 $and$libresoc.v:183162$12283_Y
+ attribute \src "libresoc.v:183132.18-183132.113"
+ wire $eq$libresoc.v:183132$12253_Y
+ attribute \src "libresoc.v:183134.18-183134.119"
+ wire $eq$libresoc.v:183134$12255_Y
+ attribute \src "libresoc.v:183104.19-183104.115"
+ wire width 5 $not$libresoc.v:183104$12225_Y
+ attribute \src "libresoc.v:183115.18-183115.97"
+ wire $not$libresoc.v:183115$12236_Y
+ attribute \src "libresoc.v:183117.18-183117.99"
+ wire $not$libresoc.v:183117$12238_Y
+ attribute \src "libresoc.v:183120.18-183120.113"
+ wire width 3 $not$libresoc.v:183120$12241_Y
+ attribute \src "libresoc.v:183123.18-183123.106"
+ wire $not$libresoc.v:183123$12244_Y
+ attribute \src "libresoc.v:183129.18-183129.126"
+ wire $not$libresoc.v:183129$12250_Y
+ attribute \src "libresoc.v:183140.17-183140.113"
+ wire width 5 $not$libresoc.v:183140$12261_Y
+ attribute \src "libresoc.v:183161.18-183161.136"
+ wire $not$libresoc.v:183161$12282_Y
+ attribute \src "libresoc.v:183128.18-183128.112"
+ wire $or$libresoc.v:183128$12249_Y
+ attribute \src "libresoc.v:183138.18-183138.122"
+ wire $or$libresoc.v:183138$12259_Y
+ attribute \src "libresoc.v:183139.18-183139.124"
+ wire $or$libresoc.v:183139$12260_Y
+ attribute \src "libresoc.v:183141.18-183141.155"
+ wire width 3 $or$libresoc.v:183141$12262_Y
+ attribute \src "libresoc.v:183142.18-183142.181"
+ wire width 5 $or$libresoc.v:183142$12263_Y
+ attribute \src "libresoc.v:183145.18-183145.120"
+ wire width 3 $or$libresoc.v:183145$12266_Y
+ attribute \src "libresoc.v:183151.17-183151.117"
+ wire width 5 $or$libresoc.v:183151$12272_Y
+ attribute \src "libresoc.v:183157.17-183157.104"
+ wire $reduce_and$libresoc.v:183157$12278_Y
+ attribute \src "libresoc.v:183122.18-183122.106"
+ wire $reduce_or$libresoc.v:183122$12243_Y
+ attribute \src "libresoc.v:183126.18-183126.113"
+ wire $reduce_or$libresoc.v:183126$12247_Y
+ attribute \src "libresoc.v:183127.18-183127.112"
+ wire $reduce_or$libresoc.v:183127$12248_Y
+ attribute \src "libresoc.v:183149.18-183149.165"
+ wire $ternary$libresoc.v:183149$12270_Y
+ attribute \src "libresoc.v:183150.18-183150.182"
+ wire width 64 $ternary$libresoc.v:183150$12271_Y
+ attribute \src "libresoc.v:183152.18-183152.118"
+ wire width 64 $ternary$libresoc.v:183152$12273_Y
+ attribute \src "libresoc.v:183153.18-183153.115"
+ wire width 64 $ternary$libresoc.v:183153$12274_Y
+ attribute \src "libresoc.v:183154.18-183154.118"
+ wire width 64 $ternary$libresoc.v:183154$12275_Y
+ attribute \src "libresoc.v:183155.18-183155.118"
+ wire $ternary$libresoc.v:183155$12276_Y
+ attribute \src "libresoc.v:183156.18-183156.118"
+ wire width 2 $ternary$libresoc.v:183156$12277_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 37 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 33 \cr_a_ok
wire width 4 output 34 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 2 output 36 \dest3_o
- attribute \src "libresoc.v:184721.7-184721.15"
+ attribute \src "libresoc.v:182474.7-182474.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 35 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:185352$12318
+ cell $and $and$libresoc.v:183105$12226
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$98
connect \B \$100
- connect \Y $and$libresoc.v:185352$12318_Y
+ connect \Y $and$libresoc.v:183105$12226_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:185353$12319
+ cell $and $and$libresoc.v:183106$12227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:185353$12319_Y
+ connect \Y $and$libresoc.v:183106$12227_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:185354$12320
+ cell $and $and$libresoc.v:183107$12228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:185354$12320_Y
+ connect \Y $and$libresoc.v:183107$12228_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:185355$12321
+ cell $and $and$libresoc.v:183108$12229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:185355$12321_Y
+ connect \Y $and$libresoc.v:183108$12229_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:185356$12322
+ cell $and $and$libresoc.v:183109$12230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$2
connect \B \$4
- connect \Y $and$libresoc.v:185356$12322_Y
+ connect \Y $and$libresoc.v:183109$12230_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:185357$12323
+ cell $and $and$libresoc.v:183110$12231
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B { \$104 \$106 \$108 }
- connect \Y $and$libresoc.v:185357$12323_Y
+ connect \Y $and$libresoc.v:183110$12231_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:185358$12324
+ cell $and $and$libresoc.v:183111$12232
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$110
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:185358$12324_Y
+ connect \Y $and$libresoc.v:183111$12232_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:185359$12325
+ cell $and $and$libresoc.v:183112$12233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185359$12325_Y
+ connect \Y $and$libresoc.v:183112$12233_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:185360$12326
+ cell $and $and$libresoc.v:183113$12234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185360$12326_Y
+ connect \Y $and$libresoc.v:183113$12234_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:185361$12327
+ cell $and $and$libresoc.v:183114$12235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185361$12327_Y
+ connect \Y $and$libresoc.v:183114$12235_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:185363$12329
+ cell $and $and$libresoc.v:183116$12237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$12
- connect \Y $and$libresoc.v:185363$12329_Y
+ connect \Y $and$libresoc.v:183116$12237_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:185365$12331
+ cell $and $and$libresoc.v:183118$12239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$16
- connect \Y $and$libresoc.v:185365$12331_Y
+ connect \Y $and$libresoc.v:183118$12239_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:185366$12332
+ cell $and $and$libresoc.v:183119$12240
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:185366$12332_Y
+ connect \Y $and$libresoc.v:183119$12240_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:185368$12334
+ cell $and $and$libresoc.v:183121$12242
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__rel_o
connect \B \$24
- connect \Y $and$libresoc.v:185368$12334_Y
+ connect \Y $and$libresoc.v:183121$12242_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:185371$12337
+ cell $and $and$libresoc.v:183124$12245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:185371$12337_Y
+ connect \Y $and$libresoc.v:183124$12245_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:185372$12338
+ cell $and $and$libresoc.v:183125$12246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$22
- connect \Y $and$libresoc.v:185372$12338_Y
+ connect \Y $and$libresoc.v:183125$12246_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:185377$12343
+ cell $and $and$libresoc.v:183130$12251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$38
- connect \Y $and$libresoc.v:185377$12343_Y
+ connect \Y $and$libresoc.v:183130$12251_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:185378$12344
+ cell $and $and$libresoc.v:183131$12252
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:185378$12344_Y
+ connect \Y $and$libresoc.v:183131$12252_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:185380$12346
+ cell $and $and$libresoc.v:183133$12254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$40
connect \B \$44
- connect \Y $and$libresoc.v:185380$12346_Y
+ connect \Y $and$libresoc.v:183133$12254_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:185382$12348
+ cell $and $and$libresoc.v:183135$12256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$48
connect \B \alu_shift_rot0_n_ready_i
- connect \Y $and$libresoc.v:185382$12348_Y
+ connect \Y $and$libresoc.v:183135$12256_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:185383$12349
+ cell $and $and$libresoc.v:183136$12257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$50
connect \B \alu_shift_rot0_n_valid_o
- connect \Y $and$libresoc.v:185383$12349_Y
+ connect \Y $and$libresoc.v:183136$12257_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:185384$12350
+ cell $and $and$libresoc.v:183137$12258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185384$12350_Y
+ connect \Y $and$libresoc.v:183137$12258_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:185390$12356
+ cell $and $and$libresoc.v:183143$12264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185390$12356_Y
+ connect \Y $and$libresoc.v:183143$12264_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:185391$12357
+ cell $and $and$libresoc.v:183144$12265
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:185391$12357_Y
+ connect \Y $and$libresoc.v:183144$12265_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:185393$12359
+ cell $and $and$libresoc.v:183146$12267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185393$12359_Y
+ connect \Y $and$libresoc.v:183146$12267_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:185394$12360
+ cell $and $and$libresoc.v:183147$12268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_a_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185394$12360_Y
+ connect \Y $and$libresoc.v:183147$12268_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:185395$12361
+ cell $and $and$libresoc.v:183148$12269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ca_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:185395$12361_Y
+ connect \Y $and$libresoc.v:183148$12269_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:185405$12371
+ cell $and $and$libresoc.v:183158$12279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:185405$12371_Y
+ connect \Y $and$libresoc.v:183158$12279_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:185406$12372
+ cell $and $and$libresoc.v:183159$12280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:185406$12372_Y
+ connect \Y $and$libresoc.v:183159$12280_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:185407$12373
+ cell $and $and$libresoc.v:183160$12281
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:185407$12373_Y
+ connect \Y $and$libresoc.v:183160$12281_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:185409$12375
+ cell $and $and$libresoc.v:183162$12283
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$94
connect \B { 3'111 \$96 1'1 }
- connect \Y $and$libresoc.v:185409$12375_Y
+ connect \Y $and$libresoc.v:183162$12283_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:185379$12345
+ cell $eq $eq$libresoc.v:183132$12253
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$42
connect \B 1'0
- connect \Y $eq$libresoc.v:185379$12345_Y
+ connect \Y $eq$libresoc.v:183132$12253_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:185381$12347
+ cell $eq $eq$libresoc.v:183134$12255
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:185381$12347_Y
+ connect \Y $eq$libresoc.v:183134$12255_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:185351$12317
+ cell $not $not$libresoc.v:183104$12225
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:185351$12317_Y
+ connect \Y $not$libresoc.v:183104$12225_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:185362$12328
+ cell $not $not$libresoc.v:183115$12236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:185362$12328_Y
+ connect \Y $not$libresoc.v:183115$12236_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:185364$12330
+ cell $not $not$libresoc.v:183117$12238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:185364$12330_Y
+ connect \Y $not$libresoc.v:183117$12238_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:185367$12333
+ cell $not $not$libresoc.v:183120$12241
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:185367$12333_Y
+ connect \Y $not$libresoc.v:183120$12241_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:185370$12336
+ cell $not $not$libresoc.v:183123$12244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$23
- connect \Y $not$libresoc.v:185370$12336_Y
+ connect \Y $not$libresoc.v:183123$12244_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:185376$12342
+ cell $not $not$libresoc.v:183129$12250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_ready_i
- connect \Y $not$libresoc.v:185376$12342_Y
+ connect \Y $not$libresoc.v:183129$12250_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:185387$12353
+ cell $not $not$libresoc.v:183140$12261
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:185387$12353_Y
+ connect \Y $not$libresoc.v:183140$12261_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173"
- cell $not $not$libresoc.v:185408$12374
+ cell $not $not$libresoc.v:183161$12282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $not$libresoc.v:185408$12374_Y
+ connect \Y $not$libresoc.v:183161$12282_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:185375$12341
+ cell $or $or$libresoc.v:183128$12249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$32
connect \B \$34
- connect \Y $or$libresoc.v:185375$12341_Y
+ connect \Y $or$libresoc.v:183128$12249_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:185385$12351
+ cell $or $or$libresoc.v:183138$12259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:185385$12351_Y
+ connect \Y $or$libresoc.v:183138$12259_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:185386$12352
+ cell $or $or$libresoc.v:183139$12260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:185386$12352_Y
+ connect \Y $or$libresoc.v:183139$12260_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:185388$12354
+ cell $or $or$libresoc.v:183141$12262
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:185388$12354_Y
+ connect \Y $or$libresoc.v:183141$12262_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:185389$12355
+ cell $or $or$libresoc.v:183142$12263
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:185389$12355_Y
+ connect \Y $or$libresoc.v:183142$12263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:185392$12358
+ cell $or $or$libresoc.v:183145$12266
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:185392$12358_Y
+ connect \Y $or$libresoc.v:183145$12266_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:185398$12364
+ cell $or $or$libresoc.v:183151$12272
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$5
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:185398$12364_Y
+ connect \Y $or$libresoc.v:183151$12272_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:185404$12370
+ cell $reduce_and $reduce_and$libresoc.v:183157$12278
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$7
- connect \Y $reduce_and$libresoc.v:185404$12370_Y
+ connect \Y $reduce_and$libresoc.v:183157$12278_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:185369$12335
+ cell $reduce_or $reduce_or$libresoc.v:183122$12243
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$26
- connect \Y $reduce_or$libresoc.v:185369$12335_Y
+ connect \Y $reduce_or$libresoc.v:183122$12243_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:185373$12339
+ cell $reduce_or $reduce_or$libresoc.v:183126$12247
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:185373$12339_Y
+ connect \Y $reduce_or$libresoc.v:183126$12247_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:185374$12340
+ cell $reduce_or $reduce_or$libresoc.v:183127$12248
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:185374$12340_Y
+ connect \Y $reduce_or$libresoc.v:183127$12248_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
- cell $mux $ternary$libresoc.v:185396$12362
+ cell $mux $ternary$libresoc.v:183149$12270
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $ternary$libresoc.v:185396$12362_Y
+ connect \Y $ternary$libresoc.v:183149$12270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169"
- cell $mux $ternary$libresoc.v:185397$12363
+ cell $mux $ternary$libresoc.v:183150$12271
parameter \WIDTH 64
connect \A \src2_i
connect \B \alu_shift_rot0_sr_op__imm_data__data
connect \S \alu_shift_rot0_sr_op__imm_data__ok
- connect \Y $ternary$libresoc.v:185397$12363_Y
+ connect \Y $ternary$libresoc.v:183150$12271_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:185399$12365
+ cell $mux $ternary$libresoc.v:183152$12273
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:185399$12365_Y
+ connect \Y $ternary$libresoc.v:183152$12273_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:185400$12366
+ cell $mux $ternary$libresoc.v:183153$12274
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $ternary$libresoc.v:185400$12366_Y
+ connect \Y $ternary$libresoc.v:183153$12274_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:185401$12367
+ cell $mux $ternary$libresoc.v:183154$12275
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:185401$12367_Y
+ connect \Y $ternary$libresoc.v:183154$12275_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:185402$12368
+ cell $mux $ternary$libresoc.v:183155$12276
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:185402$12368_Y
+ connect \Y $ternary$libresoc.v:183155$12276_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:185403$12369
+ cell $mux $ternary$libresoc.v:183156$12277
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:185403$12369_Y
+ connect \Y $ternary$libresoc.v:183156$12277_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185496.15-185502.4"
+ attribute \src "libresoc.v:183249.15-183255.4"
cell \alu_l$125 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185503.18-185538.4"
+ attribute \src "libresoc.v:183256.18-183291.4"
cell \alu_shift_rot0 \alu_shift_rot0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so \alu_shift_rot0_xer_so
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185539.16-185545.4"
+ attribute \src "libresoc.v:183292.16-183298.4"
cell \alui_l$124 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185546.15-185552.4"
+ attribute \src "libresoc.v:183299.15-183305.4"
cell \opc_l$120 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185553.15-185559.4"
+ attribute \src "libresoc.v:183306.15-183312.4"
cell \req_l$121 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185560.15-185566.4"
+ attribute \src "libresoc.v:183313.15-183319.4"
cell \rok_l$123 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185567.15-185572.4"
+ attribute \src "libresoc.v:183320.15-183325.4"
cell \rst_l$122 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:185573.15-185579.4"
+ attribute \src "libresoc.v:183326.15-183332.4"
cell \src_l$119 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:184721.7-184721.20"
- process $proc$libresoc.v:184721$12542
+ attribute \src "libresoc.v:182474.7-182474.20"
+ process $proc$libresoc.v:182474$12450
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:184843.7-184843.24"
- process $proc$libresoc.v:184843$12543
+ attribute \src "libresoc.v:182596.7-182596.24"
+ process $proc$libresoc.v:182596$12451
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:184853.7-184853.26"
- process $proc$libresoc.v:184853$12544
+ attribute \src "libresoc.v:182606.7-182606.26"
+ process $proc$libresoc.v:182606$12452
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:184861.7-184861.25"
- process $proc$libresoc.v:184861$12545
+ attribute \src "libresoc.v:182614.7-182614.25"
+ process $proc$libresoc.v:182614$12453
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:184903.14-184903.54"
- process $proc$libresoc.v:184903$12546
+ attribute \src "libresoc.v:182656.14-182656.54"
+ process $proc$libresoc.v:182656$12454
assign { } { }
assign $1\alu_shift_rot0_sr_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:184907.14-184907.73"
- process $proc$libresoc.v:184907$12547
+ attribute \src "libresoc.v:182660.14-182660.73"
+ process $proc$libresoc.v:182660$12455
assign { } { }
assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:184911.7-184911.48"
- process $proc$libresoc.v:184911$12548
+ attribute \src "libresoc.v:182664.7-182664.48"
+ process $proc$libresoc.v:182664$12456
assign { } { }
assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:184919.13-184919.53"
- process $proc$libresoc.v:184919$12549
+ attribute \src "libresoc.v:182672.13-182672.53"
+ process $proc$libresoc.v:182672$12457
assign { } { }
assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00
sync always
sync init
update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:184923.7-184923.44"
- process $proc$libresoc.v:184923$12550
+ attribute \src "libresoc.v:182676.7-182676.44"
+ process $proc$libresoc.v:182676$12458
assign { } { }
assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:184927.14-184927.48"
- process $proc$libresoc.v:184927$12551
+ attribute \src "libresoc.v:182680.14-182680.48"
+ process $proc$libresoc.v:182680$12459
assign { } { }
assign $1\alu_shift_rot0_sr_op__insn[31:0] 0
sync always
sync init
update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0]
end
- attribute \src "libresoc.v:185005.13-185005.52"
- process $proc$libresoc.v:185005$12552
+ attribute \src "libresoc.v:182758.13-182758.52"
+ process $proc$libresoc.v:182758$12460
assign { } { }
assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:185009.7-185009.45"
- process $proc$libresoc.v:185009$12553
+ attribute \src "libresoc.v:182762.7-182762.45"
+ process $proc$libresoc.v:182762$12461
assign { } { }
assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:185013.7-185013.44"
- process $proc$libresoc.v:185013$12554
+ attribute \src "libresoc.v:182766.7-182766.44"
+ process $proc$libresoc.v:182766$12462
assign { } { }
assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:185017.7-185017.45"
- process $proc$libresoc.v:185017$12555
+ attribute \src "libresoc.v:182770.7-182770.45"
+ process $proc$libresoc.v:182770$12463
assign { } { }
assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:185021.7-185021.42"
- process $proc$libresoc.v:185021$12556
+ attribute \src "libresoc.v:182774.7-182774.42"
+ process $proc$libresoc.v:182774$12464
assign { } { }
assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:185025.7-185025.42"
- process $proc$libresoc.v:185025$12557
+ attribute \src "libresoc.v:182778.7-182778.42"
+ process $proc$libresoc.v:182778$12465
assign { } { }
assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:185029.7-185029.48"
- process $proc$libresoc.v:185029$12558
+ attribute \src "libresoc.v:182782.7-182782.48"
+ process $proc$libresoc.v:182782$12466
assign { } { }
assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:185033.7-185033.45"
- process $proc$libresoc.v:185033$12559
+ attribute \src "libresoc.v:182786.7-182786.45"
+ process $proc$libresoc.v:182786$12467
assign { } { }
assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:185037.7-185037.42"
- process $proc$libresoc.v:185037$12560
+ attribute \src "libresoc.v:182790.7-182790.42"
+ process $proc$libresoc.v:182790$12468
assign { } { }
assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:185041.7-185041.42"
- process $proc$libresoc.v:185041$12561
+ attribute \src "libresoc.v:182794.7-182794.42"
+ process $proc$libresoc.v:182794$12469
assign { } { }
assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:185045.7-185045.45"
- process $proc$libresoc.v:185045$12562
+ attribute \src "libresoc.v:182798.7-182798.45"
+ process $proc$libresoc.v:182798$12470
assign { } { }
assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0
sync always
sync init
update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:185057.7-185057.27"
- process $proc$libresoc.v:185057$12563
+ attribute \src "libresoc.v:182810.7-182810.27"
+ process $proc$libresoc.v:182810$12471
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:185091.14-185091.47"
- process $proc$libresoc.v:185091$12564
+ attribute \src "libresoc.v:182844.14-182844.47"
+ process $proc$libresoc.v:182844$12472
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:185095.7-185095.27"
- process $proc$libresoc.v:185095$12565
+ attribute \src "libresoc.v:182848.7-182848.27"
+ process $proc$libresoc.v:182848$12473
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:185099.13-185099.33"
- process $proc$libresoc.v:185099$12566
+ attribute \src "libresoc.v:182852.13-182852.33"
+ process $proc$libresoc.v:182852$12474
assign { } { }
assign $1\data_r1__cr_a[3:0] 4'0000
sync always
sync init
update \data_r1__cr_a $1\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:185103.7-185103.30"
- process $proc$libresoc.v:185103$12567
+ attribute \src "libresoc.v:182856.7-182856.30"
+ process $proc$libresoc.v:182856$12475
assign { } { }
assign $1\data_r1__cr_a_ok[0:0] 1'0
sync always
sync init
update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:185107.13-185107.35"
- process $proc$libresoc.v:185107$12568
+ attribute \src "libresoc.v:182860.13-182860.35"
+ process $proc$libresoc.v:182860$12476
assign { } { }
assign $1\data_r2__xer_ca[1:0] 2'00
sync always
sync init
update \data_r2__xer_ca $1\data_r2__xer_ca[1:0]
end
- attribute \src "libresoc.v:185111.7-185111.32"
- process $proc$libresoc.v:185111$12569
+ attribute \src "libresoc.v:182864.7-182864.32"
+ process $proc$libresoc.v:182864$12477
assign { } { }
assign $1\data_r2__xer_ca_ok[0:0] 1'0
sync always
sync init
update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:185128.7-185128.25"
- process $proc$libresoc.v:185128$12570
+ attribute \src "libresoc.v:182881.7-182881.25"
+ process $proc$libresoc.v:182881$12478
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:185132.7-185132.25"
- process $proc$libresoc.v:185132$12571
+ attribute \src "libresoc.v:182885.7-182885.25"
+ process $proc$libresoc.v:182885$12479
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:185262.13-185262.30"
- process $proc$libresoc.v:185262$12572
+ attribute \src "libresoc.v:183015.13-183015.30"
+ process $proc$libresoc.v:183015$12480
assign { } { }
assign $1\prev_wr_go[2:0] 3'000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:185270.13-185270.31"
- process $proc$libresoc.v:185270$12573
+ attribute \src "libresoc.v:183023.13-183023.31"
+ process $proc$libresoc.v:183023$12481
assign { } { }
assign $1\req_l_r_req[2:0] 3'111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:185274.13-185274.31"
- process $proc$libresoc.v:185274$12574
+ attribute \src "libresoc.v:183027.13-183027.31"
+ process $proc$libresoc.v:183027$12482
assign { } { }
assign $1\req_l_s_req[2:0] 3'000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:185286.7-185286.26"
- process $proc$libresoc.v:185286$12575
+ attribute \src "libresoc.v:183039.7-183039.26"
+ process $proc$libresoc.v:183039$12483
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:185290.7-185290.26"
- process $proc$libresoc.v:185290$12576
+ attribute \src "libresoc.v:183043.7-183043.26"
+ process $proc$libresoc.v:183043$12484
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:185294.7-185294.25"
- process $proc$libresoc.v:185294$12577
+ attribute \src "libresoc.v:183047.7-183047.25"
+ process $proc$libresoc.v:183047$12485
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:185298.7-185298.25"
- process $proc$libresoc.v:185298$12578
+ attribute \src "libresoc.v:183051.7-183051.25"
+ process $proc$libresoc.v:183051$12486
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:185316.13-185316.32"
- process $proc$libresoc.v:185316$12579
+ attribute \src "libresoc.v:183069.13-183069.32"
+ process $proc$libresoc.v:183069$12487
assign { } { }
assign $1\src_l_r_src[4:0] 5'11111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[4:0]
end
- attribute \src "libresoc.v:185320.13-185320.32"
- process $proc$libresoc.v:185320$12580
+ attribute \src "libresoc.v:183073.13-183073.32"
+ process $proc$libresoc.v:183073$12488
assign { } { }
assign $1\src_l_s_src[4:0] 5'00000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[4:0]
end
- attribute \src "libresoc.v:185326.14-185326.43"
- process $proc$libresoc.v:185326$12581
+ attribute \src "libresoc.v:183079.14-183079.43"
+ process $proc$libresoc.v:183079$12489
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:185330.14-185330.43"
- process $proc$libresoc.v:185330$12582
+ attribute \src "libresoc.v:183083.14-183083.43"
+ process $proc$libresoc.v:183083$12490
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:185334.14-185334.43"
- process $proc$libresoc.v:185334$12583
+ attribute \src "libresoc.v:183087.14-183087.43"
+ process $proc$libresoc.v:183087$12491
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:185338.7-185338.20"
- process $proc$libresoc.v:185338$12584
+ attribute \src "libresoc.v:183091.7-183091.20"
+ process $proc$libresoc.v:183091$12492
assign { } { }
assign $1\src_r3[0:0] 1'0
sync always
sync init
update \src_r3 $1\src_r3[0:0]
end
- attribute \src "libresoc.v:185342.13-185342.26"
- process $proc$libresoc.v:185342$12585
+ attribute \src "libresoc.v:183095.13-183095.26"
+ process $proc$libresoc.v:183095$12493
assign { } { }
assign $1\src_r4[1:0] 2'00
sync always
sync init
update \src_r4 $1\src_r4[1:0]
end
- attribute \src "libresoc.v:185410.3-185411.39"
- process $proc$libresoc.v:185410$12376
+ attribute \src "libresoc.v:183163.3-183164.39"
+ process $proc$libresoc.v:183163$12284
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:185412.3-185413.43"
- process $proc$libresoc.v:185412$12377
+ attribute \src "libresoc.v:183165.3-183166.43"
+ process $proc$libresoc.v:183165$12285
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:185414.3-185415.29"
- process $proc$libresoc.v:185414$12378
+ attribute \src "libresoc.v:183167.3-183168.29"
+ process $proc$libresoc.v:183167$12286
assign { } { }
assign $0\src_r4[1:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[1:0]
end
- attribute \src "libresoc.v:185416.3-185417.29"
- process $proc$libresoc.v:185416$12379
+ attribute \src "libresoc.v:183169.3-183170.29"
+ process $proc$libresoc.v:183169$12287
assign { } { }
assign $0\src_r3[0:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[0:0]
end
- attribute \src "libresoc.v:185418.3-185419.29"
- process $proc$libresoc.v:185418$12380
+ attribute \src "libresoc.v:183171.3-183172.29"
+ process $proc$libresoc.v:183171$12288
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:185420.3-185421.29"
- process $proc$libresoc.v:185420$12381
+ attribute \src "libresoc.v:183173.3-183174.29"
+ process $proc$libresoc.v:183173$12289
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:185422.3-185423.29"
- process $proc$libresoc.v:185422$12382
+ attribute \src "libresoc.v:183175.3-183176.29"
+ process $proc$libresoc.v:183175$12290
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:185424.3-185425.47"
- process $proc$libresoc.v:185424$12383
+ attribute \src "libresoc.v:183177.3-183178.47"
+ process $proc$libresoc.v:183177$12291
assign { } { }
assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next
sync posedge \coresync_clk
update \data_r2__xer_ca $0\data_r2__xer_ca[1:0]
end
- attribute \src "libresoc.v:185426.3-185427.53"
- process $proc$libresoc.v:185426$12384
+ attribute \src "libresoc.v:183179.3-183180.53"
+ process $proc$libresoc.v:183179$12292
assign { } { }
assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next
sync posedge \coresync_clk
update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:185428.3-185429.43"
- process $proc$libresoc.v:185428$12385
+ attribute \src "libresoc.v:183181.3-183182.43"
+ process $proc$libresoc.v:183181$12293
assign { } { }
assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next
sync posedge \coresync_clk
update \data_r1__cr_a $0\data_r1__cr_a[3:0]
end
- attribute \src "libresoc.v:185430.3-185431.49"
- process $proc$libresoc.v:185430$12386
+ attribute \src "libresoc.v:183183.3-183184.49"
+ process $proc$libresoc.v:183183$12294
assign { } { }
assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next
sync posedge \coresync_clk
update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0]
end
- attribute \src "libresoc.v:185432.3-185433.37"
- process $proc$libresoc.v:185432$12387
+ attribute \src "libresoc.v:183185.3-183186.37"
+ process $proc$libresoc.v:183185$12295
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:185434.3-185435.43"
- process $proc$libresoc.v:185434$12388
+ attribute \src "libresoc.v:183187.3-183188.43"
+ process $proc$libresoc.v:183187$12296
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:185436.3-185437.79"
- process $proc$libresoc.v:185436$12389
+ attribute \src "libresoc.v:183189.3-183190.79"
+ process $proc$libresoc.v:183189$12297
assign { } { }
assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:185438.3-185439.75"
- process $proc$libresoc.v:185438$12390
+ attribute \src "libresoc.v:183191.3-183192.75"
+ process $proc$libresoc.v:183191$12298
assign { } { }
assign $0\alu_shift_rot0_sr_op__fn_unit[12:0] \alu_shift_rot0_sr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:185440.3-185441.89"
- process $proc$libresoc.v:185440$12391
+ attribute \src "libresoc.v:183193.3-183194.89"
+ process $proc$libresoc.v:183193$12299
assign { } { }
assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0]
end
- attribute \src "libresoc.v:185442.3-185443.85"
- process $proc$libresoc.v:185442$12392
+ attribute \src "libresoc.v:183195.3-183196.85"
+ process $proc$libresoc.v:183195$12300
assign { } { }
assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0]
end
- attribute \src "libresoc.v:185444.3-185445.73"
- process $proc$libresoc.v:185444$12393
+ attribute \src "libresoc.v:183197.3-183198.73"
+ process $proc$libresoc.v:183197$12301
assign { } { }
assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0]
end
- attribute \src "libresoc.v:185446.3-185447.73"
- process $proc$libresoc.v:185446$12394
+ attribute \src "libresoc.v:183199.3-183200.73"
+ process $proc$libresoc.v:183199$12302
assign { } { }
assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0]
end
- attribute \src "libresoc.v:185448.3-185449.73"
- process $proc$libresoc.v:185448$12395
+ attribute \src "libresoc.v:183201.3-183202.73"
+ process $proc$libresoc.v:183201$12303
assign { } { }
assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0]
end
- attribute \src "libresoc.v:185450.3-185451.73"
- process $proc$libresoc.v:185450$12396
+ attribute \src "libresoc.v:183203.3-183204.73"
+ process $proc$libresoc.v:183203$12304
assign { } { }
assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0]
end
- attribute \src "libresoc.v:185452.3-185453.79"
- process $proc$libresoc.v:185452$12397
+ attribute \src "libresoc.v:183205.3-183206.79"
+ process $proc$libresoc.v:183205$12305
assign { } { }
assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0]
end
- attribute \src "libresoc.v:185454.3-185455.79"
- process $proc$libresoc.v:185454$12398
+ attribute \src "libresoc.v:183207.3-183208.79"
+ process $proc$libresoc.v:183207$12306
assign { } { }
assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0]
end
- attribute \src "libresoc.v:185456.3-185457.83"
- process $proc$libresoc.v:185456$12399
+ attribute \src "libresoc.v:183209.3-183210.83"
+ process $proc$libresoc.v:183209$12307
assign { } { }
assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0]
end
- attribute \src "libresoc.v:185458.3-185459.85"
- process $proc$libresoc.v:185458$12400
+ attribute \src "libresoc.v:183211.3-183212.85"
+ process $proc$libresoc.v:183211$12308
assign { } { }
assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0]
end
- attribute \src "libresoc.v:185460.3-185461.77"
- process $proc$libresoc.v:185460$12401
+ attribute \src "libresoc.v:183213.3-183214.77"
+ process $proc$libresoc.v:183213$12309
assign { } { }
assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0]
end
- attribute \src "libresoc.v:185462.3-185463.79"
- process $proc$libresoc.v:185462$12402
+ attribute \src "libresoc.v:183215.3-183216.79"
+ process $proc$libresoc.v:183215$12310
assign { } { }
assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0]
end
- attribute \src "libresoc.v:185464.3-185465.77"
- process $proc$libresoc.v:185464$12403
+ attribute \src "libresoc.v:183217.3-183218.77"
+ process $proc$libresoc.v:183217$12311
assign { } { }
assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:185466.3-185467.79"
- process $proc$libresoc.v:185466$12404
+ attribute \src "libresoc.v:183219.3-183220.79"
+ process $proc$libresoc.v:183219$12312
assign { } { }
assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0]
end
- attribute \src "libresoc.v:185468.3-185469.69"
- process $proc$libresoc.v:185468$12405
+ attribute \src "libresoc.v:183221.3-183222.69"
+ process $proc$libresoc.v:183221$12313
assign { } { }
assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next
sync posedge \coresync_clk
update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0]
end
- attribute \src "libresoc.v:185470.3-185471.39"
- process $proc$libresoc.v:185470$12406
+ attribute \src "libresoc.v:183223.3-183224.39"
+ process $proc$libresoc.v:183223$12314
assign { } { }
assign $0\req_l_r_req[2:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[2:0]
end
- attribute \src "libresoc.v:185472.3-185473.39"
- process $proc$libresoc.v:185472$12407
+ attribute \src "libresoc.v:183225.3-183226.39"
+ process $proc$libresoc.v:183225$12315
assign { } { }
assign $0\req_l_s_req[2:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[2:0]
end
- attribute \src "libresoc.v:185474.3-185475.39"
- process $proc$libresoc.v:185474$12408
+ attribute \src "libresoc.v:183227.3-183228.39"
+ process $proc$libresoc.v:183227$12316
assign { } { }
assign $0\src_l_r_src[4:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[4:0]
end
- attribute \src "libresoc.v:185476.3-185477.39"
- process $proc$libresoc.v:185476$12409
+ attribute \src "libresoc.v:183229.3-183230.39"
+ process $proc$libresoc.v:183229$12317
assign { } { }
assign $0\src_l_s_src[4:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[4:0]
end
- attribute \src "libresoc.v:185478.3-185479.39"
- process $proc$libresoc.v:185478$12410
+ attribute \src "libresoc.v:183231.3-183232.39"
+ process $proc$libresoc.v:183231$12318
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:185480.3-185481.39"
- process $proc$libresoc.v:185480$12411
+ attribute \src "libresoc.v:183233.3-183234.39"
+ process $proc$libresoc.v:183233$12319
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:185482.3-185483.39"
- process $proc$libresoc.v:185482$12412
+ attribute \src "libresoc.v:183235.3-183236.39"
+ process $proc$libresoc.v:183235$12320
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:185484.3-185485.39"
- process $proc$libresoc.v:185484$12413
+ attribute \src "libresoc.v:183237.3-183238.39"
+ process $proc$libresoc.v:183237$12321
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:185486.3-185487.41"
- process $proc$libresoc.v:185486$12414
+ attribute \src "libresoc.v:183239.3-183240.41"
+ process $proc$libresoc.v:183239$12322
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:185488.3-185489.41"
- process $proc$libresoc.v:185488$12415
+ attribute \src "libresoc.v:183241.3-183242.41"
+ process $proc$libresoc.v:183241$12323
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:185490.3-185491.37"
- process $proc$libresoc.v:185490$12416
+ attribute \src "libresoc.v:183243.3-183244.37"
+ process $proc$libresoc.v:183243$12324
assign { } { }
assign $0\prev_wr_go[2:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[2:0]
end
- attribute \src "libresoc.v:185492.3-185493.46"
- process $proc$libresoc.v:185492$12417
+ attribute \src "libresoc.v:183245.3-183246.46"
+ process $proc$libresoc.v:183245$12325
assign { } { }
assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:185494.3-185495.25"
- process $proc$libresoc.v:185494$12418
+ attribute \src "libresoc.v:183247.3-183248.25"
+ process $proc$libresoc.v:183247$12326
assign { } { }
assign $0\all_rd_dly[0:0] \$10
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:185580.3-185589.6"
- process $proc$libresoc.v:185580$12419
+ attribute \src "libresoc.v:183333.3-183342.6"
+ process $proc$libresoc.v:183333$12327
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:185581.5-185581.29"
+ attribute \src "libresoc.v:183334.5-183334.29"
switch \initial
- attribute \src "libresoc.v:185581.9-185581.17"
+ attribute \src "libresoc.v:183334.9-183334.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:185590.3-185598.6"
- process $proc$libresoc.v:185590$12420
+ attribute \src "libresoc.v:183343.3-183351.6"
+ process $proc$libresoc.v:183343$12328
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$12421 $1\rok_l_s_rdok$next[0:0]$12422
- attribute \src "libresoc.v:185591.5-185591.29"
+ assign $0\rok_l_s_rdok$next[0:0]$12329 $1\rok_l_s_rdok$next[0:0]$12330
+ attribute \src "libresoc.v:183344.5-183344.29"
switch \initial
- attribute \src "libresoc.v:185591.9-185591.17"
+ attribute \src "libresoc.v:183344.9-183344.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$12422 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$12330 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$12422 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$12330 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12421
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12329
end
- attribute \src "libresoc.v:185599.3-185607.6"
- process $proc$libresoc.v:185599$12423
+ attribute \src "libresoc.v:183352.3-183360.6"
+ process $proc$libresoc.v:183352$12331
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$12424 $1\rok_l_r_rdok$next[0:0]$12425
- attribute \src "libresoc.v:185600.5-185600.29"
+ assign $0\rok_l_r_rdok$next[0:0]$12332 $1\rok_l_r_rdok$next[0:0]$12333
+ attribute \src "libresoc.v:183353.5-183353.29"
switch \initial
- attribute \src "libresoc.v:185600.9-185600.17"
+ attribute \src "libresoc.v:183353.9-183353.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$12425 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$12333 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$12425 \$64
+ assign $1\rok_l_r_rdok$next[0:0]$12333 \$64
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12424
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12332
end
- attribute \src "libresoc.v:185608.3-185616.6"
- process $proc$libresoc.v:185608$12426
+ attribute \src "libresoc.v:183361.3-183369.6"
+ process $proc$libresoc.v:183361$12334
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$12427 $1\rst_l_s_rst$next[0:0]$12428
- attribute \src "libresoc.v:185609.5-185609.29"
+ assign $0\rst_l_s_rst$next[0:0]$12335 $1\rst_l_s_rst$next[0:0]$12336
+ attribute \src "libresoc.v:183362.5-183362.29"
switch \initial
- attribute \src "libresoc.v:185609.9-185609.17"
+ attribute \src "libresoc.v:183362.9-183362.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$12428 1'0
+ assign $1\rst_l_s_rst$next[0:0]$12336 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$12428 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$12336 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12427
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12335
end
- attribute \src "libresoc.v:185617.3-185625.6"
- process $proc$libresoc.v:185617$12429
+ attribute \src "libresoc.v:183370.3-183378.6"
+ process $proc$libresoc.v:183370$12337
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$12430 $1\rst_l_r_rst$next[0:0]$12431
- attribute \src "libresoc.v:185618.5-185618.29"
+ assign $0\rst_l_r_rst$next[0:0]$12338 $1\rst_l_r_rst$next[0:0]$12339
+ attribute \src "libresoc.v:183371.5-183371.29"
switch \initial
- attribute \src "libresoc.v:185618.9-185618.17"
+ attribute \src "libresoc.v:183371.9-183371.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$12431 1'1
+ assign $1\rst_l_r_rst$next[0:0]$12339 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$12431 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$12339 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12430
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12338
end
- attribute \src "libresoc.v:185626.3-185634.6"
- process $proc$libresoc.v:185626$12432
+ attribute \src "libresoc.v:183379.3-183387.6"
+ process $proc$libresoc.v:183379$12340
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$12433 $1\opc_l_s_opc$next[0:0]$12434
- attribute \src "libresoc.v:185627.5-185627.29"
+ assign $0\opc_l_s_opc$next[0:0]$12341 $1\opc_l_s_opc$next[0:0]$12342
+ attribute \src "libresoc.v:183380.5-183380.29"
switch \initial
- attribute \src "libresoc.v:185627.9-185627.17"
+ attribute \src "libresoc.v:183380.9-183380.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$12434 1'0
+ assign $1\opc_l_s_opc$next[0:0]$12342 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$12434 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$12342 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12433
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12341
end
- attribute \src "libresoc.v:185635.3-185643.6"
- process $proc$libresoc.v:185635$12435
+ attribute \src "libresoc.v:183388.3-183396.6"
+ process $proc$libresoc.v:183388$12343
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$12436 $1\opc_l_r_opc$next[0:0]$12437
- attribute \src "libresoc.v:185636.5-185636.29"
+ assign $0\opc_l_r_opc$next[0:0]$12344 $1\opc_l_r_opc$next[0:0]$12345
+ attribute \src "libresoc.v:183389.5-183389.29"
switch \initial
- attribute \src "libresoc.v:185636.9-185636.17"
+ attribute \src "libresoc.v:183389.9-183389.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$12437 1'1
+ assign $1\opc_l_r_opc$next[0:0]$12345 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$12437 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$12345 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12436
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12344
end
- attribute \src "libresoc.v:185644.3-185652.6"
- process $proc$libresoc.v:185644$12438
+ attribute \src "libresoc.v:183397.3-183405.6"
+ process $proc$libresoc.v:183397$12346
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[4:0]$12439 $1\src_l_s_src$next[4:0]$12440
- attribute \src "libresoc.v:185645.5-185645.29"
+ assign $0\src_l_s_src$next[4:0]$12347 $1\src_l_s_src$next[4:0]$12348
+ attribute \src "libresoc.v:183398.5-183398.29"
switch \initial
- attribute \src "libresoc.v:185645.9-185645.17"
+ attribute \src "libresoc.v:183398.9-183398.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[4:0]$12440 5'00000
+ assign $1\src_l_s_src$next[4:0]$12348 5'00000
case
- assign $1\src_l_s_src$next[4:0]$12440 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[4:0]$12348 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12439
+ update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12347
end
- attribute \src "libresoc.v:185653.3-185661.6"
- process $proc$libresoc.v:185653$12441
+ attribute \src "libresoc.v:183406.3-183414.6"
+ process $proc$libresoc.v:183406$12349
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[4:0]$12442 $1\src_l_r_src$next[4:0]$12443
- attribute \src "libresoc.v:185654.5-185654.29"
+ assign $0\src_l_r_src$next[4:0]$12350 $1\src_l_r_src$next[4:0]$12351
+ attribute \src "libresoc.v:183407.5-183407.29"
switch \initial
- attribute \src "libresoc.v:185654.9-185654.17"
+ attribute \src "libresoc.v:183407.9-183407.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[4:0]$12443 5'11111
+ assign $1\src_l_r_src$next[4:0]$12351 5'11111
case
- assign $1\src_l_r_src$next[4:0]$12443 \reset_r
+ assign $1\src_l_r_src$next[4:0]$12351 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12442
+ update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12350
end
- attribute \src "libresoc.v:185662.3-185670.6"
- process $proc$libresoc.v:185662$12444
+ attribute \src "libresoc.v:183415.3-183423.6"
+ process $proc$libresoc.v:183415$12352
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[2:0]$12445 $1\req_l_s_req$next[2:0]$12446
- attribute \src "libresoc.v:185663.5-185663.29"
+ assign $0\req_l_s_req$next[2:0]$12353 $1\req_l_s_req$next[2:0]$12354
+ attribute \src "libresoc.v:183416.5-183416.29"
switch \initial
- attribute \src "libresoc.v:185663.9-185663.17"
+ attribute \src "libresoc.v:183416.9-183416.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[2:0]$12446 3'000
+ assign $1\req_l_s_req$next[2:0]$12354 3'000
case
- assign $1\req_l_s_req$next[2:0]$12446 \$66
+ assign $1\req_l_s_req$next[2:0]$12354 \$66
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12445
+ update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12353
end
- attribute \src "libresoc.v:185671.3-185679.6"
- process $proc$libresoc.v:185671$12447
+ attribute \src "libresoc.v:183424.3-183432.6"
+ process $proc$libresoc.v:183424$12355
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[2:0]$12448 $1\req_l_r_req$next[2:0]$12449
- attribute \src "libresoc.v:185672.5-185672.29"
+ assign $0\req_l_r_req$next[2:0]$12356 $1\req_l_r_req$next[2:0]$12357
+ attribute \src "libresoc.v:183425.5-183425.29"
switch \initial
- attribute \src "libresoc.v:185672.9-185672.17"
+ attribute \src "libresoc.v:183425.9-183425.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[2:0]$12449 3'111
+ assign $1\req_l_r_req$next[2:0]$12357 3'111
case
- assign $1\req_l_r_req$next[2:0]$12449 \$68
+ assign $1\req_l_r_req$next[2:0]$12357 \$68
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12448
+ update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12356
end
- attribute \src "libresoc.v:185680.3-185717.6"
- process $proc$libresoc.v:185680$12450
+ attribute \src "libresoc.v:183433.3-183470.6"
+ process $proc$libresoc.v:183433$12358
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468
+ assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471
- assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472
- assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473
- assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474
- assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475
- assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476
- assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477
+ assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379
+ assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380
+ assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381
+ assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382
+ assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383
+ assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384
+ assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480
- assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481
+ assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388
+ assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389
assign { } { }
assign { } { }
- assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484
- assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485
- assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486
- assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487
- assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488
- assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489
- assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490
- attribute \src "libresoc.v:185681.5-185681.29"
+ assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392
+ assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393
+ assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394
+ assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395
+ assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396
+ assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397
+ assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398
+ attribute \src "libresoc.v:183434.5-183434.29"
switch \initial
- attribute \src "libresoc.v:185681.9-185681.17"
+ attribute \src "libresoc.v:183434.9-183434.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
+ assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
case
- assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 \alu_shift_rot0_sr_op__fn_unit
- assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 \alu_shift_rot0_sr_op__imm_data__data
- assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 \alu_shift_rot0_sr_op__imm_data__ok
- assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 \alu_shift_rot0_sr_op__input_carry
- assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 \alu_shift_rot0_sr_op__input_cr
- assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 \alu_shift_rot0_sr_op__insn
- assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 \alu_shift_rot0_sr_op__insn_type
- assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 \alu_shift_rot0_sr_op__invert_in
- assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 \alu_shift_rot0_sr_op__is_32bit
- assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 \alu_shift_rot0_sr_op__is_signed
- assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 \alu_shift_rot0_sr_op__oe__oe
- assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 \alu_shift_rot0_sr_op__oe__ok
- assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 \alu_shift_rot0_sr_op__output_carry
- assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 \alu_shift_rot0_sr_op__output_cr
- assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 \alu_shift_rot0_sr_op__rc__ok
- assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 \alu_shift_rot0_sr_op__rc__rc
- assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 \alu_shift_rot0_sr_op__write_cr0
+ assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 \alu_shift_rot0_sr_op__fn_unit
+ assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 \alu_shift_rot0_sr_op__imm_data__data
+ assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 \alu_shift_rot0_sr_op__imm_data__ok
+ assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 \alu_shift_rot0_sr_op__input_carry
+ assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 \alu_shift_rot0_sr_op__input_cr
+ assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 \alu_shift_rot0_sr_op__insn
+ assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 \alu_shift_rot0_sr_op__insn_type
+ assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 \alu_shift_rot0_sr_op__invert_in
+ assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 \alu_shift_rot0_sr_op__is_32bit
+ assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 \alu_shift_rot0_sr_op__is_signed
+ assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 \alu_shift_rot0_sr_op__oe__oe
+ assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 \alu_shift_rot0_sr_op__oe__ok
+ assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 \alu_shift_rot0_sr_op__output_carry
+ assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 \alu_shift_rot0_sr_op__output_cr
+ assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 \alu_shift_rot0_sr_op__rc__ok
+ assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 \alu_shift_rot0_sr_op__rc__rc
+ assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 \alu_shift_rot0_sr_op__write_cr0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
assign { } { }
assign { } { }
assign { } { }
- assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 1'0
- assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 1'0
- assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 1'0
- assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 1'0
- assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 1'0
+ assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 1'0
+ assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 1'0
+ assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 1'0
+ assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 1'0
+ assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 1'0
case
- assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469
- assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470
- assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478
- assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479
- assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482
- assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483
+ assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377
+ assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378
+ assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386
+ assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387
+ assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390
+ assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391
end
sync always
- update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451
- update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452
- update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453
- update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454
- update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455
- update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456
- update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457
- update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458
- update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459
- update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460
- update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461
- update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462
- update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463
- update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464
- update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465
- update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466
- update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467
+ update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359
+ update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360
+ update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361
+ update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362
+ update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363
+ update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364
+ update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365
+ update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366
+ update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367
+ update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368
+ update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369
+ update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370
+ update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371
+ update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372
+ update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373
+ update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374
+ update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375
end
- attribute \src "libresoc.v:185718.3-185739.6"
- process $proc$libresoc.v:185718$12491
+ attribute \src "libresoc.v:183471.3-183492.6"
+ process $proc$libresoc.v:183471$12399
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$12492 $2\data_r0__o$next[63:0]$12496
+ assign $0\data_r0__o$next[63:0]$12400 $2\data_r0__o$next[63:0]$12404
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$12493 $3\data_r0__o_ok$next[0:0]$12498
- attribute \src "libresoc.v:185719.5-185719.29"
+ assign $0\data_r0__o_ok$next[0:0]$12401 $3\data_r0__o_ok$next[0:0]$12406
+ attribute \src "libresoc.v:183472.5-183472.29"
switch \initial
- attribute \src "libresoc.v:185719.9-185719.17"
+ attribute \src "libresoc.v:183472.9-183472.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$12495 $1\data_r0__o$next[63:0]$12494 } { \o_ok \alu_shift_rot0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$12403 $1\data_r0__o$next[63:0]$12402 } { \o_ok \alu_shift_rot0_o }
case
- assign $1\data_r0__o$next[63:0]$12494 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$12495 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$12402 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$12403 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$12497 $2\data_r0__o$next[63:0]$12496 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$12405 $2\data_r0__o$next[63:0]$12404 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$12496 $1\data_r0__o$next[63:0]$12494
- assign $2\data_r0__o_ok$next[0:0]$12497 $1\data_r0__o_ok$next[0:0]$12495
+ assign $2\data_r0__o$next[63:0]$12404 $1\data_r0__o$next[63:0]$12402
+ assign $2\data_r0__o_ok$next[0:0]$12405 $1\data_r0__o_ok$next[0:0]$12403
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$12498 1'0
+ assign $3\data_r0__o_ok$next[0:0]$12406 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$12498 $2\data_r0__o_ok$next[0:0]$12497
+ assign $3\data_r0__o_ok$next[0:0]$12406 $2\data_r0__o_ok$next[0:0]$12405
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$12492
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12493
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$12400
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12401
end
- attribute \src "libresoc.v:185740.3-185761.6"
- process $proc$libresoc.v:185740$12499
+ attribute \src "libresoc.v:183493.3-183514.6"
+ process $proc$libresoc.v:183493$12407
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__cr_a$next[3:0]$12500 $2\data_r1__cr_a$next[3:0]$12504
+ assign $0\data_r1__cr_a$next[3:0]$12408 $2\data_r1__cr_a$next[3:0]$12412
assign { } { }
- assign $0\data_r1__cr_a_ok$next[0:0]$12501 $3\data_r1__cr_a_ok$next[0:0]$12506
- attribute \src "libresoc.v:185741.5-185741.29"
+ assign $0\data_r1__cr_a_ok$next[0:0]$12409 $3\data_r1__cr_a_ok$next[0:0]$12414
+ attribute \src "libresoc.v:183494.5-183494.29"
switch \initial
- attribute \src "libresoc.v:185741.9-185741.17"
+ attribute \src "libresoc.v:183494.9-183494.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__cr_a_ok$next[0:0]$12503 $1\data_r1__cr_a$next[3:0]$12502 } { \cr_a_ok \alu_shift_rot0_cr_a }
+ assign { $1\data_r1__cr_a_ok$next[0:0]$12411 $1\data_r1__cr_a$next[3:0]$12410 } { \cr_a_ok \alu_shift_rot0_cr_a }
case
- assign $1\data_r1__cr_a$next[3:0]$12502 \data_r1__cr_a
- assign $1\data_r1__cr_a_ok$next[0:0]$12503 \data_r1__cr_a_ok
+ assign $1\data_r1__cr_a$next[3:0]$12410 \data_r1__cr_a
+ assign $1\data_r1__cr_a_ok$next[0:0]$12411 \data_r1__cr_a_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__cr_a_ok$next[0:0]$12505 $2\data_r1__cr_a$next[3:0]$12504 } 5'00000
+ assign { $2\data_r1__cr_a_ok$next[0:0]$12413 $2\data_r1__cr_a$next[3:0]$12412 } 5'00000
case
- assign $2\data_r1__cr_a$next[3:0]$12504 $1\data_r1__cr_a$next[3:0]$12502
- assign $2\data_r1__cr_a_ok$next[0:0]$12505 $1\data_r1__cr_a_ok$next[0:0]$12503
+ assign $2\data_r1__cr_a$next[3:0]$12412 $1\data_r1__cr_a$next[3:0]$12410
+ assign $2\data_r1__cr_a_ok$next[0:0]$12413 $1\data_r1__cr_a_ok$next[0:0]$12411
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__cr_a_ok$next[0:0]$12506 1'0
+ assign $3\data_r1__cr_a_ok$next[0:0]$12414 1'0
case
- assign $3\data_r1__cr_a_ok$next[0:0]$12506 $2\data_r1__cr_a_ok$next[0:0]$12505
+ assign $3\data_r1__cr_a_ok$next[0:0]$12414 $2\data_r1__cr_a_ok$next[0:0]$12413
end
sync always
- update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12500
- update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12501
+ update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12408
+ update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12409
end
- attribute \src "libresoc.v:185762.3-185783.6"
- process $proc$libresoc.v:185762$12507
+ attribute \src "libresoc.v:183515.3-183536.6"
+ process $proc$libresoc.v:183515$12415
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__xer_ca$next[1:0]$12508 $2\data_r2__xer_ca$next[1:0]$12512
+ assign $0\data_r2__xer_ca$next[1:0]$12416 $2\data_r2__xer_ca$next[1:0]$12420
assign { } { }
- assign $0\data_r2__xer_ca_ok$next[0:0]$12509 $3\data_r2__xer_ca_ok$next[0:0]$12514
- attribute \src "libresoc.v:185763.5-185763.29"
+ assign $0\data_r2__xer_ca_ok$next[0:0]$12417 $3\data_r2__xer_ca_ok$next[0:0]$12422
+ attribute \src "libresoc.v:183516.5-183516.29"
switch \initial
- attribute \src "libresoc.v:185763.9-185763.17"
+ attribute \src "libresoc.v:183516.9-183516.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__xer_ca_ok$next[0:0]$12511 $1\data_r2__xer_ca$next[1:0]$12510 } { \xer_ca_ok \alu_shift_rot0_xer_ca }
+ assign { $1\data_r2__xer_ca_ok$next[0:0]$12419 $1\data_r2__xer_ca$next[1:0]$12418 } { \xer_ca_ok \alu_shift_rot0_xer_ca }
case
- assign $1\data_r2__xer_ca$next[1:0]$12510 \data_r2__xer_ca
- assign $1\data_r2__xer_ca_ok$next[0:0]$12511 \data_r2__xer_ca_ok
+ assign $1\data_r2__xer_ca$next[1:0]$12418 \data_r2__xer_ca
+ assign $1\data_r2__xer_ca_ok$next[0:0]$12419 \data_r2__xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__xer_ca_ok$next[0:0]$12513 $2\data_r2__xer_ca$next[1:0]$12512 } 3'000
+ assign { $2\data_r2__xer_ca_ok$next[0:0]$12421 $2\data_r2__xer_ca$next[1:0]$12420 } 3'000
case
- assign $2\data_r2__xer_ca$next[1:0]$12512 $1\data_r2__xer_ca$next[1:0]$12510
- assign $2\data_r2__xer_ca_ok$next[0:0]$12513 $1\data_r2__xer_ca_ok$next[0:0]$12511
+ assign $2\data_r2__xer_ca$next[1:0]$12420 $1\data_r2__xer_ca$next[1:0]$12418
+ assign $2\data_r2__xer_ca_ok$next[0:0]$12421 $1\data_r2__xer_ca_ok$next[0:0]$12419
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__xer_ca_ok$next[0:0]$12514 1'0
+ assign $3\data_r2__xer_ca_ok$next[0:0]$12422 1'0
case
- assign $3\data_r2__xer_ca_ok$next[0:0]$12514 $2\data_r2__xer_ca_ok$next[0:0]$12513
+ assign $3\data_r2__xer_ca_ok$next[0:0]$12422 $2\data_r2__xer_ca_ok$next[0:0]$12421
end
sync always
- update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12508
- update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12509
+ update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12416
+ update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12417
end
- attribute \src "libresoc.v:185784.3-185793.6"
- process $proc$libresoc.v:185784$12515
+ attribute \src "libresoc.v:183537.3-183546.6"
+ process $proc$libresoc.v:183537$12423
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$12516 $1\src_r0$next[63:0]$12517
- attribute \src "libresoc.v:185785.5-185785.29"
+ assign $0\src_r0$next[63:0]$12424 $1\src_r0$next[63:0]$12425
+ attribute \src "libresoc.v:183538.5-183538.29"
switch \initial
- attribute \src "libresoc.v:185785.9-185785.17"
+ attribute \src "libresoc.v:183538.9-183538.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$12517 \src1_i
+ assign $1\src_r0$next[63:0]$12425 \src1_i
case
- assign $1\src_r0$next[63:0]$12517 \src_r0
+ assign $1\src_r0$next[63:0]$12425 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$12516
+ update \src_r0$next $0\src_r0$next[63:0]$12424
end
- attribute \src "libresoc.v:185794.3-185803.6"
- process $proc$libresoc.v:185794$12518
+ attribute \src "libresoc.v:183547.3-183556.6"
+ process $proc$libresoc.v:183547$12426
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$12519 $1\src_r1$next[63:0]$12520
- attribute \src "libresoc.v:185795.5-185795.29"
+ assign $0\src_r1$next[63:0]$12427 $1\src_r1$next[63:0]$12428
+ attribute \src "libresoc.v:183548.5-183548.29"
switch \initial
- attribute \src "libresoc.v:185795.9-185795.17"
+ attribute \src "libresoc.v:183548.9-183548.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$12520 \src_or_imm
+ assign $1\src_r1$next[63:0]$12428 \src_or_imm
case
- assign $1\src_r1$next[63:0]$12520 \src_r1
+ assign $1\src_r1$next[63:0]$12428 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$12519
+ update \src_r1$next $0\src_r1$next[63:0]$12427
end
- attribute \src "libresoc.v:185804.3-185813.6"
- process $proc$libresoc.v:185804$12521
+ attribute \src "libresoc.v:183557.3-183566.6"
+ process $proc$libresoc.v:183557$12429
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$12522 $1\src_r2$next[63:0]$12523
- attribute \src "libresoc.v:185805.5-185805.29"
+ assign $0\src_r2$next[63:0]$12430 $1\src_r2$next[63:0]$12431
+ attribute \src "libresoc.v:183558.5-183558.29"
switch \initial
- attribute \src "libresoc.v:185805.9-185805.17"
+ attribute \src "libresoc.v:183558.9-183558.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$12523 \src3_i
+ assign $1\src_r2$next[63:0]$12431 \src3_i
case
- assign $1\src_r2$next[63:0]$12523 \src_r2
+ assign $1\src_r2$next[63:0]$12431 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$12522
+ update \src_r2$next $0\src_r2$next[63:0]$12430
end
- attribute \src "libresoc.v:185814.3-185823.6"
- process $proc$libresoc.v:185814$12524
+ attribute \src "libresoc.v:183567.3-183576.6"
+ process $proc$libresoc.v:183567$12432
assign { } { }
assign { } { }
- assign $0\src_r3$next[0:0]$12525 $1\src_r3$next[0:0]$12526
- attribute \src "libresoc.v:185815.5-185815.29"
+ assign $0\src_r3$next[0:0]$12433 $1\src_r3$next[0:0]$12434
+ attribute \src "libresoc.v:183568.5-183568.29"
switch \initial
- attribute \src "libresoc.v:185815.9-185815.17"
+ attribute \src "libresoc.v:183568.9-183568.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[0:0]$12526 \src4_i
+ assign $1\src_r3$next[0:0]$12434 \src4_i
case
- assign $1\src_r3$next[0:0]$12526 \src_r3
+ assign $1\src_r3$next[0:0]$12434 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[0:0]$12525
+ update \src_r3$next $0\src_r3$next[0:0]$12433
end
- attribute \src "libresoc.v:185824.3-185833.6"
- process $proc$libresoc.v:185824$12527
+ attribute \src "libresoc.v:183577.3-183586.6"
+ process $proc$libresoc.v:183577$12435
assign { } { }
assign { } { }
- assign $0\src_r4$next[1:0]$12528 $1\src_r4$next[1:0]$12529
- attribute \src "libresoc.v:185825.5-185825.29"
+ assign $0\src_r4$next[1:0]$12436 $1\src_r4$next[1:0]$12437
+ attribute \src "libresoc.v:183578.5-183578.29"
switch \initial
- attribute \src "libresoc.v:185825.9-185825.17"
+ attribute \src "libresoc.v:183578.9-183578.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[1:0]$12529 \src5_i
+ assign $1\src_r4$next[1:0]$12437 \src5_i
case
- assign $1\src_r4$next[1:0]$12529 \src_r4
+ assign $1\src_r4$next[1:0]$12437 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[1:0]$12528
+ update \src_r4$next $0\src_r4$next[1:0]$12436
end
- attribute \src "libresoc.v:185834.3-185842.6"
- process $proc$libresoc.v:185834$12530
+ attribute \src "libresoc.v:183587.3-183595.6"
+ process $proc$libresoc.v:183587$12438
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$12531 $1\alui_l_r_alui$next[0:0]$12532
- attribute \src "libresoc.v:185835.5-185835.29"
+ assign $0\alui_l_r_alui$next[0:0]$12439 $1\alui_l_r_alui$next[0:0]$12440
+ attribute \src "libresoc.v:183588.5-183588.29"
switch \initial
- attribute \src "libresoc.v:185835.9-185835.17"
+ attribute \src "libresoc.v:183588.9-183588.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$12532 1'1
+ assign $1\alui_l_r_alui$next[0:0]$12440 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$12532 \$90
+ assign $1\alui_l_r_alui$next[0:0]$12440 \$90
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12531
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12439
end
- attribute \src "libresoc.v:185843.3-185851.6"
- process $proc$libresoc.v:185843$12533
+ attribute \src "libresoc.v:183596.3-183604.6"
+ process $proc$libresoc.v:183596$12441
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$12534 $1\alu_l_r_alu$next[0:0]$12535
- attribute \src "libresoc.v:185844.5-185844.29"
+ assign $0\alu_l_r_alu$next[0:0]$12442 $1\alu_l_r_alu$next[0:0]$12443
+ attribute \src "libresoc.v:183597.5-183597.29"
switch \initial
- attribute \src "libresoc.v:185844.9-185844.17"
+ attribute \src "libresoc.v:183597.9-183597.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$12535 1'1
+ assign $1\alu_l_r_alu$next[0:0]$12443 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$12535 \$92
+ assign $1\alu_l_r_alu$next[0:0]$12443 \$92
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12534
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12442
end
- attribute \src "libresoc.v:185852.3-185861.6"
- process $proc$libresoc.v:185852$12536
+ attribute \src "libresoc.v:183605.3-183614.6"
+ process $proc$libresoc.v:183605$12444
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:185853.5-185853.29"
+ attribute \src "libresoc.v:183606.5-183606.29"
switch \initial
- attribute \src "libresoc.v:185853.9-185853.17"
+ attribute \src "libresoc.v:183606.9-183606.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:185862.3-185871.6"
- process $proc$libresoc.v:185862$12537
+ attribute \src "libresoc.v:183615.3-183624.6"
+ process $proc$libresoc.v:183615$12445
assign { } { }
assign { } { }
assign $0\dest2_o[3:0] $1\dest2_o[3:0]
- attribute \src "libresoc.v:185863.5-185863.29"
+ attribute \src "libresoc.v:183616.5-183616.29"
switch \initial
- attribute \src "libresoc.v:185863.9-185863.17"
+ attribute \src "libresoc.v:183616.9-183616.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[3:0]
end
- attribute \src "libresoc.v:185872.3-185881.6"
- process $proc$libresoc.v:185872$12538
+ attribute \src "libresoc.v:183625.3-183634.6"
+ process $proc$libresoc.v:183625$12446
assign { } { }
assign { } { }
assign $0\dest3_o[1:0] $1\dest3_o[1:0]
- attribute \src "libresoc.v:185873.5-185873.29"
+ attribute \src "libresoc.v:183626.5-183626.29"
switch \initial
- attribute \src "libresoc.v:185873.9-185873.17"
+ attribute \src "libresoc.v:183626.9-183626.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[1:0]
end
- attribute \src "libresoc.v:185882.3-185890.6"
- process $proc$libresoc.v:185882$12539
+ attribute \src "libresoc.v:183635.3-183643.6"
+ process $proc$libresoc.v:183635$12447
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[2:0]$12540 $1\prev_wr_go$next[2:0]$12541
- attribute \src "libresoc.v:185883.5-185883.29"
+ assign $0\prev_wr_go$next[2:0]$12448 $1\prev_wr_go$next[2:0]$12449
+ attribute \src "libresoc.v:183636.5-183636.29"
switch \initial
- attribute \src "libresoc.v:185883.9-185883.17"
+ attribute \src "libresoc.v:183636.9-183636.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[2:0]$12541 3'000
- case
- assign $1\prev_wr_go$next[2:0]$12541 \$20
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12540
- end
- connect \$100 $not$libresoc.v:185351$12317_Y
- connect \$102 $and$libresoc.v:185352$12318_Y
- connect \$104 $and$libresoc.v:185353$12319_Y
- connect \$106 $and$libresoc.v:185354$12320_Y
- connect \$108 $and$libresoc.v:185355$12321_Y
- connect \$10 $and$libresoc.v:185356$12322_Y
- connect \$110 $and$libresoc.v:185357$12323_Y
- connect \$112 $and$libresoc.v:185358$12324_Y
- connect \$114 $and$libresoc.v:185359$12325_Y
- connect \$116 $and$libresoc.v:185360$12326_Y
- connect \$118 $and$libresoc.v:185361$12327_Y
- connect \$12 $not$libresoc.v:185362$12328_Y
- connect \$14 $and$libresoc.v:185363$12329_Y
- connect \$16 $not$libresoc.v:185364$12330_Y
- connect \$18 $and$libresoc.v:185365$12331_Y
- connect \$20 $and$libresoc.v:185366$12332_Y
- connect \$24 $not$libresoc.v:185367$12333_Y
- connect \$26 $and$libresoc.v:185368$12334_Y
- connect \$23 $reduce_or$libresoc.v:185369$12335_Y
- connect \$22 $not$libresoc.v:185370$12336_Y
- connect \$2 $and$libresoc.v:185371$12337_Y
- connect \$30 $and$libresoc.v:185372$12338_Y
- connect \$32 $reduce_or$libresoc.v:185373$12339_Y
- connect \$34 $reduce_or$libresoc.v:185374$12340_Y
- connect \$36 $or$libresoc.v:185375$12341_Y
- connect \$38 $not$libresoc.v:185376$12342_Y
- connect \$40 $and$libresoc.v:185377$12343_Y
- connect \$42 $and$libresoc.v:185378$12344_Y
- connect \$44 $eq$libresoc.v:185379$12345_Y
- connect \$46 $and$libresoc.v:185380$12346_Y
- connect \$48 $eq$libresoc.v:185381$12347_Y
- connect \$50 $and$libresoc.v:185382$12348_Y
- connect \$52 $and$libresoc.v:185383$12349_Y
- connect \$54 $and$libresoc.v:185384$12350_Y
- connect \$56 $or$libresoc.v:185385$12351_Y
- connect \$58 $or$libresoc.v:185386$12352_Y
- connect \$5 $not$libresoc.v:185387$12353_Y
- connect \$60 $or$libresoc.v:185388$12354_Y
- connect \$62 $or$libresoc.v:185389$12355_Y
- connect \$64 $and$libresoc.v:185390$12356_Y
- connect \$66 $and$libresoc.v:185391$12357_Y
- connect \$68 $or$libresoc.v:185392$12358_Y
- connect \$70 $and$libresoc.v:185393$12359_Y
- connect \$72 $and$libresoc.v:185394$12360_Y
- connect \$74 $and$libresoc.v:185395$12361_Y
- connect \$76 $ternary$libresoc.v:185396$12362_Y
- connect \$78 $ternary$libresoc.v:185397$12363_Y
- connect \$7 $or$libresoc.v:185398$12364_Y
- connect \$80 $ternary$libresoc.v:185399$12365_Y
- connect \$82 $ternary$libresoc.v:185400$12366_Y
- connect \$84 $ternary$libresoc.v:185401$12367_Y
- connect \$86 $ternary$libresoc.v:185402$12368_Y
- connect \$88 $ternary$libresoc.v:185403$12369_Y
- connect \$4 $reduce_and$libresoc.v:185404$12370_Y
- connect \$90 $and$libresoc.v:185405$12371_Y
- connect \$92 $and$libresoc.v:185406$12372_Y
- connect \$94 $and$libresoc.v:185407$12373_Y
- connect \$96 $not$libresoc.v:185408$12374_Y
- connect \$98 $and$libresoc.v:185409$12375_Y
+ assign $1\prev_wr_go$next[2:0]$12449 3'000
+ case
+ assign $1\prev_wr_go$next[2:0]$12449 \$20
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12448
+ end
+ connect \$100 $not$libresoc.v:183104$12225_Y
+ connect \$102 $and$libresoc.v:183105$12226_Y
+ connect \$104 $and$libresoc.v:183106$12227_Y
+ connect \$106 $and$libresoc.v:183107$12228_Y
+ connect \$108 $and$libresoc.v:183108$12229_Y
+ connect \$10 $and$libresoc.v:183109$12230_Y
+ connect \$110 $and$libresoc.v:183110$12231_Y
+ connect \$112 $and$libresoc.v:183111$12232_Y
+ connect \$114 $and$libresoc.v:183112$12233_Y
+ connect \$116 $and$libresoc.v:183113$12234_Y
+ connect \$118 $and$libresoc.v:183114$12235_Y
+ connect \$12 $not$libresoc.v:183115$12236_Y
+ connect \$14 $and$libresoc.v:183116$12237_Y
+ connect \$16 $not$libresoc.v:183117$12238_Y
+ connect \$18 $and$libresoc.v:183118$12239_Y
+ connect \$20 $and$libresoc.v:183119$12240_Y
+ connect \$24 $not$libresoc.v:183120$12241_Y
+ connect \$26 $and$libresoc.v:183121$12242_Y
+ connect \$23 $reduce_or$libresoc.v:183122$12243_Y
+ connect \$22 $not$libresoc.v:183123$12244_Y
+ connect \$2 $and$libresoc.v:183124$12245_Y
+ connect \$30 $and$libresoc.v:183125$12246_Y
+ connect \$32 $reduce_or$libresoc.v:183126$12247_Y
+ connect \$34 $reduce_or$libresoc.v:183127$12248_Y
+ connect \$36 $or$libresoc.v:183128$12249_Y
+ connect \$38 $not$libresoc.v:183129$12250_Y
+ connect \$40 $and$libresoc.v:183130$12251_Y
+ connect \$42 $and$libresoc.v:183131$12252_Y
+ connect \$44 $eq$libresoc.v:183132$12253_Y
+ connect \$46 $and$libresoc.v:183133$12254_Y
+ connect \$48 $eq$libresoc.v:183134$12255_Y
+ connect \$50 $and$libresoc.v:183135$12256_Y
+ connect \$52 $and$libresoc.v:183136$12257_Y
+ connect \$54 $and$libresoc.v:183137$12258_Y
+ connect \$56 $or$libresoc.v:183138$12259_Y
+ connect \$58 $or$libresoc.v:183139$12260_Y
+ connect \$5 $not$libresoc.v:183140$12261_Y
+ connect \$60 $or$libresoc.v:183141$12262_Y
+ connect \$62 $or$libresoc.v:183142$12263_Y
+ connect \$64 $and$libresoc.v:183143$12264_Y
+ connect \$66 $and$libresoc.v:183144$12265_Y
+ connect \$68 $or$libresoc.v:183145$12266_Y
+ connect \$70 $and$libresoc.v:183146$12267_Y
+ connect \$72 $and$libresoc.v:183147$12268_Y
+ connect \$74 $and$libresoc.v:183148$12269_Y
+ connect \$76 $ternary$libresoc.v:183149$12270_Y
+ connect \$78 $ternary$libresoc.v:183150$12271_Y
+ connect \$7 $or$libresoc.v:183151$12272_Y
+ connect \$80 $ternary$libresoc.v:183152$12273_Y
+ connect \$82 $ternary$libresoc.v:183153$12274_Y
+ connect \$84 $ternary$libresoc.v:183154$12275_Y
+ connect \$86 $ternary$libresoc.v:183155$12276_Y
+ connect \$88 $ternary$libresoc.v:183156$12277_Y
+ connect \$4 $reduce_and$libresoc.v:183157$12278_Y
+ connect \$90 $and$libresoc.v:183158$12279_Y
+ connect \$92 $and$libresoc.v:183159$12280_Y
+ connect \$94 $and$libresoc.v:183160$12281_Y
+ connect \$96 $not$libresoc.v:183161$12282_Y
+ connect \$98 $and$libresoc.v:183162$12283_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$112
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:185927.1-186107.10"
+attribute \src "libresoc.v:183680.1-183860.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.spr"
attribute \generator "nMigen"
module \spr
- attribute \src "libresoc.v:186079.3-186082.6"
- wire width 7 $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702
- attribute \src "libresoc.v:186079.3-186082.6"
- wire width 64 $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703
- attribute \src "libresoc.v:186079.3-186082.6"
- wire width 64 $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704
- attribute \src "libresoc.v:186079.3-186082.6"
+ attribute \src "libresoc.v:183832.3-183835.6"
+ wire width 7 $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610
+ attribute \src "libresoc.v:183832.3-183835.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611
+ attribute \src "libresoc.v:183832.3-183835.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612
+ attribute \src "libresoc.v:183832.3-183835.6"
wire width 7 $0\_0_[6:0]
- attribute \src "libresoc.v:185928.7-185928.20"
+ attribute \src "libresoc.v:183681.7-183681.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186084.3-186092.6"
- wire $0\ren_delay$next[0:0]$12707
- attribute \src "libresoc.v:185960.3-185961.35"
+ attribute \src "libresoc.v:183837.3-183845.6"
+ wire $0\ren_delay$next[0:0]$12615
+ attribute \src "libresoc.v:183713.3-183714.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:186093.3-186102.6"
+ attribute \src "libresoc.v:183846.3-183855.6"
wire width 64 $0\spr1__data_o[63:0]
- attribute \src "libresoc.v:186084.3-186092.6"
- wire $1\ren_delay$next[0:0]$12708
- attribute \src "libresoc.v:185944.7-185944.23"
+ attribute \src "libresoc.v:183837.3-183845.6"
+ wire $1\ren_delay$next[0:0]$12616
+ attribute \src "libresoc.v:183697.7-183697.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:186093.3-186102.6"
+ attribute \src "libresoc.v:183846.3-183855.6"
wire width 64 $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:186083.26-186083.32"
- wire width 64 $memrd$\memory$libresoc.v:186083$12705_DATA
+ attribute \src "libresoc.v:183836.26-183836.32"
+ wire width 64 $memrd$\memory$libresoc.v:183836$12613_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 7 $memwr$\memory$libresoc.v:186081$12699_ADDR
+ wire width 7 $memwr$\memory$libresoc.v:183834$12607_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:186081$12699_DATA
+ wire width 64 $memwr$\memory$libresoc.v:183834$12607_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:186081$12699_EN
- attribute \src "libresoc.v:186078.13-186078.16"
+ wire width 64 $memwr$\memory$libresoc.v:183834$12607_EN
+ attribute \src "libresoc.v:183831.13-183831.16"
wire width 7 \_0_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 8 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:185928.7-185928.15"
+ attribute \src "libresoc.v:183681.7-183681.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 7 \memory_r_addr
wire input 4 \spr1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 7 \spr1__wen
- attribute \src "libresoc.v:185962.14-185962.20"
+ attribute \src "libresoc.v:183715.14-183715.20"
memory width 64 size 113 \memory
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12710
+ cell $meminit $meminit$\memory$libresoc.v:0$12618
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12710
+ parameter \PRIORITY 12618
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12711
+ cell $meminit $meminit$\memory$libresoc.v:0$12619
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12711
+ parameter \PRIORITY 12619
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12712
+ cell $meminit $meminit$\memory$libresoc.v:0$12620
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12712
+ parameter \PRIORITY 12620
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12713
+ cell $meminit $meminit$\memory$libresoc.v:0$12621
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12713
+ parameter \PRIORITY 12621
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12714
+ cell $meminit $meminit$\memory$libresoc.v:0$12622
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12714
+ parameter \PRIORITY 12622
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12715
+ cell $meminit $meminit$\memory$libresoc.v:0$12623
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12715
+ parameter \PRIORITY 12623
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12716
+ cell $meminit $meminit$\memory$libresoc.v:0$12624
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12716
+ parameter \PRIORITY 12624
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12717
+ cell $meminit $meminit$\memory$libresoc.v:0$12625
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12717
+ parameter \PRIORITY 12625
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12718
+ cell $meminit $meminit$\memory$libresoc.v:0$12626
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12718
+ parameter \PRIORITY 12626
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 8
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12719
+ cell $meminit $meminit$\memory$libresoc.v:0$12627
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12719
+ parameter \PRIORITY 12627
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 9
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12720
+ cell $meminit $meminit$\memory$libresoc.v:0$12628
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12720
+ parameter \PRIORITY 12628
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 10
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12721
+ cell $meminit $meminit$\memory$libresoc.v:0$12629
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12721
+ parameter \PRIORITY 12629
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 11
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12722
+ cell $meminit $meminit$\memory$libresoc.v:0$12630
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12722
+ parameter \PRIORITY 12630
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 12
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12723
+ cell $meminit $meminit$\memory$libresoc.v:0$12631
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12723
+ parameter \PRIORITY 12631
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 13
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12724
+ cell $meminit $meminit$\memory$libresoc.v:0$12632
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12724
+ parameter \PRIORITY 12632
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 14
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12725
+ cell $meminit $meminit$\memory$libresoc.v:0$12633
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12725
+ parameter \PRIORITY 12633
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 15
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12726
+ cell $meminit $meminit$\memory$libresoc.v:0$12634
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12726
+ parameter \PRIORITY 12634
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 16
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12727
+ cell $meminit $meminit$\memory$libresoc.v:0$12635
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12727
+ parameter \PRIORITY 12635
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 17
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12728
+ cell $meminit $meminit$\memory$libresoc.v:0$12636
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12728
+ parameter \PRIORITY 12636
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 18
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12729
+ cell $meminit $meminit$\memory$libresoc.v:0$12637
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12729
+ parameter \PRIORITY 12637
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 19
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12730
+ cell $meminit $meminit$\memory$libresoc.v:0$12638
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12730
+ parameter \PRIORITY 12638
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 20
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12731
+ cell $meminit $meminit$\memory$libresoc.v:0$12639
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12731
+ parameter \PRIORITY 12639
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 21
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12732
+ cell $meminit $meminit$\memory$libresoc.v:0$12640
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12732
+ parameter \PRIORITY 12640
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 22
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12733
+ cell $meminit $meminit$\memory$libresoc.v:0$12641
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12733
+ parameter \PRIORITY 12641
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 23
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12734
+ cell $meminit $meminit$\memory$libresoc.v:0$12642
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12734
+ parameter \PRIORITY 12642
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 24
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12735
+ cell $meminit $meminit$\memory$libresoc.v:0$12643
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12735
+ parameter \PRIORITY 12643
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 25
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12736
+ cell $meminit $meminit$\memory$libresoc.v:0$12644
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12736
+ parameter \PRIORITY 12644
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 26
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12737
+ cell $meminit $meminit$\memory$libresoc.v:0$12645
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12737
+ parameter \PRIORITY 12645
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 27
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12738
+ cell $meminit $meminit$\memory$libresoc.v:0$12646
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12738
+ parameter \PRIORITY 12646
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 28
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12739
+ cell $meminit $meminit$\memory$libresoc.v:0$12647
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12739
+ parameter \PRIORITY 12647
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 29
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12740
+ cell $meminit $meminit$\memory$libresoc.v:0$12648
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12740
+ parameter \PRIORITY 12648
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 30
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12741
+ cell $meminit $meminit$\memory$libresoc.v:0$12649
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12741
+ parameter \PRIORITY 12649
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 31
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12742
+ cell $meminit $meminit$\memory$libresoc.v:0$12650
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12742
+ parameter \PRIORITY 12650
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 32
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12743
+ cell $meminit $meminit$\memory$libresoc.v:0$12651
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12743
+ parameter \PRIORITY 12651
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 33
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12744
+ cell $meminit $meminit$\memory$libresoc.v:0$12652
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12744
+ parameter \PRIORITY 12652
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 34
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12745
+ cell $meminit $meminit$\memory$libresoc.v:0$12653
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12745
+ parameter \PRIORITY 12653
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 35
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12746
+ cell $meminit $meminit$\memory$libresoc.v:0$12654
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12746
+ parameter \PRIORITY 12654
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 36
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12747
+ cell $meminit $meminit$\memory$libresoc.v:0$12655
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12747
+ parameter \PRIORITY 12655
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 37
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12748
+ cell $meminit $meminit$\memory$libresoc.v:0$12656
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12748
+ parameter \PRIORITY 12656
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 38
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12749
+ cell $meminit $meminit$\memory$libresoc.v:0$12657
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12749
+ parameter \PRIORITY 12657
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 39
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12750
+ cell $meminit $meminit$\memory$libresoc.v:0$12658
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12750
+ parameter \PRIORITY 12658
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 40
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12751
+ cell $meminit $meminit$\memory$libresoc.v:0$12659
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12751
+ parameter \PRIORITY 12659
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 41
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12752
+ cell $meminit $meminit$\memory$libresoc.v:0$12660
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12752
+ parameter \PRIORITY 12660
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 42
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12753
+ cell $meminit $meminit$\memory$libresoc.v:0$12661
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12753
+ parameter \PRIORITY 12661
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 43
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12754
+ cell $meminit $meminit$\memory$libresoc.v:0$12662
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12754
+ parameter \PRIORITY 12662
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 44
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12755
+ cell $meminit $meminit$\memory$libresoc.v:0$12663
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12755
+ parameter \PRIORITY 12663
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 45
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12756
+ cell $meminit $meminit$\memory$libresoc.v:0$12664
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12756
+ parameter \PRIORITY 12664
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 46
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12757
+ cell $meminit $meminit$\memory$libresoc.v:0$12665
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12757
+ parameter \PRIORITY 12665
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 47
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12758
+ cell $meminit $meminit$\memory$libresoc.v:0$12666
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12758
+ parameter \PRIORITY 12666
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 48
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12759
+ cell $meminit $meminit$\memory$libresoc.v:0$12667
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12759
+ parameter \PRIORITY 12667
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 49
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12760
+ cell $meminit $meminit$\memory$libresoc.v:0$12668
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12760
+ parameter \PRIORITY 12668
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 50
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12761
+ cell $meminit $meminit$\memory$libresoc.v:0$12669
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12761
+ parameter \PRIORITY 12669
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 51
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12762
+ cell $meminit $meminit$\memory$libresoc.v:0$12670
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12762
+ parameter \PRIORITY 12670
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 52
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12763
+ cell $meminit $meminit$\memory$libresoc.v:0$12671
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12763
+ parameter \PRIORITY 12671
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 53
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12764
+ cell $meminit $meminit$\memory$libresoc.v:0$12672
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12764
+ parameter \PRIORITY 12672
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 54
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12765
+ cell $meminit $meminit$\memory$libresoc.v:0$12673
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12765
+ parameter \PRIORITY 12673
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 55
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12766
+ cell $meminit $meminit$\memory$libresoc.v:0$12674
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12766
+ parameter \PRIORITY 12674
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 56
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12767
+ cell $meminit $meminit$\memory$libresoc.v:0$12675
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12767
+ parameter \PRIORITY 12675
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 57
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12768
+ cell $meminit $meminit$\memory$libresoc.v:0$12676
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12768
+ parameter \PRIORITY 12676
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 58
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12769
+ cell $meminit $meminit$\memory$libresoc.v:0$12677
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12769
+ parameter \PRIORITY 12677
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 59
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12770
+ cell $meminit $meminit$\memory$libresoc.v:0$12678
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12770
+ parameter \PRIORITY 12678
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 60
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12771
+ cell $meminit $meminit$\memory$libresoc.v:0$12679
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12771
+ parameter \PRIORITY 12679
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 61
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12772
+ cell $meminit $meminit$\memory$libresoc.v:0$12680
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12772
+ parameter \PRIORITY 12680
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 62
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12773
+ cell $meminit $meminit$\memory$libresoc.v:0$12681
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12773
+ parameter \PRIORITY 12681
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 63
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12774
+ cell $meminit $meminit$\memory$libresoc.v:0$12682
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12774
+ parameter \PRIORITY 12682
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 64
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12775
+ cell $meminit $meminit$\memory$libresoc.v:0$12683
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12775
+ parameter \PRIORITY 12683
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 65
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12776
+ cell $meminit $meminit$\memory$libresoc.v:0$12684
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12776
+ parameter \PRIORITY 12684
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 66
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12777
+ cell $meminit $meminit$\memory$libresoc.v:0$12685
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12777
+ parameter \PRIORITY 12685
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 67
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12778
+ cell $meminit $meminit$\memory$libresoc.v:0$12686
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12778
+ parameter \PRIORITY 12686
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 68
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12779
+ cell $meminit $meminit$\memory$libresoc.v:0$12687
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12779
+ parameter \PRIORITY 12687
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 69
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12780
+ cell $meminit $meminit$\memory$libresoc.v:0$12688
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12780
+ parameter \PRIORITY 12688
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 70
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12781
+ cell $meminit $meminit$\memory$libresoc.v:0$12689
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12781
+ parameter \PRIORITY 12689
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 71
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12782
+ cell $meminit $meminit$\memory$libresoc.v:0$12690
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12782
+ parameter \PRIORITY 12690
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 72
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12783
+ cell $meminit $meminit$\memory$libresoc.v:0$12691
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12783
+ parameter \PRIORITY 12691
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 73
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12784
+ cell $meminit $meminit$\memory$libresoc.v:0$12692
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12784
+ parameter \PRIORITY 12692
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 74
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12785
+ cell $meminit $meminit$\memory$libresoc.v:0$12693
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12785
+ parameter \PRIORITY 12693
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 75
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12786
+ cell $meminit $meminit$\memory$libresoc.v:0$12694
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12786
+ parameter \PRIORITY 12694
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 76
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12787
+ cell $meminit $meminit$\memory$libresoc.v:0$12695
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12787
+ parameter \PRIORITY 12695
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 77
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12788
+ cell $meminit $meminit$\memory$libresoc.v:0$12696
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12788
+ parameter \PRIORITY 12696
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 78
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12789
+ cell $meminit $meminit$\memory$libresoc.v:0$12697
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12789
+ parameter \PRIORITY 12697
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 79
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12790
+ cell $meminit $meminit$\memory$libresoc.v:0$12698
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12790
+ parameter \PRIORITY 12698
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 80
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12791
+ cell $meminit $meminit$\memory$libresoc.v:0$12699
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12791
+ parameter \PRIORITY 12699
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 81
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12792
+ cell $meminit $meminit$\memory$libresoc.v:0$12700
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12792
+ parameter \PRIORITY 12700
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 82
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12793
+ cell $meminit $meminit$\memory$libresoc.v:0$12701
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12793
+ parameter \PRIORITY 12701
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 83
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12794
+ cell $meminit $meminit$\memory$libresoc.v:0$12702
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12794
+ parameter \PRIORITY 12702
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 84
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12795
+ cell $meminit $meminit$\memory$libresoc.v:0$12703
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12795
+ parameter \PRIORITY 12703
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 85
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12796
+ cell $meminit $meminit$\memory$libresoc.v:0$12704
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12796
+ parameter \PRIORITY 12704
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 86
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12797
+ cell $meminit $meminit$\memory$libresoc.v:0$12705
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12797
+ parameter \PRIORITY 12705
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 87
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12798
+ cell $meminit $meminit$\memory$libresoc.v:0$12706
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12798
+ parameter \PRIORITY 12706
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 88
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12799
+ cell $meminit $meminit$\memory$libresoc.v:0$12707
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12799
+ parameter \PRIORITY 12707
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 89
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12800
+ cell $meminit $meminit$\memory$libresoc.v:0$12708
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12800
+ parameter \PRIORITY 12708
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 90
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12801
+ cell $meminit $meminit$\memory$libresoc.v:0$12709
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12801
+ parameter \PRIORITY 12709
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 91
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12802
+ cell $meminit $meminit$\memory$libresoc.v:0$12710
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12802
+ parameter \PRIORITY 12710
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 92
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12803
+ cell $meminit $meminit$\memory$libresoc.v:0$12711
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12803
+ parameter \PRIORITY 12711
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 93
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12804
+ cell $meminit $meminit$\memory$libresoc.v:0$12712
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12804
+ parameter \PRIORITY 12712
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 94
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12805
+ cell $meminit $meminit$\memory$libresoc.v:0$12713
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12805
+ parameter \PRIORITY 12713
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 95
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12806
+ cell $meminit $meminit$\memory$libresoc.v:0$12714
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12806
+ parameter \PRIORITY 12714
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 96
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12807
+ cell $meminit $meminit$\memory$libresoc.v:0$12715
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12807
+ parameter \PRIORITY 12715
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 97
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12808
+ cell $meminit $meminit$\memory$libresoc.v:0$12716
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12808
+ parameter \PRIORITY 12716
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 98
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12809
+ cell $meminit $meminit$\memory$libresoc.v:0$12717
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12809
+ parameter \PRIORITY 12717
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 99
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12810
+ cell $meminit $meminit$\memory$libresoc.v:0$12718
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12810
+ parameter \PRIORITY 12718
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 100
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12811
+ cell $meminit $meminit$\memory$libresoc.v:0$12719
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12811
+ parameter \PRIORITY 12719
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 101
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12812
+ cell $meminit $meminit$\memory$libresoc.v:0$12720
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12812
+ parameter \PRIORITY 12720
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 102
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12813
+ cell $meminit $meminit$\memory$libresoc.v:0$12721
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12813
+ parameter \PRIORITY 12721
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 103
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12814
+ cell $meminit $meminit$\memory$libresoc.v:0$12722
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12814
+ parameter \PRIORITY 12722
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 104
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12815
+ cell $meminit $meminit$\memory$libresoc.v:0$12723
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12815
+ parameter \PRIORITY 12723
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 105
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12816
+ cell $meminit $meminit$\memory$libresoc.v:0$12724
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12816
+ parameter \PRIORITY 12724
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 106
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12817
+ cell $meminit $meminit$\memory$libresoc.v:0$12725
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12817
+ parameter \PRIORITY 12725
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 107
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12818
+ cell $meminit $meminit$\memory$libresoc.v:0$12726
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12818
+ parameter \PRIORITY 12726
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 108
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12819
+ cell $meminit $meminit$\memory$libresoc.v:0$12727
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12819
+ parameter \PRIORITY 12727
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 109
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12820
+ cell $meminit $meminit$\memory$libresoc.v:0$12728
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12820
+ parameter \PRIORITY 12728
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 110
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12821
+ cell $meminit $meminit$\memory$libresoc.v:0$12729
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12821
+ parameter \PRIORITY 12729
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 111
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:0.0-0.0"
- cell $meminit $meminit$\memory$libresoc.v:0$12822
+ cell $meminit $meminit$\memory$libresoc.v:0$12730
parameter \ABITS 32
parameter \MEMID "\\memory"
- parameter \PRIORITY 12822
+ parameter \PRIORITY 12730
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 112
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:186083.26-186083.32"
- cell $memrd $memrd$\memory$libresoc.v:186083$12705
+ attribute \src "libresoc.v:183836.26-183836.32"
+ cell $memrd $memrd$\memory$libresoc.v:183836$12613
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:186083$12705_DATA
+ connect \DATA $memrd$\memory$libresoc.v:183836$12613_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- cell $memwr $memwr$\memory$libresoc.v:0$12823
+ cell $memwr $memwr$\memory$libresoc.v:0$12731
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\memory"
- parameter \PRIORITY 12823
+ parameter \PRIORITY 12731
parameter \WIDTH 64
- connect \ADDR $memwr$\memory$libresoc.v:186081$12699_ADDR
+ connect \ADDR $memwr$\memory$libresoc.v:183834$12607_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\memory$libresoc.v:186081$12699_DATA
- connect \EN $memwr$\memory$libresoc.v:186081$12699_EN
+ connect \DATA $memwr$\memory$libresoc.v:183834$12607_DATA
+ connect \EN $memwr$\memory$libresoc.v:183834$12607_EN
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$12826
+ process $proc$libresoc.v:0$12734
sync always
sync init
end
- attribute \src "libresoc.v:185928.7-185928.20"
- process $proc$libresoc.v:185928$12824
+ attribute \src "libresoc.v:183681.7-183681.20"
+ process $proc$libresoc.v:183681$12732
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:185944.7-185944.23"
- process $proc$libresoc.v:185944$12825
+ attribute \src "libresoc.v:183697.7-183697.23"
+ process $proc$libresoc.v:183697$12733
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:185960.3-185961.35"
- process $proc$libresoc.v:185960$12700
+ attribute \src "libresoc.v:183713.3-183714.35"
+ process $proc$libresoc.v:183713$12608
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:186079.3-186082.6"
- process $proc$libresoc.v:186079$12701
+ attribute \src "libresoc.v:183832.3-183835.6"
+ process $proc$libresoc.v:183832$12609
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 7'xxxxxxx
- assign $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 7'xxxxxxx
+ assign $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 64'0000000000000000000000000000000000000000000000000000000000000000
assign $0\_0_[6:0] \spr1__addr
- attribute \src "libresoc.v:186081.5-186081.59"
+ attribute \src "libresoc.v:183834.5-183834.59"
switch \spr1__wen
- attribute \src "libresoc.v:186081.9-186081.18"
+ attribute \src "libresoc.v:183834.9-183834.18"
case 1'1
- assign $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 \spr1__addr$1
- assign $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 \spr1__data_i
- assign $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 \spr1__addr$1
+ assign $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 \spr1__data_i
+ assign $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 64'1111111111111111111111111111111111111111111111111111111111111111
case
end
sync posedge \coresync_clk
update \_0_ $0\_0_[6:0]
- update $memwr$\memory$libresoc.v:186081$12699_ADDR $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702
- update $memwr$\memory$libresoc.v:186081$12699_DATA $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703
- update $memwr$\memory$libresoc.v:186081$12699_EN $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704
+ update $memwr$\memory$libresoc.v:183834$12607_ADDR $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610
+ update $memwr$\memory$libresoc.v:183834$12607_DATA $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611
+ update $memwr$\memory$libresoc.v:183834$12607_EN $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612
end
- attribute \src "libresoc.v:186084.3-186092.6"
- process $proc$libresoc.v:186084$12706
+ attribute \src "libresoc.v:183837.3-183845.6"
+ process $proc$libresoc.v:183837$12614
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$12707 $1\ren_delay$next[0:0]$12708
- attribute \src "libresoc.v:186085.5-186085.29"
+ assign $0\ren_delay$next[0:0]$12615 $1\ren_delay$next[0:0]$12616
+ attribute \src "libresoc.v:183838.5-183838.29"
switch \initial
- attribute \src "libresoc.v:186085.9-186085.17"
+ attribute \src "libresoc.v:183838.9-183838.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$12708 1'0
+ assign $1\ren_delay$next[0:0]$12616 1'0
case
- assign $1\ren_delay$next[0:0]$12708 \spr1__ren
+ assign $1\ren_delay$next[0:0]$12616 \spr1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$12707
+ update \ren_delay$next $0\ren_delay$next[0:0]$12615
end
- attribute \src "libresoc.v:186093.3-186102.6"
- process $proc$libresoc.v:186093$12709
+ attribute \src "libresoc.v:183846.3-183855.6"
+ process $proc$libresoc.v:183846$12617
assign { } { }
assign { } { }
assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:186094.5-186094.29"
+ attribute \src "libresoc.v:183847.5-183847.29"
switch \initial
- attribute \src "libresoc.v:186094.9-186094.17"
+ attribute \src "libresoc.v:183847.9-183847.17"
case 1'1
case
end
sync always
update \spr1__data_o $0\spr1__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:186083$12705_DATA
+ connect \memory_r_data $memrd$\memory$libresoc.v:183836$12613_DATA
connect \memory_w_data \spr1__data_i
connect \memory_w_en \spr1__wen
connect \memory_w_addr \spr1__addr$1
connect \memory_r_addr \spr1__addr
end
-attribute \src "libresoc.v:186111.1-187360.10"
+attribute \src "libresoc.v:183864.1-185113.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0"
attribute \generator "nMigen"
module \spr0
- attribute \src "libresoc.v:186857.3-186858.25"
+ attribute \src "libresoc.v:184610.3-184611.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:186855.3-186856.40"
+ attribute \src "libresoc.v:184608.3-184609.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:187251.3-187259.6"
- wire $0\alu_l_r_alu$next[0:0]$13040
- attribute \src "libresoc.v:186785.3-186786.39"
+ attribute \src "libresoc.v:185004.3-185012.6"
+ wire $0\alu_l_r_alu$next[0:0]$12948
+ attribute \src "libresoc.v:184538.3-184539.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962
- attribute \src "libresoc.v:186827.3-186828.65"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870
+ attribute \src "libresoc.v:184580.3-184581.65"
wire width 13 $0\alu_spr0_spr_op__fn_unit[12:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12963
- attribute \src "libresoc.v:186829.3-186830.59"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12871
+ attribute \src "libresoc.v:184582.3-184583.59"
wire width 32 $0\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12964
- attribute \src "libresoc.v:186825.3-186826.69"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12872
+ attribute \src "libresoc.v:184578.3-184579.69"
wire width 7 $0\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965
- attribute \src "libresoc.v:186831.3-186832.67"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873
+ attribute \src "libresoc.v:184584.3-184585.67"
wire $0\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:187242.3-187250.6"
- wire $0\alui_l_r_alui$next[0:0]$13037
- attribute \src "libresoc.v:186787.3-186788.43"
+ attribute \src "libresoc.v:184995.3-185003.6"
+ wire $0\alui_l_r_alui$next[0:0]$12945
+ attribute \src "libresoc.v:184540.3-184541.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:187050.3-187071.6"
- wire width 64 $0\data_r0__o$next[63:0]$12971
- attribute \src "libresoc.v:186821.3-186822.37"
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire width 64 $0\data_r0__o$next[63:0]$12879
+ attribute \src "libresoc.v:184574.3-184575.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:187050.3-187071.6"
- wire $0\data_r0__o_ok$next[0:0]$12972
- attribute \src "libresoc.v:186823.3-186824.43"
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire $0\data_r0__o_ok$next[0:0]$12880
+ attribute \src "libresoc.v:184576.3-184577.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:187072.3-187093.6"
- wire width 64 $0\data_r1__spr1$next[63:0]$12979
- attribute \src "libresoc.v:186817.3-186818.43"
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire width 64 $0\data_r1__spr1$next[63:0]$12887
+ attribute \src "libresoc.v:184570.3-184571.43"
wire width 64 $0\data_r1__spr1[63:0]
- attribute \src "libresoc.v:187072.3-187093.6"
- wire $0\data_r1__spr1_ok$next[0:0]$12980
- attribute \src "libresoc.v:186819.3-186820.49"
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire $0\data_r1__spr1_ok$next[0:0]$12888
+ attribute \src "libresoc.v:184572.3-184573.49"
wire $0\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:187094.3-187115.6"
- wire width 64 $0\data_r2__fast1$next[63:0]$12987
- attribute \src "libresoc.v:186813.3-186814.45"
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire width 64 $0\data_r2__fast1$next[63:0]$12895
+ attribute \src "libresoc.v:184566.3-184567.45"
wire width 64 $0\data_r2__fast1[63:0]
- attribute \src "libresoc.v:187094.3-187115.6"
- wire $0\data_r2__fast1_ok$next[0:0]$12988
- attribute \src "libresoc.v:186815.3-186816.51"
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire $0\data_r2__fast1_ok$next[0:0]$12896
+ attribute \src "libresoc.v:184568.3-184569.51"
wire $0\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $0\data_r3__xer_so$next[0:0]$12995
- attribute \src "libresoc.v:186809.3-186810.47"
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $0\data_r3__xer_so$next[0:0]$12903
+ attribute \src "libresoc.v:184562.3-184563.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$12996
- attribute \src "libresoc.v:186811.3-186812.53"
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$12904
+ attribute \src "libresoc.v:184564.3-184565.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:187138.3-187159.6"
- wire width 2 $0\data_r4__xer_ov$next[1:0]$13003
- attribute \src "libresoc.v:186805.3-186806.47"
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire width 2 $0\data_r4__xer_ov$next[1:0]$12911
+ attribute \src "libresoc.v:184558.3-184559.47"
wire width 2 $0\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:187138.3-187159.6"
- wire $0\data_r4__xer_ov_ok$next[0:0]$13004
- attribute \src "libresoc.v:186807.3-186808.53"
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire $0\data_r4__xer_ov_ok$next[0:0]$12912
+ attribute \src "libresoc.v:184560.3-184561.53"
wire $0\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:187160.3-187181.6"
- wire width 2 $0\data_r5__xer_ca$next[1:0]$13011
- attribute \src "libresoc.v:186801.3-186802.47"
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire width 2 $0\data_r5__xer_ca$next[1:0]$12919
+ attribute \src "libresoc.v:184554.3-184555.47"
wire width 2 $0\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:187160.3-187181.6"
- wire $0\data_r5__xer_ca_ok$next[0:0]$13012
- attribute \src "libresoc.v:186803.3-186804.53"
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire $0\data_r5__xer_ca_ok$next[0:0]$12920
+ attribute \src "libresoc.v:184556.3-184557.53"
wire $0\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:187260.3-187269.6"
+ attribute \src "libresoc.v:185013.3-185022.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:187270.3-187279.6"
+ attribute \src "libresoc.v:185023.3-185032.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:187280.3-187289.6"
+ attribute \src "libresoc.v:185033.3-185042.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:187290.3-187299.6"
+ attribute \src "libresoc.v:185043.3-185052.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:187300.3-187309.6"
+ attribute \src "libresoc.v:185053.3-185062.6"
wire width 2 $0\dest5_o[1:0]
- attribute \src "libresoc.v:187310.3-187319.6"
+ attribute \src "libresoc.v:185063.3-185072.6"
wire width 2 $0\dest6_o[1:0]
- attribute \src "libresoc.v:186112.7-186112.20"
+ attribute \src "libresoc.v:183865.7-183865.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:186992.3-187000.6"
- wire $0\opc_l_r_opc$next[0:0]$12947
- attribute \src "libresoc.v:186841.3-186842.39"
+ attribute \src "libresoc.v:184745.3-184753.6"
+ wire $0\opc_l_r_opc$next[0:0]$12855
+ attribute \src "libresoc.v:184594.3-184595.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:186983.3-186991.6"
- wire $0\opc_l_s_opc$next[0:0]$12944
- attribute \src "libresoc.v:186843.3-186844.39"
+ attribute \src "libresoc.v:184736.3-184744.6"
+ wire $0\opc_l_s_opc$next[0:0]$12852
+ attribute \src "libresoc.v:184596.3-184597.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:187320.3-187328.6"
- wire width 6 $0\prev_wr_go$next[5:0]$13049
- attribute \src "libresoc.v:186853.3-186854.37"
+ attribute \src "libresoc.v:185073.3-185081.6"
+ wire width 6 $0\prev_wr_go$next[5:0]$12957
+ attribute \src "libresoc.v:184606.3-184607.37"
wire width 6 $0\prev_wr_go[5:0]
- attribute \src "libresoc.v:186937.3-186946.6"
+ attribute \src "libresoc.v:184690.3-184699.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:187028.3-187036.6"
- wire width 6 $0\req_l_r_req$next[5:0]$12959
- attribute \src "libresoc.v:186833.3-186834.39"
+ attribute \src "libresoc.v:184781.3-184789.6"
+ wire width 6 $0\req_l_r_req$next[5:0]$12867
+ attribute \src "libresoc.v:184586.3-184587.39"
wire width 6 $0\req_l_r_req[5:0]
- attribute \src "libresoc.v:187019.3-187027.6"
- wire width 6 $0\req_l_s_req$next[5:0]$12956
- attribute \src "libresoc.v:186835.3-186836.39"
+ attribute \src "libresoc.v:184772.3-184780.6"
+ wire width 6 $0\req_l_s_req$next[5:0]$12864
+ attribute \src "libresoc.v:184588.3-184589.39"
wire width 6 $0\req_l_s_req[5:0]
- attribute \src "libresoc.v:186956.3-186964.6"
- wire $0\rok_l_r_rdok$next[0:0]$12935
- attribute \src "libresoc.v:186849.3-186850.41"
+ attribute \src "libresoc.v:184709.3-184717.6"
+ wire $0\rok_l_r_rdok$next[0:0]$12843
+ attribute \src "libresoc.v:184602.3-184603.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:186947.3-186955.6"
- wire $0\rok_l_s_rdok$next[0:0]$12932
- attribute \src "libresoc.v:186851.3-186852.41"
+ attribute \src "libresoc.v:184700.3-184708.6"
+ wire $0\rok_l_s_rdok$next[0:0]$12840
+ attribute \src "libresoc.v:184604.3-184605.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:186974.3-186982.6"
- wire $0\rst_l_r_rst$next[0:0]$12941
- attribute \src "libresoc.v:186845.3-186846.39"
+ attribute \src "libresoc.v:184727.3-184735.6"
+ wire $0\rst_l_r_rst$next[0:0]$12849
+ attribute \src "libresoc.v:184598.3-184599.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:186965.3-186973.6"
- wire $0\rst_l_s_rst$next[0:0]$12938
- attribute \src "libresoc.v:186847.3-186848.39"
+ attribute \src "libresoc.v:184718.3-184726.6"
+ wire $0\rst_l_s_rst$next[0:0]$12846
+ attribute \src "libresoc.v:184600.3-184601.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:187010.3-187018.6"
- wire width 6 $0\src_l_r_src$next[5:0]$12953
- attribute \src "libresoc.v:186837.3-186838.39"
+ attribute \src "libresoc.v:184763.3-184771.6"
+ wire width 6 $0\src_l_r_src$next[5:0]$12861
+ attribute \src "libresoc.v:184590.3-184591.39"
wire width 6 $0\src_l_r_src[5:0]
- attribute \src "libresoc.v:187001.3-187009.6"
- wire width 6 $0\src_l_s_src$next[5:0]$12950
- attribute \src "libresoc.v:186839.3-186840.39"
+ attribute \src "libresoc.v:184754.3-184762.6"
+ wire width 6 $0\src_l_s_src$next[5:0]$12858
+ attribute \src "libresoc.v:184592.3-184593.39"
wire width 6 $0\src_l_s_src[5:0]
- attribute \src "libresoc.v:187182.3-187191.6"
- wire width 64 $0\src_r0$next[63:0]$13019
- attribute \src "libresoc.v:186799.3-186800.29"
+ attribute \src "libresoc.v:184935.3-184944.6"
+ wire width 64 $0\src_r0$next[63:0]$12927
+ attribute \src "libresoc.v:184552.3-184553.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:187192.3-187201.6"
- wire width 64 $0\src_r1$next[63:0]$13022
- attribute \src "libresoc.v:186797.3-186798.29"
+ attribute \src "libresoc.v:184945.3-184954.6"
+ wire width 64 $0\src_r1$next[63:0]$12930
+ attribute \src "libresoc.v:184550.3-184551.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:187202.3-187211.6"
- wire width 64 $0\src_r2$next[63:0]$13025
- attribute \src "libresoc.v:186795.3-186796.29"
+ attribute \src "libresoc.v:184955.3-184964.6"
+ wire width 64 $0\src_r2$next[63:0]$12933
+ attribute \src "libresoc.v:184548.3-184549.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:187212.3-187221.6"
- wire $0\src_r3$next[0:0]$13028
- attribute \src "libresoc.v:186793.3-186794.29"
+ attribute \src "libresoc.v:184965.3-184974.6"
+ wire $0\src_r3$next[0:0]$12936
+ attribute \src "libresoc.v:184546.3-184547.29"
wire $0\src_r3[0:0]
- attribute \src "libresoc.v:187222.3-187231.6"
- wire width 2 $0\src_r4$next[1:0]$13031
- attribute \src "libresoc.v:186791.3-186792.29"
+ attribute \src "libresoc.v:184975.3-184984.6"
+ wire width 2 $0\src_r4$next[1:0]$12939
+ attribute \src "libresoc.v:184544.3-184545.29"
wire width 2 $0\src_r4[1:0]
- attribute \src "libresoc.v:187232.3-187241.6"
- wire width 2 $0\src_r5$next[1:0]$13034
- attribute \src "libresoc.v:186789.3-186790.29"
+ attribute \src "libresoc.v:184985.3-184994.6"
+ wire width 2 $0\src_r5$next[1:0]$12942
+ attribute \src "libresoc.v:184542.3-184543.29"
wire width 2 $0\src_r5[1:0]
- attribute \src "libresoc.v:186248.7-186248.24"
+ attribute \src "libresoc.v:184001.7-184001.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:186258.7-186258.26"
+ attribute \src "libresoc.v:184011.7-184011.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:187251.3-187259.6"
- wire $1\alu_l_r_alu$next[0:0]$13041
- attribute \src "libresoc.v:186266.7-186266.25"
+ attribute \src "libresoc.v:185004.3-185012.6"
+ wire $1\alu_l_r_alu$next[0:0]$12949
+ attribute \src "libresoc.v:184019.7-184019.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966
- attribute \src "libresoc.v:186310.14-186310.49"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874
+ attribute \src "libresoc.v:184063.14-184063.49"
wire width 13 $1\alu_spr0_spr_op__fn_unit[12:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12967
- attribute \src "libresoc.v:186314.14-186314.43"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12875
+ attribute \src "libresoc.v:184067.14-184067.43"
wire width 32 $1\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968
- attribute \src "libresoc.v:186392.13-186392.47"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876
+ attribute \src "libresoc.v:184145.13-184145.47"
wire width 7 $1\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:187037.3-187049.6"
- wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969
- attribute \src "libresoc.v:186396.7-186396.39"
+ attribute \src "libresoc.v:184790.3-184802.6"
+ wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877
+ attribute \src "libresoc.v:184149.7-184149.39"
wire $1\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:187242.3-187250.6"
- wire $1\alui_l_r_alui$next[0:0]$13038
- attribute \src "libresoc.v:186414.7-186414.27"
+ attribute \src "libresoc.v:184995.3-185003.6"
+ wire $1\alui_l_r_alui$next[0:0]$12946
+ attribute \src "libresoc.v:184167.7-184167.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:187050.3-187071.6"
- wire width 64 $1\data_r0__o$next[63:0]$12973
- attribute \src "libresoc.v:186446.14-186446.47"
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire width 64 $1\data_r0__o$next[63:0]$12881
+ attribute \src "libresoc.v:184199.14-184199.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:187050.3-187071.6"
- wire $1\data_r0__o_ok$next[0:0]$12974
- attribute \src "libresoc.v:186450.7-186450.27"
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire $1\data_r0__o_ok$next[0:0]$12882
+ attribute \src "libresoc.v:184203.7-184203.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:187072.3-187093.6"
- wire width 64 $1\data_r1__spr1$next[63:0]$12981
- attribute \src "libresoc.v:186454.14-186454.50"
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire width 64 $1\data_r1__spr1$next[63:0]$12889
+ attribute \src "libresoc.v:184207.14-184207.50"
wire width 64 $1\data_r1__spr1[63:0]
- attribute \src "libresoc.v:187072.3-187093.6"
- wire $1\data_r1__spr1_ok$next[0:0]$12982
- attribute \src "libresoc.v:186458.7-186458.30"
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire $1\data_r1__spr1_ok$next[0:0]$12890
+ attribute \src "libresoc.v:184211.7-184211.30"
wire $1\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:187094.3-187115.6"
- wire width 64 $1\data_r2__fast1$next[63:0]$12989
- attribute \src "libresoc.v:186462.14-186462.51"
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire width 64 $1\data_r2__fast1$next[63:0]$12897
+ attribute \src "libresoc.v:184215.14-184215.51"
wire width 64 $1\data_r2__fast1[63:0]
- attribute \src "libresoc.v:187094.3-187115.6"
- wire $1\data_r2__fast1_ok$next[0:0]$12990
- attribute \src "libresoc.v:186466.7-186466.31"
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire $1\data_r2__fast1_ok$next[0:0]$12898
+ attribute \src "libresoc.v:184219.7-184219.31"
wire $1\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $1\data_r3__xer_so$next[0:0]$12997
- attribute \src "libresoc.v:186470.7-186470.29"
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $1\data_r3__xer_so$next[0:0]$12905
+ attribute \src "libresoc.v:184223.7-184223.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$12998
- attribute \src "libresoc.v:186474.7-186474.32"
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$12906
+ attribute \src "libresoc.v:184227.7-184227.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:187138.3-187159.6"
- wire width 2 $1\data_r4__xer_ov$next[1:0]$13005
- attribute \src "libresoc.v:186478.13-186478.35"
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire width 2 $1\data_r4__xer_ov$next[1:0]$12913
+ attribute \src "libresoc.v:184231.13-184231.35"
wire width 2 $1\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:187138.3-187159.6"
- wire $1\data_r4__xer_ov_ok$next[0:0]$13006
- attribute \src "libresoc.v:186482.7-186482.32"
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire $1\data_r4__xer_ov_ok$next[0:0]$12914
+ attribute \src "libresoc.v:184235.7-184235.32"
wire $1\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:187160.3-187181.6"
- wire width 2 $1\data_r5__xer_ca$next[1:0]$13013
- attribute \src "libresoc.v:186486.13-186486.35"
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire width 2 $1\data_r5__xer_ca$next[1:0]$12921
+ attribute \src "libresoc.v:184239.13-184239.35"
wire width 2 $1\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:187160.3-187181.6"
- wire $1\data_r5__xer_ca_ok$next[0:0]$13014
- attribute \src "libresoc.v:186490.7-186490.32"
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire $1\data_r5__xer_ca_ok$next[0:0]$12922
+ attribute \src "libresoc.v:184243.7-184243.32"
wire $1\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:187260.3-187269.6"
+ attribute \src "libresoc.v:185013.3-185022.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:187270.3-187279.6"
+ attribute \src "libresoc.v:185023.3-185032.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:187280.3-187289.6"
+ attribute \src "libresoc.v:185033.3-185042.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:187290.3-187299.6"
+ attribute \src "libresoc.v:185043.3-185052.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:187300.3-187309.6"
+ attribute \src "libresoc.v:185053.3-185062.6"
wire width 2 $1\dest5_o[1:0]
- attribute \src "libresoc.v:187310.3-187319.6"
+ attribute \src "libresoc.v:185063.3-185072.6"
wire width 2 $1\dest6_o[1:0]
- attribute \src "libresoc.v:186992.3-187000.6"
- wire $1\opc_l_r_opc$next[0:0]$12948
- attribute \src "libresoc.v:186518.7-186518.25"
+ attribute \src "libresoc.v:184745.3-184753.6"
+ wire $1\opc_l_r_opc$next[0:0]$12856
+ attribute \src "libresoc.v:184271.7-184271.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:186983.3-186991.6"
- wire $1\opc_l_s_opc$next[0:0]$12945
- attribute \src "libresoc.v:186522.7-186522.25"
+ attribute \src "libresoc.v:184736.3-184744.6"
+ wire $1\opc_l_s_opc$next[0:0]$12853
+ attribute \src "libresoc.v:184275.7-184275.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:187320.3-187328.6"
- wire width 6 $1\prev_wr_go$next[5:0]$13050
- attribute \src "libresoc.v:186622.13-186622.31"
+ attribute \src "libresoc.v:185073.3-185081.6"
+ wire width 6 $1\prev_wr_go$next[5:0]$12958
+ attribute \src "libresoc.v:184375.13-184375.31"
wire width 6 $1\prev_wr_go[5:0]
- attribute \src "libresoc.v:186937.3-186946.6"
+ attribute \src "libresoc.v:184690.3-184699.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:187028.3-187036.6"
- wire width 6 $1\req_l_r_req$next[5:0]$12960
- attribute \src "libresoc.v:186630.13-186630.32"
+ attribute \src "libresoc.v:184781.3-184789.6"
+ wire width 6 $1\req_l_r_req$next[5:0]$12868
+ attribute \src "libresoc.v:184383.13-184383.32"
wire width 6 $1\req_l_r_req[5:0]
- attribute \src "libresoc.v:187019.3-187027.6"
- wire width 6 $1\req_l_s_req$next[5:0]$12957
- attribute \src "libresoc.v:186634.13-186634.32"
+ attribute \src "libresoc.v:184772.3-184780.6"
+ wire width 6 $1\req_l_s_req$next[5:0]$12865
+ attribute \src "libresoc.v:184387.13-184387.32"
wire width 6 $1\req_l_s_req[5:0]
- attribute \src "libresoc.v:186956.3-186964.6"
- wire $1\rok_l_r_rdok$next[0:0]$12936
- attribute \src "libresoc.v:186646.7-186646.26"
+ attribute \src "libresoc.v:184709.3-184717.6"
+ wire $1\rok_l_r_rdok$next[0:0]$12844
+ attribute \src "libresoc.v:184399.7-184399.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:186947.3-186955.6"
- wire $1\rok_l_s_rdok$next[0:0]$12933
- attribute \src "libresoc.v:186650.7-186650.26"
+ attribute \src "libresoc.v:184700.3-184708.6"
+ wire $1\rok_l_s_rdok$next[0:0]$12841
+ attribute \src "libresoc.v:184403.7-184403.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:186974.3-186982.6"
- wire $1\rst_l_r_rst$next[0:0]$12942
- attribute \src "libresoc.v:186654.7-186654.25"
+ attribute \src "libresoc.v:184727.3-184735.6"
+ wire $1\rst_l_r_rst$next[0:0]$12850
+ attribute \src "libresoc.v:184407.7-184407.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:186965.3-186973.6"
- wire $1\rst_l_s_rst$next[0:0]$12939
- attribute \src "libresoc.v:186658.7-186658.25"
+ attribute \src "libresoc.v:184718.3-184726.6"
+ wire $1\rst_l_s_rst$next[0:0]$12847
+ attribute \src "libresoc.v:184411.7-184411.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:187010.3-187018.6"
- wire width 6 $1\src_l_r_src$next[5:0]$12954
- attribute \src "libresoc.v:186680.13-186680.32"
+ attribute \src "libresoc.v:184763.3-184771.6"
+ wire width 6 $1\src_l_r_src$next[5:0]$12862
+ attribute \src "libresoc.v:184433.13-184433.32"
wire width 6 $1\src_l_r_src[5:0]
- attribute \src "libresoc.v:187001.3-187009.6"
- wire width 6 $1\src_l_s_src$next[5:0]$12951
- attribute \src "libresoc.v:186684.13-186684.32"
+ attribute \src "libresoc.v:184754.3-184762.6"
+ wire width 6 $1\src_l_s_src$next[5:0]$12859
+ attribute \src "libresoc.v:184437.13-184437.32"
wire width 6 $1\src_l_s_src[5:0]
- attribute \src "libresoc.v:187182.3-187191.6"
- wire width 64 $1\src_r0$next[63:0]$13020
- attribute \src "libresoc.v:186688.14-186688.43"
+ attribute \src "libresoc.v:184935.3-184944.6"
+ wire width 64 $1\src_r0$next[63:0]$12928
+ attribute \src "libresoc.v:184441.14-184441.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:187192.3-187201.6"
- wire width 64 $1\src_r1$next[63:0]$13023
- attribute \src "libresoc.v:186692.14-186692.43"
+ attribute \src "libresoc.v:184945.3-184954.6"
+ wire width 64 $1\src_r1$next[63:0]$12931
+ attribute \src "libresoc.v:184445.14-184445.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:187202.3-187211.6"
- wire width 64 $1\src_r2$next[63:0]$13026
- attribute \src "libresoc.v:186696.14-186696.43"
+ attribute \src "libresoc.v:184955.3-184964.6"
+ wire width 64 $1\src_r2$next[63:0]$12934
+ attribute \src "libresoc.v:184449.14-184449.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:187212.3-187221.6"
- wire $1\src_r3$next[0:0]$13029
- attribute \src "libresoc.v:186700.7-186700.20"
+ attribute \src "libresoc.v:184965.3-184974.6"
+ wire $1\src_r3$next[0:0]$12937
+ attribute \src "libresoc.v:184453.7-184453.20"
wire $1\src_r3[0:0]
- attribute \src "libresoc.v:187222.3-187231.6"
- wire width 2 $1\src_r4$next[1:0]$13032
- attribute \src "libresoc.v:186704.13-186704.26"
+ attribute \src "libresoc.v:184975.3-184984.6"
+ wire width 2 $1\src_r4$next[1:0]$12940
+ attribute \src "libresoc.v:184457.13-184457.26"
wire width 2 $1\src_r4[1:0]
- attribute \src "libresoc.v:187232.3-187241.6"
- wire width 2 $1\src_r5$next[1:0]$13035
- attribute \src "libresoc.v:186708.13-186708.26"
+ attribute \src "libresoc.v:184985.3-184994.6"
+ wire width 2 $1\src_r5$next[1:0]$12943
+ attribute \src "libresoc.v:184461.13-184461.26"
wire width 2 $1\src_r5[1:0]
- attribute \src "libresoc.v:187050.3-187071.6"
- wire width 64 $2\data_r0__o$next[63:0]$12975
- attribute \src "libresoc.v:187050.3-187071.6"
- wire $2\data_r0__o_ok$next[0:0]$12976
- attribute \src "libresoc.v:187072.3-187093.6"
- wire width 64 $2\data_r1__spr1$next[63:0]$12983
- attribute \src "libresoc.v:187072.3-187093.6"
- wire $2\data_r1__spr1_ok$next[0:0]$12984
- attribute \src "libresoc.v:187094.3-187115.6"
- wire width 64 $2\data_r2__fast1$next[63:0]$12991
- attribute \src "libresoc.v:187094.3-187115.6"
- wire $2\data_r2__fast1_ok$next[0:0]$12992
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $2\data_r3__xer_so$next[0:0]$12999
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$13000
- attribute \src "libresoc.v:187138.3-187159.6"
- wire width 2 $2\data_r4__xer_ov$next[1:0]$13007
- attribute \src "libresoc.v:187138.3-187159.6"
- wire $2\data_r4__xer_ov_ok$next[0:0]$13008
- attribute \src "libresoc.v:187160.3-187181.6"
- wire width 2 $2\data_r5__xer_ca$next[1:0]$13015
- attribute \src "libresoc.v:187160.3-187181.6"
- wire $2\data_r5__xer_ca_ok$next[0:0]$13016
- attribute \src "libresoc.v:187050.3-187071.6"
- wire $3\data_r0__o_ok$next[0:0]$12977
- attribute \src "libresoc.v:187072.3-187093.6"
- wire $3\data_r1__spr1_ok$next[0:0]$12985
- attribute \src "libresoc.v:187094.3-187115.6"
- wire $3\data_r2__fast1_ok$next[0:0]$12993
- attribute \src "libresoc.v:187116.3-187137.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$13001
- attribute \src "libresoc.v:187138.3-187159.6"
- wire $3\data_r4__xer_ov_ok$next[0:0]$13009
- attribute \src "libresoc.v:187160.3-187181.6"
- wire $3\data_r5__xer_ca_ok$next[0:0]$13017
- attribute \src "libresoc.v:186720.19-186720.133"
- wire $and$libresoc.v:186720$12828_Y
- attribute \src "libresoc.v:186721.19-186721.183"
- wire width 6 $and$libresoc.v:186721$12829_Y
- attribute \src "libresoc.v:186722.19-186722.115"
- wire width 6 $and$libresoc.v:186722$12830_Y
- attribute \src "libresoc.v:186724.19-186724.115"
- wire width 6 $and$libresoc.v:186724$12832_Y
- attribute \src "libresoc.v:186725.19-186725.125"
- wire $and$libresoc.v:186725$12833_Y
- attribute \src "libresoc.v:186726.19-186726.125"
- wire $and$libresoc.v:186726$12834_Y
- attribute \src "libresoc.v:186727.19-186727.125"
- wire $and$libresoc.v:186727$12835_Y
- attribute \src "libresoc.v:186728.19-186728.125"
- wire $and$libresoc.v:186728$12836_Y
- attribute \src "libresoc.v:186729.19-186729.125"
- wire $and$libresoc.v:186729$12837_Y
- attribute \src "libresoc.v:186731.19-186731.125"
- wire $and$libresoc.v:186731$12839_Y
- attribute \src "libresoc.v:186732.19-186732.165"
- wire width 6 $and$libresoc.v:186732$12840_Y
- attribute \src "libresoc.v:186733.19-186733.121"
- wire width 6 $and$libresoc.v:186733$12841_Y
- attribute \src "libresoc.v:186734.19-186734.127"
- wire $and$libresoc.v:186734$12842_Y
- attribute \src "libresoc.v:186735.19-186735.127"
- wire $and$libresoc.v:186735$12843_Y
- attribute \src "libresoc.v:186737.19-186737.127"
- wire $and$libresoc.v:186737$12845_Y
- attribute \src "libresoc.v:186738.19-186738.127"
- wire $and$libresoc.v:186738$12846_Y
- attribute \src "libresoc.v:186739.19-186739.127"
- wire $and$libresoc.v:186739$12847_Y
- attribute \src "libresoc.v:186740.19-186740.127"
- wire $and$libresoc.v:186740$12848_Y
- attribute \src "libresoc.v:186741.18-186741.110"
- wire $and$libresoc.v:186741$12849_Y
- attribute \src "libresoc.v:186743.18-186743.98"
- wire $and$libresoc.v:186743$12851_Y
- attribute \src "libresoc.v:186745.18-186745.100"
- wire $and$libresoc.v:186745$12853_Y
- attribute \src "libresoc.v:186746.18-186746.182"
- wire width 6 $and$libresoc.v:186746$12854_Y
- attribute \src "libresoc.v:186748.18-186748.119"
- wire width 6 $and$libresoc.v:186748$12856_Y
- attribute \src "libresoc.v:186751.18-186751.116"
- wire $and$libresoc.v:186751$12859_Y
- attribute \src "libresoc.v:186756.18-186756.113"
- wire $and$libresoc.v:186756$12864_Y
- attribute \src "libresoc.v:186757.18-186757.125"
- wire width 6 $and$libresoc.v:186757$12865_Y
- attribute \src "libresoc.v:186759.18-186759.112"
- wire $and$libresoc.v:186759$12867_Y
- attribute \src "libresoc.v:186761.18-186761.126"
- wire $and$libresoc.v:186761$12869_Y
- attribute \src "libresoc.v:186762.18-186762.126"
- wire $and$libresoc.v:186762$12870_Y
- attribute \src "libresoc.v:186763.18-186763.117"
- wire $and$libresoc.v:186763$12871_Y
- attribute \src "libresoc.v:186768.18-186768.130"
- wire $and$libresoc.v:186768$12876_Y
- attribute \src "libresoc.v:186769.17-186769.123"
- wire $and$libresoc.v:186769$12877_Y
- attribute \src "libresoc.v:186770.18-186770.124"
- wire width 6 $and$libresoc.v:186770$12878_Y
- attribute \src "libresoc.v:186772.18-186772.116"
- wire $and$libresoc.v:186772$12880_Y
- attribute \src "libresoc.v:186773.18-186773.119"
- wire $and$libresoc.v:186773$12881_Y
- attribute \src "libresoc.v:186774.18-186774.120"
- wire $and$libresoc.v:186774$12882_Y
- attribute \src "libresoc.v:186775.18-186775.121"
- wire $and$libresoc.v:186775$12883_Y
- attribute \src "libresoc.v:186776.18-186776.121"
- wire $and$libresoc.v:186776$12884_Y
- attribute \src "libresoc.v:186777.18-186777.121"
- wire $and$libresoc.v:186777$12885_Y
- attribute \src "libresoc.v:186784.18-186784.134"
- wire $and$libresoc.v:186784$12892_Y
- attribute \src "libresoc.v:186758.18-186758.113"
- wire $eq$libresoc.v:186758$12866_Y
- attribute \src "libresoc.v:186760.18-186760.119"
- wire $eq$libresoc.v:186760$12868_Y
- attribute \src "libresoc.v:186719.17-186719.113"
- wire width 6 $not$libresoc.v:186719$12827_Y
- attribute \src "libresoc.v:186723.19-186723.115"
- wire width 6 $not$libresoc.v:186723$12831_Y
- attribute \src "libresoc.v:186742.18-186742.97"
- wire $not$libresoc.v:186742$12850_Y
- attribute \src "libresoc.v:186744.18-186744.99"
- wire $not$libresoc.v:186744$12852_Y
- attribute \src "libresoc.v:186747.18-186747.113"
- wire width 6 $not$libresoc.v:186747$12855_Y
- attribute \src "libresoc.v:186750.18-186750.106"
- wire $not$libresoc.v:186750$12858_Y
- attribute \src "libresoc.v:186755.18-186755.120"
- wire $not$libresoc.v:186755$12863_Y
- attribute \src "libresoc.v:186730.18-186730.118"
- wire width 6 $or$libresoc.v:186730$12838_Y
- attribute \src "libresoc.v:186754.18-186754.112"
- wire $or$libresoc.v:186754$12862_Y
- attribute \src "libresoc.v:186764.18-186764.122"
- wire $or$libresoc.v:186764$12872_Y
- attribute \src "libresoc.v:186765.18-186765.124"
- wire $or$libresoc.v:186765$12873_Y
- attribute \src "libresoc.v:186766.18-186766.194"
- wire width 6 $or$libresoc.v:186766$12874_Y
- attribute \src "libresoc.v:186767.18-186767.194"
- wire width 6 $or$libresoc.v:186767$12875_Y
- attribute \src "libresoc.v:186771.18-186771.120"
- wire width 6 $or$libresoc.v:186771$12879_Y
- attribute \src "libresoc.v:186736.17-186736.105"
- wire $reduce_and$libresoc.v:186736$12844_Y
- attribute \src "libresoc.v:186749.18-186749.106"
- wire $reduce_or$libresoc.v:186749$12857_Y
- attribute \src "libresoc.v:186752.18-186752.113"
- wire $reduce_or$libresoc.v:186752$12860_Y
- attribute \src "libresoc.v:186753.18-186753.112"
- wire $reduce_or$libresoc.v:186753$12861_Y
- attribute \src "libresoc.v:186778.18-186778.118"
- wire width 64 $ternary$libresoc.v:186778$12886_Y
- attribute \src "libresoc.v:186779.18-186779.118"
- wire width 64 $ternary$libresoc.v:186779$12887_Y
- attribute \src "libresoc.v:186780.18-186780.118"
- wire width 64 $ternary$libresoc.v:186780$12888_Y
- attribute \src "libresoc.v:186781.18-186781.118"
- wire $ternary$libresoc.v:186781$12889_Y
- attribute \src "libresoc.v:186782.18-186782.118"
- wire width 2 $ternary$libresoc.v:186782$12890_Y
- attribute \src "libresoc.v:186783.18-186783.118"
- wire width 2 $ternary$libresoc.v:186783$12891_Y
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire width 64 $2\data_r0__o$next[63:0]$12883
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire $2\data_r0__o_ok$next[0:0]$12884
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire width 64 $2\data_r1__spr1$next[63:0]$12891
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire $2\data_r1__spr1_ok$next[0:0]$12892
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire width 64 $2\data_r2__fast1$next[63:0]$12899
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire $2\data_r2__fast1_ok$next[0:0]$12900
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $2\data_r3__xer_so$next[0:0]$12907
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$12908
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire width 2 $2\data_r4__xer_ov$next[1:0]$12915
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire $2\data_r4__xer_ov_ok$next[0:0]$12916
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire width 2 $2\data_r5__xer_ca$next[1:0]$12923
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire $2\data_r5__xer_ca_ok$next[0:0]$12924
+ attribute \src "libresoc.v:184803.3-184824.6"
+ wire $3\data_r0__o_ok$next[0:0]$12885
+ attribute \src "libresoc.v:184825.3-184846.6"
+ wire $3\data_r1__spr1_ok$next[0:0]$12893
+ attribute \src "libresoc.v:184847.3-184868.6"
+ wire $3\data_r2__fast1_ok$next[0:0]$12901
+ attribute \src "libresoc.v:184869.3-184890.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$12909
+ attribute \src "libresoc.v:184891.3-184912.6"
+ wire $3\data_r4__xer_ov_ok$next[0:0]$12917
+ attribute \src "libresoc.v:184913.3-184934.6"
+ wire $3\data_r5__xer_ca_ok$next[0:0]$12925
+ attribute \src "libresoc.v:184473.19-184473.133"
+ wire $and$libresoc.v:184473$12736_Y
+ attribute \src "libresoc.v:184474.19-184474.183"
+ wire width 6 $and$libresoc.v:184474$12737_Y
+ attribute \src "libresoc.v:184475.19-184475.115"
+ wire width 6 $and$libresoc.v:184475$12738_Y
+ attribute \src "libresoc.v:184477.19-184477.115"
+ wire width 6 $and$libresoc.v:184477$12740_Y
+ attribute \src "libresoc.v:184478.19-184478.125"
+ wire $and$libresoc.v:184478$12741_Y
+ attribute \src "libresoc.v:184479.19-184479.125"
+ wire $and$libresoc.v:184479$12742_Y
+ attribute \src "libresoc.v:184480.19-184480.125"
+ wire $and$libresoc.v:184480$12743_Y
+ attribute \src "libresoc.v:184481.19-184481.125"
+ wire $and$libresoc.v:184481$12744_Y
+ attribute \src "libresoc.v:184482.19-184482.125"
+ wire $and$libresoc.v:184482$12745_Y
+ attribute \src "libresoc.v:184484.19-184484.125"
+ wire $and$libresoc.v:184484$12747_Y
+ attribute \src "libresoc.v:184485.19-184485.165"
+ wire width 6 $and$libresoc.v:184485$12748_Y
+ attribute \src "libresoc.v:184486.19-184486.121"
+ wire width 6 $and$libresoc.v:184486$12749_Y
+ attribute \src "libresoc.v:184487.19-184487.127"
+ wire $and$libresoc.v:184487$12750_Y
+ attribute \src "libresoc.v:184488.19-184488.127"
+ wire $and$libresoc.v:184488$12751_Y
+ attribute \src "libresoc.v:184490.19-184490.127"
+ wire $and$libresoc.v:184490$12753_Y
+ attribute \src "libresoc.v:184491.19-184491.127"
+ wire $and$libresoc.v:184491$12754_Y
+ attribute \src "libresoc.v:184492.19-184492.127"
+ wire $and$libresoc.v:184492$12755_Y
+ attribute \src "libresoc.v:184493.19-184493.127"
+ wire $and$libresoc.v:184493$12756_Y
+ attribute \src "libresoc.v:184494.18-184494.110"
+ wire $and$libresoc.v:184494$12757_Y
+ attribute \src "libresoc.v:184496.18-184496.98"
+ wire $and$libresoc.v:184496$12759_Y
+ attribute \src "libresoc.v:184498.18-184498.100"
+ wire $and$libresoc.v:184498$12761_Y
+ attribute \src "libresoc.v:184499.18-184499.182"
+ wire width 6 $and$libresoc.v:184499$12762_Y
+ attribute \src "libresoc.v:184501.18-184501.119"
+ wire width 6 $and$libresoc.v:184501$12764_Y
+ attribute \src "libresoc.v:184504.18-184504.116"
+ wire $and$libresoc.v:184504$12767_Y
+ attribute \src "libresoc.v:184509.18-184509.113"
+ wire $and$libresoc.v:184509$12772_Y
+ attribute \src "libresoc.v:184510.18-184510.125"
+ wire width 6 $and$libresoc.v:184510$12773_Y
+ attribute \src "libresoc.v:184512.18-184512.112"
+ wire $and$libresoc.v:184512$12775_Y
+ attribute \src "libresoc.v:184514.18-184514.126"
+ wire $and$libresoc.v:184514$12777_Y
+ attribute \src "libresoc.v:184515.18-184515.126"
+ wire $and$libresoc.v:184515$12778_Y
+ attribute \src "libresoc.v:184516.18-184516.117"
+ wire $and$libresoc.v:184516$12779_Y
+ attribute \src "libresoc.v:184521.18-184521.130"
+ wire $and$libresoc.v:184521$12784_Y
+ attribute \src "libresoc.v:184522.17-184522.123"
+ wire $and$libresoc.v:184522$12785_Y
+ attribute \src "libresoc.v:184523.18-184523.124"
+ wire width 6 $and$libresoc.v:184523$12786_Y
+ attribute \src "libresoc.v:184525.18-184525.116"
+ wire $and$libresoc.v:184525$12788_Y
+ attribute \src "libresoc.v:184526.18-184526.119"
+ wire $and$libresoc.v:184526$12789_Y
+ attribute \src "libresoc.v:184527.18-184527.120"
+ wire $and$libresoc.v:184527$12790_Y
+ attribute \src "libresoc.v:184528.18-184528.121"
+ wire $and$libresoc.v:184528$12791_Y
+ attribute \src "libresoc.v:184529.18-184529.121"
+ wire $and$libresoc.v:184529$12792_Y
+ attribute \src "libresoc.v:184530.18-184530.121"
+ wire $and$libresoc.v:184530$12793_Y
+ attribute \src "libresoc.v:184537.18-184537.134"
+ wire $and$libresoc.v:184537$12800_Y
+ attribute \src "libresoc.v:184511.18-184511.113"
+ wire $eq$libresoc.v:184511$12774_Y
+ attribute \src "libresoc.v:184513.18-184513.119"
+ wire $eq$libresoc.v:184513$12776_Y
+ attribute \src "libresoc.v:184472.17-184472.113"
+ wire width 6 $not$libresoc.v:184472$12735_Y
+ attribute \src "libresoc.v:184476.19-184476.115"
+ wire width 6 $not$libresoc.v:184476$12739_Y
+ attribute \src "libresoc.v:184495.18-184495.97"
+ wire $not$libresoc.v:184495$12758_Y
+ attribute \src "libresoc.v:184497.18-184497.99"
+ wire $not$libresoc.v:184497$12760_Y
+ attribute \src "libresoc.v:184500.18-184500.113"
+ wire width 6 $not$libresoc.v:184500$12763_Y
+ attribute \src "libresoc.v:184503.18-184503.106"
+ wire $not$libresoc.v:184503$12766_Y
+ attribute \src "libresoc.v:184508.18-184508.120"
+ wire $not$libresoc.v:184508$12771_Y
+ attribute \src "libresoc.v:184483.18-184483.118"
+ wire width 6 $or$libresoc.v:184483$12746_Y
+ attribute \src "libresoc.v:184507.18-184507.112"
+ wire $or$libresoc.v:184507$12770_Y
+ attribute \src "libresoc.v:184517.18-184517.122"
+ wire $or$libresoc.v:184517$12780_Y
+ attribute \src "libresoc.v:184518.18-184518.124"
+ wire $or$libresoc.v:184518$12781_Y
+ attribute \src "libresoc.v:184519.18-184519.194"
+ wire width 6 $or$libresoc.v:184519$12782_Y
+ attribute \src "libresoc.v:184520.18-184520.194"
+ wire width 6 $or$libresoc.v:184520$12783_Y
+ attribute \src "libresoc.v:184524.18-184524.120"
+ wire width 6 $or$libresoc.v:184524$12787_Y
+ attribute \src "libresoc.v:184489.17-184489.105"
+ wire $reduce_and$libresoc.v:184489$12752_Y
+ attribute \src "libresoc.v:184502.18-184502.106"
+ wire $reduce_or$libresoc.v:184502$12765_Y
+ attribute \src "libresoc.v:184505.18-184505.113"
+ wire $reduce_or$libresoc.v:184505$12768_Y
+ attribute \src "libresoc.v:184506.18-184506.112"
+ wire $reduce_or$libresoc.v:184506$12769_Y
+ attribute \src "libresoc.v:184531.18-184531.118"
+ wire width 64 $ternary$libresoc.v:184531$12794_Y
+ attribute \src "libresoc.v:184532.18-184532.118"
+ wire width 64 $ternary$libresoc.v:184532$12795_Y
+ attribute \src "libresoc.v:184533.18-184533.118"
+ wire width 64 $ternary$libresoc.v:184533$12796_Y
+ attribute \src "libresoc.v:184534.18-184534.118"
+ wire $ternary$libresoc.v:184534$12797_Y
+ attribute \src "libresoc.v:184535.18-184535.118"
+ wire width 2 $ternary$libresoc.v:184535$12798_Y
+ attribute \src "libresoc.v:184536.18-184536.118"
+ wire width 2 $ternary$libresoc.v:184536$12799_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
wire \$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 7 \cu_busy_o
wire width 2 output 22 \dest6_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 27 \fast1_ok
- attribute \src "libresoc.v:186112.7-186112.15"
+ attribute \src "libresoc.v:183865.7-183865.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 17 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 25 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:186720$12828
+ cell $and $and$libresoc.v:184473$12736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:186720$12828_Y
+ connect \Y $and$libresoc.v:184473$12736_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:186721$12829
+ cell $and $and$libresoc.v:184474$12737
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:186721$12829_Y
+ connect \Y $and$libresoc.v:184474$12737_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:186722$12830
+ cell $and $and$libresoc.v:184475$12738
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$102
connect \B 6'111111
- connect \Y $and$libresoc.v:186722$12830_Y
+ connect \Y $and$libresoc.v:184475$12738_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:186724$12832
+ cell $and $and$libresoc.v:184477$12740
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$104
connect \B \$106
- connect \Y $and$libresoc.v:186724$12832_Y
+ connect \Y $and$libresoc.v:184477$12740_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186725$12833
+ cell $and $and$libresoc.v:184478$12741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186725$12833_Y
+ connect \Y $and$libresoc.v:184478$12741_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186726$12834
+ cell $and $and$libresoc.v:184479$12742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186726$12834_Y
+ connect \Y $and$libresoc.v:184479$12742_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186727$12835
+ cell $and $and$libresoc.v:184480$12743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186727$12835_Y
+ connect \Y $and$libresoc.v:184480$12743_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186728$12836
+ cell $and $and$libresoc.v:184481$12744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186728$12836_Y
+ connect \Y $and$libresoc.v:184481$12744_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186729$12837
+ cell $and $and$libresoc.v:184482$12745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186729$12837_Y
+ connect \Y $and$libresoc.v:184482$12745_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:186731$12839
+ cell $and $and$libresoc.v:184484$12747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:186731$12839_Y
+ connect \Y $and$libresoc.v:184484$12747_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:186732$12840
+ cell $and $and$libresoc.v:184485$12748
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B { \$110 \$112 \$114 \$116 \$118 \$120 }
- connect \Y $and$libresoc.v:186732$12840_Y
+ connect \Y $and$libresoc.v:184485$12748_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:186733$12841
+ cell $and $and$libresoc.v:184486$12749
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$122
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:186733$12841_Y
+ connect \Y $and$libresoc.v:184486$12749_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186734$12842
+ cell $and $and$libresoc.v:184487$12750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186734$12842_Y
+ connect \Y $and$libresoc.v:184487$12750_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186735$12843
+ cell $and $and$libresoc.v:184488$12751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186735$12843_Y
+ connect \Y $and$libresoc.v:184488$12751_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186737$12845
+ cell $and $and$libresoc.v:184490$12753
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186737$12845_Y
+ connect \Y $and$libresoc.v:184490$12753_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186738$12846
+ cell $and $and$libresoc.v:184491$12754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186738$12846_Y
+ connect \Y $and$libresoc.v:184491$12754_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186739$12847
+ cell $and $and$libresoc.v:184492$12755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186739$12847_Y
+ connect \Y $and$libresoc.v:184492$12755_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:186740$12848
+ cell $and $and$libresoc.v:184493$12756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [5]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186740$12848_Y
+ connect \Y $and$libresoc.v:184493$12756_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:186741$12849
+ cell $and $and$libresoc.v:184494$12757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$6
connect \B \$8
- connect \Y $and$libresoc.v:186741$12849_Y
+ connect \Y $and$libresoc.v:184494$12757_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:186743$12851
+ cell $and $and$libresoc.v:184496$12759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$16
- connect \Y $and$libresoc.v:186743$12851_Y
+ connect \Y $and$libresoc.v:184496$12759_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:186745$12853
+ cell $and $and$libresoc.v:184498$12761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$20
- connect \Y $and$libresoc.v:186745$12853_Y
+ connect \Y $and$libresoc.v:184498$12761_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:186746$12854
+ cell $and $and$libresoc.v:184499$12762
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:186746$12854_Y
+ connect \Y $and$libresoc.v:184499$12762_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:186748$12856
+ cell $and $and$libresoc.v:184501$12764
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__rel_o
connect \B \$28
- connect \Y $and$libresoc.v:186748$12856_Y
+ connect \Y $and$libresoc.v:184501$12764_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:186751$12859
+ cell $and $and$libresoc.v:184504$12767
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$26
- connect \Y $and$libresoc.v:186751$12859_Y
+ connect \Y $and$libresoc.v:184504$12767_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:186756$12864
+ cell $and $and$libresoc.v:184509$12772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$42
- connect \Y $and$libresoc.v:186756$12864_Y
+ connect \Y $and$libresoc.v:184509$12772_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:186757$12865
+ cell $and $and$libresoc.v:184510$12773
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:186757$12865_Y
+ connect \Y $and$libresoc.v:184510$12773_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:186759$12867
+ cell $and $and$libresoc.v:184512$12775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$48
- connect \Y $and$libresoc.v:186759$12867_Y
+ connect \Y $and$libresoc.v:184512$12775_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:186761$12869
+ cell $and $and$libresoc.v:184514$12777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \alu_spr0_n_ready_i
- connect \Y $and$libresoc.v:186761$12869_Y
+ connect \Y $and$libresoc.v:184514$12777_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:186762$12870
+ cell $and $and$libresoc.v:184515$12778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$54
connect \B \alu_spr0_n_valid_o
- connect \Y $and$libresoc.v:186762$12870_Y
+ connect \Y $and$libresoc.v:184515$12778_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:186763$12871
+ cell $and $and$libresoc.v:184516$12779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$56
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186763$12871_Y
+ connect \Y $and$libresoc.v:184516$12779_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:186768$12876
+ cell $and $and$libresoc.v:184521$12784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186768$12876_Y
+ connect \Y $and$libresoc.v:184521$12784_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:186769$12877
+ cell $and $and$libresoc.v:184522$12785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:186769$12877_Y
+ connect \Y $and$libresoc.v:184522$12785_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:186770$12878
+ cell $and $and$libresoc.v:184523$12786
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:186770$12878_Y
+ connect \Y $and$libresoc.v:184523$12786_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186772$12880
+ cell $and $and$libresoc.v:184525$12788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186772$12880_Y
+ connect \Y $and$libresoc.v:184525$12788_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186773$12881
+ cell $and $and$libresoc.v:184526$12789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186773$12881_Y
+ connect \Y $and$libresoc.v:184526$12789_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186774$12882
+ cell $and $and$libresoc.v:184527$12790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186774$12882_Y
+ connect \Y $and$libresoc.v:184527$12790_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186775$12883
+ cell $and $and$libresoc.v:184528$12791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186775$12883_Y
+ connect \Y $and$libresoc.v:184528$12791_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186776$12884
+ cell $and $and$libresoc.v:184529$12792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186776$12884_Y
+ connect \Y $and$libresoc.v:184529$12792_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:186777$12885
+ cell $and $and$libresoc.v:184530$12793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ca_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:186777$12885_Y
+ connect \Y $and$libresoc.v:184530$12793_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:186784$12892
+ cell $and $and$libresoc.v:184537$12800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:186784$12892_Y
+ connect \Y $and$libresoc.v:184537$12800_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:186758$12866
+ cell $eq $eq$libresoc.v:184511$12774
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$46
connect \B 1'0
- connect \Y $eq$libresoc.v:186758$12866_Y
+ connect \Y $eq$libresoc.v:184511$12774_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:186760$12868
+ cell $eq $eq$libresoc.v:184513$12776
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:186760$12868_Y
+ connect \Y $eq$libresoc.v:184513$12776_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:186719$12827
+ cell $not $not$libresoc.v:184472$12735
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:186719$12827_Y
+ connect \Y $not$libresoc.v:184472$12735_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:186723$12831
+ cell $not $not$libresoc.v:184476$12739
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:186723$12831_Y
+ connect \Y $not$libresoc.v:184476$12739_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:186742$12850
+ cell $not $not$libresoc.v:184495$12758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:186742$12850_Y
+ connect \Y $not$libresoc.v:184495$12758_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:186744$12852
+ cell $not $not$libresoc.v:184497$12760
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:186744$12852_Y
+ connect \Y $not$libresoc.v:184497$12760_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:186747$12855
+ cell $not $not$libresoc.v:184500$12763
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:186747$12855_Y
+ connect \Y $not$libresoc.v:184500$12763_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:186750$12858
+ cell $not $not$libresoc.v:184503$12766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $not$libresoc.v:186750$12858_Y
+ connect \Y $not$libresoc.v:184503$12766_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:186755$12863
+ cell $not $not$libresoc.v:184508$12771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_ready_i
- connect \Y $not$libresoc.v:186755$12863_Y
+ connect \Y $not$libresoc.v:184508$12771_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:186730$12838
+ cell $or $or$libresoc.v:184483$12746
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:186730$12838_Y
+ connect \Y $or$libresoc.v:184483$12746_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:186754$12862
+ cell $or $or$libresoc.v:184507$12770
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \$38
- connect \Y $or$libresoc.v:186754$12862_Y
+ connect \Y $or$libresoc.v:184507$12770_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:186764$12872
+ cell $or $or$libresoc.v:184517$12780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:186764$12872_Y
+ connect \Y $or$libresoc.v:184517$12780_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:186765$12873
+ cell $or $or$libresoc.v:184518$12781
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:186765$12873_Y
+ connect \Y $or$libresoc.v:184518$12781_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:186766$12874
+ cell $or $or$libresoc.v:184519$12782
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:186766$12874_Y
+ connect \Y $or$libresoc.v:184519$12782_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:186767$12875
+ cell $or $or$libresoc.v:184520$12783
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:186767$12875_Y
+ connect \Y $or$libresoc.v:184520$12783_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:186771$12879
+ cell $or $or$libresoc.v:184524$12787
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:186771$12879_Y
+ connect \Y $or$libresoc.v:184524$12787_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:186736$12844
+ cell $reduce_and $reduce_and$libresoc.v:184489$12752
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$11
- connect \Y $reduce_and$libresoc.v:186736$12844_Y
+ connect \Y $reduce_and$libresoc.v:184489$12752_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:186749$12857
+ cell $reduce_or $reduce_or$libresoc.v:184502$12765
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$30
- connect \Y $reduce_or$libresoc.v:186749$12857_Y
+ connect \Y $reduce_or$libresoc.v:184502$12765_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:186752$12860
+ cell $reduce_or $reduce_or$libresoc.v:184505$12768
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:186752$12860_Y
+ connect \Y $reduce_or$libresoc.v:184505$12768_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:186753$12861
+ cell $reduce_or $reduce_or$libresoc.v:184506$12769
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:186753$12861_Y
+ connect \Y $reduce_or$libresoc.v:184506$12769_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186778$12886
+ cell $mux $ternary$libresoc.v:184531$12794
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:186778$12886_Y
+ connect \Y $ternary$libresoc.v:184531$12794_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186779$12887
+ cell $mux $ternary$libresoc.v:184532$12795
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:186779$12887_Y
+ connect \Y $ternary$libresoc.v:184532$12795_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186780$12888
+ cell $mux $ternary$libresoc.v:184533$12796
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:186780$12888_Y
+ connect \Y $ternary$libresoc.v:184533$12796_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186781$12889
+ cell $mux $ternary$libresoc.v:184534$12797
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:186781$12889_Y
+ connect \Y $ternary$libresoc.v:184534$12797_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186782$12890
+ cell $mux $ternary$libresoc.v:184535$12798
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:186782$12890_Y
+ connect \Y $ternary$libresoc.v:184535$12798_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:186783$12891
+ cell $mux $ternary$libresoc.v:184536$12799
parameter \WIDTH 2
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $ternary$libresoc.v:186783$12891_Y
+ connect \Y $ternary$libresoc.v:184536$12799_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186859.14-186865.4"
+ attribute \src "libresoc.v:184612.14-184618.4"
cell \alu_l$73 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186866.12-186895.4"
+ attribute \src "libresoc.v:184619.12-184648.4"
cell \alu_spr0 \alu_spr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186896.15-186902.4"
+ attribute \src "libresoc.v:184649.15-184655.4"
cell \alui_l$72 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186903.14-186909.4"
+ attribute \src "libresoc.v:184656.14-184662.4"
cell \opc_l$68 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186910.14-186916.4"
+ attribute \src "libresoc.v:184663.14-184669.4"
cell \req_l$69 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186917.14-186923.4"
+ attribute \src "libresoc.v:184670.14-184676.4"
cell \rok_l$71 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186924.14-186929.4"
+ attribute \src "libresoc.v:184677.14-184682.4"
cell \rst_l$70 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:186930.14-186936.4"
+ attribute \src "libresoc.v:184683.14-184689.4"
cell \src_l$67 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:186112.7-186112.20"
- process $proc$libresoc.v:186112$13051
+ attribute \src "libresoc.v:183865.7-183865.20"
+ process $proc$libresoc.v:183865$12959
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:186248.7-186248.24"
- process $proc$libresoc.v:186248$13052
+ attribute \src "libresoc.v:184001.7-184001.24"
+ process $proc$libresoc.v:184001$12960
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:186258.7-186258.26"
- process $proc$libresoc.v:186258$13053
+ attribute \src "libresoc.v:184011.7-184011.26"
+ process $proc$libresoc.v:184011$12961
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:186266.7-186266.25"
- process $proc$libresoc.v:186266$13054
+ attribute \src "libresoc.v:184019.7-184019.25"
+ process $proc$libresoc.v:184019$12962
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:186310.14-186310.49"
- process $proc$libresoc.v:186310$13055
+ attribute \src "libresoc.v:184063.14-184063.49"
+ process $proc$libresoc.v:184063$12963
assign { } { }
assign $1\alu_spr0_spr_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:186314.14-186314.43"
- process $proc$libresoc.v:186314$13056
+ attribute \src "libresoc.v:184067.14-184067.43"
+ process $proc$libresoc.v:184067$12964
assign { } { }
assign $1\alu_spr0_spr_op__insn[31:0] 0
sync always
sync init
update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:186392.13-186392.47"
- process $proc$libresoc.v:186392$13057
+ attribute \src "libresoc.v:184145.13-184145.47"
+ process $proc$libresoc.v:184145$12965
assign { } { }
assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:186396.7-186396.39"
- process $proc$libresoc.v:186396$13058
+ attribute \src "libresoc.v:184149.7-184149.39"
+ process $proc$libresoc.v:184149$12966
assign { } { }
assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:186414.7-186414.27"
- process $proc$libresoc.v:186414$13059
+ attribute \src "libresoc.v:184167.7-184167.27"
+ process $proc$libresoc.v:184167$12967
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:186446.14-186446.47"
- process $proc$libresoc.v:186446$13060
+ attribute \src "libresoc.v:184199.14-184199.47"
+ process $proc$libresoc.v:184199$12968
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:186450.7-186450.27"
- process $proc$libresoc.v:186450$13061
+ attribute \src "libresoc.v:184203.7-184203.27"
+ process $proc$libresoc.v:184203$12969
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:186454.14-186454.50"
- process $proc$libresoc.v:186454$13062
+ attribute \src "libresoc.v:184207.14-184207.50"
+ process $proc$libresoc.v:184207$12970
assign { } { }
assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__spr1 $1\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:186458.7-186458.30"
- process $proc$libresoc.v:186458$13063
+ attribute \src "libresoc.v:184211.7-184211.30"
+ process $proc$libresoc.v:184211$12971
assign { } { }
assign $1\data_r1__spr1_ok[0:0] 1'0
sync always
sync init
update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:186462.14-186462.51"
- process $proc$libresoc.v:186462$13064
+ attribute \src "libresoc.v:184215.14-184215.51"
+ process $proc$libresoc.v:184215$12972
assign { } { }
assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast1 $1\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:186466.7-186466.31"
- process $proc$libresoc.v:186466$13065
+ attribute \src "libresoc.v:184219.7-184219.31"
+ process $proc$libresoc.v:184219$12973
assign { } { }
assign $1\data_r2__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:186470.7-186470.29"
- process $proc$libresoc.v:186470$13066
+ attribute \src "libresoc.v:184223.7-184223.29"
+ process $proc$libresoc.v:184223$12974
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:186474.7-186474.32"
- process $proc$libresoc.v:186474$13067
+ attribute \src "libresoc.v:184227.7-184227.32"
+ process $proc$libresoc.v:184227$12975
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:186478.13-186478.35"
- process $proc$libresoc.v:186478$13068
+ attribute \src "libresoc.v:184231.13-184231.35"
+ process $proc$libresoc.v:184231$12976
assign { } { }
assign $1\data_r4__xer_ov[1:0] 2'00
sync always
sync init
update \data_r4__xer_ov $1\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:186482.7-186482.32"
- process $proc$libresoc.v:186482$13069
+ attribute \src "libresoc.v:184235.7-184235.32"
+ process $proc$libresoc.v:184235$12977
assign { } { }
assign $1\data_r4__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:186486.13-186486.35"
- process $proc$libresoc.v:186486$13070
+ attribute \src "libresoc.v:184239.13-184239.35"
+ process $proc$libresoc.v:184239$12978
assign { } { }
assign $1\data_r5__xer_ca[1:0] 2'00
sync always
sync init
update \data_r5__xer_ca $1\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:186490.7-186490.32"
- process $proc$libresoc.v:186490$13071
+ attribute \src "libresoc.v:184243.7-184243.32"
+ process $proc$libresoc.v:184243$12979
assign { } { }
assign $1\data_r5__xer_ca_ok[0:0] 1'0
sync always
sync init
update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:186518.7-186518.25"
- process $proc$libresoc.v:186518$13072
+ attribute \src "libresoc.v:184271.7-184271.25"
+ process $proc$libresoc.v:184271$12980
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:186522.7-186522.25"
- process $proc$libresoc.v:186522$13073
+ attribute \src "libresoc.v:184275.7-184275.25"
+ process $proc$libresoc.v:184275$12981
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:186622.13-186622.31"
- process $proc$libresoc.v:186622$13074
+ attribute \src "libresoc.v:184375.13-184375.31"
+ process $proc$libresoc.v:184375$12982
assign { } { }
assign $1\prev_wr_go[5:0] 6'000000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:186630.13-186630.32"
- process $proc$libresoc.v:186630$13075
+ attribute \src "libresoc.v:184383.13-184383.32"
+ process $proc$libresoc.v:184383$12983
assign { } { }
assign $1\req_l_r_req[5:0] 6'111111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:186634.13-186634.32"
- process $proc$libresoc.v:186634$13076
+ attribute \src "libresoc.v:184387.13-184387.32"
+ process $proc$libresoc.v:184387$12984
assign { } { }
assign $1\req_l_s_req[5:0] 6'000000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:186646.7-186646.26"
- process $proc$libresoc.v:186646$13077
+ attribute \src "libresoc.v:184399.7-184399.26"
+ process $proc$libresoc.v:184399$12985
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:186650.7-186650.26"
- process $proc$libresoc.v:186650$13078
+ attribute \src "libresoc.v:184403.7-184403.26"
+ process $proc$libresoc.v:184403$12986
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:186654.7-186654.25"
- process $proc$libresoc.v:186654$13079
+ attribute \src "libresoc.v:184407.7-184407.25"
+ process $proc$libresoc.v:184407$12987
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:186658.7-186658.25"
- process $proc$libresoc.v:186658$13080
+ attribute \src "libresoc.v:184411.7-184411.25"
+ process $proc$libresoc.v:184411$12988
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:186680.13-186680.32"
- process $proc$libresoc.v:186680$13081
+ attribute \src "libresoc.v:184433.13-184433.32"
+ process $proc$libresoc.v:184433$12989
assign { } { }
assign $1\src_l_r_src[5:0] 6'111111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:186684.13-186684.32"
- process $proc$libresoc.v:186684$13082
+ attribute \src "libresoc.v:184437.13-184437.32"
+ process $proc$libresoc.v:184437$12990
assign { } { }
assign $1\src_l_s_src[5:0] 6'000000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:186688.14-186688.43"
- process $proc$libresoc.v:186688$13083
+ attribute \src "libresoc.v:184441.14-184441.43"
+ process $proc$libresoc.v:184441$12991
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:186692.14-186692.43"
- process $proc$libresoc.v:186692$13084
+ attribute \src "libresoc.v:184445.14-184445.43"
+ process $proc$libresoc.v:184445$12992
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:186696.14-186696.43"
- process $proc$libresoc.v:186696$13085
+ attribute \src "libresoc.v:184449.14-184449.43"
+ process $proc$libresoc.v:184449$12993
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:186700.7-186700.20"
- process $proc$libresoc.v:186700$13086
+ attribute \src "libresoc.v:184453.7-184453.20"
+ process $proc$libresoc.v:184453$12994
assign { } { }
assign $1\src_r3[0:0] 1'0
sync always
sync init
update \src_r3 $1\src_r3[0:0]
end
- attribute \src "libresoc.v:186704.13-186704.26"
- process $proc$libresoc.v:186704$13087
+ attribute \src "libresoc.v:184457.13-184457.26"
+ process $proc$libresoc.v:184457$12995
assign { } { }
assign $1\src_r4[1:0] 2'00
sync always
sync init
update \src_r4 $1\src_r4[1:0]
end
- attribute \src "libresoc.v:186708.13-186708.26"
- process $proc$libresoc.v:186708$13088
+ attribute \src "libresoc.v:184461.13-184461.26"
+ process $proc$libresoc.v:184461$12996
assign { } { }
assign $1\src_r5[1:0] 2'00
sync always
sync init
update \src_r5 $1\src_r5[1:0]
end
- attribute \src "libresoc.v:186785.3-186786.39"
- process $proc$libresoc.v:186785$12893
+ attribute \src "libresoc.v:184538.3-184539.39"
+ process $proc$libresoc.v:184538$12801
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:186787.3-186788.43"
- process $proc$libresoc.v:186787$12894
+ attribute \src "libresoc.v:184540.3-184541.43"
+ process $proc$libresoc.v:184540$12802
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:186789.3-186790.29"
- process $proc$libresoc.v:186789$12895
+ attribute \src "libresoc.v:184542.3-184543.29"
+ process $proc$libresoc.v:184542$12803
assign { } { }
assign $0\src_r5[1:0] \src_r5$next
sync posedge \coresync_clk
update \src_r5 $0\src_r5[1:0]
end
- attribute \src "libresoc.v:186791.3-186792.29"
- process $proc$libresoc.v:186791$12896
+ attribute \src "libresoc.v:184544.3-184545.29"
+ process $proc$libresoc.v:184544$12804
assign { } { }
assign $0\src_r4[1:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[1:0]
end
- attribute \src "libresoc.v:186793.3-186794.29"
- process $proc$libresoc.v:186793$12897
+ attribute \src "libresoc.v:184546.3-184547.29"
+ process $proc$libresoc.v:184546$12805
assign { } { }
assign $0\src_r3[0:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[0:0]
end
- attribute \src "libresoc.v:186795.3-186796.29"
- process $proc$libresoc.v:186795$12898
+ attribute \src "libresoc.v:184548.3-184549.29"
+ process $proc$libresoc.v:184548$12806
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:186797.3-186798.29"
- process $proc$libresoc.v:186797$12899
+ attribute \src "libresoc.v:184550.3-184551.29"
+ process $proc$libresoc.v:184550$12807
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:186799.3-186800.29"
- process $proc$libresoc.v:186799$12900
+ attribute \src "libresoc.v:184552.3-184553.29"
+ process $proc$libresoc.v:184552$12808
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:186801.3-186802.47"
- process $proc$libresoc.v:186801$12901
+ attribute \src "libresoc.v:184554.3-184555.47"
+ process $proc$libresoc.v:184554$12809
assign { } { }
assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next
sync posedge \coresync_clk
update \data_r5__xer_ca $0\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:186803.3-186804.53"
- process $proc$libresoc.v:186803$12902
+ attribute \src "libresoc.v:184556.3-184557.53"
+ process $proc$libresoc.v:184556$12810
assign { } { }
assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next
sync posedge \coresync_clk
update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:186805.3-186806.47"
- process $proc$libresoc.v:186805$12903
+ attribute \src "libresoc.v:184558.3-184559.47"
+ process $proc$libresoc.v:184558$12811
assign { } { }
assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next
sync posedge \coresync_clk
update \data_r4__xer_ov $0\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:186807.3-186808.53"
- process $proc$libresoc.v:186807$12904
+ attribute \src "libresoc.v:184560.3-184561.53"
+ process $proc$libresoc.v:184560$12812
assign { } { }
assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:186809.3-186810.47"
- process $proc$libresoc.v:186809$12905
+ attribute \src "libresoc.v:184562.3-184563.47"
+ process $proc$libresoc.v:184562$12813
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:186811.3-186812.53"
- process $proc$libresoc.v:186811$12906
+ attribute \src "libresoc.v:184564.3-184565.53"
+ process $proc$libresoc.v:184564$12814
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:186813.3-186814.45"
- process $proc$libresoc.v:186813$12907
+ attribute \src "libresoc.v:184566.3-184567.45"
+ process $proc$libresoc.v:184566$12815
assign { } { }
assign $0\data_r2__fast1[63:0] \data_r2__fast1$next
sync posedge \coresync_clk
update \data_r2__fast1 $0\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:186815.3-186816.51"
- process $proc$libresoc.v:186815$12908
+ attribute \src "libresoc.v:184568.3-184569.51"
+ process $proc$libresoc.v:184568$12816
assign { } { }
assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next
sync posedge \coresync_clk
update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:186817.3-186818.43"
- process $proc$libresoc.v:186817$12909
+ attribute \src "libresoc.v:184570.3-184571.43"
+ process $proc$libresoc.v:184570$12817
assign { } { }
assign $0\data_r1__spr1[63:0] \data_r1__spr1$next
sync posedge \coresync_clk
update \data_r1__spr1 $0\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:186819.3-186820.49"
- process $proc$libresoc.v:186819$12910
+ attribute \src "libresoc.v:184572.3-184573.49"
+ process $proc$libresoc.v:184572$12818
assign { } { }
assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next
sync posedge \coresync_clk
update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:186821.3-186822.37"
- process $proc$libresoc.v:186821$12911
+ attribute \src "libresoc.v:184574.3-184575.37"
+ process $proc$libresoc.v:184574$12819
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:186823.3-186824.43"
- process $proc$libresoc.v:186823$12912
+ attribute \src "libresoc.v:184576.3-184577.43"
+ process $proc$libresoc.v:184576$12820
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:186825.3-186826.69"
- process $proc$libresoc.v:186825$12913
+ attribute \src "libresoc.v:184578.3-184579.69"
+ process $proc$libresoc.v:184578$12821
assign { } { }
assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:186827.3-186828.65"
- process $proc$libresoc.v:186827$12914
+ attribute \src "libresoc.v:184580.3-184581.65"
+ process $proc$libresoc.v:184580$12822
assign { } { }
assign $0\alu_spr0_spr_op__fn_unit[12:0] \alu_spr0_spr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:186829.3-186830.59"
- process $proc$libresoc.v:186829$12915
+ attribute \src "libresoc.v:184582.3-184583.59"
+ process $proc$libresoc.v:184582$12823
assign { } { }
assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:186831.3-186832.67"
- process $proc$libresoc.v:186831$12916
+ attribute \src "libresoc.v:184584.3-184585.67"
+ process $proc$libresoc.v:184584$12824
assign { } { }
assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:186833.3-186834.39"
- process $proc$libresoc.v:186833$12917
+ attribute \src "libresoc.v:184586.3-184587.39"
+ process $proc$libresoc.v:184586$12825
assign { } { }
assign $0\req_l_r_req[5:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:186835.3-186836.39"
- process $proc$libresoc.v:186835$12918
+ attribute \src "libresoc.v:184588.3-184589.39"
+ process $proc$libresoc.v:184588$12826
assign { } { }
assign $0\req_l_s_req[5:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:186837.3-186838.39"
- process $proc$libresoc.v:186837$12919
+ attribute \src "libresoc.v:184590.3-184591.39"
+ process $proc$libresoc.v:184590$12827
assign { } { }
assign $0\src_l_r_src[5:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:186839.3-186840.39"
- process $proc$libresoc.v:186839$12920
+ attribute \src "libresoc.v:184592.3-184593.39"
+ process $proc$libresoc.v:184592$12828
assign { } { }
assign $0\src_l_s_src[5:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:186841.3-186842.39"
- process $proc$libresoc.v:186841$12921
+ attribute \src "libresoc.v:184594.3-184595.39"
+ process $proc$libresoc.v:184594$12829
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:186843.3-186844.39"
- process $proc$libresoc.v:186843$12922
+ attribute \src "libresoc.v:184596.3-184597.39"
+ process $proc$libresoc.v:184596$12830
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:186845.3-186846.39"
- process $proc$libresoc.v:186845$12923
+ attribute \src "libresoc.v:184598.3-184599.39"
+ process $proc$libresoc.v:184598$12831
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:186847.3-186848.39"
- process $proc$libresoc.v:186847$12924
+ attribute \src "libresoc.v:184600.3-184601.39"
+ process $proc$libresoc.v:184600$12832
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:186849.3-186850.41"
- process $proc$libresoc.v:186849$12925
+ attribute \src "libresoc.v:184602.3-184603.41"
+ process $proc$libresoc.v:184602$12833
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:186851.3-186852.41"
- process $proc$libresoc.v:186851$12926
+ attribute \src "libresoc.v:184604.3-184605.41"
+ process $proc$libresoc.v:184604$12834
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:186853.3-186854.37"
- process $proc$libresoc.v:186853$12927
+ attribute \src "libresoc.v:184606.3-184607.37"
+ process $proc$libresoc.v:184606$12835
assign { } { }
assign $0\prev_wr_go[5:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:186855.3-186856.40"
- process $proc$libresoc.v:186855$12928
+ attribute \src "libresoc.v:184608.3-184609.40"
+ process $proc$libresoc.v:184608$12836
assign { } { }
assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:186857.3-186858.25"
- process $proc$libresoc.v:186857$12929
+ attribute \src "libresoc.v:184610.3-184611.25"
+ process $proc$libresoc.v:184610$12837
assign { } { }
assign $0\all_rd_dly[0:0] \$14
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:186937.3-186946.6"
- process $proc$libresoc.v:186937$12930
+ attribute \src "libresoc.v:184690.3-184699.6"
+ process $proc$libresoc.v:184690$12838
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:186938.5-186938.29"
+ attribute \src "libresoc.v:184691.5-184691.29"
switch \initial
- attribute \src "libresoc.v:186938.9-186938.17"
+ attribute \src "libresoc.v:184691.9-184691.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:186947.3-186955.6"
- process $proc$libresoc.v:186947$12931
+ attribute \src "libresoc.v:184700.3-184708.6"
+ process $proc$libresoc.v:184700$12839
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$12932 $1\rok_l_s_rdok$next[0:0]$12933
- attribute \src "libresoc.v:186948.5-186948.29"
+ assign $0\rok_l_s_rdok$next[0:0]$12840 $1\rok_l_s_rdok$next[0:0]$12841
+ attribute \src "libresoc.v:184701.5-184701.29"
switch \initial
- attribute \src "libresoc.v:186948.9-186948.17"
+ attribute \src "libresoc.v:184701.9-184701.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$12933 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$12841 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$12933 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$12841 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12932
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12840
end
- attribute \src "libresoc.v:186956.3-186964.6"
- process $proc$libresoc.v:186956$12934
+ attribute \src "libresoc.v:184709.3-184717.6"
+ process $proc$libresoc.v:184709$12842
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$12935 $1\rok_l_r_rdok$next[0:0]$12936
- attribute \src "libresoc.v:186957.5-186957.29"
+ assign $0\rok_l_r_rdok$next[0:0]$12843 $1\rok_l_r_rdok$next[0:0]$12844
+ attribute \src "libresoc.v:184710.5-184710.29"
switch \initial
- attribute \src "libresoc.v:186957.9-186957.17"
+ attribute \src "libresoc.v:184710.9-184710.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$12936 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$12844 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$12936 \$68
+ assign $1\rok_l_r_rdok$next[0:0]$12844 \$68
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12935
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12843
end
- attribute \src "libresoc.v:186965.3-186973.6"
- process $proc$libresoc.v:186965$12937
+ attribute \src "libresoc.v:184718.3-184726.6"
+ process $proc$libresoc.v:184718$12845
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$12938 $1\rst_l_s_rst$next[0:0]$12939
- attribute \src "libresoc.v:186966.5-186966.29"
+ assign $0\rst_l_s_rst$next[0:0]$12846 $1\rst_l_s_rst$next[0:0]$12847
+ attribute \src "libresoc.v:184719.5-184719.29"
switch \initial
- attribute \src "libresoc.v:186966.9-186966.17"
+ attribute \src "libresoc.v:184719.9-184719.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$12939 1'0
+ assign $1\rst_l_s_rst$next[0:0]$12847 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$12939 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$12847 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12938
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12846
end
- attribute \src "libresoc.v:186974.3-186982.6"
- process $proc$libresoc.v:186974$12940
+ attribute \src "libresoc.v:184727.3-184735.6"
+ process $proc$libresoc.v:184727$12848
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$12941 $1\rst_l_r_rst$next[0:0]$12942
- attribute \src "libresoc.v:186975.5-186975.29"
+ assign $0\rst_l_r_rst$next[0:0]$12849 $1\rst_l_r_rst$next[0:0]$12850
+ attribute \src "libresoc.v:184728.5-184728.29"
switch \initial
- attribute \src "libresoc.v:186975.9-186975.17"
+ attribute \src "libresoc.v:184728.9-184728.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$12942 1'1
+ assign $1\rst_l_r_rst$next[0:0]$12850 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$12942 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$12850 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12941
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12849
end
- attribute \src "libresoc.v:186983.3-186991.6"
- process $proc$libresoc.v:186983$12943
+ attribute \src "libresoc.v:184736.3-184744.6"
+ process $proc$libresoc.v:184736$12851
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$12944 $1\opc_l_s_opc$next[0:0]$12945
- attribute \src "libresoc.v:186984.5-186984.29"
+ assign $0\opc_l_s_opc$next[0:0]$12852 $1\opc_l_s_opc$next[0:0]$12853
+ attribute \src "libresoc.v:184737.5-184737.29"
switch \initial
- attribute \src "libresoc.v:186984.9-186984.17"
+ attribute \src "libresoc.v:184737.9-184737.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$12945 1'0
+ assign $1\opc_l_s_opc$next[0:0]$12853 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$12945 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$12853 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12944
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12852
end
- attribute \src "libresoc.v:186992.3-187000.6"
- process $proc$libresoc.v:186992$12946
+ attribute \src "libresoc.v:184745.3-184753.6"
+ process $proc$libresoc.v:184745$12854
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$12947 $1\opc_l_r_opc$next[0:0]$12948
- attribute \src "libresoc.v:186993.5-186993.29"
+ assign $0\opc_l_r_opc$next[0:0]$12855 $1\opc_l_r_opc$next[0:0]$12856
+ attribute \src "libresoc.v:184746.5-184746.29"
switch \initial
- attribute \src "libresoc.v:186993.9-186993.17"
+ attribute \src "libresoc.v:184746.9-184746.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$12948 1'1
+ assign $1\opc_l_r_opc$next[0:0]$12856 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$12948 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$12856 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12947
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12855
end
- attribute \src "libresoc.v:187001.3-187009.6"
- process $proc$libresoc.v:187001$12949
+ attribute \src "libresoc.v:184754.3-184762.6"
+ process $proc$libresoc.v:184754$12857
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[5:0]$12950 $1\src_l_s_src$next[5:0]$12951
- attribute \src "libresoc.v:187002.5-187002.29"
+ assign $0\src_l_s_src$next[5:0]$12858 $1\src_l_s_src$next[5:0]$12859
+ attribute \src "libresoc.v:184755.5-184755.29"
switch \initial
- attribute \src "libresoc.v:187002.9-187002.17"
+ attribute \src "libresoc.v:184755.9-184755.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[5:0]$12951 6'000000
+ assign $1\src_l_s_src$next[5:0]$12859 6'000000
case
- assign $1\src_l_s_src$next[5:0]$12951 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[5:0]$12859 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12950
+ update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12858
end
- attribute \src "libresoc.v:187010.3-187018.6"
- process $proc$libresoc.v:187010$12952
+ attribute \src "libresoc.v:184763.3-184771.6"
+ process $proc$libresoc.v:184763$12860
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[5:0]$12953 $1\src_l_r_src$next[5:0]$12954
- attribute \src "libresoc.v:187011.5-187011.29"
+ assign $0\src_l_r_src$next[5:0]$12861 $1\src_l_r_src$next[5:0]$12862
+ attribute \src "libresoc.v:184764.5-184764.29"
switch \initial
- attribute \src "libresoc.v:187011.9-187011.17"
+ attribute \src "libresoc.v:184764.9-184764.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[5:0]$12954 6'111111
+ assign $1\src_l_r_src$next[5:0]$12862 6'111111
case
- assign $1\src_l_r_src$next[5:0]$12954 \reset_r
+ assign $1\src_l_r_src$next[5:0]$12862 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12953
+ update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12861
end
- attribute \src "libresoc.v:187019.3-187027.6"
- process $proc$libresoc.v:187019$12955
+ attribute \src "libresoc.v:184772.3-184780.6"
+ process $proc$libresoc.v:184772$12863
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[5:0]$12956 $1\req_l_s_req$next[5:0]$12957
- attribute \src "libresoc.v:187020.5-187020.29"
+ assign $0\req_l_s_req$next[5:0]$12864 $1\req_l_s_req$next[5:0]$12865
+ attribute \src "libresoc.v:184773.5-184773.29"
switch \initial
- attribute \src "libresoc.v:187020.9-187020.17"
+ attribute \src "libresoc.v:184773.9-184773.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[5:0]$12957 6'000000
+ assign $1\req_l_s_req$next[5:0]$12865 6'000000
case
- assign $1\req_l_s_req$next[5:0]$12957 \$70
+ assign $1\req_l_s_req$next[5:0]$12865 \$70
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12956
+ update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12864
end
- attribute \src "libresoc.v:187028.3-187036.6"
- process $proc$libresoc.v:187028$12958
+ attribute \src "libresoc.v:184781.3-184789.6"
+ process $proc$libresoc.v:184781$12866
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[5:0]$12959 $1\req_l_r_req$next[5:0]$12960
- attribute \src "libresoc.v:187029.5-187029.29"
+ assign $0\req_l_r_req$next[5:0]$12867 $1\req_l_r_req$next[5:0]$12868
+ attribute \src "libresoc.v:184782.5-184782.29"
switch \initial
- attribute \src "libresoc.v:187029.9-187029.17"
+ attribute \src "libresoc.v:184782.9-184782.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[5:0]$12960 6'111111
+ assign $1\req_l_r_req$next[5:0]$12868 6'111111
case
- assign $1\req_l_r_req$next[5:0]$12960 \$72
+ assign $1\req_l_r_req$next[5:0]$12868 \$72
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12959
+ update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12867
end
- attribute \src "libresoc.v:187037.3-187049.6"
- process $proc$libresoc.v:187037$12961
+ attribute \src "libresoc.v:184790.3-184802.6"
+ process $proc$libresoc.v:184790$12869
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966
- assign $0\alu_spr0_spr_op__insn$next[31:0]$12963 $1\alu_spr0_spr_op__insn$next[31:0]$12967
- assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12964 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968
- assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969
- attribute \src "libresoc.v:187038.5-187038.29"
+ assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874
+ assign $0\alu_spr0_spr_op__insn$next[31:0]$12871 $1\alu_spr0_spr_op__insn$next[31:0]$12875
+ assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12872 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876
+ assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877
+ attribute \src "libresoc.v:184791.5-184791.29"
switch \initial
- attribute \src "libresoc.v:187038.9-187038.17"
+ attribute \src "libresoc.v:184791.9-184791.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 $1\alu_spr0_spr_op__insn$next[31:0]$12967 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
+ assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 $1\alu_spr0_spr_op__insn$next[31:0]$12875 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
case
- assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 \alu_spr0_spr_op__fn_unit
- assign $1\alu_spr0_spr_op__insn$next[31:0]$12967 \alu_spr0_spr_op__insn
- assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 \alu_spr0_spr_op__insn_type
- assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 \alu_spr0_spr_op__is_32bit
+ assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 \alu_spr0_spr_op__fn_unit
+ assign $1\alu_spr0_spr_op__insn$next[31:0]$12875 \alu_spr0_spr_op__insn
+ assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 \alu_spr0_spr_op__insn_type
+ assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 \alu_spr0_spr_op__is_32bit
end
sync always
- update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962
- update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12963
- update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12964
- update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965
+ update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870
+ update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12871
+ update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12872
+ update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873
end
- attribute \src "libresoc.v:187050.3-187071.6"
- process $proc$libresoc.v:187050$12970
+ attribute \src "libresoc.v:184803.3-184824.6"
+ process $proc$libresoc.v:184803$12878
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$12971 $2\data_r0__o$next[63:0]$12975
+ assign $0\data_r0__o$next[63:0]$12879 $2\data_r0__o$next[63:0]$12883
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$12972 $3\data_r0__o_ok$next[0:0]$12977
- attribute \src "libresoc.v:187051.5-187051.29"
+ assign $0\data_r0__o_ok$next[0:0]$12880 $3\data_r0__o_ok$next[0:0]$12885
+ attribute \src "libresoc.v:184804.5-184804.29"
switch \initial
- attribute \src "libresoc.v:187051.9-187051.17"
+ attribute \src "libresoc.v:184804.9-184804.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$12974 $1\data_r0__o$next[63:0]$12973 } { \o_ok \alu_spr0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$12882 $1\data_r0__o$next[63:0]$12881 } { \o_ok \alu_spr0_o }
case
- assign $1\data_r0__o$next[63:0]$12973 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$12974 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$12881 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$12882 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$12976 $2\data_r0__o$next[63:0]$12975 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$12884 $2\data_r0__o$next[63:0]$12883 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$12975 $1\data_r0__o$next[63:0]$12973
- assign $2\data_r0__o_ok$next[0:0]$12976 $1\data_r0__o_ok$next[0:0]$12974
+ assign $2\data_r0__o$next[63:0]$12883 $1\data_r0__o$next[63:0]$12881
+ assign $2\data_r0__o_ok$next[0:0]$12884 $1\data_r0__o_ok$next[0:0]$12882
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$12977 1'0
+ assign $3\data_r0__o_ok$next[0:0]$12885 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$12977 $2\data_r0__o_ok$next[0:0]$12976
+ assign $3\data_r0__o_ok$next[0:0]$12885 $2\data_r0__o_ok$next[0:0]$12884
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$12971
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12972
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$12879
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12880
end
- attribute \src "libresoc.v:187072.3-187093.6"
- process $proc$libresoc.v:187072$12978
+ attribute \src "libresoc.v:184825.3-184846.6"
+ process $proc$libresoc.v:184825$12886
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__spr1$next[63:0]$12979 $2\data_r1__spr1$next[63:0]$12983
+ assign $0\data_r1__spr1$next[63:0]$12887 $2\data_r1__spr1$next[63:0]$12891
assign { } { }
- assign $0\data_r1__spr1_ok$next[0:0]$12980 $3\data_r1__spr1_ok$next[0:0]$12985
- attribute \src "libresoc.v:187073.5-187073.29"
+ assign $0\data_r1__spr1_ok$next[0:0]$12888 $3\data_r1__spr1_ok$next[0:0]$12893
+ attribute \src "libresoc.v:184826.5-184826.29"
switch \initial
- attribute \src "libresoc.v:187073.9-187073.17"
+ attribute \src "libresoc.v:184826.9-184826.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__spr1_ok$next[0:0]$12982 $1\data_r1__spr1$next[63:0]$12981 } { \spr1_ok \alu_spr0_spr1 }
+ assign { $1\data_r1__spr1_ok$next[0:0]$12890 $1\data_r1__spr1$next[63:0]$12889 } { \spr1_ok \alu_spr0_spr1 }
case
- assign $1\data_r1__spr1$next[63:0]$12981 \data_r1__spr1
- assign $1\data_r1__spr1_ok$next[0:0]$12982 \data_r1__spr1_ok
+ assign $1\data_r1__spr1$next[63:0]$12889 \data_r1__spr1
+ assign $1\data_r1__spr1_ok$next[0:0]$12890 \data_r1__spr1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__spr1_ok$next[0:0]$12984 $2\data_r1__spr1$next[63:0]$12983 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__spr1_ok$next[0:0]$12892 $2\data_r1__spr1$next[63:0]$12891 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__spr1$next[63:0]$12983 $1\data_r1__spr1$next[63:0]$12981
- assign $2\data_r1__spr1_ok$next[0:0]$12984 $1\data_r1__spr1_ok$next[0:0]$12982
+ assign $2\data_r1__spr1$next[63:0]$12891 $1\data_r1__spr1$next[63:0]$12889
+ assign $2\data_r1__spr1_ok$next[0:0]$12892 $1\data_r1__spr1_ok$next[0:0]$12890
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__spr1_ok$next[0:0]$12985 1'0
+ assign $3\data_r1__spr1_ok$next[0:0]$12893 1'0
case
- assign $3\data_r1__spr1_ok$next[0:0]$12985 $2\data_r1__spr1_ok$next[0:0]$12984
+ assign $3\data_r1__spr1_ok$next[0:0]$12893 $2\data_r1__spr1_ok$next[0:0]$12892
end
sync always
- update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12979
- update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12980
+ update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12887
+ update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12888
end
- attribute \src "libresoc.v:187094.3-187115.6"
- process $proc$libresoc.v:187094$12986
+ attribute \src "libresoc.v:184847.3-184868.6"
+ process $proc$libresoc.v:184847$12894
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast1$next[63:0]$12987 $2\data_r2__fast1$next[63:0]$12991
+ assign $0\data_r2__fast1$next[63:0]$12895 $2\data_r2__fast1$next[63:0]$12899
assign { } { }
- assign $0\data_r2__fast1_ok$next[0:0]$12988 $3\data_r2__fast1_ok$next[0:0]$12993
- attribute \src "libresoc.v:187095.5-187095.29"
+ assign $0\data_r2__fast1_ok$next[0:0]$12896 $3\data_r2__fast1_ok$next[0:0]$12901
+ attribute \src "libresoc.v:184848.5-184848.29"
switch \initial
- attribute \src "libresoc.v:187095.9-187095.17"
+ attribute \src "libresoc.v:184848.9-184848.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast1_ok$next[0:0]$12990 $1\data_r2__fast1$next[63:0]$12989 } { \fast1_ok \alu_spr0_fast1 }
+ assign { $1\data_r2__fast1_ok$next[0:0]$12898 $1\data_r2__fast1$next[63:0]$12897 } { \fast1_ok \alu_spr0_fast1 }
case
- assign $1\data_r2__fast1$next[63:0]$12989 \data_r2__fast1
- assign $1\data_r2__fast1_ok$next[0:0]$12990 \data_r2__fast1_ok
+ assign $1\data_r2__fast1$next[63:0]$12897 \data_r2__fast1
+ assign $1\data_r2__fast1_ok$next[0:0]$12898 \data_r2__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast1_ok$next[0:0]$12992 $2\data_r2__fast1$next[63:0]$12991 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast1_ok$next[0:0]$12900 $2\data_r2__fast1$next[63:0]$12899 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast1$next[63:0]$12991 $1\data_r2__fast1$next[63:0]$12989
- assign $2\data_r2__fast1_ok$next[0:0]$12992 $1\data_r2__fast1_ok$next[0:0]$12990
+ assign $2\data_r2__fast1$next[63:0]$12899 $1\data_r2__fast1$next[63:0]$12897
+ assign $2\data_r2__fast1_ok$next[0:0]$12900 $1\data_r2__fast1_ok$next[0:0]$12898
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast1_ok$next[0:0]$12993 1'0
+ assign $3\data_r2__fast1_ok$next[0:0]$12901 1'0
case
- assign $3\data_r2__fast1_ok$next[0:0]$12993 $2\data_r2__fast1_ok$next[0:0]$12992
+ assign $3\data_r2__fast1_ok$next[0:0]$12901 $2\data_r2__fast1_ok$next[0:0]$12900
end
sync always
- update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12987
- update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12988
+ update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12895
+ update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12896
end
- attribute \src "libresoc.v:187116.3-187137.6"
- process $proc$libresoc.v:187116$12994
+ attribute \src "libresoc.v:184869.3-184890.6"
+ process $proc$libresoc.v:184869$12902
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$12995 $2\data_r3__xer_so$next[0:0]$12999
+ assign $0\data_r3__xer_so$next[0:0]$12903 $2\data_r3__xer_so$next[0:0]$12907
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$12996 $3\data_r3__xer_so_ok$next[0:0]$13001
- attribute \src "libresoc.v:187117.5-187117.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$12904 $3\data_r3__xer_so_ok$next[0:0]$12909
+ attribute \src "libresoc.v:184870.5-184870.29"
switch \initial
- attribute \src "libresoc.v:187117.9-187117.17"
+ attribute \src "libresoc.v:184870.9-184870.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$12998 $1\data_r3__xer_so$next[0:0]$12997 } { \xer_so_ok \alu_spr0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$12906 $1\data_r3__xer_so$next[0:0]$12905 } { \xer_so_ok \alu_spr0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$12997 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$12998 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$12905 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$12906 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$13000 $2\data_r3__xer_so$next[0:0]$12999 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$12908 $2\data_r3__xer_so$next[0:0]$12907 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$12999 $1\data_r3__xer_so$next[0:0]$12997
- assign $2\data_r3__xer_so_ok$next[0:0]$13000 $1\data_r3__xer_so_ok$next[0:0]$12998
+ assign $2\data_r3__xer_so$next[0:0]$12907 $1\data_r3__xer_so$next[0:0]$12905
+ assign $2\data_r3__xer_so_ok$next[0:0]$12908 $1\data_r3__xer_so_ok$next[0:0]$12906
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$13001 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$12909 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$13001 $2\data_r3__xer_so_ok$next[0:0]$13000
+ assign $3\data_r3__xer_so_ok$next[0:0]$12909 $2\data_r3__xer_so_ok$next[0:0]$12908
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12995
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12996
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12903
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12904
end
- attribute \src "libresoc.v:187138.3-187159.6"
- process $proc$libresoc.v:187138$13002
+ attribute \src "libresoc.v:184891.3-184912.6"
+ process $proc$libresoc.v:184891$12910
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__xer_ov$next[1:0]$13003 $2\data_r4__xer_ov$next[1:0]$13007
+ assign $0\data_r4__xer_ov$next[1:0]$12911 $2\data_r4__xer_ov$next[1:0]$12915
assign { } { }
- assign $0\data_r4__xer_ov_ok$next[0:0]$13004 $3\data_r4__xer_ov_ok$next[0:0]$13009
- attribute \src "libresoc.v:187139.5-187139.29"
+ assign $0\data_r4__xer_ov_ok$next[0:0]$12912 $3\data_r4__xer_ov_ok$next[0:0]$12917
+ attribute \src "libresoc.v:184892.5-184892.29"
switch \initial
- attribute \src "libresoc.v:187139.9-187139.17"
+ attribute \src "libresoc.v:184892.9-184892.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__xer_ov_ok$next[0:0]$13006 $1\data_r4__xer_ov$next[1:0]$13005 } { \xer_ov_ok \alu_spr0_xer_ov }
+ assign { $1\data_r4__xer_ov_ok$next[0:0]$12914 $1\data_r4__xer_ov$next[1:0]$12913 } { \xer_ov_ok \alu_spr0_xer_ov }
case
- assign $1\data_r4__xer_ov$next[1:0]$13005 \data_r4__xer_ov
- assign $1\data_r4__xer_ov_ok$next[0:0]$13006 \data_r4__xer_ov_ok
+ assign $1\data_r4__xer_ov$next[1:0]$12913 \data_r4__xer_ov
+ assign $1\data_r4__xer_ov_ok$next[0:0]$12914 \data_r4__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__xer_ov_ok$next[0:0]$13008 $2\data_r4__xer_ov$next[1:0]$13007 } 3'000
+ assign { $2\data_r4__xer_ov_ok$next[0:0]$12916 $2\data_r4__xer_ov$next[1:0]$12915 } 3'000
case
- assign $2\data_r4__xer_ov$next[1:0]$13007 $1\data_r4__xer_ov$next[1:0]$13005
- assign $2\data_r4__xer_ov_ok$next[0:0]$13008 $1\data_r4__xer_ov_ok$next[0:0]$13006
+ assign $2\data_r4__xer_ov$next[1:0]$12915 $1\data_r4__xer_ov$next[1:0]$12913
+ assign $2\data_r4__xer_ov_ok$next[0:0]$12916 $1\data_r4__xer_ov_ok$next[0:0]$12914
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__xer_ov_ok$next[0:0]$13009 1'0
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12917 1'0
case
- assign $3\data_r4__xer_ov_ok$next[0:0]$13009 $2\data_r4__xer_ov_ok$next[0:0]$13008
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12917 $2\data_r4__xer_ov_ok$next[0:0]$12916
end
sync always
- update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13003
- update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13004
+ update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12911
+ update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12912
end
- attribute \src "libresoc.v:187160.3-187181.6"
- process $proc$libresoc.v:187160$13010
+ attribute \src "libresoc.v:184913.3-184934.6"
+ process $proc$libresoc.v:184913$12918
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r5__xer_ca$next[1:0]$13011 $2\data_r5__xer_ca$next[1:0]$13015
+ assign $0\data_r5__xer_ca$next[1:0]$12919 $2\data_r5__xer_ca$next[1:0]$12923
assign { } { }
- assign $0\data_r5__xer_ca_ok$next[0:0]$13012 $3\data_r5__xer_ca_ok$next[0:0]$13017
- attribute \src "libresoc.v:187161.5-187161.29"
+ assign $0\data_r5__xer_ca_ok$next[0:0]$12920 $3\data_r5__xer_ca_ok$next[0:0]$12925
+ attribute \src "libresoc.v:184914.5-184914.29"
switch \initial
- attribute \src "libresoc.v:187161.9-187161.17"
+ attribute \src "libresoc.v:184914.9-184914.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r5__xer_ca_ok$next[0:0]$13014 $1\data_r5__xer_ca$next[1:0]$13013 } { \xer_ca_ok \alu_spr0_xer_ca }
+ assign { $1\data_r5__xer_ca_ok$next[0:0]$12922 $1\data_r5__xer_ca$next[1:0]$12921 } { \xer_ca_ok \alu_spr0_xer_ca }
case
- assign $1\data_r5__xer_ca$next[1:0]$13013 \data_r5__xer_ca
- assign $1\data_r5__xer_ca_ok$next[0:0]$13014 \data_r5__xer_ca_ok
+ assign $1\data_r5__xer_ca$next[1:0]$12921 \data_r5__xer_ca
+ assign $1\data_r5__xer_ca_ok$next[0:0]$12922 \data_r5__xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r5__xer_ca_ok$next[0:0]$13016 $2\data_r5__xer_ca$next[1:0]$13015 } 3'000
+ assign { $2\data_r5__xer_ca_ok$next[0:0]$12924 $2\data_r5__xer_ca$next[1:0]$12923 } 3'000
case
- assign $2\data_r5__xer_ca$next[1:0]$13015 $1\data_r5__xer_ca$next[1:0]$13013
- assign $2\data_r5__xer_ca_ok$next[0:0]$13016 $1\data_r5__xer_ca_ok$next[0:0]$13014
+ assign $2\data_r5__xer_ca$next[1:0]$12923 $1\data_r5__xer_ca$next[1:0]$12921
+ assign $2\data_r5__xer_ca_ok$next[0:0]$12924 $1\data_r5__xer_ca_ok$next[0:0]$12922
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r5__xer_ca_ok$next[0:0]$13017 1'0
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12925 1'0
case
- assign $3\data_r5__xer_ca_ok$next[0:0]$13017 $2\data_r5__xer_ca_ok$next[0:0]$13016
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12925 $2\data_r5__xer_ca_ok$next[0:0]$12924
end
sync always
- update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13011
- update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13012
+ update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12919
+ update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12920
end
- attribute \src "libresoc.v:187182.3-187191.6"
- process $proc$libresoc.v:187182$13018
+ attribute \src "libresoc.v:184935.3-184944.6"
+ process $proc$libresoc.v:184935$12926
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$13019 $1\src_r0$next[63:0]$13020
- attribute \src "libresoc.v:187183.5-187183.29"
+ assign $0\src_r0$next[63:0]$12927 $1\src_r0$next[63:0]$12928
+ attribute \src "libresoc.v:184936.5-184936.29"
switch \initial
- attribute \src "libresoc.v:187183.9-187183.17"
+ attribute \src "libresoc.v:184936.9-184936.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$13020 \src1_i
+ assign $1\src_r0$next[63:0]$12928 \src1_i
case
- assign $1\src_r0$next[63:0]$13020 \src_r0
+ assign $1\src_r0$next[63:0]$12928 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$13019
+ update \src_r0$next $0\src_r0$next[63:0]$12927
end
- attribute \src "libresoc.v:187192.3-187201.6"
- process $proc$libresoc.v:187192$13021
+ attribute \src "libresoc.v:184945.3-184954.6"
+ process $proc$libresoc.v:184945$12929
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$13022 $1\src_r1$next[63:0]$13023
- attribute \src "libresoc.v:187193.5-187193.29"
+ assign $0\src_r1$next[63:0]$12930 $1\src_r1$next[63:0]$12931
+ attribute \src "libresoc.v:184946.5-184946.29"
switch \initial
- attribute \src "libresoc.v:187193.9-187193.17"
+ attribute \src "libresoc.v:184946.9-184946.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$13023 \src2_i
+ assign $1\src_r1$next[63:0]$12931 \src2_i
case
- assign $1\src_r1$next[63:0]$13023 \src_r1
+ assign $1\src_r1$next[63:0]$12931 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$13022
+ update \src_r1$next $0\src_r1$next[63:0]$12930
end
- attribute \src "libresoc.v:187202.3-187211.6"
- process $proc$libresoc.v:187202$13024
+ attribute \src "libresoc.v:184955.3-184964.6"
+ process $proc$libresoc.v:184955$12932
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$13025 $1\src_r2$next[63:0]$13026
- attribute \src "libresoc.v:187203.5-187203.29"
+ assign $0\src_r2$next[63:0]$12933 $1\src_r2$next[63:0]$12934
+ attribute \src "libresoc.v:184956.5-184956.29"
switch \initial
- attribute \src "libresoc.v:187203.9-187203.17"
+ attribute \src "libresoc.v:184956.9-184956.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$13026 \src3_i
+ assign $1\src_r2$next[63:0]$12934 \src3_i
case
- assign $1\src_r2$next[63:0]$13026 \src_r2
+ assign $1\src_r2$next[63:0]$12934 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$13025
+ update \src_r2$next $0\src_r2$next[63:0]$12933
end
- attribute \src "libresoc.v:187212.3-187221.6"
- process $proc$libresoc.v:187212$13027
+ attribute \src "libresoc.v:184965.3-184974.6"
+ process $proc$libresoc.v:184965$12935
assign { } { }
assign { } { }
- assign $0\src_r3$next[0:0]$13028 $1\src_r3$next[0:0]$13029
- attribute \src "libresoc.v:187213.5-187213.29"
+ assign $0\src_r3$next[0:0]$12936 $1\src_r3$next[0:0]$12937
+ attribute \src "libresoc.v:184966.5-184966.29"
switch \initial
- attribute \src "libresoc.v:187213.9-187213.17"
+ attribute \src "libresoc.v:184966.9-184966.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[0:0]$13029 \src4_i
+ assign $1\src_r3$next[0:0]$12937 \src4_i
case
- assign $1\src_r3$next[0:0]$13029 \src_r3
+ assign $1\src_r3$next[0:0]$12937 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[0:0]$13028
+ update \src_r3$next $0\src_r3$next[0:0]$12936
end
- attribute \src "libresoc.v:187222.3-187231.6"
- process $proc$libresoc.v:187222$13030
+ attribute \src "libresoc.v:184975.3-184984.6"
+ process $proc$libresoc.v:184975$12938
assign { } { }
assign { } { }
- assign $0\src_r4$next[1:0]$13031 $1\src_r4$next[1:0]$13032
- attribute \src "libresoc.v:187223.5-187223.29"
+ assign $0\src_r4$next[1:0]$12939 $1\src_r4$next[1:0]$12940
+ attribute \src "libresoc.v:184976.5-184976.29"
switch \initial
- attribute \src "libresoc.v:187223.9-187223.17"
+ attribute \src "libresoc.v:184976.9-184976.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[1:0]$13032 \src5_i
+ assign $1\src_r4$next[1:0]$12940 \src5_i
case
- assign $1\src_r4$next[1:0]$13032 \src_r4
+ assign $1\src_r4$next[1:0]$12940 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[1:0]$13031
+ update \src_r4$next $0\src_r4$next[1:0]$12939
end
- attribute \src "libresoc.v:187232.3-187241.6"
- process $proc$libresoc.v:187232$13033
+ attribute \src "libresoc.v:184985.3-184994.6"
+ process $proc$libresoc.v:184985$12941
assign { } { }
assign { } { }
- assign $0\src_r5$next[1:0]$13034 $1\src_r5$next[1:0]$13035
- attribute \src "libresoc.v:187233.5-187233.29"
+ assign $0\src_r5$next[1:0]$12942 $1\src_r5$next[1:0]$12943
+ attribute \src "libresoc.v:184986.5-184986.29"
switch \initial
- attribute \src "libresoc.v:187233.9-187233.17"
+ attribute \src "libresoc.v:184986.9-184986.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r5$next[1:0]$13035 \src6_i
+ assign $1\src_r5$next[1:0]$12943 \src6_i
case
- assign $1\src_r5$next[1:0]$13035 \src_r5
+ assign $1\src_r5$next[1:0]$12943 \src_r5
end
sync always
- update \src_r5$next $0\src_r5$next[1:0]$13034
+ update \src_r5$next $0\src_r5$next[1:0]$12942
end
- attribute \src "libresoc.v:187242.3-187250.6"
- process $proc$libresoc.v:187242$13036
+ attribute \src "libresoc.v:184995.3-185003.6"
+ process $proc$libresoc.v:184995$12944
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$13037 $1\alui_l_r_alui$next[0:0]$13038
- attribute \src "libresoc.v:187243.5-187243.29"
+ assign $0\alui_l_r_alui$next[0:0]$12945 $1\alui_l_r_alui$next[0:0]$12946
+ attribute \src "libresoc.v:184996.5-184996.29"
switch \initial
- attribute \src "libresoc.v:187243.9-187243.17"
+ attribute \src "libresoc.v:184996.9-184996.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$13038 1'1
+ assign $1\alui_l_r_alui$next[0:0]$12946 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$13038 \$98
+ assign $1\alui_l_r_alui$next[0:0]$12946 \$98
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13037
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12945
end
- attribute \src "libresoc.v:187251.3-187259.6"
- process $proc$libresoc.v:187251$13039
+ attribute \src "libresoc.v:185004.3-185012.6"
+ process $proc$libresoc.v:185004$12947
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$13040 $1\alu_l_r_alu$next[0:0]$13041
- attribute \src "libresoc.v:187252.5-187252.29"
+ assign $0\alu_l_r_alu$next[0:0]$12948 $1\alu_l_r_alu$next[0:0]$12949
+ attribute \src "libresoc.v:185005.5-185005.29"
switch \initial
- attribute \src "libresoc.v:187252.9-187252.17"
+ attribute \src "libresoc.v:185005.9-185005.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$13041 1'1
+ assign $1\alu_l_r_alu$next[0:0]$12949 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$13041 \$100
+ assign $1\alu_l_r_alu$next[0:0]$12949 \$100
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13040
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12948
end
- attribute \src "libresoc.v:187260.3-187269.6"
- process $proc$libresoc.v:187260$13042
+ attribute \src "libresoc.v:185013.3-185022.6"
+ process $proc$libresoc.v:185013$12950
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:187261.5-187261.29"
+ attribute \src "libresoc.v:185014.5-185014.29"
switch \initial
- attribute \src "libresoc.v:187261.9-187261.17"
+ attribute \src "libresoc.v:185014.9-185014.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:187270.3-187279.6"
- process $proc$libresoc.v:187270$13043
+ attribute \src "libresoc.v:185023.3-185032.6"
+ process $proc$libresoc.v:185023$12951
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:187271.5-187271.29"
+ attribute \src "libresoc.v:185024.5-185024.29"
switch \initial
- attribute \src "libresoc.v:187271.9-187271.17"
+ attribute \src "libresoc.v:185024.9-185024.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:187280.3-187289.6"
- process $proc$libresoc.v:187280$13044
+ attribute \src "libresoc.v:185033.3-185042.6"
+ process $proc$libresoc.v:185033$12952
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:187281.5-187281.29"
+ attribute \src "libresoc.v:185034.5-185034.29"
switch \initial
- attribute \src "libresoc.v:187281.9-187281.17"
+ attribute \src "libresoc.v:185034.9-185034.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:187290.3-187299.6"
- process $proc$libresoc.v:187290$13045
+ attribute \src "libresoc.v:185043.3-185052.6"
+ process $proc$libresoc.v:185043$12953
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:187291.5-187291.29"
+ attribute \src "libresoc.v:185044.5-185044.29"
switch \initial
- attribute \src "libresoc.v:187291.9-187291.17"
+ attribute \src "libresoc.v:185044.9-185044.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:187300.3-187309.6"
- process $proc$libresoc.v:187300$13046
+ attribute \src "libresoc.v:185053.3-185062.6"
+ process $proc$libresoc.v:185053$12954
assign { } { }
assign { } { }
assign $0\dest5_o[1:0] $1\dest5_o[1:0]
- attribute \src "libresoc.v:187301.5-187301.29"
+ attribute \src "libresoc.v:185054.5-185054.29"
switch \initial
- attribute \src "libresoc.v:187301.9-187301.17"
+ attribute \src "libresoc.v:185054.9-185054.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[1:0]
end
- attribute \src "libresoc.v:187310.3-187319.6"
- process $proc$libresoc.v:187310$13047
+ attribute \src "libresoc.v:185063.3-185072.6"
+ process $proc$libresoc.v:185063$12955
assign { } { }
assign { } { }
assign $0\dest6_o[1:0] $1\dest6_o[1:0]
- attribute \src "libresoc.v:187311.5-187311.29"
+ attribute \src "libresoc.v:185064.5-185064.29"
switch \initial
- attribute \src "libresoc.v:187311.9-187311.17"
+ attribute \src "libresoc.v:185064.9-185064.17"
case 1'1
case
end
sync always
update \dest6_o $0\dest6_o[1:0]
end
- attribute \src "libresoc.v:187320.3-187328.6"
- process $proc$libresoc.v:187320$13048
+ attribute \src "libresoc.v:185073.3-185081.6"
+ process $proc$libresoc.v:185073$12956
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[5:0]$13049 $1\prev_wr_go$next[5:0]$13050
- attribute \src "libresoc.v:187321.5-187321.29"
+ assign $0\prev_wr_go$next[5:0]$12957 $1\prev_wr_go$next[5:0]$12958
+ attribute \src "libresoc.v:185074.5-185074.29"
switch \initial
- attribute \src "libresoc.v:187321.9-187321.17"
+ attribute \src "libresoc.v:185074.9-185074.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[5:0]$13050 6'000000
- case
- assign $1\prev_wr_go$next[5:0]$13050 \$24
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13049
- end
- connect \$9 $not$libresoc.v:186719$12827_Y
- connect \$100 $and$libresoc.v:186720$12828_Y
- connect \$102 $and$libresoc.v:186721$12829_Y
- connect \$104 $and$libresoc.v:186722$12830_Y
- connect \$106 $not$libresoc.v:186723$12831_Y
- connect \$108 $and$libresoc.v:186724$12832_Y
- connect \$110 $and$libresoc.v:186725$12833_Y
- connect \$112 $and$libresoc.v:186726$12834_Y
- connect \$114 $and$libresoc.v:186727$12835_Y
- connect \$116 $and$libresoc.v:186728$12836_Y
- connect \$118 $and$libresoc.v:186729$12837_Y
- connect \$11 $or$libresoc.v:186730$12838_Y
- connect \$120 $and$libresoc.v:186731$12839_Y
- connect \$122 $and$libresoc.v:186732$12840_Y
- connect \$124 $and$libresoc.v:186733$12841_Y
- connect \$126 $and$libresoc.v:186734$12842_Y
- connect \$128 $and$libresoc.v:186735$12843_Y
- connect \$8 $reduce_and$libresoc.v:186736$12844_Y
- connect \$130 $and$libresoc.v:186737$12845_Y
- connect \$132 $and$libresoc.v:186738$12846_Y
- connect \$134 $and$libresoc.v:186739$12847_Y
- connect \$136 $and$libresoc.v:186740$12848_Y
- connect \$14 $and$libresoc.v:186741$12849_Y
- connect \$16 $not$libresoc.v:186742$12850_Y
- connect \$18 $and$libresoc.v:186743$12851_Y
- connect \$20 $not$libresoc.v:186744$12852_Y
- connect \$22 $and$libresoc.v:186745$12853_Y
- connect \$24 $and$libresoc.v:186746$12854_Y
- connect \$28 $not$libresoc.v:186747$12855_Y
- connect \$30 $and$libresoc.v:186748$12856_Y
- connect \$27 $reduce_or$libresoc.v:186749$12857_Y
- connect \$26 $not$libresoc.v:186750$12858_Y
- connect \$34 $and$libresoc.v:186751$12859_Y
- connect \$36 $reduce_or$libresoc.v:186752$12860_Y
- connect \$38 $reduce_or$libresoc.v:186753$12861_Y
- connect \$40 $or$libresoc.v:186754$12862_Y
- connect \$42 $not$libresoc.v:186755$12863_Y
- connect \$44 $and$libresoc.v:186756$12864_Y
- connect \$46 $and$libresoc.v:186757$12865_Y
- connect \$48 $eq$libresoc.v:186758$12866_Y
- connect \$50 $and$libresoc.v:186759$12867_Y
- connect \$52 $eq$libresoc.v:186760$12868_Y
- connect \$54 $and$libresoc.v:186761$12869_Y
- connect \$56 $and$libresoc.v:186762$12870_Y
- connect \$58 $and$libresoc.v:186763$12871_Y
- connect \$60 $or$libresoc.v:186764$12872_Y
- connect \$62 $or$libresoc.v:186765$12873_Y
- connect \$64 $or$libresoc.v:186766$12874_Y
- connect \$66 $or$libresoc.v:186767$12875_Y
- connect \$68 $and$libresoc.v:186768$12876_Y
- connect \$6 $and$libresoc.v:186769$12877_Y
- connect \$70 $and$libresoc.v:186770$12878_Y
- connect \$72 $or$libresoc.v:186771$12879_Y
- connect \$74 $and$libresoc.v:186772$12880_Y
- connect \$76 $and$libresoc.v:186773$12881_Y
- connect \$78 $and$libresoc.v:186774$12882_Y
- connect \$80 $and$libresoc.v:186775$12883_Y
- connect \$82 $and$libresoc.v:186776$12884_Y
- connect \$84 $and$libresoc.v:186777$12885_Y
- connect \$86 $ternary$libresoc.v:186778$12886_Y
- connect \$88 $ternary$libresoc.v:186779$12887_Y
- connect \$90 $ternary$libresoc.v:186780$12888_Y
- connect \$92 $ternary$libresoc.v:186781$12889_Y
- connect \$94 $ternary$libresoc.v:186782$12890_Y
- connect \$96 $ternary$libresoc.v:186783$12891_Y
- connect \$98 $and$libresoc.v:186784$12892_Y
+ assign $1\prev_wr_go$next[5:0]$12958 6'000000
+ case
+ assign $1\prev_wr_go$next[5:0]$12958 \$24
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12957
+ end
+ connect \$9 $not$libresoc.v:184472$12735_Y
+ connect \$100 $and$libresoc.v:184473$12736_Y
+ connect \$102 $and$libresoc.v:184474$12737_Y
+ connect \$104 $and$libresoc.v:184475$12738_Y
+ connect \$106 $not$libresoc.v:184476$12739_Y
+ connect \$108 $and$libresoc.v:184477$12740_Y
+ connect \$110 $and$libresoc.v:184478$12741_Y
+ connect \$112 $and$libresoc.v:184479$12742_Y
+ connect \$114 $and$libresoc.v:184480$12743_Y
+ connect \$116 $and$libresoc.v:184481$12744_Y
+ connect \$118 $and$libresoc.v:184482$12745_Y
+ connect \$11 $or$libresoc.v:184483$12746_Y
+ connect \$120 $and$libresoc.v:184484$12747_Y
+ connect \$122 $and$libresoc.v:184485$12748_Y
+ connect \$124 $and$libresoc.v:184486$12749_Y
+ connect \$126 $and$libresoc.v:184487$12750_Y
+ connect \$128 $and$libresoc.v:184488$12751_Y
+ connect \$8 $reduce_and$libresoc.v:184489$12752_Y
+ connect \$130 $and$libresoc.v:184490$12753_Y
+ connect \$132 $and$libresoc.v:184491$12754_Y
+ connect \$134 $and$libresoc.v:184492$12755_Y
+ connect \$136 $and$libresoc.v:184493$12756_Y
+ connect \$14 $and$libresoc.v:184494$12757_Y
+ connect \$16 $not$libresoc.v:184495$12758_Y
+ connect \$18 $and$libresoc.v:184496$12759_Y
+ connect \$20 $not$libresoc.v:184497$12760_Y
+ connect \$22 $and$libresoc.v:184498$12761_Y
+ connect \$24 $and$libresoc.v:184499$12762_Y
+ connect \$28 $not$libresoc.v:184500$12763_Y
+ connect \$30 $and$libresoc.v:184501$12764_Y
+ connect \$27 $reduce_or$libresoc.v:184502$12765_Y
+ connect \$26 $not$libresoc.v:184503$12766_Y
+ connect \$34 $and$libresoc.v:184504$12767_Y
+ connect \$36 $reduce_or$libresoc.v:184505$12768_Y
+ connect \$38 $reduce_or$libresoc.v:184506$12769_Y
+ connect \$40 $or$libresoc.v:184507$12770_Y
+ connect \$42 $not$libresoc.v:184508$12771_Y
+ connect \$44 $and$libresoc.v:184509$12772_Y
+ connect \$46 $and$libresoc.v:184510$12773_Y
+ connect \$48 $eq$libresoc.v:184511$12774_Y
+ connect \$50 $and$libresoc.v:184512$12775_Y
+ connect \$52 $eq$libresoc.v:184513$12776_Y
+ connect \$54 $and$libresoc.v:184514$12777_Y
+ connect \$56 $and$libresoc.v:184515$12778_Y
+ connect \$58 $and$libresoc.v:184516$12779_Y
+ connect \$60 $or$libresoc.v:184517$12780_Y
+ connect \$62 $or$libresoc.v:184518$12781_Y
+ connect \$64 $or$libresoc.v:184519$12782_Y
+ connect \$66 $or$libresoc.v:184520$12783_Y
+ connect \$68 $and$libresoc.v:184521$12784_Y
+ connect \$6 $and$libresoc.v:184522$12785_Y
+ connect \$70 $and$libresoc.v:184523$12786_Y
+ connect \$72 $or$libresoc.v:184524$12787_Y
+ connect \$74 $and$libresoc.v:184525$12788_Y
+ connect \$76 $and$libresoc.v:184526$12789_Y
+ connect \$78 $and$libresoc.v:184527$12790_Y
+ connect \$80 $and$libresoc.v:184528$12791_Y
+ connect \$82 $and$libresoc.v:184529$12792_Y
+ connect \$84 $and$libresoc.v:184530$12793_Y
+ connect \$86 $ternary$libresoc.v:184531$12794_Y
+ connect \$88 $ternary$libresoc.v:184532$12795_Y
+ connect \$90 $ternary$libresoc.v:184533$12796_Y
+ connect \$92 $ternary$libresoc.v:184534$12797_Y
+ connect \$94 $ternary$libresoc.v:184535$12798_Y
+ connect \$96 $ternary$libresoc.v:184536$12799_Y
+ connect \$98 $and$libresoc.v:184537$12800_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$124
connect \all_rd_dly$next \all_rd
connect \all_rd \$14
end
-attribute \src "libresoc.v:187364.1-187880.10"
+attribute \src "libresoc.v:185117.1-185633.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main"
attribute \generator "nMigen"
module \spr_main
- attribute \src "libresoc.v:187633.3-187648.6"
- wire width 64 $0\fast1$7[63:0]$13097
- attribute \src "libresoc.v:187710.3-187725.6"
+ attribute \src "libresoc.v:185386.3-185401.6"
+ wire width 64 $0\fast1$7[63:0]$13005
+ attribute \src "libresoc.v:185463.3-185478.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:187365.7-187365.20"
+ attribute \src "libresoc.v:185118.7-185118.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:187858.3-187876.6"
- wire width 64 $0\spr1$6[63:0]$13122
- attribute \src "libresoc.v:187649.3-187667.6"
+ attribute \src "libresoc.v:185611.3-185629.6"
+ wire width 64 $0\spr1$6[63:0]$13030
+ attribute \src "libresoc.v:185402.3-185420.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:187813.3-187836.6"
- wire width 2 $0\xer_ca$10[1:0]$13116
- attribute \src "libresoc.v:187837.3-187857.6"
+ attribute \src "libresoc.v:185566.3-185589.6"
+ wire width 2 $0\xer_ca$10[1:0]$13024
+ attribute \src "libresoc.v:185590.3-185610.6"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:187768.3-187791.6"
- wire width 2 $0\xer_ov$9[1:0]$13110
- attribute \src "libresoc.v:187792.3-187812.6"
+ attribute \src "libresoc.v:185521.3-185544.6"
+ wire width 2 $0\xer_ov$9[1:0]$13018
+ attribute \src "libresoc.v:185545.3-185565.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:187726.3-187746.6"
- wire $0\xer_so$8[0:0]$13104
- attribute \src "libresoc.v:187747.3-187767.6"
+ attribute \src "libresoc.v:185479.3-185499.6"
+ wire $0\xer_so$8[0:0]$13012
+ attribute \src "libresoc.v:185500.3-185520.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:187633.3-187648.6"
- wire width 64 $1\fast1$7[63:0]$13098
- attribute \src "libresoc.v:187710.3-187725.6"
+ attribute \src "libresoc.v:185386.3-185401.6"
+ wire width 64 $1\fast1$7[63:0]$13006
+ attribute \src "libresoc.v:185463.3-185478.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:187858.3-187876.6"
- wire width 64 $1\spr1$6[63:0]$13123
- attribute \src "libresoc.v:187649.3-187667.6"
+ attribute \src "libresoc.v:185611.3-185629.6"
+ wire width 64 $1\spr1$6[63:0]$13031
+ attribute \src "libresoc.v:185402.3-185420.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:187813.3-187836.6"
- wire width 2 $1\xer_ca$10[1:0]$13117
- attribute \src "libresoc.v:187837.3-187857.6"
+ attribute \src "libresoc.v:185566.3-185589.6"
+ wire width 2 $1\xer_ca$10[1:0]$13025
+ attribute \src "libresoc.v:185590.3-185610.6"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:187768.3-187791.6"
- wire width 2 $1\xer_ov$9[1:0]$13111
- attribute \src "libresoc.v:187792.3-187812.6"
+ attribute \src "libresoc.v:185521.3-185544.6"
+ wire width 2 $1\xer_ov$9[1:0]$13019
+ attribute \src "libresoc.v:185545.3-185565.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:187726.3-187746.6"
- wire $1\xer_so$8[0:0]$13105
- attribute \src "libresoc.v:187747.3-187767.6"
+ attribute \src "libresoc.v:185479.3-185499.6"
+ wire $1\xer_so$8[0:0]$13013
+ attribute \src "libresoc.v:185500.3-185520.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:187633.3-187648.6"
- wire width 64 $2\fast1$7[63:0]$13099
- attribute \src "libresoc.v:187710.3-187725.6"
+ attribute \src "libresoc.v:185386.3-185401.6"
+ wire width 64 $2\fast1$7[63:0]$13007
+ attribute \src "libresoc.v:185463.3-185478.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:187858.3-187876.6"
- wire width 64 $2\spr1$6[63:0]$13124
- attribute \src "libresoc.v:187649.3-187667.6"
+ attribute \src "libresoc.v:185611.3-185629.6"
+ wire width 64 $2\spr1$6[63:0]$13032
+ attribute \src "libresoc.v:185402.3-185420.6"
wire $2\spr1_ok[0:0]
- attribute \src "libresoc.v:187813.3-187836.6"
- wire width 2 $2\xer_ca$10[1:0]$13118
- attribute \src "libresoc.v:187837.3-187857.6"
+ attribute \src "libresoc.v:185566.3-185589.6"
+ wire width 2 $2\xer_ca$10[1:0]$13026
+ attribute \src "libresoc.v:185590.3-185610.6"
wire $2\xer_ca_ok[0:0]
- attribute \src "libresoc.v:187768.3-187791.6"
- wire width 2 $2\xer_ov$9[1:0]$13112
- attribute \src "libresoc.v:187792.3-187812.6"
+ attribute \src "libresoc.v:185521.3-185544.6"
+ wire width 2 $2\xer_ov$9[1:0]$13020
+ attribute \src "libresoc.v:185545.3-185565.6"
wire $2\xer_ov_ok[0:0]
- attribute \src "libresoc.v:187726.3-187746.6"
- wire $2\xer_so$8[0:0]$13106
- attribute \src "libresoc.v:187747.3-187767.6"
+ attribute \src "libresoc.v:185479.3-185499.6"
+ wire $2\xer_so$8[0:0]$13014
+ attribute \src "libresoc.v:185500.3-185520.6"
wire $2\xer_so_ok[0:0]
- attribute \src "libresoc.v:187668.3-187709.6"
+ attribute \src "libresoc.v:185421.3-185462.6"
wire width 46 $3\o[63:18]
- attribute \src "libresoc.v:187813.3-187836.6"
- wire width 2 $3\xer_ca$10[1:0]$13119
- attribute \src "libresoc.v:187837.3-187857.6"
+ attribute \src "libresoc.v:185566.3-185589.6"
+ wire width 2 $3\xer_ca$10[1:0]$13027
+ attribute \src "libresoc.v:185590.3-185610.6"
wire $3\xer_ca_ok[0:0]
- attribute \src "libresoc.v:187768.3-187791.6"
- wire width 2 $3\xer_ov$9[1:0]$13113
- attribute \src "libresoc.v:187792.3-187812.6"
+ attribute \src "libresoc.v:185521.3-185544.6"
+ wire width 2 $3\xer_ov$9[1:0]$13021
+ attribute \src "libresoc.v:185545.3-185565.6"
wire $3\xer_ov_ok[0:0]
- attribute \src "libresoc.v:187726.3-187746.6"
- wire $3\xer_so$8[0:0]$13107
- attribute \src "libresoc.v:187747.3-187767.6"
+ attribute \src "libresoc.v:185479.3-185499.6"
+ wire $3\xer_so$8[0:0]$13015
+ attribute \src "libresoc.v:185500.3-185520.6"
wire $3\xer_so_ok[0:0]
- attribute \src "libresoc.v:187626.18-187626.106"
- wire $eq$libresoc.v:187626$13089_Y
- attribute \src "libresoc.v:187627.18-187627.106"
- wire $eq$libresoc.v:187627$13090_Y
- attribute \src "libresoc.v:187628.18-187628.106"
- wire $eq$libresoc.v:187628$13091_Y
- attribute \src "libresoc.v:187629.18-187629.106"
- wire $eq$libresoc.v:187629$13092_Y
- attribute \src "libresoc.v:187630.18-187630.106"
- wire $eq$libresoc.v:187630$13093_Y
- attribute \src "libresoc.v:187631.18-187631.106"
- wire $eq$libresoc.v:187631$13094_Y
- attribute \src "libresoc.v:187632.18-187632.106"
- wire $eq$libresoc.v:187632$13095_Y
+ attribute \src "libresoc.v:185379.18-185379.106"
+ wire $eq$libresoc.v:185379$12997_Y
+ attribute \src "libresoc.v:185380.18-185380.106"
+ wire $eq$libresoc.v:185380$12998_Y
+ attribute \src "libresoc.v:185381.18-185381.106"
+ wire $eq$libresoc.v:185381$12999_Y
+ attribute \src "libresoc.v:185382.18-185382.106"
+ wire $eq$libresoc.v:185382$13000_Y
+ attribute \src "libresoc.v:185383.18-185383.106"
+ wire $eq$libresoc.v:185383$13001_Y
+ attribute \src "libresoc.v:185384.18-185384.106"
+ wire $eq$libresoc.v:185384$13002_Y
+ attribute \src "libresoc.v:185385.18-185385.106"
+ wire $eq$libresoc.v:185385$13003_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
wire \$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
wire width 64 output 20 \fast1$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 21 \fast1_ok
- attribute \src "libresoc.v:187365.7-187365.15"
+ attribute \src "libresoc.v:185118.7-185118.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 28 \muxid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 23 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187626$13089
+ cell $eq $eq$libresoc.v:185379$12997
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187626$13089_Y
+ connect \Y $eq$libresoc.v:185379$12997_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187627$13090
+ cell $eq $eq$libresoc.v:185380$12998
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187627$13090_Y
+ connect \Y $eq$libresoc.v:185380$12998_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187628$13091
+ cell $eq $eq$libresoc.v:185381$12999
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187628$13091_Y
+ connect \Y $eq$libresoc.v:185381$12999_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187629$13092
+ cell $eq $eq$libresoc.v:185382$13000
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187629$13092_Y
+ connect \Y $eq$libresoc.v:185382$13000_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187630$13093
+ cell $eq $eq$libresoc.v:185383$13001
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187630$13093_Y
+ connect \Y $eq$libresoc.v:185383$13001_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:187631$13094
+ cell $eq $eq$libresoc.v:185384$13002
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187631$13094_Y
+ connect \Y $eq$libresoc.v:185384$13002_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82"
- cell $eq $eq$libresoc.v:187632$13095
+ cell $eq $eq$libresoc.v:185385$13003
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:187632$13095_Y
+ connect \Y $eq$libresoc.v:185385$13003_Y
end
- attribute \src "libresoc.v:187365.7-187365.20"
- process $proc$libresoc.v:187365$13125
+ attribute \src "libresoc.v:185118.7-185118.20"
+ process $proc$libresoc.v:185118$13033
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:187633.3-187648.6"
- process $proc$libresoc.v:187633$13096
+ attribute \src "libresoc.v:185386.3-185401.6"
+ process $proc$libresoc.v:185386$13004
assign { } { }
assign { } { }
- assign $0\fast1$7[63:0]$13097 $1\fast1$7[63:0]$13098
- attribute \src "libresoc.v:187634.5-187634.29"
+ assign $0\fast1$7[63:0]$13005 $1\fast1$7[63:0]$13006
+ attribute \src "libresoc.v:185387.5-185387.29"
switch \initial
- attribute \src "libresoc.v:187634.9-187634.17"
+ attribute \src "libresoc.v:185387.9-185387.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\fast1$7[63:0]$13098 $2\fast1$7[63:0]$13099
+ assign $1\fast1$7[63:0]$13006 $2\fast1$7[63:0]$13007
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\fast1$7[63:0]$13099 \ra
+ assign $2\fast1$7[63:0]$13007 \ra
case
- assign $2\fast1$7[63:0]$13099 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast1$7[63:0]$13007 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $1\fast1$7[63:0]$13098 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$7[63:0]$13006 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast1$7 $0\fast1$7[63:0]$13097
+ update \fast1$7 $0\fast1$7[63:0]$13005
end
- attribute \src "libresoc.v:187649.3-187667.6"
- process $proc$libresoc.v:187649$13100
+ attribute \src "libresoc.v:185402.3-185420.6"
+ process $proc$libresoc.v:185402$13008
assign { } { }
assign { } { }
assign $0\spr1_ok[0:0] $1\spr1_ok[0:0]
- attribute \src "libresoc.v:187650.5-187650.29"
+ attribute \src "libresoc.v:185403.5-185403.29"
switch \initial
- attribute \src "libresoc.v:187650.9-187650.17"
+ attribute \src "libresoc.v:185403.9-185403.17"
case 1'1
case
end
sync always
update \spr1_ok $0\spr1_ok[0:0]
end
- attribute \src "libresoc.v:187668.3-187709.6"
- process $proc$libresoc.v:187668$13101
+ attribute \src "libresoc.v:185421.3-185462.6"
+ process $proc$libresoc.v:185421$13009
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:187669.5-187669.29"
+ attribute \src "libresoc.v:185422.5-185422.29"
switch \initial
- attribute \src "libresoc.v:187669.9-187669.17"
+ attribute \src "libresoc.v:185422.9-185422.17"
case 1'1
case
end
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:187710.3-187725.6"
- process $proc$libresoc.v:187710$13102
+ attribute \src "libresoc.v:185463.3-185478.6"
+ process $proc$libresoc.v:185463$13010
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:187711.5-187711.29"
+ attribute \src "libresoc.v:185464.5-185464.29"
switch \initial
- attribute \src "libresoc.v:187711.9-187711.17"
+ attribute \src "libresoc.v:185464.9-185464.17"
case 1'1
case
end
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:187726.3-187746.6"
- process $proc$libresoc.v:187726$13103
+ attribute \src "libresoc.v:185479.3-185499.6"
+ process $proc$libresoc.v:185479$13011
assign { } { }
assign { } { }
- assign $0\xer_so$8[0:0]$13104 $1\xer_so$8[0:0]$13105
- attribute \src "libresoc.v:187727.5-187727.29"
+ assign $0\xer_so$8[0:0]$13012 $1\xer_so$8[0:0]$13013
+ attribute \src "libresoc.v:185480.5-185480.29"
switch \initial
- attribute \src "libresoc.v:187727.9-187727.17"
+ attribute \src "libresoc.v:185480.9-185480.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_so$8[0:0]$13105 $2\xer_so$8[0:0]$13106
+ assign $1\xer_so$8[0:0]$13013 $2\xer_so$8[0:0]$13014
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_so$8[0:0]$13106 $3\xer_so$8[0:0]$13107
+ assign $2\xer_so$8[0:0]$13014 $3\xer_so$8[0:0]$13015
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$11
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_so$8[0:0]$13107 \ra [31]
+ assign $3\xer_so$8[0:0]$13015 \ra [31]
case
- assign $3\xer_so$8[0:0]$13107 1'0
+ assign $3\xer_so$8[0:0]$13015 1'0
end
case
- assign $2\xer_so$8[0:0]$13106 1'0
+ assign $2\xer_so$8[0:0]$13014 1'0
end
case
- assign $1\xer_so$8[0:0]$13105 1'0
+ assign $1\xer_so$8[0:0]$13013 1'0
end
sync always
- update \xer_so$8 $0\xer_so$8[0:0]$13104
+ update \xer_so$8 $0\xer_so$8[0:0]$13012
end
- attribute \src "libresoc.v:187747.3-187767.6"
- process $proc$libresoc.v:187747$13108
+ attribute \src "libresoc.v:185500.3-185520.6"
+ process $proc$libresoc.v:185500$13016
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:187748.5-187748.29"
+ attribute \src "libresoc.v:185501.5-185501.29"
switch \initial
- attribute \src "libresoc.v:187748.9-187748.17"
+ attribute \src "libresoc.v:185501.9-185501.17"
case 1'1
case
end
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:187768.3-187791.6"
- process $proc$libresoc.v:187768$13109
+ attribute \src "libresoc.v:185521.3-185544.6"
+ process $proc$libresoc.v:185521$13017
assign { } { }
assign { } { }
- assign $0\xer_ov$9[1:0]$13110 $1\xer_ov$9[1:0]$13111
- attribute \src "libresoc.v:187769.5-187769.29"
+ assign $0\xer_ov$9[1:0]$13018 $1\xer_ov$9[1:0]$13019
+ attribute \src "libresoc.v:185522.5-185522.29"
switch \initial
- attribute \src "libresoc.v:187769.9-187769.17"
+ attribute \src "libresoc.v:185522.9-185522.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ov$9[1:0]$13111 $2\xer_ov$9[1:0]$13112
+ assign $1\xer_ov$9[1:0]$13019 $2\xer_ov$9[1:0]$13020
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ov$9[1:0]$13112 $3\xer_ov$9[1:0]$13113
+ assign $2\xer_ov$9[1:0]$13020 $3\xer_ov$9[1:0]$13021
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$15
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ov$9[1:0]$13113 [0] \ra [30]
- assign $3\xer_ov$9[1:0]$13113 [1] \ra [19]
+ assign $3\xer_ov$9[1:0]$13021 [0] \ra [30]
+ assign $3\xer_ov$9[1:0]$13021 [1] \ra [19]
case
- assign $3\xer_ov$9[1:0]$13113 2'00
+ assign $3\xer_ov$9[1:0]$13021 2'00
end
case
- assign $2\xer_ov$9[1:0]$13112 2'00
+ assign $2\xer_ov$9[1:0]$13020 2'00
end
case
- assign $1\xer_ov$9[1:0]$13111 2'00
+ assign $1\xer_ov$9[1:0]$13019 2'00
end
sync always
- update \xer_ov$9 $0\xer_ov$9[1:0]$13110
+ update \xer_ov$9 $0\xer_ov$9[1:0]$13018
end
- attribute \src "libresoc.v:187792.3-187812.6"
- process $proc$libresoc.v:187792$13114
+ attribute \src "libresoc.v:185545.3-185565.6"
+ process $proc$libresoc.v:185545$13022
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:187793.5-187793.29"
+ attribute \src "libresoc.v:185546.5-185546.29"
switch \initial
- attribute \src "libresoc.v:187793.9-187793.17"
+ attribute \src "libresoc.v:185546.9-185546.17"
case 1'1
case
end
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:187813.3-187836.6"
- process $proc$libresoc.v:187813$13115
+ attribute \src "libresoc.v:185566.3-185589.6"
+ process $proc$libresoc.v:185566$13023
assign { } { }
assign { } { }
- assign $0\xer_ca$10[1:0]$13116 $1\xer_ca$10[1:0]$13117
- attribute \src "libresoc.v:187814.5-187814.29"
+ assign $0\xer_ca$10[1:0]$13024 $1\xer_ca$10[1:0]$13025
+ attribute \src "libresoc.v:185567.5-185567.29"
switch \initial
- attribute \src "libresoc.v:187814.9-187814.17"
+ attribute \src "libresoc.v:185567.9-185567.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ca$10[1:0]$13117 $2\xer_ca$10[1:0]$13118
+ assign $1\xer_ca$10[1:0]$13025 $2\xer_ca$10[1:0]$13026
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ca$10[1:0]$13118 $3\xer_ca$10[1:0]$13119
+ assign $2\xer_ca$10[1:0]$13026 $3\xer_ca$10[1:0]$13027
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ca$10[1:0]$13119 [0] \ra [29]
- assign $3\xer_ca$10[1:0]$13119 [1] \ra [18]
+ assign $3\xer_ca$10[1:0]$13027 [0] \ra [29]
+ assign $3\xer_ca$10[1:0]$13027 [1] \ra [18]
case
- assign $3\xer_ca$10[1:0]$13119 2'00
+ assign $3\xer_ca$10[1:0]$13027 2'00
end
case
- assign $2\xer_ca$10[1:0]$13118 2'00
+ assign $2\xer_ca$10[1:0]$13026 2'00
end
case
- assign $1\xer_ca$10[1:0]$13117 2'00
+ assign $1\xer_ca$10[1:0]$13025 2'00
end
sync always
- update \xer_ca$10 $0\xer_ca$10[1:0]$13116
+ update \xer_ca$10 $0\xer_ca$10[1:0]$13024
end
- attribute \src "libresoc.v:187837.3-187857.6"
- process $proc$libresoc.v:187837$13120
+ attribute \src "libresoc.v:185590.3-185610.6"
+ process $proc$libresoc.v:185590$13028
assign { } { }
assign { } { }
assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:187838.5-187838.29"
+ attribute \src "libresoc.v:185591.5-185591.29"
switch \initial
- attribute \src "libresoc.v:187838.9-187838.17"
+ attribute \src "libresoc.v:185591.9-185591.17"
case 1'1
case
end
sync always
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:187858.3-187876.6"
- process $proc$libresoc.v:187858$13121
+ attribute \src "libresoc.v:185611.3-185629.6"
+ process $proc$libresoc.v:185611$13029
assign { } { }
assign { } { }
- assign $0\spr1$6[63:0]$13122 $1\spr1$6[63:0]$13123
- attribute \src "libresoc.v:187859.5-187859.29"
+ assign $0\spr1$6[63:0]$13030 $1\spr1$6[63:0]$13031
+ attribute \src "libresoc.v:185612.5-185612.29"
switch \initial
- attribute \src "libresoc.v:187859.9-187859.17"
+ attribute \src "libresoc.v:185612.9-185612.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\spr1$6[63:0]$13123 $2\spr1$6[63:0]$13124
+ assign $1\spr1$6[63:0]$13031 $2\spr1$6[63:0]$13032
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
- assign $2\spr1$6[63:0]$13124 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\spr1$6[63:0]$13032 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\spr1$6[63:0]$13124 \ra
+ assign $2\spr1$6[63:0]$13032 \ra
end
case
- assign $1\spr1$6[63:0]$13123 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\spr1$6[63:0]$13031 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \spr1$6 $0\spr1$6[63:0]$13122
+ update \spr1$6 $0\spr1$6[63:0]$13030
end
- connect \$11 $eq$libresoc.v:187626$13089_Y
- connect \$13 $eq$libresoc.v:187627$13090_Y
- connect \$15 $eq$libresoc.v:187628$13091_Y
- connect \$17 $eq$libresoc.v:187629$13092_Y
- connect \$19 $eq$libresoc.v:187630$13093_Y
- connect \$21 $eq$libresoc.v:187631$13094_Y
- connect \$23 $eq$libresoc.v:187632$13095_Y
+ connect \$11 $eq$libresoc.v:185379$12997_Y
+ connect \$13 $eq$libresoc.v:185380$12998_Y
+ connect \$15 $eq$libresoc.v:185381$12999_Y
+ connect \$17 $eq$libresoc.v:185382$13000_Y
+ connect \$19 $eq$libresoc.v:185383$13001_Y
+ connect \$21 $eq$libresoc.v:185384$13002_Y
+ connect \$23 $eq$libresoc.v:185385$13003_Y
connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
connect \muxid$1 \muxid
connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] }
end
-attribute \src "libresoc.v:187884.1-188720.10"
+attribute \src "libresoc.v:185637.1-186473.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
attribute \generator "nMigen"
module \sprmap
- attribute \src "libresoc.v:188014.3-188044.6"
+ attribute \src "libresoc.v:185767.3-185797.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:188045.3-188075.6"
+ attribute \src "libresoc.v:185798.3-185828.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:187885.7-187885.20"
+ attribute \src "libresoc.v:185638.7-185638.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:188076.3-188397.6"
+ attribute \src "libresoc.v:185829.3-186150.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:188398.3-188719.6"
+ attribute \src "libresoc.v:186151.3-186472.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:188014.3-188044.6"
+ attribute \src "libresoc.v:185767.3-185797.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:188045.3-188075.6"
+ attribute \src "libresoc.v:185798.3-185828.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:188076.3-188397.6"
+ attribute \src "libresoc.v:185829.3-186150.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:188398.3-188719.6"
+ attribute \src "libresoc.v:186151.3-186472.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:187885.7-187885.15"
+ attribute \src "libresoc.v:185638.7-185638.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:187885.7-187885.20"
- process $proc$libresoc.v:187885$13130
+ attribute \src "libresoc.v:185638.7-185638.20"
+ process $proc$libresoc.v:185638$13038
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:188014.3-188044.6"
- process $proc$libresoc.v:188014$13126
+ attribute \src "libresoc.v:185767.3-185797.6"
+ process $proc$libresoc.v:185767$13034
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:188015.5-188015.29"
+ attribute \src "libresoc.v:185768.5-185768.29"
switch \initial
- attribute \src "libresoc.v:188015.9-188015.17"
+ attribute \src "libresoc.v:185768.9-185768.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:188045.3-188075.6"
- process $proc$libresoc.v:188045$13127
+ attribute \src "libresoc.v:185798.3-185828.6"
+ process $proc$libresoc.v:185798$13035
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:188046.5-188046.29"
+ attribute \src "libresoc.v:185799.5-185799.29"
switch \initial
- attribute \src "libresoc.v:188046.9-188046.17"
+ attribute \src "libresoc.v:185799.9-185799.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:188076.3-188397.6"
- process $proc$libresoc.v:188076$13128
+ attribute \src "libresoc.v:185829.3-186150.6"
+ process $proc$libresoc.v:185829$13036
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:188077.5-188077.29"
+ attribute \src "libresoc.v:185830.5-185830.29"
switch \initial
- attribute \src "libresoc.v:188077.9-188077.17"
+ attribute \src "libresoc.v:185830.9-185830.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:188398.3-188719.6"
- process $proc$libresoc.v:188398$13129
+ attribute \src "libresoc.v:186151.3-186472.6"
+ process $proc$libresoc.v:186151$13037
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:188399.5-188399.29"
+ attribute \src "libresoc.v:186152.5-186152.29"
switch \initial
- attribute \src "libresoc.v:188399.9-188399.17"
+ attribute \src "libresoc.v:186152.9-186152.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:188724.1-189560.10"
+attribute \src "libresoc.v:186477.1-187313.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
attribute \generator "nMigen"
module \sprmap$174
- attribute \src "libresoc.v:188854.3-188884.6"
+ attribute \src "libresoc.v:186607.3-186637.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:188885.3-188915.6"
+ attribute \src "libresoc.v:186638.3-186668.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:188725.7-188725.20"
+ attribute \src "libresoc.v:186478.7-186478.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:188916.3-189237.6"
+ attribute \src "libresoc.v:186669.3-186990.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:189238.3-189559.6"
+ attribute \src "libresoc.v:186991.3-187312.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:188854.3-188884.6"
+ attribute \src "libresoc.v:186607.3-186637.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:188885.3-188915.6"
+ attribute \src "libresoc.v:186638.3-186668.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:188916.3-189237.6"
+ attribute \src "libresoc.v:186669.3-186990.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:189238.3-189559.6"
+ attribute \src "libresoc.v:186991.3-187312.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:188725.7-188725.15"
+ attribute \src "libresoc.v:186478.7-186478.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:188725.7-188725.20"
- process $proc$libresoc.v:188725$13135
+ attribute \src "libresoc.v:186478.7-186478.20"
+ process $proc$libresoc.v:186478$13043
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:188854.3-188884.6"
- process $proc$libresoc.v:188854$13131
+ attribute \src "libresoc.v:186607.3-186637.6"
+ process $proc$libresoc.v:186607$13039
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:188855.5-188855.29"
+ attribute \src "libresoc.v:186608.5-186608.29"
switch \initial
- attribute \src "libresoc.v:188855.9-188855.17"
+ attribute \src "libresoc.v:186608.9-186608.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:188885.3-188915.6"
- process $proc$libresoc.v:188885$13132
+ attribute \src "libresoc.v:186638.3-186668.6"
+ process $proc$libresoc.v:186638$13040
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:188886.5-188886.29"
+ attribute \src "libresoc.v:186639.5-186639.29"
switch \initial
- attribute \src "libresoc.v:188886.9-188886.17"
+ attribute \src "libresoc.v:186639.9-186639.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:188916.3-189237.6"
- process $proc$libresoc.v:188916$13133
+ attribute \src "libresoc.v:186669.3-186990.6"
+ process $proc$libresoc.v:186669$13041
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:188917.5-188917.29"
+ attribute \src "libresoc.v:186670.5-186670.29"
switch \initial
- attribute \src "libresoc.v:188917.9-188917.17"
+ attribute \src "libresoc.v:186670.9-186670.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:189238.3-189559.6"
- process $proc$libresoc.v:189238$13134
+ attribute \src "libresoc.v:186991.3-187312.6"
+ process $proc$libresoc.v:186991$13042
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:189239.5-189239.29"
+ attribute \src "libresoc.v:186992.5-186992.29"
switch \initial
- attribute \src "libresoc.v:189239.9-189239.17"
+ attribute \src "libresoc.v:186992.9-186992.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:189564.1-189705.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0"
-attribute \generator "nMigen"
-module \sram4k_0
- attribute \src "libresoc.v:189640.3-189654.6"
- wire width 9 $0\a[8:0]
- attribute \src "libresoc.v:189670.3-189684.6"
- wire width 64 $0\d[63:0]
- attribute \src "libresoc.v:189565.7-189565.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:189625.3-189639.6"
- wire $0\sram4k_0_wb__ack$next[0:0]$13140
- attribute \src "libresoc.v:189605.3-189606.49"
- wire $0\sram4k_0_wb__ack[0:0]
- attribute \src "libresoc.v:189655.3-189669.6"
- wire width 64 $0\sram4k_0_wb__dat_r[63:0]
- attribute \src "libresoc.v:189615.3-189624.6"
- wire $0\wb_active[0:0]
- attribute \src "libresoc.v:189685.3-189704.6"
- wire $0\we[0:0]
- attribute \src "libresoc.v:189640.3-189654.6"
- wire width 9 $1\a[8:0]
- attribute \src "libresoc.v:189670.3-189684.6"
- wire width 64 $1\d[63:0]
- attribute \src "libresoc.v:189625.3-189639.6"
- wire $1\sram4k_0_wb__ack$next[0:0]$13141
- attribute \src "libresoc.v:189582.7-189582.30"
- wire $1\sram4k_0_wb__ack[0:0]
- attribute \src "libresoc.v:189655.3-189669.6"
- wire width 64 $1\sram4k_0_wb__dat_r[63:0]
- attribute \src "libresoc.v:189615.3-189624.6"
- wire $1\wb_active[0:0]
- attribute \src "libresoc.v:189685.3-189704.6"
- wire $1\we[0:0]
- attribute \src "libresoc.v:189640.3-189654.6"
- wire width 9 $2\a[8:0]
- attribute \src "libresoc.v:189670.3-189684.6"
- wire width 64 $2\d[63:0]
- attribute \src "libresoc.v:189625.3-189639.6"
- wire $2\sram4k_0_wb__ack$next[0:0]$13142
- attribute \src "libresoc.v:189655.3-189669.6"
- wire width 64 $2\sram4k_0_wb__dat_r[63:0]
- attribute \src "libresoc.v:189685.3-189704.6"
- wire $2\we[0:0]
- attribute \src "libresoc.v:189685.3-189704.6"
- wire $3\we[0:0]
- attribute \src "libresoc.v:189604.17-189604.129"
- wire $and$libresoc.v:189604$13136_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
- wire width 9 \a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 11 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
- wire width 64 \d
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire input 2 \enable
- attribute \src "libresoc.v:189565.7-189565.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
- wire width 64 \q
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 5 \sram4k_0_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire \sram4k_0_wb__ack$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 6 \sram4k_0_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 3 \sram4k_0_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 7 \sram4k_0_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 8 \sram4k_0_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 10 \sram4k_0_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 4 \sram4k_0_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 9 \sram4k_0_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54"
- wire \wb_active
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41"
- wire \we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- cell $and $and$libresoc.v:189604$13136
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \sram4k_0_wb__cyc
- connect \B \sram4k_0_wb__stb
- connect \Y $and$libresoc.v:189604$13136_Y
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:189608.21-189614.4"
- cell \SPBlock_512W64B8W \U$$0
- connect \a \a
- connect \clk \clk
- connect \d \d
- connect \q \q
- connect \we \we
- end
- attribute \src "libresoc.v:189565.7-189565.20"
- process $proc$libresoc.v:189565$13147
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:189582.7-189582.30"
- process $proc$libresoc.v:189582$13148
- assign { } { }
- assign $1\sram4k_0_wb__ack[0:0] 1'0
- sync always
- sync init
- update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189605.3-189606.49"
- process $proc$libresoc.v:189605$13137
- assign { } { }
- assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next
- sync posedge \clk
- update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189615.3-189624.6"
- process $proc$libresoc.v:189615$13138
- assign { } { }
- assign { } { }
- assign $0\wb_active[0:0] $1\wb_active[0:0]
- attribute \src "libresoc.v:189616.5-189616.29"
- switch \initial
- attribute \src "libresoc.v:189616.9-189616.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wb_active[0:0] \$1
- case
- assign $1\wb_active[0:0] 1'0
- end
- sync always
- update \wb_active $0\wb_active[0:0]
- end
- attribute \src "libresoc.v:189625.3-189639.6"
- process $proc$libresoc.v:189625$13139
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\sram4k_0_wb__ack$next[0:0]$13140 $2\sram4k_0_wb__ack$next[0:0]$13142
- attribute \src "libresoc.v:189626.5-189626.29"
- switch \initial
- attribute \src "libresoc.v:189626.9-189626.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_0_wb__ack$next[0:0]$13141 \wb_active
- case
- assign $1\sram4k_0_wb__ack$next[0:0]$13141 \sram4k_0_wb__ack
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_0_wb__ack$next[0:0]$13142 1'0
- case
- assign $2\sram4k_0_wb__ack$next[0:0]$13142 $1\sram4k_0_wb__ack$next[0:0]$13141
- end
- sync always
- update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13140
- end
- attribute \src "libresoc.v:189640.3-189654.6"
- process $proc$libresoc.v:189640$13143
- assign { } { }
- assign { } { }
- assign $0\a[8:0] $1\a[8:0]
- attribute \src "libresoc.v:189641.5-189641.29"
- switch \initial
- attribute \src "libresoc.v:189641.9-189641.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\a[8:0] $2\a[8:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\a[8:0] \sram4k_0_wb__adr
- case
- assign $2\a[8:0] 9'000000000
- end
- case
- assign $1\a[8:0] 9'000000000
- end
- sync always
- update \a $0\a[8:0]
- end
- attribute \src "libresoc.v:189655.3-189669.6"
- process $proc$libresoc.v:189655$13144
- assign { } { }
- assign { } { }
- assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0]
- attribute \src "libresoc.v:189656.5-189656.29"
- switch \initial
- attribute \src "libresoc.v:189656.9-189656.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_0_wb__dat_r[63:0] \q
- case
- assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0]
- end
- attribute \src "libresoc.v:189670.3-189684.6"
- process $proc$libresoc.v:189670$13145
- assign { } { }
- assign { } { }
- assign $0\d[63:0] $1\d[63:0]
- attribute \src "libresoc.v:189671.5-189671.29"
- switch \initial
- attribute \src "libresoc.v:189671.9-189671.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\d[63:0] $2\d[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\d[63:0] \sram4k_0_wb__dat_w
- case
- assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \d $0\d[63:0]
- end
- attribute \src "libresoc.v:189685.3-189704.6"
- process $proc$libresoc.v:189685$13146
- assign { } { }
- assign { } { }
- assign $0\we[0:0] $1\we[0:0]
- attribute \src "libresoc.v:189686.5-189686.29"
- switch \initial
- attribute \src "libresoc.v:189686.9-189686.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\we[0:0] $2\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\we[0:0] $3\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70"
- switch \sram4k_0_wb__we
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\we[0:0] \sram4k_0_wb__sel [0]
- case
- assign $3\we[0:0] 1'0
- end
- case
- assign $2\we[0:0] 1'0
- end
- case
- assign $1\we[0:0] 1'0
- end
- sync always
- update \we $0\we[0:0]
- end
- connect \$1 $and$libresoc.v:189604$13136_Y
-end
-attribute \src "libresoc.v:189709.1-189850.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1"
-attribute \generator "nMigen"
-module \sram4k_1
- attribute \src "libresoc.v:189785.3-189799.6"
- wire width 9 $0\a[8:0]
- attribute \src "libresoc.v:189815.3-189829.6"
- wire width 64 $0\d[63:0]
- attribute \src "libresoc.v:189710.7-189710.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:189770.3-189784.6"
- wire $0\sram4k_1_wb__ack$next[0:0]$13153
- attribute \src "libresoc.v:189750.3-189751.49"
- wire $0\sram4k_1_wb__ack[0:0]
- attribute \src "libresoc.v:189800.3-189814.6"
- wire width 64 $0\sram4k_1_wb__dat_r[63:0]
- attribute \src "libresoc.v:189760.3-189769.6"
- wire $0\wb_active[0:0]
- attribute \src "libresoc.v:189830.3-189849.6"
- wire $0\we[0:0]
- attribute \src "libresoc.v:189785.3-189799.6"
- wire width 9 $1\a[8:0]
- attribute \src "libresoc.v:189815.3-189829.6"
- wire width 64 $1\d[63:0]
- attribute \src "libresoc.v:189770.3-189784.6"
- wire $1\sram4k_1_wb__ack$next[0:0]$13154
- attribute \src "libresoc.v:189727.7-189727.30"
- wire $1\sram4k_1_wb__ack[0:0]
- attribute \src "libresoc.v:189800.3-189814.6"
- wire width 64 $1\sram4k_1_wb__dat_r[63:0]
- attribute \src "libresoc.v:189760.3-189769.6"
- wire $1\wb_active[0:0]
- attribute \src "libresoc.v:189830.3-189849.6"
- wire $1\we[0:0]
- attribute \src "libresoc.v:189785.3-189799.6"
- wire width 9 $2\a[8:0]
- attribute \src "libresoc.v:189815.3-189829.6"
- wire width 64 $2\d[63:0]
- attribute \src "libresoc.v:189770.3-189784.6"
- wire $2\sram4k_1_wb__ack$next[0:0]$13155
- attribute \src "libresoc.v:189800.3-189814.6"
- wire width 64 $2\sram4k_1_wb__dat_r[63:0]
- attribute \src "libresoc.v:189830.3-189849.6"
- wire $2\we[0:0]
- attribute \src "libresoc.v:189830.3-189849.6"
- wire $3\we[0:0]
- attribute \src "libresoc.v:189749.17-189749.129"
- wire $and$libresoc.v:189749$13149_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
- wire width 9 \a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 11 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
- wire width 64 \d
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire input 2 \enable
- attribute \src "libresoc.v:189710.7-189710.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
- wire width 64 \q
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 5 \sram4k_1_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire \sram4k_1_wb__ack$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 6 \sram4k_1_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 3 \sram4k_1_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 7 \sram4k_1_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 8 \sram4k_1_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 10 \sram4k_1_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 4 \sram4k_1_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 9 \sram4k_1_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54"
- wire \wb_active
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41"
- wire \we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- cell $and $and$libresoc.v:189749$13149
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \sram4k_1_wb__cyc
- connect \B \sram4k_1_wb__stb
- connect \Y $and$libresoc.v:189749$13149_Y
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:189753.21-189759.4"
- cell \SPBlock_512W64B8W \U$$0
- connect \a \a
- connect \clk \clk
- connect \d \d
- connect \q \q
- connect \we \we
- end
- attribute \src "libresoc.v:189710.7-189710.20"
- process $proc$libresoc.v:189710$13160
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:189727.7-189727.30"
- process $proc$libresoc.v:189727$13161
- assign { } { }
- assign $1\sram4k_1_wb__ack[0:0] 1'0
- sync always
- sync init
- update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189750.3-189751.49"
- process $proc$libresoc.v:189750$13150
- assign { } { }
- assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next
- sync posedge \clk
- update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189760.3-189769.6"
- process $proc$libresoc.v:189760$13151
- assign { } { }
- assign { } { }
- assign $0\wb_active[0:0] $1\wb_active[0:0]
- attribute \src "libresoc.v:189761.5-189761.29"
- switch \initial
- attribute \src "libresoc.v:189761.9-189761.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wb_active[0:0] \$1
- case
- assign $1\wb_active[0:0] 1'0
- end
- sync always
- update \wb_active $0\wb_active[0:0]
- end
- attribute \src "libresoc.v:189770.3-189784.6"
- process $proc$libresoc.v:189770$13152
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\sram4k_1_wb__ack$next[0:0]$13153 $2\sram4k_1_wb__ack$next[0:0]$13155
- attribute \src "libresoc.v:189771.5-189771.29"
- switch \initial
- attribute \src "libresoc.v:189771.9-189771.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_1_wb__ack$next[0:0]$13154 \wb_active
- case
- assign $1\sram4k_1_wb__ack$next[0:0]$13154 \sram4k_1_wb__ack
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_1_wb__ack$next[0:0]$13155 1'0
- case
- assign $2\sram4k_1_wb__ack$next[0:0]$13155 $1\sram4k_1_wb__ack$next[0:0]$13154
- end
- sync always
- update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13153
- end
- attribute \src "libresoc.v:189785.3-189799.6"
- process $proc$libresoc.v:189785$13156
- assign { } { }
- assign { } { }
- assign $0\a[8:0] $1\a[8:0]
- attribute \src "libresoc.v:189786.5-189786.29"
- switch \initial
- attribute \src "libresoc.v:189786.9-189786.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\a[8:0] $2\a[8:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\a[8:0] \sram4k_1_wb__adr
- case
- assign $2\a[8:0] 9'000000000
- end
- case
- assign $1\a[8:0] 9'000000000
- end
- sync always
- update \a $0\a[8:0]
- end
- attribute \src "libresoc.v:189800.3-189814.6"
- process $proc$libresoc.v:189800$13157
- assign { } { }
- assign { } { }
- assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0]
- attribute \src "libresoc.v:189801.5-189801.29"
- switch \initial
- attribute \src "libresoc.v:189801.9-189801.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_1_wb__dat_r[63:0] \q
- case
- assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0]
- end
- attribute \src "libresoc.v:189815.3-189829.6"
- process $proc$libresoc.v:189815$13158
- assign { } { }
- assign { } { }
- assign $0\d[63:0] $1\d[63:0]
- attribute \src "libresoc.v:189816.5-189816.29"
- switch \initial
- attribute \src "libresoc.v:189816.9-189816.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\d[63:0] $2\d[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\d[63:0] \sram4k_1_wb__dat_w
- case
- assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \d $0\d[63:0]
- end
- attribute \src "libresoc.v:189830.3-189849.6"
- process $proc$libresoc.v:189830$13159
- assign { } { }
- assign { } { }
- assign $0\we[0:0] $1\we[0:0]
- attribute \src "libresoc.v:189831.5-189831.29"
- switch \initial
- attribute \src "libresoc.v:189831.9-189831.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\we[0:0] $2\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\we[0:0] $3\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70"
- switch \sram4k_1_wb__we
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\we[0:0] \sram4k_1_wb__sel [0]
- case
- assign $3\we[0:0] 1'0
- end
- case
- assign $2\we[0:0] 1'0
- end
- case
- assign $1\we[0:0] 1'0
- end
- sync always
- update \we $0\we[0:0]
- end
- connect \$1 $and$libresoc.v:189749$13149_Y
-end
-attribute \src "libresoc.v:189854.1-189995.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2"
-attribute \generator "nMigen"
-module \sram4k_2
- attribute \src "libresoc.v:189930.3-189944.6"
- wire width 9 $0\a[8:0]
- attribute \src "libresoc.v:189960.3-189974.6"
- wire width 64 $0\d[63:0]
- attribute \src "libresoc.v:189855.7-189855.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:189915.3-189929.6"
- wire $0\sram4k_2_wb__ack$next[0:0]$13166
- attribute \src "libresoc.v:189895.3-189896.49"
- wire $0\sram4k_2_wb__ack[0:0]
- attribute \src "libresoc.v:189945.3-189959.6"
- wire width 64 $0\sram4k_2_wb__dat_r[63:0]
- attribute \src "libresoc.v:189905.3-189914.6"
- wire $0\wb_active[0:0]
- attribute \src "libresoc.v:189975.3-189994.6"
- wire $0\we[0:0]
- attribute \src "libresoc.v:189930.3-189944.6"
- wire width 9 $1\a[8:0]
- attribute \src "libresoc.v:189960.3-189974.6"
- wire width 64 $1\d[63:0]
- attribute \src "libresoc.v:189915.3-189929.6"
- wire $1\sram4k_2_wb__ack$next[0:0]$13167
- attribute \src "libresoc.v:189872.7-189872.30"
- wire $1\sram4k_2_wb__ack[0:0]
- attribute \src "libresoc.v:189945.3-189959.6"
- wire width 64 $1\sram4k_2_wb__dat_r[63:0]
- attribute \src "libresoc.v:189905.3-189914.6"
- wire $1\wb_active[0:0]
- attribute \src "libresoc.v:189975.3-189994.6"
- wire $1\we[0:0]
- attribute \src "libresoc.v:189930.3-189944.6"
- wire width 9 $2\a[8:0]
- attribute \src "libresoc.v:189960.3-189974.6"
- wire width 64 $2\d[63:0]
- attribute \src "libresoc.v:189915.3-189929.6"
- wire $2\sram4k_2_wb__ack$next[0:0]$13168
- attribute \src "libresoc.v:189945.3-189959.6"
- wire width 64 $2\sram4k_2_wb__dat_r[63:0]
- attribute \src "libresoc.v:189975.3-189994.6"
- wire $2\we[0:0]
- attribute \src "libresoc.v:189975.3-189994.6"
- wire $3\we[0:0]
- attribute \src "libresoc.v:189894.17-189894.129"
- wire $and$libresoc.v:189894$13162_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
- wire width 9 \a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 11 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
- wire width 64 \d
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire input 2 \enable
- attribute \src "libresoc.v:189855.7-189855.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
- wire width 64 \q
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 5 \sram4k_2_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire \sram4k_2_wb__ack$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 6 \sram4k_2_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 3 \sram4k_2_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 7 \sram4k_2_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 8 \sram4k_2_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 10 \sram4k_2_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 4 \sram4k_2_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 9 \sram4k_2_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54"
- wire \wb_active
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41"
- wire \we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- cell $and $and$libresoc.v:189894$13162
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \sram4k_2_wb__cyc
- connect \B \sram4k_2_wb__stb
- connect \Y $and$libresoc.v:189894$13162_Y
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:189898.21-189904.4"
- cell \SPBlock_512W64B8W \U$$0
- connect \a \a
- connect \clk \clk
- connect \d \d
- connect \q \q
- connect \we \we
- end
- attribute \src "libresoc.v:189855.7-189855.20"
- process $proc$libresoc.v:189855$13173
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:189872.7-189872.30"
- process $proc$libresoc.v:189872$13174
- assign { } { }
- assign $1\sram4k_2_wb__ack[0:0] 1'0
- sync always
- sync init
- update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189895.3-189896.49"
- process $proc$libresoc.v:189895$13163
- assign { } { }
- assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next
- sync posedge \clk
- update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0]
- end
- attribute \src "libresoc.v:189905.3-189914.6"
- process $proc$libresoc.v:189905$13164
- assign { } { }
- assign { } { }
- assign $0\wb_active[0:0] $1\wb_active[0:0]
- attribute \src "libresoc.v:189906.5-189906.29"
- switch \initial
- attribute \src "libresoc.v:189906.9-189906.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wb_active[0:0] \$1
- case
- assign $1\wb_active[0:0] 1'0
- end
- sync always
- update \wb_active $0\wb_active[0:0]
- end
- attribute \src "libresoc.v:189915.3-189929.6"
- process $proc$libresoc.v:189915$13165
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\sram4k_2_wb__ack$next[0:0]$13166 $2\sram4k_2_wb__ack$next[0:0]$13168
- attribute \src "libresoc.v:189916.5-189916.29"
- switch \initial
- attribute \src "libresoc.v:189916.9-189916.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_2_wb__ack$next[0:0]$13167 \wb_active
- case
- assign $1\sram4k_2_wb__ack$next[0:0]$13167 \sram4k_2_wb__ack
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_2_wb__ack$next[0:0]$13168 1'0
- case
- assign $2\sram4k_2_wb__ack$next[0:0]$13168 $1\sram4k_2_wb__ack$next[0:0]$13167
- end
- sync always
- update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13166
- end
- attribute \src "libresoc.v:189930.3-189944.6"
- process $proc$libresoc.v:189930$13169
- assign { } { }
- assign { } { }
- assign $0\a[8:0] $1\a[8:0]
- attribute \src "libresoc.v:189931.5-189931.29"
- switch \initial
- attribute \src "libresoc.v:189931.9-189931.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\a[8:0] $2\a[8:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\a[8:0] \sram4k_2_wb__adr
- case
- assign $2\a[8:0] 9'000000000
- end
- case
- assign $1\a[8:0] 9'000000000
- end
- sync always
- update \a $0\a[8:0]
- end
- attribute \src "libresoc.v:189945.3-189959.6"
- process $proc$libresoc.v:189945$13170
- assign { } { }
- assign { } { }
- assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0]
- attribute \src "libresoc.v:189946.5-189946.29"
- switch \initial
- attribute \src "libresoc.v:189946.9-189946.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_2_wb__dat_r[63:0] \q
- case
- assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0]
- end
- attribute \src "libresoc.v:189960.3-189974.6"
- process $proc$libresoc.v:189960$13171
- assign { } { }
- assign { } { }
- assign $0\d[63:0] $1\d[63:0]
- attribute \src "libresoc.v:189961.5-189961.29"
- switch \initial
- attribute \src "libresoc.v:189961.9-189961.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\d[63:0] $2\d[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\d[63:0] \sram4k_2_wb__dat_w
- case
- assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \d $0\d[63:0]
- end
- attribute \src "libresoc.v:189975.3-189994.6"
- process $proc$libresoc.v:189975$13172
- assign { } { }
- assign { } { }
- assign $0\we[0:0] $1\we[0:0]
- attribute \src "libresoc.v:189976.5-189976.29"
- switch \initial
- attribute \src "libresoc.v:189976.9-189976.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\we[0:0] $2\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\we[0:0] $3\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70"
- switch \sram4k_2_wb__we
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\we[0:0] \sram4k_2_wb__sel [0]
- case
- assign $3\we[0:0] 1'0
- end
- case
- assign $2\we[0:0] 1'0
- end
- case
- assign $1\we[0:0] 1'0
- end
- sync always
- update \we $0\we[0:0]
- end
- connect \$1 $and$libresoc.v:189894$13162_Y
-end
-attribute \src "libresoc.v:189999.1-190140.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3"
-attribute \generator "nMigen"
-module \sram4k_3
- attribute \src "libresoc.v:190075.3-190089.6"
- wire width 9 $0\a[8:0]
- attribute \src "libresoc.v:190105.3-190119.6"
- wire width 64 $0\d[63:0]
- attribute \src "libresoc.v:190000.7-190000.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:190060.3-190074.6"
- wire $0\sram4k_3_wb__ack$next[0:0]$13179
- attribute \src "libresoc.v:190040.3-190041.49"
- wire $0\sram4k_3_wb__ack[0:0]
- attribute \src "libresoc.v:190090.3-190104.6"
- wire width 64 $0\sram4k_3_wb__dat_r[63:0]
- attribute \src "libresoc.v:190050.3-190059.6"
- wire $0\wb_active[0:0]
- attribute \src "libresoc.v:190120.3-190139.6"
- wire $0\we[0:0]
- attribute \src "libresoc.v:190075.3-190089.6"
- wire width 9 $1\a[8:0]
- attribute \src "libresoc.v:190105.3-190119.6"
- wire width 64 $1\d[63:0]
- attribute \src "libresoc.v:190060.3-190074.6"
- wire $1\sram4k_3_wb__ack$next[0:0]$13180
- attribute \src "libresoc.v:190017.7-190017.30"
- wire $1\sram4k_3_wb__ack[0:0]
- attribute \src "libresoc.v:190090.3-190104.6"
- wire width 64 $1\sram4k_3_wb__dat_r[63:0]
- attribute \src "libresoc.v:190050.3-190059.6"
- wire $1\wb_active[0:0]
- attribute \src "libresoc.v:190120.3-190139.6"
- wire $1\we[0:0]
- attribute \src "libresoc.v:190075.3-190089.6"
- wire width 9 $2\a[8:0]
- attribute \src "libresoc.v:190105.3-190119.6"
- wire width 64 $2\d[63:0]
- attribute \src "libresoc.v:190060.3-190074.6"
- wire $2\sram4k_3_wb__ack$next[0:0]$13181
- attribute \src "libresoc.v:190090.3-190104.6"
- wire width 64 $2\sram4k_3_wb__dat_r[63:0]
- attribute \src "libresoc.v:190120.3-190139.6"
- wire $2\we[0:0]
- attribute \src "libresoc.v:190120.3-190139.6"
- wire $3\we[0:0]
- attribute \src "libresoc.v:190039.17-190039.129"
- wire $and$libresoc.v:190039$13175_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
- wire width 9 \a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 11 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
- wire width 64 \d
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire input 2 \enable
- attribute \src "libresoc.v:190000.7-190000.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
- wire width 64 \q
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 5 \sram4k_3_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire \sram4k_3_wb__ack$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 6 \sram4k_3_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 3 \sram4k_3_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 7 \sram4k_3_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 8 \sram4k_3_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 10 \sram4k_3_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 4 \sram4k_3_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 9 \sram4k_3_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54"
- wire \wb_active
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41"
- wire \we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55"
- cell $and $and$libresoc.v:190039$13175
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \sram4k_3_wb__cyc
- connect \B \sram4k_3_wb__stb
- connect \Y $and$libresoc.v:190039$13175_Y
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:190043.21-190049.4"
- cell \SPBlock_512W64B8W \U$$0
- connect \a \a
- connect \clk \clk
- connect \d \d
- connect \q \q
- connect \we \we
- end
- attribute \src "libresoc.v:190000.7-190000.20"
- process $proc$libresoc.v:190000$13186
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:190017.7-190017.30"
- process $proc$libresoc.v:190017$13187
- assign { } { }
- assign $1\sram4k_3_wb__ack[0:0] 1'0
- sync always
- sync init
- update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0]
- end
- attribute \src "libresoc.v:190040.3-190041.49"
- process $proc$libresoc.v:190040$13176
- assign { } { }
- assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next
- sync posedge \clk
- update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0]
- end
- attribute \src "libresoc.v:190050.3-190059.6"
- process $proc$libresoc.v:190050$13177
- assign { } { }
- assign { } { }
- assign $0\wb_active[0:0] $1\wb_active[0:0]
- attribute \src "libresoc.v:190051.5-190051.29"
- switch \initial
- attribute \src "libresoc.v:190051.9-190051.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\wb_active[0:0] \$1
- case
- assign $1\wb_active[0:0] 1'0
- end
- sync always
- update \wb_active $0\wb_active[0:0]
- end
- attribute \src "libresoc.v:190060.3-190074.6"
- process $proc$libresoc.v:190060$13178
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\sram4k_3_wb__ack$next[0:0]$13179 $2\sram4k_3_wb__ack$next[0:0]$13181
- attribute \src "libresoc.v:190061.5-190061.29"
- switch \initial
- attribute \src "libresoc.v:190061.9-190061.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_3_wb__ack$next[0:0]$13180 \wb_active
- case
- assign $1\sram4k_3_wb__ack$next[0:0]$13180 \sram4k_3_wb__ack
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_3_wb__ack$next[0:0]$13181 1'0
- case
- assign $2\sram4k_3_wb__ack$next[0:0]$13181 $1\sram4k_3_wb__ack$next[0:0]$13180
- end
- sync always
- update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13179
- end
- attribute \src "libresoc.v:190075.3-190089.6"
- process $proc$libresoc.v:190075$13182
- assign { } { }
- assign { } { }
- assign $0\a[8:0] $1\a[8:0]
- attribute \src "libresoc.v:190076.5-190076.29"
- switch \initial
- attribute \src "libresoc.v:190076.9-190076.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\a[8:0] $2\a[8:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\a[8:0] \sram4k_3_wb__adr
- case
- assign $2\a[8:0] 9'000000000
- end
- case
- assign $1\a[8:0] 9'000000000
- end
- sync always
- update \a $0\a[8:0]
- end
- attribute \src "libresoc.v:190090.3-190104.6"
- process $proc$libresoc.v:190090$13183
- assign { } { }
- assign { } { }
- assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0]
- attribute \src "libresoc.v:190091.5-190091.29"
- switch \initial
- attribute \src "libresoc.v:190091.9-190091.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sram4k_3_wb__dat_r[63:0] \q
- case
- assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0]
- end
- attribute \src "libresoc.v:190105.3-190119.6"
- process $proc$libresoc.v:190105$13184
- assign { } { }
- assign { } { }
- assign $0\d[63:0] $1\d[63:0]
- attribute \src "libresoc.v:190106.5-190106.29"
- switch \initial
- attribute \src "libresoc.v:190106.9-190106.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\d[63:0] $2\d[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\d[63:0] \sram4k_3_wb__dat_w
- case
- assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- case
- assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync always
- update \d $0\d[63:0]
- end
- attribute \src "libresoc.v:190120.3-190139.6"
- process $proc$libresoc.v:190120$13185
- assign { } { }
- assign { } { }
- assign $0\we[0:0] $1\we[0:0]
- attribute \src "libresoc.v:190121.5-190121.29"
- switch \initial
- attribute \src "libresoc.v:190121.9-190121.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52"
- switch \enable
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\we[0:0] $2\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60"
- switch \wb_active
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\we[0:0] $3\we[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70"
- switch \sram4k_3_wb__we
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\we[0:0] \sram4k_3_wb__sel [0]
- case
- assign $3\we[0:0] 1'0
- end
- case
- assign $2\we[0:0] 1'0
- end
- case
- assign $1\we[0:0] 1'0
- end
- sync always
- update \we $0\we[0:0]
- end
- connect \$1 $and$libresoc.v:190039$13175_Y
-end
-attribute \src "libresoc.v:190144.1-190202.10"
+attribute \src "libresoc.v:187317.1-187375.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l"
attribute \generator "nMigen"
module \src_l
- attribute \src "libresoc.v:190145.7-190145.20"
+ attribute \src "libresoc.v:187318.7-187318.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190190.3-190198.6"
- wire width 4 $0\q_int$next[3:0]$13198
- attribute \src "libresoc.v:190188.3-190189.27"
+ attribute \src "libresoc.v:187363.3-187371.6"
+ wire width 4 $0\q_int$next[3:0]$13054
+ attribute \src "libresoc.v:187361.3-187362.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:190190.3-190198.6"
- wire width 4 $1\q_int$next[3:0]$13199
- attribute \src "libresoc.v:190167.13-190167.25"
+ attribute \src "libresoc.v:187363.3-187371.6"
+ wire width 4 $1\q_int$next[3:0]$13055
+ attribute \src "libresoc.v:187340.13-187340.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:190180.17-190180.96"
- wire width 4 $and$libresoc.v:190180$13188_Y
- attribute \src "libresoc.v:190185.17-190185.96"
- wire width 4 $and$libresoc.v:190185$13193_Y
- attribute \src "libresoc.v:190182.18-190182.93"
- wire width 4 $not$libresoc.v:190182$13190_Y
- attribute \src "libresoc.v:190184.17-190184.92"
- wire width 4 $not$libresoc.v:190184$13192_Y
- attribute \src "libresoc.v:190187.17-190187.92"
- wire width 4 $not$libresoc.v:190187$13195_Y
- attribute \src "libresoc.v:190181.18-190181.98"
- wire width 4 $or$libresoc.v:190181$13189_Y
- attribute \src "libresoc.v:190183.18-190183.99"
- wire width 4 $or$libresoc.v:190183$13191_Y
- attribute \src "libresoc.v:190186.17-190186.97"
- wire width 4 $or$libresoc.v:190186$13194_Y
+ attribute \src "libresoc.v:187353.17-187353.96"
+ wire width 4 $and$libresoc.v:187353$13044_Y
+ attribute \src "libresoc.v:187358.17-187358.96"
+ wire width 4 $and$libresoc.v:187358$13049_Y
+ attribute \src "libresoc.v:187355.18-187355.93"
+ wire width 4 $not$libresoc.v:187355$13046_Y
+ attribute \src "libresoc.v:187357.17-187357.92"
+ wire width 4 $not$libresoc.v:187357$13048_Y
+ attribute \src "libresoc.v:187360.17-187360.92"
+ wire width 4 $not$libresoc.v:187360$13051_Y
+ attribute \src "libresoc.v:187354.18-187354.98"
+ wire width 4 $or$libresoc.v:187354$13045_Y
+ attribute \src "libresoc.v:187356.18-187356.99"
+ wire width 4 $or$libresoc.v:187356$13047_Y
+ attribute \src "libresoc.v:187359.17-187359.97"
+ wire width 4 $or$libresoc.v:187359$13050_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190145.7-190145.15"
+ attribute \src "libresoc.v:187318.7-187318.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190180$13188
+ cell $and $and$libresoc.v:187353$13044
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190180$13188_Y
+ connect \Y $and$libresoc.v:187353$13044_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190185$13193
+ cell $and $and$libresoc.v:187358$13049
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190185$13193_Y
+ connect \Y $and$libresoc.v:187358$13049_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190182$13190
+ cell $not $not$libresoc.v:187355$13046
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:190182$13190_Y
+ connect \Y $not$libresoc.v:187355$13046_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190184$13192
+ cell $not $not$libresoc.v:187357$13048
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:190184$13192_Y
+ connect \Y $not$libresoc.v:187357$13048_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190187$13195
+ cell $not $not$libresoc.v:187360$13051
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:190187$13195_Y
+ connect \Y $not$libresoc.v:187360$13051_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190181$13189
+ cell $or $or$libresoc.v:187354$13045
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190181$13189_Y
+ connect \Y $or$libresoc.v:187354$13045_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190183$13191
+ cell $or $or$libresoc.v:187356$13047
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190183$13191_Y
+ connect \Y $or$libresoc.v:187356$13047_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190186$13194
+ cell $or $or$libresoc.v:187359$13050
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190186$13194_Y
+ connect \Y $or$libresoc.v:187359$13050_Y
end
- attribute \src "libresoc.v:190145.7-190145.20"
- process $proc$libresoc.v:190145$13200
+ attribute \src "libresoc.v:187318.7-187318.20"
+ process $proc$libresoc.v:187318$13056
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190167.13-190167.25"
- process $proc$libresoc.v:190167$13201
+ attribute \src "libresoc.v:187340.13-187340.25"
+ process $proc$libresoc.v:187340$13057
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:190188.3-190189.27"
- process $proc$libresoc.v:190188$13196
+ attribute \src "libresoc.v:187361.3-187362.27"
+ process $proc$libresoc.v:187361$13052
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:190190.3-190198.6"
- process $proc$libresoc.v:190190$13197
+ attribute \src "libresoc.v:187363.3-187371.6"
+ process $proc$libresoc.v:187363$13053
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13198 $1\q_int$next[3:0]$13199
- attribute \src "libresoc.v:190191.5-190191.29"
+ assign $0\q_int$next[3:0]$13054 $1\q_int$next[3:0]$13055
+ attribute \src "libresoc.v:187364.5-187364.29"
switch \initial
- attribute \src "libresoc.v:190191.9-190191.17"
+ attribute \src "libresoc.v:187364.9-187364.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13199 4'0000
+ assign $1\q_int$next[3:0]$13055 4'0000
case
- assign $1\q_int$next[3:0]$13199 \$5
+ assign $1\q_int$next[3:0]$13055 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13198
+ update \q_int$next $0\q_int$next[3:0]$13054
end
- connect \$9 $and$libresoc.v:190180$13188_Y
- connect \$11 $or$libresoc.v:190181$13189_Y
- connect \$13 $not$libresoc.v:190182$13190_Y
- connect \$15 $or$libresoc.v:190183$13191_Y
- connect \$1 $not$libresoc.v:190184$13192_Y
- connect \$3 $and$libresoc.v:190185$13193_Y
- connect \$5 $or$libresoc.v:190186$13194_Y
- connect \$7 $not$libresoc.v:190187$13195_Y
+ connect \$9 $and$libresoc.v:187353$13044_Y
+ connect \$11 $or$libresoc.v:187354$13045_Y
+ connect \$13 $not$libresoc.v:187355$13046_Y
+ connect \$15 $or$libresoc.v:187356$13047_Y
+ connect \$1 $not$libresoc.v:187357$13048_Y
+ connect \$3 $and$libresoc.v:187358$13049_Y
+ connect \$5 $or$libresoc.v:187359$13050_Y
+ connect \$7 $not$libresoc.v:187360$13051_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190206.1-190264.10"
+attribute \src "libresoc.v:187379.1-187437.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l"
attribute \generator "nMigen"
module \src_l$10
- attribute \src "libresoc.v:190207.7-190207.20"
+ attribute \src "libresoc.v:187380.7-187380.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190252.3-190260.6"
- wire width 6 $0\q_int$next[5:0]$13212
- attribute \src "libresoc.v:190250.3-190251.27"
+ attribute \src "libresoc.v:187425.3-187433.6"
+ wire width 6 $0\q_int$next[5:0]$13068
+ attribute \src "libresoc.v:187423.3-187424.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:190252.3-190260.6"
- wire width 6 $1\q_int$next[5:0]$13213
- attribute \src "libresoc.v:190229.13-190229.26"
+ attribute \src "libresoc.v:187425.3-187433.6"
+ wire width 6 $1\q_int$next[5:0]$13069
+ attribute \src "libresoc.v:187402.13-187402.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:190242.17-190242.96"
- wire width 6 $and$libresoc.v:190242$13202_Y
- attribute \src "libresoc.v:190247.17-190247.96"
- wire width 6 $and$libresoc.v:190247$13207_Y
- attribute \src "libresoc.v:190244.18-190244.93"
- wire width 6 $not$libresoc.v:190244$13204_Y
- attribute \src "libresoc.v:190246.17-190246.92"
- wire width 6 $not$libresoc.v:190246$13206_Y
- attribute \src "libresoc.v:190249.17-190249.92"
- wire width 6 $not$libresoc.v:190249$13209_Y
- attribute \src "libresoc.v:190243.18-190243.98"
- wire width 6 $or$libresoc.v:190243$13203_Y
- attribute \src "libresoc.v:190245.18-190245.99"
- wire width 6 $or$libresoc.v:190245$13205_Y
- attribute \src "libresoc.v:190248.17-190248.97"
- wire width 6 $or$libresoc.v:190248$13208_Y
+ attribute \src "libresoc.v:187415.17-187415.96"
+ wire width 6 $and$libresoc.v:187415$13058_Y
+ attribute \src "libresoc.v:187420.17-187420.96"
+ wire width 6 $and$libresoc.v:187420$13063_Y
+ attribute \src "libresoc.v:187417.18-187417.93"
+ wire width 6 $not$libresoc.v:187417$13060_Y
+ attribute \src "libresoc.v:187419.17-187419.92"
+ wire width 6 $not$libresoc.v:187419$13062_Y
+ attribute \src "libresoc.v:187422.17-187422.92"
+ wire width 6 $not$libresoc.v:187422$13065_Y
+ attribute \src "libresoc.v:187416.18-187416.98"
+ wire width 6 $or$libresoc.v:187416$13059_Y
+ attribute \src "libresoc.v:187418.18-187418.99"
+ wire width 6 $or$libresoc.v:187418$13061_Y
+ attribute \src "libresoc.v:187421.17-187421.97"
+ wire width 6 $or$libresoc.v:187421$13064_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190207.7-190207.15"
+ attribute \src "libresoc.v:187380.7-187380.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190242$13202
+ cell $and $and$libresoc.v:187415$13058
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190242$13202_Y
+ connect \Y $and$libresoc.v:187415$13058_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190247$13207
+ cell $and $and$libresoc.v:187420$13063
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190247$13207_Y
+ connect \Y $and$libresoc.v:187420$13063_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190244$13204
+ cell $not $not$libresoc.v:187417$13060
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:190244$13204_Y
+ connect \Y $not$libresoc.v:187417$13060_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190246$13206
+ cell $not $not$libresoc.v:187419$13062
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:190246$13206_Y
+ connect \Y $not$libresoc.v:187419$13062_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190249$13209
+ cell $not $not$libresoc.v:187422$13065
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:190249$13209_Y
+ connect \Y $not$libresoc.v:187422$13065_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190243$13203
+ cell $or $or$libresoc.v:187416$13059
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190243$13203_Y
+ connect \Y $or$libresoc.v:187416$13059_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190245$13205
+ cell $or $or$libresoc.v:187418$13061
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190245$13205_Y
+ connect \Y $or$libresoc.v:187418$13061_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190248$13208
+ cell $or $or$libresoc.v:187421$13064
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190248$13208_Y
+ connect \Y $or$libresoc.v:187421$13064_Y
end
- attribute \src "libresoc.v:190207.7-190207.20"
- process $proc$libresoc.v:190207$13214
+ attribute \src "libresoc.v:187380.7-187380.20"
+ process $proc$libresoc.v:187380$13070
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190229.13-190229.26"
- process $proc$libresoc.v:190229$13215
+ attribute \src "libresoc.v:187402.13-187402.26"
+ process $proc$libresoc.v:187402$13071
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:190250.3-190251.27"
- process $proc$libresoc.v:190250$13210
+ attribute \src "libresoc.v:187423.3-187424.27"
+ process $proc$libresoc.v:187423$13066
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:190252.3-190260.6"
- process $proc$libresoc.v:190252$13211
+ attribute \src "libresoc.v:187425.3-187433.6"
+ process $proc$libresoc.v:187425$13067
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13212 $1\q_int$next[5:0]$13213
- attribute \src "libresoc.v:190253.5-190253.29"
+ assign $0\q_int$next[5:0]$13068 $1\q_int$next[5:0]$13069
+ attribute \src "libresoc.v:187426.5-187426.29"
switch \initial
- attribute \src "libresoc.v:190253.9-190253.17"
+ attribute \src "libresoc.v:187426.9-187426.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13213 6'000000
+ assign $1\q_int$next[5:0]$13069 6'000000
case
- assign $1\q_int$next[5:0]$13213 \$5
+ assign $1\q_int$next[5:0]$13069 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13212
+ update \q_int$next $0\q_int$next[5:0]$13068
end
- connect \$9 $and$libresoc.v:190242$13202_Y
- connect \$11 $or$libresoc.v:190243$13203_Y
- connect \$13 $not$libresoc.v:190244$13204_Y
- connect \$15 $or$libresoc.v:190245$13205_Y
- connect \$1 $not$libresoc.v:190246$13206_Y
- connect \$3 $and$libresoc.v:190247$13207_Y
- connect \$5 $or$libresoc.v:190248$13208_Y
- connect \$7 $not$libresoc.v:190249$13209_Y
+ connect \$9 $and$libresoc.v:187415$13058_Y
+ connect \$11 $or$libresoc.v:187416$13059_Y
+ connect \$13 $not$libresoc.v:187417$13060_Y
+ connect \$15 $or$libresoc.v:187418$13061_Y
+ connect \$1 $not$libresoc.v:187419$13062_Y
+ connect \$3 $and$libresoc.v:187420$13063_Y
+ connect \$5 $or$libresoc.v:187421$13064_Y
+ connect \$7 $not$libresoc.v:187422$13065_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190268.1-190326.10"
+attribute \src "libresoc.v:187441.1-187499.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l"
attribute \generator "nMigen"
module \src_l$101
- attribute \src "libresoc.v:190269.7-190269.20"
+ attribute \src "libresoc.v:187442.7-187442.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190314.3-190322.6"
- wire width 3 $0\q_int$next[2:0]$13226
- attribute \src "libresoc.v:190312.3-190313.27"
+ attribute \src "libresoc.v:187487.3-187495.6"
+ wire width 3 $0\q_int$next[2:0]$13082
+ attribute \src "libresoc.v:187485.3-187486.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:190314.3-190322.6"
- wire width 3 $1\q_int$next[2:0]$13227
- attribute \src "libresoc.v:190291.13-190291.25"
+ attribute \src "libresoc.v:187487.3-187495.6"
+ wire width 3 $1\q_int$next[2:0]$13083
+ attribute \src "libresoc.v:187464.13-187464.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:190304.17-190304.96"
- wire width 3 $and$libresoc.v:190304$13216_Y
- attribute \src "libresoc.v:190309.17-190309.96"
- wire width 3 $and$libresoc.v:190309$13221_Y
- attribute \src "libresoc.v:190306.18-190306.93"
- wire width 3 $not$libresoc.v:190306$13218_Y
- attribute \src "libresoc.v:190308.17-190308.92"
- wire width 3 $not$libresoc.v:190308$13220_Y
- attribute \src "libresoc.v:190311.17-190311.92"
- wire width 3 $not$libresoc.v:190311$13223_Y
- attribute \src "libresoc.v:190305.18-190305.98"
- wire width 3 $or$libresoc.v:190305$13217_Y
- attribute \src "libresoc.v:190307.18-190307.99"
- wire width 3 $or$libresoc.v:190307$13219_Y
- attribute \src "libresoc.v:190310.17-190310.97"
- wire width 3 $or$libresoc.v:190310$13222_Y
+ attribute \src "libresoc.v:187477.17-187477.96"
+ wire width 3 $and$libresoc.v:187477$13072_Y
+ attribute \src "libresoc.v:187482.17-187482.96"
+ wire width 3 $and$libresoc.v:187482$13077_Y
+ attribute \src "libresoc.v:187479.18-187479.93"
+ wire width 3 $not$libresoc.v:187479$13074_Y
+ attribute \src "libresoc.v:187481.17-187481.92"
+ wire width 3 $not$libresoc.v:187481$13076_Y
+ attribute \src "libresoc.v:187484.17-187484.92"
+ wire width 3 $not$libresoc.v:187484$13079_Y
+ attribute \src "libresoc.v:187478.18-187478.98"
+ wire width 3 $or$libresoc.v:187478$13073_Y
+ attribute \src "libresoc.v:187480.18-187480.99"
+ wire width 3 $or$libresoc.v:187480$13075_Y
+ attribute \src "libresoc.v:187483.17-187483.97"
+ wire width 3 $or$libresoc.v:187483$13078_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190269.7-190269.15"
+ attribute \src "libresoc.v:187442.7-187442.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190304$13216
+ cell $and $and$libresoc.v:187477$13072
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190304$13216_Y
+ connect \Y $and$libresoc.v:187477$13072_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190309$13221
+ cell $and $and$libresoc.v:187482$13077
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190309$13221_Y
+ connect \Y $and$libresoc.v:187482$13077_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190306$13218
+ cell $not $not$libresoc.v:187479$13074
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:190306$13218_Y
+ connect \Y $not$libresoc.v:187479$13074_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190308$13220
+ cell $not $not$libresoc.v:187481$13076
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190308$13220_Y
+ connect \Y $not$libresoc.v:187481$13076_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190311$13223
+ cell $not $not$libresoc.v:187484$13079
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190311$13223_Y
+ connect \Y $not$libresoc.v:187484$13079_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190305$13217
+ cell $or $or$libresoc.v:187478$13073
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190305$13217_Y
+ connect \Y $or$libresoc.v:187478$13073_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190307$13219
+ cell $or $or$libresoc.v:187480$13075
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190307$13219_Y
+ connect \Y $or$libresoc.v:187480$13075_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190310$13222
+ cell $or $or$libresoc.v:187483$13078
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190310$13222_Y
+ connect \Y $or$libresoc.v:187483$13078_Y
end
- attribute \src "libresoc.v:190269.7-190269.20"
- process $proc$libresoc.v:190269$13228
+ attribute \src "libresoc.v:187442.7-187442.20"
+ process $proc$libresoc.v:187442$13084
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190291.13-190291.25"
- process $proc$libresoc.v:190291$13229
+ attribute \src "libresoc.v:187464.13-187464.25"
+ process $proc$libresoc.v:187464$13085
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:190312.3-190313.27"
- process $proc$libresoc.v:190312$13224
+ attribute \src "libresoc.v:187485.3-187486.27"
+ process $proc$libresoc.v:187485$13080
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:190314.3-190322.6"
- process $proc$libresoc.v:190314$13225
+ attribute \src "libresoc.v:187487.3-187495.6"
+ process $proc$libresoc.v:187487$13081
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13226 $1\q_int$next[2:0]$13227
- attribute \src "libresoc.v:190315.5-190315.29"
+ assign $0\q_int$next[2:0]$13082 $1\q_int$next[2:0]$13083
+ attribute \src "libresoc.v:187488.5-187488.29"
switch \initial
- attribute \src "libresoc.v:190315.9-190315.17"
+ attribute \src "libresoc.v:187488.9-187488.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13227 3'000
+ assign $1\q_int$next[2:0]$13083 3'000
case
- assign $1\q_int$next[2:0]$13227 \$5
+ assign $1\q_int$next[2:0]$13083 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13226
+ update \q_int$next $0\q_int$next[2:0]$13082
end
- connect \$9 $and$libresoc.v:190304$13216_Y
- connect \$11 $or$libresoc.v:190305$13217_Y
- connect \$13 $not$libresoc.v:190306$13218_Y
- connect \$15 $or$libresoc.v:190307$13219_Y
- connect \$1 $not$libresoc.v:190308$13220_Y
- connect \$3 $and$libresoc.v:190309$13221_Y
- connect \$5 $or$libresoc.v:190310$13222_Y
- connect \$7 $not$libresoc.v:190311$13223_Y
+ connect \$9 $and$libresoc.v:187477$13072_Y
+ connect \$11 $or$libresoc.v:187478$13073_Y
+ connect \$13 $not$libresoc.v:187479$13074_Y
+ connect \$15 $or$libresoc.v:187480$13075_Y
+ connect \$1 $not$libresoc.v:187481$13076_Y
+ connect \$3 $and$libresoc.v:187482$13077_Y
+ connect \$5 $or$libresoc.v:187483$13078_Y
+ connect \$7 $not$libresoc.v:187484$13079_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190330.1-190388.10"
+attribute \src "libresoc.v:187503.1-187561.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l"
attribute \generator "nMigen"
module \src_l$119
- attribute \src "libresoc.v:190331.7-190331.20"
+ attribute \src "libresoc.v:187504.7-187504.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190376.3-190384.6"
- wire width 5 $0\q_int$next[4:0]$13240
- attribute \src "libresoc.v:190374.3-190375.27"
+ attribute \src "libresoc.v:187549.3-187557.6"
+ wire width 5 $0\q_int$next[4:0]$13096
+ attribute \src "libresoc.v:187547.3-187548.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:190376.3-190384.6"
- wire width 5 $1\q_int$next[4:0]$13241
- attribute \src "libresoc.v:190353.13-190353.26"
+ attribute \src "libresoc.v:187549.3-187557.6"
+ wire width 5 $1\q_int$next[4:0]$13097
+ attribute \src "libresoc.v:187526.13-187526.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:190366.17-190366.96"
- wire width 5 $and$libresoc.v:190366$13230_Y
- attribute \src "libresoc.v:190371.17-190371.96"
- wire width 5 $and$libresoc.v:190371$13235_Y
- attribute \src "libresoc.v:190368.18-190368.93"
- wire width 5 $not$libresoc.v:190368$13232_Y
- attribute \src "libresoc.v:190370.17-190370.92"
- wire width 5 $not$libresoc.v:190370$13234_Y
- attribute \src "libresoc.v:190373.17-190373.92"
- wire width 5 $not$libresoc.v:190373$13237_Y
- attribute \src "libresoc.v:190367.18-190367.98"
- wire width 5 $or$libresoc.v:190367$13231_Y
- attribute \src "libresoc.v:190369.18-190369.99"
- wire width 5 $or$libresoc.v:190369$13233_Y
- attribute \src "libresoc.v:190372.17-190372.97"
- wire width 5 $or$libresoc.v:190372$13236_Y
+ attribute \src "libresoc.v:187539.17-187539.96"
+ wire width 5 $and$libresoc.v:187539$13086_Y
+ attribute \src "libresoc.v:187544.17-187544.96"
+ wire width 5 $and$libresoc.v:187544$13091_Y
+ attribute \src "libresoc.v:187541.18-187541.93"
+ wire width 5 $not$libresoc.v:187541$13088_Y
+ attribute \src "libresoc.v:187543.17-187543.92"
+ wire width 5 $not$libresoc.v:187543$13090_Y
+ attribute \src "libresoc.v:187546.17-187546.92"
+ wire width 5 $not$libresoc.v:187546$13093_Y
+ attribute \src "libresoc.v:187540.18-187540.98"
+ wire width 5 $or$libresoc.v:187540$13087_Y
+ attribute \src "libresoc.v:187542.18-187542.99"
+ wire width 5 $or$libresoc.v:187542$13089_Y
+ attribute \src "libresoc.v:187545.17-187545.97"
+ wire width 5 $or$libresoc.v:187545$13092_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190331.7-190331.15"
+ attribute \src "libresoc.v:187504.7-187504.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190366$13230
+ cell $and $and$libresoc.v:187539$13086
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190366$13230_Y
+ connect \Y $and$libresoc.v:187539$13086_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190371$13235
+ cell $and $and$libresoc.v:187544$13091
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190371$13235_Y
+ connect \Y $and$libresoc.v:187544$13091_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190368$13232
+ cell $not $not$libresoc.v:187541$13088
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_src
- connect \Y $not$libresoc.v:190368$13232_Y
+ connect \Y $not$libresoc.v:187541$13088_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190370$13234
+ cell $not $not$libresoc.v:187543$13090
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:190370$13234_Y
+ connect \Y $not$libresoc.v:187543$13090_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190373$13237
+ cell $not $not$libresoc.v:187546$13093
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:190373$13237_Y
+ connect \Y $not$libresoc.v:187546$13093_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190367$13231
+ cell $or $or$libresoc.v:187540$13087
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190367$13231_Y
+ connect \Y $or$libresoc.v:187540$13087_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190369$13233
+ cell $or $or$libresoc.v:187542$13089
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190369$13233_Y
+ connect \Y $or$libresoc.v:187542$13089_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190372$13236
+ cell $or $or$libresoc.v:187545$13092
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190372$13236_Y
+ connect \Y $or$libresoc.v:187545$13092_Y
end
- attribute \src "libresoc.v:190331.7-190331.20"
- process $proc$libresoc.v:190331$13242
+ attribute \src "libresoc.v:187504.7-187504.20"
+ process $proc$libresoc.v:187504$13098
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190353.13-190353.26"
- process $proc$libresoc.v:190353$13243
+ attribute \src "libresoc.v:187526.13-187526.26"
+ process $proc$libresoc.v:187526$13099
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:190374.3-190375.27"
- process $proc$libresoc.v:190374$13238
+ attribute \src "libresoc.v:187547.3-187548.27"
+ process $proc$libresoc.v:187547$13094
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:190376.3-190384.6"
- process $proc$libresoc.v:190376$13239
+ attribute \src "libresoc.v:187549.3-187557.6"
+ process $proc$libresoc.v:187549$13095
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$13240 $1\q_int$next[4:0]$13241
- attribute \src "libresoc.v:190377.5-190377.29"
+ assign $0\q_int$next[4:0]$13096 $1\q_int$next[4:0]$13097
+ attribute \src "libresoc.v:187550.5-187550.29"
switch \initial
- attribute \src "libresoc.v:190377.9-190377.17"
+ attribute \src "libresoc.v:187550.9-187550.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$13241 5'00000
+ assign $1\q_int$next[4:0]$13097 5'00000
case
- assign $1\q_int$next[4:0]$13241 \$5
+ assign $1\q_int$next[4:0]$13097 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$13240
+ update \q_int$next $0\q_int$next[4:0]$13096
end
- connect \$9 $and$libresoc.v:190366$13230_Y
- connect \$11 $or$libresoc.v:190367$13231_Y
- connect \$13 $not$libresoc.v:190368$13232_Y
- connect \$15 $or$libresoc.v:190369$13233_Y
- connect \$1 $not$libresoc.v:190370$13234_Y
- connect \$3 $and$libresoc.v:190371$13235_Y
- connect \$5 $or$libresoc.v:190372$13236_Y
- connect \$7 $not$libresoc.v:190373$13237_Y
+ connect \$9 $and$libresoc.v:187539$13086_Y
+ connect \$11 $or$libresoc.v:187540$13087_Y
+ connect \$13 $not$libresoc.v:187541$13088_Y
+ connect \$15 $or$libresoc.v:187542$13089_Y
+ connect \$1 $not$libresoc.v:187543$13090_Y
+ connect \$3 $and$libresoc.v:187544$13091_Y
+ connect \$5 $or$libresoc.v:187545$13092_Y
+ connect \$7 $not$libresoc.v:187546$13093_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190392.1-190450.10"
+attribute \src "libresoc.v:187565.1-187623.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l"
attribute \generator "nMigen"
module \src_l$127
- attribute \src "libresoc.v:190393.7-190393.20"
+ attribute \src "libresoc.v:187566.7-187566.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190438.3-190446.6"
- wire width 3 $0\q_int$next[2:0]$13254
- attribute \src "libresoc.v:190436.3-190437.27"
+ attribute \src "libresoc.v:187611.3-187619.6"
+ wire width 3 $0\q_int$next[2:0]$13110
+ attribute \src "libresoc.v:187609.3-187610.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:190438.3-190446.6"
- wire width 3 $1\q_int$next[2:0]$13255
- attribute \src "libresoc.v:190415.13-190415.25"
+ attribute \src "libresoc.v:187611.3-187619.6"
+ wire width 3 $1\q_int$next[2:0]$13111
+ attribute \src "libresoc.v:187588.13-187588.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:190428.17-190428.96"
- wire width 3 $and$libresoc.v:190428$13244_Y
- attribute \src "libresoc.v:190433.17-190433.96"
- wire width 3 $and$libresoc.v:190433$13249_Y
- attribute \src "libresoc.v:190430.18-190430.93"
- wire width 3 $not$libresoc.v:190430$13246_Y
- attribute \src "libresoc.v:190432.17-190432.92"
- wire width 3 $not$libresoc.v:190432$13248_Y
- attribute \src "libresoc.v:190435.17-190435.92"
- wire width 3 $not$libresoc.v:190435$13251_Y
- attribute \src "libresoc.v:190429.18-190429.98"
- wire width 3 $or$libresoc.v:190429$13245_Y
- attribute \src "libresoc.v:190431.18-190431.99"
- wire width 3 $or$libresoc.v:190431$13247_Y
- attribute \src "libresoc.v:190434.17-190434.97"
- wire width 3 $or$libresoc.v:190434$13250_Y
+ attribute \src "libresoc.v:187601.17-187601.96"
+ wire width 3 $and$libresoc.v:187601$13100_Y
+ attribute \src "libresoc.v:187606.17-187606.96"
+ wire width 3 $and$libresoc.v:187606$13105_Y
+ attribute \src "libresoc.v:187603.18-187603.93"
+ wire width 3 $not$libresoc.v:187603$13102_Y
+ attribute \src "libresoc.v:187605.17-187605.92"
+ wire width 3 $not$libresoc.v:187605$13104_Y
+ attribute \src "libresoc.v:187608.17-187608.92"
+ wire width 3 $not$libresoc.v:187608$13107_Y
+ attribute \src "libresoc.v:187602.18-187602.98"
+ wire width 3 $or$libresoc.v:187602$13101_Y
+ attribute \src "libresoc.v:187604.18-187604.99"
+ wire width 3 $or$libresoc.v:187604$13103_Y
+ attribute \src "libresoc.v:187607.17-187607.97"
+ wire width 3 $or$libresoc.v:187607$13106_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190393.7-190393.15"
+ attribute \src "libresoc.v:187566.7-187566.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190428$13244
+ cell $and $and$libresoc.v:187601$13100
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190428$13244_Y
+ connect \Y $and$libresoc.v:187601$13100_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190433$13249
+ cell $and $and$libresoc.v:187606$13105
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190433$13249_Y
+ connect \Y $and$libresoc.v:187606$13105_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190430$13246
+ cell $not $not$libresoc.v:187603$13102
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:190430$13246_Y
+ connect \Y $not$libresoc.v:187603$13102_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190432$13248
+ cell $not $not$libresoc.v:187605$13104
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190432$13248_Y
+ connect \Y $not$libresoc.v:187605$13104_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190435$13251
+ cell $not $not$libresoc.v:187608$13107
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190435$13251_Y
+ connect \Y $not$libresoc.v:187608$13107_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190429$13245
+ cell $or $or$libresoc.v:187602$13101
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190429$13245_Y
+ connect \Y $or$libresoc.v:187602$13101_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190431$13247
+ cell $or $or$libresoc.v:187604$13103
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190431$13247_Y
+ connect \Y $or$libresoc.v:187604$13103_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190434$13250
+ cell $or $or$libresoc.v:187607$13106
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190434$13250_Y
+ connect \Y $or$libresoc.v:187607$13106_Y
end
- attribute \src "libresoc.v:190393.7-190393.20"
- process $proc$libresoc.v:190393$13256
+ attribute \src "libresoc.v:187566.7-187566.20"
+ process $proc$libresoc.v:187566$13112
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190415.13-190415.25"
- process $proc$libresoc.v:190415$13257
+ attribute \src "libresoc.v:187588.13-187588.25"
+ process $proc$libresoc.v:187588$13113
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:190436.3-190437.27"
- process $proc$libresoc.v:190436$13252
+ attribute \src "libresoc.v:187609.3-187610.27"
+ process $proc$libresoc.v:187609$13108
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:190438.3-190446.6"
- process $proc$libresoc.v:190438$13253
+ attribute \src "libresoc.v:187611.3-187619.6"
+ process $proc$libresoc.v:187611$13109
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13254 $1\q_int$next[2:0]$13255
- attribute \src "libresoc.v:190439.5-190439.29"
+ assign $0\q_int$next[2:0]$13110 $1\q_int$next[2:0]$13111
+ attribute \src "libresoc.v:187612.5-187612.29"
switch \initial
- attribute \src "libresoc.v:190439.9-190439.17"
+ attribute \src "libresoc.v:187612.9-187612.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13255 3'000
+ assign $1\q_int$next[2:0]$13111 3'000
case
- assign $1\q_int$next[2:0]$13255 \$5
+ assign $1\q_int$next[2:0]$13111 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13254
+ update \q_int$next $0\q_int$next[2:0]$13110
end
- connect \$9 $and$libresoc.v:190428$13244_Y
- connect \$11 $or$libresoc.v:190429$13245_Y
- connect \$13 $not$libresoc.v:190430$13246_Y
- connect \$15 $or$libresoc.v:190431$13247_Y
- connect \$1 $not$libresoc.v:190432$13248_Y
- connect \$3 $and$libresoc.v:190433$13249_Y
- connect \$5 $or$libresoc.v:190434$13250_Y
- connect \$7 $not$libresoc.v:190435$13251_Y
+ connect \$9 $and$libresoc.v:187601$13100_Y
+ connect \$11 $or$libresoc.v:187602$13101_Y
+ connect \$13 $not$libresoc.v:187603$13102_Y
+ connect \$15 $or$libresoc.v:187604$13103_Y
+ connect \$1 $not$libresoc.v:187605$13104_Y
+ connect \$3 $and$libresoc.v:187606$13105_Y
+ connect \$5 $or$libresoc.v:187607$13106_Y
+ connect \$7 $not$libresoc.v:187608$13107_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190454.1-190512.10"
+attribute \src "libresoc.v:187627.1-187685.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l"
attribute \generator "nMigen"
module \src_l$23
- attribute \src "libresoc.v:190455.7-190455.20"
+ attribute \src "libresoc.v:187628.7-187628.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190500.3-190508.6"
- wire width 3 $0\q_int$next[2:0]$13268
- attribute \src "libresoc.v:190498.3-190499.27"
+ attribute \src "libresoc.v:187673.3-187681.6"
+ wire width 3 $0\q_int$next[2:0]$13124
+ attribute \src "libresoc.v:187671.3-187672.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:190500.3-190508.6"
- wire width 3 $1\q_int$next[2:0]$13269
- attribute \src "libresoc.v:190477.13-190477.25"
+ attribute \src "libresoc.v:187673.3-187681.6"
+ wire width 3 $1\q_int$next[2:0]$13125
+ attribute \src "libresoc.v:187650.13-187650.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:190490.17-190490.96"
- wire width 3 $and$libresoc.v:190490$13258_Y
- attribute \src "libresoc.v:190495.17-190495.96"
- wire width 3 $and$libresoc.v:190495$13263_Y
- attribute \src "libresoc.v:190492.18-190492.93"
- wire width 3 $not$libresoc.v:190492$13260_Y
- attribute \src "libresoc.v:190494.17-190494.92"
- wire width 3 $not$libresoc.v:190494$13262_Y
- attribute \src "libresoc.v:190497.17-190497.92"
- wire width 3 $not$libresoc.v:190497$13265_Y
- attribute \src "libresoc.v:190491.18-190491.98"
- wire width 3 $or$libresoc.v:190491$13259_Y
- attribute \src "libresoc.v:190493.18-190493.99"
- wire width 3 $or$libresoc.v:190493$13261_Y
- attribute \src "libresoc.v:190496.17-190496.97"
- wire width 3 $or$libresoc.v:190496$13264_Y
+ attribute \src "libresoc.v:187663.17-187663.96"
+ wire width 3 $and$libresoc.v:187663$13114_Y
+ attribute \src "libresoc.v:187668.17-187668.96"
+ wire width 3 $and$libresoc.v:187668$13119_Y
+ attribute \src "libresoc.v:187665.18-187665.93"
+ wire width 3 $not$libresoc.v:187665$13116_Y
+ attribute \src "libresoc.v:187667.17-187667.92"
+ wire width 3 $not$libresoc.v:187667$13118_Y
+ attribute \src "libresoc.v:187670.17-187670.92"
+ wire width 3 $not$libresoc.v:187670$13121_Y
+ attribute \src "libresoc.v:187664.18-187664.98"
+ wire width 3 $or$libresoc.v:187664$13115_Y
+ attribute \src "libresoc.v:187666.18-187666.99"
+ wire width 3 $or$libresoc.v:187666$13117_Y
+ attribute \src "libresoc.v:187669.17-187669.97"
+ wire width 3 $or$libresoc.v:187669$13120_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190455.7-190455.15"
+ attribute \src "libresoc.v:187628.7-187628.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190490$13258
+ cell $and $and$libresoc.v:187663$13114
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190490$13258_Y
+ connect \Y $and$libresoc.v:187663$13114_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190495$13263
+ cell $and $and$libresoc.v:187668$13119
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190495$13263_Y
+ connect \Y $and$libresoc.v:187668$13119_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190492$13260
+ cell $not $not$libresoc.v:187665$13116
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:190492$13260_Y
+ connect \Y $not$libresoc.v:187665$13116_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190494$13262
+ cell $not $not$libresoc.v:187667$13118
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190494$13262_Y
+ connect \Y $not$libresoc.v:187667$13118_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190497$13265
+ cell $not $not$libresoc.v:187670$13121
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190497$13265_Y
+ connect \Y $not$libresoc.v:187670$13121_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190491$13259
+ cell $or $or$libresoc.v:187664$13115
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190491$13259_Y
+ connect \Y $or$libresoc.v:187664$13115_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190493$13261
+ cell $or $or$libresoc.v:187666$13117
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190493$13261_Y
+ connect \Y $or$libresoc.v:187666$13117_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190496$13264
+ cell $or $or$libresoc.v:187669$13120
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190496$13264_Y
+ connect \Y $or$libresoc.v:187669$13120_Y
end
- attribute \src "libresoc.v:190455.7-190455.20"
- process $proc$libresoc.v:190455$13270
+ attribute \src "libresoc.v:187628.7-187628.20"
+ process $proc$libresoc.v:187628$13126
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190477.13-190477.25"
- process $proc$libresoc.v:190477$13271
+ attribute \src "libresoc.v:187650.13-187650.25"
+ process $proc$libresoc.v:187650$13127
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:190498.3-190499.27"
- process $proc$libresoc.v:190498$13266
+ attribute \src "libresoc.v:187671.3-187672.27"
+ process $proc$libresoc.v:187671$13122
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:190500.3-190508.6"
- process $proc$libresoc.v:190500$13267
+ attribute \src "libresoc.v:187673.3-187681.6"
+ process $proc$libresoc.v:187673$13123
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13268 $1\q_int$next[2:0]$13269
- attribute \src "libresoc.v:190501.5-190501.29"
+ assign $0\q_int$next[2:0]$13124 $1\q_int$next[2:0]$13125
+ attribute \src "libresoc.v:187674.5-187674.29"
switch \initial
- attribute \src "libresoc.v:190501.9-190501.17"
+ attribute \src "libresoc.v:187674.9-187674.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13269 3'000
+ assign $1\q_int$next[2:0]$13125 3'000
case
- assign $1\q_int$next[2:0]$13269 \$5
+ assign $1\q_int$next[2:0]$13125 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13268
+ update \q_int$next $0\q_int$next[2:0]$13124
end
- connect \$9 $and$libresoc.v:190490$13258_Y
- connect \$11 $or$libresoc.v:190491$13259_Y
- connect \$13 $not$libresoc.v:190492$13260_Y
- connect \$15 $or$libresoc.v:190493$13261_Y
- connect \$1 $not$libresoc.v:190494$13262_Y
- connect \$3 $and$libresoc.v:190495$13263_Y
- connect \$5 $or$libresoc.v:190496$13264_Y
- connect \$7 $not$libresoc.v:190497$13265_Y
+ connect \$9 $and$libresoc.v:187663$13114_Y
+ connect \$11 $or$libresoc.v:187664$13115_Y
+ connect \$13 $not$libresoc.v:187665$13116_Y
+ connect \$15 $or$libresoc.v:187666$13117_Y
+ connect \$1 $not$libresoc.v:187667$13118_Y
+ connect \$3 $and$libresoc.v:187668$13119_Y
+ connect \$5 $or$libresoc.v:187669$13120_Y
+ connect \$7 $not$libresoc.v:187670$13121_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190516.1-190574.10"
+attribute \src "libresoc.v:187689.1-187747.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l"
attribute \generator "nMigen"
module \src_l$39
- attribute \src "libresoc.v:190517.7-190517.20"
+ attribute \src "libresoc.v:187690.7-187690.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190562.3-190570.6"
- wire width 4 $0\q_int$next[3:0]$13282
- attribute \src "libresoc.v:190560.3-190561.27"
+ attribute \src "libresoc.v:187735.3-187743.6"
+ wire width 4 $0\q_int$next[3:0]$13138
+ attribute \src "libresoc.v:187733.3-187734.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:190562.3-190570.6"
- wire width 4 $1\q_int$next[3:0]$13283
- attribute \src "libresoc.v:190539.13-190539.25"
+ attribute \src "libresoc.v:187735.3-187743.6"
+ wire width 4 $1\q_int$next[3:0]$13139
+ attribute \src "libresoc.v:187712.13-187712.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:190552.17-190552.96"
- wire width 4 $and$libresoc.v:190552$13272_Y
- attribute \src "libresoc.v:190557.17-190557.96"
- wire width 4 $and$libresoc.v:190557$13277_Y
- attribute \src "libresoc.v:190554.18-190554.93"
- wire width 4 $not$libresoc.v:190554$13274_Y
- attribute \src "libresoc.v:190556.17-190556.92"
- wire width 4 $not$libresoc.v:190556$13276_Y
- attribute \src "libresoc.v:190559.17-190559.92"
- wire width 4 $not$libresoc.v:190559$13279_Y
- attribute \src "libresoc.v:190553.18-190553.98"
- wire width 4 $or$libresoc.v:190553$13273_Y
- attribute \src "libresoc.v:190555.18-190555.99"
- wire width 4 $or$libresoc.v:190555$13275_Y
- attribute \src "libresoc.v:190558.17-190558.97"
- wire width 4 $or$libresoc.v:190558$13278_Y
+ attribute \src "libresoc.v:187725.17-187725.96"
+ wire width 4 $and$libresoc.v:187725$13128_Y
+ attribute \src "libresoc.v:187730.17-187730.96"
+ wire width 4 $and$libresoc.v:187730$13133_Y
+ attribute \src "libresoc.v:187727.18-187727.93"
+ wire width 4 $not$libresoc.v:187727$13130_Y
+ attribute \src "libresoc.v:187729.17-187729.92"
+ wire width 4 $not$libresoc.v:187729$13132_Y
+ attribute \src "libresoc.v:187732.17-187732.92"
+ wire width 4 $not$libresoc.v:187732$13135_Y
+ attribute \src "libresoc.v:187726.18-187726.98"
+ wire width 4 $or$libresoc.v:187726$13129_Y
+ attribute \src "libresoc.v:187728.18-187728.99"
+ wire width 4 $or$libresoc.v:187728$13131_Y
+ attribute \src "libresoc.v:187731.17-187731.97"
+ wire width 4 $or$libresoc.v:187731$13134_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190517.7-190517.15"
+ attribute \src "libresoc.v:187690.7-187690.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190552$13272
+ cell $and $and$libresoc.v:187725$13128
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190552$13272_Y
+ connect \Y $and$libresoc.v:187725$13128_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190557$13277
+ cell $and $and$libresoc.v:187730$13133
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190557$13277_Y
+ connect \Y $and$libresoc.v:187730$13133_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190554$13274
+ cell $not $not$libresoc.v:187727$13130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:190554$13274_Y
+ connect \Y $not$libresoc.v:187727$13130_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190556$13276
+ cell $not $not$libresoc.v:187729$13132
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:190556$13276_Y
+ connect \Y $not$libresoc.v:187729$13132_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190559$13279
+ cell $not $not$libresoc.v:187732$13135
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:190559$13279_Y
+ connect \Y $not$libresoc.v:187732$13135_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190553$13273
+ cell $or $or$libresoc.v:187726$13129
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190553$13273_Y
+ connect \Y $or$libresoc.v:187726$13129_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190555$13275
+ cell $or $or$libresoc.v:187728$13131
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190555$13275_Y
+ connect \Y $or$libresoc.v:187728$13131_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190558$13278
+ cell $or $or$libresoc.v:187731$13134
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190558$13278_Y
+ connect \Y $or$libresoc.v:187731$13134_Y
end
- attribute \src "libresoc.v:190517.7-190517.20"
- process $proc$libresoc.v:190517$13284
+ attribute \src "libresoc.v:187690.7-187690.20"
+ process $proc$libresoc.v:187690$13140
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190539.13-190539.25"
- process $proc$libresoc.v:190539$13285
+ attribute \src "libresoc.v:187712.13-187712.25"
+ process $proc$libresoc.v:187712$13141
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:190560.3-190561.27"
- process $proc$libresoc.v:190560$13280
+ attribute \src "libresoc.v:187733.3-187734.27"
+ process $proc$libresoc.v:187733$13136
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:190562.3-190570.6"
- process $proc$libresoc.v:190562$13281
+ attribute \src "libresoc.v:187735.3-187743.6"
+ process $proc$libresoc.v:187735$13137
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13282 $1\q_int$next[3:0]$13283
- attribute \src "libresoc.v:190563.5-190563.29"
+ assign $0\q_int$next[3:0]$13138 $1\q_int$next[3:0]$13139
+ attribute \src "libresoc.v:187736.5-187736.29"
switch \initial
- attribute \src "libresoc.v:190563.9-190563.17"
+ attribute \src "libresoc.v:187736.9-187736.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13283 4'0000
+ assign $1\q_int$next[3:0]$13139 4'0000
case
- assign $1\q_int$next[3:0]$13283 \$5
+ assign $1\q_int$next[3:0]$13139 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13282
+ update \q_int$next $0\q_int$next[3:0]$13138
end
- connect \$9 $and$libresoc.v:190552$13272_Y
- connect \$11 $or$libresoc.v:190553$13273_Y
- connect \$13 $not$libresoc.v:190554$13274_Y
- connect \$15 $or$libresoc.v:190555$13275_Y
- connect \$1 $not$libresoc.v:190556$13276_Y
- connect \$3 $and$libresoc.v:190557$13277_Y
- connect \$5 $or$libresoc.v:190558$13278_Y
- connect \$7 $not$libresoc.v:190559$13279_Y
+ connect \$9 $and$libresoc.v:187725$13128_Y
+ connect \$11 $or$libresoc.v:187726$13129_Y
+ connect \$13 $not$libresoc.v:187727$13130_Y
+ connect \$15 $or$libresoc.v:187728$13131_Y
+ connect \$1 $not$libresoc.v:187729$13132_Y
+ connect \$3 $and$libresoc.v:187730$13133_Y
+ connect \$5 $or$libresoc.v:187731$13134_Y
+ connect \$7 $not$libresoc.v:187732$13135_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190578.1-190636.10"
+attribute \src "libresoc.v:187751.1-187809.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l"
attribute \generator "nMigen"
module \src_l$55
- attribute \src "libresoc.v:190579.7-190579.20"
+ attribute \src "libresoc.v:187752.7-187752.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190624.3-190632.6"
- wire width 3 $0\q_int$next[2:0]$13296
- attribute \src "libresoc.v:190622.3-190623.27"
+ attribute \src "libresoc.v:187797.3-187805.6"
+ wire width 3 $0\q_int$next[2:0]$13152
+ attribute \src "libresoc.v:187795.3-187796.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:190624.3-190632.6"
- wire width 3 $1\q_int$next[2:0]$13297
- attribute \src "libresoc.v:190601.13-190601.25"
+ attribute \src "libresoc.v:187797.3-187805.6"
+ wire width 3 $1\q_int$next[2:0]$13153
+ attribute \src "libresoc.v:187774.13-187774.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:190614.17-190614.96"
- wire width 3 $and$libresoc.v:190614$13286_Y
- attribute \src "libresoc.v:190619.17-190619.96"
- wire width 3 $and$libresoc.v:190619$13291_Y
- attribute \src "libresoc.v:190616.18-190616.93"
- wire width 3 $not$libresoc.v:190616$13288_Y
- attribute \src "libresoc.v:190618.17-190618.92"
- wire width 3 $not$libresoc.v:190618$13290_Y
- attribute \src "libresoc.v:190621.17-190621.92"
- wire width 3 $not$libresoc.v:190621$13293_Y
- attribute \src "libresoc.v:190615.18-190615.98"
- wire width 3 $or$libresoc.v:190615$13287_Y
- attribute \src "libresoc.v:190617.18-190617.99"
- wire width 3 $or$libresoc.v:190617$13289_Y
- attribute \src "libresoc.v:190620.17-190620.97"
- wire width 3 $or$libresoc.v:190620$13292_Y
+ attribute \src "libresoc.v:187787.17-187787.96"
+ wire width 3 $and$libresoc.v:187787$13142_Y
+ attribute \src "libresoc.v:187792.17-187792.96"
+ wire width 3 $and$libresoc.v:187792$13147_Y
+ attribute \src "libresoc.v:187789.18-187789.93"
+ wire width 3 $not$libresoc.v:187789$13144_Y
+ attribute \src "libresoc.v:187791.17-187791.92"
+ wire width 3 $not$libresoc.v:187791$13146_Y
+ attribute \src "libresoc.v:187794.17-187794.92"
+ wire width 3 $not$libresoc.v:187794$13149_Y
+ attribute \src "libresoc.v:187788.18-187788.98"
+ wire width 3 $or$libresoc.v:187788$13143_Y
+ attribute \src "libresoc.v:187790.18-187790.99"
+ wire width 3 $or$libresoc.v:187790$13145_Y
+ attribute \src "libresoc.v:187793.17-187793.97"
+ wire width 3 $or$libresoc.v:187793$13148_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190579.7-190579.15"
+ attribute \src "libresoc.v:187752.7-187752.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190614$13286
+ cell $and $and$libresoc.v:187787$13142
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190614$13286_Y
+ connect \Y $and$libresoc.v:187787$13142_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190619$13291
+ cell $and $and$libresoc.v:187792$13147
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190619$13291_Y
+ connect \Y $and$libresoc.v:187792$13147_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190616$13288
+ cell $not $not$libresoc.v:187789$13144
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:190616$13288_Y
+ connect \Y $not$libresoc.v:187789$13144_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190618$13290
+ cell $not $not$libresoc.v:187791$13146
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190618$13290_Y
+ connect \Y $not$libresoc.v:187791$13146_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190621$13293
+ cell $not $not$libresoc.v:187794$13149
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190621$13293_Y
+ connect \Y $not$libresoc.v:187794$13149_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190615$13287
+ cell $or $or$libresoc.v:187788$13143
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190615$13287_Y
+ connect \Y $or$libresoc.v:187788$13143_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190617$13289
+ cell $or $or$libresoc.v:187790$13145
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190617$13289_Y
+ connect \Y $or$libresoc.v:187790$13145_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190620$13292
+ cell $or $or$libresoc.v:187793$13148
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190620$13292_Y
+ connect \Y $or$libresoc.v:187793$13148_Y
end
- attribute \src "libresoc.v:190579.7-190579.20"
- process $proc$libresoc.v:190579$13298
+ attribute \src "libresoc.v:187752.7-187752.20"
+ process $proc$libresoc.v:187752$13154
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190601.13-190601.25"
- process $proc$libresoc.v:190601$13299
+ attribute \src "libresoc.v:187774.13-187774.25"
+ process $proc$libresoc.v:187774$13155
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:190622.3-190623.27"
- process $proc$libresoc.v:190622$13294
+ attribute \src "libresoc.v:187795.3-187796.27"
+ process $proc$libresoc.v:187795$13150
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:190624.3-190632.6"
- process $proc$libresoc.v:190624$13295
+ attribute \src "libresoc.v:187797.3-187805.6"
+ process $proc$libresoc.v:187797$13151
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13296 $1\q_int$next[2:0]$13297
- attribute \src "libresoc.v:190625.5-190625.29"
+ assign $0\q_int$next[2:0]$13152 $1\q_int$next[2:0]$13153
+ attribute \src "libresoc.v:187798.5-187798.29"
switch \initial
- attribute \src "libresoc.v:190625.9-190625.17"
+ attribute \src "libresoc.v:187798.9-187798.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13297 3'000
+ assign $1\q_int$next[2:0]$13153 3'000
case
- assign $1\q_int$next[2:0]$13297 \$5
+ assign $1\q_int$next[2:0]$13153 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13296
+ update \q_int$next $0\q_int$next[2:0]$13152
end
- connect \$9 $and$libresoc.v:190614$13286_Y
- connect \$11 $or$libresoc.v:190615$13287_Y
- connect \$13 $not$libresoc.v:190616$13288_Y
- connect \$15 $or$libresoc.v:190617$13289_Y
- connect \$1 $not$libresoc.v:190618$13290_Y
- connect \$3 $and$libresoc.v:190619$13291_Y
- connect \$5 $or$libresoc.v:190620$13292_Y
- connect \$7 $not$libresoc.v:190621$13293_Y
+ connect \$9 $and$libresoc.v:187787$13142_Y
+ connect \$11 $or$libresoc.v:187788$13143_Y
+ connect \$13 $not$libresoc.v:187789$13144_Y
+ connect \$15 $or$libresoc.v:187790$13145_Y
+ connect \$1 $not$libresoc.v:187791$13146_Y
+ connect \$3 $and$libresoc.v:187792$13147_Y
+ connect \$5 $or$libresoc.v:187793$13148_Y
+ connect \$7 $not$libresoc.v:187794$13149_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190640.1-190698.10"
+attribute \src "libresoc.v:187813.1-187871.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l"
attribute \generator "nMigen"
module \src_l$67
- attribute \src "libresoc.v:190641.7-190641.20"
+ attribute \src "libresoc.v:187814.7-187814.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190686.3-190694.6"
- wire width 6 $0\q_int$next[5:0]$13310
- attribute \src "libresoc.v:190684.3-190685.27"
+ attribute \src "libresoc.v:187859.3-187867.6"
+ wire width 6 $0\q_int$next[5:0]$13166
+ attribute \src "libresoc.v:187857.3-187858.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:190686.3-190694.6"
- wire width 6 $1\q_int$next[5:0]$13311
- attribute \src "libresoc.v:190663.13-190663.26"
+ attribute \src "libresoc.v:187859.3-187867.6"
+ wire width 6 $1\q_int$next[5:0]$13167
+ attribute \src "libresoc.v:187836.13-187836.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:190676.17-190676.96"
- wire width 6 $and$libresoc.v:190676$13300_Y
- attribute \src "libresoc.v:190681.17-190681.96"
- wire width 6 $and$libresoc.v:190681$13305_Y
- attribute \src "libresoc.v:190678.18-190678.93"
- wire width 6 $not$libresoc.v:190678$13302_Y
- attribute \src "libresoc.v:190680.17-190680.92"
- wire width 6 $not$libresoc.v:190680$13304_Y
- attribute \src "libresoc.v:190683.17-190683.92"
- wire width 6 $not$libresoc.v:190683$13307_Y
- attribute \src "libresoc.v:190677.18-190677.98"
- wire width 6 $or$libresoc.v:190677$13301_Y
- attribute \src "libresoc.v:190679.18-190679.99"
- wire width 6 $or$libresoc.v:190679$13303_Y
- attribute \src "libresoc.v:190682.17-190682.97"
- wire width 6 $or$libresoc.v:190682$13306_Y
+ attribute \src "libresoc.v:187849.17-187849.96"
+ wire width 6 $and$libresoc.v:187849$13156_Y
+ attribute \src "libresoc.v:187854.17-187854.96"
+ wire width 6 $and$libresoc.v:187854$13161_Y
+ attribute \src "libresoc.v:187851.18-187851.93"
+ wire width 6 $not$libresoc.v:187851$13158_Y
+ attribute \src "libresoc.v:187853.17-187853.92"
+ wire width 6 $not$libresoc.v:187853$13160_Y
+ attribute \src "libresoc.v:187856.17-187856.92"
+ wire width 6 $not$libresoc.v:187856$13163_Y
+ attribute \src "libresoc.v:187850.18-187850.98"
+ wire width 6 $or$libresoc.v:187850$13157_Y
+ attribute \src "libresoc.v:187852.18-187852.99"
+ wire width 6 $or$libresoc.v:187852$13159_Y
+ attribute \src "libresoc.v:187855.17-187855.97"
+ wire width 6 $or$libresoc.v:187855$13162_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190641.7-190641.15"
+ attribute \src "libresoc.v:187814.7-187814.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190676$13300
+ cell $and $and$libresoc.v:187849$13156
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190676$13300_Y
+ connect \Y $and$libresoc.v:187849$13156_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190681$13305
+ cell $and $and$libresoc.v:187854$13161
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190681$13305_Y
+ connect \Y $and$libresoc.v:187854$13161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190678$13302
+ cell $not $not$libresoc.v:187851$13158
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:190678$13302_Y
+ connect \Y $not$libresoc.v:187851$13158_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190680$13304
+ cell $not $not$libresoc.v:187853$13160
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:190680$13304_Y
+ connect \Y $not$libresoc.v:187853$13160_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190683$13307
+ cell $not $not$libresoc.v:187856$13163
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:190683$13307_Y
+ connect \Y $not$libresoc.v:187856$13163_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190677$13301
+ cell $or $or$libresoc.v:187850$13157
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190677$13301_Y
+ connect \Y $or$libresoc.v:187850$13157_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190679$13303
+ cell $or $or$libresoc.v:187852$13159
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190679$13303_Y
+ connect \Y $or$libresoc.v:187852$13159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190682$13306
+ cell $or $or$libresoc.v:187855$13162
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190682$13306_Y
+ connect \Y $or$libresoc.v:187855$13162_Y
end
- attribute \src "libresoc.v:190641.7-190641.20"
- process $proc$libresoc.v:190641$13312
+ attribute \src "libresoc.v:187814.7-187814.20"
+ process $proc$libresoc.v:187814$13168
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190663.13-190663.26"
- process $proc$libresoc.v:190663$13313
+ attribute \src "libresoc.v:187836.13-187836.26"
+ process $proc$libresoc.v:187836$13169
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:190684.3-190685.27"
- process $proc$libresoc.v:190684$13308
+ attribute \src "libresoc.v:187857.3-187858.27"
+ process $proc$libresoc.v:187857$13164
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:190686.3-190694.6"
- process $proc$libresoc.v:190686$13309
+ attribute \src "libresoc.v:187859.3-187867.6"
+ process $proc$libresoc.v:187859$13165
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13310 $1\q_int$next[5:0]$13311
- attribute \src "libresoc.v:190687.5-190687.29"
+ assign $0\q_int$next[5:0]$13166 $1\q_int$next[5:0]$13167
+ attribute \src "libresoc.v:187860.5-187860.29"
switch \initial
- attribute \src "libresoc.v:190687.9-190687.17"
+ attribute \src "libresoc.v:187860.9-187860.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13311 6'000000
+ assign $1\q_int$next[5:0]$13167 6'000000
case
- assign $1\q_int$next[5:0]$13311 \$5
+ assign $1\q_int$next[5:0]$13167 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13310
+ update \q_int$next $0\q_int$next[5:0]$13166
end
- connect \$9 $and$libresoc.v:190676$13300_Y
- connect \$11 $or$libresoc.v:190677$13301_Y
- connect \$13 $not$libresoc.v:190678$13302_Y
- connect \$15 $or$libresoc.v:190679$13303_Y
- connect \$1 $not$libresoc.v:190680$13304_Y
- connect \$3 $and$libresoc.v:190681$13305_Y
- connect \$5 $or$libresoc.v:190682$13306_Y
- connect \$7 $not$libresoc.v:190683$13307_Y
+ connect \$9 $and$libresoc.v:187849$13156_Y
+ connect \$11 $or$libresoc.v:187850$13157_Y
+ connect \$13 $not$libresoc.v:187851$13158_Y
+ connect \$15 $or$libresoc.v:187852$13159_Y
+ connect \$1 $not$libresoc.v:187853$13160_Y
+ connect \$3 $and$libresoc.v:187854$13161_Y
+ connect \$5 $or$libresoc.v:187855$13162_Y
+ connect \$7 $not$libresoc.v:187856$13163_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190702.1-190760.10"
+attribute \src "libresoc.v:187875.1-187933.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l"
attribute \generator "nMigen"
module \src_l$84
- attribute \src "libresoc.v:190703.7-190703.20"
+ attribute \src "libresoc.v:187876.7-187876.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190748.3-190756.6"
- wire width 3 $0\q_int$next[2:0]$13324
- attribute \src "libresoc.v:190746.3-190747.27"
+ attribute \src "libresoc.v:187921.3-187929.6"
+ wire width 3 $0\q_int$next[2:0]$13180
+ attribute \src "libresoc.v:187919.3-187920.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:190748.3-190756.6"
- wire width 3 $1\q_int$next[2:0]$13325
- attribute \src "libresoc.v:190725.13-190725.25"
+ attribute \src "libresoc.v:187921.3-187929.6"
+ wire width 3 $1\q_int$next[2:0]$13181
+ attribute \src "libresoc.v:187898.13-187898.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:190738.17-190738.96"
- wire width 3 $and$libresoc.v:190738$13314_Y
- attribute \src "libresoc.v:190743.17-190743.96"
- wire width 3 $and$libresoc.v:190743$13319_Y
- attribute \src "libresoc.v:190740.18-190740.93"
- wire width 3 $not$libresoc.v:190740$13316_Y
- attribute \src "libresoc.v:190742.17-190742.92"
- wire width 3 $not$libresoc.v:190742$13318_Y
- attribute \src "libresoc.v:190745.17-190745.92"
- wire width 3 $not$libresoc.v:190745$13321_Y
- attribute \src "libresoc.v:190739.18-190739.98"
- wire width 3 $or$libresoc.v:190739$13315_Y
- attribute \src "libresoc.v:190741.18-190741.99"
- wire width 3 $or$libresoc.v:190741$13317_Y
- attribute \src "libresoc.v:190744.17-190744.97"
- wire width 3 $or$libresoc.v:190744$13320_Y
+ attribute \src "libresoc.v:187911.17-187911.96"
+ wire width 3 $and$libresoc.v:187911$13170_Y
+ attribute \src "libresoc.v:187916.17-187916.96"
+ wire width 3 $and$libresoc.v:187916$13175_Y
+ attribute \src "libresoc.v:187913.18-187913.93"
+ wire width 3 $not$libresoc.v:187913$13172_Y
+ attribute \src "libresoc.v:187915.17-187915.92"
+ wire width 3 $not$libresoc.v:187915$13174_Y
+ attribute \src "libresoc.v:187918.17-187918.92"
+ wire width 3 $not$libresoc.v:187918$13177_Y
+ attribute \src "libresoc.v:187912.18-187912.98"
+ wire width 3 $or$libresoc.v:187912$13171_Y
+ attribute \src "libresoc.v:187914.18-187914.99"
+ wire width 3 $or$libresoc.v:187914$13173_Y
+ attribute \src "libresoc.v:187917.17-187917.97"
+ wire width 3 $or$libresoc.v:187917$13176_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190703.7-190703.15"
+ attribute \src "libresoc.v:187876.7-187876.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190738$13314
+ cell $and $and$libresoc.v:187911$13170
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190738$13314_Y
+ connect \Y $and$libresoc.v:187911$13170_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190743$13319
+ cell $and $and$libresoc.v:187916$13175
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190743$13319_Y
+ connect \Y $and$libresoc.v:187916$13175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190740$13316
+ cell $not $not$libresoc.v:187913$13172
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:190740$13316_Y
+ connect \Y $not$libresoc.v:187913$13172_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190742$13318
+ cell $not $not$libresoc.v:187915$13174
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190742$13318_Y
+ connect \Y $not$libresoc.v:187915$13174_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190745$13321
+ cell $not $not$libresoc.v:187918$13177
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:190745$13321_Y
+ connect \Y $not$libresoc.v:187918$13177_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190739$13315
+ cell $or $or$libresoc.v:187912$13171
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:190739$13315_Y
+ connect \Y $or$libresoc.v:187912$13171_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190741$13317
+ cell $or $or$libresoc.v:187914$13173
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:190741$13317_Y
+ connect \Y $or$libresoc.v:187914$13173_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190744$13320
+ cell $or $or$libresoc.v:187917$13176
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:190744$13320_Y
+ connect \Y $or$libresoc.v:187917$13176_Y
end
- attribute \src "libresoc.v:190703.7-190703.20"
- process $proc$libresoc.v:190703$13326
+ attribute \src "libresoc.v:187876.7-187876.20"
+ process $proc$libresoc.v:187876$13182
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190725.13-190725.25"
- process $proc$libresoc.v:190725$13327
+ attribute \src "libresoc.v:187898.13-187898.25"
+ process $proc$libresoc.v:187898$13183
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:190746.3-190747.27"
- process $proc$libresoc.v:190746$13322
+ attribute \src "libresoc.v:187919.3-187920.27"
+ process $proc$libresoc.v:187919$13178
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:190748.3-190756.6"
- process $proc$libresoc.v:190748$13323
+ attribute \src "libresoc.v:187921.3-187929.6"
+ process $proc$libresoc.v:187921$13179
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13324 $1\q_int$next[2:0]$13325
- attribute \src "libresoc.v:190749.5-190749.29"
+ assign $0\q_int$next[2:0]$13180 $1\q_int$next[2:0]$13181
+ attribute \src "libresoc.v:187922.5-187922.29"
switch \initial
- attribute \src "libresoc.v:190749.9-190749.17"
+ attribute \src "libresoc.v:187922.9-187922.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13325 3'000
+ assign $1\q_int$next[2:0]$13181 3'000
case
- assign $1\q_int$next[2:0]$13325 \$5
+ assign $1\q_int$next[2:0]$13181 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13324
+ update \q_int$next $0\q_int$next[2:0]$13180
end
- connect \$9 $and$libresoc.v:190738$13314_Y
- connect \$11 $or$libresoc.v:190739$13315_Y
- connect \$13 $not$libresoc.v:190740$13316_Y
- connect \$15 $or$libresoc.v:190741$13317_Y
- connect \$1 $not$libresoc.v:190742$13318_Y
- connect \$3 $and$libresoc.v:190743$13319_Y
- connect \$5 $or$libresoc.v:190744$13320_Y
- connect \$7 $not$libresoc.v:190745$13321_Y
+ connect \$9 $and$libresoc.v:187911$13170_Y
+ connect \$11 $or$libresoc.v:187912$13171_Y
+ connect \$13 $not$libresoc.v:187913$13172_Y
+ connect \$15 $or$libresoc.v:187914$13173_Y
+ connect \$1 $not$libresoc.v:187915$13174_Y
+ connect \$3 $and$libresoc.v:187916$13175_Y
+ connect \$5 $or$libresoc.v:187917$13176_Y
+ connect \$7 $not$libresoc.v:187918$13177_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:190764.1-190822.10"
+attribute \src "libresoc.v:187937.1-187995.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active"
attribute \generator "nMigen"
module \st_active
- attribute \src "libresoc.v:190765.7-190765.20"
+ attribute \src "libresoc.v:187938.7-187938.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190810.3-190818.6"
- wire $0\q_int$next[0:0]$13338
- attribute \src "libresoc.v:190808.3-190809.27"
+ attribute \src "libresoc.v:187983.3-187991.6"
+ wire $0\q_int$next[0:0]$13194
+ attribute \src "libresoc.v:187981.3-187982.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:190810.3-190818.6"
- wire $1\q_int$next[0:0]$13339
- attribute \src "libresoc.v:190787.7-190787.19"
+ attribute \src "libresoc.v:187983.3-187991.6"
+ wire $1\q_int$next[0:0]$13195
+ attribute \src "libresoc.v:187960.7-187960.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:190800.17-190800.96"
- wire $and$libresoc.v:190800$13328_Y
- attribute \src "libresoc.v:190805.17-190805.96"
- wire $and$libresoc.v:190805$13333_Y
- attribute \src "libresoc.v:190802.18-190802.99"
- wire $not$libresoc.v:190802$13330_Y
- attribute \src "libresoc.v:190804.17-190804.98"
- wire $not$libresoc.v:190804$13332_Y
- attribute \src "libresoc.v:190807.17-190807.98"
- wire $not$libresoc.v:190807$13335_Y
- attribute \src "libresoc.v:190801.18-190801.104"
- wire $or$libresoc.v:190801$13329_Y
- attribute \src "libresoc.v:190803.18-190803.105"
- wire $or$libresoc.v:190803$13331_Y
- attribute \src "libresoc.v:190806.17-190806.103"
- wire $or$libresoc.v:190806$13334_Y
+ attribute \src "libresoc.v:187973.17-187973.96"
+ wire $and$libresoc.v:187973$13184_Y
+ attribute \src "libresoc.v:187978.17-187978.96"
+ wire $and$libresoc.v:187978$13189_Y
+ attribute \src "libresoc.v:187975.18-187975.99"
+ wire $not$libresoc.v:187975$13186_Y
+ attribute \src "libresoc.v:187977.17-187977.98"
+ wire $not$libresoc.v:187977$13188_Y
+ attribute \src "libresoc.v:187980.17-187980.98"
+ wire $not$libresoc.v:187980$13191_Y
+ attribute \src "libresoc.v:187974.18-187974.104"
+ wire $or$libresoc.v:187974$13185_Y
+ attribute \src "libresoc.v:187976.18-187976.105"
+ wire $or$libresoc.v:187976$13187_Y
+ attribute \src "libresoc.v:187979.17-187979.103"
+ wire $or$libresoc.v:187979$13190_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190765.7-190765.15"
+ attribute \src "libresoc.v:187938.7-187938.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_st_active
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190800$13328
+ cell $and $and$libresoc.v:187973$13184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190800$13328_Y
+ connect \Y $and$libresoc.v:187973$13184_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190805$13333
+ cell $and $and$libresoc.v:187978$13189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190805$13333_Y
+ connect \Y $and$libresoc.v:187978$13189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190802$13330
+ cell $not $not$libresoc.v:187975$13186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_active
- connect \Y $not$libresoc.v:190802$13330_Y
+ connect \Y $not$libresoc.v:187975$13186_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190804$13332
+ cell $not $not$libresoc.v:187977$13188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:190804$13332_Y
+ connect \Y $not$libresoc.v:187977$13188_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190807$13335
+ cell $not $not$libresoc.v:187980$13191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:190807$13335_Y
+ connect \Y $not$libresoc.v:187980$13191_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190801$13329
+ cell $or $or$libresoc.v:187974$13185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_active
- connect \Y $or$libresoc.v:190801$13329_Y
+ connect \Y $or$libresoc.v:187974$13185_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190803$13331
+ cell $or $or$libresoc.v:187976$13187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_active
connect \B \q_int
- connect \Y $or$libresoc.v:190803$13331_Y
+ connect \Y $or$libresoc.v:187976$13187_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190806$13334
+ cell $or $or$libresoc.v:187979$13190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_active
- connect \Y $or$libresoc.v:190806$13334_Y
+ connect \Y $or$libresoc.v:187979$13190_Y
end
- attribute \src "libresoc.v:190765.7-190765.20"
- process $proc$libresoc.v:190765$13340
+ attribute \src "libresoc.v:187938.7-187938.20"
+ process $proc$libresoc.v:187938$13196
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190787.7-190787.19"
- process $proc$libresoc.v:190787$13341
+ attribute \src "libresoc.v:187960.7-187960.19"
+ process $proc$libresoc.v:187960$13197
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:190808.3-190809.27"
- process $proc$libresoc.v:190808$13336
+ attribute \src "libresoc.v:187981.3-187982.27"
+ process $proc$libresoc.v:187981$13192
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:190810.3-190818.6"
- process $proc$libresoc.v:190810$13337
+ attribute \src "libresoc.v:187983.3-187991.6"
+ process $proc$libresoc.v:187983$13193
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13338 $1\q_int$next[0:0]$13339
- attribute \src "libresoc.v:190811.5-190811.29"
+ assign $0\q_int$next[0:0]$13194 $1\q_int$next[0:0]$13195
+ attribute \src "libresoc.v:187984.5-187984.29"
switch \initial
- attribute \src "libresoc.v:190811.9-190811.17"
+ attribute \src "libresoc.v:187984.9-187984.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13339 1'0
+ assign $1\q_int$next[0:0]$13195 1'0
case
- assign $1\q_int$next[0:0]$13339 \$5
+ assign $1\q_int$next[0:0]$13195 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13338
+ update \q_int$next $0\q_int$next[0:0]$13194
end
- connect \$9 $and$libresoc.v:190800$13328_Y
- connect \$11 $or$libresoc.v:190801$13329_Y
- connect \$13 $not$libresoc.v:190802$13330_Y
- connect \$15 $or$libresoc.v:190803$13331_Y
- connect \$1 $not$libresoc.v:190804$13332_Y
- connect \$3 $and$libresoc.v:190805$13333_Y
- connect \$5 $or$libresoc.v:190806$13334_Y
- connect \$7 $not$libresoc.v:190807$13335_Y
+ connect \$9 $and$libresoc.v:187973$13184_Y
+ connect \$11 $or$libresoc.v:187974$13185_Y
+ connect \$13 $not$libresoc.v:187975$13186_Y
+ connect \$15 $or$libresoc.v:187976$13187_Y
+ connect \$1 $not$libresoc.v:187977$13188_Y
+ connect \$3 $and$libresoc.v:187978$13189_Y
+ connect \$5 $or$libresoc.v:187979$13190_Y
+ connect \$7 $not$libresoc.v:187980$13191_Y
connect \qlq_st_active \$15
connect \qn_st_active \$13
connect \q_st_active \$11
end
-attribute \src "libresoc.v:190826.1-190884.10"
+attribute \src "libresoc.v:187999.1-188057.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done"
attribute \generator "nMigen"
module \st_done
- attribute \src "libresoc.v:190827.7-190827.20"
+ attribute \src "libresoc.v:188000.7-188000.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190872.3-190880.6"
- wire $0\q_int$next[0:0]$13352
- attribute \src "libresoc.v:190870.3-190871.27"
+ attribute \src "libresoc.v:188045.3-188053.6"
+ wire $0\q_int$next[0:0]$13208
+ attribute \src "libresoc.v:188043.3-188044.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:190872.3-190880.6"
- wire $1\q_int$next[0:0]$13353
- attribute \src "libresoc.v:190849.7-190849.19"
+ attribute \src "libresoc.v:188045.3-188053.6"
+ wire $1\q_int$next[0:0]$13209
+ attribute \src "libresoc.v:188022.7-188022.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:190862.17-190862.96"
- wire $and$libresoc.v:190862$13342_Y
- attribute \src "libresoc.v:190867.17-190867.96"
- wire $and$libresoc.v:190867$13347_Y
- attribute \src "libresoc.v:190864.18-190864.97"
- wire $not$libresoc.v:190864$13344_Y
- attribute \src "libresoc.v:190866.17-190866.96"
- wire $not$libresoc.v:190866$13346_Y
- attribute \src "libresoc.v:190869.17-190869.96"
- wire $not$libresoc.v:190869$13349_Y
- attribute \src "libresoc.v:190863.18-190863.102"
- wire $or$libresoc.v:190863$13343_Y
- attribute \src "libresoc.v:190865.18-190865.103"
- wire $or$libresoc.v:190865$13345_Y
- attribute \src "libresoc.v:190868.17-190868.101"
- wire $or$libresoc.v:190868$13348_Y
+ attribute \src "libresoc.v:188035.17-188035.96"
+ wire $and$libresoc.v:188035$13198_Y
+ attribute \src "libresoc.v:188040.17-188040.96"
+ wire $and$libresoc.v:188040$13203_Y
+ attribute \src "libresoc.v:188037.18-188037.97"
+ wire $not$libresoc.v:188037$13200_Y
+ attribute \src "libresoc.v:188039.17-188039.96"
+ wire $not$libresoc.v:188039$13202_Y
+ attribute \src "libresoc.v:188042.17-188042.96"
+ wire $not$libresoc.v:188042$13205_Y
+ attribute \src "libresoc.v:188036.18-188036.102"
+ wire $or$libresoc.v:188036$13199_Y
+ attribute \src "libresoc.v:188038.18-188038.103"
+ wire $or$libresoc.v:188038$13201_Y
+ attribute \src "libresoc.v:188041.17-188041.101"
+ wire $or$libresoc.v:188041$13204_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:190827.7-190827.15"
+ attribute \src "libresoc.v:188000.7-188000.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_st_done
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:190862$13342
+ cell $and $and$libresoc.v:188035$13198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:190862$13342_Y
+ connect \Y $and$libresoc.v:188035$13198_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:190867$13347
+ cell $and $and$libresoc.v:188040$13203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:190867$13347_Y
+ connect \Y $and$libresoc.v:188040$13203_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:190864$13344
+ cell $not $not$libresoc.v:188037$13200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_done
- connect \Y $not$libresoc.v:190864$13344_Y
+ connect \Y $not$libresoc.v:188037$13200_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:190866$13346
+ cell $not $not$libresoc.v:188039$13202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:190866$13346_Y
+ connect \Y $not$libresoc.v:188039$13202_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:190869$13349
+ cell $not $not$libresoc.v:188042$13205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:190869$13349_Y
+ connect \Y $not$libresoc.v:188042$13205_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:190863$13343
+ cell $or $or$libresoc.v:188036$13199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_done
- connect \Y $or$libresoc.v:190863$13343_Y
+ connect \Y $or$libresoc.v:188036$13199_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:190865$13345
+ cell $or $or$libresoc.v:188038$13201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_done
connect \B \q_int
- connect \Y $or$libresoc.v:190865$13345_Y
+ connect \Y $or$libresoc.v:188038$13201_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:190868$13348
+ cell $or $or$libresoc.v:188041$13204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_done
- connect \Y $or$libresoc.v:190868$13348_Y
+ connect \Y $or$libresoc.v:188041$13204_Y
end
- attribute \src "libresoc.v:190827.7-190827.20"
- process $proc$libresoc.v:190827$13354
+ attribute \src "libresoc.v:188000.7-188000.20"
+ process $proc$libresoc.v:188000$13210
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190849.7-190849.19"
- process $proc$libresoc.v:190849$13355
+ attribute \src "libresoc.v:188022.7-188022.19"
+ process $proc$libresoc.v:188022$13211
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:190870.3-190871.27"
- process $proc$libresoc.v:190870$13350
+ attribute \src "libresoc.v:188043.3-188044.27"
+ process $proc$libresoc.v:188043$13206
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:190872.3-190880.6"
- process $proc$libresoc.v:190872$13351
+ attribute \src "libresoc.v:188045.3-188053.6"
+ process $proc$libresoc.v:188045$13207
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13352 $1\q_int$next[0:0]$13353
- attribute \src "libresoc.v:190873.5-190873.29"
+ assign $0\q_int$next[0:0]$13208 $1\q_int$next[0:0]$13209
+ attribute \src "libresoc.v:188046.5-188046.29"
switch \initial
- attribute \src "libresoc.v:190873.9-190873.17"
+ attribute \src "libresoc.v:188046.9-188046.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13353 1'0
+ assign $1\q_int$next[0:0]$13209 1'0
case
- assign $1\q_int$next[0:0]$13353 \$5
+ assign $1\q_int$next[0:0]$13209 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13352
+ update \q_int$next $0\q_int$next[0:0]$13208
end
- connect \$9 $and$libresoc.v:190862$13342_Y
- connect \$11 $or$libresoc.v:190863$13343_Y
- connect \$13 $not$libresoc.v:190864$13344_Y
- connect \$15 $or$libresoc.v:190865$13345_Y
- connect \$1 $not$libresoc.v:190866$13346_Y
- connect \$3 $and$libresoc.v:190867$13347_Y
- connect \$5 $or$libresoc.v:190868$13348_Y
- connect \$7 $not$libresoc.v:190869$13349_Y
+ connect \$9 $and$libresoc.v:188035$13198_Y
+ connect \$11 $or$libresoc.v:188036$13199_Y
+ connect \$13 $not$libresoc.v:188037$13200_Y
+ connect \$15 $or$libresoc.v:188038$13201_Y
+ connect \$1 $not$libresoc.v:188039$13202_Y
+ connect \$3 $and$libresoc.v:188040$13203_Y
+ connect \$5 $or$libresoc.v:188041$13204_Y
+ connect \$7 $not$libresoc.v:188042$13205_Y
connect \qlq_st_done \$15
connect \qn_st_done \$13
connect \q_st_done \$11
end
-attribute \src "libresoc.v:190888.1-191184.10"
+attribute \src "libresoc.v:188061.1-188357.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state"
attribute \generator "nMigen"
module \state
- attribute \src "libresoc.v:191136.3-191145.6"
+ attribute \src "libresoc.v:188309.3-188318.6"
wire width 64 $0\cia__data_o[63:0]
- attribute \src "libresoc.v:190889.7-190889.20"
+ attribute \src "libresoc.v:188062.7-188062.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:191155.3-191164.6"
+ attribute \src "libresoc.v:188328.3-188337.6"
wire width 64 $0\msr__data_o[63:0]
- attribute \src "libresoc.v:191146.3-191154.6"
- wire width 3 $0\ren_delay$12$next[2:0]$13379
- attribute \src "libresoc.v:191050.3-191051.43"
- wire width 3 $0\ren_delay$12[2:0]$13368
- attribute \src "libresoc.v:191017.13-191017.34"
- wire width 3 $0\ren_delay$12[2:0]$13385
- attribute \src "libresoc.v:191108.3-191116.6"
- wire width 3 $0\ren_delay$19$next[2:0]$13371
- attribute \src "libresoc.v:191048.3-191049.43"
- wire width 3 $0\ren_delay$19[2:0]$13366
- attribute \src "libresoc.v:191021.13-191021.34"
- wire width 3 $0\ren_delay$19[2:0]$13387
- attribute \src "libresoc.v:191127.3-191135.6"
- wire width 3 $0\ren_delay$next[2:0]$13375
- attribute \src "libresoc.v:191052.3-191053.35"
+ attribute \src "libresoc.v:188319.3-188327.6"
+ wire width 3 $0\ren_delay$12$next[2:0]$13235
+ attribute \src "libresoc.v:188223.3-188224.43"
+ wire width 3 $0\ren_delay$12[2:0]$13224
+ attribute \src "libresoc.v:188190.13-188190.34"
+ wire width 3 $0\ren_delay$12[2:0]$13241
+ attribute \src "libresoc.v:188281.3-188289.6"
+ wire width 3 $0\ren_delay$19$next[2:0]$13227
+ attribute \src "libresoc.v:188221.3-188222.43"
+ wire width 3 $0\ren_delay$19[2:0]$13222
+ attribute \src "libresoc.v:188194.13-188194.34"
+ wire width 3 $0\ren_delay$19[2:0]$13243
+ attribute \src "libresoc.v:188300.3-188308.6"
+ wire width 3 $0\ren_delay$next[2:0]$13231
+ attribute \src "libresoc.v:188225.3-188226.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:191117.3-191126.6"
+ attribute \src "libresoc.v:188290.3-188299.6"
wire width 64 $0\sv__data_o[63:0]
- attribute \src "libresoc.v:191136.3-191145.6"
+ attribute \src "libresoc.v:188309.3-188318.6"
wire width 64 $1\cia__data_o[63:0]
- attribute \src "libresoc.v:191155.3-191164.6"
+ attribute \src "libresoc.v:188328.3-188337.6"
wire width 64 $1\msr__data_o[63:0]
- attribute \src "libresoc.v:191146.3-191154.6"
- wire width 3 $1\ren_delay$12$next[2:0]$13380
- attribute \src "libresoc.v:191108.3-191116.6"
- wire width 3 $1\ren_delay$19$next[2:0]$13372
- attribute \src "libresoc.v:191127.3-191135.6"
- wire width 3 $1\ren_delay$next[2:0]$13376
- attribute \src "libresoc.v:191015.13-191015.29"
+ attribute \src "libresoc.v:188319.3-188327.6"
+ wire width 3 $1\ren_delay$12$next[2:0]$13236
+ attribute \src "libresoc.v:188281.3-188289.6"
+ wire width 3 $1\ren_delay$19$next[2:0]$13228
+ attribute \src "libresoc.v:188300.3-188308.6"
+ wire width 3 $1\ren_delay$next[2:0]$13232
+ attribute \src "libresoc.v:188188.13-188188.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:191117.3-191126.6"
+ attribute \src "libresoc.v:188290.3-188299.6"
wire width 64 $1\sv__data_o[63:0]
- attribute \src "libresoc.v:191039.18-191039.109"
- wire width 64 $or$libresoc.v:191039$13356_Y
- attribute \src "libresoc.v:191041.18-191041.124"
- wire width 64 $or$libresoc.v:191041$13358_Y
- attribute \src "libresoc.v:191042.18-191042.110"
- wire width 64 $or$libresoc.v:191042$13359_Y
- attribute \src "libresoc.v:191044.18-191044.122"
- wire width 64 $or$libresoc.v:191044$13361_Y
- attribute \src "libresoc.v:191045.18-191045.109"
- wire width 64 $or$libresoc.v:191045$13362_Y
- attribute \src "libresoc.v:191047.17-191047.123"
- wire width 64 $or$libresoc.v:191047$13364_Y
- attribute \src "libresoc.v:191040.18-191040.100"
- wire $reduce_or$libresoc.v:191040$13357_Y
- attribute \src "libresoc.v:191043.18-191043.100"
- wire $reduce_or$libresoc.v:191043$13360_Y
- attribute \src "libresoc.v:191046.17-191046.95"
- wire $reduce_or$libresoc.v:191046$13363_Y
+ attribute \src "libresoc.v:188212.18-188212.109"
+ wire width 64 $or$libresoc.v:188212$13212_Y
+ attribute \src "libresoc.v:188214.18-188214.124"
+ wire width 64 $or$libresoc.v:188214$13214_Y
+ attribute \src "libresoc.v:188215.18-188215.110"
+ wire width 64 $or$libresoc.v:188215$13215_Y
+ attribute \src "libresoc.v:188217.18-188217.122"
+ wire width 64 $or$libresoc.v:188217$13217_Y
+ attribute \src "libresoc.v:188218.18-188218.109"
+ wire width 64 $or$libresoc.v:188218$13218_Y
+ attribute \src "libresoc.v:188220.17-188220.123"
+ wire width 64 $or$libresoc.v:188220$13220_Y
+ attribute \src "libresoc.v:188213.18-188213.100"
+ wire $reduce_or$libresoc.v:188213$13213_Y
+ attribute \src "libresoc.v:188216.18-188216.100"
+ wire $reduce_or$libresoc.v:188216$13216_Y
+ attribute \src "libresoc.v:188219.17-188219.95"
+ wire $reduce_or$libresoc.v:188219$13219_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 64 \$10
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 64 output 3 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 2 \cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 7 \data_i
wire width 64 input 13 \data_i$3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 14 \data_i$4
- attribute \src "libresoc.v:190889.7-190889.15"
+ attribute \src "libresoc.v:188062.7-188062.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 9 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:191039$13356
+ cell $or $or$libresoc.v:188212$13212
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_cia0__data_o
connect \B \$8
- connect \Y $or$libresoc.v:191039$13356_Y
+ connect \Y $or$libresoc.v:188212$13212_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:191041$13358
+ cell $or $or$libresoc.v:188214$13214
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_msr1__data_o
connect \B \reg_2_msr2__data_o
- connect \Y $or$libresoc.v:191041$13358_Y
+ connect \Y $or$libresoc.v:188214$13214_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:191042$13359
+ cell $or $or$libresoc.v:188215$13215
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_msr0__data_o
connect \B \$15
- connect \Y $or$libresoc.v:191042$13359_Y
+ connect \Y $or$libresoc.v:188215$13215_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:191044$13361
+ cell $or $or$libresoc.v:188217$13217
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_sv1__data_o
connect \B \reg_2_sv2__data_o
- connect \Y $or$libresoc.v:191044$13361_Y
+ connect \Y $or$libresoc.v:188217$13217_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:191045$13362
+ cell $or $or$libresoc.v:188218$13218
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_sv0__data_o
connect \B \$22
- connect \Y $or$libresoc.v:191045$13362_Y
+ connect \Y $or$libresoc.v:188218$13218_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:191047$13364
+ cell $or $or$libresoc.v:188220$13220
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_cia1__data_o
connect \B \reg_2_cia2__data_o
- connect \Y $or$libresoc.v:191047$13364_Y
+ connect \Y $or$libresoc.v:188220$13220_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:191040$13357
+ cell $reduce_or $reduce_or$libresoc.v:188213$13213
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$12
- connect \Y $reduce_or$libresoc.v:191040$13357_Y
+ connect \Y $reduce_or$libresoc.v:188213$13213_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:191043$13360
+ cell $reduce_or $reduce_or$libresoc.v:188216$13216
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$19
- connect \Y $reduce_or$libresoc.v:191043$13360_Y
+ connect \Y $reduce_or$libresoc.v:188216$13216_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:191046$13363
+ cell $reduce_or $reduce_or$libresoc.v:188219$13219
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:191046$13363_Y
+ connect \Y $reduce_or$libresoc.v:188219$13219_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:191054.15-191071.4"
+ attribute \src "libresoc.v:188227.15-188244.4"
cell \reg_0$135 \reg_0
connect \cia0__data_o \reg_0_cia0__data_o
connect \cia0__ren \reg_0_cia0__ren
connect \sv0__wen \reg_0_sv0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:191072.15-191089.4"
+ attribute \src "libresoc.v:188245.15-188262.4"
cell \reg_1$136 \reg_1
connect \cia1__data_o \reg_1_cia1__data_o
connect \cia1__ren \reg_1_cia1__ren
connect \sv1__wen \reg_1_sv1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:191090.15-191107.4"
+ attribute \src "libresoc.v:188263.15-188280.4"
cell \reg_2$137 \reg_2
connect \cia2__data_o \reg_2_cia2__data_o
connect \cia2__ren \reg_2_cia2__ren
connect \sv2__ren \reg_2_sv2__ren
connect \sv2__wen \reg_2_sv2__wen
end
- attribute \src "libresoc.v:190889.7-190889.20"
- process $proc$libresoc.v:190889$13382
+ attribute \src "libresoc.v:188062.7-188062.20"
+ process $proc$libresoc.v:188062$13238
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:191015.13-191015.29"
- process $proc$libresoc.v:191015$13383
+ attribute \src "libresoc.v:188188.13-188188.29"
+ process $proc$libresoc.v:188188$13239
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:191017.13-191017.34"
- process $proc$libresoc.v:191017$13384
+ attribute \src "libresoc.v:188190.13-188190.34"
+ process $proc$libresoc.v:188190$13240
assign { } { }
- assign $0\ren_delay$12[2:0]$13385 3'000
+ assign $0\ren_delay$12[2:0]$13241 3'000
sync always
sync init
- update \ren_delay$12 $0\ren_delay$12[2:0]$13385
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13241
end
- attribute \src "libresoc.v:191021.13-191021.34"
- process $proc$libresoc.v:191021$13386
+ attribute \src "libresoc.v:188194.13-188194.34"
+ process $proc$libresoc.v:188194$13242
assign { } { }
- assign $0\ren_delay$19[2:0]$13387 3'000
+ assign $0\ren_delay$19[2:0]$13243 3'000
sync always
sync init
- update \ren_delay$19 $0\ren_delay$19[2:0]$13387
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13243
end
- attribute \src "libresoc.v:191048.3-191049.43"
- process $proc$libresoc.v:191048$13365
+ attribute \src "libresoc.v:188221.3-188222.43"
+ process $proc$libresoc.v:188221$13221
assign { } { }
- assign $0\ren_delay$19[2:0]$13366 \ren_delay$19$next
+ assign $0\ren_delay$19[2:0]$13222 \ren_delay$19$next
sync posedge \coresync_clk
- update \ren_delay$19 $0\ren_delay$19[2:0]$13366
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13222
end
- attribute \src "libresoc.v:191050.3-191051.43"
- process $proc$libresoc.v:191050$13367
+ attribute \src "libresoc.v:188223.3-188224.43"
+ process $proc$libresoc.v:188223$13223
assign { } { }
- assign $0\ren_delay$12[2:0]$13368 \ren_delay$12$next
+ assign $0\ren_delay$12[2:0]$13224 \ren_delay$12$next
sync posedge \coresync_clk
- update \ren_delay$12 $0\ren_delay$12[2:0]$13368
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13224
end
- attribute \src "libresoc.v:191052.3-191053.35"
- process $proc$libresoc.v:191052$13369
+ attribute \src "libresoc.v:188225.3-188226.35"
+ process $proc$libresoc.v:188225$13225
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:191108.3-191116.6"
- process $proc$libresoc.v:191108$13370
+ attribute \src "libresoc.v:188281.3-188289.6"
+ process $proc$libresoc.v:188281$13226
assign { } { }
assign { } { }
- assign $0\ren_delay$19$next[2:0]$13371 $1\ren_delay$19$next[2:0]$13372
- attribute \src "libresoc.v:191109.5-191109.29"
+ assign $0\ren_delay$19$next[2:0]$13227 $1\ren_delay$19$next[2:0]$13228
+ attribute \src "libresoc.v:188282.5-188282.29"
switch \initial
- attribute \src "libresoc.v:191109.9-191109.17"
+ attribute \src "libresoc.v:188282.9-188282.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$19$next[2:0]$13372 3'000
+ assign $1\ren_delay$19$next[2:0]$13228 3'000
case
- assign $1\ren_delay$19$next[2:0]$13372 \sv__ren
+ assign $1\ren_delay$19$next[2:0]$13228 \sv__ren
end
sync always
- update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13371
+ update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13227
end
- attribute \src "libresoc.v:191117.3-191126.6"
- process $proc$libresoc.v:191117$13373
+ attribute \src "libresoc.v:188290.3-188299.6"
+ process $proc$libresoc.v:188290$13229
assign { } { }
assign { } { }
assign $0\sv__data_o[63:0] $1\sv__data_o[63:0]
- attribute \src "libresoc.v:191118.5-191118.29"
+ attribute \src "libresoc.v:188291.5-188291.29"
switch \initial
- attribute \src "libresoc.v:191118.9-191118.17"
+ attribute \src "libresoc.v:188291.9-188291.17"
case 1'1
case
end
sync always
update \sv__data_o $0\sv__data_o[63:0]
end
- attribute \src "libresoc.v:191127.3-191135.6"
- process $proc$libresoc.v:191127$13374
+ attribute \src "libresoc.v:188300.3-188308.6"
+ process $proc$libresoc.v:188300$13230
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$13375 $1\ren_delay$next[2:0]$13376
- attribute \src "libresoc.v:191128.5-191128.29"
+ assign $0\ren_delay$next[2:0]$13231 $1\ren_delay$next[2:0]$13232
+ attribute \src "libresoc.v:188301.5-188301.29"
switch \initial
- attribute \src "libresoc.v:191128.9-191128.17"
+ attribute \src "libresoc.v:188301.9-188301.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$13376 3'000
+ assign $1\ren_delay$next[2:0]$13232 3'000
case
- assign $1\ren_delay$next[2:0]$13376 \cia__ren
+ assign $1\ren_delay$next[2:0]$13232 \cia__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$13375
+ update \ren_delay$next $0\ren_delay$next[2:0]$13231
end
- attribute \src "libresoc.v:191136.3-191145.6"
- process $proc$libresoc.v:191136$13377
+ attribute \src "libresoc.v:188309.3-188318.6"
+ process $proc$libresoc.v:188309$13233
assign { } { }
assign { } { }
assign $0\cia__data_o[63:0] $1\cia__data_o[63:0]
- attribute \src "libresoc.v:191137.5-191137.29"
+ attribute \src "libresoc.v:188310.5-188310.29"
switch \initial
- attribute \src "libresoc.v:191137.9-191137.17"
+ attribute \src "libresoc.v:188310.9-188310.17"
case 1'1
case
end
sync always
update \cia__data_o $0\cia__data_o[63:0]
end
- attribute \src "libresoc.v:191146.3-191154.6"
- process $proc$libresoc.v:191146$13378
+ attribute \src "libresoc.v:188319.3-188327.6"
+ process $proc$libresoc.v:188319$13234
assign { } { }
assign { } { }
- assign $0\ren_delay$12$next[2:0]$13379 $1\ren_delay$12$next[2:0]$13380
- attribute \src "libresoc.v:191147.5-191147.29"
+ assign $0\ren_delay$12$next[2:0]$13235 $1\ren_delay$12$next[2:0]$13236
+ attribute \src "libresoc.v:188320.5-188320.29"
switch \initial
- attribute \src "libresoc.v:191147.9-191147.17"
+ attribute \src "libresoc.v:188320.9-188320.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$12$next[2:0]$13380 3'000
+ assign $1\ren_delay$12$next[2:0]$13236 3'000
case
- assign $1\ren_delay$12$next[2:0]$13380 \msr__ren
+ assign $1\ren_delay$12$next[2:0]$13236 \msr__ren
end
sync always
- update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13379
+ update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13235
end
- attribute \src "libresoc.v:191155.3-191164.6"
- process $proc$libresoc.v:191155$13381
+ attribute \src "libresoc.v:188328.3-188337.6"
+ process $proc$libresoc.v:188328$13237
assign { } { }
assign { } { }
assign $0\msr__data_o[63:0] $1\msr__data_o[63:0]
- attribute \src "libresoc.v:191156.5-191156.29"
+ attribute \src "libresoc.v:188329.5-188329.29"
switch \initial
- attribute \src "libresoc.v:191156.9-191156.17"
+ attribute \src "libresoc.v:188329.9-188329.17"
case 1'1
case
end
sync always
update \msr__data_o $0\msr__data_o[63:0]
end
- connect \$10 $or$libresoc.v:191039$13356_Y
- connect \$13 $reduce_or$libresoc.v:191040$13357_Y
- connect \$15 $or$libresoc.v:191041$13358_Y
- connect \$17 $or$libresoc.v:191042$13359_Y
- connect \$20 $reduce_or$libresoc.v:191043$13360_Y
- connect \$22 $or$libresoc.v:191044$13361_Y
- connect \$24 $or$libresoc.v:191045$13362_Y
- connect \$6 $reduce_or$libresoc.v:191046$13363_Y
- connect \$8 $or$libresoc.v:191047$13364_Y
+ connect \$10 $or$libresoc.v:188212$13212_Y
+ connect \$13 $reduce_or$libresoc.v:188213$13213_Y
+ connect \$15 $or$libresoc.v:188214$13214_Y
+ connect \$17 $or$libresoc.v:188215$13215_Y
+ connect \$20 $reduce_or$libresoc.v:188216$13216_Y
+ connect \$22 $or$libresoc.v:188217$13217_Y
+ connect \$24 $or$libresoc.v:188218$13218_Y
+ connect \$6 $reduce_or$libresoc.v:188219$13219_Y
+ connect \$8 $or$libresoc.v:188220$13220_Y
connect \reg_2_d_wr12__data_i \data_i
connect \reg_1_d_wr11__data_i \data_i
connect \reg_0_d_wr10__data_i \data_i
connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
end
-attribute \src "libresoc.v:191188.1-191246.10"
+attribute \src "libresoc.v:188361.1-188419.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l"
attribute \generator "nMigen"
module \sto_l
- attribute \src "libresoc.v:191189.7-191189.20"
+ attribute \src "libresoc.v:188362.7-188362.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:191234.3-191242.6"
- wire $0\q_int$next[0:0]$13398
- attribute \src "libresoc.v:191232.3-191233.27"
+ attribute \src "libresoc.v:188407.3-188415.6"
+ wire $0\q_int$next[0:0]$13254
+ attribute \src "libresoc.v:188405.3-188406.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:191234.3-191242.6"
- wire $1\q_int$next[0:0]$13399
- attribute \src "libresoc.v:191211.7-191211.19"
+ attribute \src "libresoc.v:188407.3-188415.6"
+ wire $1\q_int$next[0:0]$13255
+ attribute \src "libresoc.v:188384.7-188384.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:191224.17-191224.96"
- wire $and$libresoc.v:191224$13388_Y
- attribute \src "libresoc.v:191229.17-191229.96"
- wire $and$libresoc.v:191229$13393_Y
- attribute \src "libresoc.v:191226.18-191226.93"
- wire $not$libresoc.v:191226$13390_Y
- attribute \src "libresoc.v:191228.17-191228.92"
- wire $not$libresoc.v:191228$13392_Y
- attribute \src "libresoc.v:191231.17-191231.92"
- wire $not$libresoc.v:191231$13395_Y
- attribute \src "libresoc.v:191225.18-191225.98"
- wire $or$libresoc.v:191225$13389_Y
- attribute \src "libresoc.v:191227.18-191227.99"
- wire $or$libresoc.v:191227$13391_Y
- attribute \src "libresoc.v:191230.17-191230.97"
- wire $or$libresoc.v:191230$13394_Y
+ attribute \src "libresoc.v:188397.17-188397.96"
+ wire $and$libresoc.v:188397$13244_Y
+ attribute \src "libresoc.v:188402.17-188402.96"
+ wire $and$libresoc.v:188402$13249_Y
+ attribute \src "libresoc.v:188399.18-188399.93"
+ wire $not$libresoc.v:188399$13246_Y
+ attribute \src "libresoc.v:188401.17-188401.92"
+ wire $not$libresoc.v:188401$13248_Y
+ attribute \src "libresoc.v:188404.17-188404.92"
+ wire $not$libresoc.v:188404$13251_Y
+ attribute \src "libresoc.v:188398.18-188398.98"
+ wire $or$libresoc.v:188398$13245_Y
+ attribute \src "libresoc.v:188400.18-188400.99"
+ wire $or$libresoc.v:188400$13247_Y
+ attribute \src "libresoc.v:188403.17-188403.97"
+ wire $or$libresoc.v:188403$13250_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:191189.7-191189.15"
+ attribute \src "libresoc.v:188362.7-188362.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_sto
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:191224$13388
+ cell $and $and$libresoc.v:188397$13244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:191224$13388_Y
+ connect \Y $and$libresoc.v:188397$13244_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:191229$13393
+ cell $and $and$libresoc.v:188402$13249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:191229$13393_Y
+ connect \Y $and$libresoc.v:188402$13249_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:191226$13390
+ cell $not $not$libresoc.v:188399$13246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_sto
- connect \Y $not$libresoc.v:191226$13390_Y
+ connect \Y $not$libresoc.v:188399$13246_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:191228$13392
+ cell $not $not$libresoc.v:188401$13248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:191228$13392_Y
+ connect \Y $not$libresoc.v:188401$13248_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:191231$13395
+ cell $not $not$libresoc.v:188404$13251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:191231$13395_Y
+ connect \Y $not$libresoc.v:188404$13251_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:191225$13389
+ cell $or $or$libresoc.v:188398$13245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_sto
- connect \Y $or$libresoc.v:191225$13389_Y
+ connect \Y $or$libresoc.v:188398$13245_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:191227$13391
+ cell $or $or$libresoc.v:188400$13247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_sto
connect \B \q_int
- connect \Y $or$libresoc.v:191227$13391_Y
+ connect \Y $or$libresoc.v:188400$13247_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:191230$13394
+ cell $or $or$libresoc.v:188403$13250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_sto
- connect \Y $or$libresoc.v:191230$13394_Y
+ connect \Y $or$libresoc.v:188403$13250_Y
end
- attribute \src "libresoc.v:191189.7-191189.20"
- process $proc$libresoc.v:191189$13400
+ attribute \src "libresoc.v:188362.7-188362.20"
+ process $proc$libresoc.v:188362$13256
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:191211.7-191211.19"
- process $proc$libresoc.v:191211$13401
+ attribute \src "libresoc.v:188384.7-188384.19"
+ process $proc$libresoc.v:188384$13257
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:191232.3-191233.27"
- process $proc$libresoc.v:191232$13396
+ attribute \src "libresoc.v:188405.3-188406.27"
+ process $proc$libresoc.v:188405$13252
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:191234.3-191242.6"
- process $proc$libresoc.v:191234$13397
+ attribute \src "libresoc.v:188407.3-188415.6"
+ process $proc$libresoc.v:188407$13253
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13398 $1\q_int$next[0:0]$13399
- attribute \src "libresoc.v:191235.5-191235.29"
+ assign $0\q_int$next[0:0]$13254 $1\q_int$next[0:0]$13255
+ attribute \src "libresoc.v:188408.5-188408.29"
switch \initial
- attribute \src "libresoc.v:191235.9-191235.17"
+ attribute \src "libresoc.v:188408.9-188408.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13399 1'0
+ assign $1\q_int$next[0:0]$13255 1'0
case
- assign $1\q_int$next[0:0]$13399 \$5
+ assign $1\q_int$next[0:0]$13255 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13398
+ update \q_int$next $0\q_int$next[0:0]$13254
end
- connect \$9 $and$libresoc.v:191224$13388_Y
- connect \$11 $or$libresoc.v:191225$13389_Y
- connect \$13 $not$libresoc.v:191226$13390_Y
- connect \$15 $or$libresoc.v:191227$13391_Y
- connect \$1 $not$libresoc.v:191228$13392_Y
- connect \$3 $and$libresoc.v:191229$13393_Y
- connect \$5 $or$libresoc.v:191230$13394_Y
- connect \$7 $not$libresoc.v:191231$13395_Y
+ connect \$9 $and$libresoc.v:188397$13244_Y
+ connect \$11 $or$libresoc.v:188398$13245_Y
+ connect \$13 $not$libresoc.v:188399$13246_Y
+ connect \$15 $or$libresoc.v:188400$13247_Y
+ connect \$1 $not$libresoc.v:188401$13248_Y
+ connect \$3 $and$libresoc.v:188402$13249_Y
+ connect \$5 $or$libresoc.v:188403$13250_Y
+ connect \$7 $not$libresoc.v:188404$13251_Y
connect \qlq_sto \$15
connect \qn_sto \$13
connect \q_sto \$11
end
-attribute \src "libresoc.v:191250.1-191305.10"
-attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.ti.svp64"
-attribute \generator "nMigen"
-module \svp64
- attribute \src "libresoc.v:191251.7-191251.20"
- wire $0\initial[0:0]
- attribute \src "libresoc.v:191281.3-191290.6"
- wire width 24 $0\rm[23:0]
- attribute \src "libresoc.v:191291.3-191300.6"
- wire width 24 $0\svp64_rm[23:0]
- attribute \src "libresoc.v:191281.3-191290.6"
- wire width 24 $1\rm[23:0]
- attribute \src "libresoc.v:191291.3-191300.6"
- wire width 24 $1\svp64_rm[23:0]
- attribute \src "libresoc.v:191280.17-191280.110"
- wire $and$libresoc.v:191280$13405_Y
- attribute \src "libresoc.v:191278.17-191278.114"
- wire $eq$libresoc.v:191278$13403_Y
- attribute \src "libresoc.v:191279.17-191279.113"
- wire $eq$libresoc.v:191279$13404_Y
- attribute \src "libresoc.v:191277.17-191277.215"
- wire width 32 $ternary$libresoc.v:191277$13402_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:35"
- wire width 32 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:42"
- wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43"
- wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43"
- wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:21"
- wire input 1 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:39"
- wire width 2 \ident
- attribute \src "libresoc.v:191251.7-191251.15"
- wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:19"
- wire output 3 \is_svp64_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:38"
- wire width 6 \major
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:17"
- wire width 32 \opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:18"
- wire width 32 input 4 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:48"
- wire width 24 \rm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:20"
- wire width 24 output 2 \svp64_rm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43"
- cell $and $and$libresoc.v:191280$13405
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \$3
- connect \B \$5
- connect \Y $and$libresoc.v:191280$13405_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:42"
- cell $eq $eq$libresoc.v:191278$13403
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 1
- connect \A \major
- connect \B 6'000001
- connect \Y $eq$libresoc.v:191278$13403_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43"
- cell $eq $eq$libresoc.v:191279$13404
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A \ident
- connect \B 2'11
- connect \Y $eq$libresoc.v:191279$13404_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:35"
- cell $mux $ternary$libresoc.v:191277$13402
- parameter \WIDTH 32
- connect \A \raw_opcode_in
- connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
- connect \S \bigendian
- connect \Y $ternary$libresoc.v:191277$13402_Y
- end
- attribute \src "libresoc.v:191251.7-191251.20"
- process $proc$libresoc.v:191251$13408
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:191281.3-191290.6"
- process $proc$libresoc.v:191281$13406
- assign { } { }
- assign { } { }
- assign $0\rm[23:0] $1\rm[23:0]
- attribute \src "libresoc.v:191282.5-191282.29"
- switch \initial
- attribute \src "libresoc.v:191282.9-191282.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:46"
- switch \is_svp64_mode
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\rm[23:0] { \opcode_in [25] \opcode_in [23] \opcode_in [21:0] }
- case
- assign $1\rm[23:0] 24'000000000000000000000000
- end
- sync always
- update \rm $0\rm[23:0]
- end
- attribute \src "libresoc.v:191291.3-191300.6"
- process $proc$libresoc.v:191291$13407
- assign { } { }
- assign { } { }
- assign $0\svp64_rm[23:0] $1\svp64_rm[23:0]
- attribute \src "libresoc.v:191292.5-191292.29"
- switch \initial
- attribute \src "libresoc.v:191292.9-191292.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:46"
- switch \is_svp64_mode
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\svp64_rm[23:0] \rm
- case
- assign $1\svp64_rm[23:0] 24'000000000000000000000000
- end
- sync always
- update \svp64_rm $0\svp64_rm[23:0]
- end
- connect \$1 $ternary$libresoc.v:191277$13402_Y
- connect \$3 $eq$libresoc.v:191278$13403_Y
- connect \$5 $eq$libresoc.v:191279$13404_Y
- connect \$7 $and$libresoc.v:191280$13405_Y
- connect \is_svp64_mode \$7
- connect \ident { \opcode_in [24] \opcode_in [22] }
- connect \major \opcode_in [31:26]
- connect \opcode_in \$1
-end
-attribute \src "libresoc.v:191310.1-192547.10"
+attribute \src "libresoc.v:188424.1-189530.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
wire output 6 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire input 8 \TAP_bus__tms
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133"
wire output 5 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 404 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
- wire width 2 input 406 \clk_sel_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 368 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132"
wire input 4 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 344 \dbus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire input 334 \ibus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire output 391 \icp_wb__ack
+ wire output 355 \icp_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 28 input 385 \icp_wb__adr
+ wire width 28 input 349 \icp_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 389 \icp_wb__cyc
+ wire input 353 \icp_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 output 387 \icp_wb__dat_r
+ wire width 32 output 351 \icp_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 input 386 \icp_wb__dat_w
+ wire width 32 input 350 \icp_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 393 \icp_wb__err
+ wire input 357 \icp_wb__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 4 input 388 \icp_wb__sel
+ wire width 4 input 352 \icp_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 390 \icp_wb__stb
+ wire input 354 \icp_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 392 \icp_wb__we
+ wire input 356 \icp_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire output 400 \ics_wb__ack
+ wire output 364 \ics_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 28 input 394 \ics_wb__adr
+ wire width 28 input 358 \ics_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 398 \ics_wb__cyc
+ wire input 362 \ics_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 output 396 \ics_wb__dat_r
+ wire width 32 output 360 \ics_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 input 395 \ics_wb__dat_w
+ wire width 32 input 359 \ics_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 402 \ics_wb__err
+ wire input 366 \ics_wb__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 4 input 397 \ics_wb__sel
+ wire width 4 input 361 \ics_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 399 \ics_wb__stb
+ wire input 363 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 401 \ics_wb__we
+ wire input 365 \ics_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
- wire width 16 input 403 \int_level_i
+ wire width 16 input 367 \int_level_i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire input 17 \jtag_wb__ack
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire output 15 \jtag_wb__stb
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire output 16 \jtag_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:134"
wire input 3 \memerr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 121 \mspi0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 142 \mtwi_sda__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 64 input 409 \pc_i
+ wire width 64 input 370 \pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 1 \pc_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129"
wire width 64 output 2 \pc_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717"
- wire output 407 \pll_18_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
- wire \pll_clk_24_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
- wire \pll_clk_pll_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
- wire output 408 \pll_lck_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
- wire \pll_pll_18_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
- wire \pllclk_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
- wire \pllclk_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 145 \pwm_0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 147 \pwm_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 148 \pwm_1__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 405 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 369 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 155 \sd0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 263 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 264 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 356 \sram4k_0_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 349 \sram4k_0_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 353 \sram4k_0_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 351 \sram4k_0_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 350 \sram4k_0_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 357 \sram4k_0_wb__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 352 \sram4k_0_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 354 \sram4k_0_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 355 \sram4k_0_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 365 \sram4k_1_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 358 \sram4k_1_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 362 \sram4k_1_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 360 \sram4k_1_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 359 \sram4k_1_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 366 \sram4k_1_wb__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 361 \sram4k_1_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 363 \sram4k_1_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 364 \sram4k_1_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 374 \sram4k_2_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 367 \sram4k_2_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 371 \sram4k_2_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 369 \sram4k_2_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 368 \sram4k_2_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 375 \sram4k_2_wb__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 370 \sram4k_2_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 372 \sram4k_2_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 373 \sram4k_2_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 383 \sram4k_3_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 376 \sram4k_3_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 380 \sram4k_3_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 378 \sram4k_3_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 377 \sram4k_3_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 384 \sram4k_3_wb__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 379 \sram4k_3_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 381 \sram4k_3_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 382 \sram4k_3_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire \ti_coresync_clk
attribute \module_not_derived 1
- attribute \src "libresoc.v:192141.7-192147.4"
- cell \pll \pll
- connect \clk_24_i \pll_clk_24_i
- connect \clk_pll_o \pll_clk_pll_o
- connect \clk_sel_i \clk_sel_i
- connect \pll_18_o \pll_pll_18_o
- connect \pll_lck_o \pll_lck_o
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:192148.6-192541.4"
+ attribute \src "libresoc.v:189167.6-189528.4"
cell \ti \ti
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o
connect \sdr_we_n__core__o \sdr_we_n__core__o
connect \sdr_we_n__pad__o \sdr_we_n__pad__o
- connect \sram4k_0_wb__ack \sram4k_0_wb__ack
- connect \sram4k_0_wb__adr \sram4k_0_wb__adr
- connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc
- connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r
- connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w
- connect \sram4k_0_wb__sel \sram4k_0_wb__sel
- connect \sram4k_0_wb__stb \sram4k_0_wb__stb
- connect \sram4k_0_wb__we \sram4k_0_wb__we
- connect \sram4k_1_wb__ack \sram4k_1_wb__ack
- connect \sram4k_1_wb__adr \sram4k_1_wb__adr
- connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc
- connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r
- connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w
- connect \sram4k_1_wb__sel \sram4k_1_wb__sel
- connect \sram4k_1_wb__stb \sram4k_1_wb__stb
- connect \sram4k_1_wb__we \sram4k_1_wb__we
- connect \sram4k_2_wb__ack \sram4k_2_wb__ack
- connect \sram4k_2_wb__adr \sram4k_2_wb__adr
- connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc
- connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r
- connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w
- connect \sram4k_2_wb__sel \sram4k_2_wb__sel
- connect \sram4k_2_wb__stb \sram4k_2_wb__stb
- connect \sram4k_2_wb__we \sram4k_2_wb__we
- connect \sram4k_3_wb__ack \sram4k_3_wb__ack
- connect \sram4k_3_wb__adr \sram4k_3_wb__adr
- connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc
- connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r
- connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w
- connect \sram4k_3_wb__sel \sram4k_3_wb__sel
- connect \sram4k_3_wb__stb \sram4k_3_wb__stb
- connect \sram4k_3_wb__we \sram4k_3_wb__we
- end
- connect \ti_coresync_clk \pll_clk_pll_o
- connect \pllclk_rst \rst
- connect \pll_18_o \pll_pll_18_o
- connect \pll_clk_24_i \clk
- connect \pllclk_clk \pll_clk_pll_o
+ end
+ connect \ti_coresync_clk \clk
end
-attribute \src "libresoc.v:192551.1-197402.10"
+attribute \src "libresoc.v:189534.1-194513.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti"
attribute \generator "nMigen"
module \ti
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $0\core_asmcode$next[7:0]$13879
- attribute \src "libresoc.v:195037.3-195038.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $0\core_asmcode$next[7:0]$13738
+ attribute \src "libresoc.v:192025.3-192026.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $0\core_bigendian_i$10$next[0:0]$13668
- attribute \src "libresoc.v:195187.3-195188.57"
- wire $0\core_bigendian_i$10[0:0]$13596
- attribute \src "libresoc.v:192732.7-192732.35"
- wire $0\core_bigendian_i$10[0:0]$14204
- attribute \src "libresoc.v:196509.3-196521.6"
+ attribute \src "libresoc.v:192862.3-192886.6"
+ wire $0\core_bigendian_i$10$next[0:0]$13542
+ attribute \src "libresoc.v:192137.3-192138.57"
+ wire $0\core_bigendian_i$10[0:0]$13454
+ attribute \src "libresoc.v:189805.7-189805.35"
+ wire $0\core_bigendian_i$10[0:0]$13951
+ attribute \src "libresoc.v:193381.3-193393.6"
wire width 3 $0\core_cia__ren[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $0\core_core_core_cia$next[63:0]$13880
- attribute \src "libresoc.v:195111.3-195112.53"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $0\core_core_core_cia$next[63:0]$13739
+ attribute \src "libresoc.v:192101.3-192102.53"
wire width 64 $0\core_core_core_cia[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $0\core_core_core_cr_rd$next[7:0]$13881
- attribute \src "libresoc.v:195155.3-195156.57"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $0\core_core_core_cr_rd$next[7:0]$13740
+ attribute \src "libresoc.v:192145.3-192146.57"
wire width 8 $0\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_cr_rd_ok$next[0:0]$13882
- attribute \src "libresoc.v:195157.3-195158.63"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_cr_rd_ok$next[0:0]$13741
+ attribute \src "libresoc.v:192147.3-192148.63"
wire $0\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $0\core_core_core_cr_wr$next[7:0]$13883
- attribute \src "libresoc.v:195159.3-195160.57"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $0\core_core_core_cr_wr$next[7:0]$13742
+ attribute \src "libresoc.v:192149.3-192150.57"
wire width 8 $0\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$3$next[0:0]$13884
- attribute \src "libresoc.v:195137.3-195138.75"
- wire $0\core_core_core_exc_$signal$3[0:0]$13564
- attribute \src "libresoc.v:192758.7-192758.44"
- wire $0\core_core_core_exc_$signal$3[0:0]$14212
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$4$next[0:0]$13885
- attribute \src "libresoc.v:195139.3-195140.75"
- wire $0\core_core_core_exc_$signal$4[0:0]$13566
- attribute \src "libresoc.v:192762.7-192762.44"
- wire $0\core_core_core_exc_$signal$4[0:0]$14214
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$5$next[0:0]$13886
- attribute \src "libresoc.v:195141.3-195142.75"
- wire $0\core_core_core_exc_$signal$5[0:0]$13568
- attribute \src "libresoc.v:192766.7-192766.44"
- wire $0\core_core_core_exc_$signal$5[0:0]$14216
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$6$next[0:0]$13887
- attribute \src "libresoc.v:195145.3-195146.75"
- wire $0\core_core_core_exc_$signal$6[0:0]$13571
- attribute \src "libresoc.v:192770.7-192770.44"
- wire $0\core_core_core_exc_$signal$6[0:0]$14218
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$7$next[0:0]$13888
- attribute \src "libresoc.v:195147.3-195148.75"
- wire $0\core_core_core_exc_$signal$7[0:0]$13573
- attribute \src "libresoc.v:192774.7-192774.44"
- wire $0\core_core_core_exc_$signal$7[0:0]$14220
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$8$next[0:0]$13889
- attribute \src "libresoc.v:195149.3-195150.75"
- wire $0\core_core_core_exc_$signal$8[0:0]$13575
- attribute \src "libresoc.v:192778.7-192778.44"
- wire $0\core_core_core_exc_$signal$8[0:0]$14222
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$9$next[0:0]$13890
- attribute \src "libresoc.v:195151.3-195152.75"
- wire $0\core_core_core_exc_$signal$9[0:0]$13577
- attribute \src "libresoc.v:192782.7-192782.44"
- wire $0\core_core_core_exc_$signal$9[0:0]$14224
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_exc_$signal$next[0:0]$13891
- attribute \src "libresoc.v:195135.3-195136.71"
- wire $0\core_core_core_exc_$signal[0:0]$13562
- attribute \src "libresoc.v:192756.7-192756.42"
- wire $0\core_core_core_exc_$signal[0:0]$14210
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $0\core_core_core_fn_unit$next[12:0]$13892
- attribute \src "libresoc.v:195117.3-195118.61"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$3$next[0:0]$13743
+ attribute \src "libresoc.v:192127.3-192128.75"
+ wire $0\core_core_core_exc_$signal$3[0:0]$13444
+ attribute \src "libresoc.v:189831.7-189831.44"
+ wire $0\core_core_core_exc_$signal$3[0:0]$13959
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$4$next[0:0]$13744
+ attribute \src "libresoc.v:192129.3-192130.75"
+ wire $0\core_core_core_exc_$signal$4[0:0]$13446
+ attribute \src "libresoc.v:189835.7-189835.44"
+ wire $0\core_core_core_exc_$signal$4[0:0]$13961
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$5$next[0:0]$13745
+ attribute \src "libresoc.v:192131.3-192132.75"
+ wire $0\core_core_core_exc_$signal$5[0:0]$13448
+ attribute \src "libresoc.v:189839.7-189839.44"
+ wire $0\core_core_core_exc_$signal$5[0:0]$13963
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$6$next[0:0]$13746
+ attribute \src "libresoc.v:192133.3-192134.75"
+ wire $0\core_core_core_exc_$signal$6[0:0]$13450
+ attribute \src "libresoc.v:189843.7-189843.44"
+ wire $0\core_core_core_exc_$signal$6[0:0]$13965
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$7$next[0:0]$13747
+ attribute \src "libresoc.v:192135.3-192136.75"
+ wire $0\core_core_core_exc_$signal$7[0:0]$13452
+ attribute \src "libresoc.v:189847.7-189847.44"
+ wire $0\core_core_core_exc_$signal$7[0:0]$13967
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$8$next[0:0]$13748
+ attribute \src "libresoc.v:192139.3-192140.75"
+ wire $0\core_core_core_exc_$signal$8[0:0]$13456
+ attribute \src "libresoc.v:189851.7-189851.44"
+ wire $0\core_core_core_exc_$signal$8[0:0]$13969
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$9$next[0:0]$13749
+ attribute \src "libresoc.v:192141.3-192142.75"
+ wire $0\core_core_core_exc_$signal$9[0:0]$13458
+ attribute \src "libresoc.v:189855.7-189855.44"
+ wire $0\core_core_core_exc_$signal$9[0:0]$13971
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_exc_$signal$next[0:0]$13750
+ attribute \src "libresoc.v:192125.3-192126.71"
+ wire $0\core_core_core_exc_$signal[0:0]$13442
+ attribute \src "libresoc.v:189829.7-189829.42"
+ wire $0\core_core_core_exc_$signal[0:0]$13957
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $0\core_core_core_fn_unit$next[12:0]$13751
+ attribute \src "libresoc.v:192107.3-192108.61"
wire width 13 $0\core_core_core_fn_unit[12:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 2 $0\core_core_core_input_carry$next[1:0]$13893
- attribute \src "libresoc.v:195131.3-195132.69"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 2 $0\core_core_core_input_carry$next[1:0]$13752
+ attribute \src "libresoc.v:192121.3-192122.69"
wire width 2 $0\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 32 $0\core_core_core_insn$next[31:0]$13894
- attribute \src "libresoc.v:195113.3-195114.55"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 32 $0\core_core_core_insn$next[31:0]$13753
+ attribute \src "libresoc.v:192103.3-192104.55"
wire width 32 $0\core_core_core_insn[31:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_core_insn_type$next[6:0]$13895
- attribute \src "libresoc.v:195115.3-195116.65"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_core_insn_type$next[6:0]$13754
+ attribute \src "libresoc.v:192105.3-192106.65"
wire width 7 $0\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_is_32bit$next[0:0]$13896
- attribute \src "libresoc.v:195163.3-195164.63"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_is_32bit$next[0:0]$13755
+ attribute \src "libresoc.v:192153.3-192154.63"
wire $0\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $0\core_core_core_msr$next[63:0]$13897
- attribute \src "libresoc.v:195109.3-195110.53"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $0\core_core_core_msr$next[63:0]$13756
+ attribute \src "libresoc.v:192099.3-192100.53"
wire width 64 $0\core_core_core_msr[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_oe$next[0:0]$13898
- attribute \src "libresoc.v:195127.3-195128.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_oe$next[0:0]$13757
+ attribute \src "libresoc.v:192117.3-192118.51"
wire $0\core_core_core_oe[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_oe_ok$next[0:0]$13899
- attribute \src "libresoc.v:195129.3-195130.57"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_oe_ok$next[0:0]$13758
+ attribute \src "libresoc.v:192119.3-192120.57"
wire $0\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_rc$next[0:0]$13900
- attribute \src "libresoc.v:195123.3-195124.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_rc$next[0:0]$13759
+ attribute \src "libresoc.v:192111.3-192112.51"
wire $0\core_core_core_rc[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_core_rc_ok$next[0:0]$13901
- attribute \src "libresoc.v:195125.3-195126.57"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_core_rc_ok$next[0:0]$13760
+ attribute \src "libresoc.v:192113.3-192114.57"
wire $0\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $0\core_core_core_trapaddr$next[12:0]$13902
- attribute \src "libresoc.v:195153.3-195154.63"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $0\core_core_core_trapaddr$next[12:0]$13761
+ attribute \src "libresoc.v:192143.3-192144.63"
wire width 13 $0\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $0\core_core_core_traptype$next[7:0]$13903
- attribute \src "libresoc.v:195133.3-195134.63"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $0\core_core_core_traptype$next[7:0]$13762
+ attribute \src "libresoc.v:192123.3-192124.63"
wire width 8 $0\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_cr_in1$next[6:0]$13904
- attribute \src "libresoc.v:195091.3-195092.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_cr_in1$next[6:0]$13763
+ attribute \src "libresoc.v:192081.3-192082.49"
wire width 7 $0\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_cr_in1_ok$next[0:0]$13905
- attribute \src "libresoc.v:195093.3-195094.55"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_cr_in1_ok$next[0:0]$13764
+ attribute \src "libresoc.v:192083.3-192084.55"
wire $0\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_cr_in2$1$next[6:0]$13906
- attribute \src "libresoc.v:195101.3-195102.55"
- wire width 7 $0\core_core_cr_in2$1[6:0]$13543
- attribute \src "libresoc.v:192938.13-192938.41"
- wire width 7 $0\core_core_cr_in2$1[6:0]$14241
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_cr_in2$next[6:0]$13907
- attribute \src "libresoc.v:195095.3-195096.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_cr_in2$1$next[6:0]$13765
+ attribute \src "libresoc.v:192089.3-192090.55"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$13422
+ attribute \src "libresoc.v:190011.13-190011.41"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$13988
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_cr_in2$next[6:0]$13766
+ attribute \src "libresoc.v:192085.3-192086.49"
wire width 7 $0\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_cr_in2_ok$2$next[0:0]$13908
- attribute \src "libresoc.v:195103.3-195104.61"
- wire $0\core_core_cr_in2_ok$2[0:0]$13545
- attribute \src "libresoc.v:192946.7-192946.37"
- wire $0\core_core_cr_in2_ok$2[0:0]$14244
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_cr_in2_ok$next[0:0]$13909
- attribute \src "libresoc.v:195097.3-195098.55"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_cr_in2_ok$2$next[0:0]$13767
+ attribute \src "libresoc.v:192091.3-192092.61"
+ wire $0\core_core_cr_in2_ok$2[0:0]$13424
+ attribute \src "libresoc.v:190019.7-190019.37"
+ wire $0\core_core_cr_in2_ok$2[0:0]$13991
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_cr_in2_ok$next[0:0]$13768
+ attribute \src "libresoc.v:192087.3-192088.55"
wire $0\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_cr_out$next[6:0]$13910
- attribute \src "libresoc.v:195105.3-195106.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_cr_out$next[6:0]$13769
+ attribute \src "libresoc.v:192095.3-192096.49"
wire width 7 $0\core_core_cr_out[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_cr_wr_ok$next[0:0]$13911
- attribute \src "libresoc.v:195161.3-195162.53"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_cr_wr_ok$next[0:0]$13770
+ attribute \src "libresoc.v:192151.3-192152.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $0\core_core_dststep$next[6:0]$13620
- attribute \src "libresoc.v:195027.3-195028.51"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $0\core_core_dststep$next[6:0]$13496
+ attribute \src "libresoc.v:192017.3-192018.51"
wire width 7 $0\core_core_dststep[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_ea$next[6:0]$13912
- attribute \src "libresoc.v:195043.3-195044.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_ea$next[6:0]$13771
+ attribute \src "libresoc.v:192033.3-192034.41"
wire width 7 $0\core_core_ea[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $0\core_core_fast1$next[2:0]$13913
- attribute \src "libresoc.v:195073.3-195074.47"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $0\core_core_fast1$next[2:0]$13772
+ attribute \src "libresoc.v:192063.3-192064.47"
wire width 3 $0\core_core_fast1[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_fast1_ok$next[0:0]$13914
- attribute \src "libresoc.v:195075.3-195076.53"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_fast1_ok$next[0:0]$13773
+ attribute \src "libresoc.v:192065.3-192066.53"
wire $0\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $0\core_core_fast2$next[2:0]$13915
- attribute \src "libresoc.v:195079.3-195080.47"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $0\core_core_fast2$next[2:0]$13774
+ attribute \src "libresoc.v:192067.3-192068.47"
wire width 3 $0\core_core_fast2[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_fast2_ok$next[0:0]$13916
- attribute \src "libresoc.v:195081.3-195082.53"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_fast2_ok$next[0:0]$13775
+ attribute \src "libresoc.v:192069.3-192070.53"
wire $0\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $0\core_core_fasto1$next[2:0]$13917
- attribute \src "libresoc.v:195083.3-195084.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $0\core_core_fasto1$next[2:0]$13776
+ attribute \src "libresoc.v:192073.3-192074.49"
wire width 3 $0\core_core_fasto1[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $0\core_core_fasto2$next[2:0]$13918
- attribute \src "libresoc.v:195087.3-195088.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $0\core_core_fasto2$next[2:0]$13777
+ attribute \src "libresoc.v:192077.3-192078.49"
wire width 3 $0\core_core_fasto2[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_lk$next[0:0]$13919
- attribute \src "libresoc.v:195119.3-195120.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_lk$next[0:0]$13778
+ attribute \src "libresoc.v:192109.3-192110.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $0\core_core_maxvl$next[6:0]$13621
- attribute \src "libresoc.v:195035.3-195036.47"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $0\core_core_maxvl$next[6:0]$13497
+ attribute \src "libresoc.v:192023.3-192024.47"
wire width 7 $0\core_core_maxvl[6:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $0\core_core_pc$next[63:0]$13622
- attribute \src "libresoc.v:195013.3-195014.41"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $0\core_core_pc$next[63:0]$13498
+ attribute \src "libresoc.v:192181.3-192182.41"
wire width 64 $0\core_core_pc[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_reg1$next[6:0]$13920
- attribute \src "libresoc.v:195047.3-195048.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_reg1$next[6:0]$13779
+ attribute \src "libresoc.v:192037.3-192038.45"
wire width 7 $0\core_core_reg1[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_reg1_ok$next[0:0]$13921
- attribute \src "libresoc.v:195049.3-195050.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_reg1_ok$next[0:0]$13780
+ attribute \src "libresoc.v:192039.3-192040.51"
wire $0\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_reg2$next[6:0]$13922
- attribute \src "libresoc.v:195051.3-195052.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_reg2$next[6:0]$13781
+ attribute \src "libresoc.v:192041.3-192042.45"
wire width 7 $0\core_core_reg2[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_reg2_ok$next[0:0]$13923
- attribute \src "libresoc.v:195053.3-195054.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_reg2_ok$next[0:0]$13782
+ attribute \src "libresoc.v:192043.3-192044.51"
wire $0\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_reg3$next[6:0]$13924
- attribute \src "libresoc.v:195057.3-195058.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_reg3$next[6:0]$13783
+ attribute \src "libresoc.v:192045.3-192046.45"
wire width 7 $0\core_core_reg3[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_reg3_ok$next[0:0]$13925
- attribute \src "libresoc.v:195059.3-195060.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_reg3_ok$next[0:0]$13784
+ attribute \src "libresoc.v:192047.3-192048.51"
wire $0\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $0\core_core_rego$next[6:0]$13926
- attribute \src "libresoc.v:195039.3-195040.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $0\core_core_rego$next[6:0]$13785
+ attribute \src "libresoc.v:192029.3-192030.45"
wire width 7 $0\core_core_rego[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $0\core_core_spr1$next[9:0]$13927
- attribute \src "libresoc.v:195065.3-195066.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $0\core_core_spr1$next[9:0]$13786
+ attribute \src "libresoc.v:192055.3-192056.45"
wire width 10 $0\core_core_spr1[9:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_core_spr1_ok$next[0:0]$13928
- attribute \src "libresoc.v:195067.3-195068.51"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_core_spr1_ok$next[0:0]$13787
+ attribute \src "libresoc.v:192057.3-192058.51"
wire $0\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $0\core_core_spro$next[9:0]$13929
- attribute \src "libresoc.v:195061.3-195062.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $0\core_core_spro$next[9:0]$13788
+ attribute \src "libresoc.v:192051.3-192052.45"
wire width 10 $0\core_core_spro[9:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $0\core_core_srcstep$next[6:0]$13623
- attribute \src "libresoc.v:195029.3-195030.51"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $0\core_core_srcstep$next[6:0]$13499
+ attribute \src "libresoc.v:192019.3-192020.51"
wire width 7 $0\core_core_srcstep[6:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $0\core_core_subvl$next[1:0]$13624
- attribute \src "libresoc.v:195025.3-195026.47"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $0\core_core_subvl$next[1:0]$13500
+ attribute \src "libresoc.v:192015.3-192016.47"
wire width 2 $0\core_core_subvl[1:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $0\core_core_svstep$next[1:0]$13625
- attribute \src "libresoc.v:195023.3-195024.49"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $0\core_core_svstep$next[1:0]$13501
+ attribute \src "libresoc.v:192013.3-192014.49"
wire width 2 $0\core_core_svstep[1:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $0\core_core_vl$next[6:0]$13626
- attribute \src "libresoc.v:195031.3-195032.41"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $0\core_core_vl$next[6:0]$13502
+ attribute \src "libresoc.v:192021.3-192022.41"
wire width 7 $0\core_core_vl[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $0\core_core_xer_in$next[2:0]$13930
- attribute \src "libresoc.v:195069.3-195070.49"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $0\core_core_xer_in$next[2:0]$13789
+ attribute \src "libresoc.v:192059.3-192060.49"
wire width 3 $0\core_core_xer_in[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_cr_out_ok$next[0:0]$13931
- attribute \src "libresoc.v:195107.3-195108.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_cr_out_ok$next[0:0]$13790
+ attribute \src "libresoc.v:192097.3-192098.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:196020.3-196029.6"
- wire width 64 $0\core_data_i$12[63:0]$13680
- attribute \src "libresoc.v:196595.3-196620.6"
+ attribute \src "libresoc.v:192966.3-192975.6"
+ wire width 64 $0\core_data_i$12[63:0]$13554
+ attribute \src "libresoc.v:193500.3-193567.6"
wire width 64 $0\core_data_i[63:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $0\core_dec$next[63:0]$13627
- attribute \src "libresoc.v:195021.3-195022.33"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $0\core_dec$next[63:0]$13503
+ attribute \src "libresoc.v:192011.3-192012.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:196207.3-196216.6"
+ attribute \src "libresoc.v:193079.3-193088.6"
wire width 5 $0\core_dmi__addr[4:0]
- attribute \src "libresoc.v:196217.3-196226.6"
+ attribute \src "libresoc.v:193089.3-193098.6"
wire $0\core_dmi__ren[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_ea_ok$next[0:0]$13932
- attribute \src "libresoc.v:195045.3-195046.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_ea_ok$next[0:0]$13791
+ attribute \src "libresoc.v:192035.3-192036.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire $0\core_eint$next[0:0]$13628
- attribute \src "libresoc.v:195019.3-195020.35"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire $0\core_eint$next[0:0]$13504
+ attribute \src "libresoc.v:192009.3-192010.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_fasto1_ok$next[0:0]$13933
- attribute \src "libresoc.v:195085.3-195086.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_fasto1_ok$next[0:0]$13792
+ attribute \src "libresoc.v:192075.3-192076.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_fasto2_ok$next[0:0]$13934
- attribute \src "libresoc.v:195089.3-195090.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_fasto2_ok$next[0:0]$13793
+ attribute \src "libresoc.v:192079.3-192080.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:196256.3-196265.6"
+ attribute \src "libresoc.v:193128.3-193137.6"
wire width 8 $0\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:196295.3-196304.6"
+ attribute \src "libresoc.v:193167.3-193176.6"
wire width 3 $0\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:196403.3-196417.6"
- wire width 3 $0\core_issue__addr$13[2:0]$13733
- attribute \src "libresoc.v:196334.3-196348.6"
+ attribute \src "libresoc.v:193275.3-193289.6"
+ wire width 3 $0\core_issue__addr$13[2:0]$13594
+ attribute \src "libresoc.v:193206.3-193220.6"
wire width 3 $0\core_issue__addr[2:0]
- attribute \src "libresoc.v:196433.3-196447.6"
+ attribute \src "libresoc.v:193305.3-193319.6"
wire width 64 $0\core_issue__data_i[63:0]
- attribute \src "libresoc.v:196349.3-196363.6"
+ attribute \src "libresoc.v:193221.3-193235.6"
wire $0\core_issue__ren[0:0]
- attribute \src "libresoc.v:196418.3-196432.6"
+ attribute \src "libresoc.v:193290.3-193304.6"
wire $0\core_issue__wen[0:0]
- attribute \src "libresoc.v:196066.3-196081.6"
+ attribute \src "libresoc.v:193012.3-193027.6"
wire $0\core_issue_i[0:0]
- attribute \src "libresoc.v:196041.3-196065.6"
+ attribute \src "libresoc.v:192987.3-193011.6"
wire $0\core_ivalid_i[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $0\core_msr$next[63:0]$13629
- attribute \src "libresoc.v:195017.3-195018.33"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $0\core_msr$next[63:0]$13505
+ attribute \src "libresoc.v:191999.3-192000.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:196621.3-196636.6"
+ attribute \src "libresoc.v:193568.3-193583.6"
wire width 3 $0\core_msr__ren[2:0]
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $0\core_raw_insn_i$next[31:0]$13661
- attribute \src "libresoc.v:194991.3-194992.47"
+ attribute \src "libresoc.v:192841.3-192861.6"
+ wire width 32 $0\core_raw_insn_i$next[31:0]$13537
+ attribute \src "libresoc.v:192159.3-192160.47"
wire width 32 $0\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_rego_ok$next[0:0]$13935
- attribute \src "libresoc.v:195041.3-195042.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_rego_ok$next[0:0]$13794
+ attribute \src "libresoc.v:192031.3-192032.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_spro_ok$next[0:0]$13936
- attribute \src "libresoc.v:195063.3-195064.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_spro_ok$next[0:0]$13795
+ attribute \src "libresoc.v:192053.3-192054.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:197169.3-197199.6"
+ attribute \src "libresoc.v:194091.3-194121.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:196547.3-196559.6"
+ attribute \src "libresoc.v:193419.3-193431.6"
wire width 3 $0\core_sv__ren[2:0]
- attribute \src "libresoc.v:196010.3-196019.6"
- wire width 3 $0\core_wen$11[2:0]$13677
- attribute \src "libresoc.v:196569.3-196594.6"
+ attribute \src "libresoc.v:192956.3-192965.6"
+ wire width 3 $0\core_wen$11[2:0]$13551
+ attribute \src "libresoc.v:193432.3-193499.6"
wire width 3 $0\core_wen[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $0\core_xer_out$next[0:0]$13937
- attribute \src "libresoc.v:195071.3-195072.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $0\core_xer_out$next[0:0]$13796
+ attribute \src "libresoc.v:192061.3-192062.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:194997.3-194998.43"
+ attribute \src "libresoc.v:192193.3-192194.43"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $0\cur_cur_dststep$next[6:0]$13774
- attribute \src "libresoc.v:195197.3-195198.47"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $0\cur_cur_dststep$next[6:0]$13635
+ attribute \src "libresoc.v:192177.3-192178.47"
wire width 7 $0\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $0\cur_cur_maxvl$next[6:0]$13775
- attribute \src "libresoc.v:195203.3-195204.43"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $0\cur_cur_maxvl$next[6:0]$13636
+ attribute \src "libresoc.v:192185.3-192186.43"
wire width 7 $0\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $0\cur_cur_subvl$next[1:0]$13776
- attribute \src "libresoc.v:195195.3-195196.43"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $0\cur_cur_srcstep$next[6:0]$13637
+ attribute \src "libresoc.v:192179.3-192180.47"
+ wire width 7 $0\cur_cur_srcstep[6:0]
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $0\cur_cur_subvl$next[1:0]$13638
+ attribute \src "libresoc.v:192175.3-192176.43"
wire width 2 $0\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $0\cur_cur_svstep$next[1:0]$13777
- attribute \src "libresoc.v:195193.3-195194.45"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $0\cur_cur_svstep$next[1:0]$13639
+ attribute \src "libresoc.v:192173.3-192174.45"
wire width 2 $0\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $0\cur_cur_vl$next[6:0]$13778
- attribute \src "libresoc.v:195201.3-195202.37"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $0\cur_cur_vl$next[6:0]$13640
+ attribute \src "libresoc.v:192183.3-192184.37"
wire width 7 $0\cur_cur_vl[6:0]
- attribute \src "libresoc.v:196266.3-196274.6"
- wire $0\d_cr_delay$next[0:0]$13715
- attribute \src "libresoc.v:195077.3-195078.37"
+ attribute \src "libresoc.v:193138.3-193146.6"
+ wire $0\d_cr_delay$next[0:0]$13576
+ attribute \src "libresoc.v:192071.3-192072.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:196227.3-196235.6"
- wire $0\d_reg_delay$next[0:0]$13709
- attribute \src "libresoc.v:195099.3-195100.39"
+ attribute \src "libresoc.v:193099.3-193107.6"
+ wire $0\d_reg_delay$next[0:0]$13570
+ attribute \src "libresoc.v:192093.3-192094.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:196305.3-196313.6"
- wire $0\d_xer_delay$next[0:0]$13721
- attribute \src "libresoc.v:195055.3-195056.39"
+ attribute \src "libresoc.v:193177.3-193185.6"
+ wire $0\d_xer_delay$next[0:0]$13582
+ attribute \src "libresoc.v:192049.3-192050.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:197200.3-197230.6"
+ attribute \src "libresoc.v:194122.3-194152.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:196285.3-196294.6"
+ attribute \src "libresoc.v:193157.3-193166.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:196275.3-196284.6"
+ attribute \src "libresoc.v:193147.3-193156.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:196246.3-196255.6"
+ attribute \src "libresoc.v:193118.3-193127.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:196236.3-196245.6"
+ attribute \src "libresoc.v:193108.3-193117.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:196324.3-196333.6"
+ attribute \src "libresoc.v:193196.3-193205.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:196314.3-196323.6"
+ attribute \src "libresoc.v:193186.3-193195.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:195839.3-195847.6"
- wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13608
- attribute \src "libresoc.v:195015.3-195016.45"
+ attribute \src "libresoc.v:192778.3-192786.6"
+ wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13490
+ attribute \src "libresoc.v:192007.3-192008.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:196560.3-196568.6"
- wire width 64 $0\dbg_dmi_din$next[63:0]$13756
- attribute \src "libresoc.v:195007.3-195008.39"
+ attribute \src "libresoc.v:193584.3-193592.6"
+ wire width 64 $0\dbg_dmi_din$next[63:0]$13620
+ attribute \src "libresoc.v:192001.3-192002.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:195848.3-195856.6"
- wire $0\dbg_dmi_req_i$next[0:0]$13611
- attribute \src "libresoc.v:195011.3-195012.43"
+ attribute \src "libresoc.v:192787.3-192795.6"
+ wire $0\dbg_dmi_req_i$next[0:0]$13493
+ attribute \src "libresoc.v:192005.3-192006.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:196475.3-196483.6"
- wire $0\dbg_dmi_we_i$next[0:0]$13743
- attribute \src "libresoc.v:195009.3-195010.41"
+ attribute \src "libresoc.v:193347.3-193355.6"
+ wire $0\dbg_dmi_we_i$next[0:0]$13604
+ attribute \src "libresoc.v:192003.3-192004.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $0\dec2_cur_cur_srcstep$next[6:0]$13779
- attribute \src "libresoc.v:195199.3-195200.57"
- wire width 7 $0\dec2_cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:196448.3-196463.6"
- wire width 64 $0\dec2_cur_dec$next[63:0]$13738
- attribute \src "libresoc.v:194989.3-194990.41"
+ attribute \src "libresoc.v:193320.3-193335.6"
+ wire width 64 $0\dec2_cur_dec$next[63:0]$13599
+ attribute \src "libresoc.v:191997.3-191998.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:195857.3-195865.6"
- wire $0\dec2_cur_eint$next[0:0]$13614
- attribute \src "libresoc.v:195001.3-195002.43"
+ attribute \src "libresoc.v:194471.3-194479.6"
+ wire $0\dec2_cur_eint$next[0:0]$13943
+ attribute \src "libresoc.v:192197.3-192198.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:196944.3-196964.6"
- wire width 64 $0\dec2_cur_msr$next[63:0]$13823
- attribute \src "libresoc.v:195185.3-195186.41"
+ attribute \src "libresoc.v:193850.3-193870.6"
+ wire width 64 $0\dec2_cur_msr$next[63:0]$13683
+ attribute \src "libresoc.v:192167.3-192168.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:196783.3-196803.6"
- wire width 64 $0\dec2_cur_pc$next[63:0]$13769
- attribute \src "libresoc.v:195205.3-195206.39"
+ attribute \src "libresoc.v:193697.3-193717.6"
+ wire width 64 $0\dec2_cur_pc$next[63:0]$13630
+ attribute \src "libresoc.v:192187.3-192188.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 9 $0\dec2_dec_svp64__extra$next[8:0]$13830
- attribute \src "libresoc.v:195173.3-195174.59"
- wire width 9 $0\dec2_dec_svp64__extra[8:0]
- attribute \src "libresoc.v:195207.3-195208.40"
+ attribute \src "libresoc.v:193890.3-193920.6"
+ wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13692
+ attribute \src "libresoc.v:192163.3-192164.53"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $0\dec_svp64__elwidth$next[1:0]$13831
- attribute \src "libresoc.v:195179.3-195180.53"
- wire width 2 $0\dec_svp64__elwidth[1:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $0\dec_svp64__ewsrc$next[1:0]$13832
- attribute \src "libresoc.v:195177.3-195178.49"
- wire width 2 $0\dec_svp64__ewsrc[1:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 3 $0\dec_svp64__mask$next[2:0]$13833
- attribute \src "libresoc.v:195181.3-195182.47"
- wire width 3 $0\dec_svp64__mask[2:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire $0\dec_svp64__mmode$next[0:0]$13834
- attribute \src "libresoc.v:195183.3-195184.49"
- wire $0\dec_svp64__mmode[0:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 5 $0\dec_svp64__mode$next[4:0]$13835
- attribute \src "libresoc.v:195171.3-195172.47"
- wire width 5 $0\dec_svp64__mode[4:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $0\dec_svp64__subvl$next[1:0]$13836
- attribute \src "libresoc.v:195175.3-195176.49"
- wire width 2 $0\dec_svp64__subvl[1:0]
- attribute \src "libresoc.v:195866.3-195875.6"
- wire width 2 $0\delay$next[1:0]$13617
- attribute \src "libresoc.v:194999.3-195000.27"
+ attribute \src "libresoc.v:194480.3-194489.6"
+ wire width 2 $0\delay$next[1:0]$13946
+ attribute \src "libresoc.v:192195.3-192196.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $0\exec_fsm_state$next[0:0]$13686
- attribute \src "libresoc.v:195165.3-195166.45"
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $0\exec_fsm_state$next[0:0]$13560
+ attribute \src "libresoc.v:192115.3-192116.45"
wire $0\exec_fsm_state[0:0]
- attribute \src "libresoc.v:196030.3-196040.6"
+ attribute \src "libresoc.v:192976.3-192986.6"
wire $0\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:195983.3-195993.6"
+ attribute \src "libresoc.v:192887.3-192897.6"
wire $0\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:196191.3-196206.6"
+ attribute \src "libresoc.v:192898.3-192913.6"
wire $0\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:195994.3-196009.6"
+ attribute \src "libresoc.v:193063.3-193078.6"
wire $0\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $0\fetch_fsm_state$next[1:0]$13814
- attribute \src "libresoc.v:195189.3-195190.47"
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $0\fetch_fsm_state$next[1:0]$13675
+ attribute \src "libresoc.v:192169.3-192170.47"
wire width 2 $0\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:197060.3-197095.6"
- wire width 32 $0\fetch_insn_o[31:0]
- attribute \src "libresoc.v:197242.3-197252.6"
+ attribute \src "libresoc.v:194349.3-194359.6"
wire $0\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:197096.3-197106.6"
+ attribute \src "libresoc.v:193921.3-193931.6"
wire $0\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:196646.3-196656.6"
+ attribute \src "libresoc.v:193593.3-193603.6"
wire $0\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:197231.3-197241.6"
+ attribute \src "libresoc.v:193994.3-194009.6"
wire $0\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:196364.3-196391.6"
- wire width 2 $0\fsm_state$next[1:0]$13728
- attribute \src "libresoc.v:195033.3-195034.35"
+ attribute \src "libresoc.v:193236.3-193263.6"
+ wire width 2 $0\fsm_state$next[1:0]$13589
+ attribute \src "libresoc.v:192027.3-192028.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:196657.3-196692.6"
+ attribute \src "libresoc.v:193604.3-193619.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196693.3-196737.6"
+ attribute \src "libresoc.v:193629.3-193662.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
+ attribute \src "libresoc.v:193663.3-193696.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:192552.7-192552.20"
+ attribute \src "libresoc.v:189535.7-189535.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:196175.3-196190.6"
- wire $0\insn_done[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $0\issue_fsm_state$next[2:0]$13865
- attribute \src "libresoc.v:195167.3-195168.47"
+ attribute \src "libresoc.v:192935.3-192955.6"
+ wire $0\is_last[0:0]
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $0\issue_fsm_state$next[2:0]$13700
+ attribute \src "libresoc.v:192161.3-192162.47"
wire width 3 $0\issue_fsm_state[2:0]
- attribute \src "libresoc.v:196637.3-196645.6"
- wire $0\jtag_dmi0__ack_o$next[0:0]$13762
- attribute \src "libresoc.v:195005.3-195006.49"
+ attribute \src "libresoc.v:193620.3-193628.6"
+ wire $0\jtag_dmi0__ack_o$next[0:0]$13625
+ attribute \src "libresoc.v:192201.3-192202.49"
wire $0\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:196843.3-196851.6"
- wire width 64 $0\jtag_dmi0__dout$next[63:0]$13805
- attribute \src "libresoc.v:195003.3-195004.47"
+ attribute \src "libresoc.v:193787.3-193795.6"
+ wire width 64 $0\jtag_dmi0__dout$next[63:0]$13672
+ attribute \src "libresoc.v:192199.3-192200.47"
wire width 64 $0\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:196852.3-196881.6"
- wire $0\msr_read$next[0:0]$13808
- attribute \src "libresoc.v:195191.3-195192.33"
+ attribute \src "libresoc.v:193757.3-193786.6"
+ wire $0\msr_read$next[0:0]$13666
+ attribute \src "libresoc.v:192171.3-192172.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:196392.3-196402.6"
+ attribute \src "libresoc.v:193264.3-193274.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:196464.3-196474.6"
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $0\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $0\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $0\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $0\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $0\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $0\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:193336.3-193346.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:197041.3-197059.6"
- wire width 64 $0\nia$next[63:0]$13859
- attribute \src "libresoc.v:195169.3-195170.23"
+ attribute \src "libresoc.v:192914.3-192934.6"
+ wire width 7 $0\next_srcstep[6:0]
+ attribute \src "libresoc.v:193871.3-193889.6"
+ wire width 64 $0\nia$next[63:0]$13688
+ attribute \src "libresoc.v:192165.3-192166.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:196493.3-196508.6"
+ attribute \src "libresoc.v:193365.3-193380.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:196146.3-196174.6"
- wire $0\pc_changed$next[0:0]$13699
- attribute \src "libresoc.v:195121.3-195122.37"
+ attribute \src "libresoc.v:194153.3-194219.6"
+ wire $0\pc_changed$next[0:0]$13714
+ attribute \src "libresoc.v:192157.3-192158.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:196484.3-196492.6"
- wire $0\pc_ok_delay$next[0:0]$13746
- attribute \src "libresoc.v:194995.3-194996.39"
+ attribute \src "libresoc.v:193356.3-193364.6"
+ wire $0\pc_ok_delay$next[0:0]$13607
+ attribute \src "libresoc.v:192191.3-192192.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:196117.3-196145.6"
- wire $0\sv_changed$next[0:0]$13693
- attribute \src "libresoc.v:195143.3-195144.37"
+ attribute \src "libresoc.v:194282.3-194348.6"
+ wire $0\sv_changed$next[0:0]$13726
+ attribute \src "libresoc.v:192155.3-192156.37"
wire $0\sv_changed[0:0]
- attribute \src "libresoc.v:196984.3-197002.6"
- wire $0\svp64_bigendian[0:0]
- attribute \src "libresoc.v:196965.3-196983.6"
- wire width 32 $0\svp64_raw_opcode_in[31:0]
- attribute \src "libresoc.v:196531.3-196546.6"
+ attribute \src "libresoc.v:193403.3-193418.6"
wire width 64 $0\svstate[63:0]
- attribute \src "libresoc.v:196522.3-196530.6"
- wire $0\svstate_ok_delay$next[0:0]$13751
- attribute \src "libresoc.v:194993.3-194994.49"
+ attribute \src "libresoc.v:193394.3-193402.6"
+ wire $0\svstate_ok_delay$next[0:0]$13612
+ attribute \src "libresoc.v:192189.3-192190.49"
wire $0\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $1\core_asmcode$next[7:0]$13938
- attribute \src "libresoc.v:192726.13-192726.33"
+ attribute \src "libresoc.v:194220.3-194281.6"
+ wire $0\update_svstate[0:0]
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $10\issue_fsm_state$next[2:0]$13710
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $1\core_asmcode$next[7:0]$13797
+ attribute \src "libresoc.v:189799.13-189799.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $1\core_bigendian_i$10$next[0:0]$13669
- attribute \src "libresoc.v:196509.3-196521.6"
+ attribute \src "libresoc.v:192862.3-192886.6"
+ wire $1\core_bigendian_i$10$next[0:0]$13543
+ attribute \src "libresoc.v:193381.3-193393.6"
wire width 3 $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $1\core_core_core_cia$next[63:0]$13939
- attribute \src "libresoc.v:192740.14-192740.55"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $1\core_core_core_cia$next[63:0]$13798
+ attribute \src "libresoc.v:189813.14-189813.55"
wire width 64 $1\core_core_core_cia[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $1\core_core_core_cr_rd$next[7:0]$13940
- attribute \src "libresoc.v:192744.13-192744.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $1\core_core_core_cr_rd$next[7:0]$13799
+ attribute \src "libresoc.v:189817.13-189817.41"
wire width 8 $1\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_cr_rd_ok$next[0:0]$13941
- attribute \src "libresoc.v:192748.7-192748.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_cr_rd_ok$next[0:0]$13800
+ attribute \src "libresoc.v:189821.7-189821.37"
wire $1\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $1\core_core_core_cr_wr$next[7:0]$13942
- attribute \src "libresoc.v:192752.13-192752.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $1\core_core_core_cr_wr$next[7:0]$13801
+ attribute \src "libresoc.v:189825.13-189825.41"
wire width 8 $1\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$3$next[0:0]$13943
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$4$next[0:0]$13944
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$5$next[0:0]$13945
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$6$next[0:0]$13946
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$7$next[0:0]$13947
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$8$next[0:0]$13948
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$9$next[0:0]$13949
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_exc_$signal$next[0:0]$13950
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $1\core_core_core_fn_unit$next[12:0]$13951
- attribute \src "libresoc.v:192802.14-192802.47"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$3$next[0:0]$13802
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$4$next[0:0]$13803
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$5$next[0:0]$13804
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$6$next[0:0]$13805
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$7$next[0:0]$13806
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$8$next[0:0]$13807
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$9$next[0:0]$13808
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_exc_$signal$next[0:0]$13809
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $1\core_core_core_fn_unit$next[12:0]$13810
+ attribute \src "libresoc.v:189875.14-189875.47"
wire width 13 $1\core_core_core_fn_unit[12:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 2 $1\core_core_core_input_carry$next[1:0]$13952
- attribute \src "libresoc.v:192810.13-192810.46"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 2 $1\core_core_core_input_carry$next[1:0]$13811
+ attribute \src "libresoc.v:189883.13-189883.46"
wire width 2 $1\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 32 $1\core_core_core_insn$next[31:0]$13953
- attribute \src "libresoc.v:192814.14-192814.41"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 32 $1\core_core_core_insn$next[31:0]$13812
+ attribute \src "libresoc.v:189887.14-189887.41"
wire width 32 $1\core_core_core_insn[31:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_core_insn_type$next[6:0]$13954
- attribute \src "libresoc.v:192892.13-192892.45"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_core_insn_type$next[6:0]$13813
+ attribute \src "libresoc.v:189965.13-189965.45"
wire width 7 $1\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_is_32bit$next[0:0]$13955
- attribute \src "libresoc.v:192896.7-192896.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_is_32bit$next[0:0]$13814
+ attribute \src "libresoc.v:189969.7-189969.37"
wire $1\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $1\core_core_core_msr$next[63:0]$13956
- attribute \src "libresoc.v:192900.14-192900.55"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $1\core_core_core_msr$next[63:0]$13815
+ attribute \src "libresoc.v:189973.14-189973.55"
wire width 64 $1\core_core_core_msr[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_oe$next[0:0]$13957
- attribute \src "libresoc.v:192904.7-192904.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_oe$next[0:0]$13816
+ attribute \src "libresoc.v:189977.7-189977.31"
wire $1\core_core_core_oe[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_oe_ok$next[0:0]$13958
- attribute \src "libresoc.v:192908.7-192908.34"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_oe_ok$next[0:0]$13817
+ attribute \src "libresoc.v:189981.7-189981.34"
wire $1\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_rc$next[0:0]$13959
- attribute \src "libresoc.v:192912.7-192912.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_rc$next[0:0]$13818
+ attribute \src "libresoc.v:189985.7-189985.31"
wire $1\core_core_core_rc[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_core_rc_ok$next[0:0]$13960
- attribute \src "libresoc.v:192916.7-192916.34"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_core_rc_ok$next[0:0]$13819
+ attribute \src "libresoc.v:189989.7-189989.34"
wire $1\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $1\core_core_core_trapaddr$next[12:0]$13961
- attribute \src "libresoc.v:192920.14-192920.48"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $1\core_core_core_trapaddr$next[12:0]$13820
+ attribute \src "libresoc.v:189993.14-189993.48"
wire width 13 $1\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $1\core_core_core_traptype$next[7:0]$13962
- attribute \src "libresoc.v:192924.13-192924.44"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $1\core_core_core_traptype$next[7:0]$13821
+ attribute \src "libresoc.v:189997.13-189997.44"
wire width 8 $1\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_cr_in1$next[6:0]$13963
- attribute \src "libresoc.v:192928.13-192928.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_cr_in1$next[6:0]$13822
+ attribute \src "libresoc.v:190001.13-190001.37"
wire width 7 $1\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_cr_in1_ok$next[0:0]$13964
- attribute \src "libresoc.v:192932.7-192932.33"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_cr_in1_ok$next[0:0]$13823
+ attribute \src "libresoc.v:190005.7-190005.33"
wire $1\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_cr_in2$1$next[6:0]$13965
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_cr_in2$next[6:0]$13966
- attribute \src "libresoc.v:192936.13-192936.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_cr_in2$1$next[6:0]$13824
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_cr_in2$next[6:0]$13825
+ attribute \src "libresoc.v:190009.13-190009.37"
wire width 7 $1\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_cr_in2_ok$2$next[0:0]$13967
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_cr_in2_ok$next[0:0]$13968
- attribute \src "libresoc.v:192944.7-192944.33"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_cr_in2_ok$2$next[0:0]$13826
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_cr_in2_ok$next[0:0]$13827
+ attribute \src "libresoc.v:190017.7-190017.33"
wire $1\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_cr_out$next[6:0]$13969
- attribute \src "libresoc.v:192952.13-192952.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_cr_out$next[6:0]$13828
+ attribute \src "libresoc.v:190025.13-190025.37"
wire width 7 $1\core_core_cr_out[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_cr_wr_ok$next[0:0]$13970
- attribute \src "libresoc.v:192956.7-192956.32"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_cr_wr_ok$next[0:0]$13829
+ attribute \src "libresoc.v:190029.7-190029.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $1\core_core_dststep$next[6:0]$13630
- attribute \src "libresoc.v:192960.13-192960.38"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $1\core_core_dststep$next[6:0]$13506
+ attribute \src "libresoc.v:190033.13-190033.38"
wire width 7 $1\core_core_dststep[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_ea$next[6:0]$13971
- attribute \src "libresoc.v:192964.13-192964.33"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_ea$next[6:0]$13830
+ attribute \src "libresoc.v:190037.13-190037.33"
wire width 7 $1\core_core_ea[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $1\core_core_fast1$next[2:0]$13972
- attribute \src "libresoc.v:192968.13-192968.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $1\core_core_fast1$next[2:0]$13831
+ attribute \src "libresoc.v:190041.13-190041.35"
wire width 3 $1\core_core_fast1[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_fast1_ok$next[0:0]$13973
- attribute \src "libresoc.v:192972.7-192972.32"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_fast1_ok$next[0:0]$13832
+ attribute \src "libresoc.v:190045.7-190045.32"
wire $1\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $1\core_core_fast2$next[2:0]$13974
- attribute \src "libresoc.v:192976.13-192976.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $1\core_core_fast2$next[2:0]$13833
+ attribute \src "libresoc.v:190049.13-190049.35"
wire width 3 $1\core_core_fast2[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_fast2_ok$next[0:0]$13975
- attribute \src "libresoc.v:192980.7-192980.32"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_fast2_ok$next[0:0]$13834
+ attribute \src "libresoc.v:190053.7-190053.32"
wire $1\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $1\core_core_fasto1$next[2:0]$13976
- attribute \src "libresoc.v:192984.13-192984.36"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $1\core_core_fasto1$next[2:0]$13835
+ attribute \src "libresoc.v:190057.13-190057.36"
wire width 3 $1\core_core_fasto1[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $1\core_core_fasto2$next[2:0]$13977
- attribute \src "libresoc.v:192988.13-192988.36"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $1\core_core_fasto2$next[2:0]$13836
+ attribute \src "libresoc.v:190061.13-190061.36"
wire width 3 $1\core_core_fasto2[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_lk$next[0:0]$13978
- attribute \src "libresoc.v:192992.7-192992.26"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_lk$next[0:0]$13837
+ attribute \src "libresoc.v:190065.7-190065.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $1\core_core_maxvl$next[6:0]$13631
- attribute \src "libresoc.v:192996.13-192996.36"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $1\core_core_maxvl$next[6:0]$13507
+ attribute \src "libresoc.v:190069.13-190069.36"
wire width 7 $1\core_core_maxvl[6:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $1\core_core_pc$next[63:0]$13632
- attribute \src "libresoc.v:193000.14-193000.49"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $1\core_core_pc$next[63:0]$13508
+ attribute \src "libresoc.v:190073.14-190073.49"
wire width 64 $1\core_core_pc[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_reg1$next[6:0]$13979
- attribute \src "libresoc.v:193004.13-193004.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_reg1$next[6:0]$13838
+ attribute \src "libresoc.v:190077.13-190077.35"
wire width 7 $1\core_core_reg1[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_reg1_ok$next[0:0]$13980
- attribute \src "libresoc.v:193008.7-193008.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_reg1_ok$next[0:0]$13839
+ attribute \src "libresoc.v:190081.7-190081.31"
wire $1\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_reg2$next[6:0]$13981
- attribute \src "libresoc.v:193012.13-193012.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_reg2$next[6:0]$13840
+ attribute \src "libresoc.v:190085.13-190085.35"
wire width 7 $1\core_core_reg2[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_reg2_ok$next[0:0]$13982
- attribute \src "libresoc.v:193016.7-193016.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_reg2_ok$next[0:0]$13841
+ attribute \src "libresoc.v:190089.7-190089.31"
wire $1\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_reg3$next[6:0]$13983
- attribute \src "libresoc.v:193020.13-193020.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_reg3$next[6:0]$13842
+ attribute \src "libresoc.v:190093.13-190093.35"
wire width 7 $1\core_core_reg3[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_reg3_ok$next[0:0]$13984
- attribute \src "libresoc.v:193024.7-193024.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_reg3_ok$next[0:0]$13843
+ attribute \src "libresoc.v:190097.7-190097.31"
wire $1\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $1\core_core_rego$next[6:0]$13985
- attribute \src "libresoc.v:193028.13-193028.35"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $1\core_core_rego$next[6:0]$13844
+ attribute \src "libresoc.v:190101.13-190101.35"
wire width 7 $1\core_core_rego[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $1\core_core_spr1$next[9:0]$13986
- attribute \src "libresoc.v:193146.13-193146.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $1\core_core_spr1$next[9:0]$13845
+ attribute \src "libresoc.v:190219.13-190219.37"
wire width 10 $1\core_core_spr1[9:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_core_spr1_ok$next[0:0]$13987
- attribute \src "libresoc.v:193150.7-193150.31"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_core_spr1_ok$next[0:0]$13846
+ attribute \src "libresoc.v:190223.7-190223.31"
wire $1\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $1\core_core_spro$next[9:0]$13988
- attribute \src "libresoc.v:193268.13-193268.37"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $1\core_core_spro$next[9:0]$13847
+ attribute \src "libresoc.v:190341.13-190341.37"
wire width 10 $1\core_core_spro[9:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $1\core_core_srcstep$next[6:0]$13633
- attribute \src "libresoc.v:193272.13-193272.38"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $1\core_core_srcstep$next[6:0]$13509
+ attribute \src "libresoc.v:190345.13-190345.38"
wire width 7 $1\core_core_srcstep[6:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $1\core_core_subvl$next[1:0]$13634
- attribute \src "libresoc.v:193276.13-193276.35"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $1\core_core_subvl$next[1:0]$13510
+ attribute \src "libresoc.v:190349.13-190349.35"
wire width 2 $1\core_core_subvl[1:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $1\core_core_svstep$next[1:0]$13635
- attribute \src "libresoc.v:193280.13-193280.36"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $1\core_core_svstep$next[1:0]$13511
+ attribute \src "libresoc.v:190353.13-190353.36"
wire width 2 $1\core_core_svstep[1:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $1\core_core_vl$next[6:0]$13636
- attribute \src "libresoc.v:193286.13-193286.33"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $1\core_core_vl$next[6:0]$13512
+ attribute \src "libresoc.v:190359.13-190359.33"
wire width 7 $1\core_core_vl[6:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $1\core_core_xer_in$next[2:0]$13989
- attribute \src "libresoc.v:193290.13-193290.36"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $1\core_core_xer_in$next[2:0]$13848
+ attribute \src "libresoc.v:190363.13-190363.36"
wire width 3 $1\core_core_xer_in[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_cr_out_ok$next[0:0]$13990
- attribute \src "libresoc.v:193298.7-193298.28"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_cr_out_ok$next[0:0]$13849
+ attribute \src "libresoc.v:190371.7-190371.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:196020.3-196029.6"
- wire width 64 $1\core_data_i$12[63:0]$13681
- attribute \src "libresoc.v:196595.3-196620.6"
+ attribute \src "libresoc.v:192966.3-192975.6"
+ wire width 64 $1\core_data_i$12[63:0]$13555
+ attribute \src "libresoc.v:193500.3-193567.6"
wire width 64 $1\core_data_i[63:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $1\core_dec$next[63:0]$13637
- attribute \src "libresoc.v:193326.14-193326.45"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $1\core_dec$next[63:0]$13513
+ attribute \src "libresoc.v:190387.14-190387.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:196207.3-196216.6"
+ attribute \src "libresoc.v:193079.3-193088.6"
wire width 5 $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:196217.3-196226.6"
+ attribute \src "libresoc.v:193089.3-193098.6"
wire $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_ea_ok$next[0:0]$13991
- attribute \src "libresoc.v:193336.7-193336.24"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_ea_ok$next[0:0]$13850
+ attribute \src "libresoc.v:190397.7-190397.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire $1\core_eint$next[0:0]$13638
- attribute \src "libresoc.v:193340.7-193340.23"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire $1\core_eint$next[0:0]$13514
+ attribute \src "libresoc.v:190401.7-190401.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_fasto1_ok$next[0:0]$13992
- attribute \src "libresoc.v:193344.7-193344.28"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_fasto1_ok$next[0:0]$13851
+ attribute \src "libresoc.v:190405.7-190405.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_fasto2_ok$next[0:0]$13993
- attribute \src "libresoc.v:193348.7-193348.28"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_fasto2_ok$next[0:0]$13852
+ attribute \src "libresoc.v:190409.7-190409.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:196256.3-196265.6"
+ attribute \src "libresoc.v:193128.3-193137.6"
wire width 8 $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:196295.3-196304.6"
+ attribute \src "libresoc.v:193167.3-193176.6"
wire width 3 $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:196403.3-196417.6"
- wire width 3 $1\core_issue__addr$13[2:0]$13734
- attribute \src "libresoc.v:196334.3-196348.6"
+ attribute \src "libresoc.v:193275.3-193289.6"
+ wire width 3 $1\core_issue__addr$13[2:0]$13595
+ attribute \src "libresoc.v:193206.3-193220.6"
wire width 3 $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:196433.3-196447.6"
+ attribute \src "libresoc.v:193305.3-193319.6"
wire width 64 $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:196349.3-196363.6"
+ attribute \src "libresoc.v:193221.3-193235.6"
wire $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:196418.3-196432.6"
+ attribute \src "libresoc.v:193290.3-193304.6"
wire $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:196066.3-196081.6"
+ attribute \src "libresoc.v:193012.3-193027.6"
wire $1\core_issue_i[0:0]
- attribute \src "libresoc.v:196041.3-196065.6"
+ attribute \src "libresoc.v:192987.3-193011.6"
wire $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $1\core_msr$next[63:0]$13639
- attribute \src "libresoc.v:193376.14-193376.45"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $1\core_msr$next[63:0]$13515
+ attribute \src "libresoc.v:190437.14-190437.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:196621.3-196636.6"
+ attribute \src "libresoc.v:193568.3-193583.6"
wire width 3 $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $1\core_raw_insn_i$next[31:0]$13662
- attribute \src "libresoc.v:193384.14-193384.37"
+ attribute \src "libresoc.v:192841.3-192861.6"
+ wire width 32 $1\core_raw_insn_i$next[31:0]$13538
+ attribute \src "libresoc.v:190445.14-190445.37"
wire width 32 $1\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_rego_ok$next[0:0]$13994
- attribute \src "libresoc.v:193388.7-193388.26"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_rego_ok$next[0:0]$13853
+ attribute \src "libresoc.v:190449.7-190449.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_spro_ok$next[0:0]$13995
- attribute \src "libresoc.v:193392.7-193392.26"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_spro_ok$next[0:0]$13854
+ attribute \src "libresoc.v:190453.7-190453.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:197169.3-197199.6"
+ attribute \src "libresoc.v:194091.3-194121.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:196547.3-196559.6"
+ attribute \src "libresoc.v:193419.3-193431.6"
wire width 3 $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:196010.3-196019.6"
- wire width 3 $1\core_wen$11[2:0]$13678
- attribute \src "libresoc.v:196569.3-196594.6"
+ attribute \src "libresoc.v:192956.3-192965.6"
+ wire width 3 $1\core_wen$11[2:0]$13552
+ attribute \src "libresoc.v:193432.3-193499.6"
wire width 3 $1\core_wen[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $1\core_xer_out$next[0:0]$13996
- attribute \src "libresoc.v:193410.7-193410.26"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $1\core_xer_out$next[0:0]$13855
+ attribute \src "libresoc.v:190471.7-190471.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:193416.7-193416.30"
+ attribute \src "libresoc.v:190477.7-190477.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $1\cur_cur_dststep$next[6:0]$13780
- attribute \src "libresoc.v:193422.13-193422.36"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $1\cur_cur_dststep$next[6:0]$13641
+ attribute \src "libresoc.v:190483.13-190483.36"
wire width 7 $1\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $1\cur_cur_maxvl$next[6:0]$13781
- attribute \src "libresoc.v:193426.13-193426.34"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $1\cur_cur_maxvl$next[6:0]$13642
+ attribute \src "libresoc.v:190487.13-190487.34"
wire width 7 $1\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $1\cur_cur_subvl$next[1:0]$13782
- attribute \src "libresoc.v:193430.13-193430.33"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $1\cur_cur_srcstep$next[6:0]$13643
+ attribute \src "libresoc.v:190491.13-190491.36"
+ wire width 7 $1\cur_cur_srcstep[6:0]
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $1\cur_cur_subvl$next[1:0]$13644
+ attribute \src "libresoc.v:190495.13-190495.33"
wire width 2 $1\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $1\cur_cur_svstep$next[1:0]$13783
- attribute \src "libresoc.v:193434.13-193434.34"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $1\cur_cur_svstep$next[1:0]$13645
+ attribute \src "libresoc.v:190499.13-190499.34"
wire width 2 $1\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $1\cur_cur_vl$next[6:0]$13784
- attribute \src "libresoc.v:193438.13-193438.31"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $1\cur_cur_vl$next[6:0]$13646
+ attribute \src "libresoc.v:190503.13-190503.31"
wire width 7 $1\cur_cur_vl[6:0]
- attribute \src "libresoc.v:196266.3-196274.6"
- wire $1\d_cr_delay$next[0:0]$13716
- attribute \src "libresoc.v:193442.7-193442.24"
+ attribute \src "libresoc.v:193138.3-193146.6"
+ wire $1\d_cr_delay$next[0:0]$13577
+ attribute \src "libresoc.v:190507.7-190507.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:196227.3-196235.6"
- wire $1\d_reg_delay$next[0:0]$13710
- attribute \src "libresoc.v:193446.7-193446.25"
+ attribute \src "libresoc.v:193099.3-193107.6"
+ wire $1\d_reg_delay$next[0:0]$13571
+ attribute \src "libresoc.v:190511.7-190511.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:196305.3-196313.6"
- wire $1\d_xer_delay$next[0:0]$13722
- attribute \src "libresoc.v:193450.7-193450.25"
+ attribute \src "libresoc.v:193177.3-193185.6"
+ wire $1\d_xer_delay$next[0:0]$13583
+ attribute \src "libresoc.v:190515.7-190515.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:197200.3-197230.6"
+ attribute \src "libresoc.v:194122.3-194152.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:196285.3-196294.6"
+ attribute \src "libresoc.v:193157.3-193166.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:196275.3-196284.6"
+ attribute \src "libresoc.v:193147.3-193156.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:196246.3-196255.6"
+ attribute \src "libresoc.v:193118.3-193127.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:196236.3-196245.6"
+ attribute \src "libresoc.v:193108.3-193117.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:196324.3-196333.6"
+ attribute \src "libresoc.v:193196.3-193205.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:196314.3-196323.6"
+ attribute \src "libresoc.v:193186.3-193195.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:195839.3-195847.6"
- wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13609
- attribute \src "libresoc.v:193486.13-193486.34"
+ attribute \src "libresoc.v:192778.3-192786.6"
+ wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13491
+ attribute \src "libresoc.v:190563.13-190563.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:196560.3-196568.6"
- wire width 64 $1\dbg_dmi_din$next[63:0]$13757
- attribute \src "libresoc.v:193490.14-193490.48"
+ attribute \src "libresoc.v:193584.3-193592.6"
+ wire width 64 $1\dbg_dmi_din$next[63:0]$13621
+ attribute \src "libresoc.v:190567.14-190567.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:195848.3-195856.6"
- wire $1\dbg_dmi_req_i$next[0:0]$13612
- attribute \src "libresoc.v:193496.7-193496.27"
+ attribute \src "libresoc.v:192787.3-192795.6"
+ wire $1\dbg_dmi_req_i$next[0:0]$13494
+ attribute \src "libresoc.v:190573.7-190573.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:196475.3-196483.6"
- wire $1\dbg_dmi_we_i$next[0:0]$13744
- attribute \src "libresoc.v:193500.7-193500.26"
+ attribute \src "libresoc.v:193347.3-193355.6"
+ wire $1\dbg_dmi_we_i$next[0:0]$13605
+ attribute \src "libresoc.v:190577.7-190577.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $1\dec2_cur_cur_srcstep$next[6:0]$13785
- attribute \src "libresoc.v:193554.13-193554.41"
- wire width 7 $1\dec2_cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:196448.3-196463.6"
- wire width 64 $1\dec2_cur_dec$next[63:0]$13739
- attribute \src "libresoc.v:193558.14-193558.49"
+ attribute \src "libresoc.v:193320.3-193335.6"
+ wire width 64 $1\dec2_cur_dec$next[63:0]$13600
+ attribute \src "libresoc.v:190631.14-190631.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:195857.3-195865.6"
- wire $1\dec2_cur_eint$next[0:0]$13615
- attribute \src "libresoc.v:193562.7-193562.27"
+ attribute \src "libresoc.v:194471.3-194479.6"
+ wire $1\dec2_cur_eint$next[0:0]$13944
+ attribute \src "libresoc.v:190635.7-190635.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:196944.3-196964.6"
- wire width 64 $1\dec2_cur_msr$next[63:0]$13824
- attribute \src "libresoc.v:193566.14-193566.49"
+ attribute \src "libresoc.v:193850.3-193870.6"
+ wire width 64 $1\dec2_cur_msr$next[63:0]$13684
+ attribute \src "libresoc.v:190639.14-190639.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:196783.3-196803.6"
- wire width 64 $1\dec2_cur_pc$next[63:0]$13770
- attribute \src "libresoc.v:193570.14-193570.48"
+ attribute \src "libresoc.v:193697.3-193717.6"
+ wire width 64 $1\dec2_cur_pc$next[63:0]$13631
+ attribute \src "libresoc.v:190643.14-190643.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 9 $1\dec2_dec_svp64__extra$next[8:0]$13837
- attribute \src "libresoc.v:193574.13-193574.43"
- wire width 9 $1\dec2_dec_svp64__extra[8:0]
- attribute \src "libresoc.v:193724.14-193724.40"
+ attribute \src "libresoc.v:193890.3-193920.6"
+ wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13693
+ attribute \src "libresoc.v:190793.14-190793.40"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $1\dec_svp64__elwidth$next[1:0]$13838
- attribute \src "libresoc.v:193992.13-193992.38"
- wire width 2 $1\dec_svp64__elwidth[1:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $1\dec_svp64__ewsrc$next[1:0]$13839
- attribute \src "libresoc.v:193996.13-193996.36"
- wire width 2 $1\dec_svp64__ewsrc[1:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 3 $1\dec_svp64__mask$next[2:0]$13840
- attribute \src "libresoc.v:194000.13-194000.35"
- wire width 3 $1\dec_svp64__mask[2:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire $1\dec_svp64__mmode$next[0:0]$13841
- attribute \src "libresoc.v:194004.7-194004.30"
- wire $1\dec_svp64__mmode[0:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 5 $1\dec_svp64__mode$next[4:0]$13842
- attribute \src "libresoc.v:194008.13-194008.36"
- wire width 5 $1\dec_svp64__mode[4:0]
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $1\dec_svp64__subvl$next[1:0]$13843
- attribute \src "libresoc.v:194012.13-194012.36"
- wire width 2 $1\dec_svp64__subvl[1:0]
- attribute \src "libresoc.v:195866.3-195875.6"
- wire width 2 $1\delay$next[1:0]$13618
- attribute \src "libresoc.v:194016.13-194016.25"
+ attribute \src "libresoc.v:194480.3-194489.6"
+ wire width 2 $1\delay$next[1:0]$13947
+ attribute \src "libresoc.v:191061.13-191061.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $1\exec_fsm_state$next[0:0]$13687
- attribute \src "libresoc.v:194032.7-194032.28"
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $1\exec_fsm_state$next[0:0]$13561
+ attribute \src "libresoc.v:191077.7-191077.28"
wire $1\exec_fsm_state[0:0]
- attribute \src "libresoc.v:196030.3-196040.6"
+ attribute \src "libresoc.v:192976.3-192986.6"
wire $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:195983.3-195993.6"
+ attribute \src "libresoc.v:192887.3-192897.6"
wire $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:196191.3-196206.6"
+ attribute \src "libresoc.v:192898.3-192913.6"
wire $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:195994.3-196009.6"
+ attribute \src "libresoc.v:193063.3-193078.6"
wire $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $1\fetch_fsm_state$next[1:0]$13815
- attribute \src "libresoc.v:194044.13-194044.35"
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $1\fetch_fsm_state$next[1:0]$13676
+ attribute \src "libresoc.v:191089.13-191089.35"
wire width 2 $1\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:197060.3-197095.6"
- wire width 32 $1\fetch_insn_o[31:0]
- attribute \src "libresoc.v:197242.3-197252.6"
+ attribute \src "libresoc.v:194349.3-194359.6"
wire $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:197096.3-197106.6"
+ attribute \src "libresoc.v:193921.3-193931.6"
wire $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:196646.3-196656.6"
+ attribute \src "libresoc.v:193593.3-193603.6"
wire $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:197231.3-197241.6"
+ attribute \src "libresoc.v:193994.3-194009.6"
wire $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:196364.3-196391.6"
- wire width 2 $1\fsm_state$next[1:0]$13729
- attribute \src "libresoc.v:194058.13-194058.29"
+ attribute \src "libresoc.v:193236.3-193263.6"
+ wire width 2 $1\fsm_state$next[1:0]$13590
+ attribute \src "libresoc.v:191101.13-191101.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:196657.3-196692.6"
+ attribute \src "libresoc.v:193604.3-193619.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196693.3-196737.6"
+ attribute \src "libresoc.v:193629.3-193662.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
+ attribute \src "libresoc.v:193663.3-193696.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:196175.3-196190.6"
- wire $1\insn_done[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $1\issue_fsm_state$next[2:0]$13866
- attribute \src "libresoc.v:194314.13-194314.35"
+ attribute \src "libresoc.v:192935.3-192955.6"
+ wire $1\is_last[0:0]
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $1\issue_fsm_state$next[2:0]$13701
+ attribute \src "libresoc.v:191357.13-191357.35"
wire width 3 $1\issue_fsm_state[2:0]
- attribute \src "libresoc.v:196637.3-196645.6"
- wire $1\jtag_dmi0__ack_o$next[0:0]$13763
- attribute \src "libresoc.v:194318.7-194318.30"
+ attribute \src "libresoc.v:193620.3-193628.6"
+ wire $1\jtag_dmi0__ack_o$next[0:0]$13626
+ attribute \src "libresoc.v:191361.7-191361.30"
wire $1\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:196843.3-196851.6"
- wire width 64 $1\jtag_dmi0__dout$next[63:0]$13806
- attribute \src "libresoc.v:194326.14-194326.52"
+ attribute \src "libresoc.v:193787.3-193795.6"
+ wire width 64 $1\jtag_dmi0__dout$next[63:0]$13673
+ attribute \src "libresoc.v:191369.14-191369.52"
wire width 64 $1\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:196852.3-196881.6"
- wire $1\msr_read$next[0:0]$13809
- attribute \src "libresoc.v:194384.7-194384.22"
+ attribute \src "libresoc.v:193757.3-193786.6"
+ wire $1\msr_read$next[0:0]$13667
+ attribute \src "libresoc.v:191425.7-191425.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:196392.3-196402.6"
+ attribute \src "libresoc.v:193264.3-193274.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:196464.3-196474.6"
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $1\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $1\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $1\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $1\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $1\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $1\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:193336.3-193346.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:197041.3-197059.6"
- wire width 64 $1\nia$next[63:0]$13860
- attribute \src "libresoc.v:194420.14-194420.40"
+ attribute \src "libresoc.v:192914.3-192934.6"
+ wire width 7 $1\next_srcstep[6:0]
+ attribute \src "libresoc.v:193871.3-193889.6"
+ wire width 64 $1\nia$next[63:0]$13689
+ attribute \src "libresoc.v:191463.14-191463.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:196493.3-196508.6"
+ attribute \src "libresoc.v:193365.3-193380.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:196146.3-196174.6"
- wire $1\pc_changed$next[0:0]$13700
- attribute \src "libresoc.v:194426.7-194426.24"
+ attribute \src "libresoc.v:194153.3-194219.6"
+ wire $1\pc_changed$next[0:0]$13715
+ attribute \src "libresoc.v:191469.7-191469.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:196484.3-196492.6"
- wire $1\pc_ok_delay$next[0:0]$13747
- attribute \src "libresoc.v:194436.7-194436.25"
+ attribute \src "libresoc.v:193356.3-193364.6"
+ wire $1\pc_ok_delay$next[0:0]$13608
+ attribute \src "libresoc.v:191479.7-191479.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:196117.3-196145.6"
- wire $1\sv_changed$next[0:0]$13694
- attribute \src "libresoc.v:194880.7-194880.24"
+ attribute \src "libresoc.v:194282.3-194348.6"
+ wire $1\sv_changed$next[0:0]$13727
+ attribute \src "libresoc.v:191851.7-191851.24"
wire $1\sv_changed[0:0]
- attribute \src "libresoc.v:196984.3-197002.6"
- wire $1\svp64_bigendian[0:0]
- attribute \src "libresoc.v:196965.3-196983.6"
- wire width 32 $1\svp64_raw_opcode_in[31:0]
- attribute \src "libresoc.v:196531.3-196546.6"
+ attribute \src "libresoc.v:193403.3-193418.6"
wire width 64 $1\svstate[63:0]
- attribute \src "libresoc.v:196522.3-196530.6"
- wire $1\svstate_ok_delay$next[0:0]$13752
- attribute \src "libresoc.v:194898.7-194898.30"
+ attribute \src "libresoc.v:193394.3-193402.6"
+ wire $1\svstate_ok_delay$next[0:0]$13613
+ attribute \src "libresoc.v:191861.7-191861.30"
wire $1\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $2\core_asmcode$next[7:0]$13997
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $2\core_bigendian_i$10$next[0:0]$13670
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $2\core_core_core_cia$next[63:0]$13998
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $2\core_core_core_cr_rd$next[7:0]$13999
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_cr_rd_ok$next[0:0]$14000
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $2\core_core_core_cr_wr$next[7:0]$14001
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$3$next[0:0]$14002
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$4$next[0:0]$14003
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$5$next[0:0]$14004
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$6$next[0:0]$14005
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$7$next[0:0]$14006
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$8$next[0:0]$14007
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$9$next[0:0]$14008
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_exc_$signal$next[0:0]$14009
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $2\core_core_core_fn_unit$next[12:0]$14010
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 2 $2\core_core_core_input_carry$next[1:0]$14011
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 32 $2\core_core_core_insn$next[31:0]$14012
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_core_insn_type$next[6:0]$14013
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_is_32bit$next[0:0]$14014
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $2\core_core_core_msr$next[63:0]$14015
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_oe$next[0:0]$14016
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_oe_ok$next[0:0]$14017
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_rc$next[0:0]$14018
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_core_rc_ok$next[0:0]$14019
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $2\core_core_core_trapaddr$next[12:0]$14020
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $2\core_core_core_traptype$next[7:0]$14021
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_cr_in1$next[6:0]$14022
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_cr_in1_ok$next[0:0]$14023
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_cr_in2$1$next[6:0]$14024
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_cr_in2$next[6:0]$14025
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_cr_in2_ok$2$next[0:0]$14026
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_cr_in2_ok$next[0:0]$14027
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_cr_out$next[6:0]$14028
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_cr_wr_ok$next[0:0]$14029
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $2\core_core_dststep$next[6:0]$13640
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_ea$next[6:0]$14030
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $2\core_core_fast1$next[2:0]$14031
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_fast1_ok$next[0:0]$14032
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $2\core_core_fast2$next[2:0]$14033
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_fast2_ok$next[0:0]$14034
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $2\core_core_fasto1$next[2:0]$14035
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $2\core_core_fasto2$next[2:0]$14036
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_lk$next[0:0]$14037
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $2\core_core_maxvl$next[6:0]$13641
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $2\core_core_pc$next[63:0]$13642
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_reg1$next[6:0]$14038
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_reg1_ok$next[0:0]$14039
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_reg2$next[6:0]$14040
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_reg2_ok$next[0:0]$14041
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_reg3$next[6:0]$14042
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_reg3_ok$next[0:0]$14043
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $2\core_core_rego$next[6:0]$14044
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $2\core_core_spr1$next[9:0]$14045
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_core_spr1_ok$next[0:0]$14046
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $2\core_core_spro$next[9:0]$14047
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $2\core_core_srcstep$next[6:0]$13643
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $2\core_core_subvl$next[1:0]$13644
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $2\core_core_svstep$next[1:0]$13645
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $2\core_core_vl$next[6:0]$13646
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $2\core_core_xer_in$next[2:0]$14048
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_cr_out_ok$next[0:0]$14049
- attribute \src "libresoc.v:196595.3-196620.6"
+ attribute \src "libresoc.v:194220.3-194281.6"
+ wire $1\update_svstate[0:0]
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $2\core_asmcode$next[7:0]$13856
+ attribute \src "libresoc.v:192862.3-192886.6"
+ wire $2\core_bigendian_i$10$next[0:0]$13544
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $2\core_core_core_cia$next[63:0]$13857
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $2\core_core_core_cr_rd$next[7:0]$13858
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_cr_rd_ok$next[0:0]$13859
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $2\core_core_core_cr_wr$next[7:0]$13860
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$3$next[0:0]$13861
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$4$next[0:0]$13862
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$5$next[0:0]$13863
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$6$next[0:0]$13864
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$7$next[0:0]$13865
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$8$next[0:0]$13866
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$9$next[0:0]$13867
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_exc_$signal$next[0:0]$13868
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $2\core_core_core_fn_unit$next[12:0]$13869
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 2 $2\core_core_core_input_carry$next[1:0]$13870
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 32 $2\core_core_core_insn$next[31:0]$13871
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_core_insn_type$next[6:0]$13872
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_is_32bit$next[0:0]$13873
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 64 $2\core_core_core_msr$next[63:0]$13874
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_oe$next[0:0]$13875
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_oe_ok$next[0:0]$13876
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_rc$next[0:0]$13877
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_core_rc_ok$next[0:0]$13878
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 13 $2\core_core_core_trapaddr$next[12:0]$13879
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 8 $2\core_core_core_traptype$next[7:0]$13880
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_cr_in1$next[6:0]$13881
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_cr_in1_ok$next[0:0]$13882
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_cr_in2$1$next[6:0]$13883
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_cr_in2$next[6:0]$13884
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_cr_in2_ok$2$next[0:0]$13885
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_cr_in2_ok$next[0:0]$13886
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_cr_out$next[6:0]$13887
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_cr_wr_ok$next[0:0]$13888
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $2\core_core_dststep$next[6:0]$13516
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_ea$next[6:0]$13889
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $2\core_core_fast1$next[2:0]$13890
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_fast1_ok$next[0:0]$13891
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $2\core_core_fast2$next[2:0]$13892
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_fast2_ok$next[0:0]$13893
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $2\core_core_fasto1$next[2:0]$13894
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $2\core_core_fasto2$next[2:0]$13895
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_lk$next[0:0]$13896
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $2\core_core_maxvl$next[6:0]$13517
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $2\core_core_pc$next[63:0]$13518
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_reg1$next[6:0]$13897
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_reg1_ok$next[0:0]$13898
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_reg2$next[6:0]$13899
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_reg2_ok$next[0:0]$13900
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_reg3$next[6:0]$13901
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_reg3_ok$next[0:0]$13902
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 7 $2\core_core_rego$next[6:0]$13903
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $2\core_core_spr1$next[9:0]$13904
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_core_spr1_ok$next[0:0]$13905
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 10 $2\core_core_spro$next[9:0]$13906
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $2\core_core_srcstep$next[6:0]$13519
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $2\core_core_subvl$next[1:0]$13520
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $2\core_core_svstep$next[1:0]$13521
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $2\core_core_vl$next[6:0]$13522
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire width 3 $2\core_core_xer_in$next[2:0]$13907
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_cr_out_ok$next[0:0]$13908
+ attribute \src "libresoc.v:193500.3-193567.6"
wire width 64 $2\core_data_i[63:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $2\core_dec$next[63:0]$13647
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_ea_ok$next[0:0]$14050
- attribute \src "libresoc.v:195876.3-195916.6"
- wire $2\core_eint$next[0:0]$13648
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_fasto1_ok$next[0:0]$14051
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_fasto2_ok$next[0:0]$14052
- attribute \src "libresoc.v:196066.3-196081.6"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $2\core_dec$next[63:0]$13523
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_ea_ok$next[0:0]$13909
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire $2\core_eint$next[0:0]$13524
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_fasto1_ok$next[0:0]$13910
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_fasto2_ok$next[0:0]$13911
+ attribute \src "libresoc.v:193012.3-193027.6"
wire $2\core_issue_i[0:0]
- attribute \src "libresoc.v:196041.3-196065.6"
+ attribute \src "libresoc.v:192987.3-193011.6"
wire $2\core_ivalid_i[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $2\core_msr$next[63:0]$13649
- attribute \src "libresoc.v:196621.3-196636.6"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $2\core_msr$next[63:0]$13525
+ attribute \src "libresoc.v:193568.3-193583.6"
wire width 3 $2\core_msr__ren[2:0]
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $2\core_raw_insn_i$next[31:0]$13663
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_rego_ok$next[0:0]$14053
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_spro_ok$next[0:0]$14054
- attribute \src "libresoc.v:197169.3-197199.6"
+ attribute \src "libresoc.v:192841.3-192861.6"
+ wire width 32 $2\core_raw_insn_i$next[31:0]$13539
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_rego_ok$next[0:0]$13912
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_spro_ok$next[0:0]$13913
+ attribute \src "libresoc.v:194091.3-194121.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:196569.3-196594.6"
+ attribute \src "libresoc.v:193432.3-193499.6"
wire width 3 $2\core_wen[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $2\core_xer_out$next[0:0]$14055
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $2\cur_cur_dststep$next[6:0]$13786
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $2\cur_cur_maxvl$next[6:0]$13787
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $2\cur_cur_subvl$next[1:0]$13788
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $2\cur_cur_svstep$next[1:0]$13789
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $2\cur_cur_vl$next[6:0]$13790
- attribute \src "libresoc.v:197200.3-197230.6"
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $2\core_xer_out$next[0:0]$13914
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $2\cur_cur_dststep$next[6:0]$13647
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $2\cur_cur_maxvl$next[6:0]$13648
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $2\cur_cur_srcstep$next[6:0]$13649
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $2\cur_cur_subvl$next[1:0]$13650
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $2\cur_cur_svstep$next[1:0]$13651
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $2\cur_cur_vl$next[6:0]$13652
+ attribute \src "libresoc.v:194122.3-194152.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $2\dec2_cur_cur_srcstep$next[6:0]$13791
- attribute \src "libresoc.v:196448.3-196463.6"
- wire width 64 $2\dec2_cur_dec$next[63:0]$13740
- attribute \src "libresoc.v:196944.3-196964.6"
- wire width 64 $2\dec2_cur_msr$next[63:0]$13825
- attribute \src "libresoc.v:196783.3-196803.6"
- wire width 64 $2\dec2_cur_pc$next[63:0]$13771
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 9 $2\dec2_dec_svp64__extra$next[8:0]$13844
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $2\dec_svp64__elwidth$next[1:0]$13845
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $2\dec_svp64__ewsrc$next[1:0]$13846
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 3 $2\dec_svp64__mask$next[2:0]$13847
- attribute \src "libresoc.v:197003.3-197040.6"
- wire $2\dec_svp64__mmode$next[0:0]$13848
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 5 $2\dec_svp64__mode$next[4:0]$13849
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $2\dec_svp64__subvl$next[1:0]$13850
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $2\exec_fsm_state$next[0:0]$13688
- attribute \src "libresoc.v:196191.3-196206.6"
+ attribute \src "libresoc.v:193320.3-193335.6"
+ wire width 64 $2\dec2_cur_dec$next[63:0]$13601
+ attribute \src "libresoc.v:193850.3-193870.6"
+ wire width 64 $2\dec2_cur_msr$next[63:0]$13685
+ attribute \src "libresoc.v:193697.3-193717.6"
+ wire width 64 $2\dec2_cur_pc$next[63:0]$13632
+ attribute \src "libresoc.v:193890.3-193920.6"
+ wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13694
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $2\exec_fsm_state$next[0:0]$13562
+ attribute \src "libresoc.v:192898.3-192913.6"
wire $2\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:195994.3-196009.6"
+ attribute \src "libresoc.v:193063.3-193078.6"
wire $2\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $2\fetch_fsm_state$next[1:0]$13816
- attribute \src "libresoc.v:197060.3-197095.6"
- wire width 32 $2\fetch_insn_o[31:0]
- attribute \src "libresoc.v:196364.3-196391.6"
- wire width 2 $2\fsm_state$next[1:0]$13730
- attribute \src "libresoc.v:196657.3-196692.6"
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $2\fetch_fsm_state$next[1:0]$13677
+ attribute \src "libresoc.v:193994.3-194009.6"
+ wire $2\fetch_pc_valid_i[0:0]
+ attribute \src "libresoc.v:193236.3-193263.6"
+ wire width 2 $2\fsm_state$next[1:0]$13591
+ attribute \src "libresoc.v:193604.3-193619.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196693.3-196737.6"
+ attribute \src "libresoc.v:193629.3-193662.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
+ attribute \src "libresoc.v:193663.3-193696.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:196175.3-196190.6"
- wire $2\insn_done[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $2\issue_fsm_state$next[2:0]$13867
- attribute \src "libresoc.v:196852.3-196881.6"
- wire $2\msr_read$next[0:0]$13810
- attribute \src "libresoc.v:197041.3-197059.6"
- wire width 64 $2\nia$next[63:0]$13861
- attribute \src "libresoc.v:196493.3-196508.6"
+ attribute \src "libresoc.v:192935.3-192955.6"
+ wire $2\is_last[0:0]
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $2\issue_fsm_state$next[2:0]$13702
+ attribute \src "libresoc.v:193757.3-193786.6"
+ wire $2\msr_read$next[0:0]$13668
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $2\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $2\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $2\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $2\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $2\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $2\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:192914.3-192934.6"
+ wire width 7 $2\next_srcstep[6:0]
+ attribute \src "libresoc.v:193871.3-193889.6"
+ wire width 64 $2\nia$next[63:0]$13690
+ attribute \src "libresoc.v:193365.3-193380.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:196146.3-196174.6"
- wire $2\pc_changed$next[0:0]$13701
- attribute \src "libresoc.v:196117.3-196145.6"
- wire $2\sv_changed$next[0:0]$13695
- attribute \src "libresoc.v:196984.3-197002.6"
- wire $2\svp64_bigendian[0:0]
- attribute \src "libresoc.v:196965.3-196983.6"
- wire width 32 $2\svp64_raw_opcode_in[31:0]
- attribute \src "libresoc.v:196531.3-196546.6"
+ attribute \src "libresoc.v:194153.3-194219.6"
+ wire $2\pc_changed$next[0:0]$13716
+ attribute \src "libresoc.v:194282.3-194348.6"
+ wire $2\sv_changed$next[0:0]$13728
+ attribute \src "libresoc.v:193403.3-193418.6"
wire width 64 $2\svstate[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $3\core_asmcode$next[7:0]$14056
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $3\core_bigendian_i$10$next[0:0]$13671
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $3\core_core_core_cia$next[63:0]$14057
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $3\core_core_core_cr_rd$next[7:0]$14058
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_cr_rd_ok$next[0:0]$14059
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $3\core_core_core_cr_wr$next[7:0]$14060
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$3$next[0:0]$14061
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$4$next[0:0]$14062
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$5$next[0:0]$14063
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$6$next[0:0]$14064
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$7$next[0:0]$14065
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$8$next[0:0]$14066
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$9$next[0:0]$14067
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_exc_$signal$next[0:0]$14068
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $3\core_core_core_fn_unit$next[12:0]$14069
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 2 $3\core_core_core_input_carry$next[1:0]$14070
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 32 $3\core_core_core_insn$next[31:0]$14071
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_core_insn_type$next[6:0]$14072
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_is_32bit$next[0:0]$14073
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $3\core_core_core_msr$next[63:0]$14074
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_oe$next[0:0]$14075
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_oe_ok$next[0:0]$14076
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_rc$next[0:0]$14077
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_core_rc_ok$next[0:0]$14078
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $3\core_core_core_trapaddr$next[12:0]$14079
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $3\core_core_core_traptype$next[7:0]$14080
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_cr_in1$next[6:0]$14081
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_cr_in1_ok$next[0:0]$14082
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_cr_in2$1$next[6:0]$14083
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_cr_in2$next[6:0]$14084
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_cr_in2_ok$2$next[0:0]$14085
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_cr_in2_ok$next[0:0]$14086
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_cr_out$next[6:0]$14087
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_cr_wr_ok$next[0:0]$14088
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $3\core_core_dststep$next[6:0]$13650
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_ea$next[6:0]$14089
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $3\core_core_fast1$next[2:0]$14090
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_fast1_ok$next[0:0]$14091
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $3\core_core_fast2$next[2:0]$14092
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_fast2_ok$next[0:0]$14093
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $3\core_core_fasto1$next[2:0]$14094
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $3\core_core_fasto2$next[2:0]$14095
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_lk$next[0:0]$14096
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $3\core_core_maxvl$next[6:0]$13651
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $3\core_core_pc$next[63:0]$13652
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_reg1$next[6:0]$14097
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_reg1_ok$next[0:0]$14098
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_reg2$next[6:0]$14099
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_reg2_ok$next[0:0]$14100
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_reg3$next[6:0]$14101
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_reg3_ok$next[0:0]$14102
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $3\core_core_rego$next[6:0]$14103
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $3\core_core_spr1$next[9:0]$14104
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_core_spr1_ok$next[0:0]$14105
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $3\core_core_spro$next[9:0]$14106
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $3\core_core_srcstep$next[6:0]$13653
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $3\core_core_subvl$next[1:0]$13654
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 2 $3\core_core_svstep$next[1:0]$13655
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 7 $3\core_core_vl$next[6:0]$13656
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $3\core_core_xer_in$next[2:0]$14107
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_cr_out_ok$next[0:0]$14108
- attribute \src "libresoc.v:196595.3-196620.6"
+ attribute \src "libresoc.v:194220.3-194281.6"
+ wire $2\update_svstate[0:0]
+ attribute \src "libresoc.v:192862.3-192886.6"
+ wire $3\core_bigendian_i$10$next[0:0]$13545
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_cr_rd_ok$next[0:0]$13915
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$3$next[0:0]$13916
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$4$next[0:0]$13917
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$5$next[0:0]$13918
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$6$next[0:0]$13919
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$7$next[0:0]$13920
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$8$next[0:0]$13921
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$9$next[0:0]$13922
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_exc_$signal$next[0:0]$13923
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_oe_ok$next[0:0]$13924
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_core_rc_ok$next[0:0]$13925
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_cr_in1_ok$next[0:0]$13926
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_cr_in2_ok$2$next[0:0]$13927
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_cr_in2_ok$next[0:0]$13928
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_cr_wr_ok$next[0:0]$13929
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $3\core_core_dststep$next[6:0]$13526
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_fast1_ok$next[0:0]$13930
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_fast2_ok$next[0:0]$13931
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $3\core_core_maxvl$next[6:0]$13527
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $3\core_core_pc$next[63:0]$13528
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_reg1_ok$next[0:0]$13932
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_reg2_ok$next[0:0]$13933
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_reg3_ok$next[0:0]$13934
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_core_spr1_ok$next[0:0]$13935
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $3\core_core_srcstep$next[6:0]$13529
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $3\core_core_subvl$next[1:0]$13530
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 2 $3\core_core_svstep$next[1:0]$13531
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 7 $3\core_core_vl$next[6:0]$13532
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_cr_out_ok$next[0:0]$13936
+ attribute \src "libresoc.v:193500.3-193567.6"
wire width 64 $3\core_data_i[63:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $3\core_dec$next[63:0]$13657
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_ea_ok$next[0:0]$14109
- attribute \src "libresoc.v:195876.3-195916.6"
- wire $3\core_eint$next[0:0]$13658
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_fasto1_ok$next[0:0]$14110
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_fasto2_ok$next[0:0]$14111
- attribute \src "libresoc.v:196041.3-196065.6"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $3\core_dec$next[63:0]$13533
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_ea_ok$next[0:0]$13937
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire $3\core_eint$next[0:0]$13534
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_fasto1_ok$next[0:0]$13938
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_fasto2_ok$next[0:0]$13939
+ attribute \src "libresoc.v:192987.3-193011.6"
wire $3\core_ivalid_i[0:0]
- attribute \src "libresoc.v:195876.3-195916.6"
- wire width 64 $3\core_msr$next[63:0]$13659
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $3\core_raw_insn_i$next[31:0]$13664
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_rego_ok$next[0:0]$14112
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_spro_ok$next[0:0]$14113
- attribute \src "libresoc.v:197169.3-197199.6"
+ attribute \src "libresoc.v:192796.3-192840.6"
+ wire width 64 $3\core_msr$next[63:0]$13535
+ attribute \src "libresoc.v:192841.3-192861.6"
+ wire width 32 $3\core_raw_insn_i$next[31:0]$13540
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_rego_ok$next[0:0]$13940
+ attribute \src "libresoc.v:194360.3-194470.6"
+ wire $3\core_spro_ok$next[0:0]$13941
+ attribute \src "libresoc.v:194091.3-194121.6"
wire $3\core_stopped_i[0:0]
- attribute \src "libresoc.v:196569.3-196594.6"
+ attribute \src "libresoc.v:193432.3-193499.6"
wire width 3 $3\core_wen[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $3\core_xer_out$next[0:0]$14114
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $3\cur_cur_dststep$next[6:0]$13792
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $3\cur_cur_maxvl$next[6:0]$13793
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $3\cur_cur_subvl$next[1:0]$13794
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $3\cur_cur_svstep$next[1:0]$13795
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $3\cur_cur_vl$next[6:0]$13796
- attribute \src "libresoc.v:197200.3-197230.6"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $3\cur_cur_dststep$next[6:0]$13653
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $3\cur_cur_maxvl$next[6:0]$13654
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $3\cur_cur_srcstep$next[6:0]$13655
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $3\cur_cur_subvl$next[1:0]$13656
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $3\cur_cur_svstep$next[1:0]$13657
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $3\cur_cur_vl$next[6:0]$13658
+ attribute \src "libresoc.v:194122.3-194152.6"
wire $3\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $3\dec2_cur_cur_srcstep$next[6:0]$13797
- attribute \src "libresoc.v:196944.3-196964.6"
- wire width 64 $3\dec2_cur_msr$next[63:0]$13826
- attribute \src "libresoc.v:196783.3-196803.6"
- wire width 64 $3\dec2_cur_pc$next[63:0]$13772
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 9 $3\dec2_dec_svp64__extra$next[8:0]$13851
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $3\dec_svp64__elwidth$next[1:0]$13852
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $3\dec_svp64__ewsrc$next[1:0]$13853
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 3 $3\dec_svp64__mask$next[2:0]$13854
- attribute \src "libresoc.v:197003.3-197040.6"
- wire $3\dec_svp64__mmode$next[0:0]$13855
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 5 $3\dec_svp64__mode$next[4:0]$13856
- attribute \src "libresoc.v:197003.3-197040.6"
- wire width 2 $3\dec_svp64__subvl$next[1:0]$13857
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $3\exec_fsm_state$next[0:0]$13689
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $3\fetch_fsm_state$next[1:0]$13817
- attribute \src "libresoc.v:197060.3-197095.6"
- wire width 32 $3\fetch_insn_o[31:0]
- attribute \src "libresoc.v:196657.3-196692.6"
- wire width 48 $3\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196693.3-196737.6"
+ attribute \src "libresoc.v:193850.3-193870.6"
+ wire width 64 $3\dec2_cur_msr$next[63:0]$13686
+ attribute \src "libresoc.v:193697.3-193717.6"
+ wire width 64 $3\dec2_cur_pc$next[63:0]$13633
+ attribute \src "libresoc.v:193890.3-193920.6"
+ wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13695
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $3\exec_fsm_state$next[0:0]$13563
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $3\fetch_fsm_state$next[1:0]$13678
+ attribute \src "libresoc.v:193629.3-193662.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
+ attribute \src "libresoc.v:193663.3-193696.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $3\issue_fsm_state$next[2:0]$13868
- attribute \src "libresoc.v:196852.3-196881.6"
- wire $3\msr_read$next[0:0]$13811
- attribute \src "libresoc.v:196146.3-196174.6"
- wire $3\pc_changed$next[0:0]$13702
- attribute \src "libresoc.v:196117.3-196145.6"
- wire $3\sv_changed$next[0:0]$13696
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $4\core_asmcode$next[7:0]$14115
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $4\core_bigendian_i$10$next[0:0]$13672
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $4\core_core_core_cia$next[63:0]$14116
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $4\core_core_core_cr_rd$next[7:0]$14117
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_cr_rd_ok$next[0:0]$14118
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $4\core_core_core_cr_wr$next[7:0]$14119
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$3$next[0:0]$14120
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$4$next[0:0]$14121
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$5$next[0:0]$14122
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$6$next[0:0]$14123
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$7$next[0:0]$14124
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$8$next[0:0]$14125
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$9$next[0:0]$14126
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_exc_$signal$next[0:0]$14127
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $4\core_core_core_fn_unit$next[12:0]$14128
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 2 $4\core_core_core_input_carry$next[1:0]$14129
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 32 $4\core_core_core_insn$next[31:0]$14130
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_core_insn_type$next[6:0]$14131
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_is_32bit$next[0:0]$14132
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 64 $4\core_core_core_msr$next[63:0]$14133
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_oe$next[0:0]$14134
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_oe_ok$next[0:0]$14135
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_rc$next[0:0]$14136
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_core_rc_ok$next[0:0]$14137
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 13 $4\core_core_core_trapaddr$next[12:0]$14138
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 8 $4\core_core_core_traptype$next[7:0]$14139
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_cr_in1$next[6:0]$14140
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_cr_in1_ok$next[0:0]$14141
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_cr_in2$1$next[6:0]$14142
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_cr_in2$next[6:0]$14143
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_cr_in2_ok$2$next[0:0]$14144
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_cr_in2_ok$next[0:0]$14145
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_cr_out$next[6:0]$14146
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_cr_wr_ok$next[0:0]$14147
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_ea$next[6:0]$14148
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $4\core_core_fast1$next[2:0]$14149
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_fast1_ok$next[0:0]$14150
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $4\core_core_fast2$next[2:0]$14151
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_fast2_ok$next[0:0]$14152
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $4\core_core_fasto1$next[2:0]$14153
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $4\core_core_fasto2$next[2:0]$14154
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_lk$next[0:0]$14155
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_reg1$next[6:0]$14156
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_reg1_ok$next[0:0]$14157
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_reg2$next[6:0]$14158
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_reg2_ok$next[0:0]$14159
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_reg3$next[6:0]$14160
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_reg3_ok$next[0:0]$14161
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 7 $4\core_core_rego$next[6:0]$14162
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $4\core_core_spr1$next[9:0]$14163
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_core_spr1_ok$next[0:0]$14164
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 10 $4\core_core_spro$next[9:0]$14165
- attribute \src "libresoc.v:197253.3-197371.6"
- wire width 3 $4\core_core_xer_in$next[2:0]$14166
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_cr_out_ok$next[0:0]$14167
- attribute \src "libresoc.v:196595.3-196620.6"
+ attribute \src "libresoc.v:192935.3-192955.6"
+ wire $3\is_last[0:0]
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $3\issue_fsm_state$next[2:0]$13703
+ attribute \src "libresoc.v:193757.3-193786.6"
+ wire $3\msr_read$next[0:0]$13669
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $3\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $3\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $3\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $3\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $3\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $3\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:192914.3-192934.6"
+ wire width 7 $3\next_srcstep[6:0]
+ attribute \src "libresoc.v:194153.3-194219.6"
+ wire $3\pc_changed$next[0:0]$13717
+ attribute \src "libresoc.v:194282.3-194348.6"
+ wire $3\sv_changed$next[0:0]$13729
+ attribute \src "libresoc.v:194220.3-194281.6"
+ wire $3\update_svstate[0:0]
+ attribute \src "libresoc.v:193500.3-193567.6"
wire width 64 $4\core_data_i[63:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_ea_ok$next[0:0]$14168
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_fasto1_ok$next[0:0]$14169
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_fasto2_ok$next[0:0]$14170
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $4\core_raw_insn_i$next[31:0]$13665
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_rego_ok$next[0:0]$14171
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_spro_ok$next[0:0]$14172
- attribute \src "libresoc.v:196569.3-196594.6"
+ attribute \src "libresoc.v:193432.3-193499.6"
wire width 3 $4\core_wen[2:0]
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $4\core_xer_out$next[0:0]$14173
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $4\cur_cur_dststep$next[6:0]$13798
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $4\cur_cur_maxvl$next[6:0]$13799
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $4\cur_cur_subvl$next[1:0]$13800
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 2 $4\cur_cur_svstep$next[1:0]$13801
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $4\cur_cur_vl$next[6:0]$13802
- attribute \src "libresoc.v:196804.3-196842.6"
- wire width 7 $4\dec2_cur_cur_srcstep$next[6:0]$13803
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $4\exec_fsm_state$next[0:0]$13690
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $4\fetch_fsm_state$next[1:0]$13818
- attribute \src "libresoc.v:197060.3-197095.6"
- wire width 32 $4\fetch_insn_o[31:0]
- attribute \src "libresoc.v:196657.3-196692.6"
- wire width 48 $4\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196693.3-196737.6"
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $4\cur_cur_dststep$next[6:0]$13659
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $4\cur_cur_maxvl$next[6:0]$13660
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $4\cur_cur_srcstep$next[6:0]$13661
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $4\cur_cur_subvl$next[1:0]$13662
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 2 $4\cur_cur_svstep$next[1:0]$13663
+ attribute \src "libresoc.v:193718.3-193756.6"
+ wire width 7 $4\cur_cur_vl$next[6:0]$13664
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $4\exec_fsm_state$next[0:0]$13564
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $4\fetch_fsm_state$next[1:0]$13679
+ attribute \src "libresoc.v:193629.3-193662.6"
wire $4\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
+ attribute \src "libresoc.v:193663.3-193696.6"
wire $4\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $4\issue_fsm_state$next[2:0]$13869
- attribute \src "libresoc.v:196852.3-196881.6"
- wire $4\msr_read$next[0:0]$13812
- attribute \src "libresoc.v:196146.3-196174.6"
- wire $4\pc_changed$next[0:0]$13703
- attribute \src "libresoc.v:196117.3-196145.6"
- wire $4\sv_changed$next[0:0]$13697
- attribute \src "libresoc.v:195950.3-195982.6"
- wire $5\core_bigendian_i$10$next[0:0]$13673
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_cr_rd_ok$next[0:0]$14174
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$3$next[0:0]$14175
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$4$next[0:0]$14176
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$5$next[0:0]$14177
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$6$next[0:0]$14178
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$7$next[0:0]$14179
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$8$next[0:0]$14180
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$9$next[0:0]$14181
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_exc_$signal$next[0:0]$14182
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_oe_ok$next[0:0]$14183
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_core_rc_ok$next[0:0]$14184
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_cr_in1_ok$next[0:0]$14185
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_cr_in2_ok$2$next[0:0]$14186
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_cr_in2_ok$next[0:0]$14187
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_cr_wr_ok$next[0:0]$14188
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_fast1_ok$next[0:0]$14189
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_fast2_ok$next[0:0]$14190
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_reg1_ok$next[0:0]$14191
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_reg2_ok$next[0:0]$14192
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_reg3_ok$next[0:0]$14193
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_core_spr1_ok$next[0:0]$14194
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_cr_out_ok$next[0:0]$14195
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_ea_ok$next[0:0]$14196
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_fasto1_ok$next[0:0]$14197
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_fasto2_ok$next[0:0]$14198
- attribute \src "libresoc.v:195917.3-195949.6"
- wire width 32 $5\core_raw_insn_i$next[31:0]$13666
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_rego_ok$next[0:0]$14199
- attribute \src "libresoc.v:197253.3-197371.6"
- wire $5\core_spro_ok$next[0:0]$14200
- attribute \src "libresoc.v:196082.3-196116.6"
- wire $5\exec_fsm_state$next[0:0]$13691
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $5\fetch_fsm_state$next[1:0]$13819
- attribute \src "libresoc.v:196693.3-196737.6"
- wire $5\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196738.3-196782.6"
- wire $5\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $5\issue_fsm_state$next[2:0]$13870
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $6\fetch_fsm_state$next[1:0]$13820
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $6\issue_fsm_state$next[2:0]$13871
- attribute \src "libresoc.v:196882.3-196943.6"
- wire width 2 $7\fetch_fsm_state$next[1:0]$13821
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $7\issue_fsm_state$next[2:0]$13872
- attribute \src "libresoc.v:197107.3-197168.6"
- wire width 3 $8\issue_fsm_state$next[2:0]$13873
- attribute \src "libresoc.v:194952.19-194952.115"
- wire width 65 $add$libresoc.v:194952$13448_Y
- attribute \src "libresoc.v:194972.18-194972.107"
- wire width 65 $add$libresoc.v:194972$13469_Y
- attribute \src "libresoc.v:194981.18-194981.107"
- wire width 65 $add$libresoc.v:194981$13478_Y
- attribute \src "libresoc.v:194985.18-194985.107"
- wire width 65 $add$libresoc.v:194985$13482_Y
- attribute \src "libresoc.v:194916.19-194916.102"
- wire $and$libresoc.v:194916$13410_Y
- attribute \src "libresoc.v:194919.19-194919.104"
- wire $and$libresoc.v:194919$13413_Y
- attribute \src "libresoc.v:194922.19-194922.104"
- wire $and$libresoc.v:194922$13416_Y
- attribute \src "libresoc.v:194925.19-194925.104"
- wire $and$libresoc.v:194925$13419_Y
- attribute \src "libresoc.v:194928.19-194928.104"
- wire $and$libresoc.v:194928$13422_Y
- attribute \src "libresoc.v:194931.19-194931.104"
- wire $and$libresoc.v:194931$13425_Y
- attribute \src "libresoc.v:194937.19-194937.104"
- wire $and$libresoc.v:194937$13431_Y
- attribute \src "libresoc.v:194941.19-194941.115"
- wire width 3 $and$libresoc.v:194941$13435_Y
- attribute \src "libresoc.v:194944.19-194944.115"
- wire width 3 $and$libresoc.v:194944$13438_Y
- attribute \src "libresoc.v:194959.18-194959.109"
- wire $and$libresoc.v:194959$13455_Y
- attribute \src "libresoc.v:194965.18-194965.101"
- wire $and$libresoc.v:194965$13462_Y
- attribute \src "libresoc.v:194969.18-194969.101"
- wire $and$libresoc.v:194969$13466_Y
- attribute \src "libresoc.v:194949.19-194949.114"
- wire width 64 $extend$libresoc.v:194949$13443_Y
- attribute \src "libresoc.v:194950.19-194950.113"
- wire width 64 $extend$libresoc.v:194950$13445_Y
- attribute \src "libresoc.v:194962.18-194962.109"
- wire width 64 $extend$libresoc.v:194962$13458_Y
- attribute \src "libresoc.v:194978.18-194978.110"
- wire width 7 $mul$libresoc.v:194978$13475_Y
- attribute \src "libresoc.v:194983.18-194983.110"
- wire width 7 $mul$libresoc.v:194983$13480_Y
- attribute \src "libresoc.v:194986.18-194986.104"
- wire width 7 $mul$libresoc.v:194986$13483_Y
- attribute \src "libresoc.v:194939.19-194939.123"
- wire $ne$libresoc.v:194939$13433_Y
- attribute \src "libresoc.v:194953.18-194953.102"
- wire $ne$libresoc.v:194953$13449_Y
- attribute \src "libresoc.v:194957.18-194957.102"
- wire $ne$libresoc.v:194957$13453_Y
- attribute \src "libresoc.v:194915.18-194915.108"
- wire $not$libresoc.v:194915$13409_Y
- attribute \src "libresoc.v:194917.19-194917.107"
- wire $not$libresoc.v:194917$13411_Y
- attribute \src "libresoc.v:194918.19-194918.109"
- wire $not$libresoc.v:194918$13412_Y
- attribute \src "libresoc.v:194920.19-194920.107"
- wire $not$libresoc.v:194920$13414_Y
- attribute \src "libresoc.v:194921.19-194921.109"
- wire $not$libresoc.v:194921$13415_Y
- attribute \src "libresoc.v:194923.19-194923.107"
- wire $not$libresoc.v:194923$13417_Y
- attribute \src "libresoc.v:194924.19-194924.109"
- wire $not$libresoc.v:194924$13418_Y
- attribute \src "libresoc.v:194926.19-194926.107"
- wire $not$libresoc.v:194926$13420_Y
- attribute \src "libresoc.v:194927.19-194927.109"
- wire $not$libresoc.v:194927$13421_Y
- attribute \src "libresoc.v:194929.19-194929.107"
- wire $not$libresoc.v:194929$13423_Y
- attribute \src "libresoc.v:194930.19-194930.109"
- wire $not$libresoc.v:194930$13424_Y
- attribute \src "libresoc.v:194932.19-194932.107"
- wire $not$libresoc.v:194932$13426_Y
- attribute \src "libresoc.v:194933.19-194933.107"
- wire $not$libresoc.v:194933$13427_Y
- attribute \src "libresoc.v:194934.19-194934.107"
- wire $not$libresoc.v:194934$13428_Y
- attribute \src "libresoc.v:194935.19-194935.107"
- wire $not$libresoc.v:194935$13429_Y
- attribute \src "libresoc.v:194936.19-194936.109"
- wire $not$libresoc.v:194936$13430_Y
- attribute \src "libresoc.v:194940.19-194940.107"
- wire $not$libresoc.v:194940$13434_Y
- attribute \src "libresoc.v:194943.19-194943.107"
- wire $not$libresoc.v:194943$13437_Y
- attribute \src "libresoc.v:194946.19-194946.107"
- wire $not$libresoc.v:194946$13440_Y
- attribute \src "libresoc.v:194947.19-194947.107"
- wire $not$libresoc.v:194947$13441_Y
- attribute \src "libresoc.v:194948.19-194948.107"
- wire $not$libresoc.v:194948$13442_Y
- attribute \src "libresoc.v:194958.18-194958.103"
- wire $not$libresoc.v:194958$13454_Y
- attribute \src "libresoc.v:194960.18-194960.98"
- wire $not$libresoc.v:194960$13456_Y
- attribute \src "libresoc.v:194961.18-194961.103"
- wire $not$libresoc.v:194961$13457_Y
- attribute \src "libresoc.v:194963.18-194963.106"
- wire $not$libresoc.v:194963$13460_Y
- attribute \src "libresoc.v:194964.18-194964.108"
- wire $not$libresoc.v:194964$13461_Y
- attribute \src "libresoc.v:194966.18-194966.101"
- wire $not$libresoc.v:194966$13463_Y
- attribute \src "libresoc.v:194967.18-194967.106"
- wire $not$libresoc.v:194967$13464_Y
- attribute \src "libresoc.v:194968.18-194968.108"
- wire $not$libresoc.v:194968$13465_Y
- attribute \src "libresoc.v:194970.18-194970.101"
- wire $not$libresoc.v:194970$13467_Y
- attribute \src "libresoc.v:194971.18-194971.110"
- wire $not$libresoc.v:194971$13468_Y
- attribute \src "libresoc.v:194973.18-194973.110"
- wire $not$libresoc.v:194973$13470_Y
- attribute \src "libresoc.v:194974.18-194974.110"
- wire $not$libresoc.v:194974$13471_Y
- attribute \src "libresoc.v:194975.18-194975.99"
- wire $not$libresoc.v:194975$13472_Y
- attribute \src "libresoc.v:194976.18-194976.110"
- wire $not$libresoc.v:194976$13473_Y
- attribute \src "libresoc.v:194977.18-194977.99"
- wire $not$libresoc.v:194977$13474_Y
- attribute \src "libresoc.v:194982.18-194982.110"
- wire $not$libresoc.v:194982$13479_Y
- attribute \src "libresoc.v:194988.18-194988.106"
- wire $not$libresoc.v:194988$13485_Y
- attribute \src "libresoc.v:194955.18-194955.110"
- wire $or$libresoc.v:194955$13451_Y
- attribute \src "libresoc.v:194956.18-194956.100"
- wire $or$libresoc.v:194956$13452_Y
- attribute \src "libresoc.v:194938.19-194938.211"
- wire width 64 $pos$libresoc.v:194938$13432_Y
- attribute \src "libresoc.v:194949.19-194949.114"
- wire width 64 $pos$libresoc.v:194949$13444_Y
- attribute \src "libresoc.v:194950.19-194950.113"
- wire width 64 $pos$libresoc.v:194950$13446_Y
- attribute \src "libresoc.v:194962.18-194962.109"
- wire width 64 $pos$libresoc.v:194962$13459_Y
- attribute \src "libresoc.v:194942.19-194942.93"
- wire $reduce_or$libresoc.v:194942$13436_Y
- attribute \src "libresoc.v:194945.19-194945.93"
- wire $reduce_or$libresoc.v:194945$13439_Y
- attribute \src "libresoc.v:194979.18-194979.40"
- wire width 64 $shr$libresoc.v:194979$13476_Y
- attribute \src "libresoc.v:194984.18-194984.40"
- wire width 64 $shr$libresoc.v:194984$13481_Y
- attribute \src "libresoc.v:194987.18-194987.40"
- wire width 64 $shr$libresoc.v:194987$13484_Y
- attribute \src "libresoc.v:194951.19-194951.115"
- wire width 65 $sub$libresoc.v:194951$13447_Y
- attribute \src "libresoc.v:194954.18-194954.101"
- wire width 3 $sub$libresoc.v:194954$13450_Y
- attribute \src "libresoc.v:194980.18-194980.122"
- wire width 4 $ternary$libresoc.v:194980$13477_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$117
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$121
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$123
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$131
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$133
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$135
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$137
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$139
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$141
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- wire \$143
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \$145
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
- wire \$147
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$149
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $4\issue_fsm_state$next[2:0]$13704
+ attribute \src "libresoc.v:193757.3-193786.6"
+ wire $4\msr_read$next[0:0]$13670
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $4\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $4\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $4\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $4\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $4\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $4\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:194153.3-194219.6"
+ wire $4\pc_changed$next[0:0]$13718
+ attribute \src "libresoc.v:194282.3-194348.6"
+ wire $4\sv_changed$next[0:0]$13730
+ attribute \src "libresoc.v:194220.3-194281.6"
+ wire $4\update_svstate[0:0]
+ attribute \src "libresoc.v:193500.3-193567.6"
+ wire width 64 $5\core_data_i[63:0]
+ attribute \src "libresoc.v:193432.3-193499.6"
+ wire width 3 $5\core_wen[2:0]
+ attribute \src "libresoc.v:193028.3-193062.6"
+ wire $5\exec_fsm_state$next[0:0]$13565
+ attribute \src "libresoc.v:193796.3-193849.6"
+ wire width 2 $5\fetch_fsm_state$next[1:0]$13680
+ attribute \src "libresoc.v:194010.3-194090.6"
+ wire width 3 $5\issue_fsm_state$next[2:0]$13705
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $5\new_svstate_dststep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $5\new_svstate_maxvl[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $5\new_svstate_srcstep[6:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $5\new_svstate_subvl[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 2 $5\new_svstate_svstep[1:0]
+ attribute \src "libresoc.v:193932.3-193993.6"
+ wire width 7 $5\new_svstate_vl[6:0]
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$186
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- wire \$151
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
- wire width 3 \$152
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$155
+ wire \$188
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+ wire width 3 \$189
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$192
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$194
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$196
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$198
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$200
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$202
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ wire \$204
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ wire \$206
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366"
+ wire \$208
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$210
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$212
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$214
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$216
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$218
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$220
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- wire \$157
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
- wire width 3 \$158
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$161
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$163
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- wire \$165
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \$167
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 64 \$169
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
- wire width 65 \$171
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
- wire width 65 \$172
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
- wire width 65 \$174
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
- wire width 65 \$175
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
+ wire \$222
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444"
+ wire width 3 \$223
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$226
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$228
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$230
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$232
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$234
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$236
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342"
+ wire width 8 \$238
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342"
+ wire width 8 \$239
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$241
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$243
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$245
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346"
+ wire \$247
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
+ wire width 64 \$249
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
wire width 3 \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441"
+ wire \$251
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ wire \$253
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ wire \$255
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
+ wire width 64 \$257
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
+ wire width 64 \$259
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
wire width 3 \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702"
+ wire width 65 \$261
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702"
+ wire width 65 \$262
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ wire width 65 \$264
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ wire width 65 \$265
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
wire \$32
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$34
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
wire \$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
wire \$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
wire \$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
wire \$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
wire \$60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
- wire width 65 \$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
- wire width 65 \$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- wire \$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ wire \$62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ wire \$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ wire \$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ wire \$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ wire \$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ wire \$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ wire \$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ wire \$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ wire \$86
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- wire \$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- wire \$71
+ wire \$88
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- wire \$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
- wire width 32 \$75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- wire width 7 \$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
- wire width 65 \$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
- wire width 4 \$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
- wire width 65 \$82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- wire \$84
+ wire \$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230"
+ wire width 65 \$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230"
+ wire width 65 \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
- wire width 32 \$86
+ wire width 32 \$95
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- wire width 7 \$87
+ wire width 7 \$96
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
- wire width 32 \$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
- wire width 65 \$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
- wire width 65 \$92
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- wire width 7 \$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- wire \$99
+ wire width 32 \$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire input 342 \TAP_bus__tck
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire output 333 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire input 343 \TAP_bus__tms
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133"
wire output 3 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 392 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 1 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
wire width 8 \core_asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
wire width 8 \core_asmcode$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132"
wire input 4 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90"
wire \core_bigendian_i$10
wire width 3 \core_core_xer_in$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95"
wire \core_corebusy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire \core_coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \core_cr_out_ok
wire width 64 \core_data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \core_data_i$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
- wire width 7 \core_dbg_core_dbg_dststep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31"
- wire width 7 \core_dbg_core_dbg_maxvl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
- wire width 7 \core_dbg_core_dbg_srcstep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27"
- wire width 2 \core_dbg_core_dbg_subvl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26"
- wire width 2 \core_dbg_core_dbg_svstep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
- wire width 7 \core_dbg_core_dbg_vl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire width 64 \core_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire \core_xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire \core_xer_out$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
- wire input 2 \coresync_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
+ wire input 360 \coresync_clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
wire \cu_st__rel_o_dly
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
wire width 7 \cur_cur_maxvl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31"
wire width 7 \cur_cur_maxvl$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
+ wire width 7 \cur_cur_srcstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
+ wire width 7 \cur_cur_srcstep$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27"
wire width 2 \cur_cur_subvl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27"
wire width 7 \cur_cur_vl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \cur_cur_vl$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:657"
wire \d_cr_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:657"
wire \d_cr_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647"
wire \d_reg_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647"
wire \d_reg_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667"
wire \d_xer_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667"
wire \d_xer_delay$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
+ wire width 7 \dbg_core_dbg_core_dbg_dststep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31"
+ wire width 7 \dbg_core_dbg_core_dbg_maxvl
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
+ wire width 7 \dbg_core_dbg_core_dbg_srcstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27"
+ wire width 2 \dbg_core_dbg_core_dbg_subvl
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26"
+ wire width 2 \dbg_core_dbg_core_dbg_svstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
+ wire width 7 \dbg_core_dbg_core_dbg_vl
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
wire width 64 \dbg_core_dbg_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire width 64 \dbg_core_dbg_pc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99"
wire \dbg_core_rst_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
wire \dbg_core_stop_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104"
wire \dbg_core_stopped_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
wire \dbg_d_cr_ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
wire width 64 \dbg_d_cr_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
- wire \dbg_d_cr_req
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
- wire \dbg_d_gpr_ack
+ wire \dbg_d_cr_req
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
- wire width 7 \dbg_d_gpr_addr
+ wire \dbg_d_gpr_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
+ wire width 7 \dbg_d_gpr_addr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
wire width 64 \dbg_d_gpr_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
- wire \dbg_d_gpr_req
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
+ wire \dbg_d_gpr_req
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
wire \dbg_d_xer_ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
wire width 64 \dbg_d_xer_data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
wire \dbg_d_xer_req
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63"
wire \dbg_dmi_ack_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
wire width 4 \dbg_dmi_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
- wire width 4 \dbg_dmi_addr_i$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
+ wire width 4 \dbg_dmi_addr_i$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
wire width 64 \dbg_dmi_din
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
- wire width 64 \dbg_dmi_din$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
- wire width 64 \dbg_dmi_dout
+ wire width 64 \dbg_dmi_din$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
+ wire width 64 \dbg_dmi_dout
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
wire \dbg_dmi_req_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
- wire \dbg_dmi_req_i$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
+ wire \dbg_dmi_req_i$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
wire \dbg_dmi_we_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
wire \dbg_dmi_we_i$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
wire \dbg_terminate_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 9 \dbus__ack
wire width 8 \dec2_cr_wr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \dec2_cr_wr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
- wire width 7 \dec2_cur_cur_srcstep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29"
- wire width 7 \dec2_cur_cur_srcstep$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire width 64 \dec2_cur_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire width 64 \dec2_cur_pc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire width 64 \dec2_cur_pc$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 9 \dec2_dec_svp64__extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 9 \dec2_dec_svp64__extra$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 7 \dec2_ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 \dec2_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
wire \dec2_xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__elwidth
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__elwidth$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__ewsrc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__ewsrc$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 3 \dec_svp64__mask
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 3 \dec_svp64__mask$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire \dec_svp64__mmode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire \dec_svp64__mmode$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 5 \dec_svp64__mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 5 \dec_svp64__mode$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__subvl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
- wire width 2 \dec_svp64__subvl$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
wire width 2 \delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
wire width 2 \delay$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 179 \eint_0__core__i
wire output 181 \eint_2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 26 \eint_2__pad__i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
wire \exec_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
wire \exec_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593"
wire \exec_insn_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592"
wire \exec_insn_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597"
wire \exec_pc_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:541"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596"
wire \exec_pc_valid_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
wire width 2 \fetch_fsm_state
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
wire width 2 \fetch_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166"
- wire width 32 \fetch_insn_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589"
wire \fetch_insn_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:533"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588"
wire \fetch_insn_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585"
wire \fetch_pc_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:529"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584"
wire \fetch_pc_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
wire width 2 \fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
wire width 2 \fsm_state$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 188 \gpio_e10__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire output 20 \ibus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire output 376 \icp_wb__ack
+ wire output 344 \icp_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 28 input 382 \icp_wb__adr
+ wire width 28 input 350 \icp_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 377 \icp_wb__cyc
+ wire input 345 \icp_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 output 378 \icp_wb__dat_r
+ wire width 32 output 346 \icp_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 input 379 \icp_wb__dat_w
+ wire width 32 input 347 \icp_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 4 input 383 \icp_wb__sel
+ wire width 4 input 351 \icp_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 380 \icp_wb__stb
+ wire input 348 \icp_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 381 \icp_wb__we
+ wire input 349 \icp_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire output 389 \ics_wb__ack
+ wire output 357 \ics_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 28 input 384 \ics_wb__adr
+ wire width 28 input 352 \ics_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 386 \ics_wb__cyc
+ wire input 354 \ics_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 output 388 \ics_wb__dat_r
+ wire width 32 output 356 \ics_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 input 390 \ics_wb__dat_w
+ wire width 32 input 358 \ics_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 387 \ics_wb__stb
+ wire input 355 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 391 \ics_wb__we
+ wire input 359 \ics_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
wire width 48 \imem_a_pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
wire \imem_f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire \imem_wb_icache_en
- attribute \src "libresoc.v:192552.7-192552.15"
+ attribute \src "libresoc.v:189535.7-189535.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:477"
- wire \insn_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
- wire width 16 input 385 \int_level_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ wire width 16 input 353 \int_level_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ wire \is_last
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
wire width 3 \issue_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
wire width 3 \issue_fsm_state$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire \jtag_dmi0__ack_o
wire output 337 \jtag_wb__stb
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire output 338 \jtag_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95"
- wire \jtag_wb_sram_en
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 75 \mspi0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 239 \mtwi_sda__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 240 \mtwi_sda__pad__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700"
wire width 64 \new_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 \new_svstate_dststep
wire width 2 \new_svstate_svstep
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \new_svstate_vl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717"
wire width 64 \new_tb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
+ wire width 7 \next_srcstep
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571"
wire width 64 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571"
wire width 64 \nia$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535"
wire width 64 \pc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531"
wire \pc_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531"
wire \pc_changed$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 64 input 7 \pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 6 \pc_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129"
wire width 64 output 5 \pc_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536"
wire \pc_ok_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536"
wire \pc_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:502"
wire \por_clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 87 \pwm_0__core__o
wire input 88 \pwm_1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 243 \pwm_1__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 2 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 92 \sd0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 146 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 301 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire \sram4k_0_enable
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 346 \sram4k_0_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 347 \sram4k_0_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 344 \sram4k_0_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 348 \sram4k_0_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 349 \sram4k_0_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 351 \sram4k_0_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 345 \sram4k_0_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 350 \sram4k_0_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire \sram4k_1_enable
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 354 \sram4k_1_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 355 \sram4k_1_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 352 \sram4k_1_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 356 \sram4k_1_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 357 \sram4k_1_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 359 \sram4k_1_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 353 \sram4k_1_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 358 \sram4k_1_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire \sram4k_2_enable
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 362 \sram4k_2_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 363 \sram4k_2_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 360 \sram4k_2_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 364 \sram4k_2_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 365 \sram4k_2_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 367 \sram4k_2_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 361 \sram4k_2_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 366 \sram4k_2_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16"
- wire \sram4k_3_enable
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire output 370 \sram4k_3_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 9 input 371 \sram4k_3_wb__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 368 \sram4k_3_wb__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 output 372 \sram4k_3_wb__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 64 input 373 \sram4k_3_wb__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire width 8 input 375 \sram4k_3_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 369 \sram4k_3_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
- wire input 374 \sram4k_3_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532"
wire \sv_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532"
wire \sv_changed$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:21"
- wire \svp64_bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:19"
- wire \svp64_is_svp64_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:18"
- wire width 32 \svp64_raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:20"
- wire width 24 \svp64_svp64_rm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549"
wire width 64 \svstate
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 32 \svstate_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire \svstate_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:550"
wire \svstate_ok_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:550"
wire \svstate_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507"
wire \ti_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
wire \update_svstate
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire \xics_icp_core_irq_o
wire width 8 \xics_ics_icp_o_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
- cell $add $add$libresoc.v:194952$13448
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241"
+ cell $add $add$libresoc.v:191878$13258
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 65
+ connect \A \dec2_cur_pc
+ connect \B 3'100
+ connect \Y $add$libresoc.v:191878$13258_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342"
+ cell $add $add$libresoc.v:191948$13325
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 8
+ connect \A \cur_cur_srcstep
+ connect \B 1'1
+ connect \Y $add$libresoc.v:191948$13325_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ cell $add $add$libresoc.v:191960$13339
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:194952$13448_Y
+ connect \Y $add$libresoc.v:191960$13339_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
- cell $add $add$libresoc.v:194972$13469
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230"
+ cell $add $add$libresoc.v:191994$13372
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:194972$13469_Y
+ connect \Y $add$libresoc.v:191994$13372_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
- cell $add $add$libresoc.v:194981$13478
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191883$13263
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 65
- connect \A \dec2_cur_pc
- connect \B \$80
- connect \Y $add$libresoc.v:194981$13478_Y
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$106
+ connect \B \$108
+ connect \Y $and$libresoc.v:191883$13263_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
- cell $add $add$libresoc.v:194985$13482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191886$13266
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 65
- connect \A \dec2_cur_pc
- connect \B 3'100
- connect \Y $add$libresoc.v:194985$13482_Y
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$112
+ connect \B \$114
+ connect \Y $and$libresoc.v:191886$13266_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $and $and$libresoc.v:194916$13410
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191892$13271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$97
- connect \B \$99
- connect \Y $and$libresoc.v:194916$13410_Y
+ connect \A \$124
+ connect \B \$126
+ connect \Y $and$libresoc.v:191892$13271_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194919$13413
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191895$13274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$103
- connect \B \$105
- connect \Y $and$libresoc.v:194919$13413_Y
+ connect \A \$130
+ connect \B \$132
+ connect \Y $and$libresoc.v:191895$13274_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $and $and$libresoc.v:194922$13416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $and $and$libresoc.v:191898$13276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$109
- connect \B \$111
- connect \Y $and$libresoc.v:194922$13416_Y
+ connect \A \$136
+ connect \B \$138
+ connect \Y $and$libresoc.v:191898$13276_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194925$13419
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191901$13279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$115
- connect \B \$117
- connect \Y $and$libresoc.v:194925$13419_Y
+ connect \A \$142
+ connect \B \$144
+ connect \Y $and$libresoc.v:191901$13279_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $and $and$libresoc.v:194928$13422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191906$13284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$121
- connect \B \$123
- connect \Y $and$libresoc.v:194928$13422_Y
+ connect \A \$152
+ connect \B \$154
+ connect \Y $and$libresoc.v:191906$13284_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194931$13425
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191909$13287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$127
- connect \B \$129
- connect \Y $and$libresoc.v:194931$13425_Y
+ connect \A \$158
+ connect \B \$160
+ connect \Y $and$libresoc.v:191909$13287_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191912$13290
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$164
+ connect \B \$166
+ connect \Y $and$libresoc.v:191912$13290_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194937$13431
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191915$13293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$139
- connect \B \$141
- connect \Y $and$libresoc.v:194937$13431_Y
+ connect \A \$170
+ connect \B \$172
+ connect \Y $and$libresoc.v:191915$13293_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
- cell $and $and$libresoc.v:194941$13435
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191918$13296
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$176
+ connect \B \$178
+ connect \Y $and$libresoc.v:191918$13296_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191921$13299
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$182
+ connect \B \$184
+ connect \Y $and$libresoc.v:191921$13299_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+ cell $and $and$libresoc.v:191922$13300
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 3
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
- connect \B 3'100
- connect \Y $and$libresoc.v:194941$13435_Y
+ connect \B 1'1
+ connect \Y $and$libresoc.v:191922$13300_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
- cell $and $and$libresoc.v:194944$13438
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191926$13304
parameter \A_SIGNED 0
- parameter \A_WIDTH 3
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$192
+ connect \B \$194
+ connect \Y $and$libresoc.v:191926$13304_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191929$13307
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$198
+ connect \B \$200
+ connect \Y $and$libresoc.v:191929$13307_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191935$13312
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$210
+ connect \B \$212
+ connect \Y $and$libresoc.v:191935$13312_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191938$13315
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$216
+ connect \B \$218
+ connect \Y $and$libresoc.v:191938$13315_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444"
+ cell $and $and$libresoc.v:191939$13316
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
- connect \B 1'1
- connect \Y $and$libresoc.v:194944$13438_Y
+ connect \B 3'100
+ connect \Y $and$libresoc.v:191939$13316_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191943$13320
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$226
+ connect \B \$228
+ connect \Y $and$libresoc.v:191943$13320_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191946$13323
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$232
+ connect \B \$234
+ connect \Y $and$libresoc.v:191946$13323_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191951$13328
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$241
+ connect \B \$243
+ connect \Y $and$libresoc.v:191951$13328_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:194959$13455
+ cell $and $and$libresoc.v:191966$13345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_cu_st__rel_o
connect \B \$34
- connect \Y $and$libresoc.v:194959$13455_Y
+ connect \Y $and$libresoc.v:191966$13345_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194965$13462
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191972$13352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:194965$13462_Y
+ connect \Y $and$libresoc.v:191972$13352_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $and $and$libresoc.v:194969$13466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $and $and$libresoc.v:191975$13354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$52
- connect \B \$54
- connect \Y $and$libresoc.v:194969$13466_Y
+ connect \A \$50
+ connect \B \$52
+ connect \Y $and$libresoc.v:191975$13354_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191978$13357
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$56
+ connect \B \$58
+ connect \Y $and$libresoc.v:191978$13357_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $and $and$libresoc.v:191983$13362
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$66
+ connect \B \$68
+ connect \Y $and$libresoc.v:191983$13362_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $and $and$libresoc.v:191986$13364
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$72
+ connect \B \$74
+ connect \Y $and$libresoc.v:191986$13364_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $and $and$libresoc.v:191989$13367
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \$78
+ connect \B \$80
+ connect \Y $and$libresoc.v:191989$13367_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $eq $eq$libresoc.v:191897$13275
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \cur_cur_vl
+ connect \B 1'0
+ connect \Y $eq$libresoc.v:191897$13275_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346"
+ cell $eq $eq$libresoc.v:191952$13329
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \next_srcstep
+ connect \B \cur_cur_vl
+ connect \Y $eq$libresoc.v:191952$13329_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $eq $eq$libresoc.v:191974$13353
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \cur_cur_vl
+ connect \B 1'0
+ connect \Y $eq$libresoc.v:191974$13353_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ cell $eq $eq$libresoc.v:191985$13363
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \cur_cur_vl
+ connect \B 1'0
+ connect \Y $eq$libresoc.v:191985$13363_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:194949$13443
+ cell $pos $extend$libresoc.v:191957$13334
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \core_full_rd2__data_o
- connect \Y $extend$libresoc.v:194949$13443_Y
+ connect \Y $extend$libresoc.v:191957$13334_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:194950$13445
+ cell $pos $extend$libresoc.v:191958$13336
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \core_full_rd__data_o
- connect \Y $extend$libresoc.v:194950$13445_Y
+ connect \Y $extend$libresoc.v:191958$13336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:194962$13458
+ cell $pos $extend$libresoc.v:191969$13348
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \svstate_i
- connect \Y $extend$libresoc.v:194962$13458_Y
+ connect \Y $extend$libresoc.v:191969$13348_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:194978$13475
+ cell $mul $mul$libresoc.v:191879$13259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 7
- connect \A \dec2_cur_pc [2]
+ connect \A \$100 [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:194978$13475_Y
+ connect \Y $mul$libresoc.v:191879$13259_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:194983$13480
+ cell $mul $mul$libresoc.v:191995$13373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:194983$13480_Y
+ connect \Y $mul$libresoc.v:191995$13373_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:194986$13483
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509"
+ cell $ne $ne$libresoc.v:191947$13324
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 2
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 7
- connect \A \$91 [2]
- connect \B 6'100000
- connect \Y $mul$libresoc.v:194986$13483_Y
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \delay
+ connect \B 1'0
+ connect \Y $ne$libresoc.v:191947$13324_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
- cell $ne $ne$libresoc.v:194939$13433
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441"
+ cell $ne $ne$libresoc.v:191954$13331
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_core_insn_type
connect \B 7'0000001
- connect \Y $ne$libresoc.v:194939$13433_Y
+ connect \Y $ne$libresoc.v:191954$13331_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
- cell $ne $ne$libresoc.v:194953$13449
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+ cell $ne $ne$libresoc.v:191964$13343
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \delay
- connect \B 1'0
- connect \Y $ne$libresoc.v:194953$13449_Y
+ connect \B \$30
+ connect \Y $ne$libresoc.v:191964$13343_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
- cell $ne $ne$libresoc.v:194957$13453
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191881$13261
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \delay
- connect \B \$30
- connect \Y $ne$libresoc.v:194957$13453_Y
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191881$13261_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191882$13262
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191882$13262_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191884$13264
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191884$13264_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191885$13265
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191885$13265_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191890$13269
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191890$13269_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191891$13270
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191891$13270_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191893$13272
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191893$13272_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191894$13273
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191894$13273_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191899$13277
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191899$13277_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191900$13278
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191900$13278_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191904$13282
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191904$13282_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191905$13283
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191905$13283_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191907$13285
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191907$13285_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191908$13286
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191908$13286_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191910$13288
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191910$13288_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191911$13289
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191911$13289_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191913$13291
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191913$13291_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191914$13292
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191914$13292_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191916$13294
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191916$13294_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191917$13295
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191917$13295_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191919$13297
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191919$13297_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191920$13298
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191920$13298_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191924$13302
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191924$13302_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194915$13409
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191925$13303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194915$13409_Y
+ connect \Y $not$libresoc.v:191925$13303_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194917$13411
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191927$13305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194917$13411_Y
+ connect \Y $not$libresoc.v:191927$13305_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194918$13412
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191928$13306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194918$13412_Y
+ connect \Y $not$libresoc.v:191928$13306_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194920$13414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191933$13310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194920$13414_Y
+ connect \Y $not$libresoc.v:191933$13310_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194921$13415
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191934$13311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194921$13415_Y
+ connect \Y $not$libresoc.v:191934$13311_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194923$13417
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191936$13313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194923$13417_Y
+ connect \Y $not$libresoc.v:191936$13313_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194924$13418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191937$13314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194924$13418_Y
+ connect \Y $not$libresoc.v:191937$13314_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194926$13420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191941$13318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194926$13420_Y
+ connect \Y $not$libresoc.v:191941$13318_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194927$13421
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191942$13319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194927$13421_Y
+ connect \Y $not$libresoc.v:191942$13319_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194929$13423
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191944$13321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194929$13423_Y
+ connect \Y $not$libresoc.v:191944$13321_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194930$13424
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191945$13322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194930$13424_Y
+ connect \Y $not$libresoc.v:191945$13322_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194932$13426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191949$13326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194932$13426_Y
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191949$13326_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194933$13427
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191950$13327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194933$13427_Y
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191950$13327_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194934$13428
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ cell $not $not$libresoc.v:191955$13332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194934$13428_Y
+ connect \Y $not$libresoc.v:191955$13332_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194935$13429
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ cell $not $not$libresoc.v:191956$13333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194935$13429_Y
+ connect \A \core_corebusy_o
+ connect \Y $not$libresoc.v:191956$13333_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194936$13430
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
+ cell $not $not$libresoc.v:191965$13344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194936$13430_Y
+ connect \A \cu_st__rel_o_dly
+ connect \Y $not$libresoc.v:191965$13344_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194940$13434
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537"
+ cell $not $not$libresoc.v:191967$13346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194940$13434_Y
+ connect \A \pc_i_ok
+ connect \Y $not$libresoc.v:191967$13346_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194943$13437
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551"
+ cell $not $not$libresoc.v:191968$13347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194943$13437_Y
+ connect \A \svstate_i_ok
+ connect \Y $not$libresoc.v:191968$13347_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194946$13440
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191970$13350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194946$13440_Y
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191970$13350_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194947$13441
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191971$13351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194947$13441_Y
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191971$13351_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- cell $not $not$libresoc.v:194948$13442
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191976$13355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:194948$13442_Y
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191976$13355_Y
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:194958$13454
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191977$13356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \cu_st__rel_o_dly
- connect \Y $not$libresoc.v:194958$13454_Y
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191977$13356_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
- cell $not $not$libresoc.v:194960$13456
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191981$13360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \pc_i_ok
- connect \Y $not$libresoc.v:194960$13456_Y
+ connect \A \dbg_core_stop_o
+ connect \Y $not$libresoc.v:191981$13360_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
- cell $not $not$libresoc.v:194961$13457
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ cell $not $not$libresoc.v:191982$13361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svstate_i_ok
- connect \Y $not$libresoc.v:194961$13457_Y
+ connect \A \core_coresync_rst
+ connect \Y $not$libresoc.v:191982$13361_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194963$13460
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191987$13365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194963$13460_Y
+ connect \Y $not$libresoc.v:191987$13365_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194964$13461
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ cell $not $not$libresoc.v:191988$13366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194964$13461_Y
+ connect \Y $not$libresoc.v:191988$13366_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
- cell $not $not$libresoc.v:194966$13463
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
+ cell $not $not$libresoc.v:191992$13370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \pc_changed
- connect \Y $not$libresoc.v:194966$13463_Y
+ connect \A \msr_read
+ connect \Y $not$libresoc.v:191992$13370_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194967$13464
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
+ cell $not $not$libresoc.v:191993$13371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194967$13464_Y
+ connect \A \msr_read
+ connect \Y $not$libresoc.v:191993$13371_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- cell $not $not$libresoc.v:194968$13465
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ cell $or $or$libresoc.v:191887$13267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:194968$13465_Y
+ connect \A \pc_changed
+ connect \B \sv_changed
+ connect \Y $or$libresoc.v:191887$13267_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
- cell $not $not$libresoc.v:194970$13467
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ cell $or $or$libresoc.v:191888$13268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \pc_changed
- connect \Y $not$libresoc.v:194970$13467_Y
+ connect \A 1'1
+ connect \B \is_last
+ connect \Y $or$libresoc.v:191888$13268_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- cell $not $not$libresoc.v:194971$13468
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ cell $or $or$libresoc.v:191902$13280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svp64_is_svp64_mode
- connect \Y $not$libresoc.v:194971$13468_Y
+ connect \A \pc_changed
+ connect \B \sv_changed
+ connect \Y $or$libresoc.v:191902$13280_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- cell $not $not$libresoc.v:194973$13470
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ cell $or $or$libresoc.v:191903$13281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svp64_is_svp64_mode
- connect \Y $not$libresoc.v:194973$13470_Y
+ connect \A 1'1
+ connect \B \is_last
+ connect \Y $or$libresoc.v:191903$13281_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- cell $not $not$libresoc.v:194974$13471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ cell $or $or$libresoc.v:191930$13308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svp64_is_svp64_mode
- connect \Y $not$libresoc.v:194974$13471_Y
+ connect \A \pc_changed
+ connect \B \sv_changed
+ connect \Y $or$libresoc.v:191930$13308_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- cell $not $not$libresoc.v:194975$13472
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ cell $or $or$libresoc.v:191931$13309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \msr_read
- connect \Y $not$libresoc.v:194975$13472_Y
+ connect \A 1'1
+ connect \B \is_last
+ connect \Y $or$libresoc.v:191931$13309_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- cell $not $not$libresoc.v:194976$13473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+ cell $or $or$libresoc.v:191962$13341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svp64_is_svp64_mode
- connect \Y $not$libresoc.v:194976$13473_Y
+ connect \A 1'0
+ connect \B \dbg_core_rst_o
+ connect \Y $or$libresoc.v:191962$13341_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- cell $not $not$libresoc.v:194977$13474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+ cell $or $or$libresoc.v:191963$13342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \msr_read
- connect \Y $not$libresoc.v:194977$13474_Y
+ connect \A \$28
+ connect \B \rst
+ connect \Y $or$libresoc.v:191963$13342_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- cell $not $not$libresoc.v:194982$13479
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ cell $or $or$libresoc.v:191979$13358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \svp64_is_svp64_mode
- connect \Y $not$libresoc.v:194982$13479_Y
+ connect \A \pc_changed
+ connect \B \sv_changed
+ connect \Y $or$libresoc.v:191979$13358_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- cell $not $not$libresoc.v:194988$13485
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ cell $or $or$libresoc.v:191980$13359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:194988$13485_Y
+ connect \A 1'1
+ connect \B \is_last
+ connect \Y $or$libresoc.v:191980$13359_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
- cell $or $or$libresoc.v:194955$13451
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ cell $or $or$libresoc.v:191990$13368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A 1'0
- connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:194955$13451_Y
+ connect \A \pc_changed
+ connect \B \sv_changed
+ connect \Y $or$libresoc.v:191990$13368_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
- cell $or $or$libresoc.v:194956$13452
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357"
+ cell $or $or$libresoc.v:191991$13369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \$28
- connect \B \rst
- connect \Y $or$libresoc.v:194956$13452_Y
+ connect \A 1'1
+ connect \B \is_last
+ connect \Y $or$libresoc.v:191991$13369_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:194938$13432
+ cell $pos $pos$libresoc.v:191953$13330
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
- connect \Y $pos$libresoc.v:194938$13432_Y
+ connect \Y $pos$libresoc.v:191953$13330_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:194949$13444
+ cell $pos $pos$libresoc.v:191957$13335
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:194949$13443_Y
- connect \Y $pos$libresoc.v:194949$13444_Y
+ connect \A $extend$libresoc.v:191957$13334_Y
+ connect \Y $pos$libresoc.v:191957$13335_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:194950$13446
+ cell $pos $pos$libresoc.v:191958$13337
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:194950$13445_Y
- connect \Y $pos$libresoc.v:194950$13446_Y
+ connect \A $extend$libresoc.v:191958$13336_Y
+ connect \Y $pos$libresoc.v:191958$13337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:194962$13459
+ cell $pos $pos$libresoc.v:191969$13349
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:194962$13458_Y
- connect \Y $pos$libresoc.v:194962$13459_Y
+ connect \A $extend$libresoc.v:191969$13348_Y
+ connect \Y $pos$libresoc.v:191969$13349_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:194942$13436
+ cell $reduce_or $reduce_or$libresoc.v:191923$13301
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \$152
- connect \Y $reduce_or$libresoc.v:194942$13436_Y
+ connect \A \$189
+ connect \Y $reduce_or$libresoc.v:191923$13301_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:194945$13439
+ cell $reduce_or $reduce_or$libresoc.v:191940$13317
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \$158
- connect \Y $reduce_or$libresoc.v:194945$13439_Y
- end
- attribute \src "libresoc.v:194979.18-194979.40"
- cell $shr $shr$libresoc.v:194979$13476
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 64
- connect \A \imem_f_instr_o
- connect \B \$76
- connect \Y $shr$libresoc.v:194979$13476_Y
+ connect \A \$223
+ connect \Y $reduce_or$libresoc.v:191940$13317_Y
end
- attribute \src "libresoc.v:194984.18-194984.40"
- cell $shr $shr$libresoc.v:194984$13481
+ attribute \src "libresoc.v:191880.18-191880.41"
+ cell $shr $shr$libresoc.v:191880$13260
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
- connect \B \$87
- connect \Y $shr$libresoc.v:194984$13481_Y
+ connect \B \$103
+ connect \Y $shr$libresoc.v:191880$13260_Y
end
- attribute \src "libresoc.v:194987.18-194987.40"
- cell $shr $shr$libresoc.v:194987$13484
+ attribute \src "libresoc.v:191996.18-191996.40"
+ cell $shr $shr$libresoc.v:191996$13374
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
- connect \B \$94
- connect \Y $shr$libresoc.v:194987$13484_Y
+ connect \B \$96
+ connect \Y $shr$libresoc.v:191996$13374_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
- cell $sub $sub$libresoc.v:194951$13447
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702"
+ cell $sub $sub$libresoc.v:191959$13338
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:194951$13447_Y
+ connect \Y $sub$libresoc.v:191959$13338_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
- cell $sub $sub$libresoc.v:194954$13450
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ cell $sub $sub$libresoc.v:191961$13340
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:194954$13450_Y
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
- cell $mux $ternary$libresoc.v:194980$13477
- parameter \WIDTH 4
- connect \A 4'0100
- connect \B 4'1000
- connect \S \svp64_is_svp64_mode
- connect \Y $ternary$libresoc.v:194980$13477_Y
+ connect \Y $sub$libresoc.v:191961$13340_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195209.8-195306.4"
+ attribute \src "libresoc.v:192203.8-192300.4"
cell \core \core
connect \bigendian_i \core_bigendian_i$10
connect \cia__data_o \core_cia__data_o
connect \wen$10 \core_wen$11
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195307.7-195332.4"
+ attribute \src "libresoc.v:192301.7-192332.4"
cell \dbg \dbg
connect \clk \clk
+ connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep
+ connect \core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_maxvl
+ connect \core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_srcstep
+ connect \core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_subvl
+ connect \core_dbg_core_dbg_svstep \dbg_core_dbg_core_dbg_svstep
+ connect \core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_vl
connect \core_dbg_msr \dbg_core_dbg_msr
connect \core_dbg_pc \dbg_core_dbg_pc
connect \core_rst_o \dbg_core_rst_o
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195333.8-195401.4"
+ attribute \src "libresoc.v:192333.8-192399.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \cr_rd_ok \dec2_cr_rd_ok
connect \cr_wr \dec2_cr_wr
connect \cr_wr_ok \dec2_cr_wr_ok
- connect \cur_cur_srcstep \dec2_cur_cur_srcstep
connect \cur_dec \dec2_cur_dec
connect \cur_eint \dec2_cur_eint
connect \cur_msr \dec2_cur_msr
connect \cur_pc \dec2_cur_pc
- connect \dec_svp64__extra \dec2_dec_svp64__extra
connect \ea \dec2_ea
connect \ea_ok \dec2_ea_ok
connect \exc_$signal \dec2_exc_$signal
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195402.8-195418.4"
+ attribute \src "libresoc.v:192400.8-192416.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195419.8-195751.4"
+ attribute \src "libresoc.v:192417.8-192748.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \sdr_we_n__pad__o \sdr_we_n__pad__o
connect \wb_dcache_en \core_wb_dcache_en
connect \wb_icache_en \imem_wb_icache_en
- connect \wb_sram_en \jtag_wb_sram_en
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:195752.12-195764.4"
- cell \sram4k_0 \sram4k_0
- connect \clk \clk
- connect \enable \sram4k_0_enable
- connect \rst \rst
- connect \sram4k_0_wb__ack \sram4k_0_wb__ack
- connect \sram4k_0_wb__adr \sram4k_0_wb__adr
- connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc
- connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r
- connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w
- connect \sram4k_0_wb__sel \sram4k_0_wb__sel
- connect \sram4k_0_wb__stb \sram4k_0_wb__stb
- connect \sram4k_0_wb__we \sram4k_0_wb__we
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:195765.12-195777.4"
- cell \sram4k_1 \sram4k_1
- connect \clk \clk
- connect \enable \sram4k_1_enable
- connect \rst \rst
- connect \sram4k_1_wb__ack \sram4k_1_wb__ack
- connect \sram4k_1_wb__adr \sram4k_1_wb__adr
- connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc
- connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r
- connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w
- connect \sram4k_1_wb__sel \sram4k_1_wb__sel
- connect \sram4k_1_wb__stb \sram4k_1_wb__stb
- connect \sram4k_1_wb__we \sram4k_1_wb__we
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:195778.12-195790.4"
- cell \sram4k_2 \sram4k_2
- connect \clk \clk
- connect \enable \sram4k_2_enable
- connect \rst \rst
- connect \sram4k_2_wb__ack \sram4k_2_wb__ack
- connect \sram4k_2_wb__adr \sram4k_2_wb__adr
- connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc
- connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r
- connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w
- connect \sram4k_2_wb__sel \sram4k_2_wb__sel
- connect \sram4k_2_wb__stb \sram4k_2_wb__stb
- connect \sram4k_2_wb__we \sram4k_2_wb__we
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:195791.12-195803.4"
- cell \sram4k_3 \sram4k_3
- connect \clk \clk
- connect \enable \sram4k_3_enable
- connect \rst \rst
- connect \sram4k_3_wb__ack \sram4k_3_wb__ack
- connect \sram4k_3_wb__adr \sram4k_3_wb__adr
- connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc
- connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r
- connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w
- connect \sram4k_3_wb__sel \sram4k_3_wb__sel
- connect \sram4k_3_wb__stb \sram4k_3_wb__stb
- connect \sram4k_3_wb__we \sram4k_3_wb__we
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195804.9-195809.4"
- cell \svp64 \svp64
- connect \bigendian \svp64_bigendian
- connect \is_svp64_mode \svp64_is_svp64_mode
- connect \raw_opcode_in \svp64_raw_opcode_in
- connect \svp64_rm \svp64_svp64_rm
- end
- attribute \module_not_derived 1
- attribute \src "libresoc.v:195810.12-195824.4"
+ attribute \src "libresoc.v:192749.12-192763.4"
cell \xics_icp \xics_icp
connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \rst \rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195825.12-195838.4"
+ attribute \src "libresoc.v:192764.12-192777.4"
cell \xics_ics \xics_ics
connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \int_level_i \int_level_i
connect \rst \rst
end
- attribute \src "libresoc.v:192552.7-192552.20"
- process $proc$libresoc.v:192552$14201
+ attribute \src "libresoc.v:189535.7-189535.20"
+ process $proc$libresoc.v:189535$13948
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:192726.13-192726.33"
- process $proc$libresoc.v:192726$14202
+ attribute \src "libresoc.v:189799.13-189799.33"
+ process $proc$libresoc.v:189799$13949
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:192732.7-192732.35"
- process $proc$libresoc.v:192732$14203
+ attribute \src "libresoc.v:189805.7-189805.35"
+ process $proc$libresoc.v:189805$13950
assign { } { }
- assign $0\core_bigendian_i$10[0:0]$14204 1'0
+ assign $0\core_bigendian_i$10[0:0]$13951 1'0
sync always
sync init
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14204
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13951
end
- attribute \src "libresoc.v:192740.14-192740.55"
- process $proc$libresoc.v:192740$14205
+ attribute \src "libresoc.v:189813.14-189813.55"
+ process $proc$libresoc.v:189813$13952
assign { } { }
assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_cia $1\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:192744.13-192744.41"
- process $proc$libresoc.v:192744$14206
+ attribute \src "libresoc.v:189817.13-189817.41"
+ process $proc$libresoc.v:189817$13953
assign { } { }
assign $1\core_core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:192748.7-192748.37"
- process $proc$libresoc.v:192748$14207
+ attribute \src "libresoc.v:189821.7-189821.37"
+ process $proc$libresoc.v:189821$13954
assign { } { }
assign $1\core_core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:192752.13-192752.41"
- process $proc$libresoc.v:192752$14208
+ attribute \src "libresoc.v:189825.13-189825.41"
+ process $proc$libresoc.v:189825$13955
assign { } { }
assign $1\core_core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:192756.7-192756.42"
- process $proc$libresoc.v:192756$14209
+ attribute \src "libresoc.v:189829.7-189829.42"
+ process $proc$libresoc.v:189829$13956
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$14210 1'0
+ assign $0\core_core_core_exc_$signal[0:0]$13957 1'0
sync always
sync init
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14210
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13957
end
- attribute \src "libresoc.v:192758.7-192758.44"
- process $proc$libresoc.v:192758$14211
+ attribute \src "libresoc.v:189831.7-189831.44"
+ process $proc$libresoc.v:189831$13958
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$14212 1'0
+ assign $0\core_core_core_exc_$signal$3[0:0]$13959 1'0
sync always
sync init
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14212
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13959
end
- attribute \src "libresoc.v:192762.7-192762.44"
- process $proc$libresoc.v:192762$14213
+ attribute \src "libresoc.v:189835.7-189835.44"
+ process $proc$libresoc.v:189835$13960
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$14214 1'0
+ assign $0\core_core_core_exc_$signal$4[0:0]$13961 1'0
sync always
sync init
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14214
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13961
end
- attribute \src "libresoc.v:192766.7-192766.44"
- process $proc$libresoc.v:192766$14215
+ attribute \src "libresoc.v:189839.7-189839.44"
+ process $proc$libresoc.v:189839$13962
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$14216 1'0
+ assign $0\core_core_core_exc_$signal$5[0:0]$13963 1'0
sync always
sync init
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14216
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13963
end
- attribute \src "libresoc.v:192770.7-192770.44"
- process $proc$libresoc.v:192770$14217
+ attribute \src "libresoc.v:189843.7-189843.44"
+ process $proc$libresoc.v:189843$13964
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$14218 1'0
+ assign $0\core_core_core_exc_$signal$6[0:0]$13965 1'0
sync always
sync init
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14218
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13965
end
- attribute \src "libresoc.v:192774.7-192774.44"
- process $proc$libresoc.v:192774$14219
+ attribute \src "libresoc.v:189847.7-189847.44"
+ process $proc$libresoc.v:189847$13966
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$14220 1'0
+ assign $0\core_core_core_exc_$signal$7[0:0]$13967 1'0
sync always
sync init
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14220
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13967
end
- attribute \src "libresoc.v:192778.7-192778.44"
- process $proc$libresoc.v:192778$14221
+ attribute \src "libresoc.v:189851.7-189851.44"
+ process $proc$libresoc.v:189851$13968
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$14222 1'0
+ assign $0\core_core_core_exc_$signal$8[0:0]$13969 1'0
sync always
sync init
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14222
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13969
end
- attribute \src "libresoc.v:192782.7-192782.44"
- process $proc$libresoc.v:192782$14223
+ attribute \src "libresoc.v:189855.7-189855.44"
+ process $proc$libresoc.v:189855$13970
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$14224 1'0
+ assign $0\core_core_core_exc_$signal$9[0:0]$13971 1'0
sync always
sync init
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14224
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13971
end
- attribute \src "libresoc.v:192802.14-192802.47"
- process $proc$libresoc.v:192802$14225
+ attribute \src "libresoc.v:189875.14-189875.47"
+ process $proc$libresoc.v:189875$13972
assign { } { }
assign $1\core_core_core_fn_unit[12:0] 13'0000000000000
sync always
sync init
update \core_core_core_fn_unit $1\core_core_core_fn_unit[12:0]
end
- attribute \src "libresoc.v:192810.13-192810.46"
- process $proc$libresoc.v:192810$14226
+ attribute \src "libresoc.v:189883.13-189883.46"
+ process $proc$libresoc.v:189883$13973
assign { } { }
assign $1\core_core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_core_input_carry $1\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:192814.14-192814.41"
- process $proc$libresoc.v:192814$14227
+ attribute \src "libresoc.v:189887.14-189887.41"
+ process $proc$libresoc.v:189887$13974
assign { } { }
assign $1\core_core_core_insn[31:0] 0
sync always
sync init
update \core_core_core_insn $1\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:192892.13-192892.45"
- process $proc$libresoc.v:192892$14228
+ attribute \src "libresoc.v:189965.13-189965.45"
+ process $proc$libresoc.v:189965$13975
assign { } { }
assign $1\core_core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_core_insn_type $1\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:192896.7-192896.37"
- process $proc$libresoc.v:192896$14229
+ attribute \src "libresoc.v:189969.7-189969.37"
+ process $proc$libresoc.v:189969$13976
assign { } { }
assign $1\core_core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:192900.14-192900.55"
- process $proc$libresoc.v:192900$14230
+ attribute \src "libresoc.v:189973.14-189973.55"
+ process $proc$libresoc.v:189973$13977
assign { } { }
assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_msr $1\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:192904.7-192904.31"
- process $proc$libresoc.v:192904$14231
+ attribute \src "libresoc.v:189977.7-189977.31"
+ process $proc$libresoc.v:189977$13978
assign { } { }
assign $1\core_core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_core_oe $1\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:192908.7-192908.34"
- process $proc$libresoc.v:192908$14232
+ attribute \src "libresoc.v:189981.7-189981.34"
+ process $proc$libresoc.v:189981$13979
assign { } { }
assign $1\core_core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:192912.7-192912.31"
- process $proc$libresoc.v:192912$14233
+ attribute \src "libresoc.v:189985.7-189985.31"
+ process $proc$libresoc.v:189985$13980
assign { } { }
assign $1\core_core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_core_rc $1\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:192916.7-192916.34"
- process $proc$libresoc.v:192916$14234
+ attribute \src "libresoc.v:189989.7-189989.34"
+ process $proc$libresoc.v:189989$13981
assign { } { }
assign $1\core_core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:192920.14-192920.48"
- process $proc$libresoc.v:192920$14235
+ attribute \src "libresoc.v:189993.14-189993.48"
+ process $proc$libresoc.v:189993$13982
assign { } { }
assign $1\core_core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:192924.13-192924.44"
- process $proc$libresoc.v:192924$14236
+ attribute \src "libresoc.v:189997.13-189997.44"
+ process $proc$libresoc.v:189997$13983
assign { } { }
assign $1\core_core_core_traptype[7:0] 8'00000000
sync always
sync init
update \core_core_core_traptype $1\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:192928.13-192928.37"
- process $proc$libresoc.v:192928$14237
+ attribute \src "libresoc.v:190001.13-190001.37"
+ process $proc$libresoc.v:190001$13984
assign { } { }
assign $1\core_core_cr_in1[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in1 $1\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:192932.7-192932.33"
- process $proc$libresoc.v:192932$14238
+ attribute \src "libresoc.v:190005.7-190005.33"
+ process $proc$libresoc.v:190005$13985
assign { } { }
assign $1\core_core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:192936.13-192936.37"
- process $proc$libresoc.v:192936$14239
+ attribute \src "libresoc.v:190009.13-190009.37"
+ process $proc$libresoc.v:190009$13986
assign { } { }
assign $1\core_core_cr_in2[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in2 $1\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:192938.13-192938.41"
- process $proc$libresoc.v:192938$14240
+ attribute \src "libresoc.v:190011.13-190011.41"
+ process $proc$libresoc.v:190011$13987
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$14241 7'0000000
+ assign $0\core_core_cr_in2$1[6:0]$13988 7'0000000
sync always
sync init
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14241
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13988
end
- attribute \src "libresoc.v:192944.7-192944.33"
- process $proc$libresoc.v:192944$14242
+ attribute \src "libresoc.v:190017.7-190017.33"
+ process $proc$libresoc.v:190017$13989
assign { } { }
assign $1\core_core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:192946.7-192946.37"
- process $proc$libresoc.v:192946$14243
+ attribute \src "libresoc.v:190019.7-190019.37"
+ process $proc$libresoc.v:190019$13990
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$14244 1'0
+ assign $0\core_core_cr_in2_ok$2[0:0]$13991 1'0
sync always
sync init
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14244
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13991
end
- attribute \src "libresoc.v:192952.13-192952.37"
- process $proc$libresoc.v:192952$14245
+ attribute \src "libresoc.v:190025.13-190025.37"
+ process $proc$libresoc.v:190025$13992
assign { } { }
assign $1\core_core_cr_out[6:0] 7'0000000
sync always
sync init
update \core_core_cr_out $1\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:192956.7-192956.32"
- process $proc$libresoc.v:192956$14246
+ attribute \src "libresoc.v:190029.7-190029.32"
+ process $proc$libresoc.v:190029$13993
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:192960.13-192960.38"
- process $proc$libresoc.v:192960$14247
+ attribute \src "libresoc.v:190033.13-190033.38"
+ process $proc$libresoc.v:190033$13994
assign { } { }
assign $1\core_core_dststep[6:0] 7'0000000
sync always
sync init
update \core_core_dststep $1\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:192964.13-192964.33"
- process $proc$libresoc.v:192964$14248
+ attribute \src "libresoc.v:190037.13-190037.33"
+ process $proc$libresoc.v:190037$13995
assign { } { }
assign $1\core_core_ea[6:0] 7'0000000
sync always
sync init
update \core_core_ea $1\core_core_ea[6:0]
end
- attribute \src "libresoc.v:192968.13-192968.35"
- process $proc$libresoc.v:192968$14249
+ attribute \src "libresoc.v:190041.13-190041.35"
+ process $proc$libresoc.v:190041$13996
assign { } { }
assign $1\core_core_fast1[2:0] 3'000
sync always
sync init
update \core_core_fast1 $1\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:192972.7-192972.32"
- process $proc$libresoc.v:192972$14250
+ attribute \src "libresoc.v:190045.7-190045.32"
+ process $proc$libresoc.v:190045$13997
assign { } { }
assign $1\core_core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_core_fast1_ok $1\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:192976.13-192976.35"
- process $proc$libresoc.v:192976$14251
+ attribute \src "libresoc.v:190049.13-190049.35"
+ process $proc$libresoc.v:190049$13998
assign { } { }
assign $1\core_core_fast2[2:0] 3'000
sync always
sync init
update \core_core_fast2 $1\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:192980.7-192980.32"
- process $proc$libresoc.v:192980$14252
+ attribute \src "libresoc.v:190053.7-190053.32"
+ process $proc$libresoc.v:190053$13999
assign { } { }
assign $1\core_core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_core_fast2_ok $1\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:192984.13-192984.36"
- process $proc$libresoc.v:192984$14253
+ attribute \src "libresoc.v:190057.13-190057.36"
+ process $proc$libresoc.v:190057$14000
assign { } { }
assign $1\core_core_fasto1[2:0] 3'000
sync always
sync init
update \core_core_fasto1 $1\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:192988.13-192988.36"
- process $proc$libresoc.v:192988$14254
+ attribute \src "libresoc.v:190061.13-190061.36"
+ process $proc$libresoc.v:190061$14001
assign { } { }
assign $1\core_core_fasto2[2:0] 3'000
sync always
sync init
update \core_core_fasto2 $1\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:192992.7-192992.26"
- process $proc$libresoc.v:192992$14255
+ attribute \src "libresoc.v:190065.7-190065.26"
+ process $proc$libresoc.v:190065$14002
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:192996.13-192996.36"
- process $proc$libresoc.v:192996$14256
+ attribute \src "libresoc.v:190069.13-190069.36"
+ process $proc$libresoc.v:190069$14003
assign { } { }
assign $1\core_core_maxvl[6:0] 7'0000000
sync always
sync init
update \core_core_maxvl $1\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:193000.14-193000.49"
- process $proc$libresoc.v:193000$14257
+ attribute \src "libresoc.v:190073.14-190073.49"
+ process $proc$libresoc.v:190073$14004
assign { } { }
assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_pc $1\core_core_pc[63:0]
end
- attribute \src "libresoc.v:193004.13-193004.35"
- process $proc$libresoc.v:193004$14258
+ attribute \src "libresoc.v:190077.13-190077.35"
+ process $proc$libresoc.v:190077$14005
assign { } { }
assign $1\core_core_reg1[6:0] 7'0000000
sync always
sync init
update \core_core_reg1 $1\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:193008.7-193008.31"
- process $proc$libresoc.v:193008$14259
+ attribute \src "libresoc.v:190081.7-190081.31"
+ process $proc$libresoc.v:190081$14006
assign { } { }
assign $1\core_core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_core_reg1_ok $1\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:193012.13-193012.35"
- process $proc$libresoc.v:193012$14260
+ attribute \src "libresoc.v:190085.13-190085.35"
+ process $proc$libresoc.v:190085$14007
assign { } { }
assign $1\core_core_reg2[6:0] 7'0000000
sync always
sync init
update \core_core_reg2 $1\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:193016.7-193016.31"
- process $proc$libresoc.v:193016$14261
+ attribute \src "libresoc.v:190089.7-190089.31"
+ process $proc$libresoc.v:190089$14008
assign { } { }
assign $1\core_core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_core_reg2_ok $1\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:193020.13-193020.35"
- process $proc$libresoc.v:193020$14262
+ attribute \src "libresoc.v:190093.13-190093.35"
+ process $proc$libresoc.v:190093$14009
assign { } { }
assign $1\core_core_reg3[6:0] 7'0000000
sync always
sync init
update \core_core_reg3 $1\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:193024.7-193024.31"
- process $proc$libresoc.v:193024$14263
+ attribute \src "libresoc.v:190097.7-190097.31"
+ process $proc$libresoc.v:190097$14010
assign { } { }
assign $1\core_core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_core_reg3_ok $1\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:193028.13-193028.35"
- process $proc$libresoc.v:193028$14264
+ attribute \src "libresoc.v:190101.13-190101.35"
+ process $proc$libresoc.v:190101$14011
assign { } { }
assign $1\core_core_rego[6:0] 7'0000000
sync always
sync init
update \core_core_rego $1\core_core_rego[6:0]
end
- attribute \src "libresoc.v:193146.13-193146.37"
- process $proc$libresoc.v:193146$14265
+ attribute \src "libresoc.v:190219.13-190219.37"
+ process $proc$libresoc.v:190219$14012
assign { } { }
assign $1\core_core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_core_spr1 $1\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:193150.7-193150.31"
- process $proc$libresoc.v:193150$14266
+ attribute \src "libresoc.v:190223.7-190223.31"
+ process $proc$libresoc.v:190223$14013
assign { } { }
assign $1\core_core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_core_spr1_ok $1\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:193268.13-193268.37"
- process $proc$libresoc.v:193268$14267
+ attribute \src "libresoc.v:190341.13-190341.37"
+ process $proc$libresoc.v:190341$14014
assign { } { }
assign $1\core_core_spro[9:0] 10'0000000000
sync always
sync init
update \core_core_spro $1\core_core_spro[9:0]
end
- attribute \src "libresoc.v:193272.13-193272.38"
- process $proc$libresoc.v:193272$14268
+ attribute \src "libresoc.v:190345.13-190345.38"
+ process $proc$libresoc.v:190345$14015
assign { } { }
assign $1\core_core_srcstep[6:0] 7'0000000
sync always
sync init
update \core_core_srcstep $1\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:193276.13-193276.35"
- process $proc$libresoc.v:193276$14269
+ attribute \src "libresoc.v:190349.13-190349.35"
+ process $proc$libresoc.v:190349$14016
assign { } { }
assign $1\core_core_subvl[1:0] 2'00
sync always
sync init
update \core_core_subvl $1\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:193280.13-193280.36"
- process $proc$libresoc.v:193280$14270
+ attribute \src "libresoc.v:190353.13-190353.36"
+ process $proc$libresoc.v:190353$14017
assign { } { }
assign $1\core_core_svstep[1:0] 2'00
sync always
sync init
update \core_core_svstep $1\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:193286.13-193286.33"
- process $proc$libresoc.v:193286$14271
+ attribute \src "libresoc.v:190359.13-190359.33"
+ process $proc$libresoc.v:190359$14018
assign { } { }
assign $1\core_core_vl[6:0] 7'0000000
sync always
sync init
update \core_core_vl $1\core_core_vl[6:0]
end
- attribute \src "libresoc.v:193290.13-193290.36"
- process $proc$libresoc.v:193290$14272
+ attribute \src "libresoc.v:190363.13-190363.36"
+ process $proc$libresoc.v:190363$14019
assign { } { }
assign $1\core_core_xer_in[2:0] 3'000
sync always
sync init
update \core_core_xer_in $1\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:193298.7-193298.28"
- process $proc$libresoc.v:193298$14273
+ attribute \src "libresoc.v:190371.7-190371.28"
+ process $proc$libresoc.v:190371$14020
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:193326.14-193326.45"
- process $proc$libresoc.v:193326$14274
+ attribute \src "libresoc.v:190387.14-190387.45"
+ process $proc$libresoc.v:190387$14021
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:193336.7-193336.24"
- process $proc$libresoc.v:193336$14275
+ attribute \src "libresoc.v:190397.7-190397.24"
+ process $proc$libresoc.v:190397$14022
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:193340.7-193340.23"
- process $proc$libresoc.v:193340$14276
+ attribute \src "libresoc.v:190401.7-190401.23"
+ process $proc$libresoc.v:190401$14023
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:193344.7-193344.28"
- process $proc$libresoc.v:193344$14277
+ attribute \src "libresoc.v:190405.7-190405.28"
+ process $proc$libresoc.v:190405$14024
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:193348.7-193348.28"
- process $proc$libresoc.v:193348$14278
+ attribute \src "libresoc.v:190409.7-190409.28"
+ process $proc$libresoc.v:190409$14025
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:193376.14-193376.45"
- process $proc$libresoc.v:193376$14279
+ attribute \src "libresoc.v:190437.14-190437.45"
+ process $proc$libresoc.v:190437$14026
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:193384.14-193384.37"
- process $proc$libresoc.v:193384$14280
+ attribute \src "libresoc.v:190445.14-190445.37"
+ process $proc$libresoc.v:190445$14027
assign { } { }
assign $1\core_raw_insn_i[31:0] 0
sync always
sync init
update \core_raw_insn_i $1\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:193388.7-193388.26"
- process $proc$libresoc.v:193388$14281
+ attribute \src "libresoc.v:190449.7-190449.26"
+ process $proc$libresoc.v:190449$14028
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:193392.7-193392.26"
- process $proc$libresoc.v:193392$14282
+ attribute \src "libresoc.v:190453.7-190453.26"
+ process $proc$libresoc.v:190453$14029
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:193410.7-193410.26"
- process $proc$libresoc.v:193410$14283
+ attribute \src "libresoc.v:190471.7-190471.26"
+ process $proc$libresoc.v:190471$14030
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:193416.7-193416.30"
- process $proc$libresoc.v:193416$14284
+ attribute \src "libresoc.v:190477.7-190477.30"
+ process $proc$libresoc.v:190477$14031
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:193422.13-193422.36"
- process $proc$libresoc.v:193422$14285
+ attribute \src "libresoc.v:190483.13-190483.36"
+ process $proc$libresoc.v:190483$14032
assign { } { }
assign $1\cur_cur_dststep[6:0] 7'0000000
sync always
sync init
update \cur_cur_dststep $1\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:193426.13-193426.34"
- process $proc$libresoc.v:193426$14286
+ attribute \src "libresoc.v:190487.13-190487.34"
+ process $proc$libresoc.v:190487$14033
assign { } { }
assign $1\cur_cur_maxvl[6:0] 7'0000000
sync always
sync init
update \cur_cur_maxvl $1\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:193430.13-193430.33"
- process $proc$libresoc.v:193430$14287
+ attribute \src "libresoc.v:190491.13-190491.36"
+ process $proc$libresoc.v:190491$14034
+ assign { } { }
+ assign $1\cur_cur_srcstep[6:0] 7'0000000
+ sync always
+ sync init
+ update \cur_cur_srcstep $1\cur_cur_srcstep[6:0]
+ end
+ attribute \src "libresoc.v:190495.13-190495.33"
+ process $proc$libresoc.v:190495$14035
assign { } { }
assign $1\cur_cur_subvl[1:0] 2'00
sync always
sync init
update \cur_cur_subvl $1\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:193434.13-193434.34"
- process $proc$libresoc.v:193434$14288
+ attribute \src "libresoc.v:190499.13-190499.34"
+ process $proc$libresoc.v:190499$14036
assign { } { }
assign $1\cur_cur_svstep[1:0] 2'00
sync always
sync init
update \cur_cur_svstep $1\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:193438.13-193438.31"
- process $proc$libresoc.v:193438$14289
+ attribute \src "libresoc.v:190503.13-190503.31"
+ process $proc$libresoc.v:190503$14037
assign { } { }
assign $1\cur_cur_vl[6:0] 7'0000000
sync always
sync init
update \cur_cur_vl $1\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:193442.7-193442.24"
- process $proc$libresoc.v:193442$14290
+ attribute \src "libresoc.v:190507.7-190507.24"
+ process $proc$libresoc.v:190507$14038
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:193446.7-193446.25"
- process $proc$libresoc.v:193446$14291
+ attribute \src "libresoc.v:190511.7-190511.25"
+ process $proc$libresoc.v:190511$14039
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:193450.7-193450.25"
- process $proc$libresoc.v:193450$14292
+ attribute \src "libresoc.v:190515.7-190515.25"
+ process $proc$libresoc.v:190515$14040
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:193486.13-193486.34"
- process $proc$libresoc.v:193486$14293
+ attribute \src "libresoc.v:190563.13-190563.34"
+ process $proc$libresoc.v:190563$14041
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:193490.14-193490.48"
- process $proc$libresoc.v:193490$14294
+ attribute \src "libresoc.v:190567.14-190567.48"
+ process $proc$libresoc.v:190567$14042
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:193496.7-193496.27"
- process $proc$libresoc.v:193496$14295
+ attribute \src "libresoc.v:190573.7-190573.27"
+ process $proc$libresoc.v:190573$14043
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:193500.7-193500.26"
- process $proc$libresoc.v:193500$14296
+ attribute \src "libresoc.v:190577.7-190577.26"
+ process $proc$libresoc.v:190577$14044
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:193554.13-193554.41"
- process $proc$libresoc.v:193554$14297
- assign { } { }
- assign $1\dec2_cur_cur_srcstep[6:0] 7'0000000
- sync always
- sync init
- update \dec2_cur_cur_srcstep $1\dec2_cur_cur_srcstep[6:0]
- end
- attribute \src "libresoc.v:193558.14-193558.49"
- process $proc$libresoc.v:193558$14298
+ attribute \src "libresoc.v:190631.14-190631.49"
+ process $proc$libresoc.v:190631$14045
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:193562.7-193562.27"
- process $proc$libresoc.v:193562$14299
+ attribute \src "libresoc.v:190635.7-190635.27"
+ process $proc$libresoc.v:190635$14046
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:193566.14-193566.49"
- process $proc$libresoc.v:193566$14300
+ attribute \src "libresoc.v:190639.14-190639.49"
+ process $proc$libresoc.v:190639$14047
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:193570.14-193570.48"
- process $proc$libresoc.v:193570$14301
+ attribute \src "libresoc.v:190643.14-190643.48"
+ process $proc$libresoc.v:190643$14048
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:193574.13-193574.43"
- process $proc$libresoc.v:193574$14302
- assign { } { }
- assign $1\dec2_dec_svp64__extra[8:0] 9'000000000
- sync always
- sync init
- update \dec2_dec_svp64__extra $1\dec2_dec_svp64__extra[8:0]
- end
- attribute \src "libresoc.v:193724.14-193724.40"
- process $proc$libresoc.v:193724$14303
+ attribute \src "libresoc.v:190793.14-190793.40"
+ process $proc$libresoc.v:190793$14049
assign { } { }
assign $1\dec2_raw_opcode_in[31:0] 0
sync always
sync init
update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:193992.13-193992.38"
- process $proc$libresoc.v:193992$14304
- assign { } { }
- assign $1\dec_svp64__elwidth[1:0] 2'00
- sync always
- sync init
- update \dec_svp64__elwidth $1\dec_svp64__elwidth[1:0]
- end
- attribute \src "libresoc.v:193996.13-193996.36"
- process $proc$libresoc.v:193996$14305
- assign { } { }
- assign $1\dec_svp64__ewsrc[1:0] 2'00
- sync always
- sync init
- update \dec_svp64__ewsrc $1\dec_svp64__ewsrc[1:0]
- end
- attribute \src "libresoc.v:194000.13-194000.35"
- process $proc$libresoc.v:194000$14306
- assign { } { }
- assign $1\dec_svp64__mask[2:0] 3'000
- sync always
- sync init
- update \dec_svp64__mask $1\dec_svp64__mask[2:0]
- end
- attribute \src "libresoc.v:194004.7-194004.30"
- process $proc$libresoc.v:194004$14307
- assign { } { }
- assign $1\dec_svp64__mmode[0:0] 1'0
- sync always
- sync init
- update \dec_svp64__mmode $1\dec_svp64__mmode[0:0]
- end
- attribute \src "libresoc.v:194008.13-194008.36"
- process $proc$libresoc.v:194008$14308
- assign { } { }
- assign $1\dec_svp64__mode[4:0] 5'00000
- sync always
- sync init
- update \dec_svp64__mode $1\dec_svp64__mode[4:0]
- end
- attribute \src "libresoc.v:194012.13-194012.36"
- process $proc$libresoc.v:194012$14309
- assign { } { }
- assign $1\dec_svp64__subvl[1:0] 2'00
- sync always
- sync init
- update \dec_svp64__subvl $1\dec_svp64__subvl[1:0]
- end
- attribute \src "libresoc.v:194016.13-194016.25"
- process $proc$libresoc.v:194016$14310
+ attribute \src "libresoc.v:191061.13-191061.25"
+ process $proc$libresoc.v:191061$14050
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:194032.7-194032.28"
- process $proc$libresoc.v:194032$14311
+ attribute \src "libresoc.v:191077.7-191077.28"
+ process $proc$libresoc.v:191077$14051
assign { } { }
assign $1\exec_fsm_state[0:0] 1'0
sync always
sync init
update \exec_fsm_state $1\exec_fsm_state[0:0]
end
- attribute \src "libresoc.v:194044.13-194044.35"
- process $proc$libresoc.v:194044$14312
+ attribute \src "libresoc.v:191089.13-191089.35"
+ process $proc$libresoc.v:191089$14052
assign { } { }
assign $1\fetch_fsm_state[1:0] 2'00
sync always
sync init
update \fetch_fsm_state $1\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:194058.13-194058.29"
- process $proc$libresoc.v:194058$14313
+ attribute \src "libresoc.v:191101.13-191101.29"
+ process $proc$libresoc.v:191101$14053
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:194314.13-194314.35"
- process $proc$libresoc.v:194314$14314
+ attribute \src "libresoc.v:191357.13-191357.35"
+ process $proc$libresoc.v:191357$14054
assign { } { }
assign $1\issue_fsm_state[2:0] 3'000
sync always
sync init
update \issue_fsm_state $1\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:194318.7-194318.30"
- process $proc$libresoc.v:194318$14315
+ attribute \src "libresoc.v:191361.7-191361.30"
+ process $proc$libresoc.v:191361$14055
assign { } { }
assign $1\jtag_dmi0__ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:194326.14-194326.52"
- process $proc$libresoc.v:194326$14316
+ attribute \src "libresoc.v:191369.14-191369.52"
+ process $proc$libresoc.v:191369$14056
assign { } { }
assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:194384.7-194384.22"
- process $proc$libresoc.v:194384$14317
+ attribute \src "libresoc.v:191425.7-191425.22"
+ process $proc$libresoc.v:191425$14057
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:194420.14-194420.40"
- process $proc$libresoc.v:194420$14318
+ attribute \src "libresoc.v:191463.14-191463.40"
+ process $proc$libresoc.v:191463$14058
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:194426.7-194426.24"
- process $proc$libresoc.v:194426$14319
+ attribute \src "libresoc.v:191469.7-191469.24"
+ process $proc$libresoc.v:191469$14059
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:194436.7-194436.25"
- process $proc$libresoc.v:194436$14320
+ attribute \src "libresoc.v:191479.7-191479.25"
+ process $proc$libresoc.v:191479$14060
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:194880.7-194880.24"
- process $proc$libresoc.v:194880$14321
+ attribute \src "libresoc.v:191851.7-191851.24"
+ process $proc$libresoc.v:191851$14061
assign { } { }
assign $1\sv_changed[0:0] 1'0
sync always
sync init
update \sv_changed $1\sv_changed[0:0]
end
- attribute \src "libresoc.v:194898.7-194898.30"
- process $proc$libresoc.v:194898$14322
+ attribute \src "libresoc.v:191861.7-191861.30"
+ process $proc$libresoc.v:191861$14062
assign { } { }
assign $1\svstate_ok_delay[0:0] 1'0
sync always
sync init
update \svstate_ok_delay $1\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:194989.3-194990.41"
- process $proc$libresoc.v:194989$13486
+ attribute \src "libresoc.v:191997.3-191998.41"
+ process $proc$libresoc.v:191997$13375
assign { } { }
assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
sync posedge \clk
update \dec2_cur_dec $0\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:194991.3-194992.47"
- process $proc$libresoc.v:194991$13487
- assign { } { }
- assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next
- sync posedge \clk
- update \core_raw_insn_i $0\core_raw_insn_i[31:0]
- end
- attribute \src "libresoc.v:194993.3-194994.49"
- process $proc$libresoc.v:194993$13488
- assign { } { }
- assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next
- sync posedge \clk
- update \svstate_ok_delay $0\svstate_ok_delay[0:0]
- end
- attribute \src "libresoc.v:194995.3-194996.39"
- process $proc$libresoc.v:194995$13489
- assign { } { }
- assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
- sync posedge \clk
- update \pc_ok_delay $0\pc_ok_delay[0:0]
- end
- attribute \src "libresoc.v:194997.3-194998.43"
- process $proc$libresoc.v:194997$13490
- assign { } { }
- assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o
- sync posedge \clk
- update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
- end
- attribute \src "libresoc.v:194999.3-195000.27"
- process $proc$libresoc.v:194999$13491
- assign { } { }
- assign $0\delay[1:0] \delay$next
- sync posedge \por_clk
- update \delay $0\delay[1:0]
- end
- attribute \src "libresoc.v:195001.3-195002.43"
- process $proc$libresoc.v:195001$13492
- assign { } { }
- assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
- sync posedge \clk
- update \dec2_cur_eint $0\dec2_cur_eint[0:0]
- end
- attribute \src "libresoc.v:195003.3-195004.47"
- process $proc$libresoc.v:195003$13493
+ attribute \src "libresoc.v:191999.3-192000.33"
+ process $proc$libresoc.v:191999$13376
assign { } { }
- assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
- sync posedge \clk
- update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
- end
- attribute \src "libresoc.v:195005.3-195006.49"
- process $proc$libresoc.v:195005$13494
- assign { } { }
- assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
+ assign $0\core_msr[63:0] \core_msr$next
sync posedge \clk
- update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
+ update \core_msr $0\core_msr[63:0]
end
- attribute \src "libresoc.v:195007.3-195008.39"
- process $proc$libresoc.v:195007$13495
+ attribute \src "libresoc.v:192001.3-192002.39"
+ process $proc$libresoc.v:192001$13377
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
sync posedge \clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:195009.3-195010.41"
- process $proc$libresoc.v:195009$13496
+ attribute \src "libresoc.v:192003.3-192004.41"
+ process $proc$libresoc.v:192003$13378
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
sync posedge \clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:195011.3-195012.43"
- process $proc$libresoc.v:195011$13497
+ attribute \src "libresoc.v:192005.3-192006.43"
+ process $proc$libresoc.v:192005$13379
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
sync posedge \clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:195013.3-195014.41"
- process $proc$libresoc.v:195013$13498
- assign { } { }
- assign $0\core_core_pc[63:0] \core_core_pc$next
- sync posedge \clk
- update \core_core_pc $0\core_core_pc[63:0]
- end
- attribute \src "libresoc.v:195015.3-195016.45"
- process $proc$libresoc.v:195015$13499
+ attribute \src "libresoc.v:192007.3-192008.45"
+ process $proc$libresoc.v:192007$13380
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
sync posedge \clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:195017.3-195018.33"
- process $proc$libresoc.v:195017$13500
- assign { } { }
- assign $0\core_msr[63:0] \core_msr$next
- sync posedge \clk
- update \core_msr $0\core_msr[63:0]
- end
- attribute \src "libresoc.v:195019.3-195020.35"
- process $proc$libresoc.v:195019$13501
+ attribute \src "libresoc.v:192009.3-192010.35"
+ process $proc$libresoc.v:192009$13381
assign { } { }
assign $0\core_eint[0:0] \core_eint$next
sync posedge \clk
update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:195021.3-195022.33"
- process $proc$libresoc.v:195021$13502
+ attribute \src "libresoc.v:192011.3-192012.33"
+ process $proc$libresoc.v:192011$13382
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
sync posedge \clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:195023.3-195024.49"
- process $proc$libresoc.v:195023$13503
+ attribute \src "libresoc.v:192013.3-192014.49"
+ process $proc$libresoc.v:192013$13383
assign { } { }
assign $0\core_core_svstep[1:0] \core_core_svstep$next
sync posedge \clk
update \core_core_svstep $0\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:195025.3-195026.47"
- process $proc$libresoc.v:195025$13504
+ attribute \src "libresoc.v:192015.3-192016.47"
+ process $proc$libresoc.v:192015$13384
assign { } { }
assign $0\core_core_subvl[1:0] \core_core_subvl$next
sync posedge \clk
update \core_core_subvl $0\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:195027.3-195028.51"
- process $proc$libresoc.v:195027$13505
+ attribute \src "libresoc.v:192017.3-192018.51"
+ process $proc$libresoc.v:192017$13385
assign { } { }
assign $0\core_core_dststep[6:0] \core_core_dststep$next
sync posedge \clk
update \core_core_dststep $0\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:195029.3-195030.51"
- process $proc$libresoc.v:195029$13506
+ attribute \src "libresoc.v:192019.3-192020.51"
+ process $proc$libresoc.v:192019$13386
assign { } { }
assign $0\core_core_srcstep[6:0] \core_core_srcstep$next
sync posedge \clk
update \core_core_srcstep $0\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:195031.3-195032.41"
- process $proc$libresoc.v:195031$13507
+ attribute \src "libresoc.v:192021.3-192022.41"
+ process $proc$libresoc.v:192021$13387
assign { } { }
assign $0\core_core_vl[6:0] \core_core_vl$next
sync posedge \clk
update \core_core_vl $0\core_core_vl[6:0]
end
- attribute \src "libresoc.v:195033.3-195034.35"
- process $proc$libresoc.v:195033$13508
- assign { } { }
- assign $0\fsm_state[1:0] \fsm_state$next
- sync posedge \clk
- update \fsm_state $0\fsm_state[1:0]
- end
- attribute \src "libresoc.v:195035.3-195036.47"
- process $proc$libresoc.v:195035$13509
+ attribute \src "libresoc.v:192023.3-192024.47"
+ process $proc$libresoc.v:192023$13388
assign { } { }
assign $0\core_core_maxvl[6:0] \core_core_maxvl$next
sync posedge \clk
update \core_core_maxvl $0\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:195037.3-195038.41"
- process $proc$libresoc.v:195037$13510
+ attribute \src "libresoc.v:192025.3-192026.41"
+ process $proc$libresoc.v:192025$13389
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
sync posedge \clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:195039.3-195040.45"
- process $proc$libresoc.v:195039$13511
+ attribute \src "libresoc.v:192027.3-192028.35"
+ process $proc$libresoc.v:192027$13390
+ assign { } { }
+ assign $0\fsm_state[1:0] \fsm_state$next
+ sync posedge \clk
+ update \fsm_state $0\fsm_state[1:0]
+ end
+ attribute \src "libresoc.v:192029.3-192030.45"
+ process $proc$libresoc.v:192029$13391
assign { } { }
assign $0\core_core_rego[6:0] \core_core_rego$next
sync posedge \clk
update \core_core_rego $0\core_core_rego[6:0]
end
- attribute \src "libresoc.v:195041.3-195042.41"
- process $proc$libresoc.v:195041$13512
+ attribute \src "libresoc.v:192031.3-192032.41"
+ process $proc$libresoc.v:192031$13392
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
sync posedge \clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:195043.3-195044.41"
- process $proc$libresoc.v:195043$13513
+ attribute \src "libresoc.v:192033.3-192034.41"
+ process $proc$libresoc.v:192033$13393
assign { } { }
assign $0\core_core_ea[6:0] \core_core_ea$next
sync posedge \clk
update \core_core_ea $0\core_core_ea[6:0]
end
- attribute \src "libresoc.v:195045.3-195046.37"
- process $proc$libresoc.v:195045$13514
+ attribute \src "libresoc.v:192035.3-192036.37"
+ process $proc$libresoc.v:192035$13394
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
sync posedge \clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:195047.3-195048.45"
- process $proc$libresoc.v:195047$13515
+ attribute \src "libresoc.v:192037.3-192038.45"
+ process $proc$libresoc.v:192037$13395
assign { } { }
assign $0\core_core_reg1[6:0] \core_core_reg1$next
sync posedge \clk
update \core_core_reg1 $0\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:195049.3-195050.51"
- process $proc$libresoc.v:195049$13516
+ attribute \src "libresoc.v:192039.3-192040.51"
+ process $proc$libresoc.v:192039$13396
assign { } { }
assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next
sync posedge \clk
update \core_core_reg1_ok $0\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:195051.3-195052.45"
- process $proc$libresoc.v:195051$13517
+ attribute \src "libresoc.v:192041.3-192042.45"
+ process $proc$libresoc.v:192041$13397
assign { } { }
assign $0\core_core_reg2[6:0] \core_core_reg2$next
sync posedge \clk
update \core_core_reg2 $0\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:195053.3-195054.51"
- process $proc$libresoc.v:195053$13518
+ attribute \src "libresoc.v:192043.3-192044.51"
+ process $proc$libresoc.v:192043$13398
assign { } { }
assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next
sync posedge \clk
update \core_core_reg2_ok $0\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:195055.3-195056.39"
- process $proc$libresoc.v:195055$13519
- assign { } { }
- assign $0\d_xer_delay[0:0] \d_xer_delay$next
- sync posedge \clk
- update \d_xer_delay $0\d_xer_delay[0:0]
- end
- attribute \src "libresoc.v:195057.3-195058.45"
- process $proc$libresoc.v:195057$13520
+ attribute \src "libresoc.v:192045.3-192046.45"
+ process $proc$libresoc.v:192045$13399
assign { } { }
assign $0\core_core_reg3[6:0] \core_core_reg3$next
sync posedge \clk
update \core_core_reg3 $0\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:195059.3-195060.51"
- process $proc$libresoc.v:195059$13521
+ attribute \src "libresoc.v:192047.3-192048.51"
+ process $proc$libresoc.v:192047$13400
assign { } { }
assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next
sync posedge \clk
update \core_core_reg3_ok $0\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:195061.3-195062.45"
- process $proc$libresoc.v:195061$13522
+ attribute \src "libresoc.v:192049.3-192050.39"
+ process $proc$libresoc.v:192049$13401
+ assign { } { }
+ assign $0\d_xer_delay[0:0] \d_xer_delay$next
+ sync posedge \clk
+ update \d_xer_delay $0\d_xer_delay[0:0]
+ end
+ attribute \src "libresoc.v:192051.3-192052.45"
+ process $proc$libresoc.v:192051$13402
assign { } { }
assign $0\core_core_spro[9:0] \core_core_spro$next
sync posedge \clk
update \core_core_spro $0\core_core_spro[9:0]
end
- attribute \src "libresoc.v:195063.3-195064.41"
- process $proc$libresoc.v:195063$13523
+ attribute \src "libresoc.v:192053.3-192054.41"
+ process $proc$libresoc.v:192053$13403
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
sync posedge \clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:195065.3-195066.45"
- process $proc$libresoc.v:195065$13524
+ attribute \src "libresoc.v:192055.3-192056.45"
+ process $proc$libresoc.v:192055$13404
assign { } { }
assign $0\core_core_spr1[9:0] \core_core_spr1$next
sync posedge \clk
update \core_core_spr1 $0\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:195067.3-195068.51"
- process $proc$libresoc.v:195067$13525
+ attribute \src "libresoc.v:192057.3-192058.51"
+ process $proc$libresoc.v:192057$13405
assign { } { }
assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next
sync posedge \clk
update \core_core_spr1_ok $0\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:195069.3-195070.49"
- process $proc$libresoc.v:195069$13526
+ attribute \src "libresoc.v:192059.3-192060.49"
+ process $proc$libresoc.v:192059$13406
assign { } { }
assign $0\core_core_xer_in[2:0] \core_core_xer_in$next
sync posedge \clk
update \core_core_xer_in $0\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:195071.3-195072.41"
- process $proc$libresoc.v:195071$13527
+ attribute \src "libresoc.v:192061.3-192062.41"
+ process $proc$libresoc.v:192061$13407
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
sync posedge \clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:195073.3-195074.47"
- process $proc$libresoc.v:195073$13528
+ attribute \src "libresoc.v:192063.3-192064.47"
+ process $proc$libresoc.v:192063$13408
assign { } { }
assign $0\core_core_fast1[2:0] \core_core_fast1$next
sync posedge \clk
update \core_core_fast1 $0\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:195075.3-195076.53"
- process $proc$libresoc.v:195075$13529
+ attribute \src "libresoc.v:192065.3-192066.53"
+ process $proc$libresoc.v:192065$13409
assign { } { }
assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next
sync posedge \clk
update \core_core_fast1_ok $0\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:195077.3-195078.37"
- process $proc$libresoc.v:195077$13530
- assign { } { }
- assign $0\d_cr_delay[0:0] \d_cr_delay$next
- sync posedge \clk
- update \d_cr_delay $0\d_cr_delay[0:0]
- end
- attribute \src "libresoc.v:195079.3-195080.47"
- process $proc$libresoc.v:195079$13531
+ attribute \src "libresoc.v:192067.3-192068.47"
+ process $proc$libresoc.v:192067$13410
assign { } { }
assign $0\core_core_fast2[2:0] \core_core_fast2$next
sync posedge \clk
update \core_core_fast2 $0\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:195081.3-195082.53"
- process $proc$libresoc.v:195081$13532
+ attribute \src "libresoc.v:192069.3-192070.53"
+ process $proc$libresoc.v:192069$13411
assign { } { }
assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next
sync posedge \clk
update \core_core_fast2_ok $0\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:195083.3-195084.49"
- process $proc$libresoc.v:195083$13533
+ attribute \src "libresoc.v:192071.3-192072.37"
+ process $proc$libresoc.v:192071$13412
+ assign { } { }
+ assign $0\d_cr_delay[0:0] \d_cr_delay$next
+ sync posedge \clk
+ update \d_cr_delay $0\d_cr_delay[0:0]
+ end
+ attribute \src "libresoc.v:192073.3-192074.49"
+ process $proc$libresoc.v:192073$13413
assign { } { }
assign $0\core_core_fasto1[2:0] \core_core_fasto1$next
sync posedge \clk
update \core_core_fasto1 $0\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:195085.3-195086.45"
- process $proc$libresoc.v:195085$13534
+ attribute \src "libresoc.v:192075.3-192076.45"
+ process $proc$libresoc.v:192075$13414
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
sync posedge \clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:195087.3-195088.49"
- process $proc$libresoc.v:195087$13535
+ attribute \src "libresoc.v:192077.3-192078.49"
+ process $proc$libresoc.v:192077$13415
assign { } { }
assign $0\core_core_fasto2[2:0] \core_core_fasto2$next
sync posedge \clk
update \core_core_fasto2 $0\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:195089.3-195090.45"
- process $proc$libresoc.v:195089$13536
+ attribute \src "libresoc.v:192079.3-192080.45"
+ process $proc$libresoc.v:192079$13416
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
sync posedge \clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:195091.3-195092.49"
- process $proc$libresoc.v:195091$13537
+ attribute \src "libresoc.v:192081.3-192082.49"
+ process $proc$libresoc.v:192081$13417
assign { } { }
assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next
sync posedge \clk
update \core_core_cr_in1 $0\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:195093.3-195094.55"
- process $proc$libresoc.v:195093$13538
+ attribute \src "libresoc.v:192083.3-192084.55"
+ process $proc$libresoc.v:192083$13418
assign { } { }
assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next
sync posedge \clk
update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:195095.3-195096.49"
- process $proc$libresoc.v:195095$13539
+ attribute \src "libresoc.v:192085.3-192086.49"
+ process $proc$libresoc.v:192085$13419
assign { } { }
assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next
sync posedge \clk
update \core_core_cr_in2 $0\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:195097.3-195098.55"
- process $proc$libresoc.v:195097$13540
+ attribute \src "libresoc.v:192087.3-192088.55"
+ process $proc$libresoc.v:192087$13420
assign { } { }
assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next
sync posedge \clk
update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:195099.3-195100.39"
- process $proc$libresoc.v:195099$13541
+ attribute \src "libresoc.v:192089.3-192090.55"
+ process $proc$libresoc.v:192089$13421
assign { } { }
- assign $0\d_reg_delay[0:0] \d_reg_delay$next
+ assign $0\core_core_cr_in2$1[6:0]$13422 \core_core_cr_in2$1$next
sync posedge \clk
- update \d_reg_delay $0\d_reg_delay[0:0]
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13422
end
- attribute \src "libresoc.v:195101.3-195102.55"
- process $proc$libresoc.v:195101$13542
+ attribute \src "libresoc.v:192091.3-192092.61"
+ process $proc$libresoc.v:192091$13423
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$13543 \core_core_cr_in2$1$next
+ assign $0\core_core_cr_in2_ok$2[0:0]$13424 \core_core_cr_in2_ok$2$next
sync posedge \clk
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13543
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13424
end
- attribute \src "libresoc.v:195103.3-195104.61"
- process $proc$libresoc.v:195103$13544
+ attribute \src "libresoc.v:192093.3-192094.39"
+ process $proc$libresoc.v:192093$13425
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$13545 \core_core_cr_in2_ok$2$next
+ assign $0\d_reg_delay[0:0] \d_reg_delay$next
sync posedge \clk
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13545
+ update \d_reg_delay $0\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:195105.3-195106.49"
- process $proc$libresoc.v:195105$13546
+ attribute \src "libresoc.v:192095.3-192096.49"
+ process $proc$libresoc.v:192095$13426
assign { } { }
assign $0\core_core_cr_out[6:0] \core_core_cr_out$next
sync posedge \clk
update \core_core_cr_out $0\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:195107.3-195108.45"
- process $proc$libresoc.v:195107$13547
+ attribute \src "libresoc.v:192097.3-192098.45"
+ process $proc$libresoc.v:192097$13427
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
sync posedge \clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:195109.3-195110.53"
- process $proc$libresoc.v:195109$13548
+ attribute \src "libresoc.v:192099.3-192100.53"
+ process $proc$libresoc.v:192099$13428
assign { } { }
assign $0\core_core_core_msr[63:0] \core_core_core_msr$next
sync posedge \clk
update \core_core_core_msr $0\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:195111.3-195112.53"
- process $proc$libresoc.v:195111$13549
+ attribute \src "libresoc.v:192101.3-192102.53"
+ process $proc$libresoc.v:192101$13429
assign { } { }
assign $0\core_core_core_cia[63:0] \core_core_core_cia$next
sync posedge \clk
update \core_core_core_cia $0\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:195113.3-195114.55"
- process $proc$libresoc.v:195113$13550
+ attribute \src "libresoc.v:192103.3-192104.55"
+ process $proc$libresoc.v:192103$13430
assign { } { }
assign $0\core_core_core_insn[31:0] \core_core_core_insn$next
sync posedge \clk
update \core_core_core_insn $0\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:195115.3-195116.65"
- process $proc$libresoc.v:195115$13551
+ attribute \src "libresoc.v:192105.3-192106.65"
+ process $proc$libresoc.v:192105$13431
assign { } { }
assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next
sync posedge \clk
update \core_core_core_insn_type $0\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:195117.3-195118.61"
- process $proc$libresoc.v:195117$13552
+ attribute \src "libresoc.v:192107.3-192108.61"
+ process $proc$libresoc.v:192107$13432
assign { } { }
assign $0\core_core_core_fn_unit[12:0] \core_core_core_fn_unit$next
sync posedge \clk
update \core_core_core_fn_unit $0\core_core_core_fn_unit[12:0]
end
- attribute \src "libresoc.v:195119.3-195120.41"
- process $proc$libresoc.v:195119$13553
+ attribute \src "libresoc.v:192109.3-192110.41"
+ process $proc$libresoc.v:192109$13433
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
sync posedge \clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:195121.3-195122.37"
- process $proc$libresoc.v:195121$13554
- assign { } { }
- assign $0\pc_changed[0:0] \pc_changed$next
- sync posedge \clk
- update \pc_changed $0\pc_changed[0:0]
- end
- attribute \src "libresoc.v:195123.3-195124.51"
- process $proc$libresoc.v:195123$13555
+ attribute \src "libresoc.v:192111.3-192112.51"
+ process $proc$libresoc.v:192111$13434
assign { } { }
assign $0\core_core_core_rc[0:0] \core_core_core_rc$next
sync posedge \clk
update \core_core_core_rc $0\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:195125.3-195126.57"
- process $proc$libresoc.v:195125$13556
+ attribute \src "libresoc.v:192113.3-192114.57"
+ process $proc$libresoc.v:192113$13435
assign { } { }
assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next
sync posedge \clk
update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:195127.3-195128.51"
- process $proc$libresoc.v:195127$13557
+ attribute \src "libresoc.v:192115.3-192116.45"
+ process $proc$libresoc.v:192115$13436
+ assign { } { }
+ assign $0\exec_fsm_state[0:0] \exec_fsm_state$next
+ sync posedge \clk
+ update \exec_fsm_state $0\exec_fsm_state[0:0]
+ end
+ attribute \src "libresoc.v:192117.3-192118.51"
+ process $proc$libresoc.v:192117$13437
assign { } { }
assign $0\core_core_core_oe[0:0] \core_core_core_oe$next
sync posedge \clk
update \core_core_core_oe $0\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:195129.3-195130.57"
- process $proc$libresoc.v:195129$13558
+ attribute \src "libresoc.v:192119.3-192120.57"
+ process $proc$libresoc.v:192119$13438
assign { } { }
assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next
sync posedge \clk
update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:195131.3-195132.69"
- process $proc$libresoc.v:195131$13559
+ attribute \src "libresoc.v:192121.3-192122.69"
+ process $proc$libresoc.v:192121$13439
assign { } { }
assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next
sync posedge \clk
update \core_core_core_input_carry $0\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:195133.3-195134.63"
- process $proc$libresoc.v:195133$13560
+ attribute \src "libresoc.v:192123.3-192124.63"
+ process $proc$libresoc.v:192123$13440
assign { } { }
assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next
sync posedge \clk
update \core_core_core_traptype $0\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:195135.3-195136.71"
- process $proc$libresoc.v:195135$13561
+ attribute \src "libresoc.v:192125.3-192126.71"
+ process $proc$libresoc.v:192125$13441
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$13562 \core_core_core_exc_$signal$next
+ assign $0\core_core_core_exc_$signal[0:0]$13442 \core_core_core_exc_$signal$next
sync posedge \clk
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13562
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13442
end
- attribute \src "libresoc.v:195137.3-195138.75"
- process $proc$libresoc.v:195137$13563
+ attribute \src "libresoc.v:192127.3-192128.75"
+ process $proc$libresoc.v:192127$13443
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$13564 \core_core_core_exc_$signal$3$next
+ assign $0\core_core_core_exc_$signal$3[0:0]$13444 \core_core_core_exc_$signal$3$next
sync posedge \clk
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13564
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13444
end
- attribute \src "libresoc.v:195139.3-195140.75"
- process $proc$libresoc.v:195139$13565
+ attribute \src "libresoc.v:192129.3-192130.75"
+ process $proc$libresoc.v:192129$13445
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$13566 \core_core_core_exc_$signal$4$next
+ assign $0\core_core_core_exc_$signal$4[0:0]$13446 \core_core_core_exc_$signal$4$next
sync posedge \clk
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13566
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13446
end
- attribute \src "libresoc.v:195141.3-195142.75"
- process $proc$libresoc.v:195141$13567
+ attribute \src "libresoc.v:192131.3-192132.75"
+ process $proc$libresoc.v:192131$13447
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$13568 \core_core_core_exc_$signal$5$next
+ assign $0\core_core_core_exc_$signal$5[0:0]$13448 \core_core_core_exc_$signal$5$next
sync posedge \clk
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13568
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13448
end
- attribute \src "libresoc.v:195143.3-195144.37"
- process $proc$libresoc.v:195143$13569
+ attribute \src "libresoc.v:192133.3-192134.75"
+ process $proc$libresoc.v:192133$13449
assign { } { }
- assign $0\sv_changed[0:0] \sv_changed$next
+ assign $0\core_core_core_exc_$signal$6[0:0]$13450 \core_core_core_exc_$signal$6$next
sync posedge \clk
- update \sv_changed $0\sv_changed[0:0]
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13450
end
- attribute \src "libresoc.v:195145.3-195146.75"
- process $proc$libresoc.v:195145$13570
+ attribute \src "libresoc.v:192135.3-192136.75"
+ process $proc$libresoc.v:192135$13451
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$13571 \core_core_core_exc_$signal$6$next
+ assign $0\core_core_core_exc_$signal$7[0:0]$13452 \core_core_core_exc_$signal$7$next
sync posedge \clk
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13571
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13452
end
- attribute \src "libresoc.v:195147.3-195148.75"
- process $proc$libresoc.v:195147$13572
+ attribute \src "libresoc.v:192137.3-192138.57"
+ process $proc$libresoc.v:192137$13453
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$13573 \core_core_core_exc_$signal$7$next
+ assign $0\core_bigendian_i$10[0:0]$13454 \core_bigendian_i$10$next
sync posedge \clk
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13573
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13454
end
- attribute \src "libresoc.v:195149.3-195150.75"
- process $proc$libresoc.v:195149$13574
+ attribute \src "libresoc.v:192139.3-192140.75"
+ process $proc$libresoc.v:192139$13455
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$13575 \core_core_core_exc_$signal$8$next
+ assign $0\core_core_core_exc_$signal$8[0:0]$13456 \core_core_core_exc_$signal$8$next
sync posedge \clk
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13575
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13456
end
- attribute \src "libresoc.v:195151.3-195152.75"
- process $proc$libresoc.v:195151$13576
+ attribute \src "libresoc.v:192141.3-192142.75"
+ process $proc$libresoc.v:192141$13457
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$13577 \core_core_core_exc_$signal$9$next
+ assign $0\core_core_core_exc_$signal$9[0:0]$13458 \core_core_core_exc_$signal$9$next
sync posedge \clk
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13577
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13458
end
- attribute \src "libresoc.v:195153.3-195154.63"
- process $proc$libresoc.v:195153$13578
+ attribute \src "libresoc.v:192143.3-192144.63"
+ process $proc$libresoc.v:192143$13459
assign { } { }
assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next
sync posedge \clk
update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:195155.3-195156.57"
- process $proc$libresoc.v:195155$13579
+ attribute \src "libresoc.v:192145.3-192146.57"
+ process $proc$libresoc.v:192145$13460
assign { } { }
assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next
sync posedge \clk
update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:195157.3-195158.63"
- process $proc$libresoc.v:195157$13580
+ attribute \src "libresoc.v:192147.3-192148.63"
+ process $proc$libresoc.v:192147$13461
assign { } { }
assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next
sync posedge \clk
update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:195159.3-195160.57"
- process $proc$libresoc.v:195159$13581
+ attribute \src "libresoc.v:192149.3-192150.57"
+ process $proc$libresoc.v:192149$13462
assign { } { }
assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next
sync posedge \clk
update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:195161.3-195162.53"
- process $proc$libresoc.v:195161$13582
+ attribute \src "libresoc.v:192151.3-192152.53"
+ process $proc$libresoc.v:192151$13463
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
sync posedge \clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:195163.3-195164.63"
- process $proc$libresoc.v:195163$13583
+ attribute \src "libresoc.v:192153.3-192154.63"
+ process $proc$libresoc.v:192153$13464
assign { } { }
assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next
sync posedge \clk
update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:195165.3-195166.45"
- process $proc$libresoc.v:195165$13584
- assign { } { }
- assign $0\exec_fsm_state[0:0] \exec_fsm_state$next
- sync posedge \clk
- update \exec_fsm_state $0\exec_fsm_state[0:0]
- end
- attribute \src "libresoc.v:195167.3-195168.47"
- process $proc$libresoc.v:195167$13585
- assign { } { }
- assign $0\issue_fsm_state[2:0] \issue_fsm_state$next
- sync posedge \clk
- update \issue_fsm_state $0\issue_fsm_state[2:0]
- end
- attribute \src "libresoc.v:195169.3-195170.23"
- process $proc$libresoc.v:195169$13586
+ attribute \src "libresoc.v:192155.3-192156.37"
+ process $proc$libresoc.v:192155$13465
assign { } { }
- assign $0\nia[63:0] \nia$next
- sync posedge \clk
- update \nia $0\nia[63:0]
- end
- attribute \src "libresoc.v:195171.3-195172.47"
- process $proc$libresoc.v:195171$13587
- assign { } { }
- assign $0\dec_svp64__mode[4:0] \dec_svp64__mode$next
- sync posedge \clk
- update \dec_svp64__mode $0\dec_svp64__mode[4:0]
- end
- attribute \src "libresoc.v:195173.3-195174.59"
- process $proc$libresoc.v:195173$13588
- assign { } { }
- assign $0\dec2_dec_svp64__extra[8:0] \dec2_dec_svp64__extra$next
+ assign $0\sv_changed[0:0] \sv_changed$next
sync posedge \clk
- update \dec2_dec_svp64__extra $0\dec2_dec_svp64__extra[8:0]
+ update \sv_changed $0\sv_changed[0:0]
end
- attribute \src "libresoc.v:195175.3-195176.49"
- process $proc$libresoc.v:195175$13589
+ attribute \src "libresoc.v:192157.3-192158.37"
+ process $proc$libresoc.v:192157$13466
assign { } { }
- assign $0\dec_svp64__subvl[1:0] \dec_svp64__subvl$next
+ assign $0\pc_changed[0:0] \pc_changed$next
sync posedge \clk
- update \dec_svp64__subvl $0\dec_svp64__subvl[1:0]
+ update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:195177.3-195178.49"
- process $proc$libresoc.v:195177$13590
+ attribute \src "libresoc.v:192159.3-192160.47"
+ process $proc$libresoc.v:192159$13467
assign { } { }
- assign $0\dec_svp64__ewsrc[1:0] \dec_svp64__ewsrc$next
+ assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next
sync posedge \clk
- update \dec_svp64__ewsrc $0\dec_svp64__ewsrc[1:0]
+ update \core_raw_insn_i $0\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:195179.3-195180.53"
- process $proc$libresoc.v:195179$13591
+ attribute \src "libresoc.v:192161.3-192162.47"
+ process $proc$libresoc.v:192161$13468
assign { } { }
- assign $0\dec_svp64__elwidth[1:0] \dec_svp64__elwidth$next
+ assign $0\issue_fsm_state[2:0] \issue_fsm_state$next
sync posedge \clk
- update \dec_svp64__elwidth $0\dec_svp64__elwidth[1:0]
+ update \issue_fsm_state $0\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:195181.3-195182.47"
- process $proc$libresoc.v:195181$13592
+ attribute \src "libresoc.v:192163.3-192164.53"
+ process $proc$libresoc.v:192163$13469
assign { } { }
- assign $0\dec_svp64__mask[2:0] \dec_svp64__mask$next
+ assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next
sync posedge \clk
- update \dec_svp64__mask $0\dec_svp64__mask[2:0]
+ update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:195183.3-195184.49"
- process $proc$libresoc.v:195183$13593
+ attribute \src "libresoc.v:192165.3-192166.23"
+ process $proc$libresoc.v:192165$13470
assign { } { }
- assign $0\dec_svp64__mmode[0:0] \dec_svp64__mmode$next
+ assign $0\nia[63:0] \nia$next
sync posedge \clk
- update \dec_svp64__mmode $0\dec_svp64__mmode[0:0]
+ update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:195185.3-195186.41"
- process $proc$libresoc.v:195185$13594
+ attribute \src "libresoc.v:192167.3-192168.41"
+ process $proc$libresoc.v:192167$13471
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
sync posedge \clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:195187.3-195188.57"
- process $proc$libresoc.v:195187$13595
- assign { } { }
- assign $0\core_bigendian_i$10[0:0]$13596 \core_bigendian_i$10$next
- sync posedge \clk
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13596
- end
- attribute \src "libresoc.v:195189.3-195190.47"
- process $proc$libresoc.v:195189$13597
+ attribute \src "libresoc.v:192169.3-192170.47"
+ process $proc$libresoc.v:192169$13472
assign { } { }
assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next
sync posedge \clk
update \fetch_fsm_state $0\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:195191.3-195192.33"
- process $proc$libresoc.v:195191$13598
+ attribute \src "libresoc.v:192171.3-192172.33"
+ process $proc$libresoc.v:192171$13473
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
sync posedge \clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:195193.3-195194.45"
- process $proc$libresoc.v:195193$13599
+ attribute \src "libresoc.v:192173.3-192174.45"
+ process $proc$libresoc.v:192173$13474
assign { } { }
assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next
sync posedge \clk
update \cur_cur_svstep $0\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:195195.3-195196.43"
- process $proc$libresoc.v:195195$13600
+ attribute \src "libresoc.v:192175.3-192176.43"
+ process $proc$libresoc.v:192175$13475
assign { } { }
assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next
sync posedge \clk
update \cur_cur_subvl $0\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:195197.3-195198.47"
- process $proc$libresoc.v:195197$13601
+ attribute \src "libresoc.v:192177.3-192178.47"
+ process $proc$libresoc.v:192177$13476
assign { } { }
assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next
sync posedge \clk
update \cur_cur_dststep $0\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:195199.3-195200.57"
- process $proc$libresoc.v:195199$13602
+ attribute \src "libresoc.v:192179.3-192180.47"
+ process $proc$libresoc.v:192179$13477
assign { } { }
- assign $0\dec2_cur_cur_srcstep[6:0] \dec2_cur_cur_srcstep$next
+ assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next
sync posedge \clk
- update \dec2_cur_cur_srcstep $0\dec2_cur_cur_srcstep[6:0]
+ update \cur_cur_srcstep $0\cur_cur_srcstep[6:0]
end
- attribute \src "libresoc.v:195201.3-195202.37"
- process $proc$libresoc.v:195201$13603
+ attribute \src "libresoc.v:192181.3-192182.41"
+ process $proc$libresoc.v:192181$13478
+ assign { } { }
+ assign $0\core_core_pc[63:0] \core_core_pc$next
+ sync posedge \clk
+ update \core_core_pc $0\core_core_pc[63:0]
+ end
+ attribute \src "libresoc.v:192183.3-192184.37"
+ process $proc$libresoc.v:192183$13479
assign { } { }
assign $0\cur_cur_vl[6:0] \cur_cur_vl$next
sync posedge \clk
update \cur_cur_vl $0\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:195203.3-195204.43"
- process $proc$libresoc.v:195203$13604
+ attribute \src "libresoc.v:192185.3-192186.43"
+ process $proc$libresoc.v:192185$13480
assign { } { }
assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next
sync posedge \clk
update \cur_cur_maxvl $0\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:195205.3-195206.39"
- process $proc$libresoc.v:195205$13605
+ attribute \src "libresoc.v:192187.3-192188.39"
+ process $proc$libresoc.v:192187$13481
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
sync posedge \clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:195207.3-195208.40"
- process $proc$libresoc.v:195207$13606
+ attribute \src "libresoc.v:192189.3-192190.49"
+ process $proc$libresoc.v:192189$13482
assign { } { }
- assign $0\dec2_raw_opcode_in[31:0] \fetch_insn_o
+ assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next
sync posedge \clk
- update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
+ update \svstate_ok_delay $0\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:195839.3-195847.6"
- process $proc$libresoc.v:195839$13607
+ attribute \src "libresoc.v:192191.3-192192.39"
+ process $proc$libresoc.v:192191$13483
assign { } { }
+ assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
+ sync posedge \clk
+ update \pc_ok_delay $0\pc_ok_delay[0:0]
+ end
+ attribute \src "libresoc.v:192193.3-192194.43"
+ process $proc$libresoc.v:192193$13484
assign { } { }
- assign $0\dbg_dmi_addr_i$next[3:0]$13608 $1\dbg_dmi_addr_i$next[3:0]$13609
- attribute \src "libresoc.v:195840.5-195840.29"
- switch \initial
- attribute \src "libresoc.v:195840.9-195840.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dbg_dmi_addr_i$next[3:0]$13609 4'0000
- case
- assign $1\dbg_dmi_addr_i$next[3:0]$13609 \jtag_dmi0__addr_i
- end
- sync always
- update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13608
+ assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o
+ sync posedge \clk
+ update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:195848.3-195856.6"
- process $proc$libresoc.v:195848$13610
+ attribute \src "libresoc.v:192195.3-192196.27"
+ process $proc$libresoc.v:192195$13485
assign { } { }
+ assign $0\delay[1:0] \delay$next
+ sync posedge \por_clk
+ update \delay $0\delay[1:0]
+ end
+ attribute \src "libresoc.v:192197.3-192198.43"
+ process $proc$libresoc.v:192197$13486
assign { } { }
- assign $0\dbg_dmi_req_i$next[0:0]$13611 $1\dbg_dmi_req_i$next[0:0]$13612
- attribute \src "libresoc.v:195849.5-195849.29"
- switch \initial
- attribute \src "libresoc.v:195849.9-195849.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dbg_dmi_req_i$next[0:0]$13612 1'0
- case
- assign $1\dbg_dmi_req_i$next[0:0]$13612 \jtag_dmi0__req_i
- end
- sync always
- update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13611
+ assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
+ sync posedge \clk
+ update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:195857.3-195865.6"
- process $proc$libresoc.v:195857$13613
+ attribute \src "libresoc.v:192199.3-192200.47"
+ process $proc$libresoc.v:192199$13487
+ assign { } { }
+ assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
+ sync posedge \clk
+ update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
+ end
+ attribute \src "libresoc.v:192201.3-192202.49"
+ process $proc$libresoc.v:192201$13488
+ assign { } { }
+ assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
+ sync posedge \clk
+ update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
+ end
+ attribute \src "libresoc.v:192778.3-192786.6"
+ process $proc$libresoc.v:192778$13489
assign { } { }
assign { } { }
- assign $0\dec2_cur_eint$next[0:0]$13614 $1\dec2_cur_eint$next[0:0]$13615
- attribute \src "libresoc.v:195858.5-195858.29"
+ assign $0\dbg_dmi_addr_i$next[3:0]$13490 $1\dbg_dmi_addr_i$next[3:0]$13491
+ attribute \src "libresoc.v:192779.5-192779.29"
switch \initial
- attribute \src "libresoc.v:195858.9-195858.17"
+ attribute \src "libresoc.v:192779.9-192779.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dec2_cur_eint$next[0:0]$13615 1'0
+ assign $1\dbg_dmi_addr_i$next[3:0]$13491 4'0000
case
- assign $1\dec2_cur_eint$next[0:0]$13615 \xics_icp_core_irq_o
+ assign $1\dbg_dmi_addr_i$next[3:0]$13491 \jtag_dmi0__addr_i
end
sync always
- update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13614
+ update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13490
end
- attribute \src "libresoc.v:195866.3-195875.6"
- process $proc$libresoc.v:195866$13616
+ attribute \src "libresoc.v:192787.3-192795.6"
+ process $proc$libresoc.v:192787$13492
assign { } { }
assign { } { }
- assign $0\delay$next[1:0]$13617 $1\delay$next[1:0]$13618
- attribute \src "libresoc.v:195867.5-195867.29"
+ assign $0\dbg_dmi_req_i$next[0:0]$13493 $1\dbg_dmi_req_i$next[0:0]$13494
+ attribute \src "libresoc.v:192788.5-192788.29"
switch \initial
- attribute \src "libresoc.v:195867.9-195867.17"
+ attribute \src "libresoc.v:192788.9-192788.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
- switch \$23
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\delay$next[1:0]$13618 \$25 [1:0]
+ assign $1\dbg_dmi_req_i$next[0:0]$13494 1'0
case
- assign $1\delay$next[1:0]$13618 \delay
+ assign $1\dbg_dmi_req_i$next[0:0]$13494 \jtag_dmi0__req_i
end
sync always
- update \delay$next $0\delay$next[1:0]$13617
+ update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13493
end
- attribute \src "libresoc.v:195876.3-195916.6"
- process $proc$libresoc.v:195876$13619
+ attribute \src "libresoc.v:192796.3-192840.6"
+ process $proc$libresoc.v:192796$13495
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_dststep$next[6:0]$13620 $3\core_core_dststep$next[6:0]$13650
- assign $0\core_core_maxvl$next[6:0]$13621 $3\core_core_maxvl$next[6:0]$13651
- assign $0\core_core_pc$next[63:0]$13622 $3\core_core_pc$next[63:0]$13652
- assign $0\core_core_srcstep$next[6:0]$13623 $3\core_core_srcstep$next[6:0]$13653
- assign $0\core_core_subvl$next[1:0]$13624 $3\core_core_subvl$next[1:0]$13654
- assign $0\core_core_svstep$next[1:0]$13625 $3\core_core_svstep$next[1:0]$13655
- assign $0\core_core_vl$next[6:0]$13626 $3\core_core_vl$next[6:0]$13656
- assign $0\core_dec$next[63:0]$13627 $3\core_dec$next[63:0]$13657
- assign $0\core_eint$next[0:0]$13628 $3\core_eint$next[0:0]$13658
- assign $0\core_msr$next[63:0]$13629 $3\core_msr$next[63:0]$13659
- attribute \src "libresoc.v:195877.5-195877.29"
+ assign $0\core_core_dststep$next[6:0]$13496 $3\core_core_dststep$next[6:0]$13526
+ assign $0\core_core_maxvl$next[6:0]$13497 $3\core_core_maxvl$next[6:0]$13527
+ assign $0\core_core_pc$next[63:0]$13498 $3\core_core_pc$next[63:0]$13528
+ assign $0\core_core_srcstep$next[6:0]$13499 $3\core_core_srcstep$next[6:0]$13529
+ assign $0\core_core_subvl$next[1:0]$13500 $3\core_core_subvl$next[1:0]$13530
+ assign $0\core_core_svstep$next[1:0]$13501 $3\core_core_svstep$next[1:0]$13531
+ assign $0\core_core_vl$next[6:0]$13502 $3\core_core_vl$next[6:0]$13532
+ assign $0\core_dec$next[63:0]$13503 $3\core_dec$next[63:0]$13533
+ assign $0\core_eint$next[0:0]$13504 $3\core_eint$next[0:0]$13534
+ assign $0\core_msr$next[63:0]$13505 $3\core_msr$next[63:0]$13535
+ attribute \src "libresoc.v:192797.5-192797.29"
switch \initial
- attribute \src "libresoc.v:195877.9-195877.17"
+ attribute \src "libresoc.v:192797.9-192797.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'010
+ case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_core_dststep$next[6:0]$13630 $2\core_core_dststep$next[6:0]$13640
- assign $1\core_core_maxvl$next[6:0]$13631 $2\core_core_maxvl$next[6:0]$13641
- assign $1\core_core_pc$next[63:0]$13632 $2\core_core_pc$next[63:0]$13642
- assign $1\core_core_srcstep$next[6:0]$13633 $2\core_core_srcstep$next[6:0]$13643
- assign $1\core_core_subvl$next[1:0]$13634 $2\core_core_subvl$next[1:0]$13644
- assign $1\core_core_svstep$next[1:0]$13635 $2\core_core_svstep$next[1:0]$13645
- assign $1\core_core_vl$next[6:0]$13636 $2\core_core_vl$next[6:0]$13646
- assign $1\core_dec$next[63:0]$13637 $2\core_dec$next[63:0]$13647
- assign $1\core_eint$next[0:0]$13638 $2\core_eint$next[0:0]$13648
- assign $1\core_msr$next[63:0]$13639 $2\core_msr$next[63:0]$13649
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
+ assign $1\core_core_dststep$next[6:0]$13506 $2\core_core_dststep$next[6:0]$13516
+ assign $1\core_core_maxvl$next[6:0]$13507 $2\core_core_maxvl$next[6:0]$13517
+ assign $1\core_core_pc$next[63:0]$13508 $2\core_core_pc$next[63:0]$13518
+ assign $1\core_core_srcstep$next[6:0]$13509 $2\core_core_srcstep$next[6:0]$13519
+ assign $1\core_core_subvl$next[1:0]$13510 $2\core_core_subvl$next[1:0]$13520
+ assign $1\core_core_svstep$next[1:0]$13511 $2\core_core_svstep$next[1:0]$13521
+ assign $1\core_core_vl$next[6:0]$13512 $2\core_core_vl$next[6:0]$13522
+ assign $1\core_dec$next[63:0]$13513 $2\core_dec$next[63:0]$13523
+ assign $1\core_eint$next[0:0]$13514 $2\core_eint$next[0:0]$13524
+ assign $1\core_msr$next[63:0]$13515 $2\core_msr$next[63:0]$13525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_maxvl$next[6:0]$13641 $2\core_core_vl$next[6:0]$13646 $2\core_core_srcstep$next[6:0]$13643 $2\core_core_dststep$next[6:0]$13640 $2\core_core_subvl$next[1:0]$13644 $2\core_core_svstep$next[1:0]$13645 $2\core_dec$next[63:0]$13647 $2\core_eint$next[0:0]$13648 $2\core_msr$next[63:0]$13649 $2\core_core_pc$next[63:0]$13642 } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $2\core_core_maxvl$next[6:0]$13517 $2\core_core_vl$next[6:0]$13522 $2\core_core_srcstep$next[6:0]$13519 $2\core_core_dststep$next[6:0]$13516 $2\core_core_subvl$next[1:0]$13520 $2\core_core_svstep$next[1:0]$13521 $2\core_dec$next[63:0]$13523 $2\core_eint$next[0:0]$13524 $2\core_msr$next[63:0]$13525 $2\core_core_pc$next[63:0]$13518 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $2\core_core_dststep$next[6:0]$13640 \core_core_dststep
- assign $2\core_core_maxvl$next[6:0]$13641 \core_core_maxvl
- assign $2\core_core_pc$next[63:0]$13642 \core_core_pc
- assign $2\core_core_srcstep$next[6:0]$13643 \core_core_srcstep
- assign $2\core_core_subvl$next[1:0]$13644 \core_core_subvl
- assign $2\core_core_svstep$next[1:0]$13645 \core_core_svstep
- assign $2\core_core_vl$next[6:0]$13646 \core_core_vl
- assign $2\core_dec$next[63:0]$13647 \core_dec
- assign $2\core_eint$next[0:0]$13648 \core_eint
- assign $2\core_msr$next[63:0]$13649 \core_msr
+ assign $2\core_core_dststep$next[6:0]$13516 \core_core_dststep
+ assign $2\core_core_maxvl$next[6:0]$13517 \core_core_maxvl
+ assign $2\core_core_pc$next[63:0]$13518 \core_core_pc
+ assign $2\core_core_srcstep$next[6:0]$13519 \core_core_srcstep
+ assign $2\core_core_subvl$next[1:0]$13520 \core_core_subvl
+ assign $2\core_core_svstep$next[1:0]$13521 \core_core_svstep
+ assign $2\core_core_vl$next[6:0]$13522 \core_core_vl
+ assign $2\core_dec$next[63:0]$13523 \core_dec
+ assign $2\core_eint$next[0:0]$13524 \core_eint
+ assign $2\core_msr$next[63:0]$13525 \core_msr
end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'100
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { $1\core_core_maxvl$next[6:0]$13507 $1\core_core_vl$next[6:0]$13512 $1\core_core_srcstep$next[6:0]$13509 $1\core_core_dststep$next[6:0]$13506 $1\core_core_subvl$next[1:0]$13510 $1\core_core_svstep$next[1:0]$13511 $1\core_dec$next[63:0]$13513 $1\core_eint$next[0:0]$13514 $1\core_msr$next[63:0]$13515 $1\core_core_pc$next[63:0]$13508 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $1\core_core_dststep$next[6:0]$13630 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13631 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13632 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13633 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13634 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13635 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13636 \core_core_vl
- assign $1\core_dec$next[63:0]$13637 \core_dec
- assign $1\core_eint$next[0:0]$13638 \core_eint
- assign $1\core_msr$next[63:0]$13639 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13506 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13507 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13508 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13509 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13510 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13511 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13512 \core_core_vl
+ assign $1\core_dec$next[63:0]$13513 \core_dec
+ assign $1\core_eint$next[0:0]$13514 \core_eint
+ assign $1\core_msr$next[63:0]$13515 \core_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_core_pc$next[63:0]$13652 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_msr$next[63:0]$13659 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_eint$next[0:0]$13658 1'0
- assign $3\core_dec$next[63:0]$13657 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_core_svstep$next[1:0]$13655 2'00
- assign $3\core_core_subvl$next[1:0]$13654 2'00
- assign $3\core_core_dststep$next[6:0]$13650 7'0000000
- assign $3\core_core_srcstep$next[6:0]$13653 7'0000000
- assign $3\core_core_vl$next[6:0]$13656 7'0000000
- assign $3\core_core_maxvl$next[6:0]$13651 7'0000000
+ assign $3\core_core_pc$next[63:0]$13528 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_msr$next[63:0]$13535 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_eint$next[0:0]$13534 1'0
+ assign $3\core_dec$next[63:0]$13533 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_core_svstep$next[1:0]$13531 2'00
+ assign $3\core_core_subvl$next[1:0]$13530 2'00
+ assign $3\core_core_dststep$next[6:0]$13526 7'0000000
+ assign $3\core_core_srcstep$next[6:0]$13529 7'0000000
+ assign $3\core_core_vl$next[6:0]$13532 7'0000000
+ assign $3\core_core_maxvl$next[6:0]$13527 7'0000000
case
- assign $3\core_core_dststep$next[6:0]$13650 $1\core_core_dststep$next[6:0]$13630
- assign $3\core_core_maxvl$next[6:0]$13651 $1\core_core_maxvl$next[6:0]$13631
- assign $3\core_core_pc$next[63:0]$13652 $1\core_core_pc$next[63:0]$13632
- assign $3\core_core_srcstep$next[6:0]$13653 $1\core_core_srcstep$next[6:0]$13633
- assign $3\core_core_subvl$next[1:0]$13654 $1\core_core_subvl$next[1:0]$13634
- assign $3\core_core_svstep$next[1:0]$13655 $1\core_core_svstep$next[1:0]$13635
- assign $3\core_core_vl$next[6:0]$13656 $1\core_core_vl$next[6:0]$13636
- assign $3\core_dec$next[63:0]$13657 $1\core_dec$next[63:0]$13637
- assign $3\core_eint$next[0:0]$13658 $1\core_eint$next[0:0]$13638
- assign $3\core_msr$next[63:0]$13659 $1\core_msr$next[63:0]$13639
+ assign $3\core_core_dststep$next[6:0]$13526 $1\core_core_dststep$next[6:0]$13506
+ assign $3\core_core_maxvl$next[6:0]$13527 $1\core_core_maxvl$next[6:0]$13507
+ assign $3\core_core_pc$next[63:0]$13528 $1\core_core_pc$next[63:0]$13508
+ assign $3\core_core_srcstep$next[6:0]$13529 $1\core_core_srcstep$next[6:0]$13509
+ assign $3\core_core_subvl$next[1:0]$13530 $1\core_core_subvl$next[1:0]$13510
+ assign $3\core_core_svstep$next[1:0]$13531 $1\core_core_svstep$next[1:0]$13511
+ assign $3\core_core_vl$next[6:0]$13532 $1\core_core_vl$next[6:0]$13512
+ assign $3\core_dec$next[63:0]$13533 $1\core_dec$next[63:0]$13513
+ assign $3\core_eint$next[0:0]$13534 $1\core_eint$next[0:0]$13514
+ assign $3\core_msr$next[63:0]$13535 $1\core_msr$next[63:0]$13515
end
sync always
- update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13620
- update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13621
- update \core_core_pc$next $0\core_core_pc$next[63:0]$13622
- update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13623
- update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13624
- update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13625
- update \core_core_vl$next $0\core_core_vl$next[6:0]$13626
- update \core_dec$next $0\core_dec$next[63:0]$13627
- update \core_eint$next $0\core_eint$next[0:0]$13628
- update \core_msr$next $0\core_msr$next[63:0]$13629
+ update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13496
+ update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13497
+ update \core_core_pc$next $0\core_core_pc$next[63:0]$13498
+ update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13499
+ update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13500
+ update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13501
+ update \core_core_vl$next $0\core_core_vl$next[6:0]$13502
+ update \core_dec$next $0\core_dec$next[63:0]$13503
+ update \core_eint$next $0\core_eint$next[0:0]$13504
+ update \core_msr$next $0\core_msr$next[63:0]$13505
end
- attribute \src "libresoc.v:195917.3-195949.6"
- process $proc$libresoc.v:195917$13660
+ attribute \src "libresoc.v:192841.3-192861.6"
+ process $proc$libresoc.v:192841$13536
assign { } { }
assign { } { }
assign { } { }
- assign { } { }
- assign $0\core_raw_insn_i$next[31:0]$13661 $5\core_raw_insn_i$next[31:0]$13666
- attribute \src "libresoc.v:195918.5-195918.29"
+ assign $0\core_raw_insn_i$next[31:0]$13537 $3\core_raw_insn_i$next[31:0]$13540
+ attribute \src "libresoc.v:192842.5-192842.29"
switch \initial
- attribute \src "libresoc.v:195918.9-195918.17"
+ attribute \src "libresoc.v:192842.9-192842.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'010
+ case 3'001
assign { } { }
- assign $1\core_raw_insn_i$next[31:0]$13662 $2\core_raw_insn_i$next[31:0]$13663
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
+ assign $1\core_raw_insn_i$next[31:0]$13538 $2\core_raw_insn_i$next[31:0]$13539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_raw_insn_i$next[31:0]$13663 \dec2_raw_opcode_in
+ assign $2\core_raw_insn_i$next[31:0]$13539 \dec2_raw_opcode_in
case
- assign $2\core_raw_insn_i$next[31:0]$13663 \core_raw_insn_i
+ assign $2\core_raw_insn_i$next[31:0]$13539 \core_raw_insn_i
end
case
- assign $1\core_raw_insn_i$next[31:0]$13662 \core_raw_insn_i
+ assign $1\core_raw_insn_i$next[31:0]$13538 \core_raw_insn_i
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_raw_insn_i$next[31:0]$13664 $4\core_raw_insn_i$next[31:0]$13665
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$135
+ assign $3\core_raw_insn_i$next[31:0]$13540 0
+ case
+ assign $3\core_raw_insn_i$next[31:0]$13540 $1\core_raw_insn_i$next[31:0]$13538
+ end
+ sync always
+ update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13537
+ end
+ attribute \src "libresoc.v:192862.3-192886.6"
+ process $proc$libresoc.v:192862$13541
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\core_bigendian_i$10$next[0:0]$13542 $3\core_bigendian_i$10$next[0:0]$13545
+ attribute \src "libresoc.v:192863.5-192863.29"
+ switch \initial
+ attribute \src "libresoc.v:192863.9-192863.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'001
+ assign { } { }
+ assign $1\core_bigendian_i$10$next[0:0]$13543 $2\core_bigendian_i$10$next[0:0]$13544
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
+ switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\core_raw_insn_i$next[31:0]$13665 0
+ assign $2\core_bigendian_i$10$next[0:0]$13544 \core_bigendian_i
case
- assign $4\core_raw_insn_i$next[31:0]$13665 $1\core_raw_insn_i$next[31:0]$13662
+ assign $2\core_bigendian_i$10$next[0:0]$13544 \core_bigendian_i$10
end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'100
+ assign { } { }
+ assign $1\core_bigendian_i$10$next[0:0]$13543 \core_bigendian_i
case
- assign $3\core_raw_insn_i$next[31:0]$13664 $1\core_raw_insn_i$next[31:0]$13662
+ assign $1\core_bigendian_i$10$next[0:0]$13543 \core_bigendian_i$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\core_raw_insn_i$next[31:0]$13666 0
+ assign $3\core_bigendian_i$10$next[0:0]$13545 1'0
case
- assign $5\core_raw_insn_i$next[31:0]$13666 $3\core_raw_insn_i$next[31:0]$13664
+ assign $3\core_bigendian_i$10$next[0:0]$13545 $1\core_bigendian_i$10$next[0:0]$13543
end
sync always
- update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13661
+ update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13542
end
- attribute \src "libresoc.v:195950.3-195982.6"
- process $proc$libresoc.v:195950$13667
- assign { } { }
- assign { } { }
+ attribute \src "libresoc.v:192887.3-192897.6"
+ process $proc$libresoc.v:192887$13546
assign { } { }
assign { } { }
- assign $0\core_bigendian_i$10$next[0:0]$13668 $5\core_bigendian_i$10$next[0:0]$13673
- attribute \src "libresoc.v:195951.5-195951.29"
+ assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0]
+ attribute \src "libresoc.v:192888.5-192888.29"
switch \initial
- attribute \src "libresoc.v:195951.9-195951.17"
+ attribute \src "libresoc.v:192888.9-192888.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\core_bigendian_i$10$next[0:0]$13669 $2\core_bigendian_i$10$next[0:0]$13670
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
- switch \fetch_insn_valid_o
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\core_bigendian_i$10$next[0:0]$13670 \core_bigendian_i
- case
- assign $2\core_bigendian_i$10$next[0:0]$13670 \core_bigendian_i$10
- end
+ assign $1\exec_insn_valid_i[0:0] 1'1
case
- assign $1\core_bigendian_i$10$next[0:0]$13669 \core_bigendian_i$10
+ assign $1\exec_insn_valid_i[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
- attribute \src "libresoc.v:0.0-0.0"
+ sync always
+ update \exec_insn_valid_i $0\exec_insn_valid_i[0:0]
+ end
+ attribute \src "libresoc.v:192898.3-192913.6"
+ process $proc$libresoc.v:192898$13547
+ assign { } { }
+ assign { } { }
+ assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0]
+ attribute \src "libresoc.v:192899.5-192899.29"
+ switch \initial
+ attribute \src "libresoc.v:192899.9-192899.17"
case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
assign { } { }
- assign $3\core_bigendian_i$10$next[0:0]$13671 $4\core_bigendian_i$10$next[0:0]$13672
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$137
+ assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$230
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\core_bigendian_i$10$next[0:0]$13672 1'0
+ assign $2\exec_pc_ready_i[0:0] 1'1
case
- assign $4\core_bigendian_i$10$next[0:0]$13672 $1\core_bigendian_i$10$next[0:0]$13669
+ assign $2\exec_pc_ready_i[0:0] 1'0
end
case
- assign $3\core_bigendian_i$10$next[0:0]$13671 $1\core_bigendian_i$10$next[0:0]$13669
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\core_bigendian_i$10$next[0:0]$13673 1'0
- case
- assign $5\core_bigendian_i$10$next[0:0]$13673 $3\core_bigendian_i$10$next[0:0]$13671
+ assign $1\exec_pc_ready_i[0:0] 1'0
end
sync always
- update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13668
+ update \exec_pc_ready_i $0\exec_pc_ready_i[0:0]
end
- attribute \src "libresoc.v:195983.3-195993.6"
- process $proc$libresoc.v:195983$13674
+ attribute \src "libresoc.v:192914.3-192934.6"
+ process $proc$libresoc.v:192914$13548
assign { } { }
assign { } { }
- assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:195984.5-195984.29"
+ assign $0\next_srcstep[6:0] $1\next_srcstep[6:0]
+ attribute \src "libresoc.v:192915.5-192915.29"
switch \initial
- attribute \src "libresoc.v:195984.9-195984.17"
+ attribute \src "libresoc.v:192915.9-192915.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\exec_insn_valid_i[0:0] 1'1
+ assign $1\next_srcstep[6:0] $2\next_srcstep[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$236
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\next_srcstep[6:0] $3\next_srcstep[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\next_srcstep[6:0] \$238 [6:0]
+ case
+ assign $3\next_srcstep[6:0] 7'0000000
+ end
+ case
+ assign $2\next_srcstep[6:0] 7'0000000
+ end
case
- assign $1\exec_insn_valid_i[0:0] 1'0
+ assign $1\next_srcstep[6:0] 7'0000000
end
sync always
- update \exec_insn_valid_i $0\exec_insn_valid_i[0:0]
+ update \next_srcstep $0\next_srcstep[6:0]
end
- attribute \src "libresoc.v:195994.3-196009.6"
- process $proc$libresoc.v:195994$13675
+ attribute \src "libresoc.v:192935.3-192955.6"
+ process $proc$libresoc.v:192935$13549
assign { } { }
assign { } { }
- assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:195995.5-195995.29"
+ assign $0\is_last[0:0] $1\is_last[0:0]
+ attribute \src "libresoc.v:192936.5-192936.29"
switch \initial
- attribute \src "libresoc.v:195995.9-195995.17"
+ attribute \src "libresoc.v:192936.9-192936.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'011
assign { } { }
- assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- switch \$143
+ assign $1\is_last[0:0] $2\is_last[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$245
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\exec_pc_valid_o[0:0] 1'1
+ assign $2\is_last[0:0] $3\is_last[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\is_last[0:0] \$247
+ case
+ assign $3\is_last[0:0] 1'0
+ end
case
- assign $2\exec_pc_valid_o[0:0] 1'0
+ assign $2\is_last[0:0] 1'0
end
case
- assign $1\exec_pc_valid_o[0:0] 1'0
+ assign $1\is_last[0:0] 1'0
end
sync always
- update \exec_pc_valid_o $0\exec_pc_valid_o[0:0]
+ update \is_last $0\is_last[0:0]
end
- attribute \src "libresoc.v:196010.3-196019.6"
- process $proc$libresoc.v:196010$13676
+ attribute \src "libresoc.v:192956.3-192965.6"
+ process $proc$libresoc.v:192956$13550
assign { } { }
assign { } { }
- assign $0\core_wen$11[2:0]$13677 $1\core_wen$11[2:0]$13678
- attribute \src "libresoc.v:196011.5-196011.29"
+ assign $0\core_wen$11[2:0]$13551 $1\core_wen$11[2:0]$13552
+ attribute \src "libresoc.v:192957.5-192957.29"
switch \initial
- attribute \src "libresoc.v:196011.9-196011.17"
+ attribute \src "libresoc.v:192957.9-192957.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_wen$11[2:0]$13678 3'100
+ assign $1\core_wen$11[2:0]$13552 3'100
case
- assign $1\core_wen$11[2:0]$13678 3'000
+ assign $1\core_wen$11[2:0]$13552 3'000
end
sync always
- update \core_wen$11 $0\core_wen$11[2:0]$13677
+ update \core_wen$11 $0\core_wen$11[2:0]$13551
end
- attribute \src "libresoc.v:196020.3-196029.6"
- process $proc$libresoc.v:196020$13679
+ attribute \src "libresoc.v:192966.3-192975.6"
+ process $proc$libresoc.v:192966$13553
assign { } { }
assign { } { }
- assign $0\core_data_i$12[63:0]$13680 $1\core_data_i$12[63:0]$13681
- attribute \src "libresoc.v:196021.5-196021.29"
+ assign $0\core_data_i$12[63:0]$13554 $1\core_data_i$12[63:0]$13555
+ attribute \src "libresoc.v:192967.5-192967.29"
switch \initial
- attribute \src "libresoc.v:196021.9-196021.17"
+ attribute \src "libresoc.v:192967.9-192967.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_data_i$12[63:0]$13681 \$145
+ assign $1\core_data_i$12[63:0]$13555 \$249
case
- assign $1\core_data_i$12[63:0]$13681 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\core_data_i$12[63:0]$13555 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \core_data_i$12 $0\core_data_i$12[63:0]$13680
+ update \core_data_i$12 $0\core_data_i$12[63:0]$13554
end
- attribute \src "libresoc.v:196030.3-196040.6"
- process $proc$libresoc.v:196030$13682
+ attribute \src "libresoc.v:192976.3-192986.6"
+ process $proc$libresoc.v:192976$13556
assign { } { }
assign { } { }
assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:196031.5-196031.29"
+ attribute \src "libresoc.v:192977.5-192977.29"
switch \initial
- attribute \src "libresoc.v:196031.9-196031.17"
+ attribute \src "libresoc.v:192977.9-192977.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
sync always
update \exec_insn_ready_o $0\exec_insn_ready_o[0:0]
end
- attribute \src "libresoc.v:196041.3-196065.6"
- process $proc$libresoc.v:196041$13683
+ attribute \src "libresoc.v:192987.3-193011.6"
+ process $proc$libresoc.v:192987$13557
assign { } { }
assign { } { }
assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:196042.5-196042.29"
+ attribute \src "libresoc.v:192988.5-192988.29"
switch \initial
- attribute \src "libresoc.v:196042.9-196042.17"
+ attribute \src "libresoc.v:192988.9-192988.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
assign { } { }
assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
- switch \$147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441"
+ switch \$251
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
sync always
update \core_ivalid_i $0\core_ivalid_i[0:0]
end
- attribute \src "libresoc.v:196066.3-196081.6"
- process $proc$libresoc.v:196066$13684
+ attribute \src "libresoc.v:193012.3-193027.6"
+ process $proc$libresoc.v:193012$13558
assign { } { }
assign { } { }
assign $0\core_issue_i[0:0] $1\core_issue_i[0:0]
- attribute \src "libresoc.v:196067.5-196067.29"
+ attribute \src "libresoc.v:193013.5-193013.29"
switch \initial
- attribute \src "libresoc.v:196067.9-196067.17"
+ attribute \src "libresoc.v:193013.9-193013.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_issue_i[0:0] $2\core_issue_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_issue_i $0\core_issue_i[0:0]
end
- attribute \src "libresoc.v:196082.3-196116.6"
- process $proc$libresoc.v:196082$13685
+ attribute \src "libresoc.v:193028.3-193062.6"
+ process $proc$libresoc.v:193028$13559
assign { } { }
assign { } { }
assign { } { }
- assign $0\exec_fsm_state$next[0:0]$13686 $5\exec_fsm_state$next[0:0]$13691
- attribute \src "libresoc.v:196083.5-196083.29"
+ assign $0\exec_fsm_state$next[0:0]$13560 $5\exec_fsm_state$next[0:0]$13565
+ attribute \src "libresoc.v:193029.5-193029.29"
switch \initial
- attribute \src "libresoc.v:196083.9-196083.17"
+ attribute \src "libresoc.v:193029.9-193029.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13687 $2\exec_fsm_state$next[0:0]$13688
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
+ assign $1\exec_fsm_state$next[0:0]$13561 $2\exec_fsm_state$next[0:0]$13562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\exec_fsm_state$next[0:0]$13688 1'1
+ assign $2\exec_fsm_state$next[0:0]$13562 1'1
case
- assign $2\exec_fsm_state$next[0:0]$13688 \exec_fsm_state
+ assign $2\exec_fsm_state$next[0:0]$13562 \exec_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13687 $3\exec_fsm_state$next[0:0]$13689
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$149
+ assign $1\exec_fsm_state$next[0:0]$13561 $3\exec_fsm_state$next[0:0]$13563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ switch \$253
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\exec_fsm_state$next[0:0]$13689 $4\exec_fsm_state$next[0:0]$13690
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:395"
- switch \exec_pc_valid_o
+ assign $3\exec_fsm_state$next[0:0]$13563 $4\exec_fsm_state$next[0:0]$13564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:450"
+ switch \exec_pc_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\exec_fsm_state$next[0:0]$13690 1'0
+ assign $4\exec_fsm_state$next[0:0]$13564 1'0
case
- assign $4\exec_fsm_state$next[0:0]$13690 \exec_fsm_state
+ assign $4\exec_fsm_state$next[0:0]$13564 \exec_fsm_state
end
case
- assign $3\exec_fsm_state$next[0:0]$13689 \exec_fsm_state
- end
- case
- assign $1\exec_fsm_state$next[0:0]$13687 \exec_fsm_state
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $5\exec_fsm_state$next[0:0]$13691 1'0
- case
- assign $5\exec_fsm_state$next[0:0]$13691 $1\exec_fsm_state$next[0:0]$13687
- end
- sync always
- update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13686
- end
- attribute \src "libresoc.v:196117.3-196145.6"
- process $proc$libresoc.v:196117$13692
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\sv_changed$next[0:0]$13693 $4\sv_changed$next[0:0]$13697
- attribute \src "libresoc.v:196118.5-196118.29"
- switch \initial
- attribute \src "libresoc.v:196118.9-196118.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign $1\sv_changed$next[0:0]$13694 $3\sv_changed$next[0:0]$13696
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
- switch \$151
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\sv_changed$next[0:0]$13695 1'1
- case
- assign $2\sv_changed$next[0:0]$13695 \sv_changed
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$155
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\sv_changed$next[0:0]$13696 1'0
- case
- assign $3\sv_changed$next[0:0]$13696 $2\sv_changed$next[0:0]$13695
- end
- case
- assign $1\sv_changed$next[0:0]$13694 \sv_changed
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\sv_changed$next[0:0]$13697 1'0
- case
- assign $4\sv_changed$next[0:0]$13697 $1\sv_changed$next[0:0]$13694
- end
- sync always
- update \sv_changed$next $0\sv_changed$next[0:0]$13693
- end
- attribute \src "libresoc.v:196146.3-196174.6"
- process $proc$libresoc.v:196146$13698
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\pc_changed$next[0:0]$13699 $4\pc_changed$next[0:0]$13703
- attribute \src "libresoc.v:196147.5-196147.29"
- switch \initial
- attribute \src "libresoc.v:196147.9-196147.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign $1\pc_changed$next[0:0]$13700 $3\pc_changed$next[0:0]$13702
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
- switch \$157
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\pc_changed$next[0:0]$13701 1'1
- case
- assign $2\pc_changed$next[0:0]$13701 \pc_changed
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$161
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\pc_changed$next[0:0]$13702 1'0
- case
- assign $3\pc_changed$next[0:0]$13702 $2\pc_changed$next[0:0]$13701
+ assign $3\exec_fsm_state$next[0:0]$13563 \exec_fsm_state
end
case
- assign $1\pc_changed$next[0:0]$13700 \pc_changed
+ assign $1\exec_fsm_state$next[0:0]$13561 \exec_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\pc_changed$next[0:0]$13703 1'0
+ assign $5\exec_fsm_state$next[0:0]$13565 1'0
case
- assign $4\pc_changed$next[0:0]$13703 $1\pc_changed$next[0:0]$13700
+ assign $5\exec_fsm_state$next[0:0]$13565 $1\exec_fsm_state$next[0:0]$13561
end
sync always
- update \pc_changed$next $0\pc_changed$next[0:0]$13699
+ update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13560
end
- attribute \src "libresoc.v:196175.3-196190.6"
- process $proc$libresoc.v:196175$13704
+ attribute \src "libresoc.v:193063.3-193078.6"
+ process $proc$libresoc.v:193063$13566
assign { } { }
assign { } { }
- assign $0\insn_done[0:0] $1\insn_done[0:0]
- attribute \src "libresoc.v:196176.5-196176.29"
- switch \initial
- attribute \src "libresoc.v:196176.9-196176.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\insn_done[0:0] $2\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$163
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $2\insn_done[0:0] 1'1
- case
- assign $2\insn_done[0:0] 1'0
- end
- case
- assign $1\insn_done[0:0] 1'0
- end
- sync always
- update \insn_done $0\insn_done[0:0]
- end
- attribute \src "libresoc.v:196191.3-196206.6"
- process $proc$libresoc.v:196191$13705
- assign { } { }
- assign { } { }
- assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:196192.5-196192.29"
+ assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0]
+ attribute \src "libresoc.v:193064.5-193064.29"
switch \initial
- attribute \src "libresoc.v:196192.9-196192.17"
+ attribute \src "libresoc.v:193064.9-193064.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$165
+ assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ switch \$255
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\exec_pc_ready_i[0:0] 1'1
+ assign $2\exec_pc_valid_o[0:0] 1'1
case
- assign $2\exec_pc_ready_i[0:0] 1'0
+ assign $2\exec_pc_valid_o[0:0] 1'0
end
case
- assign $1\exec_pc_ready_i[0:0] 1'0
+ assign $1\exec_pc_valid_o[0:0] 1'0
end
sync always
- update \exec_pc_ready_i $0\exec_pc_ready_i[0:0]
+ update \exec_pc_valid_o $0\exec_pc_valid_o[0:0]
end
- attribute \src "libresoc.v:196207.3-196216.6"
- process $proc$libresoc.v:196207$13706
+ attribute \src "libresoc.v:193079.3-193088.6"
+ process $proc$libresoc.v:193079$13567
assign { } { }
assign { } { }
assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:196208.5-196208.29"
+ attribute \src "libresoc.v:193080.5-193080.29"
switch \initial
- attribute \src "libresoc.v:196208.9-196208.17"
+ attribute \src "libresoc.v:193080.9-193080.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__addr $0\core_dmi__addr[4:0]
end
- attribute \src "libresoc.v:196217.3-196226.6"
- process $proc$libresoc.v:196217$13707
+ attribute \src "libresoc.v:193089.3-193098.6"
+ process $proc$libresoc.v:193089$13568
assign { } { }
assign { } { }
assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:196218.5-196218.29"
+ attribute \src "libresoc.v:193090.5-193090.29"
switch \initial
- attribute \src "libresoc.v:196218.9-196218.17"
+ attribute \src "libresoc.v:193090.9-193090.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__ren $0\core_dmi__ren[0:0]
end
- attribute \src "libresoc.v:196227.3-196235.6"
- process $proc$libresoc.v:196227$13708
+ attribute \src "libresoc.v:193099.3-193107.6"
+ process $proc$libresoc.v:193099$13569
assign { } { }
assign { } { }
- assign $0\d_reg_delay$next[0:0]$13709 $1\d_reg_delay$next[0:0]$13710
- attribute \src "libresoc.v:196228.5-196228.29"
+ assign $0\d_reg_delay$next[0:0]$13570 $1\d_reg_delay$next[0:0]$13571
+ attribute \src "libresoc.v:193100.5-193100.29"
switch \initial
- attribute \src "libresoc.v:196228.9-196228.17"
+ attribute \src "libresoc.v:193100.9-193100.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_reg_delay$next[0:0]$13710 1'0
+ assign $1\d_reg_delay$next[0:0]$13571 1'0
case
- assign $1\d_reg_delay$next[0:0]$13710 \dbg_d_gpr_req
+ assign $1\d_reg_delay$next[0:0]$13571 \dbg_d_gpr_req
end
sync always
- update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13709
+ update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13570
end
- attribute \src "libresoc.v:196236.3-196245.6"
- process $proc$libresoc.v:196236$13711
+ attribute \src "libresoc.v:193108.3-193117.6"
+ process $proc$libresoc.v:193108$13572
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:196237.5-196237.29"
+ attribute \src "libresoc.v:193109.5-193109.29"
switch \initial
- attribute \src "libresoc.v:196237.9-196237.17"
+ attribute \src "libresoc.v:193109.9-193109.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:196246.3-196255.6"
- process $proc$libresoc.v:196246$13712
+ attribute \src "libresoc.v:193118.3-193127.6"
+ process $proc$libresoc.v:193118$13573
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:196247.5-196247.29"
+ attribute \src "libresoc.v:193119.5-193119.29"
switch \initial
- attribute \src "libresoc.v:196247.9-196247.17"
+ attribute \src "libresoc.v:193119.9-193119.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:196256.3-196265.6"
- process $proc$libresoc.v:196256$13713
+ attribute \src "libresoc.v:193128.3-193137.6"
+ process $proc$libresoc.v:193128$13574
assign { } { }
assign { } { }
assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:196257.5-196257.29"
+ attribute \src "libresoc.v:193129.5-193129.29"
switch \initial
- attribute \src "libresoc.v:196257.9-196257.17"
+ attribute \src "libresoc.v:193129.9-193129.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
switch \dbg_d_cr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd2__ren $0\core_full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:196266.3-196274.6"
- process $proc$libresoc.v:196266$13714
+ attribute \src "libresoc.v:193138.3-193146.6"
+ process $proc$libresoc.v:193138$13575
assign { } { }
assign { } { }
- assign $0\d_cr_delay$next[0:0]$13715 $1\d_cr_delay$next[0:0]$13716
- attribute \src "libresoc.v:196267.5-196267.29"
+ assign $0\d_cr_delay$next[0:0]$13576 $1\d_cr_delay$next[0:0]$13577
+ attribute \src "libresoc.v:193139.5-193139.29"
switch \initial
- attribute \src "libresoc.v:196267.9-196267.17"
+ attribute \src "libresoc.v:193139.9-193139.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_cr_delay$next[0:0]$13716 1'0
+ assign $1\d_cr_delay$next[0:0]$13577 1'0
case
- assign $1\d_cr_delay$next[0:0]$13716 \dbg_d_cr_req
+ assign $1\d_cr_delay$next[0:0]$13577 \dbg_d_cr_req
end
sync always
- update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13715
+ update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13576
end
- attribute \src "libresoc.v:196275.3-196284.6"
- process $proc$libresoc.v:196275$13717
+ attribute \src "libresoc.v:193147.3-193156.6"
+ process $proc$libresoc.v:193147$13578
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:196276.5-196276.29"
+ attribute \src "libresoc.v:193148.5-193148.29"
switch \initial
- attribute \src "libresoc.v:196276.9-196276.17"
+ attribute \src "libresoc.v:193148.9-193148.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:590"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_d_cr_data[63:0] \$167
+ assign $1\dbg_d_cr_data[63:0] \$257
case
assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:196285.3-196294.6"
- process $proc$libresoc.v:196285$13718
+ attribute \src "libresoc.v:193157.3-193166.6"
+ process $proc$libresoc.v:193157$13579
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:196286.5-196286.29"
+ attribute \src "libresoc.v:193158.5-193158.29"
switch \initial
- attribute \src "libresoc.v:196286.9-196286.17"
+ attribute \src "libresoc.v:193158.9-193158.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:590"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:196295.3-196304.6"
- process $proc$libresoc.v:196295$13719
+ attribute \src "libresoc.v:193167.3-193176.6"
+ process $proc$libresoc.v:193167$13580
assign { } { }
assign { } { }
assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:196296.5-196296.29"
+ attribute \src "libresoc.v:193168.5-193168.29"
switch \initial
- attribute \src "libresoc.v:196296.9-196296.17"
+ attribute \src "libresoc.v:193168.9-193168.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665"
switch \dbg_d_xer_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd__ren $0\core_full_rd__ren[2:0]
end
- attribute \src "libresoc.v:196305.3-196313.6"
- process $proc$libresoc.v:196305$13720
+ attribute \src "libresoc.v:193177.3-193185.6"
+ process $proc$libresoc.v:193177$13581
assign { } { }
assign { } { }
- assign $0\d_xer_delay$next[0:0]$13721 $1\d_xer_delay$next[0:0]$13722
- attribute \src "libresoc.v:196306.5-196306.29"
+ assign $0\d_xer_delay$next[0:0]$13582 $1\d_xer_delay$next[0:0]$13583
+ attribute \src "libresoc.v:193178.5-193178.29"
switch \initial
- attribute \src "libresoc.v:196306.9-196306.17"
+ attribute \src "libresoc.v:193178.9-193178.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_xer_delay$next[0:0]$13722 1'0
+ assign $1\d_xer_delay$next[0:0]$13583 1'0
case
- assign $1\d_xer_delay$next[0:0]$13722 \dbg_d_xer_req
+ assign $1\d_xer_delay$next[0:0]$13583 \dbg_d_xer_req
end
sync always
- update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13721
+ update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13582
end
- attribute \src "libresoc.v:196314.3-196323.6"
- process $proc$libresoc.v:196314$13723
+ attribute \src "libresoc.v:193186.3-193195.6"
+ process $proc$libresoc.v:193186$13584
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:196315.5-196315.29"
+ attribute \src "libresoc.v:193187.5-193187.29"
switch \initial
- attribute \src "libresoc.v:196315.9-196315.17"
+ attribute \src "libresoc.v:193187.9-193187.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_d_xer_data[63:0] \$169
+ assign $1\dbg_d_xer_data[63:0] \$259
case
assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:196324.3-196333.6"
- process $proc$libresoc.v:196324$13724
+ attribute \src "libresoc.v:193196.3-193205.6"
+ process $proc$libresoc.v:193196$13585
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:196325.5-196325.29"
+ attribute \src "libresoc.v:193197.5-193197.29"
switch \initial
- attribute \src "libresoc.v:196325.9-196325.17"
+ attribute \src "libresoc.v:193197.9-193197.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:196334.3-196348.6"
- process $proc$libresoc.v:196334$13725
+ attribute \src "libresoc.v:193206.3-193220.6"
+ process $proc$libresoc.v:193206$13586
assign { } { }
assign { } { }
assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:196335.5-196335.29"
+ attribute \src "libresoc.v:193207.5-193207.29"
switch \initial
- attribute \src "libresoc.v:196335.9-196335.17"
+ attribute \src "libresoc.v:193207.9-193207.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__addr $0\core_issue__addr[2:0]
end
- attribute \src "libresoc.v:196349.3-196363.6"
- process $proc$libresoc.v:196349$13726
+ attribute \src "libresoc.v:193221.3-193235.6"
+ process $proc$libresoc.v:193221$13587
assign { } { }
assign { } { }
assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:196350.5-196350.29"
+ attribute \src "libresoc.v:193222.5-193222.29"
switch \initial
- attribute \src "libresoc.v:196350.9-196350.17"
+ attribute \src "libresoc.v:193222.9-193222.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__ren $0\core_issue__ren[0:0]
end
- attribute \src "libresoc.v:196364.3-196391.6"
- process $proc$libresoc.v:196364$13727
+ attribute \src "libresoc.v:193236.3-193263.6"
+ process $proc$libresoc.v:193236$13588
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$13728 $2\fsm_state$next[1:0]$13730
- attribute \src "libresoc.v:196365.5-196365.29"
+ assign $0\fsm_state$next[1:0]$13589 $2\fsm_state$next[1:0]$13591
+ attribute \src "libresoc.v:193237.5-193237.29"
switch \initial
- attribute \src "libresoc.v:196365.9-196365.17"
+ attribute \src "libresoc.v:193237.9-193237.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$13729 2'01
+ assign $1\fsm_state$next[1:0]$13590 2'01
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$13729 2'10
+ assign $1\fsm_state$next[1:0]$13590 2'10
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$13729 2'11
+ assign $1\fsm_state$next[1:0]$13590 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$next[1:0]$13729 2'00
+ assign $1\fsm_state$next[1:0]$13590 2'00
case
- assign $1\fsm_state$next[1:0]$13729 \fsm_state
+ assign $1\fsm_state$next[1:0]$13590 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$13730 2'00
+ assign $2\fsm_state$next[1:0]$13591 2'00
case
- assign $2\fsm_state$next[1:0]$13730 $1\fsm_state$next[1:0]$13729
+ assign $2\fsm_state$next[1:0]$13591 $1\fsm_state$next[1:0]$13590
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$13728
+ update \fsm_state$next $0\fsm_state$next[1:0]$13589
end
- attribute \src "libresoc.v:196392.3-196402.6"
- process $proc$libresoc.v:196392$13731
+ attribute \src "libresoc.v:193264.3-193274.6"
+ process $proc$libresoc.v:193264$13592
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:196393.5-196393.29"
+ attribute \src "libresoc.v:193265.5-193265.29"
switch \initial
- attribute \src "libresoc.v:196393.9-196393.17"
+ attribute \src "libresoc.v:193265.9-193265.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\new_dec[63:0] \$171 [63:0]
+ assign $1\new_dec[63:0] \$261 [63:0]
case
assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:196403.3-196417.6"
- process $proc$libresoc.v:196403$13732
+ attribute \src "libresoc.v:193275.3-193289.6"
+ process $proc$libresoc.v:193275$13593
assign { } { }
assign { } { }
- assign $0\core_issue__addr$13[2:0]$13733 $1\core_issue__addr$13[2:0]$13734
- attribute \src "libresoc.v:196404.5-196404.29"
+ assign $0\core_issue__addr$13[2:0]$13594 $1\core_issue__addr$13[2:0]$13595
+ attribute \src "libresoc.v:193276.5-193276.29"
switch \initial
- attribute \src "libresoc.v:196404.9-196404.17"
+ attribute \src "libresoc.v:193276.9-193276.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13734 3'110
+ assign $1\core_issue__addr$13[2:0]$13595 3'110
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13734 3'111
+ assign $1\core_issue__addr$13[2:0]$13595 3'111
case
- assign $1\core_issue__addr$13[2:0]$13734 3'000
+ assign $1\core_issue__addr$13[2:0]$13595 3'000
end
sync always
- update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13733
+ update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13594
end
- attribute \src "libresoc.v:196418.3-196432.6"
- process $proc$libresoc.v:196418$13735
+ attribute \src "libresoc.v:193290.3-193304.6"
+ process $proc$libresoc.v:193290$13596
assign { } { }
assign { } { }
assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:196419.5-196419.29"
+ attribute \src "libresoc.v:193291.5-193291.29"
switch \initial
- attribute \src "libresoc.v:196419.9-196419.17"
+ attribute \src "libresoc.v:193291.9-193291.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
sync always
update \core_issue__wen $0\core_issue__wen[0:0]
end
- attribute \src "libresoc.v:196433.3-196447.6"
- process $proc$libresoc.v:196433$13736
+ attribute \src "libresoc.v:193305.3-193319.6"
+ process $proc$libresoc.v:193305$13597
assign { } { }
assign { } { }
assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:196434.5-196434.29"
+ attribute \src "libresoc.v:193306.5-193306.29"
switch \initial
- attribute \src "libresoc.v:196434.9-196434.17"
+ attribute \src "libresoc.v:193306.9-193306.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
sync always
update \core_issue__data_i $0\core_issue__data_i[63:0]
end
- attribute \src "libresoc.v:196448.3-196463.6"
- process $proc$libresoc.v:196448$13737
+ attribute \src "libresoc.v:193320.3-193335.6"
+ process $proc$libresoc.v:193320$13598
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_dec$next[63:0]$13738 $2\dec2_cur_dec$next[63:0]$13740
- attribute \src "libresoc.v:196449.5-196449.29"
+ assign $0\dec2_cur_dec$next[63:0]$13599 $2\dec2_cur_dec$next[63:0]$13601
+ attribute \src "libresoc.v:193321.5-193321.29"
switch \initial
- attribute \src "libresoc.v:196449.9-196449.17"
+ attribute \src "libresoc.v:193321.9-193321.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_dec$next[63:0]$13739 \new_dec
+ assign $1\dec2_cur_dec$next[63:0]$13600 \new_dec
case
- assign $1\dec2_cur_dec$next[63:0]$13739 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$13600 \dec2_cur_dec
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_dec$next[63:0]$13740 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dec2_cur_dec$next[63:0]$13601 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\dec2_cur_dec$next[63:0]$13740 $1\dec2_cur_dec$next[63:0]$13739
+ assign $2\dec2_cur_dec$next[63:0]$13601 $1\dec2_cur_dec$next[63:0]$13600
end
sync always
- update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13738
+ update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13599
end
- attribute \src "libresoc.v:196464.3-196474.6"
- process $proc$libresoc.v:196464$13741
+ attribute \src "libresoc.v:193336.3-193346.6"
+ process $proc$libresoc.v:193336$13602
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:196465.5-196465.29"
+ attribute \src "libresoc.v:193337.5-193337.29"
switch \initial
- attribute \src "libresoc.v:196465.9-196465.17"
+ attribute \src "libresoc.v:193337.9-193337.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\new_tb[63:0] \$174 [63:0]
+ assign $1\new_tb[63:0] \$264 [63:0]
case
assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:196475.3-196483.6"
- process $proc$libresoc.v:196475$13742
+ attribute \src "libresoc.v:193347.3-193355.6"
+ process $proc$libresoc.v:193347$13603
assign { } { }
assign { } { }
- assign $0\dbg_dmi_we_i$next[0:0]$13743 $1\dbg_dmi_we_i$next[0:0]$13744
- attribute \src "libresoc.v:196476.5-196476.29"
+ assign $0\dbg_dmi_we_i$next[0:0]$13604 $1\dbg_dmi_we_i$next[0:0]$13605
+ attribute \src "libresoc.v:193348.5-193348.29"
switch \initial
- attribute \src "libresoc.v:196476.9-196476.17"
+ attribute \src "libresoc.v:193348.9-193348.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_we_i$next[0:0]$13744 1'0
+ assign $1\dbg_dmi_we_i$next[0:0]$13605 1'0
case
- assign $1\dbg_dmi_we_i$next[0:0]$13744 \jtag_dmi0__we_i
+ assign $1\dbg_dmi_we_i$next[0:0]$13605 \jtag_dmi0__we_i
end
sync always
- update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13743
+ update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13604
end
- attribute \src "libresoc.v:196484.3-196492.6"
- process $proc$libresoc.v:196484$13745
+ attribute \src "libresoc.v:193356.3-193364.6"
+ process $proc$libresoc.v:193356$13606
assign { } { }
assign { } { }
- assign $0\pc_ok_delay$next[0:0]$13746 $1\pc_ok_delay$next[0:0]$13747
- attribute \src "libresoc.v:196485.5-196485.29"
+ assign $0\pc_ok_delay$next[0:0]$13607 $1\pc_ok_delay$next[0:0]$13608
+ attribute \src "libresoc.v:193357.5-193357.29"
switch \initial
- attribute \src "libresoc.v:196485.9-196485.17"
+ attribute \src "libresoc.v:193357.9-193357.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pc_ok_delay$next[0:0]$13747 1'0
+ assign $1\pc_ok_delay$next[0:0]$13608 1'0
case
- assign $1\pc_ok_delay$next[0:0]$13747 \$38
+ assign $1\pc_ok_delay$next[0:0]$13608 \$38
end
sync always
- update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13746
+ update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13607
end
- attribute \src "libresoc.v:196493.3-196508.6"
- process $proc$libresoc.v:196493$13748
+ attribute \src "libresoc.v:193365.3-193380.6"
+ process $proc$libresoc.v:193365$13609
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:196494.5-196494.29"
+ attribute \src "libresoc.v:193366.5-193366.29"
switch \initial
- attribute \src "libresoc.v:196494.9-196494.17"
+ attribute \src "libresoc.v:193366.9-193366.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:483"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:490"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:545"
switch \pc_ok_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:196509.3-196521.6"
- process $proc$libresoc.v:196509$13749
+ attribute \src "libresoc.v:193381.3-193393.6"
+ process $proc$libresoc.v:193381$13610
assign { } { }
assign { } { }
assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:196510.5-196510.29"
+ attribute \src "libresoc.v:193382.5-193382.29"
switch \initial
- attribute \src "libresoc.v:196510.9-196510.17"
+ attribute \src "libresoc.v:193382.9-193382.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:483"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_cia__ren $0\core_cia__ren[2:0]
end
- attribute \src "libresoc.v:196522.3-196530.6"
- process $proc$libresoc.v:196522$13750
+ attribute \src "libresoc.v:193394.3-193402.6"
+ process $proc$libresoc.v:193394$13611
assign { } { }
assign { } { }
- assign $0\svstate_ok_delay$next[0:0]$13751 $1\svstate_ok_delay$next[0:0]$13752
- attribute \src "libresoc.v:196523.5-196523.29"
+ assign $0\svstate_ok_delay$next[0:0]$13612 $1\svstate_ok_delay$next[0:0]$13613
+ attribute \src "libresoc.v:193395.5-193395.29"
switch \initial
- attribute \src "libresoc.v:196523.9-196523.17"
+ attribute \src "libresoc.v:193395.9-193395.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\svstate_ok_delay$next[0:0]$13752 1'0
+ assign $1\svstate_ok_delay$next[0:0]$13613 1'0
case
- assign $1\svstate_ok_delay$next[0:0]$13752 \$40
+ assign $1\svstate_ok_delay$next[0:0]$13613 \$40
end
sync always
- update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13751
+ update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13612
end
- attribute \src "libresoc.v:196531.3-196546.6"
- process $proc$libresoc.v:196531$13753
+ attribute \src "libresoc.v:193403.3-193418.6"
+ process $proc$libresoc.v:193403$13614
assign { } { }
assign { } { }
assign { } { }
assign $0\svstate[63:0] $2\svstate[63:0]
- attribute \src "libresoc.v:196532.5-196532.29"
+ attribute \src "libresoc.v:193404.5-193404.29"
switch \initial
- attribute \src "libresoc.v:196532.9-196532.17"
+ attribute \src "libresoc.v:193404.9-193404.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:497"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
switch \svstate_ok_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \svstate $0\svstate[63:0]
end
- attribute \src "libresoc.v:196547.3-196559.6"
- process $proc$libresoc.v:196547$13754
+ attribute \src "libresoc.v:193419.3-193431.6"
+ process $proc$libresoc.v:193419$13615
assign { } { }
assign { } { }
assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:196548.5-196548.29"
+ attribute \src "libresoc.v:193420.5-193420.29"
switch \initial
- attribute \src "libresoc.v:196548.9-196548.17"
+ attribute \src "libresoc.v:193420.9-193420.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:497"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_sv__ren $0\core_sv__ren[2:0]
end
- attribute \src "libresoc.v:196560.3-196568.6"
- process $proc$libresoc.v:196560$13755
- assign { } { }
- assign { } { }
- assign $0\dbg_dmi_din$next[63:0]$13756 $1\dbg_dmi_din$next[63:0]$13757
- attribute \src "libresoc.v:196561.5-196561.29"
- switch \initial
- attribute \src "libresoc.v:196561.9-196561.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dbg_dmi_din$next[63:0]$13757 64'0000000000000000000000000000000000000000000000000000000000000000
- case
- assign $1\dbg_dmi_din$next[63:0]$13757 \jtag_dmi0__din
- end
- sync always
- update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13756
- end
- attribute \src "libresoc.v:196569.3-196594.6"
- process $proc$libresoc.v:196569$13758
+ attribute \src "libresoc.v:193432.3-193499.6"
+ process $proc$libresoc.v:193432$13616
assign { } { }
assign { } { }
assign $0\core_wen[2:0] $1\core_wen[2:0]
- attribute \src "libresoc.v:196570.5-196570.29"
+ attribute \src "libresoc.v:193433.5-193433.29"
switch \initial
- attribute \src "libresoc.v:196570.9-196570.17"
+ attribute \src "libresoc.v:193433.9-193433.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'000
assign { } { }
assign $1\core_wen[2:0] $2\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
switch \$48
attribute \src "libresoc.v:0.0-0.0"
case 1'1
+ assign $2\core_wen[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case
assign { } { }
assign $2\core_wen[2:0] $3\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
- switch \exec_pc_ready_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
+ switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_wen[2:0] $4\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
- switch \$50
+ assign $3\core_wen[2:0] 3'001
+ case
+ assign $3\core_wen[2:0] 3'000
+ end
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'001
+ assign { } { }
+ assign $1\core_wen[2:0] $4\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
+ switch \fetch_insn_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\core_wen[2:0] $5\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ switch \$54
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\core_wen[2:0] 3'001
+ case
+ assign $5\core_wen[2:0] 3'000
+ end
+ case
+ assign $4\core_wen[2:0] 3'000
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\core_wen[2:0] $6\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$60
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\core_wen[2:0] $7\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\core_wen[2:0] $8\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ switch { \$64 \$62 }
attribute \src "libresoc.v:0.0-0.0"
- case 1'1
+ case 2'-1
+ assign $8\core_wen[2:0] 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
assign { } { }
- assign $4\core_wen[2:0] 3'001
+ assign $8\core_wen[2:0] 3'001
case
- assign $4\core_wen[2:0] 3'000
+ assign $8\core_wen[2:0] 3'000
end
case
- assign $3\core_wen[2:0] 3'000
+ assign $7\core_wen[2:0] 3'000
end
+ attribute \src "libresoc.v:0.0-0.0"
case
- assign $2\core_wen[2:0] 3'000
+ assign { } { }
+ assign $6\core_wen[2:0] $9\core_wen[2:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
+ switch \pc_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $9\core_wen[2:0] 3'001
+ case
+ assign $9\core_wen[2:0] 3'000
+ end
end
case
assign $1\core_wen[2:0] 3'000
sync always
update \core_wen $0\core_wen[2:0]
end
- attribute \src "libresoc.v:196595.3-196620.6"
- process $proc$libresoc.v:196595$13759
+ attribute \src "libresoc.v:193500.3-193567.6"
+ process $proc$libresoc.v:193500$13617
assign { } { }
assign { } { }
assign $0\core_data_i[63:0] $1\core_data_i[63:0]
- attribute \src "libresoc.v:196596.5-196596.29"
+ attribute \src "libresoc.v:193501.5-193501.29"
switch \initial
- attribute \src "libresoc.v:196596.9-196596.17"
+ attribute \src "libresoc.v:193501.9-193501.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'000
assign { } { }
assign $1\core_data_i[63:0] $2\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- switch \$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$70
attribute \src "libresoc.v:0.0-0.0"
case 1'1
+ assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case
assign { } { }
assign $2\core_data_i[63:0] $3\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
- switch \exec_pc_ready_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
+ switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_data_i[63:0] $4\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
- switch \$58
+ assign $3\core_data_i[63:0] \pc_i
+ case
+ assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'001
+ assign { } { }
+ assign $1\core_data_i[63:0] $4\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
+ switch \fetch_insn_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\core_data_i[63:0] $5\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ switch \$76
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\core_data_i[63:0] \nia
+ case
+ assign $5\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ case
+ assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\core_data_i[63:0] $6\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$82
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\core_data_i[63:0] $7\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\core_data_i[63:0] $8\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ switch { \$86 \$84 }
attribute \src "libresoc.v:0.0-0.0"
- case 1'1
+ case 2'-1
+ assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
assign { } { }
- assign $4\core_data_i[63:0] \nia
+ assign $8\core_data_i[63:0] \nia
case
- assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $7\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
+ attribute \src "libresoc.v:0.0-0.0"
case
- assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign { } { }
+ assign $6\core_data_i[63:0] $9\core_data_i[63:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
+ switch \pc_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $9\core_data_i[63:0] \pc_i
+ case
+ assign $9\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
end
case
assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \core_data_i $0\core_data_i[63:0]
end
- attribute \src "libresoc.v:196621.3-196636.6"
- process $proc$libresoc.v:196621$13760
+ attribute \src "libresoc.v:193568.3-193583.6"
+ process $proc$libresoc.v:193568$13618
assign { } { }
assign { } { }
assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:196622.5-196622.29"
+ attribute \src "libresoc.v:193569.5-193569.29"
switch \initial
- attribute \src "libresoc.v:196622.9-196622.17"
+ attribute \src "libresoc.v:193569.9-193569.17"
case 1'1
case
end
sync always
update \core_msr__ren $0\core_msr__ren[2:0]
end
- attribute \src "libresoc.v:196637.3-196645.6"
- process $proc$libresoc.v:196637$13761
+ attribute \src "libresoc.v:193584.3-193592.6"
+ process $proc$libresoc.v:193584$13619
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__ack_o$next[0:0]$13762 $1\jtag_dmi0__ack_o$next[0:0]$13763
- attribute \src "libresoc.v:196638.5-196638.29"
+ assign $0\dbg_dmi_din$next[63:0]$13620 $1\dbg_dmi_din$next[63:0]$13621
+ attribute \src "libresoc.v:193585.5-193585.29"
switch \initial
- attribute \src "libresoc.v:196638.9-196638.17"
+ attribute \src "libresoc.v:193585.9-193585.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__ack_o$next[0:0]$13763 1'0
+ assign $1\dbg_dmi_din$next[63:0]$13621 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\jtag_dmi0__ack_o$next[0:0]$13763 \dbg_dmi_ack_o
+ assign $1\dbg_dmi_din$next[63:0]$13621 \jtag_dmi0__din
end
sync always
- update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13762
+ update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13620
end
- attribute \src "libresoc.v:196646.3-196656.6"
- process $proc$libresoc.v:196646$13764
+ attribute \src "libresoc.v:193593.3-193603.6"
+ process $proc$libresoc.v:193593$13622
assign { } { }
assign { } { }
assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:196647.5-196647.29"
+ attribute \src "libresoc.v:193594.5-193594.29"
switch \initial
- attribute \src "libresoc.v:196647.9-196647.17"
+ attribute \src "libresoc.v:193594.9-193594.17"
case 1'1
case
end
sync always
update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0]
end
- attribute \src "libresoc.v:196657.3-196692.6"
- process $proc$libresoc.v:196657$13765
+ attribute \src "libresoc.v:193604.3-193619.6"
+ process $proc$libresoc.v:193604$13623
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:196658.5-196658.29"
+ attribute \src "libresoc.v:193605.5-193605.29"
switch \initial
- attribute \src "libresoc.v:196658.9-196658.17"
+ attribute \src "libresoc.v:193605.9-193605.17"
case 1'1
case
end
case
assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
end
- attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign { } { }
- assign $1\imem_a_pc_i[47:0] $3\imem_a_pc_i[47:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
- switch \imem_f_busy_o
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign $3\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $3\imem_a_pc_i[47:0] $4\imem_a_pc_i[47:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- switch \$60
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign $4\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $4\imem_a_pc_i[47:0] \$62 [47:0]
- end
- end
case
assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
end
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:196693.3-196737.6"
- process $proc$libresoc.v:196693$13766
+ attribute \src "libresoc.v:193620.3-193628.6"
+ process $proc$libresoc.v:193620$13624
+ assign { } { }
+ assign { } { }
+ assign $0\jtag_dmi0__ack_o$next[0:0]$13625 $1\jtag_dmi0__ack_o$next[0:0]$13626
+ attribute \src "libresoc.v:193621.5-193621.29"
+ switch \initial
+ attribute \src "libresoc.v:193621.9-193621.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13626 1'0
+ case
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13626 \dbg_dmi_ack_o
+ end
+ sync always
+ update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13625
+ end
+ attribute \src "libresoc.v:193629.3-193662.6"
+ process $proc$libresoc.v:193629$13627
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:196694.5-196694.29"
+ attribute \src "libresoc.v:193630.5-193630.29"
switch \initial
- attribute \src "libresoc.v:196694.9-196694.17"
+ attribute \src "libresoc.v:193630.9-193630.17"
case 1'1
case
end
case 1'1
assign { } { }
assign $3\imem_a_valid_i[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
case
- assign { } { }
- assign $3\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- switch \$65
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign $4\imem_a_valid_i[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $4\imem_a_valid_i[0:0] 1'1
- end
+ assign $3\imem_a_valid_i[0:0] 1'0
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\imem_a_valid_i[0:0] $5\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
+ assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\imem_a_valid_i[0:0] 1'1
+ assign $4\imem_a_valid_i[0:0] 1'1
case
- assign $5\imem_a_valid_i[0:0] 1'0
+ assign $4\imem_a_valid_i[0:0] 1'0
end
case
assign $1\imem_a_valid_i[0:0] 1'0
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:196738.3-196782.6"
- process $proc$libresoc.v:196738$13767
+ attribute \src "libresoc.v:193663.3-193696.6"
+ process $proc$libresoc.v:193663$13628
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:196739.5-196739.29"
+ attribute \src "libresoc.v:193664.5-193664.29"
switch \initial
- attribute \src "libresoc.v:196739.9-196739.17"
+ attribute \src "libresoc.v:193664.9-193664.17"
case 1'1
case
end
case 1'1
assign { } { }
assign $3\imem_f_valid_i[0:0] 1'1
- attribute \src "libresoc.v:0.0-0.0"
case
- assign { } { }
- assign $3\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- switch \$67
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign $4\imem_f_valid_i[0:0] 1'0
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $4\imem_f_valid_i[0:0] 1'1
- end
+ assign $3\imem_f_valid_i[0:0] 1'0
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\imem_f_valid_i[0:0] $5\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
+ assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\imem_f_valid_i[0:0] 1'1
+ assign $4\imem_f_valid_i[0:0] 1'1
case
- assign $5\imem_f_valid_i[0:0] 1'0
+ assign $4\imem_f_valid_i[0:0] 1'0
end
case
assign $1\imem_f_valid_i[0:0] 1'0
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:196783.3-196803.6"
- process $proc$libresoc.v:196783$13768
+ attribute \src "libresoc.v:193697.3-193717.6"
+ process $proc$libresoc.v:193697$13629
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_pc$next[63:0]$13769 $3\dec2_cur_pc$next[63:0]$13772
- attribute \src "libresoc.v:196784.5-196784.29"
+ assign $0\dec2_cur_pc$next[63:0]$13630 $3\dec2_cur_pc$next[63:0]$13633
+ attribute \src "libresoc.v:193698.5-193698.29"
switch \initial
- attribute \src "libresoc.v:196784.9-196784.17"
+ attribute \src "libresoc.v:193698.9-193698.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\dec2_cur_pc$next[63:0]$13770 $2\dec2_cur_pc$next[63:0]$13771
+ assign $1\dec2_cur_pc$next[63:0]$13631 $2\dec2_cur_pc$next[63:0]$13632
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_pc$next[63:0]$13771 \pc
+ assign $2\dec2_cur_pc$next[63:0]$13632 \pc
case
- assign $2\dec2_cur_pc$next[63:0]$13771 \dec2_cur_pc
+ assign $2\dec2_cur_pc$next[63:0]$13632 \dec2_cur_pc
end
case
- assign $1\dec2_cur_pc$next[63:0]$13770 \dec2_cur_pc
+ assign $1\dec2_cur_pc$next[63:0]$13631 \dec2_cur_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_pc$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_pc$next[63:0]$13633 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_pc$next[63:0]$13772 $1\dec2_cur_pc$next[63:0]$13770
+ assign $3\dec2_cur_pc$next[63:0]$13633 $1\dec2_cur_pc$next[63:0]$13631
end
sync always
- update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13769
+ update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13630
end
- attribute \src "libresoc.v:196804.3-196842.6"
- process $proc$libresoc.v:196804$13773
+ attribute \src "libresoc.v:193718.3-193756.6"
+ process $proc$libresoc.v:193718$13634
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cur_cur_dststep$next[6:0]$13774 $4\cur_cur_dststep$next[6:0]$13798
- assign $0\cur_cur_maxvl$next[6:0]$13775 $4\cur_cur_maxvl$next[6:0]$13799
- assign $0\cur_cur_subvl$next[1:0]$13776 $4\cur_cur_subvl$next[1:0]$13800
- assign $0\cur_cur_svstep$next[1:0]$13777 $4\cur_cur_svstep$next[1:0]$13801
- assign $0\cur_cur_vl$next[6:0]$13778 $4\cur_cur_vl$next[6:0]$13802
- assign $0\dec2_cur_cur_srcstep$next[6:0]$13779 $4\dec2_cur_cur_srcstep$next[6:0]$13803
- attribute \src "libresoc.v:196805.5-196805.29"
+ assign $0\cur_cur_dststep$next[6:0]$13635 $4\cur_cur_dststep$next[6:0]$13659
+ assign $0\cur_cur_maxvl$next[6:0]$13636 $4\cur_cur_maxvl$next[6:0]$13660
+ assign $0\cur_cur_srcstep$next[6:0]$13637 $4\cur_cur_srcstep$next[6:0]$13661
+ assign $0\cur_cur_subvl$next[1:0]$13638 $4\cur_cur_subvl$next[1:0]$13662
+ assign $0\cur_cur_svstep$next[1:0]$13639 $4\cur_cur_svstep$next[1:0]$13663
+ assign $0\cur_cur_vl$next[6:0]$13640 $4\cur_cur_vl$next[6:0]$13664
+ attribute \src "libresoc.v:193719.5-193719.29"
switch \initial
- attribute \src "libresoc.v:196805.9-196805.17"
+ attribute \src "libresoc.v:193719.9-193719.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\cur_cur_dststep$next[6:0]$13780 $2\cur_cur_dststep$next[6:0]$13786
- assign $1\cur_cur_maxvl$next[6:0]$13781 $2\cur_cur_maxvl$next[6:0]$13787
- assign $1\cur_cur_subvl$next[1:0]$13782 $2\cur_cur_subvl$next[1:0]$13788
- assign $1\cur_cur_svstep$next[1:0]$13783 $2\cur_cur_svstep$next[1:0]$13789
- assign $1\cur_cur_vl$next[6:0]$13784 $2\cur_cur_vl$next[6:0]$13790
- assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 $2\dec2_cur_cur_srcstep$next[6:0]$13791
+ assign $1\cur_cur_dststep$next[6:0]$13641 $2\cur_cur_dststep$next[6:0]$13647
+ assign $1\cur_cur_maxvl$next[6:0]$13642 $2\cur_cur_maxvl$next[6:0]$13648
+ assign $1\cur_cur_srcstep$next[6:0]$13643 $2\cur_cur_srcstep$next[6:0]$13649
+ assign $1\cur_cur_subvl$next[1:0]$13644 $2\cur_cur_subvl$next[1:0]$13650
+ assign $1\cur_cur_svstep$next[1:0]$13645 $2\cur_cur_svstep$next[1:0]$13651
+ assign $1\cur_cur_vl$next[6:0]$13646 $2\cur_cur_vl$next[6:0]$13652
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $2\cur_cur_maxvl$next[6:0]$13787 $2\cur_cur_vl$next[6:0]$13790 $2\dec2_cur_cur_srcstep$next[6:0]$13791 $2\cur_cur_dststep$next[6:0]$13786 $2\cur_cur_subvl$next[1:0]$13788 $2\cur_cur_svstep$next[1:0]$13789 } \svstate [31:0]
+ assign { $2\cur_cur_maxvl$next[6:0]$13648 $2\cur_cur_vl$next[6:0]$13652 $2\cur_cur_srcstep$next[6:0]$13649 $2\cur_cur_dststep$next[6:0]$13647 $2\cur_cur_subvl$next[1:0]$13650 $2\cur_cur_svstep$next[1:0]$13651 } \svstate [31:0]
case
- assign $2\cur_cur_dststep$next[6:0]$13786 \cur_cur_dststep
- assign $2\cur_cur_maxvl$next[6:0]$13787 \cur_cur_maxvl
- assign $2\cur_cur_subvl$next[1:0]$13788 \cur_cur_subvl
- assign $2\cur_cur_svstep$next[1:0]$13789 \cur_cur_svstep
- assign $2\cur_cur_vl$next[6:0]$13790 \cur_cur_vl
- assign $2\dec2_cur_cur_srcstep$next[6:0]$13791 \dec2_cur_cur_srcstep
+ assign $2\cur_cur_dststep$next[6:0]$13647 \cur_cur_dststep
+ assign $2\cur_cur_maxvl$next[6:0]$13648 \cur_cur_maxvl
+ assign $2\cur_cur_srcstep$next[6:0]$13649 \cur_cur_srcstep
+ assign $2\cur_cur_subvl$next[1:0]$13650 \cur_cur_subvl
+ assign $2\cur_cur_svstep$next[1:0]$13651 \cur_cur_svstep
+ assign $2\cur_cur_vl$next[6:0]$13652 \cur_cur_vl
end
case
- assign $1\cur_cur_dststep$next[6:0]$13780 \cur_cur_dststep
- assign $1\cur_cur_maxvl$next[6:0]$13781 \cur_cur_maxvl
- assign $1\cur_cur_subvl$next[1:0]$13782 \cur_cur_subvl
- assign $1\cur_cur_svstep$next[1:0]$13783 \cur_cur_svstep
- assign $1\cur_cur_vl$next[6:0]$13784 \cur_cur_vl
- assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 \dec2_cur_cur_srcstep
+ assign $1\cur_cur_dststep$next[6:0]$13641 \cur_cur_dststep
+ assign $1\cur_cur_maxvl$next[6:0]$13642 \cur_cur_maxvl
+ assign $1\cur_cur_srcstep$next[6:0]$13643 \cur_cur_srcstep
+ assign $1\cur_cur_subvl$next[1:0]$13644 \cur_cur_subvl
+ assign $1\cur_cur_svstep$next[1:0]$13645 \cur_cur_svstep
+ assign $1\cur_cur_vl$next[6:0]$13646 \cur_cur_vl
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $3\cur_cur_maxvl$next[6:0]$13793 $3\cur_cur_vl$next[6:0]$13796 $3\dec2_cur_cur_srcstep$next[6:0]$13797 $3\cur_cur_dststep$next[6:0]$13792 $3\cur_cur_subvl$next[1:0]$13794 $3\cur_cur_svstep$next[1:0]$13795 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
+ assign { $3\cur_cur_maxvl$next[6:0]$13654 $3\cur_cur_vl$next[6:0]$13658 $3\cur_cur_srcstep$next[6:0]$13655 $3\cur_cur_dststep$next[6:0]$13653 $3\cur_cur_subvl$next[1:0]$13656 $3\cur_cur_svstep$next[1:0]$13657 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
case
- assign $3\cur_cur_dststep$next[6:0]$13792 $1\cur_cur_dststep$next[6:0]$13780
- assign $3\cur_cur_maxvl$next[6:0]$13793 $1\cur_cur_maxvl$next[6:0]$13781
- assign $3\cur_cur_subvl$next[1:0]$13794 $1\cur_cur_subvl$next[1:0]$13782
- assign $3\cur_cur_svstep$next[1:0]$13795 $1\cur_cur_svstep$next[1:0]$13783
- assign $3\cur_cur_vl$next[6:0]$13796 $1\cur_cur_vl$next[6:0]$13784
- assign $3\dec2_cur_cur_srcstep$next[6:0]$13797 $1\dec2_cur_cur_srcstep$next[6:0]$13785
+ assign $3\cur_cur_dststep$next[6:0]$13653 $1\cur_cur_dststep$next[6:0]$13641
+ assign $3\cur_cur_maxvl$next[6:0]$13654 $1\cur_cur_maxvl$next[6:0]$13642
+ assign $3\cur_cur_srcstep$next[6:0]$13655 $1\cur_cur_srcstep$next[6:0]$13643
+ assign $3\cur_cur_subvl$next[1:0]$13656 $1\cur_cur_subvl$next[1:0]$13644
+ assign $3\cur_cur_svstep$next[1:0]$13657 $1\cur_cur_svstep$next[1:0]$13645
+ assign $3\cur_cur_vl$next[6:0]$13658 $1\cur_cur_vl$next[6:0]$13646
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\cur_cur_svstep$next[1:0]$13801 2'00
- assign $4\cur_cur_subvl$next[1:0]$13800 2'00
- assign $4\cur_cur_dststep$next[6:0]$13798 7'0000000
- assign $4\dec2_cur_cur_srcstep$next[6:0]$13803 7'0000000
- assign $4\cur_cur_vl$next[6:0]$13802 7'0000000
- assign $4\cur_cur_maxvl$next[6:0]$13799 7'0000000
- case
- assign $4\cur_cur_dststep$next[6:0]$13798 $3\cur_cur_dststep$next[6:0]$13792
- assign $4\cur_cur_maxvl$next[6:0]$13799 $3\cur_cur_maxvl$next[6:0]$13793
- assign $4\cur_cur_subvl$next[1:0]$13800 $3\cur_cur_subvl$next[1:0]$13794
- assign $4\cur_cur_svstep$next[1:0]$13801 $3\cur_cur_svstep$next[1:0]$13795
- assign $4\cur_cur_vl$next[6:0]$13802 $3\cur_cur_vl$next[6:0]$13796
- assign $4\dec2_cur_cur_srcstep$next[6:0]$13803 $3\dec2_cur_cur_srcstep$next[6:0]$13797
- end
- sync always
- update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13774
- update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13775
- update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13776
- update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13777
- update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13778
- update \dec2_cur_cur_srcstep$next $0\dec2_cur_cur_srcstep$next[6:0]$13779
- end
- attribute \src "libresoc.v:196843.3-196851.6"
- process $proc$libresoc.v:196843$13804
- assign { } { }
- assign { } { }
- assign $0\jtag_dmi0__dout$next[63:0]$13805 $1\jtag_dmi0__dout$next[63:0]$13806
- attribute \src "libresoc.v:196844.5-196844.29"
- switch \initial
- attribute \src "libresoc.v:196844.9-196844.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\jtag_dmi0__dout$next[63:0]$13806 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $4\cur_cur_svstep$next[1:0]$13663 2'00
+ assign $4\cur_cur_subvl$next[1:0]$13662 2'00
+ assign $4\cur_cur_dststep$next[6:0]$13659 7'0000000
+ assign $4\cur_cur_srcstep$next[6:0]$13661 7'0000000
+ assign $4\cur_cur_vl$next[6:0]$13664 7'0000000
+ assign $4\cur_cur_maxvl$next[6:0]$13660 7'0000000
case
- assign $1\jtag_dmi0__dout$next[63:0]$13806 \dbg_dmi_dout
+ assign $4\cur_cur_dststep$next[6:0]$13659 $3\cur_cur_dststep$next[6:0]$13653
+ assign $4\cur_cur_maxvl$next[6:0]$13660 $3\cur_cur_maxvl$next[6:0]$13654
+ assign $4\cur_cur_srcstep$next[6:0]$13661 $3\cur_cur_srcstep$next[6:0]$13655
+ assign $4\cur_cur_subvl$next[1:0]$13662 $3\cur_cur_subvl$next[1:0]$13656
+ assign $4\cur_cur_svstep$next[1:0]$13663 $3\cur_cur_svstep$next[1:0]$13657
+ assign $4\cur_cur_vl$next[6:0]$13664 $3\cur_cur_vl$next[6:0]$13658
end
sync always
- update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13805
+ update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13635
+ update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13636
+ update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13637
+ update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13638
+ update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13639
+ update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13640
end
- attribute \src "libresoc.v:196852.3-196881.6"
- process $proc$libresoc.v:196852$13807
+ attribute \src "libresoc.v:193757.3-193786.6"
+ process $proc$libresoc.v:193757$13665
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr_read$next[0:0]$13808 $4\msr_read$next[0:0]$13812
- attribute \src "libresoc.v:196853.5-196853.29"
+ assign $0\msr_read$next[0:0]$13666 $4\msr_read$next[0:0]$13670
+ attribute \src "libresoc.v:193758.5-193758.29"
switch \initial
- attribute \src "libresoc.v:196853.9-196853.17"
+ attribute \src "libresoc.v:193758.9-193758.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\msr_read$next[0:0]$13809 $2\msr_read$next[0:0]$13810
+ assign $1\msr_read$next[0:0]$13667 $2\msr_read$next[0:0]$13668
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_read$next[0:0]$13810 1'0
+ assign $2\msr_read$next[0:0]$13668 1'0
case
- assign $2\msr_read$next[0:0]$13810 \msr_read
+ assign $2\msr_read$next[0:0]$13668 \msr_read
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\msr_read$next[0:0]$13809 $3\msr_read$next[0:0]$13811
+ assign $1\msr_read$next[0:0]$13667 $3\msr_read$next[0:0]$13669
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- switch \$69
+ switch \$88
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr_read$next[0:0]$13811 1'1
+ assign $3\msr_read$next[0:0]$13669 1'1
case
- assign $3\msr_read$next[0:0]$13811 \msr_read
+ assign $3\msr_read$next[0:0]$13669 \msr_read
end
case
- assign $1\msr_read$next[0:0]$13809 \msr_read
+ assign $1\msr_read$next[0:0]$13667 \msr_read
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\msr_read$next[0:0]$13670 1'1
+ case
+ assign $4\msr_read$next[0:0]$13670 $1\msr_read$next[0:0]$13667
+ end
+ sync always
+ update \msr_read$next $0\msr_read$next[0:0]$13666
+ end
+ attribute \src "libresoc.v:193787.3-193795.6"
+ process $proc$libresoc.v:193787$13671
+ assign { } { }
+ assign { } { }
+ assign $0\jtag_dmi0__dout$next[63:0]$13672 $1\jtag_dmi0__dout$next[63:0]$13673
+ attribute \src "libresoc.v:193788.5-193788.29"
+ switch \initial
+ attribute \src "libresoc.v:193788.9-193788.17"
+ case 1'1
+ case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr_read$next[0:0]$13812 1'1
+ assign $1\jtag_dmi0__dout$next[63:0]$13673 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $4\msr_read$next[0:0]$13812 $1\msr_read$next[0:0]$13809
+ assign $1\jtag_dmi0__dout$next[63:0]$13673 \dbg_dmi_dout
end
sync always
- update \msr_read$next $0\msr_read$next[0:0]$13808
+ update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13672
end
- attribute \src "libresoc.v:196882.3-196943.6"
- process $proc$libresoc.v:196882$13813
+ attribute \src "libresoc.v:193796.3-193849.6"
+ process $proc$libresoc.v:193796$13674
assign { } { }
assign { } { }
assign { } { }
- assign $0\fetch_fsm_state$next[1:0]$13814 $7\fetch_fsm_state$next[1:0]$13821
- attribute \src "libresoc.v:196883.5-196883.29"
+ assign $0\fetch_fsm_state$next[1:0]$13675 $6\fetch_fsm_state$next[1:0]$13681
+ attribute \src "libresoc.v:193797.5-193797.29"
switch \initial
- attribute \src "libresoc.v:196883.9-196883.17"
+ attribute \src "libresoc.v:193797.9-193797.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13815 $2\fetch_fsm_state$next[1:0]$13816
+ assign $1\fetch_fsm_state$next[1:0]$13676 $2\fetch_fsm_state$next[1:0]$13677
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fetch_fsm_state$next[1:0]$13816 2'01
+ assign $2\fetch_fsm_state$next[1:0]$13677 2'01
case
- assign $2\fetch_fsm_state$next[1:0]$13816 \fetch_fsm_state
+ assign $2\fetch_fsm_state$next[1:0]$13677 \fetch_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13815 $3\fetch_fsm_state$next[1:0]$13817
+ assign $1\fetch_fsm_state$next[1:0]$13676 $3\fetch_fsm_state$next[1:0]$13678
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\fetch_fsm_state$next[1:0]$13817 \fetch_fsm_state
+ assign $3\fetch_fsm_state$next[1:0]$13678 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\fetch_fsm_state$next[1:0]$13817 $4\fetch_fsm_state$next[1:0]$13818
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- switch \$71
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\fetch_fsm_state$next[1:0]$13818 2'10
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $4\fetch_fsm_state$next[1:0]$13818 2'11
- end
+ assign $3\fetch_fsm_state$next[1:0]$13678 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13815 $5\fetch_fsm_state$next[1:0]$13819
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
+ assign $1\fetch_fsm_state$next[1:0]$13676 $4\fetch_fsm_state$next[1:0]$13679
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $5\fetch_fsm_state$next[1:0]$13819 \fetch_fsm_state
+ assign $4\fetch_fsm_state$next[1:0]$13679 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $5\fetch_fsm_state$next[1:0]$13819 2'10
+ assign $4\fetch_fsm_state$next[1:0]$13679 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13815 $6\fetch_fsm_state$next[1:0]$13820
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241"
+ assign $1\fetch_fsm_state$next[1:0]$13676 $5\fetch_fsm_state$next[1:0]$13680
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:248"
switch \fetch_insn_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\fetch_fsm_state$next[1:0]$13820 2'00
+ assign $5\fetch_fsm_state$next[1:0]$13680 2'00
case
- assign $6\fetch_fsm_state$next[1:0]$13820 \fetch_fsm_state
+ assign $5\fetch_fsm_state$next[1:0]$13680 \fetch_fsm_state
end
case
- assign $1\fetch_fsm_state$next[1:0]$13815 \fetch_fsm_state
+ assign $1\fetch_fsm_state$next[1:0]$13676 \fetch_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\fetch_fsm_state$next[1:0]$13821 2'00
+ assign $6\fetch_fsm_state$next[1:0]$13681 2'00
case
- assign $7\fetch_fsm_state$next[1:0]$13821 $1\fetch_fsm_state$next[1:0]$13815
+ assign $6\fetch_fsm_state$next[1:0]$13681 $1\fetch_fsm_state$next[1:0]$13676
end
sync always
- update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13814
+ update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13675
end
- attribute \src "libresoc.v:196944.3-196964.6"
- process $proc$libresoc.v:196944$13822
+ attribute \src "libresoc.v:193850.3-193870.6"
+ process $proc$libresoc.v:193850$13682
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_msr$next[63:0]$13823 $3\dec2_cur_msr$next[63:0]$13826
- attribute \src "libresoc.v:196945.5-196945.29"
+ assign $0\dec2_cur_msr$next[63:0]$13683 $3\dec2_cur_msr$next[63:0]$13686
+ attribute \src "libresoc.v:193851.5-193851.29"
switch \initial
- attribute \src "libresoc.v:196945.9-196945.17"
+ attribute \src "libresoc.v:193851.9-193851.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_msr$next[63:0]$13824 $2\dec2_cur_msr$next[63:0]$13825
+ assign $1\dec2_cur_msr$next[63:0]$13684 $2\dec2_cur_msr$next[63:0]$13685
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
- switch \$73
+ switch \$90
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_msr$next[63:0]$13825 \core_msr__data_o
+ assign $2\dec2_cur_msr$next[63:0]$13685 \core_msr__data_o
case
- assign $2\dec2_cur_msr$next[63:0]$13825 \dec2_cur_msr
+ assign $2\dec2_cur_msr$next[63:0]$13685 \dec2_cur_msr
end
case
- assign $1\dec2_cur_msr$next[63:0]$13824 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$13684 \dec2_cur_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_msr$next[63:0]$13826 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_msr$next[63:0]$13686 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_msr$next[63:0]$13826 $1\dec2_cur_msr$next[63:0]$13824
+ assign $3\dec2_cur_msr$next[63:0]$13686 $1\dec2_cur_msr$next[63:0]$13684
end
sync always
- update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13823
+ update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13683
end
- attribute \src "libresoc.v:196965.3-196983.6"
- process $proc$libresoc.v:196965$13827
+ attribute \src "libresoc.v:193871.3-193889.6"
+ process $proc$libresoc.v:193871$13687
assign { } { }
assign { } { }
- assign $0\svp64_raw_opcode_in[31:0] $1\svp64_raw_opcode_in[31:0]
- attribute \src "libresoc.v:196966.5-196966.29"
+ assign $0\nia$next[63:0]$13688 $1\nia$next[63:0]$13689
+ attribute \src "libresoc.v:193872.5-193872.29"
switch \initial
- attribute \src "libresoc.v:196966.9-196966.17"
+ attribute \src "libresoc.v:193872.9-193872.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\svp64_raw_opcode_in[31:0] $2\svp64_raw_opcode_in[31:0]
+ assign $1\nia$next[63:0]$13689 $2\nia$next[63:0]$13690
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\svp64_raw_opcode_in[31:0] 0
+ assign $2\nia$next[63:0]$13690 \nia
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\svp64_raw_opcode_in[31:0] \$75
+ assign $2\nia$next[63:0]$13690 \$92 [63:0]
end
case
- assign $1\svp64_raw_opcode_in[31:0] 0
+ assign $1\nia$next[63:0]$13689 \nia
end
sync always
- update \svp64_raw_opcode_in $0\svp64_raw_opcode_in[31:0]
+ update \nia$next $0\nia$next[63:0]$13688
end
- attribute \src "libresoc.v:196984.3-197002.6"
- process $proc$libresoc.v:196984$13828
+ attribute \src "libresoc.v:193890.3-193920.6"
+ process $proc$libresoc.v:193890$13691
assign { } { }
assign { } { }
- assign $0\svp64_bigendian[0:0] $1\svp64_bigendian[0:0]
- attribute \src "libresoc.v:196985.5-196985.29"
+ assign $0\dec2_raw_opcode_in$next[31:0]$13692 $1\dec2_raw_opcode_in$next[31:0]$13693
+ attribute \src "libresoc.v:193891.5-193891.29"
switch \initial
- attribute \src "libresoc.v:196985.9-196985.17"
+ attribute \src "libresoc.v:193891.9-193891.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\svp64_bigendian[0:0] $2\svp64_bigendian[0:0]
+ assign $1\dec2_raw_opcode_in$next[31:0]$13693 $2\dec2_raw_opcode_in$next[31:0]$13694
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\svp64_bigendian[0:0] 1'0
+ assign $2\dec2_raw_opcode_in$next[31:0]$13694 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\svp64_bigendian[0:0] \core_bigendian_i
+ assign $2\dec2_raw_opcode_in$next[31:0]$13694 \$95
end
- case
- assign $1\svp64_bigendian[0:0] 1'0
- end
- sync always
- update \svp64_bigendian $0\svp64_bigendian[0:0]
- end
- attribute \src "libresoc.v:197003.3-197040.6"
- process $proc$libresoc.v:197003$13829
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0\dec2_dec_svp64__extra$next[8:0]$13830 $3\dec2_dec_svp64__extra$next[8:0]$13851
- assign $0\dec_svp64__elwidth$next[1:0]$13831 $3\dec_svp64__elwidth$next[1:0]$13852
- assign $0\dec_svp64__ewsrc$next[1:0]$13832 $3\dec_svp64__ewsrc$next[1:0]$13853
- assign $0\dec_svp64__mask$next[2:0]$13833 $3\dec_svp64__mask$next[2:0]$13854
- assign $0\dec_svp64__mmode$next[0:0]$13834 $3\dec_svp64__mmode$next[0:0]$13855
- assign $0\dec_svp64__mode$next[4:0]$13835 $3\dec_svp64__mode$next[4:0]$13856
- assign $0\dec_svp64__subvl$next[1:0]$13836 $3\dec_svp64__subvl$next[1:0]$13857
- attribute \src "libresoc.v:197004.5-197004.29"
- switch \initial
- attribute \src "libresoc.v:197004.9-197004.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
- switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 2'01
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
+ case 2'11
assign { } { }
- assign $1\dec2_dec_svp64__extra$next[8:0]$13837 $2\dec2_dec_svp64__extra$next[8:0]$13844
- assign $1\dec_svp64__elwidth$next[1:0]$13838 $2\dec_svp64__elwidth$next[1:0]$13845
- assign $1\dec_svp64__ewsrc$next[1:0]$13839 $2\dec_svp64__ewsrc$next[1:0]$13846
- assign $1\dec_svp64__mask$next[2:0]$13840 $2\dec_svp64__mask$next[2:0]$13847
- assign $1\dec_svp64__mmode$next[0:0]$13841 $2\dec_svp64__mmode$next[0:0]$13848
- assign $1\dec_svp64__mode$next[4:0]$13842 $2\dec_svp64__mode$next[4:0]$13849
- assign $1\dec_svp64__subvl$next[1:0]$13843 $2\dec_svp64__subvl$next[1:0]$13850
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
+ assign $1\dec2_raw_opcode_in$next[31:0]$13693 $3\dec2_raw_opcode_in$next[31:0]$13695
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\dec2_dec_svp64__extra$next[8:0]$13844 \dec2_dec_svp64__extra
- assign $2\dec_svp64__elwidth$next[1:0]$13845 \dec_svp64__elwidth
- assign $2\dec_svp64__ewsrc$next[1:0]$13846 \dec_svp64__ewsrc
- assign $2\dec_svp64__mask$next[2:0]$13847 \dec_svp64__mask
- assign $2\dec_svp64__mmode$next[0:0]$13848 \dec_svp64__mmode
- assign $2\dec_svp64__mode$next[4:0]$13849 \dec_svp64__mode
- assign $2\dec_svp64__subvl$next[1:0]$13850 \dec_svp64__subvl
+ assign $3\dec2_raw_opcode_in$next[31:0]$13695 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { $2\dec_svp64__mmode$next[0:0]$13848 $2\dec_svp64__mask$next[2:0]$13847 $2\dec_svp64__elwidth$next[1:0]$13845 $2\dec_svp64__ewsrc$next[1:0]$13846 $2\dec_svp64__subvl$next[1:0]$13850 $2\dec2_dec_svp64__extra$next[8:0]$13844 $2\dec_svp64__mode$next[4:0]$13849 } \svp64_svp64_rm
+ assign $3\dec2_raw_opcode_in$next[31:0]$13695 \$99
end
case
- assign $1\dec2_dec_svp64__extra$next[8:0]$13837 \dec2_dec_svp64__extra
- assign $1\dec_svp64__elwidth$next[1:0]$13838 \dec_svp64__elwidth
- assign $1\dec_svp64__ewsrc$next[1:0]$13839 \dec_svp64__ewsrc
- assign $1\dec_svp64__mask$next[2:0]$13840 \dec_svp64__mask
- assign $1\dec_svp64__mmode$next[0:0]$13841 \dec_svp64__mmode
- assign $1\dec_svp64__mode$next[4:0]$13842 \dec_svp64__mode
- assign $1\dec_svp64__subvl$next[1:0]$13843 \dec_svp64__subvl
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $3\dec_svp64__mode$next[4:0]$13856 5'00000
- assign $3\dec2_dec_svp64__extra$next[8:0]$13851 9'000000000
- assign $3\dec_svp64__subvl$next[1:0]$13857 2'00
- assign $3\dec_svp64__ewsrc$next[1:0]$13853 2'00
- assign $3\dec_svp64__elwidth$next[1:0]$13852 2'00
- assign $3\dec_svp64__mask$next[2:0]$13854 3'000
- assign $3\dec_svp64__mmode$next[0:0]$13855 1'0
- case
- assign $3\dec2_dec_svp64__extra$next[8:0]$13851 $1\dec2_dec_svp64__extra$next[8:0]$13837
- assign $3\dec_svp64__elwidth$next[1:0]$13852 $1\dec_svp64__elwidth$next[1:0]$13838
- assign $3\dec_svp64__ewsrc$next[1:0]$13853 $1\dec_svp64__ewsrc$next[1:0]$13839
- assign $3\dec_svp64__mask$next[2:0]$13854 $1\dec_svp64__mask$next[2:0]$13840
- assign $3\dec_svp64__mmode$next[0:0]$13855 $1\dec_svp64__mmode$next[0:0]$13841
- assign $3\dec_svp64__mode$next[4:0]$13856 $1\dec_svp64__mode$next[4:0]$13842
- assign $3\dec_svp64__subvl$next[1:0]$13857 $1\dec_svp64__subvl$next[1:0]$13843
+ assign $1\dec2_raw_opcode_in$next[31:0]$13693 \dec2_raw_opcode_in
end
sync always
- update \dec2_dec_svp64__extra$next $0\dec2_dec_svp64__extra$next[8:0]$13830
- update \dec_svp64__elwidth$next $0\dec_svp64__elwidth$next[1:0]$13831
- update \dec_svp64__ewsrc$next $0\dec_svp64__ewsrc$next[1:0]$13832
- update \dec_svp64__mask$next $0\dec_svp64__mask$next[2:0]$13833
- update \dec_svp64__mmode$next $0\dec_svp64__mmode$next[0:0]$13834
- update \dec_svp64__mode$next $0\dec_svp64__mode$next[4:0]$13835
- update \dec_svp64__subvl$next $0\dec_svp64__subvl$next[1:0]$13836
+ update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13692
end
- attribute \src "libresoc.v:197041.3-197059.6"
- process $proc$libresoc.v:197041$13858
+ attribute \src "libresoc.v:193921.3-193931.6"
+ process $proc$libresoc.v:193921$13696
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$13859 $1\nia$next[63:0]$13860
- attribute \src "libresoc.v:197042.5-197042.29"
+ assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0]
+ attribute \src "libresoc.v:193922.5-193922.29"
switch \initial
- attribute \src "libresoc.v:197042.9-197042.17"
+ attribute \src "libresoc.v:193922.9-193922.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 2'01
+ case 2'10
assign { } { }
- assign $1\nia$next[63:0]$13860 $2\nia$next[63:0]$13861
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
- switch \imem_f_busy_o
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign $2\nia$next[63:0]$13861 \nia
- attribute \src "libresoc.v:0.0-0.0"
- case
- assign { } { }
- assign $2\nia$next[63:0]$13861 \$79 [63:0]
- end
+ assign $1\fetch_insn_valid_o[0:0] 1'1
case
- assign $1\nia$next[63:0]$13860 \nia
+ assign $1\fetch_insn_valid_o[0:0] 1'0
end
sync always
- update \nia$next $0\nia$next[63:0]$13859
+ update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0]
end
- attribute \src "libresoc.v:197060.3-197095.6"
- process $proc$libresoc.v:197060$13862
+ attribute \src "libresoc.v:193932.3-193993.6"
+ process $proc$libresoc.v:193932$13697
assign { } { }
assign { } { }
- assign $0\fetch_insn_o[31:0] $1\fetch_insn_o[31:0]
- attribute \src "libresoc.v:197061.5-197061.29"
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\new_svstate_dststep[6:0] $1\new_svstate_dststep[6:0]
+ assign $0\new_svstate_maxvl[6:0] $1\new_svstate_maxvl[6:0]
+ assign $0\new_svstate_srcstep[6:0] $1\new_svstate_srcstep[6:0]
+ assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0]
+ assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0]
+ assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0]
+ attribute \src "libresoc.v:193933.5-193933.29"
switch \initial
- attribute \src "libresoc.v:197061.9-197061.17"
+ attribute \src "libresoc.v:193933.9-193933.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
- switch \fetch_fsm_state
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 2'01
+ case 3'000
assign { } { }
- assign $1\fetch_insn_o[31:0] $2\fetch_insn_o[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
- switch \imem_f_busy_o
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $1\new_svstate_dststep[6:0] $2\new_svstate_dststep[6:0]
+ assign $1\new_svstate_maxvl[6:0] $2\new_svstate_maxvl[6:0]
+ assign $1\new_svstate_srcstep[6:0] $2\new_svstate_srcstep[6:0]
+ assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0]
+ assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0]
+ assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$110
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\fetch_insn_o[31:0] 0
+ assign $2\new_svstate_dststep[6:0] \cur_cur_dststep
+ assign $2\new_svstate_maxvl[6:0] \cur_cur_maxvl
+ assign $2\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ assign $2\new_svstate_subvl[1:0] \cur_cur_subvl
+ assign $2\new_svstate_svstep[1:0] \cur_cur_svstep
+ assign $2\new_svstate_vl[6:0] \cur_cur_vl
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\fetch_insn_o[31:0] $3\fetch_insn_o[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
- switch \$84
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $2\new_svstate_dststep[6:0] $3\new_svstate_dststep[6:0]
+ assign $2\new_svstate_maxvl[6:0] $3\new_svstate_maxvl[6:0]
+ assign $2\new_svstate_srcstep[6:0] $3\new_svstate_srcstep[6:0]
+ assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0]
+ assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0]
+ assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301"
+ switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fetch_insn_o[31:0] \$86
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { $3\new_svstate_maxvl[6:0] $3\new_svstate_vl[6:0] $3\new_svstate_srcstep[6:0] $3\new_svstate_dststep[6:0] $3\new_svstate_subvl[1:0] $3\new_svstate_svstep[1:0] } \svstate_i
case
- assign $3\fetch_insn_o[31:0] 0
+ assign $3\new_svstate_dststep[6:0] \cur_cur_dststep
+ assign $3\new_svstate_maxvl[6:0] \cur_cur_maxvl
+ assign $3\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ assign $3\new_svstate_subvl[1:0] \cur_cur_subvl
+ assign $3\new_svstate_svstep[1:0] \cur_cur_svstep
+ assign $3\new_svstate_vl[6:0] \cur_cur_vl
end
end
attribute \src "libresoc.v:0.0-0.0"
- case 2'11
+ case 3'011
assign { } { }
- assign $1\fetch_insn_o[31:0] $4\fetch_insn_o[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
- switch \imem_f_busy_o
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $1\new_svstate_dststep[6:0] $4\new_svstate_dststep[6:0]
+ assign $1\new_svstate_maxvl[6:0] $4\new_svstate_maxvl[6:0]
+ assign $1\new_svstate_srcstep[6:0] $4\new_svstate_srcstep[6:0]
+ assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0]
+ assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0]
+ assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$116
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\fetch_insn_o[31:0] 0
+ assign $4\new_svstate_dststep[6:0] \cur_cur_dststep
+ assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl
+ assign { } { }
+ assign $4\new_svstate_subvl[1:0] \cur_cur_subvl
+ assign $4\new_svstate_svstep[1:0] \cur_cur_svstep
+ assign $4\new_svstate_vl[6:0] \cur_cur_vl
+ assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ switch { \$120 \$118 }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $6\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366"
+ switch \$122
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\new_svstate_srcstep[6:0] 7'0000000
+ case
+ assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $6\new_svstate_srcstep[6:0] \next_srcstep
+ end
+ case
+ assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ end
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\fetch_insn_o[31:0] \$90
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0]
+ assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0]
+ assign $4\new_svstate_srcstep[6:0] $8\new_svstate_srcstep[6:0]
+ assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0]
+ assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0]
+ assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
+ switch \svstate_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $8\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i
+ case
+ assign $5\new_svstate_dststep[6:0] \cur_cur_dststep
+ assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl
+ assign $8\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ assign $5\new_svstate_subvl[1:0] \cur_cur_subvl
+ assign $5\new_svstate_svstep[1:0] \cur_cur_svstep
+ assign $5\new_svstate_vl[6:0] \cur_cur_vl
+ end
end
case
- assign $1\fetch_insn_o[31:0] 0
+ assign $1\new_svstate_dststep[6:0] \cur_cur_dststep
+ assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl
+ assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep
+ assign $1\new_svstate_subvl[1:0] \cur_cur_subvl
+ assign $1\new_svstate_svstep[1:0] \cur_cur_svstep
+ assign $1\new_svstate_vl[6:0] \cur_cur_vl
end
sync always
- update \fetch_insn_o $0\fetch_insn_o[31:0]
+ update \new_svstate_dststep $0\new_svstate_dststep[6:0]
+ update \new_svstate_maxvl $0\new_svstate_maxvl[6:0]
+ update \new_svstate_srcstep $0\new_svstate_srcstep[6:0]
+ update \new_svstate_subvl $0\new_svstate_subvl[1:0]
+ update \new_svstate_svstep $0\new_svstate_svstep[1:0]
+ update \new_svstate_vl $0\new_svstate_vl[6:0]
end
- attribute \src "libresoc.v:197096.3-197106.6"
- process $proc$libresoc.v:197096$13863
+ attribute \src "libresoc.v:193994.3-194009.6"
+ process $proc$libresoc.v:193994$13698
assign { } { }
assign { } { }
- assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:197097.5-197097.29"
+ assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0]
+ attribute \src "libresoc.v:193995.5-193995.29"
switch \initial
- attribute \src "libresoc.v:197097.9-197097.17"
+ attribute \src "libresoc.v:193995.9-193995.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
- switch \fetch_fsm_state
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 2'10
+ case 3'000
assign { } { }
- assign $1\fetch_insn_valid_o[0:0] 1'1
+ assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$128
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\fetch_pc_valid_i[0:0] 1'1
+ case
+ assign $2\fetch_pc_valid_i[0:0] 1'0
+ end
case
- assign $1\fetch_insn_valid_o[0:0] 1'0
+ assign $1\fetch_pc_valid_i[0:0] 1'0
end
sync always
- update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0]
+ update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0]
end
- attribute \src "libresoc.v:197107.3-197168.6"
- process $proc$libresoc.v:197107$13864
+ attribute \src "libresoc.v:194010.3-194090.6"
+ process $proc$libresoc.v:194010$13699
assign { } { }
assign { } { }
assign { } { }
- assign $0\issue_fsm_state$next[2:0]$13865 $8\issue_fsm_state$next[2:0]$13873
- attribute \src "libresoc.v:197108.5-197108.29"
+ assign $0\issue_fsm_state$next[2:0]$13700 $10\issue_fsm_state$next[2:0]$13710
+ attribute \src "libresoc.v:194011.5-194011.29"
switch \initial
- attribute \src "libresoc.v:197108.9-197108.17"
+ attribute \src "libresoc.v:194011.9-194011.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13866 $2\issue_fsm_state$next[2:0]$13867
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- switch \$101
+ assign $1\issue_fsm_state$next[2:0]$13701 $2\issue_fsm_state$next[2:0]$13702
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$134
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\issue_fsm_state$next[2:0]$13867 3'001
+ assign $2\issue_fsm_state$next[2:0]$13702 $3\issue_fsm_state$next[2:0]$13703
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ switch \fetch_pc_ready_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\issue_fsm_state$next[2:0]$13703 3'001
+ case
+ assign $3\issue_fsm_state$next[2:0]$13703 \issue_fsm_state
+ end
case
- assign $2\issue_fsm_state$next[2:0]$13867 \issue_fsm_state
+ assign $2\issue_fsm_state$next[2:0]$13702 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13866 $3\issue_fsm_state$next[2:0]$13868
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290"
- switch \fetch_pc_ready_o
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $3\issue_fsm_state$next[2:0]$13868 3'010
- case
- assign $3\issue_fsm_state$next[2:0]$13868 \issue_fsm_state
- end
- attribute \src "libresoc.v:0.0-0.0"
- case 3'010
- assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13866 $4\issue_fsm_state$next[2:0]$13869
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
+ assign $1\issue_fsm_state$next[2:0]$13701 $4\issue_fsm_state$next[2:0]$13704
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\issue_fsm_state$next[2:0]$13869 3'011
+ assign $4\issue_fsm_state$next[2:0]$13704 $5\issue_fsm_state$next[2:0]$13705
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319"
+ switch \$140
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\issue_fsm_state$next[2:0]$13705 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $5\issue_fsm_state$next[2:0]$13705 3'010
+ end
case
- assign $4\issue_fsm_state$next[2:0]$13869 \issue_fsm_state
+ assign $4\issue_fsm_state$next[2:0]$13704 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
- case 3'011
+ case 3'010
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13866 $5\issue_fsm_state$next[2:0]$13870
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
+ assign $1\issue_fsm_state$next[2:0]$13701 $6\issue_fsm_state$next[2:0]$13706
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331"
switch \exec_insn_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\issue_fsm_state$next[2:0]$13870 3'100
+ assign $6\issue_fsm_state$next[2:0]$13706 3'011
case
- assign $5\issue_fsm_state$next[2:0]$13870 \issue_fsm_state
+ assign $6\issue_fsm_state$next[2:0]$13706 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'011
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13866 $6\issue_fsm_state$next[2:0]$13871
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- switch \$107
+ assign $1\issue_fsm_state$next[2:0]$13701 $7\issue_fsm_state$next[2:0]$13707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$146
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\issue_fsm_state$next[2:0]$13871 $7\issue_fsm_state$next[2:0]$13872
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
- switch \exec_pc_ready_i
+ assign $7\issue_fsm_state$next[2:0]$13707 $8\issue_fsm_state$next[2:0]$13708
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\issue_fsm_state$next[2:0]$13872 3'001
+ assign $8\issue_fsm_state$next[2:0]$13708 $9\issue_fsm_state$next[2:0]$13709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ switch { \$150 \$148 }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign { } { }
+ assign $9\issue_fsm_state$next[2:0]$13709 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $9\issue_fsm_state$next[2:0]$13709 3'000
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $9\issue_fsm_state$next[2:0]$13709 3'100
+ end
case
- assign $7\issue_fsm_state$next[2:0]$13872 \issue_fsm_state
+ assign $8\issue_fsm_state$next[2:0]$13708 \issue_fsm_state
end
case
- assign $6\issue_fsm_state$next[2:0]$13871 \issue_fsm_state
+ assign $7\issue_fsm_state$next[2:0]$13707 \issue_fsm_state
end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'100
+ assign { } { }
+ assign $1\issue_fsm_state$next[2:0]$13701 3'010
case
- assign $1\issue_fsm_state$next[2:0]$13866 \issue_fsm_state
+ assign $1\issue_fsm_state$next[2:0]$13701 \issue_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\issue_fsm_state$next[2:0]$13873 3'000
+ assign $10\issue_fsm_state$next[2:0]$13710 3'000
case
- assign $8\issue_fsm_state$next[2:0]$13873 $1\issue_fsm_state$next[2:0]$13866
+ assign $10\issue_fsm_state$next[2:0]$13710 $1\issue_fsm_state$next[2:0]$13701
end
sync always
- update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13865
+ update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13700
end
- attribute \src "libresoc.v:197169.3-197199.6"
- process $proc$libresoc.v:197169$13874
+ attribute \src "libresoc.v:194091.3-194121.6"
+ process $proc$libresoc.v:194091$13711
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:197170.5-197170.29"
+ attribute \src "libresoc.v:194092.5-194092.29"
switch \initial
- attribute \src "libresoc.v:197170.9-197170.17"
+ attribute \src "libresoc.v:194092.9-194092.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- switch \$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$156
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $2\core_stopped_i[0:0] 1'0
assign $2\core_stopped_i[0:0] 1'1
end
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'011
assign { } { }
assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- switch \$119
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$162
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $3\core_stopped_i[0:0] 1'0
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:197200.3-197230.6"
- process $proc$libresoc.v:197200$13875
+ attribute \src "libresoc.v:194122.3-194152.6"
+ process $proc$libresoc.v:194122$13712
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:197201.5-197201.29"
+ attribute \src "libresoc.v:194123.5-194123.29"
switch \initial
- attribute \src "libresoc.v:197201.9-197201.17"
+ attribute \src "libresoc.v:194123.9-194123.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
- switch \$125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$168
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $2\dbg_core_stopped_i[0:0] 1'0
assign $2\dbg_core_stopped_i[0:0] 1'1
end
attribute \src "libresoc.v:0.0-0.0"
- case 3'100
+ case 3'011
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
- switch \$131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$174
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $3\dbg_core_stopped_i[0:0] 1'0
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- attribute \src "libresoc.v:197231.3-197241.6"
- process $proc$libresoc.v:197231$13876
+ attribute \src "libresoc.v:194153.3-194219.6"
+ process $proc$libresoc.v:194153$13713
assign { } { }
assign { } { }
- assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:197232.5-197232.29"
+ assign { } { }
+ assign { } { }
+ assign $0\pc_changed$next[0:0]$13714 $9\pc_changed$next[0:0]$13723
+ attribute \src "libresoc.v:194154.5-194154.29"
switch \initial
- attribute \src "libresoc.v:197232.9-197232.17"
+ attribute \src "libresoc.v:194154.9-194154.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'001
+ case 3'000
assign { } { }
- assign $1\fetch_pc_valid_i[0:0] 1'1
+ assign $1\pc_changed$next[0:0]$13715 $2\pc_changed$next[0:0]$13716
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$180
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign $2\pc_changed$next[0:0]$13716 \pc_changed
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $2\pc_changed$next[0:0]$13716 $3\pc_changed$next[0:0]$13717
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
+ switch \pc_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\pc_changed$next[0:0]$13717 1'1
+ case
+ assign $3\pc_changed$next[0:0]$13717 \pc_changed
+ end
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\pc_changed$next[0:0]$13715 $4\pc_changed$next[0:0]$13718
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$186
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign $4\pc_changed$next[0:0]$13718 \pc_changed
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $4\pc_changed$next[0:0]$13718 $5\pc_changed$next[0:0]$13719
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
+ switch \pc_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\pc_changed$next[0:0]$13719 1'1
+ case
+ assign $5\pc_changed$next[0:0]$13719 \pc_changed
+ end
+ end
case
- assign $1\fetch_pc_valid_i[0:0] 1'0
+ assign $1\pc_changed$next[0:0]$13715 \pc_changed
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
+ switch \exec_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'0
+ assign { } { }
+ assign $6\pc_changed$next[0:0]$13720 $7\pc_changed$next[0:0]$13721
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432"
+ switch \exec_insn_valid_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\pc_changed$next[0:0]$13721 1'0
+ case
+ assign $7\pc_changed$next[0:0]$13721 $1\pc_changed$next[0:0]$13715
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\pc_changed$next[0:0]$13720 $8\pc_changed$next[0:0]$13722
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+ switch \$188
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $8\pc_changed$next[0:0]$13722 1'1
+ case
+ assign $8\pc_changed$next[0:0]$13722 $1\pc_changed$next[0:0]$13715
+ end
+ case
+ assign $6\pc_changed$next[0:0]$13720 $1\pc_changed$next[0:0]$13715
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $9\pc_changed$next[0:0]$13723 1'0
+ case
+ assign $9\pc_changed$next[0:0]$13723 $6\pc_changed$next[0:0]$13720
end
sync always
- update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0]
+ update \pc_changed$next $0\pc_changed$next[0:0]$13714
end
- attribute \src "libresoc.v:197242.3-197252.6"
- process $proc$libresoc.v:197242$13877
+ attribute \src "libresoc.v:194220.3-194281.6"
+ process $proc$libresoc.v:194220$13724
assign { } { }
assign { } { }
- assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:197243.5-197243.29"
+ assign $0\update_svstate[0:0] $1\update_svstate[0:0]
+ attribute \src "libresoc.v:194221.5-194221.29"
switch \initial
- attribute \src "libresoc.v:197243.9-197243.17"
+ attribute \src "libresoc.v:194221.9-194221.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'010
+ case 3'000
assign { } { }
- assign $1\fetch_insn_ready_i[0:0] 1'1
+ assign $1\update_svstate[0:0] $2\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$196
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign $2\update_svstate[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $2\update_svstate[0:0] $3\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301"
+ switch \svstate_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\update_svstate[0:0] 1'1
+ case
+ assign $3\update_svstate[0:0] 1'0
+ end
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\update_svstate[0:0] $4\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$202
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\update_svstate[0:0] $5\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ switch \exec_pc_valid_o
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\update_svstate[0:0] $6\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
+ switch { \$206 \$204 }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'-1
+ assign $6\update_svstate[0:0] 1'0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 2'1-
+ assign { } { }
+ assign $6\update_svstate[0:0] $7\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366"
+ switch \$208
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\update_svstate[0:0] 1'1
+ case
+ assign $7\update_svstate[0:0] 1'0
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $6\update_svstate[0:0] 1'1
+ end
+ case
+ assign $5\update_svstate[0:0] 1'0
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $4\update_svstate[0:0] $8\update_svstate[0:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
+ switch \svstate_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $8\update_svstate[0:0] 1'1
+ case
+ assign $8\update_svstate[0:0] 1'0
+ end
+ end
case
- assign $1\fetch_insn_ready_i[0:0] 1'0
+ assign $1\update_svstate[0:0] 1'0
end
sync always
- update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0]
+ update \update_svstate $0\update_svstate[0:0]
end
- attribute \src "libresoc.v:197253.3-197371.6"
- process $proc$libresoc.v:197253$13878
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
+ attribute \src "libresoc.v:194282.3-194348.6"
+ process $proc$libresoc.v:194282$13725
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sv_changed$next[0:0]$13726 $9\sv_changed$next[0:0]$13735
+ attribute \src "libresoc.v:194283.5-194283.29"
+ switch \initial
+ attribute \src "libresoc.v:194283.9-194283.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'000
+ assign { } { }
+ assign $1\sv_changed$next[0:0]$13727 $2\sv_changed$next[0:0]$13728
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ switch \$214
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign $2\sv_changed$next[0:0]$13728 \sv_changed
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $2\sv_changed$next[0:0]$13728 $3\sv_changed$next[0:0]$13729
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301"
+ switch \svstate_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\sv_changed$next[0:0]$13729 1'1
+ case
+ assign $3\sv_changed$next[0:0]$13729 \sv_changed
+ end
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\sv_changed$next[0:0]$13727 $4\sv_changed$next[0:0]$13730
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
+ switch \$220
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign $4\sv_changed$next[0:0]$13730 \sv_changed
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $4\sv_changed$next[0:0]$13730 $5\sv_changed$next[0:0]$13731
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
+ switch \svstate_i_ok
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $5\sv_changed$next[0:0]$13731 1'1
+ case
+ assign $5\sv_changed$next[0:0]$13731 \sv_changed
+ end
+ end
+ case
+ assign $1\sv_changed$next[0:0]$13727 \sv_changed
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427"
+ switch \exec_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'0
+ assign { } { }
+ assign $6\sv_changed$next[0:0]$13732 $7\sv_changed$next[0:0]$13733
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432"
+ switch \exec_insn_valid_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\sv_changed$next[0:0]$13733 1'0
+ case
+ assign $7\sv_changed$next[0:0]$13733 $1\sv_changed$next[0:0]$13727
+ end
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\sv_changed$next[0:0]$13732 $8\sv_changed$next[0:0]$13734
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444"
+ switch \$222
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $8\sv_changed$next[0:0]$13734 1'1
+ case
+ assign $8\sv_changed$next[0:0]$13734 $1\sv_changed$next[0:0]$13727
+ end
+ case
+ assign $6\sv_changed$next[0:0]$13732 $1\sv_changed$next[0:0]$13727
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $9\sv_changed$next[0:0]$13735 1'0
+ case
+ assign $9\sv_changed$next[0:0]$13735 $6\sv_changed$next[0:0]$13732
+ end
+ sync always
+ update \sv_changed$next $0\sv_changed$next[0:0]$13726
+ end
+ attribute \src "libresoc.v:194349.3-194359.6"
+ process $proc$libresoc.v:194349$13736
assign { } { }
assign { } { }
+ assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0]
+ attribute \src "libresoc.v:194350.5-194350.29"
+ switch \initial
+ attribute \src "libresoc.v:194350.9-194350.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
+ switch \issue_fsm_state
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'001
+ assign { } { }
+ assign $1\fetch_insn_ready_i[0:0] 1'1
+ case
+ assign $1\fetch_insn_ready_i[0:0] 1'0
+ end
+ sync always
+ update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0]
+ end
+ attribute \src "libresoc.v:194360.3-194470.6"
+ process $proc$libresoc.v:194360$13737
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_asmcode$next[7:0]$13879 $3\core_asmcode$next[7:0]$14056
- assign $0\core_core_core_cia$next[63:0]$13880 $3\core_core_core_cia$next[63:0]$14057
- assign $0\core_core_core_cr_rd$next[7:0]$13881 $3\core_core_core_cr_rd$next[7:0]$14058
+ assign $0\core_asmcode$next[7:0]$13738 $1\core_asmcode$next[7:0]$13797
+ assign $0\core_core_core_cia$next[63:0]$13739 $1\core_core_core_cia$next[63:0]$13798
+ assign $0\core_core_core_cr_rd$next[7:0]$13740 $1\core_core_core_cr_rd$next[7:0]$13799
assign { } { }
- assign $0\core_core_core_cr_wr$next[7:0]$13883 $3\core_core_core_cr_wr$next[7:0]$14060
+ assign $0\core_core_core_cr_wr$next[7:0]$13742 $1\core_core_core_cr_wr$next[7:0]$13801
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_core_fn_unit$next[12:0]$13892 $3\core_core_core_fn_unit$next[12:0]$14069
- assign $0\core_core_core_input_carry$next[1:0]$13893 $3\core_core_core_input_carry$next[1:0]$14070
- assign $0\core_core_core_insn$next[31:0]$13894 $3\core_core_core_insn$next[31:0]$14071
- assign $0\core_core_core_insn_type$next[6:0]$13895 $3\core_core_core_insn_type$next[6:0]$14072
- assign $0\core_core_core_is_32bit$next[0:0]$13896 $3\core_core_core_is_32bit$next[0:0]$14073
- assign $0\core_core_core_msr$next[63:0]$13897 $3\core_core_core_msr$next[63:0]$14074
- assign $0\core_core_core_oe$next[0:0]$13898 $3\core_core_core_oe$next[0:0]$14075
+ assign $0\core_core_core_fn_unit$next[12:0]$13751 $1\core_core_core_fn_unit$next[12:0]$13810
+ assign $0\core_core_core_input_carry$next[1:0]$13752 $1\core_core_core_input_carry$next[1:0]$13811
+ assign $0\core_core_core_insn$next[31:0]$13753 $1\core_core_core_insn$next[31:0]$13812
+ assign $0\core_core_core_insn_type$next[6:0]$13754 $1\core_core_core_insn_type$next[6:0]$13813
+ assign $0\core_core_core_is_32bit$next[0:0]$13755 $1\core_core_core_is_32bit$next[0:0]$13814
+ assign $0\core_core_core_msr$next[63:0]$13756 $1\core_core_core_msr$next[63:0]$13815
+ assign $0\core_core_core_oe$next[0:0]$13757 $1\core_core_core_oe$next[0:0]$13816
assign { } { }
- assign $0\core_core_core_rc$next[0:0]$13900 $3\core_core_core_rc$next[0:0]$14077
+ assign $0\core_core_core_rc$next[0:0]$13759 $1\core_core_core_rc$next[0:0]$13818
assign { } { }
- assign $0\core_core_core_trapaddr$next[12:0]$13902 $3\core_core_core_trapaddr$next[12:0]$14079
- assign $0\core_core_core_traptype$next[7:0]$13903 $3\core_core_core_traptype$next[7:0]$14080
- assign $0\core_core_cr_in1$next[6:0]$13904 $3\core_core_cr_in1$next[6:0]$14081
+ assign $0\core_core_core_trapaddr$next[12:0]$13761 $1\core_core_core_trapaddr$next[12:0]$13820
+ assign $0\core_core_core_traptype$next[7:0]$13762 $1\core_core_core_traptype$next[7:0]$13821
+ assign $0\core_core_cr_in1$next[6:0]$13763 $1\core_core_cr_in1$next[6:0]$13822
assign { } { }
- assign $0\core_core_cr_in2$1$next[6:0]$13906 $3\core_core_cr_in2$1$next[6:0]$14083
- assign $0\core_core_cr_in2$next[6:0]$13907 $3\core_core_cr_in2$next[6:0]$14084
+ assign $0\core_core_cr_in2$1$next[6:0]$13765 $1\core_core_cr_in2$1$next[6:0]$13824
+ assign $0\core_core_cr_in2$next[6:0]$13766 $1\core_core_cr_in2$next[6:0]$13825
assign { } { }
assign { } { }
- assign $0\core_core_cr_out$next[6:0]$13910 $3\core_core_cr_out$next[6:0]$14087
+ assign $0\core_core_cr_out$next[6:0]$13769 $1\core_core_cr_out$next[6:0]$13828
assign { } { }
- assign $0\core_core_ea$next[6:0]$13912 $3\core_core_ea$next[6:0]$14089
- assign $0\core_core_fast1$next[2:0]$13913 $3\core_core_fast1$next[2:0]$14090
+ assign $0\core_core_ea$next[6:0]$13771 $1\core_core_ea$next[6:0]$13830
+ assign $0\core_core_fast1$next[2:0]$13772 $1\core_core_fast1$next[2:0]$13831
assign { } { }
- assign $0\core_core_fast2$next[2:0]$13915 $3\core_core_fast2$next[2:0]$14092
+ assign $0\core_core_fast2$next[2:0]$13774 $1\core_core_fast2$next[2:0]$13833
assign { } { }
- assign $0\core_core_fasto1$next[2:0]$13917 $3\core_core_fasto1$next[2:0]$14094
- assign $0\core_core_fasto2$next[2:0]$13918 $3\core_core_fasto2$next[2:0]$14095
- assign $0\core_core_lk$next[0:0]$13919 $3\core_core_lk$next[0:0]$14096
- assign $0\core_core_reg1$next[6:0]$13920 $3\core_core_reg1$next[6:0]$14097
+ assign $0\core_core_fasto1$next[2:0]$13776 $1\core_core_fasto1$next[2:0]$13835
+ assign $0\core_core_fasto2$next[2:0]$13777 $1\core_core_fasto2$next[2:0]$13836
+ assign $0\core_core_lk$next[0:0]$13778 $1\core_core_lk$next[0:0]$13837
+ assign $0\core_core_reg1$next[6:0]$13779 $1\core_core_reg1$next[6:0]$13838
assign { } { }
- assign $0\core_core_reg2$next[6:0]$13922 $3\core_core_reg2$next[6:0]$14099
+ assign $0\core_core_reg2$next[6:0]$13781 $1\core_core_reg2$next[6:0]$13840
assign { } { }
- assign $0\core_core_reg3$next[6:0]$13924 $3\core_core_reg3$next[6:0]$14101
+ assign $0\core_core_reg3$next[6:0]$13783 $1\core_core_reg3$next[6:0]$13842
assign { } { }
- assign $0\core_core_rego$next[6:0]$13926 $3\core_core_rego$next[6:0]$14103
- assign $0\core_core_spr1$next[9:0]$13927 $3\core_core_spr1$next[9:0]$14104
+ assign $0\core_core_rego$next[6:0]$13785 $1\core_core_rego$next[6:0]$13844
+ assign $0\core_core_spr1$next[9:0]$13786 $1\core_core_spr1$next[9:0]$13845
assign { } { }
- assign $0\core_core_spro$next[9:0]$13929 $3\core_core_spro$next[9:0]$14106
- assign $0\core_core_xer_in$next[2:0]$13930 $3\core_core_xer_in$next[2:0]$14107
+ assign $0\core_core_spro$next[9:0]$13788 $1\core_core_spro$next[9:0]$13847
+ assign $0\core_core_xer_in$next[2:0]$13789 $1\core_core_xer_in$next[2:0]$13848
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_xer_out$next[0:0]$13937 $3\core_xer_out$next[0:0]$14114
- assign $0\core_core_core_cr_rd_ok$next[0:0]$13882 $5\core_core_core_cr_rd_ok$next[0:0]$14174
- assign $0\core_core_core_exc_$signal$3$next[0:0]$13884 $5\core_core_core_exc_$signal$3$next[0:0]$14175
- assign $0\core_core_core_exc_$signal$4$next[0:0]$13885 $5\core_core_core_exc_$signal$4$next[0:0]$14176
- assign $0\core_core_core_exc_$signal$5$next[0:0]$13886 $5\core_core_core_exc_$signal$5$next[0:0]$14177
- assign $0\core_core_core_exc_$signal$6$next[0:0]$13887 $5\core_core_core_exc_$signal$6$next[0:0]$14178
- assign $0\core_core_core_exc_$signal$7$next[0:0]$13888 $5\core_core_core_exc_$signal$7$next[0:0]$14179
- assign $0\core_core_core_exc_$signal$8$next[0:0]$13889 $5\core_core_core_exc_$signal$8$next[0:0]$14180
- assign $0\core_core_core_exc_$signal$9$next[0:0]$13890 $5\core_core_core_exc_$signal$9$next[0:0]$14181
- assign $0\core_core_core_exc_$signal$next[0:0]$13891 $5\core_core_core_exc_$signal$next[0:0]$14182
- assign $0\core_core_core_oe_ok$next[0:0]$13899 $5\core_core_core_oe_ok$next[0:0]$14183
- assign $0\core_core_core_rc_ok$next[0:0]$13901 $5\core_core_core_rc_ok$next[0:0]$14184
- assign $0\core_core_cr_in1_ok$next[0:0]$13905 $5\core_core_cr_in1_ok$next[0:0]$14185
- assign $0\core_core_cr_in2_ok$2$next[0:0]$13908 $5\core_core_cr_in2_ok$2$next[0:0]$14186
- assign $0\core_core_cr_in2_ok$next[0:0]$13909 $5\core_core_cr_in2_ok$next[0:0]$14187
- assign $0\core_core_cr_wr_ok$next[0:0]$13911 $5\core_core_cr_wr_ok$next[0:0]$14188
- assign $0\core_core_fast1_ok$next[0:0]$13914 $5\core_core_fast1_ok$next[0:0]$14189
- assign $0\core_core_fast2_ok$next[0:0]$13916 $5\core_core_fast2_ok$next[0:0]$14190
- assign $0\core_core_reg1_ok$next[0:0]$13921 $5\core_core_reg1_ok$next[0:0]$14191
- assign $0\core_core_reg2_ok$next[0:0]$13923 $5\core_core_reg2_ok$next[0:0]$14192
- assign $0\core_core_reg3_ok$next[0:0]$13925 $5\core_core_reg3_ok$next[0:0]$14193
- assign $0\core_core_spr1_ok$next[0:0]$13928 $5\core_core_spr1_ok$next[0:0]$14194
- assign $0\core_cr_out_ok$next[0:0]$13931 $5\core_cr_out_ok$next[0:0]$14195
- assign $0\core_ea_ok$next[0:0]$13932 $5\core_ea_ok$next[0:0]$14196
- assign $0\core_fasto1_ok$next[0:0]$13933 $5\core_fasto1_ok$next[0:0]$14197
- assign $0\core_fasto2_ok$next[0:0]$13934 $5\core_fasto2_ok$next[0:0]$14198
- assign $0\core_rego_ok$next[0:0]$13935 $5\core_rego_ok$next[0:0]$14199
- assign $0\core_spro_ok$next[0:0]$13936 $5\core_spro_ok$next[0:0]$14200
- attribute \src "libresoc.v:197254.5-197254.29"
+ assign $0\core_xer_out$next[0:0]$13796 $1\core_xer_out$next[0:0]$13855
+ assign $0\core_core_core_cr_rd_ok$next[0:0]$13741 $3\core_core_core_cr_rd_ok$next[0:0]$13915
+ assign $0\core_core_core_exc_$signal$3$next[0:0]$13743 $3\core_core_core_exc_$signal$3$next[0:0]$13916
+ assign $0\core_core_core_exc_$signal$4$next[0:0]$13744 $3\core_core_core_exc_$signal$4$next[0:0]$13917
+ assign $0\core_core_core_exc_$signal$5$next[0:0]$13745 $3\core_core_core_exc_$signal$5$next[0:0]$13918
+ assign $0\core_core_core_exc_$signal$6$next[0:0]$13746 $3\core_core_core_exc_$signal$6$next[0:0]$13919
+ assign $0\core_core_core_exc_$signal$7$next[0:0]$13747 $3\core_core_core_exc_$signal$7$next[0:0]$13920
+ assign $0\core_core_core_exc_$signal$8$next[0:0]$13748 $3\core_core_core_exc_$signal$8$next[0:0]$13921
+ assign $0\core_core_core_exc_$signal$9$next[0:0]$13749 $3\core_core_core_exc_$signal$9$next[0:0]$13922
+ assign $0\core_core_core_exc_$signal$next[0:0]$13750 $3\core_core_core_exc_$signal$next[0:0]$13923
+ assign $0\core_core_core_oe_ok$next[0:0]$13758 $3\core_core_core_oe_ok$next[0:0]$13924
+ assign $0\core_core_core_rc_ok$next[0:0]$13760 $3\core_core_core_rc_ok$next[0:0]$13925
+ assign $0\core_core_cr_in1_ok$next[0:0]$13764 $3\core_core_cr_in1_ok$next[0:0]$13926
+ assign $0\core_core_cr_in2_ok$2$next[0:0]$13767 $3\core_core_cr_in2_ok$2$next[0:0]$13927
+ assign $0\core_core_cr_in2_ok$next[0:0]$13768 $3\core_core_cr_in2_ok$next[0:0]$13928
+ assign $0\core_core_cr_wr_ok$next[0:0]$13770 $3\core_core_cr_wr_ok$next[0:0]$13929
+ assign $0\core_core_fast1_ok$next[0:0]$13773 $3\core_core_fast1_ok$next[0:0]$13930
+ assign $0\core_core_fast2_ok$next[0:0]$13775 $3\core_core_fast2_ok$next[0:0]$13931
+ assign $0\core_core_reg1_ok$next[0:0]$13780 $3\core_core_reg1_ok$next[0:0]$13932
+ assign $0\core_core_reg2_ok$next[0:0]$13782 $3\core_core_reg2_ok$next[0:0]$13933
+ assign $0\core_core_reg3_ok$next[0:0]$13784 $3\core_core_reg3_ok$next[0:0]$13934
+ assign $0\core_core_spr1_ok$next[0:0]$13787 $3\core_core_spr1_ok$next[0:0]$13935
+ assign $0\core_cr_out_ok$next[0:0]$13790 $3\core_cr_out_ok$next[0:0]$13936
+ assign $0\core_ea_ok$next[0:0]$13791 $3\core_ea_ok$next[0:0]$13937
+ assign $0\core_fasto1_ok$next[0:0]$13792 $3\core_fasto1_ok$next[0:0]$13938
+ assign $0\core_fasto2_ok$next[0:0]$13793 $3\core_fasto2_ok$next[0:0]$13939
+ assign $0\core_rego_ok$next[0:0]$13794 $3\core_rego_ok$next[0:0]$13940
+ assign $0\core_spro_ok$next[0:0]$13795 $3\core_spro_ok$next[0:0]$13941
+ attribute \src "libresoc.v:194361.5-194361.29"
switch \initial
- attribute \src "libresoc.v:197254.9-197254.17"
+ attribute \src "libresoc.v:194361.9-194361.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 3'010
+ case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$13938 $2\core_asmcode$next[7:0]$13997
- assign $1\core_core_core_cia$next[63:0]$13939 $2\core_core_core_cia$next[63:0]$13998
- assign $1\core_core_core_cr_rd$next[7:0]$13940 $2\core_core_core_cr_rd$next[7:0]$13999
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13941 $2\core_core_core_cr_rd_ok$next[0:0]$14000
- assign $1\core_core_core_cr_wr$next[7:0]$13942 $2\core_core_core_cr_wr$next[7:0]$14001
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13943 $2\core_core_core_exc_$signal$3$next[0:0]$14002
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13944 $2\core_core_core_exc_$signal$4$next[0:0]$14003
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13945 $2\core_core_core_exc_$signal$5$next[0:0]$14004
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13946 $2\core_core_core_exc_$signal$6$next[0:0]$14005
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13947 $2\core_core_core_exc_$signal$7$next[0:0]$14006
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13948 $2\core_core_core_exc_$signal$8$next[0:0]$14007
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13949 $2\core_core_core_exc_$signal$9$next[0:0]$14008
- assign $1\core_core_core_exc_$signal$next[0:0]$13950 $2\core_core_core_exc_$signal$next[0:0]$14009
- assign $1\core_core_core_fn_unit$next[12:0]$13951 $2\core_core_core_fn_unit$next[12:0]$14010
- assign $1\core_core_core_input_carry$next[1:0]$13952 $2\core_core_core_input_carry$next[1:0]$14011
- assign $1\core_core_core_insn$next[31:0]$13953 $2\core_core_core_insn$next[31:0]$14012
- assign $1\core_core_core_insn_type$next[6:0]$13954 $2\core_core_core_insn_type$next[6:0]$14013
- assign $1\core_core_core_is_32bit$next[0:0]$13955 $2\core_core_core_is_32bit$next[0:0]$14014
- assign $1\core_core_core_msr$next[63:0]$13956 $2\core_core_core_msr$next[63:0]$14015
- assign $1\core_core_core_oe$next[0:0]$13957 $2\core_core_core_oe$next[0:0]$14016
- assign $1\core_core_core_oe_ok$next[0:0]$13958 $2\core_core_core_oe_ok$next[0:0]$14017
- assign $1\core_core_core_rc$next[0:0]$13959 $2\core_core_core_rc$next[0:0]$14018
- assign $1\core_core_core_rc_ok$next[0:0]$13960 $2\core_core_core_rc_ok$next[0:0]$14019
- assign $1\core_core_core_trapaddr$next[12:0]$13961 $2\core_core_core_trapaddr$next[12:0]$14020
- assign $1\core_core_core_traptype$next[7:0]$13962 $2\core_core_core_traptype$next[7:0]$14021
- assign $1\core_core_cr_in1$next[6:0]$13963 $2\core_core_cr_in1$next[6:0]$14022
- assign $1\core_core_cr_in1_ok$next[0:0]$13964 $2\core_core_cr_in1_ok$next[0:0]$14023
- assign $1\core_core_cr_in2$1$next[6:0]$13965 $2\core_core_cr_in2$1$next[6:0]$14024
- assign $1\core_core_cr_in2$next[6:0]$13966 $2\core_core_cr_in2$next[6:0]$14025
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13967 $2\core_core_cr_in2_ok$2$next[0:0]$14026
- assign $1\core_core_cr_in2_ok$next[0:0]$13968 $2\core_core_cr_in2_ok$next[0:0]$14027
- assign $1\core_core_cr_out$next[6:0]$13969 $2\core_core_cr_out$next[6:0]$14028
- assign $1\core_core_cr_wr_ok$next[0:0]$13970 $2\core_core_cr_wr_ok$next[0:0]$14029
- assign $1\core_core_ea$next[6:0]$13971 $2\core_core_ea$next[6:0]$14030
- assign $1\core_core_fast1$next[2:0]$13972 $2\core_core_fast1$next[2:0]$14031
- assign $1\core_core_fast1_ok$next[0:0]$13973 $2\core_core_fast1_ok$next[0:0]$14032
- assign $1\core_core_fast2$next[2:0]$13974 $2\core_core_fast2$next[2:0]$14033
- assign $1\core_core_fast2_ok$next[0:0]$13975 $2\core_core_fast2_ok$next[0:0]$14034
- assign $1\core_core_fasto1$next[2:0]$13976 $2\core_core_fasto1$next[2:0]$14035
- assign $1\core_core_fasto2$next[2:0]$13977 $2\core_core_fasto2$next[2:0]$14036
- assign $1\core_core_lk$next[0:0]$13978 $2\core_core_lk$next[0:0]$14037
- assign $1\core_core_reg1$next[6:0]$13979 $2\core_core_reg1$next[6:0]$14038
- assign $1\core_core_reg1_ok$next[0:0]$13980 $2\core_core_reg1_ok$next[0:0]$14039
- assign $1\core_core_reg2$next[6:0]$13981 $2\core_core_reg2$next[6:0]$14040
- assign $1\core_core_reg2_ok$next[0:0]$13982 $2\core_core_reg2_ok$next[0:0]$14041
- assign $1\core_core_reg3$next[6:0]$13983 $2\core_core_reg3$next[6:0]$14042
- assign $1\core_core_reg3_ok$next[0:0]$13984 $2\core_core_reg3_ok$next[0:0]$14043
- assign $1\core_core_rego$next[6:0]$13985 $2\core_core_rego$next[6:0]$14044
- assign $1\core_core_spr1$next[9:0]$13986 $2\core_core_spr1$next[9:0]$14045
- assign $1\core_core_spr1_ok$next[0:0]$13987 $2\core_core_spr1_ok$next[0:0]$14046
- assign $1\core_core_spro$next[9:0]$13988 $2\core_core_spro$next[9:0]$14047
- assign $1\core_core_xer_in$next[2:0]$13989 $2\core_core_xer_in$next[2:0]$14048
- assign $1\core_cr_out_ok$next[0:0]$13990 $2\core_cr_out_ok$next[0:0]$14049
- assign $1\core_ea_ok$next[0:0]$13991 $2\core_ea_ok$next[0:0]$14050
- assign $1\core_fasto1_ok$next[0:0]$13992 $2\core_fasto1_ok$next[0:0]$14051
- assign $1\core_fasto2_ok$next[0:0]$13993 $2\core_fasto2_ok$next[0:0]$14052
- assign $1\core_rego_ok$next[0:0]$13994 $2\core_rego_ok$next[0:0]$14053
- assign $1\core_spro_ok$next[0:0]$13995 $2\core_spro_ok$next[0:0]$14054
- assign $1\core_xer_out$next[0:0]$13996 $2\core_xer_out$next[0:0]$14055
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
+ assign $1\core_asmcode$next[7:0]$13797 $2\core_asmcode$next[7:0]$13856
+ assign $1\core_core_core_cia$next[63:0]$13798 $2\core_core_core_cia$next[63:0]$13857
+ assign $1\core_core_core_cr_rd$next[7:0]$13799 $2\core_core_core_cr_rd$next[7:0]$13858
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13800 $2\core_core_core_cr_rd_ok$next[0:0]$13859
+ assign $1\core_core_core_cr_wr$next[7:0]$13801 $2\core_core_core_cr_wr$next[7:0]$13860
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13802 $2\core_core_core_exc_$signal$3$next[0:0]$13861
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13803 $2\core_core_core_exc_$signal$4$next[0:0]$13862
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13804 $2\core_core_core_exc_$signal$5$next[0:0]$13863
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13805 $2\core_core_core_exc_$signal$6$next[0:0]$13864
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13806 $2\core_core_core_exc_$signal$7$next[0:0]$13865
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13807 $2\core_core_core_exc_$signal$8$next[0:0]$13866
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13808 $2\core_core_core_exc_$signal$9$next[0:0]$13867
+ assign $1\core_core_core_exc_$signal$next[0:0]$13809 $2\core_core_core_exc_$signal$next[0:0]$13868
+ assign $1\core_core_core_fn_unit$next[12:0]$13810 $2\core_core_core_fn_unit$next[12:0]$13869
+ assign $1\core_core_core_input_carry$next[1:0]$13811 $2\core_core_core_input_carry$next[1:0]$13870
+ assign $1\core_core_core_insn$next[31:0]$13812 $2\core_core_core_insn$next[31:0]$13871
+ assign $1\core_core_core_insn_type$next[6:0]$13813 $2\core_core_core_insn_type$next[6:0]$13872
+ assign $1\core_core_core_is_32bit$next[0:0]$13814 $2\core_core_core_is_32bit$next[0:0]$13873
+ assign $1\core_core_core_msr$next[63:0]$13815 $2\core_core_core_msr$next[63:0]$13874
+ assign $1\core_core_core_oe$next[0:0]$13816 $2\core_core_core_oe$next[0:0]$13875
+ assign $1\core_core_core_oe_ok$next[0:0]$13817 $2\core_core_core_oe_ok$next[0:0]$13876
+ assign $1\core_core_core_rc$next[0:0]$13818 $2\core_core_core_rc$next[0:0]$13877
+ assign $1\core_core_core_rc_ok$next[0:0]$13819 $2\core_core_core_rc_ok$next[0:0]$13878
+ assign $1\core_core_core_trapaddr$next[12:0]$13820 $2\core_core_core_trapaddr$next[12:0]$13879
+ assign $1\core_core_core_traptype$next[7:0]$13821 $2\core_core_core_traptype$next[7:0]$13880
+ assign $1\core_core_cr_in1$next[6:0]$13822 $2\core_core_cr_in1$next[6:0]$13881
+ assign $1\core_core_cr_in1_ok$next[0:0]$13823 $2\core_core_cr_in1_ok$next[0:0]$13882
+ assign $1\core_core_cr_in2$1$next[6:0]$13824 $2\core_core_cr_in2$1$next[6:0]$13883
+ assign $1\core_core_cr_in2$next[6:0]$13825 $2\core_core_cr_in2$next[6:0]$13884
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13826 $2\core_core_cr_in2_ok$2$next[0:0]$13885
+ assign $1\core_core_cr_in2_ok$next[0:0]$13827 $2\core_core_cr_in2_ok$next[0:0]$13886
+ assign $1\core_core_cr_out$next[6:0]$13828 $2\core_core_cr_out$next[6:0]$13887
+ assign $1\core_core_cr_wr_ok$next[0:0]$13829 $2\core_core_cr_wr_ok$next[0:0]$13888
+ assign $1\core_core_ea$next[6:0]$13830 $2\core_core_ea$next[6:0]$13889
+ assign $1\core_core_fast1$next[2:0]$13831 $2\core_core_fast1$next[2:0]$13890
+ assign $1\core_core_fast1_ok$next[0:0]$13832 $2\core_core_fast1_ok$next[0:0]$13891
+ assign $1\core_core_fast2$next[2:0]$13833 $2\core_core_fast2$next[2:0]$13892
+ assign $1\core_core_fast2_ok$next[0:0]$13834 $2\core_core_fast2_ok$next[0:0]$13893
+ assign $1\core_core_fasto1$next[2:0]$13835 $2\core_core_fasto1$next[2:0]$13894
+ assign $1\core_core_fasto2$next[2:0]$13836 $2\core_core_fasto2$next[2:0]$13895
+ assign $1\core_core_lk$next[0:0]$13837 $2\core_core_lk$next[0:0]$13896
+ assign $1\core_core_reg1$next[6:0]$13838 $2\core_core_reg1$next[6:0]$13897
+ assign $1\core_core_reg1_ok$next[0:0]$13839 $2\core_core_reg1_ok$next[0:0]$13898
+ assign $1\core_core_reg2$next[6:0]$13840 $2\core_core_reg2$next[6:0]$13899
+ assign $1\core_core_reg2_ok$next[0:0]$13841 $2\core_core_reg2_ok$next[0:0]$13900
+ assign $1\core_core_reg3$next[6:0]$13842 $2\core_core_reg3$next[6:0]$13901
+ assign $1\core_core_reg3_ok$next[0:0]$13843 $2\core_core_reg3_ok$next[0:0]$13902
+ assign $1\core_core_rego$next[6:0]$13844 $2\core_core_rego$next[6:0]$13903
+ assign $1\core_core_spr1$next[9:0]$13845 $2\core_core_spr1$next[9:0]$13904
+ assign $1\core_core_spr1_ok$next[0:0]$13846 $2\core_core_spr1_ok$next[0:0]$13905
+ assign $1\core_core_spro$next[9:0]$13847 $2\core_core_spro$next[9:0]$13906
+ assign $1\core_core_xer_in$next[2:0]$13848 $2\core_core_xer_in$next[2:0]$13907
+ assign $1\core_cr_out_ok$next[0:0]$13849 $2\core_cr_out_ok$next[0:0]$13908
+ assign $1\core_ea_ok$next[0:0]$13850 $2\core_ea_ok$next[0:0]$13909
+ assign $1\core_fasto1_ok$next[0:0]$13851 $2\core_fasto1_ok$next[0:0]$13910
+ assign $1\core_fasto2_ok$next[0:0]$13852 $2\core_fasto2_ok$next[0:0]$13911
+ assign $1\core_rego_ok$next[0:0]$13853 $2\core_rego_ok$next[0:0]$13912
+ assign $1\core_spro_ok$next[0:0]$13854 $2\core_spro_ok$next[0:0]$13913
+ assign $1\core_xer_out$next[0:0]$13855 $2\core_xer_out$next[0:0]$13914
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_core_is_32bit$next[0:0]$14014 $2\core_core_cr_wr_ok$next[0:0]$14029 $2\core_core_core_cr_wr$next[7:0]$14001 $2\core_core_core_cr_rd_ok$next[0:0]$14000 $2\core_core_core_cr_rd$next[7:0]$13999 $2\core_core_core_trapaddr$next[12:0]$14020 $2\core_core_core_exc_$signal$9$next[0:0]$14008 $2\core_core_core_exc_$signal$8$next[0:0]$14007 $2\core_core_core_exc_$signal$7$next[0:0]$14006 $2\core_core_core_exc_$signal$6$next[0:0]$14005 $2\core_core_core_exc_$signal$5$next[0:0]$14004 $2\core_core_core_exc_$signal$4$next[0:0]$14003 $2\core_core_core_exc_$signal$3$next[0:0]$14002 $2\core_core_core_exc_$signal$next[0:0]$14009 $2\core_core_core_traptype$next[7:0]$14021 $2\core_core_core_input_carry$next[1:0]$14011 $2\core_core_core_oe_ok$next[0:0]$14017 $2\core_core_core_oe$next[0:0]$14016 $2\core_core_core_rc_ok$next[0:0]$14019 $2\core_core_core_rc$next[0:0]$14018 $2\core_core_lk$next[0:0]$14037 $2\core_core_core_fn_unit$next[12:0]$14010 $2\core_core_core_insn_type$next[6:0]$14013 $2\core_core_core_insn$next[31:0]$14012 $2\core_core_core_cia$next[63:0]$13998 $2\core_core_core_msr$next[63:0]$14015 $2\core_cr_out_ok$next[0:0]$14049 $2\core_core_cr_out$next[6:0]$14028 $2\core_core_cr_in2_ok$2$next[0:0]$14026 $2\core_core_cr_in2$1$next[6:0]$14024 $2\core_core_cr_in2_ok$next[0:0]$14027 $2\core_core_cr_in2$next[6:0]$14025 $2\core_core_cr_in1_ok$next[0:0]$14023 $2\core_core_cr_in1$next[6:0]$14022 $2\core_fasto2_ok$next[0:0]$14052 $2\core_core_fasto2$next[2:0]$14036 $2\core_fasto1_ok$next[0:0]$14051 $2\core_core_fasto1$next[2:0]$14035 $2\core_core_fast2_ok$next[0:0]$14034 $2\core_core_fast2$next[2:0]$14033 $2\core_core_fast1_ok$next[0:0]$14032 $2\core_core_fast1$next[2:0]$14031 $2\core_xer_out$next[0:0]$14055 $2\core_core_xer_in$next[2:0]$14048 $2\core_core_spr1_ok$next[0:0]$14046 $2\core_core_spr1$next[9:0]$14045 $2\core_spro_ok$next[0:0]$14054 $2\core_core_spro$next[9:0]$14047 $2\core_core_reg3_ok$next[0:0]$14043 $2\core_core_reg3$next[6:0]$14042 $2\core_core_reg2_ok$next[0:0]$14041 $2\core_core_reg2$next[6:0]$14040 $2\core_core_reg1_ok$next[0:0]$14039 $2\core_core_reg1$next[6:0]$14038 $2\core_ea_ok$next[0:0]$14050 $2\core_core_ea$next[6:0]$14030 $2\core_rego_ok$next[0:0]$14053 $2\core_core_rego$next[6:0]$14044 $2\core_asmcode$next[7:0]$13997 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $2\core_core_core_is_32bit$next[0:0]$13873 $2\core_core_cr_wr_ok$next[0:0]$13888 $2\core_core_core_cr_wr$next[7:0]$13860 $2\core_core_core_cr_rd_ok$next[0:0]$13859 $2\core_core_core_cr_rd$next[7:0]$13858 $2\core_core_core_trapaddr$next[12:0]$13879 $2\core_core_core_exc_$signal$9$next[0:0]$13867 $2\core_core_core_exc_$signal$8$next[0:0]$13866 $2\core_core_core_exc_$signal$7$next[0:0]$13865 $2\core_core_core_exc_$signal$6$next[0:0]$13864 $2\core_core_core_exc_$signal$5$next[0:0]$13863 $2\core_core_core_exc_$signal$4$next[0:0]$13862 $2\core_core_core_exc_$signal$3$next[0:0]$13861 $2\core_core_core_exc_$signal$next[0:0]$13868 $2\core_core_core_traptype$next[7:0]$13880 $2\core_core_core_input_carry$next[1:0]$13870 $2\core_core_core_oe_ok$next[0:0]$13876 $2\core_core_core_oe$next[0:0]$13875 $2\core_core_core_rc_ok$next[0:0]$13878 $2\core_core_core_rc$next[0:0]$13877 $2\core_core_lk$next[0:0]$13896 $2\core_core_core_fn_unit$next[12:0]$13869 $2\core_core_core_insn_type$next[6:0]$13872 $2\core_core_core_insn$next[31:0]$13871 $2\core_core_core_cia$next[63:0]$13857 $2\core_core_core_msr$next[63:0]$13874 $2\core_cr_out_ok$next[0:0]$13908 $2\core_core_cr_out$next[6:0]$13887 $2\core_core_cr_in2_ok$2$next[0:0]$13885 $2\core_core_cr_in2$1$next[6:0]$13883 $2\core_core_cr_in2_ok$next[0:0]$13886 $2\core_core_cr_in2$next[6:0]$13884 $2\core_core_cr_in1_ok$next[0:0]$13882 $2\core_core_cr_in1$next[6:0]$13881 $2\core_fasto2_ok$next[0:0]$13911 $2\core_core_fasto2$next[2:0]$13895 $2\core_fasto1_ok$next[0:0]$13910 $2\core_core_fasto1$next[2:0]$13894 $2\core_core_fast2_ok$next[0:0]$13893 $2\core_core_fast2$next[2:0]$13892 $2\core_core_fast1_ok$next[0:0]$13891 $2\core_core_fast1$next[2:0]$13890 $2\core_xer_out$next[0:0]$13914 $2\core_core_xer_in$next[2:0]$13907 $2\core_core_spr1_ok$next[0:0]$13905 $2\core_core_spr1$next[9:0]$13904 $2\core_spro_ok$next[0:0]$13913 $2\core_core_spro$next[9:0]$13906 $2\core_core_reg3_ok$next[0:0]$13902 $2\core_core_reg3$next[6:0]$13901 $2\core_core_reg2_ok$next[0:0]$13900 $2\core_core_reg2$next[6:0]$13899 $2\core_core_reg1_ok$next[0:0]$13898 $2\core_core_reg1$next[6:0]$13897 $2\core_ea_ok$next[0:0]$13909 $2\core_core_ea$next[6:0]$13889 $2\core_rego_ok$next[0:0]$13912 $2\core_core_rego$next[6:0]$13903 $2\core_asmcode$next[7:0]$13856 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $2\core_asmcode$next[7:0]$13997 \core_asmcode
- assign $2\core_core_core_cia$next[63:0]$13998 \core_core_core_cia
- assign $2\core_core_core_cr_rd$next[7:0]$13999 \core_core_core_cr_rd
- assign $2\core_core_core_cr_rd_ok$next[0:0]$14000 \core_core_core_cr_rd_ok
- assign $2\core_core_core_cr_wr$next[7:0]$14001 \core_core_core_cr_wr
- assign $2\core_core_core_exc_$signal$3$next[0:0]$14002 \core_core_core_exc_$signal$3
- assign $2\core_core_core_exc_$signal$4$next[0:0]$14003 \core_core_core_exc_$signal$4
- assign $2\core_core_core_exc_$signal$5$next[0:0]$14004 \core_core_core_exc_$signal$5
- assign $2\core_core_core_exc_$signal$6$next[0:0]$14005 \core_core_core_exc_$signal$6
- assign $2\core_core_core_exc_$signal$7$next[0:0]$14006 \core_core_core_exc_$signal$7
- assign $2\core_core_core_exc_$signal$8$next[0:0]$14007 \core_core_core_exc_$signal$8
- assign $2\core_core_core_exc_$signal$9$next[0:0]$14008 \core_core_core_exc_$signal$9
- assign $2\core_core_core_exc_$signal$next[0:0]$14009 \core_core_core_exc_$signal
- assign $2\core_core_core_fn_unit$next[12:0]$14010 \core_core_core_fn_unit
- assign $2\core_core_core_input_carry$next[1:0]$14011 \core_core_core_input_carry
- assign $2\core_core_core_insn$next[31:0]$14012 \core_core_core_insn
- assign $2\core_core_core_insn_type$next[6:0]$14013 \core_core_core_insn_type
- assign $2\core_core_core_is_32bit$next[0:0]$14014 \core_core_core_is_32bit
- assign $2\core_core_core_msr$next[63:0]$14015 \core_core_core_msr
- assign $2\core_core_core_oe$next[0:0]$14016 \core_core_core_oe
- assign $2\core_core_core_oe_ok$next[0:0]$14017 \core_core_core_oe_ok
- assign $2\core_core_core_rc$next[0:0]$14018 \core_core_core_rc
- assign $2\core_core_core_rc_ok$next[0:0]$14019 \core_core_core_rc_ok
- assign $2\core_core_core_trapaddr$next[12:0]$14020 \core_core_core_trapaddr
- assign $2\core_core_core_traptype$next[7:0]$14021 \core_core_core_traptype
- assign $2\core_core_cr_in1$next[6:0]$14022 \core_core_cr_in1
- assign $2\core_core_cr_in1_ok$next[0:0]$14023 \core_core_cr_in1_ok
- assign $2\core_core_cr_in2$1$next[6:0]$14024 \core_core_cr_in2$1
- assign $2\core_core_cr_in2$next[6:0]$14025 \core_core_cr_in2
- assign $2\core_core_cr_in2_ok$2$next[0:0]$14026 \core_core_cr_in2_ok$2
- assign $2\core_core_cr_in2_ok$next[0:0]$14027 \core_core_cr_in2_ok
- assign $2\core_core_cr_out$next[6:0]$14028 \core_core_cr_out
- assign $2\core_core_cr_wr_ok$next[0:0]$14029 \core_core_cr_wr_ok
- assign $2\core_core_ea$next[6:0]$14030 \core_core_ea
- assign $2\core_core_fast1$next[2:0]$14031 \core_core_fast1
- assign $2\core_core_fast1_ok$next[0:0]$14032 \core_core_fast1_ok
- assign $2\core_core_fast2$next[2:0]$14033 \core_core_fast2
- assign $2\core_core_fast2_ok$next[0:0]$14034 \core_core_fast2_ok
- assign $2\core_core_fasto1$next[2:0]$14035 \core_core_fasto1
- assign $2\core_core_fasto2$next[2:0]$14036 \core_core_fasto2
- assign $2\core_core_lk$next[0:0]$14037 \core_core_lk
- assign $2\core_core_reg1$next[6:0]$14038 \core_core_reg1
- assign $2\core_core_reg1_ok$next[0:0]$14039 \core_core_reg1_ok
- assign $2\core_core_reg2$next[6:0]$14040 \core_core_reg2
- assign $2\core_core_reg2_ok$next[0:0]$14041 \core_core_reg2_ok
- assign $2\core_core_reg3$next[6:0]$14042 \core_core_reg3
- assign $2\core_core_reg3_ok$next[0:0]$14043 \core_core_reg3_ok
- assign $2\core_core_rego$next[6:0]$14044 \core_core_rego
- assign $2\core_core_spr1$next[9:0]$14045 \core_core_spr1
- assign $2\core_core_spr1_ok$next[0:0]$14046 \core_core_spr1_ok
- assign $2\core_core_spro$next[9:0]$14047 \core_core_spro
- assign $2\core_core_xer_in$next[2:0]$14048 \core_core_xer_in
- assign $2\core_cr_out_ok$next[0:0]$14049 \core_cr_out_ok
- assign $2\core_ea_ok$next[0:0]$14050 \core_ea_ok
- assign $2\core_fasto1_ok$next[0:0]$14051 \core_fasto1_ok
- assign $2\core_fasto2_ok$next[0:0]$14052 \core_fasto2_ok
- assign $2\core_rego_ok$next[0:0]$14053 \core_rego_ok
- assign $2\core_spro_ok$next[0:0]$14054 \core_spro_ok
- assign $2\core_xer_out$next[0:0]$14055 \core_xer_out
+ assign $2\core_asmcode$next[7:0]$13856 \core_asmcode
+ assign $2\core_core_core_cia$next[63:0]$13857 \core_core_core_cia
+ assign $2\core_core_core_cr_rd$next[7:0]$13858 \core_core_core_cr_rd
+ assign $2\core_core_core_cr_rd_ok$next[0:0]$13859 \core_core_core_cr_rd_ok
+ assign $2\core_core_core_cr_wr$next[7:0]$13860 \core_core_core_cr_wr
+ assign $2\core_core_core_exc_$signal$3$next[0:0]$13861 \core_core_core_exc_$signal$3
+ assign $2\core_core_core_exc_$signal$4$next[0:0]$13862 \core_core_core_exc_$signal$4
+ assign $2\core_core_core_exc_$signal$5$next[0:0]$13863 \core_core_core_exc_$signal$5
+ assign $2\core_core_core_exc_$signal$6$next[0:0]$13864 \core_core_core_exc_$signal$6
+ assign $2\core_core_core_exc_$signal$7$next[0:0]$13865 \core_core_core_exc_$signal$7
+ assign $2\core_core_core_exc_$signal$8$next[0:0]$13866 \core_core_core_exc_$signal$8
+ assign $2\core_core_core_exc_$signal$9$next[0:0]$13867 \core_core_core_exc_$signal$9
+ assign $2\core_core_core_exc_$signal$next[0:0]$13868 \core_core_core_exc_$signal
+ assign $2\core_core_core_fn_unit$next[12:0]$13869 \core_core_core_fn_unit
+ assign $2\core_core_core_input_carry$next[1:0]$13870 \core_core_core_input_carry
+ assign $2\core_core_core_insn$next[31:0]$13871 \core_core_core_insn
+ assign $2\core_core_core_insn_type$next[6:0]$13872 \core_core_core_insn_type
+ assign $2\core_core_core_is_32bit$next[0:0]$13873 \core_core_core_is_32bit
+ assign $2\core_core_core_msr$next[63:0]$13874 \core_core_core_msr
+ assign $2\core_core_core_oe$next[0:0]$13875 \core_core_core_oe
+ assign $2\core_core_core_oe_ok$next[0:0]$13876 \core_core_core_oe_ok
+ assign $2\core_core_core_rc$next[0:0]$13877 \core_core_core_rc
+ assign $2\core_core_core_rc_ok$next[0:0]$13878 \core_core_core_rc_ok
+ assign $2\core_core_core_trapaddr$next[12:0]$13879 \core_core_core_trapaddr
+ assign $2\core_core_core_traptype$next[7:0]$13880 \core_core_core_traptype
+ assign $2\core_core_cr_in1$next[6:0]$13881 \core_core_cr_in1
+ assign $2\core_core_cr_in1_ok$next[0:0]$13882 \core_core_cr_in1_ok
+ assign $2\core_core_cr_in2$1$next[6:0]$13883 \core_core_cr_in2$1
+ assign $2\core_core_cr_in2$next[6:0]$13884 \core_core_cr_in2
+ assign $2\core_core_cr_in2_ok$2$next[0:0]$13885 \core_core_cr_in2_ok$2
+ assign $2\core_core_cr_in2_ok$next[0:0]$13886 \core_core_cr_in2_ok
+ assign $2\core_core_cr_out$next[6:0]$13887 \core_core_cr_out
+ assign $2\core_core_cr_wr_ok$next[0:0]$13888 \core_core_cr_wr_ok
+ assign $2\core_core_ea$next[6:0]$13889 \core_core_ea
+ assign $2\core_core_fast1$next[2:0]$13890 \core_core_fast1
+ assign $2\core_core_fast1_ok$next[0:0]$13891 \core_core_fast1_ok
+ assign $2\core_core_fast2$next[2:0]$13892 \core_core_fast2
+ assign $2\core_core_fast2_ok$next[0:0]$13893 \core_core_fast2_ok
+ assign $2\core_core_fasto1$next[2:0]$13894 \core_core_fasto1
+ assign $2\core_core_fasto2$next[2:0]$13895 \core_core_fasto2
+ assign $2\core_core_lk$next[0:0]$13896 \core_core_lk
+ assign $2\core_core_reg1$next[6:0]$13897 \core_core_reg1
+ assign $2\core_core_reg1_ok$next[0:0]$13898 \core_core_reg1_ok
+ assign $2\core_core_reg2$next[6:0]$13899 \core_core_reg2
+ assign $2\core_core_reg2_ok$next[0:0]$13900 \core_core_reg2_ok
+ assign $2\core_core_reg3$next[6:0]$13901 \core_core_reg3
+ assign $2\core_core_reg3_ok$next[0:0]$13902 \core_core_reg3_ok
+ assign $2\core_core_rego$next[6:0]$13903 \core_core_rego
+ assign $2\core_core_spr1$next[9:0]$13904 \core_core_spr1
+ assign $2\core_core_spr1_ok$next[0:0]$13905 \core_core_spr1_ok
+ assign $2\core_core_spro$next[9:0]$13906 \core_core_spro
+ assign $2\core_core_xer_in$next[2:0]$13907 \core_core_xer_in
+ assign $2\core_cr_out_ok$next[0:0]$13908 \core_cr_out_ok
+ assign $2\core_ea_ok$next[0:0]$13909 \core_ea_ok
+ assign $2\core_fasto1_ok$next[0:0]$13910 \core_fasto1_ok
+ assign $2\core_fasto2_ok$next[0:0]$13911 \core_fasto2_ok
+ assign $2\core_rego_ok$next[0:0]$13912 \core_rego_ok
+ assign $2\core_spro_ok$next[0:0]$13913 \core_spro_ok
+ assign $2\core_xer_out$next[0:0]$13914 \core_xer_out
end
- case
- assign $1\core_asmcode$next[7:0]$13938 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13939 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13940 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13941 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13942 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13943 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13944 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13945 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13946 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13947 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13948 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13949 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13950 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[12:0]$13951 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13952 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13953 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13954 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13955 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13956 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13957 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13958 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13959 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13960 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13961 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13962 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13963 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13964 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13965 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13966 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13967 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13968 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13969 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13970 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13971 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13972 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13973 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13974 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13975 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13976 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13977 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13978 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13979 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13980 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13981 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13982 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13983 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13984 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13985 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13986 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13987 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13988 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13989 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13990 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13991 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13992 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13993 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13994 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13995 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13996 \core_xer_out
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
- switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
- case 1'1
+ case 3'100
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_asmcode$next[7:0]$14056 $4\core_asmcode$next[7:0]$14115
- assign $3\core_core_core_cia$next[63:0]$14057 $4\core_core_core_cia$next[63:0]$14116
- assign $3\core_core_core_cr_rd$next[7:0]$14058 $4\core_core_core_cr_rd$next[7:0]$14117
- assign $3\core_core_core_cr_rd_ok$next[0:0]$14059 $4\core_core_core_cr_rd_ok$next[0:0]$14118
- assign $3\core_core_core_cr_wr$next[7:0]$14060 $4\core_core_core_cr_wr$next[7:0]$14119
- assign $3\core_core_core_exc_$signal$3$next[0:0]$14061 $4\core_core_core_exc_$signal$3$next[0:0]$14120
- assign $3\core_core_core_exc_$signal$4$next[0:0]$14062 $4\core_core_core_exc_$signal$4$next[0:0]$14121
- assign $3\core_core_core_exc_$signal$5$next[0:0]$14063 $4\core_core_core_exc_$signal$5$next[0:0]$14122
- assign $3\core_core_core_exc_$signal$6$next[0:0]$14064 $4\core_core_core_exc_$signal$6$next[0:0]$14123
- assign $3\core_core_core_exc_$signal$7$next[0:0]$14065 $4\core_core_core_exc_$signal$7$next[0:0]$14124
- assign $3\core_core_core_exc_$signal$8$next[0:0]$14066 $4\core_core_core_exc_$signal$8$next[0:0]$14125
- assign $3\core_core_core_exc_$signal$9$next[0:0]$14067 $4\core_core_core_exc_$signal$9$next[0:0]$14126
- assign $3\core_core_core_exc_$signal$next[0:0]$14068 $4\core_core_core_exc_$signal$next[0:0]$14127
- assign $3\core_core_core_fn_unit$next[12:0]$14069 $4\core_core_core_fn_unit$next[12:0]$14128
- assign $3\core_core_core_input_carry$next[1:0]$14070 $4\core_core_core_input_carry$next[1:0]$14129
- assign $3\core_core_core_insn$next[31:0]$14071 $4\core_core_core_insn$next[31:0]$14130
- assign $3\core_core_core_insn_type$next[6:0]$14072 $4\core_core_core_insn_type$next[6:0]$14131
- assign $3\core_core_core_is_32bit$next[0:0]$14073 $4\core_core_core_is_32bit$next[0:0]$14132
- assign $3\core_core_core_msr$next[63:0]$14074 $4\core_core_core_msr$next[63:0]$14133
- assign $3\core_core_core_oe$next[0:0]$14075 $4\core_core_core_oe$next[0:0]$14134
- assign $3\core_core_core_oe_ok$next[0:0]$14076 $4\core_core_core_oe_ok$next[0:0]$14135
- assign $3\core_core_core_rc$next[0:0]$14077 $4\core_core_core_rc$next[0:0]$14136
- assign $3\core_core_core_rc_ok$next[0:0]$14078 $4\core_core_core_rc_ok$next[0:0]$14137
- assign $3\core_core_core_trapaddr$next[12:0]$14079 $4\core_core_core_trapaddr$next[12:0]$14138
- assign $3\core_core_core_traptype$next[7:0]$14080 $4\core_core_core_traptype$next[7:0]$14139
- assign $3\core_core_cr_in1$next[6:0]$14081 $4\core_core_cr_in1$next[6:0]$14140
- assign $3\core_core_cr_in1_ok$next[0:0]$14082 $4\core_core_cr_in1_ok$next[0:0]$14141
- assign $3\core_core_cr_in2$1$next[6:0]$14083 $4\core_core_cr_in2$1$next[6:0]$14142
- assign $3\core_core_cr_in2$next[6:0]$14084 $4\core_core_cr_in2$next[6:0]$14143
- assign $3\core_core_cr_in2_ok$2$next[0:0]$14085 $4\core_core_cr_in2_ok$2$next[0:0]$14144
- assign $3\core_core_cr_in2_ok$next[0:0]$14086 $4\core_core_cr_in2_ok$next[0:0]$14145
- assign $3\core_core_cr_out$next[6:0]$14087 $4\core_core_cr_out$next[6:0]$14146
- assign $3\core_core_cr_wr_ok$next[0:0]$14088 $4\core_core_cr_wr_ok$next[0:0]$14147
- assign $3\core_core_ea$next[6:0]$14089 $4\core_core_ea$next[6:0]$14148
- assign $3\core_core_fast1$next[2:0]$14090 $4\core_core_fast1$next[2:0]$14149
- assign $3\core_core_fast1_ok$next[0:0]$14091 $4\core_core_fast1_ok$next[0:0]$14150
- assign $3\core_core_fast2$next[2:0]$14092 $4\core_core_fast2$next[2:0]$14151
- assign $3\core_core_fast2_ok$next[0:0]$14093 $4\core_core_fast2_ok$next[0:0]$14152
- assign $3\core_core_fasto1$next[2:0]$14094 $4\core_core_fasto1$next[2:0]$14153
- assign $3\core_core_fasto2$next[2:0]$14095 $4\core_core_fasto2$next[2:0]$14154
- assign $3\core_core_lk$next[0:0]$14096 $4\core_core_lk$next[0:0]$14155
- assign $3\core_core_reg1$next[6:0]$14097 $4\core_core_reg1$next[6:0]$14156
- assign $3\core_core_reg1_ok$next[0:0]$14098 $4\core_core_reg1_ok$next[0:0]$14157
- assign $3\core_core_reg2$next[6:0]$14099 $4\core_core_reg2$next[6:0]$14158
- assign $3\core_core_reg2_ok$next[0:0]$14100 $4\core_core_reg2_ok$next[0:0]$14159
- assign $3\core_core_reg3$next[6:0]$14101 $4\core_core_reg3$next[6:0]$14160
- assign $3\core_core_reg3_ok$next[0:0]$14102 $4\core_core_reg3_ok$next[0:0]$14161
- assign $3\core_core_rego$next[6:0]$14103 $4\core_core_rego$next[6:0]$14162
- assign $3\core_core_spr1$next[9:0]$14104 $4\core_core_spr1$next[9:0]$14163
- assign $3\core_core_spr1_ok$next[0:0]$14105 $4\core_core_spr1_ok$next[0:0]$14164
- assign $3\core_core_spro$next[9:0]$14106 $4\core_core_spro$next[9:0]$14165
- assign $3\core_core_xer_in$next[2:0]$14107 $4\core_core_xer_in$next[2:0]$14166
- assign $3\core_cr_out_ok$next[0:0]$14108 $4\core_cr_out_ok$next[0:0]$14167
- assign $3\core_ea_ok$next[0:0]$14109 $4\core_ea_ok$next[0:0]$14168
- assign $3\core_fasto1_ok$next[0:0]$14110 $4\core_fasto1_ok$next[0:0]$14169
- assign $3\core_fasto2_ok$next[0:0]$14111 $4\core_fasto2_ok$next[0:0]$14170
- assign $3\core_rego_ok$next[0:0]$14112 $4\core_rego_ok$next[0:0]$14171
- assign $3\core_spro_ok$next[0:0]$14113 $4\core_spro_ok$next[0:0]$14172
- assign $3\core_xer_out$next[0:0]$14114 $4\core_xer_out$next[0:0]$14173
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
- switch \$133
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { $4\core_core_core_is_32bit$next[0:0]$14132 $4\core_core_cr_wr_ok$next[0:0]$14147 $4\core_core_core_cr_wr$next[7:0]$14119 $4\core_core_core_cr_rd_ok$next[0:0]$14118 $4\core_core_core_cr_rd$next[7:0]$14117 $4\core_core_core_trapaddr$next[12:0]$14138 $4\core_core_core_exc_$signal$9$next[0:0]$14126 $4\core_core_core_exc_$signal$8$next[0:0]$14125 $4\core_core_core_exc_$signal$7$next[0:0]$14124 $4\core_core_core_exc_$signal$6$next[0:0]$14123 $4\core_core_core_exc_$signal$5$next[0:0]$14122 $4\core_core_core_exc_$signal$4$next[0:0]$14121 $4\core_core_core_exc_$signal$3$next[0:0]$14120 $4\core_core_core_exc_$signal$next[0:0]$14127 $4\core_core_core_traptype$next[7:0]$14139 $4\core_core_core_input_carry$next[1:0]$14129 $4\core_core_core_oe_ok$next[0:0]$14135 $4\core_core_core_oe$next[0:0]$14134 $4\core_core_core_rc_ok$next[0:0]$14137 $4\core_core_core_rc$next[0:0]$14136 $4\core_core_lk$next[0:0]$14155 $4\core_core_core_fn_unit$next[12:0]$14128 $4\core_core_core_insn_type$next[6:0]$14131 $4\core_core_core_insn$next[31:0]$14130 $4\core_core_core_cia$next[63:0]$14116 $4\core_core_core_msr$next[63:0]$14133 $4\core_cr_out_ok$next[0:0]$14167 $4\core_core_cr_out$next[6:0]$14146 $4\core_core_cr_in2_ok$2$next[0:0]$14144 $4\core_core_cr_in2$1$next[6:0]$14142 $4\core_core_cr_in2_ok$next[0:0]$14145 $4\core_core_cr_in2$next[6:0]$14143 $4\core_core_cr_in1_ok$next[0:0]$14141 $4\core_core_cr_in1$next[6:0]$14140 $4\core_fasto2_ok$next[0:0]$14170 $4\core_core_fasto2$next[2:0]$14154 $4\core_fasto1_ok$next[0:0]$14169 $4\core_core_fasto1$next[2:0]$14153 $4\core_core_fast2_ok$next[0:0]$14152 $4\core_core_fast2$next[2:0]$14151 $4\core_core_fast1_ok$next[0:0]$14150 $4\core_core_fast1$next[2:0]$14149 $4\core_xer_out$next[0:0]$14173 $4\core_core_xer_in$next[2:0]$14166 $4\core_core_spr1_ok$next[0:0]$14164 $4\core_core_spr1$next[9:0]$14163 $4\core_spro_ok$next[0:0]$14172 $4\core_core_spro$next[9:0]$14165 $4\core_core_reg3_ok$next[0:0]$14161 $4\core_core_reg3$next[6:0]$14160 $4\core_core_reg2_ok$next[0:0]$14159 $4\core_core_reg2$next[6:0]$14158 $4\core_core_reg1_ok$next[0:0]$14157 $4\core_core_reg1$next[6:0]$14156 $4\core_ea_ok$next[0:0]$14168 $4\core_core_ea$next[6:0]$14148 $4\core_rego_ok$next[0:0]$14171 $4\core_core_rego$next[6:0]$14162 $4\core_asmcode$next[7:0]$14115 } 357'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- case
- assign $4\core_asmcode$next[7:0]$14115 $1\core_asmcode$next[7:0]$13938
- assign $4\core_core_core_cia$next[63:0]$14116 $1\core_core_core_cia$next[63:0]$13939
- assign $4\core_core_core_cr_rd$next[7:0]$14117 $1\core_core_core_cr_rd$next[7:0]$13940
- assign $4\core_core_core_cr_rd_ok$next[0:0]$14118 $1\core_core_core_cr_rd_ok$next[0:0]$13941
- assign $4\core_core_core_cr_wr$next[7:0]$14119 $1\core_core_core_cr_wr$next[7:0]$13942
- assign $4\core_core_core_exc_$signal$3$next[0:0]$14120 $1\core_core_core_exc_$signal$3$next[0:0]$13943
- assign $4\core_core_core_exc_$signal$4$next[0:0]$14121 $1\core_core_core_exc_$signal$4$next[0:0]$13944
- assign $4\core_core_core_exc_$signal$5$next[0:0]$14122 $1\core_core_core_exc_$signal$5$next[0:0]$13945
- assign $4\core_core_core_exc_$signal$6$next[0:0]$14123 $1\core_core_core_exc_$signal$6$next[0:0]$13946
- assign $4\core_core_core_exc_$signal$7$next[0:0]$14124 $1\core_core_core_exc_$signal$7$next[0:0]$13947
- assign $4\core_core_core_exc_$signal$8$next[0:0]$14125 $1\core_core_core_exc_$signal$8$next[0:0]$13948
- assign $4\core_core_core_exc_$signal$9$next[0:0]$14126 $1\core_core_core_exc_$signal$9$next[0:0]$13949
- assign $4\core_core_core_exc_$signal$next[0:0]$14127 $1\core_core_core_exc_$signal$next[0:0]$13950
- assign $4\core_core_core_fn_unit$next[12:0]$14128 $1\core_core_core_fn_unit$next[12:0]$13951
- assign $4\core_core_core_input_carry$next[1:0]$14129 $1\core_core_core_input_carry$next[1:0]$13952
- assign $4\core_core_core_insn$next[31:0]$14130 $1\core_core_core_insn$next[31:0]$13953
- assign $4\core_core_core_insn_type$next[6:0]$14131 $1\core_core_core_insn_type$next[6:0]$13954
- assign $4\core_core_core_is_32bit$next[0:0]$14132 $1\core_core_core_is_32bit$next[0:0]$13955
- assign $4\core_core_core_msr$next[63:0]$14133 $1\core_core_core_msr$next[63:0]$13956
- assign $4\core_core_core_oe$next[0:0]$14134 $1\core_core_core_oe$next[0:0]$13957
- assign $4\core_core_core_oe_ok$next[0:0]$14135 $1\core_core_core_oe_ok$next[0:0]$13958
- assign $4\core_core_core_rc$next[0:0]$14136 $1\core_core_core_rc$next[0:0]$13959
- assign $4\core_core_core_rc_ok$next[0:0]$14137 $1\core_core_core_rc_ok$next[0:0]$13960
- assign $4\core_core_core_trapaddr$next[12:0]$14138 $1\core_core_core_trapaddr$next[12:0]$13961
- assign $4\core_core_core_traptype$next[7:0]$14139 $1\core_core_core_traptype$next[7:0]$13962
- assign $4\core_core_cr_in1$next[6:0]$14140 $1\core_core_cr_in1$next[6:0]$13963
- assign $4\core_core_cr_in1_ok$next[0:0]$14141 $1\core_core_cr_in1_ok$next[0:0]$13964
- assign $4\core_core_cr_in2$1$next[6:0]$14142 $1\core_core_cr_in2$1$next[6:0]$13965
- assign $4\core_core_cr_in2$next[6:0]$14143 $1\core_core_cr_in2$next[6:0]$13966
- assign $4\core_core_cr_in2_ok$2$next[0:0]$14144 $1\core_core_cr_in2_ok$2$next[0:0]$13967
- assign $4\core_core_cr_in2_ok$next[0:0]$14145 $1\core_core_cr_in2_ok$next[0:0]$13968
- assign $4\core_core_cr_out$next[6:0]$14146 $1\core_core_cr_out$next[6:0]$13969
- assign $4\core_core_cr_wr_ok$next[0:0]$14147 $1\core_core_cr_wr_ok$next[0:0]$13970
- assign $4\core_core_ea$next[6:0]$14148 $1\core_core_ea$next[6:0]$13971
- assign $4\core_core_fast1$next[2:0]$14149 $1\core_core_fast1$next[2:0]$13972
- assign $4\core_core_fast1_ok$next[0:0]$14150 $1\core_core_fast1_ok$next[0:0]$13973
- assign $4\core_core_fast2$next[2:0]$14151 $1\core_core_fast2$next[2:0]$13974
- assign $4\core_core_fast2_ok$next[0:0]$14152 $1\core_core_fast2_ok$next[0:0]$13975
- assign $4\core_core_fasto1$next[2:0]$14153 $1\core_core_fasto1$next[2:0]$13976
- assign $4\core_core_fasto2$next[2:0]$14154 $1\core_core_fasto2$next[2:0]$13977
- assign $4\core_core_lk$next[0:0]$14155 $1\core_core_lk$next[0:0]$13978
- assign $4\core_core_reg1$next[6:0]$14156 $1\core_core_reg1$next[6:0]$13979
- assign $4\core_core_reg1_ok$next[0:0]$14157 $1\core_core_reg1_ok$next[0:0]$13980
- assign $4\core_core_reg2$next[6:0]$14158 $1\core_core_reg2$next[6:0]$13981
- assign $4\core_core_reg2_ok$next[0:0]$14159 $1\core_core_reg2_ok$next[0:0]$13982
- assign $4\core_core_reg3$next[6:0]$14160 $1\core_core_reg3$next[6:0]$13983
- assign $4\core_core_reg3_ok$next[0:0]$14161 $1\core_core_reg3_ok$next[0:0]$13984
- assign $4\core_core_rego$next[6:0]$14162 $1\core_core_rego$next[6:0]$13985
- assign $4\core_core_spr1$next[9:0]$14163 $1\core_core_spr1$next[9:0]$13986
- assign $4\core_core_spr1_ok$next[0:0]$14164 $1\core_core_spr1_ok$next[0:0]$13987
- assign $4\core_core_spro$next[9:0]$14165 $1\core_core_spro$next[9:0]$13988
- assign $4\core_core_xer_in$next[2:0]$14166 $1\core_core_xer_in$next[2:0]$13989
- assign $4\core_cr_out_ok$next[0:0]$14167 $1\core_cr_out_ok$next[0:0]$13990
- assign $4\core_ea_ok$next[0:0]$14168 $1\core_ea_ok$next[0:0]$13991
- assign $4\core_fasto1_ok$next[0:0]$14169 $1\core_fasto1_ok$next[0:0]$13992
- assign $4\core_fasto2_ok$next[0:0]$14170 $1\core_fasto2_ok$next[0:0]$13993
- assign $4\core_rego_ok$next[0:0]$14171 $1\core_rego_ok$next[0:0]$13994
- assign $4\core_spro_ok$next[0:0]$14172 $1\core_spro_ok$next[0:0]$13995
- assign $4\core_xer_out$next[0:0]$14173 $1\core_xer_out$next[0:0]$13996
- end
+ assign { $1\core_core_core_is_32bit$next[0:0]$13814 $1\core_core_cr_wr_ok$next[0:0]$13829 $1\core_core_core_cr_wr$next[7:0]$13801 $1\core_core_core_cr_rd_ok$next[0:0]$13800 $1\core_core_core_cr_rd$next[7:0]$13799 $1\core_core_core_trapaddr$next[12:0]$13820 $1\core_core_core_exc_$signal$9$next[0:0]$13808 $1\core_core_core_exc_$signal$8$next[0:0]$13807 $1\core_core_core_exc_$signal$7$next[0:0]$13806 $1\core_core_core_exc_$signal$6$next[0:0]$13805 $1\core_core_core_exc_$signal$5$next[0:0]$13804 $1\core_core_core_exc_$signal$4$next[0:0]$13803 $1\core_core_core_exc_$signal$3$next[0:0]$13802 $1\core_core_core_exc_$signal$next[0:0]$13809 $1\core_core_core_traptype$next[7:0]$13821 $1\core_core_core_input_carry$next[1:0]$13811 $1\core_core_core_oe_ok$next[0:0]$13817 $1\core_core_core_oe$next[0:0]$13816 $1\core_core_core_rc_ok$next[0:0]$13819 $1\core_core_core_rc$next[0:0]$13818 $1\core_core_lk$next[0:0]$13837 $1\core_core_core_fn_unit$next[12:0]$13810 $1\core_core_core_insn_type$next[6:0]$13813 $1\core_core_core_insn$next[31:0]$13812 $1\core_core_core_cia$next[63:0]$13798 $1\core_core_core_msr$next[63:0]$13815 $1\core_cr_out_ok$next[0:0]$13849 $1\core_core_cr_out$next[6:0]$13828 $1\core_core_cr_in2_ok$2$next[0:0]$13826 $1\core_core_cr_in2$1$next[6:0]$13824 $1\core_core_cr_in2_ok$next[0:0]$13827 $1\core_core_cr_in2$next[6:0]$13825 $1\core_core_cr_in1_ok$next[0:0]$13823 $1\core_core_cr_in1$next[6:0]$13822 $1\core_fasto2_ok$next[0:0]$13852 $1\core_core_fasto2$next[2:0]$13836 $1\core_fasto1_ok$next[0:0]$13851 $1\core_core_fasto1$next[2:0]$13835 $1\core_core_fast2_ok$next[0:0]$13834 $1\core_core_fast2$next[2:0]$13833 $1\core_core_fast1_ok$next[0:0]$13832 $1\core_core_fast1$next[2:0]$13831 $1\core_xer_out$next[0:0]$13855 $1\core_core_xer_in$next[2:0]$13848 $1\core_core_spr1_ok$next[0:0]$13846 $1\core_core_spr1$next[9:0]$13845 $1\core_spro_ok$next[0:0]$13854 $1\core_core_spro$next[9:0]$13847 $1\core_core_reg3_ok$next[0:0]$13843 $1\core_core_reg3$next[6:0]$13842 $1\core_core_reg2_ok$next[0:0]$13841 $1\core_core_reg2$next[6:0]$13840 $1\core_core_reg1_ok$next[0:0]$13839 $1\core_core_reg1$next[6:0]$13838 $1\core_ea_ok$next[0:0]$13850 $1\core_core_ea$next[6:0]$13830 $1\core_rego_ok$next[0:0]$13853 $1\core_core_rego$next[6:0]$13844 $1\core_asmcode$next[7:0]$13797 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $3\core_asmcode$next[7:0]$14056 $1\core_asmcode$next[7:0]$13938
- assign $3\core_core_core_cia$next[63:0]$14057 $1\core_core_core_cia$next[63:0]$13939
- assign $3\core_core_core_cr_rd$next[7:0]$14058 $1\core_core_core_cr_rd$next[7:0]$13940
- assign $3\core_core_core_cr_rd_ok$next[0:0]$14059 $1\core_core_core_cr_rd_ok$next[0:0]$13941
- assign $3\core_core_core_cr_wr$next[7:0]$14060 $1\core_core_core_cr_wr$next[7:0]$13942
- assign $3\core_core_core_exc_$signal$3$next[0:0]$14061 $1\core_core_core_exc_$signal$3$next[0:0]$13943
- assign $3\core_core_core_exc_$signal$4$next[0:0]$14062 $1\core_core_core_exc_$signal$4$next[0:0]$13944
- assign $3\core_core_core_exc_$signal$5$next[0:0]$14063 $1\core_core_core_exc_$signal$5$next[0:0]$13945
- assign $3\core_core_core_exc_$signal$6$next[0:0]$14064 $1\core_core_core_exc_$signal$6$next[0:0]$13946
- assign $3\core_core_core_exc_$signal$7$next[0:0]$14065 $1\core_core_core_exc_$signal$7$next[0:0]$13947
- assign $3\core_core_core_exc_$signal$8$next[0:0]$14066 $1\core_core_core_exc_$signal$8$next[0:0]$13948
- assign $3\core_core_core_exc_$signal$9$next[0:0]$14067 $1\core_core_core_exc_$signal$9$next[0:0]$13949
- assign $3\core_core_core_exc_$signal$next[0:0]$14068 $1\core_core_core_exc_$signal$next[0:0]$13950
- assign $3\core_core_core_fn_unit$next[12:0]$14069 $1\core_core_core_fn_unit$next[12:0]$13951
- assign $3\core_core_core_input_carry$next[1:0]$14070 $1\core_core_core_input_carry$next[1:0]$13952
- assign $3\core_core_core_insn$next[31:0]$14071 $1\core_core_core_insn$next[31:0]$13953
- assign $3\core_core_core_insn_type$next[6:0]$14072 $1\core_core_core_insn_type$next[6:0]$13954
- assign $3\core_core_core_is_32bit$next[0:0]$14073 $1\core_core_core_is_32bit$next[0:0]$13955
- assign $3\core_core_core_msr$next[63:0]$14074 $1\core_core_core_msr$next[63:0]$13956
- assign $3\core_core_core_oe$next[0:0]$14075 $1\core_core_core_oe$next[0:0]$13957
- assign $3\core_core_core_oe_ok$next[0:0]$14076 $1\core_core_core_oe_ok$next[0:0]$13958
- assign $3\core_core_core_rc$next[0:0]$14077 $1\core_core_core_rc$next[0:0]$13959
- assign $3\core_core_core_rc_ok$next[0:0]$14078 $1\core_core_core_rc_ok$next[0:0]$13960
- assign $3\core_core_core_trapaddr$next[12:0]$14079 $1\core_core_core_trapaddr$next[12:0]$13961
- assign $3\core_core_core_traptype$next[7:0]$14080 $1\core_core_core_traptype$next[7:0]$13962
- assign $3\core_core_cr_in1$next[6:0]$14081 $1\core_core_cr_in1$next[6:0]$13963
- assign $3\core_core_cr_in1_ok$next[0:0]$14082 $1\core_core_cr_in1_ok$next[0:0]$13964
- assign $3\core_core_cr_in2$1$next[6:0]$14083 $1\core_core_cr_in2$1$next[6:0]$13965
- assign $3\core_core_cr_in2$next[6:0]$14084 $1\core_core_cr_in2$next[6:0]$13966
- assign $3\core_core_cr_in2_ok$2$next[0:0]$14085 $1\core_core_cr_in2_ok$2$next[0:0]$13967
- assign $3\core_core_cr_in2_ok$next[0:0]$14086 $1\core_core_cr_in2_ok$next[0:0]$13968
- assign $3\core_core_cr_out$next[6:0]$14087 $1\core_core_cr_out$next[6:0]$13969
- assign $3\core_core_cr_wr_ok$next[0:0]$14088 $1\core_core_cr_wr_ok$next[0:0]$13970
- assign $3\core_core_ea$next[6:0]$14089 $1\core_core_ea$next[6:0]$13971
- assign $3\core_core_fast1$next[2:0]$14090 $1\core_core_fast1$next[2:0]$13972
- assign $3\core_core_fast1_ok$next[0:0]$14091 $1\core_core_fast1_ok$next[0:0]$13973
- assign $3\core_core_fast2$next[2:0]$14092 $1\core_core_fast2$next[2:0]$13974
- assign $3\core_core_fast2_ok$next[0:0]$14093 $1\core_core_fast2_ok$next[0:0]$13975
- assign $3\core_core_fasto1$next[2:0]$14094 $1\core_core_fasto1$next[2:0]$13976
- assign $3\core_core_fasto2$next[2:0]$14095 $1\core_core_fasto2$next[2:0]$13977
- assign $3\core_core_lk$next[0:0]$14096 $1\core_core_lk$next[0:0]$13978
- assign $3\core_core_reg1$next[6:0]$14097 $1\core_core_reg1$next[6:0]$13979
- assign $3\core_core_reg1_ok$next[0:0]$14098 $1\core_core_reg1_ok$next[0:0]$13980
- assign $3\core_core_reg2$next[6:0]$14099 $1\core_core_reg2$next[6:0]$13981
- assign $3\core_core_reg2_ok$next[0:0]$14100 $1\core_core_reg2_ok$next[0:0]$13982
- assign $3\core_core_reg3$next[6:0]$14101 $1\core_core_reg3$next[6:0]$13983
- assign $3\core_core_reg3_ok$next[0:0]$14102 $1\core_core_reg3_ok$next[0:0]$13984
- assign $3\core_core_rego$next[6:0]$14103 $1\core_core_rego$next[6:0]$13985
- assign $3\core_core_spr1$next[9:0]$14104 $1\core_core_spr1$next[9:0]$13986
- assign $3\core_core_spr1_ok$next[0:0]$14105 $1\core_core_spr1_ok$next[0:0]$13987
- assign $3\core_core_spro$next[9:0]$14106 $1\core_core_spro$next[9:0]$13988
- assign $3\core_core_xer_in$next[2:0]$14107 $1\core_core_xer_in$next[2:0]$13989
- assign $3\core_cr_out_ok$next[0:0]$14108 $1\core_cr_out_ok$next[0:0]$13990
- assign $3\core_ea_ok$next[0:0]$14109 $1\core_ea_ok$next[0:0]$13991
- assign $3\core_fasto1_ok$next[0:0]$14110 $1\core_fasto1_ok$next[0:0]$13992
- assign $3\core_fasto2_ok$next[0:0]$14111 $1\core_fasto2_ok$next[0:0]$13993
- assign $3\core_rego_ok$next[0:0]$14112 $1\core_rego_ok$next[0:0]$13994
- assign $3\core_spro_ok$next[0:0]$14113 $1\core_spro_ok$next[0:0]$13995
- assign $3\core_xer_out$next[0:0]$14114 $1\core_xer_out$next[0:0]$13996
+ assign $1\core_asmcode$next[7:0]$13797 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13798 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13799 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13800 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13801 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13802 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13803 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13804 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13805 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13806 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13807 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13808 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13809 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[12:0]$13810 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13811 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13812 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13813 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13814 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13815 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13816 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13817 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13818 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13819 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13820 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13821 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13822 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13823 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13824 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13825 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13826 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13827 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13828 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13829 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13830 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13831 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13832 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13833 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13834 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13835 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13836 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13837 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13838 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13839 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13840 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13841 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13842 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13843 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13844 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13845 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13846 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13847 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13848 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13849 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13850 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13851 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13852 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13853 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13854 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13855 \core_xer_out
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $5\core_rego_ok$next[0:0]$14199 1'0
- assign $5\core_ea_ok$next[0:0]$14196 1'0
- assign $5\core_core_reg1_ok$next[0:0]$14191 1'0
- assign $5\core_core_reg2_ok$next[0:0]$14192 1'0
- assign $5\core_core_reg3_ok$next[0:0]$14193 1'0
- assign $5\core_spro_ok$next[0:0]$14200 1'0
- assign $5\core_core_spr1_ok$next[0:0]$14194 1'0
- assign $5\core_core_fast1_ok$next[0:0]$14189 1'0
- assign $5\core_core_fast2_ok$next[0:0]$14190 1'0
- assign $5\core_fasto1_ok$next[0:0]$14197 1'0
- assign $5\core_fasto2_ok$next[0:0]$14198 1'0
- assign $5\core_core_cr_in1_ok$next[0:0]$14185 1'0
- assign $5\core_core_cr_in2_ok$next[0:0]$14187 1'0
- assign $5\core_core_cr_in2_ok$2$next[0:0]$14186 1'0
- assign $5\core_cr_out_ok$next[0:0]$14195 1'0
- assign $5\core_core_core_rc_ok$next[0:0]$14184 1'0
- assign $5\core_core_core_oe_ok$next[0:0]$14183 1'0
- assign $5\core_core_core_exc_$signal$next[0:0]$14182 1'0
- assign $5\core_core_core_exc_$signal$3$next[0:0]$14175 1'0
- assign $5\core_core_core_exc_$signal$4$next[0:0]$14176 1'0
- assign $5\core_core_core_exc_$signal$5$next[0:0]$14177 1'0
- assign $5\core_core_core_exc_$signal$6$next[0:0]$14178 1'0
- assign $5\core_core_core_exc_$signal$7$next[0:0]$14179 1'0
- assign $5\core_core_core_exc_$signal$8$next[0:0]$14180 1'0
- assign $5\core_core_core_exc_$signal$9$next[0:0]$14181 1'0
- assign $5\core_core_core_cr_rd_ok$next[0:0]$14174 1'0
- assign $5\core_core_cr_wr_ok$next[0:0]$14188 1'0
- case
- assign $5\core_core_core_cr_rd_ok$next[0:0]$14174 $3\core_core_core_cr_rd_ok$next[0:0]$14059
- assign $5\core_core_core_exc_$signal$3$next[0:0]$14175 $3\core_core_core_exc_$signal$3$next[0:0]$14061
- assign $5\core_core_core_exc_$signal$4$next[0:0]$14176 $3\core_core_core_exc_$signal$4$next[0:0]$14062
- assign $5\core_core_core_exc_$signal$5$next[0:0]$14177 $3\core_core_core_exc_$signal$5$next[0:0]$14063
- assign $5\core_core_core_exc_$signal$6$next[0:0]$14178 $3\core_core_core_exc_$signal$6$next[0:0]$14064
- assign $5\core_core_core_exc_$signal$7$next[0:0]$14179 $3\core_core_core_exc_$signal$7$next[0:0]$14065
- assign $5\core_core_core_exc_$signal$8$next[0:0]$14180 $3\core_core_core_exc_$signal$8$next[0:0]$14066
- assign $5\core_core_core_exc_$signal$9$next[0:0]$14181 $3\core_core_core_exc_$signal$9$next[0:0]$14067
- assign $5\core_core_core_exc_$signal$next[0:0]$14182 $3\core_core_core_exc_$signal$next[0:0]$14068
- assign $5\core_core_core_oe_ok$next[0:0]$14183 $3\core_core_core_oe_ok$next[0:0]$14076
- assign $5\core_core_core_rc_ok$next[0:0]$14184 $3\core_core_core_rc_ok$next[0:0]$14078
- assign $5\core_core_cr_in1_ok$next[0:0]$14185 $3\core_core_cr_in1_ok$next[0:0]$14082
- assign $5\core_core_cr_in2_ok$2$next[0:0]$14186 $3\core_core_cr_in2_ok$2$next[0:0]$14085
- assign $5\core_core_cr_in2_ok$next[0:0]$14187 $3\core_core_cr_in2_ok$next[0:0]$14086
- assign $5\core_core_cr_wr_ok$next[0:0]$14188 $3\core_core_cr_wr_ok$next[0:0]$14088
- assign $5\core_core_fast1_ok$next[0:0]$14189 $3\core_core_fast1_ok$next[0:0]$14091
- assign $5\core_core_fast2_ok$next[0:0]$14190 $3\core_core_fast2_ok$next[0:0]$14093
- assign $5\core_core_reg1_ok$next[0:0]$14191 $3\core_core_reg1_ok$next[0:0]$14098
- assign $5\core_core_reg2_ok$next[0:0]$14192 $3\core_core_reg2_ok$next[0:0]$14100
- assign $5\core_core_reg3_ok$next[0:0]$14193 $3\core_core_reg3_ok$next[0:0]$14102
- assign $5\core_core_spr1_ok$next[0:0]$14194 $3\core_core_spr1_ok$next[0:0]$14105
- assign $5\core_cr_out_ok$next[0:0]$14195 $3\core_cr_out_ok$next[0:0]$14108
- assign $5\core_ea_ok$next[0:0]$14196 $3\core_ea_ok$next[0:0]$14109
- assign $5\core_fasto1_ok$next[0:0]$14197 $3\core_fasto1_ok$next[0:0]$14110
- assign $5\core_fasto2_ok$next[0:0]$14198 $3\core_fasto2_ok$next[0:0]$14111
- assign $5\core_rego_ok$next[0:0]$14199 $3\core_rego_ok$next[0:0]$14112
- assign $5\core_spro_ok$next[0:0]$14200 $3\core_spro_ok$next[0:0]$14113
- end
- sync always
- update \core_asmcode$next $0\core_asmcode$next[7:0]$13879
- update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13880
- update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13881
- update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13882
- update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13883
- update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13884
- update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13885
- update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13886
- update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13887
- update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13888
- update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13889
- update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13890
- update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13891
- update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$13892
- update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13893
- update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13894
- update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13895
- update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13896
- update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13897
- update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13898
- update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13899
- update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13900
- update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13901
- update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13902
- update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13903
- update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13904
- update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13905
- update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13906
- update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13907
- update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13908
- update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13909
- update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13910
- update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13911
- update \core_core_ea$next $0\core_core_ea$next[6:0]$13912
- update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13913
- update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13914
- update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13915
- update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13916
- update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13917
- update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13918
- update \core_core_lk$next $0\core_core_lk$next[0:0]$13919
- update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13920
- update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13921
- update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13922
- update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13923
- update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13924
- update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13925
- update \core_core_rego$next $0\core_core_rego$next[6:0]$13926
- update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13927
- update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13928
- update \core_core_spro$next $0\core_core_spro$next[9:0]$13929
- update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13930
- update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13931
- update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13932
- update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13933
- update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13934
- update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13935
- update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13936
- update \core_xer_out$next $0\core_xer_out$next[0:0]$13937
- end
- connect \$99 $not$libresoc.v:194915$13409_Y
- connect \$101 $and$libresoc.v:194916$13410_Y
- connect \$103 $not$libresoc.v:194917$13411_Y
- connect \$105 $not$libresoc.v:194918$13412_Y
- connect \$107 $and$libresoc.v:194919$13413_Y
- connect \$109 $not$libresoc.v:194920$13414_Y
- connect \$111 $not$libresoc.v:194921$13415_Y
- connect \$113 $and$libresoc.v:194922$13416_Y
- connect \$115 $not$libresoc.v:194923$13417_Y
- connect \$117 $not$libresoc.v:194924$13418_Y
- connect \$119 $and$libresoc.v:194925$13419_Y
- connect \$121 $not$libresoc.v:194926$13420_Y
- connect \$123 $not$libresoc.v:194927$13421_Y
- connect \$125 $and$libresoc.v:194928$13422_Y
- connect \$127 $not$libresoc.v:194929$13423_Y
- connect \$129 $not$libresoc.v:194930$13424_Y
- connect \$131 $and$libresoc.v:194931$13425_Y
- connect \$133 $not$libresoc.v:194932$13426_Y
- connect \$135 $not$libresoc.v:194933$13427_Y
- connect \$137 $not$libresoc.v:194934$13428_Y
- connect \$139 $not$libresoc.v:194935$13429_Y
- connect \$141 $not$libresoc.v:194936$13430_Y
- connect \$143 $and$libresoc.v:194937$13431_Y
- connect \$145 $pos$libresoc.v:194938$13432_Y
- connect \$147 $ne$libresoc.v:194939$13433_Y
- connect \$149 $not$libresoc.v:194940$13434_Y
- connect \$152 $and$libresoc.v:194941$13435_Y
- connect \$151 $reduce_or$libresoc.v:194942$13436_Y
- connect \$155 $not$libresoc.v:194943$13437_Y
- connect \$158 $and$libresoc.v:194944$13438_Y
- connect \$157 $reduce_or$libresoc.v:194945$13439_Y
- connect \$161 $not$libresoc.v:194946$13440_Y
- connect \$163 $not$libresoc.v:194947$13441_Y
- connect \$165 $not$libresoc.v:194948$13442_Y
- connect \$167 $pos$libresoc.v:194949$13444_Y
- connect \$169 $pos$libresoc.v:194950$13446_Y
- connect \$172 $sub$libresoc.v:194951$13447_Y
- connect \$175 $add$libresoc.v:194952$13448_Y
- connect \$23 $ne$libresoc.v:194953$13449_Y
- connect \$26 $sub$libresoc.v:194954$13450_Y
- connect \$28 $or$libresoc.v:194955$13451_Y
- connect \$30 $or$libresoc.v:194956$13452_Y
- connect \$32 $ne$libresoc.v:194957$13453_Y
- connect \$34 $not$libresoc.v:194958$13454_Y
- connect \$36 $and$libresoc.v:194959$13455_Y
- connect \$38 $not$libresoc.v:194960$13456_Y
- connect \$40 $not$libresoc.v:194961$13457_Y
- connect \$42 $pos$libresoc.v:194962$13459_Y
- connect \$44 $not$libresoc.v:194963$13460_Y
- connect \$46 $not$libresoc.v:194964$13461_Y
- connect \$48 $and$libresoc.v:194965$13462_Y
- connect \$50 $not$libresoc.v:194966$13463_Y
- connect \$52 $not$libresoc.v:194967$13464_Y
- connect \$54 $not$libresoc.v:194968$13465_Y
- connect \$56 $and$libresoc.v:194969$13466_Y
- connect \$58 $not$libresoc.v:194970$13467_Y
- connect \$60 $not$libresoc.v:194971$13468_Y
- connect \$63 $add$libresoc.v:194972$13469_Y
- connect \$65 $not$libresoc.v:194973$13470_Y
- connect \$67 $not$libresoc.v:194974$13471_Y
- connect \$69 $not$libresoc.v:194975$13472_Y
- connect \$71 $not$libresoc.v:194976$13473_Y
- connect \$73 $not$libresoc.v:194977$13474_Y
- connect \$76 $mul$libresoc.v:194978$13475_Y
- connect \$75 $shr$libresoc.v:194979$13476_Y [31:0]
- connect \$80 $ternary$libresoc.v:194980$13477_Y
- connect \$82 $add$libresoc.v:194981$13478_Y
- connect \$84 $not$libresoc.v:194982$13479_Y
- connect \$87 $mul$libresoc.v:194983$13480_Y
- connect \$86 $shr$libresoc.v:194984$13481_Y [31:0]
- connect \$92 $add$libresoc.v:194985$13482_Y
- connect \$94 $mul$libresoc.v:194986$13483_Y
- connect \$90 $shr$libresoc.v:194987$13484_Y [31:0]
- connect \$97 $not$libresoc.v:194988$13485_Y
+ assign $3\core_rego_ok$next[0:0]$13940 1'0
+ assign $3\core_ea_ok$next[0:0]$13937 1'0
+ assign $3\core_core_reg1_ok$next[0:0]$13932 1'0
+ assign $3\core_core_reg2_ok$next[0:0]$13933 1'0
+ assign $3\core_core_reg3_ok$next[0:0]$13934 1'0
+ assign $3\core_spro_ok$next[0:0]$13941 1'0
+ assign $3\core_core_spr1_ok$next[0:0]$13935 1'0
+ assign $3\core_core_fast1_ok$next[0:0]$13930 1'0
+ assign $3\core_core_fast2_ok$next[0:0]$13931 1'0
+ assign $3\core_fasto1_ok$next[0:0]$13938 1'0
+ assign $3\core_fasto2_ok$next[0:0]$13939 1'0
+ assign $3\core_core_cr_in1_ok$next[0:0]$13926 1'0
+ assign $3\core_core_cr_in2_ok$next[0:0]$13928 1'0
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13927 1'0
+ assign $3\core_cr_out_ok$next[0:0]$13936 1'0
+ assign $3\core_core_core_rc_ok$next[0:0]$13925 1'0
+ assign $3\core_core_core_oe_ok$next[0:0]$13924 1'0
+ assign $3\core_core_core_exc_$signal$next[0:0]$13923 1'0
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13916 1'0
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13917 1'0
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13918 1'0
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13919 1'0
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13920 1'0
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13921 1'0
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13922 1'0
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13915 1'0
+ assign $3\core_core_cr_wr_ok$next[0:0]$13929 1'0
+ case
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13915 $1\core_core_core_cr_rd_ok$next[0:0]$13800
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13916 $1\core_core_core_exc_$signal$3$next[0:0]$13802
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13917 $1\core_core_core_exc_$signal$4$next[0:0]$13803
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13918 $1\core_core_core_exc_$signal$5$next[0:0]$13804
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13919 $1\core_core_core_exc_$signal$6$next[0:0]$13805
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13920 $1\core_core_core_exc_$signal$7$next[0:0]$13806
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13921 $1\core_core_core_exc_$signal$8$next[0:0]$13807
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13922 $1\core_core_core_exc_$signal$9$next[0:0]$13808
+ assign $3\core_core_core_exc_$signal$next[0:0]$13923 $1\core_core_core_exc_$signal$next[0:0]$13809
+ assign $3\core_core_core_oe_ok$next[0:0]$13924 $1\core_core_core_oe_ok$next[0:0]$13817
+ assign $3\core_core_core_rc_ok$next[0:0]$13925 $1\core_core_core_rc_ok$next[0:0]$13819
+ assign $3\core_core_cr_in1_ok$next[0:0]$13926 $1\core_core_cr_in1_ok$next[0:0]$13823
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13927 $1\core_core_cr_in2_ok$2$next[0:0]$13826
+ assign $3\core_core_cr_in2_ok$next[0:0]$13928 $1\core_core_cr_in2_ok$next[0:0]$13827
+ assign $3\core_core_cr_wr_ok$next[0:0]$13929 $1\core_core_cr_wr_ok$next[0:0]$13829
+ assign $3\core_core_fast1_ok$next[0:0]$13930 $1\core_core_fast1_ok$next[0:0]$13832
+ assign $3\core_core_fast2_ok$next[0:0]$13931 $1\core_core_fast2_ok$next[0:0]$13834
+ assign $3\core_core_reg1_ok$next[0:0]$13932 $1\core_core_reg1_ok$next[0:0]$13839
+ assign $3\core_core_reg2_ok$next[0:0]$13933 $1\core_core_reg2_ok$next[0:0]$13841
+ assign $3\core_core_reg3_ok$next[0:0]$13934 $1\core_core_reg3_ok$next[0:0]$13843
+ assign $3\core_core_spr1_ok$next[0:0]$13935 $1\core_core_spr1_ok$next[0:0]$13846
+ assign $3\core_cr_out_ok$next[0:0]$13936 $1\core_cr_out_ok$next[0:0]$13849
+ assign $3\core_ea_ok$next[0:0]$13937 $1\core_ea_ok$next[0:0]$13850
+ assign $3\core_fasto1_ok$next[0:0]$13938 $1\core_fasto1_ok$next[0:0]$13851
+ assign $3\core_fasto2_ok$next[0:0]$13939 $1\core_fasto2_ok$next[0:0]$13852
+ assign $3\core_rego_ok$next[0:0]$13940 $1\core_rego_ok$next[0:0]$13853
+ assign $3\core_spro_ok$next[0:0]$13941 $1\core_spro_ok$next[0:0]$13854
+ end
+ sync always
+ update \core_asmcode$next $0\core_asmcode$next[7:0]$13738
+ update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13739
+ update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13740
+ update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13741
+ update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13742
+ update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13743
+ update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13744
+ update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13745
+ update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13746
+ update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13747
+ update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13748
+ update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13749
+ update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13750
+ update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$13751
+ update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13752
+ update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13753
+ update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13754
+ update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13755
+ update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13756
+ update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13757
+ update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13758
+ update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13759
+ update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13760
+ update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13761
+ update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13762
+ update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13763
+ update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13764
+ update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13765
+ update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13766
+ update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13767
+ update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13768
+ update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13769
+ update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13770
+ update \core_core_ea$next $0\core_core_ea$next[6:0]$13771
+ update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13772
+ update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13773
+ update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13774
+ update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13775
+ update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13776
+ update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13777
+ update \core_core_lk$next $0\core_core_lk$next[0:0]$13778
+ update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13779
+ update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13780
+ update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13781
+ update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13782
+ update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13783
+ update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13784
+ update \core_core_rego$next $0\core_core_rego$next[6:0]$13785
+ update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13786
+ update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13787
+ update \core_core_spro$next $0\core_core_spro$next[9:0]$13788
+ update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13789
+ update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13790
+ update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13791
+ update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13792
+ update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13793
+ update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13794
+ update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13795
+ update \core_xer_out$next $0\core_xer_out$next[0:0]$13796
+ end
+ attribute \src "libresoc.v:194471.3-194479.6"
+ process $proc$libresoc.v:194471$13942
+ assign { } { }
+ assign { } { }
+ assign $0\dec2_cur_eint$next[0:0]$13943 $1\dec2_cur_eint$next[0:0]$13944
+ attribute \src "libresoc.v:194472.5-194472.29"
+ switch \initial
+ attribute \src "libresoc.v:194472.9-194472.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\dec2_cur_eint$next[0:0]$13944 1'0
+ case
+ assign $1\dec2_cur_eint$next[0:0]$13944 \xics_icp_core_irq_o
+ end
+ sync always
+ update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13943
+ end
+ attribute \src "libresoc.v:194480.3-194489.6"
+ process $proc$libresoc.v:194480$13945
+ assign { } { }
+ assign { } { }
+ assign $0\delay$next[1:0]$13946 $1\delay$next[1:0]$13947
+ attribute \src "libresoc.v:194481.5-194481.29"
+ switch \initial
+ attribute \src "libresoc.v:194481.9-194481.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509"
+ switch \$23
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\delay$next[1:0]$13947 \$25 [1:0]
+ case
+ assign $1\delay$next[1:0]$13947 \delay
+ end
+ sync always
+ update \delay$next $0\delay$next[1:0]$13946
+ end
+ connect \$101 $add$libresoc.v:191878$13258_Y
+ connect \$103 $mul$libresoc.v:191879$13259_Y
+ connect \$99 $shr$libresoc.v:191880$13260_Y [31:0]
+ connect \$106 $not$libresoc.v:191881$13261_Y
+ connect \$108 $not$libresoc.v:191882$13262_Y
+ connect \$110 $and$libresoc.v:191883$13263_Y
+ connect \$112 $not$libresoc.v:191884$13264_Y
+ connect \$114 $not$libresoc.v:191885$13265_Y
+ connect \$116 $and$libresoc.v:191886$13266_Y
+ connect \$118 $or$libresoc.v:191887$13267_Y
+ connect \$120 $or$libresoc.v:191888$13268_Y
+ connect \$122 1'0
+ connect \$124 $not$libresoc.v:191890$13269_Y
+ connect \$126 $not$libresoc.v:191891$13270_Y
+ connect \$128 $and$libresoc.v:191892$13271_Y
+ connect \$130 $not$libresoc.v:191893$13272_Y
+ connect \$132 $not$libresoc.v:191894$13273_Y
+ connect \$134 $and$libresoc.v:191895$13274_Y
+ connect \$136 1'0
+ connect \$138 $eq$libresoc.v:191897$13275_Y
+ connect \$140 $and$libresoc.v:191898$13276_Y
+ connect \$142 $not$libresoc.v:191899$13277_Y
+ connect \$144 $not$libresoc.v:191900$13278_Y
+ connect \$146 $and$libresoc.v:191901$13279_Y
+ connect \$148 $or$libresoc.v:191902$13280_Y
+ connect \$150 $or$libresoc.v:191903$13281_Y
+ connect \$152 $not$libresoc.v:191904$13282_Y
+ connect \$154 $not$libresoc.v:191905$13283_Y
+ connect \$156 $and$libresoc.v:191906$13284_Y
+ connect \$158 $not$libresoc.v:191907$13285_Y
+ connect \$160 $not$libresoc.v:191908$13286_Y
+ connect \$162 $and$libresoc.v:191909$13287_Y
+ connect \$164 $not$libresoc.v:191910$13288_Y
+ connect \$166 $not$libresoc.v:191911$13289_Y
+ connect \$168 $and$libresoc.v:191912$13290_Y
+ connect \$170 $not$libresoc.v:191913$13291_Y
+ connect \$172 $not$libresoc.v:191914$13292_Y
+ connect \$174 $and$libresoc.v:191915$13293_Y
+ connect \$176 $not$libresoc.v:191916$13294_Y
+ connect \$178 $not$libresoc.v:191917$13295_Y
+ connect \$180 $and$libresoc.v:191918$13296_Y
+ connect \$182 $not$libresoc.v:191919$13297_Y
+ connect \$184 $not$libresoc.v:191920$13298_Y
+ connect \$186 $and$libresoc.v:191921$13299_Y
+ connect \$189 $and$libresoc.v:191922$13300_Y
+ connect \$188 $reduce_or$libresoc.v:191923$13301_Y
+ connect \$192 $not$libresoc.v:191924$13302_Y
+ connect \$194 $not$libresoc.v:191925$13303_Y
+ connect \$196 $and$libresoc.v:191926$13304_Y
+ connect \$198 $not$libresoc.v:191927$13305_Y
+ connect \$200 $not$libresoc.v:191928$13306_Y
+ connect \$202 $and$libresoc.v:191929$13307_Y
+ connect \$204 $or$libresoc.v:191930$13308_Y
+ connect \$206 $or$libresoc.v:191931$13309_Y
+ connect \$208 1'0
+ connect \$210 $not$libresoc.v:191933$13310_Y
+ connect \$212 $not$libresoc.v:191934$13311_Y
+ connect \$214 $and$libresoc.v:191935$13312_Y
+ connect \$216 $not$libresoc.v:191936$13313_Y
+ connect \$218 $not$libresoc.v:191937$13314_Y
+ connect \$220 $and$libresoc.v:191938$13315_Y
+ connect \$223 $and$libresoc.v:191939$13316_Y
+ connect \$222 $reduce_or$libresoc.v:191940$13317_Y
+ connect \$226 $not$libresoc.v:191941$13318_Y
+ connect \$228 $not$libresoc.v:191942$13319_Y
+ connect \$230 $and$libresoc.v:191943$13320_Y
+ connect \$232 $not$libresoc.v:191944$13321_Y
+ connect \$234 $not$libresoc.v:191945$13322_Y
+ connect \$236 $and$libresoc.v:191946$13323_Y
+ connect \$23 $ne$libresoc.v:191947$13324_Y
+ connect \$239 $add$libresoc.v:191948$13325_Y
+ connect \$241 $not$libresoc.v:191949$13326_Y
+ connect \$243 $not$libresoc.v:191950$13327_Y
+ connect \$245 $and$libresoc.v:191951$13328_Y
+ connect \$247 $eq$libresoc.v:191952$13329_Y
+ connect \$249 $pos$libresoc.v:191953$13330_Y
+ connect \$251 $ne$libresoc.v:191954$13331_Y
+ connect \$253 $not$libresoc.v:191955$13332_Y
+ connect \$255 $not$libresoc.v:191956$13333_Y
+ connect \$257 $pos$libresoc.v:191957$13335_Y
+ connect \$259 $pos$libresoc.v:191958$13337_Y
+ connect \$262 $sub$libresoc.v:191959$13338_Y
+ connect \$265 $add$libresoc.v:191960$13339_Y
+ connect \$26 $sub$libresoc.v:191961$13340_Y
+ connect \$28 $or$libresoc.v:191962$13341_Y
+ connect \$30 $or$libresoc.v:191963$13342_Y
+ connect \$32 $ne$libresoc.v:191964$13343_Y
+ connect \$34 $not$libresoc.v:191965$13344_Y
+ connect \$36 $and$libresoc.v:191966$13345_Y
+ connect \$38 $not$libresoc.v:191967$13346_Y
+ connect \$40 $not$libresoc.v:191968$13347_Y
+ connect \$42 $pos$libresoc.v:191969$13349_Y
+ connect \$44 $not$libresoc.v:191970$13350_Y
+ connect \$46 $not$libresoc.v:191971$13351_Y
+ connect \$48 $and$libresoc.v:191972$13352_Y
+ connect \$50 1'0
+ connect \$52 $eq$libresoc.v:191974$13353_Y
+ connect \$54 $and$libresoc.v:191975$13354_Y
+ connect \$56 $not$libresoc.v:191976$13355_Y
+ connect \$58 $not$libresoc.v:191977$13356_Y
+ connect \$60 $and$libresoc.v:191978$13357_Y
+ connect \$62 $or$libresoc.v:191979$13358_Y
+ connect \$64 $or$libresoc.v:191980$13359_Y
+ connect \$66 $not$libresoc.v:191981$13360_Y
+ connect \$68 $not$libresoc.v:191982$13361_Y
+ connect \$70 $and$libresoc.v:191983$13362_Y
+ connect \$72 1'0
+ connect \$74 $eq$libresoc.v:191985$13363_Y
+ connect \$76 $and$libresoc.v:191986$13364_Y
+ connect \$78 $not$libresoc.v:191987$13365_Y
+ connect \$80 $not$libresoc.v:191988$13366_Y
+ connect \$82 $and$libresoc.v:191989$13367_Y
+ connect \$84 $or$libresoc.v:191990$13368_Y
+ connect \$86 $or$libresoc.v:191991$13369_Y
+ connect \$88 $not$libresoc.v:191992$13370_Y
+ connect \$90 $not$libresoc.v:191993$13371_Y
+ connect \$93 $add$libresoc.v:191994$13372_Y
+ connect \$96 $mul$libresoc.v:191995$13373_Y
+ connect \$95 $shr$libresoc.v:191996$13374_Y [31:0]
connect \$25 \$26
- connect \$62 \$63
- connect \$79 \$82
- connect \$91 \$92
- connect \$171 \$172
- connect \$174 \$175
+ connect \$92 \$93
+ connect \$100 \$101
+ connect \$238 \$239
+ connect \$261 \$262
+ connect \$264 \$265
connect \svstate_i_ok 1'0
connect \svstate_i 0
- connect \update_svstate 1'0
- connect { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep }
- connect \dec2_raw_opcode_in$next \fetch_insn_o
connect \dbg_core_dbg_msr \dec2_cur_msr
- connect { \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } \svstate [31:0]
+ connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0]
connect \dbg_core_dbg_pc \pc
connect \dbg_terminate_i \core_core_terminate_o
connect \pc_o \dec2_cur_pc
connect \ti_rst \$32
connect \por_clk \clk
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
- connect \sram4k_3_enable \jtag_wb_sram_en
- connect \sram4k_2_enable \jtag_wb_sram_en
- connect \sram4k_1_enable \jtag_wb_sram_en
- connect \sram4k_0_enable \jtag_wb_sram_en
end
-attribute \src "libresoc.v:197406.1-198593.10"
+attribute \src "libresoc.v:194517.1-195704.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0"
attribute \generator "nMigen"
module \trap0
- attribute \src "libresoc.v:198138.3-198139.25"
+ attribute \src "libresoc.v:195249.3-195250.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:198136.3-198137.41"
+ attribute \src "libresoc.v:195247.3-195248.41"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:198496.3-198504.6"
- wire $0\alu_l_r_alu$next[0:0]$14528
- attribute \src "libresoc.v:198064.3-198065.39"
+ attribute \src "libresoc.v:195607.3-195615.6"
+ wire $0\alu_l_r_alu$next[0:0]$14268
+ attribute \src "libresoc.v:195175.3-195176.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14454
- attribute \src "libresoc.v:198104.3-198105.61"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14194
+ attribute \src "libresoc.v:195215.3-195216.61"
wire width 64 $0\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455
- attribute \src "libresoc.v:198098.3-198099.69"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195
+ attribute \src "libresoc.v:195209.3-195210.69"
wire width 13 $0\alu_trap0_trap_op__fn_unit[12:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14456
- attribute \src "libresoc.v:198100.3-198101.63"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14196
+ attribute \src "libresoc.v:195211.3-195212.63"
wire width 32 $0\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14457
- attribute \src "libresoc.v:198096.3-198097.73"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14197
+ attribute \src "libresoc.v:195207.3-195208.73"
wire width 7 $0\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458
- attribute \src "libresoc.v:198106.3-198107.71"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198
+ attribute \src "libresoc.v:195217.3-195218.71"
wire $0\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459
- attribute \src "libresoc.v:198112.3-198113.71"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199
+ attribute \src "libresoc.v:195223.3-195224.71"
wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14460
- attribute \src "libresoc.v:198102.3-198103.61"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14200
+ attribute \src "libresoc.v:195213.3-195214.61"
wire width 64 $0\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461
- attribute \src "libresoc.v:198110.3-198111.71"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201
+ attribute \src "libresoc.v:195221.3-195222.71"
wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14462
- attribute \src "libresoc.v:198108.3-198109.71"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14202
+ attribute \src "libresoc.v:195219.3-195220.71"
wire width 8 $0\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:198487.3-198495.6"
- wire $0\alui_l_r_alui$next[0:0]$14525
- attribute \src "libresoc.v:198066.3-198067.43"
+ attribute \src "libresoc.v:195598.3-195606.6"
+ wire $0\alui_l_r_alui$next[0:0]$14265
+ attribute \src "libresoc.v:195177.3-195178.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:198337.3-198358.6"
- wire width 64 $0\data_r0__o$next[63:0]$14473
- attribute \src "libresoc.v:198092.3-198093.37"
+ attribute \src "libresoc.v:195448.3-195469.6"
+ wire width 64 $0\data_r0__o$next[63:0]$14213
+ attribute \src "libresoc.v:195203.3-195204.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:198337.3-198358.6"
- wire $0\data_r0__o_ok$next[0:0]$14474
- attribute \src "libresoc.v:198094.3-198095.43"
+ attribute \src "libresoc.v:195448.3-195469.6"
+ wire $0\data_r0__o_ok$next[0:0]$14214
+ attribute \src "libresoc.v:195205.3-195206.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:198359.3-198380.6"
- wire width 64 $0\data_r1__fast1$next[63:0]$14481
- attribute \src "libresoc.v:198088.3-198089.45"
+ attribute \src "libresoc.v:195470.3-195491.6"
+ wire width 64 $0\data_r1__fast1$next[63:0]$14221
+ attribute \src "libresoc.v:195199.3-195200.45"
wire width 64 $0\data_r1__fast1[63:0]
- attribute \src "libresoc.v:198359.3-198380.6"
- wire $0\data_r1__fast1_ok$next[0:0]$14482
- attribute \src "libresoc.v:198090.3-198091.51"
+ attribute \src "libresoc.v:195470.3-195491.6"
+ wire $0\data_r1__fast1_ok$next[0:0]$14222
+ attribute \src "libresoc.v:195201.3-195202.51"
wire $0\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:198381.3-198402.6"
- wire width 64 $0\data_r2__fast2$next[63:0]$14489
- attribute \src "libresoc.v:198084.3-198085.45"
+ attribute \src "libresoc.v:195492.3-195513.6"
+ wire width 64 $0\data_r2__fast2$next[63:0]$14229
+ attribute \src "libresoc.v:195195.3-195196.45"
wire width 64 $0\data_r2__fast2[63:0]
- attribute \src "libresoc.v:198381.3-198402.6"
- wire $0\data_r2__fast2_ok$next[0:0]$14490
- attribute \src "libresoc.v:198086.3-198087.51"
+ attribute \src "libresoc.v:195492.3-195513.6"
+ wire $0\data_r2__fast2_ok$next[0:0]$14230
+ attribute \src "libresoc.v:195197.3-195198.51"
wire $0\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:198403.3-198424.6"
- wire width 64 $0\data_r3__nia$next[63:0]$14497
- attribute \src "libresoc.v:198080.3-198081.41"
+ attribute \src "libresoc.v:195514.3-195535.6"
+ wire width 64 $0\data_r3__nia$next[63:0]$14237
+ attribute \src "libresoc.v:195191.3-195192.41"
wire width 64 $0\data_r3__nia[63:0]
- attribute \src "libresoc.v:198403.3-198424.6"
- wire $0\data_r3__nia_ok$next[0:0]$14498
- attribute \src "libresoc.v:198082.3-198083.47"
+ attribute \src "libresoc.v:195514.3-195535.6"
+ wire $0\data_r3__nia_ok$next[0:0]$14238
+ attribute \src "libresoc.v:195193.3-195194.47"
wire $0\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:198425.3-198446.6"
- wire width 64 $0\data_r4__msr$next[63:0]$14505
- attribute \src "libresoc.v:198076.3-198077.41"
+ attribute \src "libresoc.v:195536.3-195557.6"
+ wire width 64 $0\data_r4__msr$next[63:0]$14245
+ attribute \src "libresoc.v:195187.3-195188.41"
wire width 64 $0\data_r4__msr[63:0]
- attribute \src "libresoc.v:198425.3-198446.6"
- wire $0\data_r4__msr_ok$next[0:0]$14506
- attribute \src "libresoc.v:198078.3-198079.47"
+ attribute \src "libresoc.v:195536.3-195557.6"
+ wire $0\data_r4__msr_ok$next[0:0]$14246
+ attribute \src "libresoc.v:195189.3-195190.47"
wire $0\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:198505.3-198514.6"
+ attribute \src "libresoc.v:195616.3-195625.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:198515.3-198524.6"
+ attribute \src "libresoc.v:195626.3-195635.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:198525.3-198534.6"
+ attribute \src "libresoc.v:195636.3-195645.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:198535.3-198544.6"
+ attribute \src "libresoc.v:195646.3-195655.6"
wire width 64 $0\dest4_o[63:0]
- attribute \src "libresoc.v:198545.3-198554.6"
+ attribute \src "libresoc.v:195656.3-195665.6"
wire width 64 $0\dest5_o[63:0]
- attribute \src "libresoc.v:197407.7-197407.20"
+ attribute \src "libresoc.v:194518.7-194518.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:198274.3-198282.6"
- wire $0\opc_l_r_opc$next[0:0]$14439
- attribute \src "libresoc.v:198122.3-198123.39"
+ attribute \src "libresoc.v:195385.3-195393.6"
+ wire $0\opc_l_r_opc$next[0:0]$14179
+ attribute \src "libresoc.v:195233.3-195234.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:198265.3-198273.6"
- wire $0\opc_l_s_opc$next[0:0]$14436
- attribute \src "libresoc.v:198124.3-198125.39"
+ attribute \src "libresoc.v:195376.3-195384.6"
+ wire $0\opc_l_s_opc$next[0:0]$14176
+ attribute \src "libresoc.v:195235.3-195236.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:198555.3-198563.6"
- wire width 5 $0\prev_wr_go$next[4:0]$14536
- attribute \src "libresoc.v:198134.3-198135.37"
+ attribute \src "libresoc.v:195666.3-195674.6"
+ wire width 5 $0\prev_wr_go$next[4:0]$14276
+ attribute \src "libresoc.v:195245.3-195246.37"
wire width 5 $0\prev_wr_go[4:0]
- attribute \src "libresoc.v:198219.3-198228.6"
+ attribute \src "libresoc.v:195330.3-195339.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:198310.3-198318.6"
- wire width 5 $0\req_l_r_req$next[4:0]$14451
- attribute \src "libresoc.v:198114.3-198115.39"
+ attribute \src "libresoc.v:195421.3-195429.6"
+ wire width 5 $0\req_l_r_req$next[4:0]$14191
+ attribute \src "libresoc.v:195225.3-195226.39"
wire width 5 $0\req_l_r_req[4:0]
- attribute \src "libresoc.v:198301.3-198309.6"
- wire width 5 $0\req_l_s_req$next[4:0]$14448
- attribute \src "libresoc.v:198116.3-198117.39"
+ attribute \src "libresoc.v:195412.3-195420.6"
+ wire width 5 $0\req_l_s_req$next[4:0]$14188
+ attribute \src "libresoc.v:195227.3-195228.39"
wire width 5 $0\req_l_s_req[4:0]
- attribute \src "libresoc.v:198238.3-198246.6"
- wire $0\rok_l_r_rdok$next[0:0]$14427
- attribute \src "libresoc.v:198130.3-198131.41"
+ attribute \src "libresoc.v:195349.3-195357.6"
+ wire $0\rok_l_r_rdok$next[0:0]$14167
+ attribute \src "libresoc.v:195241.3-195242.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:198229.3-198237.6"
- wire $0\rok_l_s_rdok$next[0:0]$14424
- attribute \src "libresoc.v:198132.3-198133.41"
+ attribute \src "libresoc.v:195340.3-195348.6"
+ wire $0\rok_l_s_rdok$next[0:0]$14164
+ attribute \src "libresoc.v:195243.3-195244.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:198256.3-198264.6"
- wire $0\rst_l_r_rst$next[0:0]$14433
- attribute \src "libresoc.v:198126.3-198127.39"
+ attribute \src "libresoc.v:195367.3-195375.6"
+ wire $0\rst_l_r_rst$next[0:0]$14173
+ attribute \src "libresoc.v:195237.3-195238.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:198247.3-198255.6"
- wire $0\rst_l_s_rst$next[0:0]$14430
- attribute \src "libresoc.v:198128.3-198129.39"
+ attribute \src "libresoc.v:195358.3-195366.6"
+ wire $0\rst_l_s_rst$next[0:0]$14170
+ attribute \src "libresoc.v:195239.3-195240.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:198292.3-198300.6"
- wire width 4 $0\src_l_r_src$next[3:0]$14445
- attribute \src "libresoc.v:198118.3-198119.39"
+ attribute \src "libresoc.v:195403.3-195411.6"
+ wire width 4 $0\src_l_r_src$next[3:0]$14185
+ attribute \src "libresoc.v:195229.3-195230.39"
wire width 4 $0\src_l_r_src[3:0]
- attribute \src "libresoc.v:198283.3-198291.6"
- wire width 4 $0\src_l_s_src$next[3:0]$14442
- attribute \src "libresoc.v:198120.3-198121.39"
+ attribute \src "libresoc.v:195394.3-195402.6"
+ wire width 4 $0\src_l_s_src$next[3:0]$14182
+ attribute \src "libresoc.v:195231.3-195232.39"
wire width 4 $0\src_l_s_src[3:0]
- attribute \src "libresoc.v:198447.3-198456.6"
- wire width 64 $0\src_r0$next[63:0]$14513
- attribute \src "libresoc.v:198074.3-198075.29"
+ attribute \src "libresoc.v:195558.3-195567.6"
+ wire width 64 $0\src_r0$next[63:0]$14253
+ attribute \src "libresoc.v:195185.3-195186.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:198457.3-198466.6"
- wire width 64 $0\src_r1$next[63:0]$14516
- attribute \src "libresoc.v:198072.3-198073.29"
+ attribute \src "libresoc.v:195568.3-195577.6"
+ wire width 64 $0\src_r1$next[63:0]$14256
+ attribute \src "libresoc.v:195183.3-195184.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:198467.3-198476.6"
- wire width 64 $0\src_r2$next[63:0]$14519
- attribute \src "libresoc.v:198070.3-198071.29"
+ attribute \src "libresoc.v:195578.3-195587.6"
+ wire width 64 $0\src_r2$next[63:0]$14259
+ attribute \src "libresoc.v:195181.3-195182.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:198477.3-198486.6"
- wire width 64 $0\src_r3$next[63:0]$14522
- attribute \src "libresoc.v:198068.3-198069.29"
+ attribute \src "libresoc.v:195588.3-195597.6"
+ wire width 64 $0\src_r3$next[63:0]$14262
+ attribute \src "libresoc.v:195179.3-195180.29"
wire width 64 $0\src_r3[63:0]
- attribute \src "libresoc.v:197533.7-197533.24"
+ attribute \src "libresoc.v:194644.7-194644.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:197543.7-197543.26"
+ attribute \src "libresoc.v:194654.7-194654.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:198496.3-198504.6"
- wire $1\alu_l_r_alu$next[0:0]$14529
- attribute \src "libresoc.v:197551.7-197551.25"
+ attribute \src "libresoc.v:195607.3-195615.6"
+ wire $1\alu_l_r_alu$next[0:0]$14269
+ attribute \src "libresoc.v:194662.7-194662.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14463
- attribute \src "libresoc.v:197587.14-197587.59"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14203
+ attribute \src "libresoc.v:194698.14-194698.59"
wire width 64 $1\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464
- attribute \src "libresoc.v:197605.14-197605.51"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204
+ attribute \src "libresoc.v:194716.14-194716.51"
wire width 13 $1\alu_trap0_trap_op__fn_unit[12:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14465
- attribute \src "libresoc.v:197609.14-197609.45"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14205
+ attribute \src "libresoc.v:194720.14-194720.45"
wire width 32 $1\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466
- attribute \src "libresoc.v:197687.13-197687.49"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206
+ attribute \src "libresoc.v:194798.13-194798.49"
wire width 7 $1\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467
- attribute \src "libresoc.v:197691.7-197691.41"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207
+ attribute \src "libresoc.v:194802.7-194802.41"
wire $1\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468
- attribute \src "libresoc.v:197695.13-197695.48"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208
+ attribute \src "libresoc.v:194806.13-194806.48"
wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14469
- attribute \src "libresoc.v:197699.14-197699.59"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14209
+ attribute \src "libresoc.v:194810.14-194810.59"
wire width 64 $1\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470
- attribute \src "libresoc.v:197703.14-197703.52"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210
+ attribute \src "libresoc.v:194814.14-194814.52"
wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:198319.3-198336.6"
- wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14471
- attribute \src "libresoc.v:197707.13-197707.48"
+ attribute \src "libresoc.v:195430.3-195447.6"
+ wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14211
+ attribute \src "libresoc.v:194818.13-194818.48"
wire width 8 $1\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:198487.3-198495.6"
- wire $1\alui_l_r_alui$next[0:0]$14526
- attribute \src "libresoc.v:197713.7-197713.27"
+ attribute \src "libresoc.v:195598.3-195606.6"
+ wire $1\alui_l_r_alui$next[0:0]$14266
+ attribute \src "libresoc.v:194824.7-194824.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:198337.3-198358.6"
- wire width 64 $1\data_r0__o$next[63:0]$14475
- attribute \src "libresoc.v:197745.14-197745.47"
+ attribute \src "libresoc.v:195448.3-195469.6"
+ wire width 64 $1\data_r0__o$next[63:0]$14215
+ attribute \src "libresoc.v:194856.14-194856.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:198337.3-198358.6"
- wire $1\data_r0__o_ok$next[0:0]$14476
- attribute \src "libresoc.v:197749.7-197749.27"
+ attribute \src "libresoc.v:195448.3-195469.6"
+ wire $1\data_r0__o_ok$next[0:0]$14216
+ attribute \src "libresoc.v:194860.7-194860.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:198359.3-198380.6"
- wire width 64 $1\data_r1__fast1$next[63:0]$14483
- attribute \src "libresoc.v:197753.14-197753.51"
+ attribute \src "libresoc.v:195470.3-195491.6"
+ wire width 64 $1\data_r1__fast1$next[63:0]$14223
+ attribute \src "libresoc.v:194864.14-194864.51"
wire width 64 $1\data_r1__fast1[63:0]
- attribute \src "libresoc.v:198359.3-198380.6"
- wire $1\data_r1__fast1_ok$next[0:0]$14484
- attribute \src "libresoc.v:197757.7-197757.31"
+ attribute \src "libresoc.v:195470.3-195491.6"
+ wire $1\data_r1__fast1_ok$next[0:0]$14224
+ attribute \src "libresoc.v:194868.7-194868.31"
wire $1\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:198381.3-198402.6"
- wire width 64 $1\data_r2__fast2$next[63:0]$14491
- attribute \src "libresoc.v:197761.14-197761.51"
+ attribute \src "libresoc.v:195492.3-195513.6"
+ wire width 64 $1\data_r2__fast2$next[63:0]$14231
+ attribute \src "libresoc.v:194872.14-194872.51"
wire width 64 $1\data_r2__fast2[63:0]
- attribute \src "libresoc.v:198381.3-198402.6"
- wire $1\data_r2__fast2_ok$next[0:0]$14492
- attribute \src "libresoc.v:197765.7-197765.31"
+ attribute \src "libresoc.v:195492.3-195513.6"
+ wire $1\data_r2__fast2_ok$next[0:0]$14232
+ attribute \src "libresoc.v:194876.7-194876.31"
wire $1\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:198403.3-198424.6"
- wire width 64 $1\data_r3__nia$next[63:0]$14499
- attribute \src "libresoc.v:197769.14-197769.49"
+ attribute \src "libresoc.v:195514.3-195535.6"
+ wire width 64 $1\data_r3__nia$next[63:0]$14239
+ attribute \src "libresoc.v:194880.14-194880.49"
wire width 64 $1\data_r3__nia[63:0]
- attribute \src "libresoc.v:198403.3-198424.6"
- wire $1\data_r3__nia_ok$next[0:0]$14500
- attribute \src "libresoc.v:197773.7-197773.29"
+ attribute \src "libresoc.v:195514.3-195535.6"
+ wire $1\data_r3__nia_ok$next[0:0]$14240
+ attribute \src "libresoc.v:194884.7-194884.29"
wire $1\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:198425.3-198446.6"
- wire width 64 $1\data_r4__msr$next[63:0]$14507
- attribute \src "libresoc.v:197777.14-197777.49"
+ attribute \src "libresoc.v:195536.3-195557.6"
+ wire width 64 $1\data_r4__msr$next[63:0]$14247
+ attribute \src "libresoc.v:194888.14-194888.49"
wire width 64 $1\data_r4__msr[63:0]
- attribute \src "libresoc.v:198425.3-198446.6"
- wire $1\data_r4__msr_ok$next[0:0]$14508
- attribute \src "libresoc.v:197781.7-197781.29"
+ attribute \src "libresoc.v:195536.3-195557.6"
+ wire $1\data_r4__msr_ok$next[0:0]$14248
+ attribute \src "libresoc.v:194892.7-194892.29"
wire $1\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:198505.3-198514.6"
+ attribute \src "libresoc.v:195616.3-195625.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:198515.3-198524.6"
+ attribute \src "libresoc.v:195626.3-195635.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:198525.3-198534.6"
+ attribute \src "libresoc.v:195636.3-195645.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:198535.3-198544.6"
+ attribute \src "libresoc.v:195646.3-195655.6"
wire width 64 $1\dest4_o[63:0]
- attribute \src "libresoc.v:198545.3-198554.6"
+ attribute \src "libresoc.v:195656.3-195665.6"
wire width 64 $1\dest5_o[63:0]
- attribute \src "libresoc.v:198274.3-198282.6"
- wire $1\opc_l_r_opc$next[0:0]$14440
- attribute \src "libresoc.v:197812.7-197812.25"
+ attribute \src "libresoc.v:195385.3-195393.6"
+ wire $1\opc_l_r_opc$next[0:0]$14180
+ attribute \src "libresoc.v:194923.7-194923.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:198265.3-198273.6"
- wire $1\opc_l_s_opc$next[0:0]$14437
- attribute \src "libresoc.v:197816.7-197816.25"
+ attribute \src "libresoc.v:195376.3-195384.6"
+ wire $1\opc_l_s_opc$next[0:0]$14177
+ attribute \src "libresoc.v:194927.7-194927.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:198555.3-198563.6"
- wire width 5 $1\prev_wr_go$next[4:0]$14537
- attribute \src "libresoc.v:197926.13-197926.31"
+ attribute \src "libresoc.v:195666.3-195674.6"
+ wire width 5 $1\prev_wr_go$next[4:0]$14277
+ attribute \src "libresoc.v:195037.13-195037.31"
wire width 5 $1\prev_wr_go[4:0]
- attribute \src "libresoc.v:198219.3-198228.6"
+ attribute \src "libresoc.v:195330.3-195339.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:198310.3-198318.6"
- wire width 5 $1\req_l_r_req$next[4:0]$14452
- attribute \src "libresoc.v:197934.13-197934.32"
+ attribute \src "libresoc.v:195421.3-195429.6"
+ wire width 5 $1\req_l_r_req$next[4:0]$14192
+ attribute \src "libresoc.v:195045.13-195045.32"
wire width 5 $1\req_l_r_req[4:0]
- attribute \src "libresoc.v:198301.3-198309.6"
- wire width 5 $1\req_l_s_req$next[4:0]$14449
- attribute \src "libresoc.v:197938.13-197938.32"
+ attribute \src "libresoc.v:195412.3-195420.6"
+ wire width 5 $1\req_l_s_req$next[4:0]$14189
+ attribute \src "libresoc.v:195049.13-195049.32"
wire width 5 $1\req_l_s_req[4:0]
- attribute \src "libresoc.v:198238.3-198246.6"
- wire $1\rok_l_r_rdok$next[0:0]$14428
- attribute \src "libresoc.v:197950.7-197950.26"
+ attribute \src "libresoc.v:195349.3-195357.6"
+ wire $1\rok_l_r_rdok$next[0:0]$14168
+ attribute \src "libresoc.v:195061.7-195061.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:198229.3-198237.6"
- wire $1\rok_l_s_rdok$next[0:0]$14425
- attribute \src "libresoc.v:197954.7-197954.26"
+ attribute \src "libresoc.v:195340.3-195348.6"
+ wire $1\rok_l_s_rdok$next[0:0]$14165
+ attribute \src "libresoc.v:195065.7-195065.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:198256.3-198264.6"
- wire $1\rst_l_r_rst$next[0:0]$14434
- attribute \src "libresoc.v:197958.7-197958.25"
+ attribute \src "libresoc.v:195367.3-195375.6"
+ wire $1\rst_l_r_rst$next[0:0]$14174
+ attribute \src "libresoc.v:195069.7-195069.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:198247.3-198255.6"
- wire $1\rst_l_s_rst$next[0:0]$14431
- attribute \src "libresoc.v:197962.7-197962.25"
+ attribute \src "libresoc.v:195358.3-195366.6"
+ wire $1\rst_l_s_rst$next[0:0]$14171
+ attribute \src "libresoc.v:195073.7-195073.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:198292.3-198300.6"
- wire width 4 $1\src_l_r_src$next[3:0]$14446
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wire width 4 $1\src_l_r_src[3:0]
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wire width 4 $1\src_l_s_src[3:0]
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wire width 64 $1\src_r0[63:0]
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wire width 64 $1\src_r1[63:0]
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wire width 64 $1\src_r2[63:0]
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- wire width 64 $ternary$libresoc.v:198057$14377_Y
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+ wire $2\data_r4__msr_ok$next[0:0]$14250
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+ wire $3\data_r0__o_ok$next[0:0]$14219
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+ wire $reduce_and$libresoc.v:195114$14063_Y
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+ wire $reduce_or$libresoc.v:195136$14085_Y
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+ wire $reduce_or$libresoc.v:195139$14088_Y
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+ wire width 64 $ternary$libresoc.v:195166$14115_Y
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+ wire width 64 $ternary$libresoc.v:195167$14116_Y
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+ wire width 64 $ternary$libresoc.v:195168$14117_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 12 \cu_busy_o
wire output 24 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 25 \fast2_ok
- attribute \src "libresoc.v:197407.7-197407.15"
+ attribute \src "libresoc.v:194518.7-194518.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 30 \msr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:198004$14324
+ cell $and $and$libresoc.v:195115$14064
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:198004$14324_Y
+ connect \Y $and$libresoc.v:195115$14064_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:198005$14325
+ cell $and $and$libresoc.v:195116$14065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:198005$14325_Y
+ connect \Y $and$libresoc.v:195116$14065_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:198006$14326
+ cell $and $and$libresoc.v:195117$14066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:198006$14326_Y
+ connect \Y $and$libresoc.v:195117$14066_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:198007$14327
+ cell $and $and$libresoc.v:195118$14067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:198007$14327_Y
+ connect \Y $and$libresoc.v:195118$14067_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:198008$14328
+ cell $and $and$libresoc.v:195119$14068
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:198008$14328_Y
+ connect \Y $and$libresoc.v:195119$14068_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:198009$14329
+ cell $and $and$libresoc.v:195120$14069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:198009$14329_Y
+ connect \Y $and$libresoc.v:195120$14069_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:198010$14330
+ cell $and $and$libresoc.v:195121$14070
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B { \$101 \$103 \$105 \$107 \$109 }
- connect \Y $and$libresoc.v:198010$14330_Y
+ connect \Y $and$libresoc.v:195121$14070_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:198011$14331
+ cell $and $and$libresoc.v:195122$14071
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$111
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:198011$14331_Y
+ connect \Y $and$libresoc.v:195122$14071_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:198012$14332
+ cell $and $and$libresoc.v:195123$14072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198012$14332_Y
+ connect \Y $and$libresoc.v:195123$14072_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:198013$14333
+ cell $and $and$libresoc.v:195124$14073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198013$14333_Y
+ connect \Y $and$libresoc.v:195124$14073_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:198014$14334
+ cell $and $and$libresoc.v:195125$14074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:198014$14334_Y
+ connect \Y $and$libresoc.v:195125$14074_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:198015$14335
+ cell $and $and$libresoc.v:195126$14075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198015$14335_Y
+ connect \Y $and$libresoc.v:195126$14075_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:198016$14336
+ cell $and $and$libresoc.v:195127$14076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198016$14336_Y
+ connect \Y $and$libresoc.v:195127$14076_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:198017$14337
+ cell $and $and$libresoc.v:195128$14077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198017$14337_Y
+ connect \Y $and$libresoc.v:195128$14077_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:198019$14339
+ cell $and $and$libresoc.v:195130$14079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$13
- connect \Y $and$libresoc.v:198019$14339_Y
+ connect \Y $and$libresoc.v:195130$14079_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:198021$14341
+ cell $and $and$libresoc.v:195132$14081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$17
- connect \Y $and$libresoc.v:198021$14341_Y
+ connect \Y $and$libresoc.v:195132$14081_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:198022$14342
+ cell $and $and$libresoc.v:195133$14082
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:198022$14342_Y
+ connect \Y $and$libresoc.v:195133$14082_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:198024$14344
+ cell $and $and$libresoc.v:195135$14084
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__rel_o
connect \B \$25
- connect \Y $and$libresoc.v:198024$14344_Y
+ connect \Y $and$libresoc.v:195135$14084_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:198027$14347
+ cell $and $and$libresoc.v:195138$14087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$23
- connect \Y $and$libresoc.v:198027$14347_Y
+ connect \Y $and$libresoc.v:195138$14087_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:198031$14351
+ cell $and $and$libresoc.v:195142$14091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:198031$14351_Y
+ connect \Y $and$libresoc.v:195142$14091_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:198033$14353
+ cell $and $and$libresoc.v:195144$14093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$39
- connect \Y $and$libresoc.v:198033$14353_Y
+ connect \Y $and$libresoc.v:195144$14093_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:198034$14354
+ cell $and $and$libresoc.v:195145$14094
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:198034$14354_Y
+ connect \Y $and$libresoc.v:195145$14094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:198036$14356
+ cell $and $and$libresoc.v:195147$14096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B \$45
- connect \Y $and$libresoc.v:198036$14356_Y
+ connect \Y $and$libresoc.v:195147$14096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:198038$14358
+ cell $and $and$libresoc.v:195149$14098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_trap0_n_ready_i
- connect \Y $and$libresoc.v:198038$14358_Y
+ connect \Y $and$libresoc.v:195149$14098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:198039$14359
+ cell $and $and$libresoc.v:195150$14099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \alu_trap0_n_valid_o
- connect \Y $and$libresoc.v:198039$14359_Y
+ connect \Y $and$libresoc.v:195150$14099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:198040$14360
+ cell $and $and$libresoc.v:195151$14100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198040$14360_Y
+ connect \Y $and$libresoc.v:195151$14100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:198045$14365
+ cell $and $and$libresoc.v:195156$14105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198045$14365_Y
+ connect \Y $and$libresoc.v:195156$14105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:198046$14366
+ cell $and $and$libresoc.v:195157$14106
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:198046$14366_Y
+ connect \Y $and$libresoc.v:195157$14106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:198049$14369
+ cell $and $and$libresoc.v:195160$14109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198049$14369_Y
+ connect \Y $and$libresoc.v:195160$14109_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:198050$14370
+ cell $and $and$libresoc.v:195161$14110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198050$14370_Y
+ connect \Y $and$libresoc.v:195161$14110_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:198051$14371
+ cell $and $and$libresoc.v:195162$14111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast2_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198051$14371_Y
+ connect \Y $and$libresoc.v:195162$14111_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:198052$14372
+ cell $and $and$libresoc.v:195163$14112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nia_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198052$14372_Y
+ connect \Y $and$libresoc.v:195163$14112_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:198053$14373
+ cell $and $and$libresoc.v:195164$14113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msr_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:198053$14373_Y
+ connect \Y $and$libresoc.v:195164$14113_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:198059$14379
+ cell $and $and$libresoc.v:195170$14119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:198059$14379_Y
+ connect \Y $and$libresoc.v:195170$14119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:198060$14380
+ cell $and $and$libresoc.v:195171$14120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:198060$14380_Y
+ connect \Y $and$libresoc.v:195171$14120_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:198061$14381
+ cell $and $and$libresoc.v:195172$14121
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:198061$14381_Y
+ connect \Y $and$libresoc.v:195172$14121_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:198062$14382
+ cell $and $and$libresoc.v:195173$14122
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$93
connect \B 4'1111
- connect \Y $and$libresoc.v:198062$14382_Y
+ connect \Y $and$libresoc.v:195173$14122_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:198035$14355
+ cell $eq $eq$libresoc.v:195146$14095
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B 1'0
- connect \Y $eq$libresoc.v:198035$14355_Y
+ connect \Y $eq$libresoc.v:195146$14095_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:198037$14357
+ cell $eq $eq$libresoc.v:195148$14097
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:198037$14357_Y
+ connect \Y $eq$libresoc.v:195148$14097_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:198018$14338
+ cell $not $not$libresoc.v:195129$14078
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:198018$14338_Y
+ connect \Y $not$libresoc.v:195129$14078_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:198020$14340
+ cell $not $not$libresoc.v:195131$14080
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:198020$14340_Y
+ connect \Y $not$libresoc.v:195131$14080_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:198023$14343
+ cell $not $not$libresoc.v:195134$14083
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:198023$14343_Y
+ connect \Y $not$libresoc.v:195134$14083_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:198026$14346
+ cell $not $not$libresoc.v:195137$14086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:198026$14346_Y
+ connect \Y $not$libresoc.v:195137$14086_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:198032$14352
+ cell $not $not$libresoc.v:195143$14092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_ready_i
- connect \Y $not$libresoc.v:198032$14352_Y
+ connect \Y $not$libresoc.v:195143$14092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:198047$14367
+ cell $not $not$libresoc.v:195158$14107
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:198047$14367_Y
+ connect \Y $not$libresoc.v:195158$14107_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:198063$14383
+ cell $not $not$libresoc.v:195174$14123
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:198063$14383_Y
+ connect \Y $not$libresoc.v:195174$14123_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:198030$14350
+ cell $or $or$libresoc.v:195141$14090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:198030$14350_Y
+ connect \Y $or$libresoc.v:195141$14090_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:198041$14361
+ cell $or $or$libresoc.v:195152$14101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:198041$14361_Y
+ connect \Y $or$libresoc.v:195152$14101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:198042$14362
+ cell $or $or$libresoc.v:195153$14102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:198042$14362_Y
+ connect \Y $or$libresoc.v:195153$14102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:198043$14363
+ cell $or $or$libresoc.v:195154$14103
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:198043$14363_Y
+ connect \Y $or$libresoc.v:195154$14103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:198044$14364
+ cell $or $or$libresoc.v:195155$14104
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:198044$14364_Y
+ connect \Y $or$libresoc.v:195155$14104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:198048$14368
+ cell $or $or$libresoc.v:195159$14108
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:198048$14368_Y
+ connect \Y $or$libresoc.v:195159$14108_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:198058$14378
+ cell $or $or$libresoc.v:195169$14118
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$6
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:198058$14378_Y
+ connect \Y $or$libresoc.v:195169$14118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:198003$14323
+ cell $reduce_and $reduce_and$libresoc.v:195114$14063
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $reduce_and$libresoc.v:198003$14323_Y
+ connect \Y $reduce_and$libresoc.v:195114$14063_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:198025$14345
+ cell $reduce_or $reduce_or$libresoc.v:195136$14085
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $reduce_or$libresoc.v:198025$14345_Y
+ connect \Y $reduce_or$libresoc.v:195136$14085_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:198028$14348
+ cell $reduce_or $reduce_or$libresoc.v:195139$14088
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:198028$14348_Y
+ connect \Y $reduce_or$libresoc.v:195139$14088_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:198029$14349
+ cell $reduce_or $reduce_or$libresoc.v:195140$14089
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:198029$14349_Y
+ connect \Y $reduce_or$libresoc.v:195140$14089_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:198054$14374
+ cell $mux $ternary$libresoc.v:195165$14114
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:198054$14374_Y
+ connect \Y $ternary$libresoc.v:195165$14114_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:198055$14375
+ cell $mux $ternary$libresoc.v:195166$14115
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:198055$14375_Y
+ connect \Y $ternary$libresoc.v:195166$14115_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:198056$14376
+ cell $mux $ternary$libresoc.v:195167$14116
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:198056$14376_Y
+ connect \Y $ternary$libresoc.v:195167$14116_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:198057$14377
+ cell $mux $ternary$libresoc.v:195168$14117
parameter \WIDTH 64
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:198057$14377_Y
+ connect \Y $ternary$libresoc.v:195168$14117_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198140.14-198146.4"
+ attribute \src "libresoc.v:195251.14-195257.4"
cell \alu_l$45 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198147.13-198177.4"
+ attribute \src "libresoc.v:195258.13-195288.4"
cell \alu_trap0 \alu_trap0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \trap_op__traptype \alu_trap0_trap_op__traptype
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198178.15-198184.4"
+ attribute \src "libresoc.v:195289.15-195295.4"
cell \alui_l$44 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198185.14-198191.4"
+ attribute \src "libresoc.v:195296.14-195302.4"
cell \opc_l$40 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198192.14-198198.4"
+ attribute \src "libresoc.v:195303.14-195309.4"
cell \req_l$41 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198199.14-198205.4"
+ attribute \src "libresoc.v:195310.14-195316.4"
cell \rok_l$43 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198206.14-198211.4"
+ attribute \src "libresoc.v:195317.14-195322.4"
cell \rst_l$42 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198212.14-198218.4"
+ attribute \src "libresoc.v:195323.14-195329.4"
cell \src_l$39 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:197407.7-197407.20"
- process $proc$libresoc.v:197407$14538
+ attribute \src "libresoc.v:194518.7-194518.20"
+ process $proc$libresoc.v:194518$14278
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:197533.7-197533.24"
- process $proc$libresoc.v:197533$14539
+ attribute \src "libresoc.v:194644.7-194644.24"
+ process $proc$libresoc.v:194644$14279
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:197543.7-197543.26"
- process $proc$libresoc.v:197543$14540
+ attribute \src "libresoc.v:194654.7-194654.26"
+ process $proc$libresoc.v:194654$14280
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:197551.7-197551.25"
- process $proc$libresoc.v:197551$14541
+ attribute \src "libresoc.v:194662.7-194662.25"
+ process $proc$libresoc.v:194662$14281
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:197587.14-197587.59"
- process $proc$libresoc.v:197587$14542
+ attribute \src "libresoc.v:194698.14-194698.59"
+ process $proc$libresoc.v:194698$14282
assign { } { }
assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:197605.14-197605.51"
- process $proc$libresoc.v:197605$14543
+ attribute \src "libresoc.v:194716.14-194716.51"
+ process $proc$libresoc.v:194716$14283
assign { } { }
assign $1\alu_trap0_trap_op__fn_unit[12:0] 13'0000000000000
sync always
sync init
update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:197609.14-197609.45"
- process $proc$libresoc.v:197609$14544
+ attribute \src "libresoc.v:194720.14-194720.45"
+ process $proc$libresoc.v:194720$14284
assign { } { }
assign $1\alu_trap0_trap_op__insn[31:0] 0
sync always
sync init
update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:197687.13-197687.49"
- process $proc$libresoc.v:197687$14545
+ attribute \src "libresoc.v:194798.13-194798.49"
+ process $proc$libresoc.v:194798$14285
assign { } { }
assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:197691.7-197691.41"
- process $proc$libresoc.v:197691$14546
+ attribute \src "libresoc.v:194802.7-194802.41"
+ process $proc$libresoc.v:194802$14286
assign { } { }
assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:197695.13-197695.48"
- process $proc$libresoc.v:197695$14547
+ attribute \src "libresoc.v:194806.13-194806.48"
+ process $proc$libresoc.v:194806$14287
assign { } { }
assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:197699.14-197699.59"
- process $proc$libresoc.v:197699$14548
+ attribute \src "libresoc.v:194810.14-194810.59"
+ process $proc$libresoc.v:194810$14288
assign { } { }
assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:197703.14-197703.52"
- process $proc$libresoc.v:197703$14549
+ attribute \src "libresoc.v:194814.14-194814.52"
+ process $proc$libresoc.v:194814$14289
assign { } { }
assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000
sync always
sync init
update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:197707.13-197707.48"
- process $proc$libresoc.v:197707$14550
+ attribute \src "libresoc.v:194818.13-194818.48"
+ process $proc$libresoc.v:194818$14290
assign { } { }
assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:197713.7-197713.27"
- process $proc$libresoc.v:197713$14551
+ attribute \src "libresoc.v:194824.7-194824.27"
+ process $proc$libresoc.v:194824$14291
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:197745.14-197745.47"
- process $proc$libresoc.v:197745$14552
+ attribute \src "libresoc.v:194856.14-194856.47"
+ process $proc$libresoc.v:194856$14292
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:197749.7-197749.27"
- process $proc$libresoc.v:197749$14553
+ attribute \src "libresoc.v:194860.7-194860.27"
+ process $proc$libresoc.v:194860$14293
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:197753.14-197753.51"
- process $proc$libresoc.v:197753$14554
+ attribute \src "libresoc.v:194864.14-194864.51"
+ process $proc$libresoc.v:194864$14294
assign { } { }
assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__fast1 $1\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:197757.7-197757.31"
- process $proc$libresoc.v:197757$14555
+ attribute \src "libresoc.v:194868.7-194868.31"
+ process $proc$libresoc.v:194868$14295
assign { } { }
assign $1\data_r1__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:197761.14-197761.51"
- process $proc$libresoc.v:197761$14556
+ attribute \src "libresoc.v:194872.14-194872.51"
+ process $proc$libresoc.v:194872$14296
assign { } { }
assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast2 $1\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:197765.7-197765.31"
- process $proc$libresoc.v:197765$14557
+ attribute \src "libresoc.v:194876.7-194876.31"
+ process $proc$libresoc.v:194876$14297
assign { } { }
assign $1\data_r2__fast2_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:197769.14-197769.49"
- process $proc$libresoc.v:197769$14558
+ attribute \src "libresoc.v:194880.14-194880.49"
+ process $proc$libresoc.v:194880$14298
assign { } { }
assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r3__nia $1\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:197773.7-197773.29"
- process $proc$libresoc.v:197773$14559
+ attribute \src "libresoc.v:194884.7-194884.29"
+ process $proc$libresoc.v:194884$14299
assign { } { }
assign $1\data_r3__nia_ok[0:0] 1'0
sync always
sync init
update \data_r3__nia_ok $1\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:197777.14-197777.49"
- process $proc$libresoc.v:197777$14560
+ attribute \src "libresoc.v:194888.14-194888.49"
+ process $proc$libresoc.v:194888$14300
assign { } { }
assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r4__msr $1\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:197781.7-197781.29"
- process $proc$libresoc.v:197781$14561
+ attribute \src "libresoc.v:194892.7-194892.29"
+ process $proc$libresoc.v:194892$14301
assign { } { }
assign $1\data_r4__msr_ok[0:0] 1'0
sync always
sync init
update \data_r4__msr_ok $1\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:197812.7-197812.25"
- process $proc$libresoc.v:197812$14562
+ attribute \src "libresoc.v:194923.7-194923.25"
+ process $proc$libresoc.v:194923$14302
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:197816.7-197816.25"
- process $proc$libresoc.v:197816$14563
+ attribute \src "libresoc.v:194927.7-194927.25"
+ process $proc$libresoc.v:194927$14303
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:197926.13-197926.31"
- process $proc$libresoc.v:197926$14564
+ attribute \src "libresoc.v:195037.13-195037.31"
+ process $proc$libresoc.v:195037$14304
assign { } { }
assign $1\prev_wr_go[4:0] 5'00000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:197934.13-197934.32"
- process $proc$libresoc.v:197934$14565
+ attribute \src "libresoc.v:195045.13-195045.32"
+ process $proc$libresoc.v:195045$14305
assign { } { }
assign $1\req_l_r_req[4:0] 5'11111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:197938.13-197938.32"
- process $proc$libresoc.v:197938$14566
+ attribute \src "libresoc.v:195049.13-195049.32"
+ process $proc$libresoc.v:195049$14306
assign { } { }
assign $1\req_l_s_req[4:0] 5'00000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:197950.7-197950.26"
- process $proc$libresoc.v:197950$14567
+ attribute \src "libresoc.v:195061.7-195061.26"
+ process $proc$libresoc.v:195061$14307
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:197954.7-197954.26"
- process $proc$libresoc.v:197954$14568
+ attribute \src "libresoc.v:195065.7-195065.26"
+ process $proc$libresoc.v:195065$14308
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:197958.7-197958.25"
- process $proc$libresoc.v:197958$14569
+ attribute \src "libresoc.v:195069.7-195069.25"
+ process $proc$libresoc.v:195069$14309
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:197962.7-197962.25"
- process $proc$libresoc.v:197962$14570
+ attribute \src "libresoc.v:195073.7-195073.25"
+ process $proc$libresoc.v:195073$14310
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:197978.13-197978.31"
- process $proc$libresoc.v:197978$14571
+ attribute \src "libresoc.v:195089.13-195089.31"
+ process $proc$libresoc.v:195089$14311
assign { } { }
assign $1\src_l_r_src[3:0] 4'1111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:197982.13-197982.31"
- process $proc$libresoc.v:197982$14572
+ attribute \src "libresoc.v:195093.13-195093.31"
+ process $proc$libresoc.v:195093$14312
assign { } { }
assign $1\src_l_s_src[3:0] 4'0000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:197986.14-197986.43"
- process $proc$libresoc.v:197986$14573
+ attribute \src "libresoc.v:195097.14-195097.43"
+ process $proc$libresoc.v:195097$14313
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:197990.14-197990.43"
- process $proc$libresoc.v:197990$14574
+ attribute \src "libresoc.v:195101.14-195101.43"
+ process $proc$libresoc.v:195101$14314
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:197994.14-197994.43"
- process $proc$libresoc.v:197994$14575
+ attribute \src "libresoc.v:195105.14-195105.43"
+ process $proc$libresoc.v:195105$14315
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:197998.14-197998.43"
- process $proc$libresoc.v:197998$14576
+ attribute \src "libresoc.v:195109.14-195109.43"
+ process $proc$libresoc.v:195109$14316
assign { } { }
assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r3 $1\src_r3[63:0]
end
- attribute \src "libresoc.v:198064.3-198065.39"
- process $proc$libresoc.v:198064$14384
+ attribute \src "libresoc.v:195175.3-195176.39"
+ process $proc$libresoc.v:195175$14124
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:198066.3-198067.43"
- process $proc$libresoc.v:198066$14385
+ attribute \src "libresoc.v:195177.3-195178.43"
+ process $proc$libresoc.v:195177$14125
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:198068.3-198069.29"
- process $proc$libresoc.v:198068$14386
+ attribute \src "libresoc.v:195179.3-195180.29"
+ process $proc$libresoc.v:195179$14126
assign { } { }
assign $0\src_r3[63:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[63:0]
end
- attribute \src "libresoc.v:198070.3-198071.29"
- process $proc$libresoc.v:198070$14387
+ attribute \src "libresoc.v:195181.3-195182.29"
+ process $proc$libresoc.v:195181$14127
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:198072.3-198073.29"
- process $proc$libresoc.v:198072$14388
+ attribute \src "libresoc.v:195183.3-195184.29"
+ process $proc$libresoc.v:195183$14128
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:198074.3-198075.29"
- process $proc$libresoc.v:198074$14389
+ attribute \src "libresoc.v:195185.3-195186.29"
+ process $proc$libresoc.v:195185$14129
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:198076.3-198077.41"
- process $proc$libresoc.v:198076$14390
+ attribute \src "libresoc.v:195187.3-195188.41"
+ process $proc$libresoc.v:195187$14130
assign { } { }
assign $0\data_r4__msr[63:0] \data_r4__msr$next
sync posedge \coresync_clk
update \data_r4__msr $0\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:198078.3-198079.47"
- process $proc$libresoc.v:198078$14391
+ attribute \src "libresoc.v:195189.3-195190.47"
+ process $proc$libresoc.v:195189$14131
assign { } { }
assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next
sync posedge \coresync_clk
update \data_r4__msr_ok $0\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:198080.3-198081.41"
- process $proc$libresoc.v:198080$14392
+ attribute \src "libresoc.v:195191.3-195192.41"
+ process $proc$libresoc.v:195191$14132
assign { } { }
assign $0\data_r3__nia[63:0] \data_r3__nia$next
sync posedge \coresync_clk
update \data_r3__nia $0\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:198082.3-198083.47"
- process $proc$libresoc.v:198082$14393
+ attribute \src "libresoc.v:195193.3-195194.47"
+ process $proc$libresoc.v:195193$14133
assign { } { }
assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next
sync posedge \coresync_clk
update \data_r3__nia_ok $0\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:198084.3-198085.45"
- process $proc$libresoc.v:198084$14394
+ attribute \src "libresoc.v:195195.3-195196.45"
+ process $proc$libresoc.v:195195$14134
assign { } { }
assign $0\data_r2__fast2[63:0] \data_r2__fast2$next
sync posedge \coresync_clk
update \data_r2__fast2 $0\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:198086.3-198087.51"
- process $proc$libresoc.v:198086$14395
+ attribute \src "libresoc.v:195197.3-195198.51"
+ process $proc$libresoc.v:195197$14135
assign { } { }
assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next
sync posedge \coresync_clk
update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:198088.3-198089.45"
- process $proc$libresoc.v:198088$14396
+ attribute \src "libresoc.v:195199.3-195200.45"
+ process $proc$libresoc.v:195199$14136
assign { } { }
assign $0\data_r1__fast1[63:0] \data_r1__fast1$next
sync posedge \coresync_clk
update \data_r1__fast1 $0\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:198090.3-198091.51"
- process $proc$libresoc.v:198090$14397
+ attribute \src "libresoc.v:195201.3-195202.51"
+ process $proc$libresoc.v:195201$14137
assign { } { }
assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next
sync posedge \coresync_clk
update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:198092.3-198093.37"
- process $proc$libresoc.v:198092$14398
+ attribute \src "libresoc.v:195203.3-195204.37"
+ process $proc$libresoc.v:195203$14138
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:198094.3-198095.43"
- process $proc$libresoc.v:198094$14399
+ attribute \src "libresoc.v:195205.3-195206.43"
+ process $proc$libresoc.v:195205$14139
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:198096.3-198097.73"
- process $proc$libresoc.v:198096$14400
+ attribute \src "libresoc.v:195207.3-195208.73"
+ process $proc$libresoc.v:195207$14140
assign { } { }
assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:198098.3-198099.69"
- process $proc$libresoc.v:198098$14401
+ attribute \src "libresoc.v:195209.3-195210.69"
+ process $proc$libresoc.v:195209$14141
assign { } { }
assign $0\alu_trap0_trap_op__fn_unit[12:0] \alu_trap0_trap_op__fn_unit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[12:0]
end
- attribute \src "libresoc.v:198100.3-198101.63"
- process $proc$libresoc.v:198100$14402
+ attribute \src "libresoc.v:195211.3-195212.63"
+ process $proc$libresoc.v:195211$14142
assign { } { }
assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:198102.3-198103.61"
- process $proc$libresoc.v:198102$14403
+ attribute \src "libresoc.v:195213.3-195214.61"
+ process $proc$libresoc.v:195213$14143
assign { } { }
assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:198104.3-198105.61"
- process $proc$libresoc.v:198104$14404
+ attribute \src "libresoc.v:195215.3-195216.61"
+ process $proc$libresoc.v:195215$14144
assign { } { }
assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:198106.3-198107.71"
- process $proc$libresoc.v:198106$14405
+ attribute \src "libresoc.v:195217.3-195218.71"
+ process $proc$libresoc.v:195217$14145
assign { } { }
assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:198108.3-198109.71"
- process $proc$libresoc.v:198108$14406
+ attribute \src "libresoc.v:195219.3-195220.71"
+ process $proc$libresoc.v:195219$14146
assign { } { }
assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:198110.3-198111.71"
- process $proc$libresoc.v:198110$14407
+ attribute \src "libresoc.v:195221.3-195222.71"
+ process $proc$libresoc.v:195221$14147
assign { } { }
assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:198112.3-198113.71"
- process $proc$libresoc.v:198112$14408
+ attribute \src "libresoc.v:195223.3-195224.71"
+ process $proc$libresoc.v:195223$14148
assign { } { }
assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:198114.3-198115.39"
- process $proc$libresoc.v:198114$14409
+ attribute \src "libresoc.v:195225.3-195226.39"
+ process $proc$libresoc.v:195225$14149
assign { } { }
assign $0\req_l_r_req[4:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:198116.3-198117.39"
- process $proc$libresoc.v:198116$14410
+ attribute \src "libresoc.v:195227.3-195228.39"
+ process $proc$libresoc.v:195227$14150
assign { } { }
assign $0\req_l_s_req[4:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:198118.3-198119.39"
- process $proc$libresoc.v:198118$14411
+ attribute \src "libresoc.v:195229.3-195230.39"
+ process $proc$libresoc.v:195229$14151
assign { } { }
assign $0\src_l_r_src[3:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:198120.3-198121.39"
- process $proc$libresoc.v:198120$14412
+ attribute \src "libresoc.v:195231.3-195232.39"
+ process $proc$libresoc.v:195231$14152
assign { } { }
assign $0\src_l_s_src[3:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:198122.3-198123.39"
- process $proc$libresoc.v:198122$14413
+ attribute \src "libresoc.v:195233.3-195234.39"
+ process $proc$libresoc.v:195233$14153
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:198124.3-198125.39"
- process $proc$libresoc.v:198124$14414
+ attribute \src "libresoc.v:195235.3-195236.39"
+ process $proc$libresoc.v:195235$14154
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:198126.3-198127.39"
- process $proc$libresoc.v:198126$14415
+ attribute \src "libresoc.v:195237.3-195238.39"
+ process $proc$libresoc.v:195237$14155
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:198128.3-198129.39"
- process $proc$libresoc.v:198128$14416
+ attribute \src "libresoc.v:195239.3-195240.39"
+ process $proc$libresoc.v:195239$14156
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:198130.3-198131.41"
- process $proc$libresoc.v:198130$14417
+ attribute \src "libresoc.v:195241.3-195242.41"
+ process $proc$libresoc.v:195241$14157
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:198132.3-198133.41"
- process $proc$libresoc.v:198132$14418
+ attribute \src "libresoc.v:195243.3-195244.41"
+ process $proc$libresoc.v:195243$14158
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:198134.3-198135.37"
- process $proc$libresoc.v:198134$14419
+ attribute \src "libresoc.v:195245.3-195246.37"
+ process $proc$libresoc.v:195245$14159
assign { } { }
assign $0\prev_wr_go[4:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:198136.3-198137.41"
- process $proc$libresoc.v:198136$14420
+ attribute \src "libresoc.v:195247.3-195248.41"
+ process $proc$libresoc.v:195247$14160
assign { } { }
assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:198138.3-198139.25"
- process $proc$libresoc.v:198138$14421
+ attribute \src "libresoc.v:195249.3-195250.25"
+ process $proc$libresoc.v:195249$14161
assign { } { }
assign $0\all_rd_dly[0:0] \$11
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:198219.3-198228.6"
- process $proc$libresoc.v:198219$14422
+ attribute \src "libresoc.v:195330.3-195339.6"
+ process $proc$libresoc.v:195330$14162
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:198220.5-198220.29"
+ attribute \src "libresoc.v:195331.5-195331.29"
switch \initial
- attribute \src "libresoc.v:198220.9-198220.17"
+ attribute \src "libresoc.v:195331.9-195331.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:198229.3-198237.6"
- process $proc$libresoc.v:198229$14423
+ attribute \src "libresoc.v:195340.3-195348.6"
+ process $proc$libresoc.v:195340$14163
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$14424 $1\rok_l_s_rdok$next[0:0]$14425
- attribute \src "libresoc.v:198230.5-198230.29"
+ assign $0\rok_l_s_rdok$next[0:0]$14164 $1\rok_l_s_rdok$next[0:0]$14165
+ attribute \src "libresoc.v:195341.5-195341.29"
switch \initial
- attribute \src "libresoc.v:198230.9-198230.17"
+ attribute \src "libresoc.v:195341.9-195341.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$14425 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$14165 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$14425 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$14165 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14424
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14164
end
- attribute \src "libresoc.v:198238.3-198246.6"
- process $proc$libresoc.v:198238$14426
+ attribute \src "libresoc.v:195349.3-195357.6"
+ process $proc$libresoc.v:195349$14166
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$14427 $1\rok_l_r_rdok$next[0:0]$14428
- attribute \src "libresoc.v:198239.5-198239.29"
+ assign $0\rok_l_r_rdok$next[0:0]$14167 $1\rok_l_r_rdok$next[0:0]$14168
+ attribute \src "libresoc.v:195350.5-195350.29"
switch \initial
- attribute \src "libresoc.v:198239.9-198239.17"
+ attribute \src "libresoc.v:195350.9-195350.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$14428 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$14168 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$14428 \$65
+ assign $1\rok_l_r_rdok$next[0:0]$14168 \$65
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14427
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14167
end
- attribute \src "libresoc.v:198247.3-198255.6"
- process $proc$libresoc.v:198247$14429
+ attribute \src "libresoc.v:195358.3-195366.6"
+ process $proc$libresoc.v:195358$14169
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$14430 $1\rst_l_s_rst$next[0:0]$14431
- attribute \src "libresoc.v:198248.5-198248.29"
+ assign $0\rst_l_s_rst$next[0:0]$14170 $1\rst_l_s_rst$next[0:0]$14171
+ attribute \src "libresoc.v:195359.5-195359.29"
switch \initial
- attribute \src "libresoc.v:198248.9-198248.17"
+ attribute \src "libresoc.v:195359.9-195359.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$14431 1'0
+ assign $1\rst_l_s_rst$next[0:0]$14171 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$14431 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$14171 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14430
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14170
end
- attribute \src "libresoc.v:198256.3-198264.6"
- process $proc$libresoc.v:198256$14432
+ attribute \src "libresoc.v:195367.3-195375.6"
+ process $proc$libresoc.v:195367$14172
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$14433 $1\rst_l_r_rst$next[0:0]$14434
- attribute \src "libresoc.v:198257.5-198257.29"
+ assign $0\rst_l_r_rst$next[0:0]$14173 $1\rst_l_r_rst$next[0:0]$14174
+ attribute \src "libresoc.v:195368.5-195368.29"
switch \initial
- attribute \src "libresoc.v:198257.9-198257.17"
+ attribute \src "libresoc.v:195368.9-195368.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$14434 1'1
+ assign $1\rst_l_r_rst$next[0:0]$14174 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$14434 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$14174 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14433
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14173
end
- attribute \src "libresoc.v:198265.3-198273.6"
- process $proc$libresoc.v:198265$14435
+ attribute \src "libresoc.v:195376.3-195384.6"
+ process $proc$libresoc.v:195376$14175
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$14436 $1\opc_l_s_opc$next[0:0]$14437
- attribute \src "libresoc.v:198266.5-198266.29"
+ assign $0\opc_l_s_opc$next[0:0]$14176 $1\opc_l_s_opc$next[0:0]$14177
+ attribute \src "libresoc.v:195377.5-195377.29"
switch \initial
- attribute \src "libresoc.v:198266.9-198266.17"
+ attribute \src "libresoc.v:195377.9-195377.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$14437 1'0
+ assign $1\opc_l_s_opc$next[0:0]$14177 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$14437 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$14177 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14436
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14176
end
- attribute \src "libresoc.v:198274.3-198282.6"
- process $proc$libresoc.v:198274$14438
+ attribute \src "libresoc.v:195385.3-195393.6"
+ process $proc$libresoc.v:195385$14178
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$14439 $1\opc_l_r_opc$next[0:0]$14440
- attribute \src "libresoc.v:198275.5-198275.29"
+ assign $0\opc_l_r_opc$next[0:0]$14179 $1\opc_l_r_opc$next[0:0]$14180
+ attribute \src "libresoc.v:195386.5-195386.29"
switch \initial
- attribute \src "libresoc.v:198275.9-198275.17"
+ attribute \src "libresoc.v:195386.9-195386.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$14440 1'1
+ assign $1\opc_l_r_opc$next[0:0]$14180 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$14440 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$14180 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14439
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14179
end
- attribute \src "libresoc.v:198283.3-198291.6"
- process $proc$libresoc.v:198283$14441
+ attribute \src "libresoc.v:195394.3-195402.6"
+ process $proc$libresoc.v:195394$14181
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[3:0]$14442 $1\src_l_s_src$next[3:0]$14443
- attribute \src "libresoc.v:198284.5-198284.29"
+ assign $0\src_l_s_src$next[3:0]$14182 $1\src_l_s_src$next[3:0]$14183
+ attribute \src "libresoc.v:195395.5-195395.29"
switch \initial
- attribute \src "libresoc.v:198284.9-198284.17"
+ attribute \src "libresoc.v:195395.9-195395.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[3:0]$14443 4'0000
+ assign $1\src_l_s_src$next[3:0]$14183 4'0000
case
- assign $1\src_l_s_src$next[3:0]$14443 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[3:0]$14183 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14442
+ update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14182
end
- attribute \src "libresoc.v:198292.3-198300.6"
- process $proc$libresoc.v:198292$14444
+ attribute \src "libresoc.v:195403.3-195411.6"
+ process $proc$libresoc.v:195403$14184
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[3:0]$14445 $1\src_l_r_src$next[3:0]$14446
- attribute \src "libresoc.v:198293.5-198293.29"
+ assign $0\src_l_r_src$next[3:0]$14185 $1\src_l_r_src$next[3:0]$14186
+ attribute \src "libresoc.v:195404.5-195404.29"
switch \initial
- attribute \src "libresoc.v:198293.9-198293.17"
+ attribute \src "libresoc.v:195404.9-195404.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[3:0]$14446 4'1111
+ assign $1\src_l_r_src$next[3:0]$14186 4'1111
case
- assign $1\src_l_r_src$next[3:0]$14446 \reset_r
+ assign $1\src_l_r_src$next[3:0]$14186 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14445
+ update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14185
end
- attribute \src "libresoc.v:198301.3-198309.6"
- process $proc$libresoc.v:198301$14447
+ attribute \src "libresoc.v:195412.3-195420.6"
+ process $proc$libresoc.v:195412$14187
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[4:0]$14448 $1\req_l_s_req$next[4:0]$14449
- attribute \src "libresoc.v:198302.5-198302.29"
+ assign $0\req_l_s_req$next[4:0]$14188 $1\req_l_s_req$next[4:0]$14189
+ attribute \src "libresoc.v:195413.5-195413.29"
switch \initial
- attribute \src "libresoc.v:198302.9-198302.17"
+ attribute \src "libresoc.v:195413.9-195413.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[4:0]$14449 5'00000
+ assign $1\req_l_s_req$next[4:0]$14189 5'00000
case
- assign $1\req_l_s_req$next[4:0]$14449 \$67
+ assign $1\req_l_s_req$next[4:0]$14189 \$67
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14448
+ update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14188
end
- attribute \src "libresoc.v:198310.3-198318.6"
- process $proc$libresoc.v:198310$14450
+ attribute \src "libresoc.v:195421.3-195429.6"
+ process $proc$libresoc.v:195421$14190
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[4:0]$14451 $1\req_l_r_req$next[4:0]$14452
- attribute \src "libresoc.v:198311.5-198311.29"
+ assign $0\req_l_r_req$next[4:0]$14191 $1\req_l_r_req$next[4:0]$14192
+ attribute \src "libresoc.v:195422.5-195422.29"
switch \initial
- attribute \src "libresoc.v:198311.9-198311.17"
+ attribute \src "libresoc.v:195422.9-195422.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[4:0]$14452 5'11111
+ assign $1\req_l_r_req$next[4:0]$14192 5'11111
case
- assign $1\req_l_r_req$next[4:0]$14452 \$69
+ assign $1\req_l_r_req$next[4:0]$14192 \$69
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14451
+ update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14191
end
- attribute \src "libresoc.v:198319.3-198336.6"
- process $proc$libresoc.v:198319$14453
+ attribute \src "libresoc.v:195430.3-195447.6"
+ process $proc$libresoc.v:195430$14193
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_trap0_trap_op__cia$next[63:0]$14454 $1\alu_trap0_trap_op__cia$next[63:0]$14463
- assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464
- assign $0\alu_trap0_trap_op__insn$next[31:0]$14456 $1\alu_trap0_trap_op__insn$next[31:0]$14465
- assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14457 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466
- assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467
- assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468
- assign $0\alu_trap0_trap_op__msr$next[63:0]$14460 $1\alu_trap0_trap_op__msr$next[63:0]$14469
- assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470
- assign $0\alu_trap0_trap_op__traptype$next[7:0]$14462 $1\alu_trap0_trap_op__traptype$next[7:0]$14471
- attribute \src "libresoc.v:198320.5-198320.29"
+ assign $0\alu_trap0_trap_op__cia$next[63:0]$14194 $1\alu_trap0_trap_op__cia$next[63:0]$14203
+ assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204
+ assign $0\alu_trap0_trap_op__insn$next[31:0]$14196 $1\alu_trap0_trap_op__insn$next[31:0]$14205
+ assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14197 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206
+ assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207
+ assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208
+ assign $0\alu_trap0_trap_op__msr$next[63:0]$14200 $1\alu_trap0_trap_op__msr$next[63:0]$14209
+ assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210
+ assign $0\alu_trap0_trap_op__traptype$next[7:0]$14202 $1\alu_trap0_trap_op__traptype$next[7:0]$14211
+ attribute \src "libresoc.v:195431.5-195431.29"
switch \initial
- attribute \src "libresoc.v:198320.9-198320.17"
+ attribute \src "libresoc.v:195431.9-195431.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 $1\alu_trap0_trap_op__traptype$next[7:0]$14471 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 $1\alu_trap0_trap_op__cia$next[63:0]$14463 $1\alu_trap0_trap_op__msr$next[63:0]$14469 $1\alu_trap0_trap_op__insn$next[31:0]$14465 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
+ assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 $1\alu_trap0_trap_op__traptype$next[7:0]$14211 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 $1\alu_trap0_trap_op__cia$next[63:0]$14203 $1\alu_trap0_trap_op__msr$next[63:0]$14209 $1\alu_trap0_trap_op__insn$next[31:0]$14205 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
case
- assign $1\alu_trap0_trap_op__cia$next[63:0]$14463 \alu_trap0_trap_op__cia
- assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 \alu_trap0_trap_op__fn_unit
- assign $1\alu_trap0_trap_op__insn$next[31:0]$14465 \alu_trap0_trap_op__insn
- assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 \alu_trap0_trap_op__insn_type
- assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 \alu_trap0_trap_op__is_32bit
- assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 \alu_trap0_trap_op__ldst_exc
- assign $1\alu_trap0_trap_op__msr$next[63:0]$14469 \alu_trap0_trap_op__msr
- assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 \alu_trap0_trap_op__trapaddr
- assign $1\alu_trap0_trap_op__traptype$next[7:0]$14471 \alu_trap0_trap_op__traptype
+ assign $1\alu_trap0_trap_op__cia$next[63:0]$14203 \alu_trap0_trap_op__cia
+ assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 \alu_trap0_trap_op__fn_unit
+ assign $1\alu_trap0_trap_op__insn$next[31:0]$14205 \alu_trap0_trap_op__insn
+ assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 \alu_trap0_trap_op__insn_type
+ assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 \alu_trap0_trap_op__is_32bit
+ assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 \alu_trap0_trap_op__ldst_exc
+ assign $1\alu_trap0_trap_op__msr$next[63:0]$14209 \alu_trap0_trap_op__msr
+ assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 \alu_trap0_trap_op__trapaddr
+ assign $1\alu_trap0_trap_op__traptype$next[7:0]$14211 \alu_trap0_trap_op__traptype
end
sync always
- update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14454
- update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455
- update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14456
- update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14457
- update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458
- update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459
- update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14460
- update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461
- update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14462
+ update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14194
+ update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195
+ update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14196
+ update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14197
+ update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198
+ update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199
+ update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14200
+ update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201
+ update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14202
end
- attribute \src "libresoc.v:198337.3-198358.6"
- process $proc$libresoc.v:198337$14472
+ attribute \src "libresoc.v:195448.3-195469.6"
+ process $proc$libresoc.v:195448$14212
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$14473 $2\data_r0__o$next[63:0]$14477
+ assign $0\data_r0__o$next[63:0]$14213 $2\data_r0__o$next[63:0]$14217
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$14474 $3\data_r0__o_ok$next[0:0]$14479
- attribute \src "libresoc.v:198338.5-198338.29"
+ assign $0\data_r0__o_ok$next[0:0]$14214 $3\data_r0__o_ok$next[0:0]$14219
+ attribute \src "libresoc.v:195449.5-195449.29"
switch \initial
- attribute \src "libresoc.v:198338.9-198338.17"
+ attribute \src "libresoc.v:195449.9-195449.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$14476 $1\data_r0__o$next[63:0]$14475 } { \o_ok \alu_trap0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$14216 $1\data_r0__o$next[63:0]$14215 } { \o_ok \alu_trap0_o }
case
- assign $1\data_r0__o$next[63:0]$14475 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$14476 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$14215 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$14216 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$14478 $2\data_r0__o$next[63:0]$14477 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$14218 $2\data_r0__o$next[63:0]$14217 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$14477 $1\data_r0__o$next[63:0]$14475
- assign $2\data_r0__o_ok$next[0:0]$14478 $1\data_r0__o_ok$next[0:0]$14476
+ assign $2\data_r0__o$next[63:0]$14217 $1\data_r0__o$next[63:0]$14215
+ assign $2\data_r0__o_ok$next[0:0]$14218 $1\data_r0__o_ok$next[0:0]$14216
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$14479 1'0
+ assign $3\data_r0__o_ok$next[0:0]$14219 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$14479 $2\data_r0__o_ok$next[0:0]$14478
+ assign $3\data_r0__o_ok$next[0:0]$14219 $2\data_r0__o_ok$next[0:0]$14218
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$14473
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14474
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$14213
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14214
end
- attribute \src "libresoc.v:198359.3-198380.6"
- process $proc$libresoc.v:198359$14480
+ attribute \src "libresoc.v:195470.3-195491.6"
+ process $proc$libresoc.v:195470$14220
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__fast1$next[63:0]$14481 $2\data_r1__fast1$next[63:0]$14485
+ assign $0\data_r1__fast1$next[63:0]$14221 $2\data_r1__fast1$next[63:0]$14225
assign { } { }
- assign $0\data_r1__fast1_ok$next[0:0]$14482 $3\data_r1__fast1_ok$next[0:0]$14487
- attribute \src "libresoc.v:198360.5-198360.29"
+ assign $0\data_r1__fast1_ok$next[0:0]$14222 $3\data_r1__fast1_ok$next[0:0]$14227
+ attribute \src "libresoc.v:195471.5-195471.29"
switch \initial
- attribute \src "libresoc.v:198360.9-198360.17"
+ attribute \src "libresoc.v:195471.9-195471.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__fast1_ok$next[0:0]$14484 $1\data_r1__fast1$next[63:0]$14483 } { \fast1_ok \alu_trap0_fast1 }
+ assign { $1\data_r1__fast1_ok$next[0:0]$14224 $1\data_r1__fast1$next[63:0]$14223 } { \fast1_ok \alu_trap0_fast1 }
case
- assign $1\data_r1__fast1$next[63:0]$14483 \data_r1__fast1
- assign $1\data_r1__fast1_ok$next[0:0]$14484 \data_r1__fast1_ok
+ assign $1\data_r1__fast1$next[63:0]$14223 \data_r1__fast1
+ assign $1\data_r1__fast1_ok$next[0:0]$14224 \data_r1__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__fast1_ok$next[0:0]$14486 $2\data_r1__fast1$next[63:0]$14485 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__fast1_ok$next[0:0]$14226 $2\data_r1__fast1$next[63:0]$14225 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__fast1$next[63:0]$14485 $1\data_r1__fast1$next[63:0]$14483
- assign $2\data_r1__fast1_ok$next[0:0]$14486 $1\data_r1__fast1_ok$next[0:0]$14484
+ assign $2\data_r1__fast1$next[63:0]$14225 $1\data_r1__fast1$next[63:0]$14223
+ assign $2\data_r1__fast1_ok$next[0:0]$14226 $1\data_r1__fast1_ok$next[0:0]$14224
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__fast1_ok$next[0:0]$14487 1'0
+ assign $3\data_r1__fast1_ok$next[0:0]$14227 1'0
case
- assign $3\data_r1__fast1_ok$next[0:0]$14487 $2\data_r1__fast1_ok$next[0:0]$14486
+ assign $3\data_r1__fast1_ok$next[0:0]$14227 $2\data_r1__fast1_ok$next[0:0]$14226
end
sync always
- update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14481
- update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14482
+ update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14221
+ update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14222
end
- attribute \src "libresoc.v:198381.3-198402.6"
- process $proc$libresoc.v:198381$14488
+ attribute \src "libresoc.v:195492.3-195513.6"
+ process $proc$libresoc.v:195492$14228
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast2$next[63:0]$14489 $2\data_r2__fast2$next[63:0]$14493
+ assign $0\data_r2__fast2$next[63:0]$14229 $2\data_r2__fast2$next[63:0]$14233
assign { } { }
- assign $0\data_r2__fast2_ok$next[0:0]$14490 $3\data_r2__fast2_ok$next[0:0]$14495
- attribute \src "libresoc.v:198382.5-198382.29"
+ assign $0\data_r2__fast2_ok$next[0:0]$14230 $3\data_r2__fast2_ok$next[0:0]$14235
+ attribute \src "libresoc.v:195493.5-195493.29"
switch \initial
- attribute \src "libresoc.v:198382.9-198382.17"
+ attribute \src "libresoc.v:195493.9-195493.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast2_ok$next[0:0]$14492 $1\data_r2__fast2$next[63:0]$14491 } { \fast2_ok \alu_trap0_fast2 }
+ assign { $1\data_r2__fast2_ok$next[0:0]$14232 $1\data_r2__fast2$next[63:0]$14231 } { \fast2_ok \alu_trap0_fast2 }
case
- assign $1\data_r2__fast2$next[63:0]$14491 \data_r2__fast2
- assign $1\data_r2__fast2_ok$next[0:0]$14492 \data_r2__fast2_ok
+ assign $1\data_r2__fast2$next[63:0]$14231 \data_r2__fast2
+ assign $1\data_r2__fast2_ok$next[0:0]$14232 \data_r2__fast2_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast2_ok$next[0:0]$14494 $2\data_r2__fast2$next[63:0]$14493 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast2_ok$next[0:0]$14234 $2\data_r2__fast2$next[63:0]$14233 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast2$next[63:0]$14493 $1\data_r2__fast2$next[63:0]$14491
- assign $2\data_r2__fast2_ok$next[0:0]$14494 $1\data_r2__fast2_ok$next[0:0]$14492
+ assign $2\data_r2__fast2$next[63:0]$14233 $1\data_r2__fast2$next[63:0]$14231
+ assign $2\data_r2__fast2_ok$next[0:0]$14234 $1\data_r2__fast2_ok$next[0:0]$14232
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast2_ok$next[0:0]$14495 1'0
+ assign $3\data_r2__fast2_ok$next[0:0]$14235 1'0
case
- assign $3\data_r2__fast2_ok$next[0:0]$14495 $2\data_r2__fast2_ok$next[0:0]$14494
+ assign $3\data_r2__fast2_ok$next[0:0]$14235 $2\data_r2__fast2_ok$next[0:0]$14234
end
sync always
- update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14489
- update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14490
+ update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14229
+ update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14230
end
- attribute \src "libresoc.v:198403.3-198424.6"
- process $proc$libresoc.v:198403$14496
+ attribute \src "libresoc.v:195514.3-195535.6"
+ process $proc$libresoc.v:195514$14236
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__nia$next[63:0]$14497 $2\data_r3__nia$next[63:0]$14501
+ assign $0\data_r3__nia$next[63:0]$14237 $2\data_r3__nia$next[63:0]$14241
assign { } { }
- assign $0\data_r3__nia_ok$next[0:0]$14498 $3\data_r3__nia_ok$next[0:0]$14503
- attribute \src "libresoc.v:198404.5-198404.29"
+ assign $0\data_r3__nia_ok$next[0:0]$14238 $3\data_r3__nia_ok$next[0:0]$14243
+ attribute \src "libresoc.v:195515.5-195515.29"
switch \initial
- attribute \src "libresoc.v:198404.9-198404.17"
+ attribute \src "libresoc.v:195515.9-195515.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__nia_ok$next[0:0]$14500 $1\data_r3__nia$next[63:0]$14499 } { \nia_ok \alu_trap0_nia }
+ assign { $1\data_r3__nia_ok$next[0:0]$14240 $1\data_r3__nia$next[63:0]$14239 } { \nia_ok \alu_trap0_nia }
case
- assign $1\data_r3__nia$next[63:0]$14499 \data_r3__nia
- assign $1\data_r3__nia_ok$next[0:0]$14500 \data_r3__nia_ok
+ assign $1\data_r3__nia$next[63:0]$14239 \data_r3__nia
+ assign $1\data_r3__nia_ok$next[0:0]$14240 \data_r3__nia_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__nia_ok$next[0:0]$14502 $2\data_r3__nia$next[63:0]$14501 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r3__nia_ok$next[0:0]$14242 $2\data_r3__nia$next[63:0]$14241 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r3__nia$next[63:0]$14501 $1\data_r3__nia$next[63:0]$14499
- assign $2\data_r3__nia_ok$next[0:0]$14502 $1\data_r3__nia_ok$next[0:0]$14500
+ assign $2\data_r3__nia$next[63:0]$14241 $1\data_r3__nia$next[63:0]$14239
+ assign $2\data_r3__nia_ok$next[0:0]$14242 $1\data_r3__nia_ok$next[0:0]$14240
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__nia_ok$next[0:0]$14503 1'0
+ assign $3\data_r3__nia_ok$next[0:0]$14243 1'0
case
- assign $3\data_r3__nia_ok$next[0:0]$14503 $2\data_r3__nia_ok$next[0:0]$14502
+ assign $3\data_r3__nia_ok$next[0:0]$14243 $2\data_r3__nia_ok$next[0:0]$14242
end
sync always
- update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14497
- update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14498
+ update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14237
+ update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14238
end
- attribute \src "libresoc.v:198425.3-198446.6"
- process $proc$libresoc.v:198425$14504
+ attribute \src "libresoc.v:195536.3-195557.6"
+ process $proc$libresoc.v:195536$14244
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__msr$next[63:0]$14505 $2\data_r4__msr$next[63:0]$14509
+ assign $0\data_r4__msr$next[63:0]$14245 $2\data_r4__msr$next[63:0]$14249
assign { } { }
- assign $0\data_r4__msr_ok$next[0:0]$14506 $3\data_r4__msr_ok$next[0:0]$14511
- attribute \src "libresoc.v:198426.5-198426.29"
+ assign $0\data_r4__msr_ok$next[0:0]$14246 $3\data_r4__msr_ok$next[0:0]$14251
+ attribute \src "libresoc.v:195537.5-195537.29"
switch \initial
- attribute \src "libresoc.v:198426.9-198426.17"
+ attribute \src "libresoc.v:195537.9-195537.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__msr_ok$next[0:0]$14508 $1\data_r4__msr$next[63:0]$14507 } { \msr_ok \alu_trap0_msr }
+ assign { $1\data_r4__msr_ok$next[0:0]$14248 $1\data_r4__msr$next[63:0]$14247 } { \msr_ok \alu_trap0_msr }
case
- assign $1\data_r4__msr$next[63:0]$14507 \data_r4__msr
- assign $1\data_r4__msr_ok$next[0:0]$14508 \data_r4__msr_ok
+ assign $1\data_r4__msr$next[63:0]$14247 \data_r4__msr
+ assign $1\data_r4__msr_ok$next[0:0]$14248 \data_r4__msr_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__msr_ok$next[0:0]$14510 $2\data_r4__msr$next[63:0]$14509 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r4__msr_ok$next[0:0]$14250 $2\data_r4__msr$next[63:0]$14249 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r4__msr$next[63:0]$14509 $1\data_r4__msr$next[63:0]$14507
- assign $2\data_r4__msr_ok$next[0:0]$14510 $1\data_r4__msr_ok$next[0:0]$14508
+ assign $2\data_r4__msr$next[63:0]$14249 $1\data_r4__msr$next[63:0]$14247
+ assign $2\data_r4__msr_ok$next[0:0]$14250 $1\data_r4__msr_ok$next[0:0]$14248
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__msr_ok$next[0:0]$14511 1'0
+ assign $3\data_r4__msr_ok$next[0:0]$14251 1'0
case
- assign $3\data_r4__msr_ok$next[0:0]$14511 $2\data_r4__msr_ok$next[0:0]$14510
+ assign $3\data_r4__msr_ok$next[0:0]$14251 $2\data_r4__msr_ok$next[0:0]$14250
end
sync always
- update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14505
- update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14506
+ update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14245
+ update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14246
end
- attribute \src "libresoc.v:198447.3-198456.6"
- process $proc$libresoc.v:198447$14512
+ attribute \src "libresoc.v:195558.3-195567.6"
+ process $proc$libresoc.v:195558$14252
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$14513 $1\src_r0$next[63:0]$14514
- attribute \src "libresoc.v:198448.5-198448.29"
+ assign $0\src_r0$next[63:0]$14253 $1\src_r0$next[63:0]$14254
+ attribute \src "libresoc.v:195559.5-195559.29"
switch \initial
- attribute \src "libresoc.v:198448.9-198448.17"
+ attribute \src "libresoc.v:195559.9-195559.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$14514 \src1_i
+ assign $1\src_r0$next[63:0]$14254 \src1_i
case
- assign $1\src_r0$next[63:0]$14514 \src_r0
+ assign $1\src_r0$next[63:0]$14254 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$14513
+ update \src_r0$next $0\src_r0$next[63:0]$14253
end
- attribute \src "libresoc.v:198457.3-198466.6"
- process $proc$libresoc.v:198457$14515
+ attribute \src "libresoc.v:195568.3-195577.6"
+ process $proc$libresoc.v:195568$14255
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$14516 $1\src_r1$next[63:0]$14517
- attribute \src "libresoc.v:198458.5-198458.29"
+ assign $0\src_r1$next[63:0]$14256 $1\src_r1$next[63:0]$14257
+ attribute \src "libresoc.v:195569.5-195569.29"
switch \initial
- attribute \src "libresoc.v:198458.9-198458.17"
+ attribute \src "libresoc.v:195569.9-195569.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$14517 \src2_i
+ assign $1\src_r1$next[63:0]$14257 \src2_i
case
- assign $1\src_r1$next[63:0]$14517 \src_r1
+ assign $1\src_r1$next[63:0]$14257 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$14516
+ update \src_r1$next $0\src_r1$next[63:0]$14256
end
- attribute \src "libresoc.v:198467.3-198476.6"
- process $proc$libresoc.v:198467$14518
+ attribute \src "libresoc.v:195578.3-195587.6"
+ process $proc$libresoc.v:195578$14258
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$14519 $1\src_r2$next[63:0]$14520
- attribute \src "libresoc.v:198468.5-198468.29"
+ assign $0\src_r2$next[63:0]$14259 $1\src_r2$next[63:0]$14260
+ attribute \src "libresoc.v:195579.5-195579.29"
switch \initial
- attribute \src "libresoc.v:198468.9-198468.17"
+ attribute \src "libresoc.v:195579.9-195579.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$14520 \src3_i
+ assign $1\src_r2$next[63:0]$14260 \src3_i
case
- assign $1\src_r2$next[63:0]$14520 \src_r2
+ assign $1\src_r2$next[63:0]$14260 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$14519
+ update \src_r2$next $0\src_r2$next[63:0]$14259
end
- attribute \src "libresoc.v:198477.3-198486.6"
- process $proc$libresoc.v:198477$14521
+ attribute \src "libresoc.v:195588.3-195597.6"
+ process $proc$libresoc.v:195588$14261
assign { } { }
assign { } { }
- assign $0\src_r3$next[63:0]$14522 $1\src_r3$next[63:0]$14523
- attribute \src "libresoc.v:198478.5-198478.29"
+ assign $0\src_r3$next[63:0]$14262 $1\src_r3$next[63:0]$14263
+ attribute \src "libresoc.v:195589.5-195589.29"
switch \initial
- attribute \src "libresoc.v:198478.9-198478.17"
+ attribute \src "libresoc.v:195589.9-195589.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[63:0]$14523 \src4_i
+ assign $1\src_r3$next[63:0]$14263 \src4_i
case
- assign $1\src_r3$next[63:0]$14523 \src_r3
+ assign $1\src_r3$next[63:0]$14263 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[63:0]$14522
+ update \src_r3$next $0\src_r3$next[63:0]$14262
end
- attribute \src "libresoc.v:198487.3-198495.6"
- process $proc$libresoc.v:198487$14524
+ attribute \src "libresoc.v:195598.3-195606.6"
+ process $proc$libresoc.v:195598$14264
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$14525 $1\alui_l_r_alui$next[0:0]$14526
- attribute \src "libresoc.v:198488.5-198488.29"
+ assign $0\alui_l_r_alui$next[0:0]$14265 $1\alui_l_r_alui$next[0:0]$14266
+ attribute \src "libresoc.v:195599.5-195599.29"
switch \initial
- attribute \src "libresoc.v:198488.9-198488.17"
+ attribute \src "libresoc.v:195599.9-195599.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$14526 1'1
+ assign $1\alui_l_r_alui$next[0:0]$14266 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$14526 \$89
+ assign $1\alui_l_r_alui$next[0:0]$14266 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14525
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14265
end
- attribute \src "libresoc.v:198496.3-198504.6"
- process $proc$libresoc.v:198496$14527
+ attribute \src "libresoc.v:195607.3-195615.6"
+ process $proc$libresoc.v:195607$14267
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$14528 $1\alu_l_r_alu$next[0:0]$14529
- attribute \src "libresoc.v:198497.5-198497.29"
+ assign $0\alu_l_r_alu$next[0:0]$14268 $1\alu_l_r_alu$next[0:0]$14269
+ attribute \src "libresoc.v:195608.5-195608.29"
switch \initial
- attribute \src "libresoc.v:198497.9-198497.17"
+ attribute \src "libresoc.v:195608.9-195608.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$14529 1'1
+ assign $1\alu_l_r_alu$next[0:0]$14269 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$14529 \$91
+ assign $1\alu_l_r_alu$next[0:0]$14269 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14528
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14268
end
- attribute \src "libresoc.v:198505.3-198514.6"
- process $proc$libresoc.v:198505$14530
+ attribute \src "libresoc.v:195616.3-195625.6"
+ process $proc$libresoc.v:195616$14270
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:198506.5-198506.29"
+ attribute \src "libresoc.v:195617.5-195617.29"
switch \initial
- attribute \src "libresoc.v:198506.9-198506.17"
+ attribute \src "libresoc.v:195617.9-195617.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:198515.3-198524.6"
- process $proc$libresoc.v:198515$14531
+ attribute \src "libresoc.v:195626.3-195635.6"
+ process $proc$libresoc.v:195626$14271
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:198516.5-198516.29"
+ attribute \src "libresoc.v:195627.5-195627.29"
switch \initial
- attribute \src "libresoc.v:198516.9-198516.17"
+ attribute \src "libresoc.v:195627.9-195627.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:198525.3-198534.6"
- process $proc$libresoc.v:198525$14532
+ attribute \src "libresoc.v:195636.3-195645.6"
+ process $proc$libresoc.v:195636$14272
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:198526.5-198526.29"
+ attribute \src "libresoc.v:195637.5-195637.29"
switch \initial
- attribute \src "libresoc.v:198526.9-198526.17"
+ attribute \src "libresoc.v:195637.9-195637.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:198535.3-198544.6"
- process $proc$libresoc.v:198535$14533
+ attribute \src "libresoc.v:195646.3-195655.6"
+ process $proc$libresoc.v:195646$14273
assign { } { }
assign { } { }
assign $0\dest4_o[63:0] $1\dest4_o[63:0]
- attribute \src "libresoc.v:198536.5-198536.29"
+ attribute \src "libresoc.v:195647.5-195647.29"
switch \initial
- attribute \src "libresoc.v:198536.9-198536.17"
+ attribute \src "libresoc.v:195647.9-195647.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[63:0]
end
- attribute \src "libresoc.v:198545.3-198554.6"
- process $proc$libresoc.v:198545$14534
+ attribute \src "libresoc.v:195656.3-195665.6"
+ process $proc$libresoc.v:195656$14274
assign { } { }
assign { } { }
assign $0\dest5_o[63:0] $1\dest5_o[63:0]
- attribute \src "libresoc.v:198546.5-198546.29"
+ attribute \src "libresoc.v:195657.5-195657.29"
switch \initial
- attribute \src "libresoc.v:198546.9-198546.17"
+ attribute \src "libresoc.v:195657.9-195657.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[63:0]
end
- attribute \src "libresoc.v:198555.3-198563.6"
- process $proc$libresoc.v:198555$14535
+ attribute \src "libresoc.v:195666.3-195674.6"
+ process $proc$libresoc.v:195666$14275
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[4:0]$14536 $1\prev_wr_go$next[4:0]$14537
- attribute \src "libresoc.v:198556.5-198556.29"
+ assign $0\prev_wr_go$next[4:0]$14276 $1\prev_wr_go$next[4:0]$14277
+ attribute \src "libresoc.v:195667.5-195667.29"
switch \initial
- attribute \src "libresoc.v:198556.9-198556.17"
+ attribute \src "libresoc.v:195667.9-195667.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[4:0]$14537 5'00000
- case
- assign $1\prev_wr_go$next[4:0]$14537 \$21
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14536
- end
- connect \$5 $reduce_and$libresoc.v:198003$14323_Y
- connect \$99 $and$libresoc.v:198004$14324_Y
- connect \$101 $and$libresoc.v:198005$14325_Y
- connect \$103 $and$libresoc.v:198006$14326_Y
- connect \$105 $and$libresoc.v:198007$14327_Y
- connect \$107 $and$libresoc.v:198008$14328_Y
- connect \$109 $and$libresoc.v:198009$14329_Y
- connect \$111 $and$libresoc.v:198010$14330_Y
- connect \$113 $and$libresoc.v:198011$14331_Y
- connect \$115 $and$libresoc.v:198012$14332_Y
- connect \$117 $and$libresoc.v:198013$14333_Y
- connect \$11 $and$libresoc.v:198014$14334_Y
- connect \$119 $and$libresoc.v:198015$14335_Y
- connect \$121 $and$libresoc.v:198016$14336_Y
- connect \$123 $and$libresoc.v:198017$14337_Y
- connect \$13 $not$libresoc.v:198018$14338_Y
- connect \$15 $and$libresoc.v:198019$14339_Y
- connect \$17 $not$libresoc.v:198020$14340_Y
- connect \$19 $and$libresoc.v:198021$14341_Y
- connect \$21 $and$libresoc.v:198022$14342_Y
- connect \$25 $not$libresoc.v:198023$14343_Y
- connect \$27 $and$libresoc.v:198024$14344_Y
- connect \$24 $reduce_or$libresoc.v:198025$14345_Y
- connect \$23 $not$libresoc.v:198026$14346_Y
- connect \$31 $and$libresoc.v:198027$14347_Y
- connect \$33 $reduce_or$libresoc.v:198028$14348_Y
- connect \$35 $reduce_or$libresoc.v:198029$14349_Y
- connect \$37 $or$libresoc.v:198030$14350_Y
- connect \$3 $and$libresoc.v:198031$14351_Y
- connect \$39 $not$libresoc.v:198032$14352_Y
- connect \$41 $and$libresoc.v:198033$14353_Y
- connect \$43 $and$libresoc.v:198034$14354_Y
- connect \$45 $eq$libresoc.v:198035$14355_Y
- connect \$47 $and$libresoc.v:198036$14356_Y
- connect \$49 $eq$libresoc.v:198037$14357_Y
- connect \$51 $and$libresoc.v:198038$14358_Y
- connect \$53 $and$libresoc.v:198039$14359_Y
- connect \$55 $and$libresoc.v:198040$14360_Y
- connect \$57 $or$libresoc.v:198041$14361_Y
- connect \$59 $or$libresoc.v:198042$14362_Y
- connect \$61 $or$libresoc.v:198043$14363_Y
- connect \$63 $or$libresoc.v:198044$14364_Y
- connect \$65 $and$libresoc.v:198045$14365_Y
- connect \$67 $and$libresoc.v:198046$14366_Y
- connect \$6 $not$libresoc.v:198047$14367_Y
- connect \$69 $or$libresoc.v:198048$14368_Y
- connect \$71 $and$libresoc.v:198049$14369_Y
- connect \$73 $and$libresoc.v:198050$14370_Y
- connect \$75 $and$libresoc.v:198051$14371_Y
- connect \$77 $and$libresoc.v:198052$14372_Y
- connect \$79 $and$libresoc.v:198053$14373_Y
- connect \$81 $ternary$libresoc.v:198054$14374_Y
- connect \$83 $ternary$libresoc.v:198055$14375_Y
- connect \$85 $ternary$libresoc.v:198056$14376_Y
- connect \$87 $ternary$libresoc.v:198057$14377_Y
- connect \$8 $or$libresoc.v:198058$14378_Y
- connect \$89 $and$libresoc.v:198059$14379_Y
- connect \$91 $and$libresoc.v:198060$14380_Y
- connect \$93 $and$libresoc.v:198061$14381_Y
- connect \$95 $and$libresoc.v:198062$14382_Y
- connect \$97 $not$libresoc.v:198063$14383_Y
+ assign $1\prev_wr_go$next[4:0]$14277 5'00000
+ case
+ assign $1\prev_wr_go$next[4:0]$14277 \$21
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14276
+ end
+ connect \$5 $reduce_and$libresoc.v:195114$14063_Y
+ connect \$99 $and$libresoc.v:195115$14064_Y
+ connect \$101 $and$libresoc.v:195116$14065_Y
+ connect \$103 $and$libresoc.v:195117$14066_Y
+ connect \$105 $and$libresoc.v:195118$14067_Y
+ connect \$107 $and$libresoc.v:195119$14068_Y
+ connect \$109 $and$libresoc.v:195120$14069_Y
+ connect \$111 $and$libresoc.v:195121$14070_Y
+ connect \$113 $and$libresoc.v:195122$14071_Y
+ connect \$115 $and$libresoc.v:195123$14072_Y
+ connect \$117 $and$libresoc.v:195124$14073_Y
+ connect \$11 $and$libresoc.v:195125$14074_Y
+ connect \$119 $and$libresoc.v:195126$14075_Y
+ connect \$121 $and$libresoc.v:195127$14076_Y
+ connect \$123 $and$libresoc.v:195128$14077_Y
+ connect \$13 $not$libresoc.v:195129$14078_Y
+ connect \$15 $and$libresoc.v:195130$14079_Y
+ connect \$17 $not$libresoc.v:195131$14080_Y
+ connect \$19 $and$libresoc.v:195132$14081_Y
+ connect \$21 $and$libresoc.v:195133$14082_Y
+ connect \$25 $not$libresoc.v:195134$14083_Y
+ connect \$27 $and$libresoc.v:195135$14084_Y
+ connect \$24 $reduce_or$libresoc.v:195136$14085_Y
+ connect \$23 $not$libresoc.v:195137$14086_Y
+ connect \$31 $and$libresoc.v:195138$14087_Y
+ connect \$33 $reduce_or$libresoc.v:195139$14088_Y
+ connect \$35 $reduce_or$libresoc.v:195140$14089_Y
+ connect \$37 $or$libresoc.v:195141$14090_Y
+ connect \$3 $and$libresoc.v:195142$14091_Y
+ connect \$39 $not$libresoc.v:195143$14092_Y
+ connect \$41 $and$libresoc.v:195144$14093_Y
+ connect \$43 $and$libresoc.v:195145$14094_Y
+ connect \$45 $eq$libresoc.v:195146$14095_Y
+ connect \$47 $and$libresoc.v:195147$14096_Y
+ connect \$49 $eq$libresoc.v:195148$14097_Y
+ connect \$51 $and$libresoc.v:195149$14098_Y
+ connect \$53 $and$libresoc.v:195150$14099_Y
+ connect \$55 $and$libresoc.v:195151$14100_Y
+ connect \$57 $or$libresoc.v:195152$14101_Y
+ connect \$59 $or$libresoc.v:195153$14102_Y
+ connect \$61 $or$libresoc.v:195154$14103_Y
+ connect \$63 $or$libresoc.v:195155$14104_Y
+ connect \$65 $and$libresoc.v:195156$14105_Y
+ connect \$67 $and$libresoc.v:195157$14106_Y
+ connect \$6 $not$libresoc.v:195158$14107_Y
+ connect \$69 $or$libresoc.v:195159$14108_Y
+ connect \$71 $and$libresoc.v:195160$14109_Y
+ connect \$73 $and$libresoc.v:195161$14110_Y
+ connect \$75 $and$libresoc.v:195162$14111_Y
+ connect \$77 $and$libresoc.v:195163$14112_Y
+ connect \$79 $and$libresoc.v:195164$14113_Y
+ connect \$81 $ternary$libresoc.v:195165$14114_Y
+ connect \$83 $ternary$libresoc.v:195166$14115_Y
+ connect \$85 $ternary$libresoc.v:195167$14116_Y
+ connect \$87 $ternary$libresoc.v:195168$14117_Y
+ connect \$8 $or$libresoc.v:195169$14118_Y
+ connect \$89 $and$libresoc.v:195170$14119_Y
+ connect \$91 $and$libresoc.v:195171$14120_Y
+ connect \$93 $and$libresoc.v:195172$14121_Y
+ connect \$95 $and$libresoc.v:195173$14122_Y
+ connect \$97 $not$libresoc.v:195174$14123_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$113
connect \all_rd_dly$next \all_rd
connect \all_rd \$11
end
-attribute \src "libresoc.v:198597.1-198655.10"
+attribute \src "libresoc.v:195708.1-195766.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l"
attribute \generator "nMigen"
module \upd_l
- attribute \src "libresoc.v:198598.7-198598.20"
+ attribute \src "libresoc.v:195709.7-195709.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:198643.3-198651.6"
- wire $0\q_int$next[0:0]$14587
- attribute \src "libresoc.v:198641.3-198642.27"
+ attribute \src "libresoc.v:195754.3-195762.6"
+ wire $0\q_int$next[0:0]$14327
+ attribute \src "libresoc.v:195752.3-195753.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:198643.3-198651.6"
- wire $1\q_int$next[0:0]$14588
- attribute \src "libresoc.v:198620.7-198620.19"
+ attribute \src "libresoc.v:195754.3-195762.6"
+ wire $1\q_int$next[0:0]$14328
+ attribute \src "libresoc.v:195731.7-195731.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:198633.17-198633.96"
- wire $and$libresoc.v:198633$14577_Y
- attribute \src "libresoc.v:198638.17-198638.96"
- wire $and$libresoc.v:198638$14582_Y
- attribute \src "libresoc.v:198635.18-198635.93"
- wire $not$libresoc.v:198635$14579_Y
- attribute \src "libresoc.v:198637.17-198637.92"
- wire $not$libresoc.v:198637$14581_Y
- attribute \src "libresoc.v:198640.17-198640.92"
- wire $not$libresoc.v:198640$14584_Y
- attribute \src "libresoc.v:198634.18-198634.98"
- wire $or$libresoc.v:198634$14578_Y
- attribute \src "libresoc.v:198636.18-198636.99"
- wire $or$libresoc.v:198636$14580_Y
- attribute \src "libresoc.v:198639.17-198639.97"
- wire $or$libresoc.v:198639$14583_Y
+ attribute \src "libresoc.v:195744.17-195744.96"
+ wire $and$libresoc.v:195744$14317_Y
+ attribute \src "libresoc.v:195749.17-195749.96"
+ wire $and$libresoc.v:195749$14322_Y
+ attribute \src "libresoc.v:195746.18-195746.93"
+ wire $not$libresoc.v:195746$14319_Y
+ attribute \src "libresoc.v:195748.17-195748.92"
+ wire $not$libresoc.v:195748$14321_Y
+ attribute \src "libresoc.v:195751.17-195751.92"
+ wire $not$libresoc.v:195751$14324_Y
+ attribute \src "libresoc.v:195745.18-195745.98"
+ wire $or$libresoc.v:195745$14318_Y
+ attribute \src "libresoc.v:195747.18-195747.99"
+ wire $or$libresoc.v:195747$14320_Y
+ attribute \src "libresoc.v:195750.17-195750.97"
+ wire $or$libresoc.v:195750$14323_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:198598.7-198598.15"
+ attribute \src "libresoc.v:195709.7-195709.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_upd
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:198633$14577
+ cell $and $and$libresoc.v:195744$14317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:198633$14577_Y
+ connect \Y $and$libresoc.v:195744$14317_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:198638$14582
+ cell $and $and$libresoc.v:195749$14322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:198638$14582_Y
+ connect \Y $and$libresoc.v:195749$14322_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:198635$14579
+ cell $not $not$libresoc.v:195746$14319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_upd
- connect \Y $not$libresoc.v:198635$14579_Y
+ connect \Y $not$libresoc.v:195746$14319_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:198637$14581
+ cell $not $not$libresoc.v:195748$14321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:198637$14581_Y
+ connect \Y $not$libresoc.v:195748$14321_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:198640$14584
+ cell $not $not$libresoc.v:195751$14324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:198640$14584_Y
+ connect \Y $not$libresoc.v:195751$14324_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:198634$14578
+ cell $or $or$libresoc.v:195745$14318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_upd
- connect \Y $or$libresoc.v:198634$14578_Y
+ connect \Y $or$libresoc.v:195745$14318_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:198636$14580
+ cell $or $or$libresoc.v:195747$14320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_upd
connect \B \q_int
- connect \Y $or$libresoc.v:198636$14580_Y
+ connect \Y $or$libresoc.v:195747$14320_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:198639$14583
+ cell $or $or$libresoc.v:195750$14323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_upd
- connect \Y $or$libresoc.v:198639$14583_Y
+ connect \Y $or$libresoc.v:195750$14323_Y
end
- attribute \src "libresoc.v:198598.7-198598.20"
- process $proc$libresoc.v:198598$14589
+ attribute \src "libresoc.v:195709.7-195709.20"
+ process $proc$libresoc.v:195709$14329
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:198620.7-198620.19"
- process $proc$libresoc.v:198620$14590
+ attribute \src "libresoc.v:195731.7-195731.19"
+ process $proc$libresoc.v:195731$14330
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:198641.3-198642.27"
- process $proc$libresoc.v:198641$14585
+ attribute \src "libresoc.v:195752.3-195753.27"
+ process $proc$libresoc.v:195752$14325
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:198643.3-198651.6"
- process $proc$libresoc.v:198643$14586
+ attribute \src "libresoc.v:195754.3-195762.6"
+ process $proc$libresoc.v:195754$14326
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14587 $1\q_int$next[0:0]$14588
- attribute \src "libresoc.v:198644.5-198644.29"
+ assign $0\q_int$next[0:0]$14327 $1\q_int$next[0:0]$14328
+ attribute \src "libresoc.v:195755.5-195755.29"
switch \initial
- attribute \src "libresoc.v:198644.9-198644.17"
+ attribute \src "libresoc.v:195755.9-195755.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14588 1'0
+ assign $1\q_int$next[0:0]$14328 1'0
case
- assign $1\q_int$next[0:0]$14588 \$5
+ assign $1\q_int$next[0:0]$14328 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14587
+ update \q_int$next $0\q_int$next[0:0]$14327
end
- connect \$9 $and$libresoc.v:198633$14577_Y
- connect \$11 $or$libresoc.v:198634$14578_Y
- connect \$13 $not$libresoc.v:198635$14579_Y
- connect \$15 $or$libresoc.v:198636$14580_Y
- connect \$1 $not$libresoc.v:198637$14581_Y
- connect \$3 $and$libresoc.v:198638$14582_Y
- connect \$5 $or$libresoc.v:198639$14583_Y
- connect \$7 $not$libresoc.v:198640$14584_Y
+ connect \$9 $and$libresoc.v:195744$14317_Y
+ connect \$11 $or$libresoc.v:195745$14318_Y
+ connect \$13 $not$libresoc.v:195746$14319_Y
+ connect \$15 $or$libresoc.v:195747$14320_Y
+ connect \$1 $not$libresoc.v:195748$14321_Y
+ connect \$3 $and$libresoc.v:195749$14322_Y
+ connect \$5 $or$libresoc.v:195750$14323_Y
+ connect \$7 $not$libresoc.v:195751$14324_Y
connect \qlq_upd \$15
connect \qn_upd \$13
connect \q_upd \$11
end
-attribute \src "libresoc.v:198659.1-198717.10"
+attribute \src "libresoc.v:195770.1-195828.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l"
attribute \generator "nMigen"
module \valid_l
- attribute \src "libresoc.v:198660.7-198660.20"
+ attribute \src "libresoc.v:195771.7-195771.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:198705.3-198713.6"
- wire $0\q_int$next[0:0]$14601
- attribute \src "libresoc.v:198703.3-198704.27"
+ attribute \src "libresoc.v:195816.3-195824.6"
+ wire $0\q_int$next[0:0]$14341
+ attribute \src "libresoc.v:195814.3-195815.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:198705.3-198713.6"
- wire $1\q_int$next[0:0]$14602
- attribute \src "libresoc.v:198682.7-198682.19"
+ attribute \src "libresoc.v:195816.3-195824.6"
+ wire $1\q_int$next[0:0]$14342
+ attribute \src "libresoc.v:195793.7-195793.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:198695.17-198695.96"
- wire $and$libresoc.v:198695$14591_Y
- attribute \src "libresoc.v:198700.17-198700.96"
- wire $and$libresoc.v:198700$14596_Y
- attribute \src "libresoc.v:198697.18-198697.95"
- wire $not$libresoc.v:198697$14593_Y
- attribute \src "libresoc.v:198699.17-198699.94"
- wire $not$libresoc.v:198699$14595_Y
- attribute \src "libresoc.v:198702.17-198702.94"
- wire $not$libresoc.v:198702$14598_Y
- attribute \src "libresoc.v:198696.18-198696.100"
- wire $or$libresoc.v:198696$14592_Y
- attribute \src "libresoc.v:198698.18-198698.101"
- wire $or$libresoc.v:198698$14594_Y
- attribute \src "libresoc.v:198701.17-198701.99"
- wire $or$libresoc.v:198701$14597_Y
+ attribute \src "libresoc.v:195806.17-195806.96"
+ wire $and$libresoc.v:195806$14331_Y
+ attribute \src "libresoc.v:195811.17-195811.96"
+ wire $and$libresoc.v:195811$14336_Y
+ attribute \src "libresoc.v:195808.18-195808.95"
+ wire $not$libresoc.v:195808$14333_Y
+ attribute \src "libresoc.v:195810.17-195810.94"
+ wire $not$libresoc.v:195810$14335_Y
+ attribute \src "libresoc.v:195813.17-195813.94"
+ wire $not$libresoc.v:195813$14338_Y
+ attribute \src "libresoc.v:195807.18-195807.100"
+ wire $or$libresoc.v:195807$14332_Y
+ attribute \src "libresoc.v:195809.18-195809.101"
+ wire $or$libresoc.v:195809$14334_Y
+ attribute \src "libresoc.v:195812.17-195812.99"
+ wire $or$libresoc.v:195812$14337_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:198660.7-198660.15"
+ attribute \src "libresoc.v:195771.7-195771.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_valid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:198695$14591
+ cell $and $and$libresoc.v:195806$14331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:198695$14591_Y
+ connect \Y $and$libresoc.v:195806$14331_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:198700$14596
+ cell $and $and$libresoc.v:195811$14336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:198700$14596_Y
+ connect \Y $and$libresoc.v:195811$14336_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:198697$14593
+ cell $not $not$libresoc.v:195808$14333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_valid
- connect \Y $not$libresoc.v:198697$14593_Y
+ connect \Y $not$libresoc.v:195808$14333_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:198699$14595
+ cell $not $not$libresoc.v:195810$14335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:198699$14595_Y
+ connect \Y $not$libresoc.v:195810$14335_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:198702$14598
+ cell $not $not$libresoc.v:195813$14338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:198702$14598_Y
+ connect \Y $not$libresoc.v:195813$14338_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:198696$14592
+ cell $or $or$libresoc.v:195807$14332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_valid
- connect \Y $or$libresoc.v:198696$14592_Y
+ connect \Y $or$libresoc.v:195807$14332_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:198698$14594
+ cell $or $or$libresoc.v:195809$14334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_valid
connect \B \q_int
- connect \Y $or$libresoc.v:198698$14594_Y
+ connect \Y $or$libresoc.v:195809$14334_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:198701$14597
+ cell $or $or$libresoc.v:195812$14337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_valid
- connect \Y $or$libresoc.v:198701$14597_Y
+ connect \Y $or$libresoc.v:195812$14337_Y
end
- attribute \src "libresoc.v:198660.7-198660.20"
- process $proc$libresoc.v:198660$14603
+ attribute \src "libresoc.v:195771.7-195771.20"
+ process $proc$libresoc.v:195771$14343
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:198682.7-198682.19"
- process $proc$libresoc.v:198682$14604
+ attribute \src "libresoc.v:195793.7-195793.19"
+ process $proc$libresoc.v:195793$14344
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:198703.3-198704.27"
- process $proc$libresoc.v:198703$14599
+ attribute \src "libresoc.v:195814.3-195815.27"
+ process $proc$libresoc.v:195814$14339
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:198705.3-198713.6"
- process $proc$libresoc.v:198705$14600
+ attribute \src "libresoc.v:195816.3-195824.6"
+ process $proc$libresoc.v:195816$14340
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14601 $1\q_int$next[0:0]$14602
- attribute \src "libresoc.v:198706.5-198706.29"
+ assign $0\q_int$next[0:0]$14341 $1\q_int$next[0:0]$14342
+ attribute \src "libresoc.v:195817.5-195817.29"
switch \initial
- attribute \src "libresoc.v:198706.9-198706.17"
+ attribute \src "libresoc.v:195817.9-195817.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14602 1'0
+ assign $1\q_int$next[0:0]$14342 1'0
case
- assign $1\q_int$next[0:0]$14602 \$5
+ assign $1\q_int$next[0:0]$14342 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14601
+ update \q_int$next $0\q_int$next[0:0]$14341
end
- connect \$9 $and$libresoc.v:198695$14591_Y
- connect \$11 $or$libresoc.v:198696$14592_Y
- connect \$13 $not$libresoc.v:198697$14593_Y
- connect \$15 $or$libresoc.v:198698$14594_Y
- connect \$1 $not$libresoc.v:198699$14595_Y
- connect \$3 $and$libresoc.v:198700$14596_Y
- connect \$5 $or$libresoc.v:198701$14597_Y
- connect \$7 $not$libresoc.v:198702$14598_Y
+ connect \$9 $and$libresoc.v:195806$14331_Y
+ connect \$11 $or$libresoc.v:195807$14332_Y
+ connect \$13 $not$libresoc.v:195808$14333_Y
+ connect \$15 $or$libresoc.v:195809$14334_Y
+ connect \$1 $not$libresoc.v:195810$14335_Y
+ connect \$3 $and$libresoc.v:195811$14336_Y
+ connect \$5 $or$libresoc.v:195812$14337_Y
+ connect \$7 $not$libresoc.v:195813$14338_Y
connect \qlq_valid \$15
connect \qn_valid \$13
connect \q_valid \$11
end
-attribute \src "libresoc.v:198721.1-198779.10"
+attribute \src "libresoc.v:195832.1-195890.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l"
attribute \generator "nMigen"
module \wri_l
- attribute \src "libresoc.v:198722.7-198722.20"
+ attribute \src "libresoc.v:195833.7-195833.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:198767.3-198775.6"
- wire $0\q_int$next[0:0]$14615
- attribute \src "libresoc.v:198765.3-198766.27"
+ attribute \src "libresoc.v:195878.3-195886.6"
+ wire $0\q_int$next[0:0]$14355
+ attribute \src "libresoc.v:195876.3-195877.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:198767.3-198775.6"
- wire $1\q_int$next[0:0]$14616
- attribute \src "libresoc.v:198744.7-198744.19"
+ attribute \src "libresoc.v:195878.3-195886.6"
+ wire $1\q_int$next[0:0]$14356
+ attribute \src "libresoc.v:195855.7-195855.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:198757.17-198757.96"
- wire $and$libresoc.v:198757$14605_Y
- attribute \src "libresoc.v:198762.17-198762.96"
- wire $and$libresoc.v:198762$14610_Y
- attribute \src "libresoc.v:198759.18-198759.93"
- wire $not$libresoc.v:198759$14607_Y
- attribute \src "libresoc.v:198761.17-198761.92"
- wire $not$libresoc.v:198761$14609_Y
- attribute \src "libresoc.v:198764.17-198764.92"
- wire $not$libresoc.v:198764$14612_Y
- attribute \src "libresoc.v:198758.18-198758.98"
- wire $or$libresoc.v:198758$14606_Y
- attribute \src "libresoc.v:198760.18-198760.99"
- wire $or$libresoc.v:198760$14608_Y
- attribute \src "libresoc.v:198763.17-198763.97"
- wire $or$libresoc.v:198763$14611_Y
+ attribute \src "libresoc.v:195868.17-195868.96"
+ wire $and$libresoc.v:195868$14345_Y
+ attribute \src "libresoc.v:195873.17-195873.96"
+ wire $and$libresoc.v:195873$14350_Y
+ attribute \src "libresoc.v:195870.18-195870.93"
+ wire $not$libresoc.v:195870$14347_Y
+ attribute \src "libresoc.v:195872.17-195872.92"
+ wire $not$libresoc.v:195872$14349_Y
+ attribute \src "libresoc.v:195875.17-195875.92"
+ wire $not$libresoc.v:195875$14352_Y
+ attribute \src "libresoc.v:195869.18-195869.98"
+ wire $or$libresoc.v:195869$14346_Y
+ attribute \src "libresoc.v:195871.18-195871.99"
+ wire $or$libresoc.v:195871$14348_Y
+ attribute \src "libresoc.v:195874.17-195874.97"
+ wire $or$libresoc.v:195874$14351_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:198722.7-198722.15"
+ attribute \src "libresoc.v:195833.7-195833.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_wri
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:198757$14605
+ cell $and $and$libresoc.v:195868$14345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:198757$14605_Y
+ connect \Y $and$libresoc.v:195868$14345_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:198762$14610
+ cell $and $and$libresoc.v:195873$14350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:198762$14610_Y
+ connect \Y $and$libresoc.v:195873$14350_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:198759$14607
+ cell $not $not$libresoc.v:195870$14347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_wri
- connect \Y $not$libresoc.v:198759$14607_Y
+ connect \Y $not$libresoc.v:195870$14347_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:198761$14609
+ cell $not $not$libresoc.v:195872$14349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:198761$14609_Y
+ connect \Y $not$libresoc.v:195872$14349_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:198764$14612
+ cell $not $not$libresoc.v:195875$14352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:198764$14612_Y
+ connect \Y $not$libresoc.v:195875$14352_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:198758$14606
+ cell $or $or$libresoc.v:195869$14346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_wri
- connect \Y $or$libresoc.v:198758$14606_Y
+ connect \Y $or$libresoc.v:195869$14346_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:198760$14608
+ cell $or $or$libresoc.v:195871$14348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_wri
connect \B \q_int
- connect \Y $or$libresoc.v:198760$14608_Y
+ connect \Y $or$libresoc.v:195871$14348_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:198763$14611
+ cell $or $or$libresoc.v:195874$14351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_wri
- connect \Y $or$libresoc.v:198763$14611_Y
+ connect \Y $or$libresoc.v:195874$14351_Y
end
- attribute \src "libresoc.v:198722.7-198722.20"
- process $proc$libresoc.v:198722$14617
+ attribute \src "libresoc.v:195833.7-195833.20"
+ process $proc$libresoc.v:195833$14357
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:198744.7-198744.19"
- process $proc$libresoc.v:198744$14618
+ attribute \src "libresoc.v:195855.7-195855.19"
+ process $proc$libresoc.v:195855$14358
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:198765.3-198766.27"
- process $proc$libresoc.v:198765$14613
+ attribute \src "libresoc.v:195876.3-195877.27"
+ process $proc$libresoc.v:195876$14353
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:198767.3-198775.6"
- process $proc$libresoc.v:198767$14614
+ attribute \src "libresoc.v:195878.3-195886.6"
+ process $proc$libresoc.v:195878$14354
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14615 $1\q_int$next[0:0]$14616
- attribute \src "libresoc.v:198768.5-198768.29"
+ assign $0\q_int$next[0:0]$14355 $1\q_int$next[0:0]$14356
+ attribute \src "libresoc.v:195879.5-195879.29"
switch \initial
- attribute \src "libresoc.v:198768.9-198768.17"
+ attribute \src "libresoc.v:195879.9-195879.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14616 1'0
+ assign $1\q_int$next[0:0]$14356 1'0
case
- assign $1\q_int$next[0:0]$14616 \$5
+ assign $1\q_int$next[0:0]$14356 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14615
+ update \q_int$next $0\q_int$next[0:0]$14355
end
- connect \$9 $and$libresoc.v:198757$14605_Y
- connect \$11 $or$libresoc.v:198758$14606_Y
- connect \$13 $not$libresoc.v:198759$14607_Y
- connect \$15 $or$libresoc.v:198760$14608_Y
- connect \$1 $not$libresoc.v:198761$14609_Y
- connect \$3 $and$libresoc.v:198762$14610_Y
- connect \$5 $or$libresoc.v:198763$14611_Y
- connect \$7 $not$libresoc.v:198764$14612_Y
+ connect \$9 $and$libresoc.v:195868$14345_Y
+ connect \$11 $or$libresoc.v:195869$14346_Y
+ connect \$13 $not$libresoc.v:195870$14347_Y
+ connect \$15 $or$libresoc.v:195871$14348_Y
+ connect \$1 $not$libresoc.v:195872$14349_Y
+ connect \$3 $and$libresoc.v:195873$14350_Y
+ connect \$5 $or$libresoc.v:195874$14351_Y
+ connect \$7 $not$libresoc.v:195875$14352_Y
connect \qlq_wri \$15
connect \qn_wri \$13
connect \q_wri \$11
end
-attribute \src "libresoc.v:198783.1-198849.10"
+attribute \src "libresoc.v:195894.1-195960.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a"
attribute \generator "nMigen"
module \wrpick_CR_cr_a
- attribute \src "libresoc.v:198828.17-198828.91"
- wire $not$libresoc.v:198828$14619_Y
- attribute \src "libresoc.v:198830.18-198830.93"
- wire $not$libresoc.v:198830$14621_Y
- attribute \src "libresoc.v:198832.18-198832.93"
- wire $not$libresoc.v:198832$14623_Y
- attribute \src "libresoc.v:198833.17-198833.89"
- wire width 6 $not$libresoc.v:198833$14624_Y
- attribute \src "libresoc.v:198835.18-198835.93"
- wire $not$libresoc.v:198835$14626_Y
- attribute \src "libresoc.v:198838.17-198838.91"
- wire $not$libresoc.v:198838$14629_Y
- attribute \src "libresoc.v:198829.18-198829.106"
- wire $reduce_or$libresoc.v:198829$14620_Y
- attribute \src "libresoc.v:198831.18-198831.106"
- wire $reduce_or$libresoc.v:198831$14622_Y
- attribute \src "libresoc.v:198834.18-198834.106"
- wire $reduce_or$libresoc.v:198834$14625_Y
- attribute \src "libresoc.v:198836.18-198836.90"
- wire $reduce_or$libresoc.v:198836$14627_Y
- attribute \src "libresoc.v:198837.17-198837.103"
- wire $reduce_or$libresoc.v:198837$14628_Y
- attribute \src "libresoc.v:198839.17-198839.105"
- wire $reduce_or$libresoc.v:198839$14630_Y
+ attribute \src "libresoc.v:195939.17-195939.91"
+ wire $not$libresoc.v:195939$14359_Y
+ attribute \src "libresoc.v:195941.18-195941.93"
+ wire $not$libresoc.v:195941$14361_Y
+ attribute \src "libresoc.v:195943.18-195943.93"
+ wire $not$libresoc.v:195943$14363_Y
+ attribute \src "libresoc.v:195944.17-195944.89"
+ wire width 6 $not$libresoc.v:195944$14364_Y
+ attribute \src "libresoc.v:195946.18-195946.93"
+ wire $not$libresoc.v:195946$14366_Y
+ attribute \src "libresoc.v:195949.17-195949.91"
+ wire $not$libresoc.v:195949$14369_Y
+ attribute \src "libresoc.v:195940.18-195940.106"
+ wire $reduce_or$libresoc.v:195940$14360_Y
+ attribute \src "libresoc.v:195942.18-195942.106"
+ wire $reduce_or$libresoc.v:195942$14362_Y
+ attribute \src "libresoc.v:195945.18-195945.106"
+ wire $reduce_or$libresoc.v:195945$14365_Y
+ attribute \src "libresoc.v:195947.18-195947.90"
+ wire $reduce_or$libresoc.v:195947$14367_Y
+ attribute \src "libresoc.v:195948.17-195948.103"
+ wire $reduce_or$libresoc.v:195948$14368_Y
+ attribute \src "libresoc.v:195950.17-195950.105"
+ wire $reduce_or$libresoc.v:195950$14370_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198828$14619
+ cell $not $not$libresoc.v:195939$14359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:198828$14619_Y
+ connect \Y $not$libresoc.v:195939$14359_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198830$14621
+ cell $not $not$libresoc.v:195941$14361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:198830$14621_Y
+ connect \Y $not$libresoc.v:195941$14361_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198832$14623
+ cell $not $not$libresoc.v:195943$14363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:198832$14623_Y
+ connect \Y $not$libresoc.v:195943$14363_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:198833$14624
+ cell $not $not$libresoc.v:195944$14364
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \i
- connect \Y $not$libresoc.v:198833$14624_Y
+ connect \Y $not$libresoc.v:195944$14364_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198835$14626
+ cell $not $not$libresoc.v:195946$14366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:198835$14626_Y
+ connect \Y $not$libresoc.v:195946$14366_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198838$14629
+ cell $not $not$libresoc.v:195949$14369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:198838$14629_Y
+ connect \Y $not$libresoc.v:195949$14369_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198829$14620
+ cell $reduce_or $reduce_or$libresoc.v:195940$14360
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:198829$14620_Y
+ connect \Y $reduce_or$libresoc.v:195940$14360_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198831$14622
+ cell $reduce_or $reduce_or$libresoc.v:195942$14362
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:198831$14622_Y
+ connect \Y $reduce_or$libresoc.v:195942$14362_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198834$14625
+ cell $reduce_or $reduce_or$libresoc.v:195945$14365
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:198834$14625_Y
+ connect \Y $reduce_or$libresoc.v:195945$14365_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:198836$14627
+ cell $reduce_or $reduce_or$libresoc.v:195947$14367
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:198836$14627_Y
+ connect \Y $reduce_or$libresoc.v:195947$14367_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198837$14628
+ cell $reduce_or $reduce_or$libresoc.v:195948$14368
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:198837$14628_Y
+ connect \Y $reduce_or$libresoc.v:195948$14368_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198839$14630
+ cell $reduce_or $reduce_or$libresoc.v:195950$14370
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:198839$14630_Y
- end
- connect \$7 $not$libresoc.v:198828$14619_Y
- connect \$12 $reduce_or$libresoc.v:198829$14620_Y
- connect \$11 $not$libresoc.v:198830$14621_Y
- connect \$16 $reduce_or$libresoc.v:198831$14622_Y
- connect \$15 $not$libresoc.v:198832$14623_Y
- connect \$1 $not$libresoc.v:198833$14624_Y
- connect \$20 $reduce_or$libresoc.v:198834$14625_Y
- connect \$19 $not$libresoc.v:198835$14626_Y
- connect \$23 $reduce_or$libresoc.v:198836$14627_Y
- connect \$4 $reduce_or$libresoc.v:198837$14628_Y
- connect \$3 $not$libresoc.v:198838$14629_Y
- connect \$8 $reduce_or$libresoc.v:198839$14630_Y
+ connect \Y $reduce_or$libresoc.v:195950$14370_Y
+ end
+ connect \$7 $not$libresoc.v:195939$14359_Y
+ connect \$12 $reduce_or$libresoc.v:195940$14360_Y
+ connect \$11 $not$libresoc.v:195941$14361_Y
+ connect \$16 $reduce_or$libresoc.v:195942$14362_Y
+ connect \$15 $not$libresoc.v:195943$14363_Y
+ connect \$1 $not$libresoc.v:195944$14364_Y
+ connect \$20 $reduce_or$libresoc.v:195945$14365_Y
+ connect \$19 $not$libresoc.v:195946$14366_Y
+ connect \$23 $reduce_or$libresoc.v:195947$14367_Y
+ connect \$4 $reduce_or$libresoc.v:195948$14368_Y
+ connect \$3 $not$libresoc.v:195949$14369_Y
+ connect \$8 $reduce_or$libresoc.v:195950$14370_Y
connect \en_o \$23
connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t5 \$19
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:198853.1-198874.10"
+attribute \src "libresoc.v:195964.1-195985.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr"
attribute \generator "nMigen"
module \wrpick_CR_full_cr
- attribute \src "libresoc.v:198868.17-198868.89"
- wire $not$libresoc.v:198868$14631_Y
- attribute \src "libresoc.v:198869.17-198869.89"
- wire $reduce_or$libresoc.v:198869$14632_Y
+ attribute \src "libresoc.v:195979.17-195979.89"
+ wire $not$libresoc.v:195979$14371_Y
+ attribute \src "libresoc.v:195980.17-195980.89"
+ wire $reduce_or$libresoc.v:195980$14372_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:198868$14631
+ cell $not $not$libresoc.v:195979$14371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:198868$14631_Y
+ connect \Y $not$libresoc.v:195979$14371_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:198869$14632
+ cell $reduce_or $reduce_or$libresoc.v:195980$14372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:198869$14632_Y
+ connect \Y $reduce_or$libresoc.v:195980$14372_Y
end
- connect \$1 $not$libresoc.v:198868$14631_Y
- connect \$3 $reduce_or$libresoc.v:198869$14632_Y
+ connect \$1 $not$libresoc.v:195979$14371_Y
+ connect \$3 $reduce_or$libresoc.v:195980$14372_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:198878.1-198935.10"
+attribute \src "libresoc.v:195989.1-196046.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1"
attribute \generator "nMigen"
module \wrpick_FAST_fast1
- attribute \src "libresoc.v:198917.17-198917.91"
- wire $not$libresoc.v:198917$14633_Y
- attribute \src "libresoc.v:198919.18-198919.93"
- wire $not$libresoc.v:198919$14635_Y
- attribute \src "libresoc.v:198921.18-198921.93"
- wire $not$libresoc.v:198921$14637_Y
- attribute \src "libresoc.v:198922.17-198922.89"
- wire width 5 $not$libresoc.v:198922$14638_Y
- attribute \src "libresoc.v:198925.17-198925.91"
- wire $not$libresoc.v:198925$14641_Y
- attribute \src "libresoc.v:198918.18-198918.106"
- wire $reduce_or$libresoc.v:198918$14634_Y
- attribute \src "libresoc.v:198920.18-198920.106"
- wire $reduce_or$libresoc.v:198920$14636_Y
- attribute \src "libresoc.v:198923.18-198923.90"
- wire $reduce_or$libresoc.v:198923$14639_Y
- attribute \src "libresoc.v:198924.17-198924.103"
- wire $reduce_or$libresoc.v:198924$14640_Y
- attribute \src "libresoc.v:198926.17-198926.105"
- wire $reduce_or$libresoc.v:198926$14642_Y
+ attribute \src "libresoc.v:196028.17-196028.91"
+ wire $not$libresoc.v:196028$14373_Y
+ attribute \src "libresoc.v:196030.18-196030.93"
+ wire $not$libresoc.v:196030$14375_Y
+ attribute \src "libresoc.v:196032.18-196032.93"
+ wire $not$libresoc.v:196032$14377_Y
+ attribute \src "libresoc.v:196033.17-196033.89"
+ wire width 5 $not$libresoc.v:196033$14378_Y
+ attribute \src "libresoc.v:196036.17-196036.91"
+ wire $not$libresoc.v:196036$14381_Y
+ attribute \src "libresoc.v:196029.18-196029.106"
+ wire $reduce_or$libresoc.v:196029$14374_Y
+ attribute \src "libresoc.v:196031.18-196031.106"
+ wire $reduce_or$libresoc.v:196031$14376_Y
+ attribute \src "libresoc.v:196034.18-196034.90"
+ wire $reduce_or$libresoc.v:196034$14379_Y
+ attribute \src "libresoc.v:196035.17-196035.103"
+ wire $reduce_or$libresoc.v:196035$14380_Y
+ attribute \src "libresoc.v:196037.17-196037.105"
+ wire $reduce_or$libresoc.v:196037$14382_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198917$14633
+ cell $not $not$libresoc.v:196028$14373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:198917$14633_Y
+ connect \Y $not$libresoc.v:196028$14373_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198919$14635
+ cell $not $not$libresoc.v:196030$14375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:198919$14635_Y
+ connect \Y $not$libresoc.v:196030$14375_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198921$14637
+ cell $not $not$libresoc.v:196032$14377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:198921$14637_Y
+ connect \Y $not$libresoc.v:196032$14377_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:198922$14638
+ cell $not $not$libresoc.v:196033$14378
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \i
- connect \Y $not$libresoc.v:198922$14638_Y
+ connect \Y $not$libresoc.v:196033$14378_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:198925$14641
+ cell $not $not$libresoc.v:196036$14381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:198925$14641_Y
+ connect \Y $not$libresoc.v:196036$14381_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198918$14634
+ cell $reduce_or $reduce_or$libresoc.v:196029$14374
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:198918$14634_Y
+ connect \Y $reduce_or$libresoc.v:196029$14374_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198920$14636
+ cell $reduce_or $reduce_or$libresoc.v:196031$14376
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:198920$14636_Y
+ connect \Y $reduce_or$libresoc.v:196031$14376_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:198923$14639
+ cell $reduce_or $reduce_or$libresoc.v:196034$14379
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:198923$14639_Y
+ connect \Y $reduce_or$libresoc.v:196034$14379_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198924$14640
+ cell $reduce_or $reduce_or$libresoc.v:196035$14380
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:198924$14640_Y
+ connect \Y $reduce_or$libresoc.v:196035$14380_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:198926$14642
+ cell $reduce_or $reduce_or$libresoc.v:196037$14382
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:198926$14642_Y
- end
- connect \$7 $not$libresoc.v:198917$14633_Y
- connect \$12 $reduce_or$libresoc.v:198918$14634_Y
- connect \$11 $not$libresoc.v:198919$14635_Y
- connect \$16 $reduce_or$libresoc.v:198920$14636_Y
- connect \$15 $not$libresoc.v:198921$14637_Y
- connect \$1 $not$libresoc.v:198922$14638_Y
- connect \$19 $reduce_or$libresoc.v:198923$14639_Y
- connect \$4 $reduce_or$libresoc.v:198924$14640_Y
- connect \$3 $not$libresoc.v:198925$14641_Y
- connect \$8 $reduce_or$libresoc.v:198926$14642_Y
+ connect \Y $reduce_or$libresoc.v:196037$14382_Y
+ end
+ connect \$7 $not$libresoc.v:196028$14373_Y
+ connect \$12 $reduce_or$libresoc.v:196029$14374_Y
+ connect \$11 $not$libresoc.v:196030$14375_Y
+ connect \$16 $reduce_or$libresoc.v:196031$14376_Y
+ connect \$15 $not$libresoc.v:196032$14377_Y
+ connect \$1 $not$libresoc.v:196033$14378_Y
+ connect \$19 $reduce_or$libresoc.v:196034$14379_Y
+ connect \$4 $reduce_or$libresoc.v:196035$14380_Y
+ connect \$3 $not$libresoc.v:196036$14381_Y
+ connect \$8 $reduce_or$libresoc.v:196037$14382_Y
connect \en_o \$19
connect \o { \t4 \t3 \t2 \t1 \t0 }
connect \t4 \$15
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:198939.1-199041.10"
+attribute \src "libresoc.v:196050.1-196152.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o"
attribute \generator "nMigen"
module \wrpick_INT_o
- attribute \src "libresoc.v:199008.17-199008.91"
- wire $not$libresoc.v:199008$14643_Y
- attribute \src "libresoc.v:199010.18-199010.93"
- wire $not$libresoc.v:199010$14645_Y
- attribute \src "libresoc.v:199012.18-199012.93"
- wire $not$libresoc.v:199012$14647_Y
- attribute \src "libresoc.v:199013.17-199013.89"
- wire width 10 $not$libresoc.v:199013$14648_Y
- attribute \src "libresoc.v:199015.18-199015.93"
- wire $not$libresoc.v:199015$14650_Y
- attribute \src "libresoc.v:199017.18-199017.93"
- wire $not$libresoc.v:199017$14652_Y
- attribute \src "libresoc.v:199019.18-199019.93"
- wire $not$libresoc.v:199019$14654_Y
- attribute \src "libresoc.v:199021.18-199021.93"
- wire $not$libresoc.v:199021$14656_Y
- attribute \src "libresoc.v:199023.18-199023.93"
- wire $not$libresoc.v:199023$14658_Y
- attribute \src "libresoc.v:199026.17-199026.91"
- wire $not$libresoc.v:199026$14661_Y
- attribute \src "libresoc.v:199009.18-199009.106"
- wire $reduce_or$libresoc.v:199009$14644_Y
- attribute \src "libresoc.v:199011.18-199011.106"
- wire $reduce_or$libresoc.v:199011$14646_Y
- attribute \src "libresoc.v:199014.18-199014.106"
- wire $reduce_or$libresoc.v:199014$14649_Y
- attribute \src "libresoc.v:199016.18-199016.106"
- wire $reduce_or$libresoc.v:199016$14651_Y
- attribute \src "libresoc.v:199018.18-199018.106"
- wire $reduce_or$libresoc.v:199018$14653_Y
- attribute \src "libresoc.v:199020.18-199020.106"
- wire $reduce_or$libresoc.v:199020$14655_Y
- attribute \src "libresoc.v:199022.18-199022.106"
- wire $reduce_or$libresoc.v:199022$14657_Y
- attribute \src "libresoc.v:199024.18-199024.90"
- wire $reduce_or$libresoc.v:199024$14659_Y
- attribute \src "libresoc.v:199025.17-199025.103"
- wire $reduce_or$libresoc.v:199025$14660_Y
- attribute \src "libresoc.v:199027.17-199027.105"
- wire $reduce_or$libresoc.v:199027$14662_Y
+ attribute \src "libresoc.v:196119.17-196119.91"
+ wire $not$libresoc.v:196119$14383_Y
+ attribute \src "libresoc.v:196121.18-196121.93"
+ wire $not$libresoc.v:196121$14385_Y
+ attribute \src "libresoc.v:196123.18-196123.93"
+ wire $not$libresoc.v:196123$14387_Y
+ attribute \src "libresoc.v:196124.17-196124.89"
+ wire width 10 $not$libresoc.v:196124$14388_Y
+ attribute \src "libresoc.v:196126.18-196126.93"
+ wire $not$libresoc.v:196126$14390_Y
+ attribute \src "libresoc.v:196128.18-196128.93"
+ wire $not$libresoc.v:196128$14392_Y
+ attribute \src "libresoc.v:196130.18-196130.93"
+ wire $not$libresoc.v:196130$14394_Y
+ attribute \src "libresoc.v:196132.18-196132.93"
+ wire $not$libresoc.v:196132$14396_Y
+ attribute \src "libresoc.v:196134.18-196134.93"
+ wire $not$libresoc.v:196134$14398_Y
+ attribute \src "libresoc.v:196137.17-196137.91"
+ wire $not$libresoc.v:196137$14401_Y
+ attribute \src "libresoc.v:196120.18-196120.106"
+ wire $reduce_or$libresoc.v:196120$14384_Y
+ attribute \src "libresoc.v:196122.18-196122.106"
+ wire $reduce_or$libresoc.v:196122$14386_Y
+ attribute \src "libresoc.v:196125.18-196125.106"
+ wire $reduce_or$libresoc.v:196125$14389_Y
+ attribute \src "libresoc.v:196127.18-196127.106"
+ wire $reduce_or$libresoc.v:196127$14391_Y
+ attribute \src "libresoc.v:196129.18-196129.106"
+ wire $reduce_or$libresoc.v:196129$14393_Y
+ attribute \src "libresoc.v:196131.18-196131.106"
+ wire $reduce_or$libresoc.v:196131$14395_Y
+ attribute \src "libresoc.v:196133.18-196133.106"
+ wire $reduce_or$libresoc.v:196133$14397_Y
+ attribute \src "libresoc.v:196135.18-196135.90"
+ wire $reduce_or$libresoc.v:196135$14399_Y
+ attribute \src "libresoc.v:196136.17-196136.103"
+ wire $reduce_or$libresoc.v:196136$14400_Y
+ attribute \src "libresoc.v:196138.17-196138.105"
+ wire $reduce_or$libresoc.v:196138$14402_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 10 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199008$14643
+ cell $not $not$libresoc.v:196119$14383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:199008$14643_Y
+ connect \Y $not$libresoc.v:196119$14383_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199010$14645
+ cell $not $not$libresoc.v:196121$14385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:199010$14645_Y
+ connect \Y $not$libresoc.v:196121$14385_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199012$14647
+ cell $not $not$libresoc.v:196123$14387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:199012$14647_Y
+ connect \Y $not$libresoc.v:196123$14387_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199013$14648
+ cell $not $not$libresoc.v:196124$14388
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 10
connect \A \i
- connect \Y $not$libresoc.v:199013$14648_Y
+ connect \Y $not$libresoc.v:196124$14388_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199015$14650
+ cell $not $not$libresoc.v:196126$14390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:199015$14650_Y
+ connect \Y $not$libresoc.v:196126$14390_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199017$14652
+ cell $not $not$libresoc.v:196128$14392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:199017$14652_Y
+ connect \Y $not$libresoc.v:196128$14392_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199019$14654
+ cell $not $not$libresoc.v:196130$14394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:199019$14654_Y
+ connect \Y $not$libresoc.v:196130$14394_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199021$14656
+ cell $not $not$libresoc.v:196132$14396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$32
- connect \Y $not$libresoc.v:199021$14656_Y
+ connect \Y $not$libresoc.v:196132$14396_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199023$14658
+ cell $not $not$libresoc.v:196134$14398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$36
- connect \Y $not$libresoc.v:199023$14658_Y
+ connect \Y $not$libresoc.v:196134$14398_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199026$14661
+ cell $not $not$libresoc.v:196137$14401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:199026$14661_Y
+ connect \Y $not$libresoc.v:196137$14401_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199009$14644
+ cell $reduce_or $reduce_or$libresoc.v:196120$14384
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:199009$14644_Y
+ connect \Y $reduce_or$libresoc.v:196120$14384_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199011$14646
+ cell $reduce_or $reduce_or$libresoc.v:196122$14386
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:199011$14646_Y
+ connect \Y $reduce_or$libresoc.v:196122$14386_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199014$14649
+ cell $reduce_or $reduce_or$libresoc.v:196125$14389
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:199014$14649_Y
+ connect \Y $reduce_or$libresoc.v:196125$14389_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199016$14651
+ cell $reduce_or $reduce_or$libresoc.v:196127$14391
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:199016$14651_Y
+ connect \Y $reduce_or$libresoc.v:196127$14391_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199018$14653
+ cell $reduce_or $reduce_or$libresoc.v:196129$14393
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:199018$14653_Y
+ connect \Y $reduce_or$libresoc.v:196129$14393_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199020$14655
+ cell $reduce_or $reduce_or$libresoc.v:196131$14395
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 1
connect \A { \i [7:0] \ni [8] }
- connect \Y $reduce_or$libresoc.v:199020$14655_Y
+ connect \Y $reduce_or$libresoc.v:196131$14395_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199022$14657
+ cell $reduce_or $reduce_or$libresoc.v:196133$14397
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A { \i [8:0] \ni [9] }
- connect \Y $reduce_or$libresoc.v:199022$14657_Y
+ connect \Y $reduce_or$libresoc.v:196133$14397_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199024$14659
+ cell $reduce_or $reduce_or$libresoc.v:196135$14399
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199024$14659_Y
+ connect \Y $reduce_or$libresoc.v:196135$14399_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199025$14660
+ cell $reduce_or $reduce_or$libresoc.v:196136$14400
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:199025$14660_Y
+ connect \Y $reduce_or$libresoc.v:196136$14400_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199027$14662
+ cell $reduce_or $reduce_or$libresoc.v:196138$14402
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:199027$14662_Y
- end
- connect \$7 $not$libresoc.v:199008$14643_Y
- connect \$12 $reduce_or$libresoc.v:199009$14644_Y
- connect \$11 $not$libresoc.v:199010$14645_Y
- connect \$16 $reduce_or$libresoc.v:199011$14646_Y
- connect \$15 $not$libresoc.v:199012$14647_Y
- connect \$1 $not$libresoc.v:199013$14648_Y
- connect \$20 $reduce_or$libresoc.v:199014$14649_Y
- connect \$19 $not$libresoc.v:199015$14650_Y
- connect \$24 $reduce_or$libresoc.v:199016$14651_Y
- connect \$23 $not$libresoc.v:199017$14652_Y
- connect \$28 $reduce_or$libresoc.v:199018$14653_Y
- connect \$27 $not$libresoc.v:199019$14654_Y
- connect \$32 $reduce_or$libresoc.v:199020$14655_Y
- connect \$31 $not$libresoc.v:199021$14656_Y
- connect \$36 $reduce_or$libresoc.v:199022$14657_Y
- connect \$35 $not$libresoc.v:199023$14658_Y
- connect \$39 $reduce_or$libresoc.v:199024$14659_Y
- connect \$4 $reduce_or$libresoc.v:199025$14660_Y
- connect \$3 $not$libresoc.v:199026$14661_Y
- connect \$8 $reduce_or$libresoc.v:199027$14662_Y
+ connect \Y $reduce_or$libresoc.v:196138$14402_Y
+ end
+ connect \$7 $not$libresoc.v:196119$14383_Y
+ connect \$12 $reduce_or$libresoc.v:196120$14384_Y
+ connect \$11 $not$libresoc.v:196121$14385_Y
+ connect \$16 $reduce_or$libresoc.v:196122$14386_Y
+ connect \$15 $not$libresoc.v:196123$14387_Y
+ connect \$1 $not$libresoc.v:196124$14388_Y
+ connect \$20 $reduce_or$libresoc.v:196125$14389_Y
+ connect \$19 $not$libresoc.v:196126$14390_Y
+ connect \$24 $reduce_or$libresoc.v:196127$14391_Y
+ connect \$23 $not$libresoc.v:196128$14392_Y
+ connect \$28 $reduce_or$libresoc.v:196129$14393_Y
+ connect \$27 $not$libresoc.v:196130$14394_Y
+ connect \$32 $reduce_or$libresoc.v:196131$14395_Y
+ connect \$31 $not$libresoc.v:196132$14396_Y
+ connect \$36 $reduce_or$libresoc.v:196133$14397_Y
+ connect \$35 $not$libresoc.v:196134$14398_Y
+ connect \$39 $reduce_or$libresoc.v:196135$14399_Y
+ connect \$4 $reduce_or$libresoc.v:196136$14400_Y
+ connect \$3 $not$libresoc.v:196137$14401_Y
+ connect \$8 $reduce_or$libresoc.v:196138$14402_Y
connect \en_o \$39
connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t9 \$35
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:199045.1-199066.10"
+attribute \src "libresoc.v:196156.1-196177.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1"
attribute \generator "nMigen"
module \wrpick_SPR_spr1
- attribute \src "libresoc.v:199060.17-199060.89"
- wire $not$libresoc.v:199060$14663_Y
- attribute \src "libresoc.v:199061.17-199061.89"
- wire $reduce_or$libresoc.v:199061$14664_Y
+ attribute \src "libresoc.v:196171.17-196171.89"
+ wire $not$libresoc.v:196171$14403_Y
+ attribute \src "libresoc.v:196172.17-196172.89"
+ wire $reduce_or$libresoc.v:196172$14404_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199060$14663
+ cell $not $not$libresoc.v:196171$14403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:199060$14663_Y
+ connect \Y $not$libresoc.v:196171$14403_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199061$14664
+ cell $reduce_or $reduce_or$libresoc.v:196172$14404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199061$14664_Y
+ connect \Y $reduce_or$libresoc.v:196172$14404_Y
end
- connect \$1 $not$libresoc.v:199060$14663_Y
- connect \$3 $reduce_or$libresoc.v:199061$14664_Y
+ connect \$1 $not$libresoc.v:196171$14403_Y
+ connect \$3 $reduce_or$libresoc.v:196172$14404_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:199070.1-199091.10"
+attribute \src "libresoc.v:196181.1-196202.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr"
attribute \generator "nMigen"
module \wrpick_STATE_msr
- attribute \src "libresoc.v:199085.17-199085.89"
- wire $not$libresoc.v:199085$14665_Y
- attribute \src "libresoc.v:199086.17-199086.89"
- wire $reduce_or$libresoc.v:199086$14666_Y
+ attribute \src "libresoc.v:196196.17-196196.89"
+ wire $not$libresoc.v:196196$14405_Y
+ attribute \src "libresoc.v:196197.17-196197.89"
+ wire $reduce_or$libresoc.v:196197$14406_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199085$14665
+ cell $not $not$libresoc.v:196196$14405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:199085$14665_Y
+ connect \Y $not$libresoc.v:196196$14405_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199086$14666
+ cell $reduce_or $reduce_or$libresoc.v:196197$14406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199086$14666_Y
+ connect \Y $reduce_or$libresoc.v:196197$14406_Y
end
- connect \$1 $not$libresoc.v:199085$14665_Y
- connect \$3 $reduce_or$libresoc.v:199086$14666_Y
+ connect \$1 $not$libresoc.v:196196$14405_Y
+ connect \$3 $reduce_or$libresoc.v:196197$14406_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:199095.1-199125.10"
+attribute \src "libresoc.v:196206.1-196236.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia"
attribute \generator "nMigen"
module \wrpick_STATE_nia
- attribute \src "libresoc.v:199116.17-199116.89"
- wire width 2 $not$libresoc.v:199116$14667_Y
- attribute \src "libresoc.v:199118.17-199118.91"
- wire $not$libresoc.v:199118$14669_Y
- attribute \src "libresoc.v:199117.17-199117.103"
- wire $reduce_or$libresoc.v:199117$14668_Y
- attribute \src "libresoc.v:199119.17-199119.89"
- wire $reduce_or$libresoc.v:199119$14670_Y
+ attribute \src "libresoc.v:196227.17-196227.89"
+ wire width 2 $not$libresoc.v:196227$14407_Y
+ attribute \src "libresoc.v:196229.17-196229.91"
+ wire $not$libresoc.v:196229$14409_Y
+ attribute \src "libresoc.v:196228.17-196228.103"
+ wire $reduce_or$libresoc.v:196228$14408_Y
+ attribute \src "libresoc.v:196230.17-196230.89"
+ wire $reduce_or$libresoc.v:196230$14410_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199116$14667
+ cell $not $not$libresoc.v:196227$14407
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:199116$14667_Y
+ connect \Y $not$libresoc.v:196227$14407_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199118$14669
+ cell $not $not$libresoc.v:196229$14409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:199118$14669_Y
+ connect \Y $not$libresoc.v:196229$14409_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199117$14668
+ cell $reduce_or $reduce_or$libresoc.v:196228$14408
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:199117$14668_Y
+ connect \Y $reduce_or$libresoc.v:196228$14408_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199119$14670
+ cell $reduce_or $reduce_or$libresoc.v:196230$14410
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199119$14670_Y
+ connect \Y $reduce_or$libresoc.v:196230$14410_Y
end
- connect \$1 $not$libresoc.v:199116$14667_Y
- connect \$4 $reduce_or$libresoc.v:199117$14668_Y
- connect \$3 $not$libresoc.v:199118$14669_Y
- connect \$7 $reduce_or$libresoc.v:199119$14670_Y
+ connect \$1 $not$libresoc.v:196227$14407_Y
+ connect \$4 $reduce_or$libresoc.v:196228$14408_Y
+ connect \$3 $not$libresoc.v:196229$14409_Y
+ connect \$7 $reduce_or$libresoc.v:196230$14410_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:199129.1-199168.10"
+attribute \src "libresoc.v:196240.1-196279.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca"
attribute \generator "nMigen"
module \wrpick_XER_xer_ca
- attribute \src "libresoc.v:199156.17-199156.91"
- wire $not$libresoc.v:199156$14671_Y
- attribute \src "libresoc.v:199158.17-199158.89"
- wire width 3 $not$libresoc.v:199158$14673_Y
- attribute \src "libresoc.v:199160.17-199160.91"
- wire $not$libresoc.v:199160$14675_Y
- attribute \src "libresoc.v:199157.18-199157.90"
- wire $reduce_or$libresoc.v:199157$14672_Y
- attribute \src "libresoc.v:199159.17-199159.103"
- wire $reduce_or$libresoc.v:199159$14674_Y
- attribute \src "libresoc.v:199161.17-199161.105"
- wire $reduce_or$libresoc.v:199161$14676_Y
+ attribute \src "libresoc.v:196267.17-196267.91"
+ wire $not$libresoc.v:196267$14411_Y
+ attribute \src "libresoc.v:196269.17-196269.89"
+ wire width 3 $not$libresoc.v:196269$14413_Y
+ attribute \src "libresoc.v:196271.17-196271.91"
+ wire $not$libresoc.v:196271$14415_Y
+ attribute \src "libresoc.v:196268.18-196268.90"
+ wire $reduce_or$libresoc.v:196268$14412_Y
+ attribute \src "libresoc.v:196270.17-196270.103"
+ wire $reduce_or$libresoc.v:196270$14414_Y
+ attribute \src "libresoc.v:196272.17-196272.105"
+ wire $reduce_or$libresoc.v:196272$14416_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199156$14671
+ cell $not $not$libresoc.v:196267$14411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:199156$14671_Y
+ connect \Y $not$libresoc.v:196267$14411_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199158$14673
+ cell $not $not$libresoc.v:196269$14413
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:199158$14673_Y
+ connect \Y $not$libresoc.v:196269$14413_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199160$14675
+ cell $not $not$libresoc.v:196271$14415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:199160$14675_Y
+ connect \Y $not$libresoc.v:196271$14415_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199157$14672
+ cell $reduce_or $reduce_or$libresoc.v:196268$14412
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199157$14672_Y
+ connect \Y $reduce_or$libresoc.v:196268$14412_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199159$14674
+ cell $reduce_or $reduce_or$libresoc.v:196270$14414
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:199159$14674_Y
+ connect \Y $reduce_or$libresoc.v:196270$14414_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199161$14676
+ cell $reduce_or $reduce_or$libresoc.v:196272$14416
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:199161$14676_Y
- end
- connect \$7 $not$libresoc.v:199156$14671_Y
- connect \$11 $reduce_or$libresoc.v:199157$14672_Y
- connect \$1 $not$libresoc.v:199158$14673_Y
- connect \$4 $reduce_or$libresoc.v:199159$14674_Y
- connect \$3 $not$libresoc.v:199160$14675_Y
- connect \$8 $reduce_or$libresoc.v:199161$14676_Y
+ connect \Y $reduce_or$libresoc.v:196272$14416_Y
+ end
+ connect \$7 $not$libresoc.v:196267$14411_Y
+ connect \$11 $reduce_or$libresoc.v:196268$14412_Y
+ connect \$1 $not$libresoc.v:196269$14413_Y
+ connect \$4 $reduce_or$libresoc.v:196270$14414_Y
+ connect \$3 $not$libresoc.v:196271$14415_Y
+ connect \$8 $reduce_or$libresoc.v:196272$14416_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:199172.1-199220.10"
+attribute \src "libresoc.v:196283.1-196331.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov"
attribute \generator "nMigen"
module \wrpick_XER_xer_ov
- attribute \src "libresoc.v:199205.17-199205.91"
- wire $not$libresoc.v:199205$14677_Y
- attribute \src "libresoc.v:199207.18-199207.93"
- wire $not$libresoc.v:199207$14679_Y
- attribute \src "libresoc.v:199209.17-199209.89"
- wire width 4 $not$libresoc.v:199209$14681_Y
- attribute \src "libresoc.v:199211.17-199211.91"
- wire $not$libresoc.v:199211$14683_Y
- attribute \src "libresoc.v:199206.18-199206.106"
- wire $reduce_or$libresoc.v:199206$14678_Y
- attribute \src "libresoc.v:199208.18-199208.90"
- wire $reduce_or$libresoc.v:199208$14680_Y
- attribute \src "libresoc.v:199210.17-199210.103"
- wire $reduce_or$libresoc.v:199210$14682_Y
- attribute \src "libresoc.v:199212.17-199212.105"
- wire $reduce_or$libresoc.v:199212$14684_Y
+ attribute \src "libresoc.v:196316.17-196316.91"
+ wire $not$libresoc.v:196316$14417_Y
+ attribute \src "libresoc.v:196318.18-196318.93"
+ wire $not$libresoc.v:196318$14419_Y
+ attribute \src "libresoc.v:196320.17-196320.89"
+ wire width 4 $not$libresoc.v:196320$14421_Y
+ attribute \src "libresoc.v:196322.17-196322.91"
+ wire $not$libresoc.v:196322$14423_Y
+ attribute \src "libresoc.v:196317.18-196317.106"
+ wire $reduce_or$libresoc.v:196317$14418_Y
+ attribute \src "libresoc.v:196319.18-196319.90"
+ wire $reduce_or$libresoc.v:196319$14420_Y
+ attribute \src "libresoc.v:196321.17-196321.103"
+ wire $reduce_or$libresoc.v:196321$14422_Y
+ attribute \src "libresoc.v:196323.17-196323.105"
+ wire $reduce_or$libresoc.v:196323$14424_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199205$14677
+ cell $not $not$libresoc.v:196316$14417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:199205$14677_Y
+ connect \Y $not$libresoc.v:196316$14417_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199207$14679
+ cell $not $not$libresoc.v:196318$14419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:199207$14679_Y
+ connect \Y $not$libresoc.v:196318$14419_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199209$14681
+ cell $not $not$libresoc.v:196320$14421
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:199209$14681_Y
+ connect \Y $not$libresoc.v:196320$14421_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199211$14683
+ cell $not $not$libresoc.v:196322$14423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:199211$14683_Y
+ connect \Y $not$libresoc.v:196322$14423_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199206$14678
+ cell $reduce_or $reduce_or$libresoc.v:196317$14418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:199206$14678_Y
+ connect \Y $reduce_or$libresoc.v:196317$14418_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199208$14680
+ cell $reduce_or $reduce_or$libresoc.v:196319$14420
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199208$14680_Y
+ connect \Y $reduce_or$libresoc.v:196319$14420_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199210$14682
+ cell $reduce_or $reduce_or$libresoc.v:196321$14422
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:199210$14682_Y
+ connect \Y $reduce_or$libresoc.v:196321$14422_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199212$14684
+ cell $reduce_or $reduce_or$libresoc.v:196323$14424
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:199212$14684_Y
- end
- connect \$7 $not$libresoc.v:199205$14677_Y
- connect \$12 $reduce_or$libresoc.v:199206$14678_Y
- connect \$11 $not$libresoc.v:199207$14679_Y
- connect \$15 $reduce_or$libresoc.v:199208$14680_Y
- connect \$1 $not$libresoc.v:199209$14681_Y
- connect \$4 $reduce_or$libresoc.v:199210$14682_Y
- connect \$3 $not$libresoc.v:199211$14683_Y
- connect \$8 $reduce_or$libresoc.v:199212$14684_Y
+ connect \Y $reduce_or$libresoc.v:196323$14424_Y
+ end
+ connect \$7 $not$libresoc.v:196316$14417_Y
+ connect \$12 $reduce_or$libresoc.v:196317$14418_Y
+ connect \$11 $not$libresoc.v:196318$14419_Y
+ connect \$15 $reduce_or$libresoc.v:196319$14420_Y
+ connect \$1 $not$libresoc.v:196320$14421_Y
+ connect \$4 $reduce_or$libresoc.v:196321$14422_Y
+ connect \$3 $not$libresoc.v:196322$14423_Y
+ connect \$8 $reduce_or$libresoc.v:196323$14424_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:199224.1-199272.10"
+attribute \src "libresoc.v:196335.1-196383.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so"
attribute \generator "nMigen"
module \wrpick_XER_xer_so
- attribute \src "libresoc.v:199257.17-199257.91"
- wire $not$libresoc.v:199257$14685_Y
- attribute \src "libresoc.v:199259.18-199259.93"
- wire $not$libresoc.v:199259$14687_Y
- attribute \src "libresoc.v:199261.17-199261.89"
- wire width 4 $not$libresoc.v:199261$14689_Y
- attribute \src "libresoc.v:199263.17-199263.91"
- wire $not$libresoc.v:199263$14691_Y
- attribute \src "libresoc.v:199258.18-199258.106"
- wire $reduce_or$libresoc.v:199258$14686_Y
- attribute \src "libresoc.v:199260.18-199260.90"
- wire $reduce_or$libresoc.v:199260$14688_Y
- attribute \src "libresoc.v:199262.17-199262.103"
- wire $reduce_or$libresoc.v:199262$14690_Y
- attribute \src "libresoc.v:199264.17-199264.105"
- wire $reduce_or$libresoc.v:199264$14692_Y
+ attribute \src "libresoc.v:196368.17-196368.91"
+ wire $not$libresoc.v:196368$14425_Y
+ attribute \src "libresoc.v:196370.18-196370.93"
+ wire $not$libresoc.v:196370$14427_Y
+ attribute \src "libresoc.v:196372.17-196372.89"
+ wire width 4 $not$libresoc.v:196372$14429_Y
+ attribute \src "libresoc.v:196374.17-196374.91"
+ wire $not$libresoc.v:196374$14431_Y
+ attribute \src "libresoc.v:196369.18-196369.106"
+ wire $reduce_or$libresoc.v:196369$14426_Y
+ attribute \src "libresoc.v:196371.18-196371.90"
+ wire $reduce_or$libresoc.v:196371$14428_Y
+ attribute \src "libresoc.v:196373.17-196373.103"
+ wire $reduce_or$libresoc.v:196373$14430_Y
+ attribute \src "libresoc.v:196375.17-196375.105"
+ wire $reduce_or$libresoc.v:196375$14432_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199257$14685
+ cell $not $not$libresoc.v:196368$14425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:199257$14685_Y
+ connect \Y $not$libresoc.v:196368$14425_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199259$14687
+ cell $not $not$libresoc.v:196370$14427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:199259$14687_Y
+ connect \Y $not$libresoc.v:196370$14427_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:199261$14689
+ cell $not $not$libresoc.v:196372$14429
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:199261$14689_Y
+ connect \Y $not$libresoc.v:196372$14429_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:199263$14691
+ cell $not $not$libresoc.v:196374$14431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:199263$14691_Y
+ connect \Y $not$libresoc.v:196374$14431_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199258$14686
+ cell $reduce_or $reduce_or$libresoc.v:196369$14426
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:199258$14686_Y
+ connect \Y $reduce_or$libresoc.v:196369$14426_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:199260$14688
+ cell $reduce_or $reduce_or$libresoc.v:196371$14428
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:199260$14688_Y
+ connect \Y $reduce_or$libresoc.v:196371$14428_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199262$14690
+ cell $reduce_or $reduce_or$libresoc.v:196373$14430
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:199262$14690_Y
+ connect \Y $reduce_or$libresoc.v:196373$14430_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:199264$14692
+ cell $reduce_or $reduce_or$libresoc.v:196375$14432
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:199264$14692_Y
- end
- connect \$7 $not$libresoc.v:199257$14685_Y
- connect \$12 $reduce_or$libresoc.v:199258$14686_Y
- connect \$11 $not$libresoc.v:199259$14687_Y
- connect \$15 $reduce_or$libresoc.v:199260$14688_Y
- connect \$1 $not$libresoc.v:199261$14689_Y
- connect \$4 $reduce_or$libresoc.v:199262$14690_Y
- connect \$3 $not$libresoc.v:199263$14691_Y
- connect \$8 $reduce_or$libresoc.v:199264$14692_Y
+ connect \Y $reduce_or$libresoc.v:196375$14432_Y
+ end
+ connect \$7 $not$libresoc.v:196368$14425_Y
+ connect \$12 $reduce_or$libresoc.v:196369$14426_Y
+ connect \$11 $not$libresoc.v:196370$14427_Y
+ connect \$15 $reduce_or$libresoc.v:196371$14428_Y
+ connect \$1 $not$libresoc.v:196372$14429_Y
+ connect \$4 $reduce_or$libresoc.v:196373$14430_Y
+ connect \$3 $not$libresoc.v:196374$14431_Y
+ connect \$8 $reduce_or$libresoc.v:196375$14432_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:199276.1-199596.10"
+attribute \src "libresoc.v:196387.1-196707.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer"
attribute \generator "nMigen"
module \xer
- attribute \src "libresoc.v:199277.7-199277.20"
+ attribute \src "libresoc.v:196388.7-196388.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:199556.3-199564.6"
- wire width 3 $0\ren_delay$11$next[2:0]$14716
- attribute \src "libresoc.v:199454.3-199455.43"
- wire width 3 $0\ren_delay$11[2:0]$14705
- attribute \src "libresoc.v:199413.13-199413.34"
- wire width 3 $0\ren_delay$11[2:0]$14722
- attribute \src "libresoc.v:199518.3-199526.6"
- wire width 3 $0\ren_delay$18$next[2:0]$14708
- attribute \src "libresoc.v:199452.3-199453.43"
- wire width 3 $0\ren_delay$18[2:0]$14703
- attribute \src "libresoc.v:199417.13-199417.34"
- wire width 3 $0\ren_delay$18[2:0]$14724
- attribute \src "libresoc.v:199537.3-199545.6"
- wire width 3 $0\ren_delay$next[2:0]$14712
- attribute \src "libresoc.v:199456.3-199457.35"
+ attribute \src "libresoc.v:196667.3-196675.6"
+ wire width 3 $0\ren_delay$11$next[2:0]$14456
+ attribute \src "libresoc.v:196565.3-196566.43"
+ wire width 3 $0\ren_delay$11[2:0]$14445
+ attribute \src "libresoc.v:196524.13-196524.34"
+ wire width 3 $0\ren_delay$11[2:0]$14462
+ attribute \src "libresoc.v:196629.3-196637.6"
+ wire width 3 $0\ren_delay$18$next[2:0]$14448
+ attribute \src "libresoc.v:196563.3-196564.43"
+ wire width 3 $0\ren_delay$18[2:0]$14443
+ attribute \src "libresoc.v:196528.13-196528.34"
+ wire width 3 $0\ren_delay$18[2:0]$14464
+ attribute \src "libresoc.v:196648.3-196656.6"
+ wire width 3 $0\ren_delay$next[2:0]$14452
+ attribute \src "libresoc.v:196567.3-196568.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:199546.3-199555.6"
+ attribute \src "libresoc.v:196657.3-196666.6"
wire width 2 $0\src1__data_o[1:0]
- attribute \src "libresoc.v:199565.3-199574.6"
+ attribute \src "libresoc.v:196676.3-196685.6"
wire width 2 $0\src2__data_o[1:0]
- attribute \src "libresoc.v:199527.3-199536.6"
+ attribute \src "libresoc.v:196638.3-196647.6"
wire width 2 $0\src3__data_o[1:0]
- attribute \src "libresoc.v:199556.3-199564.6"
- wire width 3 $1\ren_delay$11$next[2:0]$14717
- attribute \src "libresoc.v:199518.3-199526.6"
- wire width 3 $1\ren_delay$18$next[2:0]$14709
- attribute \src "libresoc.v:199537.3-199545.6"
- wire width 3 $1\ren_delay$next[2:0]$14713
- attribute \src "libresoc.v:199411.13-199411.29"
+ attribute \src "libresoc.v:196667.3-196675.6"
+ wire width 3 $1\ren_delay$11$next[2:0]$14457
+ attribute \src "libresoc.v:196629.3-196637.6"
+ wire width 3 $1\ren_delay$18$next[2:0]$14449
+ attribute \src "libresoc.v:196648.3-196656.6"
+ wire width 3 $1\ren_delay$next[2:0]$14453
+ attribute \src "libresoc.v:196522.13-196522.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:199546.3-199555.6"
+ attribute \src "libresoc.v:196657.3-196666.6"
wire width 2 $1\src1__data_o[1:0]
- attribute \src "libresoc.v:199565.3-199574.6"
+ attribute \src "libresoc.v:196676.3-196685.6"
wire width 2 $1\src2__data_o[1:0]
- attribute \src "libresoc.v:199527.3-199536.6"
+ attribute \src "libresoc.v:196638.3-196647.6"
wire width 2 $1\src3__data_o[1:0]
- attribute \src "libresoc.v:199443.17-199443.109"
- wire width 2 $or$libresoc.v:199443$14693_Y
- attribute \src "libresoc.v:199445.18-199445.126"
- wire width 2 $or$libresoc.v:199445$14695_Y
- attribute \src "libresoc.v:199446.18-199446.111"
- wire width 2 $or$libresoc.v:199446$14696_Y
- attribute \src "libresoc.v:199448.18-199448.126"
- wire width 2 $or$libresoc.v:199448$14698_Y
- attribute \src "libresoc.v:199449.18-199449.111"
- wire width 2 $or$libresoc.v:199449$14699_Y
- attribute \src "libresoc.v:199451.17-199451.125"
- wire width 2 $or$libresoc.v:199451$14701_Y
- attribute \src "libresoc.v:199444.18-199444.100"
- wire $reduce_or$libresoc.v:199444$14694_Y
- attribute \src "libresoc.v:199447.18-199447.100"
- wire $reduce_or$libresoc.v:199447$14697_Y
- attribute \src "libresoc.v:199450.17-199450.95"
- wire $reduce_or$libresoc.v:199450$14700_Y
+ attribute \src "libresoc.v:196554.17-196554.109"
+ wire width 2 $or$libresoc.v:196554$14433_Y
+ attribute \src "libresoc.v:196556.18-196556.126"
+ wire width 2 $or$libresoc.v:196556$14435_Y
+ attribute \src "libresoc.v:196557.18-196557.111"
+ wire width 2 $or$libresoc.v:196557$14436_Y
+ attribute \src "libresoc.v:196559.18-196559.126"
+ wire width 2 $or$libresoc.v:196559$14438_Y
+ attribute \src "libresoc.v:196560.18-196560.111"
+ wire width 2 $or$libresoc.v:196560$14439_Y
+ attribute \src "libresoc.v:196562.17-196562.125"
+ wire width 2 $or$libresoc.v:196562$14441_Y
+ attribute \src "libresoc.v:196555.18-196555.100"
+ wire $reduce_or$libresoc.v:196555$14434_Y
+ attribute \src "libresoc.v:196558.18-196558.100"
+ wire $reduce_or$libresoc.v:196558$14437_Y
+ attribute \src "libresoc.v:196561.17-196561.95"
+ wire $reduce_or$libresoc.v:196561$14440_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$12
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 10 \data_i
wire width 6 \full_wr__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \full_wr__wen
- attribute \src "libresoc.v:199277.7-199277.15"
+ attribute \src "libresoc.v:196388.7-196388.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 \reg_0_dest10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:199443$14693
+ cell $or $or$libresoc.v:196554$14433
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src10__data_o
connect \B \$7
- connect \Y $or$libresoc.v:199443$14693_Y
+ connect \Y $or$libresoc.v:196554$14433_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:199445$14695
+ cell $or $or$libresoc.v:196556$14435
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src21__data_o
connect \B \reg_2_src22__data_o
- connect \Y $or$libresoc.v:199445$14695_Y
+ connect \Y $or$libresoc.v:196556$14435_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:199446$14696
+ cell $or $or$libresoc.v:196557$14436
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src20__data_o
connect \B \$14
- connect \Y $or$libresoc.v:199446$14696_Y
+ connect \Y $or$libresoc.v:196557$14436_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:199448$14698
+ cell $or $or$libresoc.v:196559$14438
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src31__data_o
connect \B \reg_2_src32__data_o
- connect \Y $or$libresoc.v:199448$14698_Y
+ connect \Y $or$libresoc.v:196559$14438_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:199449$14699
+ cell $or $or$libresoc.v:196560$14439
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src30__data_o
connect \B \$21
- connect \Y $or$libresoc.v:199449$14699_Y
+ connect \Y $or$libresoc.v:196560$14439_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:199451$14701
+ cell $or $or$libresoc.v:196562$14441
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src11__data_o
connect \B \reg_2_src12__data_o
- connect \Y $or$libresoc.v:199451$14701_Y
+ connect \Y $or$libresoc.v:196562$14441_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:199444$14694
+ cell $reduce_or $reduce_or$libresoc.v:196555$14434
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$11
- connect \Y $reduce_or$libresoc.v:199444$14694_Y
+ connect \Y $reduce_or$libresoc.v:196555$14434_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:199447$14697
+ cell $reduce_or $reduce_or$libresoc.v:196558$14437
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$18
- connect \Y $reduce_or$libresoc.v:199447$14697_Y
+ connect \Y $reduce_or$libresoc.v:196558$14437_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:199450$14700
+ cell $reduce_or $reduce_or$libresoc.v:196561$14440
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:199450$14700_Y
+ connect \Y $reduce_or$libresoc.v:196561$14440_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199458.15-199477.4"
+ attribute \src "libresoc.v:196569.15-196588.4"
cell \reg_0$132 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w0__wen \reg_0_w0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199478.15-199497.4"
+ attribute \src "libresoc.v:196589.15-196608.4"
cell \reg_1$133 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w1__wen \reg_1_w1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:199498.15-199517.4"
+ attribute \src "libresoc.v:196609.15-196628.4"
cell \reg_2$134 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w2__data_i \reg_2_w2__data_i
connect \w2__wen \reg_2_w2__wen
end
- attribute \src "libresoc.v:199277.7-199277.20"
- process $proc$libresoc.v:199277$14719
+ attribute \src "libresoc.v:196388.7-196388.20"
+ process $proc$libresoc.v:196388$14459
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:199411.13-199411.29"
- process $proc$libresoc.v:199411$14720
+ attribute \src "libresoc.v:196522.13-196522.29"
+ process $proc$libresoc.v:196522$14460
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:199413.13-199413.34"
- process $proc$libresoc.v:199413$14721
+ attribute \src "libresoc.v:196524.13-196524.34"
+ process $proc$libresoc.v:196524$14461
assign { } { }
- assign $0\ren_delay$11[2:0]$14722 3'000
+ assign $0\ren_delay$11[2:0]$14462 3'000
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[2:0]$14722
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14462
end
- attribute \src "libresoc.v:199417.13-199417.34"
- process $proc$libresoc.v:199417$14723
+ attribute \src "libresoc.v:196528.13-196528.34"
+ process $proc$libresoc.v:196528$14463
assign { } { }
- assign $0\ren_delay$18[2:0]$14724 3'000
+ assign $0\ren_delay$18[2:0]$14464 3'000
sync always
sync init
- update \ren_delay$18 $0\ren_delay$18[2:0]$14724
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14464
end
- attribute \src "libresoc.v:199452.3-199453.43"
- process $proc$libresoc.v:199452$14702
+ attribute \src "libresoc.v:196563.3-196564.43"
+ process $proc$libresoc.v:196563$14442
assign { } { }
- assign $0\ren_delay$18[2:0]$14703 \ren_delay$18$next
+ assign $0\ren_delay$18[2:0]$14443 \ren_delay$18$next
sync posedge \coresync_clk
- update \ren_delay$18 $0\ren_delay$18[2:0]$14703
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14443
end
- attribute \src "libresoc.v:199454.3-199455.43"
- process $proc$libresoc.v:199454$14704
+ attribute \src "libresoc.v:196565.3-196566.43"
+ process $proc$libresoc.v:196565$14444
assign { } { }
- assign $0\ren_delay$11[2:0]$14705 \ren_delay$11$next
+ assign $0\ren_delay$11[2:0]$14445 \ren_delay$11$next
sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[2:0]$14705
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14445
end
- attribute \src "libresoc.v:199456.3-199457.35"
- process $proc$libresoc.v:199456$14706
+ attribute \src "libresoc.v:196567.3-196568.35"
+ process $proc$libresoc.v:196567$14446
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:199518.3-199526.6"
- process $proc$libresoc.v:199518$14707
+ attribute \src "libresoc.v:196629.3-196637.6"
+ process $proc$libresoc.v:196629$14447
assign { } { }
assign { } { }
- assign $0\ren_delay$18$next[2:0]$14708 $1\ren_delay$18$next[2:0]$14709
- attribute \src "libresoc.v:199519.5-199519.29"
+ assign $0\ren_delay$18$next[2:0]$14448 $1\ren_delay$18$next[2:0]$14449
+ attribute \src "libresoc.v:196630.5-196630.29"
switch \initial
- attribute \src "libresoc.v:199519.9-199519.17"
+ attribute \src "libresoc.v:196630.9-196630.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$18$next[2:0]$14709 3'000
+ assign $1\ren_delay$18$next[2:0]$14449 3'000
case
- assign $1\ren_delay$18$next[2:0]$14709 \src3__ren
+ assign $1\ren_delay$18$next[2:0]$14449 \src3__ren
end
sync always
- update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14708
+ update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14448
end
- attribute \src "libresoc.v:199527.3-199536.6"
- process $proc$libresoc.v:199527$14710
+ attribute \src "libresoc.v:196638.3-196647.6"
+ process $proc$libresoc.v:196638$14450
assign { } { }
assign { } { }
assign $0\src3__data_o[1:0] $1\src3__data_o[1:0]
- attribute \src "libresoc.v:199528.5-199528.29"
+ attribute \src "libresoc.v:196639.5-196639.29"
switch \initial
- attribute \src "libresoc.v:199528.9-199528.17"
+ attribute \src "libresoc.v:196639.9-196639.17"
case 1'1
case
end
sync always
update \src3__data_o $0\src3__data_o[1:0]
end
- attribute \src "libresoc.v:199537.3-199545.6"
- process $proc$libresoc.v:199537$14711
+ attribute \src "libresoc.v:196648.3-196656.6"
+ process $proc$libresoc.v:196648$14451
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$14712 $1\ren_delay$next[2:0]$14713
- attribute \src "libresoc.v:199538.5-199538.29"
+ assign $0\ren_delay$next[2:0]$14452 $1\ren_delay$next[2:0]$14453
+ attribute \src "libresoc.v:196649.5-196649.29"
switch \initial
- attribute \src "libresoc.v:199538.9-199538.17"
+ attribute \src "libresoc.v:196649.9-196649.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$14713 3'000
+ assign $1\ren_delay$next[2:0]$14453 3'000
case
- assign $1\ren_delay$next[2:0]$14713 \src1__ren
+ assign $1\ren_delay$next[2:0]$14453 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$14712
+ update \ren_delay$next $0\ren_delay$next[2:0]$14452
end
- attribute \src "libresoc.v:199546.3-199555.6"
- process $proc$libresoc.v:199546$14714
+ attribute \src "libresoc.v:196657.3-196666.6"
+ process $proc$libresoc.v:196657$14454
assign { } { }
assign { } { }
assign $0\src1__data_o[1:0] $1\src1__data_o[1:0]
- attribute \src "libresoc.v:199547.5-199547.29"
+ attribute \src "libresoc.v:196658.5-196658.29"
switch \initial
- attribute \src "libresoc.v:199547.9-199547.17"
+ attribute \src "libresoc.v:196658.9-196658.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[1:0]
end
- attribute \src "libresoc.v:199556.3-199564.6"
- process $proc$libresoc.v:199556$14715
+ attribute \src "libresoc.v:196667.3-196675.6"
+ process $proc$libresoc.v:196667$14455
assign { } { }
assign { } { }
- assign $0\ren_delay$11$next[2:0]$14716 $1\ren_delay$11$next[2:0]$14717
- attribute \src "libresoc.v:199557.5-199557.29"
+ assign $0\ren_delay$11$next[2:0]$14456 $1\ren_delay$11$next[2:0]$14457
+ attribute \src "libresoc.v:196668.5-196668.29"
switch \initial
- attribute \src "libresoc.v:199557.9-199557.17"
+ attribute \src "libresoc.v:196668.9-196668.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$11$next[2:0]$14717 3'000
+ assign $1\ren_delay$11$next[2:0]$14457 3'000
case
- assign $1\ren_delay$11$next[2:0]$14717 \src2__ren
+ assign $1\ren_delay$11$next[2:0]$14457 \src2__ren
end
sync always
- update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14716
+ update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14456
end
- attribute \src "libresoc.v:199565.3-199574.6"
- process $proc$libresoc.v:199565$14718
+ attribute \src "libresoc.v:196676.3-196685.6"
+ process $proc$libresoc.v:196676$14458
assign { } { }
assign { } { }
assign $0\src2__data_o[1:0] $1\src2__data_o[1:0]
- attribute \src "libresoc.v:199566.5-199566.29"
+ attribute \src "libresoc.v:196677.5-196677.29"
switch \initial
- attribute \src "libresoc.v:199566.9-199566.17"
+ attribute \src "libresoc.v:196677.9-196677.17"
case 1'1
case
end
sync always
update \src2__data_o $0\src2__data_o[1:0]
end
- connect \$9 $or$libresoc.v:199443$14693_Y
- connect \$12 $reduce_or$libresoc.v:199444$14694_Y
- connect \$14 $or$libresoc.v:199445$14695_Y
- connect \$16 $or$libresoc.v:199446$14696_Y
- connect \$19 $reduce_or$libresoc.v:199447$14697_Y
- connect \$21 $or$libresoc.v:199448$14698_Y
- connect \$23 $or$libresoc.v:199449$14699_Y
- connect \$5 $reduce_or$libresoc.v:199450$14700_Y
- connect \$7 $or$libresoc.v:199451$14701_Y
+ connect \$9 $or$libresoc.v:196554$14433_Y
+ connect \$12 $reduce_or$libresoc.v:196555$14434_Y
+ connect \$14 $or$libresoc.v:196556$14435_Y
+ connect \$16 $or$libresoc.v:196557$14436_Y
+ connect \$19 $reduce_or$libresoc.v:196558$14437_Y
+ connect \$21 $or$libresoc.v:196559$14438_Y
+ connect \$23 $or$libresoc.v:196560$14439_Y
+ connect \$5 $reduce_or$libresoc.v:196561$14440_Y
+ connect \$7 $or$libresoc.v:196562$14441_Y
connect \full_wr__data_i 6'000000
connect \full_wr__wen 3'000
connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000
connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
end
-attribute \src "libresoc.v:199600.1-199914.10"
+attribute \src "libresoc.v:196711.1-197025.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:199778.3-199806.6"
+ attribute \src "libresoc.v:196889.3-196917.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:199829.3-199837.6"
- wire $0\core_irq_o$next[0:0]$14760
- attribute \src "libresoc.v:199720.3-199721.37"
+ attribute \src "libresoc.v:196940.3-196948.6"
+ wire $0\core_irq_o$next[0:0]$14500
+ attribute \src "libresoc.v:196831.3-196832.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $0\cppr$10[7:0]$14764
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 8 $0\cppr$next[7:0]$14743
- attribute \src "libresoc.v:199724.3-199725.25"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $0\cppr$10[7:0]$14504
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 8 $0\cppr$next[7:0]$14483
+ attribute \src "libresoc.v:196835.3-196836.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:199838.3-199847.6"
+ attribute \src "libresoc.v:196949.3-196958.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:199601.7-199601.20"
+ attribute \src "libresoc.v:196712.7-196712.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire $0\irq$12[0:0]$14765
- attribute \src "libresoc.v:199734.3-199749.6"
- wire $0\irq$next[0:0]$14744
- attribute \src "libresoc.v:199728.3-199729.23"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire $0\irq$12[0:0]$14505
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire $0\irq$next[0:0]$14484
+ attribute \src "libresoc.v:196839.3-196840.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $0\mfrr$11[7:0]$14766
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 8 $0\mfrr$next[7:0]$14745
- attribute \src "libresoc.v:199726.3-199727.25"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $0\mfrr$11[7:0]$14506
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 8 $0\mfrr$next[7:0]$14485
+ attribute \src "libresoc.v:196837.3-196838.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:199817.3-199828.6"
+ attribute \src "libresoc.v:196928.3-196939.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:199807.3-199816.6"
+ attribute \src "libresoc.v:196918.3-196927.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire $0\wb_ack$14[0:0]$14767
- attribute \src "libresoc.v:199734.3-199749.6"
- wire $0\wb_ack$next[0:0]$14746
- attribute \src "libresoc.v:199732.3-199733.29"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire $0\wb_ack$14[0:0]$14507
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire $0\wb_ack$next[0:0]$14486
+ attribute \src "libresoc.v:196843.3-196844.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 32 $0\wb_rd_data$13[31:0]$14768
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 32 $0\wb_rd_data$next[31:0]$14747
- attribute \src "libresoc.v:199730.3-199731.37"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 32 $0\wb_rd_data$13[31:0]$14508
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 32 $0\wb_rd_data$next[31:0]$14487
+ attribute \src "libresoc.v:196841.3-196842.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:199750.3-199777.6"
+ attribute \src "libresoc.v:196861.3-196888.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 24 $0\xisr$9[23:0]$14769
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 24 $0\xisr$next[23:0]$14748
- attribute \src "libresoc.v:199722.3-199723.25"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 24 $0\xisr$9[23:0]$14509
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 24 $0\xisr$next[23:0]$14488
+ attribute \src "libresoc.v:196833.3-196834.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:199778.3-199806.6"
+ attribute \src "libresoc.v:196889.3-196917.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:199829.3-199837.6"
- wire $1\core_irq_o$next[0:0]$14761
- attribute \src "libresoc.v:199630.7-199630.24"
+ attribute \src "libresoc.v:196940.3-196948.6"
+ wire $1\core_irq_o$next[0:0]$14501
+ attribute \src "libresoc.v:196741.7-196741.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $1\cppr$10[7:0]$14770
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 8 $1\cppr$next[7:0]$14749
- attribute \src "libresoc.v:199634.13-199634.25"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $1\cppr$10[7:0]$14510
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 8 $1\cppr$next[7:0]$14489
+ attribute \src "libresoc.v:196745.13-196745.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:199838.3-199847.6"
+ attribute \src "libresoc.v:196949.3-196958.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire $1\irq$12[0:0]$14780
- attribute \src "libresoc.v:199734.3-199749.6"
- wire $1\irq$next[0:0]$14750
- attribute \src "libresoc.v:199663.7-199663.17"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire $1\irq$12[0:0]$14520
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire $1\irq$next[0:0]$14490
+ attribute \src "libresoc.v:196774.7-196774.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $1\mfrr$11[7:0]$14771
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 8 $1\mfrr$next[7:0]$14751
- attribute \src "libresoc.v:199671.13-199671.25"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $1\mfrr$11[7:0]$14511
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 8 $1\mfrr$next[7:0]$14491
+ attribute \src "libresoc.v:196782.13-196782.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:199817.3-199828.6"
+ attribute \src "libresoc.v:196928.3-196939.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:199807.3-199816.6"
+ attribute \src "libresoc.v:196918.3-196927.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire $1\wb_ack$14[0:0]$14772
- attribute \src "libresoc.v:199734.3-199749.6"
- wire $1\wb_ack$next[0:0]$14752
- attribute \src "libresoc.v:199685.7-199685.20"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire $1\wb_ack$14[0:0]$14512
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire $1\wb_ack$next[0:0]$14492
+ attribute \src "libresoc.v:196796.7-196796.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 32 $1\wb_rd_data$next[31:0]$14753
- attribute \src "libresoc.v:199693.14-199693.32"
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 32 $1\wb_rd_data$next[31:0]$14493
+ attribute \src "libresoc.v:196804.14-196804.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:199750.3-199777.6"
+ attribute \src "libresoc.v:196861.3-196888.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 24 $1\xisr$9[23:0]$14777
- attribute \src "libresoc.v:199734.3-199749.6"
- wire width 24 $1\xisr$next[23:0]$14754
- attribute \src "libresoc.v:199703.14-199703.31"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 24 $1\xisr$9[23:0]$14517
+ attribute \src "libresoc.v:196845.3-196860.6"
+ wire width 24 $1\xisr$next[23:0]$14494
+ attribute \src "libresoc.v:196814.14-196814.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:199778.3-199806.6"
+ attribute \src "libresoc.v:196889.3-196917.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $2\cppr$10[7:0]$14773
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $2\mfrr$11[7:0]$14774
- attribute \src "libresoc.v:199750.3-199777.6"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $2\cppr$10[7:0]$14513
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $2\mfrr$11[7:0]$14514
+ attribute \src "libresoc.v:196861.3-196888.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 24 $2\xisr$9[23:0]$14778
- attribute \src "libresoc.v:199778.3-199806.6"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 24 $2\xisr$9[23:0]$14518
+ attribute \src "libresoc.v:196889.3-196917.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $3\cppr$10[7:0]$14775
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $3\mfrr$11[7:0]$14776
- attribute \src "libresoc.v:199750.3-199777.6"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $3\cppr$10[7:0]$14515
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $3\mfrr$11[7:0]$14516
+ attribute \src "libresoc.v:196861.3-196888.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199848.3-199910.6"
- wire width 8 $4\cppr$10[7:0]$14779
- attribute \src "libresoc.v:199750.3-199777.6"
+ attribute \src "libresoc.v:196959.3-197021.6"
+ wire width 8 $4\cppr$10[7:0]$14519
+ attribute \src "libresoc.v:196861.3-196888.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199710.18-199710.116"
- wire $and$libresoc.v:199710$14725_Y
- attribute \src "libresoc.v:199714.18-199714.116"
- wire $and$libresoc.v:199714$14729_Y
- attribute \src "libresoc.v:199716.18-199716.116"
- wire $and$libresoc.v:199716$14731_Y
- attribute \src "libresoc.v:199719.17-199719.109"
- wire $and$libresoc.v:199719$14734_Y
- attribute \src "libresoc.v:199715.18-199715.110"
- wire $eq$libresoc.v:199715$14730_Y
- attribute \src "libresoc.v:199712.18-199712.114"
- wire $lt$libresoc.v:199712$14727_Y
- attribute \src "libresoc.v:199713.18-199713.109"
- wire $lt$libresoc.v:199713$14728_Y
- attribute \src "libresoc.v:199718.18-199718.114"
- wire $lt$libresoc.v:199718$14733_Y
- attribute \src "libresoc.v:199711.18-199711.109"
- wire $ne$libresoc.v:199711$14726_Y
- attribute \src "libresoc.v:199717.18-199717.109"
- wire $ne$libresoc.v:199717$14732_Y
+ attribute \src "libresoc.v:196821.18-196821.116"
+ wire $and$libresoc.v:196821$14465_Y
+ attribute \src "libresoc.v:196825.18-196825.116"
+ wire $and$libresoc.v:196825$14469_Y
+ attribute \src "libresoc.v:196827.18-196827.116"
+ wire $and$libresoc.v:196827$14471_Y
+ attribute \src "libresoc.v:196830.17-196830.109"
+ wire $and$libresoc.v:196830$14474_Y
+ attribute \src "libresoc.v:196826.18-196826.110"
+ wire $eq$libresoc.v:196826$14470_Y
+ attribute \src "libresoc.v:196823.18-196823.114"
+ wire $lt$libresoc.v:196823$14467_Y
+ attribute \src "libresoc.v:196824.18-196824.109"
+ wire $lt$libresoc.v:196824$14468_Y
+ attribute \src "libresoc.v:196829.18-196829.114"
+ wire $lt$libresoc.v:196829$14473_Y
+ attribute \src "libresoc.v:196822.18-196822.109"
+ wire $ne$libresoc.v:196822$14466_Y
+ attribute \src "libresoc.v:196828.18-196828.109"
+ wire $ne$libresoc.v:196828$14472_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
wire input 13 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
- wire output 4 \core_irq_o
+ wire output 3 \core_irq_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire \core_irq_o$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire input 10 \icp_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
- wire width 8 input 3 \ics_i_pri
+ wire width 8 input 2 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
- wire width 4 input 2 \ics_i_src
- attribute \src "libresoc.v:199601.7-199601.15"
+ wire width 4 input 1 \ics_i_src
+ attribute \src "libresoc.v:196712.7-196712.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
wire width 8 \min_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
wire width 8 \pending_priority
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 4 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
wire \wb_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:199710$14725
+ cell $and $and$libresoc.v:196821$14465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:199710$14725_Y
+ connect \Y $and$libresoc.v:196821$14465_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:199714$14729
+ cell $and $and$libresoc.v:196825$14469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:199714$14729_Y
+ connect \Y $and$libresoc.v:196825$14469_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:199716$14731
+ cell $and $and$libresoc.v:196827$14471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:199716$14731_Y
+ connect \Y $and$libresoc.v:196827$14471_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:199719$14734
+ cell $and $and$libresoc.v:196830$14474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:199719$14734_Y
+ connect \Y $and$libresoc.v:196830$14474_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:199715$14730
+ cell $eq $eq$libresoc.v:196826$14470
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:199715$14730_Y
+ connect \Y $eq$libresoc.v:196826$14470_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:199712$14727
+ cell $lt $lt$libresoc.v:196823$14467
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:199712$14727_Y
+ connect \Y $lt$libresoc.v:196823$14467_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:199713$14728
+ cell $lt $lt$libresoc.v:196824$14468
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:199713$14728_Y
+ connect \Y $lt$libresoc.v:196824$14468_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:199718$14733
+ cell $lt $lt$libresoc.v:196829$14473
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:199718$14733_Y
+ connect \Y $lt$libresoc.v:196829$14473_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:199711$14726
+ cell $ne $ne$libresoc.v:196822$14466
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:199711$14726_Y
+ connect \Y $ne$libresoc.v:196822$14466_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:199717$14732
+ cell $ne $ne$libresoc.v:196828$14472
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:199717$14732_Y
+ connect \Y $ne$libresoc.v:196828$14472_Y
end
- attribute \src "libresoc.v:199601.7-199601.20"
- process $proc$libresoc.v:199601$14781
+ attribute \src "libresoc.v:196712.7-196712.20"
+ process $proc$libresoc.v:196712$14521
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:199630.7-199630.24"
- process $proc$libresoc.v:199630$14782
+ attribute \src "libresoc.v:196741.7-196741.24"
+ process $proc$libresoc.v:196741$14522
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:199634.13-199634.25"
- process $proc$libresoc.v:199634$14783
+ attribute \src "libresoc.v:196745.13-196745.25"
+ process $proc$libresoc.v:196745$14523
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:199663.7-199663.17"
- process $proc$libresoc.v:199663$14784
+ attribute \src "libresoc.v:196774.7-196774.17"
+ process $proc$libresoc.v:196774$14524
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:199671.13-199671.25"
- process $proc$libresoc.v:199671$14785
+ attribute \src "libresoc.v:196782.13-196782.25"
+ process $proc$libresoc.v:196782$14525
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:199685.7-199685.20"
- process $proc$libresoc.v:199685$14786
+ attribute \src "libresoc.v:196796.7-196796.20"
+ process $proc$libresoc.v:196796$14526
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:199693.14-199693.32"
- process $proc$libresoc.v:199693$14787
+ attribute \src "libresoc.v:196804.14-196804.32"
+ process $proc$libresoc.v:196804$14527
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:199703.14-199703.31"
- process $proc$libresoc.v:199703$14788
+ attribute \src "libresoc.v:196814.14-196814.31"
+ process $proc$libresoc.v:196814$14528
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:199720.3-199721.37"
- process $proc$libresoc.v:199720$14735
+ attribute \src "libresoc.v:196831.3-196832.37"
+ process $proc$libresoc.v:196831$14475
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
sync posedge \clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:199722.3-199723.25"
- process $proc$libresoc.v:199722$14736
+ attribute \src "libresoc.v:196833.3-196834.25"
+ process $proc$libresoc.v:196833$14476
assign { } { }
assign $0\xisr[23:0] \xisr$next
sync posedge \clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:199724.3-199725.25"
- process $proc$libresoc.v:199724$14737
+ attribute \src "libresoc.v:196835.3-196836.25"
+ process $proc$libresoc.v:196835$14477
assign { } { }
assign $0\cppr[7:0] \cppr$next
sync posedge \clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:199726.3-199727.25"
- process $proc$libresoc.v:199726$14738
+ attribute \src "libresoc.v:196837.3-196838.25"
+ process $proc$libresoc.v:196837$14478
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
sync posedge \clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:199728.3-199729.23"
- process $proc$libresoc.v:199728$14739
+ attribute \src "libresoc.v:196839.3-196840.23"
+ process $proc$libresoc.v:196839$14479
assign { } { }
assign $0\irq[0:0] \irq$next
sync posedge \clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:199730.3-199731.37"
- process $proc$libresoc.v:199730$14740
+ attribute \src "libresoc.v:196841.3-196842.37"
+ process $proc$libresoc.v:196841$14480
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
sync posedge \clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:199732.3-199733.29"
- process $proc$libresoc.v:199732$14741
+ attribute \src "libresoc.v:196843.3-196844.29"
+ process $proc$libresoc.v:196843$14481
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
sync posedge \clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:199734.3-199749.6"
- process $proc$libresoc.v:199734$14742
+ attribute \src "libresoc.v:196845.3-196860.6"
+ process $proc$libresoc.v:196845$14482
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cppr$next[7:0]$14743 $1\cppr$next[7:0]$14749
- assign $0\irq$next[0:0]$14744 $1\irq$next[0:0]$14750
- assign $0\mfrr$next[7:0]$14745 $1\mfrr$next[7:0]$14751
- assign $0\wb_ack$next[0:0]$14746 $1\wb_ack$next[0:0]$14752
- assign $0\wb_rd_data$next[31:0]$14747 $1\wb_rd_data$next[31:0]$14753
- assign $0\xisr$next[23:0]$14748 $1\xisr$next[23:0]$14754
- attribute \src "libresoc.v:199735.5-199735.29"
+ assign $0\cppr$next[7:0]$14483 $1\cppr$next[7:0]$14489
+ assign $0\irq$next[0:0]$14484 $1\irq$next[0:0]$14490
+ assign $0\mfrr$next[7:0]$14485 $1\mfrr$next[7:0]$14491
+ assign $0\wb_ack$next[0:0]$14486 $1\wb_ack$next[0:0]$14492
+ assign $0\wb_rd_data$next[31:0]$14487 $1\wb_rd_data$next[31:0]$14493
+ assign $0\xisr$next[23:0]$14488 $1\xisr$next[23:0]$14494
+ attribute \src "libresoc.v:196846.5-196846.29"
switch \initial
- attribute \src "libresoc.v:199735.9-199735.17"
+ attribute \src "libresoc.v:196846.9-196846.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xisr$next[23:0]$14754 24'000000000000000000000000
- assign $1\cppr$next[7:0]$14749 8'00000000
- assign $1\mfrr$next[7:0]$14751 8'11111111
- assign $1\irq$next[0:0]$14750 1'0
- assign $1\wb_rd_data$next[31:0]$14753 0
- assign $1\wb_ack$next[0:0]$14752 1'0
+ assign $1\xisr$next[23:0]$14494 24'000000000000000000000000
+ assign $1\cppr$next[7:0]$14489 8'00000000
+ assign $1\mfrr$next[7:0]$14491 8'11111111
+ assign $1\irq$next[0:0]$14490 1'0
+ assign $1\wb_rd_data$next[31:0]$14493 0
+ assign $1\wb_ack$next[0:0]$14492 1'0
case
- assign $1\cppr$next[7:0]$14749 \cppr$2
- assign $1\irq$next[0:0]$14750 \irq$4
- assign $1\mfrr$next[7:0]$14751 \mfrr$3
- assign $1\wb_ack$next[0:0]$14752 \wb_ack$6
- assign $1\wb_rd_data$next[31:0]$14753 \wb_rd_data$5
- assign $1\xisr$next[23:0]$14754 \xisr$1
+ assign $1\cppr$next[7:0]$14489 \cppr$2
+ assign $1\irq$next[0:0]$14490 \irq$4
+ assign $1\mfrr$next[7:0]$14491 \mfrr$3
+ assign $1\wb_ack$next[0:0]$14492 \wb_ack$6
+ assign $1\wb_rd_data$next[31:0]$14493 \wb_rd_data$5
+ assign $1\xisr$next[23:0]$14494 \xisr$1
end
sync always
- update \cppr$next $0\cppr$next[7:0]$14743
- update \irq$next $0\irq$next[0:0]$14744
- update \mfrr$next $0\mfrr$next[7:0]$14745
- update \wb_ack$next $0\wb_ack$next[0:0]$14746
- update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14747
- update \xisr$next $0\xisr$next[23:0]$14748
+ update \cppr$next $0\cppr$next[7:0]$14483
+ update \irq$next $0\irq$next[0:0]$14484
+ update \mfrr$next $0\mfrr$next[7:0]$14485
+ update \wb_ack$next $0\wb_ack$next[0:0]$14486
+ update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14487
+ update \xisr$next $0\xisr$next[23:0]$14488
end
- attribute \src "libresoc.v:199750.3-199777.6"
- process $proc$libresoc.v:199750$14755
+ attribute \src "libresoc.v:196861.3-196888.6"
+ process $proc$libresoc.v:196861$14495
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:199751.5-199751.29"
+ attribute \src "libresoc.v:196862.5-196862.29"
switch \initial
- attribute \src "libresoc.v:199751.9-199751.17"
+ attribute \src "libresoc.v:196862.9-196862.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:199778.3-199806.6"
- process $proc$libresoc.v:199778$14756
+ attribute \src "libresoc.v:196889.3-196917.6"
+ process $proc$libresoc.v:196889$14496
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:199779.5-199779.29"
+ attribute \src "libresoc.v:196890.5-196890.29"
switch \initial
- attribute \src "libresoc.v:199779.9-199779.17"
+ attribute \src "libresoc.v:196890.9-196890.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:199807.3-199816.6"
- process $proc$libresoc.v:199807$14757
+ attribute \src "libresoc.v:196918.3-196927.6"
+ process $proc$libresoc.v:196918$14497
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:199808.5-199808.29"
+ attribute \src "libresoc.v:196919.5-196919.29"
switch \initial
- attribute \src "libresoc.v:199808.9-199808.17"
+ attribute \src "libresoc.v:196919.9-196919.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:199817.3-199828.6"
- process $proc$libresoc.v:199817$14758
+ attribute \src "libresoc.v:196928.3-196939.6"
+ process $proc$libresoc.v:196928$14498
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:199818.5-199818.29"
+ attribute \src "libresoc.v:196929.5-196929.29"
switch \initial
- attribute \src "libresoc.v:199818.9-199818.17"
+ attribute \src "libresoc.v:196929.9-196929.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:199829.3-199837.6"
- process $proc$libresoc.v:199829$14759
+ attribute \src "libresoc.v:196940.3-196948.6"
+ process $proc$libresoc.v:196940$14499
assign { } { }
assign { } { }
- assign $0\core_irq_o$next[0:0]$14760 $1\core_irq_o$next[0:0]$14761
- attribute \src "libresoc.v:199830.5-199830.29"
+ assign $0\core_irq_o$next[0:0]$14500 $1\core_irq_o$next[0:0]$14501
+ attribute \src "libresoc.v:196941.5-196941.29"
switch \initial
- attribute \src "libresoc.v:199830.9-199830.17"
+ attribute \src "libresoc.v:196941.9-196941.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_irq_o$next[0:0]$14761 1'0
+ assign $1\core_irq_o$next[0:0]$14501 1'0
case
- assign $1\core_irq_o$next[0:0]$14761 \irq
+ assign $1\core_irq_o$next[0:0]$14501 \irq
end
sync always
- update \core_irq_o$next $0\core_irq_o$next[0:0]$14760
+ update \core_irq_o$next $0\core_irq_o$next[0:0]$14500
end
- attribute \src "libresoc.v:199838.3-199847.6"
- process $proc$libresoc.v:199838$14762
+ attribute \src "libresoc.v:196949.3-196958.6"
+ process $proc$libresoc.v:196949$14502
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:199839.5-199839.29"
+ attribute \src "libresoc.v:196950.5-196950.29"
switch \initial
- attribute \src "libresoc.v:199839.9-199839.17"
+ attribute \src "libresoc.v:196950.9-196950.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:199848.3-199910.6"
- process $proc$libresoc.v:199848$14763
+ attribute \src "libresoc.v:196959.3-197021.6"
+ process $proc$libresoc.v:196959$14503
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mfrr$11[7:0]$14766 $1\mfrr$11[7:0]$14771
- assign $0\wb_ack$14[0:0]$14767 $1\wb_ack$14[0:0]$14772
+ assign $0\mfrr$11[7:0]$14506 $1\mfrr$11[7:0]$14511
+ assign $0\wb_ack$14[0:0]$14507 $1\wb_ack$14[0:0]$14512
assign { } { }
assign { } { }
assign { } { }
- assign $0\xisr$9[23:0]$14769 $2\xisr$9[23:0]$14778
- assign $0\cppr$10[7:0]$14764 $4\cppr$10[7:0]$14779
- assign $0\wb_rd_data$13[31:0]$14768 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
- assign $0\irq$12[0:0]$14765 $1\irq$12[0:0]$14780
- attribute \src "libresoc.v:199849.5-199849.29"
+ assign $0\xisr$9[23:0]$14509 $2\xisr$9[23:0]$14518
+ assign $0\cppr$10[7:0]$14504 $4\cppr$10[7:0]$14519
+ assign $0\wb_rd_data$13[31:0]$14508 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $0\irq$12[0:0]$14505 $1\irq$12[0:0]$14520
+ attribute \src "libresoc.v:196960.5-196960.29"
switch \initial
- attribute \src "libresoc.v:199849.9-199849.17"
+ attribute \src "libresoc.v:196960.9-196960.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wb_ack$14[0:0]$14772 1'1
- assign $1\cppr$10[7:0]$14770 $2\cppr$10[7:0]$14773
- assign $1\mfrr$11[7:0]$14771 $2\mfrr$11[7:0]$14774
+ assign $1\wb_ack$14[0:0]$14512 1'1
+ assign $1\cppr$10[7:0]$14510 $2\cppr$10[7:0]$14513
+ assign $1\mfrr$11[7:0]$14511 $2\mfrr$11[7:0]$14514
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
switch \icp_wb__we
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
- assign $2\cppr$10[7:0]$14773 $3\cppr$10[7:0]$14775
- assign $2\mfrr$11[7:0]$14774 $3\mfrr$11[7:0]$14776
+ assign $2\cppr$10[7:0]$14513 $3\cppr$10[7:0]$14515
+ assign $2\mfrr$11[7:0]$14514 $3\mfrr$11[7:0]$14516
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
switch \icp_wb__adr [5:0]
attribute \src "libresoc.v:0.0-0.0"
case 6'000000
assign { } { }
- assign $3\mfrr$11[7:0]$14776 \mfrr
- assign $3\cppr$10[7:0]$14775 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14516 \mfrr
+ assign $3\cppr$10[7:0]$14515 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000001
assign { } { }
- assign $3\mfrr$11[7:0]$14776 \mfrr
- assign $3\cppr$10[7:0]$14775 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14516 \mfrr
+ assign $3\cppr$10[7:0]$14515 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000011
- assign $3\cppr$10[7:0]$14775 \cppr
+ assign $3\cppr$10[7:0]$14515 \cppr
assign { } { }
- assign $3\mfrr$11[7:0]$14776 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14516 \be_in [31:24]
case
- assign $3\cppr$10[7:0]$14775 \cppr
- assign $3\mfrr$11[7:0]$14776 \mfrr
+ assign $3\cppr$10[7:0]$14515 \cppr
+ assign $3\mfrr$11[7:0]$14516 \mfrr
end
case
- assign $2\cppr$10[7:0]$14773 \cppr
- assign $2\mfrr$11[7:0]$14774 \mfrr
+ assign $2\cppr$10[7:0]$14513 \cppr
+ assign $2\mfrr$11[7:0]$14514 \mfrr
end
case
- assign $1\cppr$10[7:0]$14770 \cppr
- assign $1\mfrr$11[7:0]$14771 \mfrr
- assign $1\wb_ack$14[0:0]$14772 1'0
+ assign $1\cppr$10[7:0]$14510 \cppr
+ assign $1\mfrr$11[7:0]$14511 \mfrr
+ assign $1\wb_ack$14[0:0]$14512 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xisr$9[23:0]$14777 { 20'00000000000000000001 \ics_i_src }
+ assign $1\xisr$9[23:0]$14517 { 20'00000000000000000001 \ics_i_src }
case
- assign $1\xisr$9[23:0]$14777 24'000000000000000000000000
+ assign $1\xisr$9[23:0]$14517 24'000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xisr$9[23:0]$14778 24'000000000000000000000010
+ assign $2\xisr$9[23:0]$14518 24'000000000000000000000010
case
- assign $2\xisr$9[23:0]$14778 $1\xisr$9[23:0]$14777
+ assign $2\xisr$9[23:0]$14518 $1\xisr$9[23:0]$14517
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
switch \xirr_accept_rd
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cppr$10[7:0]$14779 \min_pri
+ assign $4\cppr$10[7:0]$14519 \min_pri
case
- assign $4\cppr$10[7:0]$14779 $1\cppr$10[7:0]$14770
+ assign $4\cppr$10[7:0]$14519 $1\cppr$10[7:0]$14510
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
switch { \irq \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\irq$12[0:0]$14780 1'1
+ assign $1\irq$12[0:0]$14520 1'1
case
- assign $1\irq$12[0:0]$14780 1'0
+ assign $1\irq$12[0:0]$14520 1'0
end
sync always
- update \cppr$10 $0\cppr$10[7:0]$14764
- update \irq$12 $0\irq$12[0:0]$14765
- update \mfrr$11 $0\mfrr$11[7:0]$14766
- update \wb_ack$14 $0\wb_ack$14[0:0]$14767
- update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14768
- update \xisr$9 $0\xisr$9[23:0]$14769
+ update \cppr$10 $0\cppr$10[7:0]$14504
+ update \irq$12 $0\irq$12[0:0]$14505
+ update \mfrr$11 $0\mfrr$11[7:0]$14506
+ update \wb_ack$14 $0\wb_ack$14[0:0]$14507
+ update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14508
+ update \xisr$9 $0\xisr$9[23:0]$14509
end
- connect \$15 $and$libresoc.v:199710$14725_Y
- connect \$17 $ne$libresoc.v:199711$14726_Y
- connect \$19 $lt$libresoc.v:199712$14727_Y
- connect \$21 $lt$libresoc.v:199713$14728_Y
- connect \$23 $and$libresoc.v:199714$14729_Y
- connect \$25 $eq$libresoc.v:199715$14730_Y
- connect \$27 $and$libresoc.v:199716$14731_Y
- connect \$29 $ne$libresoc.v:199717$14732_Y
- connect \$31 $lt$libresoc.v:199718$14733_Y
- connect \$7 $and$libresoc.v:199719$14734_Y
+ connect \$15 $and$libresoc.v:196821$14465_Y
+ connect \$17 $ne$libresoc.v:196822$14466_Y
+ connect \$19 $lt$libresoc.v:196823$14467_Y
+ connect \$21 $lt$libresoc.v:196824$14468_Y
+ connect \$23 $and$libresoc.v:196825$14469_Y
+ connect \$25 $eq$libresoc.v:196826$14470_Y
+ connect \$27 $and$libresoc.v:196827$14471_Y
+ connect \$29 $ne$libresoc.v:196828$14472_Y
+ connect \$31 $lt$libresoc.v:196829$14473_Y
+ connect \$7 $and$libresoc.v:196830$14474_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:199918.1-200967.10"
+attribute \src "libresoc.v:197029.1-198078.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:200848.3-200897.6"
+ attribute \src "libresoc.v:197959.3-198008.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:200559.3-200568.6"
+ attribute \src "libresoc.v:197670.3-197679.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:200768.3-200777.6"
+ attribute \src "libresoc.v:197879.3-197888.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:200788.3-200797.6"
+ attribute \src "libresoc.v:197899.3-197908.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:200808.3-200817.6"
+ attribute \src "libresoc.v:197919.3-197928.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:200828.3-200837.6"
+ attribute \src "libresoc.v:197939.3-197948.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:200898.3-200907.6"
+ attribute \src "libresoc.v:198009.3-198018.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:200918.3-200927.6"
+ attribute \src "libresoc.v:198029.3-198038.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:200579.3-200588.6"
+ attribute \src "libresoc.v:197690.3-197699.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:200599.3-200608.6"
+ attribute \src "libresoc.v:197710.3-197719.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:200619.3-200628.6"
+ attribute \src "libresoc.v:197730.3-197739.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:200648.3-200657.6"
+ attribute \src "libresoc.v:197759.3-197768.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:200668.3-200677.6"
+ attribute \src "libresoc.v:197779.3-197788.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:200688.3-200697.6"
+ attribute \src "libresoc.v:197799.3-197808.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:200708.3-200717.6"
+ attribute \src "libresoc.v:197819.3-197828.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:200728.3-200737.6"
+ attribute \src "libresoc.v:197839.3-197848.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:200748.3-200757.6"
+ attribute \src "libresoc.v:197859.3-197868.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:200549.3-200558.6"
+ attribute \src "libresoc.v:197660.3-197669.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:200758.3-200767.6"
+ attribute \src "libresoc.v:197869.3-197878.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:200778.3-200787.6"
+ attribute \src "libresoc.v:197889.3-197898.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:200798.3-200807.6"
+ attribute \src "libresoc.v:197909.3-197918.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:200818.3-200827.6"
+ attribute \src "libresoc.v:197929.3-197938.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:200838.3-200847.6"
+ attribute \src "libresoc.v:197949.3-197958.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:200908.3-200917.6"
+ attribute \src "libresoc.v:198019.3-198028.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:200569.3-200578.6"
+ attribute \src "libresoc.v:197680.3-197689.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:200589.3-200598.6"
+ attribute \src "libresoc.v:197700.3-197709.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:200609.3-200618.6"
+ attribute \src "libresoc.v:197720.3-197729.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:200629.3-200638.6"
+ attribute \src "libresoc.v:197740.3-197749.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:200658.3-200667.6"
+ attribute \src "libresoc.v:197769.3-197778.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:200678.3-200687.6"
+ attribute \src "libresoc.v:197789.3-197798.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:200698.3-200707.6"
+ attribute \src "libresoc.v:197809.3-197818.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:200718.3-200727.6"
+ attribute \src "libresoc.v:197829.3-197838.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:200738.3-200747.6"
+ attribute \src "libresoc.v:197849.3-197858.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:200928.3-200937.6"
+ attribute \src "libresoc.v:198039.3-198048.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:200423.3-200424.25"
+ attribute \src "libresoc.v:197534.3-197535.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:200421.3-200422.28"
+ attribute \src "libresoc.v:197532.3-197533.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:200947.3-200955.6"
- wire $0\ics_wb__ack$next[0:0]$15035
- attribute \src "libresoc.v:200457.3-200458.39"
+ attribute \src "libresoc.v:198058.3-198066.6"
+ wire $0\ics_wb__ack$next[0:0]$14775
+ attribute \src "libresoc.v:197568.3-197569.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:200938.3-200946.6"
- wire width 32 $0\ics_wb__dat_r$next[31:0]$15032
- attribute \src "libresoc.v:200459.3-200460.43"
+ attribute \src "libresoc.v:198049.3-198057.6"
+ wire width 32 $0\ics_wb__dat_r$next[31:0]$14772
+ attribute \src "libresoc.v:197570.3-197571.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:199919.7-199919.20"
+ attribute \src "libresoc.v:197030.7-197030.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:200639.3-200647.6"
- wire width 16 $0\int_level_l$next[15:0]$15004
- attribute \src "libresoc.v:200461.3-200462.39"
+ attribute \src "libresoc.v:197750.3-197758.6"
+ wire width 16 $0\int_level_l$next[15:0]$14744
+ attribute \src "libresoc.v:197572.3-197573.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive0_pri$next[7:0]$14914
- attribute \src "libresoc.v:200425.3-200426.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive0_pri$next[7:0]$14654
+ attribute \src "libresoc.v:197536.3-197537.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive10_pri$next[7:0]$14915
- attribute \src "libresoc.v:200445.3-200446.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive10_pri$next[7:0]$14655
+ attribute \src "libresoc.v:197556.3-197557.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive11_pri$next[7:0]$14916
- attribute \src "libresoc.v:200447.3-200448.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive11_pri$next[7:0]$14656
+ attribute \src "libresoc.v:197558.3-197559.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive12_pri$next[7:0]$14917
- attribute \src "libresoc.v:200449.3-200450.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive12_pri$next[7:0]$14657
+ attribute \src "libresoc.v:197560.3-197561.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive13_pri$next[7:0]$14918
- attribute \src "libresoc.v:200451.3-200452.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive13_pri$next[7:0]$14658
+ attribute \src "libresoc.v:197562.3-197563.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive14_pri$next[7:0]$14919
- attribute \src "libresoc.v:200453.3-200454.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive14_pri$next[7:0]$14659
+ attribute \src "libresoc.v:197564.3-197565.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive15_pri$next[7:0]$14920
- attribute \src "libresoc.v:200455.3-200456.37"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive15_pri$next[7:0]$14660
+ attribute \src "libresoc.v:197566.3-197567.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive1_pri$next[7:0]$14921
- attribute \src "libresoc.v:200427.3-200428.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive1_pri$next[7:0]$14661
+ attribute \src "libresoc.v:197538.3-197539.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive2_pri$next[7:0]$14922
- attribute \src "libresoc.v:200429.3-200430.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive2_pri$next[7:0]$14662
+ attribute \src "libresoc.v:197540.3-197541.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive3_pri$next[7:0]$14923
- attribute \src "libresoc.v:200431.3-200432.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive3_pri$next[7:0]$14663
+ attribute \src "libresoc.v:197542.3-197543.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive4_pri$next[7:0]$14924
- attribute \src "libresoc.v:200433.3-200434.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive4_pri$next[7:0]$14664
+ attribute \src "libresoc.v:197544.3-197545.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive5_pri$next[7:0]$14925
- attribute \src "libresoc.v:200435.3-200436.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive5_pri$next[7:0]$14665
+ attribute \src "libresoc.v:197546.3-197547.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive6_pri$next[7:0]$14926
- attribute \src "libresoc.v:200437.3-200438.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive6_pri$next[7:0]$14666
+ attribute \src "libresoc.v:197548.3-197549.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive7_pri$next[7:0]$14927
- attribute \src "libresoc.v:200439.3-200440.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive7_pri$next[7:0]$14667
+ attribute \src "libresoc.v:197550.3-197551.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive8_pri$next[7:0]$14928
- attribute \src "libresoc.v:200441.3-200442.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive8_pri$next[7:0]$14668
+ attribute \src "libresoc.v:197552.3-197553.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $0\xive9_pri$next[7:0]$14929
- attribute \src "libresoc.v:200443.3-200444.35"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $0\xive9_pri$next[7:0]$14669
+ attribute \src "libresoc.v:197554.3-197555.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:200848.3-200897.6"
+ attribute \src "libresoc.v:197959.3-198008.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:200559.3-200568.6"
+ attribute \src "libresoc.v:197670.3-197679.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:200768.3-200777.6"
+ attribute \src "libresoc.v:197879.3-197888.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:200788.3-200797.6"
+ attribute \src "libresoc.v:197899.3-197908.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:200808.3-200817.6"
+ attribute \src "libresoc.v:197919.3-197928.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:200828.3-200837.6"
+ attribute \src "libresoc.v:197939.3-197948.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:200898.3-200907.6"
+ attribute \src "libresoc.v:198009.3-198018.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:200918.3-200927.6"
+ attribute \src "libresoc.v:198029.3-198038.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:200579.3-200588.6"
+ attribute \src "libresoc.v:197690.3-197699.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:200599.3-200608.6"
+ attribute \src "libresoc.v:197710.3-197719.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:200619.3-200628.6"
+ attribute \src "libresoc.v:197730.3-197739.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:200648.3-200657.6"
+ attribute \src "libresoc.v:197759.3-197768.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:200668.3-200677.6"
+ attribute \src "libresoc.v:197779.3-197788.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:200688.3-200697.6"
+ attribute \src "libresoc.v:197799.3-197808.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:200708.3-200717.6"
+ attribute \src "libresoc.v:197819.3-197828.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:200728.3-200737.6"
+ attribute \src "libresoc.v:197839.3-197848.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:200748.3-200757.6"
+ attribute \src "libresoc.v:197859.3-197868.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:200549.3-200558.6"
+ attribute \src "libresoc.v:197660.3-197669.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:200758.3-200767.6"
+ attribute \src "libresoc.v:197869.3-197878.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:200778.3-200787.6"
+ attribute \src "libresoc.v:197889.3-197898.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:200798.3-200807.6"
+ attribute \src "libresoc.v:197909.3-197918.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:200818.3-200827.6"
+ attribute \src "libresoc.v:197929.3-197938.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:200838.3-200847.6"
+ attribute \src "libresoc.v:197949.3-197958.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:200908.3-200917.6"
+ attribute \src "libresoc.v:198019.3-198028.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:200569.3-200578.6"
+ attribute \src "libresoc.v:197680.3-197689.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:200589.3-200598.6"
+ attribute \src "libresoc.v:197700.3-197709.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:200609.3-200618.6"
+ attribute \src "libresoc.v:197720.3-197729.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:200629.3-200638.6"
+ attribute \src "libresoc.v:197740.3-197749.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:200658.3-200667.6"
+ attribute \src "libresoc.v:197769.3-197778.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:200678.3-200687.6"
+ attribute \src "libresoc.v:197789.3-197798.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:200698.3-200707.6"
+ attribute \src "libresoc.v:197809.3-197818.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:200718.3-200727.6"
+ attribute \src "libresoc.v:197829.3-197838.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:200738.3-200747.6"
+ attribute \src "libresoc.v:197849.3-197858.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:200928.3-200937.6"
+ attribute \src "libresoc.v:198039.3-198048.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:200200.13-200200.30"
+ attribute \src "libresoc.v:197311.13-197311.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:200205.13-200205.29"
+ attribute \src "libresoc.v:197316.13-197316.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:200947.3-200955.6"
- wire $1\ics_wb__ack$next[0:0]$15036
- attribute \src "libresoc.v:200214.7-200214.25"
+ attribute \src "libresoc.v:198058.3-198066.6"
+ wire $1\ics_wb__ack$next[0:0]$14776
+ attribute \src "libresoc.v:197325.7-197325.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:200938.3-200946.6"
- wire width 32 $1\ics_wb__dat_r$next[31:0]$15033
- attribute \src "libresoc.v:200223.14-200223.35"
+ attribute \src "libresoc.v:198049.3-198057.6"
+ wire width 32 $1\ics_wb__dat_r$next[31:0]$14773
+ attribute \src "libresoc.v:197334.14-197334.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:200639.3-200647.6"
- wire width 16 $1\int_level_l$next[15:0]$15005
- attribute \src "libresoc.v:200235.14-200235.36"
+ attribute \src "libresoc.v:197750.3-197758.6"
+ wire width 16 $1\int_level_l$next[15:0]$14745
+ attribute \src "libresoc.v:197346.14-197346.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive0_pri$next[7:0]$14930
- attribute \src "libresoc.v:200255.13-200255.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive0_pri$next[7:0]$14670
+ attribute \src "libresoc.v:197366.13-197366.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive10_pri$next[7:0]$14931
- attribute \src "libresoc.v:200259.13-200259.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive10_pri$next[7:0]$14671
+ attribute \src "libresoc.v:197370.13-197370.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive11_pri$next[7:0]$14932
- attribute \src "libresoc.v:200263.13-200263.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive11_pri$next[7:0]$14672
+ attribute \src "libresoc.v:197374.13-197374.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive12_pri$next[7:0]$14933
- attribute \src "libresoc.v:200267.13-200267.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive12_pri$next[7:0]$14673
+ attribute \src "libresoc.v:197378.13-197378.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive13_pri$next[7:0]$14934
- attribute \src "libresoc.v:200271.13-200271.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive13_pri$next[7:0]$14674
+ attribute \src "libresoc.v:197382.13-197382.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive14_pri$next[7:0]$14935
- attribute \src "libresoc.v:200275.13-200275.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive14_pri$next[7:0]$14675
+ attribute \src "libresoc.v:197386.13-197386.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive15_pri$next[7:0]$14936
- attribute \src "libresoc.v:200279.13-200279.31"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive15_pri$next[7:0]$14676
+ attribute \src "libresoc.v:197390.13-197390.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive1_pri$next[7:0]$14937
- attribute \src "libresoc.v:200283.13-200283.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive1_pri$next[7:0]$14677
+ attribute \src "libresoc.v:197394.13-197394.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive2_pri$next[7:0]$14938
- attribute \src "libresoc.v:200287.13-200287.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive2_pri$next[7:0]$14678
+ attribute \src "libresoc.v:197398.13-197398.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive3_pri$next[7:0]$14939
- attribute \src "libresoc.v:200291.13-200291.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive3_pri$next[7:0]$14679
+ attribute \src "libresoc.v:197402.13-197402.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive4_pri$next[7:0]$14940
- attribute \src "libresoc.v:200295.13-200295.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive4_pri$next[7:0]$14680
+ attribute \src "libresoc.v:197406.13-197406.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive5_pri$next[7:0]$14941
- attribute \src "libresoc.v:200299.13-200299.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive5_pri$next[7:0]$14681
+ attribute \src "libresoc.v:197410.13-197410.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive6_pri$next[7:0]$14942
- attribute \src "libresoc.v:200303.13-200303.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive6_pri$next[7:0]$14682
+ attribute \src "libresoc.v:197414.13-197414.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive7_pri$next[7:0]$14943
- attribute \src "libresoc.v:200307.13-200307.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive7_pri$next[7:0]$14683
+ attribute \src "libresoc.v:197418.13-197418.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive8_pri$next[7:0]$14944
- attribute \src "libresoc.v:200311.13-200311.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive8_pri$next[7:0]$14684
+ attribute \src "libresoc.v:197422.13-197422.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $1\xive9_pri$next[7:0]$14945
- attribute \src "libresoc.v:200315.13-200315.30"
+ attribute \src "libresoc.v:197574.3-197659.6"
+ wire width 8 $1\xive9_pri$next[7:0]$14685
+ attribute \src "libresoc.v:197426.13-197426.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:200848.3-200897.6"
+ attribute \src "libresoc.v:197959.3-198008.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive0_pri$next[7:0]$14946
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive10_pri$next[7:0]$14947
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive11_pri$next[7:0]$14948
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive12_pri$next[7:0]$14949
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive13_pri$next[7:0]$14950
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive14_pri$next[7:0]$14951
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive15_pri$next[7:0]$14952
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive1_pri$next[7:0]$14953
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive2_pri$next[7:0]$14954
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive3_pri$next[7:0]$14955
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive4_pri$next[7:0]$14956
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive5_pri$next[7:0]$14957
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive6_pri$next[7:0]$14958
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive7_pri$next[7:0]$14959
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive8_pri$next[7:0]$14960
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $2\xive9_pri$next[7:0]$14961
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive0_pri$next[7:0]$14962
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive10_pri$next[7:0]$14963
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive11_pri$next[7:0]$14964
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive12_pri$next[7:0]$14965
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive13_pri$next[7:0]$14966
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive14_pri$next[7:0]$14967
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive15_pri$next[7:0]$14968
- attribute \src "libresoc.v:200463.3-200548.6"
- wire width 8 $3\xive1_pri$next[7:0]$14969
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+ attribute \src "libresoc.v:197448.19-197448.114"
+ wire $and$libresoc.v:197448$14548_Y
+ attribute \src "libresoc.v:197450.19-197450.114"
+ wire $and$libresoc.v:197450$14550_Y
+ attribute \src "libresoc.v:197453.19-197453.114"
+ wire $and$libresoc.v:197453$14553_Y
+ attribute \src "libresoc.v:197455.19-197455.114"
+ wire $and$libresoc.v:197455$14555_Y
+ attribute \src "libresoc.v:197457.19-197457.114"
+ wire $and$libresoc.v:197457$14557_Y
+ attribute \src "libresoc.v:197459.19-197459.114"
+ wire $and$libresoc.v:197459$14559_Y
+ attribute \src "libresoc.v:197461.19-197461.115"
+ wire $and$libresoc.v:197461$14561_Y
+ attribute \src "libresoc.v:197463.19-197463.115"
+ wire $and$libresoc.v:197463$14563_Y
+ attribute \src "libresoc.v:197465.19-197465.115"
+ wire $and$libresoc.v:197465$14565_Y
+ attribute \src "libresoc.v:197468.19-197468.115"
+ wire $and$libresoc.v:197468$14568_Y
+ attribute \src "libresoc.v:197470.19-197470.115"
+ wire $and$libresoc.v:197470$14570_Y
+ attribute \src "libresoc.v:197472.19-197472.115"
+ wire $and$libresoc.v:197472$14572_Y
+ attribute \src "libresoc.v:197475.19-197475.115"
+ wire $and$libresoc.v:197475$14575_Y
+ attribute \src "libresoc.v:197477.19-197477.115"
+ wire $and$libresoc.v:197477$14577_Y
+ attribute \src "libresoc.v:197479.19-197479.115"
+ wire $and$libresoc.v:197479$14579_Y
+ attribute \src "libresoc.v:197481.19-197481.115"
+ wire $and$libresoc.v:197481$14581_Y
+ attribute \src "libresoc.v:197483.19-197483.115"
+ wire $and$libresoc.v:197483$14583_Y
+ attribute \src "libresoc.v:197486.19-197486.115"
+ wire $and$libresoc.v:197486$14586_Y
+ attribute \src "libresoc.v:197510.17-197510.115"
+ wire $and$libresoc.v:197510$14610_Y
+ attribute \src "libresoc.v:197518.18-197518.112"
+ wire $and$libresoc.v:197518$14618_Y
+ attribute \src "libresoc.v:197520.18-197520.112"
+ wire $and$libresoc.v:197520$14620_Y
+ attribute \src "libresoc.v:197522.18-197522.112"
+ wire $and$libresoc.v:197522$14622_Y
+ attribute \src "libresoc.v:197524.18-197524.112"
+ wire $and$libresoc.v:197524$14624_Y
+ attribute \src "libresoc.v:197527.18-197527.112"
+ wire $and$libresoc.v:197527$14627_Y
+ attribute \src "libresoc.v:197529.18-197529.112"
+ wire $and$libresoc.v:197529$14629_Y
+ attribute \src "libresoc.v:197531.18-197531.112"
+ wire $and$libresoc.v:197531$14631_Y
+ attribute \src "libresoc.v:197445.18-197445.109"
+ wire $eq$libresoc.v:197445$14545_Y
+ attribute \src "libresoc.v:197467.18-197467.109"
+ wire $eq$libresoc.v:197467$14567_Y
+ attribute \src "libresoc.v:197484.17-197484.114"
+ wire $eq$libresoc.v:197484$14584_Y
+ attribute \src "libresoc.v:197487.19-197487.110"
+ wire $eq$libresoc.v:197487$14587_Y
+ attribute \src "libresoc.v:197489.18-197489.109"
+ wire $eq$libresoc.v:197489$14589_Y
+ attribute \src "libresoc.v:197491.18-197491.109"
+ wire $eq$libresoc.v:197491$14591_Y
+ attribute \src "libresoc.v:197493.18-197493.109"
+ wire $eq$libresoc.v:197493$14593_Y
+ attribute \src "libresoc.v:197495.18-197495.109"
+ wire $eq$libresoc.v:197495$14595_Y
+ attribute \src "libresoc.v:197497.18-197497.109"
+ wire $eq$libresoc.v:197497$14597_Y
+ attribute \src "libresoc.v:197499.17-197499.114"
+ wire $eq$libresoc.v:197499$14599_Y
+ attribute \src "libresoc.v:197500.18-197500.109"
+ wire $eq$libresoc.v:197500$14600_Y
+ attribute \src "libresoc.v:197502.18-197502.109"
+ wire $eq$libresoc.v:197502$14602_Y
+ attribute \src "libresoc.v:197504.18-197504.110"
+ wire $eq$libresoc.v:197504$14604_Y
+ attribute \src "libresoc.v:197506.18-197506.110"
+ wire $eq$libresoc.v:197506$14606_Y
+ attribute \src "libresoc.v:197508.18-197508.110"
+ wire $eq$libresoc.v:197508$14608_Y
+ attribute \src "libresoc.v:197511.18-197511.110"
+ wire $eq$libresoc.v:197511$14611_Y
+ attribute \src "libresoc.v:197513.18-197513.110"
+ wire $eq$libresoc.v:197513$14613_Y
+ attribute \src "libresoc.v:197515.18-197515.110"
+ wire $eq$libresoc.v:197515$14615_Y
+ attribute \src "libresoc.v:197526.17-197526.108"
+ wire $eq$libresoc.v:197526$14626_Y
+ attribute \src "libresoc.v:197430.18-197430.111"
+ wire $lt$libresoc.v:197430$14530_Y
+ attribute \src "libresoc.v:197432.19-197432.112"
+ wire $lt$libresoc.v:197432$14532_Y
+ attribute \src "libresoc.v:197434.19-197434.112"
+ wire $lt$libresoc.v:197434$14534_Y
+ attribute \src "libresoc.v:197436.19-197436.112"
+ wire $lt$libresoc.v:197436$14536_Y
+ attribute \src "libresoc.v:197438.19-197438.112"
+ wire $lt$libresoc.v:197438$14538_Y
+ attribute \src "libresoc.v:197440.19-197440.112"
+ wire $lt$libresoc.v:197440$14540_Y
+ attribute \src "libresoc.v:197442.19-197442.112"
+ wire $lt$libresoc.v:197442$14542_Y
+ attribute \src "libresoc.v:197444.19-197444.112"
+ wire $lt$libresoc.v:197444$14544_Y
+ attribute \src "libresoc.v:197447.19-197447.112"
+ wire $lt$libresoc.v:197447$14547_Y
+ attribute \src "libresoc.v:197449.19-197449.112"
+ wire $lt$libresoc.v:197449$14549_Y
+ attribute \src "libresoc.v:197452.19-197452.112"
+ wire $lt$libresoc.v:197452$14552_Y
+ attribute \src "libresoc.v:197454.19-197454.112"
+ wire $lt$libresoc.v:197454$14554_Y
+ attribute \src "libresoc.v:197456.19-197456.112"
+ wire $lt$libresoc.v:197456$14556_Y
+ attribute \src "libresoc.v:197458.19-197458.112"
+ wire $lt$libresoc.v:197458$14558_Y
+ attribute \src "libresoc.v:197460.19-197460.113"
+ wire $lt$libresoc.v:197460$14560_Y
+ attribute \src "libresoc.v:197462.19-197462.113"
+ wire $lt$libresoc.v:197462$14562_Y
+ attribute \src "libresoc.v:197464.19-197464.114"
+ wire $lt$libresoc.v:197464$14564_Y
+ attribute \src "libresoc.v:197466.19-197466.114"
+ wire $lt$libresoc.v:197466$14566_Y
+ attribute \src "libresoc.v:197469.19-197469.114"
+ wire $lt$libresoc.v:197469$14569_Y
+ attribute \src "libresoc.v:197471.19-197471.114"
+ wire $lt$libresoc.v:197471$14571_Y
+ attribute \src "libresoc.v:197474.19-197474.114"
+ wire $lt$libresoc.v:197474$14574_Y
+ attribute \src "libresoc.v:197476.19-197476.114"
+ wire $lt$libresoc.v:197476$14576_Y
+ attribute \src "libresoc.v:197478.19-197478.114"
+ wire $lt$libresoc.v:197478$14578_Y
+ attribute \src "libresoc.v:197480.19-197480.114"
+ wire $lt$libresoc.v:197480$14580_Y
+ attribute \src "libresoc.v:197482.19-197482.114"
+ wire $lt$libresoc.v:197482$14582_Y
+ attribute \src "libresoc.v:197485.19-197485.114"
+ wire $lt$libresoc.v:197485$14585_Y
+ attribute \src "libresoc.v:197519.18-197519.110"
+ wire $lt$libresoc.v:197519$14619_Y
+ attribute \src "libresoc.v:197521.18-197521.110"
+ wire $lt$libresoc.v:197521$14621_Y
+ attribute \src "libresoc.v:197523.18-197523.111"
+ wire $lt$libresoc.v:197523$14623_Y
+ attribute \src "libresoc.v:197525.18-197525.111"
+ wire $lt$libresoc.v:197525$14625_Y
+ attribute \src "libresoc.v:197528.18-197528.111"
+ wire $lt$libresoc.v:197528$14628_Y
+ attribute \src "libresoc.v:197530.18-197530.111"
+ wire $lt$libresoc.v:197530$14630_Y
+ attribute \src "libresoc.v:197517.18-197517.40"
+ wire width 16 $shr$libresoc.v:197517$14617_Y
+ attribute \src "libresoc.v:197429.17-197429.114"
+ wire width 8 $ternary$libresoc.v:197429$14529_Y
+ attribute \src "libresoc.v:197451.18-197451.116"
+ wire width 8 $ternary$libresoc.v:197451$14551_Y
+ attribute \src "libresoc.v:197473.18-197473.116"
+ wire width 8 $ternary$libresoc.v:197473$14573_Y
+ attribute \src "libresoc.v:197488.19-197488.118"
+ wire width 8 $ternary$libresoc.v:197488$14588_Y
+ attribute \src "libresoc.v:197490.18-197490.116"
+ wire width 8 $ternary$libresoc.v:197490$14590_Y
+ attribute \src "libresoc.v:197492.18-197492.116"
+ wire width 8 $ternary$libresoc.v:197492$14592_Y
+ attribute \src "libresoc.v:197494.18-197494.116"
+ wire width 8 $ternary$libresoc.v:197494$14594_Y
+ attribute \src "libresoc.v:197496.18-197496.116"
+ wire width 8 $ternary$libresoc.v:197496$14596_Y
+ attribute \src "libresoc.v:197498.18-197498.116"
+ wire width 8 $ternary$libresoc.v:197498$14598_Y
+ attribute \src "libresoc.v:197501.18-197501.116"
+ wire width 8 $ternary$libresoc.v:197501$14601_Y
+ attribute \src "libresoc.v:197503.18-197503.116"
+ wire width 8 $ternary$libresoc.v:197503$14603_Y
+ attribute \src "libresoc.v:197505.18-197505.117"
+ wire width 8 $ternary$libresoc.v:197505$14605_Y
+ attribute \src "libresoc.v:197507.18-197507.117"
+ wire width 8 $ternary$libresoc.v:197507$14607_Y
+ attribute \src "libresoc.v:197509.18-197509.117"
+ wire width 8 $ternary$libresoc.v:197509$14609_Y
+ attribute \src "libresoc.v:197512.18-197512.117"
+ wire width 8 $ternary$libresoc.v:197512$14612_Y
+ attribute \src "libresoc.v:197514.18-197514.117"
+ wire width 8 $ternary$libresoc.v:197514$14614_Y
+ attribute \src "libresoc.v:197516.18-197516.117"
+ wire width 8 $ternary$libresoc.v:197516$14616_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
wire input 12 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
wire width 4 \cur_idx0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314"
wire \ibit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
- wire width 8 output 3 \icp_o_pri
+ wire width 8 output 2 \icp_o_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
wire width 8 \icp_o_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
- wire width 4 output 2 \icp_o_src
+ wire width 4 output 1 \icp_o_src
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \icp_o_src$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:199919.7-199919.15"
+ attribute \src "libresoc.v:197030.7-197030.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
wire \reg_is_debug
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
wire \reg_is_xive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
- wire input 1 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+ wire input 3 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
wire \wb_valid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200320$14791
+ cell $and $and$libresoc.v:197431$14531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:200320$14791_Y
+ connect \Y $and$libresoc.v:197431$14531_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200322$14793
+ cell $and $and$libresoc.v:197433$14533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:200322$14793_Y
+ connect \Y $and$libresoc.v:197433$14533_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200324$14795
+ cell $and $and$libresoc.v:197435$14535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:200324$14795_Y
+ connect \Y $and$libresoc.v:197435$14535_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200326$14797
+ cell $and $and$libresoc.v:197437$14537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:200326$14797_Y
+ connect \Y $and$libresoc.v:197437$14537_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200328$14799
+ cell $and $and$libresoc.v:197439$14539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:200328$14799_Y
+ connect \Y $and$libresoc.v:197439$14539_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200330$14801
+ cell $and $and$libresoc.v:197441$14541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:200330$14801_Y
+ connect \Y $and$libresoc.v:197441$14541_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200332$14803
+ cell $and $and$libresoc.v:197443$14543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:200332$14803_Y
+ connect \Y $and$libresoc.v:197443$14543_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200335$14806
+ cell $and $and$libresoc.v:197446$14546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:200335$14806_Y
+ connect \Y $and$libresoc.v:197446$14546_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200337$14808
+ cell $and $and$libresoc.v:197448$14548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:200337$14808_Y
+ connect \Y $and$libresoc.v:197448$14548_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200339$14810
+ cell $and $and$libresoc.v:197450$14550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:200339$14810_Y
+ connect \Y $and$libresoc.v:197450$14550_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200342$14813
+ cell $and $and$libresoc.v:197453$14553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:200342$14813_Y
+ connect \Y $and$libresoc.v:197453$14553_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200344$14815
+ cell $and $and$libresoc.v:197455$14555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:200344$14815_Y
+ connect \Y $and$libresoc.v:197455$14555_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200346$14817
+ cell $and $and$libresoc.v:197457$14557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:200346$14817_Y
+ connect \Y $and$libresoc.v:197457$14557_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200348$14819
+ cell $and $and$libresoc.v:197459$14559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:200348$14819_Y
+ connect \Y $and$libresoc.v:197459$14559_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200350$14821
+ cell $and $and$libresoc.v:197461$14561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:200350$14821_Y
+ connect \Y $and$libresoc.v:197461$14561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200352$14823
+ cell $and $and$libresoc.v:197463$14563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:200352$14823_Y
+ connect \Y $and$libresoc.v:197463$14563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200354$14825
+ cell $and $and$libresoc.v:197465$14565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:200354$14825_Y
+ connect \Y $and$libresoc.v:197465$14565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200357$14828
+ cell $and $and$libresoc.v:197468$14568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:200357$14828_Y
+ connect \Y $and$libresoc.v:197468$14568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200359$14830
+ cell $and $and$libresoc.v:197470$14570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:200359$14830_Y
+ connect \Y $and$libresoc.v:197470$14570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200361$14832
+ cell $and $and$libresoc.v:197472$14572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:200361$14832_Y
+ connect \Y $and$libresoc.v:197472$14572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200364$14835
+ cell $and $and$libresoc.v:197475$14575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:200364$14835_Y
+ connect \Y $and$libresoc.v:197475$14575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200366$14837
+ cell $and $and$libresoc.v:197477$14577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:200366$14837_Y
+ connect \Y $and$libresoc.v:197477$14577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200368$14839
+ cell $and $and$libresoc.v:197479$14579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:200368$14839_Y
+ connect \Y $and$libresoc.v:197479$14579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200370$14841
+ cell $and $and$libresoc.v:197481$14581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:200370$14841_Y
+ connect \Y $and$libresoc.v:197481$14581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200372$14843
+ cell $and $and$libresoc.v:197483$14583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:200372$14843_Y
+ connect \Y $and$libresoc.v:197483$14583_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200375$14846
+ cell $and $and$libresoc.v:197486$14586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:200375$14846_Y
+ connect \Y $and$libresoc.v:197486$14586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:200399$14870
+ cell $and $and$libresoc.v:197510$14610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:200399$14870_Y
+ connect \Y $and$libresoc.v:197510$14610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:200407$14878
+ cell $and $and$libresoc.v:197518$14618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:200407$14878_Y
+ connect \Y $and$libresoc.v:197518$14618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200409$14880
+ cell $and $and$libresoc.v:197520$14620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:200409$14880_Y
+ connect \Y $and$libresoc.v:197520$14620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200411$14882
+ cell $and $and$libresoc.v:197522$14622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:200411$14882_Y
+ connect \Y $and$libresoc.v:197522$14622_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200413$14884
+ cell $and $and$libresoc.v:197524$14624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:200413$14884_Y
+ connect \Y $and$libresoc.v:197524$14624_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200416$14887
+ cell $and $and$libresoc.v:197527$14627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:200416$14887_Y
+ connect \Y $and$libresoc.v:197527$14627_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200418$14889
+ cell $and $and$libresoc.v:197529$14629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:200418$14889_Y
+ connect \Y $and$libresoc.v:197529$14629_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:200420$14891
+ cell $and $and$libresoc.v:197531$14631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:200420$14891_Y
+ connect \Y $and$libresoc.v:197531$14631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200334$14805
+ cell $eq $eq$libresoc.v:197445$14545
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200334$14805_Y
+ connect \Y $eq$libresoc.v:197445$14545_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200356$14827
+ cell $eq $eq$libresoc.v:197467$14567
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200356$14827_Y
+ connect \Y $eq$libresoc.v:197467$14567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:200373$14844
+ cell $eq $eq$libresoc.v:197484$14584
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:200373$14844_Y
+ connect \Y $eq$libresoc.v:197484$14584_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200376$14847
+ cell $eq $eq$libresoc.v:197487$14587
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200376$14847_Y
+ connect \Y $eq$libresoc.v:197487$14587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200378$14849
+ cell $eq $eq$libresoc.v:197489$14589
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200378$14849_Y
+ connect \Y $eq$libresoc.v:197489$14589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200380$14851
+ cell $eq $eq$libresoc.v:197491$14591
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200380$14851_Y
+ connect \Y $eq$libresoc.v:197491$14591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200382$14853
+ cell $eq $eq$libresoc.v:197493$14593
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200382$14853_Y
+ connect \Y $eq$libresoc.v:197493$14593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200384$14855
+ cell $eq $eq$libresoc.v:197495$14595
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200384$14855_Y
+ connect \Y $eq$libresoc.v:197495$14595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200386$14857
+ cell $eq $eq$libresoc.v:197497$14597
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200386$14857_Y
+ connect \Y $eq$libresoc.v:197497$14597_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:200388$14859
+ cell $eq $eq$libresoc.v:197499$14599
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:200388$14859_Y
+ connect \Y $eq$libresoc.v:197499$14599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200389$14860
+ cell $eq $eq$libresoc.v:197500$14600
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200389$14860_Y
+ connect \Y $eq$libresoc.v:197500$14600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200391$14862
+ cell $eq $eq$libresoc.v:197502$14602
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200391$14862_Y
+ connect \Y $eq$libresoc.v:197502$14602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200393$14864
+ cell $eq $eq$libresoc.v:197504$14604
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200393$14864_Y
+ connect \Y $eq$libresoc.v:197504$14604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200395$14866
+ cell $eq $eq$libresoc.v:197506$14606
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200395$14866_Y
+ connect \Y $eq$libresoc.v:197506$14606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200397$14868
+ cell $eq $eq$libresoc.v:197508$14608
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200397$14868_Y
+ connect \Y $eq$libresoc.v:197508$14608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200400$14871
+ cell $eq $eq$libresoc.v:197511$14611
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200400$14871_Y
+ connect \Y $eq$libresoc.v:197511$14611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200402$14873
+ cell $eq $eq$libresoc.v:197513$14613
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200402$14873_Y
+ connect \Y $eq$libresoc.v:197513$14613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200404$14875
+ cell $eq $eq$libresoc.v:197515$14615
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200404$14875_Y
+ connect \Y $eq$libresoc.v:197515$14615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:200415$14886
+ cell $eq $eq$libresoc.v:197526$14626
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:200415$14886_Y
+ connect \Y $eq$libresoc.v:197526$14626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200319$14790
+ cell $lt $lt$libresoc.v:197430$14530
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:200319$14790_Y
+ connect \Y $lt$libresoc.v:197430$14530_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200321$14792
+ cell $lt $lt$libresoc.v:197432$14532
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:200321$14792_Y
+ connect \Y $lt$libresoc.v:197432$14532_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200323$14794
+ cell $lt $lt$libresoc.v:197434$14534
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:200323$14794_Y
+ connect \Y $lt$libresoc.v:197434$14534_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200325$14796
+ cell $lt $lt$libresoc.v:197436$14536
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:200325$14796_Y
+ connect \Y $lt$libresoc.v:197436$14536_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200327$14798
+ cell $lt $lt$libresoc.v:197438$14538
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:200327$14798_Y
+ connect \Y $lt$libresoc.v:197438$14538_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200329$14800
+ cell $lt $lt$libresoc.v:197440$14540
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:200329$14800_Y
+ connect \Y $lt$libresoc.v:197440$14540_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200331$14802
+ cell $lt $lt$libresoc.v:197442$14542
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:200331$14802_Y
+ connect \Y $lt$libresoc.v:197442$14542_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200333$14804
+ cell $lt $lt$libresoc.v:197444$14544
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:200333$14804_Y
+ connect \Y $lt$libresoc.v:197444$14544_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200336$14807
+ cell $lt $lt$libresoc.v:197447$14547
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:200336$14807_Y
+ connect \Y $lt$libresoc.v:197447$14547_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200338$14809
+ cell $lt $lt$libresoc.v:197449$14549
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:200338$14809_Y
+ connect \Y $lt$libresoc.v:197449$14549_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200341$14812
+ cell $lt $lt$libresoc.v:197452$14552
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:200341$14812_Y
+ connect \Y $lt$libresoc.v:197452$14552_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200343$14814
+ cell $lt $lt$libresoc.v:197454$14554
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:200343$14814_Y
+ connect \Y $lt$libresoc.v:197454$14554_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200345$14816
+ cell $lt $lt$libresoc.v:197456$14556
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:200345$14816_Y
+ connect \Y $lt$libresoc.v:197456$14556_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200347$14818
+ cell $lt $lt$libresoc.v:197458$14558
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:200347$14818_Y
+ connect \Y $lt$libresoc.v:197458$14558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200349$14820
+ cell $lt $lt$libresoc.v:197460$14560
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:200349$14820_Y
+ connect \Y $lt$libresoc.v:197460$14560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200351$14822
+ cell $lt $lt$libresoc.v:197462$14562
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:200351$14822_Y
+ connect \Y $lt$libresoc.v:197462$14562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200353$14824
+ cell $lt $lt$libresoc.v:197464$14564
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:200353$14824_Y
+ connect \Y $lt$libresoc.v:197464$14564_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200355$14826
+ cell $lt $lt$libresoc.v:197466$14566
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:200355$14826_Y
+ connect \Y $lt$libresoc.v:197466$14566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200358$14829
+ cell $lt $lt$libresoc.v:197469$14569
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:200358$14829_Y
+ connect \Y $lt$libresoc.v:197469$14569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200360$14831
+ cell $lt $lt$libresoc.v:197471$14571
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:200360$14831_Y
+ connect \Y $lt$libresoc.v:197471$14571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200363$14834
+ cell $lt $lt$libresoc.v:197474$14574
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:200363$14834_Y
+ connect \Y $lt$libresoc.v:197474$14574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200365$14836
+ cell $lt $lt$libresoc.v:197476$14576
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:200365$14836_Y
+ connect \Y $lt$libresoc.v:197476$14576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200367$14838
+ cell $lt $lt$libresoc.v:197478$14578
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:200367$14838_Y
+ connect \Y $lt$libresoc.v:197478$14578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200369$14840
+ cell $lt $lt$libresoc.v:197480$14580
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:200369$14840_Y
+ connect \Y $lt$libresoc.v:197480$14580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200371$14842
+ cell $lt $lt$libresoc.v:197482$14582
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:200371$14842_Y
+ connect \Y $lt$libresoc.v:197482$14582_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200374$14845
+ cell $lt $lt$libresoc.v:197485$14585
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:200374$14845_Y
+ connect \Y $lt$libresoc.v:197485$14585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200408$14879
+ cell $lt $lt$libresoc.v:197519$14619
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:200408$14879_Y
+ connect \Y $lt$libresoc.v:197519$14619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200410$14881
+ cell $lt $lt$libresoc.v:197521$14621
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:200410$14881_Y
+ connect \Y $lt$libresoc.v:197521$14621_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200412$14883
+ cell $lt $lt$libresoc.v:197523$14623
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:200412$14883_Y
+ connect \Y $lt$libresoc.v:197523$14623_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200414$14885
+ cell $lt $lt$libresoc.v:197525$14625
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:200414$14885_Y
+ connect \Y $lt$libresoc.v:197525$14625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200417$14888
+ cell $lt $lt$libresoc.v:197528$14628
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:200417$14888_Y
+ connect \Y $lt$libresoc.v:197528$14628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:200419$14890
+ cell $lt $lt$libresoc.v:197530$14630
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:200419$14890_Y
+ connect \Y $lt$libresoc.v:197530$14630_Y
end
- attribute \src "libresoc.v:200406.18-200406.40"
- cell $shr $shr$libresoc.v:200406$14877
+ attribute \src "libresoc.v:197517.18-197517.40"
+ cell $shr $shr$libresoc.v:197517$14617
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:200406$14877_Y
+ connect \Y $shr$libresoc.v:197517$14617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200318$14789
+ cell $mux $ternary$libresoc.v:197429$14529
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:200318$14789_Y
+ connect \Y $ternary$libresoc.v:197429$14529_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200340$14811
+ cell $mux $ternary$libresoc.v:197451$14551
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:200340$14811_Y
+ connect \Y $ternary$libresoc.v:197451$14551_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200362$14833
+ cell $mux $ternary$libresoc.v:197473$14573
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:200362$14833_Y
+ connect \Y $ternary$libresoc.v:197473$14573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200377$14848
+ cell $mux $ternary$libresoc.v:197488$14588
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:200377$14848_Y
+ connect \Y $ternary$libresoc.v:197488$14588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200379$14850
+ cell $mux $ternary$libresoc.v:197490$14590
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:200379$14850_Y
+ connect \Y $ternary$libresoc.v:197490$14590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200381$14852
+ cell $mux $ternary$libresoc.v:197492$14592
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:200381$14852_Y
+ connect \Y $ternary$libresoc.v:197492$14592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200383$14854
+ cell $mux $ternary$libresoc.v:197494$14594
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:200383$14854_Y
+ connect \Y $ternary$libresoc.v:197494$14594_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200385$14856
+ cell $mux $ternary$libresoc.v:197496$14596
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:200385$14856_Y
+ connect \Y $ternary$libresoc.v:197496$14596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200387$14858
+ cell $mux $ternary$libresoc.v:197498$14598
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:200387$14858_Y
+ connect \Y $ternary$libresoc.v:197498$14598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200390$14861
+ cell $mux $ternary$libresoc.v:197501$14601
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:200390$14861_Y
+ connect \Y $ternary$libresoc.v:197501$14601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200392$14863
+ cell $mux $ternary$libresoc.v:197503$14603
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:200392$14863_Y
+ connect \Y $ternary$libresoc.v:197503$14603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200394$14865
+ cell $mux $ternary$libresoc.v:197505$14605
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:200394$14865_Y
+ connect \Y $ternary$libresoc.v:197505$14605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200396$14867
+ cell $mux $ternary$libresoc.v:197507$14607
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:200396$14867_Y
+ connect \Y $ternary$libresoc.v:197507$14607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200398$14869
+ cell $mux $ternary$libresoc.v:197509$14609
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:200398$14869_Y
+ connect \Y $ternary$libresoc.v:197509$14609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200401$14872
+ cell $mux $ternary$libresoc.v:197512$14612
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:200401$14872_Y
+ connect \Y $ternary$libresoc.v:197512$14612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200403$14874
+ cell $mux $ternary$libresoc.v:197514$14614
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:200403$14874_Y
+ connect \Y $ternary$libresoc.v:197514$14614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:200405$14876
+ cell $mux $ternary$libresoc.v:197516$14616
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:200405$14876_Y
+ connect \Y $ternary$libresoc.v:197516$14616_Y
end
- attribute \src "libresoc.v:199919.7-199919.20"
- process $proc$libresoc.v:199919$15037
+ attribute \src "libresoc.v:197030.7-197030.20"
+ process $proc$libresoc.v:197030$14777
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:200200.13-200200.30"
- process $proc$libresoc.v:200200$15038
+ attribute \src "libresoc.v:197311.13-197311.30"
+ process $proc$libresoc.v:197311$14778
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:200205.13-200205.29"
- process $proc$libresoc.v:200205$15039
+ attribute \src "libresoc.v:197316.13-197316.29"
+ process $proc$libresoc.v:197316$14779
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:200214.7-200214.25"
- process $proc$libresoc.v:200214$15040
+ attribute \src "libresoc.v:197325.7-197325.25"
+ process $proc$libresoc.v:197325$14780
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:200223.14-200223.35"
- process $proc$libresoc.v:200223$15041
+ attribute \src "libresoc.v:197334.14-197334.35"
+ process $proc$libresoc.v:197334$14781
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:200235.14-200235.36"
- process $proc$libresoc.v:200235$15042
+ attribute \src "libresoc.v:197346.14-197346.36"
+ process $proc$libresoc.v:197346$14782
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:200255.13-200255.30"
- process $proc$libresoc.v:200255$15043
+ attribute \src "libresoc.v:197366.13-197366.30"
+ process $proc$libresoc.v:197366$14783
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:200259.13-200259.31"
- process $proc$libresoc.v:200259$15044
+ attribute \src "libresoc.v:197370.13-197370.31"
+ process $proc$libresoc.v:197370$14784
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:200263.13-200263.31"
- process $proc$libresoc.v:200263$15045
+ attribute \src "libresoc.v:197374.13-197374.31"
+ process $proc$libresoc.v:197374$14785
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:200267.13-200267.31"
- process $proc$libresoc.v:200267$15046
+ attribute \src "libresoc.v:197378.13-197378.31"
+ process $proc$libresoc.v:197378$14786
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:200271.13-200271.31"
- process $proc$libresoc.v:200271$15047
+ attribute \src "libresoc.v:197382.13-197382.31"
+ process $proc$libresoc.v:197382$14787
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:200275.13-200275.31"
- process $proc$libresoc.v:200275$15048
+ attribute \src "libresoc.v:197386.13-197386.31"
+ process $proc$libresoc.v:197386$14788
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:200279.13-200279.31"
- process $proc$libresoc.v:200279$15049
+ attribute \src "libresoc.v:197390.13-197390.31"
+ process $proc$libresoc.v:197390$14789
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:200283.13-200283.30"
- process $proc$libresoc.v:200283$15050
+ attribute \src "libresoc.v:197394.13-197394.30"
+ process $proc$libresoc.v:197394$14790
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:200287.13-200287.30"
- process $proc$libresoc.v:200287$15051
+ attribute \src "libresoc.v:197398.13-197398.30"
+ process $proc$libresoc.v:197398$14791
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:200291.13-200291.30"
- process $proc$libresoc.v:200291$15052
+ attribute \src "libresoc.v:197402.13-197402.30"
+ process $proc$libresoc.v:197402$14792
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:200295.13-200295.30"
- process $proc$libresoc.v:200295$15053
+ attribute \src "libresoc.v:197406.13-197406.30"
+ process $proc$libresoc.v:197406$14793
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:200299.13-200299.30"
- process $proc$libresoc.v:200299$15054
+ attribute \src "libresoc.v:197410.13-197410.30"
+ process $proc$libresoc.v:197410$14794
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:200303.13-200303.30"
- process $proc$libresoc.v:200303$15055
+ attribute \src "libresoc.v:197414.13-197414.30"
+ process $proc$libresoc.v:197414$14795
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:200307.13-200307.30"
- process $proc$libresoc.v:200307$15056
+ attribute \src "libresoc.v:197418.13-197418.30"
+ process $proc$libresoc.v:197418$14796
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:200311.13-200311.30"
- process $proc$libresoc.v:200311$15057
+ attribute \src "libresoc.v:197422.13-197422.30"
+ process $proc$libresoc.v:197422$14797
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:200315.13-200315.30"
- process $proc$libresoc.v:200315$15058
+ attribute \src "libresoc.v:197426.13-197426.30"
+ process $proc$libresoc.v:197426$14798
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:200421.3-200422.28"
- process $proc$libresoc.v:200421$14892
+ attribute \src "libresoc.v:197532.3-197533.28"
+ process $proc$libresoc.v:197532$14632
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
sync posedge \clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:200423.3-200424.25"
- process $proc$libresoc.v:200423$14893
+ attribute \src "libresoc.v:197534.3-197535.25"
+ process $proc$libresoc.v:197534$14633
assign { } { }
assign $0\icp_o_pri[7:0] \$203
sync posedge \clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:200425.3-200426.35"
- process $proc$libresoc.v:200425$14894
+ attribute \src "libresoc.v:197536.3-197537.35"
+ process $proc$libresoc.v:197536$14634
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
sync posedge \clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:200427.3-200428.35"
- process $proc$libresoc.v:200427$14895
+ attribute \src "libresoc.v:197538.3-197539.35"
+ process $proc$libresoc.v:197538$14635
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
sync posedge \clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:200429.3-200430.35"
- process $proc$libresoc.v:200429$14896
+ attribute \src "libresoc.v:197540.3-197541.35"
+ process $proc$libresoc.v:197540$14636
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
sync posedge \clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:200431.3-200432.35"
- process $proc$libresoc.v:200431$14897
+ attribute \src "libresoc.v:197542.3-197543.35"
+ process $proc$libresoc.v:197542$14637
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
sync posedge \clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:200433.3-200434.35"
- process $proc$libresoc.v:200433$14898
+ attribute \src "libresoc.v:197544.3-197545.35"
+ process $proc$libresoc.v:197544$14638
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
sync posedge \clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:200435.3-200436.35"
- process $proc$libresoc.v:200435$14899
+ attribute \src "libresoc.v:197546.3-197547.35"
+ process $proc$libresoc.v:197546$14639
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
sync posedge \clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:200437.3-200438.35"
- process $proc$libresoc.v:200437$14900
+ attribute \src "libresoc.v:197548.3-197549.35"
+ process $proc$libresoc.v:197548$14640
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
sync posedge \clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:200439.3-200440.35"
- process $proc$libresoc.v:200439$14901
+ attribute \src "libresoc.v:197550.3-197551.35"
+ process $proc$libresoc.v:197550$14641
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
sync posedge \clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:200441.3-200442.35"
- process $proc$libresoc.v:200441$14902
+ attribute \src "libresoc.v:197552.3-197553.35"
+ process $proc$libresoc.v:197552$14642
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
sync posedge \clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:200443.3-200444.35"
- process $proc$libresoc.v:200443$14903
+ attribute \src "libresoc.v:197554.3-197555.35"
+ process $proc$libresoc.v:197554$14643
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
sync posedge \clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:200445.3-200446.37"
- process $proc$libresoc.v:200445$14904
+ attribute \src "libresoc.v:197556.3-197557.37"
+ process $proc$libresoc.v:197556$14644
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
sync posedge \clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:200447.3-200448.37"
- process $proc$libresoc.v:200447$14905
+ attribute \src "libresoc.v:197558.3-197559.37"
+ process $proc$libresoc.v:197558$14645
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
sync posedge \clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:200449.3-200450.37"
- process $proc$libresoc.v:200449$14906
+ attribute \src "libresoc.v:197560.3-197561.37"
+ process $proc$libresoc.v:197560$14646
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
sync posedge \clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:200451.3-200452.37"
- process $proc$libresoc.v:200451$14907
+ attribute \src "libresoc.v:197562.3-197563.37"
+ process $proc$libresoc.v:197562$14647
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
sync posedge \clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:200453.3-200454.37"
- process $proc$libresoc.v:200453$14908
+ attribute \src "libresoc.v:197564.3-197565.37"
+ process $proc$libresoc.v:197564$14648
assign { } { }
assign $0\xive14_pri[7:0] \xive14_pri$next
sync posedge \clk
update \xive14_pri $0\xive14_pri[7:0]
end
- attribute \src "libresoc.v:200455.3-200456.37"
- process $proc$libresoc.v:200455$14909
+ attribute \src "libresoc.v:197566.3-197567.37"
+ process $proc$libresoc.v:197566$14649
assign { } { }
assign $0\xive15_pri[7:0] \xive15_pri$next
sync posedge \clk
update \xive15_pri $0\xive15_pri[7:0]
end
- attribute \src "libresoc.v:200457.3-200458.39"
- process $proc$libresoc.v:200457$14910
+ attribute \src "libresoc.v:197568.3-197569.39"
+ process $proc$libresoc.v:197568$14650
assign { } { }
assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
sync posedge \clk
update \ics_wb__ack $0\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:200459.3-200460.43"
- process $proc$libresoc.v:200459$14911
+ attribute \src "libresoc.v:197570.3-197571.43"
+ process $proc$libresoc.v:197570$14651
assign { } { }
assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
sync posedge \clk
update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:200461.3-200462.39"
- process $proc$libresoc.v:200461$14912
+ attribute \src "libresoc.v:197572.3-197573.39"
+ process $proc$libresoc.v:197572$14652
assign { } { }
assign $0\int_level_l[15:0] \int_level_l$next
sync posedge \clk
update \int_level_l $0\int_level_l[15:0]
end
- attribute \src "libresoc.v:200463.3-200548.6"
- process $proc$libresoc.v:200463$14913
+ attribute \src "libresoc.v:197574.3-197659.6"
+ process $proc$libresoc.v:197574$14653
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xive0_pri$next[7:0]$14914 $4\xive0_pri$next[7:0]$14978
- assign $0\xive10_pri$next[7:0]$14915 $4\xive10_pri$next[7:0]$14979
- assign $0\xive11_pri$next[7:0]$14916 $4\xive11_pri$next[7:0]$14980
- assign $0\xive12_pri$next[7:0]$14917 $4\xive12_pri$next[7:0]$14981
- assign $0\xive13_pri$next[7:0]$14918 $4\xive13_pri$next[7:0]$14982
- assign $0\xive14_pri$next[7:0]$14919 $4\xive14_pri$next[7:0]$14983
- assign $0\xive15_pri$next[7:0]$14920 $4\xive15_pri$next[7:0]$14984
- assign $0\xive1_pri$next[7:0]$14921 $4\xive1_pri$next[7:0]$14985
- assign $0\xive2_pri$next[7:0]$14922 $4\xive2_pri$next[7:0]$14986
- assign $0\xive3_pri$next[7:0]$14923 $4\xive3_pri$next[7:0]$14987
- assign $0\xive4_pri$next[7:0]$14924 $4\xive4_pri$next[7:0]$14988
- assign $0\xive5_pri$next[7:0]$14925 $4\xive5_pri$next[7:0]$14989
- assign $0\xive6_pri$next[7:0]$14926 $4\xive6_pri$next[7:0]$14990
- assign $0\xive7_pri$next[7:0]$14927 $4\xive7_pri$next[7:0]$14991
- assign $0\xive8_pri$next[7:0]$14928 $4\xive8_pri$next[7:0]$14992
- assign $0\xive9_pri$next[7:0]$14929 $4\xive9_pri$next[7:0]$14993
- attribute \src "libresoc.v:200464.5-200464.29"
+ assign $0\xive0_pri$next[7:0]$14654 $4\xive0_pri$next[7:0]$14718
+ assign $0\xive10_pri$next[7:0]$14655 $4\xive10_pri$next[7:0]$14719
+ assign $0\xive11_pri$next[7:0]$14656 $4\xive11_pri$next[7:0]$14720
+ assign $0\xive12_pri$next[7:0]$14657 $4\xive12_pri$next[7:0]$14721
+ assign $0\xive13_pri$next[7:0]$14658 $4\xive13_pri$next[7:0]$14722
+ assign $0\xive14_pri$next[7:0]$14659 $4\xive14_pri$next[7:0]$14723
+ assign $0\xive15_pri$next[7:0]$14660 $4\xive15_pri$next[7:0]$14724
+ assign $0\xive1_pri$next[7:0]$14661 $4\xive1_pri$next[7:0]$14725
+ assign $0\xive2_pri$next[7:0]$14662 $4\xive2_pri$next[7:0]$14726
+ assign $0\xive3_pri$next[7:0]$14663 $4\xive3_pri$next[7:0]$14727
+ assign $0\xive4_pri$next[7:0]$14664 $4\xive4_pri$next[7:0]$14728
+ assign $0\xive5_pri$next[7:0]$14665 $4\xive5_pri$next[7:0]$14729
+ assign $0\xive6_pri$next[7:0]$14666 $4\xive6_pri$next[7:0]$14730
+ assign $0\xive7_pri$next[7:0]$14667 $4\xive7_pri$next[7:0]$14731
+ assign $0\xive8_pri$next[7:0]$14668 $4\xive8_pri$next[7:0]$14732
+ assign $0\xive9_pri$next[7:0]$14669 $4\xive9_pri$next[7:0]$14733
+ attribute \src "libresoc.v:197575.5-197575.29"
switch \initial
- attribute \src "libresoc.v:200464.9-200464.17"
+ attribute \src "libresoc.v:197575.9-197575.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xive0_pri$next[7:0]$14930 $2\xive0_pri$next[7:0]$14946
- assign $1\xive10_pri$next[7:0]$14931 $2\xive10_pri$next[7:0]$14947
- assign $1\xive11_pri$next[7:0]$14932 $2\xive11_pri$next[7:0]$14948
- assign $1\xive12_pri$next[7:0]$14933 $2\xive12_pri$next[7:0]$14949
- assign $1\xive13_pri$next[7:0]$14934 $2\xive13_pri$next[7:0]$14950
- assign $1\xive14_pri$next[7:0]$14935 $2\xive14_pri$next[7:0]$14951
- assign $1\xive15_pri$next[7:0]$14936 $2\xive15_pri$next[7:0]$14952
- assign $1\xive1_pri$next[7:0]$14937 $2\xive1_pri$next[7:0]$14953
- assign $1\xive2_pri$next[7:0]$14938 $2\xive2_pri$next[7:0]$14954
- assign $1\xive3_pri$next[7:0]$14939 $2\xive3_pri$next[7:0]$14955
- assign $1\xive4_pri$next[7:0]$14940 $2\xive4_pri$next[7:0]$14956
- assign $1\xive5_pri$next[7:0]$14941 $2\xive5_pri$next[7:0]$14957
- assign $1\xive6_pri$next[7:0]$14942 $2\xive6_pri$next[7:0]$14958
- assign $1\xive7_pri$next[7:0]$14943 $2\xive7_pri$next[7:0]$14959
- assign $1\xive8_pri$next[7:0]$14944 $2\xive8_pri$next[7:0]$14960
- assign $1\xive9_pri$next[7:0]$14945 $2\xive9_pri$next[7:0]$14961
+ assign $1\xive0_pri$next[7:0]$14670 $2\xive0_pri$next[7:0]$14686
+ assign $1\xive10_pri$next[7:0]$14671 $2\xive10_pri$next[7:0]$14687
+ assign $1\xive11_pri$next[7:0]$14672 $2\xive11_pri$next[7:0]$14688
+ assign $1\xive12_pri$next[7:0]$14673 $2\xive12_pri$next[7:0]$14689
+ assign $1\xive13_pri$next[7:0]$14674 $2\xive13_pri$next[7:0]$14690
+ assign $1\xive14_pri$next[7:0]$14675 $2\xive14_pri$next[7:0]$14691
+ assign $1\xive15_pri$next[7:0]$14676 $2\xive15_pri$next[7:0]$14692
+ assign $1\xive1_pri$next[7:0]$14677 $2\xive1_pri$next[7:0]$14693
+ assign $1\xive2_pri$next[7:0]$14678 $2\xive2_pri$next[7:0]$14694
+ assign $1\xive3_pri$next[7:0]$14679 $2\xive3_pri$next[7:0]$14695
+ assign $1\xive4_pri$next[7:0]$14680 $2\xive4_pri$next[7:0]$14696
+ assign $1\xive5_pri$next[7:0]$14681 $2\xive5_pri$next[7:0]$14697
+ assign $1\xive6_pri$next[7:0]$14682 $2\xive6_pri$next[7:0]$14698
+ assign $1\xive7_pri$next[7:0]$14683 $2\xive7_pri$next[7:0]$14699
+ assign $1\xive8_pri$next[7:0]$14684 $2\xive8_pri$next[7:0]$14700
+ assign $1\xive9_pri$next[7:0]$14685 $2\xive9_pri$next[7:0]$14701
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
switch \reg_is_xive
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\xive0_pri$next[7:0]$14946 $3\xive0_pri$next[7:0]$14962
- assign $2\xive10_pri$next[7:0]$14947 $3\xive10_pri$next[7:0]$14963
- assign $2\xive11_pri$next[7:0]$14948 $3\xive11_pri$next[7:0]$14964
- assign $2\xive12_pri$next[7:0]$14949 $3\xive12_pri$next[7:0]$14965
- assign $2\xive13_pri$next[7:0]$14950 $3\xive13_pri$next[7:0]$14966
- assign $2\xive14_pri$next[7:0]$14951 $3\xive14_pri$next[7:0]$14967
- assign $2\xive15_pri$next[7:0]$14952 $3\xive15_pri$next[7:0]$14968
- assign $2\xive1_pri$next[7:0]$14953 $3\xive1_pri$next[7:0]$14969
- assign $2\xive2_pri$next[7:0]$14954 $3\xive2_pri$next[7:0]$14970
- assign $2\xive3_pri$next[7:0]$14955 $3\xive3_pri$next[7:0]$14971
- assign $2\xive4_pri$next[7:0]$14956 $3\xive4_pri$next[7:0]$14972
- assign $2\xive5_pri$next[7:0]$14957 $3\xive5_pri$next[7:0]$14973
- assign $2\xive6_pri$next[7:0]$14958 $3\xive6_pri$next[7:0]$14974
- assign $2\xive7_pri$next[7:0]$14959 $3\xive7_pri$next[7:0]$14975
- assign $2\xive8_pri$next[7:0]$14960 $3\xive8_pri$next[7:0]$14976
- assign $2\xive9_pri$next[7:0]$14961 $3\xive9_pri$next[7:0]$14977
+ assign $2\xive0_pri$next[7:0]$14686 $3\xive0_pri$next[7:0]$14702
+ assign $2\xive10_pri$next[7:0]$14687 $3\xive10_pri$next[7:0]$14703
+ assign $2\xive11_pri$next[7:0]$14688 $3\xive11_pri$next[7:0]$14704
+ assign $2\xive12_pri$next[7:0]$14689 $3\xive12_pri$next[7:0]$14705
+ assign $2\xive13_pri$next[7:0]$14690 $3\xive13_pri$next[7:0]$14706
+ assign $2\xive14_pri$next[7:0]$14691 $3\xive14_pri$next[7:0]$14707
+ assign $2\xive15_pri$next[7:0]$14692 $3\xive15_pri$next[7:0]$14708
+ assign $2\xive1_pri$next[7:0]$14693 $3\xive1_pri$next[7:0]$14709
+ assign $2\xive2_pri$next[7:0]$14694 $3\xive2_pri$next[7:0]$14710
+ assign $2\xive3_pri$next[7:0]$14695 $3\xive3_pri$next[7:0]$14711
+ assign $2\xive4_pri$next[7:0]$14696 $3\xive4_pri$next[7:0]$14712
+ assign $2\xive5_pri$next[7:0]$14697 $3\xive5_pri$next[7:0]$14713
+ assign $2\xive6_pri$next[7:0]$14698 $3\xive6_pri$next[7:0]$14714
+ assign $2\xive7_pri$next[7:0]$14699 $3\xive7_pri$next[7:0]$14715
+ assign $2\xive8_pri$next[7:0]$14700 $3\xive8_pri$next[7:0]$14716
+ assign $2\xive9_pri$next[7:0]$14701 $3\xive9_pri$next[7:0]$14717
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
switch \reg_idx
attribute \src "libresoc.v:0.0-0.0"
case 4'0000
assign { } { }
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive0_pri$next[7:0]$14962 \be_in [7:0]
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14702 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
assign { } { }
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive1_pri$next[7:0]$14969 \be_in [7:0]
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive1_pri$next[7:0]$14709 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
assign { } { }
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive2_pri$next[7:0]$14970 \be_in [7:0]
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive2_pri$next[7:0]$14710 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0011
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
assign { } { }
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive3_pri$next[7:0]$14971 \be_in [7:0]
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive3_pri$next[7:0]$14711 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0100
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
assign { } { }
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive4_pri$next[7:0]$14972 \be_in [7:0]
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive4_pri$next[7:0]$14712 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
assign { } { }
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive5_pri$next[7:0]$14973 \be_in [7:0]
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive5_pri$next[7:0]$14713 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0110
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
assign { } { }
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive6_pri$next[7:0]$14974 \be_in [7:0]
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive6_pri$next[7:0]$14714 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0111
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
assign { } { }
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive7_pri$next[7:0]$14975 \be_in [7:0]
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive7_pri$next[7:0]$14715 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive8_pri$next[7:0]$14976 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive8_pri$next[7:0]$14716 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14977 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14717 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1010
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
assign { } { }
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive10_pri$next[7:0]$14963 \be_in [7:0]
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive10_pri$next[7:0]$14703 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1011
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
assign { } { }
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive11_pri$next[7:0]$14964 \be_in [7:0]
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive11_pri$next[7:0]$14704 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1100
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
assign { } { }
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive12_pri$next[7:0]$14965 \be_in [7:0]
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive12_pri$next[7:0]$14705 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1101
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
assign { } { }
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive13_pri$next[7:0]$14966 \be_in [7:0]
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive13_pri$next[7:0]$14706 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1110
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
assign { } { }
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive14_pri$next[7:0]$14967 \be_in [7:0]
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive14_pri$next[7:0]$14707 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'----
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
assign { } { }
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
- assign $3\xive15_pri$next[7:0]$14968 \be_in [7:0]
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
+ assign $3\xive15_pri$next[7:0]$14708 \be_in [7:0]
case
- assign $3\xive0_pri$next[7:0]$14962 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14963 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14964 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14965 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14966 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14967 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14968 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14969 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14970 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14971 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14972 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14973 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14974 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14975 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14976 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14977 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14702 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14703 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14704 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14705 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14706 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14707 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14708 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14709 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14710 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14711 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14712 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14713 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14714 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14715 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14716 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14717 \xive9_pri
end
case
- assign $2\xive0_pri$next[7:0]$14946 \xive0_pri
- assign $2\xive10_pri$next[7:0]$14947 \xive10_pri
- assign $2\xive11_pri$next[7:0]$14948 \xive11_pri
- assign $2\xive12_pri$next[7:0]$14949 \xive12_pri
- assign $2\xive13_pri$next[7:0]$14950 \xive13_pri
- assign $2\xive14_pri$next[7:0]$14951 \xive14_pri
- assign $2\xive15_pri$next[7:0]$14952 \xive15_pri
- assign $2\xive1_pri$next[7:0]$14953 \xive1_pri
- assign $2\xive2_pri$next[7:0]$14954 \xive2_pri
- assign $2\xive3_pri$next[7:0]$14955 \xive3_pri
- assign $2\xive4_pri$next[7:0]$14956 \xive4_pri
- assign $2\xive5_pri$next[7:0]$14957 \xive5_pri
- assign $2\xive6_pri$next[7:0]$14958 \xive6_pri
- assign $2\xive7_pri$next[7:0]$14959 \xive7_pri
- assign $2\xive8_pri$next[7:0]$14960 \xive8_pri
- assign $2\xive9_pri$next[7:0]$14961 \xive9_pri
- end
- case
- assign $1\xive0_pri$next[7:0]$14930 \xive0_pri
- assign $1\xive10_pri$next[7:0]$14931 \xive10_pri
- assign $1\xive11_pri$next[7:0]$14932 \xive11_pri
- assign $1\xive12_pri$next[7:0]$14933 \xive12_pri
- assign $1\xive13_pri$next[7:0]$14934 \xive13_pri
- assign $1\xive14_pri$next[7:0]$14935 \xive14_pri
- assign $1\xive15_pri$next[7:0]$14936 \xive15_pri
- assign $1\xive1_pri$next[7:0]$14937 \xive1_pri
- assign $1\xive2_pri$next[7:0]$14938 \xive2_pri
- assign $1\xive3_pri$next[7:0]$14939 \xive3_pri
- assign $1\xive4_pri$next[7:0]$14940 \xive4_pri
- assign $1\xive5_pri$next[7:0]$14941 \xive5_pri
- assign $1\xive6_pri$next[7:0]$14942 \xive6_pri
- assign $1\xive7_pri$next[7:0]$14943 \xive7_pri
- assign $1\xive8_pri$next[7:0]$14944 \xive8_pri
- assign $1\xive9_pri$next[7:0]$14945 \xive9_pri
+ assign $2\xive0_pri$next[7:0]$14686 \xive0_pri
+ assign $2\xive10_pri$next[7:0]$14687 \xive10_pri
+ assign $2\xive11_pri$next[7:0]$14688 \xive11_pri
+ assign $2\xive12_pri$next[7:0]$14689 \xive12_pri
+ assign $2\xive13_pri$next[7:0]$14690 \xive13_pri
+ assign $2\xive14_pri$next[7:0]$14691 \xive14_pri
+ assign $2\xive15_pri$next[7:0]$14692 \xive15_pri
+ assign $2\xive1_pri$next[7:0]$14693 \xive1_pri
+ assign $2\xive2_pri$next[7:0]$14694 \xive2_pri
+ assign $2\xive3_pri$next[7:0]$14695 \xive3_pri
+ assign $2\xive4_pri$next[7:0]$14696 \xive4_pri
+ assign $2\xive5_pri$next[7:0]$14697 \xive5_pri
+ assign $2\xive6_pri$next[7:0]$14698 \xive6_pri
+ assign $2\xive7_pri$next[7:0]$14699 \xive7_pri
+ assign $2\xive8_pri$next[7:0]$14700 \xive8_pri
+ assign $2\xive9_pri$next[7:0]$14701 \xive9_pri
+ end
+ case
+ assign $1\xive0_pri$next[7:0]$14670 \xive0_pri
+ assign $1\xive10_pri$next[7:0]$14671 \xive10_pri
+ assign $1\xive11_pri$next[7:0]$14672 \xive11_pri
+ assign $1\xive12_pri$next[7:0]$14673 \xive12_pri
+ assign $1\xive13_pri$next[7:0]$14674 \xive13_pri
+ assign $1\xive14_pri$next[7:0]$14675 \xive14_pri
+ assign $1\xive15_pri$next[7:0]$14676 \xive15_pri
+ assign $1\xive1_pri$next[7:0]$14677 \xive1_pri
+ assign $1\xive2_pri$next[7:0]$14678 \xive2_pri
+ assign $1\xive3_pri$next[7:0]$14679 \xive3_pri
+ assign $1\xive4_pri$next[7:0]$14680 \xive4_pri
+ assign $1\xive5_pri$next[7:0]$14681 \xive5_pri
+ assign $1\xive6_pri$next[7:0]$14682 \xive6_pri
+ assign $1\xive7_pri$next[7:0]$14683 \xive7_pri
+ assign $1\xive8_pri$next[7:0]$14684 \xive8_pri
+ assign $1\xive9_pri$next[7:0]$14685 \xive9_pri
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\xive0_pri$next[7:0]$14978 8'11111111
- assign $4\xive1_pri$next[7:0]$14985 8'11111111
- assign $4\xive2_pri$next[7:0]$14986 8'11111111
- assign $4\xive3_pri$next[7:0]$14987 8'11111111
- assign $4\xive4_pri$next[7:0]$14988 8'11111111
- assign $4\xive5_pri$next[7:0]$14989 8'11111111
- assign $4\xive6_pri$next[7:0]$14990 8'11111111
- assign $4\xive7_pri$next[7:0]$14991 8'11111111
- assign $4\xive8_pri$next[7:0]$14992 8'11111111
- assign $4\xive9_pri$next[7:0]$14993 8'11111111
- assign $4\xive10_pri$next[7:0]$14979 8'11111111
- assign $4\xive11_pri$next[7:0]$14980 8'11111111
- assign $4\xive12_pri$next[7:0]$14981 8'11111111
- assign $4\xive13_pri$next[7:0]$14982 8'11111111
- assign $4\xive14_pri$next[7:0]$14983 8'11111111
- assign $4\xive15_pri$next[7:0]$14984 8'11111111
+ assign $4\xive0_pri$next[7:0]$14718 8'11111111
+ assign $4\xive1_pri$next[7:0]$14725 8'11111111
+ assign $4\xive2_pri$next[7:0]$14726 8'11111111
+ assign $4\xive3_pri$next[7:0]$14727 8'11111111
+ assign $4\xive4_pri$next[7:0]$14728 8'11111111
+ assign $4\xive5_pri$next[7:0]$14729 8'11111111
+ assign $4\xive6_pri$next[7:0]$14730 8'11111111
+ assign $4\xive7_pri$next[7:0]$14731 8'11111111
+ assign $4\xive8_pri$next[7:0]$14732 8'11111111
+ assign $4\xive9_pri$next[7:0]$14733 8'11111111
+ assign $4\xive10_pri$next[7:0]$14719 8'11111111
+ assign $4\xive11_pri$next[7:0]$14720 8'11111111
+ assign $4\xive12_pri$next[7:0]$14721 8'11111111
+ assign $4\xive13_pri$next[7:0]$14722 8'11111111
+ assign $4\xive14_pri$next[7:0]$14723 8'11111111
+ assign $4\xive15_pri$next[7:0]$14724 8'11111111
case
- assign $4\xive0_pri$next[7:0]$14978 $1\xive0_pri$next[7:0]$14930
- assign $4\xive10_pri$next[7:0]$14979 $1\xive10_pri$next[7:0]$14931
- assign $4\xive11_pri$next[7:0]$14980 $1\xive11_pri$next[7:0]$14932
- assign $4\xive12_pri$next[7:0]$14981 $1\xive12_pri$next[7:0]$14933
- assign $4\xive13_pri$next[7:0]$14982 $1\xive13_pri$next[7:0]$14934
- assign $4\xive14_pri$next[7:0]$14983 $1\xive14_pri$next[7:0]$14935
- assign $4\xive15_pri$next[7:0]$14984 $1\xive15_pri$next[7:0]$14936
- assign $4\xive1_pri$next[7:0]$14985 $1\xive1_pri$next[7:0]$14937
- assign $4\xive2_pri$next[7:0]$14986 $1\xive2_pri$next[7:0]$14938
- assign $4\xive3_pri$next[7:0]$14987 $1\xive3_pri$next[7:0]$14939
- assign $4\xive4_pri$next[7:0]$14988 $1\xive4_pri$next[7:0]$14940
- assign $4\xive5_pri$next[7:0]$14989 $1\xive5_pri$next[7:0]$14941
- assign $4\xive6_pri$next[7:0]$14990 $1\xive6_pri$next[7:0]$14942
- assign $4\xive7_pri$next[7:0]$14991 $1\xive7_pri$next[7:0]$14943
- assign $4\xive8_pri$next[7:0]$14992 $1\xive8_pri$next[7:0]$14944
- assign $4\xive9_pri$next[7:0]$14993 $1\xive9_pri$next[7:0]$14945
+ assign $4\xive0_pri$next[7:0]$14718 $1\xive0_pri$next[7:0]$14670
+ assign $4\xive10_pri$next[7:0]$14719 $1\xive10_pri$next[7:0]$14671
+ assign $4\xive11_pri$next[7:0]$14720 $1\xive11_pri$next[7:0]$14672
+ assign $4\xive12_pri$next[7:0]$14721 $1\xive12_pri$next[7:0]$14673
+ assign $4\xive13_pri$next[7:0]$14722 $1\xive13_pri$next[7:0]$14674
+ assign $4\xive14_pri$next[7:0]$14723 $1\xive14_pri$next[7:0]$14675
+ assign $4\xive15_pri$next[7:0]$14724 $1\xive15_pri$next[7:0]$14676
+ assign $4\xive1_pri$next[7:0]$14725 $1\xive1_pri$next[7:0]$14677
+ assign $4\xive2_pri$next[7:0]$14726 $1\xive2_pri$next[7:0]$14678
+ assign $4\xive3_pri$next[7:0]$14727 $1\xive3_pri$next[7:0]$14679
+ assign $4\xive4_pri$next[7:0]$14728 $1\xive4_pri$next[7:0]$14680
+ assign $4\xive5_pri$next[7:0]$14729 $1\xive5_pri$next[7:0]$14681
+ assign $4\xive6_pri$next[7:0]$14730 $1\xive6_pri$next[7:0]$14682
+ assign $4\xive7_pri$next[7:0]$14731 $1\xive7_pri$next[7:0]$14683
+ assign $4\xive8_pri$next[7:0]$14732 $1\xive8_pri$next[7:0]$14684
+ assign $4\xive9_pri$next[7:0]$14733 $1\xive9_pri$next[7:0]$14685
end
sync always
- update \xive0_pri$next $0\xive0_pri$next[7:0]$14914
- update \xive10_pri$next $0\xive10_pri$next[7:0]$14915
- update \xive11_pri$next $0\xive11_pri$next[7:0]$14916
- update \xive12_pri$next $0\xive12_pri$next[7:0]$14917
- update \xive13_pri$next $0\xive13_pri$next[7:0]$14918
- update \xive14_pri$next $0\xive14_pri$next[7:0]$14919
- update \xive15_pri$next $0\xive15_pri$next[7:0]$14920
- update \xive1_pri$next $0\xive1_pri$next[7:0]$14921
- update \xive2_pri$next $0\xive2_pri$next[7:0]$14922
- update \xive3_pri$next $0\xive3_pri$next[7:0]$14923
- update \xive4_pri$next $0\xive4_pri$next[7:0]$14924
- update \xive5_pri$next $0\xive5_pri$next[7:0]$14925
- update \xive6_pri$next $0\xive6_pri$next[7:0]$14926
- update \xive7_pri$next $0\xive7_pri$next[7:0]$14927
- update \xive8_pri$next $0\xive8_pri$next[7:0]$14928
- update \xive9_pri$next $0\xive9_pri$next[7:0]$14929
+ update \xive0_pri$next $0\xive0_pri$next[7:0]$14654
+ update \xive10_pri$next $0\xive10_pri$next[7:0]$14655
+ update \xive11_pri$next $0\xive11_pri$next[7:0]$14656
+ update \xive12_pri$next $0\xive12_pri$next[7:0]$14657
+ update \xive13_pri$next $0\xive13_pri$next[7:0]$14658
+ update \xive14_pri$next $0\xive14_pri$next[7:0]$14659
+ update \xive15_pri$next $0\xive15_pri$next[7:0]$14660
+ update \xive1_pri$next $0\xive1_pri$next[7:0]$14661
+ update \xive2_pri$next $0\xive2_pri$next[7:0]$14662
+ update \xive3_pri$next $0\xive3_pri$next[7:0]$14663
+ update \xive4_pri$next $0\xive4_pri$next[7:0]$14664
+ update \xive5_pri$next $0\xive5_pri$next[7:0]$14665
+ update \xive6_pri$next $0\xive6_pri$next[7:0]$14666
+ update \xive7_pri$next $0\xive7_pri$next[7:0]$14667
+ update \xive8_pri$next $0\xive8_pri$next[7:0]$14668
+ update \xive9_pri$next $0\xive9_pri$next[7:0]$14669
end
- attribute \src "libresoc.v:200549.3-200558.6"
- process $proc$libresoc.v:200549$14994
+ attribute \src "libresoc.v:197660.3-197669.6"
+ process $proc$libresoc.v:197660$14734
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:200550.5-200550.29"
+ attribute \src "libresoc.v:197661.5-197661.29"
switch \initial
- attribute \src "libresoc.v:200550.9-200550.17"
+ attribute \src "libresoc.v:197661.9-197661.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:200559.3-200568.6"
- process $proc$libresoc.v:200559$14995
+ attribute \src "libresoc.v:197670.3-197679.6"
+ process $proc$libresoc.v:197670$14735
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:200560.5-200560.29"
+ attribute \src "libresoc.v:197671.5-197671.29"
switch \initial
- attribute \src "libresoc.v:200560.9-200560.17"
+ attribute \src "libresoc.v:197671.9-197671.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:200569.3-200578.6"
- process $proc$libresoc.v:200569$14996
+ attribute \src "libresoc.v:197680.3-197689.6"
+ process $proc$libresoc.v:197680$14736
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:200570.5-200570.29"
+ attribute \src "libresoc.v:197681.5-197681.29"
switch \initial
- attribute \src "libresoc.v:200570.9-200570.17"
+ attribute \src "libresoc.v:197681.9-197681.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:200579.3-200588.6"
- process $proc$libresoc.v:200579$14997
+ attribute \src "libresoc.v:197690.3-197699.6"
+ process $proc$libresoc.v:197690$14737
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:200580.5-200580.29"
+ attribute \src "libresoc.v:197691.5-197691.29"
switch \initial
- attribute \src "libresoc.v:200580.9-200580.17"
+ attribute \src "libresoc.v:197691.9-197691.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:200589.3-200598.6"
- process $proc$libresoc.v:200589$14998
+ attribute \src "libresoc.v:197700.3-197709.6"
+ process $proc$libresoc.v:197700$14738
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:200590.5-200590.29"
+ attribute \src "libresoc.v:197701.5-197701.29"
switch \initial
- attribute \src "libresoc.v:200590.9-200590.17"
+ attribute \src "libresoc.v:197701.9-197701.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:200599.3-200608.6"
- process $proc$libresoc.v:200599$14999
+ attribute \src "libresoc.v:197710.3-197719.6"
+ process $proc$libresoc.v:197710$14739
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:200600.5-200600.29"
+ attribute \src "libresoc.v:197711.5-197711.29"
switch \initial
- attribute \src "libresoc.v:200600.9-200600.17"
+ attribute \src "libresoc.v:197711.9-197711.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:200609.3-200618.6"
- process $proc$libresoc.v:200609$15000
+ attribute \src "libresoc.v:197720.3-197729.6"
+ process $proc$libresoc.v:197720$14740
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:200610.5-200610.29"
+ attribute \src "libresoc.v:197721.5-197721.29"
switch \initial
- attribute \src "libresoc.v:200610.9-200610.17"
+ attribute \src "libresoc.v:197721.9-197721.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:200619.3-200628.6"
- process $proc$libresoc.v:200619$15001
+ attribute \src "libresoc.v:197730.3-197739.6"
+ process $proc$libresoc.v:197730$14741
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:200620.5-200620.29"
+ attribute \src "libresoc.v:197731.5-197731.29"
switch \initial
- attribute \src "libresoc.v:200620.9-200620.17"
+ attribute \src "libresoc.v:197731.9-197731.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:200629.3-200638.6"
- process $proc$libresoc.v:200629$15002
+ attribute \src "libresoc.v:197740.3-197749.6"
+ process $proc$libresoc.v:197740$14742
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:200630.5-200630.29"
+ attribute \src "libresoc.v:197741.5-197741.29"
switch \initial
- attribute \src "libresoc.v:200630.9-200630.17"
+ attribute \src "libresoc.v:197741.9-197741.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:200639.3-200647.6"
- process $proc$libresoc.v:200639$15003
+ attribute \src "libresoc.v:197750.3-197758.6"
+ process $proc$libresoc.v:197750$14743
assign { } { }
assign { } { }
- assign $0\int_level_l$next[15:0]$15004 $1\int_level_l$next[15:0]$15005
- attribute \src "libresoc.v:200640.5-200640.29"
+ assign $0\int_level_l$next[15:0]$14744 $1\int_level_l$next[15:0]$14745
+ attribute \src "libresoc.v:197751.5-197751.29"
switch \initial
- attribute \src "libresoc.v:200640.9-200640.17"
+ attribute \src "libresoc.v:197751.9-197751.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\int_level_l$next[15:0]$15005 16'0000000000000000
+ assign $1\int_level_l$next[15:0]$14745 16'0000000000000000
case
- assign $1\int_level_l$next[15:0]$15005 \int_level_i
+ assign $1\int_level_l$next[15:0]$14745 \int_level_i
end
sync always
- update \int_level_l$next $0\int_level_l$next[15:0]$15004
+ update \int_level_l$next $0\int_level_l$next[15:0]$14744
end
- attribute \src "libresoc.v:200648.3-200657.6"
- process $proc$libresoc.v:200648$15006
+ attribute \src "libresoc.v:197759.3-197768.6"
+ process $proc$libresoc.v:197759$14746
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:200649.5-200649.29"
+ attribute \src "libresoc.v:197760.5-197760.29"
switch \initial
- attribute \src "libresoc.v:200649.9-200649.17"
+ attribute \src "libresoc.v:197760.9-197760.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:200658.3-200667.6"
- process $proc$libresoc.v:200658$15007
+ attribute \src "libresoc.v:197769.3-197778.6"
+ process $proc$libresoc.v:197769$14747
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:200659.5-200659.29"
+ attribute \src "libresoc.v:197770.5-197770.29"
switch \initial
- attribute \src "libresoc.v:200659.9-200659.17"
+ attribute \src "libresoc.v:197770.9-197770.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:200668.3-200677.6"
- process $proc$libresoc.v:200668$15008
+ attribute \src "libresoc.v:197779.3-197788.6"
+ process $proc$libresoc.v:197779$14748
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:200669.5-200669.29"
+ attribute \src "libresoc.v:197780.5-197780.29"
switch \initial
- attribute \src "libresoc.v:200669.9-200669.17"
+ attribute \src "libresoc.v:197780.9-197780.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:200678.3-200687.6"
- process $proc$libresoc.v:200678$15009
+ attribute \src "libresoc.v:197789.3-197798.6"
+ process $proc$libresoc.v:197789$14749
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:200679.5-200679.29"
+ attribute \src "libresoc.v:197790.5-197790.29"
switch \initial
- attribute \src "libresoc.v:200679.9-200679.17"
+ attribute \src "libresoc.v:197790.9-197790.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:200688.3-200697.6"
- process $proc$libresoc.v:200688$15010
+ attribute \src "libresoc.v:197799.3-197808.6"
+ process $proc$libresoc.v:197799$14750
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:200689.5-200689.29"
+ attribute \src "libresoc.v:197800.5-197800.29"
switch \initial
- attribute \src "libresoc.v:200689.9-200689.17"
+ attribute \src "libresoc.v:197800.9-197800.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:200698.3-200707.6"
- process $proc$libresoc.v:200698$15011
+ attribute \src "libresoc.v:197809.3-197818.6"
+ process $proc$libresoc.v:197809$14751
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:200699.5-200699.29"
+ attribute \src "libresoc.v:197810.5-197810.29"
switch \initial
- attribute \src "libresoc.v:200699.9-200699.17"
+ attribute \src "libresoc.v:197810.9-197810.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:200708.3-200717.6"
- process $proc$libresoc.v:200708$15012
+ attribute \src "libresoc.v:197819.3-197828.6"
+ process $proc$libresoc.v:197819$14752
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:200709.5-200709.29"
+ attribute \src "libresoc.v:197820.5-197820.29"
switch \initial
- attribute \src "libresoc.v:200709.9-200709.17"
+ attribute \src "libresoc.v:197820.9-197820.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:200718.3-200727.6"
- process $proc$libresoc.v:200718$15013
+ attribute \src "libresoc.v:197829.3-197838.6"
+ process $proc$libresoc.v:197829$14753
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:200719.5-200719.29"
+ attribute \src "libresoc.v:197830.5-197830.29"
switch \initial
- attribute \src "libresoc.v:200719.9-200719.17"
+ attribute \src "libresoc.v:197830.9-197830.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:200728.3-200737.6"
- process $proc$libresoc.v:200728$15014
+ attribute \src "libresoc.v:197839.3-197848.6"
+ process $proc$libresoc.v:197839$14754
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:200729.5-200729.29"
+ attribute \src "libresoc.v:197840.5-197840.29"
switch \initial
- attribute \src "libresoc.v:200729.9-200729.17"
+ attribute \src "libresoc.v:197840.9-197840.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:200738.3-200747.6"
- process $proc$libresoc.v:200738$15015
+ attribute \src "libresoc.v:197849.3-197858.6"
+ process $proc$libresoc.v:197849$14755
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:200739.5-200739.29"
+ attribute \src "libresoc.v:197850.5-197850.29"
switch \initial
- attribute \src "libresoc.v:200739.9-200739.17"
+ attribute \src "libresoc.v:197850.9-197850.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:200748.3-200757.6"
- process $proc$libresoc.v:200748$15016
+ attribute \src "libresoc.v:197859.3-197868.6"
+ process $proc$libresoc.v:197859$14756
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:200749.5-200749.29"
+ attribute \src "libresoc.v:197860.5-197860.29"
switch \initial
- attribute \src "libresoc.v:200749.9-200749.17"
+ attribute \src "libresoc.v:197860.9-197860.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:200758.3-200767.6"
- process $proc$libresoc.v:200758$15017
+ attribute \src "libresoc.v:197869.3-197878.6"
+ process $proc$libresoc.v:197869$14757
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:200759.5-200759.29"
+ attribute \src "libresoc.v:197870.5-197870.29"
switch \initial
- attribute \src "libresoc.v:200759.9-200759.17"
+ attribute \src "libresoc.v:197870.9-197870.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:200768.3-200777.6"
- process $proc$libresoc.v:200768$15018
+ attribute \src "libresoc.v:197879.3-197888.6"
+ process $proc$libresoc.v:197879$14758
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:200769.5-200769.29"
+ attribute \src "libresoc.v:197880.5-197880.29"
switch \initial
- attribute \src "libresoc.v:200769.9-200769.17"
+ attribute \src "libresoc.v:197880.9-197880.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:200778.3-200787.6"
- process $proc$libresoc.v:200778$15019
+ attribute \src "libresoc.v:197889.3-197898.6"
+ process $proc$libresoc.v:197889$14759
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:200779.5-200779.29"
+ attribute \src "libresoc.v:197890.5-197890.29"
switch \initial
- attribute \src "libresoc.v:200779.9-200779.17"
+ attribute \src "libresoc.v:197890.9-197890.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:200788.3-200797.6"
- process $proc$libresoc.v:200788$15020
+ attribute \src "libresoc.v:197899.3-197908.6"
+ process $proc$libresoc.v:197899$14760
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:200789.5-200789.29"
+ attribute \src "libresoc.v:197900.5-197900.29"
switch \initial
- attribute \src "libresoc.v:200789.9-200789.17"
+ attribute \src "libresoc.v:197900.9-197900.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:200798.3-200807.6"
- process $proc$libresoc.v:200798$15021
+ attribute \src "libresoc.v:197909.3-197918.6"
+ process $proc$libresoc.v:197909$14761
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:200799.5-200799.29"
+ attribute \src "libresoc.v:197910.5-197910.29"
switch \initial
- attribute \src "libresoc.v:200799.9-200799.17"
+ attribute \src "libresoc.v:197910.9-197910.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:200808.3-200817.6"
- process $proc$libresoc.v:200808$15022
+ attribute \src "libresoc.v:197919.3-197928.6"
+ process $proc$libresoc.v:197919$14762
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:200809.5-200809.29"
+ attribute \src "libresoc.v:197920.5-197920.29"
switch \initial
- attribute \src "libresoc.v:200809.9-200809.17"
+ attribute \src "libresoc.v:197920.9-197920.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:200818.3-200827.6"
- process $proc$libresoc.v:200818$15023
+ attribute \src "libresoc.v:197929.3-197938.6"
+ process $proc$libresoc.v:197929$14763
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:200819.5-200819.29"
+ attribute \src "libresoc.v:197930.5-197930.29"
switch \initial
- attribute \src "libresoc.v:200819.9-200819.17"
+ attribute \src "libresoc.v:197930.9-197930.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:200828.3-200837.6"
- process $proc$libresoc.v:200828$15024
+ attribute \src "libresoc.v:197939.3-197948.6"
+ process $proc$libresoc.v:197939$14764
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:200829.5-200829.29"
+ attribute \src "libresoc.v:197940.5-197940.29"
switch \initial
- attribute \src "libresoc.v:200829.9-200829.17"
+ attribute \src "libresoc.v:197940.9-197940.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:200838.3-200847.6"
- process $proc$libresoc.v:200838$15025
+ attribute \src "libresoc.v:197949.3-197958.6"
+ process $proc$libresoc.v:197949$14765
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:200839.5-200839.29"
+ attribute \src "libresoc.v:197950.5-197950.29"
switch \initial
- attribute \src "libresoc.v:200839.9-200839.17"
+ attribute \src "libresoc.v:197950.9-197950.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:200848.3-200897.6"
- process $proc$libresoc.v:200848$15026
+ attribute \src "libresoc.v:197959.3-198008.6"
+ process $proc$libresoc.v:197959$14766
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:200849.5-200849.29"
+ attribute \src "libresoc.v:197960.5-197960.29"
switch \initial
- attribute \src "libresoc.v:200849.9-200849.17"
+ attribute \src "libresoc.v:197960.9-197960.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:200898.3-200907.6"
- process $proc$libresoc.v:200898$15027
+ attribute \src "libresoc.v:198009.3-198018.6"
+ process $proc$libresoc.v:198009$14767
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:200899.5-200899.29"
+ attribute \src "libresoc.v:198010.5-198010.29"
switch \initial
- attribute \src "libresoc.v:200899.9-200899.17"
+ attribute \src "libresoc.v:198010.9-198010.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:200908.3-200917.6"
- process $proc$libresoc.v:200908$15028
+ attribute \src "libresoc.v:198019.3-198028.6"
+ process $proc$libresoc.v:198019$14768
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:200909.5-200909.29"
+ attribute \src "libresoc.v:198020.5-198020.29"
switch \initial
- attribute \src "libresoc.v:200909.9-200909.17"
+ attribute \src "libresoc.v:198020.9-198020.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:200918.3-200927.6"
- process $proc$libresoc.v:200918$15029
+ attribute \src "libresoc.v:198029.3-198038.6"
+ process $proc$libresoc.v:198029$14769
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:200919.5-200919.29"
+ attribute \src "libresoc.v:198030.5-198030.29"
switch \initial
- attribute \src "libresoc.v:200919.9-200919.17"
+ attribute \src "libresoc.v:198030.9-198030.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:200928.3-200937.6"
- process $proc$libresoc.v:200928$15030
+ attribute \src "libresoc.v:198039.3-198048.6"
+ process $proc$libresoc.v:198039$14770
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:200929.5-200929.29"
+ attribute \src "libresoc.v:198040.5-198040.29"
switch \initial
- attribute \src "libresoc.v:200929.9-200929.17"
+ attribute \src "libresoc.v:198040.9-198040.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:200938.3-200946.6"
- process $proc$libresoc.v:200938$15031
+ attribute \src "libresoc.v:198049.3-198057.6"
+ process $proc$libresoc.v:198049$14771
assign { } { }
assign { } { }
- assign $0\ics_wb__dat_r$next[31:0]$15032 $1\ics_wb__dat_r$next[31:0]$15033
- attribute \src "libresoc.v:200939.5-200939.29"
+ assign $0\ics_wb__dat_r$next[31:0]$14772 $1\ics_wb__dat_r$next[31:0]$14773
+ attribute \src "libresoc.v:198050.5-198050.29"
switch \initial
- attribute \src "libresoc.v:200939.9-200939.17"
+ attribute \src "libresoc.v:198050.9-198050.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__dat_r$next[31:0]$15033 0
+ assign $1\ics_wb__dat_r$next[31:0]$14773 0
case
- assign $1\ics_wb__dat_r$next[31:0]$15033 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $1\ics_wb__dat_r$next[31:0]$14773 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
end
sync always
- update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15032
+ update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14772
end
- attribute \src "libresoc.v:200947.3-200955.6"
- process $proc$libresoc.v:200947$15034
+ attribute \src "libresoc.v:198058.3-198066.6"
+ process $proc$libresoc.v:198058$14774
assign { } { }
assign { } { }
- assign $0\ics_wb__ack$next[0:0]$15035 $1\ics_wb__ack$next[0:0]$15036
- attribute \src "libresoc.v:200948.5-200948.29"
+ assign $0\ics_wb__ack$next[0:0]$14775 $1\ics_wb__ack$next[0:0]$14776
+ attribute \src "libresoc.v:198059.5-198059.29"
switch \initial
- attribute \src "libresoc.v:200948.9-200948.17"
+ attribute \src "libresoc.v:198059.9-198059.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__ack$next[0:0]$15036 1'0
- case
- assign $1\ics_wb__ack$next[0:0]$15036 \wb_valid
- end
- sync always
- update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15035
- end
- connect \$7 $ternary$libresoc.v:200318$14789_Y
- connect \$99 $lt$libresoc.v:200319$14790_Y
- connect \$101 $and$libresoc.v:200320$14791_Y
- connect \$103 $lt$libresoc.v:200321$14792_Y
- connect \$105 $and$libresoc.v:200322$14793_Y
- connect \$107 $lt$libresoc.v:200323$14794_Y
- connect \$109 $and$libresoc.v:200324$14795_Y
- connect \$111 $lt$libresoc.v:200325$14796_Y
- connect \$113 $and$libresoc.v:200326$14797_Y
- connect \$115 $lt$libresoc.v:200327$14798_Y
- connect \$117 $and$libresoc.v:200328$14799_Y
- connect \$119 $lt$libresoc.v:200329$14800_Y
- connect \$121 $and$libresoc.v:200330$14801_Y
- connect \$123 $lt$libresoc.v:200331$14802_Y
- connect \$125 $and$libresoc.v:200332$14803_Y
- connect \$127 $lt$libresoc.v:200333$14804_Y
- connect \$12 $eq$libresoc.v:200334$14805_Y
- connect \$129 $and$libresoc.v:200335$14806_Y
- connect \$131 $lt$libresoc.v:200336$14807_Y
- connect \$133 $and$libresoc.v:200337$14808_Y
- connect \$135 $lt$libresoc.v:200338$14809_Y
- connect \$137 $and$libresoc.v:200339$14810_Y
- connect \$11 $ternary$libresoc.v:200340$14811_Y
- connect \$139 $lt$libresoc.v:200341$14812_Y
- connect \$141 $and$libresoc.v:200342$14813_Y
- connect \$143 $lt$libresoc.v:200343$14814_Y
- connect \$145 $and$libresoc.v:200344$14815_Y
- connect \$147 $lt$libresoc.v:200345$14816_Y
- connect \$149 $and$libresoc.v:200346$14817_Y
- connect \$151 $lt$libresoc.v:200347$14818_Y
- connect \$153 $and$libresoc.v:200348$14819_Y
- connect \$155 $lt$libresoc.v:200349$14820_Y
- connect \$157 $and$libresoc.v:200350$14821_Y
- connect \$159 $lt$libresoc.v:200351$14822_Y
- connect \$161 $and$libresoc.v:200352$14823_Y
- connect \$163 $lt$libresoc.v:200353$14824_Y
- connect \$165 $and$libresoc.v:200354$14825_Y
- connect \$167 $lt$libresoc.v:200355$14826_Y
- connect \$16 $eq$libresoc.v:200356$14827_Y
- connect \$169 $and$libresoc.v:200357$14828_Y
- connect \$171 $lt$libresoc.v:200358$14829_Y
- connect \$173 $and$libresoc.v:200359$14830_Y
- connect \$175 $lt$libresoc.v:200360$14831_Y
- connect \$177 $and$libresoc.v:200361$14832_Y
- connect \$15 $ternary$libresoc.v:200362$14833_Y
- connect \$179 $lt$libresoc.v:200363$14834_Y
- connect \$181 $and$libresoc.v:200364$14835_Y
- connect \$183 $lt$libresoc.v:200365$14836_Y
- connect \$185 $and$libresoc.v:200366$14837_Y
- connect \$187 $lt$libresoc.v:200367$14838_Y
- connect \$189 $and$libresoc.v:200368$14839_Y
- connect \$191 $lt$libresoc.v:200369$14840_Y
- connect \$193 $and$libresoc.v:200370$14841_Y
- connect \$195 $lt$libresoc.v:200371$14842_Y
- connect \$197 $and$libresoc.v:200372$14843_Y
- connect \$1 $eq$libresoc.v:200373$14844_Y
- connect \$199 $lt$libresoc.v:200374$14845_Y
- connect \$201 $and$libresoc.v:200375$14846_Y
- connect \$204 $eq$libresoc.v:200376$14847_Y
- connect \$203 $ternary$libresoc.v:200377$14848_Y
- connect \$20 $eq$libresoc.v:200378$14849_Y
- connect \$19 $ternary$libresoc.v:200379$14850_Y
- connect \$24 $eq$libresoc.v:200380$14851_Y
- connect \$23 $ternary$libresoc.v:200381$14852_Y
- connect \$28 $eq$libresoc.v:200382$14853_Y
- connect \$27 $ternary$libresoc.v:200383$14854_Y
- connect \$32 $eq$libresoc.v:200384$14855_Y
- connect \$31 $ternary$libresoc.v:200385$14856_Y
- connect \$36 $eq$libresoc.v:200386$14857_Y
- connect \$35 $ternary$libresoc.v:200387$14858_Y
- connect \$3 $eq$libresoc.v:200388$14859_Y
- connect \$40 $eq$libresoc.v:200389$14860_Y
- connect \$39 $ternary$libresoc.v:200390$14861_Y
- connect \$44 $eq$libresoc.v:200391$14862_Y
- connect \$43 $ternary$libresoc.v:200392$14863_Y
- connect \$48 $eq$libresoc.v:200393$14864_Y
- connect \$47 $ternary$libresoc.v:200394$14865_Y
- connect \$52 $eq$libresoc.v:200395$14866_Y
- connect \$51 $ternary$libresoc.v:200396$14867_Y
- connect \$56 $eq$libresoc.v:200397$14868_Y
- connect \$55 $ternary$libresoc.v:200398$14869_Y
- connect \$5 $and$libresoc.v:200399$14870_Y
- connect \$60 $eq$libresoc.v:200400$14871_Y
- connect \$59 $ternary$libresoc.v:200401$14872_Y
- connect \$64 $eq$libresoc.v:200402$14873_Y
- connect \$63 $ternary$libresoc.v:200403$14874_Y
- connect \$68 $eq$libresoc.v:200404$14875_Y
- connect \$67 $ternary$libresoc.v:200405$14876_Y
- connect \$71 $shr$libresoc.v:200406$14877_Y [0]
- connect \$73 $and$libresoc.v:200407$14878_Y
- connect \$75 $lt$libresoc.v:200408$14879_Y
- connect \$77 $and$libresoc.v:200409$14880_Y
- connect \$79 $lt$libresoc.v:200410$14881_Y
- connect \$81 $and$libresoc.v:200411$14882_Y
- connect \$83 $lt$libresoc.v:200412$14883_Y
- connect \$85 $and$libresoc.v:200413$14884_Y
- connect \$87 $lt$libresoc.v:200414$14885_Y
- connect \$8 $eq$libresoc.v:200415$14886_Y
- connect \$89 $and$libresoc.v:200416$14887_Y
- connect \$91 $lt$libresoc.v:200417$14888_Y
- connect \$93 $and$libresoc.v:200418$14889_Y
- connect \$95 $lt$libresoc.v:200419$14890_Y
- connect \$97 $and$libresoc.v:200420$14891_Y
+ assign $1\ics_wb__ack$next[0:0]$14776 1'0
+ case
+ assign $1\ics_wb__ack$next[0:0]$14776 \wb_valid
+ end
+ sync always
+ update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14775
+ end
+ connect \$7 $ternary$libresoc.v:197429$14529_Y
+ connect \$99 $lt$libresoc.v:197430$14530_Y
+ connect \$101 $and$libresoc.v:197431$14531_Y
+ connect \$103 $lt$libresoc.v:197432$14532_Y
+ connect \$105 $and$libresoc.v:197433$14533_Y
+ connect \$107 $lt$libresoc.v:197434$14534_Y
+ connect \$109 $and$libresoc.v:197435$14535_Y
+ connect \$111 $lt$libresoc.v:197436$14536_Y
+ connect \$113 $and$libresoc.v:197437$14537_Y
+ connect \$115 $lt$libresoc.v:197438$14538_Y
+ connect \$117 $and$libresoc.v:197439$14539_Y
+ connect \$119 $lt$libresoc.v:197440$14540_Y
+ connect \$121 $and$libresoc.v:197441$14541_Y
+ connect \$123 $lt$libresoc.v:197442$14542_Y
+ connect \$125 $and$libresoc.v:197443$14543_Y
+ connect \$127 $lt$libresoc.v:197444$14544_Y
+ connect \$12 $eq$libresoc.v:197445$14545_Y
+ connect \$129 $and$libresoc.v:197446$14546_Y
+ connect \$131 $lt$libresoc.v:197447$14547_Y
+ connect \$133 $and$libresoc.v:197448$14548_Y
+ connect \$135 $lt$libresoc.v:197449$14549_Y
+ connect \$137 $and$libresoc.v:197450$14550_Y
+ connect \$11 $ternary$libresoc.v:197451$14551_Y
+ connect \$139 $lt$libresoc.v:197452$14552_Y
+ connect \$141 $and$libresoc.v:197453$14553_Y
+ connect \$143 $lt$libresoc.v:197454$14554_Y
+ connect \$145 $and$libresoc.v:197455$14555_Y
+ connect \$147 $lt$libresoc.v:197456$14556_Y
+ connect \$149 $and$libresoc.v:197457$14557_Y
+ connect \$151 $lt$libresoc.v:197458$14558_Y
+ connect \$153 $and$libresoc.v:197459$14559_Y
+ connect \$155 $lt$libresoc.v:197460$14560_Y
+ connect \$157 $and$libresoc.v:197461$14561_Y
+ connect \$159 $lt$libresoc.v:197462$14562_Y
+ connect \$161 $and$libresoc.v:197463$14563_Y
+ connect \$163 $lt$libresoc.v:197464$14564_Y
+ connect \$165 $and$libresoc.v:197465$14565_Y
+ connect \$167 $lt$libresoc.v:197466$14566_Y
+ connect \$16 $eq$libresoc.v:197467$14567_Y
+ connect \$169 $and$libresoc.v:197468$14568_Y
+ connect \$171 $lt$libresoc.v:197469$14569_Y
+ connect \$173 $and$libresoc.v:197470$14570_Y
+ connect \$175 $lt$libresoc.v:197471$14571_Y
+ connect \$177 $and$libresoc.v:197472$14572_Y
+ connect \$15 $ternary$libresoc.v:197473$14573_Y
+ connect \$179 $lt$libresoc.v:197474$14574_Y
+ connect \$181 $and$libresoc.v:197475$14575_Y
+ connect \$183 $lt$libresoc.v:197476$14576_Y
+ connect \$185 $and$libresoc.v:197477$14577_Y
+ connect \$187 $lt$libresoc.v:197478$14578_Y
+ connect \$189 $and$libresoc.v:197479$14579_Y
+ connect \$191 $lt$libresoc.v:197480$14580_Y
+ connect \$193 $and$libresoc.v:197481$14581_Y
+ connect \$195 $lt$libresoc.v:197482$14582_Y
+ connect \$197 $and$libresoc.v:197483$14583_Y
+ connect \$1 $eq$libresoc.v:197484$14584_Y
+ connect \$199 $lt$libresoc.v:197485$14585_Y
+ connect \$201 $and$libresoc.v:197486$14586_Y
+ connect \$204 $eq$libresoc.v:197487$14587_Y
+ connect \$203 $ternary$libresoc.v:197488$14588_Y
+ connect \$20 $eq$libresoc.v:197489$14589_Y
+ connect \$19 $ternary$libresoc.v:197490$14590_Y
+ connect \$24 $eq$libresoc.v:197491$14591_Y
+ connect \$23 $ternary$libresoc.v:197492$14592_Y
+ connect \$28 $eq$libresoc.v:197493$14593_Y
+ connect \$27 $ternary$libresoc.v:197494$14594_Y
+ connect \$32 $eq$libresoc.v:197495$14595_Y
+ connect \$31 $ternary$libresoc.v:197496$14596_Y
+ connect \$36 $eq$libresoc.v:197497$14597_Y
+ connect \$35 $ternary$libresoc.v:197498$14598_Y
+ connect \$3 $eq$libresoc.v:197499$14599_Y
+ connect \$40 $eq$libresoc.v:197500$14600_Y
+ connect \$39 $ternary$libresoc.v:197501$14601_Y
+ connect \$44 $eq$libresoc.v:197502$14602_Y
+ connect \$43 $ternary$libresoc.v:197503$14603_Y
+ connect \$48 $eq$libresoc.v:197504$14604_Y
+ connect \$47 $ternary$libresoc.v:197505$14605_Y
+ connect \$52 $eq$libresoc.v:197506$14606_Y
+ connect \$51 $ternary$libresoc.v:197507$14607_Y
+ connect \$56 $eq$libresoc.v:197508$14608_Y
+ connect \$55 $ternary$libresoc.v:197509$14609_Y
+ connect \$5 $and$libresoc.v:197510$14610_Y
+ connect \$60 $eq$libresoc.v:197511$14611_Y
+ connect \$59 $ternary$libresoc.v:197512$14612_Y
+ connect \$64 $eq$libresoc.v:197513$14613_Y
+ connect \$63 $ternary$libresoc.v:197514$14614_Y
+ connect \$68 $eq$libresoc.v:197515$14615_Y
+ connect \$67 $ternary$libresoc.v:197516$14616_Y
+ connect \$71 $shr$libresoc.v:197517$14617_Y [0]
+ connect \$73 $and$libresoc.v:197518$14618_Y
+ connect \$75 $lt$libresoc.v:197519$14619_Y
+ connect \$77 $and$libresoc.v:197520$14620_Y
+ connect \$79 $lt$libresoc.v:197521$14621_Y
+ connect \$81 $and$libresoc.v:197522$14622_Y
+ connect \$83 $lt$libresoc.v:197523$14623_Y
+ connect \$85 $and$libresoc.v:197524$14624_Y
+ connect \$87 $lt$libresoc.v:197525$14625_Y
+ connect \$8 $eq$libresoc.v:197526$14626_Y
+ connect \$89 $and$libresoc.v:197527$14627_Y
+ connect \$91 $lt$libresoc.v:197528$14628_Y
+ connect \$93 $and$libresoc.v:197529$14629_Y
+ connect \$95 $lt$libresoc.v:197530$14630_Y
+ connect \$97 $and$libresoc.v:197531$14631_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff