add extra args to ISA in branch test_pipe_caller

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 99913dcbc8ee82e2861c5288ca69c6ca6ca6519c..199a5eba9e9b17adb22d3e06c73ad6c4df3e7e07 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -181,7 +181,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                                test.mem, test.msr)
                 initial_cia = 0x2000
                 simulator.set_pc(initial_cia)
                 gen = program.generate_instructions()