tweak pin names to allow pack to be called

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 379b01237db3074eb891c1fbd89a938929e86351..0a94bdbe07cadd27e8b6e7bc5a0b4054140a9e26 100644 (file)
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -130,26 +130,6 @@ package slow_peripherals;
     /*========== pinmux connections ============*/
 {7}
 {8}
-    rule connect_i2c0_scl;
-      pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
-      pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
-    endrule
-    rule connect_i2c0_scl_in;
-      i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
-    endrule
-    rule connect_i2c0_sda;
-      pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
-      pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
-    endrule
-    rule connect_i2c0_sda_in;
-      i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
-    endrule
-    rule connect_uart1tx;
-      pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
-    endrule
-    rule connect_uart1rx;
-      uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
-    endrule
     for(Integer i=0;i<32;i=i+ 1)begin
       rule connect_int_to_plic(wr_interrupt[i]==1);
                                ff_gateway_queue[i].enq(1);

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 9d63f874e28a70f5d71345ad60c992e5aef6a428..82d7e6b1a3cd0ac37e45738afde6bfba8c4a02d6 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -61,7 +61,9 @@ class PBase(object):
                 if p.get('outen'):
                     fname = self.pinname_outen(pname)
                 if fname:
-                    ret.append("      {0}_outen({1}.{2});".format(ps, n, fname))
+                    fname = "{0}{1}.{2}".format(n, count, fname)
+                    fname = self.pinname_tweak(pname, 'outen', fname)
+                    ret.append("      {0}_outen({1});".format(ps, fname))
                 ret.append("    endrule")
             if typ == 'in' or typ == 'inout':
                 fname = self.pinname_in(pname)
@@ -112,6 +114,8 @@ class PBase(object):
     def pinname_outen(self, pname):
         return ''
 
+    def pinname_tweak(self, pname, typ, txt):
+        return txt
 
 class uart(PBase):
 
@@ -200,6 +204,10 @@ class twi(PBase):
         return {'sda': 'out.sda_outen',
                 'scl': 'out.scl_outen'}.get(pname, '')
 
+    def pinname_tweak(self, pname, typ, txt):
+        if typ == 'outen':
+            return "pack({0})".format(txt)
+        return txt
 
 
 class qspi(PBase):