adding bus data width of 64 in litex sim doesnt work

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 7d883b911976ccc0957a00890c7b369c2ca95f54..4ecb3ad550654e94be484b68d9df2048f8555906 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -32,6 +32,7 @@ class LibreSoCSim(SoCCore):
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
+            #bus_data_width           = 64,
             uart_name                = "sim",
             integrated_rom_size      = 0x10000,
             integrated_main_ram_size = 0x10000000) # 256MB