update comments on condition register

diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py
index dea936a6071417fc4d28c3dffdd8d903bf8bace0..b3b2b44fa1aa6dff2e7d6d90e82e376b1fd419b2 100644 (file)
--- a/src/soc/cr/main_stage.py
+++ b/src/soc/cr/main_stage.py
@@ -1,6 +1,7 @@
 # This stage is intended to do Condition Register instructions
 # and output, as well as carry and overflow generation.
-# NOTE: we really should be doing the field decoding which
+# NOTE: with the exception of mtcrf and mfcr, we really should be doing
+# the field decoding which
 # selects which bits of CR are to be read / written, back in the
 # decoder / insn-isue, have both self.i.cr and self.o.cr
 # be broken down into 4-bit-wide "registers", with their