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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 12 May 2021 12:04:51 +0000 (13:04 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 12 May 2021 12:04:51 +0000 (13:04 +0100)
src/soc/experiment/test/test_mmu_dcache_pi.py

index 7f95f7d6a1d1d242dbee26dc833d50440675a0ed..3faeb53f24c932b3a71457917fe864442a18fc55 100644 (file)
@@ -90,6 +90,7 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase):
         data = self.dcache.d_out.data
         return data, ld_ok
 
+
         # DCacheToLoadStore1Type NC
         # store_done
         # error
@@ -223,6 +224,7 @@ def mmu_sim(dut):
 
     stop = True
 
+
 def test_mmu():
     mmu = MMU()
     dcache = DCache()
@@ -240,5 +242,6 @@ def test_mmu():
     with sim.write_vcd('test_mmu_pi.vcd'):
         sim.run()
 
+
 if __name__ == '__main__':
     test_mmu()