instrs = []
if False:
- for i in range(2):
+ for i in range(50):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
dest = randint(1, dut.n_regs-1)
- break
if dest not in [src1, src2]:
break
#src1 = 2
#dest = 2
op = randint(0, 1)
- op = i % 2
- op = 0
- instrs.append((src1, src2, dest, op))
+ #op = i % 2
+ #op = 0
+
+ instrs.append((src1, src2, dest, op))
if False:
instrs.append((2, 3, 3, 0))
instrs.append((5, 3, 3, 1))
- if True:
+ if False:
instrs.append((5, 6, 2, 1))
instrs.append((2, 2, 4, 0))
#instrs.append((2, 2, 3, 1))
+ if False:
+ instrs.append((2, 1, 2, 0))
+
+ if False:
+ instrs.append((2, 6, 2, 1))
+ instrs.append((2, 1, 2, 0))
+
+ if True:
+ instrs.append((1, 4, 7, 1))
+ instrs.append((7, 1, 5, 0))
+ instrs.append((4, 3, 1, 1))
+ instrs.append((6, 5, 7, 1))
+
for i, (src1, src2, dest, op) in enumerate(instrs):
print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
(src2_c, self.src2_i)]:
m.d.comb += c.reg_i.eq(reg)
+ # wark-wark: yes, writing to the same reg you are reading is *NOT*
+ # a write-after-read hazard.
+ selfhazard = Signal(reset_less=False)
+ m.d.comb += selfhazard.eq((self.dest_i & self.src1_i) |
+ (self.dest_i & self.src2_i))
+
# connect up hazard checks: read-after-write and write-after-read
- m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
+ with m.If(~selfhazard):
+ m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
# to be accumulated to indicate if register is in use (globally)
# after ORing, is fed back in to rd_pend_i / wr_pend_i
m.d.comb += self.rd_rsel_o.eq(src1_c.q_o | src2_c.q_o)
- m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
+ with m.If(~selfhazard):
+ m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
return m