intfu_rd_pend_v = Signal(n_int_fus, reset_less = True)
intfu_wr_pend_v = Signal(n_int_fus, reset_less = True)
for i in range(n_int_fus):
- m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_rd_pend_o.bool())
- m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_wr_pend_o.bool())
- #m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_readable_o)
- #m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_writable_o)
+ #m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_rd_pend_o.bool())
+ #m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_wr_pend_o.bool())
+ m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_readable_o)
+ m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_writable_o)
# Connect INT Fn Unit global wr/rd pending
for fu in if_l:
- m.d.comb += fu.g_int_wr_pend_i.eq(intfu_wr_pend_v)
- m.d.comb += fu.g_int_rd_pend_i.eq(intfu_rd_pend_v)
+ m.d.sync += fu.g_int_wr_pend_i.eq(intfu_wr_pend_v)
+ m.d.sync += fu.g_int_rd_pend_i.eq(intfu_rd_pend_v)
# Connect FU-FU Matrix, NOTE: FN Units readable/writable considered
# to be unit "read-pending / write-pending"
g_rd = Signal(self.reg_width, reset_less=True)
ro = Signal(reset_less=True)
m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
- m.d.comb += ro.eq(~g_rd.bool())
- m.d.comb += self.readable_o.eq(ro & rd_l.q)
+ m.d.comb += ro.eq(~g_rd.bool() & rd_l.q)
+ m.d.comb += self.readable_o.eq(ro)
# writable output signal
g_wr_v = Signal(self.reg_width, reset_less=True)
wo = Signal(reset_less=True)
m.d.comb += g_wr_v.eq(g_pend_i & xx_pend_o)
m.d.comb += g_wr.eq(~g_wr_v.bool())
- m.d.comb += wo.eq(g_wr & rd_l.qn & self.req_rel_i & shadown)
+ m.d.comb += wo.eq(g_wr & rd_l.q & shadown)
m.d.comb += writable_o.eq(wo)
return m
def elaborate(self, platform):
m = Module()
m.d.comb += self.readable_o.eq(self.rd_pend_i.bool())
- m.d.comb += self.writable_o.eq(~self.wr_pend_i.bool())
+ m.d.comb += self.writable_o.eq(self.wr_pend_i.bool())
return m