sigh - another instance where write-mask needed to mask out wr.rel

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 350b4b82a46d0d064f4ac6cd0329e60c00bb7952..baebed0974d86b6af81df45cbdbec14a9db68bb9 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -199,7 +199,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # is enough, when combined with when read-phase is done (rst_l.q)
         wr_any = Signal(reset_less=True)
         req_done = Signal(reset_less=True)
-        m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel.bool()))
+        m.d.comb += self.done_o.eq(self.busy_o & \
+                                   ~((self.wr.rel & ~self.wrmask).bool()))
         m.d.comb += wr_any.eq(self.wr.go.bool())
         m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \
                 ((req_l.q & self.wrmask) == 0))