Revert Microwatt workaround

The Icache and Dcache controllers are sending
out invalid accesses to Wishbone address space
that is not wired to peripherals, due to a old
Microwat workaround being re-added.

This commit removes the workaround and reenables
the lower address bits, re-aligning the *Cache and
Wishbone address spaces, thus allowing access to
the peripherals.

This partially resolves bug #812

diff --git a/src/soc/bus/external_core.py b/src/soc/bus/external_core.py
index 102e66cffcdf0e35a07cd4985c41ab680acadef1..498f9cf346e04050182c54c7d0d542d2beb8a74f 100644 (file)
--- a/src/soc/bus/external_core.py
+++ b/src/soc/bus/external_core.py
@@ -82,11 +82,10 @@ class ExternalCore(Elaboratable):
         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
         ibus, dbus, dmi = self.ibus, self.dbus, self.dmi
 
-        # sigh, microwatt wishbone address is borked, it contains the 3 LSBs
         ibus_adr = Signal(32)
         dbus_adr = Signal(32)
-        m.d.comb += ibus.adr.eq(ibus_adr[3:])
-        m.d.comb += dbus.adr.eq(dbus_adr[3:])
+        m.d.comb += ibus.adr.eq(ibus_adr)
+        m.d.comb += dbus.adr.eq(dbus_adr)
 
         kwargs = {
             # clock/reset signals