Reduce ECP5 85 nest frequency to 75MHz

This gets much closer to passing timing on the
-7 speed grade parts, and should pass timing
on the -8 speed grade parts.

Verified to boot correctly:

fw..DRAM init... initseq
done
MR profile: 00000B20 00000806 00000200 00000000
Rdly
p0: 01110011
Rdly
p1: 01110011
Auto calibrating... find mindone
Auto calibration profile:p0 rdly:00000002 p1 rdly:00000002
Reloading built-in calibration profile...DRAM test...
done

diff --git a/src/ls2.py b/src/ls2.py
index b05cf2e489520fe19a42426609a4b2b8eedc7c27..3f1e78a3f985cbb5467a9b377a703448fd6ac18e 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -738,10 +738,10 @@ def build_platform(fpga, firmware):
         core_freq = 50e6
         # DDR3 system interface is clocked at the nest frequency.
         # 50MHz works.  100MHz works.  55MHz does NOT work.
-        # Stick with multiples of 50MHz...
+        # Stick with multiples of 25MHz...
         # Note the actual DDR3 clock is 2x the nest, as the name
         # implies...
-        nest_freq = 100e6
+        nest_freq = 75e6
     if fpga == 'arty_a7':
         core_freq = 50e6
         nest_freq = core_freq