adjusting ISACaller unit test to use ISACaller.setup_one()

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index e85cd6269f54f5de1da71709ad58e7ce73d1a8e7..c1372a9a550117d37573970f7b7df7cd6dfda0ef 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -13,6 +13,7 @@ related bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=424
 """
 
+from nmigen.back.pysim import Settle
 from functools import wraps
 from copy import copy
 from soc.decoder.orderedset import OrderedSet
@@ -358,7 +359,7 @@ class ISACaller:
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
-        self.svstate = SVSTATE(initial_svstate)
+        self.svstate = SVP64State(initial_svstate)
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
@@ -607,6 +608,10 @@ class ISACaller:
         yield self.dec2.state.msr.eq(self.msr.value)
         yield self.dec2.state.pc.eq(pc)
 
+        # SVP64.  first, check if the opcode is EXT001
+        yield Settle()
+        opcode = yield self.dec2.dec.opcode_in
+
     def execute_one(self):
         """execute one instruction
         """

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 4a6229bcea87f61dba1672fc65dc05c955521c83..998f611bc2de3548a7973acc38b5efbc06460bb2 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.isa.caller import ISACaller
@@ -26,19 +26,32 @@ class DecoderTestCase(FHDLTestCase):
 
         pdecode = create_pdecode()
 
+        gen = list(generator.generate_instructions())
+        insncode = generator.assembly.splitlines()
+        instructions = list(zip(gen, insncode))
+
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-        simulator = ISA(pdecode2, initial_regs, initial_sprs, 0)
+        simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
+                        initial_insns=gen, respect_pc=True,
+                        disassembly=insncode,
+                        bigendian=0)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
-        gen = generator.generate_instructions()
+
 
         def process():
-            instructions = list(zip(gen, generator.assembly.splitlines()))
 
-            index = simulator.pc.CIA.value//4
+            pc = simulator.pc.CIA.value
+            index = pc//4
             while index < len(instructions):
-                ins, code = instructions[index]
+                print("instr pc", pc)
+                try:
+                    yield from simulator.setup_one()
+                except KeyError:  # indicates instruction not in imem: stop
+                    break
+                yield Settle()
 
+                ins, code = instructions[index]
                 print("0x{:X}".format(ins & 0xffffffff))
                 print(code)
 
@@ -48,7 +61,8 @@ class DecoderTestCase(FHDLTestCase):
                 yield Delay(1e-6)
                 opname = code.split(' ')[0]
                 yield from simulator.call(opname)
-                index = simulator.pc.CIA.value//4
+                pc = simulator.pc.CIA.value
+                index = pc//4
 
         sim.add_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -295,11 +309,11 @@ class DecoderTestCase(FHDLTestCase):
                 sim = self.run_tst_program(program)
             print("cr", sim.cr)
             expected = (7-i)
-            # check CR itself
-            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
             # check CR[0]/1/2/3 as well
             print("cr%d", sim.crl[i])
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
+            # check CR itself
+            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 92c12f632fdea9b382fdb18d2f7d00200fb39fa1..e8edc2f933dcf9f4b60c17703f4c5983c19fad0a 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -9,7 +9,7 @@ from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.isa.caller import ISACaller, special_sprs
+from soc.decoder.isa.caller import special_sprs
 import unittest
 from nmigen.cli import rtlil
 from nmutil.formaltest import FHDLTestCase