class CheckEvent(Elaboratable):
- """helper to add indication to vcd when signals are checked"""
+ """helper to add indication to vcd when signals are checked
+ """
def __init__(self):
self.event = Signal()
class DivStateCombTest(Elaboratable):
- """Test stringing a bunch of copies of the FSM state-function together"""
+ """Test stringing a bunch of copies of the FSM state-function together
+ """
def __init__(self, quotient_width):
self.check_event = CheckEvent()
with self.subTest(quotient=f"{quotient:#x}",
remainder=f"{remainder:#x}"):
self.assertTrue((yield dut.expected_valid))
- self.assertEqual((yield dut.expected_quotient), quotient)
- self.assertEqual((yield dut.expected_remainder), remainder)
+ self.assertEqual((yield dut.expected_quotient),
+ quotient)
+ self.assertEqual((yield dut.expected_remainder),
+ remainder)
self.assertEqual((yield dut.quotient), quotient)
self.assertEqual((yield dut.remainder), remainder)
else:
remainder=f"{remainder:#x}",
now=f"{now}"):
self.assertTrue((yield dut.expected_valid))
- self.assertEqual((yield dut.expected_quotient), quotient)
- self.assertEqual((yield dut.expected_remainder), remainder)
+ self.assertEqual((yield dut.expected_quotient),
+ quotient)
+ self.assertEqual((yield dut.expected_remainder),
+ remainder)
self.assertEqual((yield dut.quotient), quotient)
self.assertEqual((yield dut.remainder), remainder)
else: