#include <gram.h>
#include "dfii.h"
#include "helpers.h"
+#include "io.h"
static void set_rdly(const struct gramCtx *ctx, unsigned int phase, unsigned int rdly) {
#ifdef GRAM_RW_FUNC
}
#else
if (phase == 0) {
- ctx->phy->rdly_p0 = rdly;
+ writel(rdly, (unsigned long)&ctx->phy->rdly_p0);
} else if (phase == 1) {
- ctx->phy->rdly_p1 = rdly;
+ writel(rdly, (unsigned long)&ctx->phy->rdly_p1);
}
#endif
}
#ifdef GRAM_RW_FUNC
gram_write(ctx, (void*)&(ctx->phy->burstdet), 0);
#else
- ctx->phy->burstdet = 0;
+ writel(0, (unsigned long)&(ctx->phy->burstdet));
#endif
}
#ifdef GRAM_RW_FUNC
return !!(gram_read(ctx, (void*)&(ctx->phy->burstdet)) & (1 << phase));
#else
- return !!(ctx->phy->burstdet & (1 << phase));
+ return !!(readl((unsigned long)&ctx->phy->burstdet) & (1 << phase));
#endif
}
#include <gram.h>
#include "dfii.h"
#include "helpers.h"
+#include "io.h"
-static void dfii_setcontrol(const struct gramCtx *ctx, uint8_t val) {
+static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) {
#ifdef GRAM_RW_FUNC
gram_write(ctx, (void*)&(ctx->core->control), val);
#else
- ctx->core->control = val;
+ writel(val, (unsigned long)&(ctx->core->control));
#endif
}
#ifdef GRAM_RW_FUNC
gram_write(ctx, (void*)&(ctx->core->phases[0].address), val);
#else
- ctx->core->phases[0].address = val;
+ writel(val, (unsigned long)&ctx->core->phases[0].address);
#endif
}
#ifdef GRAM_RW_FUNC
gram_write(ctx, (void*)&(ctx->core->phases[0].baddress), val);
#else
- ctx->core->phases[0].baddress = val;
+ writel(val, (unsigned long)&ctx->core->phases[0].baddress);
#endif
}
gram_write(ctx, (void*)&(ctx->core->phases[0].command), cmd);
gram_write(ctx, (void*)&(ctx->core->phases[0].command_issue), 1);
#else
- ctx->core->phases[0].command = cmd;
- ctx->core->phases[0].command_issue = 1;
+ writel(cmd, (unsigned long)&ctx->core->phases[0].command);
+ writel(1, (unsigned long)&ctx->core->phases[0].command_issue);
#endif
}
#include <gram.h>
#include "dfii.h"
+#include "console.h"
int gram_init(struct gramCtx *ctx, const struct gramProfile *profile, void *ddr_base, void *core_base, void *phy_base) {
ctx->ddr_base = ddr_base;
ctx->phy = phy_base;
dfii_setsw(ctx, true);
+ puts("dfii_setsw\n");
dfii_initseq(ctx, profile);
+ puts("initseq\n");
gram_load_calibration(ctx, profile);
+ puts("cal");
dfii_setsw(ctx, false);
return GRAM_ERR_NONE;