[submodule "libreriscv"]
path = libreriscv
url = https://git.libre-soc.org/git/libreriscv.git
+[submodule "src/soc/litex/florent"]
+ path = src/soc/litex/florent
+ url = https://git.libre-soc.org/git/libresoc-litex.git
+++ /dev/null
-.section .text, "ax", @progbits
-.global boot_helper
-boot_helper:
- nop # FIXME
+++ /dev/null
-# Copyright (c) 2018 Jean-François Nguyen <jf@lambdaconcept.fr>
-# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# License: BSD
-
-import os
-import subprocess
-
-from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
-
-from litex import get_data_mod
-from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
-
-CPU_VARIANTS = ["standard"]
-
-
-class LibreSOC(CPU):
- name = "libre_soc"
- human_name = "Libre-SOC"
- variants = CPU_VARIANTS
- data_width = 64
- endianness = "little"
- gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
- linker_output_format = "elf64-powerpcle"
- nop = "nop"
- io_regions = {0xc0000000: 0x10000000} # origin, length
-
- @property
- def mem_map(self):
- return {"csr": 0xc0000000}
-
- @property
- def gcc_flags(self):
- flags = "-m64 "
- flags += "-mabi=elfv2 "
- flags += "-msoft-float "
- flags += "-mno-string "
- flags += "-mno-multiple "
- flags += "-mno-vsx "
- flags += "-mno-altivec "
- flags += "-mlittle-endian "
- flags += "-mstrict-align "
- flags += "-fno-stack-protector "
- flags += "-D__microwatt__ "
- return flags
-
- def __init__(self, platform, variant="standard"):
- self.platform = platform
- self.variant = variant
- self.reset = Signal()
- self.interrupt = Signal(32)
-
- self.pc = Signal(64) # new program counter
- self.pc_ok = Signal() # change PC
- self.core_start = Signal() # stop the core
- self.core_stop = Signal() # start the core
- self.bigendian = Signal() # set to 1 for bigendian
- self.core_halted = Signal() # core is halted
- self.core_busy = Signal() # core is running (busy)
-
- # instruction and data bus: 64-bit, 48 bit addressing
- # sigh self.ibus = wishbone.Interface(data_width=32, adr_width=48)
- self.ibus = wishbone.Interface(data_width=64, adr_width=48)
- self.dbus = wishbone.Interface(data_width=64, adr_width=48)
-
- self.periph_buses = [self.ibus, self.dbus]
- self.memory_buses = []
-
- # TODO: create variants
-
- # # #
-
- self.cpu_params = dict(
- # clock / reset
- i_clk=ClockSignal(),
- i_rst=ResetSignal() | self.reset,
-
- # TODO interrupts
- #i_timer_interrupt = 0,
- #i_software_interrupt = 0,
- #i_external_interrupt = self.interrupt,
-
- # ibus
- o_ibus__stb = self.ibus.stb,
- o_ibus__cyc = self.ibus.cyc,
- o_ibus__cti = self.ibus.cti,
- o_ibus__bte = self.ibus.bte,
- o_ibus__we = self.ibus.we,
- # sigh o_ibus__adr = self.ibus.adr, # for 32-bit
- o_ibus__adr = Cat(Signal(3), self.ibus.adr), # 64-bit
- o_ibus__dat_w = self.ibus.dat_w,
- o_ibus__sel = self.ibus.sel,
- i_ibus__ack = self.ibus.ack,
- i_ibus__err = self.ibus.err,
- i_ibus__dat_r = self.ibus.dat_r,
-
- # dbus
- o_dbus__stb = self.dbus.stb,
- o_dbus__cyc = self.dbus.cyc,
- o_dbus__cti = self.dbus.cti,
- o_dbus__bte = self.dbus.bte,
- o_dbus__we = self.dbus.we,
- o_dbus__adr = Cat(Signal(3), self.dbus.adr), # 64-bit
- o_dbus__dat_w = self.dbus.dat_w,
- o_dbus__sel = self.dbus.sel,
- i_dbus__ack = self.dbus.ack,
- i_dbus__err = self.dbus.err,
- i_dbus__dat_r = self.dbus.dat_r,
-
- # monitoring / debugging
- i_go_insn_i = 1, # set to "always running"
- i_pc_i = self.pc,
- i_pc_i_ok = self.pc_ok,
- i_core_start_i = self.core_start,
- i_core_stop_i = self.core_stop,
- i_core_bigendian_i = self.bigendian,
- o_halted_o = self.core_halted,
- o_busy_o = self.core_busy
- )
-
- def set_reset_address(self, reset_address):
- assert not hasattr(self, "reset_address")
- self.reset_address = reset_address
- assert reset_address == 0x00000000
-
- @staticmethod
- def elaborate(verilog_filename):
- cli_params = []
- #sdir = get_data_mod("cpu", "libre_soc").data_location
- sdir = "./simple"
- if subprocess.call(["python3", os.path.join(sdir, "issuer_verilog.py"),
- *cli_params, verilog_filename],
- ):
- raise OSError("Unable to elaborate Libre-SOC CPU, "
- "please check your nMigen/Yosys install")
-
- def do_finalize(self):
- verilog_filename = os.path.join(self.platform.output_dir,
- "gateware", "libre-soc.v")
- self.elaborate(verilog_filename=verilog_filename)
- self.platform.add_source(verilog_filename)
- self.specials += Instance("test_issuer", **self.cpu_params)
-
+++ /dev/null
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define FIXUP_ENDIAN \
- tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
- b 191f; /* Skip trampoline if endian is good */ \
- .long 0xa600607d; /* mfmsr r11 */ \
- .long 0x01006b69; /* xori r11,r11,1 */ \
- .long 0x05009f42; /* bcl 20,31,$+4 */ \
- .long 0xa602487d; /* mflr r10 */ \
- .long 0x14004a39; /* addi r10,r10,20 */ \
- .long 0xa64b5a7d; /* mthsrr0 r10 */ \
- .long 0xa64b7b7d; /* mthsrr1 r11 */ \
- .long 0x2402004c; /* hrfid */ \
-191:
-
-
-/* Load an immediate 64-bit value into a register */
-#define LOAD_IMM64(r, e) \
- lis r,(e)@highest; \
- ori r,r,(e)@higher; \
- rldicr r,r, 32, 31; \
- oris r,r, (e)@h; \
- ori r,r, (e)@l;
-
- . = 0
-.global _start
-_start:
- FIXUP_ENDIAN
-
- /* setup stack */
- LOAD_IMM64(%r1, _fstack - 0x100)
- LOAD_IMM64(%r12, main)
- mtctr %r12,
- bctrl
- b .
-
-#define EXCEPTION(nr) \
- .= nr; \
- b .
-
- /* More exception stubs */
- EXCEPTION(0x100)
- EXCEPTION(0x200)
- EXCEPTION(0x300)
- EXCEPTION(0x380)
- EXCEPTION(0x400)
- EXCEPTION(0x480)
- EXCEPTION(0x500)
- EXCEPTION(0x600)
- EXCEPTION(0x700)
- EXCEPTION(0x800)
- EXCEPTION(0x900)
- EXCEPTION(0x980)
- EXCEPTION(0xa00)
- EXCEPTION(0xb00)
- EXCEPTION(0xc00)
- EXCEPTION(0xd00)
- EXCEPTION(0xe00)
- EXCEPTION(0xe20)
- EXCEPTION(0xe40)
- EXCEPTION(0xe60)
- EXCEPTION(0xe80)
- EXCEPTION(0xf00)
- EXCEPTION(0xf20)
- EXCEPTION(0xf40)
- EXCEPTION(0xf60)
- EXCEPTION(0xf80)
-#if 0
- EXCEPTION(0x1000)
- EXCEPTION(0x1100)
- EXCEPTION(0x1200)
- EXCEPTION(0x1300)
- EXCEPTION(0x1400)
- EXCEPTION(0x1500)
- EXCEPTION(0x1600)
-#endif
-
- .text
-
--- /dev/null
+Subproject commit c2808c908523d44211057913b68c3e24b8bf74bf
+++ /dev/null
-ls180:
- ./ls180soc.py --build --platform=ls180
- cp build/ls180/gateware/ls180.v .
- cp build/ls180/gateware/mem.init .
- cp build/ls180/gateware/mem_1.init .
- cp build/ls180/gateware/mem_2.init .
- cp build/ls180/gateware/mem_3.init .
- cp build/ls180/gateware/mem_4.init .
- cp libresoc/libresoc.v .
- yosys -p 'read_verilog libresoc.v' \
- -p 'write_ilang libresoc_cvt.il'
- yosys -p 'read_verilog ls180.v' \
- -p 'read_verilog SPBlock_512W64B8W.v' \
- -p 'write_ilang ls180_cvt.il'
- yosys -p 'read_ilang ls180_cvt.il' \
- -p 'read_ilang libresoc_cvt.il' \
- -p 'write_ilang ls180.il'
-
-versaecp5:
- ./versa_ecp5.py --sys-clk-freq=55e6 --build
-
-versaecp5load:
- ./versa_ecp5.py --sys-clk-freq=55e6 --load
+++ /dev/null
-# sim openocd test
-
-create verilog file "python issuer_verilog libresoc.v"
-copy to libresoc/ directory
-terminal 1: ./sim.py
-terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
-
-# ecp5 build
-
-./versa_ecp5.py --sys-clk-freq=55e6 --build
-./versa_ecp5.py --sys-clk-freq=55e6 --load
+++ /dev/null
-(* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a,
- input [63:0] d,
- output [63:0] q,
- input [7:0] we,
- input clk);
-endmodule // SPBlock_512W64B8W
+++ /dev/null
-// Created using Xilinx iMPACT Software [ISE WebPACK - 5.1i]
-TRST OFF;
-ENDIR IDLE;
-ENDDR IDLE;
-STATE RESET IDLE;
-TIR 0 ;
-HIR 0 ;
-TDR 0 ;
-HDR 0 ;
-// Validating chain...
-TIR 0 ;
-HIR 0 ;
-TDR 0 ;
-HDR 0 ;
-SIR 4 TDI (f) SMASK (f) ;
-TIR 0 ;
-HIR 5 TDI (1f) SMASK (1f) ;
-// don't set header to 1 extra bit
-//HDR 1 TDI (00) SMASK (01) ;
-TDR 0 ;
-//Loading device with 'idcode' instruction.
-SIR 4 TDI (1) SMASK (f) ;
-SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
-//Loading device with 'conld' instruction.
-//SIR 8 TDI (f0) ;
-RUNTEST 110000 TCK;
-
+++ /dev/null
-STATE RESET IDLE;
-TIR 0 ;
-HIR 5 TDI (1f) SMASK (1f) ;
-//HDR 1 TDI (00) SMASK (01) ;
-TDR 0 ;
-//Loading device with 'idcode' instruction.
-SIR 4 TDI (1) SMASK (f) ;
-//SDR 32 TDI (00000000) SMASK (ffffffff) TDO (00000c7f) SMASK (ffffffff) ;
-SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
-
-// set to DMI "address"
-SIR 4 TDI (8) SMASK (f) ;
-// set DMI "PC" address (2)
-SDR 8 TDI (2) SMASK (ff) ;
-// set to DMI "data read"
-SIR 4 TDI (9) SMASK (f) ;
-// read 64 bit
-SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (0000000000000000) ;
-
-// set to DMI "address"
-SIR 4 TDI (8) SMASK (f) ;
-// set DMI "CR" address (8)
-SDR 8 TDI (8) SMASK (ff) ;
-// set to DMI "data read"
-SIR 4 TDI (9) SMASK (f) ;
-// read 64 bit
-SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (ffffffffffffffff) ;
-
+++ /dev/null
-from libresoc.core import LibreSoC
\ No newline at end of file
+++ /dev/null
-.section .text, "ax", @progbits
-.global boot_helper
-boot_helper:
- nop # FIXME
+++ /dev/null
-import os
-
-from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
-
-from litex.soc.interconnect import wishbone as wb
-from litex.soc.cores.cpu import CPU
-
-from soc.config.pinouts import get_pinspecs
-from soc.debug.jtag import Pins
-from c4m.nmigen.jtag.tap import IOType
-
-from libresoc.ls180 import io
-from litex.build.generic_platform import ConstraintManager
-
-
-CPU_VARIANTS = ["standard", "standard32", "standardjtag",
- "standardjtagtestgpio", "ls180",
- "standardjtagnoirq"]
-
-
-def make_wb_bus(prefix, obj, simple=False):
- res = {}
- outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
- if not simple:
- outpins += ['cti', 'bte']
- for o in outpins:
- res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
- for i in ['ack', 'err', 'dat_r']:
- res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
- return res
-
-def make_wb_slave(prefix, obj, simple=False):
- res = {}
- inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
- if not simple:
- inpins += ['cti', 'bte']
- for i in inpins:
- res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
- for o in ['ack', 'err', 'dat_r']:
- res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
- return res
-
-def make_pad(res, dirn, name, suffix, cpup, iop):
- cpud, iod = ('i', 'o') if dirn else ('o', 'i')
- cname = '%s_%s__core__%s' % (cpud, name, suffix)
- pname = '%s_%s__pad__%s' % (iod, name, suffix)
- print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
- res[cname], res[pname] = cpup, iop
-
-def get_field(rec, name):
- for f in rec.layout:
- f = f[0]
- if f.endswith(name):
- return getattr(rec, f)
-
-
-def make_jtag_ioconn(res, pin, cpupads, iopads):
- (fn, pin, iotype, pin_name, scan_idx) = pin
- #serial_tx__core__o, serial_rx__pad__i,
- # special-case sdram_clock
- if pin == 'clock' and fn == 'sdr':
- cpu = cpupads['sdram_clock']
- io = iopads['sdram_clock']
- else:
- cpu = cpupads[fn]
- io = iopads[fn]
- print ("cpupads", cpupads)
- print ("iopads", iopads)
- print ("pin", fn, pin, iotype, pin_name)
- print ("cpu fn", cpu)
- print ("io fn", io)
- name = "%s_%s" % (fn, pin)
- print ("name", name)
- sigs = []
-
- if iotype in (IOType.In, IOType.Out):
- ps = pin.split("_")
- if pin == 'clock' and fn == 'sdr':
- cpup = cpu
- iop = io
- elif len(ps) == 2 and ps[-1].isdigit():
- pin, idx = ps
- idx = int(idx)
- print ("ps split", pin, idx)
- cpup = getattr(cpu, pin)[idx]
- iop = getattr(io, pin)[idx]
- elif pin.isdigit():
- idx = int(pin)
- print ("digit", idx)
- cpup = cpu[idx]
- iop = io[idx]
- else:
- cpup = getattr(cpu, pin)
- iop = getattr(io, pin)
-
- if iotype == IOType.Out:
- # output from the pad is routed through C4M JTAG and so
- # is an *INPUT* into core. ls180soc connects this to "real" peripheral
- make_pad(res, True, name, "o", cpup, iop)
-
- elif iotype == IOType.In:
- # input to the pad is routed through C4M JTAG and so
- # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
- make_pad(res, True, name, "i", cpup, iop)
-
- elif iotype == IOType.InTriOut:
- if fn == 'gpio': # sigh decode GPIO special-case
- idx = int(pin[1:])
- oe_idx = idx
- elif fn == 'sdr': # sigh
- idx = int(pin.split('_')[-1])
- oe_idx = 0
- else:
- idx = 0
- oe_idx = 0
- print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
- cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
- make_pad(res, True, name, "i", cpup, iop)
- cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
- make_pad(res, True, name, "o", cpup, iop)
- cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
- make_pad(res, True, name, "oe", cpup, iop)
-
- if iotype in (IOType.In, IOType.InTriOut):
- sigs.append(("i", 1))
- if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
- sigs.append(("o", 1))
- if iotype in (IOType.TriOut, IOType.InTriOut):
- sigs.append(("oe", 1))
-
-
-class LibreSoC(CPU):
- name = "libre_soc"
- human_name = "Libre-SoC"
- variants = CPU_VARIANTS
- endianness = "little"
- gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
- linker_output_format = "elf64-powerpcle"
- nop = "nop"
- io_regions = {0xc0000000: 0x10000000} # origin, length
-
- @property
- def mem_map(self):
- return {"csr": 0xc0000000}
-
- @property
- def gcc_flags(self):
- flags = "-m64 "
- flags += "-mabi=elfv2 "
- flags += "-msoft-float "
- flags += "-mno-string "
- flags += "-mno-multiple "
- flags += "-mno-vsx "
- flags += "-mno-altivec "
- flags += "-mlittle-endian "
- flags += "-mstrict-align "
- flags += "-fno-stack-protector "
- flags += "-mcmodel=small "
- flags += "-D__microwatt__ "
- return flags
-
- def __init__(self, platform, variant="standard"):
- self.platform = platform
- self.variant = variant
- self.reset = Signal()
-
- irq_en = "noirq" not in variant
-
- if irq_en:
- self.interrupt = Signal(16)
-
- if variant == "standard32":
- self.data_width = 32
- self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
- else:
- self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
- self.data_width = 64
- self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
-
- self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
- self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
-
- jtag_en = ('jtag' in variant) or variant == 'ls180'
-
- if "testgpio" in variant:
- self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
- if jtag_en:
- self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
-
- if "sram4k" in variant or variant == 'ls180':
- self.srams = srams = []
- for i in range(4):
- srams.append(wb.Interface(data_width=64, adr_width=29))
-
- self.periph_buses = [ibus, dbus]
- self.memory_buses = []
-
- if jtag_en:
- self.periph_buses.append(jtag_wb)
- self.jtag_tck = Signal(1)
- self.jtag_tms = Signal(1)
- self.jtag_tdi = Signal(1)
- self.jtag_tdo = Signal(1)
- else:
- self.dmi_addr = Signal(4)
- self.dmi_din = Signal(64)
- self.dmi_dout = Signal(64)
- self.dmi_wr = Signal(1)
- self.dmi_ack = Signal(1)
- self.dmi_req = Signal(1)
-
- # # #
-
- self.cpu_params = dict(
- # Clock / Reset
- i_clk = ClockSignal(),
- i_rst = ResetSignal() | self.reset,
-
- # Monitoring / Debugging
- i_pc_i = 0,
- i_pc_i_ok = 0,
- i_core_bigendian_i = 0, # Signal(),
- o_busy_o = Signal(), # not connected
- o_memerr_o = Signal(), # not connected
- o_pc_o = Signal(64), # not connected
- )
-
- if irq_en:
- # interrupts
- self.cpu_params['i_int_level_i'] = self.interrupt
-
- if jtag_en:
- self.cpu_params.update(dict(
- # JTAG Debug bus
- o_TAP_bus__tdo = self.jtag_tdo,
- i_TAP_bus__tdi = self.jtag_tdi,
- i_TAP_bus__tms = self.jtag_tms,
- i_TAP_bus__tck = self.jtag_tck,
- ))
- else:
- self.cpu_params.update(dict(
- # DMI Debug bus
- i_dmi_addr_i = self.dmi_addr,
- i_dmi_din = self.dmi_din,
- o_dmi_dout = self.dmi_dout,
- i_dmi_req_i = self.dmi_req,
- i_dmi_we_i = self.dmi_wr,
- o_dmi_ack_o = self.dmi_ack,
- ))
-
- # add clock select, pll output
- if variant == "ls180":
- self.pll_18_o = Signal()
- self.clk_sel = Signal(2)
- self.pll_lck_o = Signal()
- self.cpu_params['i_clk_sel_i'] = self.clk_sel
- self.cpu_params['o_pll_18_o'] = self.pll_18_o
- self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
-
- # add wishbone buses to cpu params
- self.cpu_params.update(make_wb_bus("ibus", ibus, True))
- self.cpu_params.update(make_wb_bus("dbus", dbus, True))
- self.cpu_params.update(make_wb_slave("ics_wb", ics, True))
- self.cpu_params.update(make_wb_slave("icp_wb", icp, True))
- if "testgpio" in variant:
- self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
- if jtag_en:
- self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
- if "sram4k" in variant or variant == 'ls180':
- for i, sram in enumerate(srams):
- self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i,
- sram, simple=True))
-
- # and set ibus advanced tags to zero (disable)
- self.cpu_params['i_ibus__cti'] = 0
- self.cpu_params['i_ibus__bte'] = 0
- self.cpu_params['i_dbus__cti'] = 0
- self.cpu_params['i_dbus__bte'] = 0
-
- if variant == 'ls180':
- # urr yuk. have to expose iopads / pins from core to litex
- # then back again. cut _some_ of that out by connecting
- self.padresources = io()
- self.pad_cm = ConstraintManager(self.padresources, [])
- self.cpupads = {}
- iopads = {}
- litexmap = {}
- subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
- 'pwm', 'sd0', 'sdr'}
- for periph in subset:
- origperiph = periph
- num = None
- if periph[-1].isdigit():
- periph, num = periph[:-1], int(periph[-1])
- print ("periph request", periph, num)
- if periph == 'mspi':
- if num == 0:
- periph, num = 'spimaster', None
- else:
- periph, num = 'spisdcard', None
- elif periph == 'sdr':
- periph = 'sdram'
- elif periph == 'mtwi':
- periph = 'i2c'
- elif periph == 'sd':
- periph, num = 'sdcard', None
- litexmap[origperiph] = (periph, num)
- self.cpupads[origperiph] = platform.request(periph, num)
- iopads[origperiph] = self.pad_cm.request(periph, num)
- if periph == 'sdram':
- # special-case sdram clock
- ck = platform.request("sdram_clock")
- self.cpupads['sdram_clock'] = ck
- ck = self.pad_cm.request("sdram_clock")
- iopads['sdram_clock'] = ck
-
- pinset = get_pinspecs(subset=subset)
- p = Pins(pinset)
- for pin in list(p):
- make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
-
- # add verilog sources
- self.add_sources(platform)
-
- def set_reset_address(self, reset_address):
- assert not hasattr(self, "reset_address")
- self.reset_address = reset_address
- assert reset_address == 0x00000000
-
- @staticmethod
- def add_sources(platform):
- cdir = os.path.dirname(__file__)
- platform.add_source(os.path.join(cdir, "libresoc.v"))
-
- def do_finalize(self):
- self.specials += Instance("test_issuer", **self.cpu_params)
-
+++ /dev/null
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define FIXUP_ENDIAN \
- tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
- b 191f; /* Skip trampoline if endian is good */ \
- .long 0xa600607d; /* mfmsr r11 */ \
- .long 0x01006b69; /* xori r11,r11,1 */ \
- .long 0x05009f42; /* bcl 20,31,$+4 */ \
- .long 0xa602487d; /* mflr r10 */ \
- .long 0x14004a39; /* addi r10,r10,20 */ \
- .long 0xa64b5a7d; /* mthsrr0 r10 */ \
- .long 0xa64b7b7d; /* mthsrr1 r11 */ \
- .long 0x2402004c; /* hrfid */ \
-191:
-
-
-/* Load an immediate 64-bit value into a register */
-#define LOAD_IMM64(r, e) \
- lis r,(e)@highest; \
- ori r,r,(e)@higher; \
- rldicr r,r, 32, 31; \
- oris r,r, (e)@h; \
- ori r,r, (e)@l;
-
- . = 0
-.global _start
-_start:
- FIXUP_ENDIAN
-
- /* setup stack */
- LOAD_IMM64(%r1, _fstack - 0x100)
- LOAD_IMM64(%r12, main)
- mtctr %r12,
- bctrl
- b .
-
-#define EXCEPTION(nr) \
- .= nr; \
- b .
-
- /* More exception stubs */
- EXCEPTION(0x100)
- EXCEPTION(0x200)
- EXCEPTION(0x300)
- EXCEPTION(0x380)
- EXCEPTION(0x400)
- EXCEPTION(0x480)
- EXCEPTION(0x500)
- EXCEPTION(0x600)
- EXCEPTION(0x700)
- EXCEPTION(0x800)
- EXCEPTION(0x900)
- EXCEPTION(0x980)
- EXCEPTION(0xa00)
- EXCEPTION(0xb00)
- EXCEPTION(0xc00)
- EXCEPTION(0xd00)
- EXCEPTION(0xe00)
- EXCEPTION(0xe20)
- EXCEPTION(0xe40)
- EXCEPTION(0xe60)
- EXCEPTION(0xe80)
- EXCEPTION(0xf00)
- EXCEPTION(0xf20)
- EXCEPTION(0xf40)
- EXCEPTION(0xf60)
- EXCEPTION(0xf80)
-#if 0
- EXCEPTION(0x1000)
- EXCEPTION(0x1100)
- EXCEPTION(0x1200)
- EXCEPTION(0x1300)
- EXCEPTION(0x1400)
- EXCEPTION(0x1500)
- EXCEPTION(0x1600)
-#endif
-
- .text
-
+++ /dev/null
-#ifndef __IRQ_H
-#define __IRQ_H
-
-static inline unsigned int irq_getie(void)
-{
- return 0;
-}
-
-static inline void irq_setie(unsigned int ie)
-{
- /*if(ie) csrs(); else csrc();*/
-}
-
-static inline unsigned int irq_getmask(void)
-{
- unsigned int mask = 0;
- //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
- return mask;
-}
-
-static inline void irq_setmask(unsigned int mask)
-{
- //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-}
-
-static inline unsigned int irq_pending(void)
-{
- unsigned int pending = 0;
- //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
- return pending;
-}
-
-#endif /* __IRQ_H */
+++ /dev/null
-#
-# This file is part of LiteX.
-#
-# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# SPDX-License-Identifier: BSD-2-Clause
-
-"""ls180 ASIC platform
-
-conceptually similar to the following:
-
-* https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
-* https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
-
-Total I/O pins: 84.
-Fits in a JEDEC QFP-100
-
-"""
-
-from migen.fhdl.structure import _Fragment
-from litex.build.generic_platform import (GenericPlatform, Pins,
- Subsignal, IOStandard, Misc,
- )
-import os
-
-
-def make_uart(name, num):
- return (name, num,
- Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
- Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
- )
-
-def make_gpio(name, num, n_gpio):
- pins = []
- for i in range(n_gpio):
- pins.append("X%d" % i)
- pins = ' '.join(pins)
- return (name, 0,
- Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
- Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
- Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
- IOStandard("LVCMOS33"))
-
-
-
-# IOs ---------------------------------------------------------------------
-
-def io():
- _io = [
- # CLK/RST: 2 pins
- ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
- ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
- ("sys_clksel_i", 0, Pins("R1 R2"), IOStandard("LVCMOS33")),
- ("sys_pll_18_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
- ("sys_pll_lck_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
-
- # JTAG0: 4 pins
- ("jtag", 0,
- Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
- Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
- Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
- Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
- ),
-
- # I2C0: 2 pins
- ("i2c", 0,
- Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
- Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
- Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
- Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
- ),
-
- # SPI0: 4 pins
- ("spimaster", 0,
- Subsignal("clk", Pins("J1")),
- Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
- Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
- Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
- Misc("SLEWRATE=FAST"),
- IOStandard("LVCMOS33"),
- ),
-
- # SPICARD0: 4 pins
- ("spisdcard", 0,
- Subsignal("clk", Pins("J1")),
- Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
- Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
- Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
- Misc("SLEWRATE=FAST"),
- IOStandard("LVCMOS33"),
- ),
-
- # SDCARD0: 6 pins
- ("sdcard", 0,
- Subsignal("clk", Pins("J1")),
- Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
- Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
- Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
- Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
- Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
- Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
- Misc("SLEWRATE=FAST"),
- IOStandard("LVCMOS33"),
- ),
-
- # SDRAM: 39 pins
- ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
- ("sdram", 0,
- Subsignal("a", Pins(
- "M20 M19 L20 L19 K20 K19 K18 J20",
- "J19 H20 N19 G20 G19")),
- Subsignal("dq_i", Pins(
- "J16 L18 M18 N18 P18 T18 T17 U20",
- "E19 D20 D19 C20 E18 F18 J18 J17")),
- Subsignal("dq_o", Pins(
- "J16 L18 M18 N18 P18 T18 T17 U20",
- "E19 D20 D19 C20 E18 F18 J18 J17")),
- Subsignal("dq_oe", Pins("J17")),
- Subsignal("we_n", Pins("T20")),
- Subsignal("ras_n", Pins("R20")),
- Subsignal("cas_n", Pins("T19")),
- Subsignal("cs_n", Pins("P30")),
- Subsignal("cke", Pins("F21")),
- Subsignal("ba", Pins("P19 N20")),
- Subsignal("dm", Pins("U19 E20")),
- IOStandard("LVCMOS33"),
- Misc("SLEWRATE=FAST"),
- ),
-
- # PWM: 2 pins
- ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")),
- ]
-
- n_gpio = 16
-
- # 16 GPIOs
- _io.append( make_gpio("gpio", 0, n_gpio) )
-
- # EINT: 3 pins
- _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
-
- # UART0: 2 pins
- _io.append(make_uart("uart", 0))
- # UART1: 2 pins
- _io.append(make_uart("uart", 1))
-
- # not connected - eurgh have to adjust this to match the total pincount.
- num_nc = 24
- nc = ' '.join("NC%d" % i for i in range(num_nc))
- _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
-
- return _io
-
-# Platform ----------------------------------------------------------------
-
-class LS180Platform(GenericPlatform):
- default_clk_name = "sys_clk"
- default_clk_period = 1e9/50e6
-
- def __init__(self, device="LS180", **kwargs):
- assert device in ["LS180"]
- GenericPlatform.__init__(self, device, io(), **kwargs)
-
- def build(self, fragment,
- build_dir = "build",
- build_name = "top",
- run = True,
- timingstrict = True,
- **kwargs):
-
- platform = self
-
- # Create build directory
- os.makedirs(build_dir, exist_ok=True)
- cwd = os.getcwd()
- os.chdir(build_dir)
-
- # Finalize design
- if not isinstance(fragment, _Fragment):
- fragment = fragment.get_fragment()
- platform.finalize(fragment)
-
- # Generate verilog
- v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
- named_sc, named_pc = platform.resolve_signals(v_output.ns)
- v_file = build_name + ".v"
- v_output.write(v_file)
- platform.add_source(v_file)
-
- os.chdir(cwd)
-
- return v_output.ns
-
- def do_finalize(self, fragment):
- super().do_finalize(fragment)
- return
- self.add_period_constraint(self.lookup_request("clk", loose=True),
- 1e9/50e6)
+++ /dev/null
-#ifndef __SYSTEM_H
-#define __SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
-__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
-void flush_l2_cache(void);
-
-void busy_wait(unsigned int ms);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_H */
+++ /dev/null
-N0 | VSS
-N1 | sys_clk
-N2 | VSS
-N3 | sys_rst
-N4 | JTAG0 tck
-N5 | JTAG0 tms
-N6 | JTAG0 tdi
-N7 | JTAG0 tdo
-N8 | UART0 tx
-N9 | UART0 rx
-N10 | GPIO0 gpio0
-N11 | GPIO0 gpio1
-N12 | VDD
-N13 | SPI0 clk
-N14 | SPI0 mosi
-N15 | SPI0 cs_n
-N16 | SPI0 miso
-N17 | VSS
-N18 | SDCARD0 clk
-N19 | SDCARD0 cmd
-N20 | SDCARD0 data0
-N21 | SDCARD0 data1
-N22 | SDCARD0 data2
-N23 | SDCARD0 data3
-N24 | VDD
-N25 | SDRAM0 cs0_n
-N26 | SDRAM0 cs1_n
-N27 | SDRAM0 cke0
-N28 | SDRAM0 cke1
-N29 | VDD
-N30 | nc
-N31 | VSS
-
-E0 | VDD
-E1 | SDRAM0 a0
-E2 | SDRAM0 a1
-E3 | SDRAM0 a2
-E4 | SDRAM0 a3
-E5 | SDRAM0 a4
-E6 | SDRAM0 a5
-E7 | SDRAM0 a6
-E8 | SDRAM0 a7
-E9 | VSS
-E10 | SDRAM0 a8
-E11 | SDRAM0 a9
-E12 | SDRAM0 a10
-E13 | SDRAM0 a11
-E14 | SDRAM0 a12
-E15 | SDRAM0 a13
-E16 | SDRAM0 a14
-E17 | SDRAM0 a15
-E18 | VDD
-E19 | nc
-E20 | VSS
-E21 | SDRAM0 we_n
-E22 | SDRAM0 ras_n
-E23 | SDRAM0 cas_n
-E24 | nc
-E25 | VDD
-E26 | SDRAM0 ba0
-E27 | SDRAM0 ba1
-E28 | SDRAM0 dm0
-E29 | SDRAM0 dm1
-E30 | VSS
-E31 | SDRAM0 sdram_clock
-
-S0 | nc
-S1 | VDD
-S2 | SDRAM0 dq0
-S3 | SDRAM0 dq1
-S4 | SDRAM0 dq2
-S5 | SDRAM0 dq3
-S6 | SDRAM0 dq4
-S7 | SDRAM0 dq5
-S8 | SDRAM0 dq6
-S9 | SDRAM0 dq7
-S10 | VSS
-S11 | SDRAM0 dq8
-S12 | SDRAM0 dq9
-S13 | SDRAM0 dq10
-S14 | SDRAM0 dq11
-S15 | SDRAM0 dq12
-S16 | SDRAM0 dq13
-S17 | SDRAM0 dq14
-S18 | SDRAM0 dq15
-S19 | VDD
-S20 | PWM0 pwm0
-S21 | PWM1 pwm1
-S22 | VSS
-S23 | EINT0 eint0
-S24 | GPIO0 gpio14
-S25 | GPIO0 gpio15
-S26 | nc
-S27 | nc
-S28 | nc
-S29 | nc
-S30 | nc
-S31 | VDD
-
-W0 | VSS
-W1 | SPI1 clk
-W2 | SPI1 mosi
-W3 | SPI1 cs_n
-W4 | SPI1 miso
-W5 | VDD
-W6 | UART1 tx
-W7 | UART1 rx
-W8 | GPIO0 gpio2
-W9 | GPIO0 gpio3
-W10 | GPIO0 gpio4
-W11 | GPIO0 gpio5
-W12 | GPIO0 gpio6
-W13 | GPIO0 gpio7
-W14 | GPIO0 gpio8
-W15 | GPIO0 gpio9
-W16 | GPIO0 gpio10
-W17 | GPIO0 gpio11
-W18 | GPIO0 gpio12
-W19 | GPIO0 gpio13
-W20 | VSS
-W21 | EINT0 eint1
-W22 | EINT0 eint2
-W23 | I2C0 sda
-W24 | I2C0 scl
-W25 | nc
-W26 | nc
-W27 | nc
-W28 | nc
-W29 | nc
-W30 | nc
-W31 | VDD
+++ /dev/null
-#!/usr/bin/env python3
-
-import os
-import argparse
-from functools import reduce
-from operator import or_
-
-from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
- Cat, Record, ClockSignal, wrap, ResetInserter)
-
-from litex.build.generic_platform import Pins, Subsignal
-from litex.build.sim import SimPlatform
-from litex.build.io import CRG
-from litex.build.sim.config import SimConfig
-
-from litex.soc.integration.soc import SoCRegion
-from litex.soc.integration.soc_core import SoCCore
-from litex.soc.integration.soc_sdram import SoCSDRAM
-from litex.soc.integration.builder import Builder
-from litex.soc.integration.common import get_mem_data
-
-from litedram import modules as litedram_modules
-from litedram.phy.model import SDRAMPHYModel
-#from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
-from litedram.common import PHYPadsCombiner, PhySettings
-from litedram.phy.dfi import Interface as DFIInterface
-from litex.soc.cores.spi import SPIMaster
-from litex.soc.cores.pwm import PWM
-#from litex.soc.cores.bitbang import I2CMaster
-from litex.soc.cores import uart
-
-from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
-
-from litex.tools.litex_sim import Platform
-from libresoc.ls180 import LS180Platform
-
-from migen import Module
-from litex.soc.interconnect.csr import AutoCSR
-
-from libresoc import LibreSoC
-from microwatt import Microwatt
-
-# HACK!
-from litex.soc.integration.soc import SoCCSRHandler
-SoCCSRHandler.supported_address_width.append(12)
-
-# GPIO Tristate -------------------------------------------------------
-# doesn't work properly.
-#from litex.soc.cores.gpio import GPIOTristate
-from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
-from migen.genlib.cdc import MultiReg
-
-# Imports
-from litex.soc.interconnect import wishbone
-from litesdcard.phy import (SDPHY, SDPHYClocker,
- SDPHYInit, SDPHYCMDW, SDPHYCMDR,
- SDPHYDATAW, SDPHYDATAR,
- _sdpads_layout)
-from litesdcard.core import SDCore
-from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
-from litex.build.io import SDROutput, SDRInput
-
-
-# I2C Master Bit-Banging --------------------------------------------------
-
-class I2CMaster(Module, AutoCSR):
- """I2C Master Bit-Banging
-
- Provides the minimal hardware to do software I2C Master bit banging.
-
- On the same write CSRStorage (_w), software can control SCL (I2C_SCL),
- SDA direction and value (I2C_OE, I2C_W). Software get back SDA value
- with the read CSRStatus (_r).
- """
- pads_layout = [("scl", 1), ("sda", 1)]
- def __init__(self, pads):
- self.pads = pads
- self._w = CSRStorage(fields=[
- CSRField("scl", size=1, offset=0),
- CSRField("oe", size=1, offset=1),
- CSRField("sda", size=1, offset=2)],
- name="w")
- self._r = CSRStatus(fields=[
- CSRField("sda", size=1, offset=0)],
- name="r")
-
- self.connect(pads)
-
- def connect(self, pads):
- _sda_w = Signal()
- _sda_oe = Signal()
- _sda_r = Signal()
- self.comb += [
- pads.scl.eq(self._w.fields.scl),
- pads.sda_oe.eq( self._w.fields.oe),
- pads.sda_o.eq( self._w.fields.sda),
- self._r.fields.sda.eq(pads.sda_i),
- ]
-
-
-class GPIOTristateASIC(Module, AutoCSR):
- def __init__(self, pads, prange=None):
- nbits = len(pads.oe) # hack
- self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
- self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
- self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
-
- # # #
-
- _pads = Record( (("i", nbits),
- ("o", nbits),
- ("oe", nbits)))
- self.comb += _pads.i.eq(pads.i)
- self.comb += pads.o.eq(_pads.o)
- self.comb += pads.oe.eq(_pads.oe)
-
- self.comb += _pads.oe.eq(self._oe.storage)
- self.comb += _pads.o.eq(self._out.storage)
- if prange is None:
- prange = range(nbits)
- for i in prange:
- self.specials += MultiReg(_pads.i[i], self._in.status[i])
-
-# SDCard PHY IO -------------------------------------------------------
-
-class SDRPad(Module):
- def __init__(self, pad, name, o, oe, i):
- clk = ClockSignal()
- _o = getattr(pad, "%s_o" % name)
- _oe = getattr(pad, "%s_oe" % name)
- _i = getattr(pad, "%s_i" % name)
- self.specials += SDROutput(clk=clk, i=oe, o=_oe)
- for j in range(len(_o)):
- self.specials += SDROutput(clk=clk, i=o[j], o=_o[j])
- self.specials += SDRInput(clk=clk, i=_i[j], o=i[j])
-
-
-class SDPHYIOGen(Module):
- def __init__(self, clocker, sdpads, pads):
- # Rst
- if hasattr(pads, "rst"):
- self.comb += pads.rst.eq(0)
-
- # Clk
- self.specials += SDROutput(
- clk = ClockSignal(),
- i = ~clocker.clk & sdpads.clk,
- o = pads.clk
- )
-
- # Cmd
- c = sdpads.cmd
- self.submodules.sd_cmd = SDRPad(pads, "cmd", c.o, c.oe, c.i)
-
- # Data
- d = sdpads.data
- self.submodules.sd_data = SDRPad(pads, "data", d.o, d.oe, d.i)
-
-
-class SDPHY(Module, AutoCSR):
- def __init__(self, pads, device, sys_clk_freq,
- cmd_timeout=10e-3, data_timeout=10e-3):
- self.card_detect = CSRStatus() # Assume SDCard is present if no cd pin.
- self.comb += self.card_detect.status.eq(getattr(pads, "cd", 0))
-
- self.submodules.clocker = clocker = SDPHYClocker()
- self.submodules.init = init = SDPHYInit()
- self.submodules.cmdw = cmdw = SDPHYCMDW()
- self.submodules.cmdr = cmdr = SDPHYCMDR(sys_clk_freq,
- cmd_timeout, cmdw)
- self.submodules.dataw = dataw = SDPHYDATAW()
- self.submodules.datar = datar = SDPHYDATAR(sys_clk_freq,
- data_timeout)
-
- # # #
-
- self.sdpads = sdpads = Record(_sdpads_layout)
-
- # IOs
- sdphy_cls = SDPHYIOGen
- self.submodules.io = sdphy_cls(clocker, sdpads, pads)
-
- # Connect pads_out of submodules to physical pads --------------
- pl = [init, cmdw, cmdr, dataw, datar]
- self.comb += [
- sdpads.clk.eq( reduce(or_, [m.pads_out.clk for m in pl])),
- sdpads.cmd.oe.eq( reduce(or_, [m.pads_out.cmd.oe for m in pl])),
- sdpads.cmd.o.eq( reduce(or_, [m.pads_out.cmd.o for m in pl])),
- sdpads.data.oe.eq(reduce(or_, [m.pads_out.data.oe for m in pl])),
- sdpads.data.o.eq( reduce(or_, [m.pads_out.data.o for m in pl])),
- ]
- for m in pl:
- self.comb += m.pads_out.ready.eq(self.clocker.ce)
-
- # Connect physical pads to pads_in of submodules ---------------
- for m in pl:
- self.comb += m.pads_in.valid.eq(self.clocker.ce)
- self.comb += m.pads_in.cmd.i.eq(sdpads.cmd.i)
- self.comb += m.pads_in.data.i.eq(sdpads.data.i)
-
- # Speed Throttling -------------------------------------------
- self.comb += clocker.stop.eq(dataw.stop | datar.stop)
-
-
-# Generic SDR PHY ---------------------------------------------------------
-
-class GENSDRPHY(Module):
- def __init__(self, pads, cl=2, cmd_latency=1):
- pads = PHYPadsCombiner(pads)
- addressbits = len(pads.a)
- bankbits = len(pads.ba)
- nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
- databits = len(pads.dq_i)
- assert cl in [2, 3]
- assert databits%8 == 0
-
- # PHY settings ----------------------------------------------------
- self.settings = PhySettings(
- phytype = "GENSDRPHY",
- memtype = "SDR",
- databits = databits,
- dfi_databits = databits,
- nranks = nranks,
- nphases = 1,
- rdphase = 0,
- wrphase = 0,
- rdcmdphase = 0,
- wrcmdphase = 0,
- cl = cl,
- read_latency = cl + cmd_latency,
- write_latency = 0
- )
-
- # DFI Interface ---------------------------------------------------
- self.dfi = dfi = DFIInterface(addressbits, bankbits, nranks, databits)
-
- # # #
-
- # Iterate on pads groups ------------------------------------------
- for pads_group in range(len(pads.groups)):
- pads.sel_group(pads_group)
-
- # Addresses and Commands --------------------------------------
- p0 = dfi.p0
- self.specials += [SDROutput(i=p0.address[i], o=pads.a[i])
- for i in range(len(pads.a))]
- self.specials += [SDROutput(i=p0.bank[i], o=pads.ba[i])
- for i in range(len(pads.ba))]
- self.specials += SDROutput(i=p0.cas_n, o=pads.cas_n)
- self.specials += SDROutput(i=p0.ras_n, o=pads.ras_n)
- self.specials += SDROutput(i=p0.we_n, o=pads.we_n)
- if hasattr(pads, "cke"):
- for i in range(len(pads.cke)):
- self.specials += SDROutput(i=p0.cke[i], o=pads.cke[i])
- if hasattr(pads, "cs_n"):
- for i in range(len(pads.cs_n)):
- self.specials += SDROutput(i=p0.cs_n[i], o=pads.cs_n[i])
-
- # DQ/DM Data Path -------------------------------------------------
-
- d = dfi.p0
- wren = []
- self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata)
-
- if hasattr(pads, "dm"):
- for i in range(len(pads.dm)):
- self.specials += SDROutput(i=d.wrdata_mask[i], o=pads.dm[i])
-
- # DQ/DM Control Path ----------------------------------------------
- rddata_en = Signal(cl + cmd_latency)
- self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en))
- self.sync += dfi.p0.rddata_valid.eq(rddata_en[-1])
-
-
-# LibreSoC 180nm ASIC -------------------------------------------------------
-
-class LibreSoCSim(SoCCore):
- def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
- sdram_module = "AS4C16M16",
- #sdram_data_width = 16,
- #sdram_module = "MT48LC16M16",
- sdram_data_width = 16,
- irq_reserved_irqs = {'uart': 0},
- platform='sim',
- ):
- assert cpu in ["libresoc", "microwatt"]
- sys_clk_freq = int(50e6)
-
- if platform == 'sim':
- platform = Platform()
- uart_name = "sim"
- elif platform == 'ls180':
- platform = LS180Platform()
- uart_name = "uart"
-
- #cpu_data_width = 32
- cpu_data_width = 64
-
- variant = "ls180"
-
- # reserve XICS ICP and XICS memory addresses.
- self.mem_map['icp'] = 0xc0010000
- self.mem_map['ics'] = 0xc0011000
- #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
- #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
-
- ram_init = []
- if False:
- #ram_init = get_mem_data({
- # ram_fname: "0x00000000",
- # }, "little")
- ram_init = get_mem_data(ram_fname, "little")
-
- # remap the main RAM to reset-start-address
-
- # without sram nothing works, therefore move it to higher up
- self.mem_map["sram"] = 0x90000000
-
- # put UART at 0xc000200 (w00t! this works!)
- self.csr_map["uart"] = 4
-
- self.mem_map["main_ram"] = 0x90000000
- self.mem_map["sram"] = 0x00000000
- self.mem_map["sram1"] = 0x00000200
- self.mem_map["sram2"] = 0x00000400
- self.mem_map["sram3"] = 0x00000600
- self.mem_map["sram4"] = 0x00000800
- self.mem_map["sram4k_0"] = 0x00001000
- self.mem_map["sram4k_1"] = 0x00002000
- self.mem_map["sram4k_2"] = 0x00003000
- self.mem_map["sram4k_3"] = 0x00004000
-
- # SoCCore -------------------------------------------------------------
- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
- cpu_type = "microwatt",
- cpu_cls = LibreSoC if cpu == "libresoc" \
- else Microwatt,
- bus_data_width = 64,
- csr_address_width = 14, # limit to 0x8000
- cpu_variant = variant,
- csr_data_width = 8,
- l2_size = 0,
- with_uart = False,
- uart_name = None,
- with_sdram = with_sdram,
- sdram_module = sdram_module,
- sdram_data_width = sdram_data_width,
- integrated_rom_size = 0, # if ram_fname else 0x10000,
- #integrated_sram_size = 0x1000, - problem with yosys ABC
- integrated_sram_size = 0x200,
- #integrated_main_ram_init = ram_init,
- integrated_main_ram_size = 0x00000000 if with_sdram \
- else 0x10000000 , # 256MB
- )
- self.platform.name = "ls180"
-
- # add 4 more 4k integrated SRAMs
- self.add_ram("sram1", self.mem_map["sram1"], 0x200)
- self.add_ram("sram2", self.mem_map["sram2"], 0x200)
- self.add_ram("sram3", self.mem_map["sram3"], 0x200)
- self.add_ram("sram4", self.mem_map["sram4"], 0x200)
-
- # SDR SDRAM ----------------------------------------------
- if False: # not self.integrated_main_ram_size:
- self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
-
- if cpu == "libresoc":
- # XICS interrupt devices
- icp_addr = self.mem_map['icp']
- icp_wb = self.cpu.xics_icp
- icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
- self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
-
- ics_addr = self.mem_map['ics']
- ics_wb = self.cpu.xics_ics
- ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
- self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
-
- # add 4x 4k SRAMs
- for i, sram_wb in enumerate(self.cpu.srams):
- name = 'sram4k_%d' % i
- sram_adr = self.mem_map[name]
- ics_region = SoCRegion(origin=sram_adr, size=0x1000)
- self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
-
- # CRG -----------------------------------------------------------------
- self.submodules.crg = CRG(platform.request("sys_clk"),
- platform.request("sys_rst"))
-
- # PLL/Clock Select
- clksel_i = platform.request("sys_clksel_i")
- pll18_o = platform.request("sys_pll_18_o")
- pll_lck_o = platform.request("sys_pll_lck_o")
-
- self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
- self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
- self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
-
- #ram_init = []
-
- # SDRAM ----------------------------------------------------
- if with_sdram:
- sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
- sdram_module_cls = getattr(litedram_modules, sdram_module)
- sdram_rate = "1:{}".format(
- sdram_module_nphases[sdram_module_cls.memtype])
- sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
- phy_settings = get_sdram_phy_settings(
- memtype = sdram_module.memtype,
- data_width = sdram_data_width,
- clk_freq = sdram_clk_freq)
- #sdrphy_cls = HalfRateGENSDRPHY
- sdrphy_cls = GENSDRPHY
- sdram_pads = self.cpu.cpupads['sdr']
- self.submodules.sdrphy = sdrphy_cls(sdram_pads)
- #self.submodules.sdrphy = sdrphy_cls(sdram_module,
- # phy_settings,
- # init=ram_init
- # )
- self.add_sdram("sdram",
- phy = self.sdrphy,
- module = sdram_module,
- origin = self.mem_map["main_ram"],
- size = 0x80000000,
- l2_cache_size = 0, # 8192
- l2_cache_min_data_width = 128,
- l2_cache_reverse = True
- )
- # FIXME: skip memtest to avoid corrupting memory
- self.add_constant("MEMTEST_BUS_SIZE", 128//16)
- self.add_constant("MEMTEST_DATA_SIZE", 128//16)
- self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
- self.add_constant("MEMTEST_BUS_DEBUG", 1)
- self.add_constant("MEMTEST_ADDR_DEBUG", 1)
- self.add_constant("MEMTEST_DATA_DEBUG", 1)
-
- # SDRAM clock
- sys_clk = ClockSignal()
- sdr_clk = self.cpu.cpupads['sdram_clock']
- #self.specials += DDROutput(1, 0, , sdram_clk)
- self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
-
- # UART
- uart_core_pads = self.cpu.cpupads['uart']
- self.submodules.uart_phy = uart.UARTPHY(
- pads = uart_core_pads,
- clk_freq = self.sys_clk_freq,
- baudrate = 115200)
- self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
- tx_fifo_depth = 16,
- rx_fifo_depth = 16))
-
- self.csr.add("uart_phy", use_loc_if_exists=True)
- self.csr.add("uart", use_loc_if_exists=True)
- self.irq.add("uart", use_loc_if_exists=True)
-
- # GPIOs (bi-directional)
- gpio_core_pads = self.cpu.cpupads['gpio']
- self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
- self.add_csr("gpio")
-
- self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
- self.add_csr("gpio1")
-
- # SPI Master
- print ("cpupadkeys", self.cpu.cpupads.keys())
- self.submodules.spimaster = SPIMaster(
- pads = self.cpu.cpupads['mspi1'],
- data_width = 8,
- sys_clk_freq = sys_clk_freq,
- spi_clk_freq = 8e6,
- )
- self.add_csr("spimaster")
-
- # SPI SDCard (1 wide)
- spi_clk_freq = 400e3
- pads = self.cpu.cpupads['mspi0']
- spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
- spisdcard.add_clk_divider()
- setattr(self.submodules, 'spisdcard', spisdcard)
- self.add_csr('spisdcard')
-
- # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
- eintpads = self.cpu.cpupads['eint']
- print ("eintpads", eintpads)
- self.comb += self.cpu.interrupt[12:16].eq(eintpads)
-
- # JTAG
- jtagpads = platform.request("jtag")
- self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
- self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
- self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
- self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
-
- # NC - allows some iopads to be connected up
- # sigh, just do something, anything, to stop yosys optimising these out
- nc_pads = platform.request("nc")
- num_nc = len(nc_pads)
- self.nc = Signal(num_nc)
- self.comb += self.nc.eq(nc_pads)
- self.dummy = Signal(num_nc)
- for i in range(num_nc):
- self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0])
-
- # PWM
- pwmpads = self.cpu.cpupads['pwm']
- for i in range(2):
- name = "pwm%d" % i
- setattr(self.submodules, name, PWM(pwmpads[i]))
- self.add_csr(name)
-
- # I2C Master
- i2c_core_pads = self.cpu.cpupads['mtwi']
- self.submodules.i2c = I2CMaster(i2c_core_pads)
- self.add_csr("i2c")
-
- # SDCard -----------------------------------------------------
-
- # Emulator / Pads
- sdcard_pads = self.cpu.cpupads['sd0']
-
- # Core
- self.submodules.sdphy = SDPHY(sdcard_pads,
- self.platform.device, self.clk_freq)
- self.submodules.sdcore = SDCore(self.sdphy)
- self.add_csr("sdphy")
- self.add_csr("sdcore")
-
- # Block2Mem DMA
- bus = wishbone.Interface(data_width=self.bus.data_width,
- adr_width=self.bus.address_width)
- self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
- endianness=self.cpu.endianness)
- self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
- dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
- dma_bus.add_master("sdblock2mem", master=bus)
- self.add_csr("sdblock2mem")
-
- # Mem2Block DMA
- bus = wishbone.Interface(data_width=self.bus.data_width,
- adr_width=self.bus.address_width)
- self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
- endianness=self.cpu.endianness)
- self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
- dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
- dma_bus.add_master("sdmem2block", master=bus)
- self.add_csr("sdmem2block")
-
- # Debug ---------------------------------------------------------------
- if not debug:
- return
-
- jtag_en = ('jtag' in variant) or variant == 'ls180'
-
- # setup running of DMI FSM
- dmi_addr = Signal(4)
- dmi_din = Signal(64)
- dmi_dout = Signal(64)
- dmi_wen = Signal(1)
- dmi_req = Signal(1)
-
- # debug log out
- dbg_addr = Signal(4)
- dbg_dout = Signal(64)
- dbg_msg = Signal(1)
-
- # capture pc from dmi
- pc = Signal(64)
- active_dbg = Signal()
- active_dbg_cr = Signal()
- active_dbg_xer = Signal()
-
- # xer flags
- xer_so = Signal()
- xer_ca = Signal()
- xer_ca32 = Signal()
- xer_ov = Signal()
- xer_ov32 = Signal()
-
- # increment counter, Stop after 100000 cycles
- uptime = Signal(64)
- self.sync += uptime.eq(uptime + 1)
- #self.sync += If(uptime == 1000000000000, Finish())
-
- # DMI FSM counter and FSM itself
- dmicount = Signal(10)
- dmirunning = Signal(1)
- dmi_monitor = Signal(1)
- dmifsm = FSM()
- self.submodules += dmifsm
-
- # DMI FSM
- dmifsm.act("START",
- If(dmi_req & dmi_wen,
- (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
- self.cpu.dmi_din.eq(dmi_din), # DMI in
- self.cpu.dmi_req.eq(1), # DMI request
- self.cpu.dmi_wr.eq(1), # DMI write
- If(self.cpu.dmi_ack,
- (NextState("IDLE"),
- )
- ),
- ),
- ),
- If(dmi_req & ~dmi_wen,
- (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
- self.cpu.dmi_req.eq(1), # DMI request
- self.cpu.dmi_wr.eq(0), # DMI read
- If(self.cpu.dmi_ack,
- # acknowledge received: capture data.
- (NextState("IDLE"),
- NextValue(dbg_addr, dmi_addr),
- NextValue(dbg_dout, self.cpu.dmi_dout),
- NextValue(dbg_msg, 1),
- ),
- ),
- ),
- )
- )
-
- # DMI response received: reset the dmi request and check if
- # in "monitor" mode
- dmifsm.act("IDLE",
- If(dmi_monitor,
- NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
- ).Else(
- NextState("START"), # back to start on next cycle
- ),
- NextValue(dmi_req, 0),
- NextValue(dmi_addr, 0),
- NextValue(dmi_din, 0),
- NextValue(dmi_wen, 0),
- )
-
- # "monitor" mode fires off a STAT request
- dmifsm.act("FIRE_MONITOR",
- (NextValue(dmi_req, 1),
- NextValue(dmi_addr, 1), # DMI STAT address
- NextValue(dmi_din, 0),
- NextValue(dmi_wen, 0), # read STAT
- NextState("START"), # back to start on next cycle
- )
- )
-
- self.comb += xer_so.eq((dbg_dout & 1) == 1)
- self.comb += xer_ca.eq((dbg_dout & 4) == 4)
- self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
- self.comb += xer_ov.eq((dbg_dout & 16) == 16)
- self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
-
- # debug messages out
- self.sync += If(dbg_msg,
- (If(active_dbg & (dbg_addr == 0b10), # PC
- Display("pc : %016x", dbg_dout),
- ),
- If(dbg_addr == 0b10, # PC
- pc.eq(dbg_dout), # capture PC
- ),
- #If(dbg_addr == 0b11, # MSR
- # Display(" msr: %016x", dbg_dout),
- #),
- If(dbg_addr == 0b1000, # CR
- Display(" cr : %016x", dbg_dout),
- ),
- If(dbg_addr == 0b1001, # XER
- Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
- xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
- ),
- If(dbg_addr == 0b101, # GPR
- Display(" gpr: %016x", dbg_dout),
- ),
- # also check if this is a "stat"
- If(dbg_addr == 1, # requested a STAT
- #Display(" stat: %x", dbg_dout),
- If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
- dmirunning.eq(1), # continue running
- dmi_monitor.eq(0), # and stop monitor mode
- ),
- ),
- dbg_msg.eq(0)
- )
- )
-
- # kick off a "stop"
- self.sync += If(uptime == 0,
- (dmi_addr.eq(0), # CTRL
- dmi_din.eq(1<<0), # STOP
- dmi_req.eq(1),
- dmi_wen.eq(1),
- )
- )
-
- self.sync += If(uptime == 4,
- dmirunning.eq(1),
- )
-
- self.sync += If(dmirunning,
- dmicount.eq(dmicount + 1),
- )
-
- # loop every 1<<N cycles
- cyclewid = 9
-
- # get the PC
- self.sync += If(dmicount == 4,
- (dmi_addr.eq(0b10), # NIA
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # kick off a "step"
- self.sync += If(dmicount == 8,
- (dmi_addr.eq(0), # CTRL
- dmi_din.eq(1<<3), # STEP
- dmi_req.eq(1),
- dmi_wen.eq(1),
- dmirunning.eq(0), # stop counter, need to fire "monitor"
- dmi_monitor.eq(1), # start "monitor" instead
- )
- )
-
- # limit range of pc for debug reporting
- #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
- #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
- self.comb += active_dbg.eq(1)
-
-
- # get the MSR
- self.sync += If(active_dbg & (dmicount == 12),
- (dmi_addr.eq(0b11), # MSR
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- if cpu == "libresoc":
- #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
- self.comb += active_dbg_cr.eq(0)
-
- # get the CR
- self.sync += If(active_dbg_cr & (dmicount == 16),
- (dmi_addr.eq(0b1000), # CR
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
- self.comb += active_dbg_xer.eq(active_dbg_cr)
-
- # get the CR
- self.sync += If(active_dbg_xer & (dmicount == 20),
- (dmi_addr.eq(0b1001), # XER
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # read all 32 GPRs
- for i in range(32):
- self.sync += If(active_dbg & (dmicount == 24+(i*8)),
- (dmi_addr.eq(0b100), # GSPR addr
- dmi_din.eq(i), # r1
- dmi_req.eq(1),
- dmi_wen.eq(1),
- )
- )
-
- self.sync += If(active_dbg & (dmicount == 28+(i*8)),
- (dmi_addr.eq(0b101), # GSPR data
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # monitor bbus read/write
- self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
- Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
- #uptime,
- 0,
- self.cpu.dbus.adr,
- self.cpu.dbus.we,
- self.cpu.dbus.sel,
- self.cpu.dbus.dat_w,
- self.cpu.dbus.dat_r
- )
- )
-
- return
-
- # monitor ibus write
- self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
- self.cpu.ibus.we,
- Display(" [%06x] iadr: %8x, s %01x w %016x",
- #uptime,
- 0,
- self.cpu.ibus.adr,
- self.cpu.ibus.sel,
- self.cpu.ibus.dat_w,
- )
- )
- # monitor ibus read
- self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
- ~self.cpu.ibus.we,
- Display(" [%06x] iadr: %8x, s %01x r %016x",
- #uptime,
- 0,
- self.cpu.ibus.adr,
- self.cpu.ibus.sel,
- self.cpu.ibus.dat_r
- )
- )
-
-# Build -----------------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
- parser.add_argument("--cpu", default="libresoc",
- help="CPU to use: libresoc (default) or microwatt")
- parser.add_argument("--platform", default="sim",
- help="platform (sim or ls180)")
- parser.add_argument("--debug", action="store_true",
- help="Enable debug traces")
- parser.add_argument("--trace", action="store_true",
- help="Enable tracing")
- parser.add_argument("--trace-start", default=0,
- help="Cycle to start FST tracing")
- parser.add_argument("--trace-end", default=-1,
- help="Cycle to end FST tracing")
- parser.add_argument("--build", action="store_true", help="Build bitstream")
- args = parser.parse_args()
-
-
- if args.platform == 'ls180':
- soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
- platform=args.platform)
- builder = Builder(soc, compile_gateware = True)
- builder.build(run = True)
- os.chdir("../")
- else:
-
- sim_config = SimConfig(default_clk="sys_clk")
- sim_config.add_module("serial2console", "serial")
-
- for i in range(2):
- soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
- platform=args.platform)
- builder = Builder(soc, compile_gateware = i!=0)
- builder.build(sim_config=sim_config,
- run = i!=0,
- trace = args.trace,
- trace_start = int(args.trace_start),
- trace_end = int(args.trace_end),
- trace_fst = 0)
- os.chdir("../")
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-from microwatt.core import Microwatt
+++ /dev/null
-.section .text, "ax", @progbits
-.global boot_helper
-boot_helper:
- nop # FIXME
+++ /dev/null
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# This file is Copyright (c) 2019 Benjamin Herrenschmidt <benh@ozlabs.org>
-# License: BSD
-
-import os
-
-from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
-
-from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
-
-
-CPU_VARIANTS = ["standard"]
-
-
-class Microwatt(CPU):
- name = "microwatt"
- human_name = "Microwatt"
- variants = CPU_VARIANTS
- data_width = 64
- endianness = "little"
- gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
- linker_output_format = "elf64-powerpcle"
- nop = "nop"
- io_regions = {0xc0000000: 0x10000000} # origin, length
-
- @property
- def mem_map(self):
- return {"csr": 0xc0000000}
-
- @property
- def gcc_flags(self):
- flags = "-m64 "
- flags += "-mabi=elfv2 "
- flags += "-msoft-float "
- flags += "-mno-string "
- flags += "-mno-multiple "
- flags += "-mno-vsx "
- flags += "-mno-altivec "
- flags += "-mlittle-endian "
- flags += "-mstrict-align "
- flags += "-fno-stack-protector "
- flags += "-mcmodel=small "
- flags += "-D__microwatt__ "
- return flags
-
- def __init__(self, platform, variant="standard"):
- self.platform = platform
- self.variant = variant
- self.reset = Signal()
- self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
- self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
- self.periph_buses = [ibus, dbus]
- self.memory_buses = []
-
- self.dmi_addr = Signal(4)
- self.dmi_din = Signal(64)
- self.dmi_dout = Signal(64)
- self.dmi_wr = Signal(1)
- self.dmi_ack = Signal(1)
- self.dmi_req = Signal(1)
-
- # # #
-
- self.cpu_params = dict(
- # Clock / Reset
- i_clk = ClockSignal(),
- i_rst = ResetSignal() | self.reset,
-
- # Wishbone instruction bus
- i_wishbone_insn_dat_r = ibus.dat_r,
- i_wishbone_insn_ack = ibus.ack,
- i_wishbone_insn_stall = ibus.cyc & ~ibus.ack, # No burst support
-
- o_wishbone_insn_adr = Cat(Signal(3), ibus.adr),
- o_wishbone_insn_dat_w = ibus.dat_w,
- o_wishbone_insn_cyc = ibus.cyc,
- o_wishbone_insn_stb = ibus.stb,
- o_wishbone_insn_sel = ibus.sel,
- o_wishbone_insn_we = ibus.we,
-
- # Wishbone data bus
- i_wishbone_data_dat_r = dbus.dat_r,
- i_wishbone_data_ack = dbus.ack,
- i_wishbone_data_stall = dbus.cyc & ~dbus.ack, # No burst support
-
- o_wishbone_data_adr = Cat(Signal(3), dbus.adr),
- o_wishbone_data_dat_w = dbus.dat_w,
- o_wishbone_data_cyc = dbus.cyc,
- o_wishbone_data_stb = dbus.stb,
- o_wishbone_data_sel = dbus.sel,
- o_wishbone_data_we = dbus.we,
-
-
- # Debug bus
- i_dmi_addr = self.dmi_addr,
- i_dmi_din = self.dmi_din,
- o_dmi_dout = self.dmi_dout,
- i_dmi_req = self.dmi_req,
- i_dmi_wr = self.dmi_wr,
- o_dmi_ack = self.dmi_ack,
- )
-
- # add vhdl sources
- self.add_sources(platform)
-
- def set_reset_address(self, reset_address):
- assert not hasattr(self, "reset_address")
- self.reset_address = reset_address
- assert reset_address == 0x00000000
-
- @staticmethod
- def add_sources(platform):
- cdir = os.path.dirname(__file__)
- platform.add_source(os.path.join(cdir, "microwatt.v"))
-
- def do_finalize(self):
- self.specials += Instance("microwatt_wrapper", **self.cpu_params)
+++ /dev/null
-/* Copyright 2013-2014 IBM Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
- * implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define FIXUP_ENDIAN \
- tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
- b 191f; /* Skip trampoline if endian is good */ \
- .long 0xa600607d; /* mfmsr r11 */ \
- .long 0x01006b69; /* xori r11,r11,1 */ \
- .long 0x05009f42; /* bcl 20,31,$+4 */ \
- .long 0xa602487d; /* mflr r10 */ \
- .long 0x14004a39; /* addi r10,r10,20 */ \
- .long 0xa64b5a7d; /* mthsrr0 r10 */ \
- .long 0xa64b7b7d; /* mthsrr1 r11 */ \
- .long 0x2402004c; /* hrfid */ \
-191:
-
-
-/* Load an immediate 64-bit value into a register */
-#define LOAD_IMM64(r, e) \
- lis r,(e)@highest; \
- ori r,r,(e)@higher; \
- rldicr r,r, 32, 31; \
- oris r,r, (e)@h; \
- ori r,r, (e)@l;
-
- . = 0
-.global _start
-_start:
- FIXUP_ENDIAN
-
- /* setup stack */
- LOAD_IMM64(%r1, _fstack - 0x100)
- LOAD_IMM64(%r12, main)
- mtctr %r12,
- bctrl
- b .
-
-#define EXCEPTION(nr) \
- .= nr; \
- b .
-
- /* More exception stubs */
- EXCEPTION(0x100)
- EXCEPTION(0x200)
- EXCEPTION(0x300)
- EXCEPTION(0x380)
- EXCEPTION(0x400)
- EXCEPTION(0x480)
- EXCEPTION(0x500)
- EXCEPTION(0x600)
- EXCEPTION(0x700)
- EXCEPTION(0x800)
- EXCEPTION(0x900)
- EXCEPTION(0x980)
- EXCEPTION(0xa00)
- EXCEPTION(0xb00)
- EXCEPTION(0xc00)
- EXCEPTION(0xd00)
- EXCEPTION(0xe00)
- EXCEPTION(0xe20)
- EXCEPTION(0xe40)
- EXCEPTION(0xe60)
- EXCEPTION(0xe80)
- EXCEPTION(0xf00)
- EXCEPTION(0xf20)
- EXCEPTION(0xf40)
- EXCEPTION(0xf60)
- EXCEPTION(0xf80)
-#if 0
- EXCEPTION(0x1000)
- EXCEPTION(0x1100)
- EXCEPTION(0x1200)
- EXCEPTION(0x1300)
- EXCEPTION(0x1400)
- EXCEPTION(0x1500)
- EXCEPTION(0x1600)
-#endif
-
- .text
-
+++ /dev/null
-#ifndef __IRQ_H
-#define __IRQ_H
-
-static inline unsigned int irq_getie(void)
-{
- return 0;
-}
-
-static inline void irq_setie(unsigned int ie)
-{
- /*if(ie) csrs(); else csrc();*/
-}
-
-static inline unsigned int irq_getmask(void)
-{
- unsigned int mask = 0;
- //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
- return mask;
-}
-
-static inline void irq_setmask(unsigned int mask)
-{
- //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-}
-
-static inline unsigned int irq_pending(void)
-{
- unsigned int pending = 0;
- //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
- return pending;
-}
-
-#endif /* __IRQ_H */
+++ /dev/null
-/* Generated by Yosys 0.9+3558 (git sha1 c66d1dfa, clang 9.0.1-12 -fPIC -Os) */
-
-module cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
- wire [2047:0] _00_;
- wire [7:0] _01_;
- wire [2047:0] _02_;
- wire [7:0] _03_;
- wire [2047:0] _04_;
- wire [7:0] _05_;
- wire [2047:0] _06_;
- wire [7:0] _07_;
- wire [2047:0] _08_;
- wire [7:0] _09_;
- wire [2047:0] _10_;
- wire [7:0] _11_;
- wire [2047:0] _12_;
- wire [7:0] _13_;
- wire [2047:0] _14_;
- wire [7:0] _15_;
- input clk;
- input [7:0] rd_addr;
- output [63:0] rd_data;
- input rd_en;
- input [7:0] wr_addr;
- input [63:0] wr_data;
- input [7:0] wr_sel;
- reg [7:0] \$mem$\17901 [255:0];
- reg [7:0] \$mem$\17902 [255:0];
- reg [7:0] \$mem$\17903 [255:0];
- reg [7:0] \$mem$\17904 [255:0];
- reg [7:0] \$mem$\17905 [255:0];
- reg [7:0] \$mem$\17906 [255:0];
- reg [7:0] \$mem$\17907 [255:0];
- reg [7:0] \$mem$\17908 [255:0];
- (* ram_style = "block" *)
- reg [7:0] \17901 [255:0];
- reg [7:0] _16_;
- always @(posedge clk) begin
- if (rd_en) _16_ <= \17901 [rd_addr];
- if (wr_sel[0]) \17901 [wr_addr] <= wr_data[7:0];
- end
- assign _01_ = _16_;
- (* ram_style = "block" *)
- reg [7:0] \17902 [255:0];
- reg [7:0] _17_;
- always @(posedge clk) begin
- if (rd_en) _17_ <= \17902 [rd_addr];
- if (wr_sel[1]) \17902 [wr_addr] <= wr_data[15:8];
- end
- assign _03_ = _17_;
- (* ram_style = "block" *)
- reg [7:0] \17903 [255:0];
- reg [7:0] _18_;
- always @(posedge clk) begin
- if (rd_en) _18_ <= \17903 [rd_addr];
- if (wr_sel[2]) \17903 [wr_addr] <= wr_data[23:16];
- end
- assign _05_ = _18_;
- (* ram_style = "block" *)
- reg [7:0] \17904 [255:0];
- reg [7:0] _19_;
- always @(posedge clk) begin
- if (rd_en) _19_ <= \17904 [rd_addr];
- if (wr_sel[3]) \17904 [wr_addr] <= wr_data[31:24];
- end
- assign _07_ = _19_;
- (* ram_style = "block" *)
- reg [7:0] \17905 [255:0];
- reg [7:0] _20_;
- always @(posedge clk) begin
- if (rd_en) _20_ <= \17905 [rd_addr];
- if (wr_sel[4]) \17905 [wr_addr] <= wr_data[39:32];
- end
- assign _09_ = _20_;
- (* ram_style = "block" *)
- reg [7:0] \17906 [255:0];
- reg [7:0] _21_;
- always @(posedge clk) begin
- if (rd_en) _21_ <= \17906 [rd_addr];
- if (wr_sel[5]) \17906 [wr_addr] <= wr_data[47:40];
- end
- assign _11_ = _21_;
- (* ram_style = "block" *)
- reg [7:0] \17907 [255:0];
- reg [7:0] _22_;
- always @(posedge clk) begin
- if (rd_en) _22_ <= \17907 [rd_addr];
- if (wr_sel[6]) \17907 [wr_addr] <= wr_data[55:48];
- end
- assign _13_ = _22_;
- (* ram_style = "block" *)
- reg [7:0] \17908 [255:0];
- reg [7:0] _23_;
- always @(posedge clk) begin
- if (rd_en) _23_ <= \17908 [rd_addr];
- if (wr_sel[7]) \17908 [wr_addr] <= wr_data[63:56];
- end
- assign _15_ = _23_;
- assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
-endmodule
-
-module cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
- reg [63:0] _00_;
- wire [2047:0] _01_;
- wire [7:0] _02_;
- wire [2047:0] _03_;
- wire [7:0] _04_;
- wire [2047:0] _05_;
- wire [7:0] _06_;
- wire [2047:0] _07_;
- wire [7:0] _08_;
- wire [2047:0] _09_;
- wire [7:0] _10_;
- wire [2047:0] _11_;
- wire [7:0] _12_;
- wire [2047:0] _13_;
- wire [7:0] _14_;
- wire [2047:0] _15_;
- wire [7:0] _16_;
- input clk;
- input [7:0] rd_addr;
- output [63:0] rd_data;
- input rd_en;
- input [7:0] wr_addr;
- input [63:0] wr_data;
- input [7:0] wr_sel;
- reg [7:0] \$mem$\20460 [255:0];
- reg [7:0] \$mem$\20461 [255:0];
- reg [7:0] \$mem$\20462 [255:0];
- reg [7:0] \$mem$\20463 [255:0];
- reg [7:0] \$mem$\20464 [255:0];
- reg [7:0] \$mem$\20465 [255:0];
- reg [7:0] \$mem$\20466 [255:0];
- reg [7:0] \$mem$\20467 [255:0];
- always @(posedge clk)
- _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
- (* ram_style = "block" *)
- reg [7:0] \20460 [255:0];
- reg [7:0] _17_;
- always @(posedge clk) begin
- if (rd_en) _17_ <= \20460 [rd_addr];
- if (wr_sel[0]) \20460 [wr_addr] <= wr_data[7:0];
- end
- assign _02_ = _17_;
- (* ram_style = "block" *)
- reg [7:0] \20461 [255:0];
- reg [7:0] _18_;
- always @(posedge clk) begin
- if (rd_en) _18_ <= \20461 [rd_addr];
- if (wr_sel[1]) \20461 [wr_addr] <= wr_data[15:8];
- end
- assign _04_ = _18_;
- (* ram_style = "block" *)
- reg [7:0] \20462 [255:0];
- reg [7:0] _19_;
- always @(posedge clk) begin
- if (rd_en) _19_ <= \20462 [rd_addr];
- if (wr_sel[2]) \20462 [wr_addr] <= wr_data[23:16];
- end
- assign _06_ = _19_;
- (* ram_style = "block" *)
- reg [7:0] \20463 [255:0];
- reg [7:0] _20_;
- always @(posedge clk) begin
- if (rd_en) _20_ <= \20463 [rd_addr];
- if (wr_sel[3]) \20463 [wr_addr] <= wr_data[31:24];
- end
- assign _08_ = _20_;
- (* ram_style = "block" *)
- reg [7:0] \20464 [255:0];
- reg [7:0] _21_;
- always @(posedge clk) begin
- if (rd_en) _21_ <= \20464 [rd_addr];
- if (wr_sel[4]) \20464 [wr_addr] <= wr_data[39:32];
- end
- assign _10_ = _21_;
- (* ram_style = "block" *)
- reg [7:0] \20465 [255:0];
- reg [7:0] _22_;
- always @(posedge clk) begin
- if (rd_en) _22_ <= \20465 [rd_addr];
- if (wr_sel[5]) \20465 [wr_addr] <= wr_data[47:40];
- end
- assign _12_ = _22_;
- (* ram_style = "block" *)
- reg [7:0] \20466 [255:0];
- reg [7:0] _23_;
- always @(posedge clk) begin
- if (rd_en) _23_ <= \20466 [rd_addr];
- if (wr_sel[6]) \20466 [wr_addr] <= wr_data[55:48];
- end
- assign _14_ = _23_;
- (* ram_style = "block" *)
- reg [7:0] \20467 [255:0];
- reg [7:0] _24_;
- always @(posedge clk) begin
- if (rd_en) _24_ <= \20467 [rd_addr];
- if (wr_sel[7]) \20467 [wr_addr] <= wr_data[63:56];
- end
- assign _16_ = _24_;
- assign rd_data = _00_;
-endmodule
-
-module control_1(clk, rst, complete_in, valid_in, flush_in, stall_in, sgl_pipe_in, stop_mark_in, gpr_write_valid_in, gpr_write_in, gpr_bypassable, gpr_a_read_valid_in, gpr_a_read_in, gpr_b_read_valid_in, gpr_b_read_in, gpr_c_read_valid_in, gpr_c_read_in, cr_read_in, cr_write_in, valid_out, stall_out, stopped_out, gpr_bypass_a, gpr_bypass_b, gpr_bypass_c);
- wire _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- reg _08_ = 1'h1;
- wire _09_;
- wire _10_;
- wire _11_;
- wire _12_;
- wire [31:0] _13_;
- wire [2:0] _14_;
- wire [4:0] _15_;
- wire _16_;
- wire _17_;
- wire _18_;
- wire _19_;
- wire _20_;
- wire _21_;
- wire [1:0] _22_;
- wire _23_;
- wire _24_;
- wire _25_;
- wire _26_;
- wire [1:0] _27_;
- wire _28_;
- wire _29_;
- wire _30_;
- wire _31_;
- wire _32_;
- wire [1:0] _33_;
- wire _34_;
- wire _35_;
- wire _36_;
- wire _37_;
- wire [1:0] _38_;
- wire _39_;
- wire _40_;
- wire _41_;
- wire _42_;
- wire [1:0] _43_;
- wire _44_;
- wire _45_;
- wire _46_;
- wire [1:0] _47_;
- wire _48_;
- wire _49_;
- wire [1:0] _50_;
- wire _51_;
- wire _52_;
- wire [31:0] _53_;
- wire [2:0] _54_;
- input clk;
- input complete_in;
- input cr_read_in;
- wire cr_stall_out;
- input cr_write_in;
- wire cr_write_valid;
- input flush_in;
- input [5:0] gpr_a_read_in;
- input gpr_a_read_valid_in;
- input [5:0] gpr_b_read_in;
- input gpr_b_read_valid_in;
- output gpr_bypass_a;
- output gpr_bypass_b;
- output gpr_bypass_c;
- input gpr_bypassable;
- input [4:0] gpr_c_read_in;
- input gpr_c_read_valid_in;
- input [5:0] gpr_write_in;
- wire gpr_write_valid;
- input gpr_write_valid_in;
- reg [4:0] r_int = 5'h00;
- input rst;
- input sgl_pipe_in;
- wire stall_a_out;
- wire stall_b_out;
- wire stall_c_out;
- input stall_in;
- output stall_out;
- input stop_mark_in;
- output stopped_out;
- input valid_in;
- output valid_out;
- assign _03_ = $signed({ r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] }) >= $signed(32'd0);
- assign _04_ = $signed({ r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] }) <= $signed(32'd2);
- assign _05_ = _03_ & _04_;
- assign _06_ = ~ 1'h1;
- assign _07_ = _06_ | _05_;
- always @(posedge clk)
- _08_ <= _07_;
- always @(posedge clk)
- r_int <= { _54_, _50_ };
- assign _09_ = ~ flush_in;
- assign _10_ = valid_in & _09_;
- assign _11_ = ~ stall_in;
- assign _12_ = _10_ & _11_;
- assign _13_ = { r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] } - 32'd1;
- assign _14_ = complete_in ? _13_[2:0] : r_int[4:2];
- assign _15_ = rst ? 5'h00 : { _14_, r_int[1:0] };
- assign _16_ = rst ? 1'h0 : _12_;
- assign _17_ = rst ? 1'h0 : stall_in;
- assign _18_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
- assign _19_ = stop_mark_in & _18_;
- assign _20_ = _19_ ? 1'h1 : 1'h0;
- assign _21_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } != 32'd0;
- assign _22_ = _21_ ? 2'h1 : 2'h2;
- assign _23_ = _21_ ? 1'h1 : _17_;
- assign _24_ = stall_a_out | stall_b_out;
- assign _25_ = _24_ | stall_c_out;
- assign _26_ = _25_ | cr_stall_out;
- assign _27_ = _29_ ? _22_ : _15_[1:0];
- assign _28_ = sgl_pipe_in ? _23_ : _26_;
- assign _29_ = _16_ & sgl_pipe_in;
- assign _30_ = _16_ ? _28_ : _17_;
- assign _31_ = r_int[1:0] == 2'h0;
- assign _32_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
- assign _33_ = _32_ ? 2'h2 : _15_[1:0];
- assign _34_ = _32_ ? _17_ : 1'h1;
- assign _35_ = r_int[1:0] == 2'h1;
- assign _36_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
- assign _37_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } != 32'd0;
- assign _38_ = _37_ ? 2'h1 : 2'h2;
- assign _39_ = _37_ ? 1'h1 : _17_;
- assign _40_ = stall_a_out | stall_b_out;
- assign _41_ = _40_ | stall_c_out;
- assign _42_ = _41_ | cr_stall_out;
- assign _43_ = _45_ ? _38_ : 2'h0;
- assign _44_ = sgl_pipe_in ? _39_ : _42_;
- assign _45_ = _16_ & sgl_pipe_in;
- assign _46_ = _16_ ? _44_ : _17_;
- assign _47_ = _36_ ? _43_ : _15_[1:0];
- assign _48_ = _36_ ? _46_ : 1'h1;
- assign _49_ = r_int[1:0] == 2'h2;
- function [1:0] \18110 ;
- input [1:0] a;
- input [5:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \18110 = b[1:0];
- 3'b?1?:
- \18110 = b[3:2];
- 3'b1??:
- \18110 = b[5:4];
- default:
- \18110 = a;
- endcase
- endfunction
- assign _50_ = \18110 (2'hx, { _47_, _33_, _27_ }, { _49_, _35_, _31_ });
- function [0:0] \18113 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \18113 = b[0:0];
- 3'b?1?:
- \18113 = b[1:1];
- 3'b1??:
- \18113 = b[2:2];
- default:
- \18113 = a;
- endcase
- endfunction
- assign _51_ = \18113 (1'hx, { _48_, _34_, _30_ }, { _49_, _35_, _31_ });
- assign _52_ = _51_ ? 1'h0 : _16_;
- assign _53_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } + 32'd1;
- assign gpr_write_valid = _52_ ? gpr_write_valid_in : 1'h0;
- assign cr_write_valid = _52_ ? cr_write_in : 1'h0;
- assign _54_ = _52_ ? _53_[2:0] : _15_[4:2];
- cr_hazard_1 cr_hazard0 (
- .clk(clk),
- .cr_read_in(cr_read_in),
- .cr_write_in(cr_write_valid),
- .stall_in(stall_in),
- .stall_out(cr_stall_out)
- );
- gpr_hazard_1 gpr_hazard0 (
- .bypass_avail(gpr_bypassable),
- .clk(clk),
- .gpr_read_in(gpr_a_read_in),
- .gpr_read_valid_in(gpr_a_read_valid_in),
- .gpr_write_in(gpr_write_in),
- .gpr_write_valid_in(gpr_write_valid),
- .stall_in(stall_in),
- .stall_out(stall_a_out),
- .use_bypass(_00_)
- );
- gpr_hazard_1 gpr_hazard1 (
- .bypass_avail(gpr_bypassable),
- .clk(clk),
- .gpr_read_in(gpr_b_read_in),
- .gpr_read_valid_in(gpr_b_read_valid_in),
- .gpr_write_in(gpr_write_in),
- .gpr_write_valid_in(gpr_write_valid),
- .stall_in(stall_in),
- .stall_out(stall_b_out),
- .use_bypass(_01_)
- );
- gpr_hazard_1 gpr_hazard2 (
- .bypass_avail(gpr_bypassable),
- .clk(clk),
- .gpr_read_in({ 1'h0, gpr_c_read_in }),
- .gpr_read_valid_in(gpr_c_read_valid_in),
- .gpr_write_in(gpr_write_in),
- .gpr_write_valid_in(gpr_write_valid),
- .stall_in(stall_in),
- .stall_out(stall_c_out),
- .use_bypass(_02_)
- );
- assign valid_out = _52_;
- assign stall_out = _51_;
- assign stopped_out = _20_;
- assign gpr_bypass_a = _00_;
- assign gpr_bypass_b = _01_;
- assign gpr_bypass_c = _02_;
-endmodule
-
-module core_71ba14ecdd9e9507b1aeafd985ac12164cac4c4e(clk, rst, alt_reset, wishbone_insn_in, wishbone_data_in, dmi_addr, dmi_din, dmi_req, dmi_wr, ext_irq, wishbone_insn_out, wishbone_data_out, dmi_dout, dmi_ack, terminated_out);
- wire [106:0] _0_;
- wire _1_;
- wire [106:0] _2_;
- wire [63:0] _3_;
- wire _4_;
- wire _5_;
- input alt_reset;
- reg alt_reset_d;
- input clk;
- wire complete;
- wire core_rst;
- wire [36:0] cr_file_to_decode2;
- wire dbg_core_is_stopped;
- wire dbg_core_rst;
- wire dbg_core_stop;
- wire dbg_gpr_ack;
- wire [5:0] dbg_gpr_addr;
- wire [63:0] dbg_gpr_data;
- wire dbg_gpr_req;
- wire dbg_icache_rst;
- wire dcache_stall_out;
- wire [67:0] dcache_to_loadstore1;
- wire [66:0] dcache_to_mmu;
- wire [147:0] decode1_to_decode2;
- wire decode2_stall_in;
- wire decode2_stall_out;
- wire decode2_to_cr_file;
- wire [374:0] decode2_to_execute1;
- wire [19:0] decode2_to_register_file;
- output dmi_ack;
- input [3:0] dmi_addr;
- input [63:0] dmi_din;
- output [63:0] dmi_dout;
- input dmi_req;
- input dmi_wr;
- wire ex1_icache_inval;
- wire ex1_stall_out;
- wire [66:0] execute1_to_fetch1;
- wire [321:0] execute1_to_loadstore1;
- wire [190:0] execute1_to_writeback;
- input ext_irq;
- wire fetch1_stall_in;
- wire [67:0] fetch1_to_icache;
- wire [98:0] fetch2_to_decode1;
- wire flush;
- wire icache_stall_out;
- wire [98:0] icache_to_fetch2;
- wire [142:0] loadstore1_to_dcache;
- wire [6:0] loadstore1_to_execute1;
- wire [144:0] loadstore1_to_mmu;
- wire [77:0] loadstore1_to_writeback;
- wire ls1_stall_out;
- wire [131:0] mmu_to_dcache;
- wire [130:0] mmu_to_icache;
- wire [69:0] mmu_to_loadstore1;
- wire [63:0] msr;
- wire [191:0] register_file_to_decode2;
- input rst;
- reg rst_dbg = 1'h1;
- reg rst_dcache = 1'h1;
- reg rst_dec1 = 1'h1;
- reg rst_dec2 = 1'h1;
- reg rst_ex1 = 1'h1;
- reg rst_fetch1 = 1'h1;
- reg rst_fetch2 = 1'h1;
- reg rst_icache = 1'h1;
- reg rst_ls1 = 1'h1;
- wire sim_cr_dump;
- wire terminate;
- output terminated_out;
- input [65:0] wishbone_data_in;
- output [106:0] wishbone_data_out;
- input [65:0] wishbone_insn_in;
- output [106:0] wishbone_insn_out;
- wire [46:0] writeback_to_cr_file;
- wire [70:0] writeback_to_register_file;
- assign decode2_stall_in = ex1_stall_out | ls1_stall_out;
- assign core_rst = dbg_core_rst | rst;
- always @(posedge clk)
- rst_fetch1 <= core_rst;
- always @(posedge clk)
- rst_fetch2 <= core_rst;
- always @(posedge clk)
- rst_icache <= core_rst;
- always @(posedge clk)
- rst_dcache <= core_rst;
- always @(posedge clk)
- rst_dec1 <= core_rst;
- always @(posedge clk)
- rst_dec2 <= core_rst;
- always @(posedge clk)
- rst_ex1 <= core_rst;
- always @(posedge clk)
- rst_ls1 <= core_rst;
- always @(posedge clk)
- rst_dbg <= rst;
- always @(posedge clk)
- alt_reset_d <= alt_reset;
- assign fetch1_stall_in = icache_stall_out | decode2_stall_out;
- assign _1_ = dbg_icache_rst | ex1_icache_inval;
- cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f cr_file_0 (
- .clk(clk),
- .d_in(decode2_to_cr_file),
- .d_out(cr_file_to_decode2),
- .sim_dump(sim_cr_dump),
- .w_in(writeback_to_cr_file)
- );
- dcache_64_32_2_64_2_12 dcache_0 (
- .clk(clk),
- .d_in(loadstore1_to_dcache),
- .d_out(dcache_to_loadstore1),
- .m_in(mmu_to_dcache),
- .m_out(dcache_to_mmu),
- .rst(rst_dcache),
- .stall_out(dcache_stall_out),
- .wishbone_in(wishbone_data_in),
- .wishbone_out(_2_)
- );
- core_debug debug_0 (
- .clk(clk),
- .core_rst(dbg_core_rst),
- .core_stop(dbg_core_stop),
- .core_stopped(dbg_core_is_stopped),
- .dbg_gpr_ack(dbg_gpr_ack),
- .dbg_gpr_addr(dbg_gpr_addr),
- .dbg_gpr_data(dbg_gpr_data),
- .dbg_gpr_req(dbg_gpr_req),
- .dmi_ack(_4_),
- .dmi_addr(dmi_addr),
- .dmi_din(dmi_din),
- .dmi_dout(_3_),
- .dmi_req(dmi_req),
- .dmi_wr(dmi_wr),
- .icache_rst(dbg_icache_rst),
- .msr(msr),
- .nia(fetch1_to_icache[67:4]),
- .rst(rst_dbg),
- .terminate(terminate),
- .terminated_out(_5_)
- );
- decode1 decode1_0 (
- .clk(clk),
- .d_out(decode1_to_decode2),
- .f_in(fetch2_to_decode1),
- .flush_in(flush),
- .rst(rst_dec1),
- .stall_in(decode2_stall_out)
- );
- decode2_bf8b4530d8d246dd74ac53a13471bba17941dff7 decode2_0 (
- .c_in(cr_file_to_decode2),
- .c_out(decode2_to_cr_file),
- .clk(clk),
- .complete_in(complete),
- .d_in(decode1_to_decode2),
- .e_out(decode2_to_execute1),
- .flush_in(flush),
- .r_in(register_file_to_decode2),
- .r_out(decode2_to_register_file),
- .rst(rst_dec2),
- .stall_in(decode2_stall_in),
- .stall_out(decode2_stall_out),
- .stopped_out(dbg_core_is_stopped)
- );
- execute1_bf8b4530d8d246dd74ac53a13471bba17941dff7 execute1_0 (
- .clk(clk),
- .dbg_msr_out(msr),
- .e_in(decode2_to_execute1),
- .e_out(execute1_to_writeback),
- .ext_irq_in(ext_irq),
- .f_out(execute1_to_fetch1),
- .flush_out(flush),
- .icache_inval(ex1_icache_inval),
- .l_in(loadstore1_to_execute1),
- .l_out(execute1_to_loadstore1),
- .rst(rst_ex1),
- .stall_out(ex1_stall_out),
- .terminate_out(terminate)
- );
- fetch1_3f28fda38b1ec2f6fdb16c0bce5a53c28d1424e5 fetch1_0 (
- .alt_reset_in(alt_reset_d),
- .clk(clk),
- .e_in(execute1_to_fetch1),
- .flush_in(flush),
- .i_out(fetch1_to_icache),
- .rst(rst_fetch1),
- .stall_in(fetch1_stall_in),
- .stop_in(dbg_core_stop)
- );
- fetch2 fetch2_0 (
- .clk(clk),
- .f_out(fetch2_to_decode1),
- .flush_in(flush),
- .i_in(icache_to_fetch2),
- .rst(rst_fetch2),
- .stall_in(decode2_stall_out)
- );
- icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f icache_0 (
- .clk(clk),
- .flush_in(flush),
- .i_in(fetch1_to_icache),
- .i_out(icache_to_fetch2),
- .inval_in(_1_),
- .m_in(mmu_to_icache),
- .rst(rst_icache),
- .stall_out(icache_stall_out),
- .wishbone_in(wishbone_insn_in),
- .wishbone_out(_0_)
- );
- loadstore1 loadstore1_0 (
- .clk(clk),
- .d_in(dcache_to_loadstore1),
- .d_out(loadstore1_to_dcache),
- .dc_stall(dcache_stall_out),
- .e_out(loadstore1_to_execute1),
- .l_in(execute1_to_loadstore1),
- .l_out(loadstore1_to_writeback),
- .m_in(mmu_to_loadstore1),
- .m_out(loadstore1_to_mmu),
- .rst(rst_ls1),
- .stall_out(ls1_stall_out)
- );
- mmu mmu_0 (
- .clk(clk),
- .d_in(dcache_to_mmu),
- .d_out(mmu_to_dcache),
- .i_out(mmu_to_icache),
- .l_in(loadstore1_to_mmu),
- .l_out(mmu_to_loadstore1),
- .rst(core_rst)
- );
- register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0 (
- .clk(clk),
- .d_in(decode2_to_register_file),
- .d_out(register_file_to_decode2),
- .dbg_gpr_ack(dbg_gpr_ack),
- .dbg_gpr_addr(dbg_gpr_addr),
- .dbg_gpr_data(dbg_gpr_data),
- .dbg_gpr_req(dbg_gpr_req),
- .sim_dump(terminate),
- .sim_dump_done(sim_cr_dump),
- .w_in(writeback_to_register_file)
- );
- writeback writeback_0 (
- .c_out(writeback_to_cr_file),
- .clk(clk),
- .complete_out(complete),
- .e_in(execute1_to_writeback),
- .l_in(loadstore1_to_writeback),
- .w_out(writeback_to_register_file)
- );
- assign wishbone_insn_out = _0_;
- assign wishbone_data_out = _2_;
- assign dmi_dout = _3_;
- assign dmi_ack = _4_;
- assign terminated_out = _5_;
-endmodule
-
-module core_debug(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_stopped, nia, msr, dbg_gpr_ack, dbg_gpr_data, dmi_dout, dmi_ack, core_stop, core_rst, icache_rst, dbg_gpr_req, dbg_gpr_addr, terminated_out);
- wire _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- wire [63:0] _08_;
- wire _09_;
- wire _10_;
- wire _11_;
- wire _12_;
- wire _13_;
- wire _14_;
- wire _15_;
- wire _16_;
- wire _17_;
- wire _18_;
- wire _19_;
- wire _20_;
- wire [5:0] _21_;
- wire _22_;
- wire _23_;
- wire _24_;
- wire _25_;
- wire _26_;
- wire [5:0] _27_;
- wire _28_;
- wire _29_;
- wire _30_;
- wire _31_;
- wire _32_;
- wire [5:0] _33_;
- wire _34_;
- wire _35_;
- wire _36_;
- wire _37_;
- wire _38_;
- wire _39_;
- wire _40_;
- wire _41_;
- wire _42_;
- wire _43_;
- wire _44_;
- wire _45_;
- wire _46_;
- wire _47_;
- wire [5:0] _48_;
- wire _49_;
- wire _50_;
- input clk;
- output core_rst;
- output core_stop;
- input core_stopped;
- input dbg_gpr_ack;
- output [5:0] dbg_gpr_addr;
- input [63:0] dbg_gpr_data;
- output dbg_gpr_req;
- output dmi_ack;
- input [3:0] dmi_addr;
- input [63:0] dmi_din;
- output [63:0] dmi_dout;
- input dmi_req;
- reg dmi_req_1;
- input dmi_wr;
- reg do_icreset;
- reg do_reset;
- reg do_step;
- reg [5:0] gspr_index;
- output icache_rst;
- input [63:0] msr;
- input [63:0] nia;
- input rst;
- reg stopping;
- input terminate;
- reg terminated;
- output terminated_out;
- assign _00_ = dmi_addr != 4'h5;
- assign _01_ = _00_ ? dmi_req : dbg_gpr_ack;
- assign _02_ = dmi_addr == 4'h5;
- assign _03_ = _02_ ? dmi_req : 1'h0;
- assign _04_ = dmi_addr == 4'h1;
- assign _05_ = dmi_addr == 4'h2;
- assign _06_ = dmi_addr == 4'h3;
- assign _07_ = dmi_addr == 4'h5;
- function [63:0] \17699 ;
- input [63:0] a;
- input [255:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \17699 = b[63:0];
- 4'b??1?:
- \17699 = b[127:64];
- 4'b?1??:
- \17699 = b[191:128];
- 4'b1???:
- \17699 = b[255:192];
- default:
- \17699 = a;
- endcase
- endfunction
- assign _08_ = \17699 (64'h0000000000000000, { dbg_gpr_data, msr, nia, 61'h0000000000000000, terminated, core_stopped, stopping }, { _07_, _06_, _05_, _04_ });
- assign _09_ = ~ dmi_req_1;
- assign _10_ = dmi_req & _09_;
- assign _11_ = dmi_addr == 4'h0;
- assign _12_ = dmi_din[1] ? 1'h1 : 1'h0;
- assign _13_ = dmi_din[1] ? 1'h0 : terminated;
- assign _14_ = dmi_din[0] ? 1'h1 : stopping;
- assign _15_ = dmi_din[3] ? 1'h1 : 1'h0;
- assign _16_ = dmi_din[3] ? 1'h0 : _13_;
- assign _17_ = dmi_din[2] ? 1'h1 : 1'h0;
- assign _18_ = dmi_din[4] ? 1'h0 : _14_;
- assign _19_ = dmi_din[4] ? 1'h0 : _16_;
- assign _20_ = dmi_addr == 4'h4;
- assign _21_ = _20_ ? dmi_din[5:0] : gspr_index;
- assign _22_ = _34_ ? _18_ : stopping;
- assign _23_ = _11_ ? _15_ : 1'h0;
- assign _24_ = _11_ ? _12_ : 1'h0;
- assign _25_ = _11_ ? _17_ : 1'h0;
- assign _26_ = _38_ ? _19_ : terminated;
- assign _27_ = _11_ ? gspr_index : _21_;
- assign _28_ = dmi_wr & _11_;
- assign _29_ = dmi_wr ? _23_ : 1'h0;
- assign _30_ = dmi_wr ? _24_ : 1'h0;
- assign _31_ = dmi_wr ? _25_ : 1'h0;
- assign _32_ = dmi_wr & _11_;
- assign _33_ = _39_ ? _27_ : gspr_index;
- assign _34_ = _10_ & _28_;
- assign _35_ = _10_ ? _29_ : 1'h0;
- assign _36_ = _10_ ? _30_ : 1'h0;
- assign _37_ = _10_ ? _31_ : 1'h0;
- assign _38_ = _10_ & _32_;
- assign _39_ = _10_ & dmi_wr;
- assign _40_ = terminate ? 1'h1 : _22_;
- assign _41_ = terminate ? 1'h1 : _26_;
- assign _42_ = rst ? dmi_req_1 : dmi_req;
- assign _43_ = rst ? 1'h0 : _40_;
- assign _44_ = rst ? 1'h0 : _35_;
- assign _45_ = rst ? 1'h0 : _36_;
- assign _46_ = rst ? 1'h0 : _37_;
- assign _47_ = rst ? 1'h0 : _41_;
- assign _48_ = rst ? gspr_index : _33_;
- always @(posedge clk)
- dmi_req_1 <= _42_;
- always @(posedge clk)
- stopping <= _43_;
- always @(posedge clk)
- do_step <= _44_;
- always @(posedge clk)
- do_reset <= _45_;
- always @(posedge clk)
- do_icreset <= _46_;
- always @(posedge clk)
- terminated <= _47_;
- always @(posedge clk)
- gspr_index <= _48_;
- assign _49_ = ~ do_step;
- assign _50_ = stopping & _49_;
- assign dmi_dout = _08_;
- assign dmi_ack = _01_;
- assign core_stop = _50_;
- assign core_rst = do_reset;
- assign icache_rst = do_icreset;
- assign dbg_gpr_req = _03_;
- assign dbg_gpr_addr = gspr_index;
- assign terminated_out = terminated;
-endmodule
-
-module cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, sim_dump, d_out);
- wire [3:0] _0_;
- wire [3:0] _1_;
- wire [3:0] _2_;
- wire [3:0] _3_;
- wire [3:0] _4_;
- wire [3:0] _5_;
- wire [3:0] _6_;
- wire [3:0] _7_;
- wire [31:0] _8_;
- wire [4:0] _9_;
- input clk;
- reg [31:0] crs = 32'd0;
- input d_in;
- output [36:0] d_out;
- input sim_dump;
- input [46:0] w_in;
- reg [4:0] xerc = 5'h00;
- wire [4:0] xerc_updated;
- assign _0_ = w_in[1] ? w_in[12:9] : crs[3:0];
- assign _1_ = w_in[2] ? w_in[16:13] : crs[7:4];
- assign _2_ = w_in[3] ? w_in[20:17] : crs[11:8];
- assign _3_ = w_in[4] ? w_in[24:21] : crs[15:12];
- assign _4_ = w_in[5] ? w_in[28:25] : crs[19:16];
- assign _5_ = w_in[6] ? w_in[32:29] : crs[23:20];
- assign _6_ = w_in[7] ? w_in[36:33] : crs[27:24];
- assign _7_ = w_in[8] ? w_in[40:37] : crs[31:28];
- assign xerc_updated = w_in[41] ? w_in[46:42] : xerc;
- assign _8_ = w_in[0] ? { _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ } : crs;
- always @(posedge clk)
- crs <= _8_;
- assign _9_ = w_in[41] ? xerc_updated : xerc;
- always @(posedge clk)
- xerc <= _9_;
- assign d_out = { xerc_updated, _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
-endmodule
-
-module cr_hazard_1(clk, stall_in, cr_read_in, cr_write_in, stall_out);
- wire _0_;
- wire _1_;
- wire _2_;
- wire _3_;
- wire _4_;
- wire _5_;
- input clk;
- input cr_read_in;
- input cr_write_in;
- reg r = 1'h0;
- input stall_in;
- output stall_out;
- assign _0_ = ~ stall_in;
- assign _1_ = _0_ ? cr_write_in : r;
- always @(posedge clk)
- r <= _1_;
- assign _2_ = r == cr_read_in;
- assign _3_ = _2_ ? 1'h1 : 1'h0;
- assign _4_ = ~ cr_read_in;
- assign _5_ = _4_ ? 1'h0 : _3_;
- assign stall_out = _5_;
-endmodule
-
-module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
- wire _0000_;
- wire _0001_;
- wire _0002_;
- wire _0003_;
- wire _0004_;
- wire _0005_;
- wire _0006_;
- wire [146:0] _0007_;
- wire [146:0] _0008_;
- wire _0009_;
- wire _0010_;
- wire [145:0] _0011_;
- wire _0012_;
- reg _0013_ = 1'h1;
- wire _0014_;
- wire _0015_;
- wire _0016_;
- wire [5:0] _0017_;
- wire [5:0] _0018_;
- wire [5:0] _0019_;
- wire _0020_;
- wire _0021_;
- wire _0022_;
- wire _0023_;
- wire _0024_;
- wire _0025_;
- wire _0026_;
- wire _0027_;
- wire _0028_;
- wire _0029_;
- wire _0030_;
- wire _0031_;
- wire _0032_;
- wire _0033_;
- wire _0034_;
- wire _0035_;
- wire _0036_;
- wire _0037_;
- wire _0038_;
- wire _0039_;
- wire _0040_;
- wire _0041_;
- wire _0042_;
- wire _0043_;
- wire _0044_;
- wire _0045_;
- wire _0046_;
- wire _0047_;
- wire _0048_;
- wire _0049_;
- wire _0050_;
- wire _0051_;
- wire _0052_;
- wire _0053_;
- wire _0054_;
- wire _0055_;
- wire _0056_;
- wire _0057_;
- wire _0058_;
- wire _0059_;
- wire _0060_;
- wire _0061_;
- wire _0062_;
- wire _0063_;
- wire _0064_;
- wire _0065_;
- wire _0066_;
- wire _0067_;
- wire _0068_;
- wire _0069_;
- wire _0070_;
- wire _0071_;
- wire _0072_;
- wire _0073_;
- wire _0074_;
- wire _0075_;
- wire _0076_;
- wire _0077_;
- wire _0078_;
- wire _0079_;
- wire _0080_;
- wire _0081_;
- wire _0082_;
- wire _0083_;
- wire _0084_;
- wire _0085_;
- wire _0086_;
- wire _0087_;
- wire _0088_;
- wire _0089_;
- wire _0090_;
- wire _0091_;
- wire _0092_;
- wire _0093_;
- wire _0094_;
- wire _0095_;
- wire _0096_;
- wire _0097_;
- wire _0098_;
- wire _0099_;
- wire _0100_;
- wire _0101_;
- wire _0102_;
- wire _0103_;
- wire _0104_;
- wire _0105_;
- wire _0106_;
- wire _0107_;
- wire _0108_;
- wire _0109_;
- wire _0110_;
- wire _0111_;
- wire _0112_;
- wire _0113_;
- wire _0114_;
- wire _0115_;
- wire _0116_;
- wire _0117_;
- wire _0118_;
- wire _0119_;
- wire _0120_;
- wire _0121_;
- wire _0122_;
- wire _0123_;
- wire _0124_;
- wire _0125_;
- wire _0126_;
- wire _0127_;
- wire _0128_;
- wire _0129_;
- wire _0130_;
- wire _0131_;
- wire _0132_;
- wire _0133_;
- wire _0134_;
- wire _0135_;
- wire _0136_;
- wire _0137_;
- wire _0138_;
- wire _0139_;
- wire _0140_;
- wire _0141_;
- wire _0142_;
- wire _0143_;
- wire _0144_;
- wire _0145_;
- wire _0146_;
- wire _0147_;
- wire _0148_;
- wire _0149_;
- wire _0150_;
- wire _0151_;
- wire _0152_;
- wire _0153_;
- wire _0154_;
- wire _0155_;
- wire _0156_;
- wire _0157_;
- wire _0158_;
- wire [5:0] _0159_;
- wire [127:0] _0160_;
- wire [5:0] _0161_;
- wire _0162_;
- wire [5:0] _0163_;
- wire [127:0] _0164_;
- wire [127:0] _0165_;
- wire [127:0] _0166_;
- wire _0167_;
- wire _0168_;
- wire _0169_;
- wire _0170_;
- wire _0171_;
- wire _0172_;
- wire _0173_;
- wire _0174_;
- wire _0175_;
- wire _0176_;
- wire _0177_;
- wire _0178_;
- wire _0179_;
- wire _0180_;
- wire _0181_;
- wire _0182_;
- wire _0183_;
- wire _0184_;
- wire _0185_;
- wire _0186_;
- wire _0187_;
- wire _0188_;
- wire _0189_;
- wire _0190_;
- wire _0191_;
- wire _0192_;
- wire _0193_;
- wire _0194_;
- wire _0195_;
- wire _0196_;
- wire _0197_;
- wire _0198_;
- wire _0199_;
- wire _0200_;
- wire _0201_;
- wire _0202_;
- wire _0203_;
- wire _0204_;
- wire _0205_;
- wire _0206_;
- wire _0207_;
- wire _0208_;
- wire _0209_;
- wire _0210_;
- wire _0211_;
- wire _0212_;
- wire _0213_;
- wire _0214_;
- wire _0215_;
- wire _0216_;
- wire _0217_;
- wire _0218_;
- wire _0219_;
- wire _0220_;
- wire _0221_;
- wire _0222_;
- wire _0223_;
- wire _0224_;
- wire _0225_;
- wire _0226_;
- wire _0227_;
- wire _0228_;
- wire _0229_;
- wire _0230_;
- wire _0231_;
- wire _0232_;
- wire _0233_;
- wire _0234_;
- wire _0235_;
- wire _0236_;
- wire _0237_;
- wire _0238_;
- wire _0239_;
- wire _0240_;
- wire _0241_;
- wire _0242_;
- wire _0243_;
- wire _0244_;
- wire _0245_;
- wire _0246_;
- wire _0247_;
- wire _0248_;
- wire _0249_;
- wire _0250_;
- wire _0251_;
- wire _0252_;
- wire _0253_;
- wire _0254_;
- wire _0255_;
- wire _0256_;
- wire _0257_;
- wire _0258_;
- wire _0259_;
- wire _0260_;
- wire _0261_;
- wire _0262_;
- wire _0263_;
- wire _0264_;
- wire _0265_;
- wire _0266_;
- wire _0267_;
- wire _0268_;
- wire _0269_;
- wire _0270_;
- wire _0271_;
- wire _0272_;
- wire _0273_;
- wire _0274_;
- wire _0275_;
- wire _0276_;
- wire _0277_;
- wire _0278_;
- wire _0279_;
- wire _0280_;
- wire _0281_;
- wire _0282_;
- wire _0283_;
- wire _0284_;
- wire _0285_;
- wire _0286_;
- wire _0287_;
- wire _0288_;
- wire _0289_;
- wire _0290_;
- wire _0291_;
- wire _0292_;
- wire _0293_;
- wire _0294_;
- wire _0295_;
- wire _0296_;
- wire _0297_;
- wire _0298_;
- wire _0299_;
- wire _0300_;
- wire _0301_;
- wire _0302_;
- wire _0303_;
- wire _0304_;
- wire _0305_;
- wire _0306_;
- wire _0307_;
- wire _0308_;
- wire _0309_;
- wire _0310_;
- wire _0311_;
- wire _0312_;
- wire _0313_;
- wire _0314_;
- wire _0315_;
- wire _0316_;
- wire _0317_;
- wire _0318_;
- wire _0319_;
- wire _0320_;
- wire _0321_;
- wire _0322_;
- wire _0323_;
- wire _0324_;
- wire _0325_;
- wire _0326_;
- wire _0327_;
- wire _0328_;
- wire _0329_;
- wire _0330_;
- wire _0331_;
- wire _0332_;
- wire _0333_;
- wire _0334_;
- wire _0335_;
- wire _0336_;
- wire _0337_;
- wire [4:0] _0338_;
- wire _0339_;
- wire [4:0] _0340_;
- wire _0341_;
- wire _0342_;
- wire _0343_;
- wire _0344_;
- wire _0345_;
- wire [4:0] _0346_;
- wire _0347_;
- wire [4:0] _0348_;
- wire _0349_;
- wire _0350_;
- wire _0351_;
- wire _0352_;
- wire _0353_;
- wire [4:0] _0354_;
- wire _0355_;
- wire [4:0] _0356_;
- wire _0357_;
- wire _0358_;
- wire _0359_;
- wire _0360_;
- wire _0361_;
- wire [4:0] _0362_;
- wire _0363_;
- wire [4:0] _0364_;
- wire _0365_;
- wire _0366_;
- wire _0367_;
- wire _0368_;
- wire _0369_;
- wire _0370_;
- wire _0371_;
- wire _0372_;
- wire [4:0] _0373_;
- wire _0374_;
- wire [4:0] _0375_;
- wire _0376_;
- wire _0377_;
- wire _0378_;
- wire [4:0] _0379_;
- wire _0380_;
- wire [4:0] _0381_;
- wire _0382_;
- wire _0383_;
- wire _0384_;
- wire _0385_;
- wire _0386_;
- wire [4:0] _0387_;
- wire _0388_;
- wire _0389_;
- wire _0390_;
- wire _0391_;
- wire _0392_;
- wire _0393_;
- wire _0394_;
- wire _0395_;
- wire _0396_;
- wire _0397_;
- wire _0398_;
- wire _0399_;
- wire _0400_;
- wire _0401_;
- wire _0402_;
- wire _0403_;
- wire [2:0] _0404_;
- wire [2:0] _0405_;
- wire _0406_;
- wire [7:0] _0407_;
- wire _0408_;
- wire _0409_;
- wire _0410_;
- wire _0411_;
- wire _0412_;
- wire _0413_;
- wire _0414_;
- wire _0415_;
- wire _0416_;
- wire _0417_;
- wire _0418_;
- wire [58:0] _0419_;
- wire _0420_;
- wire [57:0] _0421_;
- wire _0422_;
- wire _0423_;
- wire _0424_;
- wire _0425_;
- wire _0426_;
- wire _0427_;
- wire _0428_;
- wire _0429_;
- wire _0430_;
- wire _0431_;
- wire [1:0] _0432_;
- wire [63:0] _0433_;
- wire [65:0] _0434_;
- wire _0435_;
- wire _0436_;
- wire _0437_;
- wire [1:0] _0438_;
- wire _0439_;
- wire [63:0] _0440_;
- wire [67:0] _0441_;
- wire [65:0] _0442_;
- wire _0443_;
- wire [63:0] _0444_;
- wire _0445_;
- wire _0446_;
- wire _0447_;
- wire _0448_;
- wire _0449_;
- wire _0450_;
- wire _0451_;
- wire _0452_;
- wire _0453_;
- wire _0454_;
- wire _0455_;
- wire _0456_;
- wire _0457_;
- wire _0458_;
- wire _0459_;
- wire _0460_;
- wire _0461_;
- wire _0462_;
- wire _0463_;
- wire _0464_;
- wire _0465_;
- wire _0466_;
- wire _0467_;
- wire _0468_;
- wire _0469_;
- wire [63:0] _0470_;
- wire _0471_;
- wire _0472_;
- wire _0473_;
- wire _0474_;
- wire _0475_;
- wire _0476_;
- wire _0477_;
- wire _0478_;
- wire _0479_;
- wire _0480_;
- wire _0481_;
- wire _0482_;
- wire _0483_;
- wire _0484_;
- wire _0485_;
- wire _0486_;
- wire _0487_;
- wire _0488_;
- wire _0489_;
- wire _0490_;
- wire _0491_;
- wire _0492_;
- wire _0493_;
- wire _0494_;
- wire _0495_;
- wire _0496_;
- wire _0497_;
- wire [143:0] _0498_;
- wire _0499_;
- wire _0500_;
- wire _0501_;
- wire _0502_;
- wire _0503_;
- wire [1:0] _0504_;
- wire [1:0] _0505_;
- wire _0506_;
- wire _0507_;
- reg [145:0] _0508_;
- reg [2:0] _0509_;
- wire _0510_;
- wire [4:0] _0511_;
- wire _0512_;
- wire [4:0] _0513_;
- wire [4:0] _0514_;
- wire [2879:0] _0515_;
- wire _0516_;
- wire [4:0] _0517_;
- wire [4:0] _0518_;
- wire [2879:0] _0519_;
- wire _0520_;
- wire _0521_;
- wire _0522_;
- wire _0523_;
- wire _0524_;
- wire [2:0] _0525_;
- wire [1:0] _0526_;
- wire _0527_;
- wire _0528_;
- wire [4:0] _0529_;
- wire _0530_;
- wire [4:0] _0531_;
- wire [4:0] _0532_;
- wire [2879:0] _0533_;
- wire _0534_;
- wire [4:0] _0535_;
- wire [4:0] _0536_;
- wire [2879:0] _0537_;
- wire [2879:0] _0538_;
- wire [63:0] _0539_;
- wire _0540_;
- wire [2879:0] _0541_;
- wire [63:0] _0542_;
- wire _0543_;
- wire [109:0] _0544_;
- wire [13:0] _0545_;
- wire _0546_;
- wire _0547_;
- wire _0548_;
- wire _0549_;
- wire _0550_;
- wire _0551_;
- wire [2879:0] _0552_;
- wire [63:0] _0553_;
- wire _0554_;
- wire [2:0] _0555_;
- wire [31:0] _0556_;
- wire [63:0] _0557_;
- wire _0558_;
- wire _0559_;
- wire [7:0] _0560_;
- wire _0561_;
- wire _0562_;
- wire [7:0] _0563_;
- wire [4:0] _0564_;
- wire _0565_;
- wire _0566_;
- wire _0567_;
- wire _0568_;
- wire _0569_;
- wire _0570_;
- wire _0571_;
- wire _0572_;
- wire [2:0] _0573_;
- wire [31:0] _0574_;
- wire _0575_;
- wire _0576_;
- wire _0577_;
- wire _0578_;
- wire _0579_;
- wire [63:0] _0580_;
- wire _0581_;
- wire _0582_;
- wire [4:0] _0583_;
- wire [63:0] _0584_;
- wire [2:0] _0585_;
- wire _0586_;
- wire [2:0] _0587_;
- wire _0588_;
- wire _0589_;
- wire _0590_;
- wire _0591_;
- wire [7:0] _0592_;
- wire _0593_;
- wire _0594_;
- wire _0595_;
- wire _0596_;
- wire _0597_;
- wire [63:0] _0598_;
- wire [64:0] _0599_;
- wire [2:0] _0600_;
- wire [1:0] _0601_;
- wire _0602_;
- wire _0603_;
- wire _0604_;
- wire [2879:0] _0605_;
- wire [63:0] _0606_;
- wire [63:0] _0607_;
- wire _0608_;
- wire _0609_;
- wire [2:0] _0610_;
- wire [31:0] _0611_;
- wire [63:0] _0612_;
- wire _0613_;
- wire _0614_;
- wire [7:0] _0615_;
- wire _0616_;
- wire _0617_;
- wire [7:0] _0618_;
- wire [4:0] _0619_;
- wire [2879:0] _0620_;
- wire [63:0] _0621_;
- wire [63:0] _0622_;
- wire _0623_;
- wire _0624_;
- wire [34:0] _0625_;
- wire [63:0] _0626_;
- wire [1:0] _0627_;
- wire [22:0] _0628_;
- reg [189:0] _0629_;
- wire [5887:0] _0630_;
- wire [8191:0] _0631_;
- wire [1:0] _0632_;
- wire [1:0] _0633_;
- wire [1:0] _0634_;
- wire [1:0] _0635_;
- wire [1:0] _0636_;
- wire [1:0] _0637_;
- wire [1:0] _0638_;
- wire [1:0] _0639_;
- wire [1:0] _0640_;
- wire [1:0] _0641_;
- wire [1:0] _0642_;
- wire [1:0] _0643_;
- wire [1:0] _0644_;
- wire [1:0] _0645_;
- wire [1:0] _0646_;
- wire [1:0] _0647_;
- wire [1:0] _0648_;
- wire [1:0] _0649_;
- wire [1:0] _0650_;
- wire [1:0] _0651_;
- wire [1:0] _0652_;
- wire [63:0] _0653_;
- wire _0654_;
- wire _0655_;
- wire _0656_;
- wire _0657_;
- wire _0658_;
- wire _0659_;
- wire _0660_;
- wire _0661_;
- wire _0662_;
- wire _0663_;
- wire _0664_;
- wire _0665_;
- wire _0666_;
- wire _0667_;
- wire _0668_;
- wire _0669_;
- wire _0670_;
- wire _0671_;
- wire _0672_;
- wire _0673_;
- wire _0674_;
- wire _0675_;
- wire _0676_;
- wire _0677_;
- wire _0678_;
- wire _0679_;
- wire _0680_;
- wire _0681_;
- wire _0682_;
- wire _0683_;
- wire _0684_;
- wire _0685_;
- wire _0686_;
- wire _0687_;
- wire _0688_;
- wire _0689_;
- wire _0690_;
- wire _0691_;
- wire _0692_;
- wire _0693_;
- wire _0694_;
- wire _0695_;
- wire _0696_;
- wire _0697_;
- wire _0698_;
- wire _0699_;
- wire _0700_;
- wire _0701_;
- wire _0702_;
- wire _0703_;
- wire _0704_;
- wire _0705_;
- wire _0706_;
- wire _0707_;
- wire _0708_;
- wire _0709_;
- wire _0710_;
- wire _0711_;
- wire _0712_;
- wire _0713_;
- wire _0714_;
- wire _0715_;
- wire _0716_;
- wire _0717_;
- wire _0718_;
- wire _0719_;
- wire _0720_;
- wire _0721_;
- wire _0722_;
- wire _0723_;
- wire _0724_;
- wire _0725_;
- wire _0726_;
- wire _0727_;
- wire _0728_;
- wire _0729_;
- wire _0730_;
- wire _0731_;
- wire _0732_;
- wire _0733_;
- wire _0734_;
- wire _0735_;
- wire _0736_;
- wire _0737_;
- wire _0738_;
- wire _0739_;
- wire _0740_;
- wire _0741_;
- wire _0742_;
- wire _0743_;
- wire _0744_;
- wire _0745_;
- wire _0746_;
- wire _0747_;
- wire _0748_;
- wire _0749_;
- wire _0750_;
- wire _0751_;
- wire _0752_;
- wire _0753_;
- wire _0754_;
- wire _0755_;
- wire _0756_;
- wire _0757_;
- wire _0758_;
- wire _0759_;
- wire _0760_;
- wire _0761_;
- wire _0762_;
- wire _0763_;
- wire _0764_;
- wire _0765_;
- wire _0766_;
- wire _0767_;
- wire _0768_;
- wire _0769_;
- wire _0770_;
- wire _0771_;
- wire _0772_;
- wire _0773_;
- wire _0774_;
- wire _0775_;
- wire _0776_;
- wire _0777_;
- wire _0778_;
- wire _0779_;
- wire _0780_;
- wire _0781_;
- wire _0782_;
- wire _0783_;
- wire _0784_;
- wire _0785_;
- wire _0786_;
- wire _0787_;
- wire _0788_;
- wire _0789_;
- wire _0790_;
- wire _0791_;
- wire _0792_;
- wire _0793_;
- wire _0794_;
- wire _0795_;
- wire _0796_;
- wire _0797_;
- wire _0798_;
- wire _0799_;
- wire _0800_;
- wire _0801_;
- wire _0802_;
- wire _0803_;
- wire _0804_;
- wire _0805_;
- wire _0806_;
- wire _0807_;
- wire _0808_;
- wire _0809_;
- wire _0810_;
- wire _0811_;
- wire _0812_;
- wire _0813_;
- wire _0814_;
- wire _0815_;
- wire _0816_;
- wire _0817_;
- wire _0818_;
- wire _0819_;
- wire _0820_;
- wire _0821_;
- wire _0822_;
- wire _0823_;
- wire _0824_;
- wire _0825_;
- wire _0826_;
- wire _0827_;
- wire _0828_;
- wire _0829_;
- wire _0830_;
- wire _0831_;
- wire _0832_;
- wire _0833_;
- wire _0834_;
- wire _0835_;
- wire _0836_;
- wire _0837_;
- wire _0838_;
- wire _0839_;
- wire _0840_;
- wire _0841_;
- wire _0842_;
- wire _0843_;
- wire _0844_;
- wire _0845_;
- wire _0846_;
- wire _0847_;
- wire _0848_;
- wire _0849_;
- wire _0850_;
- wire _0851_;
- wire _0852_;
- wire _0853_;
- wire _0854_;
- wire _0855_;
- wire _0856_;
- wire _0857_;
- wire _0858_;
- wire _0859_;
- wire _0860_;
- wire _0861_;
- wire _0862_;
- wire _0863_;
- wire _0864_;
- wire _0865_;
- wire _0866_;
- wire _0867_;
- wire _0868_;
- wire _0869_;
- wire _0870_;
- wire _0871_;
- wire _0872_;
- wire _0873_;
- wire _0874_;
- wire _0875_;
- wire _0876_;
- wire _0877_;
- wire _0878_;
- wire _0879_;
- wire _0880_;
- wire _0881_;
- wire _0882_;
- wire _0883_;
- wire _0884_;
- wire _0885_;
- wire _0886_;
- wire _0887_;
- wire _0888_;
- wire _0889_;
- wire _0890_;
- wire _0891_;
- wire _0892_;
- wire _0893_;
- wire _0894_;
- wire _0895_;
- wire _0896_;
- wire _0897_;
- wire _0898_;
- wire _0899_;
- wire _0900_;
- wire _0901_;
- wire _0902_;
- wire _0903_;
- wire _0904_;
- wire _0905_;
- wire _0906_;
- wire _0907_;
- wire _0908_;
- wire _0909_;
- wire _0910_;
- wire _0911_;
- wire _0912_;
- wire _0913_;
- wire _0914_;
- wire _0915_;
- wire _0916_;
- wire _0917_;
- wire _0918_;
- wire _0919_;
- wire _0920_;
- wire _0921_;
- wire _0922_;
- wire _0923_;
- wire _0924_;
- wire _0925_;
- wire _0926_;
- wire _0927_;
- wire _0928_;
- wire _0929_;
- wire _0930_;
- wire _0931_;
- wire _0932_;
- wire _0933_;
- wire _0934_;
- wire _0935_;
- wire _0936_;
- wire _0937_;
- wire _0938_;
- wire _0939_;
- wire _0940_;
- wire _0941_;
- wire _0942_;
- wire _0943_;
- wire _0944_;
- wire _0945_;
- wire _0946_;
- wire _0947_;
- wire _0948_;
- wire _0949_;
- wire _0950_;
- wire _0951_;
- wire _0952_;
- wire _0953_;
- wire _0954_;
- wire _0955_;
- wire _0956_;
- wire _0957_;
- wire _0958_;
- wire _0959_;
- wire _0960_;
- wire _0961_;
- wire _0962_;
- wire _0963_;
- wire _0964_;
- wire _0965_;
- wire _0966_;
- wire _0967_;
- wire _0968_;
- wire _0969_;
- wire _0970_;
- wire _0971_;
- wire _0972_;
- wire _0973_;
- wire _0974_;
- wire _0975_;
- wire _0976_;
- wire _0977_;
- wire _0978_;
- wire _0979_;
- wire _0980_;
- wire _0981_;
- wire _0982_;
- wire _0983_;
- wire _0984_;
- wire _0985_;
- wire _0986_;
- wire _0987_;
- wire _0988_;
- wire _0989_;
- wire _0990_;
- wire _0991_;
- wire _0992_;
- wire _0993_;
- wire _0994_;
- wire _0995_;
- wire _0996_;
- wire _0997_;
- wire _0998_;
- wire _0999_;
- wire _1000_;
- wire _1001_;
- wire _1002_;
- wire _1003_;
- wire _1004_;
- wire _1005_;
- wire _1006_;
- wire _1007_;
- wire _1008_;
- wire _1009_;
- wire _1010_;
- wire _1011_;
- wire _1012_;
- wire _1013_;
- wire _1014_;
- wire _1015_;
- wire _1016_;
- wire _1017_;
- wire _1018_;
- wire _1019_;
- wire _1020_;
- wire _1021_;
- wire _1022_;
- wire _1023_;
- wire _1024_;
- wire _1025_;
- wire _1026_;
- wire _1027_;
- wire _1028_;
- wire _1029_;
- wire _1030_;
- wire _1031_;
- wire _1032_;
- wire _1033_;
- wire _1034_;
- wire _1035_;
- wire _1036_;
- wire _1037_;
- wire _1038_;
- wire _1039_;
- wire _1040_;
- wire _1041_;
- wire _1042_;
- wire _1043_;
- wire _1044_;
- wire _1045_;
- wire _1046_;
- wire _1047_;
- wire _1048_;
- wire _1049_;
- wire _1050_;
- wire _1051_;
- wire _1052_;
- wire _1053_;
- wire _1054_;
- wire _1055_;
- wire _1056_;
- wire _1057_;
- wire _1058_;
- wire _1059_;
- wire _1060_;
- wire _1061_;
- wire _1062_;
- wire [45:0] _1063_;
- wire [45:0] _1064_;
- wire _1065_;
- wire [63:0] _1066_;
- wire [63:0] _1067_;
- wire _1068_;
- wire _1069_;
- wire _1070_;
- wire _1071_;
- wire _1072_;
- wire _1073_;
- wire _1074_;
- wire _1075_;
- wire _1076_;
- wire _1077_;
- wire _1078_;
- wire _1079_;
- wire _1080_;
- wire _1081_;
- wire _1082_;
- wire _1083_;
- wire _1084_;
- wire _1085_;
- wire _1086_;
- wire _1087_;
- wire _1088_;
- wire _1089_;
- wire _1090_;
- wire _1091_;
- wire _1092_;
- wire _1093_;
- wire _1094_;
- wire _1095_;
- wire _1096_;
- wire _1097_;
- wire _1098_;
- wire _1099_;
- wire _1100_;
- wire _1101_;
- wire _1102_;
- wire _1103_;
- wire _1104_;
- wire _1105_;
- wire _1106_;
- wire _1107_;
- wire _1108_;
- wire _1109_;
- wire _1110_;
- wire _1111_;
- wire _1112_;
- wire _1113_;
- wire _1114_;
- wire _1115_;
- wire _1116_;
- wire _1117_;
- wire _1118_;
- wire _1119_;
- wire _1120_;
- wire _1121_;
- wire _1122_;
- wire _1123_;
- wire _1124_;
- wire _1125_;
- wire _1126_;
- wire _1127_;
- wire _1128_;
- wire _1129_;
- wire _1130_;
- wire _1131_;
- wire _1132_;
- wire _1133_;
- wire _1134_;
- wire _1135_;
- wire _1136_;
- wire _1137_;
- wire _1138_;
- wire _1139_;
- wire _1140_;
- wire _1141_;
- wire _1142_;
- wire _1143_;
- wire _1144_;
- wire _1145_;
- wire _1146_;
- wire _1147_;
- wire _1148_;
- wire _1149_;
- wire _1150_;
- wire _1151_;
- wire _1152_;
- wire _1153_;
- wire _1154_;
- wire _1155_;
- wire _1156_;
- wire _1157_;
- wire _1158_;
- wire _1159_;
- wire _1160_;
- wire _1161_;
- wire _1162_;
- wire _1163_;
- wire _1164_;
- wire _1165_;
- wire _1166_;
- wire _1167_;
- wire _1168_;
- wire _1169_;
- wire _1170_;
- wire _1171_;
- wire _1172_;
- wire _1173_;
- wire _1174_;
- wire _1175_;
- wire _1176_;
- wire _1177_;
- wire _1178_;
- wire _1179_;
- wire _1180_;
- wire _1181_;
- wire _1182_;
- wire _1183_;
- wire _1184_;
- wire _1185_;
- wire _1186_;
- wire _1187_;
- wire _1188_;
- wire _1189_;
- wire _1190_;
- wire _1191_;
- wire _1192_;
- wire _1193_;
- wire _1194_;
- wire _1195_;
- wire _1196_;
- wire _1197_;
- wire _1198_;
- wire _1199_;
- wire _1200_;
- wire _1201_;
- wire _1202_;
- wire _1203_;
- wire _1204_;
- wire _1205_;
- wire _1206_;
- wire _1207_;
- wire _1208_;
- wire _1209_;
- wire _1210_;
- wire _1211_;
- wire _1212_;
- wire _1213_;
- wire _1214_;
- wire _1215_;
- wire _1216_;
- wire _1217_;
- wire _1218_;
- wire _1219_;
- wire _1220_;
- wire _1221_;
- wire _1222_;
- wire _1223_;
- wire _1224_;
- wire _1225_;
- wire _1226_;
- wire _1227_;
- wire _1228_;
- wire _1229_;
- wire _1230_;
- wire _1231_;
- wire _1232_;
- wire _1233_;
- wire _1234_;
- wire _1235_;
- wire _1236_;
- wire _1237_;
- wire _1238_;
- wire _1239_;
- wire _1240_;
- wire _1241_;
- wire _1242_;
- wire _1243_;
- wire _1244_;
- wire _1245_;
- wire _1246_;
- wire _1247_;
- wire _1248_;
- wire _1249_;
- wire _1250_;
- wire _1251_;
- wire _1252_;
- wire _1253_;
- wire _1254_;
- wire _1255_;
- wire _1256_;
- wire _1257_;
- wire _1258_;
- wire _1259_;
- wire _1260_;
- wire _1261_;
- wire _1262_;
- wire _1263_;
- wire _1264_;
- wire _1265_;
- wire _1266_;
- wire _1267_;
- wire _1268_;
- wire _1269_;
- wire _1270_;
- wire _1271_;
- wire _1272_;
- wire _1273_;
- wire _1274_;
- wire _1275_;
- wire _1276_;
- wire _1277_;
- wire _1278_;
- wire _1279_;
- wire _1280_;
- wire _1281_;
- wire _1282_;
- wire _1283_;
- wire _1284_;
- wire _1285_;
- wire _1286_;
- wire _1287_;
- wire _1288_;
- wire _1289_;
- wire _1290_;
- wire _1291_;
- wire _1292_;
- wire _1293_;
- wire _1294_;
- wire _1295_;
- wire _1296_;
- wire _1297_;
- wire _1298_;
- wire _1299_;
- wire _1300_;
- wire _1301_;
- wire _1302_;
- wire _1303_;
- wire _1304_;
- wire _1305_;
- wire _1306_;
- wire _1307_;
- wire _1308_;
- wire _1309_;
- wire _1310_;
- wire _1311_;
- wire _1312_;
- wire _1313_;
- wire _1314_;
- wire _1315_;
- wire _1316_;
- wire _1317_;
- wire _1318_;
- wire _1319_;
- wire _1320_;
- wire _1321_;
- wire _1322_;
- wire _1323_;
- wire _1324_;
- wire _1325_;
- wire _1326_;
- wire _1327_;
- wire _1328_;
- wire _1329_;
- wire _1330_;
- wire _1331_;
- wire _1332_;
- wire _1333_;
- wire _1334_;
- wire _1335_;
- wire _1336_;
- wire _1337_;
- wire _1338_;
- wire _1339_;
- wire _1340_;
- wire _1341_;
- wire _1342_;
- wire _1343_;
- wire _1344_;
- wire _1345_;
- wire _1346_;
- wire _1347_;
- wire _1348_;
- wire _1349_;
- wire _1350_;
- wire _1351_;
- wire _1352_;
- wire _1353_;
- wire _1354_;
- wire _1355_;
- wire _1356_;
- wire _1357_;
- wire _1358_;
- wire _1359_;
- wire _1360_;
- wire _1361_;
- wire _1362_;
- wire _1363_;
- wire _1364_;
- wire _1365_;
- wire _1366_;
- wire _1367_;
- wire _1368_;
- wire _1369_;
- wire _1370_;
- wire _1371_;
- wire _1372_;
- wire _1373_;
- wire _1374_;
- wire _1375_;
- wire _1376_;
- wire _1377_;
- wire _1378_;
- wire _1379_;
- wire _1380_;
- wire _1381_;
- wire _1382_;
- wire _1383_;
- wire _1384_;
- wire _1385_;
- wire _1386_;
- wire _1387_;
- wire _1388_;
- wire _1389_;
- wire _1390_;
- wire _1391_;
- wire _1392_;
- wire _1393_;
- wire _1394_;
- wire _1395_;
- wire _1396_;
- wire _1397_;
- wire _1398_;
- wire _1399_;
- wire _1400_;
- wire _1401_;
- wire _1402_;
- wire _1403_;
- wire _1404_;
- wire _1405_;
- wire _1406_;
- wire _1407_;
- wire _1408_;
- wire _1409_;
- wire _1410_;
- wire _1411_;
- wire _1412_;
- wire _1413_;
- wire _1414_;
- wire _1415_;
- wire _1416_;
- wire _1417_;
- wire _1418_;
- wire _1419_;
- wire _1420_;
- wire _1421_;
- wire _1422_;
- wire _1423_;
- wire _1424_;
- wire _1425_;
- wire _1426_;
- wire _1427_;
- wire _1428_;
- wire _1429_;
- wire _1430_;
- wire _1431_;
- wire _1432_;
- wire _1433_;
- wire _1434_;
- wire _1435_;
- wire _1436_;
- wire _1437_;
- wire _1438_;
- wire _1439_;
- wire _1440_;
- wire _1441_;
- wire _1442_;
- wire _1443_;
- wire _1444_;
- wire _1445_;
- wire _1446_;
- wire _1447_;
- wire _1448_;
- wire _1449_;
- wire _1450_;
- wire _1451_;
- wire _1452_;
- wire _1453_;
- wire _1454_;
- wire _1455_;
- wire _1456_;
- wire _1457_;
- wire _1458_;
- wire _1459_;
- wire _1460_;
- wire _1461_;
- wire _1462_;
- wire _1463_;
- wire _1464_;
- wire _1465_;
- wire [89:0] _1466_;
- wire [89:0] _1467_;
- wire [89:0] _1468_;
- wire [89:0] _1469_;
- wire [89:0] _1470_;
- wire [89:0] _1471_;
- wire [89:0] _1472_;
- wire [89:0] _1473_;
- wire [89:0] _1474_;
- wire [89:0] _1475_;
- wire [89:0] _1476_;
- wire _1477_;
- wire _1478_;
- wire _1479_;
- wire _1480_;
- wire _1481_;
- wire _1482_;
- wire _1483_;
- wire _1484_;
- wire _1485_;
- wire _1486_;
- wire _1487_;
- wire [89:0] _1488_;
- wire [89:0] _1489_;
- wire [89:0] _1490_;
- wire [89:0] _1491_;
- wire [89:0] _1492_;
- wire [89:0] _1493_;
- wire [89:0] _1494_;
- wire [89:0] _1495_;
- wire [89:0] _1496_;
- wire [89:0] _1497_;
- wire [89:0] _1498_;
- wire _1499_;
- wire _1500_;
- wire _1501_;
- wire _1502_;
- wire _1503_;
- wire _1504_;
- wire _1505_;
- wire _1506_;
- wire _1507_;
- wire _1508_;
- wire _1509_;
- wire [89:0] _1510_;
- wire [89:0] _1511_;
- wire [89:0] _1512_;
- wire [89:0] _1513_;
- wire [89:0] _1514_;
- wire [89:0] _1515_;
- wire [89:0] _1516_;
- wire [89:0] _1517_;
- wire [89:0] _1518_;
- wire [89:0] _1519_;
- wire [89:0] _1520_;
- wire _1521_;
- wire _1522_;
- wire _1523_;
- wire _1524_;
- wire _1525_;
- wire _1526_;
- wire _1527_;
- wire _1528_;
- wire _1529_;
- wire _1530_;
- wire _1531_;
- wire [89:0] _1532_;
- wire [89:0] _1533_;
- wire [89:0] _1534_;
- wire [89:0] _1535_;
- wire [89:0] _1536_;
- wire [89:0] _1537_;
- wire [89:0] _1538_;
- wire [89:0] _1539_;
- wire [89:0] _1540_;
- wire [89:0] _1541_;
- wire [89:0] _1542_;
- wire _1543_;
- wire _1544_;
- wire _1545_;
- wire _1546_;
- wire _1547_;
- wire _1548_;
- wire _1549_;
- wire _1550_;
- wire _1551_;
- wire _1552_;
- wire _1553_;
- wire _1554_;
- wire _1555_;
- wire [89:0] _1556_;
- wire [89:0] _1557_;
- wire [89:0] _1558_;
- wire [89:0] _1559_;
- wire [89:0] _1560_;
- wire [89:0] _1561_;
- wire [89:0] _1562_;
- wire [89:0] _1563_;
- wire [89:0] _1564_;
- wire [89:0] _1565_;
- wire [89:0] _1566_;
- wire _1567_;
- wire _1568_;
- wire _1569_;
- wire _1570_;
- wire _1571_;
- wire _1572_;
- wire _1573_;
- wire _1574_;
- wire _1575_;
- wire _1576_;
- wire _1577_;
- wire [89:0] _1578_;
- wire [89:0] _1579_;
- wire [89:0] _1580_;
- wire [89:0] _1581_;
- wire [89:0] _1582_;
- wire [89:0] _1583_;
- wire [89:0] _1584_;
- wire [89:0] _1585_;
- wire [89:0] _1586_;
- wire [89:0] _1587_;
- wire [89:0] _1588_;
- wire _1589_;
- wire _1590_;
- wire _1591_;
- wire _1592_;
- wire _1593_;
- wire _1594_;
- wire _1595_;
- wire _1596_;
- wire _1597_;
- wire _1598_;
- wire [63:0] _1599_;
- wire [63:0] _1600_;
- wire _1601_;
- wire _1602_;
- wire _1603_;
- wire _1604_;
- wire _1605_;
- wire _1606_;
- wire _1607_;
- wire _1608_;
- wire _1609_;
- wire _1610_;
- wire _1611_;
- wire _1612_;
- wire _1613_;
- wire _1614_;
- wire _1615_;
- wire _1616_;
- wire _1617_;
- wire _1618_;
- wire _1619_;
- wire _1620_;
- wire _1621_;
- wire _1622_;
- wire _1623_;
- wire _1624_;
- wire _1625_;
- wire _1626_;
- wire _1627_;
- wire _1628_;
- wire _1629_;
- wire _1630_;
- wire _1631_;
- wire _1632_;
- wire _1633_;
- wire _1634_;
- wire _1635_;
- wire _1636_;
- wire _1637_;
- wire _1638_;
- wire _1639_;
- wire _1640_;
- wire _1641_;
- wire _1642_;
- wire _1643_;
- wire _1644_;
- wire _1645_;
- wire _1646_;
- wire _1647_;
- wire _1648_;
- wire _1649_;
- wire _1650_;
- wire _1651_;
- wire _1652_;
- wire _1653_;
- wire _1654_;
- wire _1655_;
- wire _1656_;
- wire _1657_;
- wire _1658_;
- wire _1659_;
- wire _1660_;
- wire _1661_;
- wire _1662_;
- wire _1663_;
- wire _1664_;
- wire _1665_;
- wire _1666_;
- wire _1667_;
- wire _1668_;
- wire _1669_;
- wire _1670_;
- wire _1671_;
- wire _1672_;
- wire _1673_;
- wire _1674_;
- wire _1675_;
- wire _1676_;
- wire _1677_;
- wire _1678_;
- wire _1679_;
- wire _1680_;
- wire _1681_;
- wire _1682_;
- wire _1683_;
- wire _1684_;
- wire _1685_;
- wire _1686_;
- wire _1687_;
- wire _1688_;
- wire _1689_;
- wire _1690_;
- wire _1691_;
- wire _1692_;
- wire _1693_;
- wire _1694_;
- wire _1695_;
- wire _1696_;
- wire _1697_;
- wire _1698_;
- wire _1699_;
- wire _1700_;
- wire _1701_;
- wire _1702_;
- wire _1703_;
- wire _1704_;
- wire _1705_;
- wire _1706_;
- wire _1707_;
- wire _1708_;
- wire _1709_;
- wire _1710_;
- wire _1711_;
- wire _1712_;
- wire _1713_;
- wire _1714_;
- wire _1715_;
- wire _1716_;
- wire _1717_;
- wire _1718_;
- wire _1719_;
- wire _1720_;
- wire _1721_;
- wire _1722_;
- wire _1723_;
- wire _1724_;
- wire _1725_;
- wire _1726_;
- wire _1727_;
- wire _1728_;
- wire _1729_;
- wire _1730_;
- wire _1731_;
- wire _1732_;
- wire _1733_;
- wire _1734_;
- wire _1735_;
- wire _1736_;
- wire _1737_;
- wire _1738_;
- wire _1739_;
- wire _1740_;
- wire _1741_;
- wire _1742_;
- wire _1743_;
- wire _1744_;
- wire _1745_;
- wire _1746_;
- wire _1747_;
- wire _1748_;
- wire _1749_;
- wire _1750_;
- wire _1751_;
- wire _1752_;
- wire _1753_;
- wire _1754_;
- wire _1755_;
- wire _1756_;
- wire _1757_;
- wire _1758_;
- wire _1759_;
- wire _1760_;
- wire _1761_;
- wire _1762_;
- wire _1763_;
- wire _1764_;
- wire _1765_;
- wire _1766_;
- wire _1767_;
- wire _1768_;
- wire _1769_;
- wire _1770_;
- wire _1771_;
- wire _1772_;
- wire _1773_;
- wire _1774_;
- wire _1775_;
- wire _1776_;
- wire _1777_;
- wire _1778_;
- wire _1779_;
- wire _1780_;
- wire _1781_;
- wire _1782_;
- wire _1783_;
- wire _1784_;
- wire _1785_;
- wire _1786_;
- wire _1787_;
- wire _1788_;
- wire _1789_;
- wire _1790_;
- wire _1791_;
- wire _1792_;
- wire _1793_;
- wire _1794_;
- wire [89:0] _1795_;
- wire [89:0] _1796_;
- wire [89:0] _1797_;
- wire [89:0] _1798_;
- wire [89:0] _1799_;
- wire [89:0] _1800_;
- wire [89:0] _1801_;
- wire [89:0] _1802_;
- wire [89:0] _1803_;
- wire [89:0] _1804_;
- wire [89:0] _1805_;
- wire _1806_;
- wire _1807_;
- wire _1808_;
- wire _1809_;
- wire _1810_;
- wire _1811_;
- wire _1812_;
- wire _1813_;
- wire _1814_;
- wire _1815_;
- wire _1816_;
- wire _1817_;
- wire _1818_;
- wire _1819_;
- wire _1820_;
- wire _1821_;
- wire _1822_;
- wire _1823_;
- wire _1824_;
- wire _1825_;
- wire _1826_;
- wire _1827_;
- wire _1828_;
- wire _1829_;
- wire _1830_;
- wire _1831_;
- wire _1832_;
- wire _1833_;
- wire _1834_;
- wire _1835_;
- wire _1836_;
- wire _1837_;
- wire _1838_;
- wire _1839_;
- wire _1840_;
- wire _1841_;
- wire _1842_;
- wire _1843_;
- wire _1844_;
- wire _1845_;
- wire _1846_;
- wire _1847_;
- wire _1848_;
- wire _1849_;
- wire _1850_;
- wire _1851_;
- wire _1852_;
- wire _1853_;
- wire _1854_;
- wire _1855_;
- wire _1856_;
- wire _1857_;
- wire _1858_;
- wire _1859_;
- wire _1860_;
- wire _1861_;
- wire _1862_;
- wire _1863_;
- wire _1864_;
- wire _1865_;
- wire _1866_;
- wire _1867_;
- wire _1868_;
- wire _1869_;
- wire _1870_;
- wire [89:0] _1871_;
- wire [89:0] _1872_;
- wire [89:0] _1873_;
- wire [89:0] _1874_;
- wire [89:0] _1875_;
- wire [89:0] _1876_;
- wire [89:0] _1877_;
- wire [89:0] _1878_;
- wire [89:0] _1879_;
- wire [89:0] _1880_;
- wire [89:0] _1881_;
- wire [89:0] _1882_;
- wire [89:0] _1883_;
- wire [89:0] _1884_;
- wire [89:0] _1885_;
- wire [89:0] _1886_;
- wire [89:0] _1887_;
- wire [89:0] _1888_;
- wire [89:0] _1889_;
- wire [89:0] _1890_;
- wire [89:0] _1891_;
- wire [89:0] _1892_;
- wire [89:0] _1893_;
- wire [89:0] _1894_;
- wire [89:0] _1895_;
- wire [89:0] _1896_;
- wire [89:0] _1897_;
- wire [89:0] _1898_;
- wire [89:0] _1899_;
- wire [89:0] _1900_;
- wire [89:0] _1901_;
- wire [89:0] _1902_;
- wire [89:0] _1903_;
- wire [89:0] _1904_;
- wire [89:0] _1905_;
- wire [89:0] _1906_;
- wire [89:0] _1907_;
- wire [89:0] _1908_;
- wire [89:0] _1909_;
- wire [89:0] _1910_;
- wire [89:0] _1911_;
- wire [89:0] _1912_;
- wire [89:0] _1913_;
- wire _1914_;
- wire _1915_;
- wire _1916_;
- wire _1917_;
- wire _1918_;
- wire _1919_;
- wire _1920_;
- wire _1921_;
- wire _1922_;
- wire _1923_;
- wire _1924_;
- wire _1925_;
- wire _1926_;
- wire _1927_;
- wire _1928_;
- wire _1929_;
- wire _1930_;
- wire _1931_;
- wire _1932_;
- wire _1933_;
- wire _1934_;
- wire _1935_;
- wire _1936_;
- wire _1937_;
- wire _1938_;
- wire _1939_;
- wire _1940_;
- wire _1941_;
- wire _1942_;
- wire _1943_;
- wire _1944_;
- wire _1945_;
- wire _1946_;
- wire _1947_;
- wire _1948_;
- wire _1949_;
- wire _1950_;
- wire _1951_;
- wire _1952_;
- wire _1953_;
- wire _1954_;
- wire _1955_;
- wire _1956_;
- wire _1957_;
- wire _1958_;
- wire _1959_;
- wire _1960_;
- wire _1961_;
- wire _1962_;
- wire _1963_;
- wire _1964_;
- wire _1965_;
- wire _1966_;
- wire _1967_;
- wire _1968_;
- wire _1969_;
- wire _1970_;
- wire _1971_;
- wire _1972_;
- wire _1973_;
- wire _1974_;
- wire _1975_;
- wire _1976_;
- wire _1977_;
- wire _1978_;
- wire [89:0] _1979_;
- wire [89:0] _1980_;
- wire [89:0] _1981_;
- wire [89:0] _1982_;
- wire [89:0] _1983_;
- wire [89:0] _1984_;
- wire [89:0] _1985_;
- wire [89:0] _1986_;
- wire [89:0] _1987_;
- wire [89:0] _1988_;
- wire [89:0] _1989_;
- wire [89:0] _1990_;
- wire [89:0] _1991_;
- wire [89:0] _1992_;
- wire [89:0] _1993_;
- wire [89:0] _1994_;
- wire [89:0] _1995_;
- wire [89:0] _1996_;
- wire [89:0] _1997_;
- wire [89:0] _1998_;
- wire [89:0] _1999_;
- wire [89:0] _2000_;
- wire [89:0] _2001_;
- wire [89:0] _2002_;
- wire [89:0] _2003_;
- wire [89:0] _2004_;
- wire [89:0] _2005_;
- wire [89:0] _2006_;
- wire [89:0] _2007_;
- wire [89:0] _2008_;
- wire [89:0] _2009_;
- wire [89:0] _2010_;
- wire _2011_;
- wire _2012_;
- wire _2013_;
- wire _2014_;
- wire _2015_;
- wire _2016_;
- wire _2017_;
- wire _2018_;
- wire _2019_;
- wire _2020_;
- wire _2021_;
- wire _2022_;
- wire _2023_;
- wire _2024_;
- wire _2025_;
- wire _2026_;
- wire _2027_;
- wire _2028_;
- wire _2029_;
- wire _2030_;
- wire _2031_;
- wire _2032_;
- wire _2033_;
- wire _2034_;
- wire _2035_;
- wire _2036_;
- wire _2037_;
- wire _2038_;
- wire _2039_;
- wire _2040_;
- wire _2041_;
- wire _2042_;
- wire _2043_;
- wire _2044_;
- wire _2045_;
- wire _2046_;
- wire _2047_;
- wire _2048_;
- wire _2049_;
- wire _2050_;
- wire _2051_;
- wire _2052_;
- wire _2053_;
- wire _2054_;
- wire _2055_;
- wire _2056_;
- wire _2057_;
- wire _2058_;
- wire _2059_;
- wire _2060_;
- wire _2061_;
- wire _2062_;
- wire _2063_;
- wire _2064_;
- wire _2065_;
- wire _2066_;
- wire _2067_;
- wire _2068_;
- wire _2069_;
- wire _2070_;
- wire _2071_;
- wire _2072_;
- wire _2073_;
- wire _2074_;
- wire _2075_;
- wire _2076_;
- wire _2077_;
- wire _2078_;
- wire _2079_;
- wire _2080_;
- wire _2081_;
- wire _2082_;
- wire _2083_;
- wire _2084_;
- wire _2085_;
- wire _2086_;
- wire _2087_;
- wire _2088_;
- wire _2089_;
- wire _2090_;
- wire _2091_;
- wire _2092_;
- wire _2093_;
- wire _2094_;
- wire _2095_;
- wire _2096_;
- wire _2097_;
- wire _2098_;
- wire _2099_;
- wire _2100_;
- wire _2101_;
- wire _2102_;
- wire _2103_;
- wire _2104_;
- wire _2105_;
- wire _2106_;
- wire _2107_;
- wire _2108_;
- wire _2109_;
- wire _2110_;
- wire _2111_;
- wire _2112_;
- wire _2113_;
- wire _2114_;
- wire _2115_;
- wire _2116_;
- wire _2117_;
- wire _2118_;
- wire _2119_;
- wire _2120_;
- wire _2121_;
- wire _2122_;
- wire _2123_;
- wire _2124_;
- wire _2125_;
- wire _2126_;
- wire _2127_;
- wire _2128_;
- wire _2129_;
- wire _2130_;
- wire _2131_;
- wire _2132_;
- wire _2133_;
- wire _2134_;
- wire _2135_;
- wire _2136_;
- wire _2137_;
- wire _2138_;
- wire _2139_;
- wire _2140_;
- wire _2141_;
- wire _2142_;
- wire _2143_;
- wire _2144_;
- wire _2145_;
- wire _2146_;
- wire _2147_;
- wire _2148_;
- wire _2149_;
- wire _2150_;
- wire _2151_;
- wire _2152_;
- wire _2153_;
- wire _2154_;
- wire _2155_;
- wire _2156_;
- wire _2157_;
- wire _2158_;
- wire _2159_;
- wire _2160_;
- wire _2161_;
- wire _2162_;
- wire _2163_;
- wire _2164_;
- wire _2165_;
- wire _2166_;
- wire _2167_;
- wire _2168_;
- wire _2169_;
- wire _2170_;
- wire _2171_;
- wire _2172_;
- wire _2173_;
- wire _2174_;
- wire _2175_;
- wire _2176_;
- wire _2177_;
- wire _2178_;
- wire _2179_;
- wire _2180_;
- wire _2181_;
- wire _2182_;
- wire _2183_;
- wire _2184_;
- wire _2185_;
- wire _2186_;
- wire _2187_;
- wire _2188_;
- wire _2189_;
- wire _2190_;
- wire _2191_;
- wire _2192_;
- wire _2193_;
- wire _2194_;
- wire _2195_;
- wire _2196_;
- wire _2197_;
- wire _2198_;
- wire _2199_;
- wire _2200_;
- wire _2201_;
- wire _2202_;
- wire _2203_;
- wire _2204_;
- wire [89:0] _2205_;
- wire [89:0] _2206_;
- wire [89:0] _2207_;
- wire [89:0] _2208_;
- wire [89:0] _2209_;
- wire [89:0] _2210_;
- wire [89:0] _2211_;
- wire [89:0] _2212_;
- wire [89:0] _2213_;
- wire [89:0] _2214_;
- wire [89:0] _2215_;
- wire _2216_;
- wire _2217_;
- wire _2218_;
- wire _2219_;
- wire _2220_;
- wire _2221_;
- wire _2222_;
- wire _2223_;
- wire _2224_;
- wire _2225_;
- wire _2226_;
- wire _2227_;
- wire _2228_;
- wire _2229_;
- wire _2230_;
- wire _2231_;
- wire _2232_;
- wire _2233_;
- wire _2234_;
- wire _2235_;
- wire _2236_;
- wire _2237_;
- wire _2238_;
- wire _2239_;
- wire _2240_;
- wire _2241_;
- wire _2242_;
- wire _2243_;
- wire _2244_;
- wire _2245_;
- wire _2246_;
- wire _2247_;
- wire _2248_;
- wire _2249_;
- wire _2250_;
- wire _2251_;
- wire _2252_;
- wire _2253_;
- wire _2254_;
- wire _2255_;
- wire _2256_;
- wire _2257_;
- wire _2258_;
- wire _2259_;
- wire _2260_;
- wire _2261_;
- wire _2262_;
- wire _2263_;
- wire _2264_;
- wire _2265_;
- wire _2266_;
- wire _2267_;
- wire _2268_;
- wire _2269_;
- wire _2270_;
- wire _2271_;
- wire _2272_;
- wire _2273_;
- wire _2274_;
- wire _2275_;
- wire _2276_;
- wire _2277_;
- wire _2278_;
- wire _2279_;
- wire _2280_;
- wire [89:0] _2281_;
- wire [89:0] _2282_;
- wire [89:0] _2283_;
- wire [89:0] _2284_;
- wire [89:0] _2285_;
- wire [89:0] _2286_;
- wire [89:0] _2287_;
- wire [89:0] _2288_;
- wire [89:0] _2289_;
- wire [89:0] _2290_;
- wire [89:0] _2291_;
- wire [89:0] _2292_;
- wire [89:0] _2293_;
- wire [89:0] _2294_;
- wire [89:0] _2295_;
- wire [89:0] _2296_;
- wire [89:0] _2297_;
- wire [89:0] _2298_;
- wire [89:0] _2299_;
- wire [89:0] _2300_;
- wire [89:0] _2301_;
- wire [89:0] _2302_;
- wire [89:0] _2303_;
- wire [89:0] _2304_;
- wire [89:0] _2305_;
- wire [89:0] _2306_;
- wire [89:0] _2307_;
- wire [89:0] _2308_;
- wire [89:0] _2309_;
- wire [89:0] _2310_;
- wire [89:0] _2311_;
- wire [89:0] _2312_;
- wire [89:0] _2313_;
- wire [89:0] _2314_;
- wire [89:0] _2315_;
- wire [89:0] _2316_;
- wire [89:0] _2317_;
- wire [89:0] _2318_;
- wire [89:0] _2319_;
- wire [89:0] _2320_;
- wire [89:0] _2321_;
- wire [89:0] _2322_;
- wire [89:0] _2323_;
- wire _2324_;
- wire _2325_;
- wire _2326_;
- wire _2327_;
- wire _2328_;
- wire _2329_;
- wire _2330_;
- wire _2331_;
- wire _2332_;
- wire _2333_;
- wire _2334_;
- wire _2335_;
- wire _2336_;
- wire _2337_;
- wire _2338_;
- wire _2339_;
- wire _2340_;
- wire _2341_;
- wire _2342_;
- wire _2343_;
- wire _2344_;
- wire _2345_;
- wire _2346_;
- wire _2347_;
- wire _2348_;
- wire _2349_;
- wire _2350_;
- wire _2351_;
- wire _2352_;
- wire _2353_;
- wire _2354_;
- wire _2355_;
- wire _2356_;
- wire _2357_;
- wire _2358_;
- wire _2359_;
- wire _2360_;
- wire _2361_;
- wire _2362_;
- wire _2363_;
- wire _2364_;
- wire _2365_;
- wire _2366_;
- wire _2367_;
- wire _2368_;
- wire _2369_;
- wire _2370_;
- wire _2371_;
- wire _2372_;
- wire _2373_;
- wire _2374_;
- wire _2375_;
- wire _2376_;
- wire _2377_;
- wire _2378_;
- wire _2379_;
- wire _2380_;
- wire _2381_;
- wire _2382_;
- wire _2383_;
- wire _2384_;
- wire _2385_;
- wire _2386_;
- wire _2387_;
- wire _2388_;
- wire [89:0] _2389_;
- wire [89:0] _2390_;
- wire [89:0] _2391_;
- wire [89:0] _2392_;
- wire [89:0] _2393_;
- wire [89:0] _2394_;
- wire [89:0] _2395_;
- wire [89:0] _2396_;
- wire [89:0] _2397_;
- wire [89:0] _2398_;
- wire [89:0] _2399_;
- wire [89:0] _2400_;
- wire [89:0] _2401_;
- wire [89:0] _2402_;
- wire [89:0] _2403_;
- wire [89:0] _2404_;
- wire [89:0] _2405_;
- wire [89:0] _2406_;
- wire [89:0] _2407_;
- wire [89:0] _2408_;
- wire [89:0] _2409_;
- wire [89:0] _2410_;
- wire [89:0] _2411_;
- wire [89:0] _2412_;
- wire [89:0] _2413_;
- wire [89:0] _2414_;
- wire [89:0] _2415_;
- wire [89:0] _2416_;
- wire [89:0] _2417_;
- wire [89:0] _2418_;
- wire [89:0] _2419_;
- wire [89:0] _2420_;
- wire _2421_;
- wire _2422_;
- wire _2423_;
- wire _2424_;
- wire _2425_;
- wire _2426_;
- wire _2427_;
- wire _2428_;
- wire _2429_;
- wire _2430_;
- wire _2431_;
- wire _2432_;
- wire _2433_;
- wire _2434_;
- wire _2435_;
- wire _2436_;
- wire _2437_;
- wire _2438_;
- wire _2439_;
- wire _2440_;
- wire _2441_;
- wire _2442_;
- wire _2443_;
- wire _2444_;
- wire _2445_;
- wire _2446_;
- wire _2447_;
- wire _2448_;
- wire _2449_;
- wire _2450_;
- wire _2451_;
- wire _2452_;
- wire _2453_;
- wire _2454_;
- wire _2455_;
- wire _2456_;
- wire _2457_;
- wire _2458_;
- wire _2459_;
- wire _2460_;
- wire _2461_;
- wire _2462_;
- wire _2463_;
- wire _2464_;
- wire _2465_;
- wire _2466_;
- wire _2467_;
- wire _2468_;
- wire _2469_;
- wire _2470_;
- wire _2471_;
- wire _2472_;
- wire _2473_;
- wire _2474_;
- wire _2475_;
- wire _2476_;
- wire _2477_;
- wire _2478_;
- wire _2479_;
- wire _2480_;
- wire _2481_;
- wire _2482_;
- wire _2483_;
- wire _2484_;
- wire _2485_;
- wire _2486_;
- wire _2487_;
- wire _2488_;
- wire _2489_;
- wire _2490_;
- wire _2491_;
- wire _2492_;
- wire _2493_;
- wire _2494_;
- wire _2495_;
- wire _2496_;
- wire _2497_;
- wire _2498_;
- wire _2499_;
- wire _2500_;
- wire _2501_;
- wire _2502_;
- wire _2503_;
- wire _2504_;
- wire _2505_;
- wire _2506_;
- wire _2507_;
- wire _2508_;
- wire _2509_;
- wire _2510_;
- wire _2511_;
- wire _2512_;
- wire _2513_;
- wire _2514_;
- wire _2515_;
- wire _2516_;
- wire _2517_;
- wire _2518_;
- wire _2519_;
- wire _2520_;
- wire _2521_;
- wire _2522_;
- wire _2523_;
- wire _2524_;
- wire _2525_;
- wire _2526_;
- wire _2527_;
- wire _2528_;
- wire _2529_;
- wire _2530_;
- wire _2531_;
- wire _2532_;
- wire _2533_;
- wire _2534_;
- wire _2535_;
- wire _2536_;
- wire _2537_;
- wire _2538_;
- wire _2539_;
- wire _2540_;
- wire _2541_;
- wire _2542_;
- wire _2543_;
- wire _2544_;
- wire _2545_;
- wire _2546_;
- wire _2547_;
- wire _2548_;
- wire _2549_;
- wire _2550_;
- wire _2551_;
- wire _2552_;
- wire _2553_;
- wire _2554_;
- wire _2555_;
- wire _2556_;
- wire _2557_;
- wire _2558_;
- wire _2559_;
- wire _2560_;
- wire _2561_;
- wire _2562_;
- wire _2563_;
- wire _2564_;
- wire _2565_;
- wire _2566_;
- wire _2567_;
- wire _2568_;
- wire _2569_;
- wire _2570_;
- wire _2571_;
- wire _2572_;
- wire _2573_;
- wire _2574_;
- wire _2575_;
- wire _2576_;
- wire _2577_;
- wire _2578_;
- wire _2579_;
- wire _2580_;
- wire _2581_;
- wire _2582_;
- wire _2583_;
- wire _2584_;
- wire _2585_;
- wire _2586_;
- wire _2587_;
- wire _2588_;
- wire _2589_;
- wire _2590_;
- wire _2591_;
- wire _2592_;
- wire _2593_;
- wire _2594_;
- wire _2595_;
- wire _2596_;
- wire _2597_;
- wire _2598_;
- wire _2599_;
- wire _2600_;
- wire _2601_;
- wire _2602_;
- wire _2603_;
- wire _2604_;
- wire _2605_;
- wire _2606_;
- wire _2607_;
- wire _2608_;
- wire _2609_;
- wire _2610_;
- wire _2611_;
- wire _2612_;
- wire _2613_;
- wire _2614_;
- wire [1:0] _2615_;
- wire [1:0] _2616_;
- wire [1:0] _2617_;
- wire [1:0] _2618_;
- wire [1:0] _2619_;
- wire [1:0] _2620_;
- wire [1:0] _2621_;
- wire [1:0] _2622_;
- wire [1:0] _2623_;
- wire [1:0] _2624_;
- wire [1:0] _2625_;
- wire [1:0] _2626_;
- wire [1:0] _2627_;
- wire [1:0] _2628_;
- wire [1:0] _2629_;
- wire [1:0] _2630_;
- wire [1:0] _2631_;
- wire [1:0] _2632_;
- wire [1:0] _2633_;
- wire [1:0] _2634_;
- wire [1:0] _2635_;
- wire _2636_;
- wire _2637_;
- wire _2638_;
- wire _2639_;
- wire _2640_;
- wire _2641_;
- wire _2642_;
- wire _2643_;
- wire _2644_;
- wire _2645_;
- wire _2646_;
- wire _2647_;
- wire _2648_;
- wire _2649_;
- wire _2650_;
- wire _2651_;
- wire _2652_;
- wire _2653_;
- wire _2654_;
- wire _2655_;
- wire _2656_;
- wire _2657_;
- wire _2658_;
- wire _2659_;
- wire _2660_;
- wire _2661_;
- wire _2662_;
- wire _2663_;
- wire _2664_;
- wire _2665_;
- wire _2666_;
- wire [89:0] _2667_;
- wire [89:0] _2668_;
- wire [89:0] _2669_;
- wire [89:0] _2670_;
- wire [89:0] _2671_;
- wire [89:0] _2672_;
- wire [89:0] _2673_;
- wire [89:0] _2674_;
- wire [89:0] _2675_;
- wire [89:0] _2676_;
- wire _2677_;
- wire _2678_;
- wire _2679_;
- wire _2680_;
- wire _2681_;
- wire _2682_;
- wire _2683_;
- wire _2684_;
- wire _2685_;
- wire _2686_;
- wire [89:0] _2687_;
- wire [89:0] _2688_;
- wire [89:0] _2689_;
- wire [89:0] _2690_;
- wire [89:0] _2691_;
- wire [89:0] _2692_;
- wire [89:0] _2693_;
- wire [89:0] _2694_;
- wire [89:0] _2695_;
- wire [89:0] _2696_;
- wire _2697_;
- wire _2698_;
- wire _2699_;
- wire _2700_;
- wire _2701_;
- wire _2702_;
- wire _2703_;
- wire _2704_;
- wire _2705_;
- wire _2706_;
- wire [89:0] _2707_;
- wire [89:0] _2708_;
- wire [89:0] _2709_;
- wire [89:0] _2710_;
- wire [89:0] _2711_;
- wire [89:0] _2712_;
- wire [89:0] _2713_;
- wire [89:0] _2714_;
- wire [89:0] _2715_;
- wire [89:0] _2716_;
- wire _2717_;
- wire _2718_;
- wire _2719_;
- wire _2720_;
- wire _2721_;
- wire _2722_;
- wire _2723_;
- wire _2724_;
- wire _2725_;
- wire _2726_;
- wire [89:0] _2727_;
- wire [89:0] _2728_;
- wire [89:0] _2729_;
- wire [89:0] _2730_;
- wire [89:0] _2731_;
- wire [89:0] _2732_;
- wire [89:0] _2733_;
- wire [89:0] _2734_;
- wire [89:0] _2735_;
- wire [89:0] _2736_;
- wire _2737_;
- wire _2738_;
- wire _2739_;
- wire _2740_;
- wire _2741_;
- wire _2742_;
- wire _2743_;
- wire _2744_;
- wire _2745_;
- wire _2746_;
- wire [89:0] _2747_;
- wire [89:0] _2748_;
- wire [89:0] _2749_;
- wire [89:0] _2750_;
- wire [89:0] _2751_;
- wire [89:0] _2752_;
- wire [89:0] _2753_;
- wire [89:0] _2754_;
- wire [89:0] _2755_;
- wire [89:0] _2756_;
- wire _2757_;
- wire _2758_;
- wire _2759_;
- wire _2760_;
- wire _2761_;
- wire _2762_;
- wire _2763_;
- wire _2764_;
- wire _2765_;
- wire _2766_;
- wire [89:0] _2767_;
- wire [89:0] _2768_;
- wire [89:0] _2769_;
- wire [89:0] _2770_;
- wire [89:0] _2771_;
- wire [89:0] _2772_;
- wire [89:0] _2773_;
- wire [89:0] _2774_;
- wire [89:0] _2775_;
- wire [89:0] _2776_;
- wire _2777_;
- wire _2778_;
- wire _2779_;
- wire _2780_;
- wire _2781_;
- wire _2782_;
- wire _2783_;
- wire _2784_;
- wire _2785_;
- wire _2786_;
- wire [89:0] _2787_;
- wire [89:0] _2788_;
- wire [89:0] _2789_;
- wire [89:0] _2790_;
- wire [89:0] _2791_;
- wire [89:0] _2792_;
- wire [89:0] _2793_;
- wire [89:0] _2794_;
- wire [89:0] _2795_;
- wire [89:0] _2796_;
- wire [89:0] _2797_;
- wire [89:0] _2798_;
- wire [89:0] _2799_;
- wire [89:0] _2800_;
- wire [89:0] _2801_;
- wire [89:0] _2802_;
- wire [89:0] _2803_;
- wire [89:0] _2804_;
- wire [89:0] _2805_;
- wire [89:0] _2806_;
- wire [89:0] _2807_;
- wire [89:0] _2808_;
- wire [89:0] _2809_;
- wire [89:0] _2810_;
- wire [89:0] _2811_;
- wire [89:0] _2812_;
- wire [89:0] _2813_;
- wire [89:0] _2814_;
- wire [89:0] _2815_;
- wire [89:0] _2816_;
- wire [89:0] _2817_;
- wire [89:0] _2818_;
- wire [89:0] _2819_;
- wire [89:0] _2820_;
- wire [89:0] _2821_;
- wire [89:0] _2822_;
- wire [89:0] _2823_;
- wire [89:0] _2824_;
- wire [89:0] _2825_;
- wire [89:0] _2826_;
- wire [1:0] _2827_;
- wire [1:0] _2828_;
- wire [1:0] _2829_;
- wire [1:0] _2830_;
- wire [1:0] _2831_;
- wire [1:0] _2832_;
- wire [1:0] _2833_;
- wire [1:0] _2834_;
- wire [1:0] _2835_;
- wire [1:0] _2836_;
- wire [1:0] _2837_;
- wire [1:0] _2838_;
- wire [1:0] _2839_;
- wire [1:0] _2840_;
- wire [1:0] _2841_;
- wire [1:0] _2842_;
- wire [1:0] _2843_;
- wire [1:0] _2844_;
- wire [1:0] _2845_;
- wire [1:0] _2846_;
- wire [1:0] _2847_;
- wire _2848_;
- wire _2849_;
- wire _2850_;
- wire _2851_;
- wire _2852_;
- wire _2853_;
- wire _2854_;
- wire _2855_;
- wire _2856_;
- wire _2857_;
- wire _2858_;
- wire _2859_;
- wire _2860_;
- wire _2861_;
- wire _2862_;
- wire _2863_;
- wire _2864_;
- wire _2865_;
- wire _2866_;
- wire _2867_;
- wire _2868_;
- wire _2869_;
- wire _2870_;
- wire _2871_;
- wire _2872_;
- wire _2873_;
- wire _2874_;
- wire _2875_;
- wire _2876_;
- wire _2877_;
- wire _2878_;
- wire [89:0] _2879_;
- wire [89:0] _2880_;
- wire [89:0] _2881_;
- wire [89:0] _2882_;
- wire [89:0] _2883_;
- wire [89:0] _2884_;
- wire [89:0] _2885_;
- wire [89:0] _2886_;
- wire [89:0] _2887_;
- wire [89:0] _2888_;
- wire _2889_;
- wire _2890_;
- wire _2891_;
- wire _2892_;
- wire _2893_;
- wire _2894_;
- wire _2895_;
- wire _2896_;
- wire _2897_;
- wire _2898_;
- wire [89:0] _2899_;
- wire [89:0] _2900_;
- wire [89:0] _2901_;
- wire [89:0] _2902_;
- wire [89:0] _2903_;
- wire [89:0] _2904_;
- wire [89:0] _2905_;
- wire [89:0] _2906_;
- wire [89:0] _2907_;
- wire [89:0] _2908_;
- wire _2909_;
- wire _2910_;
- wire _2911_;
- wire _2912_;
- wire _2913_;
- wire _2914_;
- wire _2915_;
- wire _2916_;
- wire _2917_;
- wire _2918_;
- wire [89:0] _2919_;
- wire [89:0] _2920_;
- wire [89:0] _2921_;
- wire [89:0] _2922_;
- wire [89:0] _2923_;
- wire [89:0] _2924_;
- wire [89:0] _2925_;
- wire [89:0] _2926_;
- wire [89:0] _2927_;
- wire [89:0] _2928_;
- wire _2929_;
- wire _2930_;
- wire _2931_;
- wire _2932_;
- wire _2933_;
- wire _2934_;
- wire _2935_;
- wire _2936_;
- wire _2937_;
- wire _2938_;
- wire [89:0] _2939_;
- wire [89:0] _2940_;
- wire [89:0] _2941_;
- wire [89:0] _2942_;
- wire [89:0] _2943_;
- wire [89:0] _2944_;
- wire [89:0] _2945_;
- wire [89:0] _2946_;
- wire [89:0] _2947_;
- wire [89:0] _2948_;
- wire _2949_;
- wire _2950_;
- wire _2951_;
- wire _2952_;
- wire _2953_;
- wire _2954_;
- wire _2955_;
- wire _2956_;
- wire _2957_;
- wire _2958_;
- wire [89:0] _2959_;
- wire [89:0] _2960_;
- wire [89:0] _2961_;
- wire [89:0] _2962_;
- wire [89:0] _2963_;
- wire [89:0] _2964_;
- wire [89:0] _2965_;
- wire [89:0] _2966_;
- wire [89:0] _2967_;
- wire [89:0] _2968_;
- wire _2969_;
- wire _2970_;
- wire _2971_;
- wire _2972_;
- wire _2973_;
- wire _2974_;
- wire _2975_;
- wire _2976_;
- wire _2977_;
- wire _2978_;
- wire [89:0] _2979_;
- wire [89:0] _2980_;
- wire [89:0] _2981_;
- wire [89:0] _2982_;
- wire [89:0] _2983_;
- wire [89:0] _2984_;
- wire [89:0] _2985_;
- wire [89:0] _2986_;
- wire [89:0] _2987_;
- wire [89:0] _2988_;
- wire _2989_;
- wire _2990_;
- wire _2991_;
- wire _2992_;
- wire _2993_;
- wire _2994_;
- wire _2995_;
- wire _2996_;
- wire _2997_;
- wire _2998_;
- wire [89:0] _2999_;
- wire [89:0] _3000_;
- wire [89:0] _3001_;
- wire [89:0] _3002_;
- wire [89:0] _3003_;
- wire [89:0] _3004_;
- wire [89:0] _3005_;
- wire [89:0] _3006_;
- wire [89:0] _3007_;
- wire [89:0] _3008_;
- wire [89:0] _3009_;
- wire [89:0] _3010_;
- wire [89:0] _3011_;
- wire [89:0] _3012_;
- wire [89:0] _3013_;
- wire [89:0] _3014_;
- wire [89:0] _3015_;
- wire [89:0] _3016_;
- wire [89:0] _3017_;
- wire [89:0] _3018_;
- wire [89:0] _3019_;
- wire [89:0] _3020_;
- wire [89:0] _3021_;
- wire [89:0] _3022_;
- wire [89:0] _3023_;
- wire [89:0] _3024_;
- wire [89:0] _3025_;
- wire [89:0] _3026_;
- wire [89:0] _3027_;
- wire [89:0] _3028_;
- wire [89:0] _3029_;
- wire [89:0] _3030_;
- wire [89:0] _3031_;
- wire [89:0] _3032_;
- wire [89:0] _3033_;
- wire [89:0] _3034_;
- wire [89:0] _3035_;
- wire [89:0] _3036_;
- wire [89:0] _3037_;
- wire [89:0] _3038_;
- reg [2879:0] cache_tags;
- reg [63:0] cache_valids;
- wire cancel_store;
- wire clear_rsrv;
- input clk;
- input [142:0] d_in;
- output [67:0] d_out;
- reg [127:0] dtlb_valids;
- wire [7:0] early_req_row;
- input [131:0] m_in;
- output [66:0] m_out;
- wire \maybe_plrus.plrus%0.plru_acc_en ;
- wire \maybe_plrus.plrus%0.plru_out ;
- wire \maybe_plrus.plrus%1.plru_acc_en ;
- wire \maybe_plrus.plrus%1.plru_out ;
- wire \maybe_plrus.plrus%10.plru_acc_en ;
- wire \maybe_plrus.plrus%10.plru_out ;
- wire \maybe_plrus.plrus%11.plru_acc_en ;
- wire \maybe_plrus.plrus%11.plru_out ;
- wire \maybe_plrus.plrus%12.plru_acc_en ;
- wire \maybe_plrus.plrus%12.plru_out ;
- wire \maybe_plrus.plrus%13.plru_acc_en ;
- wire \maybe_plrus.plrus%13.plru_out ;
- wire \maybe_plrus.plrus%14.plru_acc_en ;
- wire \maybe_plrus.plrus%14.plru_out ;
- wire \maybe_plrus.plrus%15.plru_acc_en ;
- wire \maybe_plrus.plrus%15.plru_out ;
- wire \maybe_plrus.plrus%16.plru_acc_en ;
- wire \maybe_plrus.plrus%16.plru_out ;
- wire \maybe_plrus.plrus%17.plru_acc_en ;
- wire \maybe_plrus.plrus%17.plru_out ;
- wire \maybe_plrus.plrus%18.plru_acc_en ;
- wire \maybe_plrus.plrus%18.plru_out ;
- wire \maybe_plrus.plrus%19.plru_acc_en ;
- wire \maybe_plrus.plrus%19.plru_out ;
- wire \maybe_plrus.plrus%2.plru_acc_en ;
- wire \maybe_plrus.plrus%2.plru_out ;
- wire \maybe_plrus.plrus%20.plru_acc_en ;
- wire \maybe_plrus.plrus%20.plru_out ;
- wire \maybe_plrus.plrus%21.plru_acc_en ;
- wire \maybe_plrus.plrus%21.plru_out ;
- wire \maybe_plrus.plrus%22.plru_acc_en ;
- wire \maybe_plrus.plrus%22.plru_out ;
- wire \maybe_plrus.plrus%23.plru_acc_en ;
- wire \maybe_plrus.plrus%23.plru_out ;
- wire \maybe_plrus.plrus%24.plru_acc_en ;
- wire \maybe_plrus.plrus%24.plru_out ;
- wire \maybe_plrus.plrus%25.plru_acc_en ;
- wire \maybe_plrus.plrus%25.plru_out ;
- wire \maybe_plrus.plrus%26.plru_acc_en ;
- wire \maybe_plrus.plrus%26.plru_out ;
- wire \maybe_plrus.plrus%27.plru_acc_en ;
- wire \maybe_plrus.plrus%27.plru_out ;
- wire \maybe_plrus.plrus%28.plru_acc_en ;
- wire \maybe_plrus.plrus%28.plru_out ;
- wire \maybe_plrus.plrus%29.plru_acc_en ;
- wire \maybe_plrus.plrus%29.plru_out ;
- wire \maybe_plrus.plrus%3.plru_acc_en ;
- wire \maybe_plrus.plrus%3.plru_out ;
- wire \maybe_plrus.plrus%30.plru_acc_en ;
- wire \maybe_plrus.plrus%30.plru_out ;
- wire \maybe_plrus.plrus%31.plru_acc_en ;
- wire \maybe_plrus.plrus%31.plru_out ;
- wire \maybe_plrus.plrus%4.plru_acc_en ;
- wire \maybe_plrus.plrus%4.plru_out ;
- wire \maybe_plrus.plrus%5.plru_acc_en ;
- wire \maybe_plrus.plrus%5.plru_out ;
- wire \maybe_plrus.plrus%6.plru_acc_en ;
- wire \maybe_plrus.plrus%6.plru_out ;
- wire \maybe_plrus.plrus%7.plru_acc_en ;
- wire \maybe_plrus.plrus%7.plru_out ;
- wire \maybe_plrus.plrus%8.plru_acc_en ;
- wire \maybe_plrus.plrus%8.plru_out ;
- wire \maybe_plrus.plrus%9.plru_acc_en ;
- wire \maybe_plrus.plrus%9.plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out ;
- wire \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en ;
- wire \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ;
- wire [5:0] perm_attr;
- wire perm_ok;
- wire [63:0] pte;
- reg [146:0] r0;
- wire r0_valid;
- wire [55:0] ra;
- wire \rams%0.do_write ;
- wire [63:0] \rams%0.dout ;
- wire [7:0] \rams%0.wr_addr ;
- wire [63:0] \rams%0.wr_data ;
- wire [7:0] \rams%0.wr_sel ;
- wire \rams%1.do_write ;
- wire [63:0] \rams%1.dout ;
- wire [7:0] \rams%1.wr_addr ;
- wire [63:0] \rams%1.wr_data ;
- wire [7:0] \rams%1.wr_sel ;
- wire rc_ok;
- wire replace_way;
- wire req_hit_way;
- wire [2:0] req_op;
- reg [58:0] reservation;
- input rst;
- wire set_rsrv;
- output stall_out;
- wire tlb_hit;
- wire tlb_hit_way;
- wire [127:0] tlb_pte_way;
- wire [91:0] tlb_tag_way;
- reg [1:0] tlb_valid_way;
- wire valid_ra;
- input [65:0] wishbone_in;
- output [106:0] wishbone_out;
- reg [91:0] \$mem$\13892 [63:0];
- reg [127:0] \$mem$\13896 [63:0];
- assign _2615_ = _0019_[0] ? dtlb_valids[3:2] : dtlb_valids[1:0];
- assign _2616_ = _0019_[0] ? dtlb_valids[11:10] : dtlb_valids[9:8];
- assign _2617_ = _0019_[0] ? dtlb_valids[19:18] : dtlb_valids[17:16];
- assign _2618_ = _0019_[0] ? dtlb_valids[27:26] : dtlb_valids[25:24];
- assign _2619_ = _0019_[0] ? dtlb_valids[35:34] : dtlb_valids[33:32];
- assign _2620_ = _0019_[0] ? dtlb_valids[43:42] : dtlb_valids[41:40];
- assign _2621_ = _0019_[0] ? dtlb_valids[51:50] : dtlb_valids[49:48];
- assign _2622_ = _0019_[0] ? dtlb_valids[59:58] : dtlb_valids[57:56];
- assign _2623_ = _0019_[0] ? dtlb_valids[67:66] : dtlb_valids[65:64];
- assign _2624_ = _0019_[0] ? dtlb_valids[75:74] : dtlb_valids[73:72];
- assign _2625_ = _0019_[0] ? dtlb_valids[83:82] : dtlb_valids[81:80];
- assign _2626_ = _0019_[0] ? dtlb_valids[91:90] : dtlb_valids[89:88];
- assign _2627_ = _0019_[0] ? dtlb_valids[99:98] : dtlb_valids[97:96];
- assign _2628_ = _0019_[0] ? dtlb_valids[107:106] : dtlb_valids[105:104];
- assign _2629_ = _0019_[0] ? dtlb_valids[115:114] : dtlb_valids[113:112];
- assign _2630_ = _0019_[0] ? dtlb_valids[123:122] : dtlb_valids[121:120];
- assign _2631_ = _0019_[2] ? _0633_ : _0632_;
- assign _2632_ = _0019_[2] ? _0637_ : _0636_;
- assign _2633_ = _0019_[2] ? _0641_ : _0640_;
- assign _2634_ = _0019_[2] ? _0645_ : _0644_;
- assign _2635_ = _0019_[4] ? _0649_ : _0648_;
- assign _2636_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ;
- assign _2637_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ;
- assign _2638_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ;
- assign _2639_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ;
- assign _2640_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ;
- assign _2641_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ;
- assign _2642_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ;
- assign _2643_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ;
- assign _2644_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ;
- assign _2645_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ;
- assign _2646_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ;
- assign _2647_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ;
- assign _2648_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ;
- assign _2649_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ;
- assign _2650_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ;
- assign _2651_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ;
- assign _2652_ = _0161_[2] ? _1042_ : _1041_;
- assign _2653_ = _0161_[2] ? _1046_ : _1045_;
- assign _2654_ = _0161_[2] ? _1050_ : _1049_;
- assign _2655_ = _0161_[2] ? _1054_ : _1053_;
- assign _2656_ = _0161_[4] ? _1058_ : _1057_;
- assign _2657_ = _0338_[0] ? cache_valids[2] : cache_valids[0];
- assign _2658_ = _0338_[0] ? cache_valids[10] : cache_valids[8];
- assign _2659_ = _0338_[0] ? cache_valids[18] : cache_valids[16];
- assign _2660_ = _0338_[0] ? cache_valids[26] : cache_valids[24];
- assign _2661_ = _0338_[0] ? cache_valids[34] : cache_valids[32];
- assign _2662_ = _0338_[0] ? cache_valids[42] : cache_valids[40];
- assign _2663_ = _0338_[0] ? cache_valids[50] : cache_valids[48];
- assign _2664_ = _0338_[0] ? cache_valids[58] : cache_valids[56];
- assign _2665_ = _0338_[2] ? _1456_ : _1455_;
- assign _2666_ = _0338_[2] ? _1460_ : _1459_;
- assign _2667_ = _0340_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2668_ = _0340_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2669_ = _0340_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2670_ = _0340_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2671_ = _0340_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2672_ = _0340_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2673_ = _0340_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2674_ = _0340_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2675_ = _0340_[2] ? _1467_ : _1466_;
- assign _2676_ = _0340_[2] ? _1471_ : _1470_;
- assign _2677_ = _0346_[0] ? cache_valids[3] : cache_valids[1];
- assign _2678_ = _0346_[0] ? cache_valids[11] : cache_valids[9];
- assign _2679_ = _0346_[0] ? cache_valids[19] : cache_valids[17];
- assign _2680_ = _0346_[0] ? cache_valids[27] : cache_valids[25];
- assign _2681_ = _0346_[0] ? cache_valids[35] : cache_valids[33];
- assign _2682_ = _0346_[0] ? cache_valids[43] : cache_valids[41];
- assign _2683_ = _0346_[0] ? cache_valids[51] : cache_valids[49];
- assign _2684_ = _0346_[0] ? cache_valids[59] : cache_valids[57];
- assign _2685_ = _0346_[2] ? _1478_ : _1477_;
- assign _2686_ = _0346_[2] ? _1482_ : _1481_;
- assign _2687_ = _0348_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2688_ = _0348_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2689_ = _0348_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2690_ = _0348_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2691_ = _0348_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2692_ = _0348_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2693_ = _0348_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2694_ = _0348_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2695_ = _0348_[2] ? _1489_ : _1488_;
- assign _2696_ = _0348_[2] ? _1493_ : _1492_;
- assign _2697_ = _0354_[0] ? cache_valids[2] : cache_valids[0];
- assign _2698_ = _0354_[0] ? cache_valids[10] : cache_valids[8];
- assign _2699_ = _0354_[0] ? cache_valids[18] : cache_valids[16];
- assign _2700_ = _0354_[0] ? cache_valids[26] : cache_valids[24];
- assign _2701_ = _0354_[0] ? cache_valids[34] : cache_valids[32];
- assign _2702_ = _0354_[0] ? cache_valids[42] : cache_valids[40];
- assign _2703_ = _0354_[0] ? cache_valids[50] : cache_valids[48];
- assign _2704_ = _0354_[0] ? cache_valids[58] : cache_valids[56];
- assign _2705_ = _0354_[2] ? _1500_ : _1499_;
- assign _2706_ = _0354_[2] ? _1504_ : _1503_;
- assign _2707_ = _0356_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2708_ = _0356_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2709_ = _0356_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2710_ = _0356_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2711_ = _0356_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2712_ = _0356_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2713_ = _0356_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2714_ = _0356_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2715_ = _0356_[2] ? _1511_ : _1510_;
- assign _2716_ = _0356_[2] ? _1515_ : _1514_;
- assign _2717_ = _0362_[0] ? cache_valids[3] : cache_valids[1];
- assign _2718_ = _0362_[0] ? cache_valids[11] : cache_valids[9];
- assign _2719_ = _0362_[0] ? cache_valids[19] : cache_valids[17];
- assign _2720_ = _0362_[0] ? cache_valids[27] : cache_valids[25];
- assign _2721_ = _0362_[0] ? cache_valids[35] : cache_valids[33];
- assign _2722_ = _0362_[0] ? cache_valids[43] : cache_valids[41];
- assign _2723_ = _0362_[0] ? cache_valids[51] : cache_valids[49];
- assign _2724_ = _0362_[0] ? cache_valids[59] : cache_valids[57];
- assign _2725_ = _0362_[2] ? _1522_ : _1521_;
- assign _2726_ = _0362_[2] ? _1526_ : _1525_;
- assign _2727_ = _0364_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2728_ = _0364_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2729_ = _0364_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2730_ = _0364_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2731_ = _0364_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2732_ = _0364_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2733_ = _0364_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2734_ = _0364_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2735_ = _0364_[2] ? _1533_ : _1532_;
- assign _2736_ = _0364_[2] ? _1537_ : _1536_;
- assign _2737_ = _0373_[0] ? cache_valids[2] : cache_valids[0];
- assign _2738_ = _0373_[0] ? cache_valids[10] : cache_valids[8];
- assign _2739_ = _0373_[0] ? cache_valids[18] : cache_valids[16];
- assign _2740_ = _0373_[0] ? cache_valids[26] : cache_valids[24];
- assign _2741_ = _0373_[0] ? cache_valids[34] : cache_valids[32];
- assign _2742_ = _0373_[0] ? cache_valids[42] : cache_valids[40];
- assign _2743_ = _0373_[0] ? cache_valids[50] : cache_valids[48];
- assign _2744_ = _0373_[0] ? cache_valids[58] : cache_valids[56];
- assign _2745_ = _0373_[2] ? _1546_ : _1545_;
- assign _2746_ = _0373_[2] ? _1550_ : _1549_;
- assign _2747_ = _0375_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2748_ = _0375_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2749_ = _0375_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2750_ = _0375_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2751_ = _0375_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2752_ = _0375_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2753_ = _0375_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2754_ = _0375_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2755_ = _0375_[2] ? _1557_ : _1556_;
- assign _2756_ = _0375_[2] ? _1561_ : _1560_;
- assign _2757_ = _0379_[0] ? cache_valids[3] : cache_valids[1];
- assign _2758_ = _0379_[0] ? cache_valids[11] : cache_valids[9];
- assign _2759_ = _0379_[0] ? cache_valids[19] : cache_valids[17];
- assign _2760_ = _0379_[0] ? cache_valids[27] : cache_valids[25];
- assign _2761_ = _0379_[0] ? cache_valids[35] : cache_valids[33];
- assign _2762_ = _0379_[0] ? cache_valids[43] : cache_valids[41];
- assign _2763_ = _0379_[0] ? cache_valids[51] : cache_valids[49];
- assign _2764_ = _0379_[0] ? cache_valids[59] : cache_valids[57];
- assign _2765_ = _0379_[2] ? _1568_ : _1567_;
- assign _2766_ = _0379_[2] ? _1572_ : _1571_;
- assign _2767_ = _0381_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2768_ = _0381_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2769_ = _0381_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2770_ = _0381_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2771_ = _0381_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2772_ = _0381_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2773_ = _0381_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2774_ = _0381_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2775_ = _0381_[2] ? _1579_ : _1578_;
- assign _2776_ = _0381_[2] ? _1583_ : _1582_;
- assign _2777_ = _0387_[0] ? \maybe_plrus.plrus%30.plru_out : \maybe_plrus.plrus%31.plru_out ;
- assign _2778_ = _0387_[0] ? \maybe_plrus.plrus%26.plru_out : \maybe_plrus.plrus%27.plru_out ;
- assign _2779_ = _0387_[0] ? \maybe_plrus.plrus%22.plru_out : \maybe_plrus.plrus%23.plru_out ;
- assign _2780_ = _0387_[0] ? \maybe_plrus.plrus%18.plru_out : \maybe_plrus.plrus%19.plru_out ;
- assign _2781_ = _0387_[0] ? \maybe_plrus.plrus%14.plru_out : \maybe_plrus.plrus%15.plru_out ;
- assign _2782_ = _0387_[0] ? \maybe_plrus.plrus%10.plru_out : \maybe_plrus.plrus%11.plru_out ;
- assign _2783_ = _0387_[0] ? \maybe_plrus.plrus%6.plru_out : \maybe_plrus.plrus%7.plru_out ;
- assign _2784_ = _0387_[0] ? \maybe_plrus.plrus%2.plru_out : \maybe_plrus.plrus%3.plru_out ;
- assign _2785_ = _0387_[2] ? _1590_ : _1589_;
- assign _2786_ = _0387_[2] ? _1594_ : _1593_;
- assign _2787_ = _0513_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2788_ = _0513_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2789_ = _0513_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2790_ = _0513_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2791_ = _0513_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2792_ = _0513_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2793_ = _0513_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2794_ = _0513_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2795_ = _0513_[2] ? _1796_ : _1795_;
- assign _2796_ = _0513_[2] ? _1800_ : _1799_;
- assign _2797_ = _0517_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2798_ = _0517_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2799_ = _0517_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2800_ = _0517_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2801_ = _0517_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2802_ = _0517_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2803_ = _0517_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2804_ = _0517_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2805_ = _0517_[2] ? _1904_ : _1903_;
- assign _2806_ = _0517_[2] ? _1908_ : _1907_;
- assign _2807_ = _0531_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2808_ = _0531_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2809_ = _0531_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2810_ = _0531_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2811_ = _0531_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2812_ = _0531_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2813_ = _0531_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2814_ = _0531_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2815_ = _0531_[2] ? _2206_ : _2205_;
- assign _2816_ = _0531_[2] ? _2210_ : _2209_;
- assign _2817_ = _0535_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _2818_ = _0535_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _2819_ = _0535_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _2820_ = _0535_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _2821_ = _0535_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _2822_ = _0535_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _2823_ = _0535_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _2824_ = _0535_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _2825_ = _0535_[2] ? _2314_ : _2313_;
- assign _2826_ = _0535_[2] ? _2318_ : _2317_;
- assign _2827_ = _0019_[0] ? dtlb_valids[7:6] : dtlb_valids[5:4];
- assign _2828_ = _0019_[0] ? dtlb_valids[15:14] : dtlb_valids[13:12];
- assign _2829_ = _0019_[0] ? dtlb_valids[23:22] : dtlb_valids[21:20];
- assign _2830_ = _0019_[0] ? dtlb_valids[31:30] : dtlb_valids[29:28];
- assign _2831_ = _0019_[0] ? dtlb_valids[39:38] : dtlb_valids[37:36];
- assign _2832_ = _0019_[0] ? dtlb_valids[47:46] : dtlb_valids[45:44];
- assign _2833_ = _0019_[0] ? dtlb_valids[55:54] : dtlb_valids[53:52];
- assign _2834_ = _0019_[0] ? dtlb_valids[63:62] : dtlb_valids[61:60];
- assign _2835_ = _0019_[0] ? dtlb_valids[71:70] : dtlb_valids[69:68];
- assign _2836_ = _0019_[0] ? dtlb_valids[79:78] : dtlb_valids[77:76];
- assign _2837_ = _0019_[0] ? dtlb_valids[87:86] : dtlb_valids[85:84];
- assign _2838_ = _0019_[0] ? dtlb_valids[95:94] : dtlb_valids[93:92];
- assign _2839_ = _0019_[0] ? dtlb_valids[103:102] : dtlb_valids[101:100];
- assign _2840_ = _0019_[0] ? dtlb_valids[111:110] : dtlb_valids[109:108];
- assign _2841_ = _0019_[0] ? dtlb_valids[119:118] : dtlb_valids[117:116];
- assign _2842_ = _0019_[0] ? dtlb_valids[127:126] : dtlb_valids[125:124];
- assign _2843_ = _0019_[2] ? _0635_ : _0634_;
- assign _2844_ = _0019_[2] ? _0639_ : _0638_;
- assign _2845_ = _0019_[2] ? _0643_ : _0642_;
- assign _2846_ = _0019_[2] ? _0647_ : _0646_;
- assign _2847_ = _0019_[4] ? _0651_ : _0650_;
- assign _2848_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ;
- assign _2849_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ;
- assign _2850_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ;
- assign _2851_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ;
- assign _2852_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ;
- assign _2853_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ;
- assign _2854_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ;
- assign _2855_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ;
- assign _2856_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ;
- assign _2857_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ;
- assign _2858_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ;
- assign _2859_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ;
- assign _2860_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ;
- assign _2861_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ;
- assign _2862_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ;
- assign _2863_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ;
- assign _2864_ = _0161_[2] ? _1044_ : _1043_;
- assign _2865_ = _0161_[2] ? _1048_ : _1047_;
- assign _2866_ = _0161_[2] ? _1052_ : _1051_;
- assign _2867_ = _0161_[2] ? _1056_ : _1055_;
- assign _2868_ = _0161_[4] ? _1060_ : _1059_;
- assign _2869_ = _0338_[0] ? cache_valids[6] : cache_valids[4];
- assign _2870_ = _0338_[0] ? cache_valids[14] : cache_valids[12];
- assign _2871_ = _0338_[0] ? cache_valids[22] : cache_valids[20];
- assign _2872_ = _0338_[0] ? cache_valids[30] : cache_valids[28];
- assign _2873_ = _0338_[0] ? cache_valids[38] : cache_valids[36];
- assign _2874_ = _0338_[0] ? cache_valids[46] : cache_valids[44];
- assign _2875_ = _0338_[0] ? cache_valids[54] : cache_valids[52];
- assign _2876_ = _0338_[0] ? cache_valids[62] : cache_valids[60];
- assign _2877_ = _0338_[2] ? _1458_ : _1457_;
- assign _2878_ = _0338_[2] ? _1462_ : _1461_;
- assign _2879_ = _0340_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2880_ = _0340_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2881_ = _0340_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2882_ = _0340_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2883_ = _0340_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2884_ = _0340_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2885_ = _0340_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2886_ = _0340_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2887_ = _0340_[2] ? _1469_ : _1468_;
- assign _2888_ = _0340_[2] ? _1473_ : _1472_;
- assign _2889_ = _0346_[0] ? cache_valids[7] : cache_valids[5];
- assign _2890_ = _0346_[0] ? cache_valids[15] : cache_valids[13];
- assign _2891_ = _0346_[0] ? cache_valids[23] : cache_valids[21];
- assign _2892_ = _0346_[0] ? cache_valids[31] : cache_valids[29];
- assign _2893_ = _0346_[0] ? cache_valids[39] : cache_valids[37];
- assign _2894_ = _0346_[0] ? cache_valids[47] : cache_valids[45];
- assign _2895_ = _0346_[0] ? cache_valids[55] : cache_valids[53];
- assign _2896_ = _0346_[0] ? cache_valids[63] : cache_valids[61];
- assign _2897_ = _0346_[2] ? _1480_ : _1479_;
- assign _2898_ = _0346_[2] ? _1484_ : _1483_;
- assign _2899_ = _0348_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2900_ = _0348_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2901_ = _0348_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2902_ = _0348_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2903_ = _0348_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2904_ = _0348_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2905_ = _0348_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2906_ = _0348_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2907_ = _0348_[2] ? _1491_ : _1490_;
- assign _2908_ = _0348_[2] ? _1495_ : _1494_;
- assign _2909_ = _0354_[0] ? cache_valids[6] : cache_valids[4];
- assign _2910_ = _0354_[0] ? cache_valids[14] : cache_valids[12];
- assign _2911_ = _0354_[0] ? cache_valids[22] : cache_valids[20];
- assign _2912_ = _0354_[0] ? cache_valids[30] : cache_valids[28];
- assign _2913_ = _0354_[0] ? cache_valids[38] : cache_valids[36];
- assign _2914_ = _0354_[0] ? cache_valids[46] : cache_valids[44];
- assign _2915_ = _0354_[0] ? cache_valids[54] : cache_valids[52];
- assign _2916_ = _0354_[0] ? cache_valids[62] : cache_valids[60];
- assign _2917_ = _0354_[2] ? _1502_ : _1501_;
- assign _2918_ = _0354_[2] ? _1506_ : _1505_;
- assign _2919_ = _0356_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2920_ = _0356_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2921_ = _0356_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2922_ = _0356_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2923_ = _0356_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2924_ = _0356_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2925_ = _0356_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2926_ = _0356_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2927_ = _0356_[2] ? _1513_ : _1512_;
- assign _2928_ = _0356_[2] ? _1517_ : _1516_;
- assign _2929_ = _0362_[0] ? cache_valids[7] : cache_valids[5];
- assign _2930_ = _0362_[0] ? cache_valids[15] : cache_valids[13];
- assign _2931_ = _0362_[0] ? cache_valids[23] : cache_valids[21];
- assign _2932_ = _0362_[0] ? cache_valids[31] : cache_valids[29];
- assign _2933_ = _0362_[0] ? cache_valids[39] : cache_valids[37];
- assign _2934_ = _0362_[0] ? cache_valids[47] : cache_valids[45];
- assign _2935_ = _0362_[0] ? cache_valids[55] : cache_valids[53];
- assign _2936_ = _0362_[0] ? cache_valids[63] : cache_valids[61];
- assign _2937_ = _0362_[2] ? _1524_ : _1523_;
- assign _2938_ = _0362_[2] ? _1528_ : _1527_;
- assign _2939_ = _0364_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2940_ = _0364_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2941_ = _0364_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2942_ = _0364_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2943_ = _0364_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2944_ = _0364_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2945_ = _0364_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2946_ = _0364_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2947_ = _0364_[2] ? _1535_ : _1534_;
- assign _2948_ = _0364_[2] ? _1539_ : _1538_;
- assign _2949_ = _0373_[0] ? cache_valids[6] : cache_valids[4];
- assign _2950_ = _0373_[0] ? cache_valids[14] : cache_valids[12];
- assign _2951_ = _0373_[0] ? cache_valids[22] : cache_valids[20];
- assign _2952_ = _0373_[0] ? cache_valids[30] : cache_valids[28];
- assign _2953_ = _0373_[0] ? cache_valids[38] : cache_valids[36];
- assign _2954_ = _0373_[0] ? cache_valids[46] : cache_valids[44];
- assign _2955_ = _0373_[0] ? cache_valids[54] : cache_valids[52];
- assign _2956_ = _0373_[0] ? cache_valids[62] : cache_valids[60];
- assign _2957_ = _0373_[2] ? _1548_ : _1547_;
- assign _2958_ = _0373_[2] ? _1552_ : _1551_;
- assign _2959_ = _0375_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2960_ = _0375_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2961_ = _0375_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2962_ = _0375_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2963_ = _0375_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2964_ = _0375_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2965_ = _0375_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2966_ = _0375_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2967_ = _0375_[2] ? _1559_ : _1558_;
- assign _2968_ = _0375_[2] ? _1563_ : _1562_;
- assign _2969_ = _0379_[0] ? cache_valids[7] : cache_valids[5];
- assign _2970_ = _0379_[0] ? cache_valids[15] : cache_valids[13];
- assign _2971_ = _0379_[0] ? cache_valids[23] : cache_valids[21];
- assign _2972_ = _0379_[0] ? cache_valids[31] : cache_valids[29];
- assign _2973_ = _0379_[0] ? cache_valids[39] : cache_valids[37];
- assign _2974_ = _0379_[0] ? cache_valids[47] : cache_valids[45];
- assign _2975_ = _0379_[0] ? cache_valids[55] : cache_valids[53];
- assign _2976_ = _0379_[0] ? cache_valids[63] : cache_valids[61];
- assign _2977_ = _0379_[2] ? _1570_ : _1569_;
- assign _2978_ = _0379_[2] ? _1574_ : _1573_;
- assign _2979_ = _0381_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _2980_ = _0381_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _2981_ = _0381_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _2982_ = _0381_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _2983_ = _0381_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _2984_ = _0381_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _2985_ = _0381_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _2986_ = _0381_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _2987_ = _0381_[2] ? _1581_ : _1580_;
- assign _2988_ = _0381_[2] ? _1585_ : _1584_;
- assign _2989_ = _0387_[0] ? \maybe_plrus.plrus%28.plru_out : \maybe_plrus.plrus%29.plru_out ;
- assign _2990_ = _0387_[0] ? \maybe_plrus.plrus%24.plru_out : \maybe_plrus.plrus%25.plru_out ;
- assign _2991_ = _0387_[0] ? \maybe_plrus.plrus%20.plru_out : \maybe_plrus.plrus%21.plru_out ;
- assign _2992_ = _0387_[0] ? \maybe_plrus.plrus%16.plru_out : \maybe_plrus.plrus%17.plru_out ;
- assign _2993_ = _0387_[0] ? \maybe_plrus.plrus%12.plru_out : \maybe_plrus.plrus%13.plru_out ;
- assign _2994_ = _0387_[0] ? \maybe_plrus.plrus%8.plru_out : \maybe_plrus.plrus%9.plru_out ;
- assign _2995_ = _0387_[0] ? \maybe_plrus.plrus%4.plru_out : \maybe_plrus.plrus%5.plru_out ;
- assign _2996_ = _0387_[0] ? \maybe_plrus.plrus%0.plru_out : \maybe_plrus.plrus%1.plru_out ;
- assign _2997_ = _0387_[2] ? _1592_ : _1591_;
- assign _2998_ = _0387_[2] ? _1596_ : _1595_;
- assign _2999_ = _0513_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _3000_ = _0513_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _3001_ = _0513_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _3002_ = _0513_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _3003_ = _0513_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _3004_ = _0513_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _3005_ = _0513_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _3006_ = _0513_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _3007_ = _0513_[2] ? _1798_ : _1797_;
- assign _3008_ = _0513_[2] ? _1802_ : _1801_;
- assign _3009_ = _0517_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _3010_ = _0517_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _3011_ = _0517_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _3012_ = _0517_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _3013_ = _0517_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _3014_ = _0517_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _3015_ = _0517_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _3016_ = _0517_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _3017_ = _0517_[2] ? _1906_ : _1905_;
- assign _3018_ = _0517_[2] ? _1910_ : _1909_;
- assign _3019_ = _0531_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _3020_ = _0531_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _3021_ = _0531_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _3022_ = _0531_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _3023_ = _0531_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _3024_ = _0531_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _3025_ = _0531_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _3026_ = _0531_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _3027_ = _0531_[2] ? _2208_ : _2207_;
- assign _3028_ = _0531_[2] ? _2212_ : _2211_;
- assign _3029_ = _0535_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _3030_ = _0535_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _3031_ = _0535_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _3032_ = _0535_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _3033_ = _0535_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _3034_ = _0535_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _3035_ = _0535_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _3036_ = _0535_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _3037_ = _0535_[2] ? _2316_ : _2315_;
- assign _3038_ = _0535_[2] ? _2320_ : _2319_;
- assign _0632_ = _0019_[1] ? _2827_ : _2615_;
- assign _0633_ = _0019_[1] ? _2828_ : _2616_;
- assign _0634_ = _0019_[1] ? _2829_ : _2617_;
- assign _0635_ = _0019_[1] ? _2830_ : _2618_;
- assign _0636_ = _0019_[1] ? _2831_ : _2619_;
- assign _0637_ = _0019_[1] ? _2832_ : _2620_;
- assign _0638_ = _0019_[1] ? _2833_ : _2621_;
- assign _0639_ = _0019_[1] ? _2834_ : _2622_;
- assign _0640_ = _0019_[1] ? _2835_ : _2623_;
- assign _0641_ = _0019_[1] ? _2836_ : _2624_;
- assign _0642_ = _0019_[1] ? _2837_ : _2625_;
- assign _0643_ = _0019_[1] ? _2838_ : _2626_;
- assign _0644_ = _0019_[1] ? _2839_ : _2627_;
- assign _0645_ = _0019_[1] ? _2840_ : _2628_;
- assign _0646_ = _0019_[1] ? _2841_ : _2629_;
- assign _0647_ = _0019_[1] ? _2842_ : _2630_;
- assign _0648_ = _0019_[3] ? _2843_ : _2631_;
- assign _0649_ = _0019_[3] ? _2844_ : _2632_;
- assign _0650_ = _0019_[3] ? _2845_ : _2633_;
- assign _0651_ = _0019_[3] ? _2846_ : _2634_;
- assign _0652_ = _0019_[5] ? _2847_ : _2635_;
- assign _1041_ = _0161_[1] ? _2848_ : _2636_;
- assign _1042_ = _0161_[1] ? _2849_ : _2637_;
- assign _1043_ = _0161_[1] ? _2850_ : _2638_;
- assign _1044_ = _0161_[1] ? _2851_ : _2639_;
- assign _1045_ = _0161_[1] ? _2852_ : _2640_;
- assign _1046_ = _0161_[1] ? _2853_ : _2641_;
- assign _1047_ = _0161_[1] ? _2854_ : _2642_;
- assign _1048_ = _0161_[1] ? _2855_ : _2643_;
- assign _1049_ = _0161_[1] ? _2856_ : _2644_;
- assign _1050_ = _0161_[1] ? _2857_ : _2645_;
- assign _1051_ = _0161_[1] ? _2858_ : _2646_;
- assign _1052_ = _0161_[1] ? _2859_ : _2647_;
- assign _1053_ = _0161_[1] ? _2860_ : _2648_;
- assign _1054_ = _0161_[1] ? _2861_ : _2649_;
- assign _1055_ = _0161_[1] ? _2862_ : _2650_;
- assign _1056_ = _0161_[1] ? _2863_ : _2651_;
- assign _1057_ = _0161_[3] ? _2864_ : _2652_;
- assign _1058_ = _0161_[3] ? _2865_ : _2653_;
- assign _1059_ = _0161_[3] ? _2866_ : _2654_;
- assign _1060_ = _0161_[3] ? _2867_ : _2655_;
- assign _1061_ = _0161_[5] ? _2868_ : _2656_;
- assign _1455_ = _0338_[1] ? _2869_ : _2657_;
- assign _1456_ = _0338_[1] ? _2870_ : _2658_;
- assign _1457_ = _0338_[1] ? _2871_ : _2659_;
- assign _1458_ = _0338_[1] ? _2872_ : _2660_;
- assign _1459_ = _0338_[1] ? _2873_ : _2661_;
- assign _1460_ = _0338_[1] ? _2874_ : _2662_;
- assign _1461_ = _0338_[1] ? _2875_ : _2663_;
- assign _1462_ = _0338_[1] ? _2876_ : _2664_;
- assign _1463_ = _0338_[3] ? _2877_ : _2665_;
- assign _1464_ = _0338_[3] ? _2878_ : _2666_;
- assign _1466_ = _0340_[1] ? _2879_ : _2667_;
- assign _1467_ = _0340_[1] ? _2880_ : _2668_;
- assign _1468_ = _0340_[1] ? _2881_ : _2669_;
- assign _1469_ = _0340_[1] ? _2882_ : _2670_;
- assign _1470_ = _0340_[1] ? _2883_ : _2671_;
- assign _1471_ = _0340_[1] ? _2884_ : _2672_;
- assign _1472_ = _0340_[1] ? _2885_ : _2673_;
- assign _1473_ = _0340_[1] ? _2886_ : _2674_;
- assign _1474_ = _0340_[3] ? _2887_ : _2675_;
- assign _1475_ = _0340_[3] ? _2888_ : _2676_;
- assign _1477_ = _0346_[1] ? _2889_ : _2677_;
- assign _1478_ = _0346_[1] ? _2890_ : _2678_;
- assign _1479_ = _0346_[1] ? _2891_ : _2679_;
- assign _1480_ = _0346_[1] ? _2892_ : _2680_;
- assign _1481_ = _0346_[1] ? _2893_ : _2681_;
- assign _1482_ = _0346_[1] ? _2894_ : _2682_;
- assign _1483_ = _0346_[1] ? _2895_ : _2683_;
- assign _1484_ = _0346_[1] ? _2896_ : _2684_;
- assign _1485_ = _0346_[3] ? _2897_ : _2685_;
- assign _1486_ = _0346_[3] ? _2898_ : _2686_;
- assign _1488_ = _0348_[1] ? _2899_ : _2687_;
- assign _1489_ = _0348_[1] ? _2900_ : _2688_;
- assign _1490_ = _0348_[1] ? _2901_ : _2689_;
- assign _1491_ = _0348_[1] ? _2902_ : _2690_;
- assign _1492_ = _0348_[1] ? _2903_ : _2691_;
- assign _1493_ = _0348_[1] ? _2904_ : _2692_;
- assign _1494_ = _0348_[1] ? _2905_ : _2693_;
- assign _1495_ = _0348_[1] ? _2906_ : _2694_;
- assign _1496_ = _0348_[3] ? _2907_ : _2695_;
- assign _1497_ = _0348_[3] ? _2908_ : _2696_;
- assign _1499_ = _0354_[1] ? _2909_ : _2697_;
- assign _1500_ = _0354_[1] ? _2910_ : _2698_;
- assign _1501_ = _0354_[1] ? _2911_ : _2699_;
- assign _1502_ = _0354_[1] ? _2912_ : _2700_;
- assign _1503_ = _0354_[1] ? _2913_ : _2701_;
- assign _1504_ = _0354_[1] ? _2914_ : _2702_;
- assign _1505_ = _0354_[1] ? _2915_ : _2703_;
- assign _1506_ = _0354_[1] ? _2916_ : _2704_;
- assign _1507_ = _0354_[3] ? _2917_ : _2705_;
- assign _1508_ = _0354_[3] ? _2918_ : _2706_;
- assign _1510_ = _0356_[1] ? _2919_ : _2707_;
- assign _1511_ = _0356_[1] ? _2920_ : _2708_;
- assign _1512_ = _0356_[1] ? _2921_ : _2709_;
- assign _1513_ = _0356_[1] ? _2922_ : _2710_;
- assign _1514_ = _0356_[1] ? _2923_ : _2711_;
- assign _1515_ = _0356_[1] ? _2924_ : _2712_;
- assign _1516_ = _0356_[1] ? _2925_ : _2713_;
- assign _1517_ = _0356_[1] ? _2926_ : _2714_;
- assign _1518_ = _0356_[3] ? _2927_ : _2715_;
- assign _1519_ = _0356_[3] ? _2928_ : _2716_;
- assign _1521_ = _0362_[1] ? _2929_ : _2717_;
- assign _1522_ = _0362_[1] ? _2930_ : _2718_;
- assign _1523_ = _0362_[1] ? _2931_ : _2719_;
- assign _1524_ = _0362_[1] ? _2932_ : _2720_;
- assign _1525_ = _0362_[1] ? _2933_ : _2721_;
- assign _1526_ = _0362_[1] ? _2934_ : _2722_;
- assign _1527_ = _0362_[1] ? _2935_ : _2723_;
- assign _1528_ = _0362_[1] ? _2936_ : _2724_;
- assign _1529_ = _0362_[3] ? _2937_ : _2725_;
- assign _1530_ = _0362_[3] ? _2938_ : _2726_;
- assign _1532_ = _0364_[1] ? _2939_ : _2727_;
- assign _1533_ = _0364_[1] ? _2940_ : _2728_;
- assign _1534_ = _0364_[1] ? _2941_ : _2729_;
- assign _1535_ = _0364_[1] ? _2942_ : _2730_;
- assign _1536_ = _0364_[1] ? _2943_ : _2731_;
- assign _1537_ = _0364_[1] ? _2944_ : _2732_;
- assign _1538_ = _0364_[1] ? _2945_ : _2733_;
- assign _1539_ = _0364_[1] ? _2946_ : _2734_;
- assign _1540_ = _0364_[3] ? _2947_ : _2735_;
- assign _1541_ = _0364_[3] ? _2948_ : _2736_;
- assign _1545_ = _0373_[1] ? _2949_ : _2737_;
- assign _1546_ = _0373_[1] ? _2950_ : _2738_;
- assign _1547_ = _0373_[1] ? _2951_ : _2739_;
- assign _1548_ = _0373_[1] ? _2952_ : _2740_;
- assign _1549_ = _0373_[1] ? _2953_ : _2741_;
- assign _1550_ = _0373_[1] ? _2954_ : _2742_;
- assign _1551_ = _0373_[1] ? _2955_ : _2743_;
- assign _1552_ = _0373_[1] ? _2956_ : _2744_;
- assign _1553_ = _0373_[3] ? _2957_ : _2745_;
- assign _1554_ = _0373_[3] ? _2958_ : _2746_;
- assign _1556_ = _0375_[1] ? _2959_ : _2747_;
- assign _1557_ = _0375_[1] ? _2960_ : _2748_;
- assign _1558_ = _0375_[1] ? _2961_ : _2749_;
- assign _1559_ = _0375_[1] ? _2962_ : _2750_;
- assign _1560_ = _0375_[1] ? _2963_ : _2751_;
- assign _1561_ = _0375_[1] ? _2964_ : _2752_;
- assign _1562_ = _0375_[1] ? _2965_ : _2753_;
- assign _1563_ = _0375_[1] ? _2966_ : _2754_;
- assign _1564_ = _0375_[3] ? _2967_ : _2755_;
- assign _1565_ = _0375_[3] ? _2968_ : _2756_;
- assign _1567_ = _0379_[1] ? _2969_ : _2757_;
- assign _1568_ = _0379_[1] ? _2970_ : _2758_;
- assign _1569_ = _0379_[1] ? _2971_ : _2759_;
- assign _1570_ = _0379_[1] ? _2972_ : _2760_;
- assign _1571_ = _0379_[1] ? _2973_ : _2761_;
- assign _1572_ = _0379_[1] ? _2974_ : _2762_;
- assign _1573_ = _0379_[1] ? _2975_ : _2763_;
- assign _1574_ = _0379_[1] ? _2976_ : _2764_;
- assign _1575_ = _0379_[3] ? _2977_ : _2765_;
- assign _1576_ = _0379_[3] ? _2978_ : _2766_;
- assign _1578_ = _0381_[1] ? _2979_ : _2767_;
- assign _1579_ = _0381_[1] ? _2980_ : _2768_;
- assign _1580_ = _0381_[1] ? _2981_ : _2769_;
- assign _1581_ = _0381_[1] ? _2982_ : _2770_;
- assign _1582_ = _0381_[1] ? _2983_ : _2771_;
- assign _1583_ = _0381_[1] ? _2984_ : _2772_;
- assign _1584_ = _0381_[1] ? _2985_ : _2773_;
- assign _1585_ = _0381_[1] ? _2986_ : _2774_;
- assign _1586_ = _0381_[3] ? _2987_ : _2775_;
- assign _1587_ = _0381_[3] ? _2988_ : _2776_;
- assign _1589_ = _0387_[1] ? _2989_ : _2777_;
- assign _1590_ = _0387_[1] ? _2990_ : _2778_;
- assign _1591_ = _0387_[1] ? _2991_ : _2779_;
- assign _1592_ = _0387_[1] ? _2992_ : _2780_;
- assign _1593_ = _0387_[1] ? _2993_ : _2781_;
- assign _1594_ = _0387_[1] ? _2994_ : _2782_;
- assign _1595_ = _0387_[1] ? _2995_ : _2783_;
- assign _1596_ = _0387_[1] ? _2996_ : _2784_;
- assign _1597_ = _0387_[3] ? _2997_ : _2785_;
- assign _1598_ = _0387_[3] ? _2998_ : _2786_;
- assign _1795_ = _0513_[1] ? _2999_ : _2787_;
- assign _1796_ = _0513_[1] ? _3000_ : _2788_;
- assign _1797_ = _0513_[1] ? _3001_ : _2789_;
- assign _1798_ = _0513_[1] ? _3002_ : _2790_;
- assign _1799_ = _0513_[1] ? _3003_ : _2791_;
- assign _1800_ = _0513_[1] ? _3004_ : _2792_;
- assign _1801_ = _0513_[1] ? _3005_ : _2793_;
- assign _1802_ = _0513_[1] ? _3006_ : _2794_;
- assign _1803_ = _0513_[3] ? _3007_ : _2795_;
- assign _1804_ = _0513_[3] ? _3008_ : _2796_;
- assign _1903_ = _0517_[1] ? _3009_ : _2797_;
- assign _1904_ = _0517_[1] ? _3010_ : _2798_;
- assign _1905_ = _0517_[1] ? _3011_ : _2799_;
- assign _1906_ = _0517_[1] ? _3012_ : _2800_;
- assign _1907_ = _0517_[1] ? _3013_ : _2801_;
- assign _1908_ = _0517_[1] ? _3014_ : _2802_;
- assign _1909_ = _0517_[1] ? _3015_ : _2803_;
- assign _1910_ = _0517_[1] ? _3016_ : _2804_;
- assign _1911_ = _0517_[3] ? _3017_ : _2805_;
- assign _1912_ = _0517_[3] ? _3018_ : _2806_;
- assign _2205_ = _0531_[1] ? _3019_ : _2807_;
- assign _2206_ = _0531_[1] ? _3020_ : _2808_;
- assign _2207_ = _0531_[1] ? _3021_ : _2809_;
- assign _2208_ = _0531_[1] ? _3022_ : _2810_;
- assign _2209_ = _0531_[1] ? _3023_ : _2811_;
- assign _2210_ = _0531_[1] ? _3024_ : _2812_;
- assign _2211_ = _0531_[1] ? _3025_ : _2813_;
- assign _2212_ = _0531_[1] ? _3026_ : _2814_;
- assign _2213_ = _0531_[3] ? _3027_ : _2815_;
- assign _2214_ = _0531_[3] ? _3028_ : _2816_;
- assign _2313_ = _0535_[1] ? _3029_ : _2817_;
- assign _2314_ = _0535_[1] ? _3030_ : _2818_;
- assign _2315_ = _0535_[1] ? _3031_ : _2819_;
- assign _2316_ = _0535_[1] ? _3032_ : _2820_;
- assign _2317_ = _0535_[1] ? _3033_ : _2821_;
- assign _2318_ = _0535_[1] ? _3034_ : _2822_;
- assign _2319_ = _0535_[1] ? _3035_ : _2823_;
- assign _2320_ = _0535_[1] ? _3036_ : _2824_;
- assign _2321_ = _0535_[3] ? _3037_ : _2825_;
- assign _2322_ = _0535_[3] ? _3038_ : _2826_;
- assign _0000_ = ~ _0409_;
- assign _0001_ = d_in[0] & m_in[0];
- assign _0002_ = ~ _0001_;
- assign _0003_ = ~ _0012_;
- assign _0004_ = _0003_ | _0002_;
- assign _0005_ = m_in[1] | m_in[3];
- assign _0006_ = ~ _0005_;
- assign _0007_ = m_in[0] ? { 1'h1, m_in[3:1], 8'hff, m_in[131:4], 5'h10, _0006_, 1'h1 } : { 4'h0, d_in };
- assign _0008_ = _0000_ ? _0007_ : r0;
- assign _0009_ = _0000_ ? 1'h1 : 1'h0;
- assign _0010_ = rst ? 1'h0 : _0008_[0];
- assign _0011_ = rst ? r0[146:1] : _0008_[146:1];
- assign _0012_ = rst ? 1'h0 : _0009_;
- always @(posedge clk)
- _0013_ <= _0004_;
- always @(posedge clk)
- r0 <= { _0011_, _0010_ };
- assign _0014_ = ~ _0409_;
- assign _0015_ = r0[0] & _0014_;
- assign _0016_ = ~ _0509_[0];
- assign r0_valid = _0015_ & _0016_;
- assign _0017_ = m_in[0] ? m_in[21:16] : d_in[24:19];
- assign _0018_ = _0409_ ? r0[24:19] : _0017_;
- assign _0019_ = 6'h3f - _0018_;
- always @(posedge clk)
- tlb_valid_way <= _0652_;
- assign _0020_ = { 26'h0000000, r0[24:19] } == 32'd0;
- assign _0021_ = tlb_hit & _0020_;
- assign \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en = _0021_ ? 1'h1 : 1'h0;
- assign _0022_ = { 26'h0000000, r0[24:19] } == 32'd1;
- assign _0023_ = tlb_hit & _0022_;
- assign \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en = _0023_ ? 1'h1 : 1'h0;
- assign _0024_ = { 26'h0000000, r0[24:19] } == 32'd2;
- assign _0025_ = tlb_hit & _0024_;
- assign \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en = _0025_ ? 1'h1 : 1'h0;
- assign _0026_ = { 26'h0000000, r0[24:19] } == 32'd3;
- assign _0027_ = tlb_hit & _0026_;
- assign \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en = _0027_ ? 1'h1 : 1'h0;
- assign _0028_ = { 26'h0000000, r0[24:19] } == 32'd4;
- assign _0029_ = tlb_hit & _0028_;
- assign \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en = _0029_ ? 1'h1 : 1'h0;
- assign _0030_ = { 26'h0000000, r0[24:19] } == 32'd5;
- assign _0031_ = tlb_hit & _0030_;
- assign \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en = _0031_ ? 1'h1 : 1'h0;
- assign _0032_ = { 26'h0000000, r0[24:19] } == 32'd6;
- assign _0033_ = tlb_hit & _0032_;
- assign \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en = _0033_ ? 1'h1 : 1'h0;
- assign _0034_ = { 26'h0000000, r0[24:19] } == 32'd7;
- assign _0035_ = tlb_hit & _0034_;
- assign \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en = _0035_ ? 1'h1 : 1'h0;
- assign _0036_ = { 26'h0000000, r0[24:19] } == 32'd8;
- assign _0037_ = tlb_hit & _0036_;
- assign \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en = _0037_ ? 1'h1 : 1'h0;
- assign _0038_ = { 26'h0000000, r0[24:19] } == 32'd9;
- assign _0039_ = tlb_hit & _0038_;
- assign \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en = _0039_ ? 1'h1 : 1'h0;
- assign _0040_ = { 26'h0000000, r0[24:19] } == 32'd10;
- assign _0041_ = tlb_hit & _0040_;
- assign \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en = _0041_ ? 1'h1 : 1'h0;
- assign _0042_ = { 26'h0000000, r0[24:19] } == 32'd11;
- assign _0043_ = tlb_hit & _0042_;
- assign \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en = _0043_ ? 1'h1 : 1'h0;
- assign _0044_ = { 26'h0000000, r0[24:19] } == 32'd12;
- assign _0045_ = tlb_hit & _0044_;
- assign \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en = _0045_ ? 1'h1 : 1'h0;
- assign _0046_ = { 26'h0000000, r0[24:19] } == 32'd13;
- assign _0047_ = tlb_hit & _0046_;
- assign \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en = _0047_ ? 1'h1 : 1'h0;
- assign _0048_ = { 26'h0000000, r0[24:19] } == 32'd14;
- assign _0049_ = tlb_hit & _0048_;
- assign \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en = _0049_ ? 1'h1 : 1'h0;
- assign _0050_ = { 26'h0000000, r0[24:19] } == 32'd15;
- assign _0051_ = tlb_hit & _0050_;
- assign \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en = _0051_ ? 1'h1 : 1'h0;
- assign _0052_ = { 26'h0000000, r0[24:19] } == 32'd16;
- assign _0053_ = tlb_hit & _0052_;
- assign \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en = _0053_ ? 1'h1 : 1'h0;
- assign _0054_ = { 26'h0000000, r0[24:19] } == 32'd17;
- assign _0055_ = tlb_hit & _0054_;
- assign \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en = _0055_ ? 1'h1 : 1'h0;
- assign _0056_ = { 26'h0000000, r0[24:19] } == 32'd18;
- assign _0057_ = tlb_hit & _0056_;
- assign \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en = _0057_ ? 1'h1 : 1'h0;
- assign _0058_ = { 26'h0000000, r0[24:19] } == 32'd19;
- assign _0059_ = tlb_hit & _0058_;
- assign \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en = _0059_ ? 1'h1 : 1'h0;
- assign _0060_ = { 26'h0000000, r0[24:19] } == 32'd20;
- assign _0061_ = tlb_hit & _0060_;
- assign \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en = _0061_ ? 1'h1 : 1'h0;
- assign _0062_ = { 26'h0000000, r0[24:19] } == 32'd21;
- assign _0063_ = tlb_hit & _0062_;
- assign \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en = _0063_ ? 1'h1 : 1'h0;
- assign _0064_ = { 26'h0000000, r0[24:19] } == 32'd22;
- assign _0065_ = tlb_hit & _0064_;
- assign \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en = _0065_ ? 1'h1 : 1'h0;
- assign _0066_ = { 26'h0000000, r0[24:19] } == 32'd23;
- assign _0067_ = tlb_hit & _0066_;
- assign \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en = _0067_ ? 1'h1 : 1'h0;
- assign _0068_ = { 26'h0000000, r0[24:19] } == 32'd24;
- assign _0069_ = tlb_hit & _0068_;
- assign \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en = _0069_ ? 1'h1 : 1'h0;
- assign _0070_ = { 26'h0000000, r0[24:19] } == 32'd25;
- assign _0071_ = tlb_hit & _0070_;
- assign \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en = _0071_ ? 1'h1 : 1'h0;
- assign _0072_ = { 26'h0000000, r0[24:19] } == 32'd26;
- assign _0073_ = tlb_hit & _0072_;
- assign \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en = _0073_ ? 1'h1 : 1'h0;
- assign _0074_ = { 26'h0000000, r0[24:19] } == 32'd27;
- assign _0075_ = tlb_hit & _0074_;
- assign \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en = _0075_ ? 1'h1 : 1'h0;
- assign _0076_ = { 26'h0000000, r0[24:19] } == 32'd28;
- assign _0077_ = tlb_hit & _0076_;
- assign \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en = _0077_ ? 1'h1 : 1'h0;
- assign _0078_ = { 26'h0000000, r0[24:19] } == 32'd29;
- assign _0079_ = tlb_hit & _0078_;
- assign \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en = _0079_ ? 1'h1 : 1'h0;
- assign _0080_ = { 26'h0000000, r0[24:19] } == 32'd30;
- assign _0081_ = tlb_hit & _0080_;
- assign \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en = _0081_ ? 1'h1 : 1'h0;
- assign _0082_ = { 26'h0000000, r0[24:19] } == 32'd31;
- assign _0083_ = tlb_hit & _0082_;
- assign \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en = _0083_ ? 1'h1 : 1'h0;
- assign _0084_ = { 26'h0000000, r0[24:19] } == 32'd32;
- assign _0085_ = tlb_hit & _0084_;
- assign \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en = _0085_ ? 1'h1 : 1'h0;
- assign _0086_ = { 26'h0000000, r0[24:19] } == 32'd33;
- assign _0087_ = tlb_hit & _0086_;
- assign \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en = _0087_ ? 1'h1 : 1'h0;
- assign _0088_ = { 26'h0000000, r0[24:19] } == 32'd34;
- assign _0089_ = tlb_hit & _0088_;
- assign \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en = _0089_ ? 1'h1 : 1'h0;
- assign _0090_ = { 26'h0000000, r0[24:19] } == 32'd35;
- assign _0091_ = tlb_hit & _0090_;
- assign \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en = _0091_ ? 1'h1 : 1'h0;
- assign _0092_ = { 26'h0000000, r0[24:19] } == 32'd36;
- assign _0093_ = tlb_hit & _0092_;
- assign \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en = _0093_ ? 1'h1 : 1'h0;
- assign _0094_ = { 26'h0000000, r0[24:19] } == 32'd37;
- assign _0095_ = tlb_hit & _0094_;
- assign \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en = _0095_ ? 1'h1 : 1'h0;
- assign _0096_ = { 26'h0000000, r0[24:19] } == 32'd38;
- assign _0097_ = tlb_hit & _0096_;
- assign \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en = _0097_ ? 1'h1 : 1'h0;
- assign _0098_ = { 26'h0000000, r0[24:19] } == 32'd39;
- assign _0099_ = tlb_hit & _0098_;
- assign \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en = _0099_ ? 1'h1 : 1'h0;
- assign _0100_ = { 26'h0000000, r0[24:19] } == 32'd40;
- assign _0101_ = tlb_hit & _0100_;
- assign \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en = _0101_ ? 1'h1 : 1'h0;
- assign _0102_ = { 26'h0000000, r0[24:19] } == 32'd41;
- assign _0103_ = tlb_hit & _0102_;
- assign \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en = _0103_ ? 1'h1 : 1'h0;
- assign _0104_ = { 26'h0000000, r0[24:19] } == 32'd42;
- assign _0105_ = tlb_hit & _0104_;
- assign \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en = _0105_ ? 1'h1 : 1'h0;
- assign _0106_ = { 26'h0000000, r0[24:19] } == 32'd43;
- assign _0107_ = tlb_hit & _0106_;
- assign \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en = _0107_ ? 1'h1 : 1'h0;
- assign _0108_ = { 26'h0000000, r0[24:19] } == 32'd44;
- assign _0109_ = tlb_hit & _0108_;
- assign \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en = _0109_ ? 1'h1 : 1'h0;
- assign _0110_ = { 26'h0000000, r0[24:19] } == 32'd45;
- assign _0111_ = tlb_hit & _0110_;
- assign \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en = _0111_ ? 1'h1 : 1'h0;
- assign _0112_ = { 26'h0000000, r0[24:19] } == 32'd46;
- assign _0113_ = tlb_hit & _0112_;
- assign \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en = _0113_ ? 1'h1 : 1'h0;
- assign _0114_ = { 26'h0000000, r0[24:19] } == 32'd47;
- assign _0115_ = tlb_hit & _0114_;
- assign \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en = _0115_ ? 1'h1 : 1'h0;
- assign _0116_ = { 26'h0000000, r0[24:19] } == 32'd48;
- assign _0117_ = tlb_hit & _0116_;
- assign \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en = _0117_ ? 1'h1 : 1'h0;
- assign _0118_ = { 26'h0000000, r0[24:19] } == 32'd49;
- assign _0119_ = tlb_hit & _0118_;
- assign \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en = _0119_ ? 1'h1 : 1'h0;
- assign _0120_ = { 26'h0000000, r0[24:19] } == 32'd50;
- assign _0121_ = tlb_hit & _0120_;
- assign \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en = _0121_ ? 1'h1 : 1'h0;
- assign _0122_ = { 26'h0000000, r0[24:19] } == 32'd51;
- assign _0123_ = tlb_hit & _0122_;
- assign \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en = _0123_ ? 1'h1 : 1'h0;
- assign _0124_ = { 26'h0000000, r0[24:19] } == 32'd52;
- assign _0125_ = tlb_hit & _0124_;
- assign \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en = _0125_ ? 1'h1 : 1'h0;
- assign _0126_ = { 26'h0000000, r0[24:19] } == 32'd53;
- assign _0127_ = tlb_hit & _0126_;
- assign \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en = _0127_ ? 1'h1 : 1'h0;
- assign _0128_ = { 26'h0000000, r0[24:19] } == 32'd54;
- assign _0129_ = tlb_hit & _0128_;
- assign \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en = _0129_ ? 1'h1 : 1'h0;
- assign _0130_ = { 26'h0000000, r0[24:19] } == 32'd55;
- assign _0131_ = tlb_hit & _0130_;
- assign \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en = _0131_ ? 1'h1 : 1'h0;
- assign _0132_ = { 26'h0000000, r0[24:19] } == 32'd56;
- assign _0133_ = tlb_hit & _0132_;
- assign \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en = _0133_ ? 1'h1 : 1'h0;
- assign _0134_ = { 26'h0000000, r0[24:19] } == 32'd57;
- assign _0135_ = tlb_hit & _0134_;
- assign \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en = _0135_ ? 1'h1 : 1'h0;
- assign _0136_ = { 26'h0000000, r0[24:19] } == 32'd58;
- assign _0137_ = tlb_hit & _0136_;
- assign \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en = _0137_ ? 1'h1 : 1'h0;
- assign _0138_ = { 26'h0000000, r0[24:19] } == 32'd59;
- assign _0139_ = tlb_hit & _0138_;
- assign \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en = _0139_ ? 1'h1 : 1'h0;
- assign _0140_ = { 26'h0000000, r0[24:19] } == 32'd60;
- assign _0141_ = tlb_hit & _0140_;
- assign \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en = _0141_ ? 1'h1 : 1'h0;
- assign _0142_ = { 26'h0000000, r0[24:19] } == 32'd61;
- assign _0143_ = tlb_hit & _0142_;
- assign \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en = _0143_ ? 1'h1 : 1'h0;
- assign _0144_ = { 26'h0000000, r0[24:19] } == 32'd62;
- assign _0145_ = tlb_hit & _0144_;
- assign \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en = _0145_ ? 1'h1 : 1'h0;
- assign _0146_ = { 26'h0000000, r0[24:19] } == 32'd63;
- assign _0147_ = tlb_hit & _0146_;
- assign \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en = _0147_ ? 1'h1 : 1'h0;
- assign _0148_ = tlb_tag_way[45:0] == r0[70:25];
- assign _0149_ = tlb_valid_way[0] & _0148_;
- assign _0150_ = _0149_ ? 1'h1 : 1'h0;
- assign _0151_ = tlb_tag_way[91:46] == r0[70:25];
- assign _0152_ = tlb_valid_way[1] & _0151_;
- assign tlb_hit_way = _0152_ ? 1'h1 : 1'h0;
- assign _0153_ = _0152_ ? 1'h1 : _0150_;
- assign tlb_hit = _0153_ & r0_valid;
- assign pte = tlb_hit ? _0653_ : 64'h0000000000000000;
- assign _0154_ = ~ r0[5];
- assign valid_ra = tlb_hit | _0154_;
- assign ra = r0[5] ? { pte[55:12], r0[18:7] } : r0[62:7];
- assign perm_attr = r0[5] ? { pte[1], pte[2], pte[3], pte[5], pte[7], pte[8] } : 6'h3b;
- assign _0155_ = r0_valid & r0[143];
- assign _0156_ = r0_valid & r0[145];
- assign _0157_ = _0155_ & r0[144];
- assign _0158_ = rst | _0157_;
- assign _0159_ = 6'h3f - r0[24:19];
- assign _0160_ = tlb_hit ? { _1040_, _1039_, _1038_, _1037_, _1036_, _1035_, _1034_, _1033_, _1032_, _1031_, _1030_, _1029_, _1028_, _1027_, _1026_, _1025_, _1024_, _1023_, _1022_, _1021_, _1020_, _1019_, _1018_, _1017_, _1016_, _1015_, _1014_, _1013_, _1012_, _1011_, _1010_, _1009_, _1008_, _1007_, _1006_, _1005_, _1004_, _1003_, _1002_, _1001_, _1000_, _0999_, _0998_, _0997_, _0996_, _0995_, _0994_, _0993_, _0992_, _0991_, _0990_, _0989_, _0988_, _0987_, _0986_, _0985_, _0984_, _0983_, _0982_, _0981_, _0980_, _0979_, _0978_, _0977_, _0976_, _0975_, _0974_, _0973_, _0972_, _0971_, _0970_, _0969_, _0968_, _0967_, _0966_, _0965_, _0964_, _0963_, _0962_, _0961_, _0960_, _0959_, _0958_, _0957_, _0956_, _0955_, _0954_, _0953_, _0952_, _0951_, _0950_, _0949_, _0948_, _0947_, _0946_, _0945_, _0944_, _0943_, _0942_, _0941_, _0940_, _0939_, _0938_, _0937_, _0936_, _0935_, _0934_, _0933_, _0932_, _0931_, _0930_, _0929_, _0928_, _0927_, _0926_, _0925_, _0924_, _0923_, _0922_, _0921_, _0920_, _0919_, _0918_, _0917_, _0916_, _0915_, _0914_, _0913_ } : dtlb_valids;
- assign _0161_ = 6'h3f - r0[24:19];
- assign _0162_ = tlb_hit ? tlb_hit_way : _1061_;
- assign _0163_ = 6'h3f - r0[24:19];
- assign _0164_ = _0156_ ? { _1454_, _1453_, _1452_, _1451_, _1450_, _1449_, _1448_, _1447_, _1446_, _1445_, _1444_, _1443_, _1442_, _1441_, _1440_, _1439_, _1438_, _1437_, _1436_, _1435_, _1434_, _1433_, _1432_, _1431_, _1430_, _1429_, _1428_, _1427_, _1426_, _1425_, _1424_, _1423_, _1422_, _1421_, _1420_, _1419_, _1418_, _1417_, _1416_, _1415_, _1414_, _1413_, _1412_, _1411_, _1410_, _1409_, _1408_, _1407_, _1406_, _1405_, _1404_, _1403_, _1402_, _1401_, _1400_, _1399_, _1398_, _1397_, _1396_, _1395_, _1394_, _1393_, _1392_, _1391_, _1390_, _1389_, _1388_, _1387_, _1386_, _1385_, _1384_, _1383_, _1382_, _1381_, _1380_, _1379_, _1378_, _1377_, _1376_, _1375_, _1374_, _1373_, _1372_, _1371_, _1370_, _1369_, _1368_, _1367_, _1366_, _1365_, _1364_, _1363_, _1362_, _1361_, _1360_, _1359_, _1358_, _1357_, _1356_, _1355_, _1354_, _1353_, _1352_, _1351_, _1350_, _1349_, _1348_, _1347_, _1346_, _1345_, _1344_, _1343_, _1342_, _1341_, _1340_, _1339_, _1338_, _1337_, _1336_, _1335_, _1334_, _1333_, _1332_, _1331_, _1330_, _1329_, _1328_, _1327_ } : dtlb_valids;
- assign _0165_ = _0155_ ? _0160_ : _0164_;
- assign _0166_ = _0158_ ? 128'h00000000000000000000000000000000 : _0165_;
- always @(posedge clk)
- dtlb_valids <= _0166_;
- assign _0167_ = ~ _0158_;
- assign _0168_ = ~ _0155_;
- assign _0169_ = _0167_ & _0168_;
- assign _0170_ = _0169_ & _0156_;
- assign _0171_ = ~ _0158_;
- assign _0172_ = ~ _0155_;
- assign _0173_ = _0171_ & _0172_;
- assign _0174_ = _0173_ & _0156_;
- assign _0175_ = req_op == 3'h1;
- assign _0176_ = req_op == 3'h6;
- assign _0177_ = _0175_ | _0176_;
- assign _0178_ = { 27'h0000000, r0[17:13] } == 32'd0;
- assign _0179_ = _0177_ & _0178_;
- assign \maybe_plrus.plrus%0.plru_acc_en = _0179_ ? 1'h1 : 1'h0;
- assign _0180_ = req_op == 3'h1;
- assign _0181_ = req_op == 3'h6;
- assign _0182_ = _0180_ | _0181_;
- assign _0183_ = { 27'h0000000, r0[17:13] } == 32'd1;
- assign _0184_ = _0182_ & _0183_;
- assign \maybe_plrus.plrus%1.plru_acc_en = _0184_ ? 1'h1 : 1'h0;
- assign _0185_ = req_op == 3'h1;
- assign _0186_ = req_op == 3'h6;
- assign _0187_ = _0185_ | _0186_;
- assign _0188_ = { 27'h0000000, r0[17:13] } == 32'd2;
- assign _0189_ = _0187_ & _0188_;
- assign \maybe_plrus.plrus%2.plru_acc_en = _0189_ ? 1'h1 : 1'h0;
- assign _0190_ = req_op == 3'h1;
- assign _0191_ = req_op == 3'h6;
- assign _0192_ = _0190_ | _0191_;
- assign _0193_ = { 27'h0000000, r0[17:13] } == 32'd3;
- assign _0194_ = _0192_ & _0193_;
- assign \maybe_plrus.plrus%3.plru_acc_en = _0194_ ? 1'h1 : 1'h0;
- assign _0195_ = req_op == 3'h1;
- assign _0196_ = req_op == 3'h6;
- assign _0197_ = _0195_ | _0196_;
- assign _0198_ = { 27'h0000000, r0[17:13] } == 32'd4;
- assign _0199_ = _0197_ & _0198_;
- assign \maybe_plrus.plrus%4.plru_acc_en = _0199_ ? 1'h1 : 1'h0;
- assign _0200_ = req_op == 3'h1;
- assign _0201_ = req_op == 3'h6;
- assign _0202_ = _0200_ | _0201_;
- assign _0203_ = { 27'h0000000, r0[17:13] } == 32'd5;
- assign _0204_ = _0202_ & _0203_;
- assign \maybe_plrus.plrus%5.plru_acc_en = _0204_ ? 1'h1 : 1'h0;
- assign _0205_ = req_op == 3'h1;
- assign _0206_ = req_op == 3'h6;
- assign _0207_ = _0205_ | _0206_;
- assign _0208_ = { 27'h0000000, r0[17:13] } == 32'd6;
- assign _0209_ = _0207_ & _0208_;
- assign \maybe_plrus.plrus%6.plru_acc_en = _0209_ ? 1'h1 : 1'h0;
- assign _0210_ = req_op == 3'h1;
- assign _0211_ = req_op == 3'h6;
- assign _0212_ = _0210_ | _0211_;
- assign _0213_ = { 27'h0000000, r0[17:13] } == 32'd7;
- assign _0214_ = _0212_ & _0213_;
- assign \maybe_plrus.plrus%7.plru_acc_en = _0214_ ? 1'h1 : 1'h0;
- assign _0215_ = req_op == 3'h1;
- assign _0216_ = req_op == 3'h6;
- assign _0217_ = _0215_ | _0216_;
- assign _0218_ = { 27'h0000000, r0[17:13] } == 32'd8;
- assign _0219_ = _0217_ & _0218_;
- assign \maybe_plrus.plrus%8.plru_acc_en = _0219_ ? 1'h1 : 1'h0;
- assign _0220_ = req_op == 3'h1;
- assign _0221_ = req_op == 3'h6;
- assign _0222_ = _0220_ | _0221_;
- assign _0223_ = { 27'h0000000, r0[17:13] } == 32'd9;
- assign _0224_ = _0222_ & _0223_;
- assign \maybe_plrus.plrus%9.plru_acc_en = _0224_ ? 1'h1 : 1'h0;
- assign _0225_ = req_op == 3'h1;
- assign _0226_ = req_op == 3'h6;
- assign _0227_ = _0225_ | _0226_;
- assign _0228_ = { 27'h0000000, r0[17:13] } == 32'd10;
- assign _0229_ = _0227_ & _0228_;
- assign \maybe_plrus.plrus%10.plru_acc_en = _0229_ ? 1'h1 : 1'h0;
- assign _0230_ = req_op == 3'h1;
- assign _0231_ = req_op == 3'h6;
- assign _0232_ = _0230_ | _0231_;
- assign _0233_ = { 27'h0000000, r0[17:13] } == 32'd11;
- assign _0234_ = _0232_ & _0233_;
- assign \maybe_plrus.plrus%11.plru_acc_en = _0234_ ? 1'h1 : 1'h0;
- assign _0235_ = req_op == 3'h1;
- assign _0236_ = req_op == 3'h6;
- assign _0237_ = _0235_ | _0236_;
- assign _0238_ = { 27'h0000000, r0[17:13] } == 32'd12;
- assign _0239_ = _0237_ & _0238_;
- assign \maybe_plrus.plrus%12.plru_acc_en = _0239_ ? 1'h1 : 1'h0;
- assign _0240_ = req_op == 3'h1;
- assign _0241_ = req_op == 3'h6;
- assign _0242_ = _0240_ | _0241_;
- assign _0243_ = { 27'h0000000, r0[17:13] } == 32'd13;
- assign _0244_ = _0242_ & _0243_;
- assign \maybe_plrus.plrus%13.plru_acc_en = _0244_ ? 1'h1 : 1'h0;
- assign _0245_ = req_op == 3'h1;
- assign _0246_ = req_op == 3'h6;
- assign _0247_ = _0245_ | _0246_;
- assign _0248_ = { 27'h0000000, r0[17:13] } == 32'd14;
- assign _0249_ = _0247_ & _0248_;
- assign \maybe_plrus.plrus%14.plru_acc_en = _0249_ ? 1'h1 : 1'h0;
- assign _0250_ = req_op == 3'h1;
- assign _0251_ = req_op == 3'h6;
- assign _0252_ = _0250_ | _0251_;
- assign _0253_ = { 27'h0000000, r0[17:13] } == 32'd15;
- assign _0254_ = _0252_ & _0253_;
- assign \maybe_plrus.plrus%15.plru_acc_en = _0254_ ? 1'h1 : 1'h0;
- assign _0255_ = req_op == 3'h1;
- assign _0256_ = req_op == 3'h6;
- assign _0257_ = _0255_ | _0256_;
- assign _0258_ = { 27'h0000000, r0[17:13] } == 32'd16;
- assign _0259_ = _0257_ & _0258_;
- assign \maybe_plrus.plrus%16.plru_acc_en = _0259_ ? 1'h1 : 1'h0;
- assign _0260_ = req_op == 3'h1;
- assign _0261_ = req_op == 3'h6;
- assign _0262_ = _0260_ | _0261_;
- assign _0263_ = { 27'h0000000, r0[17:13] } == 32'd17;
- assign _0264_ = _0262_ & _0263_;
- assign \maybe_plrus.plrus%17.plru_acc_en = _0264_ ? 1'h1 : 1'h0;
- assign _0265_ = req_op == 3'h1;
- assign _0266_ = req_op == 3'h6;
- assign _0267_ = _0265_ | _0266_;
- assign _0268_ = { 27'h0000000, r0[17:13] } == 32'd18;
- assign _0269_ = _0267_ & _0268_;
- assign \maybe_plrus.plrus%18.plru_acc_en = _0269_ ? 1'h1 : 1'h0;
- assign _0270_ = req_op == 3'h1;
- assign _0271_ = req_op == 3'h6;
- assign _0272_ = _0270_ | _0271_;
- assign _0273_ = { 27'h0000000, r0[17:13] } == 32'd19;
- assign _0274_ = _0272_ & _0273_;
- assign \maybe_plrus.plrus%19.plru_acc_en = _0274_ ? 1'h1 : 1'h0;
- assign _0275_ = req_op == 3'h1;
- assign _0276_ = req_op == 3'h6;
- assign _0277_ = _0275_ | _0276_;
- assign _0278_ = { 27'h0000000, r0[17:13] } == 32'd20;
- assign _0279_ = _0277_ & _0278_;
- assign \maybe_plrus.plrus%20.plru_acc_en = _0279_ ? 1'h1 : 1'h0;
- assign _0280_ = req_op == 3'h1;
- assign _0281_ = req_op == 3'h6;
- assign _0282_ = _0280_ | _0281_;
- assign _0283_ = { 27'h0000000, r0[17:13] } == 32'd21;
- assign _0284_ = _0282_ & _0283_;
- assign \maybe_plrus.plrus%21.plru_acc_en = _0284_ ? 1'h1 : 1'h0;
- assign _0285_ = req_op == 3'h1;
- assign _0286_ = req_op == 3'h6;
- assign _0287_ = _0285_ | _0286_;
- assign _0288_ = { 27'h0000000, r0[17:13] } == 32'd22;
- assign _0289_ = _0287_ & _0288_;
- assign \maybe_plrus.plrus%22.plru_acc_en = _0289_ ? 1'h1 : 1'h0;
- assign _0290_ = req_op == 3'h1;
- assign _0291_ = req_op == 3'h6;
- assign _0292_ = _0290_ | _0291_;
- assign _0293_ = { 27'h0000000, r0[17:13] } == 32'd23;
- assign _0294_ = _0292_ & _0293_;
- assign \maybe_plrus.plrus%23.plru_acc_en = _0294_ ? 1'h1 : 1'h0;
- assign _0295_ = req_op == 3'h1;
- assign _0296_ = req_op == 3'h6;
- assign _0297_ = _0295_ | _0296_;
- assign _0298_ = { 27'h0000000, r0[17:13] } == 32'd24;
- assign _0299_ = _0297_ & _0298_;
- assign \maybe_plrus.plrus%24.plru_acc_en = _0299_ ? 1'h1 : 1'h0;
- assign _0300_ = req_op == 3'h1;
- assign _0301_ = req_op == 3'h6;
- assign _0302_ = _0300_ | _0301_;
- assign _0303_ = { 27'h0000000, r0[17:13] } == 32'd25;
- assign _0304_ = _0302_ & _0303_;
- assign \maybe_plrus.plrus%25.plru_acc_en = _0304_ ? 1'h1 : 1'h0;
- assign _0305_ = req_op == 3'h1;
- assign _0306_ = req_op == 3'h6;
- assign _0307_ = _0305_ | _0306_;
- assign _0308_ = { 27'h0000000, r0[17:13] } == 32'd26;
- assign _0309_ = _0307_ & _0308_;
- assign \maybe_plrus.plrus%26.plru_acc_en = _0309_ ? 1'h1 : 1'h0;
- assign _0310_ = req_op == 3'h1;
- assign _0311_ = req_op == 3'h6;
- assign _0312_ = _0310_ | _0311_;
- assign _0313_ = { 27'h0000000, r0[17:13] } == 32'd27;
- assign _0314_ = _0312_ & _0313_;
- assign \maybe_plrus.plrus%27.plru_acc_en = _0314_ ? 1'h1 : 1'h0;
- assign _0315_ = req_op == 3'h1;
- assign _0316_ = req_op == 3'h6;
- assign _0317_ = _0315_ | _0316_;
- assign _0318_ = { 27'h0000000, r0[17:13] } == 32'd28;
- assign _0319_ = _0317_ & _0318_;
- assign \maybe_plrus.plrus%28.plru_acc_en = _0319_ ? 1'h1 : 1'h0;
- assign _0320_ = req_op == 3'h1;
- assign _0321_ = req_op == 3'h6;
- assign _0322_ = _0320_ | _0321_;
- assign _0323_ = { 27'h0000000, r0[17:13] } == 32'd29;
- assign _0324_ = _0322_ & _0323_;
- assign \maybe_plrus.plrus%29.plru_acc_en = _0324_ ? 1'h1 : 1'h0;
- assign _0325_ = req_op == 3'h1;
- assign _0326_ = req_op == 3'h6;
- assign _0327_ = _0325_ | _0326_;
- assign _0328_ = { 27'h0000000, r0[17:13] } == 32'd30;
- assign _0329_ = _0327_ & _0328_;
- assign \maybe_plrus.plrus%30.plru_acc_en = _0329_ ? 1'h1 : 1'h0;
- assign _0330_ = req_op == 3'h1;
- assign _0331_ = req_op == 3'h6;
- assign _0332_ = _0330_ | _0331_;
- assign _0333_ = { 27'h0000000, r0[17:13] } == 32'd31;
- assign _0334_ = _0332_ & _0333_;
- assign \maybe_plrus.plrus%31.plru_acc_en = _0334_ ? 1'h1 : 1'h0;
- assign _0335_ = r0[143] | r0[145];
- assign _0336_ = ~ _0335_;
- assign _0337_ = r0_valid & _0336_;
- assign _0338_ = 5'h1f - r0[17:13];
- assign _0339_ = _0337_ & _1465_;
- assign _0340_ = 5'h1f - r0[17:13];
- assign _0341_ = _1476_[44:0] == { tlb_pte_way[55:12], r0[18] };
- assign _0342_ = _0339_ & _0341_;
- assign _0343_ = _0342_ & tlb_valid_way[0];
- assign _0344_ = _0343_ ? 1'h1 : 1'h0;
- assign _0345_ = _0343_ ? 1'h0 : 1'h0;
- assign _0346_ = 5'h1f - r0[17:13];
- assign _0347_ = _0337_ & _1487_;
- assign _0348_ = 5'h1f - r0[17:13];
- assign _0349_ = _1498_[89:45] == { tlb_pte_way[55:12], r0[18] };
- assign _0350_ = _0347_ & _0349_;
- assign _0351_ = _0350_ & tlb_valid_way[0];
- assign _0352_ = _0351_ ? 1'h1 : _0344_;
- assign _0353_ = _0351_ ? 1'h1 : _0345_;
- assign _0354_ = 5'h1f - r0[17:13];
- assign _0355_ = _0337_ & _1509_;
- assign _0356_ = 5'h1f - r0[17:13];
- assign _0357_ = _1520_[44:0] == { tlb_pte_way[119:76], r0[18] };
- assign _0358_ = _0355_ & _0357_;
- assign _0359_ = _0358_ & tlb_valid_way[1];
- assign _0360_ = _0359_ ? 1'h1 : 1'h0;
- assign _0361_ = _0359_ ? 1'h0 : 1'h0;
- assign _0362_ = 5'h1f - r0[17:13];
- assign _0363_ = _0337_ & _1531_;
- assign _0364_ = 5'h1f - r0[17:13];
- assign _0365_ = _1542_[89:45] == { tlb_pte_way[119:76], r0[18] };
- assign _0366_ = _0363_ & _0365_;
- assign _0367_ = _0366_ & tlb_valid_way[1];
- assign _0368_ = _0367_ ? 1'h1 : _0360_;
- assign _0369_ = _0367_ ? 1'h1 : _0361_;
- assign _0370_ = 1'h1 - tlb_hit_way;
- assign _0371_ = tlb_hit ? _1543_ : 1'h0;
- assign _0372_ = tlb_hit ? _1544_ : 1'h0;
- assign _0373_ = 5'h1f - r0[17:13];
- assign _0374_ = _0337_ & _1555_;
- assign _0375_ = 5'h1f - r0[17:13];
- assign _0376_ = _1566_[44:0] == r0[62:18];
- assign _0377_ = _0374_ & _0376_;
- assign _0378_ = _0377_ ? 1'h1 : 1'h0;
- assign _0379_ = 5'h1f - r0[17:13];
- assign _0380_ = _0337_ & _1577_;
- assign _0381_ = 5'h1f - r0[17:13];
- assign _0382_ = _1588_[89:45] == r0[62:18];
- assign _0383_ = _0380_ & _0382_;
- assign _0384_ = _0383_ ? 1'h1 : _0378_;
- assign _0385_ = _0383_ ? 1'h1 : 1'h0;
- assign _0386_ = r0[5] ? _0371_ : _0384_;
- assign req_hit_way = r0[5] ? _0372_ : _0385_;
- assign _0387_ = 5'h1f - r0[17:13];
- assign _0388_ = r0[1] | perm_attr[1];
- assign rc_ok = perm_attr[0] & _0388_;
- assign _0389_ = ~ perm_attr[3];
- assign _0390_ = r0[6] | _0389_;
- assign _0391_ = r0[1] & perm_attr[4];
- assign _0392_ = perm_attr[5] | _0391_;
- assign perm_ok = _0390_ & _0392_;
- assign _0393_ = r0[3] | perm_attr[2];
- assign _0394_ = valid_ra & rc_ok;
- assign _0395_ = _0394_ & perm_ok;
- assign _0396_ = { r0[1], _0393_, _0386_ } == 3'h5;
- assign _0397_ = { r0[1], _0393_, _0386_ } == 3'h4;
- assign _0398_ = { r0[1], _0393_, _0386_ } == 3'h6;
- assign _0399_ = { r0[1], _0393_, _0386_ } == 3'h1;
- assign _0400_ = { r0[1], _0393_, _0386_ } == 3'h0;
- assign _0401_ = { r0[1], _0393_, _0386_ } == 3'h2;
- assign _0402_ = { r0[1], _0393_, _0386_ } == 3'h3;
- assign _0403_ = { r0[1], _0393_, _0386_ } == 3'h7;
- function [2:0] \12974 ;
- input [2:0] a;
- input [23:0] b;
- input [7:0] s;
- (* parallel_case *)
- casez (s)
- 8'b???????1:
- \12974 = b[2:0];
- 8'b??????1?:
- \12974 = b[5:3];
- 8'b?????1??:
- \12974 = b[8:6];
- 8'b????1???:
- \12974 = b[11:9];
- 8'b???1????:
- \12974 = b[14:12];
- 8'b??1?????:
- \12974 = b[17:15];
- 8'b?1??????:
- \12974 = b[20:18];
- 8'b1???????:
- \12974 = b[23:21];
- default:
- \12974 = a;
- endcase
- endfunction
- assign _0404_ = \12974 (3'h0, 24'h93fcd1, { _0403_, _0402_, _0401_, _0400_, _0399_, _0398_, _0397_, _0396_ });
- assign _0405_ = _0395_ ? _0404_ : 3'h5;
- assign req_op = _0337_ ? _0405_ : 3'h0;
- assign _0406_ = ~ _0409_;
- assign _0407_ = m_in[0] ? m_in[14:7] : d_in[17:10];
- assign early_req_row = _0406_ ? _0407_ : r0[17:10];
- assign _0408_ = _0629_[68:66] != 3'h0;
- assign _0409_ = _0408_ ? 1'h1 : 1'h0;
- assign _0410_ = r0_valid & r0[4];
- assign _0411_ = ~ reservation[0];
- assign _0412_ = r0[70:13] != reservation[58:1];
- assign _0413_ = _0411_ | _0412_;
- assign _0414_ = _0413_ ? 1'h1 : 1'h0;
- assign _0415_ = r0[1] ? 1'h0 : _0414_;
- assign _0416_ = r0[1] ? 1'h1 : 1'h0;
- assign _0417_ = r0[1] ? 1'h0 : 1'h1;
- assign cancel_store = _0410_ ? _0415_ : 1'h0;
- assign set_rsrv = _0410_ ? _0416_ : 1'h0;
- assign clear_rsrv = _0410_ ? _0417_ : 1'h0;
- assign _0418_ = rst | clear_rsrv;
- assign _0419_ = set_rsrv ? { r0[70:13], 1'h1 } : reservation;
- assign _0420_ = _0418_ ? 1'h0 : _0419_[0];
- assign _0421_ = _0418_ ? reservation[58:1] : _0419_[58:1];
- always @(posedge clk)
- reservation <= { _0421_, _0420_ };
- assign _0422_ = 1'h1 - _0508_[144];
- assign _0423_ = 1'h1 - _0508_[144];
- assign _0424_ = _0629_[64] & _0629_[65];
- assign _0425_ = _0424_ != 1'h1;
- assign _0426_ = _0629_[64] | _0629_[65];
- assign _0427_ = _0426_ & _0508_[145];
- assign _0428_ = _0427_ != 1'h1;
- assign _0429_ = ~ _0508_[143];
- assign _0430_ = _0508_[145] ? 1'h1 : 1'h0;
- assign _0431_ = _0509_[0] ? 1'h1 : _0430_;
- assign _0432_ = _0509_[0] ? { _0509_[1], 1'h1 } : 2'h0;
- assign _0433_ = _0508_[1] ? _0629_[63:0] : _1599_;
- assign _0434_ = _0629_[64] ? { 1'h1, _0433_, 1'h1 } : { 1'h0, _1599_, _0431_ };
- assign _0435_ = _0629_[65] ? 1'h1 : _0434_[0];
- assign _0436_ = _0629_[65] ? 1'h0 : _0434_[65];
- assign _0437_ = _0508_[145] ? 1'h1 : _0509_[2];
- assign _0438_ = _0509_[0] ? 2'h3 : { 1'h0, _0437_ };
- assign _0439_ = _0629_[64] ? 1'h1 : _0438_[0];
- assign _0440_ = _0629_[64] ? _0629_[63:0] : _1600_;
- assign _0441_ = _0429_ ? { _0432_, _0436_, _0434_[64:1], _0435_ } : { 3'h0, _1599_, 1'h0 };
- assign _0442_ = _0429_ ? { _1600_, 1'h0, _0509_[2] } : { _0440_, _0438_[1], _0439_ };
- assign _0443_ = _0629_[68:66] == 3'h0;
- assign _0444_ = _0508_[2] ? 64'h0000000000000000 : wishbone_in[63:0];
- assign \rams%0.wr_addr = _0443_ ? r0[17:10] : _0629_[184:177];
- assign \rams%0.wr_data = _0443_ ? r0[134:71] : _0444_;
- assign \rams%0.wr_sel = _0443_ ? r0[142:135] : 8'hff;
- assign _0445_ = _0629_[68:66] == 3'h1;
- assign _0446_ = _0445_ & wishbone_in[64];
- assign _0447_ = { 31'h00000000, _0629_[176] } == 32'd0;
- assign _0448_ = _0446_ & _0447_;
- assign _0449_ = _0448_ ? 1'h1 : 1'h0;
- assign _0450_ = req_op == 3'h6;
- assign _0451_ = { 31'h00000000, req_hit_way } == 32'd0;
- assign _0452_ = _0450_ & _0451_;
- assign _0453_ = ~ cancel_store;
- assign _0454_ = _0452_ & _0453_;
- assign _0455_ = ~ r0[2];
- assign _0456_ = _0454_ & _0455_;
- assign _0457_ = ~ _0445_;
- assign _0458_ = ~ _0460_;
- assign _0459_ = _0458_ | _0457_;
- assign \rams%0.do_write = _0456_ ? 1'h1 : _0449_;
- assign _0460_ = _0456_ ? 1'h1 : 1'h0;
- assign _0461_ = \rams%0.wr_sel [0] & \rams%0.do_write ;
- assign _0462_ = \rams%0.wr_sel [1] & \rams%0.do_write ;
- assign _0463_ = \rams%0.wr_sel [2] & \rams%0.do_write ;
- assign _0464_ = \rams%0.wr_sel [3] & \rams%0.do_write ;
- assign _0465_ = \rams%0.wr_sel [4] & \rams%0.do_write ;
- assign _0466_ = \rams%0.wr_sel [5] & \rams%0.do_write ;
- assign _0467_ = \rams%0.wr_sel [6] & \rams%0.do_write ;
- assign _0468_ = \rams%0.wr_sel [7] & \rams%0.do_write ;
- assign _0469_ = _0629_[68:66] == 3'h0;
- assign _0470_ = _0508_[2] ? 64'h0000000000000000 : wishbone_in[63:0];
- assign \rams%1.wr_addr = _0469_ ? r0[17:10] : _0629_[184:177];
- assign \rams%1.wr_data = _0469_ ? r0[134:71] : _0470_;
- assign \rams%1.wr_sel = _0469_ ? r0[142:135] : 8'hff;
- assign _0471_ = _0629_[68:66] == 3'h1;
- assign _0472_ = _0471_ & wishbone_in[64];
- assign _0473_ = { 31'h00000000, _0629_[176] } == 32'd1;
- assign _0474_ = _0472_ & _0473_;
- assign _0475_ = _0474_ ? 1'h1 : 1'h0;
- assign _0476_ = req_op == 3'h6;
- assign _0477_ = { 31'h00000000, req_hit_way } == 32'd1;
- assign _0478_ = _0476_ & _0477_;
- assign _0479_ = ~ cancel_store;
- assign _0480_ = _0478_ & _0479_;
- assign _0481_ = ~ r0[2];
- assign _0482_ = _0480_ & _0481_;
- assign _0483_ = ~ _0471_;
- assign _0484_ = ~ _0486_;
- assign _0485_ = _0484_ | _0483_;
- assign \rams%1.do_write = _0482_ ? 1'h1 : _0475_;
- assign _0486_ = _0482_ ? 1'h1 : 1'h0;
- assign _0487_ = \rams%1.wr_sel [0] & \rams%1.do_write ;
- assign _0488_ = \rams%1.wr_sel [1] & \rams%1.do_write ;
- assign _0489_ = \rams%1.wr_sel [2] & \rams%1.do_write ;
- assign _0490_ = \rams%1.wr_sel [3] & \rams%1.do_write ;
- assign _0491_ = \rams%1.wr_sel [4] & \rams%1.do_write ;
- assign _0492_ = \rams%1.wr_sel [5] & \rams%1.do_write ;
- assign _0493_ = \rams%1.wr_sel [6] & \rams%1.do_write ;
- assign _0494_ = \rams%1.wr_sel [7] & \rams%1.do_write ;
- assign _0495_ = req_op != 3'h0;
- assign _0496_ = ~ _0409_;
- assign _0497_ = _0495_ & _0496_;
- assign _0498_ = _0497_ ? { r0[146], r0[142:0] } : _0508_[143:0];
- assign _0499_ = req_op == 3'h1;
- assign _0500_ = _0499_ ? req_hit_way : _0508_[144];
- assign _0501_ = _0499_ ? 1'h1 : 1'h0;
- assign _0502_ = req_op == 3'h5;
- assign _0503_ = req_op == 3'h4;
- assign _0504_ = _0503_ ? 2'h3 : 2'h0;
- assign _0505_ = _0502_ ? 2'h1 : _0504_;
- assign _0506_ = r0[143] | r0[145];
- assign _0507_ = r0_valid & _0506_;
- always @(posedge clk)
- _0508_ <= { _0501_, _0500_, _0498_ };
- always @(posedge clk)
- _0509_ <= { _0507_, _0505_ };
- assign _0510_ = req_op == 3'h1;
- assign _0511_ = 5'h1f - r0[17:13];
- assign _0512_ = 32'd0 == { 31'h00000000, replace_way };
- assign _0513_ = 5'h1f - r0[17:13];
- assign _0514_ = 5'h1f - r0[17:13];
- assign _0515_ = _0512_ ? { _1902_, _1901_, _1900_, _1899_, _1898_, _1897_, _1896_, _1895_, _1894_, _1893_, _1892_, _1891_, _1890_, _1889_, _1888_, _1887_, _1886_, _1885_, _1884_, _1883_, _1882_, _1881_, _1880_, _1879_, _1878_, _1877_, _1876_, _1875_, _1874_, _1873_, _1872_, _1871_ } : cache_tags;
- assign _0516_ = 32'd1 == { 31'h00000000, replace_way };
- assign _0517_ = 5'h1f - r0[17:13];
- assign _0518_ = 5'h1f - r0[17:13];
- assign _0519_ = _0516_ ? { _2010_, _2009_, _2008_, _2007_, _2006_, _2005_, _2004_, _2003_, _2002_, _2001_, _2000_, _1999_, _1998_, _1997_, _1996_, _1995_, _1994_, _1993_, _1992_, _1991_, _1990_, _1989_, _1988_, _1987_, _1986_, _1985_, _1984_, _1983_, _1982_, _1981_, _1980_, _1979_ } : _0515_;
- assign _0520_ = req_op == 3'h2;
- assign _0521_ = req_op == 3'h3;
- assign _0522_ = ~ r0[2];
- assign _0523_ = ~ cancel_store;
- assign _0524_ = _0523_ ? 1'h0 : 1'h1;
- assign _0525_ = _0523_ ? 3'h3 : 3'h0;
- assign _0526_ = _0523_ ? 2'h3 : _0629_[166:165];
- assign _0527_ = _0523_ ? 1'h1 : _0629_[175];
- assign _0528_ = req_op == 3'h6;
- assign _0529_ = 5'h1f - r0[17:13];
- assign _0530_ = 32'd0 == { 31'h00000000, replace_way };
- assign _0531_ = 5'h1f - r0[17:13];
- assign _0532_ = 5'h1f - r0[17:13];
- assign _0533_ = _0530_ ? { _2312_, _2311_, _2310_, _2309_, _2308_, _2307_, _2306_, _2305_, _2304_, _2303_, _2302_, _2301_, _2300_, _2299_, _2298_, _2297_, _2296_, _2295_, _2294_, _2293_, _2292_, _2291_, _2290_, _2289_, _2288_, _2287_, _2286_, _2285_, _2284_, _2283_, _2282_, _2281_ } : cache_tags;
- assign _0534_ = 32'd1 == { 31'h00000000, replace_way };
- assign _0535_ = 5'h1f - r0[17:13];
- assign _0536_ = 5'h1f - r0[17:13];
- assign _0537_ = _0534_ ? { _2420_, _2419_, _2418_, _2417_, _2416_, _2415_, _2414_, _2413_, _2412_, _2411_, _2410_, _2409_, _2408_, _2407_, _2406_, _2405_, _2404_, _2403_, _2402_, _2401_, _2400_, _2399_, _2398_, _2397_, _2396_, _2395_, _2394_, _2393_, _2392_, _2391_, _2390_, _2389_ } : _0533_;
- assign _0538_ = _0528_ ? cache_tags : _0537_;
- assign _0539_ = _0528_ ? cache_valids : { _2204_, _2203_, _2202_, _2201_, _2200_, _2199_, _2198_, _2197_, _2196_, _2195_, _2194_, _2193_, _2192_, _2191_, _2190_, _2189_, _2188_, _2187_, _2186_, _2185_, _2184_, _2183_, _2182_, _2181_, _2180_, _2179_, _2178_, _2177_, _2176_, _2175_, _2174_, _2173_, _2172_, _2171_, _2170_, _2169_, _2168_, _2167_, _2166_, _2165_, _2164_, _2163_, _2162_, _2161_, _2160_, _2159_, _2158_, _2157_, _2156_, _2155_, _2154_, _2153_, _2152_, _2151_, _2150_, _2149_, _2148_, _2147_, _2146_, _2145_, _2144_, _2143_, _2142_, _2141_ };
- assign _0540_ = _0528_ ? req_hit_way : replace_way;
- assign _0541_ = _0522_ ? cache_tags : _0538_;
- assign _0542_ = _0522_ ? cache_valids : _0539_;
- assign _0543_ = _0522_ ? _0524_ : 1'h0;
- assign _0544_ = _0522_ ? { _0527_, r0[142:135], _0526_, r0[134:71], ra[31:3], 3'h0, _0525_ } : { 75'h7ff0000000000000000, ra[31:6], 9'h001 };
- assign _0545_ = _0522_ ? _0629_[189:176] : { r0[17:13], ra[10:6], 3'h0, _0540_ };
- assign _0546_ = req_op == 3'h6;
- assign _0547_ = req_op == 3'h7;
- assign _0548_ = _0546_ | _0547_;
- assign _0549_ = req_op == 3'h0;
- assign _0550_ = req_op == 3'h4;
- assign _0551_ = req_op == 3'h5;
- function [2879:0] \13588 ;
- input [2879:0] a;
- input [20159:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13588 = b[2879:0];
- 7'b?????1?:
- \13588 = b[5759:2880];
- 7'b????1??:
- \13588 = b[8639:5760];
- 7'b???1???:
- \13588 = b[11519:8640];
- 7'b??1????:
- \13588 = b[14399:11520];
- 7'b?1?????:
- \13588 = b[17279:14400];
- 7'b1??????:
- \13588 = b[20159:17280];
- default:
- \13588 = a;
- endcase
- endfunction
- assign _0552_ = \13588 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, cache_tags, cache_tags, _0541_, cache_tags, _0519_, cache_tags }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [63:0] \13590 ;
- input [63:0] a;
- input [447:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13590 = b[63:0];
- 7'b?????1?:
- \13590 = b[127:64];
- 7'b????1??:
- \13590 = b[191:128];
- 7'b???1???:
- \13590 = b[255:192];
- 7'b??1????:
- \13590 = b[319:256];
- 7'b?1?????:
- \13590 = b[383:320];
- 7'b1??????:
- \13590 = b[447:384];
- default:
- \13590 = a;
- endcase
- endfunction
- assign _0553_ = \13590 (64'hxxxxxxxxxxxxxxxx, { cache_valids, cache_valids, cache_valids, _0542_, cache_valids, _1794_, _1793_, _1792_, _1791_, _1790_, _1789_, _1788_, _1787_, _1786_, _1785_, _1784_, _1783_, _1782_, _1781_, _1780_, _1779_, _1778_, _1777_, _1776_, _1775_, _1774_, _1773_, _1772_, _1771_, _1770_, _1769_, _1768_, _1767_, _1766_, _1765_, _1764_, _1763_, _1762_, _1761_, _1760_, _1759_, _1758_, _1757_, _1756_, _1755_, _1754_, _1753_, _1752_, _1751_, _1750_, _1749_, _1748_, _1747_, _1746_, _1745_, _1744_, _1743_, _1742_, _1741_, _1740_, _1739_, _1738_, _1737_, _1736_, _1735_, _1734_, _1733_, _1732_, _1731_, cache_valids }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [0:0] \13592 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13592 = b[0:0];
- 7'b?????1?:
- \13592 = b[1:1];
- 7'b????1??:
- \13592 = b[2:2];
- 7'b???1???:
- \13592 = b[3:3];
- 7'b??1????:
- \13592 = b[4:4];
- 7'b?1?????:
- \13592 = b[5:5];
- 7'b1??????:
- \13592 = b[6:6];
- default:
- \13592 = a;
- endcase
- endfunction
- assign _0554_ = \13592 (1'hx, { 3'h0, _0543_, 3'h0 }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [2:0] \13596 ;
- input [2:0] a;
- input [20:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13596 = b[2:0];
- 7'b?????1?:
- \13596 = b[5:3];
- 7'b????1??:
- \13596 = b[8:6];
- 7'b???1???:
- \13596 = b[11:9];
- 7'b??1????:
- \13596 = b[14:12];
- 7'b?1?????:
- \13596 = b[17:15];
- 7'b1??????:
- \13596 = b[20:18];
- default:
- \13596 = a;
- endcase
- endfunction
- assign _0555_ = \13596 (3'hx, { _0629_[68:66], _0629_[68:66], _0629_[68:66], _0544_[2:0], 6'h21, _0629_[68:66] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [31:0] \13600 ;
- input [31:0] a;
- input [223:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13600 = b[31:0];
- 7'b?????1?:
- \13600 = b[63:32];
- 7'b????1??:
- \13600 = b[95:64];
- 7'b???1???:
- \13600 = b[127:96];
- 7'b??1????:
- \13600 = b[159:128];
- 7'b?1?????:
- \13600 = b[191:160];
- 7'b1??????:
- \13600 = b[223:192];
- default:
- \13600 = a;
- endcase
- endfunction
- assign _0556_ = \13600 (32'hxxxxxxxx, { _0629_[100:69], _0629_[100:69], _0629_[100:69], _0544_[34:3], ra[31:3], 3'h0, ra[31:6], 6'h00, _0629_[100:69] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [63:0] \13604 ;
- input [63:0] a;
- input [447:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13604 = b[63:0];
- 7'b?????1?:
- \13604 = b[127:64];
- 7'b????1??:
- \13604 = b[191:128];
- 7'b???1???:
- \13604 = b[255:192];
- 7'b??1????:
- \13604 = b[319:256];
- 7'b?1?????:
- \13604 = b[383:320];
- 7'b1??????:
- \13604 = b[447:384];
- default:
- \13604 = a;
- endcase
- endfunction
- assign _0557_ = \13604 (64'hxxxxxxxxxxxxxxxx, { _0629_[164:101], _0629_[164:101], _0629_[164:101], _0544_[98:35], _0629_[164:101], _0629_[164:101], _0629_[164:101] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [0:0] \13608 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13608 = b[0:0];
- 7'b?????1?:
- \13608 = b[1:1];
- 7'b????1??:
- \13608 = b[2:2];
- 7'b???1???:
- \13608 = b[3:3];
- 7'b??1????:
- \13608 = b[4:4];
- 7'b?1?????:
- \13608 = b[5:5];
- 7'b1??????:
- \13608 = b[6:6];
- default:
- \13608 = a;
- endcase
- endfunction
- assign _0558_ = \13608 (1'hx, { _0629_[165], _0629_[165], _0629_[165], _0544_[99], 2'h3, _0629_[165] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [0:0] \13612 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13612 = b[0:0];
- 7'b?????1?:
- \13612 = b[1:1];
- 7'b????1??:
- \13612 = b[2:2];
- 7'b???1???:
- \13612 = b[3:3];
- 7'b??1????:
- \13612 = b[4:4];
- 7'b?1?????:
- \13612 = b[5:5];
- 7'b1??????:
- \13612 = b[6:6];
- default:
- \13612 = a;
- endcase
- endfunction
- assign _0559_ = \13612 (1'hx, { _0629_[166], _0629_[166], _0629_[166], _0544_[100], 2'h3, _0629_[166] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [7:0] \13616 ;
- input [7:0] a;
- input [55:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13616 = b[7:0];
- 7'b?????1?:
- \13616 = b[15:8];
- 7'b????1??:
- \13616 = b[23:16];
- 7'b???1???:
- \13616 = b[31:24];
- 7'b??1????:
- \13616 = b[39:32];
- 7'b?1?????:
- \13616 = b[47:40];
- 7'b1??????:
- \13616 = b[55:48];
- default:
- \13616 = a;
- endcase
- endfunction
- assign _0560_ = \13616 (8'hxx, { _0629_[174:167], _0629_[174:167], _0629_[174:167], _0544_[108:101], r0[142:135], 8'hff, _0629_[174:167] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [0:0] \13620 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13620 = b[0:0];
- 7'b?????1?:
- \13620 = b[1:1];
- 7'b????1??:
- \13620 = b[2:2];
- 7'b???1???:
- \13620 = b[3:3];
- 7'b??1????:
- \13620 = b[4:4];
- 7'b?1?????:
- \13620 = b[5:5];
- 7'b1??????:
- \13620 = b[6:6];
- default:
- \13620 = a;
- endcase
- endfunction
- assign _0561_ = \13620 (1'hx, { _0629_[175], _0629_[175], _0629_[175], _0544_[109], 2'h0, _0629_[175] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [0:0] \13624 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13624 = b[0:0];
- 7'b?????1?:
- \13624 = b[1:1];
- 7'b????1??:
- \13624 = b[2:2];
- 7'b???1???:
- \13624 = b[3:3];
- 7'b??1????:
- \13624 = b[4:4];
- 7'b?1?????:
- \13624 = b[5:5];
- 7'b1??????:
- \13624 = b[6:6];
- default:
- \13624 = a;
- endcase
- endfunction
- assign _0562_ = \13624 (1'hx, { _0629_[176], _0629_[176], _0629_[176], _0545_[0], _0629_[176], replace_way, _0629_[176] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [7:0] \13628 ;
- input [7:0] a;
- input [55:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13628 = b[7:0];
- 7'b?????1?:
- \13628 = b[15:8];
- 7'b????1??:
- \13628 = b[23:16];
- 7'b???1???:
- \13628 = b[31:24];
- 7'b??1????:
- \13628 = b[39:32];
- 7'b?1?????:
- \13628 = b[47:40];
- 7'b1??????:
- \13628 = b[55:48];
- default:
- \13628 = a;
- endcase
- endfunction
- assign _0563_ = \13628 (8'hxx, { _0629_[184:177], _0629_[184:177], _0629_[184:177], _0545_[8:1], _0629_[184:177], ra[10:6], 3'h0, _0629_[184:177] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- function [4:0] \13632 ;
- input [4:0] a;
- input [34:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \13632 = b[4:0];
- 7'b?????1?:
- \13632 = b[9:5];
- 7'b????1??:
- \13632 = b[14:10];
- 7'b???1???:
- \13632 = b[19:15];
- 7'b??1????:
- \13632 = b[24:20];
- 7'b?1?????:
- \13632 = b[29:25];
- 7'b1??????:
- \13632 = b[34:30];
- default:
- \13632 = a;
- endcase
- endfunction
- assign _0564_ = \13632 (5'hxx, { _0629_[189:185], _0629_[189:185], _0629_[189:185], _0545_[13:9], _0629_[189:185], r0[17:13], _0629_[189:185] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
- assign _0565_ = _0629_[68:66] == 3'h0;
- assign _0566_ = ~ _0629_[166];
- assign _0567_ = ~ wishbone_in[65];
- assign _0568_ = ~ _0566_;
- assign _0569_ = _0567_ & _0568_;
- assign _0570_ = _0629_[74:72] == 3'h7;
- assign _0571_ = _0575_ ? 1'h0 : _0629_[166];
- assign _0572_ = _0576_ ? 1'h1 : _0566_;
- assign _0573_ = _0629_[74:72] + 3'h1;
- assign _0574_ = _0569_ ? { _0629_[100:75], _0573_, _0629_[71:69] } : _0629_[100:69];
- assign _0575_ = _0569_ & _0570_;
- assign _0576_ = _0569_ & _0570_;
- assign _0577_ = { 24'h000000, _0629_[184:177] } == { 24'h000000, _0508_[17:10] };
- assign _0578_ = ~ _0508_[2];
- assign _0579_ = _0577_ & _0578_;
- assign _0580_ = _0589_ ? wishbone_in[63:0] : _0629_[63:0];
- assign _0581_ = _0629_[179:177] == 3'h7;
- assign _0582_ = _0572_ & _0581_;
- assign _0583_ = 5'h1f - _0629_[189:185];
- assign _0584_ = _0588_ ? { _2614_, _2613_, _2612_, _2611_, _2610_, _2609_, _2608_, _2607_, _2606_, _2605_, _2604_, _2603_, _2602_, _2601_, _2600_, _2599_, _2598_, _2597_, _2596_, _2595_, _2594_, _2593_, _2592_, _2591_, _2590_, _2589_, _2588_, _2587_, _2586_, _2585_, _2584_, _2583_, _2582_, _2581_, _2580_, _2579_, _2578_, _2577_, _2576_, _2575_, _2574_, _2573_, _2572_, _2571_, _2570_, _2569_, _2568_, _2567_, _2566_, _2565_, _2564_, _2563_, _2562_, _2561_, _2560_, _2559_, _2558_, _2557_, _2556_, _2555_, _2554_, _2553_, _2552_, _2551_ } : cache_valids;
- assign _0585_ = _0590_ ? 3'h2 : _0629_[68:66];
- assign _0586_ = _0591_ ? 1'h0 : _0629_[165];
- assign _0587_ = _0629_[179:177] + 3'h1;
- assign _0588_ = wishbone_in[64] & _0582_;
- assign _0589_ = wishbone_in[64] & _0579_;
- assign _0590_ = wishbone_in[64] & _0582_;
- assign _0591_ = wishbone_in[64] & _0582_;
- assign _0592_ = wishbone_in[64] ? { _0629_[184:180], _0587_ } : _0629_[184:177];
- assign _0593_ = _0629_[68:66] == 3'h1;
- assign _0594_ = _0629_[68:66] == 3'h2;
- assign _0595_ = ~ wishbone_in[65];
- assign _0596_ = _0595_ ? 1'h0 : _0629_[166];
- assign _0597_ = _0629_[68:66] == 3'h4;
- assign _0598_ = _0597_ ? wishbone_in[63:0] : _0629_[63:0];
- assign _0599_ = wishbone_in[64] ? { 1'h1, _0598_ } : { 1'h0, _0629_[63:0] };
- assign _0600_ = wishbone_in[64] ? 3'h0 : _0629_[68:66];
- assign _0601_ = wishbone_in[64] ? 2'h0 : { _0596_, _0629_[165] };
- assign _0602_ = _0629_[68:66] == 3'h3;
- assign _0603_ = _0629_[68:66] == 3'h4;
- assign _0604_ = _0602_ | _0603_;
- function [2879:0] \13797 ;
- input [2879:0] a;
- input [11519:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13797 = b[2879:0];
- 4'b??1?:
- \13797 = b[5759:2880];
- 4'b?1??:
- \13797 = b[8639:5760];
- 4'b1???:
- \13797 = b[11519:8640];
- default:
- \13797 = a;
- endcase
- endfunction
- assign _0605_ = \13797 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, cache_tags, cache_tags, _0552_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [63:0] \13799 ;
- input [63:0] a;
- input [255:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13799 = b[63:0];
- 4'b??1?:
- \13799 = b[127:64];
- 4'b?1??:
- \13799 = b[191:128];
- 4'b1???:
- \13799 = b[255:192];
- default:
- \13799 = a;
- endcase
- endfunction
- assign _0606_ = \13799 (64'hxxxxxxxxxxxxxxxx, { cache_valids, cache_valids, _0584_, _0553_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [63:0] \13803 ;
- input [63:0] a;
- input [255:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13803 = b[63:0];
- 4'b??1?:
- \13803 = b[127:64];
- 4'b?1??:
- \13803 = b[191:128];
- 4'b1???:
- \13803 = b[255:192];
- default:
- \13803 = a;
- endcase
- endfunction
- assign _0607_ = \13803 (64'hxxxxxxxxxxxxxxxx, { _0599_[63:0], _0629_[63:0], _0580_, _0629_[63:0] }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13806 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13806 = b[0:0];
- 4'b??1?:
- \13806 = b[1:1];
- 4'b?1??:
- \13806 = b[2:2];
- 4'b1???:
- \13806 = b[3:3];
- default:
- \13806 = a;
- endcase
- endfunction
- assign _0608_ = \13806 (1'hx, { _0599_[64], 3'h4 }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13808 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13808 = b[0:0];
- 4'b??1?:
- \13808 = b[1:1];
- 4'b?1??:
- \13808 = b[2:2];
- 4'b1???:
- \13808 = b[3:3];
- default:
- \13808 = a;
- endcase
- endfunction
- assign _0609_ = \13808 (1'hx, { 3'h0, _0554_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [2:0] \13810 ;
- input [2:0] a;
- input [11:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13810 = b[2:0];
- 4'b??1?:
- \13810 = b[5:3];
- 4'b?1??:
- \13810 = b[8:6];
- 4'b1???:
- \13810 = b[11:9];
- default:
- \13810 = a;
- endcase
- endfunction
- assign _0610_ = \13810 (3'hx, { _0600_, 3'h0, _0585_, _0555_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [31:0] \13813 ;
- input [31:0] a;
- input [127:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13813 = b[31:0];
- 4'b??1?:
- \13813 = b[63:32];
- 4'b?1??:
- \13813 = b[95:64];
- 4'b1???:
- \13813 = b[127:96];
- default:
- \13813 = a;
- endcase
- endfunction
- assign _0611_ = \13813 (32'hxxxxxxxx, { _0629_[100:69], _0629_[100:69], _0574_, _0556_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [63:0] \13816 ;
- input [63:0] a;
- input [255:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13816 = b[63:0];
- 4'b??1?:
- \13816 = b[127:64];
- 4'b?1??:
- \13816 = b[191:128];
- 4'b1???:
- \13816 = b[255:192];
- default:
- \13816 = a;
- endcase
- endfunction
- assign _0612_ = \13816 (64'hxxxxxxxxxxxxxxxx, { _0629_[164:101], _0629_[164:101], _0629_[164:101], _0557_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13820 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13820 = b[0:0];
- 4'b??1?:
- \13820 = b[1:1];
- 4'b?1??:
- \13820 = b[2:2];
- 4'b1???:
- \13820 = b[3:3];
- default:
- \13820 = a;
- endcase
- endfunction
- assign _0613_ = \13820 (1'hx, { _0601_[0], _0629_[165], _0586_, _0558_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13824 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13824 = b[0:0];
- 4'b??1?:
- \13824 = b[1:1];
- 4'b?1??:
- \13824 = b[2:2];
- 4'b1???:
- \13824 = b[3:3];
- default:
- \13824 = a;
- endcase
- endfunction
- assign _0614_ = \13824 (1'hx, { _0601_[1], _0629_[166], _0571_, _0559_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [7:0] \13827 ;
- input [7:0] a;
- input [31:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13827 = b[7:0];
- 4'b??1?:
- \13827 = b[15:8];
- 4'b?1??:
- \13827 = b[23:16];
- 4'b1???:
- \13827 = b[31:24];
- default:
- \13827 = a;
- endcase
- endfunction
- assign _0615_ = \13827 (8'hxx, { _0629_[174:167], _0629_[174:167], _0629_[174:167], _0560_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13830 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13830 = b[0:0];
- 4'b??1?:
- \13830 = b[1:1];
- 4'b?1??:
- \13830 = b[2:2];
- 4'b1???:
- \13830 = b[3:3];
- default:
- \13830 = a;
- endcase
- endfunction
- assign _0616_ = \13830 (1'hx, { _0629_[175], _0629_[175], _0629_[175], _0561_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [0:0] \13833 ;
- input [0:0] a;
- input [3:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13833 = b[0:0];
- 4'b??1?:
- \13833 = b[1:1];
- 4'b?1??:
- \13833 = b[2:2];
- 4'b1???:
- \13833 = b[3:3];
- default:
- \13833 = a;
- endcase
- endfunction
- assign _0617_ = \13833 (1'hx, { _0629_[176], _0629_[176], _0629_[176], _0562_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [7:0] \13836 ;
- input [7:0] a;
- input [31:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13836 = b[7:0];
- 4'b??1?:
- \13836 = b[15:8];
- 4'b?1??:
- \13836 = b[23:16];
- 4'b1???:
- \13836 = b[31:24];
- default:
- \13836 = a;
- endcase
- endfunction
- assign _0618_ = \13836 (8'hxx, { _0629_[184:177], _0629_[184:177], _0592_, _0563_ }, { _0604_, _0594_, _0593_, _0565_ });
- function [4:0] \13839 ;
- input [4:0] a;
- input [19:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \13839 = b[4:0];
- 4'b??1?:
- \13839 = b[9:5];
- 4'b?1??:
- \13839 = b[14:10];
- 4'b1???:
- \13839 = b[19:15];
- default:
- \13839 = a;
- endcase
- endfunction
- assign _0619_ = \13839 (5'hxx, { _0629_[189:185], _0629_[189:185], _0629_[189:185], _0564_ }, { _0604_, _0594_, _0593_, _0565_ });
- assign _0620_ = rst ? cache_tags : _0605_;
- assign _0621_ = rst ? 64'h0000000000000000 : _0606_;
- assign _0622_ = rst ? _0629_[63:0] : _0607_;
- assign _0623_ = rst ? 1'h0 : _0608_;
- assign _0624_ = rst ? _0629_[65] : _0609_;
- assign _0625_ = rst ? 35'h000000000 : { _0611_, _0610_ };
- assign _0626_ = rst ? _0629_[164:101] : _0612_;
- assign _0627_ = rst ? 2'h0 : { _0614_, _0613_ };
- assign _0628_ = rst ? _0629_[189:167] : { _0619_, _0618_, _0617_, _0616_, _0615_ };
- always @(posedge clk)
- cache_tags <= _0620_;
- always @(posedge clk)
- cache_valids <= _0621_;
- always @(posedge clk)
- _0629_ <= { _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_ };
- (* ram_style = "distributed" *)
- reg [91:0] \13892 [63:0];
- reg [91:0] _3675_;
- always @(posedge clk) begin
- _3675_ <= \13892 [_0018_];
- if (_0170_) \13892 [r0[24:19]] <= { _1064_, _1063_ };
- end
- assign tlb_tag_way = _3675_;
- (* ram_style = "distributed" *)
- reg [127:0] \13896 [63:0];
- reg [127:0] _3676_;
- always @(posedge clk) begin
- _3676_ <= \13896 [_0018_];
- if (_0174_) \13896 [r0[24:19]] <= { _1067_, _1066_ };
- end
- assign tlb_pte_way = _3676_;
- assign _0653_ = tlb_hit_way ? tlb_pte_way[127:64] : tlb_pte_way[63:0];
- assign _0654_ = ~ _0159_[5];
- assign _0655_ = ~ _0159_[4];
- assign _0656_ = _0654_ & _0655_;
- assign _0657_ = _0654_ & _0159_[4];
- assign _0658_ = _0159_[5] & _0655_;
- assign _0659_ = _0159_[5] & _0159_[4];
- assign _0660_ = ~ _0159_[3];
- assign _0661_ = _0656_ & _0660_;
- assign _0662_ = _0656_ & _0159_[3];
- assign _0663_ = _0657_ & _0660_;
- assign _0664_ = _0657_ & _0159_[3];
- assign _0665_ = _0658_ & _0660_;
- assign _0666_ = _0658_ & _0159_[3];
- assign _0667_ = _0659_ & _0660_;
- assign _0668_ = _0659_ & _0159_[3];
- assign _0669_ = ~ _0159_[2];
- assign _0670_ = _0661_ & _0669_;
- assign _0671_ = _0661_ & _0159_[2];
- assign _0672_ = _0662_ & _0669_;
- assign _0673_ = _0662_ & _0159_[2];
- assign _0674_ = _0663_ & _0669_;
- assign _0675_ = _0663_ & _0159_[2];
- assign _0676_ = _0664_ & _0669_;
- assign _0677_ = _0664_ & _0159_[2];
- assign _0678_ = _0665_ & _0669_;
- assign _0679_ = _0665_ & _0159_[2];
- assign _0680_ = _0666_ & _0669_;
- assign _0681_ = _0666_ & _0159_[2];
- assign _0682_ = _0667_ & _0669_;
- assign _0683_ = _0667_ & _0159_[2];
- assign _0684_ = _0668_ & _0669_;
- assign _0685_ = _0668_ & _0159_[2];
- assign _0686_ = ~ _0159_[1];
- assign _0687_ = _0670_ & _0686_;
- assign _0688_ = _0670_ & _0159_[1];
- assign _0689_ = _0671_ & _0686_;
- assign _0690_ = _0671_ & _0159_[1];
- assign _0691_ = _0672_ & _0686_;
- assign _0692_ = _0672_ & _0159_[1];
- assign _0693_ = _0673_ & _0686_;
- assign _0694_ = _0673_ & _0159_[1];
- assign _0695_ = _0674_ & _0686_;
- assign _0696_ = _0674_ & _0159_[1];
- assign _0697_ = _0675_ & _0686_;
- assign _0698_ = _0675_ & _0159_[1];
- assign _0699_ = _0676_ & _0686_;
- assign _0700_ = _0676_ & _0159_[1];
- assign _0701_ = _0677_ & _0686_;
- assign _0702_ = _0677_ & _0159_[1];
- assign _0703_ = _0678_ & _0686_;
- assign _0704_ = _0678_ & _0159_[1];
- assign _0705_ = _0679_ & _0686_;
- assign _0706_ = _0679_ & _0159_[1];
- assign _0707_ = _0680_ & _0686_;
- assign _0708_ = _0680_ & _0159_[1];
- assign _0709_ = _0681_ & _0686_;
- assign _0710_ = _0681_ & _0159_[1];
- assign _0711_ = _0682_ & _0686_;
- assign _0712_ = _0682_ & _0159_[1];
- assign _0713_ = _0683_ & _0686_;
- assign _0714_ = _0683_ & _0159_[1];
- assign _0715_ = _0684_ & _0686_;
- assign _0716_ = _0684_ & _0159_[1];
- assign _0717_ = _0685_ & _0686_;
- assign _0718_ = _0685_ & _0159_[1];
- assign _0719_ = ~ _0159_[0];
- assign _0720_ = _0687_ & _0719_;
- assign _0721_ = _0687_ & _0159_[0];
- assign _0722_ = _0688_ & _0719_;
- assign _0723_ = _0688_ & _0159_[0];
- assign _0724_ = _0689_ & _0719_;
- assign _0725_ = _0689_ & _0159_[0];
- assign _0726_ = _0690_ & _0719_;
- assign _0727_ = _0690_ & _0159_[0];
- assign _0728_ = _0691_ & _0719_;
- assign _0729_ = _0691_ & _0159_[0];
- assign _0730_ = _0692_ & _0719_;
- assign _0731_ = _0692_ & _0159_[0];
- assign _0732_ = _0693_ & _0719_;
- assign _0733_ = _0693_ & _0159_[0];
- assign _0734_ = _0694_ & _0719_;
- assign _0735_ = _0694_ & _0159_[0];
- assign _0736_ = _0695_ & _0719_;
- assign _0737_ = _0695_ & _0159_[0];
- assign _0738_ = _0696_ & _0719_;
- assign _0739_ = _0696_ & _0159_[0];
- assign _0740_ = _0697_ & _0719_;
- assign _0741_ = _0697_ & _0159_[0];
- assign _0742_ = _0698_ & _0719_;
- assign _0743_ = _0698_ & _0159_[0];
- assign _0744_ = _0699_ & _0719_;
- assign _0745_ = _0699_ & _0159_[0];
- assign _0746_ = _0700_ & _0719_;
- assign _0747_ = _0700_ & _0159_[0];
- assign _0748_ = _0701_ & _0719_;
- assign _0749_ = _0701_ & _0159_[0];
- assign _0750_ = _0702_ & _0719_;
- assign _0751_ = _0702_ & _0159_[0];
- assign _0752_ = _0703_ & _0719_;
- assign _0753_ = _0703_ & _0159_[0];
- assign _0754_ = _0704_ & _0719_;
- assign _0755_ = _0704_ & _0159_[0];
- assign _0756_ = _0705_ & _0719_;
- assign _0757_ = _0705_ & _0159_[0];
- assign _0758_ = _0706_ & _0719_;
- assign _0759_ = _0706_ & _0159_[0];
- assign _0760_ = _0707_ & _0719_;
- assign _0761_ = _0707_ & _0159_[0];
- assign _0762_ = _0708_ & _0719_;
- assign _0763_ = _0708_ & _0159_[0];
- assign _0764_ = _0709_ & _0719_;
- assign _0765_ = _0709_ & _0159_[0];
- assign _0766_ = _0710_ & _0719_;
- assign _0767_ = _0710_ & _0159_[0];
- assign _0768_ = _0711_ & _0719_;
- assign _0769_ = _0711_ & _0159_[0];
- assign _0770_ = _0712_ & _0719_;
- assign _0771_ = _0712_ & _0159_[0];
- assign _0772_ = _0713_ & _0719_;
- assign _0773_ = _0713_ & _0159_[0];
- assign _0774_ = _0714_ & _0719_;
- assign _0775_ = _0714_ & _0159_[0];
- assign _0776_ = _0715_ & _0719_;
- assign _0777_ = _0715_ & _0159_[0];
- assign _0778_ = _0716_ & _0719_;
- assign _0779_ = _0716_ & _0159_[0];
- assign _0780_ = _0717_ & _0719_;
- assign _0781_ = _0717_ & _0159_[0];
- assign _0782_ = _0718_ & _0719_;
- assign _0783_ = _0718_ & _0159_[0];
- assign _0784_ = ~ tlb_hit_way;
- assign _0785_ = _0720_ & _0784_;
- assign _0786_ = _0720_ & tlb_hit_way;
- assign _0787_ = _0721_ & _0784_;
- assign _0788_ = _0721_ & tlb_hit_way;
- assign _0789_ = _0722_ & _0784_;
- assign _0790_ = _0722_ & tlb_hit_way;
- assign _0791_ = _0723_ & _0784_;
- assign _0792_ = _0723_ & tlb_hit_way;
- assign _0793_ = _0724_ & _0784_;
- assign _0794_ = _0724_ & tlb_hit_way;
- assign _0795_ = _0725_ & _0784_;
- assign _0796_ = _0725_ & tlb_hit_way;
- assign _0797_ = _0726_ & _0784_;
- assign _0798_ = _0726_ & tlb_hit_way;
- assign _0799_ = _0727_ & _0784_;
- assign _0800_ = _0727_ & tlb_hit_way;
- assign _0801_ = _0728_ & _0784_;
- assign _0802_ = _0728_ & tlb_hit_way;
- assign _0803_ = _0729_ & _0784_;
- assign _0804_ = _0729_ & tlb_hit_way;
- assign _0805_ = _0730_ & _0784_;
- assign _0806_ = _0730_ & tlb_hit_way;
- assign _0807_ = _0731_ & _0784_;
- assign _0808_ = _0731_ & tlb_hit_way;
- assign _0809_ = _0732_ & _0784_;
- assign _0810_ = _0732_ & tlb_hit_way;
- assign _0811_ = _0733_ & _0784_;
- assign _0812_ = _0733_ & tlb_hit_way;
- assign _0813_ = _0734_ & _0784_;
- assign _0814_ = _0734_ & tlb_hit_way;
- assign _0815_ = _0735_ & _0784_;
- assign _0816_ = _0735_ & tlb_hit_way;
- assign _0817_ = _0736_ & _0784_;
- assign _0818_ = _0736_ & tlb_hit_way;
- assign _0819_ = _0737_ & _0784_;
- assign _0820_ = _0737_ & tlb_hit_way;
- assign _0821_ = _0738_ & _0784_;
- assign _0822_ = _0738_ & tlb_hit_way;
- assign _0823_ = _0739_ & _0784_;
- assign _0824_ = _0739_ & tlb_hit_way;
- assign _0825_ = _0740_ & _0784_;
- assign _0826_ = _0740_ & tlb_hit_way;
- assign _0827_ = _0741_ & _0784_;
- assign _0828_ = _0741_ & tlb_hit_way;
- assign _0829_ = _0742_ & _0784_;
- assign _0830_ = _0742_ & tlb_hit_way;
- assign _0831_ = _0743_ & _0784_;
- assign _0832_ = _0743_ & tlb_hit_way;
- assign _0833_ = _0744_ & _0784_;
- assign _0834_ = _0744_ & tlb_hit_way;
- assign _0835_ = _0745_ & _0784_;
- assign _0836_ = _0745_ & tlb_hit_way;
- assign _0837_ = _0746_ & _0784_;
- assign _0838_ = _0746_ & tlb_hit_way;
- assign _0839_ = _0747_ & _0784_;
- assign _0840_ = _0747_ & tlb_hit_way;
- assign _0841_ = _0748_ & _0784_;
- assign _0842_ = _0748_ & tlb_hit_way;
- assign _0843_ = _0749_ & _0784_;
- assign _0844_ = _0749_ & tlb_hit_way;
- assign _0845_ = _0750_ & _0784_;
- assign _0846_ = _0750_ & tlb_hit_way;
- assign _0847_ = _0751_ & _0784_;
- assign _0848_ = _0751_ & tlb_hit_way;
- assign _0849_ = _0752_ & _0784_;
- assign _0850_ = _0752_ & tlb_hit_way;
- assign _0851_ = _0753_ & _0784_;
- assign _0852_ = _0753_ & tlb_hit_way;
- assign _0853_ = _0754_ & _0784_;
- assign _0854_ = _0754_ & tlb_hit_way;
- assign _0855_ = _0755_ & _0784_;
- assign _0856_ = _0755_ & tlb_hit_way;
- assign _0857_ = _0756_ & _0784_;
- assign _0858_ = _0756_ & tlb_hit_way;
- assign _0859_ = _0757_ & _0784_;
- assign _0860_ = _0757_ & tlb_hit_way;
- assign _0861_ = _0758_ & _0784_;
- assign _0862_ = _0758_ & tlb_hit_way;
- assign _0863_ = _0759_ & _0784_;
- assign _0864_ = _0759_ & tlb_hit_way;
- assign _0865_ = _0760_ & _0784_;
- assign _0866_ = _0760_ & tlb_hit_way;
- assign _0867_ = _0761_ & _0784_;
- assign _0868_ = _0761_ & tlb_hit_way;
- assign _0869_ = _0762_ & _0784_;
- assign _0870_ = _0762_ & tlb_hit_way;
- assign _0871_ = _0763_ & _0784_;
- assign _0872_ = _0763_ & tlb_hit_way;
- assign _0873_ = _0764_ & _0784_;
- assign _0874_ = _0764_ & tlb_hit_way;
- assign _0875_ = _0765_ & _0784_;
- assign _0876_ = _0765_ & tlb_hit_way;
- assign _0877_ = _0766_ & _0784_;
- assign _0878_ = _0766_ & tlb_hit_way;
- assign _0879_ = _0767_ & _0784_;
- assign _0880_ = _0767_ & tlb_hit_way;
- assign _0881_ = _0768_ & _0784_;
- assign _0882_ = _0768_ & tlb_hit_way;
- assign _0883_ = _0769_ & _0784_;
- assign _0884_ = _0769_ & tlb_hit_way;
- assign _0885_ = _0770_ & _0784_;
- assign _0886_ = _0770_ & tlb_hit_way;
- assign _0887_ = _0771_ & _0784_;
- assign _0888_ = _0771_ & tlb_hit_way;
- assign _0889_ = _0772_ & _0784_;
- assign _0890_ = _0772_ & tlb_hit_way;
- assign _0891_ = _0773_ & _0784_;
- assign _0892_ = _0773_ & tlb_hit_way;
- assign _0893_ = _0774_ & _0784_;
- assign _0894_ = _0774_ & tlb_hit_way;
- assign _0895_ = _0775_ & _0784_;
- assign _0896_ = _0775_ & tlb_hit_way;
- assign _0897_ = _0776_ & _0784_;
- assign _0898_ = _0776_ & tlb_hit_way;
- assign _0899_ = _0777_ & _0784_;
- assign _0900_ = _0777_ & tlb_hit_way;
- assign _0901_ = _0778_ & _0784_;
- assign _0902_ = _0778_ & tlb_hit_way;
- assign _0903_ = _0779_ & _0784_;
- assign _0904_ = _0779_ & tlb_hit_way;
- assign _0905_ = _0780_ & _0784_;
- assign _0906_ = _0780_ & tlb_hit_way;
- assign _0907_ = _0781_ & _0784_;
- assign _0908_ = _0781_ & tlb_hit_way;
- assign _0909_ = _0782_ & _0784_;
- assign _0910_ = _0782_ & tlb_hit_way;
- assign _0911_ = _0783_ & _0784_;
- assign _0912_ = _0783_ & tlb_hit_way;
- assign _0913_ = _0785_ ? 1'h0 : dtlb_valids[0];
- assign _0914_ = _0786_ ? 1'h0 : dtlb_valids[1];
- assign _0915_ = _0787_ ? 1'h0 : dtlb_valids[2];
- assign _0916_ = _0788_ ? 1'h0 : dtlb_valids[3];
- assign _0917_ = _0789_ ? 1'h0 : dtlb_valids[4];
- assign _0918_ = _0790_ ? 1'h0 : dtlb_valids[5];
- assign _0919_ = _0791_ ? 1'h0 : dtlb_valids[6];
- assign _0920_ = _0792_ ? 1'h0 : dtlb_valids[7];
- assign _0921_ = _0793_ ? 1'h0 : dtlb_valids[8];
- assign _0922_ = _0794_ ? 1'h0 : dtlb_valids[9];
- assign _0923_ = _0795_ ? 1'h0 : dtlb_valids[10];
- assign _0924_ = _0796_ ? 1'h0 : dtlb_valids[11];
- assign _0925_ = _0797_ ? 1'h0 : dtlb_valids[12];
- assign _0926_ = _0798_ ? 1'h0 : dtlb_valids[13];
- assign _0927_ = _0799_ ? 1'h0 : dtlb_valids[14];
- assign _0928_ = _0800_ ? 1'h0 : dtlb_valids[15];
- assign _0929_ = _0801_ ? 1'h0 : dtlb_valids[16];
- assign _0930_ = _0802_ ? 1'h0 : dtlb_valids[17];
- assign _0931_ = _0803_ ? 1'h0 : dtlb_valids[18];
- assign _0932_ = _0804_ ? 1'h0 : dtlb_valids[19];
- assign _0933_ = _0805_ ? 1'h0 : dtlb_valids[20];
- assign _0934_ = _0806_ ? 1'h0 : dtlb_valids[21];
- assign _0935_ = _0807_ ? 1'h0 : dtlb_valids[22];
- assign _0936_ = _0808_ ? 1'h0 : dtlb_valids[23];
- assign _0937_ = _0809_ ? 1'h0 : dtlb_valids[24];
- assign _0938_ = _0810_ ? 1'h0 : dtlb_valids[25];
- assign _0939_ = _0811_ ? 1'h0 : dtlb_valids[26];
- assign _0940_ = _0812_ ? 1'h0 : dtlb_valids[27];
- assign _0941_ = _0813_ ? 1'h0 : dtlb_valids[28];
- assign _0942_ = _0814_ ? 1'h0 : dtlb_valids[29];
- assign _0943_ = _0815_ ? 1'h0 : dtlb_valids[30];
- assign _0944_ = _0816_ ? 1'h0 : dtlb_valids[31];
- assign _0945_ = _0817_ ? 1'h0 : dtlb_valids[32];
- assign _0946_ = _0818_ ? 1'h0 : dtlb_valids[33];
- assign _0947_ = _0819_ ? 1'h0 : dtlb_valids[34];
- assign _0948_ = _0820_ ? 1'h0 : dtlb_valids[35];
- assign _0949_ = _0821_ ? 1'h0 : dtlb_valids[36];
- assign _0950_ = _0822_ ? 1'h0 : dtlb_valids[37];
- assign _0951_ = _0823_ ? 1'h0 : dtlb_valids[38];
- assign _0952_ = _0824_ ? 1'h0 : dtlb_valids[39];
- assign _0953_ = _0825_ ? 1'h0 : dtlb_valids[40];
- assign _0954_ = _0826_ ? 1'h0 : dtlb_valids[41];
- assign _0955_ = _0827_ ? 1'h0 : dtlb_valids[42];
- assign _0956_ = _0828_ ? 1'h0 : dtlb_valids[43];
- assign _0957_ = _0829_ ? 1'h0 : dtlb_valids[44];
- assign _0958_ = _0830_ ? 1'h0 : dtlb_valids[45];
- assign _0959_ = _0831_ ? 1'h0 : dtlb_valids[46];
- assign _0960_ = _0832_ ? 1'h0 : dtlb_valids[47];
- assign _0961_ = _0833_ ? 1'h0 : dtlb_valids[48];
- assign _0962_ = _0834_ ? 1'h0 : dtlb_valids[49];
- assign _0963_ = _0835_ ? 1'h0 : dtlb_valids[50];
- assign _0964_ = _0836_ ? 1'h0 : dtlb_valids[51];
- assign _0965_ = _0837_ ? 1'h0 : dtlb_valids[52];
- assign _0966_ = _0838_ ? 1'h0 : dtlb_valids[53];
- assign _0967_ = _0839_ ? 1'h0 : dtlb_valids[54];
- assign _0968_ = _0840_ ? 1'h0 : dtlb_valids[55];
- assign _0969_ = _0841_ ? 1'h0 : dtlb_valids[56];
- assign _0970_ = _0842_ ? 1'h0 : dtlb_valids[57];
- assign _0971_ = _0843_ ? 1'h0 : dtlb_valids[58];
- assign _0972_ = _0844_ ? 1'h0 : dtlb_valids[59];
- assign _0973_ = _0845_ ? 1'h0 : dtlb_valids[60];
- assign _0974_ = _0846_ ? 1'h0 : dtlb_valids[61];
- assign _0975_ = _0847_ ? 1'h0 : dtlb_valids[62];
- assign _0976_ = _0848_ ? 1'h0 : dtlb_valids[63];
- assign _0977_ = _0849_ ? 1'h0 : dtlb_valids[64];
- assign _0978_ = _0850_ ? 1'h0 : dtlb_valids[65];
- assign _0979_ = _0851_ ? 1'h0 : dtlb_valids[66];
- assign _0980_ = _0852_ ? 1'h0 : dtlb_valids[67];
- assign _0981_ = _0853_ ? 1'h0 : dtlb_valids[68];
- assign _0982_ = _0854_ ? 1'h0 : dtlb_valids[69];
- assign _0983_ = _0855_ ? 1'h0 : dtlb_valids[70];
- assign _0984_ = _0856_ ? 1'h0 : dtlb_valids[71];
- assign _0985_ = _0857_ ? 1'h0 : dtlb_valids[72];
- assign _0986_ = _0858_ ? 1'h0 : dtlb_valids[73];
- assign _0987_ = _0859_ ? 1'h0 : dtlb_valids[74];
- assign _0988_ = _0860_ ? 1'h0 : dtlb_valids[75];
- assign _0989_ = _0861_ ? 1'h0 : dtlb_valids[76];
- assign _0990_ = _0862_ ? 1'h0 : dtlb_valids[77];
- assign _0991_ = _0863_ ? 1'h0 : dtlb_valids[78];
- assign _0992_ = _0864_ ? 1'h0 : dtlb_valids[79];
- assign _0993_ = _0865_ ? 1'h0 : dtlb_valids[80];
- assign _0994_ = _0866_ ? 1'h0 : dtlb_valids[81];
- assign _0995_ = _0867_ ? 1'h0 : dtlb_valids[82];
- assign _0996_ = _0868_ ? 1'h0 : dtlb_valids[83];
- assign _0997_ = _0869_ ? 1'h0 : dtlb_valids[84];
- assign _0998_ = _0870_ ? 1'h0 : dtlb_valids[85];
- assign _0999_ = _0871_ ? 1'h0 : dtlb_valids[86];
- assign _1000_ = _0872_ ? 1'h0 : dtlb_valids[87];
- assign _1001_ = _0873_ ? 1'h0 : dtlb_valids[88];
- assign _1002_ = _0874_ ? 1'h0 : dtlb_valids[89];
- assign _1003_ = _0875_ ? 1'h0 : dtlb_valids[90];
- assign _1004_ = _0876_ ? 1'h0 : dtlb_valids[91];
- assign _1005_ = _0877_ ? 1'h0 : dtlb_valids[92];
- assign _1006_ = _0878_ ? 1'h0 : dtlb_valids[93];
- assign _1007_ = _0879_ ? 1'h0 : dtlb_valids[94];
- assign _1008_ = _0880_ ? 1'h0 : dtlb_valids[95];
- assign _1009_ = _0881_ ? 1'h0 : dtlb_valids[96];
- assign _1010_ = _0882_ ? 1'h0 : dtlb_valids[97];
- assign _1011_ = _0883_ ? 1'h0 : dtlb_valids[98];
- assign _1012_ = _0884_ ? 1'h0 : dtlb_valids[99];
- assign _1013_ = _0885_ ? 1'h0 : dtlb_valids[100];
- assign _1014_ = _0886_ ? 1'h0 : dtlb_valids[101];
- assign _1015_ = _0887_ ? 1'h0 : dtlb_valids[102];
- assign _1016_ = _0888_ ? 1'h0 : dtlb_valids[103];
- assign _1017_ = _0889_ ? 1'h0 : dtlb_valids[104];
- assign _1018_ = _0890_ ? 1'h0 : dtlb_valids[105];
- assign _1019_ = _0891_ ? 1'h0 : dtlb_valids[106];
- assign _1020_ = _0892_ ? 1'h0 : dtlb_valids[107];
- assign _1021_ = _0893_ ? 1'h0 : dtlb_valids[108];
- assign _1022_ = _0894_ ? 1'h0 : dtlb_valids[109];
- assign _1023_ = _0895_ ? 1'h0 : dtlb_valids[110];
- assign _1024_ = _0896_ ? 1'h0 : dtlb_valids[111];
- assign _1025_ = _0897_ ? 1'h0 : dtlb_valids[112];
- assign _1026_ = _0898_ ? 1'h0 : dtlb_valids[113];
- assign _1027_ = _0899_ ? 1'h0 : dtlb_valids[114];
- assign _1028_ = _0900_ ? 1'h0 : dtlb_valids[115];
- assign _1029_ = _0901_ ? 1'h0 : dtlb_valids[116];
- assign _1030_ = _0902_ ? 1'h0 : dtlb_valids[117];
- assign _1031_ = _0903_ ? 1'h0 : dtlb_valids[118];
- assign _1032_ = _0904_ ? 1'h0 : dtlb_valids[119];
- assign _1033_ = _0905_ ? 1'h0 : dtlb_valids[120];
- assign _1034_ = _0906_ ? 1'h0 : dtlb_valids[121];
- assign _1035_ = _0907_ ? 1'h0 : dtlb_valids[122];
- assign _1036_ = _0908_ ? 1'h0 : dtlb_valids[123];
- assign _1037_ = _0909_ ? 1'h0 : dtlb_valids[124];
- assign _1038_ = _0910_ ? 1'h0 : dtlb_valids[125];
- assign _1039_ = _0911_ ? 1'h0 : dtlb_valids[126];
- assign _1040_ = _0912_ ? 1'h0 : dtlb_valids[127];
- assign _1062_ = ~ _0162_;
- assign _1063_ = _1062_ ? r0[70:25] : tlb_tag_way[45:0];
- assign _1064_ = _0162_ ? r0[70:25] : tlb_tag_way[91:46];
- assign _1065_ = ~ _0162_;
- assign _1066_ = _1065_ ? r0[134:71] : tlb_pte_way[63:0];
- assign _1067_ = _0162_ ? r0[134:71] : tlb_pte_way[127:64];
- assign _1068_ = ~ _0163_[5];
- assign _1069_ = ~ _0163_[4];
- assign _1070_ = _1068_ & _1069_;
- assign _1071_ = _1068_ & _0163_[4];
- assign _1072_ = _0163_[5] & _1069_;
- assign _1073_ = _0163_[5] & _0163_[4];
- assign _1074_ = ~ _0163_[3];
- assign _1075_ = _1070_ & _1074_;
- assign _1076_ = _1070_ & _0163_[3];
- assign _1077_ = _1071_ & _1074_;
- assign _1078_ = _1071_ & _0163_[3];
- assign _1079_ = _1072_ & _1074_;
- assign _1080_ = _1072_ & _0163_[3];
- assign _1081_ = _1073_ & _1074_;
- assign _1082_ = _1073_ & _0163_[3];
- assign _1083_ = ~ _0163_[2];
- assign _1084_ = _1075_ & _1083_;
- assign _1085_ = _1075_ & _0163_[2];
- assign _1086_ = _1076_ & _1083_;
- assign _1087_ = _1076_ & _0163_[2];
- assign _1088_ = _1077_ & _1083_;
- assign _1089_ = _1077_ & _0163_[2];
- assign _1090_ = _1078_ & _1083_;
- assign _1091_ = _1078_ & _0163_[2];
- assign _1092_ = _1079_ & _1083_;
- assign _1093_ = _1079_ & _0163_[2];
- assign _1094_ = _1080_ & _1083_;
- assign _1095_ = _1080_ & _0163_[2];
- assign _1096_ = _1081_ & _1083_;
- assign _1097_ = _1081_ & _0163_[2];
- assign _1098_ = _1082_ & _1083_;
- assign _1099_ = _1082_ & _0163_[2];
- assign _1100_ = ~ _0163_[1];
- assign _1101_ = _1084_ & _1100_;
- assign _1102_ = _1084_ & _0163_[1];
- assign _1103_ = _1085_ & _1100_;
- assign _1104_ = _1085_ & _0163_[1];
- assign _1105_ = _1086_ & _1100_;
- assign _1106_ = _1086_ & _0163_[1];
- assign _1107_ = _1087_ & _1100_;
- assign _1108_ = _1087_ & _0163_[1];
- assign _1109_ = _1088_ & _1100_;
- assign _1110_ = _1088_ & _0163_[1];
- assign _1111_ = _1089_ & _1100_;
- assign _1112_ = _1089_ & _0163_[1];
- assign _1113_ = _1090_ & _1100_;
- assign _1114_ = _1090_ & _0163_[1];
- assign _1115_ = _1091_ & _1100_;
- assign _1116_ = _1091_ & _0163_[1];
- assign _1117_ = _1092_ & _1100_;
- assign _1118_ = _1092_ & _0163_[1];
- assign _1119_ = _1093_ & _1100_;
- assign _1120_ = _1093_ & _0163_[1];
- assign _1121_ = _1094_ & _1100_;
- assign _1122_ = _1094_ & _0163_[1];
- assign _1123_ = _1095_ & _1100_;
- assign _1124_ = _1095_ & _0163_[1];
- assign _1125_ = _1096_ & _1100_;
- assign _1126_ = _1096_ & _0163_[1];
- assign _1127_ = _1097_ & _1100_;
- assign _1128_ = _1097_ & _0163_[1];
- assign _1129_ = _1098_ & _1100_;
- assign _1130_ = _1098_ & _0163_[1];
- assign _1131_ = _1099_ & _1100_;
- assign _1132_ = _1099_ & _0163_[1];
- assign _1133_ = ~ _0163_[0];
- assign _1134_ = _1101_ & _1133_;
- assign _1135_ = _1101_ & _0163_[0];
- assign _1136_ = _1102_ & _1133_;
- assign _1137_ = _1102_ & _0163_[0];
- assign _1138_ = _1103_ & _1133_;
- assign _1139_ = _1103_ & _0163_[0];
- assign _1140_ = _1104_ & _1133_;
- assign _1141_ = _1104_ & _0163_[0];
- assign _1142_ = _1105_ & _1133_;
- assign _1143_ = _1105_ & _0163_[0];
- assign _1144_ = _1106_ & _1133_;
- assign _1145_ = _1106_ & _0163_[0];
- assign _1146_ = _1107_ & _1133_;
- assign _1147_ = _1107_ & _0163_[0];
- assign _1148_ = _1108_ & _1133_;
- assign _1149_ = _1108_ & _0163_[0];
- assign _1150_ = _1109_ & _1133_;
- assign _1151_ = _1109_ & _0163_[0];
- assign _1152_ = _1110_ & _1133_;
- assign _1153_ = _1110_ & _0163_[0];
- assign _1154_ = _1111_ & _1133_;
- assign _1155_ = _1111_ & _0163_[0];
- assign _1156_ = _1112_ & _1133_;
- assign _1157_ = _1112_ & _0163_[0];
- assign _1158_ = _1113_ & _1133_;
- assign _1159_ = _1113_ & _0163_[0];
- assign _1160_ = _1114_ & _1133_;
- assign _1161_ = _1114_ & _0163_[0];
- assign _1162_ = _1115_ & _1133_;
- assign _1163_ = _1115_ & _0163_[0];
- assign _1164_ = _1116_ & _1133_;
- assign _1165_ = _1116_ & _0163_[0];
- assign _1166_ = _1117_ & _1133_;
- assign _1167_ = _1117_ & _0163_[0];
- assign _1168_ = _1118_ & _1133_;
- assign _1169_ = _1118_ & _0163_[0];
- assign _1170_ = _1119_ & _1133_;
- assign _1171_ = _1119_ & _0163_[0];
- assign _1172_ = _1120_ & _1133_;
- assign _1173_ = _1120_ & _0163_[0];
- assign _1174_ = _1121_ & _1133_;
- assign _1175_ = _1121_ & _0163_[0];
- assign _1176_ = _1122_ & _1133_;
- assign _1177_ = _1122_ & _0163_[0];
- assign _1178_ = _1123_ & _1133_;
- assign _1179_ = _1123_ & _0163_[0];
- assign _1180_ = _1124_ & _1133_;
- assign _1181_ = _1124_ & _0163_[0];
- assign _1182_ = _1125_ & _1133_;
- assign _1183_ = _1125_ & _0163_[0];
- assign _1184_ = _1126_ & _1133_;
- assign _1185_ = _1126_ & _0163_[0];
- assign _1186_ = _1127_ & _1133_;
- assign _1187_ = _1127_ & _0163_[0];
- assign _1188_ = _1128_ & _1133_;
- assign _1189_ = _1128_ & _0163_[0];
- assign _1190_ = _1129_ & _1133_;
- assign _1191_ = _1129_ & _0163_[0];
- assign _1192_ = _1130_ & _1133_;
- assign _1193_ = _1130_ & _0163_[0];
- assign _1194_ = _1131_ & _1133_;
- assign _1195_ = _1131_ & _0163_[0];
- assign _1196_ = _1132_ & _1133_;
- assign _1197_ = _1132_ & _0163_[0];
- assign _1198_ = ~ _0162_;
- assign _1199_ = _1134_ & _1198_;
- assign _1200_ = _1134_ & _0162_;
- assign _1201_ = _1135_ & _1198_;
- assign _1202_ = _1135_ & _0162_;
- assign _1203_ = _1136_ & _1198_;
- assign _1204_ = _1136_ & _0162_;
- assign _1205_ = _1137_ & _1198_;
- assign _1206_ = _1137_ & _0162_;
- assign _1207_ = _1138_ & _1198_;
- assign _1208_ = _1138_ & _0162_;
- assign _1209_ = _1139_ & _1198_;
- assign _1210_ = _1139_ & _0162_;
- assign _1211_ = _1140_ & _1198_;
- assign _1212_ = _1140_ & _0162_;
- assign _1213_ = _1141_ & _1198_;
- assign _1214_ = _1141_ & _0162_;
- assign _1215_ = _1142_ & _1198_;
- assign _1216_ = _1142_ & _0162_;
- assign _1217_ = _1143_ & _1198_;
- assign _1218_ = _1143_ & _0162_;
- assign _1219_ = _1144_ & _1198_;
- assign _1220_ = _1144_ & _0162_;
- assign _1221_ = _1145_ & _1198_;
- assign _1222_ = _1145_ & _0162_;
- assign _1223_ = _1146_ & _1198_;
- assign _1224_ = _1146_ & _0162_;
- assign _1225_ = _1147_ & _1198_;
- assign _1226_ = _1147_ & _0162_;
- assign _1227_ = _1148_ & _1198_;
- assign _1228_ = _1148_ & _0162_;
- assign _1229_ = _1149_ & _1198_;
- assign _1230_ = _1149_ & _0162_;
- assign _1231_ = _1150_ & _1198_;
- assign _1232_ = _1150_ & _0162_;
- assign _1233_ = _1151_ & _1198_;
- assign _1234_ = _1151_ & _0162_;
- assign _1235_ = _1152_ & _1198_;
- assign _1236_ = _1152_ & _0162_;
- assign _1237_ = _1153_ & _1198_;
- assign _1238_ = _1153_ & _0162_;
- assign _1239_ = _1154_ & _1198_;
- assign _1240_ = _1154_ & _0162_;
- assign _1241_ = _1155_ & _1198_;
- assign _1242_ = _1155_ & _0162_;
- assign _1243_ = _1156_ & _1198_;
- assign _1244_ = _1156_ & _0162_;
- assign _1245_ = _1157_ & _1198_;
- assign _1246_ = _1157_ & _0162_;
- assign _1247_ = _1158_ & _1198_;
- assign _1248_ = _1158_ & _0162_;
- assign _1249_ = _1159_ & _1198_;
- assign _1250_ = _1159_ & _0162_;
- assign _1251_ = _1160_ & _1198_;
- assign _1252_ = _1160_ & _0162_;
- assign _1253_ = _1161_ & _1198_;
- assign _1254_ = _1161_ & _0162_;
- assign _1255_ = _1162_ & _1198_;
- assign _1256_ = _1162_ & _0162_;
- assign _1257_ = _1163_ & _1198_;
- assign _1258_ = _1163_ & _0162_;
- assign _1259_ = _1164_ & _1198_;
- assign _1260_ = _1164_ & _0162_;
- assign _1261_ = _1165_ & _1198_;
- assign _1262_ = _1165_ & _0162_;
- assign _1263_ = _1166_ & _1198_;
- assign _1264_ = _1166_ & _0162_;
- assign _1265_ = _1167_ & _1198_;
- assign _1266_ = _1167_ & _0162_;
- assign _1267_ = _1168_ & _1198_;
- assign _1268_ = _1168_ & _0162_;
- assign _1269_ = _1169_ & _1198_;
- assign _1270_ = _1169_ & _0162_;
- assign _1271_ = _1170_ & _1198_;
- assign _1272_ = _1170_ & _0162_;
- assign _1273_ = _1171_ & _1198_;
- assign _1274_ = _1171_ & _0162_;
- assign _1275_ = _1172_ & _1198_;
- assign _1276_ = _1172_ & _0162_;
- assign _1277_ = _1173_ & _1198_;
- assign _1278_ = _1173_ & _0162_;
- assign _1279_ = _1174_ & _1198_;
- assign _1280_ = _1174_ & _0162_;
- assign _1281_ = _1175_ & _1198_;
- assign _1282_ = _1175_ & _0162_;
- assign _1283_ = _1176_ & _1198_;
- assign _1284_ = _1176_ & _0162_;
- assign _1285_ = _1177_ & _1198_;
- assign _1286_ = _1177_ & _0162_;
- assign _1287_ = _1178_ & _1198_;
- assign _1288_ = _1178_ & _0162_;
- assign _1289_ = _1179_ & _1198_;
- assign _1290_ = _1179_ & _0162_;
- assign _1291_ = _1180_ & _1198_;
- assign _1292_ = _1180_ & _0162_;
- assign _1293_ = _1181_ & _1198_;
- assign _1294_ = _1181_ & _0162_;
- assign _1295_ = _1182_ & _1198_;
- assign _1296_ = _1182_ & _0162_;
- assign _1297_ = _1183_ & _1198_;
- assign _1298_ = _1183_ & _0162_;
- assign _1299_ = _1184_ & _1198_;
- assign _1300_ = _1184_ & _0162_;
- assign _1301_ = _1185_ & _1198_;
- assign _1302_ = _1185_ & _0162_;
- assign _1303_ = _1186_ & _1198_;
- assign _1304_ = _1186_ & _0162_;
- assign _1305_ = _1187_ & _1198_;
- assign _1306_ = _1187_ & _0162_;
- assign _1307_ = _1188_ & _1198_;
- assign _1308_ = _1188_ & _0162_;
- assign _1309_ = _1189_ & _1198_;
- assign _1310_ = _1189_ & _0162_;
- assign _1311_ = _1190_ & _1198_;
- assign _1312_ = _1190_ & _0162_;
- assign _1313_ = _1191_ & _1198_;
- assign _1314_ = _1191_ & _0162_;
- assign _1315_ = _1192_ & _1198_;
- assign _1316_ = _1192_ & _0162_;
- assign _1317_ = _1193_ & _1198_;
- assign _1318_ = _1193_ & _0162_;
- assign _1319_ = _1194_ & _1198_;
- assign _1320_ = _1194_ & _0162_;
- assign _1321_ = _1195_ & _1198_;
- assign _1322_ = _1195_ & _0162_;
- assign _1323_ = _1196_ & _1198_;
- assign _1324_ = _1196_ & _0162_;
- assign _1325_ = _1197_ & _1198_;
- assign _1326_ = _1197_ & _0162_;
- assign _1327_ = _1199_ ? 1'h1 : dtlb_valids[0];
- assign _1328_ = _1200_ ? 1'h1 : dtlb_valids[1];
- assign _1329_ = _1201_ ? 1'h1 : dtlb_valids[2];
- assign _1330_ = _1202_ ? 1'h1 : dtlb_valids[3];
- assign _1331_ = _1203_ ? 1'h1 : dtlb_valids[4];
- assign _1332_ = _1204_ ? 1'h1 : dtlb_valids[5];
- assign _1333_ = _1205_ ? 1'h1 : dtlb_valids[6];
- assign _1334_ = _1206_ ? 1'h1 : dtlb_valids[7];
- assign _1335_ = _1207_ ? 1'h1 : dtlb_valids[8];
- assign _1336_ = _1208_ ? 1'h1 : dtlb_valids[9];
- assign _1337_ = _1209_ ? 1'h1 : dtlb_valids[10];
- assign _1338_ = _1210_ ? 1'h1 : dtlb_valids[11];
- assign _1339_ = _1211_ ? 1'h1 : dtlb_valids[12];
- assign _1340_ = _1212_ ? 1'h1 : dtlb_valids[13];
- assign _1341_ = _1213_ ? 1'h1 : dtlb_valids[14];
- assign _1342_ = _1214_ ? 1'h1 : dtlb_valids[15];
- assign _1343_ = _1215_ ? 1'h1 : dtlb_valids[16];
- assign _1344_ = _1216_ ? 1'h1 : dtlb_valids[17];
- assign _1345_ = _1217_ ? 1'h1 : dtlb_valids[18];
- assign _1346_ = _1218_ ? 1'h1 : dtlb_valids[19];
- assign _1347_ = _1219_ ? 1'h1 : dtlb_valids[20];
- assign _1348_ = _1220_ ? 1'h1 : dtlb_valids[21];
- assign _1349_ = _1221_ ? 1'h1 : dtlb_valids[22];
- assign _1350_ = _1222_ ? 1'h1 : dtlb_valids[23];
- assign _1351_ = _1223_ ? 1'h1 : dtlb_valids[24];
- assign _1352_ = _1224_ ? 1'h1 : dtlb_valids[25];
- assign _1353_ = _1225_ ? 1'h1 : dtlb_valids[26];
- assign _1354_ = _1226_ ? 1'h1 : dtlb_valids[27];
- assign _1355_ = _1227_ ? 1'h1 : dtlb_valids[28];
- assign _1356_ = _1228_ ? 1'h1 : dtlb_valids[29];
- assign _1357_ = _1229_ ? 1'h1 : dtlb_valids[30];
- assign _1358_ = _1230_ ? 1'h1 : dtlb_valids[31];
- assign _1359_ = _1231_ ? 1'h1 : dtlb_valids[32];
- assign _1360_ = _1232_ ? 1'h1 : dtlb_valids[33];
- assign _1361_ = _1233_ ? 1'h1 : dtlb_valids[34];
- assign _1362_ = _1234_ ? 1'h1 : dtlb_valids[35];
- assign _1363_ = _1235_ ? 1'h1 : dtlb_valids[36];
- assign _1364_ = _1236_ ? 1'h1 : dtlb_valids[37];
- assign _1365_ = _1237_ ? 1'h1 : dtlb_valids[38];
- assign _1366_ = _1238_ ? 1'h1 : dtlb_valids[39];
- assign _1367_ = _1239_ ? 1'h1 : dtlb_valids[40];
- assign _1368_ = _1240_ ? 1'h1 : dtlb_valids[41];
- assign _1369_ = _1241_ ? 1'h1 : dtlb_valids[42];
- assign _1370_ = _1242_ ? 1'h1 : dtlb_valids[43];
- assign _1371_ = _1243_ ? 1'h1 : dtlb_valids[44];
- assign _1372_ = _1244_ ? 1'h1 : dtlb_valids[45];
- assign _1373_ = _1245_ ? 1'h1 : dtlb_valids[46];
- assign _1374_ = _1246_ ? 1'h1 : dtlb_valids[47];
- assign _1375_ = _1247_ ? 1'h1 : dtlb_valids[48];
- assign _1376_ = _1248_ ? 1'h1 : dtlb_valids[49];
- assign _1377_ = _1249_ ? 1'h1 : dtlb_valids[50];
- assign _1378_ = _1250_ ? 1'h1 : dtlb_valids[51];
- assign _1379_ = _1251_ ? 1'h1 : dtlb_valids[52];
- assign _1380_ = _1252_ ? 1'h1 : dtlb_valids[53];
- assign _1381_ = _1253_ ? 1'h1 : dtlb_valids[54];
- assign _1382_ = _1254_ ? 1'h1 : dtlb_valids[55];
- assign _1383_ = _1255_ ? 1'h1 : dtlb_valids[56];
- assign _1384_ = _1256_ ? 1'h1 : dtlb_valids[57];
- assign _1385_ = _1257_ ? 1'h1 : dtlb_valids[58];
- assign _1386_ = _1258_ ? 1'h1 : dtlb_valids[59];
- assign _1387_ = _1259_ ? 1'h1 : dtlb_valids[60];
- assign _1388_ = _1260_ ? 1'h1 : dtlb_valids[61];
- assign _1389_ = _1261_ ? 1'h1 : dtlb_valids[62];
- assign _1390_ = _1262_ ? 1'h1 : dtlb_valids[63];
- assign _1391_ = _1263_ ? 1'h1 : dtlb_valids[64];
- assign _1392_ = _1264_ ? 1'h1 : dtlb_valids[65];
- assign _1393_ = _1265_ ? 1'h1 : dtlb_valids[66];
- assign _1394_ = _1266_ ? 1'h1 : dtlb_valids[67];
- assign _1395_ = _1267_ ? 1'h1 : dtlb_valids[68];
- assign _1396_ = _1268_ ? 1'h1 : dtlb_valids[69];
- assign _1397_ = _1269_ ? 1'h1 : dtlb_valids[70];
- assign _1398_ = _1270_ ? 1'h1 : dtlb_valids[71];
- assign _1399_ = _1271_ ? 1'h1 : dtlb_valids[72];
- assign _1400_ = _1272_ ? 1'h1 : dtlb_valids[73];
- assign _1401_ = _1273_ ? 1'h1 : dtlb_valids[74];
- assign _1402_ = _1274_ ? 1'h1 : dtlb_valids[75];
- assign _1403_ = _1275_ ? 1'h1 : dtlb_valids[76];
- assign _1404_ = _1276_ ? 1'h1 : dtlb_valids[77];
- assign _1405_ = _1277_ ? 1'h1 : dtlb_valids[78];
- assign _1406_ = _1278_ ? 1'h1 : dtlb_valids[79];
- assign _1407_ = _1279_ ? 1'h1 : dtlb_valids[80];
- assign _1408_ = _1280_ ? 1'h1 : dtlb_valids[81];
- assign _1409_ = _1281_ ? 1'h1 : dtlb_valids[82];
- assign _1410_ = _1282_ ? 1'h1 : dtlb_valids[83];
- assign _1411_ = _1283_ ? 1'h1 : dtlb_valids[84];
- assign _1412_ = _1284_ ? 1'h1 : dtlb_valids[85];
- assign _1413_ = _1285_ ? 1'h1 : dtlb_valids[86];
- assign _1414_ = _1286_ ? 1'h1 : dtlb_valids[87];
- assign _1415_ = _1287_ ? 1'h1 : dtlb_valids[88];
- assign _1416_ = _1288_ ? 1'h1 : dtlb_valids[89];
- assign _1417_ = _1289_ ? 1'h1 : dtlb_valids[90];
- assign _1418_ = _1290_ ? 1'h1 : dtlb_valids[91];
- assign _1419_ = _1291_ ? 1'h1 : dtlb_valids[92];
- assign _1420_ = _1292_ ? 1'h1 : dtlb_valids[93];
- assign _1421_ = _1293_ ? 1'h1 : dtlb_valids[94];
- assign _1422_ = _1294_ ? 1'h1 : dtlb_valids[95];
- assign _1423_ = _1295_ ? 1'h1 : dtlb_valids[96];
- assign _1424_ = _1296_ ? 1'h1 : dtlb_valids[97];
- assign _1425_ = _1297_ ? 1'h1 : dtlb_valids[98];
- assign _1426_ = _1298_ ? 1'h1 : dtlb_valids[99];
- assign _1427_ = _1299_ ? 1'h1 : dtlb_valids[100];
- assign _1428_ = _1300_ ? 1'h1 : dtlb_valids[101];
- assign _1429_ = _1301_ ? 1'h1 : dtlb_valids[102];
- assign _1430_ = _1302_ ? 1'h1 : dtlb_valids[103];
- assign _1431_ = _1303_ ? 1'h1 : dtlb_valids[104];
- assign _1432_ = _1304_ ? 1'h1 : dtlb_valids[105];
- assign _1433_ = _1305_ ? 1'h1 : dtlb_valids[106];
- assign _1434_ = _1306_ ? 1'h1 : dtlb_valids[107];
- assign _1435_ = _1307_ ? 1'h1 : dtlb_valids[108];
- assign _1436_ = _1308_ ? 1'h1 : dtlb_valids[109];
- assign _1437_ = _1309_ ? 1'h1 : dtlb_valids[110];
- assign _1438_ = _1310_ ? 1'h1 : dtlb_valids[111];
- assign _1439_ = _1311_ ? 1'h1 : dtlb_valids[112];
- assign _1440_ = _1312_ ? 1'h1 : dtlb_valids[113];
- assign _1441_ = _1313_ ? 1'h1 : dtlb_valids[114];
- assign _1442_ = _1314_ ? 1'h1 : dtlb_valids[115];
- assign _1443_ = _1315_ ? 1'h1 : dtlb_valids[116];
- assign _1444_ = _1316_ ? 1'h1 : dtlb_valids[117];
- assign _1445_ = _1317_ ? 1'h1 : dtlb_valids[118];
- assign _1446_ = _1318_ ? 1'h1 : dtlb_valids[119];
- assign _1447_ = _1319_ ? 1'h1 : dtlb_valids[120];
- assign _1448_ = _1320_ ? 1'h1 : dtlb_valids[121];
- assign _1449_ = _1321_ ? 1'h1 : dtlb_valids[122];
- assign _1450_ = _1322_ ? 1'h1 : dtlb_valids[123];
- assign _1451_ = _1323_ ? 1'h1 : dtlb_valids[124];
- assign _1452_ = _1324_ ? 1'h1 : dtlb_valids[125];
- assign _1453_ = _1325_ ? 1'h1 : dtlb_valids[126];
- assign _1454_ = _1326_ ? 1'h1 : dtlb_valids[127];
- assign _1465_ = _0338_[4] ? _1464_ : _1463_;
- assign _1476_ = _0340_[4] ? _1475_ : _1474_;
- assign _1487_ = _0346_[4] ? _1486_ : _1485_;
- assign _1498_ = _0348_[4] ? _1497_ : _1496_;
- assign _1509_ = _0354_[4] ? _1508_ : _1507_;
- assign _1520_ = _0356_[4] ? _1519_ : _1518_;
- assign _1531_ = _0362_[4] ? _1530_ : _1529_;
- assign _1542_ = _0364_[4] ? _1541_ : _1540_;
- assign _1543_ = tlb_hit_way ? _0368_ : _0352_;
- assign _1544_ = _0370_ ? _0353_ : _0369_;
- assign _1555_ = _0373_[4] ? _1554_ : _1553_;
- assign _1566_ = _0375_[4] ? _1565_ : _1564_;
- assign _1577_ = _0379_[4] ? _1576_ : _1575_;
- assign _1588_ = _0381_[4] ? _1587_ : _1586_;
- assign replace_way = _0387_[4] ? _1598_ : _1597_;
- assign _1599_ = _0422_ ? \rams%0.dout : \rams%1.dout ;
- assign _1600_ = _0423_ ? \rams%0.dout : \rams%1.dout ;
- assign _1601_ = ~ _0511_[4];
- assign _1602_ = ~ _0511_[3];
- assign _1603_ = _1601_ & _1602_;
- assign _1604_ = _1601_ & _0511_[3];
- assign _1605_ = _0511_[4] & _1602_;
- assign _1606_ = _0511_[4] & _0511_[3];
- assign _1607_ = ~ _0511_[2];
- assign _1608_ = _1603_ & _1607_;
- assign _1609_ = _1603_ & _0511_[2];
- assign _1610_ = _1604_ & _1607_;
- assign _1611_ = _1604_ & _0511_[2];
- assign _1612_ = _1605_ & _1607_;
- assign _1613_ = _1605_ & _0511_[2];
- assign _1614_ = _1606_ & _1607_;
- assign _1615_ = _1606_ & _0511_[2];
- assign _1616_ = ~ _0511_[1];
- assign _1617_ = _1608_ & _1616_;
- assign _1618_ = _1608_ & _0511_[1];
- assign _1619_ = _1609_ & _1616_;
- assign _1620_ = _1609_ & _0511_[1];
- assign _1621_ = _1610_ & _1616_;
- assign _1622_ = _1610_ & _0511_[1];
- assign _1623_ = _1611_ & _1616_;
- assign _1624_ = _1611_ & _0511_[1];
- assign _1625_ = _1612_ & _1616_;
- assign _1626_ = _1612_ & _0511_[1];
- assign _1627_ = _1613_ & _1616_;
- assign _1628_ = _1613_ & _0511_[1];
- assign _1629_ = _1614_ & _1616_;
- assign _1630_ = _1614_ & _0511_[1];
- assign _1631_ = _1615_ & _1616_;
- assign _1632_ = _1615_ & _0511_[1];
- assign _1633_ = ~ _0511_[0];
- assign _1634_ = _1617_ & _1633_;
- assign _1635_ = _1617_ & _0511_[0];
- assign _1636_ = _1618_ & _1633_;
- assign _1637_ = _1618_ & _0511_[0];
- assign _1638_ = _1619_ & _1633_;
- assign _1639_ = _1619_ & _0511_[0];
- assign _1640_ = _1620_ & _1633_;
- assign _1641_ = _1620_ & _0511_[0];
- assign _1642_ = _1621_ & _1633_;
- assign _1643_ = _1621_ & _0511_[0];
- assign _1644_ = _1622_ & _1633_;
- assign _1645_ = _1622_ & _0511_[0];
- assign _1646_ = _1623_ & _1633_;
- assign _1647_ = _1623_ & _0511_[0];
- assign _1648_ = _1624_ & _1633_;
- assign _1649_ = _1624_ & _0511_[0];
- assign _1650_ = _1625_ & _1633_;
- assign _1651_ = _1625_ & _0511_[0];
- assign _1652_ = _1626_ & _1633_;
- assign _1653_ = _1626_ & _0511_[0];
- assign _1654_ = _1627_ & _1633_;
- assign _1655_ = _1627_ & _0511_[0];
- assign _1656_ = _1628_ & _1633_;
- assign _1657_ = _1628_ & _0511_[0];
- assign _1658_ = _1629_ & _1633_;
- assign _1659_ = _1629_ & _0511_[0];
- assign _1660_ = _1630_ & _1633_;
- assign _1661_ = _1630_ & _0511_[0];
- assign _1662_ = _1631_ & _1633_;
- assign _1663_ = _1631_ & _0511_[0];
- assign _1664_ = _1632_ & _1633_;
- assign _1665_ = _1632_ & _0511_[0];
- assign _1666_ = ~ replace_way;
- assign _1667_ = _1634_ & _1666_;
- assign _1668_ = _1634_ & replace_way;
- assign _1669_ = _1635_ & _1666_;
- assign _1670_ = _1635_ & replace_way;
- assign _1671_ = _1636_ & _1666_;
- assign _1672_ = _1636_ & replace_way;
- assign _1673_ = _1637_ & _1666_;
- assign _1674_ = _1637_ & replace_way;
- assign _1675_ = _1638_ & _1666_;
- assign _1676_ = _1638_ & replace_way;
- assign _1677_ = _1639_ & _1666_;
- assign _1678_ = _1639_ & replace_way;
- assign _1679_ = _1640_ & _1666_;
- assign _1680_ = _1640_ & replace_way;
- assign _1681_ = _1641_ & _1666_;
- assign _1682_ = _1641_ & replace_way;
- assign _1683_ = _1642_ & _1666_;
- assign _1684_ = _1642_ & replace_way;
- assign _1685_ = _1643_ & _1666_;
- assign _1686_ = _1643_ & replace_way;
- assign _1687_ = _1644_ & _1666_;
- assign _1688_ = _1644_ & replace_way;
- assign _1689_ = _1645_ & _1666_;
- assign _1690_ = _1645_ & replace_way;
- assign _1691_ = _1646_ & _1666_;
- assign _1692_ = _1646_ & replace_way;
- assign _1693_ = _1647_ & _1666_;
- assign _1694_ = _1647_ & replace_way;
- assign _1695_ = _1648_ & _1666_;
- assign _1696_ = _1648_ & replace_way;
- assign _1697_ = _1649_ & _1666_;
- assign _1698_ = _1649_ & replace_way;
- assign _1699_ = _1650_ & _1666_;
- assign _1700_ = _1650_ & replace_way;
- assign _1701_ = _1651_ & _1666_;
- assign _1702_ = _1651_ & replace_way;
- assign _1703_ = _1652_ & _1666_;
- assign _1704_ = _1652_ & replace_way;
- assign _1705_ = _1653_ & _1666_;
- assign _1706_ = _1653_ & replace_way;
- assign _1707_ = _1654_ & _1666_;
- assign _1708_ = _1654_ & replace_way;
- assign _1709_ = _1655_ & _1666_;
- assign _1710_ = _1655_ & replace_way;
- assign _1711_ = _1656_ & _1666_;
- assign _1712_ = _1656_ & replace_way;
- assign _1713_ = _1657_ & _1666_;
- assign _1714_ = _1657_ & replace_way;
- assign _1715_ = _1658_ & _1666_;
- assign _1716_ = _1658_ & replace_way;
- assign _1717_ = _1659_ & _1666_;
- assign _1718_ = _1659_ & replace_way;
- assign _1719_ = _1660_ & _1666_;
- assign _1720_ = _1660_ & replace_way;
- assign _1721_ = _1661_ & _1666_;
- assign _1722_ = _1661_ & replace_way;
- assign _1723_ = _1662_ & _1666_;
- assign _1724_ = _1662_ & replace_way;
- assign _1725_ = _1663_ & _1666_;
- assign _1726_ = _1663_ & replace_way;
- assign _1727_ = _1664_ & _1666_;
- assign _1728_ = _1664_ & replace_way;
- assign _1729_ = _1665_ & _1666_;
- assign _1730_ = _1665_ & replace_way;
- assign _1731_ = _1667_ ? 1'h0 : cache_valids[0];
- assign _1732_ = _1668_ ? 1'h0 : cache_valids[1];
- assign _1733_ = _1669_ ? 1'h0 : cache_valids[2];
- assign _1734_ = _1670_ ? 1'h0 : cache_valids[3];
- assign _1735_ = _1671_ ? 1'h0 : cache_valids[4];
- assign _1736_ = _1672_ ? 1'h0 : cache_valids[5];
- assign _1737_ = _1673_ ? 1'h0 : cache_valids[6];
- assign _1738_ = _1674_ ? 1'h0 : cache_valids[7];
- assign _1739_ = _1675_ ? 1'h0 : cache_valids[8];
- assign _1740_ = _1676_ ? 1'h0 : cache_valids[9];
- assign _1741_ = _1677_ ? 1'h0 : cache_valids[10];
- assign _1742_ = _1678_ ? 1'h0 : cache_valids[11];
- assign _1743_ = _1679_ ? 1'h0 : cache_valids[12];
- assign _1744_ = _1680_ ? 1'h0 : cache_valids[13];
- assign _1745_ = _1681_ ? 1'h0 : cache_valids[14];
- assign _1746_ = _1682_ ? 1'h0 : cache_valids[15];
- assign _1747_ = _1683_ ? 1'h0 : cache_valids[16];
- assign _1748_ = _1684_ ? 1'h0 : cache_valids[17];
- assign _1749_ = _1685_ ? 1'h0 : cache_valids[18];
- assign _1750_ = _1686_ ? 1'h0 : cache_valids[19];
- assign _1751_ = _1687_ ? 1'h0 : cache_valids[20];
- assign _1752_ = _1688_ ? 1'h0 : cache_valids[21];
- assign _1753_ = _1689_ ? 1'h0 : cache_valids[22];
- assign _1754_ = _1690_ ? 1'h0 : cache_valids[23];
- assign _1755_ = _1691_ ? 1'h0 : cache_valids[24];
- assign _1756_ = _1692_ ? 1'h0 : cache_valids[25];
- assign _1757_ = _1693_ ? 1'h0 : cache_valids[26];
- assign _1758_ = _1694_ ? 1'h0 : cache_valids[27];
- assign _1759_ = _1695_ ? 1'h0 : cache_valids[28];
- assign _1760_ = _1696_ ? 1'h0 : cache_valids[29];
- assign _1761_ = _1697_ ? 1'h0 : cache_valids[30];
- assign _1762_ = _1698_ ? 1'h0 : cache_valids[31];
- assign _1763_ = _1699_ ? 1'h0 : cache_valids[32];
- assign _1764_ = _1700_ ? 1'h0 : cache_valids[33];
- assign _1765_ = _1701_ ? 1'h0 : cache_valids[34];
- assign _1766_ = _1702_ ? 1'h0 : cache_valids[35];
- assign _1767_ = _1703_ ? 1'h0 : cache_valids[36];
- assign _1768_ = _1704_ ? 1'h0 : cache_valids[37];
- assign _1769_ = _1705_ ? 1'h0 : cache_valids[38];
- assign _1770_ = _1706_ ? 1'h0 : cache_valids[39];
- assign _1771_ = _1707_ ? 1'h0 : cache_valids[40];
- assign _1772_ = _1708_ ? 1'h0 : cache_valids[41];
- assign _1773_ = _1709_ ? 1'h0 : cache_valids[42];
- assign _1774_ = _1710_ ? 1'h0 : cache_valids[43];
- assign _1775_ = _1711_ ? 1'h0 : cache_valids[44];
- assign _1776_ = _1712_ ? 1'h0 : cache_valids[45];
- assign _1777_ = _1713_ ? 1'h0 : cache_valids[46];
- assign _1778_ = _1714_ ? 1'h0 : cache_valids[47];
- assign _1779_ = _1715_ ? 1'h0 : cache_valids[48];
- assign _1780_ = _1716_ ? 1'h0 : cache_valids[49];
- assign _1781_ = _1717_ ? 1'h0 : cache_valids[50];
- assign _1782_ = _1718_ ? 1'h0 : cache_valids[51];
- assign _1783_ = _1719_ ? 1'h0 : cache_valids[52];
- assign _1784_ = _1720_ ? 1'h0 : cache_valids[53];
- assign _1785_ = _1721_ ? 1'h0 : cache_valids[54];
- assign _1786_ = _1722_ ? 1'h0 : cache_valids[55];
- assign _1787_ = _1723_ ? 1'h0 : cache_valids[56];
- assign _1788_ = _1724_ ? 1'h0 : cache_valids[57];
- assign _1789_ = _1725_ ? 1'h0 : cache_valids[58];
- assign _1790_ = _1726_ ? 1'h0 : cache_valids[59];
- assign _1791_ = _1727_ ? 1'h0 : cache_valids[60];
- assign _1792_ = _1728_ ? 1'h0 : cache_valids[61];
- assign _1793_ = _1729_ ? 1'h0 : cache_valids[62];
- assign _1794_ = _1730_ ? 1'h0 : cache_valids[63];
- assign _1805_ = _0513_[4] ? _1804_ : _1803_;
- assign _1806_ = ~ _0514_[4];
- assign _1807_ = ~ _0514_[3];
- assign _1808_ = _1806_ & _1807_;
- assign _1809_ = _1806_ & _0514_[3];
- assign _1810_ = _0514_[4] & _1807_;
- assign _1811_ = _0514_[4] & _0514_[3];
- assign _1812_ = ~ _0514_[2];
- assign _1813_ = _1808_ & _1812_;
- assign _1814_ = _1808_ & _0514_[2];
- assign _1815_ = _1809_ & _1812_;
- assign _1816_ = _1809_ & _0514_[2];
- assign _1817_ = _1810_ & _1812_;
- assign _1818_ = _1810_ & _0514_[2];
- assign _1819_ = _1811_ & _1812_;
- assign _1820_ = _1811_ & _0514_[2];
- assign _1821_ = ~ _0514_[1];
- assign _1822_ = _1813_ & _1821_;
- assign _1823_ = _1813_ & _0514_[1];
- assign _1824_ = _1814_ & _1821_;
- assign _1825_ = _1814_ & _0514_[1];
- assign _1826_ = _1815_ & _1821_;
- assign _1827_ = _1815_ & _0514_[1];
- assign _1828_ = _1816_ & _1821_;
- assign _1829_ = _1816_ & _0514_[1];
- assign _1830_ = _1817_ & _1821_;
- assign _1831_ = _1817_ & _0514_[1];
- assign _1832_ = _1818_ & _1821_;
- assign _1833_ = _1818_ & _0514_[1];
- assign _1834_ = _1819_ & _1821_;
- assign _1835_ = _1819_ & _0514_[1];
- assign _1836_ = _1820_ & _1821_;
- assign _1837_ = _1820_ & _0514_[1];
- assign _1838_ = ~ _0514_[0];
- assign _1839_ = _1822_ & _1838_;
- assign _1840_ = _1822_ & _0514_[0];
- assign _1841_ = _1823_ & _1838_;
- assign _1842_ = _1823_ & _0514_[0];
- assign _1843_ = _1824_ & _1838_;
- assign _1844_ = _1824_ & _0514_[0];
- assign _1845_ = _1825_ & _1838_;
- assign _1846_ = _1825_ & _0514_[0];
- assign _1847_ = _1826_ & _1838_;
- assign _1848_ = _1826_ & _0514_[0];
- assign _1849_ = _1827_ & _1838_;
- assign _1850_ = _1827_ & _0514_[0];
- assign _1851_ = _1828_ & _1838_;
- assign _1852_ = _1828_ & _0514_[0];
- assign _1853_ = _1829_ & _1838_;
- assign _1854_ = _1829_ & _0514_[0];
- assign _1855_ = _1830_ & _1838_;
- assign _1856_ = _1830_ & _0514_[0];
- assign _1857_ = _1831_ & _1838_;
- assign _1858_ = _1831_ & _0514_[0];
- assign _1859_ = _1832_ & _1838_;
- assign _1860_ = _1832_ & _0514_[0];
- assign _1861_ = _1833_ & _1838_;
- assign _1862_ = _1833_ & _0514_[0];
- assign _1863_ = _1834_ & _1838_;
- assign _1864_ = _1834_ & _0514_[0];
- assign _1865_ = _1835_ & _1838_;
- assign _1866_ = _1835_ & _0514_[0];
- assign _1867_ = _1836_ & _1838_;
- assign _1868_ = _1836_ & _0514_[0];
- assign _1869_ = _1837_ & _1838_;
- assign _1870_ = _1837_ & _0514_[0];
- assign _1871_ = _1839_ ? { _1805_[89:45], ra[55:11] } : cache_tags[89:0];
- assign _1872_ = _1840_ ? { _1805_[89:45], ra[55:11] } : cache_tags[179:90];
- assign _1873_ = _1841_ ? { _1805_[89:45], ra[55:11] } : cache_tags[269:180];
- assign _1874_ = _1842_ ? { _1805_[89:45], ra[55:11] } : cache_tags[359:270];
- assign _1875_ = _1843_ ? { _1805_[89:45], ra[55:11] } : cache_tags[449:360];
- assign _1876_ = _1844_ ? { _1805_[89:45], ra[55:11] } : cache_tags[539:450];
- assign _1877_ = _1845_ ? { _1805_[89:45], ra[55:11] } : cache_tags[629:540];
- assign _1878_ = _1846_ ? { _1805_[89:45], ra[55:11] } : cache_tags[719:630];
- assign _1879_ = _1847_ ? { _1805_[89:45], ra[55:11] } : cache_tags[809:720];
- assign _1880_ = _1848_ ? { _1805_[89:45], ra[55:11] } : cache_tags[899:810];
- assign _1881_ = _1849_ ? { _1805_[89:45], ra[55:11] } : cache_tags[989:900];
- assign _1882_ = _1850_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1079:990];
- assign _1883_ = _1851_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1169:1080];
- assign _1884_ = _1852_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1259:1170];
- assign _1885_ = _1853_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1349:1260];
- assign _1886_ = _1854_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1439:1350];
- assign _1887_ = _1855_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1529:1440];
- assign _1888_ = _1856_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1619:1530];
- assign _1889_ = _1857_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1709:1620];
- assign _1890_ = _1858_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1799:1710];
- assign _1891_ = _1859_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1889:1800];
- assign _1892_ = _1860_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1979:1890];
- assign _1893_ = _1861_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2069:1980];
- assign _1894_ = _1862_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2159:2070];
- assign _1895_ = _1863_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2249:2160];
- assign _1896_ = _1864_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2339:2250];
- assign _1897_ = _1865_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2429:2340];
- assign _1898_ = _1866_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2519:2430];
- assign _1899_ = _1867_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2609:2520];
- assign _1900_ = _1868_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2699:2610];
- assign _1901_ = _1869_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2789:2700];
- assign _1902_ = _1870_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2879:2790];
- assign _1913_ = _0517_[4] ? _1912_ : _1911_;
- assign _1914_ = ~ _0518_[4];
- assign _1915_ = ~ _0518_[3];
- assign _1916_ = _1914_ & _1915_;
- assign _1917_ = _1914_ & _0518_[3];
- assign _1918_ = _0518_[4] & _1915_;
- assign _1919_ = _0518_[4] & _0518_[3];
- assign _1920_ = ~ _0518_[2];
- assign _1921_ = _1916_ & _1920_;
- assign _1922_ = _1916_ & _0518_[2];
- assign _1923_ = _1917_ & _1920_;
- assign _1924_ = _1917_ & _0518_[2];
- assign _1925_ = _1918_ & _1920_;
- assign _1926_ = _1918_ & _0518_[2];
- assign _1927_ = _1919_ & _1920_;
- assign _1928_ = _1919_ & _0518_[2];
- assign _1929_ = ~ _0518_[1];
- assign _1930_ = _1921_ & _1929_;
- assign _1931_ = _1921_ & _0518_[1];
- assign _1932_ = _1922_ & _1929_;
- assign _1933_ = _1922_ & _0518_[1];
- assign _1934_ = _1923_ & _1929_;
- assign _1935_ = _1923_ & _0518_[1];
- assign _1936_ = _1924_ & _1929_;
- assign _1937_ = _1924_ & _0518_[1];
- assign _1938_ = _1925_ & _1929_;
- assign _1939_ = _1925_ & _0518_[1];
- assign _1940_ = _1926_ & _1929_;
- assign _1941_ = _1926_ & _0518_[1];
- assign _1942_ = _1927_ & _1929_;
- assign _1943_ = _1927_ & _0518_[1];
- assign _1944_ = _1928_ & _1929_;
- assign _1945_ = _1928_ & _0518_[1];
- assign _1946_ = ~ _0518_[0];
- assign _1947_ = _1930_ & _1946_;
- assign _1948_ = _1930_ & _0518_[0];
- assign _1949_ = _1931_ & _1946_;
- assign _1950_ = _1931_ & _0518_[0];
- assign _1951_ = _1932_ & _1946_;
- assign _1952_ = _1932_ & _0518_[0];
- assign _1953_ = _1933_ & _1946_;
- assign _1954_ = _1933_ & _0518_[0];
- assign _1955_ = _1934_ & _1946_;
- assign _1956_ = _1934_ & _0518_[0];
- assign _1957_ = _1935_ & _1946_;
- assign _1958_ = _1935_ & _0518_[0];
- assign _1959_ = _1936_ & _1946_;
- assign _1960_ = _1936_ & _0518_[0];
- assign _1961_ = _1937_ & _1946_;
- assign _1962_ = _1937_ & _0518_[0];
- assign _1963_ = _1938_ & _1946_;
- assign _1964_ = _1938_ & _0518_[0];
- assign _1965_ = _1939_ & _1946_;
- assign _1966_ = _1939_ & _0518_[0];
- assign _1967_ = _1940_ & _1946_;
- assign _1968_ = _1940_ & _0518_[0];
- assign _1969_ = _1941_ & _1946_;
- assign _1970_ = _1941_ & _0518_[0];
- assign _1971_ = _1942_ & _1946_;
- assign _1972_ = _1942_ & _0518_[0];
- assign _1973_ = _1943_ & _1946_;
- assign _1974_ = _1943_ & _0518_[0];
- assign _1975_ = _1944_ & _1946_;
- assign _1976_ = _1944_ & _0518_[0];
- assign _1977_ = _1945_ & _1946_;
- assign _1978_ = _1945_ & _0518_[0];
- assign _1979_ = _1947_ ? { ra[55:11], _1913_[44:0] } : _0515_[89:0];
- assign _1980_ = _1948_ ? { ra[55:11], _1913_[44:0] } : _0515_[179:90];
- assign _1981_ = _1949_ ? { ra[55:11], _1913_[44:0] } : _0515_[269:180];
- assign _1982_ = _1950_ ? { ra[55:11], _1913_[44:0] } : _0515_[359:270];
- assign _1983_ = _1951_ ? { ra[55:11], _1913_[44:0] } : _0515_[449:360];
- assign _1984_ = _1952_ ? { ra[55:11], _1913_[44:0] } : _0515_[539:450];
- assign _1985_ = _1953_ ? { ra[55:11], _1913_[44:0] } : _0515_[629:540];
- assign _1986_ = _1954_ ? { ra[55:11], _1913_[44:0] } : _0515_[719:630];
- assign _1987_ = _1955_ ? { ra[55:11], _1913_[44:0] } : _0515_[809:720];
- assign _1988_ = _1956_ ? { ra[55:11], _1913_[44:0] } : _0515_[899:810];
- assign _1989_ = _1957_ ? { ra[55:11], _1913_[44:0] } : _0515_[989:900];
- assign _1990_ = _1958_ ? { ra[55:11], _1913_[44:0] } : _0515_[1079:990];
- assign _1991_ = _1959_ ? { ra[55:11], _1913_[44:0] } : _0515_[1169:1080];
- assign _1992_ = _1960_ ? { ra[55:11], _1913_[44:0] } : _0515_[1259:1170];
- assign _1993_ = _1961_ ? { ra[55:11], _1913_[44:0] } : _0515_[1349:1260];
- assign _1994_ = _1962_ ? { ra[55:11], _1913_[44:0] } : _0515_[1439:1350];
- assign _1995_ = _1963_ ? { ra[55:11], _1913_[44:0] } : _0515_[1529:1440];
- assign _1996_ = _1964_ ? { ra[55:11], _1913_[44:0] } : _0515_[1619:1530];
- assign _1997_ = _1965_ ? { ra[55:11], _1913_[44:0] } : _0515_[1709:1620];
- assign _1998_ = _1966_ ? { ra[55:11], _1913_[44:0] } : _0515_[1799:1710];
- assign _1999_ = _1967_ ? { ra[55:11], _1913_[44:0] } : _0515_[1889:1800];
- assign _2000_ = _1968_ ? { ra[55:11], _1913_[44:0] } : _0515_[1979:1890];
- assign _2001_ = _1969_ ? { ra[55:11], _1913_[44:0] } : _0515_[2069:1980];
- assign _2002_ = _1970_ ? { ra[55:11], _1913_[44:0] } : _0515_[2159:2070];
- assign _2003_ = _1971_ ? { ra[55:11], _1913_[44:0] } : _0515_[2249:2160];
- assign _2004_ = _1972_ ? { ra[55:11], _1913_[44:0] } : _0515_[2339:2250];
- assign _2005_ = _1973_ ? { ra[55:11], _1913_[44:0] } : _0515_[2429:2340];
- assign _2006_ = _1974_ ? { ra[55:11], _1913_[44:0] } : _0515_[2519:2430];
- assign _2007_ = _1975_ ? { ra[55:11], _1913_[44:0] } : _0515_[2609:2520];
- assign _2008_ = _1976_ ? { ra[55:11], _1913_[44:0] } : _0515_[2699:2610];
- assign _2009_ = _1977_ ? { ra[55:11], _1913_[44:0] } : _0515_[2789:2700];
- assign _2010_ = _1978_ ? { ra[55:11], _1913_[44:0] } : _0515_[2879:2790];
- assign _2011_ = ~ _0529_[4];
- assign _2012_ = ~ _0529_[3];
- assign _2013_ = _2011_ & _2012_;
- assign _2014_ = _2011_ & _0529_[3];
- assign _2015_ = _0529_[4] & _2012_;
- assign _2016_ = _0529_[4] & _0529_[3];
- assign _2017_ = ~ _0529_[2];
- assign _2018_ = _2013_ & _2017_;
- assign _2019_ = _2013_ & _0529_[2];
- assign _2020_ = _2014_ & _2017_;
- assign _2021_ = _2014_ & _0529_[2];
- assign _2022_ = _2015_ & _2017_;
- assign _2023_ = _2015_ & _0529_[2];
- assign _2024_ = _2016_ & _2017_;
- assign _2025_ = _2016_ & _0529_[2];
- assign _2026_ = ~ _0529_[1];
- assign _2027_ = _2018_ & _2026_;
- assign _2028_ = _2018_ & _0529_[1];
- assign _2029_ = _2019_ & _2026_;
- assign _2030_ = _2019_ & _0529_[1];
- assign _2031_ = _2020_ & _2026_;
- assign _2032_ = _2020_ & _0529_[1];
- assign _2033_ = _2021_ & _2026_;
- assign _2034_ = _2021_ & _0529_[1];
- assign _2035_ = _2022_ & _2026_;
- assign _2036_ = _2022_ & _0529_[1];
- assign _2037_ = _2023_ & _2026_;
- assign _2038_ = _2023_ & _0529_[1];
- assign _2039_ = _2024_ & _2026_;
- assign _2040_ = _2024_ & _0529_[1];
- assign _2041_ = _2025_ & _2026_;
- assign _2042_ = _2025_ & _0529_[1];
- assign _2043_ = ~ _0529_[0];
- assign _2044_ = _2027_ & _2043_;
- assign _2045_ = _2027_ & _0529_[0];
- assign _2046_ = _2028_ & _2043_;
- assign _2047_ = _2028_ & _0529_[0];
- assign _2048_ = _2029_ & _2043_;
- assign _2049_ = _2029_ & _0529_[0];
- assign _2050_ = _2030_ & _2043_;
- assign _2051_ = _2030_ & _0529_[0];
- assign _2052_ = _2031_ & _2043_;
- assign _2053_ = _2031_ & _0529_[0];
- assign _2054_ = _2032_ & _2043_;
- assign _2055_ = _2032_ & _0529_[0];
- assign _2056_ = _2033_ & _2043_;
- assign _2057_ = _2033_ & _0529_[0];
- assign _2058_ = _2034_ & _2043_;
- assign _2059_ = _2034_ & _0529_[0];
- assign _2060_ = _2035_ & _2043_;
- assign _2061_ = _2035_ & _0529_[0];
- assign _2062_ = _2036_ & _2043_;
- assign _2063_ = _2036_ & _0529_[0];
- assign _2064_ = _2037_ & _2043_;
- assign _2065_ = _2037_ & _0529_[0];
- assign _2066_ = _2038_ & _2043_;
- assign _2067_ = _2038_ & _0529_[0];
- assign _2068_ = _2039_ & _2043_;
- assign _2069_ = _2039_ & _0529_[0];
- assign _2070_ = _2040_ & _2043_;
- assign _2071_ = _2040_ & _0529_[0];
- assign _2072_ = _2041_ & _2043_;
- assign _2073_ = _2041_ & _0529_[0];
- assign _2074_ = _2042_ & _2043_;
- assign _2075_ = _2042_ & _0529_[0];
- assign _2076_ = ~ replace_way;
- assign _2077_ = _2044_ & _2076_;
- assign _2078_ = _2044_ & replace_way;
- assign _2079_ = _2045_ & _2076_;
- assign _2080_ = _2045_ & replace_way;
- assign _2081_ = _2046_ & _2076_;
- assign _2082_ = _2046_ & replace_way;
- assign _2083_ = _2047_ & _2076_;
- assign _2084_ = _2047_ & replace_way;
- assign _2085_ = _2048_ & _2076_;
- assign _2086_ = _2048_ & replace_way;
- assign _2087_ = _2049_ & _2076_;
- assign _2088_ = _2049_ & replace_way;
- assign _2089_ = _2050_ & _2076_;
- assign _2090_ = _2050_ & replace_way;
- assign _2091_ = _2051_ & _2076_;
- assign _2092_ = _2051_ & replace_way;
- assign _2093_ = _2052_ & _2076_;
- assign _2094_ = _2052_ & replace_way;
- assign _2095_ = _2053_ & _2076_;
- assign _2096_ = _2053_ & replace_way;
- assign _2097_ = _2054_ & _2076_;
- assign _2098_ = _2054_ & replace_way;
- assign _2099_ = _2055_ & _2076_;
- assign _2100_ = _2055_ & replace_way;
- assign _2101_ = _2056_ & _2076_;
- assign _2102_ = _2056_ & replace_way;
- assign _2103_ = _2057_ & _2076_;
- assign _2104_ = _2057_ & replace_way;
- assign _2105_ = _2058_ & _2076_;
- assign _2106_ = _2058_ & replace_way;
- assign _2107_ = _2059_ & _2076_;
- assign _2108_ = _2059_ & replace_way;
- assign _2109_ = _2060_ & _2076_;
- assign _2110_ = _2060_ & replace_way;
- assign _2111_ = _2061_ & _2076_;
- assign _2112_ = _2061_ & replace_way;
- assign _2113_ = _2062_ & _2076_;
- assign _2114_ = _2062_ & replace_way;
- assign _2115_ = _2063_ & _2076_;
- assign _2116_ = _2063_ & replace_way;
- assign _2117_ = _2064_ & _2076_;
- assign _2118_ = _2064_ & replace_way;
- assign _2119_ = _2065_ & _2076_;
- assign _2120_ = _2065_ & replace_way;
- assign _2121_ = _2066_ & _2076_;
- assign _2122_ = _2066_ & replace_way;
- assign _2123_ = _2067_ & _2076_;
- assign _2124_ = _2067_ & replace_way;
- assign _2125_ = _2068_ & _2076_;
- assign _2126_ = _2068_ & replace_way;
- assign _2127_ = _2069_ & _2076_;
- assign _2128_ = _2069_ & replace_way;
- assign _2129_ = _2070_ & _2076_;
- assign _2130_ = _2070_ & replace_way;
- assign _2131_ = _2071_ & _2076_;
- assign _2132_ = _2071_ & replace_way;
- assign _2133_ = _2072_ & _2076_;
- assign _2134_ = _2072_ & replace_way;
- assign _2135_ = _2073_ & _2076_;
- assign _2136_ = _2073_ & replace_way;
- assign _2137_ = _2074_ & _2076_;
- assign _2138_ = _2074_ & replace_way;
- assign _2139_ = _2075_ & _2076_;
- assign _2140_ = _2075_ & replace_way;
- assign _2141_ = _2077_ ? 1'h0 : cache_valids[0];
- assign _2142_ = _2078_ ? 1'h0 : cache_valids[1];
- assign _2143_ = _2079_ ? 1'h0 : cache_valids[2];
- assign _2144_ = _2080_ ? 1'h0 : cache_valids[3];
- assign _2145_ = _2081_ ? 1'h0 : cache_valids[4];
- assign _2146_ = _2082_ ? 1'h0 : cache_valids[5];
- assign _2147_ = _2083_ ? 1'h0 : cache_valids[6];
- assign _2148_ = _2084_ ? 1'h0 : cache_valids[7];
- assign _2149_ = _2085_ ? 1'h0 : cache_valids[8];
- assign _2150_ = _2086_ ? 1'h0 : cache_valids[9];
- assign _2151_ = _2087_ ? 1'h0 : cache_valids[10];
- assign _2152_ = _2088_ ? 1'h0 : cache_valids[11];
- assign _2153_ = _2089_ ? 1'h0 : cache_valids[12];
- assign _2154_ = _2090_ ? 1'h0 : cache_valids[13];
- assign _2155_ = _2091_ ? 1'h0 : cache_valids[14];
- assign _2156_ = _2092_ ? 1'h0 : cache_valids[15];
- assign _2157_ = _2093_ ? 1'h0 : cache_valids[16];
- assign _2158_ = _2094_ ? 1'h0 : cache_valids[17];
- assign _2159_ = _2095_ ? 1'h0 : cache_valids[18];
- assign _2160_ = _2096_ ? 1'h0 : cache_valids[19];
- assign _2161_ = _2097_ ? 1'h0 : cache_valids[20];
- assign _2162_ = _2098_ ? 1'h0 : cache_valids[21];
- assign _2163_ = _2099_ ? 1'h0 : cache_valids[22];
- assign _2164_ = _2100_ ? 1'h0 : cache_valids[23];
- assign _2165_ = _2101_ ? 1'h0 : cache_valids[24];
- assign _2166_ = _2102_ ? 1'h0 : cache_valids[25];
- assign _2167_ = _2103_ ? 1'h0 : cache_valids[26];
- assign _2168_ = _2104_ ? 1'h0 : cache_valids[27];
- assign _2169_ = _2105_ ? 1'h0 : cache_valids[28];
- assign _2170_ = _2106_ ? 1'h0 : cache_valids[29];
- assign _2171_ = _2107_ ? 1'h0 : cache_valids[30];
- assign _2172_ = _2108_ ? 1'h0 : cache_valids[31];
- assign _2173_ = _2109_ ? 1'h0 : cache_valids[32];
- assign _2174_ = _2110_ ? 1'h0 : cache_valids[33];
- assign _2175_ = _2111_ ? 1'h0 : cache_valids[34];
- assign _2176_ = _2112_ ? 1'h0 : cache_valids[35];
- assign _2177_ = _2113_ ? 1'h0 : cache_valids[36];
- assign _2178_ = _2114_ ? 1'h0 : cache_valids[37];
- assign _2179_ = _2115_ ? 1'h0 : cache_valids[38];
- assign _2180_ = _2116_ ? 1'h0 : cache_valids[39];
- assign _2181_ = _2117_ ? 1'h0 : cache_valids[40];
- assign _2182_ = _2118_ ? 1'h0 : cache_valids[41];
- assign _2183_ = _2119_ ? 1'h0 : cache_valids[42];
- assign _2184_ = _2120_ ? 1'h0 : cache_valids[43];
- assign _2185_ = _2121_ ? 1'h0 : cache_valids[44];
- assign _2186_ = _2122_ ? 1'h0 : cache_valids[45];
- assign _2187_ = _2123_ ? 1'h0 : cache_valids[46];
- assign _2188_ = _2124_ ? 1'h0 : cache_valids[47];
- assign _2189_ = _2125_ ? 1'h0 : cache_valids[48];
- assign _2190_ = _2126_ ? 1'h0 : cache_valids[49];
- assign _2191_ = _2127_ ? 1'h0 : cache_valids[50];
- assign _2192_ = _2128_ ? 1'h0 : cache_valids[51];
- assign _2193_ = _2129_ ? 1'h0 : cache_valids[52];
- assign _2194_ = _2130_ ? 1'h0 : cache_valids[53];
- assign _2195_ = _2131_ ? 1'h0 : cache_valids[54];
- assign _2196_ = _2132_ ? 1'h0 : cache_valids[55];
- assign _2197_ = _2133_ ? 1'h0 : cache_valids[56];
- assign _2198_ = _2134_ ? 1'h0 : cache_valids[57];
- assign _2199_ = _2135_ ? 1'h0 : cache_valids[58];
- assign _2200_ = _2136_ ? 1'h0 : cache_valids[59];
- assign _2201_ = _2137_ ? 1'h0 : cache_valids[60];
- assign _2202_ = _2138_ ? 1'h0 : cache_valids[61];
- assign _2203_ = _2139_ ? 1'h0 : cache_valids[62];
- assign _2204_ = _2140_ ? 1'h0 : cache_valids[63];
- assign _2215_ = _0531_[4] ? _2214_ : _2213_;
- assign _2216_ = ~ _0532_[4];
- assign _2217_ = ~ _0532_[3];
- assign _2218_ = _2216_ & _2217_;
- assign _2219_ = _2216_ & _0532_[3];
- assign _2220_ = _0532_[4] & _2217_;
- assign _2221_ = _0532_[4] & _0532_[3];
- assign _2222_ = ~ _0532_[2];
- assign _2223_ = _2218_ & _2222_;
- assign _2224_ = _2218_ & _0532_[2];
- assign _2225_ = _2219_ & _2222_;
- assign _2226_ = _2219_ & _0532_[2];
- assign _2227_ = _2220_ & _2222_;
- assign _2228_ = _2220_ & _0532_[2];
- assign _2229_ = _2221_ & _2222_;
- assign _2230_ = _2221_ & _0532_[2];
- assign _2231_ = ~ _0532_[1];
- assign _2232_ = _2223_ & _2231_;
- assign _2233_ = _2223_ & _0532_[1];
- assign _2234_ = _2224_ & _2231_;
- assign _2235_ = _2224_ & _0532_[1];
- assign _2236_ = _2225_ & _2231_;
- assign _2237_ = _2225_ & _0532_[1];
- assign _2238_ = _2226_ & _2231_;
- assign _2239_ = _2226_ & _0532_[1];
- assign _2240_ = _2227_ & _2231_;
- assign _2241_ = _2227_ & _0532_[1];
- assign _2242_ = _2228_ & _2231_;
- assign _2243_ = _2228_ & _0532_[1];
- assign _2244_ = _2229_ & _2231_;
- assign _2245_ = _2229_ & _0532_[1];
- assign _2246_ = _2230_ & _2231_;
- assign _2247_ = _2230_ & _0532_[1];
- assign _2248_ = ~ _0532_[0];
- assign _2249_ = _2232_ & _2248_;
- assign _2250_ = _2232_ & _0532_[0];
- assign _2251_ = _2233_ & _2248_;
- assign _2252_ = _2233_ & _0532_[0];
- assign _2253_ = _2234_ & _2248_;
- assign _2254_ = _2234_ & _0532_[0];
- assign _2255_ = _2235_ & _2248_;
- assign _2256_ = _2235_ & _0532_[0];
- assign _2257_ = _2236_ & _2248_;
- assign _2258_ = _2236_ & _0532_[0];
- assign _2259_ = _2237_ & _2248_;
- assign _2260_ = _2237_ & _0532_[0];
- assign _2261_ = _2238_ & _2248_;
- assign _2262_ = _2238_ & _0532_[0];
- assign _2263_ = _2239_ & _2248_;
- assign _2264_ = _2239_ & _0532_[0];
- assign _2265_ = _2240_ & _2248_;
- assign _2266_ = _2240_ & _0532_[0];
- assign _2267_ = _2241_ & _2248_;
- assign _2268_ = _2241_ & _0532_[0];
- assign _2269_ = _2242_ & _2248_;
- assign _2270_ = _2242_ & _0532_[0];
- assign _2271_ = _2243_ & _2248_;
- assign _2272_ = _2243_ & _0532_[0];
- assign _2273_ = _2244_ & _2248_;
- assign _2274_ = _2244_ & _0532_[0];
- assign _2275_ = _2245_ & _2248_;
- assign _2276_ = _2245_ & _0532_[0];
- assign _2277_ = _2246_ & _2248_;
- assign _2278_ = _2246_ & _0532_[0];
- assign _2279_ = _2247_ & _2248_;
- assign _2280_ = _2247_ & _0532_[0];
- assign _2281_ = _2249_ ? { _2215_[89:45], ra[55:11] } : cache_tags[89:0];
- assign _2282_ = _2250_ ? { _2215_[89:45], ra[55:11] } : cache_tags[179:90];
- assign _2283_ = _2251_ ? { _2215_[89:45], ra[55:11] } : cache_tags[269:180];
- assign _2284_ = _2252_ ? { _2215_[89:45], ra[55:11] } : cache_tags[359:270];
- assign _2285_ = _2253_ ? { _2215_[89:45], ra[55:11] } : cache_tags[449:360];
- assign _2286_ = _2254_ ? { _2215_[89:45], ra[55:11] } : cache_tags[539:450];
- assign _2287_ = _2255_ ? { _2215_[89:45], ra[55:11] } : cache_tags[629:540];
- assign _2288_ = _2256_ ? { _2215_[89:45], ra[55:11] } : cache_tags[719:630];
- assign _2289_ = _2257_ ? { _2215_[89:45], ra[55:11] } : cache_tags[809:720];
- assign _2290_ = _2258_ ? { _2215_[89:45], ra[55:11] } : cache_tags[899:810];
- assign _2291_ = _2259_ ? { _2215_[89:45], ra[55:11] } : cache_tags[989:900];
- assign _2292_ = _2260_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1079:990];
- assign _2293_ = _2261_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1169:1080];
- assign _2294_ = _2262_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1259:1170];
- assign _2295_ = _2263_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1349:1260];
- assign _2296_ = _2264_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1439:1350];
- assign _2297_ = _2265_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1529:1440];
- assign _2298_ = _2266_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1619:1530];
- assign _2299_ = _2267_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1709:1620];
- assign _2300_ = _2268_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1799:1710];
- assign _2301_ = _2269_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1889:1800];
- assign _2302_ = _2270_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1979:1890];
- assign _2303_ = _2271_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2069:1980];
- assign _2304_ = _2272_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2159:2070];
- assign _2305_ = _2273_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2249:2160];
- assign _2306_ = _2274_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2339:2250];
- assign _2307_ = _2275_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2429:2340];
- assign _2308_ = _2276_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2519:2430];
- assign _2309_ = _2277_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2609:2520];
- assign _2310_ = _2278_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2699:2610];
- assign _2311_ = _2279_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2789:2700];
- assign _2312_ = _2280_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2879:2790];
- assign _2323_ = _0535_[4] ? _2322_ : _2321_;
- assign _2324_ = ~ _0536_[4];
- assign _2325_ = ~ _0536_[3];
- assign _2326_ = _2324_ & _2325_;
- assign _2327_ = _2324_ & _0536_[3];
- assign _2328_ = _0536_[4] & _2325_;
- assign _2329_ = _0536_[4] & _0536_[3];
- assign _2330_ = ~ _0536_[2];
- assign _2331_ = _2326_ & _2330_;
- assign _2332_ = _2326_ & _0536_[2];
- assign _2333_ = _2327_ & _2330_;
- assign _2334_ = _2327_ & _0536_[2];
- assign _2335_ = _2328_ & _2330_;
- assign _2336_ = _2328_ & _0536_[2];
- assign _2337_ = _2329_ & _2330_;
- assign _2338_ = _2329_ & _0536_[2];
- assign _2339_ = ~ _0536_[1];
- assign _2340_ = _2331_ & _2339_;
- assign _2341_ = _2331_ & _0536_[1];
- assign _2342_ = _2332_ & _2339_;
- assign _2343_ = _2332_ & _0536_[1];
- assign _2344_ = _2333_ & _2339_;
- assign _2345_ = _2333_ & _0536_[1];
- assign _2346_ = _2334_ & _2339_;
- assign _2347_ = _2334_ & _0536_[1];
- assign _2348_ = _2335_ & _2339_;
- assign _2349_ = _2335_ & _0536_[1];
- assign _2350_ = _2336_ & _2339_;
- assign _2351_ = _2336_ & _0536_[1];
- assign _2352_ = _2337_ & _2339_;
- assign _2353_ = _2337_ & _0536_[1];
- assign _2354_ = _2338_ & _2339_;
- assign _2355_ = _2338_ & _0536_[1];
- assign _2356_ = ~ _0536_[0];
- assign _2357_ = _2340_ & _2356_;
- assign _2358_ = _2340_ & _0536_[0];
- assign _2359_ = _2341_ & _2356_;
- assign _2360_ = _2341_ & _0536_[0];
- assign _2361_ = _2342_ & _2356_;
- assign _2362_ = _2342_ & _0536_[0];
- assign _2363_ = _2343_ & _2356_;
- assign _2364_ = _2343_ & _0536_[0];
- assign _2365_ = _2344_ & _2356_;
- assign _2366_ = _2344_ & _0536_[0];
- assign _2367_ = _2345_ & _2356_;
- assign _2368_ = _2345_ & _0536_[0];
- assign _2369_ = _2346_ & _2356_;
- assign _2370_ = _2346_ & _0536_[0];
- assign _2371_ = _2347_ & _2356_;
- assign _2372_ = _2347_ & _0536_[0];
- assign _2373_ = _2348_ & _2356_;
- assign _2374_ = _2348_ & _0536_[0];
- assign _2375_ = _2349_ & _2356_;
- assign _2376_ = _2349_ & _0536_[0];
- assign _2377_ = _2350_ & _2356_;
- assign _2378_ = _2350_ & _0536_[0];
- assign _2379_ = _2351_ & _2356_;
- assign _2380_ = _2351_ & _0536_[0];
- assign _2381_ = _2352_ & _2356_;
- assign _2382_ = _2352_ & _0536_[0];
- assign _2383_ = _2353_ & _2356_;
- assign _2384_ = _2353_ & _0536_[0];
- assign _2385_ = _2354_ & _2356_;
- assign _2386_ = _2354_ & _0536_[0];
- assign _2387_ = _2355_ & _2356_;
- assign _2388_ = _2355_ & _0536_[0];
- assign _2389_ = _2357_ ? { ra[55:11], _2323_[44:0] } : _0533_[89:0];
- assign _2390_ = _2358_ ? { ra[55:11], _2323_[44:0] } : _0533_[179:90];
- assign _2391_ = _2359_ ? { ra[55:11], _2323_[44:0] } : _0533_[269:180];
- assign _2392_ = _2360_ ? { ra[55:11], _2323_[44:0] } : _0533_[359:270];
- assign _2393_ = _2361_ ? { ra[55:11], _2323_[44:0] } : _0533_[449:360];
- assign _2394_ = _2362_ ? { ra[55:11], _2323_[44:0] } : _0533_[539:450];
- assign _2395_ = _2363_ ? { ra[55:11], _2323_[44:0] } : _0533_[629:540];
- assign _2396_ = _2364_ ? { ra[55:11], _2323_[44:0] } : _0533_[719:630];
- assign _2397_ = _2365_ ? { ra[55:11], _2323_[44:0] } : _0533_[809:720];
- assign _2398_ = _2366_ ? { ra[55:11], _2323_[44:0] } : _0533_[899:810];
- assign _2399_ = _2367_ ? { ra[55:11], _2323_[44:0] } : _0533_[989:900];
- assign _2400_ = _2368_ ? { ra[55:11], _2323_[44:0] } : _0533_[1079:990];
- assign _2401_ = _2369_ ? { ra[55:11], _2323_[44:0] } : _0533_[1169:1080];
- assign _2402_ = _2370_ ? { ra[55:11], _2323_[44:0] } : _0533_[1259:1170];
- assign _2403_ = _2371_ ? { ra[55:11], _2323_[44:0] } : _0533_[1349:1260];
- assign _2404_ = _2372_ ? { ra[55:11], _2323_[44:0] } : _0533_[1439:1350];
- assign _2405_ = _2373_ ? { ra[55:11], _2323_[44:0] } : _0533_[1529:1440];
- assign _2406_ = _2374_ ? { ra[55:11], _2323_[44:0] } : _0533_[1619:1530];
- assign _2407_ = _2375_ ? { ra[55:11], _2323_[44:0] } : _0533_[1709:1620];
- assign _2408_ = _2376_ ? { ra[55:11], _2323_[44:0] } : _0533_[1799:1710];
- assign _2409_ = _2377_ ? { ra[55:11], _2323_[44:0] } : _0533_[1889:1800];
- assign _2410_ = _2378_ ? { ra[55:11], _2323_[44:0] } : _0533_[1979:1890];
- assign _2411_ = _2379_ ? { ra[55:11], _2323_[44:0] } : _0533_[2069:1980];
- assign _2412_ = _2380_ ? { ra[55:11], _2323_[44:0] } : _0533_[2159:2070];
- assign _2413_ = _2381_ ? { ra[55:11], _2323_[44:0] } : _0533_[2249:2160];
- assign _2414_ = _2382_ ? { ra[55:11], _2323_[44:0] } : _0533_[2339:2250];
- assign _2415_ = _2383_ ? { ra[55:11], _2323_[44:0] } : _0533_[2429:2340];
- assign _2416_ = _2384_ ? { ra[55:11], _2323_[44:0] } : _0533_[2519:2430];
- assign _2417_ = _2385_ ? { ra[55:11], _2323_[44:0] } : _0533_[2609:2520];
- assign _2418_ = _2386_ ? { ra[55:11], _2323_[44:0] } : _0533_[2699:2610];
- assign _2419_ = _2387_ ? { ra[55:11], _2323_[44:0] } : _0533_[2789:2700];
- assign _2420_ = _2388_ ? { ra[55:11], _2323_[44:0] } : _0533_[2879:2790];
- assign _2421_ = ~ _0583_[4];
- assign _2422_ = ~ _0583_[3];
- assign _2423_ = _2421_ & _2422_;
- assign _2424_ = _2421_ & _0583_[3];
- assign _2425_ = _0583_[4] & _2422_;
- assign _2426_ = _0583_[4] & _0583_[3];
- assign _2427_ = ~ _0583_[2];
- assign _2428_ = _2423_ & _2427_;
- assign _2429_ = _2423_ & _0583_[2];
- assign _2430_ = _2424_ & _2427_;
- assign _2431_ = _2424_ & _0583_[2];
- assign _2432_ = _2425_ & _2427_;
- assign _2433_ = _2425_ & _0583_[2];
- assign _2434_ = _2426_ & _2427_;
- assign _2435_ = _2426_ & _0583_[2];
- assign _2436_ = ~ _0583_[1];
- assign _2437_ = _2428_ & _2436_;
- assign _2438_ = _2428_ & _0583_[1];
- assign _2439_ = _2429_ & _2436_;
- assign _2440_ = _2429_ & _0583_[1];
- assign _2441_ = _2430_ & _2436_;
- assign _2442_ = _2430_ & _0583_[1];
- assign _2443_ = _2431_ & _2436_;
- assign _2444_ = _2431_ & _0583_[1];
- assign _2445_ = _2432_ & _2436_;
- assign _2446_ = _2432_ & _0583_[1];
- assign _2447_ = _2433_ & _2436_;
- assign _2448_ = _2433_ & _0583_[1];
- assign _2449_ = _2434_ & _2436_;
- assign _2450_ = _2434_ & _0583_[1];
- assign _2451_ = _2435_ & _2436_;
- assign _2452_ = _2435_ & _0583_[1];
- assign _2453_ = ~ _0583_[0];
- assign _2454_ = _2437_ & _2453_;
- assign _2455_ = _2437_ & _0583_[0];
- assign _2456_ = _2438_ & _2453_;
- assign _2457_ = _2438_ & _0583_[0];
- assign _2458_ = _2439_ & _2453_;
- assign _2459_ = _2439_ & _0583_[0];
- assign _2460_ = _2440_ & _2453_;
- assign _2461_ = _2440_ & _0583_[0];
- assign _2462_ = _2441_ & _2453_;
- assign _2463_ = _2441_ & _0583_[0];
- assign _2464_ = _2442_ & _2453_;
- assign _2465_ = _2442_ & _0583_[0];
- assign _2466_ = _2443_ & _2453_;
- assign _2467_ = _2443_ & _0583_[0];
- assign _2468_ = _2444_ & _2453_;
- assign _2469_ = _2444_ & _0583_[0];
- assign _2470_ = _2445_ & _2453_;
- assign _2471_ = _2445_ & _0583_[0];
- assign _2472_ = _2446_ & _2453_;
- assign _2473_ = _2446_ & _0583_[0];
- assign _2474_ = _2447_ & _2453_;
- assign _2475_ = _2447_ & _0583_[0];
- assign _2476_ = _2448_ & _2453_;
- assign _2477_ = _2448_ & _0583_[0];
- assign _2478_ = _2449_ & _2453_;
- assign _2479_ = _2449_ & _0583_[0];
- assign _2480_ = _2450_ & _2453_;
- assign _2481_ = _2450_ & _0583_[0];
- assign _2482_ = _2451_ & _2453_;
- assign _2483_ = _2451_ & _0583_[0];
- assign _2484_ = _2452_ & _2453_;
- assign _2485_ = _2452_ & _0583_[0];
- assign _2486_ = ~ _0629_[176];
- assign _2487_ = _2454_ & _2486_;
- assign _2488_ = _2454_ & _0629_[176];
- assign _2489_ = _2455_ & _2486_;
- assign _2490_ = _2455_ & _0629_[176];
- assign _2491_ = _2456_ & _2486_;
- assign _2492_ = _2456_ & _0629_[176];
- assign _2493_ = _2457_ & _2486_;
- assign _2494_ = _2457_ & _0629_[176];
- assign _2495_ = _2458_ & _2486_;
- assign _2496_ = _2458_ & _0629_[176];
- assign _2497_ = _2459_ & _2486_;
- assign _2498_ = _2459_ & _0629_[176];
- assign _2499_ = _2460_ & _2486_;
- assign _2500_ = _2460_ & _0629_[176];
- assign _2501_ = _2461_ & _2486_;
- assign _2502_ = _2461_ & _0629_[176];
- assign _2503_ = _2462_ & _2486_;
- assign _2504_ = _2462_ & _0629_[176];
- assign _2505_ = _2463_ & _2486_;
- assign _2506_ = _2463_ & _0629_[176];
- assign _2507_ = _2464_ & _2486_;
- assign _2508_ = _2464_ & _0629_[176];
- assign _2509_ = _2465_ & _2486_;
- assign _2510_ = _2465_ & _0629_[176];
- assign _2511_ = _2466_ & _2486_;
- assign _2512_ = _2466_ & _0629_[176];
- assign _2513_ = _2467_ & _2486_;
- assign _2514_ = _2467_ & _0629_[176];
- assign _2515_ = _2468_ & _2486_;
- assign _2516_ = _2468_ & _0629_[176];
- assign _2517_ = _2469_ & _2486_;
- assign _2518_ = _2469_ & _0629_[176];
- assign _2519_ = _2470_ & _2486_;
- assign _2520_ = _2470_ & _0629_[176];
- assign _2521_ = _2471_ & _2486_;
- assign _2522_ = _2471_ & _0629_[176];
- assign _2523_ = _2472_ & _2486_;
- assign _2524_ = _2472_ & _0629_[176];
- assign _2525_ = _2473_ & _2486_;
- assign _2526_ = _2473_ & _0629_[176];
- assign _2527_ = _2474_ & _2486_;
- assign _2528_ = _2474_ & _0629_[176];
- assign _2529_ = _2475_ & _2486_;
- assign _2530_ = _2475_ & _0629_[176];
- assign _2531_ = _2476_ & _2486_;
- assign _2532_ = _2476_ & _0629_[176];
- assign _2533_ = _2477_ & _2486_;
- assign _2534_ = _2477_ & _0629_[176];
- assign _2535_ = _2478_ & _2486_;
- assign _2536_ = _2478_ & _0629_[176];
- assign _2537_ = _2479_ & _2486_;
- assign _2538_ = _2479_ & _0629_[176];
- assign _2539_ = _2480_ & _2486_;
- assign _2540_ = _2480_ & _0629_[176];
- assign _2541_ = _2481_ & _2486_;
- assign _2542_ = _2481_ & _0629_[176];
- assign _2543_ = _2482_ & _2486_;
- assign _2544_ = _2482_ & _0629_[176];
- assign _2545_ = _2483_ & _2486_;
- assign _2546_ = _2483_ & _0629_[176];
- assign _2547_ = _2484_ & _2486_;
- assign _2548_ = _2484_ & _0629_[176];
- assign _2549_ = _2485_ & _2486_;
- assign _2550_ = _2485_ & _0629_[176];
- assign _2551_ = _2487_ ? 1'h1 : cache_valids[0];
- assign _2552_ = _2488_ ? 1'h1 : cache_valids[1];
- assign _2553_ = _2489_ ? 1'h1 : cache_valids[2];
- assign _2554_ = _2490_ ? 1'h1 : cache_valids[3];
- assign _2555_ = _2491_ ? 1'h1 : cache_valids[4];
- assign _2556_ = _2492_ ? 1'h1 : cache_valids[5];
- assign _2557_ = _2493_ ? 1'h1 : cache_valids[6];
- assign _2558_ = _2494_ ? 1'h1 : cache_valids[7];
- assign _2559_ = _2495_ ? 1'h1 : cache_valids[8];
- assign _2560_ = _2496_ ? 1'h1 : cache_valids[9];
- assign _2561_ = _2497_ ? 1'h1 : cache_valids[10];
- assign _2562_ = _2498_ ? 1'h1 : cache_valids[11];
- assign _2563_ = _2499_ ? 1'h1 : cache_valids[12];
- assign _2564_ = _2500_ ? 1'h1 : cache_valids[13];
- assign _2565_ = _2501_ ? 1'h1 : cache_valids[14];
- assign _2566_ = _2502_ ? 1'h1 : cache_valids[15];
- assign _2567_ = _2503_ ? 1'h1 : cache_valids[16];
- assign _2568_ = _2504_ ? 1'h1 : cache_valids[17];
- assign _2569_ = _2505_ ? 1'h1 : cache_valids[18];
- assign _2570_ = _2506_ ? 1'h1 : cache_valids[19];
- assign _2571_ = _2507_ ? 1'h1 : cache_valids[20];
- assign _2572_ = _2508_ ? 1'h1 : cache_valids[21];
- assign _2573_ = _2509_ ? 1'h1 : cache_valids[22];
- assign _2574_ = _2510_ ? 1'h1 : cache_valids[23];
- assign _2575_ = _2511_ ? 1'h1 : cache_valids[24];
- assign _2576_ = _2512_ ? 1'h1 : cache_valids[25];
- assign _2577_ = _2513_ ? 1'h1 : cache_valids[26];
- assign _2578_ = _2514_ ? 1'h1 : cache_valids[27];
- assign _2579_ = _2515_ ? 1'h1 : cache_valids[28];
- assign _2580_ = _2516_ ? 1'h1 : cache_valids[29];
- assign _2581_ = _2517_ ? 1'h1 : cache_valids[30];
- assign _2582_ = _2518_ ? 1'h1 : cache_valids[31];
- assign _2583_ = _2519_ ? 1'h1 : cache_valids[32];
- assign _2584_ = _2520_ ? 1'h1 : cache_valids[33];
- assign _2585_ = _2521_ ? 1'h1 : cache_valids[34];
- assign _2586_ = _2522_ ? 1'h1 : cache_valids[35];
- assign _2587_ = _2523_ ? 1'h1 : cache_valids[36];
- assign _2588_ = _2524_ ? 1'h1 : cache_valids[37];
- assign _2589_ = _2525_ ? 1'h1 : cache_valids[38];
- assign _2590_ = _2526_ ? 1'h1 : cache_valids[39];
- assign _2591_ = _2527_ ? 1'h1 : cache_valids[40];
- assign _2592_ = _2528_ ? 1'h1 : cache_valids[41];
- assign _2593_ = _2529_ ? 1'h1 : cache_valids[42];
- assign _2594_ = _2530_ ? 1'h1 : cache_valids[43];
- assign _2595_ = _2531_ ? 1'h1 : cache_valids[44];
- assign _2596_ = _2532_ ? 1'h1 : cache_valids[45];
- assign _2597_ = _2533_ ? 1'h1 : cache_valids[46];
- assign _2598_ = _2534_ ? 1'h1 : cache_valids[47];
- assign _2599_ = _2535_ ? 1'h1 : cache_valids[48];
- assign _2600_ = _2536_ ? 1'h1 : cache_valids[49];
- assign _2601_ = _2537_ ? 1'h1 : cache_valids[50];
- assign _2602_ = _2538_ ? 1'h1 : cache_valids[51];
- assign _2603_ = _2539_ ? 1'h1 : cache_valids[52];
- assign _2604_ = _2540_ ? 1'h1 : cache_valids[53];
- assign _2605_ = _2541_ ? 1'h1 : cache_valids[54];
- assign _2606_ = _2542_ ? 1'h1 : cache_valids[55];
- assign _2607_ = _2543_ ? 1'h1 : cache_valids[56];
- assign _2608_ = _2544_ ? 1'h1 : cache_valids[57];
- assign _2609_ = _2545_ ? 1'h1 : cache_valids[58];
- assign _2610_ = _2546_ ? 1'h1 : cache_valids[59];
- assign _2611_ = _2547_ ? 1'h1 : cache_valids[60];
- assign _2612_ = _2548_ ? 1'h1 : cache_valids[61];
- assign _2613_ = _2549_ ? 1'h1 : cache_valids[62];
- assign _2614_ = _2550_ ? 1'h1 : cache_valids[63];
- plru_1 \maybe_plrus.plrus%0.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%0.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%0.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%1.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%1.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%1.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%10.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%10.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%10.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%11.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%11.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%11.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%12.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%12.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%12.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%13.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%13.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%13.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%14.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%14.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%14.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%15.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%15.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%15.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%16.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%16.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%16.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%17.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%17.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%17.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%18.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%18.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%18.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%19.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%19.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%19.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%2.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%2.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%2.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%20.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%20.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%20.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%21.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%21.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%21.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%22.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%22.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%22.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%23.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%23.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%23.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%24.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%24.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%24.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%25.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%25.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%25.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%26.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%26.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%26.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%27.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%27.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%27.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%28.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%28.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%28.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%29.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%29.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%29.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%3.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%3.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%3.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%30.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%30.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%30.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%31.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%31.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%31.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%4.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%4.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%4.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%5.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%5.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%5.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%6.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%6.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%6.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%7.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%7.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%7.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%8.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%8.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%8.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%9.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%9.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%9.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%0.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%1.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%10.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%11.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%12.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%13.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%14.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%15.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%16.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%17.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%18.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%19.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%2.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%20.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%21.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%22.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%23.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%24.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%25.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%26.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%27.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%28.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%29.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%3.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%30.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%31.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%32.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%33.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%34.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%35.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%36.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%37.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%38.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%39.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%4.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%40.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%41.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%42.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%43.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%44.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%45.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%46.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%47.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%48.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%49.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%5.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%50.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%51.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%52.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%53.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%54.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%55.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%56.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%57.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%58.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%59.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%6.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%60.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%61.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%62.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%63.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%7.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%8.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_tlb_plrus.tlb_plrus%9.tlb_plru (
- .acc(tlb_hit_way),
- .acc_en(\maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en ),
- .clk(clk),
- .lru(\maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ),
- .rst(rst)
- );
- cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546 \rams%0.way (
- .clk(clk),
- .rd_addr(early_req_row),
- .rd_data(\rams%0.dout ),
- .rd_en(1'h1),
- .wr_addr(\rams%0.wr_addr ),
- .wr_data(\rams%0.wr_data ),
- .wr_sel({ _0468_, _0467_, _0466_, _0465_, _0464_, _0463_, _0462_, _0461_ })
- );
- cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546 \rams%1.way (
- .clk(clk),
- .rd_addr(early_req_row),
- .rd_data(\rams%1.dout ),
- .rd_en(1'h1),
- .wr_addr(\rams%1.wr_addr ),
- .wr_data(\rams%1.wr_data ),
- .wr_sel({ _0494_, _0493_, _0492_, _0491_, _0490_, _0489_, _0488_, _0487_ })
- );
- assign d_out = _0441_;
- assign m_out = { _0442_, 1'h0 };
- assign stall_out = _0409_;
- assign wishbone_out = _0629_[175:69];
-endmodule
-
-module decode1(clk, rst, stall_in, flush_in, f_in, d_out);
- wire _00_;
- wire _01_;
- wire _02_;
- wire [147:0] _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire [9:0] _07_;
- wire _08_;
- wire [9:0] _09_;
- wire _10_;
- wire [2:0] _11_;
- wire [37:0] _12_;
- wire _13_;
- wire [3:0] _14_;
- wire _15_;
- wire [1:0] _16_;
- wire _17_;
- wire [1:0] _18_;
- wire [31:0] _19_;
- wire _20_;
- wire [5:0] _21_;
- wire [37:0] _22_;
- wire [37:0] _23_;
- wire [37:0] _24_;
- wire [37:0] _25_;
- wire [37:0] _26_;
- wire [37:0] _27_;
- wire _28_;
- wire [37:0] _29_;
- wire _30_;
- wire _31_;
- wire _32_;
- wire _33_;
- wire [5:0] _34_;
- wire _35_;
- wire _36_;
- wire [5:0] _37_;
- wire [5:0] _38_;
- wire _39_;
- wire _40_;
- wire _41_;
- wire _42_;
- wire _43_;
- wire _44_;
- wire _45_;
- wire _46_;
- wire _47_;
- wire _48_;
- wire _49_;
- wire _50_;
- wire _51_;
- wire _52_;
- wire _53_;
- wire _54_;
- wire _55_;
- wire _56_;
- wire _57_;
- wire [5:0] _58_;
- wire [4:0] _59_;
- wire [4:0] _60_;
- wire [5:0] _61_;
- wire _62_;
- wire _63_;
- wire _64_;
- wire _65_;
- wire _66_;
- wire _67_;
- wire _68_;
- wire _69_;
- wire [1:0] _70_;
- wire [1:0] _71_;
- wire _72_;
- wire _73_;
- wire [11:0] _74_;
- wire [5:0] _75_;
- wire [5:0] _76_;
- wire _77_;
- wire _78_;
- wire [11:0] _79_;
- wire [1:0] _80_;
- wire _81_;
- wire _82_;
- wire [38911:0] _83_;
- wire [37:0] _84_;
- wire [1023:0] _85_;
- wire _86_;
- wire [303:0] _87_;
- wire [37:0] _88_;
- wire [607:0] _89_;
- wire [37:0] _90_;
- wire [151:0] _91_;
- wire [37:0] _92_;
- wire [151:0] _93_;
- wire [37:0] _94_;
- wire [2431:0] _95_;
- wire [37:0] _96_;
- input clk;
- output [147:0] d_out;
- input [98:0] f_in;
- input flush_in;
- reg [147:0] r;
- wire [147:0] rin;
- input rst;
- input stall_in;
- reg [37:0] \$mem$\3502 [1023:0];
- reg [0:0] \$mem$\3504 [1023:0];
- reg [37:0] \$mem$\3506 [7:0];
- reg [37:0] \$mem$\3508 [15:0];
- reg [37:0] \$mem$\3510 [3:0];
- reg [37:0] \$mem$\3512 [3:0];
- reg [37:0] \$mem$\3514 [63:0];
- assign _00_ = rst | flush_in;
- assign _01_ = ~ stall_in;
- assign _02_ = _00_ | _01_;
- assign _03_ = _02_ ? rin : r;
- always @(posedge clk)
- r <= _03_;
- assign _04_ = r[117:112] == 6'h3d;
- assign _05_ = _04_ ? 1'h0 : 1'h1;
- assign _06_ = f_in[98:93] == 6'h1f;
- assign _07_ = 10'h3ff - f_in[77:68];
- assign _08_ = f_in[98:93] == 6'h13;
- assign _09_ = 10'h3ff - f_in[77:68];
- assign _10_ = ~ _86_;
- assign _11_ = 3'h7 - { f_in[72], f_in[70:69] };
- assign _12_ = _10_ ? 38'h2800000001 : _88_;
- assign _13_ = f_in[98:93] == 6'h1e;
- assign _14_ = 4'hf - f_in[71:68];
- assign _15_ = f_in[98:93] == 6'h3a;
- assign _16_ = 2'h3 - f_in[68:67];
- assign _17_ = f_in[98:93] == 6'h3e;
- assign _18_ = 2'h3 - f_in[68:67];
- assign _19_ = f_in[98:67] & 32'd4294967295;
- assign _20_ = _19_ == 32'd1610612736;
- assign _21_ = 6'h3f - f_in[98:93];
- assign _22_ = _20_ ? 38'h0000000005 : _96_;
- assign _23_ = _17_ ? _94_ : _22_;
- assign _24_ = _15_ ? _92_ : _23_;
- assign _25_ = _13_ ? _90_ : _24_;
- assign _26_ = _08_ ? _12_ : _25_;
- assign _27_ = _06_ ? _84_ : _26_;
- assign _28_ = f_in[2] ? _05_ : f_in[0];
- assign _29_ = f_in[2] ? 38'h00000000f6 : _27_;
- assign _30_ = _29_[7:2] == 6'h06;
- assign _31_ = _29_[7:2] == 6'h07;
- assign _32_ = _30_ | _31_;
- assign _33_ = ~ f_in[90];
- assign _34_ = _33_ ? 6'h21 : 6'h00;
- assign _35_ = _29_[7:2] == 6'h07;
- assign _36_ = ~ f_in[77];
- assign _37_ = _36_ ? 6'h20 : 6'h21;
- assign _38_ = _35_ ? _37_ : 6'h00;
- assign _39_ = _29_[7:2] == 6'h26;
- assign _40_ = _29_[7:2] == 6'h2a;
- assign _41_ = _39_ | _40_;
- assign _42_ = { f_in[82:78], f_in[87:83] } == 10'h008;
- assign _43_ = { f_in[82:78], f_in[87:83] } == 10'h009;
- assign _44_ = { f_in[82:78], f_in[87:83] } == 10'h01a;
- assign _45_ = { f_in[82:78], f_in[87:83] } == 10'h01b;
- assign _46_ = { f_in[82:78], f_in[87:83] } == 10'h13a;
- assign _47_ = { f_in[82:78], f_in[87:83] } == 10'h13b;
- assign _48_ = { f_in[82:78], f_in[87:83] } == 10'h110;
- assign _49_ = { f_in[82:78], f_in[87:83] } == 10'h111;
- assign _50_ = { f_in[82:78], f_in[87:83] } == 10'h112;
- assign _51_ = { f_in[82:78], f_in[87:83] } == 10'h113;
- assign _52_ = { f_in[82:78], f_in[87:83] } == 10'h103;
- assign _53_ = _51_ | _52_;
- assign _54_ = { f_in[82:78], f_in[87:83] } == 10'h130;
- assign _55_ = { f_in[82:78], f_in[87:83] } == 10'h131;
- assign _56_ = { f_in[82:78], f_in[87:83] } == 10'h001;
- function [0:0] \3398 ;
- input [0:0] a;
- input [12:0] b;
- input [12:0] s;
- (* parallel_case *)
- casez (s)
- 13'b????????????1:
- \3398 = b[0:0];
- 13'b???????????1?:
- \3398 = b[1:1];
- 13'b??????????1??:
- \3398 = b[2:2];
- 13'b?????????1???:
- \3398 = b[3:3];
- 13'b????????1????:
- \3398 = b[4:4];
- 13'b???????1?????:
- \3398 = b[5:5];
- 13'b??????1??????:
- \3398 = b[6:6];
- 13'b?????1???????:
- \3398 = b[7:7];
- 13'b????1????????:
- \3398 = b[8:8];
- 13'b???1?????????:
- \3398 = b[9:9];
- 13'b??1??????????:
- \3398 = b[10:10];
- 13'b?1???????????:
- \3398 = b[11:11];
- 13'b1????????????:
- \3398 = b[12:12];
- default:
- \3398 = a;
- endcase
- endfunction
- assign _57_ = \3398 (1'h0, 13'h1fff, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
- function [5:0] \3404 ;
- input [5:0] a;
- input [77:0] b;
- input [12:0] s;
- (* parallel_case *)
- casez (s)
- 13'b????????????1:
- \3404 = b[5:0];
- 13'b???????????1?:
- \3404 = b[11:6];
- 13'b??????????1??:
- \3404 = b[17:12];
- 13'b?????????1???:
- \3404 = b[23:18];
- 13'b????????1????:
- \3404 = b[29:24];
- 13'b???????1?????:
- \3404 = b[35:30];
- 13'b??????1??????:
- \3404 = b[41:36];
- 13'b?????1???????:
- \3404 = b[47:42];
- 13'b????1????????:
- \3404 = b[53:48];
- 13'b???1?????????:
- \3404 = b[59:54];
- 13'b??1??????????:
- \3404 = b[65:60];
- 13'b?1???????????:
- \3404 = b[71:66];
- 13'b1????????????:
- \3404 = b[77:72];
- default:
- \3404 = a;
- endcase
- endfunction
- assign _58_ = \3404 (6'h00, 78'hxxxxxxxxxxxxxxxxxxxx, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
- function [4:0] \3419 ;
- input [4:0] a;
- input [64:0] b;
- input [12:0] s;
- (* parallel_case *)
- casez (s)
- 13'b????????????1:
- \3419 = b[4:0];
- 13'b???????????1?:
- \3419 = b[9:5];
- 13'b??????????1??:
- \3419 = b[14:10];
- 13'b?????????1???:
- \3419 = b[19:15];
- 13'b????????1????:
- \3419 = b[24:20];
- 13'b???????1?????:
- \3419 = b[29:25];
- 13'b??????1??????:
- \3419 = b[34:30];
- 13'b?????1???????:
- \3419 = b[39:35];
- 13'b????1????????:
- \3419 = b[44:40];
- 13'b???1?????????:
- \3419 = b[49:45];
- 13'b??1??????????:
- \3419 = b[54:50];
- 13'b?1???????????:
- \3419 = b[59:55];
- 13'b1????????????:
- \3419 = b[64:60];
- default:
- \3419 = a;
- endcase
- endfunction
- assign _59_ = \3419 (5'h00, 65'h0c5a928398a418820, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
- assign _60_ = _57_ ? _59_ : 5'hxx;
- assign _61_ = _57_ ? { 1'h1, _60_ } : _58_;
- assign _62_ = ~ _61_[5];
- assign _63_ = { f_in[82:78], f_in[87:83] } == 10'h013;
- assign _64_ = { f_in[82:78], f_in[87:83] } == 10'h012;
- assign _65_ = _63_ | _64_;
- assign _66_ = { f_in[82:78], f_in[87:83] } == 10'h030;
- assign _67_ = _65_ | _66_;
- assign _68_ = { f_in[82:78], f_in[87:83] } == 10'h2d0;
- assign _69_ = _67_ | _68_;
- function [1:0] \3455 ;
- input [1:0] a;
- input [1:0] b;
- input [0:0] s;
- (* parallel_case *)
- casez (s)
- 1'b1:
- \3455 = b[1:0];
- default:
- \3455 = a;
- endcase
- endfunction
- assign _70_ = \3455 (_29_[1:0], 2'h2, _69_);
- assign _71_ = _77_ ? _70_ : _29_[1:0];
- assign _72_ = _78_ ? 1'h1 : _29_[37];
- assign _73_ = _29_[7:2] == 6'h31;
- assign _74_ = _73_ ? 12'h8e2 : 12'h000;
- assign _75_ = _41_ ? _61_ : _74_[5:0];
- assign _76_ = _41_ ? 6'h00 : _74_[11:6];
- assign _77_ = _41_ & _62_;
- assign _78_ = _41_ & _62_;
- assign _79_ = _32_ ? { _38_, _34_ } : { _76_, _75_ };
- assign _80_ = _32_ ? _29_[1:0] : _71_;
- assign _81_ = _32_ ? _29_[37] : _72_;
- assign _82_ = flush_in ? 1'h0 : _28_;
- assign rin = rst ? 148'h0000000000000000000000000000000000000 : { _81_, _29_[36:2], _80_, _79_, f_in[98:3], f_in[1], _82_ };
- reg [37:0] \3502 [1023:0];
- initial begin
- \3502 [0] = 38'h2800000001;
- \3502 [1] = 38'h2800000001;
- \3502 [2] = 38'h2800000001;
- \3502 [3] = 38'h2800000001;
- \3502 [4] = 38'h2800000001;
- \3502 [5] = 38'h2800000001;
- \3502 [6] = 38'h2800000001;
- \3502 [7] = 38'h2800000001;
- \3502 [8] = 38'h2800000001;
- \3502 [9] = 38'h0000000a52;
- \3502 [10] = 38'h0008008a7a;
- \3502 [11] = 38'h2800000001;
- \3502 [12] = 38'h2800000001;
- \3502 [13] = 38'h2800000001;
- \3502 [14] = 38'h2800000001;
- \3502 [15] = 38'h2800000001;
- \3502 [16] = 38'h0000050a6d;
- \3502 [17] = 38'h2800000001;
- \3502 [18] = 38'h2800000001;
- \3502 [19] = 38'h2800000001;
- \3502 [20] = 38'h0b00010955;
- \3502 [21] = 38'h2800000001;
- \3502 [22] = 38'h0a00010955;
- \3502 [23] = 38'h2800000001;
- \3502 [24] = 38'h2800000001;
- \3502 [25] = 38'h2800000001;
- \3502 [26] = 38'h2800000001;
- \3502 [27] = 38'h2800000001;
- \3502 [28] = 38'h2800000001;
- \3502 [29] = 38'h2800000001;
- \3502 [30] = 38'h2800000001;
- \3502 [31] = 38'h2800000001;
- \3502 [32] = 38'h2800000001;
- \3502 [33] = 38'h2800000001;
- \3502 [34] = 38'h2800000001;
- \3502 [35] = 38'h2800000001;
- \3502 [36] = 38'h2800000001;
- \3502 [37] = 38'h080602805d;
- \3502 [38] = 38'h2800000001;
- \3502 [39] = 38'h2800000001;
- \3502 [40] = 38'h2800000001;
- \3502 [41] = 38'h2000000065;
- \3502 [42] = 38'h0002008a7a;
- \3502 [43] = 38'h2800000001;
- \3502 [44] = 38'h2800000001;
- \3502 [45] = 38'h2800000001;
- \3502 [46] = 38'h2800000001;
- \3502 [47] = 38'h2800000001;
- \3502 [48] = 38'h0000050a6d;
- \3502 [49] = 38'h2800000001;
- \3502 [50] = 38'h2800000001;
- \3502 [51] = 38'h2800000001;
- \3502 [52] = 38'h0900010955;
- \3502 [53] = 38'h2800000001;
- \3502 [54] = 38'h0800010955;
- \3502 [55] = 38'h2800000001;
- \3502 [56] = 38'h2800000001;
- \3502 [57] = 38'h2800000001;
- \3502 [58] = 38'h2800000001;
- \3502 [59] = 38'h2800000001;
- \3502 [60] = 38'h2800000001;
- \3502 [61] = 38'h2800000001;
- \3502 [62] = 38'h2800000001;
- \3502 [63] = 38'h2800000001;
- \3502 [64] = 38'h2800000001;
- \3502 [65] = 38'h2800000001;
- \3502 [66] = 38'h2800000001;
- \3502 [67] = 38'h2800000001;
- \3502 [68] = 38'h2800000001;
- \3502 [69] = 38'h080202805d;
- \3502 [70] = 38'h2800000001;
- \3502 [71] = 38'h2800000001;
- \3502 [72] = 38'h2800000001;
- \3502 [73] = 38'h2800000001;
- \3502 [74] = 38'h0004008a7a;
- \3502 [75] = 38'h2800000001;
- \3502 [76] = 38'h2800000001;
- \3502 [77] = 38'h2800000001;
- \3502 [78] = 38'h2800000001;
- \3502 [79] = 38'h2800000001;
- \3502 [80] = 38'h0000050a6d;
- \3502 [81] = 38'h2800000001;
- \3502 [82] = 38'h2800000001;
- \3502 [83] = 38'h2800000001;
- \3502 [84] = 38'h0b00010959;
- \3502 [85] = 38'h2800000001;
- \3502 [86] = 38'h0a00010959;
- \3502 [87] = 38'h2800000001;
- \3502 [88] = 38'h2800000001;
- \3502 [89] = 38'h2800000001;
- \3502 [90] = 38'h2800000001;
- \3502 [91] = 38'h2800000001;
- \3502 [92] = 38'h2800000001;
- \3502 [93] = 38'h2800000001;
- \3502 [94] = 38'h2800000001;
- \3502 [95] = 38'h2800000001;
- \3502 [96] = 38'h2800000001;
- \3502 [97] = 38'h2800000001;
- \3502 [98] = 38'h2800000001;
- \3502 [99] = 38'h2800000001;
- \3502 [100] = 38'h2800000001;
- \3502 [101] = 38'h080402805d;
- \3502 [102] = 38'h2800000001;
- \3502 [103] = 38'h2800000001;
- \3502 [104] = 38'h2800000001;
- \3502 [105] = 38'h0014008a7a;
- \3502 [106] = 38'h0006008a7a;
- \3502 [107] = 38'h2800000001;
- \3502 [108] = 38'h2800000001;
- \3502 [109] = 38'h2800000001;
- \3502 [110] = 38'h2800000001;
- \3502 [111] = 38'h2800000001;
- \3502 [112] = 38'h0000050a6d;
- \3502 [113] = 38'h2800000001;
- \3502 [114] = 38'h2800000001;
- \3502 [115] = 38'h2800000001;
- \3502 [116] = 38'h0900010959;
- \3502 [117] = 38'h2800000001;
- \3502 [118] = 38'h0800010959;
- \3502 [119] = 38'h2800000001;
- \3502 [120] = 38'h2800000001;
- \3502 [121] = 38'h2800000001;
- \3502 [122] = 38'h2800000001;
- \3502 [123] = 38'h2800000001;
- \3502 [124] = 38'h2800000001;
- \3502 [125] = 38'h2800000001;
- \3502 [126] = 38'h2800000001;
- \3502 [127] = 38'h2800000001;
- \3502 [128] = 38'h2800000001;
- \3502 [129] = 38'h2800000001;
- \3502 [130] = 38'h2800000001;
- \3502 [131] = 38'h2800000001;
- \3502 [132] = 38'h080002d861;
- \3502 [133] = 38'h080002d861;
- \3502 [134] = 38'h2800000001;
- \3502 [135] = 38'h2800000001;
- \3502 [136] = 38'h2800000001;
- \3502 [137] = 38'h2800000001;
- \3502 [138] = 38'h0008010a76;
- \3502 [139] = 38'h2800000001;
- \3502 [140] = 38'h2800000001;
- \3502 [141] = 38'h2800000001;
- \3502 [142] = 38'h2800000001;
- \3502 [143] = 38'h2800000001;
- \3502 [144] = 38'h0000050a6d;
- \3502 [145] = 38'h2800000001;
- \3502 [146] = 38'h2800000001;
- \3502 [147] = 38'h2800000001;
- \3502 [148] = 38'h2800000001;
- \3502 [149] = 38'h2800000001;
- \3502 [150] = 38'h2800000001;
- \3502 [151] = 38'h2800000001;
- \3502 [152] = 38'h2800000001;
- \3502 [153] = 38'h2800000001;
- \3502 [154] = 38'h2800000001;
- \3502 [155] = 38'h2800000001;
- \3502 [156] = 38'h2800000001;
- \3502 [157] = 38'h2800000001;
- \3502 [158] = 38'h2800000001;
- \3502 [159] = 38'h2800000001;
- \3502 [160] = 38'h2800000001;
- \3502 [161] = 38'h2800000001;
- \3502 [162] = 38'h2800000001;
- \3502 [163] = 38'h2800000001;
- \3502 [164] = 38'h2800000001;
- \3502 [165] = 38'h2800000001;
- \3502 [166] = 38'h2800000001;
- \3502 [167] = 38'h2800000001;
- \3502 [168] = 38'h2800000001;
- \3502 [169] = 38'h2000000005;
- \3502 [170] = 38'h0002010a76;
- \3502 [171] = 38'h2800000001;
- \3502 [172] = 38'h2800000001;
- \3502 [173] = 38'h2800000001;
- \3502 [174] = 38'h2800000001;
- \3502 [175] = 38'h2800000001;
- \3502 [176] = 38'h0000050a6d;
- \3502 [177] = 38'h2800000001;
- \3502 [178] = 38'h2800000001;
- \3502 [179] = 38'h2800000001;
- \3502 [180] = 38'h2800000001;
- \3502 [181] = 38'h2800000001;
- \3502 [182] = 38'h2800000001;
- \3502 [183] = 38'h2800000001;
- \3502 [184] = 38'h2800000001;
- \3502 [185] = 38'h2800000001;
- \3502 [186] = 38'h2800000001;
- \3502 [187] = 38'h2800000001;
- \3502 [188] = 38'h2800000001;
- \3502 [189] = 38'h2800000001;
- \3502 [190] = 38'h2800000001;
- \3502 [191] = 38'h2800000001;
- \3502 [192] = 38'h2800000001;
- \3502 [193] = 38'h2800000001;
- \3502 [194] = 38'h2800000001;
- \3502 [195] = 38'h2800000001;
- \3502 [196] = 38'h0a0102d8e1;
- \3502 [197] = 38'h0a0102d8e1;
- \3502 [198] = 38'h2800000001;
- \3502 [199] = 38'h0b0102e0e1;
- \3502 [200] = 38'h2800000001;
- \3502 [201] = 38'h2800000001;
- \3502 [202] = 38'h0004010a76;
- \3502 [203] = 38'h2800000001;
- \3502 [204] = 38'h2800000001;
- \3502 [205] = 38'h2800000001;
- \3502 [206] = 38'h2800000001;
- \3502 [207] = 38'h2800000001;
- \3502 [208] = 38'h0000050a6d;
- \3502 [209] = 38'h2800000001;
- \3502 [210] = 38'h2800000001;
- \3502 [211] = 38'h2800000001;
- \3502 [212] = 38'h2800000001;
- \3502 [213] = 38'h2800000001;
- \3502 [214] = 38'h2800000001;
- \3502 [215] = 38'h2800000001;
- \3502 [216] = 38'h2800000001;
- \3502 [217] = 38'h2800000001;
- \3502 [218] = 38'h2800000001;
- \3502 [219] = 38'h2800000001;
- \3502 [220] = 38'h2800000001;
- \3502 [221] = 38'h2800000001;
- \3502 [222] = 38'h2800000001;
- \3502 [223] = 38'h2800000001;
- \3502 [224] = 38'h2800000001;
- \3502 [225] = 38'h2800000001;
- \3502 [226] = 38'h2800000001;
- \3502 [227] = 38'h2800000001;
- \3502 [228] = 38'h2800000001;
- \3502 [229] = 38'h0a010288e1;
- \3502 [230] = 38'h2800000001;
- \3502 [231] = 38'h0b010288e1;
- \3502 [232] = 38'h2800000001;
- \3502 [233] = 38'h0014010a76;
- \3502 [234] = 38'h0006010a76;
- \3502 [235] = 38'h2800000001;
- \3502 [236] = 38'h2800000001;
- \3502 [237] = 38'h2800000001;
- \3502 [238] = 38'h2800000001;
- \3502 [239] = 38'h2800000001;
- \3502 [240] = 38'h0000050a6d;
- \3502 [241] = 38'h2800000001;
- \3502 [242] = 38'h2800000001;
- \3502 [243] = 38'h2800000001;
- \3502 [244] = 38'h030001099d;
- \3502 [245] = 38'h0800010909;
- \3502 [246] = 38'h020001099d;
- \3502 [247] = 38'h2800000001;
- \3502 [248] = 38'h2800000001;
- \3502 [249] = 38'h2800000001;
- \3502 [250] = 38'h2800000001;
- \3502 [251] = 38'h2800000001;
- \3502 [252] = 38'h2800000001;
- \3502 [253] = 38'h2800000001;
- \3502 [254] = 38'h2800000001;
- \3502 [255] = 38'h2800000001;
- \3502 [256] = 38'h2800000001;
- \3502 [257] = 38'h2800000001;
- \3502 [258] = 38'h2800000001;
- \3502 [259] = 38'h2800000001;
- \3502 [260] = 38'h2800000001;
- \3502 [261] = 38'h2800000001;
- \3502 [262] = 38'h2800000001;
- \3502 [263] = 38'h2800000001;
- \3502 [264] = 38'h2800000001;
- \3502 [265] = 38'h2800000001;
- \3502 [266] = 38'h2800000001;
- \3502 [267] = 38'h2800000001;
- \3502 [268] = 38'h2800000001;
- \3502 [269] = 38'h2800000001;
- \3502 [270] = 38'h2800000001;
- \3502 [271] = 38'h2800000001;
- \3502 [272] = 38'h0000050a6d;
- \3502 [273] = 38'h2800000001;
- \3502 [274] = 38'h2800000001;
- \3502 [275] = 38'h2800000001;
- \3502 [276] = 38'h0b000909ad;
- \3502 [277] = 38'h0801415109;
- \3502 [278] = 38'h0a000909ad;
- \3502 [279] = 38'h0801515109;
- \3502 [280] = 38'h2800000001;
- \3502 [281] = 38'h2800000001;
- \3502 [282] = 38'h2800000001;
- \3502 [283] = 38'h2800000001;
- \3502 [284] = 38'h2800000001;
- \3502 [285] = 38'h2800000001;
- \3502 [286] = 38'h2800000001;
- \3502 [287] = 38'h2800000001;
- \3502 [288] = 38'h2800000001;
- \3502 [289] = 38'h2800000001;
- \3502 [290] = 38'h2800000001;
- \3502 [291] = 38'h2800000001;
- \3502 [292] = 38'h2800000001;
- \3502 [293] = 38'h2800000001;
- \3502 [294] = 38'h2800000001;
- \3502 [295] = 38'h2800000001;
- \3502 [296] = 38'h2800000001;
- \3502 [297] = 38'h0484008a7a;
- \3502 [298] = 38'h2800000001;
- \3502 [299] = 38'h2800000001;
- \3502 [300] = 38'h2800000001;
- \3502 [301] = 38'h2800000001;
- \3502 [302] = 38'h2800000001;
- \3502 [303] = 38'h2800000001;
- \3502 [304] = 38'h0000050a6d;
- \3502 [305] = 38'h2800000001;
- \3502 [306] = 38'h2800000001;
- \3502 [307] = 38'h2800000001;
- \3502 [308] = 38'h2800000001;
- \3502 [309] = 38'h0801410109;
- \3502 [310] = 38'h2800000001;
- \3502 [311] = 38'h0801510109;
- \3502 [312] = 38'h2800000001;
- \3502 [313] = 38'h2800000001;
- \3502 [314] = 38'h2800000001;
- \3502 [315] = 38'h2800000001;
- \3502 [316] = 38'h2800000001;
- \3502 [317] = 38'h2800000001;
- \3502 [318] = 38'h2800000001;
- \3502 [319] = 38'h2800000001;
- \3502 [320] = 38'h2800000001;
- \3502 [321] = 38'h2800000001;
- \3502 [322] = 38'h2800000001;
- \3502 [323] = 38'h2800000001;
- \3502 [324] = 38'h2800000001;
- \3502 [325] = 38'h2800000001;
- \3502 [326] = 38'h2800000001;
- \3502 [327] = 38'h2800000001;
- \3502 [328] = 38'h2800000001;
- \3502 [329] = 38'h0482008a7a;
- \3502 [330] = 38'h2800000001;
- \3502 [331] = 38'h2800000001;
- \3502 [332] = 38'h2800000001;
- \3502 [333] = 38'h2800000001;
- \3502 [334] = 38'h2800000001;
- \3502 [335] = 38'h2800000001;
- \3502 [336] = 38'h0000050a6d;
- \3502 [337] = 38'h2800000001;
- \3502 [338] = 38'h2800000001;
- \3502 [339] = 38'h2800000001;
- \3502 [340] = 38'h2800000001;
- \3502 [341] = 38'h2800000001;
- \3502 [342] = 38'h2800000001;
- \3502 [343] = 38'h2800000001;
- \3502 [344] = 38'h2800000001;
- \3502 [345] = 38'h2800000001;
- \3502 [346] = 38'h2800000001;
- \3502 [347] = 38'h2800000001;
- \3502 [348] = 38'h2800000001;
- \3502 [349] = 38'h2800000001;
- \3502 [350] = 38'h2800000001;
- \3502 [351] = 38'h2800000001;
- \3502 [352] = 38'h2800000001;
- \3502 [353] = 38'h2800000001;
- \3502 [354] = 38'h2800000001;
- \3502 [355] = 38'h2800000001;
- \3502 [356] = 38'h2800000001;
- \3502 [357] = 38'h2800000001;
- \3502 [358] = 38'h2800000001;
- \3502 [359] = 38'h2800000001;
- \3502 [360] = 38'h2800000001;
- \3502 [361] = 38'h0016008a7a;
- \3502 [362] = 38'h2800000001;
- \3502 [363] = 38'h0018008a7a;
- \3502 [364] = 38'h2800000001;
- \3502 [365] = 38'h2800000001;
- \3502 [366] = 38'h2800000001;
- \3502 [367] = 38'h2800000001;
- \3502 [368] = 38'h0000050a6d;
- \3502 [369] = 38'h2800000001;
- \3502 [370] = 38'h2800000001;
- \3502 [371] = 38'h2800000001;
- \3502 [372] = 38'h2800000001;
- \3502 [373] = 38'h0801410909;
- \3502 [374] = 38'h2800000001;
- \3502 [375] = 38'h0801510909;
- \3502 [376] = 38'h2800000001;
- \3502 [377] = 38'h2800000001;
- \3502 [378] = 38'h2800000001;
- \3502 [379] = 38'h2800000001;
- \3502 [380] = 38'h2800000001;
- \3502 [381] = 38'h2800000001;
- \3502 [382] = 38'h2800000001;
- \3502 [383] = 38'h2800000001;
- \3502 [384] = 38'h2800000001;
- \3502 [385] = 38'h2800000001;
- \3502 [386] = 38'h2800000001;
- \3502 [387] = 38'h2800000001;
- \3502 [388] = 38'h2800000001;
- \3502 [389] = 38'h2800000001;
- \3502 [390] = 38'h2800000001;
- \3502 [391] = 38'h2800000001;
- \3502 [392] = 38'h2800000001;
- \3502 [393] = 38'h2800000001;
- \3502 [394] = 38'h2800000001;
- \3502 [395] = 38'h2800000001;
- \3502 [396] = 38'h2800000001;
- \3502 [397] = 38'h2800000001;
- \3502 [398] = 38'h2800000001;
- \3502 [399] = 38'h2800000001;
- \3502 [400] = 38'h0000050a6d;
- \3502 [401] = 38'h2800000001;
- \3502 [402] = 38'h2800000001;
- \3502 [403] = 38'h2800000001;
- \3502 [404] = 38'h2800000001;
- \3502 [405] = 38'h2800000001;
- \3502 [406] = 38'h2800000001;
- \3502 [407] = 38'h0800910109;
- \3502 [408] = 38'h2800000001;
- \3502 [409] = 38'h2800000001;
- \3502 [410] = 38'h2800000001;
- \3502 [411] = 38'h2800000001;
- \3502 [412] = 38'h2800000001;
- \3502 [413] = 38'h2800000001;
- \3502 [414] = 38'h2800000001;
- \3502 [415] = 38'h2800000001;
- \3502 [416] = 38'h2800000001;
- \3502 [417] = 38'h2800000001;
- \3502 [418] = 38'h2800000001;
- \3502 [419] = 38'h2800000001;
- \3502 [420] = 38'h2800000001;
- \3502 [421] = 38'h2800000001;
- \3502 [422] = 38'h2800000001;
- \3502 [423] = 38'h2800000001;
- \3502 [424] = 38'h2800000001;
- \3502 [425] = 38'h2000000005;
- \3502 [426] = 38'h2800000001;
- \3502 [427] = 38'h2800000001;
- \3502 [428] = 38'h2800000001;
- \3502 [429] = 38'h2800000001;
- \3502 [430] = 38'h2800000001;
- \3502 [431] = 38'h2800000001;
- \3502 [432] = 38'h0000050a6d;
- \3502 [433] = 38'h2800000001;
- \3502 [434] = 38'h2800000001;
- \3502 [435] = 38'h2800000001;
- \3502 [436] = 38'h0b000909b5;
- \3502 [437] = 38'h2800000001;
- \3502 [438] = 38'h0a000909b1;
- \3502 [439] = 38'h2800000001;
- \3502 [440] = 38'h2800000001;
- \3502 [441] = 38'h2800000001;
- \3502 [442] = 38'h2800000001;
- \3502 [443] = 38'h2800000001;
- \3502 [444] = 38'h2800000001;
- \3502 [445] = 38'h2800000001;
- \3502 [446] = 38'h2800000001;
- \3502 [447] = 38'h2800000001;
- \3502 [448] = 38'h2800000001;
- \3502 [449] = 38'h2800000001;
- \3502 [450] = 38'h2800000001;
- \3502 [451] = 38'h2800000001;
- \3502 [452] = 38'h2800000001;
- \3502 [453] = 38'h0800028035;
- \3502 [454] = 38'h2800000001;
- \3502 [455] = 38'h2800000001;
- \3502 [456] = 38'h2800000001;
- \3502 [457] = 38'h2800000001;
- \3502 [458] = 38'h2800000001;
- \3502 [459] = 38'h2800000001;
- \3502 [460] = 38'h2800000001;
- \3502 [461] = 38'h2800000001;
- \3502 [462] = 38'h2800000001;
- \3502 [463] = 38'h2800000001;
- \3502 [464] = 38'h0000050a6d;
- \3502 [465] = 38'h2800000001;
- \3502 [466] = 38'h2800000001;
- \3502 [467] = 38'h2800000001;
- \3502 [468] = 38'h2800000001;
- \3502 [469] = 38'h2800000001;
- \3502 [470] = 38'h2800000001;
- \3502 [471] = 38'h0800910909;
- \3502 [472] = 38'h2800000001;
- \3502 [473] = 38'h2800000001;
- \3502 [474] = 38'h2800000001;
- \3502 [475] = 38'h2800000001;
- \3502 [476] = 38'h2800000001;
- \3502 [477] = 38'h2800000001;
- \3502 [478] = 38'h2800000001;
- \3502 [479] = 38'h2800000001;
- \3502 [480] = 38'h2800000001;
- \3502 [481] = 38'h2800000001;
- \3502 [482] = 38'h2800000001;
- \3502 [483] = 38'h2800000001;
- \3502 [484] = 38'h08000288e1;
- \3502 [485] = 38'h0900028035;
- \3502 [486] = 38'h2800000001;
- \3502 [487] = 38'h09000288e1;
- \3502 [488] = 38'h2800000001;
- \3502 [489] = 38'h0016010a76;
- \3502 [490] = 38'h2800000001;
- \3502 [491] = 38'h0018010a76;
- \3502 [492] = 38'h2800000001;
- \3502 [493] = 38'h2800000001;
- \3502 [494] = 38'h2800000001;
- \3502 [495] = 38'h2800000001;
- \3502 [496] = 38'h0000050a6d;
- \3502 [497] = 38'h2800000001;
- \3502 [498] = 38'h2800000001;
- \3502 [499] = 38'h2800000001;
- \3502 [500] = 38'h09000909b5;
- \3502 [501] = 38'h0801010909;
- \3502 [502] = 38'h08000909b1;
- \3502 [503] = 38'h0801910909;
- \3502 [504] = 38'h2800000001;
- \3502 [505] = 38'h2800000001;
- \3502 [506] = 38'h2800000001;
- \3502 [507] = 38'h2800000001;
- \3502 [508] = 38'h2800000001;
- \3502 [509] = 38'h2800000001;
- \3502 [510] = 38'h2800000001;
- \3502 [511] = 38'h2800000001;
- \3502 [512] = 38'h2800000001;
- \3502 [513] = 38'h2800000001;
- \3502 [514] = 38'h2800000001;
- \3502 [515] = 38'h00000a8829;
- \3502 [516] = 38'h2800000001;
- \3502 [517] = 38'h00080280bd;
- \3502 [518] = 38'h2800000001;
- \3502 [519] = 38'h2800000001;
- \3502 [520] = 38'h2800000001;
- \3502 [521] = 38'h2800000001;
- \3502 [522] = 38'h2800000001;
- \3502 [523] = 38'h2800000001;
- \3502 [524] = 38'h2800000001;
- \3502 [525] = 38'h00000000ea;
- \3502 [526] = 38'h2800000001;
- \3502 [527] = 38'h2800000001;
- \3502 [528] = 38'h0000050a6d;
- \3502 [529] = 38'h2800000001;
- \3502 [530] = 38'h2800000001;
- \3502 [531] = 38'h2800000001;
- \3502 [532] = 38'h0b00010955;
- \3502 [533] = 38'h2800000001;
- \3502 [534] = 38'h0a00010955;
- \3502 [535] = 38'h2800000001;
- \3502 [536] = 38'h2800000001;
- \3502 [537] = 38'h2800000001;
- \3502 [538] = 38'h2800000001;
- \3502 [539] = 38'h2800000001;
- \3502 [540] = 38'h2800000001;
- \3502 [541] = 38'h2800000001;
- \3502 [542] = 38'h2800000001;
- \3502 [543] = 38'h2800000001;
- \3502 [544] = 38'h2800000001;
- \3502 [545] = 38'h2800000001;
- \3502 [546] = 38'h2800000001;
- \3502 [547] = 38'h080022880d;
- \3502 [548] = 38'h2800000001;
- \3502 [549] = 38'h2800000001;
- \3502 [550] = 38'h2800000001;
- \3502 [551] = 38'h2800000001;
- \3502 [552] = 38'h2800000001;
- \3502 [553] = 38'h2800000001;
- \3502 [554] = 38'h2800000001;
- \3502 [555] = 38'h2800000001;
- \3502 [556] = 38'h00000380a9;
- \3502 [557] = 38'h2800000001;
- \3502 [558] = 38'h2800000001;
- \3502 [559] = 38'h2800000001;
- \3502 [560] = 38'h0000050a6d;
- \3502 [561] = 38'h2800000001;
- \3502 [562] = 38'h2800000001;
- \3502 [563] = 38'h2800000001;
- \3502 [564] = 38'h0900010955;
- \3502 [565] = 38'h2800000001;
- \3502 [566] = 38'h0800010955;
- \3502 [567] = 38'h2800000001;
- \3502 [568] = 38'h2800000001;
- \3502 [569] = 38'h2800000001;
- \3502 [570] = 38'h2800000001;
- \3502 [571] = 38'h2800000001;
- \3502 [572] = 38'h2800000001;
- \3502 [573] = 38'h2800000001;
- \3502 [574] = 38'h2800000001;
- \3502 [575] = 38'h2800000001;
- \3502 [576] = 38'h2800000001;
- \3502 [577] = 38'h2800000001;
- \3502 [578] = 38'h2800000001;
- \3502 [579] = 38'h08000288b9;
- \3502 [580] = 38'h2800000001;
- \3502 [581] = 38'h2800000001;
- \3502 [582] = 38'h2800000001;
- \3502 [583] = 38'h2800000001;
- \3502 [584] = 38'h0044008a7a;
- \3502 [585] = 38'h2800000001;
- \3502 [586] = 38'h2800000001;
- \3502 [587] = 38'h2800000001;
- \3502 [588] = 38'h2800000001;
- \3502 [589] = 38'h2800000001;
- \3502 [590] = 38'h2800000001;
- \3502 [591] = 38'h2800000001;
- \3502 [592] = 38'h0000050a6d;
- \3502 [593] = 38'h2800000001;
- \3502 [594] = 38'h2800000001;
- \3502 [595] = 38'h2800000001;
- \3502 [596] = 38'h0b00010959;
- \3502 [597] = 38'h2800000001;
- \3502 [598] = 38'h0a00010959;
- \3502 [599] = 38'h2800000001;
- \3502 [600] = 38'h2800000001;
- \3502 [601] = 38'h2800000001;
- \3502 [602] = 38'h2800000001;
- \3502 [603] = 38'h2800000001;
- \3502 [604] = 38'h2800000001;
- \3502 [605] = 38'h2800000001;
- \3502 [606] = 38'h2800000001;
- \3502 [607] = 38'h2800000001;
- \3502 [608] = 38'h2800000001;
- \3502 [609] = 38'h2800000001;
- \3502 [610] = 38'h2800000001;
- \3502 [611] = 38'h08001288b9;
- \3502 [612] = 38'h2800000001;
- \3502 [613] = 38'h2800000001;
- \3502 [614] = 38'h2800000001;
- \3502 [615] = 38'h2800000001;
- \3502 [616] = 38'h0004008a7a;
- \3502 [617] = 38'h2800000001;
- \3502 [618] = 38'h2800000001;
- \3502 [619] = 38'h2800000001;
- \3502 [620] = 38'h2800000001;
- \3502 [621] = 38'h2800000001;
- \3502 [622] = 38'h2800000001;
- \3502 [623] = 38'h2800000001;
- \3502 [624] = 38'h0000050a6d;
- \3502 [625] = 38'h2800000001;
- \3502 [626] = 38'h2800000001;
- \3502 [627] = 38'h2800000001;
- \3502 [628] = 38'h0900010959;
- \3502 [629] = 38'h2800000001;
- \3502 [630] = 38'h0800010959;
- \3502 [631] = 38'h2800000001;
- \3502 [632] = 38'h2800000001;
- \3502 [633] = 38'h2800000001;
- \3502 [634] = 38'h2800000001;
- \3502 [635] = 38'h2800000001;
- \3502 [636] = 38'h2800000001;
- \3502 [637] = 38'h2800000001;
- \3502 [638] = 38'h2800000001;
- \3502 [639] = 38'h2800000001;
- \3502 [640] = 38'h2800000001;
- \3502 [641] = 38'h2800000001;
- \3502 [642] = 38'h2800000001;
- \3502 [643] = 38'h2800000001;
- \3502 [644] = 38'h2800000001;
- \3502 [645] = 38'h00060280bd;
- \3502 [646] = 38'h2800000001;
- \3502 [647] = 38'h2800000001;
- \3502 [648] = 38'h0064010a76;
- \3502 [649] = 38'h2800000001;
- \3502 [650] = 38'h0066010a76;
- \3502 [651] = 38'h2800000001;
- \3502 [652] = 38'h2800000001;
- \3502 [653] = 38'h2800000001;
- \3502 [654] = 38'h2800000001;
- \3502 [655] = 38'h2800000001;
- \3502 [656] = 38'h0000050a6d;
- \3502 [657] = 38'h2800000001;
- \3502 [658] = 38'h2800000001;
- \3502 [659] = 38'h2800000001;
- \3502 [660] = 38'h2800000001;
- \3502 [661] = 38'h2800000001;
- \3502 [662] = 38'h2800000001;
- \3502 [663] = 38'h2800000001;
- \3502 [664] = 38'h2800000001;
- \3502 [665] = 38'h2800000001;
- \3502 [666] = 38'h2800000001;
- \3502 [667] = 38'h2800000001;
- \3502 [668] = 38'h2800000001;
- \3502 [669] = 38'h2800000001;
- \3502 [670] = 38'h2800000001;
- \3502 [671] = 38'h2800000001;
- \3502 [672] = 38'h2800000001;
- \3502 [673] = 38'h2800000001;
- \3502 [674] = 38'h2800000001;
- \3502 [675] = 38'h2800000001;
- \3502 [676] = 38'h2800000001;
- \3502 [677] = 38'h2800000001;
- \3502 [678] = 38'h2800000001;
- \3502 [679] = 38'h2800000001;
- \3502 [680] = 38'h0024010a76;
- \3502 [681] = 38'h2800000001;
- \3502 [682] = 38'h0026010a76;
- \3502 [683] = 38'h2800000001;
- \3502 [684] = 38'h0000018399;
- \3502 [685] = 38'h2800000001;
- \3502 [686] = 38'h2800000001;
- \3502 [687] = 38'h2800000001;
- \3502 [688] = 38'h0000050a6d;
- \3502 [689] = 38'h2800000001;
- \3502 [690] = 38'h2800000001;
- \3502 [691] = 38'h2800000001;
- \3502 [692] = 38'h2800000001;
- \3502 [693] = 38'h2800000001;
- \3502 [694] = 38'h2800000001;
- \3502 [695] = 38'h2800000001;
- \3502 [696] = 38'h2800000001;
- \3502 [697] = 38'h2800000001;
- \3502 [698] = 38'h2800000001;
- \3502 [699] = 38'h2800000001;
- \3502 [700] = 38'h2800000001;
- \3502 [701] = 38'h2800000001;
- \3502 [702] = 38'h2800000001;
- \3502 [703] = 38'h2800000001;
- \3502 [704] = 38'h2800000001;
- \3502 [705] = 38'h2800000001;
- \3502 [706] = 38'h2800000001;
- \3502 [707] = 38'h08000288f1;
- \3502 [708] = 38'h2800000001;
- \3502 [709] = 38'h2800000001;
- \3502 [710] = 38'h2800000001;
- \3502 [711] = 38'h2800000001;
- \3502 [712] = 38'h0044010a76;
- \3502 [713] = 38'h2800000001;
- \3502 [714] = 38'h2800000001;
- \3502 [715] = 38'h2800000001;
- \3502 [716] = 38'h2800000001;
- \3502 [717] = 38'h00000088ea;
- \3502 [718] = 38'h2800000001;
- \3502 [719] = 38'h2800000001;
- \3502 [720] = 38'h0000050a6d;
- \3502 [721] = 38'h2800000001;
- \3502 [722] = 38'h2800000001;
- \3502 [723] = 38'h2800000001;
- \3502 [724] = 38'h2800000001;
- \3502 [725] = 38'h2800000001;
- \3502 [726] = 38'h2800000001;
- \3502 [727] = 38'h2800000001;
- \3502 [728] = 38'h2800000001;
- \3502 [729] = 38'h2800000001;
- \3502 [730] = 38'h2800000001;
- \3502 [731] = 38'h2800000001;
- \3502 [732] = 38'h2800000001;
- \3502 [733] = 38'h2800000001;
- \3502 [734] = 38'h2800000001;
- \3502 [735] = 38'h2800000001;
- \3502 [736] = 38'h2800000001;
- \3502 [737] = 38'h2800000001;
- \3502 [738] = 38'h2800000001;
- \3502 [739] = 38'h08002288f1;
- \3502 [740] = 38'h2800000001;
- \3502 [741] = 38'h2800000001;
- \3502 [742] = 38'h2800000001;
- \3502 [743] = 38'h2800000001;
- \3502 [744] = 38'h0004010a76;
- \3502 [745] = 38'h2000000005;
- \3502 [746] = 38'h2800000001;
- \3502 [747] = 38'h2800000001;
- \3502 [748] = 38'h2800000001;
- \3502 [749] = 38'h00000088ea;
- \3502 [750] = 38'h2800000001;
- \3502 [751] = 38'h2800000001;
- \3502 [752] = 38'h0000050a6d;
- \3502 [753] = 38'h2800000001;
- \3502 [754] = 38'h2800000001;
- \3502 [755] = 38'h2800000001;
- \3502 [756] = 38'h010001099d;
- \3502 [757] = 38'h0800010909;
- \3502 [758] = 38'h000001099d;
- \3502 [759] = 38'h2800000001;
- \3502 [760] = 38'h2800000001;
- \3502 [761] = 38'h2800000001;
- \3502 [762] = 38'h2800000001;
- \3502 [763] = 38'h2800000001;
- \3502 [764] = 38'h2800000001;
- \3502 [765] = 38'h2800000001;
- \3502 [766] = 38'h2800000001;
- \3502 [767] = 38'h2800000001;
- \3502 [768] = 38'h2800000001;
- \3502 [769] = 38'h2800000001;
- \3502 [770] = 38'h2800000001;
- \3502 [771] = 38'h2800000001;
- \3502 [772] = 38'h2800000001;
- \3502 [773] = 38'h2800000001;
- \3502 [774] = 38'h2800000001;
- \3502 [775] = 38'h2800000001;
- \3502 [776] = 38'h0042008a7a;
- \3502 [777] = 38'h2000000005;
- \3502 [778] = 38'h2800000001;
- \3502 [779] = 38'h2800000001;
- \3502 [780] = 38'h2800000001;
- \3502 [781] = 38'h2800000001;
- \3502 [782] = 38'h2800000001;
- \3502 [783] = 38'h2800000001;
- \3502 [784] = 38'h0000050a6d;
- \3502 [785] = 38'h2800000001;
- \3502 [786] = 38'h2800000001;
- \3502 [787] = 38'h2800000001;
- \3502 [788] = 38'h0b000909ad;
- \3502 [789] = 38'h0801415109;
- \3502 [790] = 38'h0a000909ad;
- \3502 [791] = 38'h0801515109;
- \3502 [792] = 38'h2800000001;
- \3502 [793] = 38'h2800000001;
- \3502 [794] = 38'h2800000001;
- \3502 [795] = 38'h2800000001;
- \3502 [796] = 38'h2800000001;
- \3502 [797] = 38'h2800000001;
- \3502 [798] = 38'h2800000001;
- \3502 [799] = 38'h2800000001;
- \3502 [800] = 38'h2800000001;
- \3502 [801] = 38'h2800000001;
- \3502 [802] = 38'h2800000001;
- \3502 [803] = 38'h2800000001;
- \3502 [804] = 38'h2800000001;
- \3502 [805] = 38'h2800000001;
- \3502 [806] = 38'h2800000001;
- \3502 [807] = 38'h2800000001;
- \3502 [808] = 38'h0002008a7a;
- \3502 [809] = 38'h0488008a7a;
- \3502 [810] = 38'h2800000001;
- \3502 [811] = 38'h2800000001;
- \3502 [812] = 38'h2800000001;
- \3502 [813] = 38'h2800000001;
- \3502 [814] = 38'h2800000001;
- \3502 [815] = 38'h2800000001;
- \3502 [816] = 38'h0000050a6d;
- \3502 [817] = 38'h2800000001;
- \3502 [818] = 38'h2800000001;
- \3502 [819] = 38'h2800000001;
- \3502 [820] = 38'h2800000001;
- \3502 [821] = 38'h0801410109;
- \3502 [822] = 38'h2800000001;
- \3502 [823] = 38'h0801510109;
- \3502 [824] = 38'h2800000001;
- \3502 [825] = 38'h2800000001;
- \3502 [826] = 38'h2800000001;
- \3502 [827] = 38'h2800000001;
- \3502 [828] = 38'h2800000001;
- \3502 [829] = 38'h2800000001;
- \3502 [830] = 38'h2800000001;
- \3502 [831] = 38'h2800000001;
- \3502 [832] = 38'h2800000001;
- \3502 [833] = 38'h2800000001;
- \3502 [834] = 38'h2800000001;
- \3502 [835] = 38'h2800000001;
- \3502 [836] = 38'h2800000001;
- \3502 [837] = 38'h00080280c1;
- \3502 [838] = 38'h2800000001;
- \3502 [839] = 38'h2800000001;
- \3502 [840] = 38'h0046008a7a;
- \3502 [841] = 38'h2800000001;
- \3502 [842] = 38'h0048008a7a;
- \3502 [843] = 38'h2800000001;
- \3502 [844] = 38'h2800000001;
- \3502 [845] = 38'h20000080a5;
- \3502 [846] = 38'h2800000001;
- \3502 [847] = 38'h2800000001;
- \3502 [848] = 38'h0000050a6d;
- \3502 [849] = 38'h2800000001;
- \3502 [850] = 38'h2800000001;
- \3502 [851] = 38'h2800000001;
- \3502 [852] = 38'h2800000001;
- \3502 [853] = 38'h2800000001;
- \3502 [854] = 38'h2800000001;
- \3502 [855] = 38'h2800000001;
- \3502 [856] = 38'h2800000001;
- \3502 [857] = 38'h2800000001;
- \3502 [858] = 38'h2800000001;
- \3502 [859] = 38'h2800000001;
- \3502 [860] = 38'h2800000001;
- \3502 [861] = 38'h2800000001;
- \3502 [862] = 38'h2800000001;
- \3502 [863] = 38'h2800000001;
- \3502 [864] = 38'h2800000001;
- \3502 [865] = 38'h2800000001;
- \3502 [866] = 38'h2800000001;
- \3502 [867] = 38'h2800000001;
- \3502 [868] = 38'h2800000001;
- \3502 [869] = 38'h00060280c1;
- \3502 [870] = 38'h2800000001;
- \3502 [871] = 38'h2800000001;
- \3502 [872] = 38'h0006008a7a;
- \3502 [873] = 38'h0486008a7a;
- \3502 [874] = 38'h0008008a7a;
- \3502 [875] = 38'h2800000001;
- \3502 [876] = 38'h2800000001;
- \3502 [877] = 38'h2800000001;
- \3502 [878] = 38'h2800000001;
- \3502 [879] = 38'h00000880a1;
- \3502 [880] = 38'h0000050a6d;
- \3502 [881] = 38'h2800000001;
- \3502 [882] = 38'h2800000001;
- \3502 [883] = 38'h2800000001;
- \3502 [884] = 38'h2800000001;
- \3502 [885] = 38'h0801410909;
- \3502 [886] = 38'h2800000001;
- \3502 [887] = 38'h0801510909;
- \3502 [888] = 38'h2800000001;
- \3502 [889] = 38'h2800000001;
- \3502 [890] = 38'h2800000001;
- \3502 [891] = 38'h2800000001;
- \3502 [892] = 38'h2800000001;
- \3502 [893] = 38'h2800000001;
- \3502 [894] = 38'h2800000001;
- \3502 [895] = 38'h2800000001;
- \3502 [896] = 38'h2800000001;
- \3502 [897] = 38'h2800000001;
- \3502 [898] = 38'h2800000001;
- \3502 [899] = 38'h08002288b9;
- \3502 [900] = 38'h2800000001;
- \3502 [901] = 38'h00020280bd;
- \3502 [902] = 38'h2800000001;
- \3502 [903] = 38'h2800000001;
- \3502 [904] = 38'h0042010a76;
- \3502 [905] = 38'h2800000001;
- \3502 [906] = 38'h2800000001;
- \3502 [907] = 38'h0084010a76;
- \3502 [908] = 38'h2800000001;
- \3502 [909] = 38'h2800000001;
- \3502 [910] = 38'h2800000001;
- \3502 [911] = 38'h2800000001;
- \3502 [912] = 38'h0000050a6d;
- \3502 [913] = 38'h2800000001;
- \3502 [914] = 38'h2800000001;
- \3502 [915] = 38'h2800000001;
- \3502 [916] = 38'h2800000001;
- \3502 [917] = 38'h2800000001;
- \3502 [918] = 38'h2800000001;
- \3502 [919] = 38'h0800910109;
- \3502 [920] = 38'h2800000001;
- \3502 [921] = 38'h2800000001;
- \3502 [922] = 38'h2800000001;
- \3502 [923] = 38'h2800000001;
- \3502 [924] = 38'h2800000001;
- \3502 [925] = 38'h2800000001;
- \3502 [926] = 38'h2800000001;
- \3502 [927] = 38'h2800000001;
- \3502 [928] = 38'h2800000001;
- \3502 [929] = 38'h2800000001;
- \3502 [930] = 38'h2800000001;
- \3502 [931] = 38'h2800000001;
- \3502 [932] = 38'h2800000001;
- \3502 [933] = 38'h2800000001;
- \3502 [934] = 38'h2800000001;
- \3502 [935] = 38'h2800000001;
- \3502 [936] = 38'h0002010a76;
- \3502 [937] = 38'h2000000005;
- \3502 [938] = 38'h2800000001;
- \3502 [939] = 38'h0088010a76;
- \3502 [940] = 38'h2000010095;
- \3502 [941] = 38'h2800000001;
- \3502 [942] = 38'h2800000001;
- \3502 [943] = 38'h2800000001;
- \3502 [944] = 38'h0000050a6d;
- \3502 [945] = 38'h2800000001;
- \3502 [946] = 38'h2800000001;
- \3502 [947] = 38'h2800000001;
- \3502 [948] = 38'h0b000909b5;
- \3502 [949] = 38'h2800000001;
- \3502 [950] = 38'h0a000909b1;
- \3502 [951] = 38'h2800000001;
- \3502 [952] = 38'h2800000001;
- \3502 [953] = 38'h2800000001;
- \3502 [954] = 38'h2800000001;
- \3502 [955] = 38'h20000009ed;
- \3502 [956] = 38'h2800000001;
- \3502 [957] = 38'h2800000001;
- \3502 [958] = 38'h2800000001;
- \3502 [959] = 38'h2800000001;
- \3502 [960] = 38'h2800000001;
- \3502 [961] = 38'h2800000001;
- \3502 [962] = 38'h2800000001;
- \3502 [963] = 38'h080012880d;
- \3502 [964] = 38'h2800000001;
- \3502 [965] = 38'h0800028035;
- \3502 [966] = 38'h2800000001;
- \3502 [967] = 38'h2800000001;
- \3502 [968] = 38'h0046010a76;
- \3502 [969] = 38'h2000000005;
- \3502 [970] = 38'h0048010a76;
- \3502 [971] = 38'h0082010a76;
- \3502 [972] = 38'h2800000001;
- \3502 [973] = 38'h2800000001;
- \3502 [974] = 38'h2800000001;
- \3502 [975] = 38'h2800000001;
- \3502 [976] = 38'h0000050a6d;
- \3502 [977] = 38'h2800000001;
- \3502 [978] = 38'h2800000001;
- \3502 [979] = 38'h2800000001;
- \3502 [980] = 38'h2800000001;
- \3502 [981] = 38'h2800000001;
- \3502 [982] = 38'h2800000001;
- \3502 [983] = 38'h0800910909;
- \3502 [984] = 38'h2800000001;
- \3502 [985] = 38'h2800000001;
- \3502 [986] = 38'h2800000001;
- \3502 [987] = 38'h2800000001;
- \3502 [988] = 38'h2800000001;
- \3502 [989] = 38'h2800000001;
- \3502 [990] = 38'h2800000001;
- \3502 [991] = 38'h0000980925;
- \3502 [992] = 38'h2800000001;
- \3502 [993] = 38'h2800000001;
- \3502 [994] = 38'h2800000001;
- \3502 [995] = 38'h080002880d;
- \3502 [996] = 38'h08000288dd;
- \3502 [997] = 38'h0900028035;
- \3502 [998] = 38'h2800000001;
- \3502 [999] = 38'h09000288dd;
- \3502 [1000] = 38'h0006010a76;
- \3502 [1001] = 38'h2000000005;
- \3502 [1002] = 38'h0008010a76;
- \3502 [1003] = 38'h0086010a76;
- \3502 [1004] = 38'h0000050091;
- \3502 [1005] = 38'h2800000001;
- \3502 [1006] = 38'h2800000001;
- \3502 [1007] = 38'h2800000001;
- \3502 [1008] = 38'h2000050a6d;
- \3502 [1009] = 38'h2800000001;
- \3502 [1010] = 38'h2800000001;
- \3502 [1011] = 38'h2800000001;
- \3502 [1012] = 38'h09000909b5;
- \3502 [1013] = 38'h0801010909;
- \3502 [1014] = 38'h08000909b1;
- \3502 [1015] = 38'h0801910909;
- \3502 [1016] = 38'h2800000001;
- \3502 [1017] = 38'h2800000001;
- \3502 [1018] = 38'h2800000001;
- \3502 [1019] = 38'h21000009ed;
- \3502 [1020] = 38'h2800000001;
- \3502 [1021] = 38'h2800000001;
- \3502 [1022] = 38'h2800000001;
- \3502 [1023] = 38'h0200980925;
- end
- assign _84_ = \3502 [_07_];
- reg [0:0] \3504 [1023:0];
- initial begin
- \3504 [0] = 1'h0;
- \3504 [1] = 1'h0;
- \3504 [2] = 1'h0;
- \3504 [3] = 1'h0;
- \3504 [4] = 1'h0;
- \3504 [5] = 1'h0;
- \3504 [6] = 1'h0;
- \3504 [7] = 1'h0;
- \3504 [8] = 1'h0;
- \3504 [9] = 1'h0;
- \3504 [10] = 1'h0;
- \3504 [11] = 1'h0;
- \3504 [12] = 1'h0;
- \3504 [13] = 1'h0;
- \3504 [14] = 1'h0;
- \3504 [15] = 1'h0;
- \3504 [16] = 1'h0;
- \3504 [17] = 1'h0;
- \3504 [18] = 1'h0;
- \3504 [19] = 1'h0;
- \3504 [20] = 1'h0;
- \3504 [21] = 1'h0;
- \3504 [22] = 1'h0;
- \3504 [23] = 1'h0;
- \3504 [24] = 1'h0;
- \3504 [25] = 1'h0;
- \3504 [26] = 1'h0;
- \3504 [27] = 1'h0;
- \3504 [28] = 1'h0;
- \3504 [29] = 1'h1;
- \3504 [30] = 1'h0;
- \3504 [31] = 1'h0;
- \3504 [32] = 1'h0;
- \3504 [33] = 1'h0;
- \3504 [34] = 1'h0;
- \3504 [35] = 1'h0;
- \3504 [36] = 1'h0;
- \3504 [37] = 1'h0;
- \3504 [38] = 1'h0;
- \3504 [39] = 1'h0;
- \3504 [40] = 1'h0;
- \3504 [41] = 1'h0;
- \3504 [42] = 1'h0;
- \3504 [43] = 1'h0;
- \3504 [44] = 1'h0;
- \3504 [45] = 1'h0;
- \3504 [46] = 1'h0;
- \3504 [47] = 1'h0;
- \3504 [48] = 1'h0;
- \3504 [49] = 1'h0;
- \3504 [50] = 1'h0;
- \3504 [51] = 1'h0;
- \3504 [52] = 1'h0;
- \3504 [53] = 1'h0;
- \3504 [54] = 1'h0;
- \3504 [55] = 1'h0;
- \3504 [56] = 1'h0;
- \3504 [57] = 1'h0;
- \3504 [58] = 1'h0;
- \3504 [59] = 1'h0;
- \3504 [60] = 1'h0;
- \3504 [61] = 1'h1;
- \3504 [62] = 1'h0;
- \3504 [63] = 1'h0;
- \3504 [64] = 1'h0;
- \3504 [65] = 1'h0;
- \3504 [66] = 1'h0;
- \3504 [67] = 1'h0;
- \3504 [68] = 1'h0;
- \3504 [69] = 1'h0;
- \3504 [70] = 1'h0;
- \3504 [71] = 1'h0;
- \3504 [72] = 1'h0;
- \3504 [73] = 1'h0;
- \3504 [74] = 1'h0;
- \3504 [75] = 1'h0;
- \3504 [76] = 1'h0;
- \3504 [77] = 1'h0;
- \3504 [78] = 1'h0;
- \3504 [79] = 1'h0;
- \3504 [80] = 1'h0;
- \3504 [81] = 1'h0;
- \3504 [82] = 1'h0;
- \3504 [83] = 1'h0;
- \3504 [84] = 1'h0;
- \3504 [85] = 1'h0;
- \3504 [86] = 1'h0;
- \3504 [87] = 1'h0;
- \3504 [88] = 1'h0;
- \3504 [89] = 1'h0;
- \3504 [90] = 1'h0;
- \3504 [91] = 1'h0;
- \3504 [92] = 1'h0;
- \3504 [93] = 1'h1;
- \3504 [94] = 1'h0;
- \3504 [95] = 1'h0;
- \3504 [96] = 1'h0;
- \3504 [97] = 1'h0;
- \3504 [98] = 1'h0;
- \3504 [99] = 1'h0;
- \3504 [100] = 1'h0;
- \3504 [101] = 1'h0;
- \3504 [102] = 1'h0;
- \3504 [103] = 1'h0;
- \3504 [104] = 1'h0;
- \3504 [105] = 1'h0;
- \3504 [106] = 1'h0;
- \3504 [107] = 1'h0;
- \3504 [108] = 1'h0;
- \3504 [109] = 1'h0;
- \3504 [110] = 1'h0;
- \3504 [111] = 1'h0;
- \3504 [112] = 1'h0;
- \3504 [113] = 1'h0;
- \3504 [114] = 1'h0;
- \3504 [115] = 1'h0;
- \3504 [116] = 1'h0;
- \3504 [117] = 1'h0;
- \3504 [118] = 1'h0;
- \3504 [119] = 1'h0;
- \3504 [120] = 1'h0;
- \3504 [121] = 1'h0;
- \3504 [122] = 1'h0;
- \3504 [123] = 1'h0;
- \3504 [124] = 1'h0;
- \3504 [125] = 1'h1;
- \3504 [126] = 1'h0;
- \3504 [127] = 1'h0;
- \3504 [128] = 1'h0;
- \3504 [129] = 1'h0;
- \3504 [130] = 1'h0;
- \3504 [131] = 1'h0;
- \3504 [132] = 1'h0;
- \3504 [133] = 1'h0;
- \3504 [134] = 1'h0;
- \3504 [135] = 1'h0;
- \3504 [136] = 1'h0;
- \3504 [137] = 1'h0;
- \3504 [138] = 1'h0;
- \3504 [139] = 1'h0;
- \3504 [140] = 1'h0;
- \3504 [141] = 1'h0;
- \3504 [142] = 1'h0;
- \3504 [143] = 1'h0;
- \3504 [144] = 1'h0;
- \3504 [145] = 1'h0;
- \3504 [146] = 1'h0;
- \3504 [147] = 1'h0;
- \3504 [148] = 1'h0;
- \3504 [149] = 1'h0;
- \3504 [150] = 1'h0;
- \3504 [151] = 1'h0;
- \3504 [152] = 1'h0;
- \3504 [153] = 1'h0;
- \3504 [154] = 1'h0;
- \3504 [155] = 1'h0;
- \3504 [156] = 1'h0;
- \3504 [157] = 1'h1;
- \3504 [158] = 1'h0;
- \3504 [159] = 1'h0;
- \3504 [160] = 1'h0;
- \3504 [161] = 1'h0;
- \3504 [162] = 1'h0;
- \3504 [163] = 1'h0;
- \3504 [164] = 1'h0;
- \3504 [165] = 1'h0;
- \3504 [166] = 1'h0;
- \3504 [167] = 1'h0;
- \3504 [168] = 1'h0;
- \3504 [169] = 1'h0;
- \3504 [170] = 1'h0;
- \3504 [171] = 1'h0;
- \3504 [172] = 1'h0;
- \3504 [173] = 1'h0;
- \3504 [174] = 1'h0;
- \3504 [175] = 1'h0;
- \3504 [176] = 1'h0;
- \3504 [177] = 1'h0;
- \3504 [178] = 1'h0;
- \3504 [179] = 1'h0;
- \3504 [180] = 1'h0;
- \3504 [181] = 1'h0;
- \3504 [182] = 1'h0;
- \3504 [183] = 1'h0;
- \3504 [184] = 1'h0;
- \3504 [185] = 1'h0;
- \3504 [186] = 1'h0;
- \3504 [187] = 1'h0;
- \3504 [188] = 1'h0;
- \3504 [189] = 1'h1;
- \3504 [190] = 1'h0;
- \3504 [191] = 1'h0;
- \3504 [192] = 1'h0;
- \3504 [193] = 1'h0;
- \3504 [194] = 1'h0;
- \3504 [195] = 1'h0;
- \3504 [196] = 1'h0;
- \3504 [197] = 1'h0;
- \3504 [198] = 1'h0;
- \3504 [199] = 1'h0;
- \3504 [200] = 1'h0;
- \3504 [201] = 1'h0;
- \3504 [202] = 1'h0;
- \3504 [203] = 1'h0;
- \3504 [204] = 1'h0;
- \3504 [205] = 1'h0;
- \3504 [206] = 1'h0;
- \3504 [207] = 1'h0;
- \3504 [208] = 1'h0;
- \3504 [209] = 1'h0;
- \3504 [210] = 1'h0;
- \3504 [211] = 1'h0;
- \3504 [212] = 1'h0;
- \3504 [213] = 1'h0;
- \3504 [214] = 1'h0;
- \3504 [215] = 1'h0;
- \3504 [216] = 1'h0;
- \3504 [217] = 1'h0;
- \3504 [218] = 1'h0;
- \3504 [219] = 1'h0;
- \3504 [220] = 1'h0;
- \3504 [221] = 1'h1;
- \3504 [222] = 1'h0;
- \3504 [223] = 1'h0;
- \3504 [224] = 1'h0;
- \3504 [225] = 1'h0;
- \3504 [226] = 1'h0;
- \3504 [227] = 1'h0;
- \3504 [228] = 1'h0;
- \3504 [229] = 1'h0;
- \3504 [230] = 1'h0;
- \3504 [231] = 1'h0;
- \3504 [232] = 1'h0;
- \3504 [233] = 1'h0;
- \3504 [234] = 1'h0;
- \3504 [235] = 1'h0;
- \3504 [236] = 1'h0;
- \3504 [237] = 1'h0;
- \3504 [238] = 1'h0;
- \3504 [239] = 1'h0;
- \3504 [240] = 1'h0;
- \3504 [241] = 1'h0;
- \3504 [242] = 1'h0;
- \3504 [243] = 1'h0;
- \3504 [244] = 1'h0;
- \3504 [245] = 1'h0;
- \3504 [246] = 1'h0;
- \3504 [247] = 1'h0;
- \3504 [248] = 1'h0;
- \3504 [249] = 1'h0;
- \3504 [250] = 1'h0;
- \3504 [251] = 1'h0;
- \3504 [252] = 1'h0;
- \3504 [253] = 1'h1;
- \3504 [254] = 1'h0;
- \3504 [255] = 1'h0;
- \3504 [256] = 1'h0;
- \3504 [257] = 1'h0;
- \3504 [258] = 1'h0;
- \3504 [259] = 1'h0;
- \3504 [260] = 1'h0;
- \3504 [261] = 1'h0;
- \3504 [262] = 1'h0;
- \3504 [263] = 1'h0;
- \3504 [264] = 1'h0;
- \3504 [265] = 1'h0;
- \3504 [266] = 1'h0;
- \3504 [267] = 1'h0;
- \3504 [268] = 1'h0;
- \3504 [269] = 1'h0;
- \3504 [270] = 1'h0;
- \3504 [271] = 1'h0;
- \3504 [272] = 1'h0;
- \3504 [273] = 1'h0;
- \3504 [274] = 1'h0;
- \3504 [275] = 1'h0;
- \3504 [276] = 1'h0;
- \3504 [277] = 1'h0;
- \3504 [278] = 1'h0;
- \3504 [279] = 1'h0;
- \3504 [280] = 1'h0;
- \3504 [281] = 1'h0;
- \3504 [282] = 1'h0;
- \3504 [283] = 1'h0;
- \3504 [284] = 1'h0;
- \3504 [285] = 1'h1;
- \3504 [286] = 1'h0;
- \3504 [287] = 1'h0;
- \3504 [288] = 1'h0;
- \3504 [289] = 1'h0;
- \3504 [290] = 1'h0;
- \3504 [291] = 1'h0;
- \3504 [292] = 1'h0;
- \3504 [293] = 1'h0;
- \3504 [294] = 1'h0;
- \3504 [295] = 1'h0;
- \3504 [296] = 1'h0;
- \3504 [297] = 1'h0;
- \3504 [298] = 1'h0;
- \3504 [299] = 1'h0;
- \3504 [300] = 1'h0;
- \3504 [301] = 1'h0;
- \3504 [302] = 1'h0;
- \3504 [303] = 1'h0;
- \3504 [304] = 1'h0;
- \3504 [305] = 1'h0;
- \3504 [306] = 1'h0;
- \3504 [307] = 1'h0;
- \3504 [308] = 1'h0;
- \3504 [309] = 1'h0;
- \3504 [310] = 1'h0;
- \3504 [311] = 1'h0;
- \3504 [312] = 1'h0;
- \3504 [313] = 1'h0;
- \3504 [314] = 1'h0;
- \3504 [315] = 1'h0;
- \3504 [316] = 1'h0;
- \3504 [317] = 1'h1;
- \3504 [318] = 1'h0;
- \3504 [319] = 1'h0;
- \3504 [320] = 1'h0;
- \3504 [321] = 1'h0;
- \3504 [322] = 1'h0;
- \3504 [323] = 1'h0;
- \3504 [324] = 1'h0;
- \3504 [325] = 1'h0;
- \3504 [326] = 1'h0;
- \3504 [327] = 1'h0;
- \3504 [328] = 1'h0;
- \3504 [329] = 1'h0;
- \3504 [330] = 1'h0;
- \3504 [331] = 1'h0;
- \3504 [332] = 1'h0;
- \3504 [333] = 1'h0;
- \3504 [334] = 1'h0;
- \3504 [335] = 1'h0;
- \3504 [336] = 1'h0;
- \3504 [337] = 1'h0;
- \3504 [338] = 1'h0;
- \3504 [339] = 1'h0;
- \3504 [340] = 1'h0;
- \3504 [341] = 1'h0;
- \3504 [342] = 1'h0;
- \3504 [343] = 1'h0;
- \3504 [344] = 1'h0;
- \3504 [345] = 1'h0;
- \3504 [346] = 1'h0;
- \3504 [347] = 1'h0;
- \3504 [348] = 1'h0;
- \3504 [349] = 1'h1;
- \3504 [350] = 1'h0;
- \3504 [351] = 1'h0;
- \3504 [352] = 1'h0;
- \3504 [353] = 1'h0;
- \3504 [354] = 1'h0;
- \3504 [355] = 1'h0;
- \3504 [356] = 1'h0;
- \3504 [357] = 1'h0;
- \3504 [358] = 1'h0;
- \3504 [359] = 1'h0;
- \3504 [360] = 1'h0;
- \3504 [361] = 1'h0;
- \3504 [362] = 1'h0;
- \3504 [363] = 1'h0;
- \3504 [364] = 1'h0;
- \3504 [365] = 1'h0;
- \3504 [366] = 1'h0;
- \3504 [367] = 1'h0;
- \3504 [368] = 1'h0;
- \3504 [369] = 1'h0;
- \3504 [370] = 1'h0;
- \3504 [371] = 1'h0;
- \3504 [372] = 1'h0;
- \3504 [373] = 1'h0;
- \3504 [374] = 1'h0;
- \3504 [375] = 1'h0;
- \3504 [376] = 1'h0;
- \3504 [377] = 1'h0;
- \3504 [378] = 1'h0;
- \3504 [379] = 1'h0;
- \3504 [380] = 1'h0;
- \3504 [381] = 1'h1;
- \3504 [382] = 1'h0;
- \3504 [383] = 1'h0;
- \3504 [384] = 1'h0;
- \3504 [385] = 1'h0;
- \3504 [386] = 1'h0;
- \3504 [387] = 1'h0;
- \3504 [388] = 1'h0;
- \3504 [389] = 1'h0;
- \3504 [390] = 1'h0;
- \3504 [391] = 1'h0;
- \3504 [392] = 1'h0;
- \3504 [393] = 1'h0;
- \3504 [394] = 1'h0;
- \3504 [395] = 1'h0;
- \3504 [396] = 1'h0;
- \3504 [397] = 1'h0;
- \3504 [398] = 1'h0;
- \3504 [399] = 1'h0;
- \3504 [400] = 1'h0;
- \3504 [401] = 1'h0;
- \3504 [402] = 1'h0;
- \3504 [403] = 1'h0;
- \3504 [404] = 1'h0;
- \3504 [405] = 1'h0;
- \3504 [406] = 1'h0;
- \3504 [407] = 1'h0;
- \3504 [408] = 1'h0;
- \3504 [409] = 1'h0;
- \3504 [410] = 1'h0;
- \3504 [411] = 1'h0;
- \3504 [412] = 1'h0;
- \3504 [413] = 1'h1;
- \3504 [414] = 1'h0;
- \3504 [415] = 1'h0;
- \3504 [416] = 1'h0;
- \3504 [417] = 1'h0;
- \3504 [418] = 1'h0;
- \3504 [419] = 1'h0;
- \3504 [420] = 1'h0;
- \3504 [421] = 1'h0;
- \3504 [422] = 1'h0;
- \3504 [423] = 1'h0;
- \3504 [424] = 1'h0;
- \3504 [425] = 1'h0;
- \3504 [426] = 1'h0;
- \3504 [427] = 1'h0;
- \3504 [428] = 1'h0;
- \3504 [429] = 1'h0;
- \3504 [430] = 1'h0;
- \3504 [431] = 1'h0;
- \3504 [432] = 1'h0;
- \3504 [433] = 1'h0;
- \3504 [434] = 1'h0;
- \3504 [435] = 1'h0;
- \3504 [436] = 1'h0;
- \3504 [437] = 1'h0;
- \3504 [438] = 1'h0;
- \3504 [439] = 1'h0;
- \3504 [440] = 1'h0;
- \3504 [441] = 1'h0;
- \3504 [442] = 1'h0;
- \3504 [443] = 1'h0;
- \3504 [444] = 1'h0;
- \3504 [445] = 1'h1;
- \3504 [446] = 1'h0;
- \3504 [447] = 1'h0;
- \3504 [448] = 1'h0;
- \3504 [449] = 1'h0;
- \3504 [450] = 1'h0;
- \3504 [451] = 1'h0;
- \3504 [452] = 1'h0;
- \3504 [453] = 1'h0;
- \3504 [454] = 1'h0;
- \3504 [455] = 1'h0;
- \3504 [456] = 1'h0;
- \3504 [457] = 1'h0;
- \3504 [458] = 1'h0;
- \3504 [459] = 1'h0;
- \3504 [460] = 1'h0;
- \3504 [461] = 1'h0;
- \3504 [462] = 1'h0;
- \3504 [463] = 1'h0;
- \3504 [464] = 1'h0;
- \3504 [465] = 1'h0;
- \3504 [466] = 1'h0;
- \3504 [467] = 1'h0;
- \3504 [468] = 1'h0;
- \3504 [469] = 1'h0;
- \3504 [470] = 1'h0;
- \3504 [471] = 1'h0;
- \3504 [472] = 1'h0;
- \3504 [473] = 1'h0;
- \3504 [474] = 1'h0;
- \3504 [475] = 1'h0;
- \3504 [476] = 1'h0;
- \3504 [477] = 1'h1;
- \3504 [478] = 1'h0;
- \3504 [479] = 1'h0;
- \3504 [480] = 1'h0;
- \3504 [481] = 1'h0;
- \3504 [482] = 1'h0;
- \3504 [483] = 1'h0;
- \3504 [484] = 1'h0;
- \3504 [485] = 1'h0;
- \3504 [486] = 1'h0;
- \3504 [487] = 1'h0;
- \3504 [488] = 1'h0;
- \3504 [489] = 1'h0;
- \3504 [490] = 1'h0;
- \3504 [491] = 1'h0;
- \3504 [492] = 1'h0;
- \3504 [493] = 1'h0;
- \3504 [494] = 1'h0;
- \3504 [495] = 1'h1;
- \3504 [496] = 1'h0;
- \3504 [497] = 1'h0;
- \3504 [498] = 1'h0;
- \3504 [499] = 1'h0;
- \3504 [500] = 1'h0;
- \3504 [501] = 1'h0;
- \3504 [502] = 1'h0;
- \3504 [503] = 1'h0;
- \3504 [504] = 1'h0;
- \3504 [505] = 1'h0;
- \3504 [506] = 1'h0;
- \3504 [507] = 1'h0;
- \3504 [508] = 1'h0;
- \3504 [509] = 1'h1;
- \3504 [510] = 1'h0;
- \3504 [511] = 1'h0;
- \3504 [512] = 1'h0;
- \3504 [513] = 1'h0;
- \3504 [514] = 1'h0;
- \3504 [515] = 1'h0;
- \3504 [516] = 1'h0;
- \3504 [517] = 1'h0;
- \3504 [518] = 1'h0;
- \3504 [519] = 1'h0;
- \3504 [520] = 1'h0;
- \3504 [521] = 1'h0;
- \3504 [522] = 1'h0;
- \3504 [523] = 1'h0;
- \3504 [524] = 1'h0;
- \3504 [525] = 1'h0;
- \3504 [526] = 1'h0;
- \3504 [527] = 1'h0;
- \3504 [528] = 1'h0;
- \3504 [529] = 1'h0;
- \3504 [530] = 1'h0;
- \3504 [531] = 1'h0;
- \3504 [532] = 1'h0;
- \3504 [533] = 1'h0;
- \3504 [534] = 1'h0;
- \3504 [535] = 1'h0;
- \3504 [536] = 1'h0;
- \3504 [537] = 1'h0;
- \3504 [538] = 1'h0;
- \3504 [539] = 1'h0;
- \3504 [540] = 1'h0;
- \3504 [541] = 1'h1;
- \3504 [542] = 1'h0;
- \3504 [543] = 1'h0;
- \3504 [544] = 1'h0;
- \3504 [545] = 1'h0;
- \3504 [546] = 1'h0;
- \3504 [547] = 1'h0;
- \3504 [548] = 1'h0;
- \3504 [549] = 1'h0;
- \3504 [550] = 1'h0;
- \3504 [551] = 1'h0;
- \3504 [552] = 1'h0;
- \3504 [553] = 1'h0;
- \3504 [554] = 1'h0;
- \3504 [555] = 1'h0;
- \3504 [556] = 1'h0;
- \3504 [557] = 1'h0;
- \3504 [558] = 1'h0;
- \3504 [559] = 1'h0;
- \3504 [560] = 1'h0;
- \3504 [561] = 1'h0;
- \3504 [562] = 1'h0;
- \3504 [563] = 1'h0;
- \3504 [564] = 1'h0;
- \3504 [565] = 1'h0;
- \3504 [566] = 1'h0;
- \3504 [567] = 1'h0;
- \3504 [568] = 1'h0;
- \3504 [569] = 1'h0;
- \3504 [570] = 1'h0;
- \3504 [571] = 1'h0;
- \3504 [572] = 1'h0;
- \3504 [573] = 1'h1;
- \3504 [574] = 1'h1;
- \3504 [575] = 1'h0;
- \3504 [576] = 1'h0;
- \3504 [577] = 1'h0;
- \3504 [578] = 1'h0;
- \3504 [579] = 1'h0;
- \3504 [580] = 1'h0;
- \3504 [581] = 1'h0;
- \3504 [582] = 1'h0;
- \3504 [583] = 1'h0;
- \3504 [584] = 1'h0;
- \3504 [585] = 1'h0;
- \3504 [586] = 1'h0;
- \3504 [587] = 1'h0;
- \3504 [588] = 1'h0;
- \3504 [589] = 1'h0;
- \3504 [590] = 1'h0;
- \3504 [591] = 1'h0;
- \3504 [592] = 1'h0;
- \3504 [593] = 1'h0;
- \3504 [594] = 1'h0;
- \3504 [595] = 1'h0;
- \3504 [596] = 1'h0;
- \3504 [597] = 1'h0;
- \3504 [598] = 1'h0;
- \3504 [599] = 1'h0;
- \3504 [600] = 1'h0;
- \3504 [601] = 1'h0;
- \3504 [602] = 1'h0;
- \3504 [603] = 1'h0;
- \3504 [604] = 1'h0;
- \3504 [605] = 1'h1;
- \3504 [606] = 1'h1;
- \3504 [607] = 1'h0;
- \3504 [608] = 1'h0;
- \3504 [609] = 1'h0;
- \3504 [610] = 1'h0;
- \3504 [611] = 1'h0;
- \3504 [612] = 1'h0;
- \3504 [613] = 1'h0;
- \3504 [614] = 1'h0;
- \3504 [615] = 1'h0;
- \3504 [616] = 1'h0;
- \3504 [617] = 1'h0;
- \3504 [618] = 1'h0;
- \3504 [619] = 1'h0;
- \3504 [620] = 1'h0;
- \3504 [621] = 1'h0;
- \3504 [622] = 1'h0;
- \3504 [623] = 1'h0;
- \3504 [624] = 1'h0;
- \3504 [625] = 1'h0;
- \3504 [626] = 1'h0;
- \3504 [627] = 1'h0;
- \3504 [628] = 1'h0;
- \3504 [629] = 1'h0;
- \3504 [630] = 1'h0;
- \3504 [631] = 1'h0;
- \3504 [632] = 1'h0;
- \3504 [633] = 1'h0;
- \3504 [634] = 1'h0;
- \3504 [635] = 1'h0;
- \3504 [636] = 1'h0;
- \3504 [637] = 1'h1;
- \3504 [638] = 1'h0;
- \3504 [639] = 1'h0;
- \3504 [640] = 1'h0;
- \3504 [641] = 1'h0;
- \3504 [642] = 1'h0;
- \3504 [643] = 1'h0;
- \3504 [644] = 1'h0;
- \3504 [645] = 1'h0;
- \3504 [646] = 1'h0;
- \3504 [647] = 1'h0;
- \3504 [648] = 1'h0;
- \3504 [649] = 1'h0;
- \3504 [650] = 1'h0;
- \3504 [651] = 1'h0;
- \3504 [652] = 1'h0;
- \3504 [653] = 1'h0;
- \3504 [654] = 1'h0;
- \3504 [655] = 1'h0;
- \3504 [656] = 1'h0;
- \3504 [657] = 1'h0;
- \3504 [658] = 1'h0;
- \3504 [659] = 1'h0;
- \3504 [660] = 1'h0;
- \3504 [661] = 1'h0;
- \3504 [662] = 1'h0;
- \3504 [663] = 1'h0;
- \3504 [664] = 1'h0;
- \3504 [665] = 1'h0;
- \3504 [666] = 1'h0;
- \3504 [667] = 1'h0;
- \3504 [668] = 1'h0;
- \3504 [669] = 1'h1;
- \3504 [670] = 1'h0;
- \3504 [671] = 1'h0;
- \3504 [672] = 1'h0;
- \3504 [673] = 1'h0;
- \3504 [674] = 1'h0;
- \3504 [675] = 1'h0;
- \3504 [676] = 1'h0;
- \3504 [677] = 1'h0;
- \3504 [678] = 1'h0;
- \3504 [679] = 1'h0;
- \3504 [680] = 1'h0;
- \3504 [681] = 1'h0;
- \3504 [682] = 1'h0;
- \3504 [683] = 1'h0;
- \3504 [684] = 1'h0;
- \3504 [685] = 1'h0;
- \3504 [686] = 1'h0;
- \3504 [687] = 1'h0;
- \3504 [688] = 1'h0;
- \3504 [689] = 1'h0;
- \3504 [690] = 1'h0;
- \3504 [691] = 1'h0;
- \3504 [692] = 1'h0;
- \3504 [693] = 1'h0;
- \3504 [694] = 1'h0;
- \3504 [695] = 1'h0;
- \3504 [696] = 1'h0;
- \3504 [697] = 1'h0;
- \3504 [698] = 1'h0;
- \3504 [699] = 1'h0;
- \3504 [700] = 1'h0;
- \3504 [701] = 1'h1;
- \3504 [702] = 1'h0;
- \3504 [703] = 1'h0;
- \3504 [704] = 1'h0;
- \3504 [705] = 1'h0;
- \3504 [706] = 1'h0;
- \3504 [707] = 1'h0;
- \3504 [708] = 1'h0;
- \3504 [709] = 1'h0;
- \3504 [710] = 1'h0;
- \3504 [711] = 1'h0;
- \3504 [712] = 1'h0;
- \3504 [713] = 1'h0;
- \3504 [714] = 1'h0;
- \3504 [715] = 1'h0;
- \3504 [716] = 1'h0;
- \3504 [717] = 1'h0;
- \3504 [718] = 1'h0;
- \3504 [719] = 1'h0;
- \3504 [720] = 1'h0;
- \3504 [721] = 1'h0;
- \3504 [722] = 1'h0;
- \3504 [723] = 1'h0;
- \3504 [724] = 1'h0;
- \3504 [725] = 1'h0;
- \3504 [726] = 1'h0;
- \3504 [727] = 1'h0;
- \3504 [728] = 1'h0;
- \3504 [729] = 1'h0;
- \3504 [730] = 1'h0;
- \3504 [731] = 1'h0;
- \3504 [732] = 1'h0;
- \3504 [733] = 1'h1;
- \3504 [734] = 1'h1;
- \3504 [735] = 1'h0;
- \3504 [736] = 1'h0;
- \3504 [737] = 1'h0;
- \3504 [738] = 1'h0;
- \3504 [739] = 1'h0;
- \3504 [740] = 1'h0;
- \3504 [741] = 1'h0;
- \3504 [742] = 1'h0;
- \3504 [743] = 1'h0;
- \3504 [744] = 1'h0;
- \3504 [745] = 1'h0;
- \3504 [746] = 1'h0;
- \3504 [747] = 1'h0;
- \3504 [748] = 1'h0;
- \3504 [749] = 1'h0;
- \3504 [750] = 1'h0;
- \3504 [751] = 1'h0;
- \3504 [752] = 1'h0;
- \3504 [753] = 1'h0;
- \3504 [754] = 1'h0;
- \3504 [755] = 1'h0;
- \3504 [756] = 1'h0;
- \3504 [757] = 1'h0;
- \3504 [758] = 1'h0;
- \3504 [759] = 1'h0;
- \3504 [760] = 1'h0;
- \3504 [761] = 1'h0;
- \3504 [762] = 1'h0;
- \3504 [763] = 1'h0;
- \3504 [764] = 1'h0;
- \3504 [765] = 1'h1;
- \3504 [766] = 1'h1;
- \3504 [767] = 1'h0;
- \3504 [768] = 1'h0;
- \3504 [769] = 1'h0;
- \3504 [770] = 1'h0;
- \3504 [771] = 1'h0;
- \3504 [772] = 1'h0;
- \3504 [773] = 1'h0;
- \3504 [774] = 1'h0;
- \3504 [775] = 1'h0;
- \3504 [776] = 1'h0;
- \3504 [777] = 1'h0;
- \3504 [778] = 1'h0;
- \3504 [779] = 1'h0;
- \3504 [780] = 1'h0;
- \3504 [781] = 1'h0;
- \3504 [782] = 1'h0;
- \3504 [783] = 1'h0;
- \3504 [784] = 1'h0;
- \3504 [785] = 1'h0;
- \3504 [786] = 1'h0;
- \3504 [787] = 1'h0;
- \3504 [788] = 1'h0;
- \3504 [789] = 1'h0;
- \3504 [790] = 1'h0;
- \3504 [791] = 1'h0;
- \3504 [792] = 1'h0;
- \3504 [793] = 1'h0;
- \3504 [794] = 1'h0;
- \3504 [795] = 1'h0;
- \3504 [796] = 1'h0;
- \3504 [797] = 1'h1;
- \3504 [798] = 1'h1;
- \3504 [799] = 1'h0;
- \3504 [800] = 1'h0;
- \3504 [801] = 1'h0;
- \3504 [802] = 1'h0;
- \3504 [803] = 1'h0;
- \3504 [804] = 1'h0;
- \3504 [805] = 1'h0;
- \3504 [806] = 1'h0;
- \3504 [807] = 1'h0;
- \3504 [808] = 1'h0;
- \3504 [809] = 1'h0;
- \3504 [810] = 1'h0;
- \3504 [811] = 1'h0;
- \3504 [812] = 1'h0;
- \3504 [813] = 1'h0;
- \3504 [814] = 1'h0;
- \3504 [815] = 1'h0;
- \3504 [816] = 1'h0;
- \3504 [817] = 1'h0;
- \3504 [818] = 1'h0;
- \3504 [819] = 1'h0;
- \3504 [820] = 1'h0;
- \3504 [821] = 1'h0;
- \3504 [822] = 1'h0;
- \3504 [823] = 1'h0;
- \3504 [824] = 1'h0;
- \3504 [825] = 1'h0;
- \3504 [826] = 1'h0;
- \3504 [827] = 1'h0;
- \3504 [828] = 1'h0;
- \3504 [829] = 1'h1;
- \3504 [830] = 1'h1;
- \3504 [831] = 1'h0;
- \3504 [832] = 1'h0;
- \3504 [833] = 1'h0;
- \3504 [834] = 1'h0;
- \3504 [835] = 1'h0;
- \3504 [836] = 1'h0;
- \3504 [837] = 1'h0;
- \3504 [838] = 1'h0;
- \3504 [839] = 1'h0;
- \3504 [840] = 1'h0;
- \3504 [841] = 1'h0;
- \3504 [842] = 1'h0;
- \3504 [843] = 1'h0;
- \3504 [844] = 1'h0;
- \3504 [845] = 1'h0;
- \3504 [846] = 1'h0;
- \3504 [847] = 1'h0;
- \3504 [848] = 1'h0;
- \3504 [849] = 1'h0;
- \3504 [850] = 1'h0;
- \3504 [851] = 1'h0;
- \3504 [852] = 1'h0;
- \3504 [853] = 1'h0;
- \3504 [854] = 1'h0;
- \3504 [855] = 1'h0;
- \3504 [856] = 1'h0;
- \3504 [857] = 1'h0;
- \3504 [858] = 1'h0;
- \3504 [859] = 1'h0;
- \3504 [860] = 1'h0;
- \3504 [861] = 1'h1;
- \3504 [862] = 1'h0;
- \3504 [863] = 1'h0;
- \3504 [864] = 1'h0;
- \3504 [865] = 1'h0;
- \3504 [866] = 1'h0;
- \3504 [867] = 1'h0;
- \3504 [868] = 1'h0;
- \3504 [869] = 1'h0;
- \3504 [870] = 1'h0;
- \3504 [871] = 1'h0;
- \3504 [872] = 1'h0;
- \3504 [873] = 1'h1;
- \3504 [874] = 1'h0;
- \3504 [875] = 1'h0;
- \3504 [876] = 1'h0;
- \3504 [877] = 1'h0;
- \3504 [878] = 1'h0;
- \3504 [879] = 1'h0;
- \3504 [880] = 1'h0;
- \3504 [881] = 1'h0;
- \3504 [882] = 1'h0;
- \3504 [883] = 1'h0;
- \3504 [884] = 1'h0;
- \3504 [885] = 1'h0;
- \3504 [886] = 1'h0;
- \3504 [887] = 1'h0;
- \3504 [888] = 1'h0;
- \3504 [889] = 1'h0;
- \3504 [890] = 1'h0;
- \3504 [891] = 1'h0;
- \3504 [892] = 1'h0;
- \3504 [893] = 1'h1;
- \3504 [894] = 1'h1;
- \3504 [895] = 1'h0;
- \3504 [896] = 1'h0;
- \3504 [897] = 1'h0;
- \3504 [898] = 1'h0;
- \3504 [899] = 1'h0;
- \3504 [900] = 1'h0;
- \3504 [901] = 1'h0;
- \3504 [902] = 1'h0;
- \3504 [903] = 1'h0;
- \3504 [904] = 1'h0;
- \3504 [905] = 1'h0;
- \3504 [906] = 1'h0;
- \3504 [907] = 1'h0;
- \3504 [908] = 1'h0;
- \3504 [909] = 1'h0;
- \3504 [910] = 1'h0;
- \3504 [911] = 1'h0;
- \3504 [912] = 1'h0;
- \3504 [913] = 1'h0;
- \3504 [914] = 1'h0;
- \3504 [915] = 1'h0;
- \3504 [916] = 1'h0;
- \3504 [917] = 1'h0;
- \3504 [918] = 1'h0;
- \3504 [919] = 1'h0;
- \3504 [920] = 1'h0;
- \3504 [921] = 1'h0;
- \3504 [922] = 1'h0;
- \3504 [923] = 1'h0;
- \3504 [924] = 1'h0;
- \3504 [925] = 1'h1;
- \3504 [926] = 1'h0;
- \3504 [927] = 1'h0;
- \3504 [928] = 1'h0;
- \3504 [929] = 1'h0;
- \3504 [930] = 1'h0;
- \3504 [931] = 1'h0;
- \3504 [932] = 1'h0;
- \3504 [933] = 1'h0;
- \3504 [934] = 1'h0;
- \3504 [935] = 1'h0;
- \3504 [936] = 1'h0;
- \3504 [937] = 1'h0;
- \3504 [938] = 1'h0;
- \3504 [939] = 1'h0;
- \3504 [940] = 1'h0;
- \3504 [941] = 1'h0;
- \3504 [942] = 1'h0;
- \3504 [943] = 1'h0;
- \3504 [944] = 1'h0;
- \3504 [945] = 1'h0;
- \3504 [946] = 1'h0;
- \3504 [947] = 1'h0;
- \3504 [948] = 1'h0;
- \3504 [949] = 1'h0;
- \3504 [950] = 1'h0;
- \3504 [951] = 1'h0;
- \3504 [952] = 1'h0;
- \3504 [953] = 1'h0;
- \3504 [954] = 1'h0;
- \3504 [955] = 1'h0;
- \3504 [956] = 1'h0;
- \3504 [957] = 1'h1;
- \3504 [958] = 1'h0;
- \3504 [959] = 1'h0;
- \3504 [960] = 1'h0;
- \3504 [961] = 1'h0;
- \3504 [962] = 1'h0;
- \3504 [963] = 1'h0;
- \3504 [964] = 1'h0;
- \3504 [965] = 1'h0;
- \3504 [966] = 1'h0;
- \3504 [967] = 1'h0;
- \3504 [968] = 1'h0;
- \3504 [969] = 1'h0;
- \3504 [970] = 1'h0;
- \3504 [971] = 1'h0;
- \3504 [972] = 1'h0;
- \3504 [973] = 1'h0;
- \3504 [974] = 1'h0;
- \3504 [975] = 1'h0;
- \3504 [976] = 1'h0;
- \3504 [977] = 1'h0;
- \3504 [978] = 1'h0;
- \3504 [979] = 1'h0;
- \3504 [980] = 1'h0;
- \3504 [981] = 1'h0;
- \3504 [982] = 1'h0;
- \3504 [983] = 1'h0;
- \3504 [984] = 1'h0;
- \3504 [985] = 1'h0;
- \3504 [986] = 1'h0;
- \3504 [987] = 1'h0;
- \3504 [988] = 1'h0;
- \3504 [989] = 1'h1;
- \3504 [990] = 1'h1;
- \3504 [991] = 1'h0;
- \3504 [992] = 1'h0;
- \3504 [993] = 1'h0;
- \3504 [994] = 1'h0;
- \3504 [995] = 1'h0;
- \3504 [996] = 1'h0;
- \3504 [997] = 1'h0;
- \3504 [998] = 1'h0;
- \3504 [999] = 1'h0;
- \3504 [1000] = 1'h0;
- \3504 [1001] = 1'h0;
- \3504 [1002] = 1'h0;
- \3504 [1003] = 1'h0;
- \3504 [1004] = 1'h0;
- \3504 [1005] = 1'h1;
- \3504 [1006] = 1'h0;
- \3504 [1007] = 1'h1;
- \3504 [1008] = 1'h0;
- \3504 [1009] = 1'h0;
- \3504 [1010] = 1'h0;
- \3504 [1011] = 1'h0;
- \3504 [1012] = 1'h0;
- \3504 [1013] = 1'h0;
- \3504 [1014] = 1'h0;
- \3504 [1015] = 1'h0;
- \3504 [1016] = 1'h0;
- \3504 [1017] = 1'h0;
- \3504 [1018] = 1'h0;
- \3504 [1019] = 1'h0;
- \3504 [1020] = 1'h0;
- \3504 [1021] = 1'h1;
- \3504 [1022] = 1'h0;
- \3504 [1023] = 1'h1;
- end
- assign _86_ = \3504 [_09_];
- reg [37:0] \3506 [7:0];
- initial begin
- \3506 [0] = 38'h2000000071;
- \3506 [1] = 38'h2800000001;
- \3506 [2] = 38'h0000006bc5;
- \3506 [3] = 38'h1000076b1d;
- \3506 [4] = 38'h2800000001;
- \3506 [5] = 38'h2800000001;
- \3506 [6] = 38'h0800014409;
- \3506 [7] = 38'h00000c0039;
- end
- assign _88_ = \3506 [_11_];
- reg [37:0] \3508 [15:0];
- initial begin
- \3508 [0] = 38'h2800000001;
- \3508 [1] = 38'h2800000001;
- \3508 [2] = 38'h2800000001;
- \3508 [3] = 38'h2800000001;
- \3508 [4] = 38'h2800000001;
- \3508 [5] = 38'h2800000001;
- \3508 [6] = 38'h08000288d1;
- \3508 [7] = 38'h08000288cd;
- \3508 [8] = 38'h080002d9c9;
- \3508 [9] = 38'h080002d9c9;
- \3508 [10] = 38'h080002d8c9;
- \3508 [11] = 38'h080002d8c9;
- \3508 [12] = 38'h080002d8d1;
- \3508 [13] = 38'h080002d8d1;
- \3508 [14] = 38'h080002d8cd;
- \3508 [15] = 38'h080002d8cd;
- end
- assign _90_ = \3508 [_14_];
- reg [37:0] \3510 [3:0];
- initial begin
- \3510 [0] = 38'h0000000000;
- \3510 [1] = 38'h0026014a76;
- \3510 [2] = 38'h0048014a76;
- \3510 [3] = 38'h0008014a76;
- end
- assign _92_ = \3510 [_16_];
- reg [37:0] \3512 [3:0];
- initial begin
- \3512 [0] = 38'h0000000000;
- \3512 [1] = 38'h0000000000;
- \3512 [2] = 38'h004800ca7a;
- \3512 [3] = 38'h000800ca7a;
- end
- assign _94_ = \3512 [_18_];
- reg [37:0] \3514 [63:0];
- initial begin
- \3514 [0] = 38'h2800000001;
- \3514 [1] = 38'h2800000001;
- \3514 [2] = 38'h2800000001;
- \3514 [3] = 38'h2800000001;
- \3514 [4] = 38'h2800000001;
- \3514 [5] = 38'h2800000001;
- \3514 [6] = 38'h2800000001;
- \3514 [7] = 38'h2800000001;
- \3514 [8] = 38'h2800000001;
- \3514 [9] = 38'h2800000001;
- \3514 [10] = 38'h2800000001;
- \3514 [11] = 38'h2800000001;
- \3514 [12] = 38'h2800000001;
- \3514 [13] = 38'h2800000001;
- \3514 [14] = 38'h2800000001;
- \3514 [15] = 38'h2800000001;
- \3514 [16] = 38'h2800000001;
- \3514 [17] = 38'h2800000001;
- \3514 [18] = 38'h0044009a7a;
- \3514 [19] = 38'h0004009a7a;
- \3514 [20] = 38'h0064011a76;
- \3514 [21] = 38'h0024011a76;
- \3514 [22] = 38'h0044011a76;
- \3514 [23] = 38'h0004011a76;
- \3514 [24] = 38'h0042009a7a;
- \3514 [25] = 38'h0002009a7a;
- \3514 [26] = 38'h0046009a7a;
- \3514 [27] = 38'h0006009a7a;
- \3514 [28] = 38'h0042011a76;
- \3514 [29] = 38'h0002011a76;
- \3514 [30] = 38'h0046011a76;
- \3514 [31] = 38'h0006011a76;
- \3514 [32] = 38'h2800000001;
- \3514 [33] = 38'h2800000001;
- \3514 [34] = 38'h040002a80d;
- \3514 [35] = 38'h040002900d;
- \3514 [36] = 38'h000002a8f1;
- \3514 [37] = 38'h00000290f1;
- \3514 [38] = 38'h000002a8b9;
- \3514 [39] = 38'h00000290b9;
- \3514 [40] = 38'h09000288c9;
- \3514 [41] = 38'h2800000001;
- \3514 [42] = 38'h090002e0c9;
- \3514 [43] = 38'h090002e1c9;
- \3514 [44] = 38'h2800000001;
- \3514 [45] = 38'h1000003015;
- \3514 [46] = 38'h00000000d5;
- \3514 [47] = 38'h1000073b19;
- \3514 [48] = 38'h0000012209;
- \3514 [49] = 38'h0000011a09;
- \3514 [50] = 38'h0401011909;
- \3514 [51] = 38'h0001011909;
- \3514 [52] = 38'h0200981925;
- \3514 [53] = 38'h0000981125;
- \3514 [54] = 38'h2800000001;
- \3514 [55] = 38'h0001911909;
- \3514 [56] = 38'h02000919ad;
- \3514 [57] = 38'h2800000001;
- \3514 [58] = 38'h2800000001;
- \3514 [59] = 38'h2800000001;
- \3514 [60] = 38'h21000019ed;
- \3514 [61] = 38'h20000019ed;
- \3514 [62] = 38'h2800000001;
- \3514 [63] = 38'h2000000011;
- end
- assign _96_ = \3514 [_21_];
- assign d_out = r;
-endmodule
-
-module decode2_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, complete_in, stall_in, flush_in, d_in, r_in, c_in, stall_out, stopped_out, e_out, r_out, c_out);
- wire _00_;
- wire _01_;
- wire [5:0] _02_;
- wire [5:0] _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- wire _08_;
- wire _09_;
- wire _10_;
- wire _11_;
- wire _12_;
- wire _13_;
- wire _14_;
- wire _15_;
- wire _16_;
- wire _17_;
- wire [70:0] _18_;
- wire [70:0] _19_;
- wire [70:0] _20_;
- wire _21_;
- wire _22_;
- wire _23_;
- wire _24_;
- wire _25_;
- wire _26_;
- wire _27_;
- wire _28_;
- wire _29_;
- wire _30_;
- wire _31_;
- wire _32_;
- wire _33_;
- wire _34_;
- wire _35_;
- wire _36_;
- wire _37_;
- wire _38_;
- wire _39_;
- wire _40_;
- wire _41_;
- wire [70:0] _42_;
- wire _43_;
- wire _44_;
- wire [70:0] _45_;
- wire _46_;
- wire _47_;
- wire _48_;
- wire _49_;
- wire _50_;
- wire _51_;
- wire _52_;
- wire _53_;
- wire [6:0] _54_;
- wire _55_;
- wire _56_;
- wire _57_;
- wire _58_;
- wire _59_;
- wire _60_;
- wire _61_;
- wire _62_;
- wire [3:0] _63_;
- wire _64_;
- wire _65_;
- wire _66_;
- wire _67_;
- wire _68_;
- wire _69_;
- wire _70_;
- wire _71_;
- wire _72_;
- wire _73_;
- wire _74_;
- wire _75_;
- wire _76_;
- wire _77_;
- wire _78_;
- wire _79_;
- wire _80_;
- wire _81_;
- wire _82_;
- wire [5:0] _83_;
- input [36:0] c_in;
- output c_out;
- input clk;
- input complete_in;
- wire control_valid_out;
- wire cr_write_valid;
- input [147:0] d_in;
- output [374:0] e_out;
- input flush_in;
- wire gpr_a_bypass;
- wire gpr_b_bypass;
- wire gpr_bypassable;
- wire gpr_c_bypass;
- reg [374:0] r;
- input [191:0] r_in;
- output [19:0] r_out;
- wire [374:0] rin;
- input rst;
- input stall_in;
- output stall_out;
- output stopped_out;
- always @(posedge clk)
- r <= rin;
- assign _02_ = d_in[103] ? d_in[103:98] : { 1'h0, d_in[86:82] };
- assign _03_ = d_in[109] ? d_in[109:104] : { 1'h0, d_in[81:77] };
- assign _04_ = d_in[120:118] == 3'h1;
- assign _05_ = d_in[120:118] == 3'h2;
- assign _06_ = d_in[86:82] != 5'h00;
- assign _07_ = _05_ & _06_;
- assign _08_ = _04_ | _07_;
- assign _09_ = ~ d_in[103];
- assign _10_ = ~ 1'h0;
- assign _11_ = _10_ | _09_;
- assign _12_ = d_in[120:118] == 3'h3;
- assign _13_ = d_in[103:98] == 6'h00;
- assign _14_ = d_in[103] | _13_;
- assign _15_ = ~ 1'h0;
- assign _16_ = _15_ | _14_;
- assign _17_ = d_in[120:118] == 3'h4;
- assign _18_ = _17_ ? { d_in[65:2], 7'h00 } : 71'h000000000000000000;
- assign _19_ = _12_ ? { r_in[63:0], d_in[103:98], d_in[103] } : _18_;
- assign _20_ = _08_ ? { r_in[63:0], 1'h0, d_in[86:82], 1'h1 } : _19_;
- assign _21_ = ~ d_in[109];
- assign _22_ = ~ 1'h0;
- assign _23_ = _22_ | _21_;
- assign _24_ = d_in[124:121] == 4'h1;
- assign _25_ = d_in[124:121] == 4'h2;
- assign _26_ = d_in[124:121] == 4'h3;
- assign _27_ = d_in[124:121] == 4'h4;
- assign _28_ = d_in[124:121] == 4'h5;
- assign _29_ = d_in[124:121] == 4'h6;
- assign _30_ = d_in[124:121] == 4'h7;
- assign _31_ = d_in[124:121] == 4'h9;
- assign _32_ = d_in[124:121] == 4'h8;
- assign _33_ = d_in[124:121] == 4'ha;
- assign _34_ = d_in[124:121] == 4'hb;
- assign _35_ = d_in[124:121] == 4'hc;
- assign _36_ = d_in[109:104] == 6'h00;
- assign _37_ = d_in[109] | _36_;
- assign _38_ = ~ 1'h0;
- assign _39_ = _38_ | _37_;
- assign _40_ = d_in[124:121] == 4'hd;
- assign _41_ = d_in[124:121] == 4'h0;
- function [70:0] \3888 ;
- input [70:0] a;
- input [993:0] b;
- input [13:0] s;
- (* parallel_case *)
- casez (s)
- 14'b?????????????1:
- \3888 = b[70:0];
- 14'b????????????1?:
- \3888 = b[141:71];
- 14'b???????????1??:
- \3888 = b[212:142];
- 14'b??????????1???:
- \3888 = b[283:213];
- 14'b?????????1????:
- \3888 = b[354:284];
- 14'b????????1?????:
- \3888 = b[425:355];
- 14'b???????1??????:
- \3888 = b[496:426];
- 14'b??????1???????:
- \3888 = b[567:497];
- 14'b?????1????????:
- \3888 = b[638:568];
- 14'b????1?????????:
- \3888 = b[709:639];
- 14'b???1??????????:
- \3888 = b[780:710];
- 14'b??1???????????:
- \3888 = b[851:781];
- 14'b?1????????????:
- \3888 = b[922:852];
- 14'b1?????????????:
- \3888 = b[993:923];
- default:
- \3888 = a;
- endcase
- endfunction
- assign _42_ = \3888 (71'hxxxxxxxxxxxxxxxxxx, { 71'h000000000000000000, r_in[127:64], d_in[109:104], d_in[109], 59'h000000000000000, d_in[81:77], 65'h00000000000000000, d_in[67], d_in[81:77], 78'h007fffffffffffffff80, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:72], d_in[86:82], d_in[66], 23'h000200, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 9'h000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 9'h000, d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91:68], 41'h00000000000, d_in[81:66], 23'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 23'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 55'h00000000000000, d_in[81:66], 7'h00, r_in[127:64], 1'h0, d_in[81:77], 1'h1 }, { _41_, _40_, _35_, _34_, _33_, _32_, _31_, _30_, _29_, _28_, _27_, _26_, _25_, _24_ });
- assign _43_ = d_in[125] == 1'h1;
- assign _44_ = d_in[125] == 1'h0;
- function [70:0] \3929 ;
- input [70:0] a;
- input [141:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \3929 = b[70:0];
- 2'b1?:
- \3929 = b[141:71];
- default:
- \3929 = a;
- endcase
- endfunction
- assign _45_ = \3929 (71'hxxxxxxxxxxxxxxxxxx, { 71'h000000000000000000, r_in[191:128], 1'h0, d_in[91:87], 1'h1 }, { _44_, _43_ });
- assign _46_ = d_in[127:126] == 2'h1;
- assign _47_ = d_in[127:126] == 2'h2;
- assign _48_ = d_in[103:98] == 6'h00;
- assign _49_ = d_in[103] | _48_;
- assign _50_ = ~ 1'h0;
- assign _51_ = _50_ | _49_;
- assign _52_ = d_in[127:126] == 2'h3;
- assign _53_ = d_in[127:126] == 2'h0;
- function [6:0] \4000 ;
- input [6:0] a;
- input [27:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \4000 = b[6:0];
- 4'b??1?:
- \4000 = b[13:7];
- 4'b?1??:
- \4000 = b[20:14];
- 4'b1???:
- \4000 = b[27:21];
- default:
- \4000 = a;
- endcase
- endfunction
- assign _54_ = \4000 (7'hxx, { 7'h00, d_in[103:98], d_in[103], 1'h0, d_in[86:82], 2'h2, d_in[91:87], 1'h1 }, { _53_, _52_, _47_, _46_ });
- assign _55_ = _20_[0] & d_in[0];
- assign _56_ = _42_[0] & d_in[0];
- assign _57_ = _45_[0] & d_in[0];
- assign _58_ = d_in[137:135] == 3'h1;
- assign _59_ = d_in[137:135] == 3'h2;
- assign _60_ = d_in[137:135] == 3'h3;
- assign _61_ = d_in[137:135] == 3'h4;
- assign _62_ = d_in[137:135] == 3'h0;
- function [3:0] \4033 ;
- input [3:0] a;
- input [19:0] b;
- input [4:0] s;
- (* parallel_case *)
- casez (s)
- 5'b????1:
- \4033 = b[3:0];
- 5'b???1?:
- \4033 = b[7:4];
- 5'b??1??:
- \4033 = b[11:8];
- 5'b?1???:
- \4033 = b[15:12];
- 5'b1????:
- \4033 = b[19:16];
- default:
- \4033 = a;
- endcase
- endfunction
- assign _63_ = \4033 (4'hx, 20'h08421, { _62_, _61_, _60_, _59_, _58_ });
- assign _64_ = d_in[145:144] == 2'h2;
- assign _65_ = d_in[145:144] == 2'h1;
- assign _66_ = d_in[145:144] == 2'h0;
- function [0:0] \4083 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \4083 = b[0:0];
- 3'b?1?:
- \4083 = b[1:1];
- 3'b1??:
- \4083 = b[2:2];
- default:
- \4083 = a;
- endcase
- endfunction
- assign _67_ = \4083 (1'hx, { 2'h1, d_in[66] }, { _66_, _65_, _64_ });
- assign _68_ = d_in[117:112] == 6'h2d;
- assign _69_ = d_in[117:112] == 6'h2c;
- assign _70_ = _68_ | _69_;
- assign _71_ = ~ _70_;
- assign _72_ = d_in[145:144] == 2'h2;
- function [0:0] \4113 ;
- input [0:0] a;
- input [0:0] b;
- input [0:0] s;
- (* parallel_case *)
- casez (s)
- 1'b1:
- \4113 = b[0:0];
- default:
- \4113 = a;
- endcase
- endfunction
- assign _73_ = \4113 (1'h0, d_in[76], _72_);
- assign _74_ = _71_ ? _73_ : 1'h0;
- assign _75_ = d_in[146] ? d_in[66] : 1'h0;
- assign _76_ = d_in[111:110] == 2'h1;
- assign _77_ = 1'h1 & _76_;
- assign gpr_bypassable = _77_ ? 1'h1 : 1'h0;
- assign _78_ = d_in[145:144] == 2'h2;
- assign _79_ = d_in[145:144] == 2'h1;
- assign _80_ = d_in[145:144] == 2'h0;
- function [0:0] \4217 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \4217 = b[0:0];
- 3'b?1?:
- \4217 = b[1:1];
- 3'b1??:
- \4217 = b[2:2];
- default:
- \4217 = a;
- endcase
- endfunction
- assign _81_ = \4217 (1'hx, { 2'h1, d_in[66] }, { _80_, _79_, _78_ });
- assign cr_write_valid = d_in[129] | _81_;
- assign _82_ = d_in[111:110] == 2'h0;
- assign _83_ = _82_ ? 6'h00 : d_in[117:112];
- assign rin = rst ? 375'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { d_in[141:138], _63_, d_in[97:66], d_in[143:142], 2'h0, d_in[134:130], _74_, _67_, _75_, c_in, gpr_c_bypass, gpr_b_bypass, gpr_a_bypass, _45_[70:7], _42_[70:7], _20_[70:7], _42_[6:1], _20_[6:1], _54_[6:1], d_in[65:2], _83_, d_in[111:110], control_valid_out };
- control_1 control_0 (
- .clk(clk),
- .complete_in(complete_in),
- .cr_read_in(d_in[128]),
- .cr_write_in(cr_write_valid),
- .flush_in(flush_in),
- .gpr_a_read_in(_20_[6:1]),
- .gpr_a_read_valid_in(_20_[0]),
- .gpr_b_read_in(_42_[6:1]),
- .gpr_b_read_valid_in(_42_[0]),
- .gpr_bypass_a(gpr_a_bypass),
- .gpr_bypass_b(gpr_b_bypass),
- .gpr_bypass_c(gpr_c_bypass),
- .gpr_bypassable(gpr_bypassable),
- .gpr_c_read_in(_45_[5:1]),
- .gpr_c_read_valid_in(_45_[0]),
- .gpr_write_in(_54_[6:1]),
- .gpr_write_valid_in(_54_[0]),
- .rst(rst),
- .sgl_pipe_in(d_in[147]),
- .stall_in(stall_in),
- .stall_out(_00_),
- .stop_mark_in(d_in[1]),
- .stopped_out(_01_),
- .valid_in(d_in[0]),
- .valid_out(control_valid_out)
- );
- assign stall_out = _00_;
- assign stopped_out = _01_;
- assign e_out = r;
- assign r_out = { d_in[91:87], _57_, _03_, _56_, _02_, _55_ };
- assign c_out = d_in[128];
-endmodule
-
-module divider(clk, rst, d_in, d_out);
- wire [128:0] _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire [63:0] _06_;
- wire [6:0] _07_;
- wire _08_;
- wire _09_;
- wire _10_;
- wire _11_;
- wire [6:0] _12_;
- wire _13_;
- wire [6:0] _14_;
- wire [128:0] _15_;
- wire [63:0] _16_;
- wire [6:0] _17_;
- wire _18_;
- wire [128:0] _19_;
- wire [63:0] _20_;
- wire [6:0] _21_;
- wire _22_;
- wire [128:0] _23_;
- wire [63:0] _24_;
- wire _25_;
- wire [6:0] _26_;
- wire _27_;
- wire _28_;
- wire [128:0] _29_;
- wire [63:0] _30_;
- wire [63:0] _31_;
- wire _32_;
- wire [6:0] _33_;
- wire _34_;
- wire _35_;
- wire _36_;
- wire _37_;
- wire _38_;
- wire _39_;
- wire [128:0] _40_;
- wire [63:0] _41_;
- wire [63:0] _42_;
- wire _43_;
- wire [6:0] _44_;
- wire _45_;
- wire _46_;
- wire _47_;
- wire _48_;
- wire _49_;
- wire _50_;
- wire [64:0] _51_;
- wire _52_;
- wire _53_;
- wire _54_;
- wire _55_;
- wire _56_;
- wire _57_;
- wire _58_;
- wire _59_;
- wire _60_;
- wire _61_;
- wire [63:0] _62_;
- wire _63_;
- wire _64_;
- reg [65:0] _65_;
- input clk;
- reg [6:0] count;
- input [133:0] d_in;
- output [65:0] d_out;
- reg [128:0] dend;
- wire did_ovf;
- reg [63:0] div;
- reg is_32bit;
- reg is_modulus;
- reg is_signed;
- reg neg_result;
- wire [63:0] oresult;
- reg overflow;
- reg ovf32;
- reg [63:0] quot;
- wire [63:0] result;
- input rst;
- reg running;
- wire [64:0] sresult;
- assign _00_ = d_in[131] ? { 1'h0, d_in[64:1], 64'h0000000000000000 } : { 65'h00000000000000000, d_in[64:1] };
- assign _01_ = count == 7'h3f;
- assign _02_ = _25_ ? 1'h0 : running;
- assign _03_ = dend[127:64] >= div;
- assign _04_ = dend[128] | _03_;
- assign _05_ = ovf32 | quot[31];
- assign _06_ = dend[127:64] - div;
- assign _07_ = count + 7'h01;
- assign _08_ = dend[128:57] == 72'h000000000000000000;
- assign _09_ = count[6:3] != 4'h7;
- assign _10_ = _08_ & _09_;
- assign _11_ = | { ovf32, quot[31:24] };
- assign _12_ = count + 7'h08;
- assign _13_ = ovf32 | quot[31];
- assign _14_ = count + 7'h01;
- assign _15_ = _10_ ? { dend[120:0], 8'h00 } : { dend[127:0], 1'h0 };
- assign _16_ = _10_ ? { quot[55:0], 8'h00 } : { quot[62:0], 1'h0 };
- assign _17_ = _10_ ? _12_ : _14_;
- assign _18_ = _10_ ? _11_ : _13_;
- assign _19_ = _04_ ? { _06_, dend[63:0], 1'h0 } : _15_;
- assign _20_ = _04_ ? { quot[62:0], 1'h1 } : _16_;
- assign _21_ = _04_ ? _07_ : _17_;
- assign _22_ = _04_ ? _05_ : _18_;
- assign _23_ = running ? _19_ : dend;
- assign _24_ = running ? _20_ : quot;
- assign _25_ = running & _01_;
- assign _26_ = running ? _21_ : 7'h00;
- assign _27_ = running ? quot[63] : overflow;
- assign _28_ = running ? _22_ : ovf32;
- assign _29_ = d_in[0] ? _00_ : _23_;
- assign _30_ = d_in[0] ? d_in[128:65] : div;
- assign _31_ = d_in[0] ? 64'h0000000000000000 : _24_;
- assign _32_ = d_in[0] ? 1'h1 : _02_;
- assign _33_ = d_in[0] ? 7'h7f : _26_;
- assign _34_ = d_in[0] ? d_in[133] : neg_result;
- assign _35_ = d_in[0] ? d_in[132] : is_modulus;
- assign _36_ = d_in[0] ? d_in[130] : is_32bit;
- assign _37_ = d_in[0] ? d_in[129] : is_signed;
- assign _38_ = d_in[0] ? 1'h0 : _27_;
- assign _39_ = d_in[0] ? 1'h0 : _28_;
- assign _40_ = rst ? 129'h000000000000000000000000000000000 : _29_;
- assign _41_ = rst ? 64'h0000000000000000 : _30_;
- assign _42_ = rst ? 64'h0000000000000000 : _31_;
- assign _43_ = rst ? 1'h0 : _32_;
- assign _44_ = rst ? 7'h00 : _33_;
- assign _45_ = rst ? neg_result : _34_;
- assign _46_ = rst ? is_modulus : _35_;
- assign _47_ = rst ? is_32bit : _36_;
- assign _48_ = rst ? is_signed : _37_;
- assign _49_ = rst ? overflow : _38_;
- assign _50_ = rst ? ovf32 : _39_;
- always @(posedge clk)
- dend <= _40_;
- always @(posedge clk)
- div <= _41_;
- always @(posedge clk)
- quot <= _42_;
- always @(posedge clk)
- running <= _43_;
- always @(posedge clk)
- count <= _44_;
- always @(posedge clk)
- neg_result <= _45_;
- always @(posedge clk)
- is_modulus <= _46_;
- always @(posedge clk)
- is_32bit <= _47_;
- always @(posedge clk)
- is_signed <= _48_;
- always @(posedge clk)
- overflow <= _49_;
- always @(posedge clk)
- ovf32 <= _50_;
- assign result = is_modulus ? dend[128:65] : quot;
- assign _51_ = - $signed({ 1'h0, result });
- assign sresult = neg_result ? _51_ : { 1'h0, result };
- assign _52_ = ~ is_32bit;
- assign _53_ = sresult[64] ^ sresult[63];
- assign _54_ = is_signed & _53_;
- assign _55_ = overflow | _54_;
- assign _56_ = sresult[32] != sresult[31];
- assign _57_ = ovf32 | _56_;
- assign _58_ = _57_ ? 1'h1 : 1'h0;
- assign _59_ = is_signed ? _58_ : ovf32;
- assign did_ovf = _52_ ? _55_ : _59_;
- assign _60_ = ~ is_modulus;
- assign _61_ = is_32bit & _60_;
- assign _62_ = _61_ ? { 32'h00000000, sresult[31:0] } : sresult[63:0];
- assign oresult = did_ovf ? 64'h0000000000000000 : _62_;
- assign _63_ = count == 7'h40;
- assign _64_ = _63_ ? 1'h1 : 1'h0;
- always @(posedge clk)
- _65_ <= { did_ovf, oresult, _64_ };
- assign d_out = _65_;
-endmodule
-
-module execute1_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, e_in, l_in, ext_irq_in, flush_out, stall_out, l_out, f_out, e_out, dbg_msr_out, icache_inval, terminate_out);
- wire _0000_;
- wire _0001_;
- wire _0002_;
- wire _0003_;
- wire _0004_;
- wire _0005_;
- wire _0006_;
- wire [334:0] _0007_;
- wire [127:0] _0008_;
- wire [64:0] _0009_;
- wire [127:0] _0010_;
- wire _0011_;
- reg _0012_ = 1'h1;
- wire [4:0] _0013_;
- wire [129:0] _0014_;
- wire [129:0] _0015_;
- wire [129:0] _0016_;
- wire _0017_;
- wire _0018_;
- wire _0019_;
- wire _0020_;
- wire _0021_;
- wire [63:0] _0022_;
- wire [63:0] _0023_;
- wire _0024_;
- wire [63:0] _0025_;
- wire [63:0] _0026_;
- wire _0027_;
- wire _0028_;
- wire _0029_;
- wire _0030_;
- wire _0031_;
- wire _0032_;
- wire _0033_;
- wire _0034_;
- wire _0035_;
- wire [63:0] _0036_;
- wire [127:0] _0037_;
- wire _0038_;
- wire [63:0] _0039_;
- wire [63:0] _0040_;
- wire [63:0] _0041_;
- wire _0042_;
- wire [63:0] _0043_;
- wire _0044_;
- wire [63:0] _0045_;
- wire _0046_;
- wire _0047_;
- wire [63:0] _0048_;
- wire _0049_;
- wire _0050_;
- wire _0051_;
- wire _0052_;
- wire _0053_;
- wire _0054_;
- wire _0055_;
- wire _0056_;
- wire _0057_;
- wire _0058_;
- wire _0059_;
- wire [5:0] _0060_;
- wire _0061_;
- wire _0062_;
- wire _0063_;
- wire _0064_;
- wire _0065_;
- wire _0066_;
- wire _0067_;
- wire _0068_;
- wire _0069_;
- wire _0070_;
- wire [127:0] _0071_;
- wire _0072_;
- wire _0073_;
- wire _0074_;
- wire _0075_;
- wire _0076_;
- wire _0077_;
- wire _0078_;
- wire _0079_;
- wire _0080_;
- wire _0081_;
- wire [63:0] _0082_;
- wire [63:0] _0083_;
- wire _0084_;
- wire _0085_;
- wire _0086_;
- wire _0087_;
- wire [64:0] _0088_;
- wire [64:0] _0089_;
- wire _0090_;
- wire _0091_;
- wire _0092_;
- wire [190:0] _0093_;
- wire _0094_;
- wire _0095_;
- wire _0096_;
- wire _0097_;
- wire _0098_;
- wire _0099_;
- wire _0100_;
- wire _0101_;
- wire _0102_;
- wire [190:0] _0103_;
- wire _0104_;
- wire _0105_;
- wire _0106_;
- wire [31:0] _0107_;
- wire _0108_;
- wire _0109_;
- wire [31:0] _0110_;
- wire _0111_;
- wire _0112_;
- wire _0113_;
- wire _0114_;
- wire _0115_;
- wire _0116_;
- wire _0117_;
- wire _0118_;
- wire _0119_;
- wire _0120_;
- wire _0121_;
- wire _0122_;
- wire _0123_;
- wire _0124_;
- wire [4:0] _0125_;
- wire [4:0] _0126_;
- wire _0127_;
- wire [3:0] _0128_;
- wire _0129_;
- wire _0130_;
- wire _0131_;
- wire _0132_;
- wire _0133_;
- wire _0134_;
- wire _0135_;
- wire _0136_;
- wire [7:0] _0137_;
- wire [4:0] _0138_;
- wire _0139_;
- wire [127:0] _0140_;
- wire _0141_;
- wire [127:0] _0142_;
- wire [40:0] _0143_;
- wire _0144_;
- wire [127:0] _0145_;
- wire [72:0] _0146_;
- wire [40:0] _0147_;
- wire [76:0] _0148_;
- wire _0149_;
- wire _0150_;
- wire _0151_;
- wire _0152_;
- wire _0153_;
- wire _0154_;
- wire _0155_;
- wire _0156_;
- wire _0157_;
- wire _0158_;
- wire _0159_;
- wire _0160_;
- wire [63:0] _0161_;
- wire [63:0] _0162_;
- wire _0163_;
- wire _0164_;
- wire [63:0] _0165_;
- wire [5:0] _0166_;
- wire [63:0] _0167_;
- wire _0168_;
- wire [31:0] _0169_;
- wire _0170_;
- wire _0171_;
- wire _0172_;
- wire _0173_;
- wire _0174_;
- wire _0175_;
- wire _0176_;
- wire _0177_;
- wire [31:0] _0178_;
- wire _0179_;
- wire [63:0] _0180_;
- wire [63:0] _0181_;
- wire _0182_;
- wire [63:0] _0183_;
- wire _0184_;
- wire _0185_;
- wire _0186_;
- wire _0187_;
- wire [63:0] _0188_;
- wire [5:0] _0189_;
- wire [63:0] _0190_;
- wire _0191_;
- wire [31:0] _0192_;
- wire _0193_;
- wire _0194_;
- wire _0195_;
- wire _0196_;
- wire _0197_;
- wire _0198_;
- wire _0199_;
- wire _0200_;
- wire [31:0] _0201_;
- wire _0202_;
- wire _0203_;
- wire [63:0] _0204_;
- wire _0205_;
- wire _0206_;
- wire _0207_;
- wire [1:0] _0208_;
- wire _0209_;
- wire _0210_;
- wire _0211_;
- wire [7:0] _0212_;
- wire _0213_;
- wire [7:0] _0214_;
- wire _0215_;
- wire [7:0] _0216_;
- wire _0217_;
- wire [7:0] _0218_;
- wire _0219_;
- wire [7:0] _0220_;
- wire _0221_;
- wire [7:0] _0222_;
- wire _0223_;
- wire [7:0] _0224_;
- wire _0225_;
- wire [7:0] _0226_;
- wire _0227_;
- wire _0228_;
- wire _0229_;
- wire _0230_;
- wire _0231_;
- wire _0232_;
- wire _0233_;
- wire [15:0] _0234_;
- wire _0235_;
- wire [7:0] _0236_;
- wire _0237_;
- wire [31:0] _0238_;
- wire [63:0] _0239_;
- wire _0240_;
- wire _0241_;
- wire _0242_;
- wire _0243_;
- wire _0244_;
- wire _0245_;
- wire _0246_;
- wire _0247_;
- wire _0248_;
- wire _0249_;
- wire [7:0] _0250_;
- wire _0251_;
- wire [3:0] _0252_;
- wire _0253_;
- wire [3:0] _0254_;
- wire _0255_;
- wire [3:0] _0256_;
- wire _0257_;
- wire [3:0] _0258_;
- wire _0259_;
- wire [3:0] _0260_;
- wire _0261_;
- wire [3:0] _0262_;
- wire _0263_;
- wire [3:0] _0264_;
- wire _0265_;
- wire [3:0] _0266_;
- wire [31:0] _0267_;
- wire [31:0] _0268_;
- wire [31:0] _0269_;
- wire [31:0] _0270_;
- wire [31:0] _0271_;
- wire [31:0] _0272_;
- wire _0273_;
- wire _0274_;
- wire _0275_;
- wire _0276_;
- wire _0277_;
- wire _0278_;
- wire _0279_;
- wire _0280_;
- wire [7:0] _0281_;
- wire _0282_;
- wire _0283_;
- wire _0284_;
- wire _0285_;
- wire _0286_;
- wire _0287_;
- wire _0288_;
- wire _0289_;
- wire _0290_;
- wire _0291_;
- wire _0292_;
- wire _0293_;
- wire _0294_;
- wire _0295_;
- wire _0296_;
- wire _0297_;
- wire _0298_;
- wire _0299_;
- wire _0300_;
- wire _0301_;
- wire _0302_;
- wire _0303_;
- wire _0304_;
- wire _0305_;
- wire _0306_;
- wire _0307_;
- wire _0308_;
- wire _0309_;
- wire _0310_;
- wire _0311_;
- wire _0312_;
- wire _0313_;
- wire _0314_;
- wire _0315_;
- wire _0316_;
- wire _0317_;
- wire _0318_;
- wire _0319_;
- wire _0320_;
- wire _0321_;
- wire _0322_;
- wire _0323_;
- wire _0324_;
- wire _0325_;
- wire _0326_;
- wire _0327_;
- wire _0328_;
- wire _0329_;
- wire _0330_;
- wire _0331_;
- wire _0332_;
- wire _0333_;
- wire _0334_;
- wire _0335_;
- wire _0336_;
- wire _0337_;
- wire _0338_;
- wire _0339_;
- wire _0340_;
- wire _0341_;
- wire _0342_;
- wire _0343_;
- wire _0344_;
- wire _0345_;
- wire [40:0] _0346_;
- wire _0347_;
- wire _0348_;
- wire _0349_;
- wire [45:0] _0350_;
- wire _0351_;
- wire _0352_;
- wire _0353_;
- wire [63:0] _0354_;
- wire _0355_;
- wire [63:0] _0356_;
- wire _0357_;
- wire _0358_;
- wire _0359_;
- wire _0360_;
- wire _0361_;
- wire [2:0] _0362_;
- wire _0363_;
- wire _0364_;
- wire [2:0] _0365_;
- wire _0366_;
- wire _0367_;
- wire _0368_;
- wire _0369_;
- wire _0370_;
- wire _0371_;
- wire _0372_;
- wire _0373_;
- wire [2:0] _0374_;
- wire _0375_;
- wire _0376_;
- wire _0377_;
- wire _0378_;
- wire _0379_;
- wire _0380_;
- wire _0381_;
- wire _0382_;
- wire [2:0] _0383_;
- wire _0384_;
- wire _0385_;
- wire _0386_;
- wire _0387_;
- wire _0388_;
- wire _0389_;
- wire _0390_;
- wire _0391_;
- wire [2:0] _0392_;
- wire _0393_;
- wire _0394_;
- wire _0395_;
- wire _0396_;
- wire _0397_;
- wire _0398_;
- wire _0399_;
- wire _0400_;
- wire [2:0] _0401_;
- wire _0402_;
- wire _0403_;
- wire _0404_;
- wire _0405_;
- wire _0406_;
- wire _0407_;
- wire _0408_;
- wire _0409_;
- wire [2:0] _0410_;
- wire _0411_;
- wire _0412_;
- wire _0413_;
- wire _0414_;
- wire _0415_;
- wire _0416_;
- wire _0417_;
- wire [2:0] _0418_;
- wire _0419_;
- wire _0420_;
- wire _0421_;
- wire _0422_;
- wire [2:0] _0423_;
- wire _0424_;
- wire [3:0] _0425_;
- wire _0426_;
- wire [3:0] _0427_;
- wire _0428_;
- wire [3:0] _0429_;
- wire _0430_;
- wire [3:0] _0431_;
- wire _0432_;
- wire [3:0] _0433_;
- wire _0434_;
- wire [3:0] _0435_;
- wire _0436_;
- wire [3:0] _0437_;
- wire _0438_;
- wire [3:0] _0439_;
- wire [63:0] _0440_;
- wire _0441_;
- wire _0442_;
- wire _0443_;
- wire _0444_;
- wire [2:0] _0445_;
- wire _0446_;
- wire _0447_;
- wire [2:0] _0448_;
- wire _0449_;
- wire _0450_;
- wire _0451_;
- wire _0452_;
- wire _0453_;
- wire _0454_;
- wire _0455_;
- wire _0456_;
- wire [2:0] _0457_;
- wire _0458_;
- wire _0459_;
- wire _0460_;
- wire _0461_;
- wire _0462_;
- wire _0463_;
- wire _0464_;
- wire _0465_;
- wire [2:0] _0466_;
- wire _0467_;
- wire _0468_;
- wire _0469_;
- wire _0470_;
- wire _0471_;
- wire _0472_;
- wire _0473_;
- wire _0474_;
- wire [2:0] _0475_;
- wire _0476_;
- wire _0477_;
- wire _0478_;
- wire _0479_;
- wire _0480_;
- wire _0481_;
- wire _0482_;
- wire _0483_;
- wire [2:0] _0484_;
- wire _0485_;
- wire _0486_;
- wire _0487_;
- wire _0488_;
- wire _0489_;
- wire _0490_;
- wire _0491_;
- wire _0492_;
- wire [2:0] _0493_;
- wire _0494_;
- wire _0495_;
- wire _0496_;
- wire _0497_;
- wire _0498_;
- wire _0499_;
- wire _0500_;
- wire [2:0] _0501_;
- wire _0502_;
- wire _0503_;
- wire _0504_;
- wire _0505_;
- wire [2:0] _0506_;
- wire _0507_;
- wire _0508_;
- wire _0509_;
- wire _0510_;
- wire _0511_;
- wire _0512_;
- wire _0513_;
- wire _0514_;
- wire [7:0] _0515_;
- wire [7:0] _0516_;
- wire _0517_;
- wire [1:0] _0518_;
- wire _0519_;
- wire _0520_;
- wire [9:0] _0521_;
- wire [1:0] _0522_;
- wire _0523_;
- wire [43:0] _0524_;
- wire [2:0] _0525_;
- wire _0526_;
- wire _0527_;
- wire [5:0] _0528_;
- wire _0529_;
- wire _0530_;
- wire [63:0] _0531_;
- wire _0532_;
- wire [63:0] _0533_;
- wire [5:0] _0534_;
- wire [63:0] _0535_;
- wire _0536_;
- wire _0537_;
- wire _0538_;
- wire _0539_;
- wire _0540_;
- wire [190:0] _0541_;
- wire _0542_;
- wire _0543_;
- wire _0544_;
- wire _0545_;
- wire _0546_;
- wire _0547_;
- wire _0548_;
- wire _0549_;
- wire _0550_;
- wire _0551_;
- wire _0552_;
- wire _0553_;
- wire _0554_;
- wire _0555_;
- wire _0556_;
- wire _0557_;
- wire _0558_;
- wire _0559_;
- wire _0560_;
- wire _0561_;
- wire _0562_;
- wire _0563_;
- wire _0564_;
- wire _0565_;
- wire _0566_;
- wire _0567_;
- wire _0568_;
- wire [63:0] _0569_;
- wire _0570_;
- wire _0571_;
- wire [63:0] _0572_;
- wire _0573_;
- wire _0574_;
- wire [1:0] _0575_;
- wire [1:0] _0576_;
- wire [5:0] _0577_;
- wire _0578_;
- wire [1:0] _0579_;
- wire _0580_;
- wire [5:0] _0581_;
- wire [4:0] _0582_;
- wire [3:0] _0583_;
- wire [28:0] _0584_;
- wire _0585_;
- wire [2:0] _0586_;
- wire [127:0] _0587_;
- wire _0588_;
- wire _0589_;
- wire _0590_;
- wire [1:0] _0591_;
- wire [5:0] _0592_;
- wire [63:0] _0593_;
- wire _0594_;
- wire [7:0] _0595_;
- wire [31:0] _0596_;
- wire [5:0] _0597_;
- wire [70:0] _0598_;
- wire _0599_;
- wire _0600_;
- wire _0601_;
- wire [7:0] _0602_;
- wire [7:0] _0603_;
- wire [15:0] _0604_;
- wire [31:0] _0605_;
- wire _0606_;
- wire _0607_;
- wire _0608_;
- wire _0609_;
- wire _0610_;
- wire _0611_;
- wire _0612_;
- wire [64:0] _0613_;
- wire _0614_;
- wire _0615_;
- wire _0616_;
- wire _0617_;
- wire _0618_;
- wire _0619_;
- wire [63:0] _0620_;
- wire _0621_;
- wire _0622_;
- wire [2:0] _0623_;
- wire _0624_;
- wire [1:0] _0625_;
- wire [5:0] _0626_;
- wire [5:0] _0627_;
- wire [1:0] _0628_;
- wire [63:0] _0629_;
- wire _0630_;
- wire _0631_;
- wire _0632_;
- wire _0633_;
- wire [5:0] _0634_;
- wire [1:0] _0635_;
- wire [63:0] _0636_;
- wire _0637_;
- wire _0638_;
- wire [1:0] _0639_;
- wire [5:0] _0640_;
- wire _0641_;
- wire [4:0] _0642_;
- wire [1:0] _0643_;
- wire [63:0] _0644_;
- wire _0645_;
- wire _0646_;
- wire _0647_;
- wire _0648_;
- wire [5:0] _0649_;
- wire [5:0] _0650_;
- wire [1:0] _0651_;
- wire [63:0] _0652_;
- wire _0653_;
- wire _0654_;
- wire _0655_;
- wire _0656_;
- wire [5:0] _0657_;
- wire [5:0] _0658_;
- wire [1:0] _0659_;
- wire [63:0] _0660_;
- wire [63:0] _0661_;
- wire _0662_;
- wire _0663_;
- wire _0664_;
- wire [66:0] _0665_;
- wire _0666_;
- wire _0667_;
- wire [127:0] _0668_;
- wire [127:0] _0669_;
- wire _0670_;
- wire _0671_;
- wire [1:0] _0672_;
- wire _0673_;
- wire [5:0] _0674_;
- wire [104:0] _0675_;
- wire [5:0] _0676_;
- wire [135:0] _0677_;
- wire [1:0] _0678_;
- wire [12:0] _0679_;
- wire [63:0] _0680_;
- wire [63:0] _0681_;
- wire _0682_;
- wire _0683_;
- wire _0684_;
- wire _0685_;
- wire _0686_;
- wire _0687_;
- wire [66:0] _0688_;
- wire _0689_;
- wire _0690_;
- wire [127:0] _0691_;
- wire [127:0] _0692_;
- wire _0693_;
- wire _0694_;
- wire [334:0] _0695_;
- wire [63:0] _0696_;
- wire _0697_;
- wire _0698_;
- wire _0699_;
- wire _0700_;
- wire _0701_;
- wire _0702_;
- wire [66:0] _0703_;
- wire _0704_;
- wire _0705_;
- wire [127:0] _0706_;
- wire [63:0] _0707_;
- wire [63:0] _0708_;
- wire _0709_;
- wire _0710_;
- wire [334:0] _0711_;
- wire [63:0] _0712_;
- wire _0713_;
- wire _0714_;
- wire _0715_;
- wire _0716_;
- wire _0717_;
- wire _0718_;
- wire [66:0] _0719_;
- wire _0720_;
- wire _0721_;
- wire [63:0] _0722_;
- wire [1:0] _0723_;
- wire [1:0] _0724_;
- wire [1:0] _0725_;
- wire [7:0] _0726_;
- wire [1:0] _0727_;
- wire [46:0] _0728_;
- wire _0729_;
- wire [127:0] _0730_;
- wire _0731_;
- wire _0732_;
- wire _0733_;
- wire [118:0] _0734_;
- wire [70:0] _0735_;
- wire [143:0] _0736_;
- wire [63:0] _0737_;
- wire _0738_;
- wire _0739_;
- wire _0740_;
- wire _0741_;
- wire _0742_;
- wire [127:0] _0743_;
- wire _0744_;
- wire [63:0] _0745_;
- wire _0746_;
- wire _0747_;
- wire _0748_;
- wire _0749_;
- wire _0750_;
- wire _0751_;
- wire [63:0] _0752_;
- wire _0753_;
- wire [63:0] _0754_;
- wire [1:0] _0755_;
- wire _0756_;
- wire _0757_;
- wire [63:0] _0758_;
- wire [1:0] _0759_;
- wire _0760_;
- wire _0761_;
- wire [128:0] _0762_;
- wire _0763_;
- wire [70:0] _0764_;
- wire _0765_;
- wire _0766_;
- wire _0767_;
- wire _0768_;
- wire _0769_;
- wire _0770_;
- wire _0771_;
- wire [61:0] _0772_;
- wire _0773_;
- wire _0774_;
- wire _0775_;
- wire _0776_;
- wire _0777_;
- wire _0778_;
- wire _0779_;
- wire _0780_;
- wire _0781_;
- wire _0782_;
- wire _0783_;
- wire _0784_;
- wire _0785_;
- wire _0786_;
- wire _0787_;
- wire _0788_;
- wire _0789_;
- wire _0790_;
- wire _0791_;
- wire _0792_;
- wire _0793_;
- wire _0794_;
- wire _0795_;
- wire _0796_;
- wire _0797_;
- wire _0798_;
- wire _0799_;
- wire _0800_;
- wire _0801_;
- wire _0802_;
- wire _0803_;
- wire _0804_;
- wire _0805_;
- wire _0806_;
- wire _0807_;
- wire _0808_;
- wire _0809_;
- wire _0810_;
- wire _0811_;
- wire _0812_;
- wire _0813_;
- wire _0814_;
- wire _0815_;
- wire _0816_;
- wire _0817_;
- wire _0818_;
- wire _0819_;
- wire _0820_;
- wire _0821_;
- wire _0822_;
- wire _0823_;
- wire _0824_;
- wire _0825_;
- wire _0826_;
- wire _0827_;
- wire _0828_;
- wire _0829_;
- wire _0830_;
- wire _0831_;
- wire _0832_;
- wire _0833_;
- wire _0834_;
- wire _0835_;
- wire _0836_;
- wire _0837_;
- wire _0838_;
- wire _0839_;
- wire _0840_;
- wire _0841_;
- wire _0842_;
- wire _0843_;
- wire _0844_;
- wire _0845_;
- wire _0846_;
- wire _0847_;
- wire _0848_;
- wire _0849_;
- wire _0850_;
- wire _0851_;
- wire _0852_;
- wire _0853_;
- wire _0854_;
- wire _0855_;
- wire _0856_;
- wire _0857_;
- wire _0858_;
- wire _0859_;
- wire _0860_;
- wire _0861_;
- wire _0862_;
- wire _0863_;
- wire _0864_;
- wire _0865_;
- wire _0866_;
- wire _0867_;
- wire _0868_;
- wire _0869_;
- wire _0870_;
- wire _0871_;
- wire _0872_;
- wire _0873_;
- wire _0874_;
- wire _0875_;
- wire _0876_;
- wire _0877_;
- wire _0878_;
- wire _0879_;
- wire _0880_;
- wire _0881_;
- wire _0882_;
- wire _0883_;
- wire _0884_;
- wire _0885_;
- wire _0886_;
- wire _0887_;
- wire _0888_;
- wire _0889_;
- wire _0890_;
- wire _0891_;
- wire _0892_;
- wire _0893_;
- wire _0894_;
- wire _0895_;
- wire _0896_;
- wire _0897_;
- wire _0898_;
- wire _0899_;
- wire _0900_;
- wire _0901_;
- wire _0902_;
- wire _0903_;
- wire _0904_;
- wire _0905_;
- wire _0906_;
- wire _0907_;
- wire _0908_;
- wire _0909_;
- wire _0910_;
- wire _0911_;
- wire _0912_;
- wire _0913_;
- wire _0914_;
- wire _0915_;
- wire _0916_;
- wire _0917_;
- wire _0918_;
- wire _0919_;
- wire _0920_;
- wire _0921_;
- wire _0922_;
- wire _0923_;
- wire _0924_;
- wire _0925_;
- wire _0926_;
- wire _0927_;
- wire _0928_;
- wire _0929_;
- wire _0930_;
- wire _0931_;
- wire _0932_;
- wire _0933_;
- wire _0934_;
- wire _0935_;
- wire _0936_;
- wire _0937_;
- wire [63:0] a_in;
- wire [63:0] b_in;
- wire [63:0] c_in;
- input clk;
- wire [63:0] countzero_result;
- reg [320:0] ctrl = 321'h000000000000000000000000000000000000000000000000000000000000000000000000000000000;
- output [63:0] dbg_msr_out;
- wire [65:0] divider_to_x;
- input [374:0] e_in;
- output [190:0] e_out;
- input ext_irq_in;
- output [66:0] f_out;
- output flush_out;
- output icache_inval;
- input [6:0] l_in;
- output [321:0] l_out;
- wire [63:0] logical_result;
- wire [65:0] multiply_to_x;
- wire [63:0] parity_result;
- wire [63:0] popcnt_result;
- reg [334:0] r;
- wire right_shift;
- wire rot_clear_left;
- wire rot_clear_right;
- wire rot_sign_ext;
- wire rotator_carry;
- wire [63:0] rotator_result;
- input rst;
- output stall_out;
- output terminate_out;
- reg [0:0] \$mem$\7795 [61:0];
- assign _0834_ = _0169_[0] ? e_in[287] : e_in[286];
- assign _0835_ = _0169_[0] ? e_in[291] : e_in[290];
- assign _0836_ = _0169_[0] ? e_in[295] : e_in[294];
- assign _0837_ = _0169_[0] ? e_in[299] : e_in[298];
- assign _0838_ = _0169_[0] ? e_in[303] : e_in[302];
- assign _0839_ = _0169_[0] ? e_in[307] : e_in[306];
- assign _0840_ = _0169_[0] ? e_in[311] : e_in[310];
- assign _0841_ = _0169_[0] ? e_in[315] : e_in[314];
- assign _0842_ = _0169_[2] ? _0775_ : _0774_;
- assign _0843_ = _0169_[2] ? _0779_ : _0778_;
- assign _0844_ = _0192_[0] ? e_in[287] : e_in[286];
- assign _0845_ = _0192_[0] ? e_in[291] : e_in[290];
- assign _0846_ = _0192_[0] ? e_in[295] : e_in[294];
- assign _0847_ = _0192_[0] ? e_in[299] : e_in[298];
- assign _0848_ = _0192_[0] ? e_in[303] : e_in[302];
- assign _0849_ = _0192_[0] ? e_in[307] : e_in[306];
- assign _0850_ = _0192_[0] ? e_in[311] : e_in[310];
- assign _0851_ = _0192_[0] ? e_in[315] : e_in[314];
- assign _0852_ = _0192_[2] ? _0786_ : _0785_;
- assign _0853_ = _0192_[2] ? _0790_ : _0789_;
- assign _0854_ = _0238_[0] ? e_in[287] : e_in[286];
- assign _0855_ = _0238_[0] ? e_in[291] : e_in[290];
- assign _0856_ = _0238_[0] ? e_in[295] : e_in[294];
- assign _0857_ = _0238_[0] ? e_in[299] : e_in[298];
- assign _0858_ = _0238_[0] ? e_in[303] : e_in[302];
- assign _0859_ = _0238_[0] ? e_in[307] : e_in[306];
- assign _0860_ = _0238_[0] ? e_in[311] : e_in[310];
- assign _0861_ = _0238_[0] ? e_in[315] : e_in[314];
- assign _0862_ = _0238_[2] ? _0797_ : _0796_;
- assign _0863_ = _0238_[2] ? _0801_ : _0800_;
- assign _0864_ = _0268_[0] ? e_in[287] : e_in[286];
- assign _0865_ = _0268_[0] ? e_in[291] : e_in[290];
- assign _0866_ = _0268_[0] ? e_in[295] : e_in[294];
- assign _0867_ = _0268_[0] ? e_in[299] : e_in[298];
- assign _0868_ = _0268_[0] ? e_in[303] : e_in[302];
- assign _0869_ = _0268_[0] ? e_in[307] : e_in[306];
- assign _0870_ = _0268_[0] ? e_in[311] : e_in[310];
- assign _0871_ = _0268_[0] ? e_in[315] : e_in[314];
- assign _0872_ = _0268_[2] ? _0808_ : _0807_;
- assign _0873_ = _0268_[2] ? _0812_ : _0811_;
- assign _0874_ = _0269_[0] ? e_in[287] : e_in[286];
- assign _0875_ = _0269_[0] ? e_in[291] : e_in[290];
- assign _0876_ = _0269_[0] ? e_in[295] : e_in[294];
- assign _0877_ = _0269_[0] ? e_in[299] : e_in[298];
- assign _0878_ = _0269_[0] ? e_in[303] : e_in[302];
- assign _0879_ = _0269_[0] ? e_in[307] : e_in[306];
- assign _0880_ = _0269_[0] ? e_in[311] : e_in[310];
- assign _0881_ = _0269_[0] ? e_in[315] : e_in[314];
- assign _0882_ = _0269_[2] ? _0819_ : _0818_;
- assign _0883_ = _0269_[2] ? _0823_ : _0822_;
- assign _0884_ = _0270_[0] ? e_in[337] : e_in[336];
- assign _0885_ = _0270_[0] ? e_in[341] : e_in[340];
- assign _0886_ = _0169_[0] ? e_in[289] : e_in[288];
- assign _0887_ = _0169_[0] ? e_in[293] : e_in[292];
- assign _0888_ = _0169_[0] ? e_in[297] : e_in[296];
- assign _0889_ = _0169_[0] ? e_in[301] : e_in[300];
- assign _0890_ = _0169_[0] ? e_in[305] : e_in[304];
- assign _0891_ = _0169_[0] ? e_in[309] : e_in[308];
- assign _0892_ = _0169_[0] ? e_in[313] : e_in[312];
- assign _0893_ = _0169_[0] ? e_in[317] : e_in[316];
- assign _0894_ = _0169_[2] ? _0777_ : _0776_;
- assign _0895_ = _0169_[2] ? _0781_ : _0780_;
- assign _0896_ = _0192_[0] ? e_in[289] : e_in[288];
- assign _0897_ = _0192_[0] ? e_in[293] : e_in[292];
- assign _0898_ = _0192_[0] ? e_in[297] : e_in[296];
- assign _0899_ = _0192_[0] ? e_in[301] : e_in[300];
- assign _0900_ = _0192_[0] ? e_in[305] : e_in[304];
- assign _0901_ = _0192_[0] ? e_in[309] : e_in[308];
- assign _0902_ = _0192_[0] ? e_in[313] : e_in[312];
- assign _0903_ = _0192_[0] ? e_in[317] : e_in[316];
- assign _0904_ = _0192_[2] ? _0788_ : _0787_;
- assign _0905_ = _0192_[2] ? _0792_ : _0791_;
- assign _0906_ = _0238_[0] ? e_in[289] : e_in[288];
- assign _0907_ = _0238_[0] ? e_in[293] : e_in[292];
- assign _0908_ = _0238_[0] ? e_in[297] : e_in[296];
- assign _0909_ = _0238_[0] ? e_in[301] : e_in[300];
- assign _0910_ = _0238_[0] ? e_in[305] : e_in[304];
- assign _0911_ = _0238_[0] ? e_in[309] : e_in[308];
- assign _0912_ = _0238_[0] ? e_in[313] : e_in[312];
- assign _0913_ = _0238_[0] ? e_in[317] : e_in[316];
- assign _0914_ = _0238_[2] ? _0799_ : _0798_;
- assign _0915_ = _0238_[2] ? _0803_ : _0802_;
- assign _0916_ = _0268_[0] ? e_in[289] : e_in[288];
- assign _0917_ = _0268_[0] ? e_in[293] : e_in[292];
- assign _0918_ = _0268_[0] ? e_in[297] : e_in[296];
- assign _0919_ = _0268_[0] ? e_in[301] : e_in[300];
- assign _0920_ = _0268_[0] ? e_in[305] : e_in[304];
- assign _0921_ = _0268_[0] ? e_in[309] : e_in[308];
- assign _0922_ = _0268_[0] ? e_in[313] : e_in[312];
- assign _0923_ = _0268_[0] ? e_in[317] : e_in[316];
- assign _0924_ = _0268_[2] ? _0810_ : _0809_;
- assign _0925_ = _0268_[2] ? _0814_ : _0813_;
- assign _0926_ = _0269_[0] ? e_in[289] : e_in[288];
- assign _0927_ = _0269_[0] ? e_in[293] : e_in[292];
- assign _0928_ = _0269_[0] ? e_in[297] : e_in[296];
- assign _0929_ = _0269_[0] ? e_in[301] : e_in[300];
- assign _0930_ = _0269_[0] ? e_in[305] : e_in[304];
- assign _0931_ = _0269_[0] ? e_in[309] : e_in[308];
- assign _0932_ = _0269_[0] ? e_in[313] : e_in[312];
- assign _0933_ = _0269_[0] ? e_in[317] : e_in[316];
- assign _0934_ = _0269_[2] ? _0821_ : _0820_;
- assign _0935_ = _0269_[2] ? _0825_ : _0824_;
- assign _0936_ = _0270_[0] ? e_in[339] : e_in[338];
- assign _0937_ = _0270_[0] ? e_in[343] : e_in[342];
- assign _0774_ = _0169_[1] ? _0886_ : _0834_;
- assign _0775_ = _0169_[1] ? _0887_ : _0835_;
- assign _0776_ = _0169_[1] ? _0888_ : _0836_;
- assign _0777_ = _0169_[1] ? _0889_ : _0837_;
- assign _0778_ = _0169_[1] ? _0890_ : _0838_;
- assign _0779_ = _0169_[1] ? _0891_ : _0839_;
- assign _0780_ = _0169_[1] ? _0892_ : _0840_;
- assign _0781_ = _0169_[1] ? _0893_ : _0841_;
- assign _0782_ = _0169_[3] ? _0894_ : _0842_;
- assign _0783_ = _0169_[3] ? _0895_ : _0843_;
- assign _0785_ = _0192_[1] ? _0896_ : _0844_;
- assign _0786_ = _0192_[1] ? _0897_ : _0845_;
- assign _0787_ = _0192_[1] ? _0898_ : _0846_;
- assign _0788_ = _0192_[1] ? _0899_ : _0847_;
- assign _0789_ = _0192_[1] ? _0900_ : _0848_;
- assign _0790_ = _0192_[1] ? _0901_ : _0849_;
- assign _0791_ = _0192_[1] ? _0902_ : _0850_;
- assign _0792_ = _0192_[1] ? _0903_ : _0851_;
- assign _0793_ = _0192_[3] ? _0904_ : _0852_;
- assign _0794_ = _0192_[3] ? _0905_ : _0853_;
- assign _0796_ = _0238_[1] ? _0906_ : _0854_;
- assign _0797_ = _0238_[1] ? _0907_ : _0855_;
- assign _0798_ = _0238_[1] ? _0908_ : _0856_;
- assign _0799_ = _0238_[1] ? _0909_ : _0857_;
- assign _0800_ = _0238_[1] ? _0910_ : _0858_;
- assign _0801_ = _0238_[1] ? _0911_ : _0859_;
- assign _0802_ = _0238_[1] ? _0912_ : _0860_;
- assign _0803_ = _0238_[1] ? _0913_ : _0861_;
- assign _0804_ = _0238_[3] ? _0914_ : _0862_;
- assign _0805_ = _0238_[3] ? _0915_ : _0863_;
- assign _0807_ = _0268_[1] ? _0916_ : _0864_;
- assign _0808_ = _0268_[1] ? _0917_ : _0865_;
- assign _0809_ = _0268_[1] ? _0918_ : _0866_;
- assign _0810_ = _0268_[1] ? _0919_ : _0867_;
- assign _0811_ = _0268_[1] ? _0920_ : _0868_;
- assign _0812_ = _0268_[1] ? _0921_ : _0869_;
- assign _0813_ = _0268_[1] ? _0922_ : _0870_;
- assign _0814_ = _0268_[1] ? _0923_ : _0871_;
- assign _0815_ = _0268_[3] ? _0924_ : _0872_;
- assign _0816_ = _0268_[3] ? _0925_ : _0873_;
- assign _0818_ = _0269_[1] ? _0926_ : _0874_;
- assign _0819_ = _0269_[1] ? _0927_ : _0875_;
- assign _0820_ = _0269_[1] ? _0928_ : _0876_;
- assign _0821_ = _0269_[1] ? _0929_ : _0877_;
- assign _0822_ = _0269_[1] ? _0930_ : _0878_;
- assign _0823_ = _0269_[1] ? _0931_ : _0879_;
- assign _0824_ = _0269_[1] ? _0932_ : _0880_;
- assign _0825_ = _0269_[1] ? _0933_ : _0881_;
- assign _0826_ = _0269_[3] ? _0934_ : _0882_;
- assign _0827_ = _0269_[3] ? _0935_ : _0883_;
- assign _0829_ = _0270_[1] ? _0936_ : _0884_;
- assign _0830_ = _0270_[1] ? _0937_ : _0885_;
- assign _0000_ = 1'h1 & e_in[283];
- assign a_in = _0000_ ? r[72:9] : e_in[154:91];
- assign _0001_ = 1'h1 & e_in[284];
- assign b_in = _0001_ ? r[72:9] : e_in[218:155];
- assign _0002_ = 1'h1 & e_in[285];
- assign c_in = _0002_ ? r[72:9] : e_in[282:219];
- assign _0003_ = r[191] & e_in[0];
- assign _0004_ = ~ _0003_;
- assign _0005_ = ~ _0011_;
- assign _0006_ = _0005_ | _0004_;
- assign _0007_ = rst ? 335'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { _0736_, _0764_, _0734_[118:72], _0737_, _0734_[7:2], _0738_, _0734_[0], _0763_ };
- assign _0008_ = rst ? ctrl[127:0] : { _0722_, _0039_ };
- assign _0009_ = rst ? 65'h08000000000000001 : { _0762_[0], _0729_, _0728_, _0727_, _0726_, _0725_, _0724_, _0723_ };
- assign _0010_ = rst ? ctrl[320:193] : _0762_[128:1];
- assign _0011_ = rst ? 1'h0 : 1'h1;
- always @(posedge clk)
- _0012_ <= _0006_;
- always @(posedge clk)
- r <= _0007_;
- always @(posedge clk)
- ctrl <= { _0010_, _0009_, _0008_ };
- assign _0013_ = r[114] ? r[119:115] : e_in[322:318];
- assign _0014_ = e_in[334] ? { b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31:0], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31:0] } : { 33'h000000000, b_in[31:0], 33'h000000000, a_in[31:0] };
- assign _0015_ = e_in[334] ? { b_in[63], b_in, a_in[63], a_in } : { 1'h0, b_in, 1'h0, a_in };
- assign _0016_ = e_in[333] ? _0014_ : _0015_;
- assign _0017_ = e_in[333] ? a_in[31] : a_in[63];
- assign _0018_ = e_in[333] ? b_in[31] : b_in[63];
- assign _0019_ = e_in[334] ? _0017_ : 1'h0;
- assign _0020_ = e_in[334] ? _0018_ : 1'h0;
- assign _0021_ = ~ _0019_;
- assign _0022_ = - $signed(a_in);
- assign _0023_ = _0021_ ? a_in : _0022_;
- assign _0024_ = ~ _0020_;
- assign _0025_ = - $signed(b_in);
- assign _0026_ = _0024_ ? b_in : _0025_;
- assign _0027_ = e_in[8:3] == 6'h27;
- assign _0028_ = _0027_ ? 1'h1 : 1'h0;
- assign _0029_ = ~ _0028_;
- assign _0030_ = _0020_ & _0029_;
- assign _0031_ = _0019_ ^ _0030_;
- assign _0032_ = ~ e_in[333];
- assign _0033_ = e_in[8:3] == 6'h16;
- assign _0034_ = _0033_ ? 1'h1 : 1'h0;
- assign _0035_ = e_in[8:3] == 6'h16;
- assign _0036_ = _0035_ ? { _0023_[31:0], 32'h00000000 } : { 32'h00000000, _0023_[31:0] };
- assign _0037_ = _0032_ ? { _0026_, _0023_ } : { 32'h00000000, _0026_[31:0], _0036_ };
- assign _0038_ = _0032_ ? _0034_ : 1'h0;
- assign _0039_ = ctrl[63:0] + 64'h0000000000000001;
- assign _0040_ = ctrl[127:64] - 64'h0000000000000001;
- assign _0041_ = ext_irq_in ? 64'h0000000000000500 : ctrl[256:193];
- assign _0042_ = ext_irq_in ? 1'h1 : 1'h0;
- assign _0043_ = ctrl[127] ? 64'h0000000000000900 : _0041_;
- assign _0044_ = ctrl[127] ? 1'h1 : _0042_;
- assign _0045_ = ctrl[143] ? _0043_ : ctrl[256:193];
- assign _0046_ = ctrl[143] ? _0044_ : 1'h0;
- assign _0047_ = ~ ctrl[142];
- assign _0048_ = e_in[72:9] + 64'h0000000000000004;
- assign _0049_ = e_in[8:3] == 6'h38;
- assign right_shift = _0049_ ? 1'h1 : 1'h0;
- assign _0050_ = e_in[8:3] == 6'h32;
- assign _0051_ = e_in[8:3] == 6'h33;
- assign _0052_ = _0050_ | _0051_;
- assign rot_clear_left = _0052_ ? 1'h1 : 1'h0;
- assign _0053_ = e_in[8:3] == 6'h32;
- assign _0054_ = e_in[8:3] == 6'h34;
- assign _0055_ = _0053_ | _0054_;
- assign rot_clear_right = _0055_ ? 1'h1 : 1'h0;
- assign _0056_ = e_in[8:3] == 6'h18;
- assign rot_sign_ext = _0056_ ? 1'h1 : 1'h0;
- assign _0057_ = ctrl[192] == 1'h1;
- assign _0058_ = _0046_ & e_in[0];
- assign _0059_ = e_in[0] & ctrl[142];
- assign _0060_ = 6'h3d - e_in[8:3];
- assign _0061_ = _0773_ == 1'h1;
- assign _0062_ = e_in[8:3] == 6'h26;
- assign _0063_ = e_in[8:3] == 6'h2a;
- assign _0064_ = _0062_ | _0063_;
- assign _0065_ = _0064_ ? e_in[355] : 1'h0;
- assign _0066_ = _0061_ ? 1'h1 : _0065_;
- assign _0067_ = _0059_ & _0066_;
- assign _0068_ = e_in[2:1] == 2'h1;
- assign _0069_ = e_in[0] & _0068_;
- assign _0070_ = e_in[8:3] == 6'h00;
- assign _0071_ = e_in[336] ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h00, ctrl[143:128], 64'h0000000000000c00 } : { ctrl[320:257], _0045_ };
- assign _0072_ = e_in[336] ? 1'h1 : 1'h0;
- assign _0073_ = e_in[336] ? 1'h1 : 1'h0;
- assign _0074_ = e_in[336] ? 1'h0 : 1'h1;
- assign _0075_ = e_in[8:3] == 6'h35;
- assign _0076_ = e_in[345:336] == 10'h100;
- assign _0077_ = _0076_ ? 1'h1 : 1'h0;
- assign _0078_ = _0076_ ? 1'h0 : 1'h1;
- assign _0079_ = e_in[8:3] == 6'h04;
- assign _0080_ = e_in[8:3] == 6'h01;
- assign _0081_ = ~ e_in[326];
- assign _0082_ = ~ a_in;
- assign _0083_ = _0081_ ? a_in : _0082_;
- assign _0084_ = e_in[329:328] == 2'h0;
- assign _0085_ = e_in[329:328] == 2'h1;
- assign _0086_ = e_in[329:328] == 2'h2;
- function [0:0] \5155 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \5155 = b[0:0];
- 3'b?1?:
- \5155 = b[1:1];
- 3'b1??:
- \5155 = b[2:2];
- default:
- \5155 = a;
- endcase
- endfunction
- assign _0087_ = \5155 (1'hx, { 1'h1, _0013_[0], 1'h0 }, { _0086_, _0085_, _0084_ });
- assign _0088_ = { 1'h0, _0083_ } + { 1'h0, b_in };
- assign _0089_ = _0088_ + { 64'h0000000000000000, _0087_ };
- assign _0090_ = _0089_[32] ^ _0083_[32];
- assign _0091_ = _0090_ ^ b_in[32];
- assign _0092_ = e_in[8:3] == 6'h02;
- assign _0093_ = e_in[330] ? { e_in[72:9], 7'h44, _0013_[4:2], _0091_, _0089_[64], 106'h200000000000000000000000000, e_in[78:73], 3'h1 } : { e_in[72:9], 7'h44, _0013_, 106'h000000000000000000000000000, e_in[78:73], 3'h1 };
- assign _0094_ = _0089_[64] ^ _0089_[63];
- assign _0095_ = _0083_[63] ^ b_in[63];
- assign _0096_ = ~ _0095_;
- assign _0097_ = _0094_ & _0096_;
- assign _0098_ = _0091_ ^ _0089_[31];
- assign _0099_ = _0083_[31] ^ b_in[31];
- assign _0100_ = ~ _0099_;
- assign _0101_ = _0098_ & _0100_;
- assign _0102_ = _0097_ ? 1'h1 : _0093_[119];
- assign _0103_ = e_in[325] ? { _0093_[190:120], _0102_, _0101_, _0097_, _0093_[116:115], 1'h1, _0093_[113:0] } : _0093_;
- assign _0104_ = e_in[8:3] == 6'h09;
- assign _0105_ = ~ e_in[333];
- assign _0106_ = _0104_ ? e_in[356] : _0105_;
- assign _0107_ = a_in[31:0] ^ b_in[31:0];
- assign _0108_ = | _0107_;
- assign _0109_ = ~ _0108_;
- assign _0110_ = a_in[63:32] ^ b_in[63:32];
- assign _0111_ = | _0110_;
- assign _0112_ = ~ _0111_;
- assign _0113_ = ~ _0106_;
- assign _0114_ = _0113_ | _0112_;
- assign _0115_ = _0109_ & _0114_;
- assign _0116_ = _0106_ ? a_in[63] : a_in[31];
- assign _0117_ = _0106_ ? b_in[63] : b_in[31];
- assign _0118_ = _0116_ != _0117_;
- assign _0119_ = ~ _0106_;
- assign _0120_ = _0119_ & _0091_;
- assign _0121_ = _0106_ & _0089_[64];
- assign _0122_ = _0120_ | _0121_;
- assign _0123_ = ~ _0122_;
- assign _0124_ = ~ _0122_;
- assign _0125_ = _0118_ ? { _0116_, _0117_, 1'h0, _0117_, _0116_ } : { _0122_, _0123_, 1'h0, _0122_, _0124_ };
- assign _0126_ = _0115_ ? 5'h04 : _0125_;
- assign _0127_ = e_in[8:3] == 6'h09;
- assign _0128_ = e_in[334] ? { _0126_[4:2], _0013_[4] } : { _0126_[1:0], _0126_[2], _0013_[4] };
- assign _0129_ = e_in[360:358] == 3'h0;
- assign _0130_ = e_in[360:358] == 3'h1;
- assign _0131_ = e_in[360:358] == 3'h2;
- assign _0132_ = e_in[360:358] == 3'h3;
- assign _0133_ = e_in[360:358] == 3'h4;
- assign _0134_ = e_in[360:358] == 3'h5;
- assign _0135_ = e_in[360:358] == 3'h6;
- assign _0136_ = e_in[360:358] == 3'h7;
- function [7:0] \5353 ;
- input [7:0] a;
- input [63:0] b;
- input [7:0] s;
- (* parallel_case *)
- casez (s)
- 8'b???????1:
- \5353 = b[7:0];
- 8'b??????1?:
- \5353 = b[15:8];
- 8'b?????1??:
- \5353 = b[23:16];
- 8'b????1???:
- \5353 = b[31:24];
- 8'b???1????:
- \5353 = b[39:32];
- 8'b??1?????:
- \5353 = b[47:40];
- 8'b?1??????:
- \5353 = b[55:48];
- 8'b1???????:
- \5353 = b[63:56];
- default:
- \5353 = a;
- endcase
- endfunction
- assign _0137_ = \5353 (8'h00, 64'h0102040810204080, { _0136_, _0135_, _0134_, _0133_, _0132_, _0131_, _0130_, _0129_ });
- assign _0138_ = _0126_ & e_in[360:356];
- assign _0139_ = | _0138_;
- assign _0140_ = _0139_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h02, ctrl[143:128], 64'h0000000000000700 } : { ctrl[320:257], _0045_ };
- assign _0141_ = _0139_ ? 1'h1 : 1'h0;
- assign _0142_ = _0127_ ? { ctrl[320:257], _0045_ } : _0140_;
- assign _0143_ = _0127_ ? { _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0137_, 1'h1 } : 41'h00000000000;
- assign _0144_ = _0127_ ? 1'h0 : _0141_;
- assign _0145_ = _0092_ ? { ctrl[320:257], _0045_ } : _0142_;
- assign _0146_ = _0092_ ? _0103_[72:0] : { 64'h0000000000000000, e_in[78:73], 3'h1 };
- assign _0147_ = _0092_ ? _0103_[113:73] : _0143_;
- assign _0148_ = _0092_ ? _0103_[190:114] : { e_in[72:9], 7'h44, _0013_, 1'h0 };
- assign _0149_ = _0092_ ? 1'h1 : 1'h0;
- assign _0150_ = _0092_ ? 1'h0 : _0144_;
- assign _0151_ = e_in[8:3] == 6'h02;
- assign _0152_ = e_in[8:3] == 6'h09;
- assign _0153_ = _0151_ | _0152_;
- assign _0154_ = e_in[8:3] == 6'h3b;
- assign _0155_ = _0153_ | _0154_;
- assign _0156_ = e_in[8:3] == 6'h03;
- assign _0157_ = e_in[8:3] == 6'h2e;
- assign _0158_ = _0156_ | _0157_;
- assign _0159_ = e_in[8:3] == 6'h3c;
- assign _0160_ = _0158_ | _0159_;
- assign _0161_ = e_in[72:9] + b_in;
- assign _0162_ = e_in[336] ? b_in : _0161_;
- assign _0163_ = e_in[8:3] == 6'h05;
- assign _0164_ = ~ e_in[358];
- assign _0165_ = a_in - 64'h0000000000000001;
- assign _0166_ = _0164_ ? 6'h21 : e_in[78:73];
- assign _0167_ = _0164_ ? _0165_ : 64'h0000000000000000;
- assign _0168_ = _0164_ ? 1'h1 : 1'h0;
- assign _0169_ = 32'd31 - { 27'h0000000, e_in[355:351] };
- assign _0170_ = _0784_ == e_in[359];
- assign _0171_ = _0170_ ? 1'h1 : 1'h0;
- assign _0172_ = a_in != 64'h0000000000000001;
- assign _0173_ = _0172_ ? 1'h1 : 1'h0;
- assign _0174_ = _0173_ ^ e_in[357];
- assign _0175_ = e_in[358] | _0174_;
- assign _0176_ = e_in[360] | _0171_;
- assign _0177_ = _0175_ & _0176_;
- assign _0178_ = _0177_ ? 32'd1 : 32'd0;
- assign _0179_ = _0178_ == 32'd1;
- assign _0180_ = e_in[72:9] + b_in;
- assign _0181_ = e_in[336] ? b_in : _0180_;
- assign _0182_ = _0179_ ? 1'h1 : 1'h0;
- assign _0183_ = _0179_ ? _0181_ : 64'h0000000000000000;
- assign _0184_ = e_in[8:3] == 6'h06;
- assign _0185_ = ~ e_in[358];
- assign _0186_ = ~ e_in[345];
- assign _0187_ = _0185_ & _0186_;
- assign _0188_ = a_in - 64'h0000000000000001;
- assign _0189_ = _0187_ ? 6'h21 : e_in[78:73];
- assign _0190_ = _0187_ ? _0188_ : 64'h0000000000000000;
- assign _0191_ = _0187_ ? 1'h1 : 1'h0;
- assign _0192_ = 32'd31 - { 27'h0000000, e_in[355:351] };
- assign _0193_ = _0795_ == e_in[359];
- assign _0194_ = _0193_ ? 1'h1 : 1'h0;
- assign _0195_ = a_in != 64'h0000000000000001;
- assign _0196_ = _0195_ ? 1'h1 : 1'h0;
- assign _0197_ = _0196_ ^ e_in[357];
- assign _0198_ = e_in[358] | _0197_;
- assign _0199_ = e_in[360] | _0194_;
- assign _0200_ = _0198_ & _0199_;
- assign _0201_ = _0200_ ? 32'd1 : 32'd0;
- assign _0202_ = _0201_ == 32'd1;
- assign _0203_ = _0202_ ? 1'h1 : 1'h0;
- assign _0204_ = _0202_ ? { b_in[63:2], 2'h0 } : 64'h0000000000000000;
- assign _0205_ = e_in[8:3] == 6'h07;
- assign _0206_ = b_in[5] | b_in[14];
- assign _0207_ = ~ b_in[14];
- assign _0208_ = b_in[14] ? 2'h3 : b_in[5:4];
- assign _0209_ = b_in[14] ? 1'h1 : b_in[15];
- assign _0210_ = e_in[8:3] == 6'h31;
- assign _0211_ = c_in[7:0] == b_in[7:0];
- assign _0212_ = _0211_ ? 8'hff : 8'h00;
- assign _0213_ = c_in[15:8] == b_in[15:8];
- assign _0214_ = _0213_ ? 8'hff : 8'h00;
- assign _0215_ = c_in[23:16] == b_in[23:16];
- assign _0216_ = _0215_ ? 8'hff : 8'h00;
- assign _0217_ = c_in[31:24] == b_in[31:24];
- assign _0218_ = _0217_ ? 8'hff : 8'h00;
- assign _0219_ = c_in[39:32] == b_in[39:32];
- assign _0220_ = _0219_ ? 8'hff : 8'h00;
- assign _0221_ = c_in[47:40] == b_in[47:40];
- assign _0222_ = _0221_ ? 8'hff : 8'h00;
- assign _0223_ = c_in[55:48] == b_in[55:48];
- assign _0224_ = _0223_ ? 8'hff : 8'h00;
- assign _0225_ = c_in[63:56] == b_in[63:56];
- assign _0226_ = _0225_ ? 8'hff : 8'h00;
- assign _0227_ = e_in[8:3] == 6'h0a;
- assign _0228_ = e_in[8:3] == 6'h0d;
- assign _0229_ = e_in[367] & c_in[7];
- assign _0230_ = e_in[368] & c_in[15];
- assign _0231_ = _0229_ | _0230_;
- assign _0232_ = e_in[369] & c_in[31];
- assign _0233_ = _0231_ | _0232_;
- assign _0234_ = e_in[369] ? c_in[31:16] : { _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_ };
- assign _0235_ = e_in[369] | e_in[368];
- assign _0236_ = _0235_ ? c_in[15:8] : { _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_ };
- assign _0237_ = e_in[8:3] == 6'h17;
- assign _0238_ = 32'd31 - { 27'h0000000, e_in[345:341] };
- assign _0239_ = _0806_ ? a_in : b_in;
- assign _0240_ = e_in[8:3] == 6'h1b;
- assign _0241_ = ~ e_in[336];
- assign _0242_ = e_in[360:358] == 3'h0;
- assign _0243_ = e_in[360:358] == 3'h1;
- assign _0244_ = e_in[360:358] == 3'h2;
- assign _0245_ = e_in[360:358] == 3'h3;
- assign _0246_ = e_in[360:358] == 3'h4;
- assign _0247_ = e_in[360:358] == 3'h5;
- assign _0248_ = e_in[360:358] == 3'h6;
- assign _0249_ = e_in[360:358] == 3'h7;
- function [7:0] \5912 ;
- input [7:0] a;
- input [63:0] b;
- input [7:0] s;
- (* parallel_case *)
- casez (s)
- 8'b???????1:
- \5912 = b[7:0];
- 8'b??????1?:
- \5912 = b[15:8];
- 8'b?????1??:
- \5912 = b[23:16];
- 8'b????1???:
- \5912 = b[31:24];
- 8'b???1????:
- \5912 = b[39:32];
- 8'b??1?????:
- \5912 = b[47:40];
- 8'b?1??????:
- \5912 = b[55:48];
- 8'b1???????:
- \5912 = b[63:56];
- default:
- \5912 = a;
- endcase
- endfunction
- assign _0250_ = \5912 (8'h00, 64'h0102040810204080, { _0249_, _0248_, _0247_, _0246_, _0245_, _0244_, _0243_, _0242_ });
- assign _0251_ = 32'd0 == { 29'h00000000, e_in[355:353] };
- assign _0252_ = _0251_ ? e_in[317:314] : 4'h0;
- assign _0253_ = 32'd1 == { 29'h00000000, e_in[355:353] };
- assign _0254_ = _0253_ ? e_in[313:310] : _0252_;
- assign _0255_ = 32'd2 == { 29'h00000000, e_in[355:353] };
- assign _0256_ = _0255_ ? e_in[309:306] : _0254_;
- assign _0257_ = 32'd3 == { 29'h00000000, e_in[355:353] };
- assign _0258_ = _0257_ ? e_in[305:302] : _0256_;
- assign _0259_ = 32'd4 == { 29'h00000000, e_in[355:353] };
- assign _0260_ = _0259_ ? e_in[301:298] : _0258_;
- assign _0261_ = 32'd5 == { 29'h00000000, e_in[355:353] };
- assign _0262_ = _0261_ ? e_in[297:294] : _0260_;
- assign _0263_ = 32'd6 == { 29'h00000000, e_in[355:353] };
- assign _0264_ = _0263_ ? e_in[293:290] : _0262_;
- assign _0265_ = 32'd7 == { 29'h00000000, e_in[355:353] };
- assign _0266_ = _0265_ ? e_in[289:286] : _0264_;
- assign _0267_ = 32'd31 - { 27'h0000000, e_in[360:356] };
- assign _0268_ = 32'd31 - { 27'h0000000, e_in[355:351] };
- assign _0269_ = 32'd31 - { 27'h0000000, e_in[350:346] };
- assign _0270_ = 32'd5 + { 30'h00000000, _0817_, _0828_ };
- assign _0271_ = 32'd31 - { 27'h0000000, _0267_[4:0] };
- assign _0272_ = $signed(_0271_) / $signed(32'd4);
- assign _0273_ = _0272_[2:0] == 3'h0;
- assign _0274_ = _0272_[2:0] == 3'h1;
- assign _0275_ = _0272_[2:0] == 3'h2;
- assign _0276_ = _0272_[2:0] == 3'h3;
- assign _0277_ = _0272_[2:0] == 3'h4;
- assign _0278_ = _0272_[2:0] == 3'h5;
- assign _0279_ = _0272_[2:0] == 3'h6;
- assign _0280_ = _0272_[2:0] == 3'h7;
- function [7:0] \6042 ;
- input [7:0] a;
- input [63:0] b;
- input [7:0] s;
- (* parallel_case *)
- casez (s)
- 8'b???????1:
- \6042 = b[7:0];
- 8'b??????1?:
- \6042 = b[15:8];
- 8'b?????1??:
- \6042 = b[23:16];
- 8'b????1???:
- \6042 = b[31:24];
- 8'b???1????:
- \6042 = b[39:32];
- 8'b??1?????:
- \6042 = b[47:40];
- 8'b?1??????:
- \6042 = b[55:48];
- 8'b1???????:
- \6042 = b[63:56];
- default:
- \6042 = a;
- endcase
- endfunction
- assign _0281_ = \6042 (8'h00, 64'h0102040810204080, { _0280_, _0279_, _0278_, _0277_, _0276_, _0275_, _0274_, _0273_ });
- assign _0282_ = 32'd0 == { 27'h0000000, _0267_[4:0] };
- assign _0283_ = _0282_ ? _0833_ : e_in[286];
- assign _0284_ = 32'd1 == { 27'h0000000, _0267_[4:0] };
- assign _0285_ = _0284_ ? _0833_ : e_in[287];
- assign _0286_ = 32'd2 == { 27'h0000000, _0267_[4:0] };
- assign _0287_ = _0286_ ? _0833_ : e_in[288];
- assign _0288_ = 32'd3 == { 27'h0000000, _0267_[4:0] };
- assign _0289_ = _0288_ ? _0833_ : e_in[289];
- assign _0290_ = 32'd4 == { 27'h0000000, _0267_[4:0] };
- assign _0291_ = _0290_ ? _0833_ : e_in[290];
- assign _0292_ = 32'd5 == { 27'h0000000, _0267_[4:0] };
- assign _0293_ = _0292_ ? _0833_ : e_in[291];
- assign _0294_ = 32'd6 == { 27'h0000000, _0267_[4:0] };
- assign _0295_ = _0294_ ? _0833_ : e_in[292];
- assign _0296_ = 32'd7 == { 27'h0000000, _0267_[4:0] };
- assign _0297_ = _0296_ ? _0833_ : e_in[293];
- assign _0298_ = 32'd8 == { 27'h0000000, _0267_[4:0] };
- assign _0299_ = _0298_ ? _0833_ : e_in[294];
- assign _0300_ = 32'd9 == { 27'h0000000, _0267_[4:0] };
- assign _0301_ = _0300_ ? _0833_ : e_in[295];
- assign _0302_ = 32'd10 == { 27'h0000000, _0267_[4:0] };
- assign _0303_ = _0302_ ? _0833_ : e_in[296];
- assign _0304_ = 32'd11 == { 27'h0000000, _0267_[4:0] };
- assign _0305_ = _0304_ ? _0833_ : e_in[297];
- assign _0306_ = 32'd12 == { 27'h0000000, _0267_[4:0] };
- assign _0307_ = _0306_ ? _0833_ : e_in[298];
- assign _0308_ = 32'd13 == { 27'h0000000, _0267_[4:0] };
- assign _0309_ = _0308_ ? _0833_ : e_in[299];
- assign _0310_ = 32'd14 == { 27'h0000000, _0267_[4:0] };
- assign _0311_ = _0310_ ? _0833_ : e_in[300];
- assign _0312_ = 32'd15 == { 27'h0000000, _0267_[4:0] };
- assign _0313_ = _0312_ ? _0833_ : e_in[301];
- assign _0314_ = 32'd16 == { 27'h0000000, _0267_[4:0] };
- assign _0315_ = _0314_ ? _0833_ : e_in[302];
- assign _0316_ = 32'd17 == { 27'h0000000, _0267_[4:0] };
- assign _0317_ = _0316_ ? _0833_ : e_in[303];
- assign _0318_ = 32'd18 == { 27'h0000000, _0267_[4:0] };
- assign _0319_ = _0318_ ? _0833_ : e_in[304];
- assign _0320_ = 32'd19 == { 27'h0000000, _0267_[4:0] };
- assign _0321_ = _0320_ ? _0833_ : e_in[305];
- assign _0322_ = 32'd20 == { 27'h0000000, _0267_[4:0] };
- assign _0323_ = _0322_ ? _0833_ : e_in[306];
- assign _0324_ = 32'd21 == { 27'h0000000, _0267_[4:0] };
- assign _0325_ = _0324_ ? _0833_ : e_in[307];
- assign _0326_ = 32'd22 == { 27'h0000000, _0267_[4:0] };
- assign _0327_ = _0326_ ? _0833_ : e_in[308];
- assign _0328_ = 32'd23 == { 27'h0000000, _0267_[4:0] };
- assign _0329_ = _0328_ ? _0833_ : e_in[309];
- assign _0330_ = 32'd24 == { 27'h0000000, _0267_[4:0] };
- assign _0331_ = _0330_ ? _0833_ : e_in[310];
- assign _0332_ = 32'd25 == { 27'h0000000, _0267_[4:0] };
- assign _0333_ = _0332_ ? _0833_ : e_in[311];
- assign _0334_ = 32'd26 == { 27'h0000000, _0267_[4:0] };
- assign _0335_ = _0334_ ? _0833_ : e_in[312];
- assign _0336_ = 32'd27 == { 27'h0000000, _0267_[4:0] };
- assign _0337_ = _0336_ ? _0833_ : e_in[313];
- assign _0338_ = 32'd28 == { 27'h0000000, _0267_[4:0] };
- assign _0339_ = _0338_ ? _0833_ : e_in[314];
- assign _0340_ = 32'd29 == { 27'h0000000, _0267_[4:0] };
- assign _0341_ = _0340_ ? _0833_ : e_in[315];
- assign _0342_ = 32'd30 == { 27'h0000000, _0267_[4:0] };
- assign _0343_ = _0342_ ? _0833_ : e_in[316];
- assign _0344_ = 32'd31 == { 27'h0000000, _0267_[4:0] };
- assign _0345_ = _0344_ ? _0833_ : e_in[317];
- assign _0346_ = _0241_ ? { _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0250_, 1'h1 } : { _0345_, _0343_, _0341_, _0339_, _0337_, _0335_, _0333_, _0331_, _0329_, _0327_, _0325_, _0323_, _0321_, _0319_, _0317_, _0315_, _0313_, _0311_, _0309_, _0307_, _0305_, _0303_, _0301_, _0299_, _0297_, _0295_, _0293_, _0291_, _0289_, _0287_, _0285_, _0283_, _0281_, 1'h1 };
- assign _0347_ = e_in[8:3] == 6'h0e;
- assign _0348_ = e_in[8:3] == 6'h25;
- assign _0349_ = { 22'h000000, e_in[350:346], e_in[355:351] } == 32'd1;
- assign _0350_ = _0349_ ? { 32'h00000000, _0013_[4], _0013_[2], _0013_[0], 9'h000, _0013_[3], _0013_[1] } : a_in[63:18];
- assign _0351_ = { e_in[350:346], e_in[355:351] } == 10'h10c;
- assign _0352_ = { e_in[350:346], e_in[355:351] } == 10'h016;
- assign _0353_ = ctrl[142] ? 1'h1 : 1'h0;
- function [63:0] \6311 ;
- input [63:0] a;
- input [127:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \6311 = b[63:0];
- 2'b1?:
- \6311 = b[127:64];
- default:
- \6311 = a;
- endcase
- endfunction
- assign _0354_ = \6311 (c_in, ctrl[127:0], { _0352_, _0351_ });
- function [0:0] \6313 ;
- input [0:0] a;
- input [1:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \6313 = b[0:0];
- 2'b1?:
- \6313 = b[1:1];
- default:
- \6313 = a;
- endcase
- endfunction
- assign _0355_ = \6313 (_0353_, 2'h0, { _0352_, _0351_ });
- assign _0356_ = e_in[84] ? { _0350_, a_in[17:0] } : _0354_;
- assign _0357_ = e_in[84] ? 1'h0 : _0355_;
- assign _0358_ = e_in[8:3] == 6'h26;
- assign _0359_ = ~ e_in[355];
- assign _0360_ = e_in[354] ? 1'h0 : 1'h1;
- assign _0361_ = e_in[354] ? 1'h0 : 1'h1;
- assign _0362_ = e_in[354] ? 3'h0 : 3'hx;
- assign _0363_ = _0369_ ? 1'h0 : _0360_;
- assign _0364_ = _0370_ ? 1'h0 : _0361_;
- assign _0365_ = _0371_ ? 3'h1 : _0362_;
- assign _0366_ = e_in[353] & _0360_;
- assign _0367_ = e_in[353] & _0360_;
- assign _0368_ = e_in[353] & _0360_;
- assign _0369_ = _0360_ & _0366_;
- assign _0370_ = _0360_ & _0367_;
- assign _0371_ = _0360_ & _0368_;
- assign _0372_ = _0378_ ? 1'h0 : _0363_;
- assign _0373_ = _0379_ ? 1'h0 : _0364_;
- assign _0374_ = _0380_ ? 3'h2 : _0365_;
- assign _0375_ = e_in[352] & _0363_;
- assign _0376_ = e_in[352] & _0363_;
- assign _0377_ = e_in[352] & _0363_;
- assign _0378_ = _0363_ & _0375_;
- assign _0379_ = _0363_ & _0376_;
- assign _0380_ = _0363_ & _0377_;
- assign _0381_ = _0387_ ? 1'h0 : _0372_;
- assign _0382_ = _0388_ ? 1'h0 : _0373_;
- assign _0383_ = _0389_ ? 3'h3 : _0374_;
- assign _0384_ = e_in[351] & _0372_;
- assign _0385_ = e_in[351] & _0372_;
- assign _0386_ = e_in[351] & _0372_;
- assign _0387_ = _0372_ & _0384_;
- assign _0388_ = _0372_ & _0385_;
- assign _0389_ = _0372_ & _0386_;
- assign _0390_ = _0396_ ? 1'h0 : _0381_;
- assign _0391_ = _0397_ ? 1'h0 : _0382_;
- assign _0392_ = _0398_ ? 3'h4 : _0383_;
- assign _0393_ = e_in[350] & _0381_;
- assign _0394_ = e_in[350] & _0381_;
- assign _0395_ = e_in[350] & _0381_;
- assign _0396_ = _0381_ & _0393_;
- assign _0397_ = _0381_ & _0394_;
- assign _0398_ = _0381_ & _0395_;
- assign _0399_ = _0405_ ? 1'h0 : _0390_;
- assign _0400_ = _0406_ ? 1'h0 : _0391_;
- assign _0401_ = _0407_ ? 3'h5 : _0392_;
- assign _0402_ = e_in[349] & _0390_;
- assign _0403_ = e_in[349] & _0390_;
- assign _0404_ = e_in[349] & _0390_;
- assign _0405_ = _0390_ & _0402_;
- assign _0406_ = _0390_ & _0403_;
- assign _0407_ = _0390_ & _0404_;
- assign _0408_ = _0414_ ? 1'h0 : _0399_;
- assign _0409_ = _0415_ ? 1'h0 : _0400_;
- assign _0410_ = _0416_ ? 3'h6 : _0401_;
- assign _0411_ = e_in[348] & _0399_;
- assign _0412_ = e_in[348] & _0399_;
- assign _0413_ = e_in[348] & _0399_;
- assign _0414_ = _0399_ & _0411_;
- assign _0415_ = _0399_ & _0412_;
- assign _0416_ = _0399_ & _0413_;
- assign _0417_ = _0421_ ? 1'h0 : _0409_;
- assign _0418_ = _0422_ ? 3'h7 : _0410_;
- assign _0419_ = e_in[347] & _0408_;
- assign _0420_ = e_in[347] & _0408_;
- assign _0421_ = _0408_ & _0419_;
- assign _0422_ = _0408_ & _0420_;
- assign _0423_ = _0417_ ? 3'h7 : _0418_;
- assign _0424_ = { 29'h00000000, _0423_ } == 32'd0;
- assign _0425_ = _0424_ ? e_in[317:314] : 4'h0;
- assign _0426_ = { 29'h00000000, _0423_ } == 32'd1;
- assign _0427_ = _0426_ ? e_in[313:310] : 4'h0;
- assign _0428_ = { 29'h00000000, _0423_ } == 32'd2;
- assign _0429_ = _0428_ ? e_in[309:306] : 4'h0;
- assign _0430_ = { 29'h00000000, _0423_ } == 32'd3;
- assign _0431_ = _0430_ ? e_in[305:302] : 4'h0;
- assign _0432_ = { 29'h00000000, _0423_ } == 32'd4;
- assign _0433_ = _0432_ ? e_in[301:298] : 4'h0;
- assign _0434_ = { 29'h00000000, _0423_ } == 32'd5;
- assign _0435_ = _0434_ ? e_in[297:294] : 4'h0;
- assign _0436_ = { 29'h00000000, _0423_ } == 32'd6;
- assign _0437_ = _0436_ ? e_in[293:290] : 4'h0;
- assign _0438_ = { 29'h00000000, _0423_ } == 32'd7;
- assign _0439_ = _0438_ ? e_in[289:286] : 4'h0;
- assign _0440_ = _0359_ ? { 32'h00000000, e_in[317:286] } : { 32'h00000000, _0425_, _0427_, _0429_, _0431_, _0433_, _0435_, _0437_, _0439_ };
- assign _0441_ = e_in[8:3] == 6'h24;
- assign _0442_ = ~ e_in[355];
- assign _0443_ = e_in[354] ? 1'h0 : 1'h1;
- assign _0444_ = e_in[354] ? 1'h0 : 1'h1;
- assign _0445_ = e_in[354] ? 3'h0 : 3'hx;
- assign _0446_ = _0452_ ? 1'h0 : _0443_;
- assign _0447_ = _0453_ ? 1'h0 : _0444_;
- assign _0448_ = _0454_ ? 3'h1 : _0445_;
- assign _0449_ = e_in[353] & _0443_;
- assign _0450_ = e_in[353] & _0443_;
- assign _0451_ = e_in[353] & _0443_;
- assign _0452_ = _0443_ & _0449_;
- assign _0453_ = _0443_ & _0450_;
- assign _0454_ = _0443_ & _0451_;
- assign _0455_ = _0461_ ? 1'h0 : _0446_;
- assign _0456_ = _0462_ ? 1'h0 : _0447_;
- assign _0457_ = _0463_ ? 3'h2 : _0448_;
- assign _0458_ = e_in[352] & _0446_;
- assign _0459_ = e_in[352] & _0446_;
- assign _0460_ = e_in[352] & _0446_;
- assign _0461_ = _0446_ & _0458_;
- assign _0462_ = _0446_ & _0459_;
- assign _0463_ = _0446_ & _0460_;
- assign _0464_ = _0470_ ? 1'h0 : _0455_;
- assign _0465_ = _0471_ ? 1'h0 : _0456_;
- assign _0466_ = _0472_ ? 3'h3 : _0457_;
- assign _0467_ = e_in[351] & _0455_;
- assign _0468_ = e_in[351] & _0455_;
- assign _0469_ = e_in[351] & _0455_;
- assign _0470_ = _0455_ & _0467_;
- assign _0471_ = _0455_ & _0468_;
- assign _0472_ = _0455_ & _0469_;
- assign _0473_ = _0479_ ? 1'h0 : _0464_;
- assign _0474_ = _0480_ ? 1'h0 : _0465_;
- assign _0475_ = _0481_ ? 3'h4 : _0466_;
- assign _0476_ = e_in[350] & _0464_;
- assign _0477_ = e_in[350] & _0464_;
- assign _0478_ = e_in[350] & _0464_;
- assign _0479_ = _0464_ & _0476_;
- assign _0480_ = _0464_ & _0477_;
- assign _0481_ = _0464_ & _0478_;
- assign _0482_ = _0488_ ? 1'h0 : _0473_;
- assign _0483_ = _0489_ ? 1'h0 : _0474_;
- assign _0484_ = _0490_ ? 3'h5 : _0475_;
- assign _0485_ = e_in[349] & _0473_;
- assign _0486_ = e_in[349] & _0473_;
- assign _0487_ = e_in[349] & _0473_;
- assign _0488_ = _0473_ & _0485_;
- assign _0489_ = _0473_ & _0486_;
- assign _0490_ = _0473_ & _0487_;
- assign _0491_ = _0497_ ? 1'h0 : _0482_;
- assign _0492_ = _0498_ ? 1'h0 : _0483_;
- assign _0493_ = _0499_ ? 3'h6 : _0484_;
- assign _0494_ = e_in[348] & _0482_;
- assign _0495_ = e_in[348] & _0482_;
- assign _0496_ = e_in[348] & _0482_;
- assign _0497_ = _0482_ & _0494_;
- assign _0498_ = _0482_ & _0495_;
- assign _0499_ = _0482_ & _0496_;
- assign _0500_ = _0504_ ? 1'h0 : _0492_;
- assign _0501_ = _0505_ ? 3'h7 : _0493_;
- assign _0502_ = e_in[347] & _0491_;
- assign _0503_ = e_in[347] & _0491_;
- assign _0504_ = _0491_ & _0502_;
- assign _0505_ = _0491_ & _0503_;
- assign _0506_ = _0500_ ? 3'h7 : _0501_;
- assign _0507_ = _0506_ == 3'h0;
- assign _0508_ = _0506_ == 3'h1;
- assign _0509_ = _0506_ == 3'h2;
- assign _0510_ = _0506_ == 3'h3;
- assign _0511_ = _0506_ == 3'h4;
- assign _0512_ = _0506_ == 3'h5;
- assign _0513_ = _0506_ == 3'h6;
- assign _0514_ = _0506_ == 3'h7;
- function [7:0] \6671 ;
- input [7:0] a;
- input [63:0] b;
- input [7:0] s;
- (* parallel_case *)
- casez (s)
- 8'b???????1:
- \6671 = b[7:0];
- 8'b??????1?:
- \6671 = b[15:8];
- 8'b?????1??:
- \6671 = b[23:16];
- 8'b????1???:
- \6671 = b[31:24];
- 8'b???1????:
- \6671 = b[39:32];
- 8'b??1?????:
- \6671 = b[47:40];
- 8'b?1??????:
- \6671 = b[55:48];
- 8'b1???????:
- \6671 = b[63:56];
- default:
- \6671 = a;
- endcase
- endfunction
- assign _0515_ = \6671 (8'h00, 64'h0102040810204080, { _0514_, _0513_, _0512_, _0511_, _0510_, _0509_, _0508_, _0507_ });
- assign _0516_ = _0442_ ? e_in[354:347] : _0515_;
- assign _0517_ = e_in[8:3] == 6'h28;
- assign _0518_ = c_in[14] ? 2'h3 : c_in[5:4];
- assign _0519_ = c_in[14] ? 1'h1 : c_in[15];
- assign _0520_ = e_in[351] ? c_in[1] : c_in[1];
- assign _0521_ = e_in[351] ? ctrl[139:130] : { c_in[11:6], _0518_, c_in[3:2] };
- assign _0522_ = e_in[351] ? ctrl[142:141] : c_in[14:13];
- assign _0523_ = e_in[351] ? c_in[15] : _0519_;
- assign _0524_ = e_in[351] ? ctrl[187:144] : c_in[59:16];
- assign _0525_ = e_in[351] ? ctrl[191:189] : c_in[63:61];
- assign _0526_ = e_in[8:3] == 6'h29;
- assign _0527_ = { 22'h000000, e_in[350:346], e_in[355:351] } == 32'd1;
- assign _0528_ = _0527_ ? { c_in[31], c_in[19], c_in[30], c_in[18], c_in[29], 1'h1 } : { _0013_, 1'h0 };
- assign _0529_ = { e_in[350:346], e_in[355:351] } == 10'h016;
- assign _0530_ = ctrl[142] ? 1'h1 : 1'h0;
- function [63:0] \6761 ;
- input [63:0] a;
- input [63:0] b;
- input [0:0] s;
- (* parallel_case *)
- casez (s)
- 1'b1:
- \6761 = b[63:0];
- default:
- \6761 = a;
- endcase
- endfunction
- assign _0531_ = \6761 (_0040_, c_in, _0529_);
- function [0:0] \6763 ;
- input [0:0] a;
- input [0:0] b;
- input [0:0] s;
- (* parallel_case *)
- casez (s)
- 1'b1:
- \6763 = b[0:0];
- default:
- \6763 = a;
- endcase
- endfunction
- assign _0532_ = \6763 (_0530_, 1'h0, _0529_);
- assign _0533_ = e_in[78] ? _0040_ : _0531_;
- assign _0534_ = e_in[78] ? _0528_ : { _0013_, 1'h0 };
- assign _0535_ = e_in[78] ? c_in : 64'h0000000000000000;
- assign _0536_ = e_in[78] ? 1'h1 : 1'h0;
- assign _0537_ = e_in[78] ? 1'h0 : _0532_;
- assign _0538_ = e_in[8:3] == 6'h2a;
- assign _0539_ = e_in[8:3] == 6'h2f;
- assign _0540_ = e_in[8:3] == 6'h30;
- assign _0541_ = e_in[330] ? { e_in[72:9], 7'h44, _0013_[4:2], rotator_carry, rotator_carry, 106'h200000000000000000000000000, e_in[78:73], 3'h1 } : { e_in[72:9], 7'h44, _0013_, 106'h000000000000000000000000000, e_in[78:73], 3'h1 };
- assign _0542_ = e_in[8:3] == 6'h32;
- assign _0543_ = e_in[8:3] == 6'h33;
- assign _0544_ = _0542_ | _0543_;
- assign _0545_ = e_in[8:3] == 6'h34;
- assign _0546_ = _0544_ | _0545_;
- assign _0547_ = e_in[8:3] == 6'h37;
- assign _0548_ = _0546_ | _0547_;
- assign _0549_ = e_in[8:3] == 6'h38;
- assign _0550_ = _0548_ | _0549_;
- assign _0551_ = e_in[8:3] == 6'h18;
- assign _0552_ = _0550_ | _0551_;
- assign _0553_ = e_in[8:3] == 6'h1c;
- assign _0554_ = e_in[8:3] == 6'h19;
- assign _0555_ = e_in[8:3] == 6'h2b;
- assign _0556_ = e_in[8:3] == 6'h2c;
- assign _0557_ = _0555_ | _0556_;
- assign _0558_ = e_in[8:3] == 6'h2d;
- assign _0559_ = _0557_ | _0558_;
- assign _0560_ = e_in[8:3] == 6'h15;
- assign _0561_ = e_in[8:3] == 6'h16;
- assign _0562_ = _0560_ | _0561_;
- assign _0563_ = e_in[8:3] == 6'h27;
- assign _0564_ = _0562_ | _0563_;
- function [0:0] \6847 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6847 = b[0:0];
- 28'b??????????????????????????1?:
- \6847 = b[1:1];
- 28'b?????????????????????????1??:
- \6847 = b[2:2];
- 28'b????????????????????????1???:
- \6847 = b[3:3];
- 28'b???????????????????????1????:
- \6847 = b[4:4];
- 28'b??????????????????????1?????:
- \6847 = b[5:5];
- 28'b?????????????????????1??????:
- \6847 = b[6:6];
- 28'b????????????????????1???????:
- \6847 = b[7:7];
- 28'b???????????????????1????????:
- \6847 = b[8:8];
- 28'b??????????????????1?????????:
- \6847 = b[9:9];
- 28'b?????????????????1??????????:
- \6847 = b[10:10];
- 28'b????????????????1???????????:
- \6847 = b[11:11];
- 28'b???????????????1????????????:
- \6847 = b[12:12];
- 28'b??????????????1?????????????:
- \6847 = b[13:13];
- 28'b?????????????1??????????????:
- \6847 = b[14:14];
- 28'b????????????1???????????????:
- \6847 = b[15:15];
- 28'b???????????1????????????????:
- \6847 = b[16:16];
- 28'b??????????1?????????????????:
- \6847 = b[17:17];
- 28'b?????????1??????????????????:
- \6847 = b[18:18];
- 28'b????????1???????????????????:
- \6847 = b[19:19];
- 28'b???????1????????????????????:
- \6847 = b[20:20];
- 28'b??????1?????????????????????:
- \6847 = b[21:21];
- 28'b?????1??????????????????????:
- \6847 = b[22:22];
- 28'b????1???????????????????????:
- \6847 = b[23:23];
- 28'b???1????????????????????????:
- \6847 = b[24:24];
- 28'b??1?????????????????????????:
- \6847 = b[25:25];
- 28'b?1??????????????????????????:
- \6847 = b[26:26];
- 28'b1???????????????????????????:
- \6847 = b[27:27];
- default:
- \6847 = a;
- endcase
- endfunction
- assign _0565_ = \6847 (1'h0, 28'hc000800, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6848 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6848 = b[0:0];
- 28'b??????????????????????????1?:
- \6848 = b[1:1];
- 28'b?????????????????????????1??:
- \6848 = b[2:2];
- 28'b????????????????????????1???:
- \6848 = b[3:3];
- 28'b???????????????????????1????:
- \6848 = b[4:4];
- 28'b??????????????????????1?????:
- \6848 = b[5:5];
- 28'b?????????????????????1??????:
- \6848 = b[6:6];
- 28'b????????????????????1???????:
- \6848 = b[7:7];
- 28'b???????????????????1????????:
- \6848 = b[8:8];
- 28'b??????????????????1?????????:
- \6848 = b[9:9];
- 28'b?????????????????1??????????:
- \6848 = b[10:10];
- 28'b????????????????1???????????:
- \6848 = b[11:11];
- 28'b???????????????1????????????:
- \6848 = b[12:12];
- 28'b??????????????1?????????????:
- \6848 = b[13:13];
- 28'b?????????????1??????????????:
- \6848 = b[14:14];
- 28'b????????????1???????????????:
- \6848 = b[15:15];
- 28'b???????????1????????????????:
- \6848 = b[16:16];
- 28'b??????????1?????????????????:
- \6848 = b[17:17];
- 28'b?????????1??????????????????:
- \6848 = b[18:18];
- 28'b????????1???????????????????:
- \6848 = b[19:19];
- 28'b???????1????????????????????:
- \6848 = b[20:20];
- 28'b??????1?????????????????????:
- \6848 = b[21:21];
- 28'b?????1??????????????????????:
- \6848 = b[22:22];
- 28'b????1???????????????????????:
- \6848 = b[23:23];
- 28'b???1????????????????????????:
- \6848 = b[24:24];
- 28'b??1?????????????????????????:
- \6848 = b[25:25];
- 28'b?1??????????????????????????:
- \6848 = b[26:26];
- 28'b1???????????????????????????:
- \6848 = b[27:27];
- default:
- \6848 = a;
- endcase
- endfunction
- assign _0566_ = \6848 (1'h0, { 19'h08001, _0203_, _0182_, 7'h40 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6849 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6849 = b[0:0];
- 28'b??????????????????????????1?:
- \6849 = b[1:1];
- 28'b?????????????????????????1??:
- \6849 = b[2:2];
- 28'b????????????????????????1???:
- \6849 = b[3:3];
- 28'b???????????????????????1????:
- \6849 = b[4:4];
- 28'b??????????????????????1?????:
- \6849 = b[5:5];
- 28'b?????????????????????1??????:
- \6849 = b[6:6];
- 28'b????????????????????1???????:
- \6849 = b[7:7];
- 28'b???????????????????1????????:
- \6849 = b[8:8];
- 28'b??????????????????1?????????:
- \6849 = b[9:9];
- 28'b?????????????????1??????????:
- \6849 = b[10:10];
- 28'b????????????????1???????????:
- \6849 = b[11:11];
- 28'b???????????????1????????????:
- \6849 = b[12:12];
- 28'b??????????????1?????????????:
- \6849 = b[13:13];
- 28'b?????????????1??????????????:
- \6849 = b[14:14];
- 28'b????????????1???????????????:
- \6849 = b[15:15];
- 28'b???????????1????????????????:
- \6849 = b[16:16];
- 28'b??????????1?????????????????:
- \6849 = b[17:17];
- 28'b?????????1??????????????????:
- \6849 = b[18:18];
- 28'b????????1???????????????????:
- \6849 = b[19:19];
- 28'b???????1????????????????????:
- \6849 = b[20:20];
- 28'b??????1?????????????????????:
- \6849 = b[21:21];
- 28'b?????1??????????????????????:
- \6849 = b[22:22];
- 28'b????1???????????????????????:
- \6849 = b[23:23];
- 28'b???1????????????????????????:
- \6849 = b[24:24];
- 28'b??1?????????????????????????:
- \6849 = b[25:25];
- 28'b?1??????????????????????????:
- \6849 = b[26:26];
- 28'b1???????????????????????????:
- \6849 = b[27:27];
- default:
- \6849 = a;
- endcase
- endfunction
- assign _0567_ = \6849 (ctrl[133], { ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], _0206_, ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6850 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6850 = b[0:0];
- 28'b??????????????????????????1?:
- \6850 = b[1:1];
- 28'b?????????????????????????1??:
- \6850 = b[2:2];
- 28'b????????????????????????1???:
- \6850 = b[3:3];
- 28'b???????????????????????1????:
- \6850 = b[4:4];
- 28'b??????????????????????1?????:
- \6850 = b[5:5];
- 28'b?????????????????????1??????:
- \6850 = b[6:6];
- 28'b????????????????????1???????:
- \6850 = b[7:7];
- 28'b???????????????????1????????:
- \6850 = b[8:8];
- 28'b??????????????????1?????????:
- \6850 = b[9:9];
- 28'b?????????????????1??????????:
- \6850 = b[10:10];
- 28'b????????????????1???????????:
- \6850 = b[11:11];
- 28'b???????????????1????????????:
- \6850 = b[12:12];
- 28'b??????????????1?????????????:
- \6850 = b[13:13];
- 28'b?????????????1??????????????:
- \6850 = b[14:14];
- 28'b????????????1???????????????:
- \6850 = b[15:15];
- 28'b???????????1????????????????:
- \6850 = b[16:16];
- 28'b??????????1?????????????????:
- \6850 = b[17:17];
- 28'b?????????1??????????????????:
- \6850 = b[18:18];
- 28'b????????1???????????????????:
- \6850 = b[19:19];
- 28'b???????1????????????????????:
- \6850 = b[20:20];
- 28'b??????1?????????????????????:
- \6850 = b[21:21];
- 28'b?????1??????????????????????:
- \6850 = b[22:22];
- 28'b????1???????????????????????:
- \6850 = b[23:23];
- 28'b???1????????????????????????:
- \6850 = b[24:24];
- 28'b??1?????????????????????????:
- \6850 = b[25:25];
- 28'b?1??????????????????????????:
- \6850 = b[26:26];
- 28'b1???????????????????????????:
- \6850 = b[27:27];
- default:
- \6850 = a;
- endcase
- endfunction
- assign _0568_ = \6850 (_0047_, { _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0207_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [63:0] \6851 ;
- input [63:0] a;
- input [1791:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6851 = b[63:0];
- 28'b??????????????????????????1?:
- \6851 = b[127:64];
- 28'b?????????????????????????1??:
- \6851 = b[191:128];
- 28'b????????????????????????1???:
- \6851 = b[255:192];
- 28'b???????????????????????1????:
- \6851 = b[319:256];
- 28'b??????????????????????1?????:
- \6851 = b[383:320];
- 28'b?????????????????????1??????:
- \6851 = b[447:384];
- 28'b????????????????????1???????:
- \6851 = b[511:448];
- 28'b???????????????????1????????:
- \6851 = b[575:512];
- 28'b??????????????????1?????????:
- \6851 = b[639:576];
- 28'b?????????????????1??????????:
- \6851 = b[703:640];
- 28'b????????????????1???????????:
- \6851 = b[767:704];
- 28'b???????????????1????????????:
- \6851 = b[831:768];
- 28'b??????????????1?????????????:
- \6851 = b[895:832];
- 28'b?????????????1??????????????:
- \6851 = b[959:896];
- 28'b????????????1???????????????:
- \6851 = b[1023:960];
- 28'b???????????1????????????????:
- \6851 = b[1087:1024];
- 28'b??????????1?????????????????:
- \6851 = b[1151:1088];
- 28'b?????????1??????????????????:
- \6851 = b[1215:1152];
- 28'b????????1???????????????????:
- \6851 = b[1279:1216];
- 28'b???????1????????????????????:
- \6851 = b[1343:1280];
- 28'b??????1?????????????????????:
- \6851 = b[1407:1344];
- 28'b?????1??????????????????????:
- \6851 = b[1471:1408];
- 28'b????1???????????????????????:
- \6851 = b[1535:1472];
- 28'b???1????????????????????????:
- \6851 = b[1599:1536];
- 28'b??1?????????????????????????:
- \6851 = b[1663:1600];
- 28'b?1??????????????????????????:
- \6851 = b[1727:1664];
- 28'b1???????????????????????????:
- \6851 = b[1791:1728];
- default:
- \6851 = a;
- endcase
- endfunction
- assign _0569_ = \6851 (64'h0000000000000000, { 192'h000000000000000000000000000000000000000000000000, _0048_, 896'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, a_in[63:2], 2'h0, _0204_, _0183_, _0162_, 384'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6854 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6854 = b[0:0];
- 28'b??????????????????????????1?:
- \6854 = b[1:1];
- 28'b?????????????????????????1??:
- \6854 = b[2:2];
- 28'b????????????????????????1???:
- \6854 = b[3:3];
- 28'b???????????????????????1????:
- \6854 = b[4:4];
- 28'b??????????????????????1?????:
- \6854 = b[5:5];
- 28'b?????????????????????1??????:
- \6854 = b[6:6];
- 28'b????????????????????1???????:
- \6854 = b[7:7];
- 28'b???????????????????1????????:
- \6854 = b[8:8];
- 28'b??????????????????1?????????:
- \6854 = b[9:9];
- 28'b?????????????????1??????????:
- \6854 = b[10:10];
- 28'b????????????????1???????????:
- \6854 = b[11:11];
- 28'b???????????????1????????????:
- \6854 = b[12:12];
- 28'b??????????????1?????????????:
- \6854 = b[13:13];
- 28'b?????????????1??????????????:
- \6854 = b[14:14];
- 28'b????????????1???????????????:
- \6854 = b[15:15];
- 28'b???????????1????????????????:
- \6854 = b[16:16];
- 28'b??????????1?????????????????:
- \6854 = b[17:17];
- 28'b?????????1??????????????????:
- \6854 = b[18:18];
- 28'b????????1???????????????????:
- \6854 = b[19:19];
- 28'b???????1????????????????????:
- \6854 = b[20:20];
- 28'b??????1?????????????????????:
- \6854 = b[21:21];
- 28'b?????1??????????????????????:
- \6854 = b[22:22];
- 28'b????1???????????????????????:
- \6854 = b[23:23];
- 28'b???1????????????????????????:
- \6854 = b[24:24];
- 28'b??1?????????????????????????:
- \6854 = b[25:25];
- 28'b?1??????????????????????????:
- \6854 = b[26:26];
- 28'b1???????????????????????????:
- \6854 = b[27:27];
- default:
- \6854 = a;
- endcase
- endfunction
- assign _0570_ = \6854 (1'h0, 28'h2000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6857 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6857 = b[0:0];
- 28'b??????????????????????????1?:
- \6857 = b[1:1];
- 28'b?????????????????????????1??:
- \6857 = b[2:2];
- 28'b????????????????????????1???:
- \6857 = b[3:3];
- 28'b???????????????????????1????:
- \6857 = b[4:4];
- 28'b??????????????????????1?????:
- \6857 = b[5:5];
- 28'b?????????????????????1??????:
- \6857 = b[6:6];
- 28'b????????????????????1???????:
- \6857 = b[7:7];
- 28'b???????????????????1????????:
- \6857 = b[8:8];
- 28'b??????????????????1?????????:
- \6857 = b[9:9];
- 28'b?????????????????1??????????:
- \6857 = b[10:10];
- 28'b????????????????1???????????:
- \6857 = b[11:11];
- 28'b???????????????1????????????:
- \6857 = b[12:12];
- 28'b??????????????1?????????????:
- \6857 = b[13:13];
- 28'b?????????????1??????????????:
- \6857 = b[14:14];
- 28'b????????????1???????????????:
- \6857 = b[15:15];
- 28'b???????????1????????????????:
- \6857 = b[16:16];
- 28'b??????????1?????????????????:
- \6857 = b[17:17];
- 28'b?????????1??????????????????:
- \6857 = b[18:18];
- 28'b????????1???????????????????:
- \6857 = b[19:19];
- 28'b???????1????????????????????:
- \6857 = b[20:20];
- 28'b??????1?????????????????????:
- \6857 = b[21:21];
- 28'b?????1??????????????????????:
- \6857 = b[22:22];
- 28'b????1???????????????????????:
- \6857 = b[23:23];
- 28'b???1????????????????????????:
- \6857 = b[24:24];
- 28'b??1?????????????????????????:
- \6857 = b[25:25];
- 28'b?1??????????????????????????:
- \6857 = b[26:26];
- 28'b1???????????????????????????:
- \6857 = b[27:27];
- default:
- \6857 = a;
- endcase
- endfunction
- assign _0571_ = \6857 (1'h1, { 25'h0000000, _0077_, 2'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [63:0] \6858 ;
- input [63:0] a;
- input [1791:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6858 = b[63:0];
- 28'b??????????????????????????1?:
- \6858 = b[127:64];
- 28'b?????????????????????????1??:
- \6858 = b[191:128];
- 28'b????????????????????????1???:
- \6858 = b[255:192];
- 28'b???????????????????????1????:
- \6858 = b[319:256];
- 28'b??????????????????????1?????:
- \6858 = b[383:320];
- 28'b?????????????????????1??????:
- \6858 = b[447:384];
- 28'b????????????????????1???????:
- \6858 = b[511:448];
- 28'b???????????????????1????????:
- \6858 = b[575:512];
- 28'b??????????????????1?????????:
- \6858 = b[639:576];
- 28'b?????????????????1??????????:
- \6858 = b[703:640];
- 28'b????????????????1???????????:
- \6858 = b[767:704];
- 28'b???????????????1????????????:
- \6858 = b[831:768];
- 28'b??????????????1?????????????:
- \6858 = b[895:832];
- 28'b?????????????1??????????????:
- \6858 = b[959:896];
- 28'b????????????1???????????????:
- \6858 = b[1023:960];
- 28'b???????????1????????????????:
- \6858 = b[1087:1024];
- 28'b??????????1?????????????????:
- \6858 = b[1151:1088];
- 28'b?????????1??????????????????:
- \6858 = b[1215:1152];
- 28'b????????1???????????????????:
- \6858 = b[1279:1216];
- 28'b???????1????????????????????:
- \6858 = b[1343:1280];
- 28'b??????1?????????????????????:
- \6858 = b[1407:1344];
- 28'b?????1??????????????????????:
- \6858 = b[1471:1408];
- 28'b????1???????????????????????:
- \6858 = b[1535:1472];
- 28'b???1????????????????????????:
- \6858 = b[1599:1536];
- 28'b??1?????????????????????????:
- \6858 = b[1663:1600];
- 28'b?1??????????????????????????:
- \6858 = b[1727:1664];
- 28'b1???????????????????????????:
- \6858 = b[1791:1728];
- default:
- \6858 = a;
- endcase
- endfunction
- assign _0572_ = \6858 (_0040_, { _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0533_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6861 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6861 = b[0:0];
- 28'b??????????????????????????1?:
- \6861 = b[1:1];
- 28'b?????????????????????????1??:
- \6861 = b[2:2];
- 28'b????????????????????????1???:
- \6861 = b[3:3];
- 28'b???????????????????????1????:
- \6861 = b[4:4];
- 28'b??????????????????????1?????:
- \6861 = b[5:5];
- 28'b?????????????????????1??????:
- \6861 = b[6:6];
- 28'b????????????????????1???????:
- \6861 = b[7:7];
- 28'b???????????????????1????????:
- \6861 = b[8:8];
- 28'b??????????????????1?????????:
- \6861 = b[9:9];
- 28'b?????????????????1??????????:
- \6861 = b[10:10];
- 28'b????????????????1???????????:
- \6861 = b[11:11];
- 28'b???????????????1????????????:
- \6861 = b[12:12];
- 28'b??????????????1?????????????:
- \6861 = b[13:13];
- 28'b?????????????1??????????????:
- \6861 = b[14:14];
- 28'b????????????1???????????????:
- \6861 = b[15:15];
- 28'b???????????1????????????????:
- \6861 = b[16:16];
- 28'b??????????1?????????????????:
- \6861 = b[17:17];
- 28'b?????????1??????????????????:
- \6861 = b[18:18];
- 28'b????????1???????????????????:
- \6861 = b[19:19];
- 28'b???????1????????????????????:
- \6861 = b[20:20];
- 28'b??????1?????????????????????:
- \6861 = b[21:21];
- 28'b?????1??????????????????????:
- \6861 = b[22:22];
- 28'b????1???????????????????????:
- \6861 = b[23:23];
- 28'b???1????????????????????????:
- \6861 = b[24:24];
- 28'b??1?????????????????????????:
- \6861 = b[25:25];
- 28'b?1??????????????????????????:
- \6861 = b[26:26];
- 28'b1???????????????????????????:
- \6861 = b[27:27];
- default:
- \6861 = a;
- endcase
- endfunction
- assign _0573_ = \6861 (ctrl[128], { ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], b_in[0], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6864 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6864 = b[0:0];
- 28'b??????????????????????????1?:
- \6864 = b[1:1];
- 28'b?????????????????????????1??:
- \6864 = b[2:2];
- 28'b????????????????????????1???:
- \6864 = b[3:3];
- 28'b???????????????????????1????:
- \6864 = b[4:4];
- 28'b??????????????????????1?????:
- \6864 = b[5:5];
- 28'b?????????????????????1??????:
- \6864 = b[6:6];
- 28'b????????????????????1???????:
- \6864 = b[7:7];
- 28'b???????????????????1????????:
- \6864 = b[8:8];
- 28'b??????????????????1?????????:
- \6864 = b[9:9];
- 28'b?????????????????1??????????:
- \6864 = b[10:10];
- 28'b????????????????1???????????:
- \6864 = b[11:11];
- 28'b???????????????1????????????:
- \6864 = b[12:12];
- 28'b??????????????1?????????????:
- \6864 = b[13:13];
- 28'b?????????????1??????????????:
- \6864 = b[14:14];
- 28'b????????????1???????????????:
- \6864 = b[15:15];
- 28'b???????????1????????????????:
- \6864 = b[16:16];
- 28'b??????????1?????????????????:
- \6864 = b[17:17];
- 28'b?????????1??????????????????:
- \6864 = b[18:18];
- 28'b????????1???????????????????:
- \6864 = b[19:19];
- 28'b???????1????????????????????:
- \6864 = b[20:20];
- 28'b??????1?????????????????????:
- \6864 = b[21:21];
- 28'b?????1??????????????????????:
- \6864 = b[22:22];
- 28'b????1???????????????????????:
- \6864 = b[23:23];
- 28'b???1????????????????????????:
- \6864 = b[24:24];
- 28'b??1?????????????????????????:
- \6864 = b[25:25];
- 28'b?1??????????????????????????:
- \6864 = b[26:26];
- 28'b1???????????????????????????:
- \6864 = b[27:27];
- default:
- \6864 = a;
- endcase
- endfunction
- assign _0574_ = \6864 (ctrl[129], { ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], _0520_, ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], b_in[1], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [1:0] \6868 ;
- input [1:0] a;
- input [55:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6868 = b[1:0];
- 28'b??????????????????????????1?:
- \6868 = b[3:2];
- 28'b?????????????????????????1??:
- \6868 = b[5:4];
- 28'b????????????????????????1???:
- \6868 = b[7:6];
- 28'b???????????????????????1????:
- \6868 = b[9:8];
- 28'b??????????????????????1?????:
- \6868 = b[11:10];
- 28'b?????????????????????1??????:
- \6868 = b[13:12];
- 28'b????????????????????1???????:
- \6868 = b[15:14];
- 28'b???????????????????1????????:
- \6868 = b[17:16];
- 28'b??????????????????1?????????:
- \6868 = b[19:18];
- 28'b?????????????????1??????????:
- \6868 = b[21:20];
- 28'b????????????????1???????????:
- \6868 = b[23:22];
- 28'b???????????????1????????????:
- \6868 = b[25:24];
- 28'b??????????????1?????????????:
- \6868 = b[27:26];
- 28'b?????????????1??????????????:
- \6868 = b[29:28];
- 28'b????????????1???????????????:
- \6868 = b[31:30];
- 28'b???????????1????????????????:
- \6868 = b[33:32];
- 28'b??????????1?????????????????:
- \6868 = b[35:34];
- 28'b?????????1??????????????????:
- \6868 = b[37:36];
- 28'b????????1???????????????????:
- \6868 = b[39:38];
- 28'b???????1????????????????????:
- \6868 = b[41:40];
- 28'b??????1?????????????????????:
- \6868 = b[43:42];
- 28'b?????1??????????????????????:
- \6868 = b[45:44];
- 28'b????1???????????????????????:
- \6868 = b[47:46];
- 28'b???1????????????????????????:
- \6868 = b[49:48];
- 28'b??1?????????????????????????:
- \6868 = b[51:50];
- 28'b?1??????????????????????????:
- \6868 = b[53:52];
- 28'b1???????????????????????????:
- \6868 = b[55:54];
- default:
- \6868 = a;
- endcase
- endfunction
- assign _0575_ = \6868 (ctrl[131:130], { ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], _0521_[1:0], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], b_in[3:2], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [1:0] \6871 ;
- input [1:0] a;
- input [55:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6871 = b[1:0];
- 28'b??????????????????????????1?:
- \6871 = b[3:2];
- 28'b?????????????????????????1??:
- \6871 = b[5:4];
- 28'b????????????????????????1???:
- \6871 = b[7:6];
- 28'b???????????????????????1????:
- \6871 = b[9:8];
- 28'b??????????????????????1?????:
- \6871 = b[11:10];
- 28'b?????????????????????1??????:
- \6871 = b[13:12];
- 28'b????????????????????1???????:
- \6871 = b[15:14];
- 28'b???????????????????1????????:
- \6871 = b[17:16];
- 28'b??????????????????1?????????:
- \6871 = b[19:18];
- 28'b?????????????????1??????????:
- \6871 = b[21:20];
- 28'b????????????????1???????????:
- \6871 = b[23:22];
- 28'b???????????????1????????????:
- \6871 = b[25:24];
- 28'b??????????????1?????????????:
- \6871 = b[27:26];
- 28'b?????????????1??????????????:
- \6871 = b[29:28];
- 28'b????????????1???????????????:
- \6871 = b[31:30];
- 28'b???????????1????????????????:
- \6871 = b[33:32];
- 28'b??????????1?????????????????:
- \6871 = b[35:34];
- 28'b?????????1??????????????????:
- \6871 = b[37:36];
- 28'b????????1???????????????????:
- \6871 = b[39:38];
- 28'b???????1????????????????????:
- \6871 = b[41:40];
- 28'b??????1?????????????????????:
- \6871 = b[43:42];
- 28'b?????1??????????????????????:
- \6871 = b[45:44];
- 28'b????1???????????????????????:
- \6871 = b[47:46];
- 28'b???1????????????????????????:
- \6871 = b[49:48];
- 28'b??1?????????????????????????:
- \6871 = b[51:50];
- 28'b?1??????????????????????????:
- \6871 = b[53:52];
- 28'b1???????????????????????????:
- \6871 = b[55:54];
- default:
- \6871 = a;
- endcase
- endfunction
- assign _0576_ = \6871 (ctrl[133:132], { ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0521_[3:2], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0208_, ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [5:0] \6875 ;
- input [5:0] a;
- input [167:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6875 = b[5:0];
- 28'b??????????????????????????1?:
- \6875 = b[11:6];
- 28'b?????????????????????????1??:
- \6875 = b[17:12];
- 28'b????????????????????????1???:
- \6875 = b[23:18];
- 28'b???????????????????????1????:
- \6875 = b[29:24];
- 28'b??????????????????????1?????:
- \6875 = b[35:30];
- 28'b?????????????????????1??????:
- \6875 = b[41:36];
- 28'b????????????????????1???????:
- \6875 = b[47:42];
- 28'b???????????????????1????????:
- \6875 = b[53:48];
- 28'b??????????????????1?????????:
- \6875 = b[59:54];
- 28'b?????????????????1??????????:
- \6875 = b[65:60];
- 28'b????????????????1???????????:
- \6875 = b[71:66];
- 28'b???????????????1????????????:
- \6875 = b[77:72];
- 28'b??????????????1?????????????:
- \6875 = b[83:78];
- 28'b?????????????1??????????????:
- \6875 = b[89:84];
- 28'b????????????1???????????????:
- \6875 = b[95:90];
- 28'b???????????1????????????????:
- \6875 = b[101:96];
- 28'b??????????1?????????????????:
- \6875 = b[107:102];
- 28'b?????????1??????????????????:
- \6875 = b[113:108];
- 28'b????????1???????????????????:
- \6875 = b[119:114];
- 28'b???????1????????????????????:
- \6875 = b[125:120];
- 28'b??????1?????????????????????:
- \6875 = b[131:126];
- 28'b?????1??????????????????????:
- \6875 = b[137:132];
- 28'b????1???????????????????????:
- \6875 = b[143:138];
- 28'b???1????????????????????????:
- \6875 = b[149:144];
- 28'b??1?????????????????????????:
- \6875 = b[155:150];
- 28'b?1??????????????????????????:
- \6875 = b[161:156];
- 28'b1???????????????????????????:
- \6875 = b[167:162];
- default:
- \6875 = a;
- endcase
- endfunction
- assign _0577_ = \6875 (ctrl[139:134], { ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], _0521_[9:4], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], b_in[11:6], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6878 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6878 = b[0:0];
- 28'b??????????????????????????1?:
- \6878 = b[1:1];
- 28'b?????????????????????????1??:
- \6878 = b[2:2];
- 28'b????????????????????????1???:
- \6878 = b[3:3];
- 28'b???????????????????????1????:
- \6878 = b[4:4];
- 28'b??????????????????????1?????:
- \6878 = b[5:5];
- 28'b?????????????????????1??????:
- \6878 = b[6:6];
- 28'b????????????????????1???????:
- \6878 = b[7:7];
- 28'b???????????????????1????????:
- \6878 = b[8:8];
- 28'b??????????????????1?????????:
- \6878 = b[9:9];
- 28'b?????????????????1??????????:
- \6878 = b[10:10];
- 28'b????????????????1???????????:
- \6878 = b[11:11];
- 28'b???????????????1????????????:
- \6878 = b[12:12];
- 28'b??????????????1?????????????:
- \6878 = b[13:13];
- 28'b?????????????1??????????????:
- \6878 = b[14:14];
- 28'b????????????1???????????????:
- \6878 = b[15:15];
- 28'b???????????1????????????????:
- \6878 = b[16:16];
- 28'b??????????1?????????????????:
- \6878 = b[17:17];
- 28'b?????????1??????????????????:
- \6878 = b[18:18];
- 28'b????????1???????????????????:
- \6878 = b[19:19];
- 28'b???????1????????????????????:
- \6878 = b[20:20];
- 28'b??????1?????????????????????:
- \6878 = b[21:21];
- 28'b?????1??????????????????????:
- \6878 = b[22:22];
- 28'b????1???????????????????????:
- \6878 = b[23:23];
- 28'b???1????????????????????????:
- \6878 = b[24:24];
- 28'b??1?????????????????????????:
- \6878 = b[25:25];
- 28'b?1??????????????????????????:
- \6878 = b[26:26];
- 28'b1???????????????????????????:
- \6878 = b[27:27];
- default:
- \6878 = a;
- endcase
- endfunction
- assign _0578_ = \6878 (ctrl[140], { ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], b_in[12], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [1:0] \6881 ;
- input [1:0] a;
- input [55:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6881 = b[1:0];
- 28'b??????????????????????????1?:
- \6881 = b[3:2];
- 28'b?????????????????????????1??:
- \6881 = b[5:4];
- 28'b????????????????????????1???:
- \6881 = b[7:6];
- 28'b???????????????????????1????:
- \6881 = b[9:8];
- 28'b??????????????????????1?????:
- \6881 = b[11:10];
- 28'b?????????????????????1??????:
- \6881 = b[13:12];
- 28'b????????????????????1???????:
- \6881 = b[15:14];
- 28'b???????????????????1????????:
- \6881 = b[17:16];
- 28'b??????????????????1?????????:
- \6881 = b[19:18];
- 28'b?????????????????1??????????:
- \6881 = b[21:20];
- 28'b????????????????1???????????:
- \6881 = b[23:22];
- 28'b???????????????1????????????:
- \6881 = b[25:24];
- 28'b??????????????1?????????????:
- \6881 = b[27:26];
- 28'b?????????????1??????????????:
- \6881 = b[29:28];
- 28'b????????????1???????????????:
- \6881 = b[31:30];
- 28'b???????????1????????????????:
- \6881 = b[33:32];
- 28'b??????????1?????????????????:
- \6881 = b[35:34];
- 28'b?????????1??????????????????:
- \6881 = b[37:36];
- 28'b????????1???????????????????:
- \6881 = b[39:38];
- 28'b???????1????????????????????:
- \6881 = b[41:40];
- 28'b??????1?????????????????????:
- \6881 = b[43:42];
- 28'b?????1??????????????????????:
- \6881 = b[45:44];
- 28'b????1???????????????????????:
- \6881 = b[47:46];
- 28'b???1????????????????????????:
- \6881 = b[49:48];
- 28'b??1?????????????????????????:
- \6881 = b[51:50];
- 28'b?1??????????????????????????:
- \6881 = b[53:52];
- 28'b1???????????????????????????:
- \6881 = b[55:54];
- default:
- \6881 = a;
- endcase
- endfunction
- assign _0579_ = \6881 (ctrl[142:141], { ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], _0522_, ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], b_in[14:13], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6883 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6883 = b[0:0];
- 28'b??????????????????????????1?:
- \6883 = b[1:1];
- 28'b?????????????????????????1??:
- \6883 = b[2:2];
- 28'b????????????????????????1???:
- \6883 = b[3:3];
- 28'b???????????????????????1????:
- \6883 = b[4:4];
- 28'b??????????????????????1?????:
- \6883 = b[5:5];
- 28'b?????????????????????1??????:
- \6883 = b[6:6];
- 28'b????????????????????1???????:
- \6883 = b[7:7];
- 28'b???????????????????1????????:
- \6883 = b[8:8];
- 28'b??????????????????1?????????:
- \6883 = b[9:9];
- 28'b?????????????????1??????????:
- \6883 = b[10:10];
- 28'b????????????????1???????????:
- \6883 = b[11:11];
- 28'b???????????????1????????????:
- \6883 = b[12:12];
- 28'b??????????????1?????????????:
- \6883 = b[13:13];
- 28'b?????????????1??????????????:
- \6883 = b[14:14];
- 28'b????????????1???????????????:
- \6883 = b[15:15];
- 28'b???????????1????????????????:
- \6883 = b[16:16];
- 28'b??????????1?????????????????:
- \6883 = b[17:17];
- 28'b?????????1??????????????????:
- \6883 = b[18:18];
- 28'b????????1???????????????????:
- \6883 = b[19:19];
- 28'b???????1????????????????????:
- \6883 = b[20:20];
- 28'b??????1?????????????????????:
- \6883 = b[21:21];
- 28'b?????1??????????????????????:
- \6883 = b[22:22];
- 28'b????1???????????????????????:
- \6883 = b[23:23];
- 28'b???1????????????????????????:
- \6883 = b[24:24];
- 28'b??1?????????????????????????:
- \6883 = b[25:25];
- 28'b?1??????????????????????????:
- \6883 = b[26:26];
- 28'b1???????????????????????????:
- \6883 = b[27:27];
- default:
- \6883 = a;
- endcase
- endfunction
- assign _0580_ = \6883 (ctrl[143], { ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0523_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0209_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [5:0] \6886 ;
- input [5:0] a;
- input [167:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6886 = b[5:0];
- 28'b??????????????????????????1?:
- \6886 = b[11:6];
- 28'b?????????????????????????1??:
- \6886 = b[17:12];
- 28'b????????????????????????1???:
- \6886 = b[23:18];
- 28'b???????????????????????1????:
- \6886 = b[29:24];
- 28'b??????????????????????1?????:
- \6886 = b[35:30];
- 28'b?????????????????????1??????:
- \6886 = b[41:36];
- 28'b????????????????????1???????:
- \6886 = b[47:42];
- 28'b???????????????????1????????:
- \6886 = b[53:48];
- 28'b??????????????????1?????????:
- \6886 = b[59:54];
- 28'b?????????????????1??????????:
- \6886 = b[65:60];
- 28'b????????????????1???????????:
- \6886 = b[71:66];
- 28'b???????????????1????????????:
- \6886 = b[77:72];
- 28'b??????????????1?????????????:
- \6886 = b[83:78];
- 28'b?????????????1??????????????:
- \6886 = b[89:84];
- 28'b????????????1???????????????:
- \6886 = b[95:90];
- 28'b???????????1????????????????:
- \6886 = b[101:96];
- 28'b??????????1?????????????????:
- \6886 = b[107:102];
- 28'b?????????1??????????????????:
- \6886 = b[113:108];
- 28'b????????1???????????????????:
- \6886 = b[119:114];
- 28'b???????1????????????????????:
- \6886 = b[125:120];
- 28'b??????1?????????????????????:
- \6886 = b[131:126];
- 28'b?????1??????????????????????:
- \6886 = b[137:132];
- 28'b????1???????????????????????:
- \6886 = b[143:138];
- 28'b???1????????????????????????:
- \6886 = b[149:144];
- 28'b??1?????????????????????????:
- \6886 = b[155:150];
- 28'b?1??????????????????????????:
- \6886 = b[161:156];
- 28'b1???????????????????????????:
- \6886 = b[167:162];
- default:
- \6886 = a;
- endcase
- endfunction
- assign _0581_ = \6886 (ctrl[149:144], { ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], _0524_[5:0], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [4:0] \6889 ;
- input [4:0] a;
- input [139:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6889 = b[4:0];
- 28'b??????????????????????????1?:
- \6889 = b[9:5];
- 28'b?????????????????????????1??:
- \6889 = b[14:10];
- 28'b????????????????????????1???:
- \6889 = b[19:15];
- 28'b???????????????????????1????:
- \6889 = b[24:20];
- 28'b??????????????????????1?????:
- \6889 = b[29:25];
- 28'b?????????????????????1??????:
- \6889 = b[34:30];
- 28'b????????????????????1???????:
- \6889 = b[39:35];
- 28'b???????????????????1????????:
- \6889 = b[44:40];
- 28'b??????????????????1?????????:
- \6889 = b[49:45];
- 28'b?????????????????1??????????:
- \6889 = b[54:50];
- 28'b????????????????1???????????:
- \6889 = b[59:55];
- 28'b???????????????1????????????:
- \6889 = b[64:60];
- 28'b??????????????1?????????????:
- \6889 = b[69:65];
- 28'b?????????????1??????????????:
- \6889 = b[74:70];
- 28'b????????????1???????????????:
- \6889 = b[79:75];
- 28'b???????????1????????????????:
- \6889 = b[84:80];
- 28'b??????????1?????????????????:
- \6889 = b[89:85];
- 28'b?????????1??????????????????:
- \6889 = b[94:90];
- 28'b????????1???????????????????:
- \6889 = b[99:95];
- 28'b???????1????????????????????:
- \6889 = b[104:100];
- 28'b??????1?????????????????????:
- \6889 = b[109:105];
- 28'b?????1??????????????????????:
- \6889 = b[114:110];
- 28'b????1???????????????????????:
- \6889 = b[119:115];
- 28'b???1????????????????????????:
- \6889 = b[124:120];
- 28'b??1?????????????????????????:
- \6889 = b[129:125];
- 28'b?1??????????????????????????:
- \6889 = b[134:130];
- 28'b1???????????????????????????:
- \6889 = b[139:135];
- default:
- \6889 = a;
- endcase
- endfunction
- assign _0582_ = \6889 (ctrl[154:150], { ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], _0524_[10:6], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], b_in[26:22], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [3:0] \6892 ;
- input [3:0] a;
- input [111:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6892 = b[3:0];
- 28'b??????????????????????????1?:
- \6892 = b[7:4];
- 28'b?????????????????????????1??:
- \6892 = b[11:8];
- 28'b????????????????????????1???:
- \6892 = b[15:12];
- 28'b???????????????????????1????:
- \6892 = b[19:16];
- 28'b??????????????????????1?????:
- \6892 = b[23:20];
- 28'b?????????????????????1??????:
- \6892 = b[27:24];
- 28'b????????????????????1???????:
- \6892 = b[31:28];
- 28'b???????????????????1????????:
- \6892 = b[35:32];
- 28'b??????????????????1?????????:
- \6892 = b[39:36];
- 28'b?????????????????1??????????:
- \6892 = b[43:40];
- 28'b????????????????1???????????:
- \6892 = b[47:44];
- 28'b???????????????1????????????:
- \6892 = b[51:48];
- 28'b??????????????1?????????????:
- \6892 = b[55:52];
- 28'b?????????????1??????????????:
- \6892 = b[59:56];
- 28'b????????????1???????????????:
- \6892 = b[63:60];
- 28'b???????????1????????????????:
- \6892 = b[67:64];
- 28'b??????????1?????????????????:
- \6892 = b[71:68];
- 28'b?????????1??????????????????:
- \6892 = b[75:72];
- 28'b????????1???????????????????:
- \6892 = b[79:76];
- 28'b???????1????????????????????:
- \6892 = b[83:80];
- 28'b??????1?????????????????????:
- \6892 = b[87:84];
- 28'b?????1??????????????????????:
- \6892 = b[91:88];
- 28'b????1???????????????????????:
- \6892 = b[95:92];
- 28'b???1????????????????????????:
- \6892 = b[99:96];
- 28'b??1?????????????????????????:
- \6892 = b[103:100];
- 28'b?1??????????????????????????:
- \6892 = b[107:104];
- 28'b1???????????????????????????:
- \6892 = b[111:108];
- default:
- \6892 = a;
- endcase
- endfunction
- assign _0583_ = \6892 (ctrl[158:155], { ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], _0524_[14:11], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [28:0] \6896 ;
- input [28:0] a;
- input [811:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6896 = b[28:0];
- 28'b??????????????????????????1?:
- \6896 = b[57:29];
- 28'b?????????????????????????1??:
- \6896 = b[86:58];
- 28'b????????????????????????1???:
- \6896 = b[115:87];
- 28'b???????????????????????1????:
- \6896 = b[144:116];
- 28'b??????????????????????1?????:
- \6896 = b[173:145];
- 28'b?????????????????????1??????:
- \6896 = b[202:174];
- 28'b????????????????????1???????:
- \6896 = b[231:203];
- 28'b???????????????????1????????:
- \6896 = b[260:232];
- 28'b??????????????????1?????????:
- \6896 = b[289:261];
- 28'b?????????????????1??????????:
- \6896 = b[318:290];
- 28'b????????????????1???????????:
- \6896 = b[347:319];
- 28'b???????????????1????????????:
- \6896 = b[376:348];
- 28'b??????????????1?????????????:
- \6896 = b[405:377];
- 28'b?????????????1??????????????:
- \6896 = b[434:406];
- 28'b????????????1???????????????:
- \6896 = b[463:435];
- 28'b???????????1????????????????:
- \6896 = b[492:464];
- 28'b??????????1?????????????????:
- \6896 = b[521:493];
- 28'b?????????1??????????????????:
- \6896 = b[550:522];
- 28'b????????1???????????????????:
- \6896 = b[579:551];
- 28'b???????1????????????????????:
- \6896 = b[608:580];
- 28'b??????1?????????????????????:
- \6896 = b[637:609];
- 28'b?????1??????????????????????:
- \6896 = b[666:638];
- 28'b????1???????????????????????:
- \6896 = b[695:667];
- 28'b???1????????????????????????:
- \6896 = b[724:696];
- 28'b??1?????????????????????????:
- \6896 = b[753:725];
- 28'b?1??????????????????????????:
- \6896 = b[782:754];
- 28'b1???????????????????????????:
- \6896 = b[811:783];
- default:
- \6896 = a;
- endcase
- endfunction
- assign _0584_ = \6896 (ctrl[187:159], { ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], _0524_[43:15], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], b_in[59:31], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6899 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6899 = b[0:0];
- 28'b??????????????????????????1?:
- \6899 = b[1:1];
- 28'b?????????????????????????1??:
- \6899 = b[2:2];
- 28'b????????????????????????1???:
- \6899 = b[3:3];
- 28'b???????????????????????1????:
- \6899 = b[4:4];
- 28'b??????????????????????1?????:
- \6899 = b[5:5];
- 28'b?????????????????????1??????:
- \6899 = b[6:6];
- 28'b????????????????????1???????:
- \6899 = b[7:7];
- 28'b???????????????????1????????:
- \6899 = b[8:8];
- 28'b??????????????????1?????????:
- \6899 = b[9:9];
- 28'b?????????????????1??????????:
- \6899 = b[10:10];
- 28'b????????????????1???????????:
- \6899 = b[11:11];
- 28'b???????????????1????????????:
- \6899 = b[12:12];
- 28'b??????????????1?????????????:
- \6899 = b[13:13];
- 28'b?????????????1??????????????:
- \6899 = b[14:14];
- 28'b????????????1???????????????:
- \6899 = b[15:15];
- 28'b???????????1????????????????:
- \6899 = b[16:16];
- 28'b??????????1?????????????????:
- \6899 = b[17:17];
- 28'b?????????1??????????????????:
- \6899 = b[18:18];
- 28'b????????1???????????????????:
- \6899 = b[19:19];
- 28'b???????1????????????????????:
- \6899 = b[20:20];
- 28'b??????1?????????????????????:
- \6899 = b[21:21];
- 28'b?????1??????????????????????:
- \6899 = b[22:22];
- 28'b????1???????????????????????:
- \6899 = b[23:23];
- 28'b???1????????????????????????:
- \6899 = b[24:24];
- 28'b??1?????????????????????????:
- \6899 = b[25:25];
- 28'b?1??????????????????????????:
- \6899 = b[26:26];
- 28'b1???????????????????????????:
- \6899 = b[27:27];
- default:
- \6899 = a;
- endcase
- endfunction
- assign _0585_ = \6899 (ctrl[188], { ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], b_in[60], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [2:0] \6902 ;
- input [2:0] a;
- input [83:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6902 = b[2:0];
- 28'b??????????????????????????1?:
- \6902 = b[5:3];
- 28'b?????????????????????????1??:
- \6902 = b[8:6];
- 28'b????????????????????????1???:
- \6902 = b[11:9];
- 28'b???????????????????????1????:
- \6902 = b[14:12];
- 28'b??????????????????????1?????:
- \6902 = b[17:15];
- 28'b?????????????????????1??????:
- \6902 = b[20:18];
- 28'b????????????????????1???????:
- \6902 = b[23:21];
- 28'b???????????????????1????????:
- \6902 = b[26:24];
- 28'b??????????????????1?????????:
- \6902 = b[29:27];
- 28'b?????????????????1??????????:
- \6902 = b[32:30];
- 28'b????????????????1???????????:
- \6902 = b[35:33];
- 28'b???????????????1????????????:
- \6902 = b[38:36];
- 28'b??????????????1?????????????:
- \6902 = b[41:39];
- 28'b?????????????1??????????????:
- \6902 = b[44:42];
- 28'b????????????1???????????????:
- \6902 = b[47:45];
- 28'b???????????1????????????????:
- \6902 = b[50:48];
- 28'b??????????1?????????????????:
- \6902 = b[53:51];
- 28'b?????????1??????????????????:
- \6902 = b[56:54];
- 28'b????????1???????????????????:
- \6902 = b[59:57];
- 28'b???????1????????????????????:
- \6902 = b[62:60];
- 28'b??????1?????????????????????:
- \6902 = b[65:63];
- 28'b?????1??????????????????????:
- \6902 = b[68:66];
- 28'b????1???????????????????????:
- \6902 = b[71:69];
- 28'b???1????????????????????????:
- \6902 = b[74:72];
- 28'b??1?????????????????????????:
- \6902 = b[77:75];
- 28'b?1??????????????????????????:
- \6902 = b[80:78];
- 28'b1???????????????????????????:
- \6902 = b[83:81];
- default:
- \6902 = a;
- endcase
- endfunction
- assign _0586_ = \6902 (ctrl[191:189], { ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], _0525_, ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], b_in[63:61], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [127:0] \6904 ;
- input [127:0] a;
- input [3583:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6904 = b[127:0];
- 28'b??????????????????????????1?:
- \6904 = b[255:128];
- 28'b?????????????????????????1??:
- \6904 = b[383:256];
- 28'b????????????????????????1???:
- \6904 = b[511:384];
- 28'b???????????????????????1????:
- \6904 = b[639:512];
- 28'b??????????????????????1?????:
- \6904 = b[767:640];
- 28'b?????????????????????1??????:
- \6904 = b[895:768];
- 28'b????????????????????1???????:
- \6904 = b[1023:896];
- 28'b???????????????????1????????:
- \6904 = b[1151:1024];
- 28'b??????????????????1?????????:
- \6904 = b[1279:1152];
- 28'b?????????????????1??????????:
- \6904 = b[1407:1280];
- 28'b????????????????1???????????:
- \6904 = b[1535:1408];
- 28'b???????????????1????????????:
- \6904 = b[1663:1536];
- 28'b??????????????1?????????????:
- \6904 = b[1791:1664];
- 28'b?????????????1??????????????:
- \6904 = b[1919:1792];
- 28'b????????????1???????????????:
- \6904 = b[2047:1920];
- 28'b???????????1????????????????:
- \6904 = b[2175:2048];
- 28'b??????????1?????????????????:
- \6904 = b[2303:2176];
- 28'b?????????1??????????????????:
- \6904 = b[2431:2304];
- 28'b????????1???????????????????:
- \6904 = b[2559:2432];
- 28'b???????1????????????????????:
- \6904 = b[2687:2560];
- 28'b??????1?????????????????????:
- \6904 = b[2815:2688];
- 28'b?????1??????????????????????:
- \6904 = b[2943:2816];
- 28'b????1???????????????????????:
- \6904 = b[3071:2944];
- 28'b???1????????????????????????:
- \6904 = b[3199:3072];
- 28'b??1?????????????????????????:
- \6904 = b[3327:3200];
- 28'b?1??????????????????????????:
- \6904 = b[3455:3328];
- 28'b1???????????????????????????:
- \6904 = b[3583:3456];
- default:
- \6904 = a;
- endcase
- endfunction
- assign _0587_ = \6904 ({ ctrl[320:257], _0045_ }, { ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, _0145_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, _0071_, ctrl[320:257], _0045_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6905 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6905 = b[0:0];
- 28'b??????????????????????????1?:
- \6905 = b[1:1];
- 28'b?????????????????????????1??:
- \6905 = b[2:2];
- 28'b????????????????????????1???:
- \6905 = b[3:3];
- 28'b???????????????????????1????:
- \6905 = b[4:4];
- 28'b??????????????????????1?????:
- \6905 = b[5:5];
- 28'b?????????????????????1??????:
- \6905 = b[6:6];
- 28'b????????????????????1???????:
- \6905 = b[7:7];
- 28'b???????????????????1????????:
- \6905 = b[8:8];
- 28'b??????????????????1?????????:
- \6905 = b[9:9];
- 28'b?????????????????1??????????:
- \6905 = b[10:10];
- 28'b????????????????1???????????:
- \6905 = b[11:11];
- 28'b???????????????1????????????:
- \6905 = b[12:12];
- 28'b??????????????1?????????????:
- \6905 = b[13:13];
- 28'b?????????????1??????????????:
- \6905 = b[14:14];
- 28'b????????????1???????????????:
- \6905 = b[15:15];
- 28'b???????????1????????????????:
- \6905 = b[16:16];
- 28'b??????????1?????????????????:
- \6905 = b[17:17];
- 28'b?????????1??????????????????:
- \6905 = b[18:18];
- 28'b????????1???????????????????:
- \6905 = b[19:19];
- 28'b???????1????????????????????:
- \6905 = b[20:20];
- 28'b??????1?????????????????????:
- \6905 = b[21:21];
- 28'b?????1??????????????????????:
- \6905 = b[22:22];
- 28'b????1???????????????????????:
- \6905 = b[23:23];
- 28'b???1????????????????????????:
- \6905 = b[24:24];
- 28'b??1?????????????????????????:
- \6905 = b[25:25];
- 28'b?1??????????????????????????:
- \6905 = b[26:26];
- 28'b1???????????????????????????:
- \6905 = b[27:27];
- default:
- \6905 = a;
- endcase
- endfunction
- assign _0588_ = \6905 (1'h0, 28'h4000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6906 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6906 = b[0:0];
- 28'b??????????????????????????1?:
- \6906 = b[1:1];
- 28'b?????????????????????????1??:
- \6906 = b[2:2];
- 28'b????????????????????????1???:
- \6906 = b[3:3];
- 28'b???????????????????????1????:
- \6906 = b[4:4];
- 28'b??????????????????????1?????:
- \6906 = b[5:5];
- 28'b?????????????????????1??????:
- \6906 = b[6:6];
- 28'b????????????????????1???????:
- \6906 = b[7:7];
- 28'b???????????????????1????????:
- \6906 = b[8:8];
- 28'b??????????????????1?????????:
- \6906 = b[9:9];
- 28'b?????????????????1??????????:
- \6906 = b[10:10];
- 28'b????????????????1???????????:
- \6906 = b[11:11];
- 28'b???????????????1????????????:
- \6906 = b[12:12];
- 28'b??????????????1?????????????:
- \6906 = b[13:13];
- 28'b?????????????1??????????????:
- \6906 = b[14:14];
- 28'b????????????1???????????????:
- \6906 = b[15:15];
- 28'b???????????1????????????????:
- \6906 = b[16:16];
- 28'b??????????1?????????????????:
- \6906 = b[17:17];
- 28'b?????????1??????????????????:
- \6906 = b[18:18];
- 28'b????????1???????????????????:
- \6906 = b[19:19];
- 28'b???????1????????????????????:
- \6906 = b[20:20];
- 28'b??????1?????????????????????:
- \6906 = b[21:21];
- 28'b?????1??????????????????????:
- \6906 = b[22:22];
- 28'b????1???????????????????????:
- \6906 = b[23:23];
- 28'b???1????????????????????????:
- \6906 = b[24:24];
- 28'b??1?????????????????????????:
- \6906 = b[25:25];
- 28'b?1??????????????????????????:
- \6906 = b[26:26];
- 28'b1???????????????????????????:
- \6906 = b[27:27];
- default:
- \6906 = a;
- endcase
- endfunction
- assign _0589_ = \6906 (1'h0, 28'h8000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6909 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6909 = b[0:0];
- 28'b??????????????????????????1?:
- \6909 = b[1:1];
- 28'b?????????????????????????1??:
- \6909 = b[2:2];
- 28'b????????????????????????1???:
- \6909 = b[3:3];
- 28'b???????????????????????1????:
- \6909 = b[4:4];
- 28'b??????????????????????1?????:
- \6909 = b[5:5];
- 28'b?????????????????????1??????:
- \6909 = b[6:6];
- 28'b????????????????????1???????:
- \6909 = b[7:7];
- 28'b???????????????????1????????:
- \6909 = b[8:8];
- 28'b??????????????????1?????????:
- \6909 = b[9:9];
- 28'b?????????????????1??????????:
- \6909 = b[10:10];
- 28'b????????????????1???????????:
- \6909 = b[11:11];
- 28'b???????????????1????????????:
- \6909 = b[12:12];
- 28'b??????????????1?????????????:
- \6909 = b[13:13];
- 28'b?????????????1??????????????:
- \6909 = b[14:14];
- 28'b????????????1???????????????:
- \6909 = b[15:15];
- 28'b???????????1????????????????:
- \6909 = b[16:16];
- 28'b??????????1?????????????????:
- \6909 = b[17:17];
- 28'b?????????1??????????????????:
- \6909 = b[18:18];
- 28'b????????1???????????????????:
- \6909 = b[19:19];
- 28'b???????1????????????????????:
- \6909 = b[20:20];
- 28'b??????1?????????????????????:
- \6909 = b[21:21];
- 28'b?????1??????????????????????:
- \6909 = b[22:22];
- 28'b????1???????????????????????:
- \6909 = b[23:23];
- 28'b???1????????????????????????:
- \6909 = b[24:24];
- 28'b??1?????????????????????????:
- \6909 = b[25:25];
- 28'b?1??????????????????????????:
- \6909 = b[26:26];
- 28'b1???????????????????????????:
- \6909 = b[27:27];
- default:
- \6909 = a;
- endcase
- endfunction
- assign _0590_ = \6909 (1'h1, { 4'h3, _0541_[0], 18'h3ffbf, _0146_[0], 4'hf }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [1:0] \6913 ;
- input [1:0] a;
- input [55:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6913 = b[1:0];
- 28'b??????????????????????????1?:
- \6913 = b[3:2];
- 28'b?????????????????????????1??:
- \6913 = b[5:4];
- 28'b????????????????????????1???:
- \6913 = b[7:6];
- 28'b???????????????????????1????:
- \6913 = b[9:8];
- 28'b??????????????????????1?????:
- \6913 = b[11:10];
- 28'b?????????????????????1??????:
- \6913 = b[13:12];
- 28'b????????????????????1???????:
- \6913 = b[15:14];
- 28'b???????????????????1????????:
- \6913 = b[17:16];
- 28'b??????????????????1?????????:
- \6913 = b[19:18];
- 28'b?????????????????1??????????:
- \6913 = b[21:20];
- 28'b????????????????1???????????:
- \6913 = b[23:22];
- 28'b???????????????1????????????:
- \6913 = b[25:24];
- 28'b??????????????1?????????????:
- \6913 = b[27:26];
- 28'b?????????????1??????????????:
- \6913 = b[29:28];
- 28'b????????????1???????????????:
- \6913 = b[31:30];
- 28'b???????????1????????????????:
- \6913 = b[33:32];
- 28'b??????????1?????????????????:
- \6913 = b[35:34];
- 28'b?????????1??????????????????:
- \6913 = b[37:36];
- 28'b????????1???????????????????:
- \6913 = b[39:38];
- 28'b???????1????????????????????:
- \6913 = b[41:40];
- 28'b??????1?????????????????????:
- \6913 = b[43:42];
- 28'b?????1??????????????????????:
- \6913 = b[45:44];
- 28'b????1???????????????????????:
- \6913 = b[47:46];
- 28'b???1????????????????????????:
- \6913 = b[49:48];
- 28'b??1?????????????????????????:
- \6913 = b[51:50];
- 28'b?1??????????????????????????:
- \6913 = b[53:52];
- 28'b1???????????????????????????:
- \6913 = b[55:54];
- default:
- \6913 = a;
- endcase
- endfunction
- assign _0591_ = \6913 (2'h0, { 8'h00, _0541_[2:1], 36'h000000000, _0146_[2:1], 8'h00 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [5:0] \6916 ;
- input [5:0] a;
- input [167:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6916 = b[5:0];
- 28'b??????????????????????????1?:
- \6916 = b[11:6];
- 28'b?????????????????????????1??:
- \6916 = b[17:12];
- 28'b????????????????????????1???:
- \6916 = b[23:18];
- 28'b???????????????????????1????:
- \6916 = b[29:24];
- 28'b??????????????????????1?????:
- \6916 = b[35:30];
- 28'b?????????????????????1??????:
- \6916 = b[41:36];
- 28'b????????????????????1???????:
- \6916 = b[47:42];
- 28'b???????????????????1????????:
- \6916 = b[53:48];
- 28'b??????????????????1?????????:
- \6916 = b[59:54];
- 28'b?????????????????1??????????:
- \6916 = b[65:60];
- 28'b????????????????1???????????:
- \6916 = b[71:66];
- 28'b???????????????1????????????:
- \6916 = b[77:72];
- 28'b??????????????1?????????????:
- \6916 = b[83:78];
- 28'b?????????????1??????????????:
- \6916 = b[89:84];
- 28'b????????????1???????????????:
- \6916 = b[95:90];
- 28'b???????????1????????????????:
- \6916 = b[101:96];
- 28'b??????????1?????????????????:
- \6916 = b[107:102];
- 28'b?????????1??????????????????:
- \6916 = b[113:108];
- 28'b????????1???????????????????:
- \6916 = b[119:114];
- 28'b???????1????????????????????:
- \6916 = b[125:120];
- 28'b??????1?????????????????????:
- \6916 = b[131:126];
- 28'b?????1??????????????????????:
- \6916 = b[137:132];
- 28'b????1???????????????????????:
- \6916 = b[143:138];
- 28'b???1????????????????????????:
- \6916 = b[149:144];
- 28'b??1?????????????????????????:
- \6916 = b[155:150];
- 28'b?1??????????????????????????:
- \6916 = b[161:156];
- 28'b1???????????????????????????:
- \6916 = b[167:162];
- default:
- \6916 = a;
- endcase
- endfunction
- assign _0592_ = \6916 (e_in[78:73], { e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], _0541_[8:3], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], _0189_, _0166_, e_in[78:73], e_in[78:73], _0146_[8:3], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [63:0] \6920 ;
- input [63:0] a;
- input [1791:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6920 = b[63:0];
- 28'b??????????????????????????1?:
- \6920 = b[127:64];
- 28'b?????????????????????????1??:
- \6920 = b[191:128];
- 28'b????????????????????????1???:
- \6920 = b[255:192];
- 28'b???????????????????????1????:
- \6920 = b[319:256];
- 28'b??????????????????????1?????:
- \6920 = b[383:320];
- 28'b?????????????????????1??????:
- \6920 = b[447:384];
- 28'b????????????????????1???????:
- \6920 = b[511:448];
- 28'b???????????????????1????????:
- \6920 = b[575:512];
- 28'b??????????????????1?????????:
- \6920 = b[639:576];
- 28'b?????????????????1??????????:
- \6920 = b[703:640];
- 28'b????????????????1???????????:
- \6920 = b[767:704];
- 28'b???????????????1????????????:
- \6920 = b[831:768];
- 28'b??????????????1?????????????:
- \6920 = b[895:832];
- 28'b?????????????1??????????????:
- \6920 = b[959:896];
- 28'b????????????1???????????????:
- \6920 = b[1023:960];
- 28'b???????????1????????????????:
- \6920 = b[1087:1024];
- 28'b??????????1?????????????????:
- \6920 = b[1151:1088];
- 28'b?????????1??????????????????:
- \6920 = b[1215:1152];
- 28'b????????1???????????????????:
- \6920 = b[1279:1216];
- 28'b???????1????????????????????:
- \6920 = b[1343:1280];
- 28'b??????1?????????????????????:
- \6920 = b[1407:1344];
- 28'b?????1??????????????????????:
- \6920 = b[1471:1408];
- 28'b????1???????????????????????:
- \6920 = b[1535:1472];
- 28'b???1????????????????????????:
- \6920 = b[1599:1536];
- 28'b??1?????????????????????????:
- \6920 = b[1663:1600];
- 28'b?1??????????????????????????:
- \6920 = b[1727:1664];
- 28'b1???????????????????????????:
- \6920 = b[1791:1728];
- default:
- \6920 = a;
- endcase
- endfunction
- assign _0593_ = \6920 (64'h0000000000000000, { 256'h0000000000000000000000000000000000000000000000000000000000000000, _0541_[72:9], 1152'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _0146_[72:9], 256'h0000000000000000000000000000000000000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6925 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6925 = b[0:0];
- 28'b??????????????????????????1?:
- \6925 = b[1:1];
- 28'b?????????????????????????1??:
- \6925 = b[2:2];
- 28'b????????????????????????1???:
- \6925 = b[3:3];
- 28'b???????????????????????1????:
- \6925 = b[4:4];
- 28'b??????????????????????1?????:
- \6925 = b[5:5];
- 28'b?????????????????????1??????:
- \6925 = b[6:6];
- 28'b????????????????????1???????:
- \6925 = b[7:7];
- 28'b???????????????????1????????:
- \6925 = b[8:8];
- 28'b??????????????????1?????????:
- \6925 = b[9:9];
- 28'b?????????????????1??????????:
- \6925 = b[10:10];
- 28'b????????????????1???????????:
- \6925 = b[11:11];
- 28'b???????????????1????????????:
- \6925 = b[12:12];
- 28'b??????????????1?????????????:
- \6925 = b[13:13];
- 28'b?????????????1??????????????:
- \6925 = b[14:14];
- 28'b????????????1???????????????:
- \6925 = b[15:15];
- 28'b???????????1????????????????:
- \6925 = b[16:16];
- 28'b??????????1?????????????????:
- \6925 = b[17:17];
- 28'b?????????1??????????????????:
- \6925 = b[18:18];
- 28'b????????1???????????????????:
- \6925 = b[19:19];
- 28'b???????1????????????????????:
- \6925 = b[20:20];
- 28'b??????1?????????????????????:
- \6925 = b[21:21];
- 28'b?????1??????????????????????:
- \6925 = b[22:22];
- 28'b????1???????????????????????:
- \6925 = b[23:23];
- 28'b???1????????????????????????:
- \6925 = b[24:24];
- 28'b??1?????????????????????????:
- \6925 = b[25:25];
- 28'b?1??????????????????????????:
- \6925 = b[26:26];
- 28'b1???????????????????????????:
- \6925 = b[27:27];
- default:
- \6925 = a;
- endcase
- endfunction
- assign _0594_ = \6925 (1'h0, { 4'h0, _0541_[73], 8'h08, _0346_[0], 9'h000, _0147_[0], 4'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [7:0] \6930 ;
- input [7:0] a;
- input [223:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6930 = b[7:0];
- 28'b??????????????????????????1?:
- \6930 = b[15:8];
- 28'b?????????????????????????1??:
- \6930 = b[23:16];
- 28'b????????????????????????1???:
- \6930 = b[31:24];
- 28'b???????????????????????1????:
- \6930 = b[39:32];
- 28'b??????????????????????1?????:
- \6930 = b[47:40];
- 28'b?????????????????????1??????:
- \6930 = b[55:48];
- 28'b????????????????????1???????:
- \6930 = b[63:56];
- 28'b???????????????????1????????:
- \6930 = b[71:64];
- 28'b??????????????????1?????????:
- \6930 = b[79:72];
- 28'b?????????????????1??????????:
- \6930 = b[87:80];
- 28'b????????????????1???????????:
- \6930 = b[95:88];
- 28'b???????????????1????????????:
- \6930 = b[103:96];
- 28'b??????????????1?????????????:
- \6930 = b[111:104];
- 28'b?????????????1??????????????:
- \6930 = b[119:112];
- 28'b????????????1???????????????:
- \6930 = b[127:120];
- 28'b???????????1????????????????:
- \6930 = b[135:128];
- 28'b??????????1?????????????????:
- \6930 = b[143:136];
- 28'b?????????1??????????????????:
- \6930 = b[151:144];
- 28'b????????1???????????????????:
- \6930 = b[159:152];
- 28'b???????1????????????????????:
- \6930 = b[167:160];
- 28'b??????1?????????????????????:
- \6930 = b[175:168];
- 28'b?????1??????????????????????:
- \6930 = b[183:176];
- 28'b????1???????????????????????:
- \6930 = b[191:184];
- 28'b???1????????????????????????:
- \6930 = b[199:192];
- 28'b??1?????????????????????????:
- \6930 = b[207:200];
- 28'b?1??????????????????????????:
- \6930 = b[215:208];
- 28'b1???????????????????????????:
- \6930 = b[223:216];
- default:
- \6930 = a;
- endcase
- endfunction
- assign _0595_ = \6930 (8'h00, { 32'h00000000, _0541_[81:74], 32'h00000000, _0516_, 24'h000000, _0346_[8:1], 72'h000000000000000000, _0147_[8:1], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [31:0] \6935 ;
- input [31:0] a;
- input [895:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6935 = b[31:0];
- 28'b??????????????????????????1?:
- \6935 = b[63:32];
- 28'b?????????????????????????1??:
- \6935 = b[95:64];
- 28'b????????????????????????1???:
- \6935 = b[127:96];
- 28'b???????????????????????1????:
- \6935 = b[159:128];
- 28'b??????????????????????1?????:
- \6935 = b[191:160];
- 28'b?????????????????????1??????:
- \6935 = b[223:192];
- 28'b????????????????????1???????:
- \6935 = b[255:224];
- 28'b???????????????????1????????:
- \6935 = b[287:256];
- 28'b??????????????????1?????????:
- \6935 = b[319:288];
- 28'b?????????????????1??????????:
- \6935 = b[351:320];
- 28'b????????????????1???????????:
- \6935 = b[383:352];
- 28'b???????????????1????????????:
- \6935 = b[415:384];
- 28'b??????????????1?????????????:
- \6935 = b[447:416];
- 28'b?????????????1??????????????:
- \6935 = b[479:448];
- 28'b????????????1???????????????:
- \6935 = b[511:480];
- 28'b???????????1????????????????:
- \6935 = b[543:512];
- 28'b??????????1?????????????????:
- \6935 = b[575:544];
- 28'b?????????1??????????????????:
- \6935 = b[607:576];
- 28'b????????1???????????????????:
- \6935 = b[639:608];
- 28'b???????1????????????????????:
- \6935 = b[671:640];
- 28'b??????1?????????????????????:
- \6935 = b[703:672];
- 28'b?????1??????????????????????:
- \6935 = b[735:704];
- 28'b????1???????????????????????:
- \6935 = b[767:736];
- 28'b???1????????????????????????:
- \6935 = b[799:768];
- 28'b??1?????????????????????????:
- \6935 = b[831:800];
- 28'b?1??????????????????????????:
- \6935 = b[863:832];
- 28'b1???????????????????????????:
- \6935 = b[895:864];
- default:
- \6935 = a;
- endcase
- endfunction
- assign _0596_ = \6935 (32'd0, { 128'h00000000000000000000000000000000, _0541_[113:82], 128'h00000000000000000000000000000000, c_in[31:0], 96'h000000000000000000000000, _0346_[40:9], 288'h000000000000000000000000000000000000000000000000000000000000000000000000, _0147_[40:9], 128'h00000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [5:0] \6940 ;
- input [5:0] a;
- input [167:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6940 = b[5:0];
- 28'b??????????????????????????1?:
- \6940 = b[11:6];
- 28'b?????????????????????????1??:
- \6940 = b[17:12];
- 28'b????????????????????????1???:
- \6940 = b[23:18];
- 28'b???????????????????????1????:
- \6940 = b[29:24];
- 28'b??????????????????????1?????:
- \6940 = b[35:30];
- 28'b?????????????????????1??????:
- \6940 = b[41:36];
- 28'b????????????????????1???????:
- \6940 = b[47:42];
- 28'b???????????????????1????????:
- \6940 = b[53:48];
- 28'b??????????????????1?????????:
- \6940 = b[59:54];
- 28'b?????????????????1??????????:
- \6940 = b[65:60];
- 28'b????????????????1???????????:
- \6940 = b[71:66];
- 28'b???????????????1????????????:
- \6940 = b[77:72];
- 28'b??????????????1?????????????:
- \6940 = b[83:78];
- 28'b?????????????1??????????????:
- \6940 = b[89:84];
- 28'b????????????1???????????????:
- \6940 = b[95:90];
- 28'b???????????1????????????????:
- \6940 = b[101:96];
- 28'b??????????1?????????????????:
- \6940 = b[107:102];
- 28'b?????????1??????????????????:
- \6940 = b[113:108];
- 28'b????????1???????????????????:
- \6940 = b[119:114];
- 28'b???????1????????????????????:
- \6940 = b[125:120];
- 28'b??????1?????????????????????:
- \6940 = b[131:126];
- 28'b?????1??????????????????????:
- \6940 = b[137:132];
- 28'b????1???????????????????????:
- \6940 = b[143:138];
- 28'b???1????????????????????????:
- \6940 = b[149:144];
- 28'b??1?????????????????????????:
- \6940 = b[155:150];
- 28'b?1??????????????????????????:
- \6940 = b[161:156];
- 28'b1???????????????????????????:
- \6940 = b[167:162];
- default:
- \6940 = a;
- endcase
- endfunction
- assign _0597_ = \6940 ({ _0013_, 1'h0 }, { _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0541_[119:114], _0013_, 1'h0, _0013_, 1'h0, _0534_, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0148_[5:0], _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [70:0] \6944 ;
- input [70:0] a;
- input [1987:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6944 = b[70:0];
- 28'b??????????????????????????1?:
- \6944 = b[141:71];
- 28'b?????????????????????????1??:
- \6944 = b[212:142];
- 28'b????????????????????????1???:
- \6944 = b[283:213];
- 28'b???????????????????????1????:
- \6944 = b[354:284];
- 28'b??????????????????????1?????:
- \6944 = b[425:355];
- 28'b?????????????????????1??????:
- \6944 = b[496:426];
- 28'b????????????????????1???????:
- \6944 = b[567:497];
- 28'b???????????????????1????????:
- \6944 = b[638:568];
- 28'b??????????????????1?????????:
- \6944 = b[709:639];
- 28'b?????????????????1??????????:
- \6944 = b[780:710];
- 28'b????????????????1???????????:
- \6944 = b[851:781];
- 28'b???????????????1????????????:
- \6944 = b[922:852];
- 28'b??????????????1?????????????:
- \6944 = b[993:923];
- 28'b?????????????1??????????????:
- \6944 = b[1064:994];
- 28'b????????????1???????????????:
- \6944 = b[1135:1065];
- 28'b???????????1????????????????:
- \6944 = b[1206:1136];
- 28'b??????????1?????????????????:
- \6944 = b[1277:1207];
- 28'b?????????1??????????????????:
- \6944 = b[1348:1278];
- 28'b????????1???????????????????:
- \6944 = b[1419:1349];
- 28'b???????1????????????????????:
- \6944 = b[1490:1420];
- 28'b??????1?????????????????????:
- \6944 = b[1561:1491];
- 28'b?????1??????????????????????:
- \6944 = b[1632:1562];
- 28'b????1???????????????????????:
- \6944 = b[1703:1633];
- 28'b???1????????????????????????:
- \6944 = b[1774:1704];
- 28'b??1?????????????????????????:
- \6944 = b[1845:1775];
- 28'b?1??????????????????????????:
- \6944 = b[1916:1846];
- 28'b1???????????????????????????:
- \6944 = b[1987:1917];
- default:
- \6944 = a;
- endcase
- endfunction
- assign _0598_ = \6944 ({ e_in[72:9], 7'h44 }, { e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, _0541_[190:120], e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, _0148_[76:6], e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6945 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6945 = b[0:0];
- 28'b??????????????????????????1?:
- \6945 = b[1:1];
- 28'b?????????????????????????1??:
- \6945 = b[2:2];
- 28'b????????????????????????1???:
- \6945 = b[3:3];
- 28'b???????????????????????1????:
- \6945 = b[4:4];
- 28'b??????????????????????1?????:
- \6945 = b[5:5];
- 28'b?????????????????????1??????:
- \6945 = b[6:6];
- 28'b????????????????????1???????:
- \6945 = b[7:7];
- 28'b???????????????????1????????:
- \6945 = b[8:8];
- 28'b??????????????????1?????????:
- \6945 = b[9:9];
- 28'b?????????????????1??????????:
- \6945 = b[10:10];
- 28'b????????????????1???????????:
- \6945 = b[11:11];
- 28'b???????????????1????????????:
- \6945 = b[12:12];
- 28'b??????????????1?????????????:
- \6945 = b[13:13];
- 28'b?????????????1??????????????:
- \6945 = b[14:14];
- 28'b????????????1???????????????:
- \6945 = b[15:15];
- 28'b???????????1????????????????:
- \6945 = b[16:16];
- 28'b??????????1?????????????????:
- \6945 = b[17:17];
- 28'b?????????1??????????????????:
- \6945 = b[18:18];
- 28'b????????1???????????????????:
- \6945 = b[19:19];
- 28'b???????1????????????????????:
- \6945 = b[20:20];
- 28'b??????1?????????????????????:
- \6945 = b[21:21];
- 28'b?????1??????????????????????:
- \6945 = b[22:22];
- 28'b????1???????????????????????:
- \6945 = b[23:23];
- 28'b???1????????????????????????:
- \6945 = b[24:24];
- 28'b??1?????????????????????????:
- \6945 = b[25:25];
- 28'b?1??????????????????????????:
- \6945 = b[26:26];
- 28'b1???????????????????????????:
- \6945 = b[27:27];
- default:
- \6945 = a;
- endcase
- endfunction
- assign _0599_ = \6945 (1'h0, 28'h4000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6946 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6946 = b[0:0];
- 28'b??????????????????????????1?:
- \6946 = b[1:1];
- 28'b?????????????????????????1??:
- \6946 = b[2:2];
- 28'b????????????????????????1???:
- \6946 = b[3:3];
- 28'b???????????????????????1????:
- \6946 = b[4:4];
- 28'b??????????????????????1?????:
- \6946 = b[5:5];
- 28'b?????????????????????1??????:
- \6946 = b[6:6];
- 28'b????????????????????1???????:
- \6946 = b[7:7];
- 28'b???????????????????1????????:
- \6946 = b[8:8];
- 28'b??????????????????1?????????:
- \6946 = b[9:9];
- 28'b?????????????????1??????????:
- \6946 = b[10:10];
- 28'b????????????????1???????????:
- \6946 = b[11:11];
- 28'b???????????????1????????????:
- \6946 = b[12:12];
- 28'b??????????????1?????????????:
- \6946 = b[13:13];
- 28'b?????????????1??????????????:
- \6946 = b[14:14];
- 28'b????????????1???????????????:
- \6946 = b[15:15];
- 28'b???????????1????????????????:
- \6946 = b[16:16];
- 28'b??????????1?????????????????:
- \6946 = b[17:17];
- 28'b?????????1??????????????????:
- \6946 = b[18:18];
- 28'b????????1???????????????????:
- \6946 = b[19:19];
- 28'b???????1????????????????????:
- \6946 = b[20:20];
- 28'b??????1?????????????????????:
- \6946 = b[21:21];
- 28'b?????1??????????????????????:
- \6946 = b[22:22];
- 28'b????1???????????????????????:
- \6946 = b[23:23];
- 28'b???1????????????????????????:
- \6946 = b[24:24];
- 28'b??1?????????????????????????:
- \6946 = b[25:25];
- 28'b?1??????????????????????????:
- \6946 = b[26:26];
- 28'b1???????????????????????????:
- \6946 = b[27:27];
- default:
- \6946 = a;
- endcase
- endfunction
- assign _0600_ = \6946 (1'h0, 28'h8000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \6947 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6947 = b[0:0];
- 28'b??????????????????????????1?:
- \6947 = b[1:1];
- 28'b?????????????????????????1??:
- \6947 = b[2:2];
- 28'b????????????????????????1???:
- \6947 = b[3:3];
- 28'b???????????????????????1????:
- \6947 = b[4:4];
- 28'b??????????????????????1?????:
- \6947 = b[5:5];
- 28'b?????????????????????1??????:
- \6947 = b[6:6];
- 28'b????????????????????1???????:
- \6947 = b[7:7];
- 28'b???????????????????1????????:
- \6947 = b[8:8];
- 28'b??????????????????1?????????:
- \6947 = b[9:9];
- 28'b?????????????????1??????????:
- \6947 = b[10:10];
- 28'b????????????????1???????????:
- \6947 = b[11:11];
- 28'b???????????????1????????????:
- \6947 = b[12:12];
- 28'b??????????????1?????????????:
- \6947 = b[13:13];
- 28'b?????????????1??????????????:
- \6947 = b[14:14];
- 28'b????????????1???????????????:
- \6947 = b[15:15];
- 28'b???????????1????????????????:
- \6947 = b[16:16];
- 28'b??????????1?????????????????:
- \6947 = b[17:17];
- 28'b?????????1??????????????????:
- \6947 = b[18:18];
- 28'b????????1???????????????????:
- \6947 = b[19:19];
- 28'b???????1????????????????????:
- \6947 = b[20:20];
- 28'b??????1?????????????????????:
- \6947 = b[21:21];
- 28'b?????1??????????????????????:
- \6947 = b[22:22];
- 28'b????1???????????????????????:
- \6947 = b[23:23];
- 28'b???1????????????????????????:
- \6947 = b[24:24];
- 28'b??1?????????????????????????:
- \6947 = b[25:25];
- 28'b?1??????????????????????????:
- \6947 = b[26:26];
- 28'b1???????????????????????????:
- \6947 = b[27:27];
- default:
- \6947 = a;
- endcase
- endfunction
- assign _0601_ = \6947 (1'h0, 28'h0000800, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [7:0] \6963 ;
- input [7:0] a;
- input [223:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6963 = b[7:0];
- 28'b??????????????????????????1?:
- \6963 = b[15:8];
- 28'b?????????????????????????1??:
- \6963 = b[23:16];
- 28'b????????????????????????1???:
- \6963 = b[31:24];
- 28'b???????????????????????1????:
- \6963 = b[39:32];
- 28'b??????????????????????1?????:
- \6963 = b[47:40];
- 28'b?????????????????????1??????:
- \6963 = b[55:48];
- 28'b????????????????????1???????:
- \6963 = b[63:56];
- 28'b???????????????????1????????:
- \6963 = b[71:64];
- 28'b??????????????????1?????????:
- \6963 = b[79:72];
- 28'b?????????????????1??????????:
- \6963 = b[87:80];
- 28'b????????????????1???????????:
- \6963 = b[95:88];
- 28'b???????????????1????????????:
- \6963 = b[103:96];
- 28'b??????????????1?????????????:
- \6963 = b[111:104];
- 28'b?????????????1??????????????:
- \6963 = b[119:112];
- 28'b????????????1???????????????:
- \6963 = b[127:120];
- 28'b???????????1????????????????:
- \6963 = b[135:128];
- 28'b??????????1?????????????????:
- \6963 = b[143:136];
- 28'b?????????1??????????????????:
- \6963 = b[151:144];
- 28'b????????1???????????????????:
- \6963 = b[159:152];
- 28'b???????1????????????????????:
- \6963 = b[167:160];
- 28'b??????1?????????????????????:
- \6963 = b[175:168];
- 28'b?????1??????????????????????:
- \6963 = b[183:176];
- 28'b????1???????????????????????:
- \6963 = b[191:184];
- 28'b???1????????????????????????:
- \6963 = b[199:192];
- 28'b??1?????????????????????????:
- \6963 = b[207:200];
- 28'b?1??????????????????????????:
- \6963 = b[215:208];
- 28'b1???????????????????????????:
- \6963 = b[223:216];
- default:
- \6963 = a;
- endcase
- endfunction
- assign _0602_ = \6963 (8'h00, { 32'h00000000, rotator_result[7:0], parity_result[7:0], popcnt_result[7:0], _0535_[7:0], 16'h0000, _0440_[7:0], _0356_[7:0], ctrl[135:128], 8'h00, _0239_[7:0], c_in[7:0], 8'h00, _0212_, 8'h00, _0190_[7:0], _0167_[7:0], 8'h00, logical_result[7:0], _0089_[7:0], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [7:0] \6978 ;
- input [7:0] a;
- input [223:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6978 = b[7:0];
- 28'b??????????????????????????1?:
- \6978 = b[15:8];
- 28'b?????????????????????????1??:
- \6978 = b[23:16];
- 28'b????????????????????????1???:
- \6978 = b[31:24];
- 28'b???????????????????????1????:
- \6978 = b[39:32];
- 28'b??????????????????????1?????:
- \6978 = b[47:40];
- 28'b?????????????????????1??????:
- \6978 = b[55:48];
- 28'b????????????????????1???????:
- \6978 = b[63:56];
- 28'b???????????????????1????????:
- \6978 = b[71:64];
- 28'b??????????????????1?????????:
- \6978 = b[79:72];
- 28'b?????????????????1??????????:
- \6978 = b[87:80];
- 28'b????????????????1???????????:
- \6978 = b[95:88];
- 28'b???????????????1????????????:
- \6978 = b[103:96];
- 28'b??????????????1?????????????:
- \6978 = b[111:104];
- 28'b?????????????1??????????????:
- \6978 = b[119:112];
- 28'b????????????1???????????????:
- \6978 = b[127:120];
- 28'b???????????1????????????????:
- \6978 = b[135:128];
- 28'b??????????1?????????????????:
- \6978 = b[143:136];
- 28'b?????????1??????????????????:
- \6978 = b[151:144];
- 28'b????????1???????????????????:
- \6978 = b[159:152];
- 28'b???????1????????????????????:
- \6978 = b[167:160];
- 28'b??????1?????????????????????:
- \6978 = b[175:168];
- 28'b?????1??????????????????????:
- \6978 = b[183:176];
- 28'b????1???????????????????????:
- \6978 = b[191:184];
- 28'b???1????????????????????????:
- \6978 = b[199:192];
- 28'b??1?????????????????????????:
- \6978 = b[207:200];
- 28'b?1??????????????????????????:
- \6978 = b[215:208];
- 28'b1???????????????????????????:
- \6978 = b[223:216];
- default:
- \6978 = a;
- endcase
- endfunction
- assign _0603_ = \6978 (8'h00, { 32'h00000000, rotator_result[15:8], parity_result[15:8], popcnt_result[15:8], _0535_[15:8], 16'h0000, _0440_[15:8], _0356_[15:8], ctrl[143:136], 8'h00, _0239_[15:8], _0236_, 8'h00, _0214_, 8'h00, _0190_[15:8], _0167_[15:8], 8'h00, logical_result[15:8], _0089_[15:8], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [15:0] \6993 ;
- input [15:0] a;
- input [447:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \6993 = b[15:0];
- 28'b??????????????????????????1?:
- \6993 = b[31:16];
- 28'b?????????????????????????1??:
- \6993 = b[47:32];
- 28'b????????????????????????1???:
- \6993 = b[63:48];
- 28'b???????????????????????1????:
- \6993 = b[79:64];
- 28'b??????????????????????1?????:
- \6993 = b[95:80];
- 28'b?????????????????????1??????:
- \6993 = b[111:96];
- 28'b????????????????????1???????:
- \6993 = b[127:112];
- 28'b???????????????????1????????:
- \6993 = b[143:128];
- 28'b??????????????????1?????????:
- \6993 = b[159:144];
- 28'b?????????????????1??????????:
- \6993 = b[175:160];
- 28'b????????????????1???????????:
- \6993 = b[191:176];
- 28'b???????????????1????????????:
- \6993 = b[207:192];
- 28'b??????????????1?????????????:
- \6993 = b[223:208];
- 28'b?????????????1??????????????:
- \6993 = b[239:224];
- 28'b????????????1???????????????:
- \6993 = b[255:240];
- 28'b???????????1????????????????:
- \6993 = b[271:256];
- 28'b??????????1?????????????????:
- \6993 = b[287:272];
- 28'b?????????1??????????????????:
- \6993 = b[303:288];
- 28'b????????1???????????????????:
- \6993 = b[319:304];
- 28'b???????1????????????????????:
- \6993 = b[335:320];
- 28'b??????1?????????????????????:
- \6993 = b[351:336];
- 28'b?????1??????????????????????:
- \6993 = b[367:352];
- 28'b????1???????????????????????:
- \6993 = b[383:368];
- 28'b???1????????????????????????:
- \6993 = b[399:384];
- 28'b??1?????????????????????????:
- \6993 = b[415:400];
- 28'b?1??????????????????????????:
- \6993 = b[431:416];
- 28'b1???????????????????????????:
- \6993 = b[447:432];
- default:
- \6993 = a;
- endcase
- endfunction
- assign _0604_ = \6993 (16'h0000, { 64'h0000000000000000, rotator_result[31:16], parity_result[31:16], popcnt_result[31:16], _0535_[31:16], 32'h00000000, _0440_[31:16], _0356_[31:16], ctrl[159:144], 16'h0000, _0239_[31:16], _0234_, 16'h0000, _0218_, _0216_, 16'h0000, _0190_[31:16], _0167_[31:16], 16'h0000, logical_result[31:16], _0089_[31:16], 64'h0000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [31:0] \7008 ;
- input [31:0] a;
- input [895:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \7008 = b[31:0];
- 28'b??????????????????????????1?:
- \7008 = b[63:32];
- 28'b?????????????????????????1??:
- \7008 = b[95:64];
- 28'b????????????????????????1???:
- \7008 = b[127:96];
- 28'b???????????????????????1????:
- \7008 = b[159:128];
- 28'b??????????????????????1?????:
- \7008 = b[191:160];
- 28'b?????????????????????1??????:
- \7008 = b[223:192];
- 28'b????????????????????1???????:
- \7008 = b[255:224];
- 28'b???????????????????1????????:
- \7008 = b[287:256];
- 28'b??????????????????1?????????:
- \7008 = b[319:288];
- 28'b?????????????????1??????????:
- \7008 = b[351:320];
- 28'b????????????????1???????????:
- \7008 = b[383:352];
- 28'b???????????????1????????????:
- \7008 = b[415:384];
- 28'b??????????????1?????????????:
- \7008 = b[447:416];
- 28'b?????????????1??????????????:
- \7008 = b[479:448];
- 28'b????????????1???????????????:
- \7008 = b[511:480];
- 28'b???????????1????????????????:
- \7008 = b[543:512];
- 28'b??????????1?????????????????:
- \7008 = b[575:544];
- 28'b?????????1??????????????????:
- \7008 = b[607:576];
- 28'b????????1???????????????????:
- \7008 = b[639:608];
- 28'b???????1????????????????????:
- \7008 = b[671:640];
- 28'b??????1?????????????????????:
- \7008 = b[703:672];
- 28'b?????1??????????????????????:
- \7008 = b[735:704];
- 28'b????1???????????????????????:
- \7008 = b[767:736];
- 28'b???1????????????????????????:
- \7008 = b[799:768];
- 28'b??1?????????????????????????:
- \7008 = b[831:800];
- 28'b?1??????????????????????????:
- \7008 = b[863:832];
- 28'b1???????????????????????????:
- \7008 = b[895:864];
- default:
- \7008 = a;
- endcase
- endfunction
- assign _0605_ = \7008 (32'd0, { 128'h00000000000000000000000000000000, rotator_result[63:32], parity_result[63:32], popcnt_result[63:32], _0535_[63:32], 64'h0000000000000000, _0440_[63:32], _0356_[63:32], ctrl[191:160], 32'h00000000, _0239_[63:32], _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, 32'h00000000, _0226_, _0224_, _0222_, _0220_, 32'h00000000, _0190_[63:32], _0167_[63:32], 32'h00000000, logical_result[63:32], _0089_[63:32], 128'h00000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \7024 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \7024 = b[0:0];
- 28'b??????????????????????????1?:
- \7024 = b[1:1];
- 28'b?????????????????????????1??:
- \7024 = b[2:2];
- 28'b????????????????????????1???:
- \7024 = b[3:3];
- 28'b???????????????????????1????:
- \7024 = b[4:4];
- 28'b??????????????????????1?????:
- \7024 = b[5:5];
- 28'b?????????????????????1??????:
- \7024 = b[6:6];
- 28'b????????????????????1???????:
- \7024 = b[7:7];
- 28'b???????????????????1????????:
- \7024 = b[8:8];
- 28'b??????????????????1?????????:
- \7024 = b[9:9];
- 28'b?????????????????1??????????:
- \7024 = b[10:10];
- 28'b????????????????1???????????:
- \7024 = b[11:11];
- 28'b???????????????1????????????:
- \7024 = b[12:12];
- 28'b??????????????1?????????????:
- \7024 = b[13:13];
- 28'b?????????????1??????????????:
- \7024 = b[14:14];
- 28'b????????????1???????????????:
- \7024 = b[15:15];
- 28'b???????????1????????????????:
- \7024 = b[16:16];
- 28'b??????????1?????????????????:
- \7024 = b[17:17];
- 28'b?????????1??????????????????:
- \7024 = b[18:18];
- 28'b????????1???????????????????:
- \7024 = b[19:19];
- 28'b???????1????????????????????:
- \7024 = b[20:20];
- 28'b??????1?????????????????????:
- \7024 = b[21:21];
- 28'b?????1??????????????????????:
- \7024 = b[22:22];
- 28'b????1???????????????????????:
- \7024 = b[23:23];
- 28'b???1????????????????????????:
- \7024 = b[24:24];
- 28'b??1?????????????????????????:
- \7024 = b[25:25];
- 28'b?1??????????????????????????:
- \7024 = b[26:26];
- 28'b1???????????????????????????:
- \7024 = b[27:27];
- default:
- \7024 = a;
- endcase
- endfunction
- assign _0606_ = \7024 (1'h0, { 7'h07, _0536_, 11'h1da, _0191_, _0168_, 2'h1, _0149_, 4'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \7053 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \7053 = b[0:0];
- 28'b??????????????????????????1?:
- \7053 = b[1:1];
- 28'b?????????????????????????1??:
- \7053 = b[2:2];
- 28'b????????????????????????1???:
- \7053 = b[3:3];
- 28'b???????????????????????1????:
- \7053 = b[4:4];
- 28'b??????????????????????1?????:
- \7053 = b[5:5];
- 28'b?????????????????????1??????:
- \7053 = b[6:6];
- 28'b????????????????????1???????:
- \7053 = b[7:7];
- 28'b???????????????????1????????:
- \7053 = b[8:8];
- 28'b??????????????????1?????????:
- \7053 = b[9:9];
- 28'b?????????????????1??????????:
- \7053 = b[10:10];
- 28'b????????????????1???????????:
- \7053 = b[11:11];
- 28'b???????????????1????????????:
- \7053 = b[12:12];
- 28'b??????????????1?????????????:
- \7053 = b[13:13];
- 28'b?????????????1??????????????:
- \7053 = b[14:14];
- 28'b????????????1???????????????:
- \7053 = b[15:15];
- 28'b???????????1????????????????:
- \7053 = b[16:16];
- 28'b??????????1?????????????????:
- \7053 = b[17:17];
- 28'b?????????1??????????????????:
- \7053 = b[18:18];
- 28'b????????1???????????????????:
- \7053 = b[19:19];
- 28'b???????1????????????????????:
- \7053 = b[20:20];
- 28'b??????1?????????????????????:
- \7053 = b[21:21];
- 28'b?????1??????????????????????:
- \7053 = b[22:22];
- 28'b????1???????????????????????:
- \7053 = b[23:23];
- 28'b???1????????????????????????:
- \7053 = b[24:24];
- 28'b??1?????????????????????????:
- \7053 = b[25:25];
- 28'b?1??????????????????????????:
- \7053 = b[26:26];
- 28'b1???????????????????????????:
- \7053 = b[27:27];
- default:
- \7053 = a;
- endcase
- endfunction
- assign _0607_ = \7053 (1'h0, { 23'h000000, _0150_, 2'h0, _0072_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \7055 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \7055 = b[0:0];
- 28'b??????????????????????????1?:
- \7055 = b[1:1];
- 28'b?????????????????????????1??:
- \7055 = b[2:2];
- 28'b????????????????????????1???:
- \7055 = b[3:3];
- 28'b???????????????????????1????:
- \7055 = b[4:4];
- 28'b??????????????????????1?????:
- \7055 = b[5:5];
- 28'b?????????????????????1??????:
- \7055 = b[6:6];
- 28'b????????????????????1???????:
- \7055 = b[7:7];
- 28'b???????????????????1????????:
- \7055 = b[8:8];
- 28'b??????????????????1?????????:
- \7055 = b[9:9];
- 28'b?????????????????1??????????:
- \7055 = b[10:10];
- 28'b????????????????1???????????:
- \7055 = b[11:11];
- 28'b???????????????1????????????:
- \7055 = b[12:12];
- 28'b??????????????1?????????????:
- \7055 = b[13:13];
- 28'b?????????????1??????????????:
- \7055 = b[14:14];
- 28'b????????????1???????????????:
- \7055 = b[15:15];
- 28'b???????????1????????????????:
- \7055 = b[16:16];
- 28'b??????????1?????????????????:
- \7055 = b[17:17];
- 28'b?????????1??????????????????:
- \7055 = b[18:18];
- 28'b????????1???????????????????:
- \7055 = b[19:19];
- 28'b???????1????????????????????:
- \7055 = b[20:20];
- 28'b??????1?????????????????????:
- \7055 = b[21:21];
- 28'b?????1??????????????????????:
- \7055 = b[22:22];
- 28'b????1???????????????????????:
- \7055 = b[23:23];
- 28'b???1????????????????????????:
- \7055 = b[24:24];
- 28'b??1?????????????????????????:
- \7055 = b[25:25];
- 28'b?1??????????????????????????:
- \7055 = b[26:26];
- 28'b1???????????????????????????:
- \7055 = b[27:27];
- default:
- \7055 = a;
- endcase
- endfunction
- assign _0608_ = \7055 (1'h0, { 26'h0000000, _0073_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- function [0:0] \7059 ;
- input [0:0] a;
- input [27:0] b;
- input [27:0] s;
- (* parallel_case *)
- casez (s)
- 28'b???????????????????????????1:
- \7059 = b[0:0];
- 28'b??????????????????????????1?:
- \7059 = b[1:1];
- 28'b?????????????????????????1??:
- \7059 = b[2:2];
- 28'b????????????????????????1???:
- \7059 = b[3:3];
- 28'b???????????????????????1????:
- \7059 = b[4:4];
- 28'b??????????????????????1?????:
- \7059 = b[5:5];
- 28'b?????????????????????1??????:
- \7059 = b[6:6];
- 28'b????????????????????1???????:
- \7059 = b[7:7];
- 28'b???????????????????1????????:
- \7059 = b[8:8];
- 28'b??????????????????1?????????:
- \7059 = b[9:9];
- 28'b?????????????????1??????????:
- \7059 = b[10:10];
- 28'b????????????????1???????????:
- \7059 = b[11:11];
- 28'b???????????????1????????????:
- \7059 = b[12:12];
- 28'b??????????????1?????????????:
- \7059 = b[13:13];
- 28'b?????????????1??????????????:
- \7059 = b[14:14];
- 28'b????????????1???????????????:
- \7059 = b[15:15];
- 28'b???????????1????????????????:
- \7059 = b[16:16];
- 28'b??????????1?????????????????:
- \7059 = b[17:17];
- 28'b?????????1??????????????????:
- \7059 = b[18:18];
- 28'b????????1???????????????????:
- \7059 = b[19:19];
- 28'b???????1????????????????????:
- \7059 = b[20:20];
- 28'b??????1?????????????????????:
- \7059 = b[21:21];
- 28'b?????1??????????????????????:
- \7059 = b[22:22];
- 28'b????1???????????????????????:
- \7059 = b[23:23];
- 28'b???1????????????????????????:
- \7059 = b[24:24];
- 28'b??1?????????????????????????:
- \7059 = b[25:25];
- 28'b?1??????????????????????????:
- \7059 = b[26:26];
- 28'b1???????????????????????????:
- \7059 = b[27:27];
- default:
- \7059 = a;
- endcase
- endfunction
- assign _0609_ = \7059 (1'h0, { 7'h00, _0537_, 3'h0, _0357_, 13'h0000, _0078_, _0074_, 1'h1 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
- assign _0610_ = e_in[324] & e_in[0];
- assign _0611_ = e_in[323] ? 1'h1 : _0565_;
- assign _0612_ = e_in[323] ? 1'h0 : _0590_;
- assign _0613_ = e_in[323] ? { _0048_, 1'h1 } : { r[255:192], 1'h0 };
- assign _0614_ = e_in[2:1] == 2'h2;
- assign _0615_ = _0614_ ? 1'h1 : 1'h0;
- assign _0616_ = r[256] | r[257];
- assign _0617_ = r[256] & multiply_to_x[0];
- assign _0618_ = r[257] & divider_to_x[0];
- assign _0619_ = _0617_ | _0618_;
- assign _0620_ = r[256] ? multiply_to_x[64:1] : divider_to_x[64:1];
- assign _0621_ = r[256] ? multiply_to_x[65] : divider_to_x[65];
- assign _0622_ = r[270] | _0621_;
- assign _0623_ = r[265] ? { _0622_, _0621_, _0621_ } : r[270:268];
- assign _0624_ = _0619_ ? 1'h0 : 1'h1;
- assign _0625_ = _0632_ ? { r[264], 1'h1 } : 2'h0;
- assign _0626_ = _0633_ ? { 1'h0, r[263:259] } : 6'h00;
- assign _0627_ = _0619_ ? { _0623_, r[267:265] } : { _0013_, 1'h0 };
- assign _0628_ = _0619_ ? 2'h0 : r[257:256];
- assign _0629_ = _0619_ ? _0620_ : 64'h0000000000000000;
- assign _0630_ = _0619_ ? 1'h1 : 1'h0;
- assign _0631_ = _0616_ ? _0624_ : 1'h0;
- assign _0632_ = _0616_ & _0619_;
- assign _0633_ = _0616_ & _0619_;
- assign _0634_ = _0616_ ? _0627_ : { _0013_, 1'h0 };
- assign _0635_ = _0616_ ? _0628_ : 2'h0;
- assign _0636_ = _0616_ ? _0629_ : 64'h0000000000000000;
- assign _0637_ = _0616_ ? _0630_ : 1'h0;
- assign _0638_ = r[258] ? 1'h0 : _0631_;
- assign _0639_ = r[258] ? { r[264], 1'h1 } : _0625_;
- assign _0640_ = r[258] ? { 1'h0, r[263:259] } : _0626_;
- assign _0641_ = r[258] ? 1'h0 : _0634_[0];
- assign _0642_ = r[258] ? r[270:266] : _0634_[5:1];
- assign _0643_ = r[258] ? 2'h0 : _0635_;
- assign _0644_ = r[258] ? countzero_result : _0636_;
- assign _0645_ = r[258] ? 1'h1 : _0637_;
- assign _0646_ = r[191] ? 1'h0 : _0638_;
- assign _0647_ = r[191] ? 1'h1 : _0639_[0];
- assign _0648_ = r[191] ? 1'h0 : _0639_[1];
- assign _0649_ = r[191] ? 6'h20 : _0640_;
- assign _0650_ = r[191] ? { _0013_, 1'h0 } : { _0642_, _0641_ };
- assign _0651_ = r[191] ? 2'h0 : _0643_;
- assign _0652_ = r[191] ? r[255:192] : _0644_;
- assign _0653_ = r[191] ? 1'h1 : _0645_;
- assign _0654_ = e_in[0] ? 1'h0 : _0646_;
- assign _0655_ = e_in[0] ? 1'h0 : _0647_;
- assign _0656_ = e_in[0] ? 1'h0 : _0648_;
- assign _0657_ = e_in[0] ? 6'h00 : _0649_;
- assign _0658_ = e_in[0] ? { _0013_, 1'h0 } : _0650_;
- assign _0659_ = e_in[0] ? 2'h0 : _0651_;
- assign _0660_ = e_in[0] ? e_in[72:9] : r[334:271];
- assign _0661_ = e_in[0] ? 64'h0000000000000000 : _0652_;
- assign _0662_ = e_in[0] ? 1'h0 : _0653_;
- assign _0663_ = e_in[0] ? _0615_ : 1'h0;
- assign _0664_ = _0069_ ? _0611_ : _0654_;
- assign _0665_ = _0069_ ? { _0569_, _0568_, _0567_, _0566_ } : { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 };
- assign _0666_ = _0069_ ? _0570_ : 1'h0;
- assign _0667_ = _0069_ ? _0571_ : 1'h0;
- assign _0668_ = _0069_ ? { _0586_, _0585_, _0584_, _0583_, _0582_, _0581_, _0580_, _0579_, _0578_, _0577_, _0576_, _0575_, _0574_, _0573_, _0572_ } : { ctrl[191:128], _0040_ };
- assign _0669_ = _0069_ ? _0587_ : { ctrl[320:257], _0045_ };
- assign _0670_ = _0069_ ? _0588_ : 1'h0;
- assign _0671_ = _0069_ ? _0589_ : 1'h0;
- assign _0672_ = _0069_ ? { _0610_, _0612_ } : { _0656_, _0655_ };
- assign _0673_ = _0069_ ? _0591_[1] : 1'h0;
- assign _0674_ = _0069_ ? _0592_ : _0657_;
- assign _0675_ = _0069_ ? { _0596_, _0595_, _0594_, _0593_ } : 105'h000000000000000000000000000;
- assign _0676_ = _0069_ ? _0597_ : _0658_;
- assign _0677_ = _0069_ ? { _0613_, _0598_ } : { r[255:192], 1'h0, e_in[72:9], 7'h44 };
- assign _0678_ = _0069_ ? { _0600_, _0599_ } : _0659_;
- assign _0679_ = _0069_ ? { _0013_, e_in[325:324], e_in[77:73], _0601_ } : { r[270:259], 1'h0 };
- assign _0680_ = _0069_ ? r[334:271] : _0660_;
- assign _0681_ = _0069_ ? { _0605_, _0604_, _0603_, _0602_ } : _0661_;
- assign _0682_ = _0069_ ? _0606_ : _0662_;
- assign _0683_ = _0069_ ? 1'h0 : _0663_;
- assign _0684_ = _0069_ ? _0607_ : 1'h0;
- assign _0685_ = _0069_ ? _0608_ : 1'h0;
- assign _0686_ = _0069_ ? _0609_ : 1'h0;
- assign _0687_ = _0067_ ? 1'h0 : _0664_;
- assign _0688_ = _0067_ ? { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 } : _0665_;
- assign _0689_ = _0067_ ? 1'h0 : _0666_;
- assign _0690_ = _0067_ ? 1'h0 : _0667_;
- assign _0691_ = _0067_ ? { ctrl[191:128], _0040_ } : _0668_;
- assign _0692_ = _0067_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h04, ctrl[143:128], 64'h0000000000000700 } : _0669_;
- assign _0693_ = _0067_ ? 1'h0 : _0670_;
- assign _0694_ = _0067_ ? 1'h0 : _0671_;
- assign _0695_ = _0067_ ? { r[334:259], 3'h0, r[255:192], 1'h0, e_in[72:9], 7'h44, _0013_, 115'h00000000000000000000000000000 } : { _0680_, _0679_, _0678_, _0677_, _0676_, _0675_, _0674_, _0673_, _0672_ };
- assign _0696_ = _0067_ ? 64'h0000000000000000 : _0681_;
- assign _0697_ = _0067_ ? 1'h0 : _0682_;
- assign _0698_ = _0067_ ? 1'h0 : _0683_;
- assign _0699_ = _0067_ ? 1'h1 : _0684_;
- assign _0700_ = _0067_ ? 1'h0 : _0685_;
- assign _0701_ = _0067_ ? 1'h0 : _0686_;
- assign _0702_ = _0058_ ? 1'h0 : _0687_;
- assign _0703_ = _0058_ ? { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 } : _0688_;
- assign _0704_ = _0058_ ? 1'h0 : _0689_;
- assign _0705_ = _0058_ ? 1'h0 : _0690_;
- assign _0706_ = _0058_ ? { ctrl[191:128], _0040_ } : _0691_;
- assign _0707_ = _0058_ ? _0045_ : _0692_[63:0];
- assign _0708_ = _0058_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h00, ctrl[143:128] } : _0692_[127:64];
- assign _0709_ = _0058_ ? 1'h0 : _0693_;
- assign _0710_ = _0058_ ? 1'h0 : _0694_;
- assign _0711_ = _0058_ ? { r[334:259], 3'h0, r[255:192], 1'h0, e_in[72:9], 7'h44, _0013_, 115'h00000000000000000000000000000 } : _0695_;
- assign _0712_ = _0058_ ? 64'h0000000000000000 : _0696_;
- assign _0713_ = _0058_ ? 1'h0 : _0697_;
- assign _0714_ = _0058_ ? 1'h0 : _0698_;
- assign _0715_ = _0058_ ? 1'h1 : _0699_;
- assign _0716_ = _0058_ ? 1'h0 : _0700_;
- assign _0717_ = _0058_ ? 1'h0 : _0701_;
- assign _0718_ = _0057_ ? 1'h0 : _0702_;
- assign _0719_ = _0057_ ? { ctrl[256:193], 3'h5 } : _0703_;
- assign _0720_ = _0057_ ? 1'h0 : _0704_;
- assign _0721_ = _0057_ ? 1'h0 : _0705_;
- assign _0722_ = _0057_ ? _0040_ : _0706_[63:0];
- assign _0723_ = _0057_ ? 2'h1 : _0706_[65:64];
- assign _0724_ = _0057_ ? ctrl[131:130] : _0706_[67:66];
- assign _0725_ = _0057_ ? 2'h0 : _0706_[69:68];
- assign _0726_ = _0057_ ? ctrl[141:134] : _0706_[77:70];
- assign _0727_ = _0057_ ? 2'h0 : _0706_[79:78];
- assign _0728_ = _0057_ ? ctrl[190:144] : _0706_[126:80];
- assign _0729_ = _0057_ ? 1'h1 : _0706_[127];
- assign _0730_ = _0057_ ? { ctrl[320:257], _0045_ } : { _0708_, _0707_ };
- assign _0731_ = _0057_ ? 1'h0 : _0709_;
- assign _0732_ = _0057_ ? 1'h0 : _0710_;
- assign _0733_ = _0057_ ? e_in[0] : _0711_[0];
- assign _0734_ = _0057_ ? { _0013_, 114'h00000000000000000000000000000 } : _0711_[119:1];
- assign _0735_ = _0057_ ? { ctrl[320:257], 7'h47 } : _0711_[190:120];
- assign _0736_ = _0057_ ? { r[334:259], 3'h0, r[255:192], 1'h0 } : _0711_[334:191];
- assign _0737_ = _0057_ ? 64'h0000000000000000 : _0712_;
- assign _0738_ = _0057_ ? 1'h0 : _0713_;
- assign _0739_ = _0057_ ? 1'h0 : _0714_;
- assign _0740_ = _0057_ ? 1'h0 : _0715_;
- assign _0741_ = _0057_ ? 1'h0 : _0716_;
- assign _0742_ = _0057_ ? 1'h0 : _0717_;
- assign _0743_ = _0742_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h08, ctrl[143:128], 64'h0000000000000700 } : _0730_;
- assign _0744_ = _0742_ ? 1'h1 : _0740_;
- assign _0745_ = _0749_ ? _0048_ : _0735_[70:7];
- assign _0746_ = _0744_ ? 1'h1 : 1'h0;
- assign _0747_ = _0744_ ? 1'h1 : _0733_;
- assign _0748_ = _0744_ ? 1'h1 : _0735_[0];
- assign _0749_ = _0744_ & _0741_;
- assign _0750_ = ~ l_in[6];
- assign _0751_ = ~ l_in[5];
- assign _0752_ = _0751_ ? 64'h0000000000000300 : 64'h0000000000000380;
- assign _0753_ = ~ l_in[5];
- assign _0754_ = _0753_ ? 64'h0000000000000400 : 64'h0000000000000480;
- assign _0755_ = _0753_ ? l_in[4:3] : 2'h0;
- assign _0756_ = _0753_ ? l_in[2] : 1'h0;
- assign _0757_ = _0753_ ? l_in[1] : 1'h0;
- assign _0758_ = _0750_ ? _0752_ : _0754_;
- assign _0759_ = _0750_ ? 2'h0 : _0755_;
- assign _0760_ = _0750_ ? 1'h0 : _0756_;
- assign _0761_ = _0750_ ? 1'h0 : _0757_;
- assign _0762_ = l_in[0] ? { ctrl[191:159], _0761_, 1'h0, _0760_, 1'h0, ctrl[154:150], 2'h0, _0759_, 2'h0, ctrl[143:128], _0758_, 1'h1 } : { _0743_, _0746_ };
- assign _0763_ = l_in[0] ? 1'h1 : _0747_;
- assign _0764_ = l_in[0] ? { r[334:271], 7'h45 } : { _0745_, _0735_[6:1], _0748_ };
- assign _0765_ = e_in[366:361] == 6'h1f;
- assign _0766_ = e_in[345:344] == 2'h3;
- assign _0767_ = _0765_ & _0766_;
- assign _0768_ = e_in[340:336] == 5'h15;
- assign _0769_ = _0767_ & _0768_;
- assign _0770_ = _0769_ ? 1'h1 : 1'h0;
- assign _0771_ = ~ ctrl[142];
- reg [0:0] \7795 [61:0];
- initial begin
- \7795 [0] = 1'h0;
- \7795 [1] = 1'h0;
- \7795 [2] = 1'h0;
- \7795 [3] = 1'h1;
- \7795 [4] = 1'h0;
- \7795 [5] = 1'h0;
- \7795 [6] = 1'h0;
- \7795 [7] = 1'h0;
- \7795 [8] = 1'h0;
- \7795 [9] = 1'h0;
- \7795 [10] = 1'h0;
- \7795 [11] = 1'h0;
- \7795 [12] = 1'h1;
- \7795 [13] = 1'h0;
- \7795 [14] = 1'h0;
- \7795 [15] = 1'h0;
- \7795 [16] = 1'h0;
- \7795 [17] = 1'h0;
- \7795 [18] = 1'h0;
- \7795 [19] = 1'h0;
- \7795 [20] = 1'h1;
- \7795 [21] = 1'h0;
- \7795 [22] = 1'h0;
- \7795 [23] = 1'h0;
- \7795 [24] = 1'h1;
- \7795 [25] = 1'h0;
- \7795 [26] = 1'h0;
- \7795 [27] = 1'h0;
- \7795 [28] = 1'h0;
- \7795 [29] = 1'h0;
- \7795 [30] = 1'h0;
- \7795 [31] = 1'h0;
- \7795 [32] = 1'h0;
- \7795 [33] = 1'h0;
- \7795 [34] = 1'h0;
- \7795 [35] = 1'h0;
- \7795 [36] = 1'h0;
- \7795 [37] = 1'h0;
- \7795 [38] = 1'h0;
- \7795 [39] = 1'h0;
- \7795 [40] = 1'h0;
- \7795 [41] = 1'h0;
- \7795 [42] = 1'h0;
- \7795 [43] = 1'h0;
- \7795 [44] = 1'h0;
- \7795 [45] = 1'h0;
- \7795 [46] = 1'h0;
- \7795 [47] = 1'h0;
- \7795 [48] = 1'h0;
- \7795 [49] = 1'h0;
- \7795 [50] = 1'h0;
- \7795 [51] = 1'h0;
- \7795 [52] = 1'h0;
- \7795 [53] = 1'h0;
- \7795 [54] = 1'h0;
- \7795 [55] = 1'h0;
- \7795 [56] = 1'h0;
- \7795 [57] = 1'h1;
- \7795 [58] = 1'h0;
- \7795 [59] = 1'h0;
- \7795 [60] = 1'h0;
- \7795 [61] = 1'h0;
- end
- assign _0773_ = \7795 [_0060_];
- assign _0784_ = _0169_[4] ? _0783_ : _0782_;
- assign _0795_ = _0192_[4] ? _0794_ : _0793_;
- assign _0806_ = _0238_[4] ? _0805_ : _0804_;
- assign _0817_ = _0268_[4] ? _0816_ : _0815_;
- assign _0828_ = _0269_[4] ? _0827_ : _0826_;
- assign _0831_ = _0270_[0] ? e_in[345] : e_in[344];
- assign _0832_ = _0270_[2] ? _0830_ : _0829_;
- assign _0833_ = _0270_[3] ? _0831_ : _0832_;
- zero_counter countzero_0 (
- .clk(clk),
- .count_right(e_in[345]),
- .is_32bit(e_in[333]),
- .result(countzero_result),
- .rs(c_in)
- );
- divider divider_0 (
- .clk(clk),
- .d_in({ _0031_, _0028_, _0038_, e_in[333], e_in[334], _0037_, _0732_ }),
- .d_out(divider_to_x),
- .rst(rst)
- );
- logical logical_0 (
- .datalen(e_in[370:367]),
- .invert_in(e_in[326]),
- .invert_out(e_in[327]),
- .op(e_in[8:3]),
- .parity(parity_result),
- .popcnt(popcnt_result),
- .rb(b_in),
- .result(logical_result),
- .rs(c_in)
- );
- multiply_16 multiply_0 (
- .clk(clk),
- .m_in({ e_in[333], _0016_, e_in[8:3], _0731_ }),
- .m_out(multiply_to_x)
- );
- rotator rotator_0 (
- .arith(e_in[334]),
- .carry_out(rotator_carry),
- .clear_left(rot_clear_left),
- .clear_right(rot_clear_right),
- .insn(e_in[366:335]),
- .is_32bit(e_in[333]),
- .ra(a_in),
- .result(rotator_result),
- .right_shift(right_shift),
- .rs(c_in),
- .shift(b_in[6:0]),
- .sign_ext_rs(rot_sign_ext)
- );
- assign flush_out = _0719_[0];
- assign stall_out = _0718_;
- assign l_out = { _0771_, ctrl[132], e_in[324], e_in[374], _0734_[118:114], e_in[83:79], e_in[373:371], _0770_, e_in[370:367], e_in[77:73], c_in, b_in, a_in, e_in[366:335], e_in[72:3], _0739_ };
- assign f_out = _0719_;
- assign e_out = r[190:0];
- assign dbg_msr_out = ctrl[191:128];
- assign icache_inval = _0720_;
- assign terminate_out = _0721_;
-endmodule
-
-module fetch1_3f28fda38b1ec2f6fdb16c0bce5a53c28d1424e5(clk, rst, stall_in, flush_in, stop_in, alt_reset_in, e_in, i_out);
- wire [63:0] _00_;
- wire _01_;
- wire [1:0] _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire [1:0] _06_;
- wire _07_;
- wire _08_;
- wire [1:0] _09_;
- wire _10_;
- wire [1:0] _11_;
- wire _12_;
- wire [63:0] _13_;
- wire [63:0] _14_;
- wire _15_;
- wire [1:0] _16_;
- wire [1:0] _17_;
- wire [63:0] _18_;
- wire [1:0] _19_;
- wire [1:0] _20_;
- wire [63:0] _21_;
- wire _22_;
- input alt_reset_in;
- input clk;
- input [66:0] e_in;
- input flush_in;
- output [67:0] i_out;
- reg [67:0] r;
- reg [1:0] r_int;
- wire [1:0] r_next_int;
- input rst;
- input stall_in;
- input stop_in;
- always @(posedge clk)
- r <= { _21_, stop_in, _20_, _22_ };
- always @(posedge clk)
- r_int <= r_next_int;
- assign _00_ = alt_reset_in ? 64'h0000000000000000 : 64'h0000000000000000;
- assign _01_ = ~ stall_in;
- assign _02_ = stop_in ? 2'h1 : r_int;
- assign _03_ = stop_in ? 1'h0 : 1'h1;
- assign _04_ = r_int == 2'h0;
- assign _05_ = ~ stop_in;
- assign _06_ = _05_ ? 2'h2 : r_int;
- assign _07_ = r_int == 2'h1;
- assign _08_ = ~ stop_in;
- assign _09_ = _08_ ? 2'h0 : 2'h1;
- assign _10_ = r_int == 2'h2;
- function [1:0] \183 ;
- input [1:0] a;
- input [5:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \183 = b[1:0];
- 3'b?1?:
- \183 = b[3:2];
- 3'b1??:
- \183 = b[5:4];
- default:
- \183 = a;
- endcase
- endfunction
- assign _11_ = \183 (2'hx, { _09_, _06_, _02_ }, { _10_, _07_, _04_ });
- function [0:0] \187 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \187 = b[0:0];
- 3'b?1?:
- \187 = b[1:1];
- 3'b1??:
- \187 = b[2:2];
- default:
- \187 = a;
- endcase
- endfunction
- assign _12_ = \187 (1'hx, { 2'h2, _03_ }, { _10_, _07_, _04_ });
- assign _13_ = r[67:4] + 64'h0000000000000004;
- assign _14_ = _15_ ? _13_ : r[67:4];
- assign _15_ = _01_ & _12_;
- assign _16_ = _01_ ? _11_ : r_int;
- assign _17_ = e_in[0] ? e_in[2:1] : r[2:1];
- assign _18_ = e_in[0] ? e_in[66:3] : _14_;
- assign _19_ = e_in[0] ? r_int : _16_;
- assign _20_ = rst ? 2'h2 : _17_;
- assign _21_ = rst ? _00_ : _18_;
- assign r_next_int = rst ? 2'h0 : _19_;
- assign _22_ = ~ rst;
- assign i_out = r;
-endmodule
-
-module fetch2(clk, rst, stall_in, flush_in, i_in, f_out);
- wire _00_;
- wire _01_;
- wire _02_;
- wire [98:0] _03_;
- wire _04_;
- wire _05_;
- wire [99:0] _06_;
- wire _07_;
- wire _08_;
- wire _09_;
- wire [98:0] _10_;
- wire _11_;
- wire _12_;
- wire _13_;
- wire _14_;
- wire _15_;
- wire _16_;
- wire _17_;
- input clk;
- output [98:0] f_out;
- input flush_in;
- input [98:0] i_in;
- reg [98:0] r;
- reg [100:0] r_int;
- input rst;
- input stall_in;
- assign _00_ = rst | flush_in;
- assign _01_ = ~ stall_in;
- assign _02_ = _00_ | _01_;
- always @(posedge clk)
- r_int <= { r_int[100], _17_, _06_[98:3], _12_, _06_[1], _11_ };
- assign _03_ = _02_ ? { _10_[98:3], _15_, _10_[1], _16_ } : r;
- always @(posedge clk)
- r <= _03_;
- assign _04_ = ~ r_int[99];
- assign _05_ = stall_in & _04_;
- assign _06_ = _05_ ? { 1'h1, i_in } : r_int[99:0];
- assign _07_ = ~ stall_in;
- assign _08_ = _06_[99] & _07_;
- assign _09_ = _08_ ? 1'h0 : _06_[99];
- assign _10_ = _08_ ? _06_[98:0] : i_in;
- assign _11_ = flush_in ? 1'h0 : _06_[0];
- assign _12_ = flush_in ? 1'h0 : _06_[2];
- assign _13_ = flush_in | _10_[1];
- assign _14_ = _13_ ? 1'h0 : _10_[0];
- assign _15_ = _13_ ? 1'h0 : _10_[2];
- assign _16_ = rst ? 1'h0 : _14_;
- assign _17_ = rst ? 1'h0 : _09_;
- assign f_out = r;
-endmodule
-
-module gpr_hazard_1(clk, stall_in, gpr_write_valid_in, gpr_write_in, bypass_avail, gpr_read_valid_in, gpr_read_in, stall_out, use_bypass);
- wire _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- wire _08_;
- wire _09_;
- wire _10_;
- input bypass_avail;
- input clk;
- input [5:0] gpr_read_in;
- input gpr_read_valid_in;
- input [5:0] gpr_write_in;
- input gpr_write_valid_in;
- reg [7:0] r = 8'h00;
- wire [7:0] rin;
- input stall_in;
- output stall_out;
- output use_bypass;
- always @(posedge clk)
- r <= rin;
- assign _00_ = r[7:2] == gpr_read_in;
- assign _01_ = r[0] & _00_;
- assign _02_ = ~ stall_in;
- assign _03_ = r[1] & _02_;
- assign _04_ = _03_ ? 1'h0 : 1'h1;
- assign _05_ = _03_ ? 1'h1 : 1'h0;
- assign _06_ = _01_ ? _04_ : 1'h0;
- assign _07_ = _01_ ? _05_ : 1'h0;
- assign _08_ = gpr_read_valid_in ? _06_ : 1'h0;
- assign _09_ = gpr_read_valid_in ? _07_ : 1'h0;
- assign _10_ = ~ stall_in;
- assign rin = _10_ ? { gpr_write_in, bypass_avail, gpr_write_valid_in } : r;
- assign stall_out = _08_;
- assign use_bypass = _09_;
-endmodule
-
-module icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, i_in, m_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out);
- wire _0000_;
- wire _0001_;
- wire _0002_;
- wire _0003_;
- wire _0004_;
- wire _0005_;
- wire _0006_;
- wire _0007_;
- wire _0008_;
- wire _0009_;
- wire _0010_;
- wire _0011_;
- wire _0012_;
- wire _0013_;
- wire _0014_;
- wire _0015_;
- wire _0016_;
- wire _0017_;
- wire _0018_;
- wire [89:0] _0019_;
- wire _0020_;
- wire [89:0] _0021_;
- wire [89:0] _0022_;
- wire [89:0] _0023_;
- wire [89:0] _0024_;
- wire [89:0] _0025_;
- wire [89:0] _0026_;
- wire [89:0] _0027_;
- wire [89:0] _0028_;
- wire [89:0] _0029_;
- wire [89:0] _0030_;
- wire _0031_;
- wire _0032_;
- wire _0033_;
- wire _0034_;
- wire _0035_;
- wire _0036_;
- wire _0037_;
- wire _0038_;
- wire _0039_;
- wire _0040_;
- wire _0041_;
- wire _0042_;
- wire _0043_;
- wire _0044_;
- wire _0045_;
- wire _0046_;
- wire _0047_;
- wire _0048_;
- wire _0049_;
- wire _0050_;
- wire _0051_;
- wire _0052_;
- wire _0053_;
- wire _0054_;
- wire _0055_;
- wire _0056_;
- wire _0057_;
- wire _0058_;
- wire _0059_;
- wire _0060_;
- wire _0061_;
- wire _0062_;
- wire _0063_;
- wire _0064_;
- wire _0065_;
- wire _0066_;
- wire _0067_;
- wire _0068_;
- wire _0069_;
- wire _0070_;
- wire _0071_;
- wire _0072_;
- wire _0073_;
- wire _0074_;
- wire _0075_;
- wire _0076_;
- wire _0077_;
- wire _0078_;
- wire _0079_;
- wire _0080_;
- wire _0081_;
- wire _0082_;
- wire _0083_;
- wire _0084_;
- wire _0085_;
- wire _0086_;
- wire _0087_;
- wire _0088_;
- wire _0089_;
- wire _0090_;
- wire _0091_;
- wire _0092_;
- wire _0093_;
- wire _0094_;
- wire _0095_;
- wire _0096_;
- wire _0097_;
- wire _0098_;
- wire [89:0] _0099_;
- wire [89:0] _0100_;
- wire [89:0] _0101_;
- wire [89:0] _0102_;
- wire [89:0] _0103_;
- wire _0104_;
- wire [89:0] _0105_;
- wire [89:0] _0106_;
- wire [89:0] _0107_;
- wire [89:0] _0108_;
- wire [89:0] _0109_;
- wire [89:0] _0110_;
- wire [89:0] _0111_;
- wire [89:0] _0112_;
- wire [89:0] _0113_;
- wire [89:0] _0114_;
- wire _0115_;
- wire [89:0] _0116_;
- wire [89:0] _0117_;
- wire [89:0] _0118_;
- wire [89:0] _0119_;
- wire [89:0] _0120_;
- wire [89:0] _0121_;
- wire [89:0] _0122_;
- wire [89:0] _0123_;
- wire [89:0] _0124_;
- wire [89:0] _0125_;
- wire [89:0] _0126_;
- wire [89:0] _0127_;
- wire [89:0] _0128_;
- wire [89:0] _0129_;
- wire [89:0] _0130_;
- wire [89:0] _0131_;
- wire [89:0] _0132_;
- wire [89:0] _0133_;
- wire [89:0] _0134_;
- wire [89:0] _0135_;
- wire [89:0] _0136_;
- wire [89:0] _0137_;
- wire [89:0] _0138_;
- wire [89:0] _0139_;
- wire [89:0] _0140_;
- wire [89:0] _0141_;
- wire [89:0] _0142_;
- wire [89:0] _0143_;
- wire _0144_;
- wire _0145_;
- wire _0146_;
- wire _0147_;
- wire _0148_;
- wire _0149_;
- wire _0150_;
- wire _0151_;
- wire _0152_;
- wire _0153_;
- wire _0154_;
- wire _0155_;
- wire _0156_;
- wire _0157_;
- wire _0158_;
- wire _0159_;
- wire _0160_;
- wire _0161_;
- wire _0162_;
- wire _0163_;
- wire _0164_;
- wire _0165_;
- wire _0166_;
- wire _0167_;
- wire _0168_;
- wire _0169_;
- wire _0170_;
- wire _0171_;
- wire _0172_;
- wire _0173_;
- wire _0174_;
- wire _0175_;
- wire _0176_;
- wire _0177_;
- wire _0178_;
- wire _0179_;
- wire _0180_;
- wire _0181_;
- wire _0182_;
- wire _0183_;
- wire _0184_;
- wire _0185_;
- wire _0186_;
- wire _0187_;
- wire _0188_;
- wire _0189_;
- wire _0190_;
- wire _0191_;
- wire _0192_;
- wire _0193_;
- wire _0194_;
- wire _0195_;
- wire _0196_;
- wire _0197_;
- wire _0198_;
- wire _0199_;
- wire _0200_;
- wire _0201_;
- wire _0202_;
- wire _0203_;
- wire _0204_;
- wire _0205_;
- wire _0206_;
- wire _0207_;
- wire _0208_;
- wire _0209_;
- wire _0210_;
- wire _0211_;
- wire _0212_;
- wire [89:0] _0213_;
- wire [89:0] _0214_;
- wire [89:0] _0215_;
- wire [89:0] _0216_;
- wire [89:0] _0217_;
- wire [89:0] _0218_;
- wire [89:0] _0219_;
- wire [89:0] _0220_;
- wire [89:0] _0221_;
- wire [89:0] _0222_;
- wire [89:0] _0223_;
- wire [89:0] _0224_;
- wire [89:0] _0225_;
- wire [89:0] _0226_;
- wire [89:0] _0227_;
- wire [89:0] _0228_;
- wire [89:0] _0229_;
- wire _0230_;
- wire [89:0] _0231_;
- wire [89:0] _0232_;
- wire [89:0] _0233_;
- wire [89:0] _0234_;
- wire [89:0] _0235_;
- wire [89:0] _0236_;
- wire [89:0] _0237_;
- wire [89:0] _0238_;
- wire [89:0] _0239_;
- wire [89:0] _0240_;
- wire _0241_;
- wire [89:0] _0242_;
- wire [89:0] _0243_;
- wire [89:0] _0244_;
- wire [89:0] _0245_;
- wire [89:0] _0246_;
- wire _0247_;
- wire _0248_;
- wire _0249_;
- wire _0250_;
- wire _0251_;
- wire _0252_;
- wire _0253_;
- wire _0254_;
- wire _0255_;
- wire _0256_;
- wire _0257_;
- wire _0258_;
- wire _0259_;
- wire _0260_;
- wire _0261_;
- wire _0262_;
- wire _0263_;
- wire _0264_;
- wire _0265_;
- wire _0266_;
- wire _0267_;
- wire _0268_;
- wire _0269_;
- wire _0270_;
- wire _0271_;
- wire _0272_;
- wire _0273_;
- wire _0274_;
- wire _0275_;
- wire _0276_;
- wire _0277_;
- wire _0278_;
- wire _0279_;
- wire _0280_;
- wire _0281_;
- wire _0282_;
- wire _0283_;
- wire _0284_;
- wire _0285_;
- wire _0286_;
- wire _0287_;
- wire _0288_;
- wire _0289_;
- wire _0290_;
- wire _0291_;
- wire _0292_;
- wire _0293_;
- wire _0294_;
- wire _0295_;
- wire _0296_;
- wire _0297_;
- wire _0298_;
- wire _0299_;
- wire _0300_;
- wire _0301_;
- wire _0302_;
- wire _0303_;
- wire _0304_;
- wire _0305_;
- wire _0306_;
- wire _0307_;
- wire _0308_;
- wire _0309_;
- wire _0310_;
- wire _0311_;
- wire _0312_;
- wire _0313_;
- wire _0314_;
- wire _0315_;
- wire _0316_;
- wire _0317_;
- wire _0318_;
- wire _0319_;
- wire _0320_;
- wire _0321_;
- wire _0322_;
- wire _0323_;
- wire _0324_;
- wire _0325_;
- wire _0326_;
- wire _0327_;
- wire _0328_;
- wire _0329_;
- wire _0330_;
- wire _0331_;
- wire _0332_;
- wire _0333_;
- wire _0334_;
- wire _0335_;
- wire _0336_;
- wire _0337_;
- wire _0338_;
- wire _0339_;
- wire _0340_;
- wire _0341_;
- wire _0342_;
- wire _0343_;
- wire _0344_;
- wire _0345_;
- wire _0346_;
- wire _0347_;
- wire _0348_;
- wire _0349_;
- wire _0350_;
- wire _0351_;
- wire _0352_;
- wire _0353_;
- wire _0354_;
- wire _0355_;
- wire _0356_;
- wire _0357_;
- wire _0358_;
- wire _0359_;
- wire _0360_;
- wire _0361_;
- wire _0362_;
- wire _0363_;
- wire _0364_;
- wire _0365_;
- wire _0366_;
- wire _0367_;
- wire _0368_;
- wire _0369_;
- wire _0370_;
- wire _0371_;
- wire _0372_;
- wire _0373_;
- wire _0374_;
- wire _0375_;
- wire _0376_;
- wire _0377_;
- wire _0378_;
- wire _0379_;
- wire _0380_;
- wire _0381_;
- wire _0382_;
- wire _0383_;
- wire _0384_;
- wire _0385_;
- wire _0386_;
- wire _0387_;
- wire _0388_;
- wire _0389_;
- wire _0390_;
- wire _0391_;
- wire _0392_;
- wire _0393_;
- wire _0394_;
- wire _0395_;
- wire _0396_;
- wire _0397_;
- wire _0398_;
- wire _0399_;
- wire _0400_;
- wire _0401_;
- wire _0402_;
- wire _0403_;
- wire _0404_;
- wire _0405_;
- wire _0406_;
- wire _0407_;
- wire _0408_;
- wire _0409_;
- wire _0410_;
- wire _0411_;
- wire _0412_;
- wire _0413_;
- wire _0414_;
- wire _0415_;
- wire _0416_;
- wire _0417_;
- wire _0418_;
- wire _0419_;
- wire _0420_;
- wire _0421_;
- wire _0422_;
- wire _0423_;
- wire _0424_;
- wire _0425_;
- wire _0426_;
- wire _0427_;
- wire _0428_;
- wire _0429_;
- wire _0430_;
- wire _0431_;
- wire _0432_;
- wire _0433_;
- wire _0434_;
- wire _0435_;
- wire _0436_;
- wire _0437_;
- wire _0438_;
- wire _0439_;
- wire _0440_;
- wire _0441_;
- wire _0442_;
- wire _0443_;
- wire _0444_;
- wire _0445_;
- wire _0446_;
- wire _0447_;
- wire _0448_;
- wire _0449_;
- wire _0450_;
- wire _0451_;
- wire _0452_;
- wire _0453_;
- wire _0454_;
- wire _0455_;
- wire _0456_;
- wire _0457_;
- wire _0458_;
- wire _0459_;
- wire _0460_;
- wire _0461_;
- wire _0462_;
- wire _0463_;
- wire _0464_;
- wire _0465_;
- wire _0466_;
- wire _0467_;
- wire _0468_;
- wire _0469_;
- wire _0470_;
- wire _0471_;
- wire _0472_;
- wire _0473_;
- wire _0474_;
- wire _0475_;
- wire _0476_;
- wire _0477_;
- wire _0478_;
- wire _0479_;
- wire _0480_;
- wire _0481_;
- wire _0482_;
- wire _0483_;
- wire _0484_;
- wire _0485_;
- wire _0486_;
- wire _0487_;
- wire _0488_;
- wire _0489_;
- wire _0490_;
- wire _0491_;
- wire _0492_;
- wire [5:0] _0493_;
- wire _0494_;
- wire [5:0] _0495_;
- wire _0496_;
- wire _0497_;
- wire _0498_;
- wire [5:0] _0499_;
- wire [5:0] _0500_;
- wire _0501_;
- wire _0502_;
- wire [5:0] _0503_;
- wire [5:0] _0504_;
- wire [63:0] _0505_;
- wire [63:0] _0506_;
- wire [63:0] _0507_;
- wire _0508_;
- wire _0509_;
- wire _0510_;
- wire _0511_;
- wire _0512_;
- wire _0513_;
- wire _0514_;
- wire _0515_;
- wire [4:0] _0516_;
- wire _0517_;
- wire [4:0] _0518_;
- wire _0519_;
- wire _0520_;
- wire _0521_;
- wire [4:0] _0522_;
- wire _0523_;
- wire [4:0] _0524_;
- wire _0525_;
- wire _0526_;
- wire _0527_;
- wire _0528_;
- wire _0529_;
- wire _0530_;
- wire _0531_;
- wire _0532_;
- wire _0533_;
- wire _0534_;
- wire [4:0] _0535_;
- wire _0536_;
- wire _0537_;
- wire _0538_;
- wire _0539_;
- wire _0540_;
- reg [66:0] _0541_;
- wire [63:0] _0542_;
- wire _0543_;
- wire [4:0] _0544_;
- wire _0545_;
- wire [4:0] _0546_;
- wire [4:0] _0547_;
- wire [2879:0] _0548_;
- wire _0549_;
- wire [4:0] _0550_;
- wire [4:0] _0551_;
- wire [2879:0] _0552_;
- wire [2879:0] _0553_;
- wire [63:0] _0554_;
- wire [32:0] _0555_;
- wire [1:0] _0556_;
- wire [14:0] _0557_;
- wire _0558_;
- wire _0559_;
- wire _0560_;
- wire _0561_;
- wire _0562_;
- wire _0563_;
- wire _0564_;
- wire _0565_;
- wire [2:0] _0566_;
- wire [31:0] _0567_;
- wire _0568_;
- wire _0569_;
- wire _0570_;
- wire _0571_;
- wire [4:0] _0572_;
- wire _0573_;
- wire _0574_;
- wire [63:0] _0575_;
- wire _0576_;
- wire _0577_;
- wire [2:0] _0578_;
- wire _0579_;
- wire _0580_;
- wire _0581_;
- wire [7:0] _0582_;
- wire _0583_;
- wire [2879:0] _0584_;
- wire [63:0] _0585_;
- wire _0586_;
- wire [31:0] _0587_;
- wire _0588_;
- wire _0589_;
- wire [5:0] _0590_;
- wire [7:0] _0591_;
- wire _0592_;
- wire [2879:0] _0593_;
- wire [63:0] _0594_;
- wire [32:0] _0595_;
- wire [63:0] _0596_;
- wire [1:0] _0597_;
- wire [8:0] _0598_;
- wire [14:0] _0599_;
- wire _0600_;
- wire _0601_;
- wire _0602_;
- wire _0603_;
- wire _0604_;
- wire _0605_;
- reg [123:0] _0606_;
- wire [4095:0] _0607_;
- wire [63:0] _0608_;
- wire [2943:0] _0609_;
- wire [45:0] _0610_;
- wire _0611_;
- wire _0612_;
- wire _0613_;
- wire _0614_;
- wire _0615_;
- wire _0616_;
- wire _0617_;
- wire _0618_;
- wire _0619_;
- wire _0620_;
- wire _0621_;
- wire _0622_;
- wire _0623_;
- wire _0624_;
- wire _0625_;
- wire _0626_;
- wire _0627_;
- wire _0628_;
- wire _0629_;
- wire _0630_;
- wire _0631_;
- wire _0632_;
- wire _0633_;
- wire _0634_;
- wire _0635_;
- wire _0636_;
- wire _0637_;
- wire _0638_;
- wire _0639_;
- wire _0640_;
- wire _0641_;
- wire _0642_;
- wire _0643_;
- wire _0644_;
- wire _0645_;
- wire _0646_;
- wire _0647_;
- wire _0648_;
- wire _0649_;
- wire _0650_;
- wire _0651_;
- wire _0652_;
- wire _0653_;
- wire _0654_;
- wire _0655_;
- wire _0656_;
- wire _0657_;
- wire _0658_;
- wire _0659_;
- wire _0660_;
- wire _0661_;
- wire _0662_;
- wire _0663_;
- wire _0664_;
- wire _0665_;
- wire _0666_;
- wire _0667_;
- wire _0668_;
- wire _0669_;
- wire _0670_;
- wire _0671_;
- wire _0672_;
- wire _0673_;
- wire _0674_;
- wire _0675_;
- wire _0676_;
- wire _0677_;
- wire _0678_;
- wire _0679_;
- wire _0680_;
- wire _0681_;
- wire _0682_;
- wire _0683_;
- wire _0684_;
- wire _0685_;
- wire _0686_;
- wire _0687_;
- wire _0688_;
- wire _0689_;
- wire _0690_;
- wire _0691_;
- wire _0692_;
- wire _0693_;
- wire _0694_;
- wire _0695_;
- wire _0696_;
- wire _0697_;
- wire _0698_;
- wire _0699_;
- wire _0700_;
- wire _0701_;
- wire _0702_;
- wire _0703_;
- wire _0704_;
- wire _0705_;
- wire _0706_;
- wire _0707_;
- wire _0708_;
- wire _0709_;
- wire _0710_;
- wire _0711_;
- wire _0712_;
- wire _0713_;
- wire _0714_;
- wire _0715_;
- wire _0716_;
- wire _0717_;
- wire _0718_;
- wire _0719_;
- wire _0720_;
- wire _0721_;
- wire _0722_;
- wire _0723_;
- wire _0724_;
- wire _0725_;
- wire _0726_;
- wire _0727_;
- wire _0728_;
- wire _0729_;
- wire _0730_;
- wire _0731_;
- wire _0732_;
- wire _0733_;
- wire _0734_;
- wire _0735_;
- wire _0736_;
- wire _0737_;
- wire _0738_;
- wire _0739_;
- wire _0740_;
- wire _0741_;
- wire _0742_;
- wire _0743_;
- wire _0744_;
- wire _0745_;
- wire _0746_;
- wire _0747_;
- wire _0748_;
- wire _0749_;
- wire _0750_;
- wire _0751_;
- wire _0752_;
- wire _0753_;
- wire _0754_;
- wire _0755_;
- wire _0756_;
- wire _0757_;
- wire _0758_;
- wire _0759_;
- wire _0760_;
- wire _0761_;
- wire _0762_;
- wire _0763_;
- wire _0764_;
- wire _0765_;
- wire _0766_;
- wire _0767_;
- wire _0768_;
- wire _0769_;
- wire _0770_;
- wire _0771_;
- wire _0772_;
- wire _0773_;
- wire _0774_;
- wire _0775_;
- wire _0776_;
- wire _0777_;
- wire _0778_;
- wire _0779_;
- wire _0780_;
- wire _0781_;
- wire _0782_;
- wire _0783_;
- wire _0784_;
- wire _0785_;
- wire _0786_;
- wire _0787_;
- wire _0788_;
- wire _0789_;
- wire _0790_;
- wire _0791_;
- wire _0792_;
- wire _0793_;
- wire _0794_;
- wire _0795_;
- wire _0796_;
- wire _0797_;
- wire _0798_;
- wire _0799_;
- wire _0800_;
- wire _0801_;
- wire _0802_;
- wire _0803_;
- wire _0804_;
- wire _0805_;
- wire _0806_;
- wire _0807_;
- wire _0808_;
- wire _0809_;
- wire _0810_;
- wire _0811_;
- wire _0812_;
- wire _0813_;
- wire _0814_;
- wire _0815_;
- wire _0816_;
- wire _0817_;
- wire _0818_;
- wire _0819_;
- wire _0820_;
- wire _0821_;
- wire _0822_;
- wire _0823_;
- wire _0824_;
- wire _0825_;
- wire _0826_;
- wire _0827_;
- wire _0828_;
- wire _0829_;
- wire _0830_;
- wire _0831_;
- wire _0832_;
- wire _0833_;
- wire _0834_;
- wire _0835_;
- wire _0836_;
- wire _0837_;
- wire _0838_;
- wire _0839_;
- wire _0840_;
- wire _0841_;
- wire _0842_;
- wire _0843_;
- wire _0844_;
- wire _0845_;
- wire _0846_;
- wire _0847_;
- wire _0848_;
- wire _0849_;
- wire _0850_;
- wire _0851_;
- wire _0852_;
- wire _0853_;
- wire _0854_;
- wire _0855_;
- wire _0856_;
- wire _0857_;
- wire _0858_;
- wire _0859_;
- wire _0860_;
- wire _0861_;
- wire _0862_;
- wire _0863_;
- wire _0864_;
- wire _0865_;
- wire _0866_;
- wire _0867_;
- wire _0868_;
- wire _0869_;
- wire _0870_;
- wire _0871_;
- wire _0872_;
- wire _0873_;
- wire _0874_;
- wire _0875_;
- wire _0876_;
- wire _0877_;
- wire _0878_;
- wire _0879_;
- wire _0880_;
- wire _0881_;
- wire _0882_;
- wire _0883_;
- wire _0884_;
- wire _0885_;
- wire _0886_;
- wire _0887_;
- wire _0888_;
- wire _0889_;
- wire _0890_;
- wire _0891_;
- wire _0892_;
- wire _0893_;
- wire _0894_;
- wire _0895_;
- wire _0896_;
- wire _0897_;
- wire _0898_;
- wire _0899_;
- wire _0900_;
- wire _0901_;
- wire _0902_;
- wire _0903_;
- wire _0904_;
- wire _0905_;
- wire _0906_;
- wire _0907_;
- wire _0908_;
- wire _0909_;
- wire _0910_;
- wire _0911_;
- wire _0912_;
- wire _0913_;
- wire _0914_;
- wire _0915_;
- wire _0916_;
- wire _0917_;
- wire _0918_;
- wire _0919_;
- wire _0920_;
- wire _0921_;
- wire _0922_;
- wire _0923_;
- wire _0924_;
- wire _0925_;
- wire _0926_;
- wire _0927_;
- wire _0928_;
- wire _0929_;
- wire _0930_;
- wire _0931_;
- wire _0932_;
- wire _0933_;
- wire _0934_;
- wire _0935_;
- wire _0936_;
- wire _0937_;
- wire _0938_;
- wire _0939_;
- wire _0940_;
- wire _0941_;
- wire _0942_;
- wire _0943_;
- wire _0944_;
- wire _0945_;
- wire _0946_;
- wire _0947_;
- wire _0948_;
- wire _0949_;
- wire _0950_;
- wire _0951_;
- wire _0952_;
- wire _0953_;
- wire _0954_;
- wire _0955_;
- wire _0956_;
- wire _0957_;
- wire _0958_;
- wire _0959_;
- wire _0960_;
- wire _0961_;
- wire _0962_;
- wire _0963_;
- wire _0964_;
- wire _0965_;
- wire _0966_;
- wire _0967_;
- wire _0968_;
- wire _0969_;
- wire _0970_;
- wire _0971_;
- wire _0972_;
- wire _0973_;
- wire _0974_;
- wire _0975_;
- wire _0976_;
- wire _0977_;
- wire _0978_;
- wire _0979_;
- wire _0980_;
- wire _0981_;
- wire _0982_;
- wire _0983_;
- wire _0984_;
- wire _0985_;
- wire _0986_;
- wire _0987_;
- wire _0988_;
- wire _0989_;
- wire _0990_;
- wire _0991_;
- wire _0992_;
- wire _0993_;
- wire _0994_;
- wire _0995_;
- wire _0996_;
- wire _0997_;
- wire _0998_;
- wire _0999_;
- wire _1000_;
- wire _1001_;
- wire _1002_;
- wire _1003_;
- wire _1004_;
- wire _1005_;
- wire _1006_;
- wire _1007_;
- wire _1008_;
- wire _1009_;
- wire _1010_;
- wire _1011_;
- wire _1012_;
- wire _1013_;
- wire _1014_;
- wire _1015_;
- wire _1016_;
- wire _1017_;
- wire _1018_;
- wire _1019_;
- wire _1020_;
- wire _1021_;
- wire _1022_;
- wire _1023_;
- wire _1024_;
- wire _1025_;
- wire _1026_;
- wire _1027_;
- wire _1028_;
- wire _1029_;
- wire _1030_;
- wire [89:0] _1031_;
- wire [89:0] _1032_;
- wire [89:0] _1033_;
- wire [89:0] _1034_;
- wire [89:0] _1035_;
- wire [89:0] _1036_;
- wire [89:0] _1037_;
- wire [89:0] _1038_;
- wire [89:0] _1039_;
- wire [89:0] _1040_;
- wire [89:0] _1041_;
- wire _1042_;
- wire _1043_;
- wire _1044_;
- wire _1045_;
- wire _1046_;
- wire _1047_;
- wire _1048_;
- wire _1049_;
- wire _1050_;
- wire _1051_;
- wire _1052_;
- wire [89:0] _1053_;
- wire [89:0] _1054_;
- wire [89:0] _1055_;
- wire [89:0] _1056_;
- wire [89:0] _1057_;
- wire [89:0] _1058_;
- wire [89:0] _1059_;
- wire [89:0] _1060_;
- wire [89:0] _1061_;
- wire [89:0] _1062_;
- wire [89:0] _1063_;
- wire _1064_;
- wire _1065_;
- wire _1066_;
- wire _1067_;
- wire _1068_;
- wire _1069_;
- wire _1070_;
- wire _1071_;
- wire _1072_;
- wire _1073_;
- wire [63:0] _1074_;
- wire [31:0] _1075_;
- wire _1076_;
- wire _1077_;
- wire _1078_;
- wire _1079_;
- wire _1080_;
- wire _1081_;
- wire _1082_;
- wire _1083_;
- wire _1084_;
- wire _1085_;
- wire _1086_;
- wire _1087_;
- wire _1088_;
- wire _1089_;
- wire _1090_;
- wire _1091_;
- wire _1092_;
- wire _1093_;
- wire _1094_;
- wire _1095_;
- wire _1096_;
- wire _1097_;
- wire _1098_;
- wire _1099_;
- wire _1100_;
- wire _1101_;
- wire _1102_;
- wire _1103_;
- wire _1104_;
- wire _1105_;
- wire _1106_;
- wire _1107_;
- wire _1108_;
- wire _1109_;
- wire _1110_;
- wire _1111_;
- wire _1112_;
- wire _1113_;
- wire _1114_;
- wire _1115_;
- wire _1116_;
- wire _1117_;
- wire _1118_;
- wire _1119_;
- wire _1120_;
- wire _1121_;
- wire _1122_;
- wire _1123_;
- wire _1124_;
- wire _1125_;
- wire _1126_;
- wire _1127_;
- wire _1128_;
- wire _1129_;
- wire _1130_;
- wire _1131_;
- wire _1132_;
- wire _1133_;
- wire _1134_;
- wire _1135_;
- wire _1136_;
- wire _1137_;
- wire _1138_;
- wire _1139_;
- wire _1140_;
- wire _1141_;
- wire _1142_;
- wire _1143_;
- wire _1144_;
- wire _1145_;
- wire _1146_;
- wire _1147_;
- wire _1148_;
- wire _1149_;
- wire _1150_;
- wire _1151_;
- wire _1152_;
- wire _1153_;
- wire _1154_;
- wire _1155_;
- wire _1156_;
- wire _1157_;
- wire _1158_;
- wire _1159_;
- wire _1160_;
- wire _1161_;
- wire _1162_;
- wire _1163_;
- wire _1164_;
- wire _1165_;
- wire _1166_;
- wire _1167_;
- wire _1168_;
- wire _1169_;
- wire _1170_;
- wire _1171_;
- wire _1172_;
- wire _1173_;
- wire _1174_;
- wire _1175_;
- wire _1176_;
- wire _1177_;
- wire _1178_;
- wire _1179_;
- wire _1180_;
- wire _1181_;
- wire _1182_;
- wire _1183_;
- wire _1184_;
- wire _1185_;
- wire _1186_;
- wire _1187_;
- wire _1188_;
- wire _1189_;
- wire _1190_;
- wire _1191_;
- wire _1192_;
- wire _1193_;
- wire _1194_;
- wire _1195_;
- wire _1196_;
- wire _1197_;
- wire _1198_;
- wire _1199_;
- wire _1200_;
- wire _1201_;
- wire _1202_;
- wire _1203_;
- wire _1204_;
- wire _1205_;
- wire _1206_;
- wire _1207_;
- wire _1208_;
- wire _1209_;
- wire _1210_;
- wire _1211_;
- wire _1212_;
- wire _1213_;
- wire _1214_;
- wire _1215_;
- wire _1216_;
- wire _1217_;
- wire _1218_;
- wire _1219_;
- wire _1220_;
- wire _1221_;
- wire _1222_;
- wire _1223_;
- wire _1224_;
- wire _1225_;
- wire _1226_;
- wire _1227_;
- wire _1228_;
- wire _1229_;
- wire _1230_;
- wire _1231_;
- wire _1232_;
- wire _1233_;
- wire _1234_;
- wire _1235_;
- wire _1236_;
- wire _1237_;
- wire _1238_;
- wire _1239_;
- wire _1240_;
- wire _1241_;
- wire _1242_;
- wire _1243_;
- wire _1244_;
- wire _1245_;
- wire _1246_;
- wire _1247_;
- wire _1248_;
- wire _1249_;
- wire _1250_;
- wire _1251_;
- wire _1252_;
- wire _1253_;
- wire _1254_;
- wire _1255_;
- wire _1256_;
- wire _1257_;
- wire _1258_;
- wire _1259_;
- wire _1260_;
- wire _1261_;
- wire _1262_;
- wire _1263_;
- wire _1264_;
- wire _1265_;
- wire _1266_;
- wire _1267_;
- wire _1268_;
- wire _1269_;
- wire _1270_;
- wire _1271_;
- wire _1272_;
- wire _1273_;
- wire _1274_;
- wire _1275_;
- wire _1276_;
- wire _1277_;
- wire _1278_;
- wire _1279_;
- wire _1280_;
- wire _1281_;
- wire _1282_;
- wire _1283_;
- wire _1284_;
- wire _1285_;
- wire [89:0] _1286_;
- wire [89:0] _1287_;
- wire [89:0] _1288_;
- wire [89:0] _1289_;
- wire [89:0] _1290_;
- wire [89:0] _1291_;
- wire [89:0] _1292_;
- wire [89:0] _1293_;
- wire [89:0] _1294_;
- wire [89:0] _1295_;
- wire _1296_;
- wire _1297_;
- wire _1298_;
- wire _1299_;
- wire _1300_;
- wire _1301_;
- wire _1302_;
- wire _1303_;
- wire _1304_;
- wire _1305_;
- wire [89:0] _1306_;
- wire [89:0] _1307_;
- wire [89:0] _1308_;
- wire [89:0] _1309_;
- wire [89:0] _1310_;
- wire [89:0] _1311_;
- wire [89:0] _1312_;
- wire [89:0] _1313_;
- wire [89:0] _1314_;
- wire [89:0] _1315_;
- wire _1316_;
- wire _1317_;
- wire _1318_;
- wire _1319_;
- wire _1320_;
- wire _1321_;
- wire _1322_;
- wire _1323_;
- wire _1324_;
- wire _1325_;
- wire [89:0] _1326_;
- wire [89:0] _1327_;
- wire [89:0] _1328_;
- wire [89:0] _1329_;
- wire [89:0] _1330_;
- wire [89:0] _1331_;
- wire [89:0] _1332_;
- wire [89:0] _1333_;
- wire [89:0] _1334_;
- wire [89:0] _1335_;
- wire [89:0] _1336_;
- wire [89:0] _1337_;
- wire [89:0] _1338_;
- wire [89:0] _1339_;
- wire [89:0] _1340_;
- wire [89:0] _1341_;
- wire [89:0] _1342_;
- wire [89:0] _1343_;
- wire [89:0] _1344_;
- wire [89:0] _1345_;
- wire _1346_;
- wire _1347_;
- wire _1348_;
- wire _1349_;
- wire _1350_;
- wire _1351_;
- wire _1352_;
- wire _1353_;
- wire _1354_;
- wire _1355_;
- wire _1356_;
- wire _1357_;
- wire _1358_;
- wire _1359_;
- wire _1360_;
- wire _1361_;
- wire _1362_;
- wire _1363_;
- wire _1364_;
- wire _1365_;
- wire _1366_;
- wire _1367_;
- wire _1368_;
- wire _1369_;
- wire _1370_;
- wire _1371_;
- wire _1372_;
- wire _1373_;
- wire _1374_;
- wire _1375_;
- wire _1376_;
- wire [89:0] _1377_;
- wire [89:0] _1378_;
- wire [89:0] _1379_;
- wire [89:0] _1380_;
- wire [89:0] _1381_;
- wire [89:0] _1382_;
- wire [89:0] _1383_;
- wire [89:0] _1384_;
- wire [89:0] _1385_;
- wire [89:0] _1386_;
- wire _1387_;
- wire _1388_;
- wire _1389_;
- wire _1390_;
- wire _1391_;
- wire _1392_;
- wire _1393_;
- wire _1394_;
- wire _1395_;
- wire _1396_;
- wire [89:0] _1397_;
- wire [89:0] _1398_;
- wire [89:0] _1399_;
- wire [89:0] _1400_;
- wire [89:0] _1401_;
- wire [89:0] _1402_;
- wire [89:0] _1403_;
- wire [89:0] _1404_;
- wire [89:0] _1405_;
- wire [89:0] _1406_;
- wire _1407_;
- wire _1408_;
- wire _1409_;
- wire _1410_;
- wire _1411_;
- wire _1412_;
- wire _1413_;
- wire _1414_;
- wire _1415_;
- wire _1416_;
- wire [89:0] _1417_;
- wire [89:0] _1418_;
- wire [89:0] _1419_;
- wire [89:0] _1420_;
- wire [89:0] _1421_;
- wire [89:0] _1422_;
- wire [89:0] _1423_;
- wire [89:0] _1424_;
- wire [89:0] _1425_;
- wire [89:0] _1426_;
- wire [89:0] _1427_;
- wire [89:0] _1428_;
- wire [89:0] _1429_;
- wire [89:0] _1430_;
- wire [89:0] _1431_;
- wire [89:0] _1432_;
- wire [89:0] _1433_;
- wire [89:0] _1434_;
- wire [89:0] _1435_;
- wire [89:0] _1436_;
- wire access_ok;
- reg [2879:0] cache_tags;
- reg [63:0] cache_valids;
- input clk;
- wire eaa_priv;
- input flush_in;
- input [67:0] i_in;
- output [98:0] i_out;
- input inval_in;
- reg [63:0] itlb_valids;
- input [130:0] m_in;
- wire \maybe_plrus.plrus%0.plru_acc_en ;
- wire \maybe_plrus.plrus%0.plru_out ;
- wire \maybe_plrus.plrus%1.plru_acc_en ;
- wire \maybe_plrus.plrus%1.plru_out ;
- wire \maybe_plrus.plrus%10.plru_acc_en ;
- wire \maybe_plrus.plrus%10.plru_out ;
- wire \maybe_plrus.plrus%11.plru_acc_en ;
- wire \maybe_plrus.plrus%11.plru_out ;
- wire \maybe_plrus.plrus%12.plru_acc_en ;
- wire \maybe_plrus.plrus%12.plru_out ;
- wire \maybe_plrus.plrus%13.plru_acc_en ;
- wire \maybe_plrus.plrus%13.plru_out ;
- wire \maybe_plrus.plrus%14.plru_acc_en ;
- wire \maybe_plrus.plrus%14.plru_out ;
- wire \maybe_plrus.plrus%15.plru_acc_en ;
- wire \maybe_plrus.plrus%15.plru_out ;
- wire \maybe_plrus.plrus%16.plru_acc_en ;
- wire \maybe_plrus.plrus%16.plru_out ;
- wire \maybe_plrus.plrus%17.plru_acc_en ;
- wire \maybe_plrus.plrus%17.plru_out ;
- wire \maybe_plrus.plrus%18.plru_acc_en ;
- wire \maybe_plrus.plrus%18.plru_out ;
- wire \maybe_plrus.plrus%19.plru_acc_en ;
- wire \maybe_plrus.plrus%19.plru_out ;
- wire \maybe_plrus.plrus%2.plru_acc_en ;
- wire \maybe_plrus.plrus%2.plru_out ;
- wire \maybe_plrus.plrus%20.plru_acc_en ;
- wire \maybe_plrus.plrus%20.plru_out ;
- wire \maybe_plrus.plrus%21.plru_acc_en ;
- wire \maybe_plrus.plrus%21.plru_out ;
- wire \maybe_plrus.plrus%22.plru_acc_en ;
- wire \maybe_plrus.plrus%22.plru_out ;
- wire \maybe_plrus.plrus%23.plru_acc_en ;
- wire \maybe_plrus.plrus%23.plru_out ;
- wire \maybe_plrus.plrus%24.plru_acc_en ;
- wire \maybe_plrus.plrus%24.plru_out ;
- wire \maybe_plrus.plrus%25.plru_acc_en ;
- wire \maybe_plrus.plrus%25.plru_out ;
- wire \maybe_plrus.plrus%26.plru_acc_en ;
- wire \maybe_plrus.plrus%26.plru_out ;
- wire \maybe_plrus.plrus%27.plru_acc_en ;
- wire \maybe_plrus.plrus%27.plru_out ;
- wire \maybe_plrus.plrus%28.plru_acc_en ;
- wire \maybe_plrus.plrus%28.plru_out ;
- wire \maybe_plrus.plrus%29.plru_acc_en ;
- wire \maybe_plrus.plrus%29.plru_out ;
- wire \maybe_plrus.plrus%3.plru_acc_en ;
- wire \maybe_plrus.plrus%3.plru_out ;
- wire \maybe_plrus.plrus%30.plru_acc_en ;
- wire \maybe_plrus.plrus%30.plru_out ;
- wire \maybe_plrus.plrus%31.plru_acc_en ;
- wire \maybe_plrus.plrus%31.plru_out ;
- wire \maybe_plrus.plrus%4.plru_acc_en ;
- wire \maybe_plrus.plrus%4.plru_out ;
- wire \maybe_plrus.plrus%5.plru_acc_en ;
- wire \maybe_plrus.plrus%5.plru_out ;
- wire \maybe_plrus.plrus%6.plru_acc_en ;
- wire \maybe_plrus.plrus%6.plru_out ;
- wire \maybe_plrus.plrus%7.plru_acc_en ;
- wire \maybe_plrus.plrus%7.plru_out ;
- wire \maybe_plrus.plrus%8.plru_acc_en ;
- wire \maybe_plrus.plrus%8.plru_out ;
- wire \maybe_plrus.plrus%9.plru_acc_en ;
- wire \maybe_plrus.plrus%9.plru_out ;
- wire priv_fault;
- wire ra_valid;
- wire \rams%0.do_write ;
- wire [63:0] \rams%0.dout ;
- wire \rams%1.do_write ;
- wire [63:0] \rams%1.dout ;
- wire [55:0] real_addr;
- wire replace_way;
- wire req_hit_way;
- wire req_is_hit;
- wire req_is_miss;
- input rst;
- output stall_out;
- wire [5:0] tlb_req_index;
- input [65:0] wishbone_in;
- output [106:0] wishbone_out;
- reg [63:0] \$mem$\1287 [63:0];
- reg [45:0] \$mem$\1290 [63:0];
- assign _1255_ = _0495_[0] ? itlb_valids[1] : itlb_valids[0];
- assign _1256_ = _0495_[0] ? itlb_valids[5] : itlb_valids[4];
- assign _1257_ = _0495_[0] ? itlb_valids[9] : itlb_valids[8];
- assign _1258_ = _0495_[0] ? itlb_valids[13] : itlb_valids[12];
- assign _1259_ = _0495_[0] ? itlb_valids[17] : itlb_valids[16];
- assign _1260_ = _0495_[0] ? itlb_valids[21] : itlb_valids[20];
- assign _1261_ = _0495_[0] ? itlb_valids[25] : itlb_valids[24];
- assign _1262_ = _0495_[0] ? itlb_valids[29] : itlb_valids[28];
- assign _1263_ = _0495_[0] ? itlb_valids[33] : itlb_valids[32];
- assign _1264_ = _0495_[0] ? itlb_valids[37] : itlb_valids[36];
- assign _1265_ = _0495_[0] ? itlb_valids[41] : itlb_valids[40];
- assign _1266_ = _0495_[0] ? itlb_valids[45] : itlb_valids[44];
- assign _1267_ = _0495_[0] ? itlb_valids[49] : itlb_valids[48];
- assign _1268_ = _0495_[0] ? itlb_valids[53] : itlb_valids[52];
- assign _1269_ = _0495_[0] ? itlb_valids[57] : itlb_valids[56];
- assign _1270_ = _0495_[0] ? itlb_valids[61] : itlb_valids[60];
- assign _1271_ = _0495_[2] ? _0612_ : _0611_;
- assign _1272_ = _0495_[2] ? _0616_ : _0615_;
- assign _1273_ = _0495_[2] ? _0620_ : _0619_;
- assign _1274_ = _0495_[2] ? _0624_ : _0623_;
- assign _1275_ = _0495_[4] ? _0628_ : _0627_;
- assign _1276_ = _0516_[0] ? cache_valids[2] : cache_valids[0];
- assign _1277_ = _0516_[0] ? cache_valids[10] : cache_valids[8];
- assign _1278_ = _0516_[0] ? cache_valids[18] : cache_valids[16];
- assign _1279_ = _0516_[0] ? cache_valids[26] : cache_valids[24];
- assign _1280_ = _0516_[0] ? cache_valids[34] : cache_valids[32];
- assign _1281_ = _0516_[0] ? cache_valids[42] : cache_valids[40];
- assign _1282_ = _0516_[0] ? cache_valids[50] : cache_valids[48];
- assign _1283_ = _0516_[0] ? cache_valids[58] : cache_valids[56];
- assign _1284_ = _0516_[2] ? _1021_ : _1020_;
- assign _1285_ = _0516_[2] ? _1025_ : _1024_;
- assign _1286_ = _0518_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _1287_ = _0518_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _1288_ = _0518_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _1289_ = _0518_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _1290_ = _0518_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _1291_ = _0518_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _1292_ = _0518_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _1293_ = _0518_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _1294_ = _0518_[2] ? _1032_ : _1031_;
- assign _1295_ = _0518_[2] ? _1036_ : _1035_;
- assign _1296_ = _0522_[0] ? cache_valids[3] : cache_valids[1];
- assign _1297_ = _0522_[0] ? cache_valids[11] : cache_valids[9];
- assign _1298_ = _0522_[0] ? cache_valids[19] : cache_valids[17];
- assign _1299_ = _0522_[0] ? cache_valids[27] : cache_valids[25];
- assign _1300_ = _0522_[0] ? cache_valids[35] : cache_valids[33];
- assign _1301_ = _0522_[0] ? cache_valids[43] : cache_valids[41];
- assign _1302_ = _0522_[0] ? cache_valids[51] : cache_valids[49];
- assign _1303_ = _0522_[0] ? cache_valids[59] : cache_valids[57];
- assign _1304_ = _0522_[2] ? _1043_ : _1042_;
- assign _1305_ = _0522_[2] ? _1047_ : _1046_;
- assign _1306_ = _0524_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _1307_ = _0524_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _1308_ = _0524_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _1309_ = _0524_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _1310_ = _0524_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _1311_ = _0524_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _1312_ = _0524_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _1313_ = _0524_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _1314_ = _0524_[2] ? _1054_ : _1053_;
- assign _1315_ = _0524_[2] ? _1058_ : _1057_;
- assign _1316_ = _0535_[0] ? \maybe_plrus.plrus%30.plru_out : \maybe_plrus.plrus%31.plru_out ;
- assign _1317_ = _0535_[0] ? \maybe_plrus.plrus%26.plru_out : \maybe_plrus.plrus%27.plru_out ;
- assign _1318_ = _0535_[0] ? \maybe_plrus.plrus%22.plru_out : \maybe_plrus.plrus%23.plru_out ;
- assign _1319_ = _0535_[0] ? \maybe_plrus.plrus%18.plru_out : \maybe_plrus.plrus%19.plru_out ;
- assign _1320_ = _0535_[0] ? \maybe_plrus.plrus%14.plru_out : \maybe_plrus.plrus%15.plru_out ;
- assign _1321_ = _0535_[0] ? \maybe_plrus.plrus%10.plru_out : \maybe_plrus.plrus%11.plru_out ;
- assign _1322_ = _0535_[0] ? \maybe_plrus.plrus%6.plru_out : \maybe_plrus.plrus%7.plru_out ;
- assign _1323_ = _0535_[0] ? \maybe_plrus.plrus%2.plru_out : \maybe_plrus.plrus%3.plru_out ;
- assign _1324_ = _0535_[2] ? _1065_ : _1064_;
- assign _1325_ = _0535_[2] ? _1069_ : _1068_;
- assign _1326_ = _0546_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _1327_ = _0546_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _1328_ = _0546_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _1329_ = _0546_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _1330_ = _0546_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _1331_ = _0546_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _1332_ = _0546_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _1333_ = _0546_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _1334_ = _0546_[2] ? _0021_ : _0019_;
- assign _1335_ = _0546_[2] ? _0025_ : _0024_;
- assign _1336_ = _0550_[0] ? cache_tags[179:90] : cache_tags[89:0];
- assign _1337_ = _0550_[0] ? cache_tags[539:450] : cache_tags[449:360];
- assign _1338_ = _0550_[0] ? cache_tags[899:810] : cache_tags[809:720];
- assign _1339_ = _0550_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
- assign _1340_ = _0550_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
- assign _1341_ = _0550_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
- assign _1342_ = _0550_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
- assign _1343_ = _0550_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
- assign _1344_ = _0550_[2] ? _0134_ : _0133_;
- assign _1345_ = _0550_[2] ? _0138_ : _0137_;
- assign _1346_ = _0495_[0] ? itlb_valids[3] : itlb_valids[2];
- assign _1347_ = _0495_[0] ? itlb_valids[7] : itlb_valids[6];
- assign _1348_ = _0495_[0] ? itlb_valids[11] : itlb_valids[10];
- assign _1349_ = _0495_[0] ? itlb_valids[15] : itlb_valids[14];
- assign _1350_ = _0495_[0] ? itlb_valids[19] : itlb_valids[18];
- assign _1351_ = _0495_[0] ? itlb_valids[23] : itlb_valids[22];
- assign _1352_ = _0495_[0] ? itlb_valids[27] : itlb_valids[26];
- assign _1353_ = _0495_[0] ? itlb_valids[31] : itlb_valids[30];
- assign _1354_ = _0495_[0] ? itlb_valids[35] : itlb_valids[34];
- assign _1355_ = _0495_[0] ? itlb_valids[39] : itlb_valids[38];
- assign _1356_ = _0495_[0] ? itlb_valids[43] : itlb_valids[42];
- assign _1357_ = _0495_[0] ? itlb_valids[47] : itlb_valids[46];
- assign _1358_ = _0495_[0] ? itlb_valids[51] : itlb_valids[50];
- assign _1359_ = _0495_[0] ? itlb_valids[55] : itlb_valids[54];
- assign _1360_ = _0495_[0] ? itlb_valids[59] : itlb_valids[58];
- assign _1361_ = _0495_[0] ? itlb_valids[63] : itlb_valids[62];
- assign _1362_ = _0495_[2] ? _0614_ : _0613_;
- assign _1363_ = _0495_[2] ? _0618_ : _0617_;
- assign _1364_ = _0495_[2] ? _0622_ : _0621_;
- assign _1365_ = _0495_[2] ? _0626_ : _0625_;
- assign _1366_ = _0495_[4] ? _0630_ : _0629_;
- assign _1367_ = _0516_[0] ? cache_valids[6] : cache_valids[4];
- assign _1368_ = _0516_[0] ? cache_valids[14] : cache_valids[12];
- assign _1369_ = _0516_[0] ? cache_valids[22] : cache_valids[20];
- assign _1370_ = _0516_[0] ? cache_valids[30] : cache_valids[28];
- assign _1371_ = _0516_[0] ? cache_valids[38] : cache_valids[36];
- assign _1372_ = _0516_[0] ? cache_valids[46] : cache_valids[44];
- assign _1373_ = _0516_[0] ? cache_valids[54] : cache_valids[52];
- assign _1374_ = _0516_[0] ? cache_valids[62] : cache_valids[60];
- assign _1375_ = _0516_[2] ? _1023_ : _1022_;
- assign _1376_ = _0516_[2] ? _1027_ : _1026_;
- assign _1377_ = _0518_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _1378_ = _0518_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _1379_ = _0518_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _1380_ = _0518_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _1381_ = _0518_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _1382_ = _0518_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _1383_ = _0518_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _1384_ = _0518_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _1385_ = _0518_[2] ? _1034_ : _1033_;
- assign _1386_ = _0518_[2] ? _1038_ : _1037_;
- assign _1387_ = _0522_[0] ? cache_valids[7] : cache_valids[5];
- assign _1388_ = _0522_[0] ? cache_valids[15] : cache_valids[13];
- assign _1389_ = _0522_[0] ? cache_valids[23] : cache_valids[21];
- assign _1390_ = _0522_[0] ? cache_valids[31] : cache_valids[29];
- assign _1391_ = _0522_[0] ? cache_valids[39] : cache_valids[37];
- assign _1392_ = _0522_[0] ? cache_valids[47] : cache_valids[45];
- assign _1393_ = _0522_[0] ? cache_valids[55] : cache_valids[53];
- assign _1394_ = _0522_[0] ? cache_valids[63] : cache_valids[61];
- assign _1395_ = _0522_[2] ? _1045_ : _1044_;
- assign _1396_ = _0522_[2] ? _1049_ : _1048_;
- assign _1397_ = _0524_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _1398_ = _0524_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _1399_ = _0524_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _1400_ = _0524_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _1401_ = _0524_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _1402_ = _0524_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _1403_ = _0524_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _1404_ = _0524_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _1405_ = _0524_[2] ? _1056_ : _1055_;
- assign _1406_ = _0524_[2] ? _1060_ : _1059_;
- assign _1407_ = _0535_[0] ? \maybe_plrus.plrus%28.plru_out : \maybe_plrus.plrus%29.plru_out ;
- assign _1408_ = _0535_[0] ? \maybe_plrus.plrus%24.plru_out : \maybe_plrus.plrus%25.plru_out ;
- assign _1409_ = _0535_[0] ? \maybe_plrus.plrus%20.plru_out : \maybe_plrus.plrus%21.plru_out ;
- assign _1410_ = _0535_[0] ? \maybe_plrus.plrus%16.plru_out : \maybe_plrus.plrus%17.plru_out ;
- assign _1411_ = _0535_[0] ? \maybe_plrus.plrus%12.plru_out : \maybe_plrus.plrus%13.plru_out ;
- assign _1412_ = _0535_[0] ? \maybe_plrus.plrus%8.plru_out : \maybe_plrus.plrus%9.plru_out ;
- assign _1413_ = _0535_[0] ? \maybe_plrus.plrus%4.plru_out : \maybe_plrus.plrus%5.plru_out ;
- assign _1414_ = _0535_[0] ? \maybe_plrus.plrus%0.plru_out : \maybe_plrus.plrus%1.plru_out ;
- assign _1415_ = _0535_[2] ? _1067_ : _1066_;
- assign _1416_ = _0535_[2] ? _1071_ : _1070_;
- assign _1417_ = _0546_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _1418_ = _0546_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _1419_ = _0546_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _1420_ = _0546_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _1421_ = _0546_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _1422_ = _0546_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _1423_ = _0546_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _1424_ = _0546_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _1425_ = _0546_[2] ? _0023_ : _0022_;
- assign _1426_ = _0546_[2] ? _0027_ : _0026_;
- assign _1427_ = _0550_[0] ? cache_tags[359:270] : cache_tags[269:180];
- assign _1428_ = _0550_[0] ? cache_tags[719:630] : cache_tags[629:540];
- assign _1429_ = _0550_[0] ? cache_tags[1079:990] : cache_tags[989:900];
- assign _1430_ = _0550_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
- assign _1431_ = _0550_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
- assign _1432_ = _0550_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
- assign _1433_ = _0550_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
- assign _1434_ = _0550_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
- assign _1435_ = _0550_[2] ? _0136_ : _0135_;
- assign _1436_ = _0550_[2] ? _0140_ : _0139_;
- assign _0611_ = _0495_[1] ? _1346_ : _1255_;
- assign _0612_ = _0495_[1] ? _1347_ : _1256_;
- assign _0613_ = _0495_[1] ? _1348_ : _1257_;
- assign _0614_ = _0495_[1] ? _1349_ : _1258_;
- assign _0615_ = _0495_[1] ? _1350_ : _1259_;
- assign _0616_ = _0495_[1] ? _1351_ : _1260_;
- assign _0617_ = _0495_[1] ? _1352_ : _1261_;
- assign _0618_ = _0495_[1] ? _1353_ : _1262_;
- assign _0619_ = _0495_[1] ? _1354_ : _1263_;
- assign _0620_ = _0495_[1] ? _1355_ : _1264_;
- assign _0621_ = _0495_[1] ? _1356_ : _1265_;
- assign _0622_ = _0495_[1] ? _1357_ : _1266_;
- assign _0623_ = _0495_[1] ? _1358_ : _1267_;
- assign _0624_ = _0495_[1] ? _1359_ : _1268_;
- assign _0625_ = _0495_[1] ? _1360_ : _1269_;
- assign _0626_ = _0495_[1] ? _1361_ : _1270_;
- assign _0627_ = _0495_[3] ? _1362_ : _1271_;
- assign _0628_ = _0495_[3] ? _1363_ : _1272_;
- assign _0629_ = _0495_[3] ? _1364_ : _1273_;
- assign _0630_ = _0495_[3] ? _1365_ : _1274_;
- assign _0631_ = _0495_[5] ? _1366_ : _1275_;
- assign _1020_ = _0516_[1] ? _1367_ : _1276_;
- assign _1021_ = _0516_[1] ? _1368_ : _1277_;
- assign _1022_ = _0516_[1] ? _1369_ : _1278_;
- assign _1023_ = _0516_[1] ? _1370_ : _1279_;
- assign _1024_ = _0516_[1] ? _1371_ : _1280_;
- assign _1025_ = _0516_[1] ? _1372_ : _1281_;
- assign _1026_ = _0516_[1] ? _1373_ : _1282_;
- assign _1027_ = _0516_[1] ? _1374_ : _1283_;
- assign _1028_ = _0516_[3] ? _1375_ : _1284_;
- assign _1029_ = _0516_[3] ? _1376_ : _1285_;
- assign _1031_ = _0518_[1] ? _1377_ : _1286_;
- assign _1032_ = _0518_[1] ? _1378_ : _1287_;
- assign _1033_ = _0518_[1] ? _1379_ : _1288_;
- assign _1034_ = _0518_[1] ? _1380_ : _1289_;
- assign _1035_ = _0518_[1] ? _1381_ : _1290_;
- assign _1036_ = _0518_[1] ? _1382_ : _1291_;
- assign _1037_ = _0518_[1] ? _1383_ : _1292_;
- assign _1038_ = _0518_[1] ? _1384_ : _1293_;
- assign _1039_ = _0518_[3] ? _1385_ : _1294_;
- assign _1040_ = _0518_[3] ? _1386_ : _1295_;
- assign _1042_ = _0522_[1] ? _1387_ : _1296_;
- assign _1043_ = _0522_[1] ? _1388_ : _1297_;
- assign _1044_ = _0522_[1] ? _1389_ : _1298_;
- assign _1045_ = _0522_[1] ? _1390_ : _1299_;
- assign _1046_ = _0522_[1] ? _1391_ : _1300_;
- assign _1047_ = _0522_[1] ? _1392_ : _1301_;
- assign _1048_ = _0522_[1] ? _1393_ : _1302_;
- assign _1049_ = _0522_[1] ? _1394_ : _1303_;
- assign _1050_ = _0522_[3] ? _1395_ : _1304_;
- assign _1051_ = _0522_[3] ? _1396_ : _1305_;
- assign _1053_ = _0524_[1] ? _1397_ : _1306_;
- assign _1054_ = _0524_[1] ? _1398_ : _1307_;
- assign _1055_ = _0524_[1] ? _1399_ : _1308_;
- assign _1056_ = _0524_[1] ? _1400_ : _1309_;
- assign _1057_ = _0524_[1] ? _1401_ : _1310_;
- assign _1058_ = _0524_[1] ? _1402_ : _1311_;
- assign _1059_ = _0524_[1] ? _1403_ : _1312_;
- assign _1060_ = _0524_[1] ? _1404_ : _1313_;
- assign _1061_ = _0524_[3] ? _1405_ : _1314_;
- assign _1062_ = _0524_[3] ? _1406_ : _1315_;
- assign _1064_ = _0535_[1] ? _1407_ : _1316_;
- assign _1065_ = _0535_[1] ? _1408_ : _1317_;
- assign _1066_ = _0535_[1] ? _1409_ : _1318_;
- assign _1067_ = _0535_[1] ? _1410_ : _1319_;
- assign _1068_ = _0535_[1] ? _1411_ : _1320_;
- assign _1069_ = _0535_[1] ? _1412_ : _1321_;
- assign _1070_ = _0535_[1] ? _1413_ : _1322_;
- assign _1071_ = _0535_[1] ? _1414_ : _1323_;
- assign _1072_ = _0535_[3] ? _1415_ : _1324_;
- assign _1073_ = _0535_[3] ? _1416_ : _1325_;
- assign _0019_ = _0546_[1] ? _1417_ : _1326_;
- assign _0021_ = _0546_[1] ? _1418_ : _1327_;
- assign _0022_ = _0546_[1] ? _1419_ : _1328_;
- assign _0023_ = _0546_[1] ? _1420_ : _1329_;
- assign _0024_ = _0546_[1] ? _1421_ : _1330_;
- assign _0025_ = _0546_[1] ? _1422_ : _1331_;
- assign _0026_ = _0546_[1] ? _1423_ : _1332_;
- assign _0027_ = _0546_[1] ? _1424_ : _1333_;
- assign _0028_ = _0546_[3] ? _1425_ : _1334_;
- assign _0029_ = _0546_[3] ? _1426_ : _1335_;
- assign _0133_ = _0550_[1] ? _1427_ : _1336_;
- assign _0134_ = _0550_[1] ? _1428_ : _1337_;
- assign _0135_ = _0550_[1] ? _1429_ : _1338_;
- assign _0136_ = _0550_[1] ? _1430_ : _1339_;
- assign _0137_ = _0550_[1] ? _1431_ : _1340_;
- assign _0138_ = _0550_[1] ? _1432_ : _1341_;
- assign _0139_ = _0550_[1] ? _1433_ : _1342_;
- assign _0140_ = _0550_[1] ? _1434_ : _1343_;
- assign _0141_ = _0550_[3] ? _1435_ : _1344_;
- assign _0142_ = _0550_[3] ? _1436_ : _1345_;
- assign _0542_ = inval_in ? 64'h0000000000000000 : cache_valids;
- assign _0543_ = inval_in ? 1'h0 : _0606_[122];
- assign _0544_ = 5'h1f - i_in[14:10];
- assign _0545_ = 32'd0 == { 31'h00000000, replace_way };
- assign _0546_ = 5'h1f - i_in[14:10];
- assign _0547_ = 5'h1f - i_in[14:10];
- assign _0548_ = _0545_ ? { _0132_, _0131_, _0130_, _0129_, _0128_, _0127_, _0126_, _0125_, _0124_, _0123_, _0122_, _0121_, _0120_, _0119_, _0118_, _0117_, _0116_, _0114_, _0113_, _0112_, _0111_, _0110_, _0109_, _0108_, _0107_, _0106_, _0105_, _0103_, _0102_, _0101_, _0100_, _0099_ } : cache_tags;
- assign _0549_ = 32'd1 == { 31'h00000000, replace_way };
- assign _0550_ = 5'h1f - i_in[14:10];
- assign _0551_ = 5'h1f - i_in[14:10];
- assign _0552_ = _0549_ ? { _0246_, _0245_, _0244_, _0243_, _0242_, _0240_, _0239_, _0238_, _0237_, _0236_, _0235_, _0234_, _0233_, _0232_, _0231_, _0229_, _0228_, _0227_, _0226_, _0225_, _0224_, _0223_, _0222_, _0221_, _0220_, _0219_, _0218_, _0217_, _0216_, _0215_, _0214_, _0213_ } : _0548_;
- assign _0553_ = req_is_miss ? _0552_ : cache_tags;
- assign _0554_ = req_is_miss ? { _0018_, _0017_, _0016_, _0015_, _0014_, _0013_, _0012_, _0011_, _0010_, _0009_, _0008_, _0007_, _0006_, _0005_, _0004_, _0003_, _0002_, _0001_, _0000_, _1254_, _1253_, _1252_, _1251_, _1250_, _1249_, _1248_, _1247_, _1246_, _1245_, _1243_, _1242_, _1241_, _1240_, _1239_, _1238_, _1237_, _1236_, _1235_, _1234_, _1232_, _1231_, _1230_, _1229_, _1228_, _1227_, _1226_, _1225_, _1224_, _1223_, _1222_, _1221_, _1220_, _1219_, _1218_, _1217_, _1216_, _1215_, _1214_, _1213_, _1212_, _1211_, _1210_, _1209_, _1208_ } : _0542_;
- assign _0555_ = req_is_miss ? { real_addr[31:6], 7'h01 } : _0606_[32:0];
- assign _0556_ = req_is_miss ? 2'h3 : _0606_[98:97];
- assign _0557_ = req_is_miss ? { 1'h1, real_addr[10:6], 3'h0, i_in[14:10], replace_way } : { _0543_, _0606_[121:108] };
- assign _0558_ = _0606_[0] == 1'h0;
- assign _0559_ = ~ _0606_[98];
- assign _0560_ = ~ wishbone_in[65];
- assign _0561_ = ~ _0559_;
- assign _0562_ = _0560_ & _0561_;
- assign _0563_ = _0606_[6:4] == 3'h7;
- assign _0564_ = _0568_ ? 1'h0 : _0606_[98];
- assign _0565_ = _0569_ ? 1'h1 : _0559_;
- assign _0566_ = _0606_[6:4] + 3'h1;
- assign _0567_ = _0562_ ? { _0606_[32:7], _0566_, _0606_[3:1] } : _0606_[32:1];
- assign _0568_ = _0562_ & _0563_;
- assign _0569_ = _0562_ & _0563_;
- assign _0570_ = _0606_[116:114] == 3'h7;
- assign _0571_ = _0565_ & _0570_;
- assign _0572_ = 5'h1f - _0606_[113:109];
- assign _0573_ = ~ inval_in;
- assign _0574_ = _0606_[122] & _0573_;
- assign _0575_ = _0579_ ? { _0449_, _0448_, _0447_, _0446_, _0445_, _0444_, _0443_, _0442_, _0441_, _0439_, _0438_, _0437_, _0436_, _0435_, _0434_, _0433_, _0432_, _0431_, _0430_, _0429_, _0428_, _0427_, _0426_, _0425_, _0424_, _0423_, _0422_, _0421_, _0420_, _0419_, _0418_, _0417_, _0416_, _0415_, _0414_, _0413_, _0412_, _0411_, _0410_, _0408_, _0407_, _0406_, _0405_, _0404_, _0403_, _0402_, _0401_, _0400_, _0399_, _0397_, _0396_, _0395_, _0394_, _0393_, _0392_, _0391_, _0390_, _0389_, _0388_, _0387_, _0386_, _0385_, _0384_, _0383_ } : _0542_;
- assign _0576_ = _0580_ ? 1'h0 : _0606_[0];
- assign _0577_ = _0581_ ? 1'h0 : _0606_[97];
- assign _0578_ = _0606_[116:114] + 3'h1;
- assign _0579_ = wishbone_in[64] & _0571_;
- assign _0580_ = wishbone_in[64] & _0571_;
- assign _0581_ = wishbone_in[64] & _0571_;
- assign _0582_ = wishbone_in[64] ? { _0606_[121:117], _0578_ } : _0606_[121:114];
- assign _0583_ = _0606_[0] == 1'h1;
- function [2879:0] \1207 ;
- input [2879:0] a;
- input [5759:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1207 = b[2879:0];
- 2'b1?:
- \1207 = b[5759:2880];
- default:
- \1207 = a;
- endcase
- endfunction
- assign _0584_ = \1207 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, _0553_ }, { _0583_, _0558_ });
- function [63:0] \1209 ;
- input [63:0] a;
- input [127:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1209 = b[63:0];
- 2'b1?:
- \1209 = b[127:64];
- default:
- \1209 = a;
- endcase
- endfunction
- assign _0585_ = \1209 (64'hxxxxxxxxxxxxxxxx, { _0575_, _0554_ }, { _0583_, _0558_ });
- function [0:0] \1212 ;
- input [0:0] a;
- input [1:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1212 = b[0:0];
- 2'b1?:
- \1212 = b[1:1];
- default:
- \1212 = a;
- endcase
- endfunction
- assign _0586_ = \1212 (1'hx, { _0576_, _0555_[0] }, { _0583_, _0558_ });
- function [31:0] \1215 ;
- input [31:0] a;
- input [63:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1215 = b[31:0];
- 2'b1?:
- \1215 = b[63:32];
- default:
- \1215 = a;
- endcase
- endfunction
- assign _0587_ = \1215 (32'hxxxxxxxx, { _0567_, _0555_[32:1] }, { _0583_, _0558_ });
- function [0:0] \1218 ;
- input [0:0] a;
- input [1:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1218 = b[0:0];
- 2'b1?:
- \1218 = b[1:1];
- default:
- \1218 = a;
- endcase
- endfunction
- assign _0588_ = \1218 (1'hx, { _0577_, _0556_[0] }, { _0583_, _0558_ });
- function [0:0] \1221 ;
- input [0:0] a;
- input [1:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1221 = b[0:0];
- 2'b1?:
- \1221 = b[1:1];
- default:
- \1221 = a;
- endcase
- endfunction
- assign _0589_ = \1221 (1'hx, { _0564_, _0556_[1] }, { _0583_, _0558_ });
- function [5:0] \1225 ;
- input [5:0] a;
- input [11:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1225 = b[5:0];
- 2'b1?:
- \1225 = b[11:6];
- default:
- \1225 = a;
- endcase
- endfunction
- assign _0590_ = \1225 (6'hxx, { _0606_[113:108], _0557_[5:0] }, { _0583_, _0558_ });
- function [7:0] \1228 ;
- input [7:0] a;
- input [15:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1228 = b[7:0];
- 2'b1?:
- \1228 = b[15:8];
- default:
- \1228 = a;
- endcase
- endfunction
- assign _0591_ = \1228 (8'hxx, { _0582_, _0557_[13:6] }, { _0583_, _0558_ });
- function [0:0] \1231 ;
- input [0:0] a;
- input [1:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \1231 = b[0:0];
- 2'b1?:
- \1231 = b[1:1];
- default:
- \1231 = a;
- endcase
- endfunction
- assign _0592_ = \1231 (1'hx, { _0543_, _0557_[14] }, { _0583_, _0558_ });
- assign _0593_ = rst ? cache_tags : _0584_;
- assign _0594_ = rst ? 64'h0000000000000000 : _0585_;
- assign _0595_ = rst ? 33'h000000000 : { _0587_, _0586_ };
- assign _0596_ = rst ? 64'h0000000000000000 : _0606_[96:33];
- assign _0597_ = rst ? 2'h0 : { _0589_, _0588_ };
- assign _0598_ = rst ? 9'h0ff : _0606_[107:99];
- assign _0599_ = rst ? _0606_[122:108] : { _0592_, _0591_, _0590_ };
- assign _0600_ = rst | flush_in;
- assign _0601_ = _0600_ | m_in[0];
- assign _0602_ = ~ access_ok;
- assign _0603_ = i_in[0] & _0602_;
- assign _0604_ = _0603_ ? 1'h1 : _0606_[123];
- assign _0605_ = _0601_ ? 1'h0 : _0604_;
- always @(posedge clk)
- cache_tags <= _0593_;
- always @(posedge clk)
- cache_valids <= _0594_;
- always @(posedge clk)
- _0606_ <= { _0605_, _0599_, _0598_, _0597_, _0596_, _0595_ };
- (* ram_style = "distributed" *)
- reg [63:0] \1287 [63:0];
- always @(posedge clk) begin
- if (_0515_) \1287 [_0500_] <= m_in[130:67];
- end
- assign _0608_ = \1287 [tlb_req_index];
- (* ram_style = "distributed" *)
- reg [45:0] \1290 [63:0];
- always @(posedge clk) begin
- if (_0511_) \1290 [_0500_] <= m_in[66:21];
- end
- assign _0610_ = \1290 [tlb_req_index];
- assign _0632_ = ~ _0503_[5];
- assign _0633_ = ~ _0503_[4];
- assign _0634_ = _0632_ & _0633_;
- assign _0635_ = _0632_ & _0503_[4];
- assign _0636_ = _0503_[5] & _0633_;
- assign _0637_ = _0503_[5] & _0503_[4];
- assign _0638_ = ~ _0503_[3];
- assign _0639_ = _0634_ & _0638_;
- assign _0640_ = _0634_ & _0503_[3];
- assign _0641_ = _0635_ & _0638_;
- assign _0642_ = _0635_ & _0503_[3];
- assign _0643_ = _0636_ & _0638_;
- assign _0644_ = _0636_ & _0503_[3];
- assign _0645_ = _0637_ & _0638_;
- assign _0646_ = _0637_ & _0503_[3];
- assign _0647_ = ~ _0503_[2];
- assign _0648_ = _0639_ & _0647_;
- assign _0649_ = _0639_ & _0503_[2];
- assign _0650_ = _0640_ & _0647_;
- assign _0651_ = _0640_ & _0503_[2];
- assign _0652_ = _0641_ & _0647_;
- assign _0653_ = _0641_ & _0503_[2];
- assign _0654_ = _0642_ & _0647_;
- assign _0655_ = _0642_ & _0503_[2];
- assign _0656_ = _0643_ & _0647_;
- assign _0657_ = _0643_ & _0503_[2];
- assign _0658_ = _0644_ & _0647_;
- assign _0659_ = _0644_ & _0503_[2];
- assign _0660_ = _0645_ & _0647_;
- assign _0661_ = _0645_ & _0503_[2];
- assign _0662_ = _0646_ & _0647_;
- assign _0663_ = _0646_ & _0503_[2];
- assign _0664_ = ~ _0503_[1];
- assign _0665_ = _0648_ & _0664_;
- assign _0666_ = _0648_ & _0503_[1];
- assign _0667_ = _0649_ & _0664_;
- assign _0668_ = _0649_ & _0503_[1];
- assign _0669_ = _0650_ & _0664_;
- assign _0670_ = _0650_ & _0503_[1];
- assign _0671_ = _0651_ & _0664_;
- assign _0672_ = _0651_ & _0503_[1];
- assign _0673_ = _0652_ & _0664_;
- assign _0674_ = _0652_ & _0503_[1];
- assign _0675_ = _0653_ & _0664_;
- assign _0676_ = _0653_ & _0503_[1];
- assign _0677_ = _0654_ & _0664_;
- assign _0678_ = _0654_ & _0503_[1];
- assign _0679_ = _0655_ & _0664_;
- assign _0680_ = _0655_ & _0503_[1];
- assign _0681_ = _0656_ & _0664_;
- assign _0682_ = _0656_ & _0503_[1];
- assign _0683_ = _0657_ & _0664_;
- assign _0684_ = _0657_ & _0503_[1];
- assign _0685_ = _0658_ & _0664_;
- assign _0686_ = _0658_ & _0503_[1];
- assign _0687_ = _0659_ & _0664_;
- assign _0688_ = _0659_ & _0503_[1];
- assign _0689_ = _0660_ & _0664_;
- assign _0690_ = _0660_ & _0503_[1];
- assign _0691_ = _0661_ & _0664_;
- assign _0692_ = _0661_ & _0503_[1];
- assign _0693_ = _0662_ & _0664_;
- assign _0694_ = _0662_ & _0503_[1];
- assign _0695_ = _0663_ & _0664_;
- assign _0696_ = _0663_ & _0503_[1];
- assign _0697_ = ~ _0503_[0];
- assign _0698_ = _0665_ & _0697_;
- assign _0699_ = _0665_ & _0503_[0];
- assign _0700_ = _0666_ & _0697_;
- assign _0701_ = _0666_ & _0503_[0];
- assign _0702_ = _0667_ & _0697_;
- assign _0703_ = _0667_ & _0503_[0];
- assign _0704_ = _0668_ & _0697_;
- assign _0705_ = _0668_ & _0503_[0];
- assign _0706_ = _0669_ & _0697_;
- assign _0707_ = _0669_ & _0503_[0];
- assign _0708_ = _0670_ & _0697_;
- assign _0709_ = _0670_ & _0503_[0];
- assign _0710_ = _0671_ & _0697_;
- assign _0711_ = _0671_ & _0503_[0];
- assign _0712_ = _0672_ & _0697_;
- assign _0713_ = _0672_ & _0503_[0];
- assign _0714_ = _0673_ & _0697_;
- assign _0715_ = _0673_ & _0503_[0];
- assign _0716_ = _0674_ & _0697_;
- assign _0717_ = _0674_ & _0503_[0];
- assign _0718_ = _0675_ & _0697_;
- assign _0719_ = _0675_ & _0503_[0];
- assign _0720_ = _0676_ & _0697_;
- assign _0721_ = _0676_ & _0503_[0];
- assign _0722_ = _0677_ & _0697_;
- assign _0723_ = _0677_ & _0503_[0];
- assign _0724_ = _0678_ & _0697_;
- assign _0725_ = _0678_ & _0503_[0];
- assign _0726_ = _0679_ & _0697_;
- assign _0727_ = _0679_ & _0503_[0];
- assign _0728_ = _0680_ & _0697_;
- assign _0729_ = _0680_ & _0503_[0];
- assign _0730_ = _0681_ & _0697_;
- assign _0731_ = _0681_ & _0503_[0];
- assign _0732_ = _0682_ & _0697_;
- assign _0733_ = _0682_ & _0503_[0];
- assign _0734_ = _0683_ & _0697_;
- assign _0735_ = _0683_ & _0503_[0];
- assign _0736_ = _0684_ & _0697_;
- assign _0737_ = _0684_ & _0503_[0];
- assign _0738_ = _0685_ & _0697_;
- assign _0739_ = _0685_ & _0503_[0];
- assign _0740_ = _0686_ & _0697_;
- assign _0741_ = _0686_ & _0503_[0];
- assign _0742_ = _0687_ & _0697_;
- assign _0743_ = _0687_ & _0503_[0];
- assign _0744_ = _0688_ & _0697_;
- assign _0745_ = _0688_ & _0503_[0];
- assign _0746_ = _0689_ & _0697_;
- assign _0747_ = _0689_ & _0503_[0];
- assign _0748_ = _0690_ & _0697_;
- assign _0749_ = _0690_ & _0503_[0];
- assign _0750_ = _0691_ & _0697_;
- assign _0751_ = _0691_ & _0503_[0];
- assign _0752_ = _0692_ & _0697_;
- assign _0753_ = _0692_ & _0503_[0];
- assign _0754_ = _0693_ & _0697_;
- assign _0755_ = _0693_ & _0503_[0];
- assign _0756_ = _0694_ & _0697_;
- assign _0757_ = _0694_ & _0503_[0];
- assign _0758_ = _0695_ & _0697_;
- assign _0759_ = _0695_ & _0503_[0];
- assign _0760_ = _0696_ & _0697_;
- assign _0761_ = _0696_ & _0503_[0];
- assign _0762_ = _0698_ ? 1'h0 : itlb_valids[0];
- assign _0763_ = _0699_ ? 1'h0 : itlb_valids[1];
- assign _0764_ = _0700_ ? 1'h0 : itlb_valids[2];
- assign _0765_ = _0701_ ? 1'h0 : itlb_valids[3];
- assign _0766_ = _0702_ ? 1'h0 : itlb_valids[4];
- assign _0767_ = _0703_ ? 1'h0 : itlb_valids[5];
- assign _0768_ = _0704_ ? 1'h0 : itlb_valids[6];
- assign _0769_ = _0705_ ? 1'h0 : itlb_valids[7];
- assign _0770_ = _0706_ ? 1'h0 : itlb_valids[8];
- assign _0771_ = _0707_ ? 1'h0 : itlb_valids[9];
- assign _0772_ = _0708_ ? 1'h0 : itlb_valids[10];
- assign _0773_ = _0709_ ? 1'h0 : itlb_valids[11];
- assign _0774_ = _0710_ ? 1'h0 : itlb_valids[12];
- assign _0775_ = _0711_ ? 1'h0 : itlb_valids[13];
- assign _0776_ = _0712_ ? 1'h0 : itlb_valids[14];
- assign _0777_ = _0713_ ? 1'h0 : itlb_valids[15];
- assign _0778_ = _0714_ ? 1'h0 : itlb_valids[16];
- assign _0779_ = _0715_ ? 1'h0 : itlb_valids[17];
- assign _0780_ = _0716_ ? 1'h0 : itlb_valids[18];
- assign _0781_ = _0717_ ? 1'h0 : itlb_valids[19];
- assign _0782_ = _0718_ ? 1'h0 : itlb_valids[20];
- assign _0783_ = _0719_ ? 1'h0 : itlb_valids[21];
- assign _0784_ = _0720_ ? 1'h0 : itlb_valids[22];
- assign _0785_ = _0721_ ? 1'h0 : itlb_valids[23];
- assign _0786_ = _0722_ ? 1'h0 : itlb_valids[24];
- assign _0787_ = _0723_ ? 1'h0 : itlb_valids[25];
- assign _0788_ = _0724_ ? 1'h0 : itlb_valids[26];
- assign _0789_ = _0725_ ? 1'h0 : itlb_valids[27];
- assign _0790_ = _0726_ ? 1'h0 : itlb_valids[28];
- assign _0791_ = _0727_ ? 1'h0 : itlb_valids[29];
- assign _0792_ = _0728_ ? 1'h0 : itlb_valids[30];
- assign _0793_ = _0729_ ? 1'h0 : itlb_valids[31];
- assign _0794_ = _0730_ ? 1'h0 : itlb_valids[32];
- assign _0795_ = _0731_ ? 1'h0 : itlb_valids[33];
- assign _0796_ = _0732_ ? 1'h0 : itlb_valids[34];
- assign _0797_ = _0733_ ? 1'h0 : itlb_valids[35];
- assign _0798_ = _0734_ ? 1'h0 : itlb_valids[36];
- assign _0799_ = _0735_ ? 1'h0 : itlb_valids[37];
- assign _0800_ = _0736_ ? 1'h0 : itlb_valids[38];
- assign _0801_ = _0737_ ? 1'h0 : itlb_valids[39];
- assign _0802_ = _0738_ ? 1'h0 : itlb_valids[40];
- assign _0803_ = _0739_ ? 1'h0 : itlb_valids[41];
- assign _0804_ = _0740_ ? 1'h0 : itlb_valids[42];
- assign _0805_ = _0741_ ? 1'h0 : itlb_valids[43];
- assign _0806_ = _0742_ ? 1'h0 : itlb_valids[44];
- assign _0807_ = _0743_ ? 1'h0 : itlb_valids[45];
- assign _0808_ = _0744_ ? 1'h0 : itlb_valids[46];
- assign _0809_ = _0745_ ? 1'h0 : itlb_valids[47];
- assign _0810_ = _0746_ ? 1'h0 : itlb_valids[48];
- assign _0811_ = _0747_ ? 1'h0 : itlb_valids[49];
- assign _0812_ = _0748_ ? 1'h0 : itlb_valids[50];
- assign _0813_ = _0749_ ? 1'h0 : itlb_valids[51];
- assign _0814_ = _0750_ ? 1'h0 : itlb_valids[52];
- assign _0815_ = _0751_ ? 1'h0 : itlb_valids[53];
- assign _0816_ = _0752_ ? 1'h0 : itlb_valids[54];
- assign _0817_ = _0753_ ? 1'h0 : itlb_valids[55];
- assign _0818_ = _0754_ ? 1'h0 : itlb_valids[56];
- assign _0819_ = _0755_ ? 1'h0 : itlb_valids[57];
- assign _0820_ = _0756_ ? 1'h0 : itlb_valids[58];
- assign _0821_ = _0757_ ? 1'h0 : itlb_valids[59];
- assign _0822_ = _0758_ ? 1'h0 : itlb_valids[60];
- assign _0823_ = _0759_ ? 1'h0 : itlb_valids[61];
- assign _0824_ = _0760_ ? 1'h0 : itlb_valids[62];
- assign _0825_ = _0761_ ? 1'h0 : itlb_valids[63];
- assign _0826_ = ~ _0504_[5];
- assign _0827_ = ~ _0504_[4];
- assign _0828_ = _0826_ & _0827_;
- assign _0829_ = _0826_ & _0504_[4];
- assign _0830_ = _0504_[5] & _0827_;
- assign _0831_ = _0504_[5] & _0504_[4];
- assign _0832_ = ~ _0504_[3];
- assign _0833_ = _0828_ & _0832_;
- assign _0834_ = _0828_ & _0504_[3];
- assign _0835_ = _0829_ & _0832_;
- assign _0836_ = _0829_ & _0504_[3];
- assign _0837_ = _0830_ & _0832_;
- assign _0838_ = _0830_ & _0504_[3];
- assign _0839_ = _0831_ & _0832_;
- assign _0840_ = _0831_ & _0504_[3];
- assign _0841_ = ~ _0504_[2];
- assign _0842_ = _0833_ & _0841_;
- assign _0843_ = _0833_ & _0504_[2];
- assign _0844_ = _0834_ & _0841_;
- assign _0845_ = _0834_ & _0504_[2];
- assign _0846_ = _0835_ & _0841_;
- assign _0847_ = _0835_ & _0504_[2];
- assign _0848_ = _0836_ & _0841_;
- assign _0849_ = _0836_ & _0504_[2];
- assign _0850_ = _0837_ & _0841_;
- assign _0851_ = _0837_ & _0504_[2];
- assign _0852_ = _0838_ & _0841_;
- assign _0853_ = _0838_ & _0504_[2];
- assign _0854_ = _0839_ & _0841_;
- assign _0855_ = _0839_ & _0504_[2];
- assign _0856_ = _0840_ & _0841_;
- assign _0857_ = _0840_ & _0504_[2];
- assign _0858_ = ~ _0504_[1];
- assign _0859_ = _0842_ & _0858_;
- assign _0860_ = _0842_ & _0504_[1];
- assign _0861_ = _0843_ & _0858_;
- assign _0862_ = _0843_ & _0504_[1];
- assign _0863_ = _0844_ & _0858_;
- assign _0864_ = _0844_ & _0504_[1];
- assign _0865_ = _0845_ & _0858_;
- assign _0866_ = _0845_ & _0504_[1];
- assign _0867_ = _0846_ & _0858_;
- assign _0868_ = _0846_ & _0504_[1];
- assign _0869_ = _0847_ & _0858_;
- assign _0870_ = _0847_ & _0504_[1];
- assign _0871_ = _0848_ & _0858_;
- assign _0872_ = _0848_ & _0504_[1];
- assign _0873_ = _0849_ & _0858_;
- assign _0874_ = _0849_ & _0504_[1];
- assign _0875_ = _0850_ & _0858_;
- assign _0876_ = _0850_ & _0504_[1];
- assign _0877_ = _0851_ & _0858_;
- assign _0878_ = _0851_ & _0504_[1];
- assign _0879_ = _0852_ & _0858_;
- assign _0880_ = _0852_ & _0504_[1];
- assign _0881_ = _0853_ & _0858_;
- assign _0882_ = _0853_ & _0504_[1];
- assign _0883_ = _0854_ & _0858_;
- assign _0884_ = _0854_ & _0504_[1];
- assign _0885_ = _0855_ & _0858_;
- assign _0886_ = _0855_ & _0504_[1];
- assign _0887_ = _0856_ & _0858_;
- assign _0888_ = _0856_ & _0504_[1];
- assign _0889_ = _0857_ & _0858_;
- assign _0890_ = _0857_ & _0504_[1];
- assign _0891_ = ~ _0504_[0];
- assign _0892_ = _0859_ & _0891_;
- assign _0893_ = _0859_ & _0504_[0];
- assign _0894_ = _0860_ & _0891_;
- assign _0895_ = _0860_ & _0504_[0];
- assign _0896_ = _0861_ & _0891_;
- assign _0897_ = _0861_ & _0504_[0];
- assign _0898_ = _0862_ & _0891_;
- assign _0899_ = _0862_ & _0504_[0];
- assign _0900_ = _0863_ & _0891_;
- assign _0901_ = _0863_ & _0504_[0];
- assign _0902_ = _0864_ & _0891_;
- assign _0903_ = _0864_ & _0504_[0];
- assign _0904_ = _0865_ & _0891_;
- assign _0905_ = _0865_ & _0504_[0];
- assign _0906_ = _0866_ & _0891_;
- assign _0907_ = _0866_ & _0504_[0];
- assign _0908_ = _0867_ & _0891_;
- assign _0909_ = _0867_ & _0504_[0];
- assign _0910_ = _0868_ & _0891_;
- assign _0911_ = _0868_ & _0504_[0];
- assign _0912_ = _0869_ & _0891_;
- assign _0913_ = _0869_ & _0504_[0];
- assign _0914_ = _0870_ & _0891_;
- assign _0915_ = _0870_ & _0504_[0];
- assign _0916_ = _0871_ & _0891_;
- assign _0917_ = _0871_ & _0504_[0];
- assign _0918_ = _0872_ & _0891_;
- assign _0919_ = _0872_ & _0504_[0];
- assign _0920_ = _0873_ & _0891_;
- assign _0921_ = _0873_ & _0504_[0];
- assign _0922_ = _0874_ & _0891_;
- assign _0923_ = _0874_ & _0504_[0];
- assign _0924_ = _0875_ & _0891_;
- assign _0925_ = _0875_ & _0504_[0];
- assign _0926_ = _0876_ & _0891_;
- assign _0927_ = _0876_ & _0504_[0];
- assign _0928_ = _0877_ & _0891_;
- assign _0929_ = _0877_ & _0504_[0];
- assign _0930_ = _0878_ & _0891_;
- assign _0931_ = _0878_ & _0504_[0];
- assign _0932_ = _0879_ & _0891_;
- assign _0933_ = _0879_ & _0504_[0];
- assign _0934_ = _0880_ & _0891_;
- assign _0935_ = _0880_ & _0504_[0];
- assign _0936_ = _0881_ & _0891_;
- assign _0937_ = _0881_ & _0504_[0];
- assign _0938_ = _0882_ & _0891_;
- assign _0939_ = _0882_ & _0504_[0];
- assign _0940_ = _0883_ & _0891_;
- assign _0941_ = _0883_ & _0504_[0];
- assign _0942_ = _0884_ & _0891_;
- assign _0943_ = _0884_ & _0504_[0];
- assign _0944_ = _0885_ & _0891_;
- assign _0945_ = _0885_ & _0504_[0];
- assign _0946_ = _0886_ & _0891_;
- assign _0947_ = _0886_ & _0504_[0];
- assign _0948_ = _0887_ & _0891_;
- assign _0949_ = _0887_ & _0504_[0];
- assign _0950_ = _0888_ & _0891_;
- assign _0951_ = _0888_ & _0504_[0];
- assign _0952_ = _0889_ & _0891_;
- assign _0953_ = _0889_ & _0504_[0];
- assign _0954_ = _0890_ & _0891_;
- assign _0955_ = _0890_ & _0504_[0];
- assign _0956_ = _0892_ ? 1'h1 : itlb_valids[0];
- assign _0957_ = _0893_ ? 1'h1 : itlb_valids[1];
- assign _0958_ = _0894_ ? 1'h1 : itlb_valids[2];
- assign _0959_ = _0895_ ? 1'h1 : itlb_valids[3];
- assign _0960_ = _0896_ ? 1'h1 : itlb_valids[4];
- assign _0961_ = _0897_ ? 1'h1 : itlb_valids[5];
- assign _0962_ = _0898_ ? 1'h1 : itlb_valids[6];
- assign _0963_ = _0899_ ? 1'h1 : itlb_valids[7];
- assign _0964_ = _0900_ ? 1'h1 : itlb_valids[8];
- assign _0965_ = _0901_ ? 1'h1 : itlb_valids[9];
- assign _0966_ = _0902_ ? 1'h1 : itlb_valids[10];
- assign _0967_ = _0903_ ? 1'h1 : itlb_valids[11];
- assign _0968_ = _0904_ ? 1'h1 : itlb_valids[12];
- assign _0969_ = _0905_ ? 1'h1 : itlb_valids[13];
- assign _0970_ = _0906_ ? 1'h1 : itlb_valids[14];
- assign _0971_ = _0907_ ? 1'h1 : itlb_valids[15];
- assign _0972_ = _0908_ ? 1'h1 : itlb_valids[16];
- assign _0973_ = _0909_ ? 1'h1 : itlb_valids[17];
- assign _0974_ = _0910_ ? 1'h1 : itlb_valids[18];
- assign _0975_ = _0911_ ? 1'h1 : itlb_valids[19];
- assign _0976_ = _0912_ ? 1'h1 : itlb_valids[20];
- assign _0977_ = _0913_ ? 1'h1 : itlb_valids[21];
- assign _0978_ = _0914_ ? 1'h1 : itlb_valids[22];
- assign _0979_ = _0915_ ? 1'h1 : itlb_valids[23];
- assign _0980_ = _0916_ ? 1'h1 : itlb_valids[24];
- assign _0981_ = _0917_ ? 1'h1 : itlb_valids[25];
- assign _0982_ = _0918_ ? 1'h1 : itlb_valids[26];
- assign _0983_ = _0919_ ? 1'h1 : itlb_valids[27];
- assign _0984_ = _0920_ ? 1'h1 : itlb_valids[28];
- assign _0985_ = _0921_ ? 1'h1 : itlb_valids[29];
- assign _0986_ = _0922_ ? 1'h1 : itlb_valids[30];
- assign _0987_ = _0923_ ? 1'h1 : itlb_valids[31];
- assign _0988_ = _0924_ ? 1'h1 : itlb_valids[32];
- assign _0989_ = _0925_ ? 1'h1 : itlb_valids[33];
- assign _0990_ = _0926_ ? 1'h1 : itlb_valids[34];
- assign _0991_ = _0927_ ? 1'h1 : itlb_valids[35];
- assign _0992_ = _0928_ ? 1'h1 : itlb_valids[36];
- assign _0993_ = _0929_ ? 1'h1 : itlb_valids[37];
- assign _0994_ = _0930_ ? 1'h1 : itlb_valids[38];
- assign _0995_ = _0931_ ? 1'h1 : itlb_valids[39];
- assign _0996_ = _0932_ ? 1'h1 : itlb_valids[40];
- assign _0997_ = _0933_ ? 1'h1 : itlb_valids[41];
- assign _0998_ = _0934_ ? 1'h1 : itlb_valids[42];
- assign _0999_ = _0935_ ? 1'h1 : itlb_valids[43];
- assign _1000_ = _0936_ ? 1'h1 : itlb_valids[44];
- assign _1001_ = _0937_ ? 1'h1 : itlb_valids[45];
- assign _1002_ = _0938_ ? 1'h1 : itlb_valids[46];
- assign _1003_ = _0939_ ? 1'h1 : itlb_valids[47];
- assign _1004_ = _0940_ ? 1'h1 : itlb_valids[48];
- assign _1005_ = _0941_ ? 1'h1 : itlb_valids[49];
- assign _1006_ = _0942_ ? 1'h1 : itlb_valids[50];
- assign _1007_ = _0943_ ? 1'h1 : itlb_valids[51];
- assign _1008_ = _0944_ ? 1'h1 : itlb_valids[52];
- assign _1009_ = _0945_ ? 1'h1 : itlb_valids[53];
- assign _1010_ = _0946_ ? 1'h1 : itlb_valids[54];
- assign _1011_ = _0947_ ? 1'h1 : itlb_valids[55];
- assign _1012_ = _0948_ ? 1'h1 : itlb_valids[56];
- assign _1013_ = _0949_ ? 1'h1 : itlb_valids[57];
- assign _1014_ = _0950_ ? 1'h1 : itlb_valids[58];
- assign _1015_ = _0951_ ? 1'h1 : itlb_valids[59];
- assign _1016_ = _0952_ ? 1'h1 : itlb_valids[60];
- assign _1017_ = _0953_ ? 1'h1 : itlb_valids[61];
- assign _1018_ = _0954_ ? 1'h1 : itlb_valids[62];
- assign _1019_ = _0955_ ? 1'h1 : itlb_valids[63];
- assign _1030_ = _0516_[4] ? _1029_ : _1028_;
- assign _1041_ = _0518_[4] ? _1040_ : _1039_;
- assign _1052_ = _0522_[4] ? _1051_ : _1050_;
- assign _1063_ = _0524_[4] ? _1062_ : _1061_;
- assign replace_way = _0535_[4] ? _1073_ : _1072_;
- assign _1074_ = _0536_ ? \rams%0.dout : \rams%1.dout ;
- assign _1075_ = _0541_[3] ? _1074_[63:32] : _1074_[31:0];
- assign _1076_ = ~ _0544_[4];
- assign _1077_ = ~ _0544_[3];
- assign _1078_ = _1076_ & _1077_;
- assign _1079_ = _1076_ & _0544_[3];
- assign _1080_ = _0544_[4] & _1077_;
- assign _1081_ = _0544_[4] & _0544_[3];
- assign _1082_ = ~ _0544_[2];
- assign _1083_ = _1078_ & _1082_;
- assign _1084_ = _1078_ & _0544_[2];
- assign _1085_ = _1079_ & _1082_;
- assign _1086_ = _1079_ & _0544_[2];
- assign _1087_ = _1080_ & _1082_;
- assign _1088_ = _1080_ & _0544_[2];
- assign _1089_ = _1081_ & _1082_;
- assign _1090_ = _1081_ & _0544_[2];
- assign _1091_ = ~ _0544_[1];
- assign _1092_ = _1083_ & _1091_;
- assign _1093_ = _1083_ & _0544_[1];
- assign _1094_ = _1084_ & _1091_;
- assign _1095_ = _1084_ & _0544_[1];
- assign _1096_ = _1085_ & _1091_;
- assign _1097_ = _1085_ & _0544_[1];
- assign _1098_ = _1086_ & _1091_;
- assign _1099_ = _1086_ & _0544_[1];
- assign _1100_ = _1087_ & _1091_;
- assign _1101_ = _1087_ & _0544_[1];
- assign _1102_ = _1088_ & _1091_;
- assign _1103_ = _1088_ & _0544_[1];
- assign _1104_ = _1089_ & _1091_;
- assign _1105_ = _1089_ & _0544_[1];
- assign _1106_ = _1090_ & _1091_;
- assign _1107_ = _1090_ & _0544_[1];
- assign _1108_ = ~ _0544_[0];
- assign _1109_ = _1092_ & _1108_;
- assign _1110_ = _1092_ & _0544_[0];
- assign _1111_ = _1093_ & _1108_;
- assign _1112_ = _1093_ & _0544_[0];
- assign _1113_ = _1094_ & _1108_;
- assign _1114_ = _1094_ & _0544_[0];
- assign _1115_ = _1095_ & _1108_;
- assign _1116_ = _1095_ & _0544_[0];
- assign _1117_ = _1096_ & _1108_;
- assign _1118_ = _1096_ & _0544_[0];
- assign _1119_ = _1097_ & _1108_;
- assign _1120_ = _1097_ & _0544_[0];
- assign _1121_ = _1098_ & _1108_;
- assign _1122_ = _1098_ & _0544_[0];
- assign _1123_ = _1099_ & _1108_;
- assign _1124_ = _1099_ & _0544_[0];
- assign _1125_ = _1100_ & _1108_;
- assign _1126_ = _1100_ & _0544_[0];
- assign _1127_ = _1101_ & _1108_;
- assign _1128_ = _1101_ & _0544_[0];
- assign _1129_ = _1102_ & _1108_;
- assign _1130_ = _1102_ & _0544_[0];
- assign _1131_ = _1103_ & _1108_;
- assign _1132_ = _1103_ & _0544_[0];
- assign _1133_ = _1104_ & _1108_;
- assign _1134_ = _1104_ & _0544_[0];
- assign _1135_ = _1105_ & _1108_;
- assign _1136_ = _1105_ & _0544_[0];
- assign _1137_ = _1106_ & _1108_;
- assign _1138_ = _1106_ & _0544_[0];
- assign _1139_ = _1107_ & _1108_;
- assign _1140_ = _1107_ & _0544_[0];
- assign _1141_ = ~ replace_way;
- assign _1142_ = _1109_ & _1141_;
- assign _1143_ = _1109_ & replace_way;
- assign _1144_ = _1110_ & _1141_;
- assign _1145_ = _1110_ & replace_way;
- assign _1146_ = _1111_ & _1141_;
- assign _1147_ = _1111_ & replace_way;
- assign _1148_ = _1112_ & _1141_;
- assign _1149_ = _1112_ & replace_way;
- assign _1150_ = _1113_ & _1141_;
- assign _1151_ = _1113_ & replace_way;
- assign _1152_ = _1114_ & _1141_;
- assign _1153_ = _1114_ & replace_way;
- assign _1154_ = _1115_ & _1141_;
- assign _1155_ = _1115_ & replace_way;
- assign _1156_ = _1116_ & _1141_;
- assign _1157_ = _1116_ & replace_way;
- assign _1158_ = _1117_ & _1141_;
- assign _1159_ = _1117_ & replace_way;
- assign _1160_ = _1118_ & _1141_;
- assign _1161_ = _1118_ & replace_way;
- assign _1162_ = _1119_ & _1141_;
- assign _1163_ = _1119_ & replace_way;
- assign _1164_ = _1120_ & _1141_;
- assign _1165_ = _1120_ & replace_way;
- assign _1166_ = _1121_ & _1141_;
- assign _1167_ = _1121_ & replace_way;
- assign _1168_ = _1122_ & _1141_;
- assign _1169_ = _1122_ & replace_way;
- assign _1170_ = _1123_ & _1141_;
- assign _1171_ = _1123_ & replace_way;
- assign _1172_ = _1124_ & _1141_;
- assign _1173_ = _1124_ & replace_way;
- assign _1174_ = _1125_ & _1141_;
- assign _1175_ = _1125_ & replace_way;
- assign _1176_ = _1126_ & _1141_;
- assign _1177_ = _1126_ & replace_way;
- assign _1178_ = _1127_ & _1141_;
- assign _1179_ = _1127_ & replace_way;
- assign _1180_ = _1128_ & _1141_;
- assign _1181_ = _1128_ & replace_way;
- assign _1182_ = _1129_ & _1141_;
- assign _1183_ = _1129_ & replace_way;
- assign _1184_ = _1130_ & _1141_;
- assign _1185_ = _1130_ & replace_way;
- assign _1186_ = _1131_ & _1141_;
- assign _1187_ = _1131_ & replace_way;
- assign _1188_ = _1132_ & _1141_;
- assign _1189_ = _1132_ & replace_way;
- assign _1190_ = _1133_ & _1141_;
- assign _1192_ = _1133_ & replace_way;
- assign _1193_ = _1134_ & _1141_;
- assign _1194_ = _1134_ & replace_way;
- assign _1195_ = _1135_ & _1141_;
- assign _1196_ = _1135_ & replace_way;
- assign _1197_ = _1136_ & _1141_;
- assign _1198_ = _1136_ & replace_way;
- assign _1199_ = _1137_ & _1141_;
- assign _1200_ = _1137_ & replace_way;
- assign _1201_ = _1138_ & _1141_;
- assign _1203_ = _1138_ & replace_way;
- assign _1204_ = _1139_ & _1141_;
- assign _1205_ = _1139_ & replace_way;
- assign _1206_ = _1140_ & _1141_;
- assign _1207_ = _1140_ & replace_way;
- assign _1208_ = _1142_ ? 1'h0 : _0542_[0];
- assign _1209_ = _1143_ ? 1'h0 : _0542_[1];
- assign _1210_ = _1144_ ? 1'h0 : _0542_[2];
- assign _1211_ = _1145_ ? 1'h0 : _0542_[3];
- assign _1212_ = _1146_ ? 1'h0 : _0542_[4];
- assign _1213_ = _1147_ ? 1'h0 : _0542_[5];
- assign _1214_ = _1148_ ? 1'h0 : _0542_[6];
- assign _1215_ = _1149_ ? 1'h0 : _0542_[7];
- assign _1216_ = _1150_ ? 1'h0 : _0542_[8];
- assign _1217_ = _1151_ ? 1'h0 : _0542_[9];
- assign _1218_ = _1152_ ? 1'h0 : _0542_[10];
- assign _1219_ = _1153_ ? 1'h0 : _0542_[11];
- assign _1220_ = _1154_ ? 1'h0 : _0542_[12];
- assign _1221_ = _1155_ ? 1'h0 : _0542_[13];
- assign _1222_ = _1156_ ? 1'h0 : _0542_[14];
- assign _1223_ = _1157_ ? 1'h0 : _0542_[15];
- assign _1224_ = _1158_ ? 1'h0 : _0542_[16];
- assign _1225_ = _1159_ ? 1'h0 : _0542_[17];
- assign _1226_ = _1160_ ? 1'h0 : _0542_[18];
- assign _1227_ = _1161_ ? 1'h0 : _0542_[19];
- assign _1228_ = _1162_ ? 1'h0 : _0542_[20];
- assign _1229_ = _1163_ ? 1'h0 : _0542_[21];
- assign _1230_ = _1164_ ? 1'h0 : _0542_[22];
- assign _1231_ = _1165_ ? 1'h0 : _0542_[23];
- assign _1232_ = _1166_ ? 1'h0 : _0542_[24];
- assign _1234_ = _1167_ ? 1'h0 : _0542_[25];
- assign _1235_ = _1168_ ? 1'h0 : _0542_[26];
- assign _1236_ = _1169_ ? 1'h0 : _0542_[27];
- assign _1237_ = _1170_ ? 1'h0 : _0542_[28];
- assign _1238_ = _1171_ ? 1'h0 : _0542_[29];
- assign _1239_ = _1172_ ? 1'h0 : _0542_[30];
- assign _1240_ = _1173_ ? 1'h0 : _0542_[31];
- assign _1241_ = _1174_ ? 1'h0 : _0542_[32];
- assign _1242_ = _1175_ ? 1'h0 : _0542_[33];
- assign _1243_ = _1176_ ? 1'h0 : _0542_[34];
- assign _1245_ = _1177_ ? 1'h0 : _0542_[35];
- assign _1246_ = _1178_ ? 1'h0 : _0542_[36];
- assign _1247_ = _1179_ ? 1'h0 : _0542_[37];
- assign _1248_ = _1180_ ? 1'h0 : _0542_[38];
- assign _1191_ = { 31'h00000000, _0606_[108] } == 32'd0;
- assign _1249_ = _1181_ ? 1'h0 : _0542_[39];
- assign _1250_ = _1182_ ? 1'h0 : _0542_[40];
- assign _1251_ = _1183_ ? 1'h0 : _0542_[41];
- assign _1252_ = _1184_ ? 1'h0 : _0542_[42];
- assign _1253_ = _1185_ ? 1'h0 : _0542_[43];
- assign _1202_ = wishbone_in[64] & _1191_;
- assign _1254_ = _1186_ ? 1'h0 : _0542_[44];
- assign _0000_ = _1187_ ? 1'h0 : _0542_[45];
- assign _0001_ = _1188_ ? 1'h0 : _0542_[46];
- assign _0002_ = _1189_ ? 1'h0 : _0542_[47];
- assign _0003_ = _1190_ ? 1'h0 : _0542_[48];
- assign _0004_ = _1192_ ? 1'h0 : _0542_[49];
- assign _0005_ = _1193_ ? 1'h0 : _0542_[50];
- assign _0006_ = _1194_ ? 1'h0 : _0542_[51];
- assign _0007_ = _1195_ ? 1'h0 : _0542_[52];
- assign _0008_ = _1196_ ? 1'h0 : _0542_[53];
- assign _0009_ = _1197_ ? 1'h0 : _0542_[54];
- assign _0010_ = _1198_ ? 1'h0 : _0542_[55];
- assign _0011_ = _1199_ ? 1'h0 : _0542_[56];
- assign _0012_ = _1200_ ? 1'h0 : _0542_[57];
- assign _0013_ = _1201_ ? 1'h0 : _0542_[58];
- assign \rams%0.do_write = _1202_ ? 1'h1 : 1'h0;
- assign _0014_ = _1203_ ? 1'h0 : _0542_[59];
- assign _0015_ = _1204_ ? 1'h0 : _0542_[60];
- assign _0016_ = _1205_ ? 1'h0 : _0542_[61];
- assign _0017_ = _1206_ ? 1'h0 : _0542_[62];
- assign _0018_ = _1207_ ? 1'h0 : _0542_[63];
- assign _0030_ = _0546_[4] ? _0029_ : _0028_;
- assign _0032_ = ~ _0547_[4];
- assign _0033_ = ~ _0547_[3];
- assign _0034_ = _0032_ & _0033_;
- assign _0035_ = _0032_ & _0547_[3];
- assign _0036_ = _0547_[4] & _0033_;
- assign _0037_ = _0547_[4] & _0547_[3];
- assign _0038_ = ~ _0547_[2];
- assign _0039_ = _0034_ & _0038_;
- assign _0040_ = _0034_ & _0547_[2];
- assign _0041_ = _0035_ & _0038_;
- assign _0042_ = _0035_ & _0547_[2];
- assign _0043_ = _0036_ & _0038_;
- assign _0044_ = _0036_ & _0547_[2];
- assign _0045_ = _0037_ & _0038_;
- assign _0046_ = _0037_ & _0547_[2];
- assign _0047_ = ~ _0547_[1];
- assign _0048_ = _0039_ & _0047_;
- assign _0049_ = _0039_ & _0547_[1];
- assign _0050_ = _0040_ & _0047_;
- assign _0051_ = _0040_ & _0547_[1];
- assign _0052_ = _0041_ & _0047_;
- assign _0053_ = _0041_ & _0547_[1];
- assign _0054_ = _0042_ & _0047_;
- assign _0055_ = _0042_ & _0547_[1];
- assign _0056_ = _0043_ & _0047_;
- assign _0057_ = _0043_ & _0547_[1];
- assign _0058_ = _0044_ & _0047_;
- assign _0059_ = _0044_ & _0547_[1];
- assign _0060_ = _0045_ & _0047_;
- assign _0061_ = _0045_ & _0547_[1];
- assign _0063_ = _0046_ & _0047_;
- assign _0064_ = _0046_ & _0547_[1];
- assign _0065_ = ~ _0547_[0];
- assign _0066_ = _0048_ & _0065_;
- assign _0067_ = _0048_ & _0547_[0];
- assign _0068_ = _0049_ & _0065_;
- assign _0069_ = _0049_ & _0547_[0];
- assign _0070_ = _0050_ & _0065_;
- assign _0071_ = _0050_ & _0547_[0];
- assign _0072_ = _0051_ & _0065_;
- assign _0074_ = _0051_ & _0547_[0];
- assign _0075_ = _0052_ & _0065_;
- assign _0076_ = _0052_ & _0547_[0];
- assign _0077_ = _0053_ & _0065_;
- assign _0078_ = _0053_ & _0547_[0];
- assign _0079_ = _0054_ & _0065_;
- assign _0080_ = _0054_ & _0547_[0];
- assign _0081_ = _0055_ & _0065_;
- assign _0082_ = _0055_ & _0547_[0];
- assign _0083_ = _0056_ & _0065_;
- assign _0084_ = _0056_ & _0547_[0];
- assign _0085_ = _0057_ & _0065_;
- assign _0086_ = _0057_ & _0547_[0];
- assign _0087_ = _0058_ & _0065_;
- assign _0088_ = _0058_ & _0547_[0];
- assign _0089_ = _0059_ & _0065_;
- assign _0090_ = _0059_ & _0547_[0];
- assign _0091_ = _0060_ & _0065_;
- assign _0092_ = _0060_ & _0547_[0];
- assign _0093_ = _0061_ & _0065_;
- assign _0094_ = _0061_ & _0547_[0];
- assign _0095_ = _0063_ & _0065_;
- assign _0096_ = _0063_ & _0547_[0];
- assign _0097_ = _0064_ & _0065_;
- assign _0098_ = _0064_ & _0547_[0];
- assign _0099_ = _0066_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[89:0];
- assign _0100_ = _0067_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[179:90];
- assign _0101_ = _0068_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[269:180];
- assign _0102_ = _0069_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[359:270];
- assign _0103_ = _0070_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[449:360];
- assign _0105_ = _0071_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[539:450];
- assign _0106_ = _0072_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[629:540];
- assign _1233_ = { 31'h00000000, _0606_[108] } == 32'd1;
- assign _0107_ = _0074_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[719:630];
- assign _0108_ = _0075_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[809:720];
- assign _0109_ = _0076_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[899:810];
- assign _0110_ = _0077_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[989:900];
- assign _0111_ = _0078_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1079:990];
- assign _1244_ = wishbone_in[64] & _1233_;
- assign _0112_ = _0079_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1169:1080];
- assign _0113_ = _0080_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1259:1170];
- assign _0114_ = _0081_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1349:1260];
- assign _0116_ = _0082_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1439:1350];
- assign _0117_ = _0083_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1529:1440];
- assign _0118_ = _0084_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1619:1530];
- assign _0119_ = _0085_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1709:1620];
- assign _0120_ = _0086_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1799:1710];
- assign _0121_ = _0087_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1889:1800];
- assign _0122_ = _0088_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1979:1890];
- assign _0123_ = _0089_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2069:1980];
- assign _0124_ = _0090_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2159:2070];
- assign _0125_ = _0091_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2249:2160];
- assign _0126_ = _0092_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2339:2250];
- assign _0127_ = _0093_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2429:2340];
- assign \rams%1.do_write = _1244_ ? 1'h1 : 1'h0;
- assign _0128_ = _0094_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2519:2430];
- assign _0129_ = _0095_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2609:2520];
- assign _0130_ = _0096_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2699:2610];
- assign _0131_ = _0097_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2789:2700];
- assign _0132_ = _0098_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2879:2790];
- assign _0143_ = _0550_[4] ? _0142_ : _0141_;
- assign _0144_ = ~ _0551_[4];
- assign _0145_ = ~ _0551_[3];
- assign _0147_ = _0144_ & _0145_;
- assign _0148_ = _0144_ & _0551_[3];
- assign _0149_ = _0551_[4] & _0145_;
- assign _0150_ = _0551_[4] & _0551_[3];
- assign _0151_ = ~ _0551_[2];
- assign _0152_ = _0147_ & _0151_;
- assign _0153_ = _0147_ & _0551_[2];
- assign _0154_ = _0148_ & _0151_;
- assign _0155_ = _0148_ & _0551_[2];
- assign _0156_ = _0149_ & _0151_;
- assign _0158_ = _0149_ & _0551_[2];
- assign _0159_ = _0150_ & _0151_;
- assign _0160_ = _0150_ & _0551_[2];
- assign _0161_ = ~ _0551_[1];
- assign _0162_ = _0152_ & _0161_;
- assign _0163_ = _0152_ & _0551_[1];
- assign _0164_ = _0153_ & _0161_;
- assign _0165_ = _0153_ & _0551_[1];
- assign _0166_ = _0154_ & _0161_;
- assign _0167_ = _0154_ & _0551_[1];
- assign _0168_ = _0155_ & _0161_;
- assign _0169_ = _0155_ & _0551_[1];
- assign _0170_ = _0156_ & _0161_;
- assign _0171_ = _0156_ & _0551_[1];
- assign _0172_ = _0158_ & _0161_;
- assign _0173_ = _0158_ & _0551_[1];
- assign _0174_ = _0159_ & _0161_;
- assign _0175_ = _0159_ & _0551_[1];
- assign _0176_ = _0160_ & _0161_;
- assign _0177_ = _0160_ & _0551_[1];
- assign _0178_ = ~ _0551_[0];
- assign _0179_ = _0162_ & _0178_;
- assign _0180_ = _0162_ & _0551_[0];
- assign _0181_ = _0163_ & _0178_;
- assign _0182_ = _0163_ & _0551_[0];
- assign _0183_ = _0164_ & _0178_;
- assign _0184_ = _0164_ & _0551_[0];
- assign _0185_ = _0165_ & _0178_;
- assign _0186_ = _0165_ & _0551_[0];
- assign _0187_ = _0166_ & _0178_;
- assign _0189_ = _0166_ & _0551_[0];
- assign _0190_ = _0167_ & _0178_;
- assign _0191_ = _0167_ & _0551_[0];
- assign _0192_ = _0168_ & _0178_;
- assign _0193_ = _0168_ & _0551_[0];
- assign _0194_ = _0169_ & _0178_;
- assign _0195_ = _0169_ & _0551_[0];
- assign _0196_ = _0170_ & _0178_;
- assign _0197_ = _0170_ & _0551_[0];
- assign _0020_ = { 27'h0000000, i_in[14:10] } == 32'd0;
- assign _0198_ = _0171_ & _0178_;
- assign _0200_ = _0171_ & _0551_[0];
- assign _0201_ = _0172_ & _0178_;
- assign _0202_ = _0172_ & _0551_[0];
- assign _0203_ = _0173_ & _0178_;
- assign _0204_ = _0173_ & _0551_[0];
- assign _0205_ = _0174_ & _0178_;
- assign _0206_ = _0174_ & _0551_[0];
- assign _0207_ = _0175_ & _0178_;
- assign _0208_ = _0175_ & _0551_[0];
- assign _0031_ = req_is_hit & _0020_;
- assign _0209_ = _0176_ & _0178_;
- assign _0210_ = _0176_ & _0551_[0];
- assign _0211_ = _0177_ & _0178_;
- assign _0212_ = _0177_ & _0551_[0];
- assign _0213_ = _0179_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[89:0];
- assign _0214_ = _0180_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[179:90];
- assign _0215_ = _0181_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[269:180];
- assign _0216_ = _0182_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[359:270];
- assign _0217_ = _0183_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[449:360];
- assign _0218_ = _0184_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[539:450];
- assign _0219_ = _0185_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[629:540];
- assign _0220_ = _0186_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[719:630];
- assign \maybe_plrus.plrus%0.plru_acc_en = _0031_ ? req_is_hit : 1'h0;
- assign _0221_ = _0187_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[809:720];
- assign _0222_ = _0189_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[899:810];
- assign _0223_ = _0190_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[989:900];
- assign _0224_ = _0191_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1079:990];
- assign _0225_ = _0192_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1169:1080];
- assign _0226_ = _0193_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1259:1170];
- assign _0227_ = _0194_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1349:1260];
- assign _0228_ = _0195_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1439:1350];
- assign _0229_ = _0196_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1529:1440];
- assign _0231_ = _0197_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1619:1530];
- assign _0232_ = _0198_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1709:1620];
- assign _0233_ = _0200_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1799:1710];
- assign _0234_ = _0201_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1889:1800];
- assign _0235_ = _0202_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1979:1890];
- assign _0236_ = _0203_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2069:1980];
- assign _0237_ = _0204_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2159:2070];
- assign _0238_ = _0205_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2249:2160];
- assign _0239_ = _0206_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2339:2250];
- assign _0240_ = _0207_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2429:2340];
- assign _0242_ = _0208_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2519:2430];
- assign _0243_ = _0209_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2609:2520];
- assign _0244_ = _0210_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2699:2610];
- assign _0245_ = _0211_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2789:2700];
- assign _0246_ = _0212_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2879:2790];
- assign _0247_ = ~ _0572_[4];
- assign _0248_ = ~ _0572_[3];
- assign _0249_ = _0247_ & _0248_;
- assign _0250_ = _0247_ & _0572_[3];
- assign _0251_ = _0572_[4] & _0248_;
- assign _0252_ = _0572_[4] & _0572_[3];
- assign _0253_ = ~ _0572_[2];
- assign _0254_ = _0249_ & _0253_;
- assign _0255_ = _0249_ & _0572_[2];
- assign _0256_ = _0250_ & _0253_;
- assign _0257_ = _0250_ & _0572_[2];
- assign _0258_ = _0251_ & _0253_;
- assign _0259_ = _0251_ & _0572_[2];
- assign _0260_ = _0252_ & _0253_;
- assign _0261_ = _0252_ & _0572_[2];
- assign _0262_ = ~ _0572_[1];
- assign _0263_ = _0254_ & _0262_;
- assign _0264_ = _0254_ & _0572_[1];
- assign _0265_ = _0255_ & _0262_;
- assign _0266_ = _0255_ & _0572_[1];
- assign _0267_ = _0256_ & _0262_;
- assign _0268_ = _0256_ & _0572_[1];
- assign _0269_ = _0257_ & _0262_;
- assign _0270_ = _0257_ & _0572_[1];
- assign _0271_ = _0258_ & _0262_;
- assign _0273_ = _0258_ & _0572_[1];
- assign _0062_ = { 27'h0000000, i_in[14:10] } == 32'd1;
- assign _0274_ = _0259_ & _0262_;
- assign _0275_ = _0259_ & _0572_[1];
- assign _0276_ = _0260_ & _0262_;
- assign _0277_ = _0260_ & _0572_[1];
- assign _0278_ = _0261_ & _0262_;
- assign _0279_ = _0261_ & _0572_[1];
- assign _0280_ = ~ _0572_[0];
- assign _0281_ = _0263_ & _0280_;
- assign _0282_ = _0263_ & _0572_[0];
- assign _0073_ = req_is_hit & _0062_;
- assign _0284_ = _0264_ & _0280_;
- assign _0285_ = _0264_ & _0572_[0];
- assign _0286_ = _0265_ & _0280_;
- assign _0287_ = _0265_ & _0572_[0];
- assign _0288_ = _0266_ & _0280_;
- assign _0289_ = _0266_ & _0572_[0];
- assign _0290_ = _0267_ & _0280_;
- assign _0291_ = _0267_ & _0572_[0];
- assign _0292_ = _0268_ & _0280_;
- assign _0293_ = _0268_ & _0572_[0];
- assign _0294_ = _0269_ & _0280_;
- assign _0295_ = _0269_ & _0572_[0];
- assign _0296_ = _0270_ & _0280_;
- assign _0297_ = _0270_ & _0572_[0];
- assign _0298_ = _0271_ & _0280_;
- assign _0299_ = _0271_ & _0572_[0];
- assign _0300_ = _0273_ & _0280_;
- assign _0301_ = _0273_ & _0572_[0];
- assign _0302_ = _0274_ & _0280_;
- assign _0303_ = _0274_ & _0572_[0];
- assign \maybe_plrus.plrus%1.plru_acc_en = _0073_ ? req_is_hit : 1'h0;
- assign _0304_ = _0275_ & _0280_;
- assign _0305_ = _0275_ & _0572_[0];
- assign _0306_ = _0276_ & _0280_;
- assign _0307_ = _0276_ & _0572_[0];
- assign _0308_ = _0277_ & _0280_;
- assign _0309_ = _0277_ & _0572_[0];
- assign _0310_ = _0278_ & _0280_;
- assign _0311_ = _0278_ & _0572_[0];
- assign _0312_ = _0279_ & _0280_;
- assign _0313_ = _0279_ & _0572_[0];
- assign _0315_ = ~ _0606_[108];
- assign _0316_ = _0281_ & _0315_;
- assign _0317_ = _0281_ & _0606_[108];
- assign _0318_ = _0282_ & _0315_;
- assign _0319_ = _0282_ & _0606_[108];
- assign _0320_ = _0284_ & _0315_;
- assign _0321_ = _0284_ & _0606_[108];
- assign _0322_ = _0285_ & _0315_;
- assign _0323_ = _0285_ & _0606_[108];
- assign _0324_ = _0286_ & _0315_;
- assign _0326_ = _0286_ & _0606_[108];
- assign _0327_ = _0287_ & _0315_;
- assign _0328_ = _0287_ & _0606_[108];
- assign _0329_ = _0288_ & _0315_;
- assign _0330_ = _0288_ & _0606_[108];
- assign _0331_ = _0289_ & _0315_;
- assign _0332_ = _0289_ & _0606_[108];
- assign _0333_ = _0290_ & _0315_;
- assign _0334_ = _0290_ & _0606_[108];
- assign _0335_ = _0291_ & _0315_;
- assign _0336_ = _0291_ & _0606_[108];
- assign _0337_ = _0292_ & _0315_;
- assign _0338_ = _0292_ & _0606_[108];
- assign _0339_ = _0293_ & _0315_;
- assign _0340_ = _0293_ & _0606_[108];
- assign _0341_ = _0294_ & _0315_;
- assign _0342_ = _0294_ & _0606_[108];
- assign _0343_ = _0295_ & _0315_;
- assign _0344_ = _0295_ & _0606_[108];
- assign _0345_ = _0296_ & _0315_;
- assign _0346_ = _0296_ & _0606_[108];
- assign _0347_ = _0297_ & _0315_;
- assign _0348_ = _0297_ & _0606_[108];
- assign _0349_ = _0298_ & _0315_;
- assign _0350_ = _0298_ & _0606_[108];
- assign _0351_ = _0299_ & _0315_;
- assign _0352_ = _0299_ & _0606_[108];
- assign _0353_ = _0300_ & _0315_;
- assign _0354_ = _0300_ & _0606_[108];
- assign _0355_ = _0301_ & _0315_;
- assign _0357_ = _0301_ & _0606_[108];
- assign _0358_ = _0302_ & _0315_;
- assign _0359_ = _0302_ & _0606_[108];
- assign _0360_ = _0303_ & _0315_;
- assign _0361_ = _0303_ & _0606_[108];
- assign _0362_ = _0304_ & _0315_;
- assign _0363_ = _0304_ & _0606_[108];
- assign _0364_ = _0305_ & _0315_;
- assign _0365_ = _0305_ & _0606_[108];
- assign _0366_ = _0306_ & _0315_;
- assign _0368_ = _0306_ & _0606_[108];
- assign _0369_ = _0307_ & _0315_;
- assign _0370_ = _0307_ & _0606_[108];
- assign _0371_ = _0308_ & _0315_;
- assign _0372_ = _0308_ & _0606_[108];
- assign _0373_ = _0309_ & _0315_;
- assign _0374_ = _0309_ & _0606_[108];
- assign _0375_ = _0310_ & _0315_;
- assign _0376_ = _0310_ & _0606_[108];
- assign _0377_ = _0311_ & _0315_;
- assign _0378_ = _0311_ & _0606_[108];
- assign _0379_ = _0312_ & _0315_;
- assign _0380_ = _0312_ & _0606_[108];
- assign _0381_ = _0313_ & _0315_;
- assign _0382_ = _0313_ & _0606_[108];
- assign _0383_ = _0316_ ? _0574_ : _0542_[0];
- assign _0384_ = _0317_ ? _0574_ : _0542_[1];
- assign _0104_ = { 27'h0000000, i_in[14:10] } == 32'd2;
- assign _0385_ = _0318_ ? _0574_ : _0542_[2];
- assign _0386_ = _0319_ ? _0574_ : _0542_[3];
- assign _0387_ = _0320_ ? _0574_ : _0542_[4];
- assign _0388_ = _0321_ ? _0574_ : _0542_[5];
- assign _0389_ = _0322_ ? _0574_ : _0542_[6];
- assign _0115_ = req_is_hit & _0104_;
- assign _0390_ = _0323_ ? _0574_ : _0542_[7];
- assign _0391_ = _0324_ ? _0574_ : _0542_[8];
- assign _0392_ = _0326_ ? _0574_ : _0542_[9];
- assign _0393_ = _0327_ ? _0574_ : _0542_[10];
- assign _0394_ = _0328_ ? _0574_ : _0542_[11];
- assign _0395_ = _0329_ ? _0574_ : _0542_[12];
- assign _0396_ = _0330_ ? _0574_ : _0542_[13];
- assign _0397_ = _0331_ ? _0574_ : _0542_[14];
- assign _0399_ = _0332_ ? _0574_ : _0542_[15];
- assign _0400_ = _0333_ ? _0574_ : _0542_[16];
- assign \maybe_plrus.plrus%2.plru_acc_en = _0115_ ? req_is_hit : 1'h0;
- assign _0401_ = _0334_ ? _0574_ : _0542_[17];
- assign _0402_ = _0335_ ? _0574_ : _0542_[18];
- assign _0403_ = _0336_ ? _0574_ : _0542_[19];
- assign _0404_ = _0337_ ? _0574_ : _0542_[20];
- assign _0405_ = _0338_ ? _0574_ : _0542_[21];
- assign _0406_ = _0339_ ? _0574_ : _0542_[22];
- assign _0407_ = _0340_ ? _0574_ : _0542_[23];
- assign _0408_ = _0341_ ? _0574_ : _0542_[24];
- assign _0410_ = _0342_ ? _0574_ : _0542_[25];
- assign _0411_ = _0343_ ? _0574_ : _0542_[26];
- assign _0412_ = _0344_ ? _0574_ : _0542_[27];
- assign _0413_ = _0345_ ? _0574_ : _0542_[28];
- assign _0414_ = _0346_ ? _0574_ : _0542_[29];
- assign _0415_ = _0347_ ? _0574_ : _0542_[30];
- assign _0416_ = _0348_ ? _0574_ : _0542_[31];
- assign _0417_ = _0349_ ? _0574_ : _0542_[32];
- assign _0418_ = _0350_ ? _0574_ : _0542_[33];
- assign _0419_ = _0351_ ? _0574_ : _0542_[34];
- assign _0420_ = _0352_ ? _0574_ : _0542_[35];
- assign _0421_ = _0353_ ? _0574_ : _0542_[36];
- assign _0422_ = _0354_ ? _0574_ : _0542_[37];
- assign _0423_ = _0355_ ? _0574_ : _0542_[38];
- assign _0424_ = _0357_ ? _0574_ : _0542_[39];
- assign _0425_ = _0358_ ? _0574_ : _0542_[40];
- assign _0426_ = _0359_ ? _0574_ : _0542_[41];
- assign _0427_ = _0360_ ? _0574_ : _0542_[42];
- assign _0428_ = _0361_ ? _0574_ : _0542_[43];
- assign _0429_ = _0362_ ? _0574_ : _0542_[44];
- assign _0430_ = _0363_ ? _0574_ : _0542_[45];
- assign _0431_ = _0364_ ? _0574_ : _0542_[46];
- assign _0432_ = _0365_ ? _0574_ : _0542_[47];
- assign _0433_ = _0366_ ? _0574_ : _0542_[48];
- assign _0434_ = _0368_ ? _0574_ : _0542_[49];
- assign _0435_ = _0369_ ? _0574_ : _0542_[50];
- assign _0436_ = _0370_ ? _0574_ : _0542_[51];
- assign _0437_ = _0371_ ? _0574_ : _0542_[52];
- assign _0438_ = _0372_ ? _0574_ : _0542_[53];
- assign _0439_ = _0373_ ? _0574_ : _0542_[54];
- assign _0441_ = _0374_ ? _0574_ : _0542_[55];
- assign _0442_ = _0375_ ? _0574_ : _0542_[56];
- assign _0146_ = { 27'h0000000, i_in[14:10] } == 32'd3;
- assign _0443_ = _0376_ ? _0574_ : _0542_[57];
- assign _0444_ = _0377_ ? _0574_ : _0542_[58];
- assign _0445_ = _0378_ ? _0574_ : _0542_[59];
- assign _0446_ = _0379_ ? _0574_ : _0542_[60];
- assign _0447_ = _0380_ ? _0574_ : _0542_[61];
- assign _0157_ = req_is_hit & _0146_;
- assign _0448_ = _0381_ ? _0574_ : _0542_[62];
- assign _0449_ = _0382_ ? _0574_ : _0542_[63];
- assign \maybe_plrus.plrus%3.plru_acc_en = _0157_ ? req_is_hit : 1'h0;
- assign _0188_ = { 27'h0000000, i_in[14:10] } == 32'd4;
- assign _0199_ = req_is_hit & _0188_;
- assign \maybe_plrus.plrus%4.plru_acc_en = _0199_ ? req_is_hit : 1'h0;
- assign _0230_ = { 27'h0000000, i_in[14:10] } == 32'd5;
- assign _0241_ = req_is_hit & _0230_;
- assign \maybe_plrus.plrus%5.plru_acc_en = _0241_ ? req_is_hit : 1'h0;
- assign _0272_ = { 27'h0000000, i_in[14:10] } == 32'd6;
- assign _0283_ = req_is_hit & _0272_;
- assign \maybe_plrus.plrus%6.plru_acc_en = _0283_ ? req_is_hit : 1'h0;
- assign _0314_ = { 27'h0000000, i_in[14:10] } == 32'd7;
- assign _0325_ = req_is_hit & _0314_;
- assign \maybe_plrus.plrus%7.plru_acc_en = _0325_ ? req_is_hit : 1'h0;
- assign _0356_ = { 27'h0000000, i_in[14:10] } == 32'd8;
- assign _0367_ = req_is_hit & _0356_;
- assign \maybe_plrus.plrus%8.plru_acc_en = _0367_ ? req_is_hit : 1'h0;
- assign _0398_ = { 27'h0000000, i_in[14:10] } == 32'd9;
- assign _0409_ = req_is_hit & _0398_;
- assign \maybe_plrus.plrus%9.plru_acc_en = _0409_ ? req_is_hit : 1'h0;
- assign _0440_ = { 27'h0000000, i_in[14:10] } == 32'd10;
- assign _0450_ = req_is_hit & _0440_;
- assign \maybe_plrus.plrus%10.plru_acc_en = _0450_ ? req_is_hit : 1'h0;
- assign _0451_ = { 27'h0000000, i_in[14:10] } == 32'd11;
- assign _0452_ = req_is_hit & _0451_;
- assign \maybe_plrus.plrus%11.plru_acc_en = _0452_ ? req_is_hit : 1'h0;
- assign _0453_ = { 27'h0000000, i_in[14:10] } == 32'd12;
- assign _0454_ = req_is_hit & _0453_;
- assign \maybe_plrus.plrus%12.plru_acc_en = _0454_ ? req_is_hit : 1'h0;
- assign _0455_ = { 27'h0000000, i_in[14:10] } == 32'd13;
- assign _0456_ = req_is_hit & _0455_;
- assign \maybe_plrus.plrus%13.plru_acc_en = _0456_ ? req_is_hit : 1'h0;
- assign _0457_ = { 27'h0000000, i_in[14:10] } == 32'd14;
- assign _0458_ = req_is_hit & _0457_;
- assign \maybe_plrus.plrus%14.plru_acc_en = _0458_ ? req_is_hit : 1'h0;
- assign _0459_ = { 27'h0000000, i_in[14:10] } == 32'd15;
- assign _0460_ = req_is_hit & _0459_;
- assign \maybe_plrus.plrus%15.plru_acc_en = _0460_ ? req_is_hit : 1'h0;
- assign _0461_ = { 27'h0000000, i_in[14:10] } == 32'd16;
- assign _0462_ = req_is_hit & _0461_;
- assign \maybe_plrus.plrus%16.plru_acc_en = _0462_ ? req_is_hit : 1'h0;
- assign _0463_ = { 27'h0000000, i_in[14:10] } == 32'd17;
- assign _0464_ = req_is_hit & _0463_;
- assign \maybe_plrus.plrus%17.plru_acc_en = _0464_ ? req_is_hit : 1'h0;
- assign _0465_ = { 27'h0000000, i_in[14:10] } == 32'd18;
- assign _0466_ = req_is_hit & _0465_;
- assign \maybe_plrus.plrus%18.plru_acc_en = _0466_ ? req_is_hit : 1'h0;
- assign _0467_ = { 27'h0000000, i_in[14:10] } == 32'd19;
- assign _0468_ = req_is_hit & _0467_;
- assign \maybe_plrus.plrus%19.plru_acc_en = _0468_ ? req_is_hit : 1'h0;
- assign _0469_ = { 27'h0000000, i_in[14:10] } == 32'd20;
- assign _0470_ = req_is_hit & _0469_;
- assign \maybe_plrus.plrus%20.plru_acc_en = _0470_ ? req_is_hit : 1'h0;
- assign _0471_ = { 27'h0000000, i_in[14:10] } == 32'd21;
- assign _0472_ = req_is_hit & _0471_;
- assign \maybe_plrus.plrus%21.plru_acc_en = _0472_ ? req_is_hit : 1'h0;
- assign _0473_ = { 27'h0000000, i_in[14:10] } == 32'd22;
- assign _0474_ = req_is_hit & _0473_;
- assign \maybe_plrus.plrus%22.plru_acc_en = _0474_ ? req_is_hit : 1'h0;
- assign _0475_ = { 27'h0000000, i_in[14:10] } == 32'd23;
- assign _0476_ = req_is_hit & _0475_;
- assign \maybe_plrus.plrus%23.plru_acc_en = _0476_ ? req_is_hit : 1'h0;
- assign _0477_ = { 27'h0000000, i_in[14:10] } == 32'd24;
- assign _0478_ = req_is_hit & _0477_;
- assign \maybe_plrus.plrus%24.plru_acc_en = _0478_ ? req_is_hit : 1'h0;
- assign _0479_ = { 27'h0000000, i_in[14:10] } == 32'd25;
- assign _0480_ = req_is_hit & _0479_;
- assign \maybe_plrus.plrus%25.plru_acc_en = _0480_ ? req_is_hit : 1'h0;
- assign _0481_ = { 27'h0000000, i_in[14:10] } == 32'd26;
- assign _0482_ = req_is_hit & _0481_;
- assign \maybe_plrus.plrus%26.plru_acc_en = _0482_ ? req_is_hit : 1'h0;
- assign _0483_ = { 27'h0000000, i_in[14:10] } == 32'd27;
- assign _0484_ = req_is_hit & _0483_;
- assign \maybe_plrus.plrus%27.plru_acc_en = _0484_ ? req_is_hit : 1'h0;
- assign _0485_ = { 27'h0000000, i_in[14:10] } == 32'd28;
- assign _0486_ = req_is_hit & _0485_;
- assign \maybe_plrus.plrus%28.plru_acc_en = _0486_ ? req_is_hit : 1'h0;
- assign _0487_ = { 27'h0000000, i_in[14:10] } == 32'd29;
- assign _0488_ = req_is_hit & _0487_;
- assign \maybe_plrus.plrus%29.plru_acc_en = _0488_ ? req_is_hit : 1'h0;
- assign _0489_ = { 27'h0000000, i_in[14:10] } == 32'd30;
- assign _0490_ = req_is_hit & _0489_;
- assign \maybe_plrus.plrus%30.plru_acc_en = _0490_ ? req_is_hit : 1'h0;
- assign _0491_ = { 27'h0000000, i_in[14:10] } == 32'd31;
- assign _0492_ = req_is_hit & _0491_;
- assign \maybe_plrus.plrus%31.plru_acc_en = _0492_ ? req_is_hit : 1'h0;
- assign _0493_ = i_in[21:16] ^ i_in[27:22];
- assign tlb_req_index = _0493_ ^ i_in[33:28];
- assign _0494_ = _0610_ == i_in[67:22];
- assign _0495_ = 6'h3f - tlb_req_index;
- assign _0496_ = _0494_ ? _0631_ : 1'h0;
- assign eaa_priv = i_in[1] ? _0608_[3] : 1'h1;
- assign real_addr = i_in[1] ? { _0608_[55:12], i_in[15:4] } : i_in[59:4];
- assign ra_valid = i_in[1] ? _0496_ : 1'h1;
- assign _0497_ = ~ i_in[2];
- assign priv_fault = eaa_priv & _0497_;
- assign _0498_ = ~ priv_fault;
- assign access_ok = ra_valid & _0498_;
- assign _0499_ = m_in[20:15] ^ m_in[26:21];
- assign _0500_ = _0499_ ^ m_in[32:27];
- assign _0501_ = m_in[1] & m_in[2];
- assign _0502_ = rst | _0501_;
- assign _0503_ = 6'h3f - _0500_;
- assign _0504_ = 6'h3f - _0500_;
- assign _0505_ = m_in[0] ? { _1019_, _1018_, _1017_, _1016_, _1015_, _1014_, _1013_, _1012_, _1011_, _1010_, _1009_, _1008_, _1007_, _1006_, _1005_, _1004_, _1003_, _1002_, _1001_, _1000_, _0999_, _0998_, _0997_, _0996_, _0995_, _0994_, _0993_, _0992_, _0991_, _0990_, _0989_, _0988_, _0987_, _0986_, _0985_, _0984_, _0983_, _0982_, _0981_, _0980_, _0979_, _0978_, _0977_, _0976_, _0975_, _0974_, _0973_, _0972_, _0971_, _0970_, _0969_, _0968_, _0967_, _0966_, _0965_, _0964_, _0963_, _0962_, _0961_, _0960_, _0959_, _0958_, _0957_, _0956_ } : itlb_valids;
- assign _0506_ = m_in[1] ? { _0825_, _0824_, _0823_, _0822_, _0821_, _0820_, _0819_, _0818_, _0817_, _0816_, _0815_, _0814_, _0813_, _0812_, _0811_, _0810_, _0809_, _0808_, _0807_, _0806_, _0805_, _0804_, _0803_, _0802_, _0801_, _0800_, _0799_, _0798_, _0797_, _0796_, _0795_, _0794_, _0793_, _0792_, _0791_, _0790_, _0789_, _0788_, _0787_, _0786_, _0785_, _0784_, _0783_, _0782_, _0781_, _0780_, _0779_, _0778_, _0777_, _0776_, _0775_, _0774_, _0773_, _0772_, _0771_, _0770_, _0769_, _0768_, _0767_, _0766_, _0765_, _0764_, _0763_, _0762_ } : _0505_;
- assign _0507_ = _0502_ ? 64'h0000000000000000 : _0506_;
- always @(posedge clk)
- itlb_valids <= _0507_;
- assign _0508_ = ~ _0502_;
- assign _0509_ = ~ m_in[1];
- assign _0510_ = _0508_ & _0509_;
- assign _0511_ = _0510_ & m_in[0];
- assign _0512_ = ~ _0502_;
- assign _0513_ = ~ m_in[1];
- assign _0514_ = _0512_ & _0513_;
- assign _0515_ = _0514_ & m_in[0];
- assign _0516_ = 5'h1f - i_in[14:10];
- assign _0517_ = i_in[0] & _1030_;
- assign _0518_ = 5'h1f - i_in[14:10];
- assign _0519_ = _1041_[44:0] == real_addr[55:11];
- assign _0520_ = _0519_ ? 1'h1 : 1'h0;
- assign _0521_ = _0517_ ? _0520_ : 1'h0;
- assign _0522_ = 5'h1f - i_in[14:10];
- assign _0523_ = i_in[0] & _1052_;
- assign _0524_ = 5'h1f - i_in[14:10];
- assign _0525_ = _1063_[89:45] == real_addr[55:11];
- assign _0526_ = _0528_ ? 1'h1 : _0521_;
- assign _0527_ = _0525_ ? 1'h1 : 1'h0;
- assign _0528_ = _0523_ & _0525_;
- assign req_hit_way = _0523_ ? _0527_ : 1'h0;
- assign _0529_ = i_in[0] & access_ok;
- assign _0530_ = ~ flush_in;
- assign _0531_ = _0529_ & _0530_;
- assign _0532_ = ~ rst;
- assign _0533_ = _0531_ & _0532_;
- assign _0534_ = ~ _0526_;
- assign req_is_hit = _0533_ ? _0526_ : 1'h0;
- assign req_is_miss = _0533_ ? _0534_ : 1'h0;
- assign _0535_ = 5'h1f - i_in[14:10];
- assign _0536_ = 1'h1 - _0541_[0];
- assign _0537_ = _0526_ & access_ok;
- assign _0538_ = ~ _0537_;
- assign _0539_ = req_is_hit ? req_hit_way : _0541_[0];
- assign _0540_ = req_is_hit ? i_in[3] : i_in[3];
- always @(posedge clk)
- _0541_ <= { req_is_hit, _0540_, i_in[67:4], _0539_ };
- plru_1 \maybe_plrus.plrus%0.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%0.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%0.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%1.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%1.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%1.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%10.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%10.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%10.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%11.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%11.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%11.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%12.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%12.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%12.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%13.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%13.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%13.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%14.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%14.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%14.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%15.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%15.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%15.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%16.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%16.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%16.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%17.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%17.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%17.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%18.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%18.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%18.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%19.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%19.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%19.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%2.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%2.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%2.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%20.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%20.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%20.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%21.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%21.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%21.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%22.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%22.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%22.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%23.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%23.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%23.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%24.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%24.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%24.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%25.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%25.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%25.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%26.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%26.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%26.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%27.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%27.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%27.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%28.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%28.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%28.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%29.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%29.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%29.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%3.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%3.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%3.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%30.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%30.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%30.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%31.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%31.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%31.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%4.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%4.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%4.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%5.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%5.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%5.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%6.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%6.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%6.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%7.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%7.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%7.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%8.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%8.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%8.plru_out ),
- .rst(rst)
- );
- plru_1 \maybe_plrus.plrus%9.plru (
- .acc(req_hit_way),
- .acc_en(\maybe_plrus.plrus%9.plru_acc_en ),
- .clk(clk),
- .lru(\maybe_plrus.plrus%9.plru_out ),
- .rst(rst)
- );
- cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams%0.way (
- .clk(clk),
- .rd_addr(i_in[14:7]),
- .rd_data(\rams%0.dout ),
- .rd_en(1'h1),
- .wr_addr(_0606_[121:114]),
- .wr_data(wishbone_in[63:0]),
- .wr_sel({ \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write })
- );
- cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams%1.way (
- .clk(clk),
- .rd_addr(i_in[14:7]),
- .rd_data(\rams%1.dout ),
- .rd_en(1'h1),
- .wr_addr(_0606_[121:114]),
- .wr_data(wishbone_in[63:0]),
- .wr_sel({ \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write })
- );
- assign i_out = { _1075_, _0541_[64:1], _0606_[123], _0541_[65], _0541_[66] };
- assign stall_out = _0538_;
- assign wishbone_out = _0606_[107:1];
-endmodule
-
-module loadstore1(clk, rst, l_in, d_in, m_in, dc_stall, e_out, l_out, d_out, m_out, stall_out);
- wire [63:0] _000_;
- wire [221:0] _001_;
- wire [2:0] _002_;
- wire [113:0] _003_;
- wire _004_;
- wire [2:0] _005_;
- wire [2:0] _006_;
- wire [2:0] _007_;
- wire [3:0] _008_;
- wire [2:0] _009_;
- wire [3:0] _010_;
- wire [2:0] _011_;
- wire [3:0] _012_;
- wire [2:0] _013_;
- wire [3:0] _014_;
- wire [2:0] _015_;
- wire [3:0] _016_;
- wire [2:0] _017_;
- wire [3:0] _018_;
- wire [2:0] _019_;
- wire [3:0] _020_;
- wire [2:0] _021_;
- wire [3:0] _022_;
- wire _023_;
- wire _024_;
- wire _025_;
- wire _026_;
- wire _027_;
- wire _028_;
- wire _029_;
- wire _030_;
- wire _031_;
- wire _032_;
- wire [1:0] _033_;
- wire _034_;
- wire [1:0] _035_;
- wire _036_;
- wire _037_;
- wire _038_;
- wire [7:0] _039_;
- wire _040_;
- wire _041_;
- wire _042_;
- wire [1:0] _043_;
- wire _044_;
- wire [1:0] _045_;
- wire _046_;
- wire _047_;
- wire _048_;
- wire [7:0] _049_;
- wire _050_;
- wire _051_;
- wire _052_;
- wire [1:0] _053_;
- wire _054_;
- wire [1:0] _055_;
- wire _056_;
- wire _057_;
- wire _058_;
- wire [7:0] _059_;
- wire _060_;
- wire _061_;
- wire _062_;
- wire [1:0] _063_;
- wire _064_;
- wire [1:0] _065_;
- wire _066_;
- wire _067_;
- wire _068_;
- wire [7:0] _069_;
- wire _070_;
- wire _071_;
- wire _072_;
- wire [1:0] _073_;
- wire _074_;
- wire [1:0] _075_;
- wire _076_;
- wire _077_;
- wire _078_;
- wire [7:0] _079_;
- wire _080_;
- wire _081_;
- wire _082_;
- wire [1:0] _083_;
- wire _084_;
- wire [1:0] _085_;
- wire _086_;
- wire _087_;
- wire _088_;
- wire [7:0] _089_;
- wire _090_;
- wire _091_;
- wire _092_;
- wire [1:0] _093_;
- wire _094_;
- wire [1:0] _095_;
- wire _096_;
- wire _097_;
- wire _098_;
- wire [7:0] _099_;
- wire _100_;
- wire _101_;
- wire _102_;
- wire [1:0] _103_;
- wire _104_;
- wire [1:0] _105_;
- wire _106_;
- wire _107_;
- wire _108_;
- wire [7:0] _109_;
- wire [60:0] _110_;
- wire _111_;
- wire _112_;
- wire _113_;
- wire _114_;
- wire _115_;
- wire _116_;
- wire _117_;
- wire _118_;
- wire [63:0] _119_;
- wire [63:0] _120_;
- wire _121_;
- wire _122_;
- wire _123_;
- wire _124_;
- wire _125_;
- wire [63:0] _126_;
- wire [31:0] _127_;
- wire [2:0] _128_;
- wire [95:0] _129_;
- wire _130_;
- wire _131_;
- wire _132_;
- wire _133_;
- wire _134_;
- wire _135_;
- wire _136_;
- wire _137_;
- wire _138_;
- wire _139_;
- wire [63:0] _140_;
- wire [2:0] _141_;
- wire [95:0] _142_;
- wire _143_;
- wire _144_;
- wire _145_;
- wire [63:0] _146_;
- wire _147_;
- wire _148_;
- wire [63:0] _149_;
- wire _150_;
- wire _151_;
- wire _152_;
- wire _153_;
- wire _154_;
- wire _155_;
- wire _156_;
- wire _157_;
- wire _158_;
- wire _159_;
- wire _160_;
- wire [7:0] _161_;
- wire [15:0] _162_;
- wire [2:0] _163_;
- wire [2:0] _164_;
- wire [2:0] _165_;
- wire [2:0] _166_;
- wire [2:0] _167_;
- wire [2:0] _168_;
- wire [2:0] _169_;
- wire [2:0] _170_;
- wire [2:0] _171_;
- wire [2:0] _172_;
- wire [2:0] _173_;
- wire [2:0] _174_;
- wire [2:0] _175_;
- wire [2:0] _176_;
- wire [2:0] _177_;
- wire [2:0] _178_;
- wire [2:0] _179_;
- wire [2:0] _180_;
- wire _181_;
- wire [2:0] _182_;
- wire [2:0] _183_;
- wire _184_;
- wire [130:0] _185_;
- wire [143:0] _186_;
- wire [7:0] _187_;
- wire _188_;
- wire _189_;
- wire [63:0] _190_;
- wire _191_;
- wire _192_;
- wire [63:0] _193_;
- wire _194_;
- wire _195_;
- wire _196_;
- wire _197_;
- wire _198_;
- wire [63:0] _199_;
- wire _200_;
- wire [2:0] _201_;
- wire _202_;
- wire _203_;
- wire _204_;
- wire _205_;
- wire _206_;
- wire _207_;
- wire [63:0] _208_;
- wire _209_;
- wire [2:0] _210_;
- wire _211_;
- wire _212_;
- wire _213_;
- wire _214_;
- wire [2:0] _215_;
- wire _216_;
- wire _217_;
- wire _218_;
- wire _219_;
- wire _220_;
- wire [63:0] _221_;
- wire [2:0] _222_;
- wire _223_;
- wire _224_;
- wire [63:0] _225_;
- wire _226_;
- wire _227_;
- wire _228_;
- wire _229_;
- wire _230_;
- wire _231_;
- wire _232_;
- wire [63:0] _233_;
- wire [3:0] _234_;
- wire _235_;
- wire _236_;
- wire _237_;
- wire _238_;
- wire _239_;
- wire _240_;
- wire _241_;
- wire _242_;
- wire _243_;
- wire _244_;
- wire [7:0] _245_;
- wire [63:0] _246_;
- wire _247_;
- wire _248_;
- wire _249_;
- wire _250_;
- wire _251_;
- wire _252_;
- wire _253_;
- wire _254_;
- wire _255_;
- wire _256_;
- wire _257_;
- wire _258_;
- wire [2:0] _259_;
- wire [2:0] _260_;
- wire _261_;
- wire _262_;
- wire _263_;
- wire _264_;
- wire [2:0] _265_;
- wire _266_;
- wire _267_;
- wire _268_;
- wire _269_;
- wire [1:0] _270_;
- wire _271_;
- wire _272_;
- wire _273_;
- wire [2:0] _274_;
- wire _275_;
- wire _276_;
- wire _277_;
- wire _278_;
- wire [1:0] _279_;
- wire _280_;
- wire _281_;
- wire _282_;
- wire _283_;
- wire [2:0] _284_;
- wire _285_;
- wire _286_;
- wire _287_;
- wire _288_;
- wire [130:0] _289_;
- wire [63:0] _290_;
- wire [26:0] _291_;
- wire [2:0] _292_;
- wire _293_;
- wire [112:0] _294_;
- wire [7:0] _295_;
- wire _296_;
- wire _297_;
- wire [63:0] _298_;
- wire _299_;
- wire _300_;
- wire _301_;
- wire _302_;
- wire [63:0] _303_;
- wire _304_;
- wire _305_;
- wire [1:0] _306_;
- wire _307_;
- wire _308_;
- wire _309_;
- wire _310_;
- wire _311_;
- wire _312_;
- wire [69:0] _313_;
- wire [69:0] _314_;
- wire _315_;
- wire _316_;
- wire _317_;
- wire _318_;
- wire [31:0] _319_;
- wire [95:0] _320_;
- wire [7:0] _321_;
- wire [7:0] _322_;
- wire [7:0] _323_;
- wire [7:0] _324_;
- wire [7:0] _325_;
- wire [7:0] _326_;
- wire [7:0] _327_;
- wire [7:0] _328_;
- wire [7:0] _329_;
- wire [7:0] _330_;
- wire [7:0] _331_;
- wire [7:0] _332_;
- wire [7:0] _333_;
- wire [7:0] _334_;
- wire [7:0] _335_;
- wire [7:0] _336_;
- wire [7:0] _337_;
- wire [7:0] _338_;
- wire [7:0] _339_;
- wire [7:0] _340_;
- wire [7:0] _341_;
- wire [7:0] _342_;
- wire [7:0] _343_;
- wire [7:0] _344_;
- wire _345_;
- wire _346_;
- wire _347_;
- wire _348_;
- wire _349_;
- wire _350_;
- wire _351_;
- wire _352_;
- wire _353_;
- wire _354_;
- wire _355_;
- wire _356_;
- wire _357_;
- wire _358_;
- wire _359_;
- wire [7:0] _360_;
- wire [7:0] _361_;
- wire [7:0] _362_;
- wire [7:0] _363_;
- wire [7:0] _364_;
- wire [7:0] _365_;
- wire [7:0] _366_;
- wire [7:0] _367_;
- wire _368_;
- wire _369_;
- wire _370_;
- wire _371_;
- wire _372_;
- wire _373_;
- wire _374_;
- wire _375_;
- wire _376_;
- wire _377_;
- wire _378_;
- wire _379_;
- wire _380_;
- wire _381_;
- wire _382_;
- wire [7:0] _383_;
- wire [7:0] _384_;
- wire [7:0] _385_;
- wire [7:0] _386_;
- wire [7:0] _387_;
- wire [7:0] _388_;
- wire [7:0] _389_;
- wire [7:0] _390_;
- wire _391_;
- wire _392_;
- wire _393_;
- wire _394_;
- wire _395_;
- wire _396_;
- wire _397_;
- wire _398_;
- wire _399_;
- wire _400_;
- wire _401_;
- wire _402_;
- wire _403_;
- wire _404_;
- wire _405_;
- wire [7:0] _406_;
- wire [7:0] _407_;
- wire [7:0] _408_;
- wire [7:0] _409_;
- wire [7:0] _410_;
- wire [7:0] _411_;
- wire [7:0] _412_;
- wire [7:0] _413_;
- wire _414_;
- wire _415_;
- wire _416_;
- wire _417_;
- wire _418_;
- wire _419_;
- wire _420_;
- wire _421_;
- wire _422_;
- wire _423_;
- wire _424_;
- wire _425_;
- wire _426_;
- wire _427_;
- wire _428_;
- wire [7:0] _429_;
- wire [7:0] _430_;
- wire [7:0] _431_;
- wire [7:0] _432_;
- wire [7:0] _433_;
- wire [7:0] _434_;
- wire [7:0] _435_;
- wire [7:0] _436_;
- wire _437_;
- wire _438_;
- wire _439_;
- wire _440_;
- wire _441_;
- wire _442_;
- wire _443_;
- wire _444_;
- wire _445_;
- wire _446_;
- wire _447_;
- wire _448_;
- wire _449_;
- wire _450_;
- wire _451_;
- wire [7:0] _452_;
- wire [7:0] _453_;
- wire [7:0] _454_;
- wire [7:0] _455_;
- wire [7:0] _456_;
- wire [7:0] _457_;
- wire [7:0] _458_;
- wire [7:0] _459_;
- wire _460_;
- wire _461_;
- wire _462_;
- wire _463_;
- wire _464_;
- wire _465_;
- wire _466_;
- wire _467_;
- wire _468_;
- wire _469_;
- wire _470_;
- wire _471_;
- wire _472_;
- wire _473_;
- wire _474_;
- wire [7:0] _475_;
- wire [7:0] _476_;
- wire [7:0] _477_;
- wire [7:0] _478_;
- wire [7:0] _479_;
- wire [7:0] _480_;
- wire [7:0] _481_;
- wire [7:0] _482_;
- wire _483_;
- wire _484_;
- wire _485_;
- wire _486_;
- wire _487_;
- wire _488_;
- wire _489_;
- wire _490_;
- wire _491_;
- wire _492_;
- wire _493_;
- wire _494_;
- wire _495_;
- wire _496_;
- wire _497_;
- wire [7:0] _498_;
- wire [7:0] _499_;
- wire [7:0] _500_;
- wire [7:0] _501_;
- wire [7:0] _502_;
- wire [7:0] _503_;
- wire [7:0] _504_;
- wire [7:0] _505_;
- wire _506_;
- wire _507_;
- wire _508_;
- wire _509_;
- wire _510_;
- wire _511_;
- wire _512_;
- wire _513_;
- wire _514_;
- wire _515_;
- wire _516_;
- wire _517_;
- wire _518_;
- wire _519_;
- wire _520_;
- wire [7:0] _521_;
- wire [7:0] _522_;
- wire [7:0] _523_;
- wire [7:0] _524_;
- wire [7:0] _525_;
- wire [7:0] _526_;
- wire [7:0] _527_;
- wire [7:0] _528_;
- wire [7:0] _529_;
- wire [7:0] _530_;
- wire [7:0] _531_;
- wire [7:0] _532_;
- wire [7:0] _533_;
- wire [7:0] _534_;
- wire [7:0] _535_;
- wire [7:0] _536_;
- wire [7:0] _537_;
- wire [7:0] _538_;
- wire [7:0] _539_;
- wire [7:0] _540_;
- wire [7:0] _541_;
- wire [7:0] _542_;
- wire [7:0] _543_;
- wire [7:0] _544_;
- wire [7:0] _545_;
- wire [7:0] _546_;
- wire [7:0] _547_;
- wire [7:0] _548_;
- wire [7:0] _549_;
- wire [7:0] _550_;
- wire [7:0] _551_;
- wire [7:0] _552_;
- wire [7:0] _553_;
- wire [7:0] _554_;
- wire [7:0] _555_;
- wire [7:0] _556_;
- wire [7:0] _557_;
- wire [7:0] _558_;
- wire [7:0] _559_;
- wire [7:0] _560_;
- input clk;
- input [67:0] d_in;
- output [142:0] d_out;
- input dc_stall;
- output [6:0] e_out;
- input [321:0] l_in;
- output [77:0] l_out;
- wire [63:0] lsu_sum;
- input [69:0] m_in;
- output [144:0] m_out;
- reg [338:0] r;
- input rst;
- output stall_out;
- assign _529_ = _008_[0] ? d_in[16:9] : d_in[8:1];
- assign _530_ = _008_[0] ? d_in[48:41] : d_in[40:33];
- assign _531_ = _010_[0] ? d_in[16:9] : d_in[8:1];
- assign _532_ = _010_[0] ? d_in[48:41] : d_in[40:33];
- assign _533_ = _012_[0] ? d_in[16:9] : d_in[8:1];
- assign _534_ = _012_[0] ? d_in[48:41] : d_in[40:33];
- assign _535_ = _014_[0] ? d_in[16:9] : d_in[8:1];
- assign _536_ = _014_[0] ? d_in[48:41] : d_in[40:33];
- assign _537_ = _016_[0] ? d_in[16:9] : d_in[8:1];
- assign _538_ = _016_[0] ? d_in[48:41] : d_in[40:33];
- assign _539_ = _018_[0] ? d_in[16:9] : d_in[8:1];
- assign _540_ = _018_[0] ? d_in[48:41] : d_in[40:33];
- assign _541_ = _020_[0] ? d_in[16:9] : d_in[8:1];
- assign _542_ = _020_[0] ? d_in[48:41] : d_in[40:33];
- assign _543_ = _022_[0] ? d_in[16:9] : d_in[8:1];
- assign _544_ = _022_[0] ? d_in[48:41] : d_in[40:33];
- assign _545_ = _008_[0] ? d_in[32:25] : d_in[24:17];
- assign _546_ = _008_[0] ? d_in[64:57] : d_in[56:49];
- assign _547_ = _010_[0] ? d_in[32:25] : d_in[24:17];
- assign _548_ = _010_[0] ? d_in[64:57] : d_in[56:49];
- assign _549_ = _012_[0] ? d_in[32:25] : d_in[24:17];
- assign _550_ = _012_[0] ? d_in[64:57] : d_in[56:49];
- assign _551_ = _014_[0] ? d_in[32:25] : d_in[24:17];
- assign _552_ = _014_[0] ? d_in[64:57] : d_in[56:49];
- assign _553_ = _016_[0] ? d_in[32:25] : d_in[24:17];
- assign _554_ = _016_[0] ? d_in[64:57] : d_in[56:49];
- assign _555_ = _018_[0] ? d_in[32:25] : d_in[24:17];
- assign _556_ = _018_[0] ? d_in[64:57] : d_in[56:49];
- assign _557_ = _020_[0] ? d_in[32:25] : d_in[24:17];
- assign _558_ = _020_[0] ? d_in[64:57] : d_in[56:49];
- assign _559_ = _022_[0] ? d_in[32:25] : d_in[24:17];
- assign _560_ = _022_[0] ? d_in[64:57] : d_in[56:49];
- assign _321_ = _008_[1] ? _545_ : _529_;
- assign _322_ = _008_[1] ? _546_ : _530_;
- assign _324_ = _010_[1] ? _547_ : _531_;
- assign _325_ = _010_[1] ? _548_ : _532_;
- assign _327_ = _012_[1] ? _549_ : _533_;
- assign _328_ = _012_[1] ? _550_ : _534_;
- assign _330_ = _014_[1] ? _551_ : _535_;
- assign _331_ = _014_[1] ? _552_ : _536_;
- assign _333_ = _016_[1] ? _553_ : _537_;
- assign _334_ = _016_[1] ? _554_ : _538_;
- assign _336_ = _018_[1] ? _555_ : _539_;
- assign _337_ = _018_[1] ? _556_ : _540_;
- assign _339_ = _020_[1] ? _557_ : _541_;
- assign _340_ = _020_[1] ? _558_ : _542_;
- assign _342_ = _022_[1] ? _559_ : _543_;
- assign _343_ = _022_[1] ? _560_ : _544_;
- assign _000_ = l_in[166:103] + l_in[230:167];
- assign lsu_sum = l_in[0] ? _000_ : 64'h0000000000000000;
- assign _001_ = rst ? r[221:0] : { _291_, _290_, _289_ };
- assign _002_ = rst ? 3'h0 : _292_;
- assign _003_ = rst ? r[338:225] : { _294_[112], _320_, _294_[15:0], _293_ };
- always @(posedge clk)
- r <= { _003_, _002_, _001_ };
- assign _004_ = | r[241:234];
- assign _005_ = r[202:200] - 3'h1;
- assign _006_ = r[204] ? _005_ : 3'h0;
- assign _007_ = 3'h0 ^ _006_;
- assign _008_ = { 1'h0, _007_ } + { 1'h0, r[5:3] };
- assign _009_ = 3'h1 ^ _006_;
- assign _010_ = { 1'h0, _009_ } + { 1'h0, r[5:3] };
- assign _011_ = 3'h2 ^ _006_;
- assign _012_ = { 1'h0, _011_ } + { 1'h0, r[5:3] };
- assign _013_ = 3'h3 ^ _006_;
- assign _014_ = { 1'h0, _013_ } + { 1'h0, r[5:3] };
- assign _015_ = 3'h4 ^ _006_;
- assign _016_ = { 1'h0, _015_ } + { 1'h0, r[5:3] };
- assign _017_ = 3'h5 ^ _006_;
- assign _018_ = { 1'h0, _017_ } + { 1'h0, r[5:3] };
- assign _019_ = 3'h6 ^ _006_;
- assign _020_ = { 1'h0, _019_ } + { 1'h0, r[5:3] };
- assign _021_ = 3'h7 ^ _006_;
- assign _022_ = { 1'h0, _021_ } + { 1'h0, r[5:3] };
- assign _023_ = r[203] & _344_[7];
- assign _024_ = r[202] & _332_[7];
- assign _025_ = _023_ | _024_;
- assign _026_ = r[201] & _326_[7];
- assign _027_ = _025_ | _026_;
- assign _028_ = r[200] & _323_[7];
- assign _029_ = _027_ | _028_;
- assign _030_ = $signed(32'd0) < $signed({ 28'h0000000, r[203:200] });
- assign _031_ = ~ _008_[3];
- assign _032_ = ~ _008_[3];
- assign _033_ = _004_ ? { 1'h1, _031_ } : { _032_, 1'h0 };
- assign _034_ = _029_ & r[205];
- assign _035_ = _030_ ? _033_ : { 1'h0, _034_ };
- assign _036_ = _035_ == 2'h3;
- assign _037_ = _035_ == 2'h2;
- assign _038_ = _035_ == 2'h1;
- function [7:0] \8364 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8364 = b[7:0];
- 3'b?1?:
- \8364 = b[15:8];
- 3'b1??:
- \8364 = b[23:16];
- default:
- \8364 = a;
- endcase
- endfunction
- assign _039_ = \8364 (8'h00, { 8'hff, _323_, r[138:131] }, { _038_, _037_, _036_ });
- assign _040_ = $signed(32'd1) < $signed({ 28'h0000000, r[203:200] });
- assign _041_ = ~ _010_[3];
- assign _042_ = ~ _010_[3];
- assign _043_ = _004_ ? { 1'h1, _041_ } : { _042_, 1'h0 };
- assign _044_ = _029_ & r[205];
- assign _045_ = _040_ ? _043_ : { 1'h0, _044_ };
- assign _046_ = _045_ == 2'h3;
- assign _047_ = _045_ == 2'h2;
- assign _048_ = _045_ == 2'h1;
- function [7:0] \8401 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8401 = b[7:0];
- 3'b?1?:
- \8401 = b[15:8];
- 3'b1??:
- \8401 = b[23:16];
- default:
- \8401 = a;
- endcase
- endfunction
- assign _049_ = \8401 (8'h00, { 8'hff, _326_, r[146:139] }, { _048_, _047_, _046_ });
- assign _050_ = $signed(32'd2) < $signed({ 28'h0000000, r[203:200] });
- assign _051_ = ~ _012_[3];
- assign _052_ = ~ _012_[3];
- assign _053_ = _004_ ? { 1'h1, _051_ } : { _052_, 1'h0 };
- assign _054_ = _029_ & r[205];
- assign _055_ = _050_ ? _053_ : { 1'h0, _054_ };
- assign _056_ = _055_ == 2'h3;
- assign _057_ = _055_ == 2'h2;
- assign _058_ = _055_ == 2'h1;
- function [7:0] \8438 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8438 = b[7:0];
- 3'b?1?:
- \8438 = b[15:8];
- 3'b1??:
- \8438 = b[23:16];
- default:
- \8438 = a;
- endcase
- endfunction
- assign _059_ = \8438 (8'h00, { 8'hff, _329_, r[154:147] }, { _058_, _057_, _056_ });
- assign _060_ = $signed(32'd3) < $signed({ 28'h0000000, r[203:200] });
- assign _061_ = ~ _014_[3];
- assign _062_ = ~ _014_[3];
- assign _063_ = _004_ ? { 1'h1, _061_ } : { _062_, 1'h0 };
- assign _064_ = _029_ & r[205];
- assign _065_ = _060_ ? _063_ : { 1'h0, _064_ };
- assign _066_ = _065_ == 2'h3;
- assign _067_ = _065_ == 2'h2;
- assign _068_ = _065_ == 2'h1;
- function [7:0] \8475 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8475 = b[7:0];
- 3'b?1?:
- \8475 = b[15:8];
- 3'b1??:
- \8475 = b[23:16];
- default:
- \8475 = a;
- endcase
- endfunction
- assign _069_ = \8475 (8'h00, { 8'hff, _332_, r[162:155] }, { _068_, _067_, _066_ });
- assign _070_ = $signed(32'd4) < $signed({ 28'h0000000, r[203:200] });
- assign _071_ = ~ _016_[3];
- assign _072_ = ~ _016_[3];
- assign _073_ = _004_ ? { 1'h1, _071_ } : { _072_, 1'h0 };
- assign _074_ = _029_ & r[205];
- assign _075_ = _070_ ? _073_ : { 1'h0, _074_ };
- assign _076_ = _075_ == 2'h3;
- assign _077_ = _075_ == 2'h2;
- assign _078_ = _075_ == 2'h1;
- function [7:0] \8512 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8512 = b[7:0];
- 3'b?1?:
- \8512 = b[15:8];
- 3'b1??:
- \8512 = b[23:16];
- default:
- \8512 = a;
- endcase
- endfunction
- assign _079_ = \8512 (8'h00, { 8'hff, _335_, r[170:163] }, { _078_, _077_, _076_ });
- assign _080_ = $signed(32'd5) < $signed({ 28'h0000000, r[203:200] });
- assign _081_ = ~ _018_[3];
- assign _082_ = ~ _018_[3];
- assign _083_ = _004_ ? { 1'h1, _081_ } : { _082_, 1'h0 };
- assign _084_ = _029_ & r[205];
- assign _085_ = _080_ ? _083_ : { 1'h0, _084_ };
- assign _086_ = _085_ == 2'h3;
- assign _087_ = _085_ == 2'h2;
- assign _088_ = _085_ == 2'h1;
- function [7:0] \8549 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8549 = b[7:0];
- 3'b?1?:
- \8549 = b[15:8];
- 3'b1??:
- \8549 = b[23:16];
- default:
- \8549 = a;
- endcase
- endfunction
- assign _089_ = \8549 (8'h00, { 8'hff, _338_, r[178:171] }, { _088_, _087_, _086_ });
- assign _090_ = $signed(32'd6) < $signed({ 28'h0000000, r[203:200] });
- assign _091_ = ~ _020_[3];
- assign _092_ = ~ _020_[3];
- assign _093_ = _004_ ? { 1'h1, _091_ } : { _092_, 1'h0 };
- assign _094_ = _029_ & r[205];
- assign _095_ = _090_ ? _093_ : { 1'h0, _094_ };
- assign _096_ = _095_ == 2'h3;
- assign _097_ = _095_ == 2'h2;
- assign _098_ = _095_ == 2'h1;
- function [7:0] \8586 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8586 = b[7:0];
- 3'b?1?:
- \8586 = b[15:8];
- 3'b1??:
- \8586 = b[23:16];
- default:
- \8586 = a;
- endcase
- endfunction
- assign _099_ = \8586 (8'h00, { 8'hff, _341_, r[186:179] }, { _098_, _097_, _096_ });
- assign _100_ = $signed(32'd7) < $signed({ 28'h0000000, r[203:200] });
- assign _101_ = ~ _022_[3];
- assign _102_ = ~ _022_[3];
- assign _103_ = _004_ ? { 1'h1, _101_ } : { _102_, 1'h0 };
- assign _104_ = _029_ & r[205];
- assign _105_ = _100_ ? _103_ : { 1'h0, _104_ };
- assign _106_ = _105_ == 2'h3;
- assign _107_ = _105_ == 2'h2;
- assign _108_ = _105_ == 2'h1;
- function [7:0] \8622 ;
- input [7:0] a;
- input [23:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \8622 = b[7:0];
- 3'b?1?:
- \8622 = b[15:8];
- 3'b1??:
- \8622 = b[23:16];
- default:
- \8622 = a;
- endcase
- endfunction
- assign _109_ = \8622 (8'h00, { 8'hff, _344_, r[194:187] }, { _108_, _107_, _106_ });
- assign _110_ = r[66:6] + 61'h0000000000000001;
- assign _111_ = l_in[6:1] == 6'h1e;
- assign _112_ = l_in[6:1] == 6'h1d;
- assign _113_ = l_in[6:1] == 6'h14;
- assign _114_ = l_in[6:1] == 6'h3a;
- assign _115_ = ~ l_in[86];
- assign _116_ = ~ l_in[82];
- assign _117_ = _115_ & _116_;
- assign _118_ = ~ l_in[87];
- assign _119_ = _118_ ? { 32'h00000000, r[337:306] } : r[305:242];
- assign _120_ = _117_ ? _119_ : m_in[69:6];
- assign _121_ = l_in[6:1] == 6'h26;
- assign _122_ = ~ l_in[86];
- assign _123_ = ~ l_in[82];
- assign _124_ = _122_ & _123_;
- assign _125_ = ~ l_in[87];
- assign _126_ = _125_ ? r[305:242] : l_in[294:231];
- assign _127_ = _125_ ? l_in[262:231] : r[337:306];
- assign _128_ = _124_ ? r[224:222] : 3'h5;
- assign _129_ = _124_ ? { _127_, _126_ } : r[337:242];
- assign _130_ = _124_ ? 1'h0 : 1'h1;
- assign _131_ = _124_ ? 1'h1 : 1'h0;
- assign _132_ = _124_ ? 1'h0 : 1'h1;
- assign _133_ = l_in[6:1] == 6'h2a;
- assign _134_ = l_in[6:1] == 6'h3d;
- assign _135_ = ~ _312_;
- assign _136_ = _135_ | 1'h0;
- function [0:0] \8706 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8706 = b[0:0];
- 7'b?????1?:
- \8706 = b[1:1];
- 7'b????1??:
- \8706 = b[2:2];
- 7'b???1???:
- \8706 = b[3:3];
- 7'b??1????:
- \8706 = b[4:4];
- 7'b?1?????:
- \8706 = b[5:5];
- 7'b1??????:
- \8706 = b[6:6];
- default:
- \8706 = a;
- endcase
- endfunction
- assign _137_ = \8706 (1'h0, 7'h02, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8707 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8707 = b[0:0];
- 7'b?????1?:
- \8707 = b[1:1];
- 7'b????1??:
- \8707 = b[2:2];
- 7'b???1???:
- \8707 = b[3:3];
- 7'b??1????:
- \8707 = b[4:4];
- 7'b?1?????:
- \8707 = b[5:5];
- 7'b1??????:
- \8707 = b[6:6];
- default:
- \8707 = a;
- endcase
- endfunction
- assign _138_ = \8707 (1'h0, 7'h08, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8708 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8708 = b[0:0];
- 7'b?????1?:
- \8708 = b[1:1];
- 7'b????1??:
- \8708 = b[2:2];
- 7'b???1???:
- \8708 = b[3:3];
- 7'b??1????:
- \8708 = b[4:4];
- 7'b?1?????:
- \8708 = b[5:5];
- 7'b1??????:
- \8708 = b[6:6];
- default:
- \8708 = a;
- endcase
- endfunction
- assign _139_ = \8708 (1'h0, 7'h04, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [63:0] \8709 ;
- input [63:0] a;
- input [447:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8709 = b[63:0];
- 7'b?????1?:
- \8709 = b[127:64];
- 7'b????1??:
- \8709 = b[191:128];
- 7'b???1???:
- \8709 = b[255:192];
- 7'b??1????:
- \8709 = b[319:256];
- 7'b?1?????:
- \8709 = b[383:320];
- 7'b1??????:
- \8709 = b[447:384];
- default:
- \8709 = a;
- endcase
- endfunction
- assign _140_ = \8709 (lsu_sum, { l_in[70:7], lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [2:0] \8711 ;
- input [2:0] a;
- input [20:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8711 = b[2:0];
- 7'b?????1?:
- \8711 = b[5:3];
- 7'b????1??:
- \8711 = b[8:6];
- 7'b???1???:
- \8711 = b[11:9];
- 7'b??1????:
- \8711 = b[14:12];
- 7'b?1?????:
- \8711 = b[17:15];
- 7'b1??????:
- \8711 = b[20:18];
- default:
- \8711 = a;
- endcase
- endfunction
- assign _141_ = \8711 (r[224:222], { 3'h4, _128_, r[224:222], 3'h5, r[224:222], r[224:222], r[224:222] }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [95:0] \8713 ;
- input [95:0] a;
- input [671:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8713 = b[95:0];
- 7'b?????1?:
- \8713 = b[191:96];
- 7'b????1??:
- \8713 = b[287:192];
- 7'b???1???:
- \8713 = b[383:288];
- 7'b??1????:
- \8713 = b[479:384];
- 7'b?1?????:
- \8713 = b[575:480];
- 7'b1??????:
- \8713 = b[671:576];
- default:
- \8713 = a;
- endcase
- endfunction
- assign _142_ = \8713 (r[337:242], { r[337:242], _129_, r[337:242], r[337:242], r[337:242], r[337:242], r[337:242] }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8714 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8714 = b[0:0];
- 7'b?????1?:
- \8714 = b[1:1];
- 7'b????1??:
- \8714 = b[2:2];
- 7'b???1???:
- \8714 = b[3:3];
- 7'b??1????:
- \8714 = b[4:4];
- 7'b?1?????:
- \8714 = b[5:5];
- 7'b1??????:
- \8714 = b[6:6];
- default:
- \8714 = a;
- endcase
- endfunction
- assign _143_ = \8714 (1'h0, 7'h40, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8719 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8719 = b[0:0];
- 7'b?????1?:
- \8719 = b[1:1];
- 7'b????1??:
- \8719 = b[2:2];
- 7'b???1???:
- \8719 = b[3:3];
- 7'b??1????:
- \8719 = b[4:4];
- 7'b?1?????:
- \8719 = b[5:5];
- 7'b1??????:
- \8719 = b[6:6];
- default:
- \8719 = a;
- endcase
- endfunction
- assign _144_ = \8719 (1'h0, 7'h07, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8723 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8723 = b[0:0];
- 7'b?????1?:
- \8723 = b[1:1];
- 7'b????1??:
- \8723 = b[2:2];
- 7'b???1???:
- \8723 = b[3:3];
- 7'b??1????:
- \8723 = b[4:4];
- 7'b?1?????:
- \8723 = b[5:5];
- 7'b1??????:
- \8723 = b[6:6];
- default:
- \8723 = a;
- endcase
- endfunction
- assign _145_ = \8723 (1'h0, { 1'h1, _130_, 5'h08 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [63:0] \8724 ;
- input [63:0] a;
- input [447:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8724 = b[63:0];
- 7'b?????1?:
- \8724 = b[127:64];
- 7'b????1??:
- \8724 = b[191:128];
- 7'b???1???:
- \8724 = b[255:192];
- 7'b??1????:
- \8724 = b[319:256];
- 7'b?1?????:
- \8724 = b[383:320];
- 7'b1??????:
- \8724 = b[447:384];
- default:
- \8724 = a;
- endcase
- endfunction
- assign _146_ = \8724 (lsu_sum, { l_in[70:7], lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8727 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8727 = b[0:0];
- 7'b?????1?:
- \8727 = b[1:1];
- 7'b????1??:
- \8727 = b[2:2];
- 7'b???1???:
- \8727 = b[3:3];
- 7'b??1????:
- \8727 = b[4:4];
- 7'b?1?????:
- \8727 = b[5:5];
- 7'b1??????:
- \8727 = b[6:6];
- default:
- \8727 = a;
- endcase
- endfunction
- assign _147_ = \8727 (1'h0, { 1'h0, _131_, 5'h10 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8730 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8730 = b[0:0];
- 7'b?????1?:
- \8730 = b[1:1];
- 7'b????1??:
- \8730 = b[2:2];
- 7'b???1???:
- \8730 = b[3:3];
- 7'b??1????:
- \8730 = b[4:4];
- 7'b?1?????:
- \8730 = b[5:5];
- 7'b1??????:
- \8730 = b[6:6];
- default:
- \8730 = a;
- endcase
- endfunction
- assign _148_ = \8730 (1'h0, 7'h10, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [63:0] \8732 ;
- input [63:0] a;
- input [447:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8732 = b[63:0];
- 7'b?????1?:
- \8732 = b[127:64];
- 7'b????1??:
- \8732 = b[191:128];
- 7'b???1???:
- \8732 = b[255:192];
- 7'b??1????:
- \8732 = b[319:256];
- 7'b?1?????:
- \8732 = b[383:320];
- 7'b1??????:
- \8732 = b[447:384];
- default:
- \8732 = a;
- endcase
- endfunction
- assign _149_ = \8732 (64'h0000000000000000, { 128'h00000000000000000000000000000000, _120_, 256'h0000000000000000000000000000000000000000000000000000000000000000 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8736 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8736 = b[0:0];
- 7'b?????1?:
- \8736 = b[1:1];
- 7'b????1??:
- \8736 = b[2:2];
- 7'b???1???:
- \8736 = b[3:3];
- 7'b??1????:
- \8736 = b[4:4];
- 7'b?1?????:
- \8736 = b[5:5];
- 7'b1??????:
- \8736 = b[6:6];
- default:
- \8736 = a;
- endcase
- endfunction
- assign _150_ = \8736 (1'h0, 7'h48, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8738 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8738 = b[0:0];
- 7'b?????1?:
- \8738 = b[1:1];
- 7'b????1??:
- \8738 = b[2:2];
- 7'b???1???:
- \8738 = b[3:3];
- 7'b??1????:
- \8738 = b[4:4];
- 7'b?1?????:
- \8738 = b[5:5];
- 7'b1??????:
- \8738 = b[6:6];
- default:
- \8738 = a;
- endcase
- endfunction
- assign _151_ = \8738 (1'h0, { 1'h0, _132_, 5'h00 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- function [0:0] \8741 ;
- input [0:0] a;
- input [6:0] b;
- input [6:0] s;
- (* parallel_case *)
- casez (s)
- 7'b??????1:
- \8741 = b[0:0];
- 7'b?????1?:
- \8741 = b[1:1];
- 7'b????1??:
- \8741 = b[2:2];
- 7'b???1???:
- \8741 = b[3:3];
- 7'b??1????:
- \8741 = b[4:4];
- 7'b?1?????:
- \8741 = b[5:5];
- 7'b1??????:
- \8741 = b[6:6];
- default:
- \8741 = a;
- endcase
- endfunction
- assign _152_ = \8741 (1'h1, 7'h00, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
- assign _153_ = lsu_sum[31:28] == 4'hc;
- assign _154_ = ~ l_in[320];
- assign _155_ = _153_ & _154_;
- assign _156_ = _155_ ? 1'h1 : l_in[304];
- assign _157_ = l_in[303:300] == 4'h1;
- assign _158_ = l_in[303:300] == 4'h2;
- assign _159_ = l_in[303:300] == 4'h4;
- assign _160_ = l_in[303:300] == 4'h8;
- function [7:0] \8792 ;
- input [7:0] a;
- input [31:0] b;
- input [3:0] s;
- (* parallel_case *)
- casez (s)
- 4'b???1:
- \8792 = b[7:0];
- 4'b??1?:
- \8792 = b[15:8];
- 4'b?1??:
- \8792 = b[23:16];
- 4'b1???:
- \8792 = b[31:24];
- default:
- \8792 = a;
- endcase
- endfunction
- assign _161_ = \8792 (8'h00, 32'd4279173889, { _160_, _159_, _158_, _157_ });
- assign _162_ = { 8'h00, _161_ } << { 28'h0000000, _140_[2:0] };
- assign _163_ = l_in[302:300] - 3'h1;
- assign _164_ = l_in[305] ? _163_ : 3'h0;
- assign _165_ = 3'h0 ^ _164_;
- assign _166_ = _165_ + lsu_sum[2:0];
- assign _167_ = 3'h1 ^ _164_;
- assign _168_ = _167_ + lsu_sum[2:0];
- assign _169_ = 3'h2 ^ _164_;
- assign _170_ = _169_ + lsu_sum[2:0];
- assign _171_ = 3'h3 ^ _164_;
- assign _172_ = _171_ + lsu_sum[2:0];
- assign _173_ = 3'h4 ^ _164_;
- assign _174_ = _173_ + lsu_sum[2:0];
- assign _175_ = 3'h5 ^ _164_;
- assign _176_ = _175_ + lsu_sum[2:0];
- assign _177_ = 3'h6 ^ _164_;
- assign _178_ = _177_ + lsu_sum[2:0];
- assign _179_ = 3'h7 ^ _164_;
- assign _180_ = _179_ + lsu_sum[2:0];
- assign _181_ = _162_[15:8] == 8'h00;
- assign _182_ = _181_ ? 3'h2 : 3'h1;
- assign _183_ = _144_ ? _182_ : _141_;
- assign _184_ = _144_ ? 1'h1 : _145_;
- assign _185_ = l_in[0] ? { _528_, _527_, _526_, _525_, _524_, _523_, _522_, _521_, _140_, _139_, _138_, _137_ } : r[130:0];
- assign _186_ = l_in[0] ? { _143_, _142_, _162_, 1'h0, _183_, l_in[321:320], _156_, l_in[319:305], l_in[303:295] } : r[338:195];
- assign _187_ = l_in[0] ? _162_[7:0] : 8'h00;
- assign _188_ = l_in[0] ? _144_ : 1'h0;
- assign _189_ = l_in[0] ? _184_ : 1'h0;
- assign _190_ = l_in[0] ? _146_ : lsu_sum;
- assign _191_ = l_in[0] ? _147_ : 1'h0;
- assign _192_ = l_in[0] ? _148_ : 1'h0;
- assign _193_ = l_in[0] ? _149_ : 64'h0000000000000000;
- assign _194_ = l_in[0] ? _150_ : 1'h0;
- assign _195_ = l_in[0] ? _151_ : 1'h0;
- assign _196_ = l_in[0] ? _152_ : 1'h0;
- assign _197_ = r[224:222] == 3'h0;
- assign _198_ = r[224:222] == 3'h1;
- assign _199_ = r[225] ? { _110_, 3'h0 } : r[66:3];
- assign _200_ = ~ r[0];
- assign _201_ = d_in[67] ? 3'h0 : 3'h4;
- assign _202_ = d_in[67] ? 1'h1 : 1'h0;
- assign _203_ = d_in[67] ? 1'h0 : 1'h1;
- assign _204_ = d_in[67] ? _200_ : 1'h0;
- assign _205_ = d_in[67] ? d_in[67] : 1'h0;
- assign _206_ = ~ r[225];
- assign _207_ = _004_ & _206_;
- assign _208_ = _214_ ? { _344_, _341_, _338_, _335_, _332_, _329_, _326_, _323_ } : r[194:131];
- assign _209_ = r[0] & r[206];
- assign _210_ = _209_ ? 3'h3 : 3'h0;
- assign _211_ = _209_ ? 1'h1 : 1'h0;
- assign _212_ = _209_ ? 1'h0 : r[206];
- assign _213_ = _209_ ? 1'h0 : 1'h1;
- assign _214_ = _207_ & r[0];
- assign _215_ = _207_ ? r[224:222] : _210_;
- assign _216_ = _207_ ? 1'h1 : r[225];
- assign _217_ = _207_ ? 1'h1 : _211_;
- assign _218_ = _207_ ? 1'h0 : r[0];
- assign _219_ = _207_ ? 1'h0 : _212_;
- assign _220_ = _207_ ? 1'h0 : _213_;
- assign _221_ = d_in[66] ? r[194:131] : _208_;
- assign _222_ = d_in[66] ? _201_ : _215_;
- assign _223_ = d_in[66] ? r[225] : _216_;
- assign _224_ = d_in[66] ? 1'h1 : _217_;
- assign _225_ = _236_ ? _199_ : lsu_sum;
- assign _226_ = d_in[66] ? 1'h0 : _218_;
- assign _227_ = d_in[66] ? 1'h0 : _219_;
- assign _228_ = d_in[66] ? 1'h0 : _220_;
- assign _229_ = d_in[66] ? _202_ : 1'h0;
- assign _230_ = d_in[66] ? _203_ : 1'h0;
- assign _231_ = d_in[66] ? _204_ : 1'h0;
- assign _232_ = d_in[66] ? _205_ : 1'h0;
- assign _233_ = d_in[0] ? _221_ : r[194:131];
- assign _234_ = d_in[0] ? { _223_, _222_ } : r[225:222];
- assign _235_ = d_in[0] ? _224_ : 1'h1;
- assign _236_ = d_in[0] & d_in[66];
- assign _237_ = d_in[0] ? _226_ : 1'h0;
- assign _238_ = d_in[0] ? _227_ : 1'h0;
- assign _239_ = d_in[0] ? _228_ : 1'h0;
- assign _240_ = d_in[0] ? _229_ : 1'h0;
- assign _241_ = d_in[0] ? _230_ : 1'h0;
- assign _242_ = d_in[0] ? _231_ : 1'h0;
- assign _243_ = d_in[0] ? _232_ : 1'h0;
- assign _244_ = r[224:222] == 3'h2;
- assign _245_ = r[225] ? r[241:234] : r[233:226];
- assign _246_ = r[225] ? { _110_, 3'h0 } : r[66:3];
- assign _247_ = ~ m_in[1];
- assign _248_ = ~ m_in[4];
- assign _249_ = _247_ & _248_;
- assign _250_ = ~ m_in[5];
- assign _251_ = _249_ & _250_;
- assign _252_ = ~ m_in[2];
- assign _253_ = _251_ & _252_;
- assign _254_ = ~ m_in[3];
- assign _255_ = _253_ & _254_;
- assign _256_ = ~ r[338];
- assign _257_ = ~ r[225];
- assign _258_ = _004_ & _257_;
- assign _259_ = _258_ ? 3'h1 : 3'h2;
- assign _260_ = _256_ ? _259_ : 3'h0;
- assign _261_ = _256_ ? 1'h1 : 1'h0;
- assign _262_ = _256_ ? 1'h1 : 1'h0;
- assign _263_ = _256_ ? 1'h0 : 1'h1;
- assign _264_ = ~ r[0];
- assign _265_ = _255_ ? _260_ : 3'h0;
- assign _266_ = _255_ ? _261_ : 1'h0;
- assign _267_ = _255_ ? _262_ : 1'h1;
- assign _268_ = _255_ ? _263_ : 1'h0;
- assign _269_ = _255_ ? 1'h0 : 1'h1;
- assign _270_ = _255_ ? 2'h0 : { m_in[2], m_in[5] };
- assign _271_ = _255_ ? 1'h0 : _264_;
- assign _272_ = _255_ ? 1'h0 : m_in[4];
- assign _273_ = _255_ ? 1'h0 : m_in[1];
- assign _274_ = m_in[0] ? _265_ : r[224:222];
- assign _275_ = m_in[0] ? _266_ : 1'h0;
- assign _276_ = m_in[0] ? _267_ : 1'h1;
- assign _277_ = m_in[0] ? _268_ : 1'h0;
- assign _278_ = m_in[0] ? _269_ : 1'h0;
- assign _279_ = m_in[0] ? _270_ : 2'h0;
- assign _280_ = m_in[0] ? _271_ : 1'h0;
- assign _281_ = m_in[0] ? _272_ : 1'h0;
- assign _282_ = m_in[0] ? _273_ : 1'h0;
- assign _283_ = r[224:222] == 3'h4;
- assign _284_ = m_in[0] ? 3'h0 : r[224:222];
- assign _285_ = m_in[0] ? 1'h0 : 1'h1;
- assign _286_ = m_in[0] ? 1'h1 : 1'h0;
- assign _287_ = r[224:222] == 3'h5;
- assign _288_ = r[224:222] == 3'h3;
- function [130:0] \9166 ;
- input [130:0] a;
- input [785:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9166 = b[130:0];
- 6'b????1?:
- \9166 = b[261:131];
- 6'b???1??:
- \9166 = b[392:262];
- 6'b??1???:
- \9166 = b[523:393];
- 6'b?1????:
- \9166 = b[654:524];
- 6'b1?????:
- \9166 = b[785:655];
- default:
- \9166 = a;
- endcase
- endfunction
- assign _289_ = \9166 (131'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { r[130:0], r[130:0], r[130:0], r[130:0], r[130:0], _185_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [63:0] \9169 ;
- input [63:0] a;
- input [383:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9169 = b[63:0];
- 6'b????1?:
- \9169 = b[127:64];
- 6'b???1??:
- \9169 = b[191:128];
- 6'b??1???:
- \9169 = b[255:192];
- 6'b?1????:
- \9169 = b[319:256];
- 6'b1?????:
- \9169 = b[383:320];
- default:
- \9169 = a;
- endcase
- endfunction
- assign _290_ = \9169 (64'hxxxxxxxxxxxxxxxx, { r[194:131], r[194:131], r[194:131], _233_, r[194:131], r[194:131] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [26:0] \9173 ;
- input [26:0] a;
- input [161:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9173 = b[26:0];
- 6'b????1?:
- \9173 = b[53:27];
- 6'b???1??:
- \9173 = b[80:54];
- 6'b??1???:
- \9173 = b[107:81];
- 6'b?1????:
- \9173 = b[134:108];
- 6'b1?????:
- \9173 = b[161:135];
- default:
- \9173 = a;
- endcase
- endfunction
- assign _291_ = \9173 (27'hxxxxxxx, { r[221:195], r[221:195], r[221:195], r[221:195], r[221:195], _186_[26:0] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [2:0] \9177 ;
- input [2:0] a;
- input [17:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9177 = b[2:0];
- 6'b????1?:
- \9177 = b[5:3];
- 6'b???1??:
- \9177 = b[8:6];
- 6'b??1???:
- \9177 = b[11:9];
- 6'b?1????:
- \9177 = b[14:12];
- 6'b1?????:
- \9177 = b[17:15];
- default:
- \9177 = a;
- endcase
- endfunction
- assign _292_ = \9177 (3'hx, { 3'h0, _284_, _274_, _234_[2:0], 3'h2, _186_[29:27] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9182 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9182 = b[0:0];
- 6'b????1?:
- \9182 = b[1:1];
- 6'b???1??:
- \9182 = b[2:2];
- 6'b??1???:
- \9182 = b[3:3];
- 6'b?1????:
- \9182 = b[4:4];
- 6'b1?????:
- \9182 = b[5:5];
- default:
- \9182 = a;
- endcase
- endfunction
- assign _293_ = \9182 (1'hx, { r[225], r[225], r[225], _234_[3], r[225], _186_[30] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [112:0] \9186 ;
- input [112:0] a;
- input [677:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9186 = b[112:0];
- 6'b????1?:
- \9186 = b[225:113];
- 6'b???1??:
- \9186 = b[338:226];
- 6'b??1???:
- \9186 = b[451:339];
- 6'b?1????:
- \9186 = b[564:452];
- 6'b1?????:
- \9186 = b[677:565];
- default:
- \9186 = a;
- endcase
- endfunction
- assign _294_ = \9186 (113'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { r[338:226], r[338:226], r[338:226], r[338:226], r[338:226], _186_[143:31] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [7:0] \9204 ;
- input [7:0] a;
- input [47:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9204 = b[7:0];
- 6'b????1?:
- \9204 = b[15:8];
- 6'b???1??:
- \9204 = b[23:16];
- 6'b??1???:
- \9204 = b[31:24];
- 6'b?1????:
- \9204 = b[39:32];
- 6'b1?????:
- \9204 = b[47:40];
- default:
- \9204 = a;
- endcase
- endfunction
- assign _295_ = \9204 (8'hxx, { 16'h0000, _245_, 8'h00, r[241:234], _187_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9209 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9209 = b[0:0];
- 6'b????1?:
- \9209 = b[1:1];
- 6'b???1??:
- \9209 = b[2:2];
- 6'b??1???:
- \9209 = b[3:3];
- 6'b?1????:
- \9209 = b[4:4];
- 6'b1?????:
- \9209 = b[5:5];
- default:
- \9209 = a;
- endcase
- endfunction
- assign _296_ = \9209 (1'hx, { 2'h0, _275_, 2'h1, _188_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9214 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9214 = b[0:0];
- 6'b????1?:
- \9214 = b[1:1];
- 6'b???1??:
- \9214 = b[2:2];
- 6'b??1???:
- \9214 = b[3:3];
- 6'b?1????:
- \9214 = b[4:4];
- 6'b1?????:
- \9214 = b[5:5];
- default:
- \9214 = a;
- endcase
- endfunction
- assign _297_ = \9214 (1'hx, { 1'h0, _285_, _276_, _235_, 1'h1, _189_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [63:0] \9217 ;
- input [63:0] a;
- input [383:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9217 = b[63:0];
- 6'b????1?:
- \9217 = b[127:64];
- 6'b???1??:
- \9217 = b[191:128];
- 6'b??1???:
- \9217 = b[255:192];
- 6'b?1????:
- \9217 = b[319:256];
- 6'b1?????:
- \9217 = b[383:320];
- default:
- \9217 = a;
- endcase
- endfunction
- assign _298_ = \9217 (64'hxxxxxxxxxxxxxxxx, { lsu_sum, lsu_sum, _246_, _225_, _110_, 3'h0, _190_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9220 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9220 = b[0:0];
- 6'b????1?:
- \9220 = b[1:1];
- 6'b???1??:
- \9220 = b[2:2];
- 6'b??1???:
- \9220 = b[3:3];
- 6'b?1????:
- \9220 = b[4:4];
- 6'b1?????:
- \9220 = b[5:5];
- default:
- \9220 = a;
- endcase
- endfunction
- assign _299_ = \9220 (1'hx, { 3'h0, _237_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9225 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9225 = b[0:0];
- 6'b????1?:
- \9225 = b[1:1];
- 6'b???1??:
- \9225 = b[2:2];
- 6'b??1???:
- \9225 = b[3:3];
- 6'b?1????:
- \9225 = b[4:4];
- 6'b1?????:
- \9225 = b[5:5];
- default:
- \9225 = a;
- endcase
- endfunction
- assign _300_ = \9225 (1'hx, { 3'h4, _238_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9230 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9230 = b[0:0];
- 6'b????1?:
- \9230 = b[1:1];
- 6'b???1??:
- \9230 = b[2:2];
- 6'b??1???:
- \9230 = b[3:3];
- 6'b?1????:
- \9230 = b[4:4];
- 6'b1?????:
- \9230 = b[5:5];
- default:
- \9230 = a;
- endcase
- endfunction
- assign _301_ = \9230 (1'hx, { 1'h1, _286_, _277_, _239_, 1'h0, _191_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9234 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9234 = b[0:0];
- 6'b????1?:
- \9234 = b[1:1];
- 6'b???1??:
- \9234 = b[2:2];
- 6'b??1???:
- \9234 = b[3:3];
- 6'b?1????:
- \9234 = b[4:4];
- 6'b1?????:
- \9234 = b[5:5];
- default:
- \9234 = a;
- endcase
- endfunction
- assign _302_ = \9234 (1'hx, { 5'h00, _192_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [63:0] \9238 ;
- input [63:0] a;
- input [383:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9238 = b[63:0];
- 6'b????1?:
- \9238 = b[127:64];
- 6'b???1??:
- \9238 = b[191:128];
- 6'b??1???:
- \9238 = b[255:192];
- 6'b?1????:
- \9238 = b[319:256];
- 6'b1?????:
- \9238 = b[383:320];
- default:
- \9238 = a;
- endcase
- endfunction
- assign _303_ = \9238 (64'hxxxxxxxxxxxxxxxx, { 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000, _193_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9242 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9242 = b[0:0];
- 6'b????1?:
- \9242 = b[1:1];
- 6'b???1??:
- \9242 = b[2:2];
- 6'b??1???:
- \9242 = b[3:3];
- 6'b?1????:
- \9242 = b[4:4];
- 6'b1?????:
- \9242 = b[5:5];
- default:
- \9242 = a;
- endcase
- endfunction
- assign _304_ = \9242 (1'hx, { 2'h0, _278_, _240_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9246 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9246 = b[0:0];
- 6'b????1?:
- \9246 = b[1:1];
- 6'b???1??:
- \9246 = b[2:2];
- 6'b??1???:
- \9246 = b[3:3];
- 6'b?1????:
- \9246 = b[4:4];
- 6'b1?????:
- \9246 = b[5:5];
- default:
- \9246 = a;
- endcase
- endfunction
- assign _305_ = \9246 (1'hx, { 3'h0, _241_, 1'h0, _194_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [1:0] \9250 ;
- input [1:0] a;
- input [11:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9250 = b[1:0];
- 6'b????1?:
- \9250 = b[3:2];
- 6'b???1??:
- \9250 = b[5:4];
- 6'b??1???:
- \9250 = b[7:6];
- 6'b?1????:
- \9250 = b[9:8];
- 6'b1?????:
- \9250 = b[11:10];
- default:
- \9250 = a;
- endcase
- endfunction
- assign _306_ = \9250 (2'hx, { 4'h0, _279_, 6'h00 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9253 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9253 = b[0:0];
- 6'b????1?:
- \9253 = b[1:1];
- 6'b???1??:
- \9253 = b[2:2];
- 6'b??1???:
- \9253 = b[3:3];
- 6'b?1????:
- \9253 = b[4:4];
- 6'b1?????:
- \9253 = b[5:5];
- default:
- \9253 = a;
- endcase
- endfunction
- assign _307_ = \9253 (1'hx, { 2'h0, _280_, _242_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9256 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9256 = b[0:0];
- 6'b????1?:
- \9256 = b[1:1];
- 6'b???1??:
- \9256 = b[2:2];
- 6'b??1???:
- \9256 = b[3:3];
- 6'b?1????:
- \9256 = b[4:4];
- 6'b1?????:
- \9256 = b[5:5];
- default:
- \9256 = a;
- endcase
- endfunction
- assign _308_ = \9256 (1'hx, { 2'h0, _281_, 3'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9259 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9259 = b[0:0];
- 6'b????1?:
- \9259 = b[1:1];
- 6'b???1??:
- \9259 = b[2:2];
- 6'b??1???:
- \9259 = b[3:3];
- 6'b?1????:
- \9259 = b[4:4];
- 6'b1?????:
- \9259 = b[5:5];
- default:
- \9259 = a;
- endcase
- endfunction
- assign _309_ = \9259 (1'hx, { 3'h0, _243_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9262 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9262 = b[0:0];
- 6'b????1?:
- \9262 = b[1:1];
- 6'b???1??:
- \9262 = b[2:2];
- 6'b??1???:
- \9262 = b[3:3];
- 6'b?1????:
- \9262 = b[4:4];
- 6'b1?????:
- \9262 = b[5:5];
- default:
- \9262 = a;
- endcase
- endfunction
- assign _310_ = \9262 (1'hx, { 2'h0, _282_, 3'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9275 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9275 = b[0:0];
- 6'b????1?:
- \9275 = b[1:1];
- 6'b???1??:
- \9275 = b[2:2];
- 6'b??1???:
- \9275 = b[3:3];
- 6'b?1????:
- \9275 = b[4:4];
- 6'b1?????:
- \9275 = b[5:5];
- default:
- \9275 = a;
- endcase
- endfunction
- assign _311_ = \9275 (1'hx, { 5'h00, _195_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- function [0:0] \9279 ;
- input [0:0] a;
- input [5:0] b;
- input [5:0] s;
- (* parallel_case *)
- casez (s)
- 6'b?????1:
- \9279 = b[0:0];
- 6'b????1?:
- \9279 = b[1:1];
- 6'b???1??:
- \9279 = b[2:2];
- 6'b??1???:
- \9279 = b[3:3];
- 6'b?1????:
- \9279 = b[4:4];
- 6'b1?????:
- \9279 = b[5:5];
- default:
- \9279 = a;
- endcase
- endfunction
- assign _312_ = \9279 (1'hx, { 5'h00, _196_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
- assign _313_ = _300_ ? { r[66:3], r[211:207], 1'h1 } : { _109_, _099_, _089_, _079_, _069_, _059_, _049_, _039_, r[199:195], _299_ };
- assign _314_ = _302_ ? { _303_, l_in[299:295], 1'h1 } : _313_;
- assign _315_ = r[218] & _301_;
- assign _316_ = ~ r[338];
- assign _317_ = _304_ & _316_;
- assign _318_ = ~ m_in[3];
- assign _319_ = _318_ ? { 1'h0, _310_, 1'h0, _309_, _308_, 1'h0, _307_, 5'h00, _306_, 18'h00000 } : _294_[111:80];
- assign _320_ = _317_ ? { _319_, _298_ } : _294_[111:16];
- assign _323_ = _008_[2] ? _322_ : _321_;
- assign _326_ = _010_[2] ? _325_ : _324_;
- assign _329_ = _012_[2] ? _328_ : _327_;
- assign _332_ = _014_[2] ? _331_ : _330_;
- assign _335_ = _016_[2] ? _334_ : _333_;
- assign _338_ = _018_[2] ? _337_ : _336_;
- assign _341_ = _020_[2] ? _340_ : _339_;
- assign _344_ = _022_[2] ? _343_ : _342_;
- assign _345_ = ~ _166_[2];
- assign _346_ = ~ _166_[1];
- assign _347_ = _345_ & _346_;
- assign _348_ = _345_ & _166_[1];
- assign _349_ = _166_[2] & _346_;
- assign _350_ = _166_[2] & _166_[1];
- assign _351_ = ~ _166_[0];
- assign _352_ = _347_ & _351_;
- assign _353_ = _347_ & _166_[0];
- assign _354_ = _348_ & _351_;
- assign _355_ = _348_ & _166_[0];
- assign _356_ = _349_ & _351_;
- assign _357_ = _349_ & _166_[0];
- assign _358_ = _350_ & _351_;
- assign _359_ = _350_ & _166_[0];
- assign _360_ = _352_ ? l_in[238:231] : r[74:67];
- assign _361_ = _353_ ? l_in[238:231] : r[82:75];
- assign _362_ = _354_ ? l_in[238:231] : r[90:83];
- assign _363_ = _355_ ? l_in[238:231] : r[98:91];
- assign _364_ = _356_ ? l_in[238:231] : r[106:99];
- assign _365_ = _357_ ? l_in[238:231] : r[114:107];
- assign _366_ = _358_ ? l_in[238:231] : r[122:115];
- assign _367_ = _359_ ? l_in[238:231] : r[130:123];
- assign _368_ = ~ _168_[2];
- assign _369_ = ~ _168_[1];
- assign _370_ = _368_ & _369_;
- assign _371_ = _368_ & _168_[1];
- assign _372_ = _168_[2] & _369_;
- assign _373_ = _168_[2] & _168_[1];
- assign _374_ = ~ _168_[0];
- assign _375_ = _370_ & _374_;
- assign _376_ = _370_ & _168_[0];
- assign _377_ = _371_ & _374_;
- assign _378_ = _371_ & _168_[0];
- assign _379_ = _372_ & _374_;
- assign _380_ = _372_ & _168_[0];
- assign _381_ = _373_ & _374_;
- assign _382_ = _373_ & _168_[0];
- assign _383_ = _375_ ? l_in[246:239] : _360_;
- assign _384_ = _376_ ? l_in[246:239] : _361_;
- assign _385_ = _377_ ? l_in[246:239] : _362_;
- assign _386_ = _378_ ? l_in[246:239] : _363_;
- assign _387_ = _379_ ? l_in[246:239] : _364_;
- assign _388_ = _380_ ? l_in[246:239] : _365_;
- assign _389_ = _381_ ? l_in[246:239] : _366_;
- assign _390_ = _382_ ? l_in[246:239] : _367_;
- assign _391_ = ~ _170_[2];
- assign _392_ = ~ _170_[1];
- assign _393_ = _391_ & _392_;
- assign _394_ = _391_ & _170_[1];
- assign _395_ = _170_[2] & _392_;
- assign _396_ = _170_[2] & _170_[1];
- assign _397_ = ~ _170_[0];
- assign _398_ = _393_ & _397_;
- assign _399_ = _393_ & _170_[0];
- assign _400_ = _394_ & _397_;
- assign _401_ = _394_ & _170_[0];
- assign _402_ = _395_ & _397_;
- assign _403_ = _395_ & _170_[0];
- assign _404_ = _396_ & _397_;
- assign _405_ = _396_ & _170_[0];
- assign _406_ = _398_ ? l_in[254:247] : _383_;
- assign _407_ = _399_ ? l_in[254:247] : _384_;
- assign _408_ = _400_ ? l_in[254:247] : _385_;
- assign _409_ = _401_ ? l_in[254:247] : _386_;
- assign _410_ = _402_ ? l_in[254:247] : _387_;
- assign _411_ = _403_ ? l_in[254:247] : _388_;
- assign _412_ = _404_ ? l_in[254:247] : _389_;
- assign _413_ = _405_ ? l_in[254:247] : _390_;
- assign _414_ = ~ _172_[2];
- assign _415_ = ~ _172_[1];
- assign _416_ = _414_ & _415_;
- assign _417_ = _414_ & _172_[1];
- assign _418_ = _172_[2] & _415_;
- assign _419_ = _172_[2] & _172_[1];
- assign _420_ = ~ _172_[0];
- assign _421_ = _416_ & _420_;
- assign _422_ = _416_ & _172_[0];
- assign _423_ = _417_ & _420_;
- assign _424_ = _417_ & _172_[0];
- assign _425_ = _418_ & _420_;
- assign _426_ = _418_ & _172_[0];
- assign _427_ = _419_ & _420_;
- assign _428_ = _419_ & _172_[0];
- assign _429_ = _421_ ? l_in[262:255] : _406_;
- assign _430_ = _422_ ? l_in[262:255] : _407_;
- assign _431_ = _423_ ? l_in[262:255] : _408_;
- assign _432_ = _424_ ? l_in[262:255] : _409_;
- assign _433_ = _425_ ? l_in[262:255] : _410_;
- assign _434_ = _426_ ? l_in[262:255] : _411_;
- assign _435_ = _427_ ? l_in[262:255] : _412_;
- assign _436_ = _428_ ? l_in[262:255] : _413_;
- assign _437_ = ~ _174_[2];
- assign _438_ = ~ _174_[1];
- assign _439_ = _437_ & _438_;
- assign _440_ = _437_ & _174_[1];
- assign _441_ = _174_[2] & _438_;
- assign _442_ = _174_[2] & _174_[1];
- assign _443_ = ~ _174_[0];
- assign _444_ = _439_ & _443_;
- assign _445_ = _439_ & _174_[0];
- assign _446_ = _440_ & _443_;
- assign _447_ = _440_ & _174_[0];
- assign _448_ = _441_ & _443_;
- assign _449_ = _441_ & _174_[0];
- assign _450_ = _442_ & _443_;
- assign _451_ = _442_ & _174_[0];
- assign _452_ = _444_ ? l_in[270:263] : _429_;
- assign _453_ = _445_ ? l_in[270:263] : _430_;
- assign _454_ = _446_ ? l_in[270:263] : _431_;
- assign _455_ = _447_ ? l_in[270:263] : _432_;
- assign _456_ = _448_ ? l_in[270:263] : _433_;
- assign _457_ = _449_ ? l_in[270:263] : _434_;
- assign _458_ = _450_ ? l_in[270:263] : _435_;
- assign _459_ = _451_ ? l_in[270:263] : _436_;
- assign _460_ = ~ _176_[2];
- assign _461_ = ~ _176_[1];
- assign _462_ = _460_ & _461_;
- assign _463_ = _460_ & _176_[1];
- assign _464_ = _176_[2] & _461_;
- assign _465_ = _176_[2] & _176_[1];
- assign _466_ = ~ _176_[0];
- assign _467_ = _462_ & _466_;
- assign _468_ = _462_ & _176_[0];
- assign _469_ = _463_ & _466_;
- assign _470_ = _463_ & _176_[0];
- assign _471_ = _464_ & _466_;
- assign _472_ = _464_ & _176_[0];
- assign _473_ = _465_ & _466_;
- assign _474_ = _465_ & _176_[0];
- assign _475_ = _467_ ? l_in[278:271] : _452_;
- assign _476_ = _468_ ? l_in[278:271] : _453_;
- assign _477_ = _469_ ? l_in[278:271] : _454_;
- assign _478_ = _470_ ? l_in[278:271] : _455_;
- assign _479_ = _471_ ? l_in[278:271] : _456_;
- assign _480_ = _472_ ? l_in[278:271] : _457_;
- assign _481_ = _473_ ? l_in[278:271] : _458_;
- assign _482_ = _474_ ? l_in[278:271] : _459_;
- assign _483_ = ~ _178_[2];
- assign _484_ = ~ _178_[1];
- assign _485_ = _483_ & _484_;
- assign _486_ = _483_ & _178_[1];
- assign _487_ = _178_[2] & _484_;
- assign _488_ = _178_[2] & _178_[1];
- assign _489_ = ~ _178_[0];
- assign _490_ = _485_ & _489_;
- assign _491_ = _485_ & _178_[0];
- assign _492_ = _486_ & _489_;
- assign _493_ = _486_ & _178_[0];
- assign _494_ = _487_ & _489_;
- assign _495_ = _487_ & _178_[0];
- assign _496_ = _488_ & _489_;
- assign _497_ = _488_ & _178_[0];
- assign _498_ = _490_ ? l_in[286:279] : _475_;
- assign _499_ = _491_ ? l_in[286:279] : _476_;
- assign _500_ = _492_ ? l_in[286:279] : _477_;
- assign _501_ = _493_ ? l_in[286:279] : _478_;
- assign _502_ = _494_ ? l_in[286:279] : _479_;
- assign _503_ = _495_ ? l_in[286:279] : _480_;
- assign _504_ = _496_ ? l_in[286:279] : _481_;
- assign _505_ = _497_ ? l_in[286:279] : _482_;
- assign _506_ = ~ _180_[2];
- assign _507_ = ~ _180_[1];
- assign _508_ = _506_ & _507_;
- assign _509_ = _506_ & _180_[1];
- assign _510_ = _180_[2] & _507_;
- assign _511_ = _180_[2] & _180_[1];
- assign _512_ = ~ _180_[0];
- assign _513_ = _508_ & _512_;
- assign _514_ = _508_ & _180_[0];
- assign _515_ = _509_ & _512_;
- assign _516_ = _509_ & _180_[0];
- assign _517_ = _510_ & _512_;
- assign _518_ = _510_ & _180_[0];
- assign _519_ = _511_ & _512_;
- assign _520_ = _511_ & _180_[0];
- assign _521_ = _513_ ? l_in[294:287] : _498_;
- assign _522_ = _514_ ? l_in[294:287] : _499_;
- assign _523_ = _515_ ? l_in[294:287] : _500_;
- assign _524_ = _516_ ? l_in[294:287] : _501_;
- assign _525_ = _517_ ? l_in[294:287] : _502_;
- assign _526_ = _518_ ? l_in[294:287] : _503_;
- assign _527_ = _519_ ? l_in[294:287] : _504_;
- assign _528_ = _520_ ? l_in[294:287] : _505_;
- assign e_out = { r[338], m_in[3:2], m_in[5:4], m_in[1], _304_ };
- assign l_out = { d_in[65], _315_, r[216:212], _314_, _301_ };
- assign d_out = { _295_, _289_[130:67], _298_, _291_[26:25], _291_[22], _291_[24], _289_[2], _289_[0], _296_ };
- assign m_out = { l_in[294:231], _298_, l_in[86:82], l_in[91:87], r[221], r[0], _294_[112], _311_, l_in[78], _289_[1], _305_ };
- assign stall_out = _297_;
-endmodule
-
-module logical(rs, rb, op, invert_in, invert_out, datalen, result, popcnt, parity);
- wire [63:0] _00_;
- wire [63:0] _01_;
- wire [63:0] _02_;
- wire _03_;
- wire [63:0] _04_;
- wire _05_;
- wire [63:0] _06_;
- wire [63:0] _07_;
- wire [63:0] _08_;
- wire [63:0] _09_;
- wire [1:0] _10_;
- wire [1:0] _11_;
- wire [1:0] _12_;
- wire [1:0] _13_;
- wire [1:0] _14_;
- wire [1:0] _15_;
- wire [1:0] _16_;
- wire [1:0] _17_;
- wire [1:0] _18_;
- wire [1:0] _19_;
- wire [1:0] _20_;
- wire [1:0] _21_;
- wire [1:0] _22_;
- wire [1:0] _23_;
- wire [1:0] _24_;
- wire [1:0] _25_;
- wire [1:0] _26_;
- wire [1:0] _27_;
- wire [1:0] _28_;
- wire [1:0] _29_;
- wire [1:0] _30_;
- wire [1:0] _31_;
- wire [1:0] _32_;
- wire [1:0] _33_;
- wire [1:0] _34_;
- wire [1:0] _35_;
- wire [1:0] _36_;
- wire [1:0] _37_;
- wire [1:0] _38_;
- wire [1:0] _39_;
- wire [1:0] _40_;
- wire [1:0] _41_;
- wire [2:0] _42_;
- wire [2:0] _43_;
- wire [2:0] _44_;
- wire [2:0] _45_;
- wire [2:0] _46_;
- wire [2:0] _47_;
- wire [2:0] _48_;
- wire [2:0] _49_;
- wire [2:0] _50_;
- wire [2:0] _51_;
- wire [2:0] _52_;
- wire [2:0] _53_;
- wire [2:0] _54_;
- wire [2:0] _55_;
- wire [2:0] _56_;
- wire [2:0] _57_;
- wire [3:0] _58_;
- wire [3:0] _59_;
- wire [3:0] _60_;
- wire [3:0] _61_;
- wire [3:0] _62_;
- wire [3:0] _63_;
- wire [3:0] _64_;
- wire [3:0] _65_;
- wire [5:0] _66_;
- wire [5:0] _67_;
- wire [5:0] _68_;
- wire [5:0] _69_;
- wire [5:0] _70_;
- wire [5:0] _71_;
- wire _72_;
- wire _73_;
- wire [6:0] _74_;
- wire [5:0] _75_;
- wire _76_;
- wire [5:0] _77_;
- wire [3:0] _78_;
- wire [2:0] _79_;
- wire [3:0] _80_;
- wire [3:0] _81_;
- wire [3:0] _82_;
- wire [3:0] _83_;
- wire [1:0] _84_;
- wire [3:0] _85_;
- wire [3:0] _86_;
- wire [3:0] _87_;
- wire _88_;
- wire _89_;
- wire _90_;
- wire _91_;
- wire _92_;
- wire _93_;
- wire _94_;
- input [3:0] datalen;
- input invert_in;
- input invert_out;
- input [5:0] op;
- wire par0;
- wire par1;
- output [63:0] parity;
- output [63:0] popcnt;
- input [63:0] rb;
- output [63:0] result;
- input [63:0] rs;
- assign _00_ = ~ rb;
- assign _01_ = invert_in ? _00_ : rb;
- assign _02_ = rs & _01_;
- assign _03_ = op == 6'h03;
- assign _04_ = rs | _01_;
- assign _05_ = op == 6'h2e;
- assign _06_ = rs ^ _01_;
- function [63:0] \19328 ;
- input [63:0] a;
- input [127:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \19328 = b[63:0];
- 2'b1?:
- \19328 = b[127:64];
- default:
- \19328 = a;
- endcase
- endfunction
- assign _07_ = \19328 (_06_, { _04_, _02_ }, { _05_, _03_ });
- assign _08_ = ~ _07_;
- assign _09_ = invert_out ? _08_ : _07_;
- assign _10_ = { 1'h0, rs[0] } + { 1'h0, rs[1] };
- assign _11_ = { 1'h0, rs[2] } + { 1'h0, rs[3] };
- assign _12_ = { 1'h0, rs[4] } + { 1'h0, rs[5] };
- assign _13_ = { 1'h0, rs[6] } + { 1'h0, rs[7] };
- assign _14_ = { 1'h0, rs[8] } + { 1'h0, rs[9] };
- assign _15_ = { 1'h0, rs[10] } + { 1'h0, rs[11] };
- assign _16_ = { 1'h0, rs[12] } + { 1'h0, rs[13] };
- assign _17_ = { 1'h0, rs[14] } + { 1'h0, rs[15] };
- assign _18_ = { 1'h0, rs[16] } + { 1'h0, rs[17] };
- assign _19_ = { 1'h0, rs[18] } + { 1'h0, rs[19] };
- assign _20_ = { 1'h0, rs[20] } + { 1'h0, rs[21] };
- assign _21_ = { 1'h0, rs[22] } + { 1'h0, rs[23] };
- assign _22_ = { 1'h0, rs[24] } + { 1'h0, rs[25] };
- assign _23_ = { 1'h0, rs[26] } + { 1'h0, rs[27] };
- assign _24_ = { 1'h0, rs[28] } + { 1'h0, rs[29] };
- assign _25_ = { 1'h0, rs[30] } + { 1'h0, rs[31] };
- assign _26_ = { 1'h0, rs[32] } + { 1'h0, rs[33] };
- assign _27_ = { 1'h0, rs[34] } + { 1'h0, rs[35] };
- assign _28_ = { 1'h0, rs[36] } + { 1'h0, rs[37] };
- assign _29_ = { 1'h0, rs[38] } + { 1'h0, rs[39] };
- assign _30_ = { 1'h0, rs[40] } + { 1'h0, rs[41] };
- assign _31_ = { 1'h0, rs[42] } + { 1'h0, rs[43] };
- assign _32_ = { 1'h0, rs[44] } + { 1'h0, rs[45] };
- assign _33_ = { 1'h0, rs[46] } + { 1'h0, rs[47] };
- assign _34_ = { 1'h0, rs[48] } + { 1'h0, rs[49] };
- assign _35_ = { 1'h0, rs[50] } + { 1'h0, rs[51] };
- assign _36_ = { 1'h0, rs[52] } + { 1'h0, rs[53] };
- assign _37_ = { 1'h0, rs[54] } + { 1'h0, rs[55] };
- assign _38_ = { 1'h0, rs[56] } + { 1'h0, rs[57] };
- assign _39_ = { 1'h0, rs[58] } + { 1'h0, rs[59] };
- assign _40_ = { 1'h0, rs[60] } + { 1'h0, rs[61] };
- assign _41_ = { 1'h0, rs[62] } + { 1'h0, rs[63] };
- assign _42_ = { 1'h0, _10_ } + { 1'h0, _11_ };
- assign _43_ = { 1'h0, _12_ } + { 1'h0, _13_ };
- assign _44_ = { 1'h0, _14_ } + { 1'h0, _15_ };
- assign _45_ = { 1'h0, _16_ } + { 1'h0, _17_ };
- assign _46_ = { 1'h0, _18_ } + { 1'h0, _19_ };
- assign _47_ = { 1'h0, _20_ } + { 1'h0, _21_ };
- assign _48_ = { 1'h0, _22_ } + { 1'h0, _23_ };
- assign _49_ = { 1'h0, _24_ } + { 1'h0, _25_ };
- assign _50_ = { 1'h0, _26_ } + { 1'h0, _27_ };
- assign _51_ = { 1'h0, _28_ } + { 1'h0, _29_ };
- assign _52_ = { 1'h0, _30_ } + { 1'h0, _31_ };
- assign _53_ = { 1'h0, _32_ } + { 1'h0, _33_ };
- assign _54_ = { 1'h0, _34_ } + { 1'h0, _35_ };
- assign _55_ = { 1'h0, _36_ } + { 1'h0, _37_ };
- assign _56_ = { 1'h0, _38_ } + { 1'h0, _39_ };
- assign _57_ = { 1'h0, _40_ } + { 1'h0, _41_ };
- assign _58_ = { 1'h0, _42_ } + { 1'h0, _43_ };
- assign _59_ = { 1'h0, _44_ } + { 1'h0, _45_ };
- assign _60_ = { 1'h0, _46_ } + { 1'h0, _47_ };
- assign _61_ = { 1'h0, _48_ } + { 1'h0, _49_ };
- assign _62_ = { 1'h0, _50_ } + { 1'h0, _51_ };
- assign _63_ = { 1'h0, _52_ } + { 1'h0, _53_ };
- assign _64_ = { 1'h0, _54_ } + { 1'h0, _55_ };
- assign _65_ = { 1'h0, _56_ } + { 1'h0, _57_ };
- assign _66_ = { 2'h0, _58_ } + { 2'h0, _59_ };
- assign _67_ = _66_ + { 2'h0, _60_ };
- assign _68_ = _67_ + { 2'h0, _61_ };
- assign _69_ = { 2'h0, _62_ } + { 2'h0, _63_ };
- assign _70_ = _69_ + { 2'h0, _64_ };
- assign _71_ = _70_ + { 2'h0, _65_ };
- assign _72_ = datalen[3:2] == 2'h0;
- assign _73_ = ~ datalen[3];
- assign _74_ = { 1'h0, _68_ } + { 1'h0, _71_ };
- assign _75_ = _73_ ? _68_ : _74_[5:0];
- assign _76_ = _73_ ? 1'h0 : _74_[6];
- assign _77_ = _73_ ? _71_ : 6'h00;
- assign _78_ = _72_ ? _58_ : _75_[3:0];
- assign _79_ = _72_ ? 3'h0 : { _76_, _75_[5:4] };
- assign _80_ = _72_ ? _59_ : 4'h0;
- assign _81_ = _72_ ? _60_ : 4'h0;
- assign _82_ = _72_ ? _61_ : 4'h0;
- assign _83_ = _72_ ? _62_ : _77_[3:0];
- assign _84_ = _72_ ? 2'h0 : _77_[5:4];
- assign _85_ = _72_ ? _63_ : 4'h0;
- assign _86_ = _72_ ? _64_ : 4'h0;
- assign _87_ = _72_ ? _65_ : 4'h0;
- assign _88_ = rs[0] ^ rs[8];
- assign _89_ = _88_ ^ rs[16];
- assign par0 = _89_ ^ rs[24];
- assign _90_ = rs[32] ^ rs[40];
- assign _91_ = _90_ ^ rs[48];
- assign par1 = _91_ ^ rs[56];
- assign _92_ = par0 ^ par1;
- assign _93_ = datalen[3] ? _92_ : par0;
- assign _94_ = datalen[3] ? 1'h0 : par1;
- assign result = _09_;
- assign popcnt = { 4'h0, _87_, 4'h0, _86_, 4'h0, _85_, 2'h0, _84_, _83_, 4'h0, _82_, 4'h0, _81_, 4'h0, _80_, 1'h0, _79_, _78_ };
- assign parity = { 31'h00000000, _94_, 31'h00000000, _93_ };
-endmodule
-
-module microwatt_wrapper(clk, rst, wishbone_insn_dat_r, wishbone_insn_ack, wishbone_insn_stall, wishbone_data_dat_r, wishbone_data_ack, wishbone_data_stall, dmi_addr, dmi_din, dmi_req, dmi_wr, wishbone_insn_adr, wishbone_insn_dat_w, wishbone_insn_cyc, wishbone_insn_stb, wishbone_insn_sel, wishbone_insn_we, wishbone_data_adr, wishbone_data_dat_w, wishbone_data_cyc, wishbone_data_stb, wishbone_data_sel, wishbone_data_we, dmi_dout, dmi_ack, terminated_out);
- wire [63:0] _0_;
- wire _1_;
- wire _2_;
- input clk;
- output dmi_ack;
- input [3:0] dmi_addr;
- input [63:0] dmi_din;
- output [63:0] dmi_dout;
- input dmi_req;
- input dmi_wr;
- input rst;
- output terminated_out;
- input wishbone_data_ack;
- output [31:0] wishbone_data_adr;
- output wishbone_data_cyc;
- input [63:0] wishbone_data_dat_r;
- output [63:0] wishbone_data_dat_w;
- wire [106:0] wishbone_data_out;
- output [7:0] wishbone_data_sel;
- input wishbone_data_stall;
- output wishbone_data_stb;
- output wishbone_data_we;
- input wishbone_insn_ack;
- output [31:0] wishbone_insn_adr;
- output wishbone_insn_cyc;
- input [63:0] wishbone_insn_dat_r;
- output [63:0] wishbone_insn_dat_w;
- wire [106:0] wishbone_insn_out;
- output [7:0] wishbone_insn_sel;
- input wishbone_insn_stall;
- output wishbone_insn_stb;
- output wishbone_insn_we;
- core_71ba14ecdd9e9507b1aeafd985ac12164cac4c4e microwatt_core (
- .alt_reset(1'h0),
- .clk(clk),
- .dmi_ack(_1_),
- .dmi_addr(dmi_addr),
- .dmi_din(dmi_din),
- .dmi_dout(_0_),
- .dmi_req(dmi_req),
- .dmi_wr(dmi_wr),
- .ext_irq(1'h0),
- .rst(rst),
- .terminated_out(_2_),
- .wishbone_data_in({ wishbone_data_stall, wishbone_data_ack, wishbone_data_dat_r }),
- .wishbone_data_out(wishbone_data_out),
- .wishbone_insn_in({ wishbone_insn_stall, wishbone_insn_ack, wishbone_insn_dat_r }),
- .wishbone_insn_out(wishbone_insn_out)
- );
- assign wishbone_insn_adr = wishbone_insn_out[31:0];
- assign wishbone_insn_dat_w = wishbone_insn_out[95:32];
- assign wishbone_insn_cyc = wishbone_insn_out[96];
- assign wishbone_insn_stb = wishbone_insn_out[97];
- assign wishbone_insn_sel = wishbone_insn_out[105:98];
- assign wishbone_insn_we = wishbone_insn_out[106];
- assign wishbone_data_adr = wishbone_data_out[31:0];
- assign wishbone_data_dat_w = wishbone_data_out[95:32];
- assign wishbone_data_cyc = wishbone_data_out[96];
- assign wishbone_data_stb = wishbone_data_out[97];
- assign wishbone_data_sel = wishbone_data_out[105:98];
- assign wishbone_data_we = wishbone_data_out[106];
- assign dmi_dout = _0_;
- assign dmi_ack = _1_;
- assign terminated_out = _2_;
-endmodule
-
-module mmu(clk, rst, l_in, d_in, l_out, d_out, i_out);
- wire [63:0] _000_;
- wire _001_;
- wire [66:0] _002_;
- wire [63:0] _003_;
- wire [31:0] _004_;
- wire [3:0] _005_;
- wire [63:0] _006_;
- wire _007_;
- wire [63:0] _008_;
- wire _009_;
- wire [135:0] _010_;
- wire _011_;
- wire _012_;
- wire [30:0] _013_;
- wire _014_;
- wire _015_;
- wire _016_;
- wire [18:0] _017_;
- wire _018_;
- wire _019_;
- wire _020_;
- wire _021_;
- wire _022_;
- wire _023_;
- wire _024_;
- wire _025_;
- wire _026_;
- wire _027_;
- wire _028_;
- wire _029_;
- wire _030_;
- wire _031_;
- wire _032_;
- wire _033_;
- wire _034_;
- wire _035_;
- wire _036_;
- wire _037_;
- wire _038_;
- wire _039_;
- wire _040_;
- wire _041_;
- wire _042_;
- wire _043_;
- wire _044_;
- wire _045_;
- wire _046_;
- wire _047_;
- wire _048_;
- wire _049_;
- wire _050_;
- wire _051_;
- wire _052_;
- wire _053_;
- wire _054_;
- wire _055_;
- wire _056_;
- wire _057_;
- wire _058_;
- wire _059_;
- wire _060_;
- wire _061_;
- wire _062_;
- wire _063_;
- wire _064_;
- wire _065_;
- wire _066_;
- wire _067_;
- wire _068_;
- wire _069_;
- wire _070_;
- wire _071_;
- wire _072_;
- wire _073_;
- wire _074_;
- wire _075_;
- wire _076_;
- wire _077_;
- wire _078_;
- wire _079_;
- wire _080_;
- wire _081_;
- wire _082_;
- wire _083_;
- wire _084_;
- wire _085_;
- wire _086_;
- wire _087_;
- wire _088_;
- wire _089_;
- wire _090_;
- wire _091_;
- wire _092_;
- wire _093_;
- wire _094_;
- wire _095_;
- wire _096_;
- wire _097_;
- wire _098_;
- wire _099_;
- wire _100_;
- wire _101_;
- wire _102_;
- wire _103_;
- wire _104_;
- wire _105_;
- wire _106_;
- wire _107_;
- wire _108_;
- wire _109_;
- wire _110_;
- wire _111_;
- wire _112_;
- wire _113_;
- wire _114_;
- wire _115_;
- wire _116_;
- wire _117_;
- wire _118_;
- wire _119_;
- wire _120_;
- wire _121_;
- wire _122_;
- wire _123_;
- wire _124_;
- wire _125_;
- wire _126_;
- wire _127_;
- wire _128_;
- wire _129_;
- wire _130_;
- wire _131_;
- wire _132_;
- wire [63:0] _133_;
- wire _134_;
- wire _135_;
- wire _136_;
- wire _137_;
- wire _138_;
- wire _139_;
- wire _140_;
- wire _141_;
- wire _142_;
- wire _143_;
- wire _144_;
- wire [3:0] _145_;
- wire _146_;
- wire [3:0] _147_;
- wire [5:0] _148_;
- wire _149_;
- wire _150_;
- wire [3:0] _151_;
- wire _152_;
- wire _153_;
- wire [5:0] _154_;
- wire _155_;
- wire _156_;
- wire _157_;
- wire _158_;
- wire [67:0] _159_;
- wire [3:0] _160_;
- wire _161_;
- wire [6:0] _162_;
- wire _163_;
- wire _164_;
- wire _165_;
- wire _166_;
- wire _167_;
- wire [63:0] _168_;
- wire [31:0] _169_;
- wire _170_;
- wire [99:0] _171_;
- wire _172_;
- wire _173_;
- wire _174_;
- wire _175_;
- wire _176_;
- wire _177_;
- wire [3:0] _178_;
- wire _179_;
- wire _180_;
- wire _181_;
- wire _182_;
- wire [64:0] _183_;
- wire [64:0] _184_;
- wire _185_;
- wire [3:0] _186_;
- wire _187_;
- wire [3:0] _188_;
- wire [196:0] _189_;
- wire _190_;
- wire _191_;
- wire [200:0] _192_;
- wire [1:0] _193_;
- wire _194_;
- wire [5:0] _195_;
- wire [5:0] _196_;
- wire [30:0] _197_;
- wire [30:0] _198_;
- wire _199_;
- wire _200_;
- wire _201_;
- wire _202_;
- wire _203_;
- wire _204_;
- wire [5:0] _205_;
- wire _206_;
- wire _207_;
- wire [3:0] _208_;
- wire _209_;
- wire [3:0] _210_;
- wire _211_;
- wire _212_;
- wire _213_;
- wire _214_;
- wire _215_;
- wire _216_;
- wire _217_;
- wire _218_;
- wire _219_;
- wire _220_;
- wire _221_;
- wire _222_;
- wire _223_;
- wire _224_;
- wire _225_;
- wire _226_;
- wire _227_;
- wire _228_;
- wire _229_;
- wire _230_;
- wire [3:0] _231_;
- wire [1:0] _232_;
- wire _233_;
- wire _234_;
- wire _235_;
- wire _236_;
- wire _237_;
- wire [5:0] _238_;
- wire [3:0] _239_;
- wire [66:0] _240_;
- wire _241_;
- wire [3:0] _242_;
- wire [66:0] _243_;
- wire _244_;
- wire [1:0] _245_;
- wire [3:0] _246_;
- wire [66:0] _247_;
- wire _248_;
- wire _249_;
- wire [1:0] _250_;
- wire [3:0] _251_;
- wire [131:0] _252_;
- wire _253_;
- wire [1:0] _254_;
- wire [3:0] _255_;
- wire [132:0] _256_;
- wire [1:0] _257_;
- wire _258_;
- wire _259_;
- wire [3:0] _260_;
- wire _261_;
- wire _262_;
- wire _263_;
- wire _264_;
- wire _265_;
- wire [67:0] _266_;
- wire [95:0] _267_;
- wire [3:0] _268_;
- wire [63:0] _269_;
- wire _270_;
- wire [63:0] _271_;
- wire _272_;
- wire [5:0] _273_;
- wire [4:0] _274_;
- wire [55:0] _275_;
- wire [63:0] _276_;
- wire _277_;
- wire _278_;
- wire _279_;
- wire [1:0] _280_;
- wire _281_;
- wire _282_;
- wire _283_;
- wire _284_;
- wire _285_;
- wire _286_;
- wire _287_;
- wire [31:0] _288_;
- wire [23:0] _289_;
- wire [23:0] _290_;
- wire [23:0] _291_;
- wire [23:0] _292_;
- wire [15:0] _293_;
- wire [15:0] _294_;
- wire [15:0] _295_;
- wire [15:0] _296_;
- wire [43:0] _297_;
- wire [43:0] _298_;
- wire [43:0] _299_;
- wire [43:0] _300_;
- wire [63:0] _301_;
- wire [63:0] _302_;
- wire [63:0] _303_;
- wire [63:0] _304_;
- wire [63:0] _305_;
- wire [15:0] addrsh;
- input clk;
- input [66:0] d_in;
- output [131:0] d_out;
- output [130:0] i_out;
- input [144:0] l_in;
- output [69:0] l_out;
- reg [433:0] r;
- input rst;
- assign _055_ = $signed(32'd6) < $signed({ 26'h0000000, r[303:298] });
- assign _056_ = _055_ ? 1'h1 : 1'h0;
- assign _057_ = $signed(32'd7) < $signed({ 26'h0000000, r[303:298] });
- assign _058_ = _057_ ? 1'h1 : 1'h0;
- assign _059_ = $signed(32'd8) < $signed({ 26'h0000000, r[303:298] });
- assign _060_ = _059_ ? 1'h1 : 1'h0;
- assign _061_ = $signed(32'd9) < $signed({ 26'h0000000, r[303:298] });
- assign _062_ = _061_ ? 1'h1 : 1'h0;
- assign _063_ = $signed(32'd10) < $signed({ 26'h0000000, r[303:298] });
- assign _064_ = _063_ ? 1'h1 : 1'h0;
- assign _065_ = $signed(32'd11) < $signed({ 26'h0000000, r[303:298] });
- assign _066_ = _065_ ? 1'h1 : 1'h0;
- assign _067_ = $signed(32'd12) < $signed({ 26'h0000000, r[303:298] });
- assign _068_ = _067_ ? 1'h1 : 1'h0;
- assign _069_ = $signed(32'd13) < $signed({ 26'h0000000, r[303:298] });
- assign _070_ = _069_ ? 1'h1 : 1'h0;
- assign _071_ = $signed(32'd14) < $signed({ 26'h0000000, r[303:298] });
- assign _072_ = _071_ ? 1'h1 : 1'h0;
- assign _073_ = $signed(32'd15) < $signed({ 26'h0000000, r[303:298] });
- assign _074_ = _073_ ? 1'h1 : 1'h0;
- assign _075_ = $signed(32'd16) < $signed({ 26'h0000000, r[303:298] });
- assign _076_ = _075_ ? 1'h1 : 1'h0;
- assign _077_ = $signed(32'd17) < $signed({ 26'h0000000, r[303:298] });
- assign _078_ = _077_ ? 1'h1 : 1'h0;
- assign _079_ = $signed(32'd18) < $signed({ 26'h0000000, r[303:298] });
- assign _080_ = _079_ ? 1'h1 : 1'h0;
- assign _081_ = $signed(32'd19) < $signed({ 26'h0000000, r[303:298] });
- assign _082_ = _081_ ? 1'h1 : 1'h0;
- assign _083_ = $signed(32'd20) < $signed({ 26'h0000000, r[303:298] });
- assign _084_ = _083_ ? 1'h1 : 1'h0;
- assign _085_ = $signed(32'd21) < $signed({ 26'h0000000, r[303:298] });
- assign _086_ = _085_ ? 1'h1 : 1'h0;
- assign _087_ = $signed(32'd22) < $signed({ 26'h0000000, r[303:298] });
- assign _088_ = _087_ ? 1'h1 : 1'h0;
- assign _089_ = $signed(32'd23) < $signed({ 26'h0000000, r[303:298] });
- assign _090_ = _089_ ? 1'h1 : 1'h0;
- assign _091_ = $signed(32'd24) < $signed({ 26'h0000000, r[303:298] });
- assign _092_ = _091_ ? 1'h1 : 1'h0;
- assign _093_ = $signed(32'd25) < $signed({ 26'h0000000, r[303:298] });
- assign _094_ = _093_ ? 1'h1 : 1'h0;
- assign _095_ = $signed(32'd26) < $signed({ 26'h0000000, r[303:298] });
- assign _096_ = _095_ ? 1'h1 : 1'h0;
- assign _097_ = $signed(32'd27) < $signed({ 26'h0000000, r[303:298] });
- assign _098_ = _097_ ? 1'h1 : 1'h0;
- assign _099_ = $signed(32'd28) < $signed({ 26'h0000000, r[303:298] });
- assign _100_ = _099_ ? 1'h1 : 1'h0;
- assign _101_ = $signed(32'd29) < $signed({ 26'h0000000, r[303:298] });
- assign _102_ = _101_ ? 1'h1 : 1'h0;
- assign _103_ = $signed(32'd30) < $signed({ 26'h0000000, r[303:298] });
- assign _104_ = _103_ ? 1'h1 : 1'h0;
- assign _105_ = $signed(32'd31) < $signed({ 26'h0000000, r[303:298] });
- assign _106_ = _105_ ? 1'h1 : 1'h0;
- assign _107_ = $signed(32'd32) < $signed({ 26'h0000000, r[303:298] });
- assign _108_ = _107_ ? 1'h1 : 1'h0;
- assign _109_ = $signed(32'd33) < $signed({ 26'h0000000, r[303:298] });
- assign _110_ = _109_ ? 1'h1 : 1'h0;
- assign _111_ = $signed(32'd34) < $signed({ 26'h0000000, r[303:298] });
- assign _112_ = _111_ ? 1'h1 : 1'h0;
- assign _113_ = $signed(32'd35) < $signed({ 26'h0000000, r[303:298] });
- assign _114_ = _113_ ? 1'h1 : 1'h0;
- assign _115_ = $signed(32'd36) < $signed({ 26'h0000000, r[303:298] });
- assign _116_ = _115_ ? 1'h1 : 1'h0;
- assign _117_ = $signed(32'd37) < $signed({ 26'h0000000, r[303:298] });
- assign _118_ = _117_ ? 1'h1 : 1'h0;
- assign _119_ = $signed(32'd38) < $signed({ 26'h0000000, r[303:298] });
- assign _120_ = _119_ ? 1'h1 : 1'h0;
- assign _121_ = $signed(32'd39) < $signed({ 26'h0000000, r[303:298] });
- assign _122_ = _121_ ? 1'h1 : 1'h0;
- assign _123_ = $signed(32'd40) < $signed({ 26'h0000000, r[303:298] });
- assign _124_ = _123_ ? 1'h1 : 1'h0;
- assign _125_ = $signed(32'd41) < $signed({ 26'h0000000, r[303:298] });
- assign _126_ = _125_ ? 1'h1 : 1'h0;
- assign _127_ = $signed(32'd42) < $signed({ 26'h0000000, r[303:298] });
- assign _128_ = _127_ ? 1'h1 : 1'h0;
- assign _129_ = $signed(32'd43) < $signed({ 26'h0000000, r[303:298] });
- assign _130_ = _129_ ? 1'h1 : 1'h0;
- assign _131_ = ~ l_in[80];
- assign _132_ = _131_ ? r[232] : r[297];
- assign _133_ = _131_ ? r[231:168] : r[296:233];
- assign _134_ = l_in[5] | l_in[4];
- assign _135_ = ~ _134_;
- assign _136_ = l_in[2] | l_in[28];
- assign _137_ = _136_ | l_in[27];
- assign _138_ = _137_ | l_in[24];
- assign _139_ = _138_ | l_in[23];
- assign _140_ = _139_ | l_in[22];
- assign _141_ = _161_ ? 1'h0 : r[232];
- assign _142_ = _153_ ? 1'h0 : r[297];
- assign _143_ = ~ _132_;
- assign _144_ = { 1'h0, _133_[4:0] } == 6'h00;
- assign _145_ = _144_ ? 4'h8 : 4'h4;
- assign _146_ = _144_ ? 1'h1 : 1'h0;
- assign _147_ = _143_ ? 4'h2 : _145_;
- assign _148_ = _143_ ? { 1'h0, r[72:68] } : { 1'h0, _133_[62:61], _133_[7:5] };
- assign _149_ = _143_ ? 1'h0 : _146_;
- assign _150_ = l_in[1] ? 1'h0 : 1'h1;
- assign _151_ = l_in[1] ? 4'h1 : _147_;
- assign _152_ = l_in[1] & l_in[10];
- assign _153_ = l_in[1] & l_in[10];
- assign _154_ = l_in[1] ? { 1'h0, _133_[62:61], _133_[7:5] } : _148_;
- assign _155_ = l_in[1] ? 1'h0 : _149_;
- assign _156_ = l_in[1] ? 1'h1 : 1'h0;
- assign _157_ = l_in[1] ? 1'h1 : 1'h0;
- assign _158_ = l_in[1] ? _140_ : 1'h0;
- assign _159_ = l_in[0] ? { l_in[80:17], l_in[6], _135_, l_in[4], _150_ } : { r[67:1], 1'h0 };
- assign _160_ = l_in[0] ? _151_ : r[167:164];
- assign _161_ = l_in[0] & _152_;
- assign _162_ = l_in[0] ? { _154_, _142_ } : { 1'h0, _133_[62:61], _133_[7:5], r[297] };
- assign _163_ = l_in[0] ? _155_ : 1'h0;
- assign _164_ = l_in[0] ? _156_ : 1'h0;
- assign _165_ = l_in[0] ? _157_ : 1'h0;
- assign _166_ = l_in[0] ? _158_ : 1'h0;
- assign _167_ = ~ l_in[16];
- assign _168_ = _167_ ? r[131:68] : l_in[144:81];
- assign _169_ = _167_ ? l_in[112:81] : r[163:132];
- assign _170_ = _167_ ? _162_[0] : 1'h0;
- assign _171_ = l_in[3] ? { 4'h1, _169_, _168_ } : { _160_, r[163:68] };
- assign _172_ = l_in[3] ? 1'h0 : _141_;
- assign _173_ = l_in[3] ? _170_ : _162_[0];
- assign _174_ = l_in[3] ? 1'h1 : _164_;
- assign _175_ = l_in[3] ? 1'h1 : _165_;
- assign _176_ = l_in[3] ? 1'h1 : _166_;
- assign _177_ = r[167:164] == 4'h0;
- assign _178_ = d_in[1] ? 4'h0 : r[167:164];
- assign _179_ = d_in[1] ? 1'h1 : 1'h0;
- assign _180_ = r[167:164] == 4'h1;
- assign _181_ = r[167:164] == 4'h2;
- assign _182_ = ~ d_in[2];
- assign _183_ = r[67] ? r[232:168] : { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] };
- assign _184_ = r[67] ? { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] } : r[297:233];
- assign _185_ = { 1'h0, d_in[63:59] } == 6'h00;
- assign _186_ = _185_ ? 4'h8 : 4'h4;
- assign _187_ = _190_ ? 1'h1 : 1'h0;
- assign _188_ = _182_ ? _186_ : 4'h8;
- assign _189_ = _182_ ? { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], 1'h0, d_in[9:8], d_in[66:64], _184_, _183_ } : r[364:168];
- assign _190_ = _182_ & _185_;
- assign _191_ = _182_ ? 1'h0 : 1'h1;
- assign _192_ = d_in[1] ? { _189_, _188_ } : r[364:164];
- assign _193_ = d_in[1] ? { _191_, _187_ } : 2'h0;
- assign _194_ = r[167:164] == 4'h3;
- assign _195_ = r[303:298] + 6'h13;
- assign _196_ = _195_ - { 1'h0, r[308:304] };
- assign _197_ = ~ { _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
- assign _198_ = r[65:35] & _197_;
- assign _199_ = | _198_;
- assign _200_ = r[67] != r[66];
- assign _201_ = _200_ | _199_;
- assign _202_ = { 1'h0, r[308:304] } < 6'h05;
- assign _203_ = { 1'h0, r[308:304] } > 6'h10;
- assign _204_ = _202_ | _203_;
- assign _205_ = r[303:298] + 6'h13;
- assign _206_ = { 1'h0, r[308:304] } > _205_;
- assign _207_ = _204_ | _206_;
- assign _208_ = _207_ ? 4'h8 : 4'h5;
- assign _209_ = _207_ ? 1'h1 : 1'h0;
- assign _210_ = _201_ ? 4'h8 : _208_;
- assign _211_ = _201_ ? 1'h0 : _209_;
- assign _212_ = _201_ ? 1'h1 : 1'h0;
- assign _213_ = r[167:164] == 4'h4;
- assign _214_ = r[167:164] == 4'h5;
- assign _215_ = ~ d_in[2];
- assign _216_ = ~ d_in[62];
- assign _217_ = r[3] | _216_;
- assign _218_ = ~ r[1];
- assign _219_ = ~ r[2];
- assign _220_ = d_in[61] & _219_;
- assign _221_ = d_in[60] | _220_;
- assign _222_ = ~ d_in[64];
- assign _223_ = d_in[59] & _222_;
- assign _224_ = _218_ ? _221_ : _223_;
- assign _225_ = _217_ ? _224_ : 1'h0;
- assign _226_ = ~ r[2];
- assign _227_ = d_in[66] | _226_;
- assign _228_ = d_in[51] & _227_;
- assign _229_ = _225_ & _228_;
- assign _230_ = ~ _225_;
- assign _231_ = _229_ ? 4'h7 : 4'h8;
- assign _232_ = _229_ ? 2'h0 : { _225_, _230_ };
- assign _233_ = { 1'h0, d_in[63:59] } < 6'h05;
- assign _234_ = { 1'h0, d_in[63:59] } > 6'h10;
- assign _235_ = _233_ | _234_;
- assign _236_ = { 1'h0, d_in[63:59] } > r[303:298];
- assign _237_ = _235_ | _236_;
- assign _238_ = r[303:298] - { 1'h0, d_in[63:59] };
- assign _239_ = _237_ ? 4'h8 : 4'h5;
- assign _240_ = _237_ ? r[364:298] : { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], _238_ };
- assign _241_ = _237_ ? 1'h1 : 1'h0;
- assign _242_ = d_in[9] ? _231_ : _239_;
- assign _243_ = d_in[9] ? r[364:298] : _240_;
- assign _244_ = d_in[9] ? 1'h0 : _241_;
- assign _245_ = d_in[9] ? _232_ : 2'h0;
- assign _246_ = d_in[10] ? _242_ : 4'h8;
- assign _247_ = d_in[10] ? _243_ : r[364:298];
- assign _248_ = d_in[10] ? 1'h0 : 1'h1;
- assign _249_ = d_in[10] ? _244_ : 1'h0;
- assign _250_ = d_in[10] ? _245_ : 2'h0;
- assign _251_ = _215_ ? _246_ : 4'h8;
- assign _252_ = _215_ ? { _248_, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59], _247_ } : { 1'h0, r[428:298] };
- assign _253_ = _215_ ? _249_ : 1'h1;
- assign _254_ = _215_ ? _250_ : 2'h0;
- assign _255_ = d_in[1] ? _251_ : r[167:164];
- assign _256_ = d_in[1] ? { _253_, _252_ } : { 2'h0, r[428:298] };
- assign _257_ = d_in[1] ? _254_ : 2'h0;
- assign _258_ = r[167:164] == 4'h6;
- assign _259_ = ~ r[1];
- assign _260_ = _259_ ? 4'h1 : 4'h0;
- assign _261_ = _259_ ? 1'h1 : 1'h0;
- assign _262_ = _259_ ? 1'h0 : 1'h1;
- assign _263_ = _259_ ? 1'h0 : 1'h1;
- assign _264_ = r[167:164] == 4'h7;
- assign _265_ = r[167:164] == 4'h8;
- function [67:0] \10776 ;
- input [67:0] a;
- input [611:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10776 = b[67:0];
- 9'b???????1?:
- \10776 = b[135:68];
- 9'b??????1??:
- \10776 = b[203:136];
- 9'b?????1???:
- \10776 = b[271:204];
- 9'b????1????:
- \10776 = b[339:272];
- 9'b???1?????:
- \10776 = b[407:340];
- 9'b??1??????:
- \10776 = b[475:408];
- 9'b?1???????:
- \10776 = b[543:476];
- 9'b1????????:
- \10776 = b[611:544];
- default:
- \10776 = a;
- endcase
- endfunction
- assign _266_ = \10776 (68'hxxxxxxxxxxxxxxxxx, { r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, _159_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [95:0] \10780 ;
- input [95:0] a;
- input [863:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10780 = b[95:0];
- 9'b???????1?:
- \10780 = b[191:96];
- 9'b??????1??:
- \10780 = b[287:192];
- 9'b?????1???:
- \10780 = b[383:288];
- 9'b????1????:
- \10780 = b[479:384];
- 9'b???1?????:
- \10780 = b[575:480];
- 9'b??1??????:
- \10780 = b[671:576];
- 9'b?1???????:
- \10780 = b[767:672];
- 9'b1????????:
- \10780 = b[863:768];
- default:
- \10780 = a;
- endcase
- endfunction
- assign _267_ = \10780 (96'hxxxxxxxxxxxxxxxxxxxxxxxx, { r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], _171_[95:0] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [3:0] \10784 ;
- input [3:0] a;
- input [35:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10784 = b[3:0];
- 9'b???????1?:
- \10784 = b[7:4];
- 9'b??????1??:
- \10784 = b[11:8];
- 9'b?????1???:
- \10784 = b[15:12];
- 9'b????1????:
- \10784 = b[19:16];
- 9'b???1?????:
- \10784 = b[23:20];
- 9'b??1??????:
- \10784 = b[27:24];
- 9'b?1???????:
- \10784 = b[31:28];
- 9'b1????????:
- \10784 = b[35:32];
- default:
- \10784 = a;
- endcase
- endfunction
- assign _268_ = \10784 (4'hx, { 4'h0, _260_, _255_, 4'h6, _210_, _192_[3:0], 4'h3, _178_, _171_[99:96] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [63:0] \10788 ;
- input [63:0] a;
- input [575:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10788 = b[63:0];
- 9'b???????1?:
- \10788 = b[127:64];
- 9'b??????1??:
- \10788 = b[191:128];
- 9'b?????1???:
- \10788 = b[255:192];
- 9'b????1????:
- \10788 = b[319:256];
- 9'b???1?????:
- \10788 = b[383:320];
- 9'b??1??????:
- \10788 = b[447:384];
- 9'b?1???????:
- \10788 = b[511:448];
- 9'b1????????:
- \10788 = b[575:512];
- default:
- \10788 = a;
- endcase
- endfunction
- assign _269_ = \10788 (64'hxxxxxxxxxxxxxxxx, { r[231:168], r[231:168], r[231:168], r[231:168], r[231:168], _192_[67:4], r[231:168], r[231:168], r[231:168] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10792 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10792 = b[0:0];
- 9'b???????1?:
- \10792 = b[1:1];
- 9'b??????1??:
- \10792 = b[2:2];
- 9'b?????1???:
- \10792 = b[3:3];
- 9'b????1????:
- \10792 = b[4:4];
- 9'b???1?????:
- \10792 = b[5:5];
- 9'b??1??????:
- \10792 = b[6:6];
- 9'b?1???????:
- \10792 = b[7:7];
- 9'b1????????:
- \10792 = b[8:8];
- default:
- \10792 = a;
- endcase
- endfunction
- assign _270_ = \10792 (1'hx, { r[232], r[232], r[232], r[232], r[232], _192_[68], r[232], r[232], _172_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [63:0] \10796 ;
- input [63:0] a;
- input [575:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10796 = b[63:0];
- 9'b???????1?:
- \10796 = b[127:64];
- 9'b??????1??:
- \10796 = b[191:128];
- 9'b?????1???:
- \10796 = b[255:192];
- 9'b????1????:
- \10796 = b[319:256];
- 9'b???1?????:
- \10796 = b[383:320];
- 9'b??1??????:
- \10796 = b[447:384];
- 9'b?1???????:
- \10796 = b[511:448];
- 9'b1????????:
- \10796 = b[575:512];
- default:
- \10796 = a;
- endcase
- endfunction
- assign _271_ = \10796 (64'hxxxxxxxxxxxxxxxx, { r[296:233], r[296:233], r[296:233], r[296:233], r[296:233], _192_[132:69], r[296:233], r[296:233], r[296:233] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10800 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10800 = b[0:0];
- 9'b???????1?:
- \10800 = b[1:1];
- 9'b??????1??:
- \10800 = b[2:2];
- 9'b?????1???:
- \10800 = b[3:3];
- 9'b????1????:
- \10800 = b[4:4];
- 9'b???1?????:
- \10800 = b[5:5];
- 9'b??1??????:
- \10800 = b[6:6];
- 9'b?1???????:
- \10800 = b[7:7];
- 9'b1????????:
- \10800 = b[8:8];
- default:
- \10800 = a;
- endcase
- endfunction
- assign _272_ = \10800 (1'hx, { r[297], r[297], r[297], r[297], r[297], _192_[133], r[297], r[297], _173_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [5:0] \10805 ;
- input [5:0] a;
- input [53:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10805 = b[5:0];
- 9'b???????1?:
- \10805 = b[11:6];
- 9'b??????1??:
- \10805 = b[17:12];
- 9'b?????1???:
- \10805 = b[23:18];
- 9'b????1????:
- \10805 = b[29:24];
- 9'b???1?????:
- \10805 = b[35:30];
- 9'b??1??????:
- \10805 = b[41:36];
- 9'b?1???????:
- \10805 = b[47:42];
- 9'b1????????:
- \10805 = b[53:48];
- default:
- \10805 = a;
- endcase
- endfunction
- assign _273_ = \10805 (6'hxx, { r[303:298], r[303:298], _256_[5:0], r[303:298], _196_, _192_[139:134], r[303:298], r[303:298], _162_[6:1] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [4:0] \10810 ;
- input [4:0] a;
- input [44:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10810 = b[4:0];
- 9'b???????1?:
- \10810 = b[9:5];
- 9'b??????1??:
- \10810 = b[14:10];
- 9'b?????1???:
- \10810 = b[19:15];
- 9'b????1????:
- \10810 = b[24:20];
- 9'b???1?????:
- \10810 = b[29:25];
- 9'b??1??????:
- \10810 = b[34:30];
- 9'b?1???????:
- \10810 = b[39:35];
- 9'b1????????:
- \10810 = b[44:40];
- default:
- \10810 = a;
- endcase
- endfunction
- assign _274_ = \10810 (5'hxx, { r[308:304], r[308:304], _256_[10:6], r[308:304], r[308:304], _192_[144:140], r[308:304], r[308:304], _133_[4:0] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [55:0] \10815 ;
- input [55:0] a;
- input [503:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10815 = b[55:0];
- 9'b???????1?:
- \10815 = b[111:56];
- 9'b??????1??:
- \10815 = b[167:112];
- 9'b?????1???:
- \10815 = b[223:168];
- 9'b????1????:
- \10815 = b[279:224];
- 9'b???1?????:
- \10815 = b[335:280];
- 9'b??1??????:
- \10815 = b[391:336];
- 9'b?1???????:
- \10815 = b[447:392];
- 9'b1????????:
- \10815 = b[503:448];
- default:
- \10815 = a;
- endcase
- endfunction
- assign _275_ = \10815 (56'hxxxxxxxxxxxxxx, { r[364:309], r[364:309], _256_[66:11], r[364:309], r[364:309], _192_[200:145], r[364:309], r[364:309], _133_[55:8], 8'h00 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [63:0] \10819 ;
- input [63:0] a;
- input [575:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10819 = b[63:0];
- 9'b???????1?:
- \10819 = b[127:64];
- 9'b??????1??:
- \10819 = b[191:128];
- 9'b?????1???:
- \10819 = b[255:192];
- 9'b????1????:
- \10819 = b[319:256];
- 9'b???1?????:
- \10819 = b[383:320];
- 9'b??1??????:
- \10819 = b[447:384];
- 9'b?1???????:
- \10819 = b[511:448];
- 9'b1????????:
- \10819 = b[575:512];
- default:
- \10819 = a;
- endcase
- endfunction
- assign _276_ = \10819 (64'hxxxxxxxxxxxxxxxx, { r[428:365], r[428:365], _256_[130:67], r[428:365], r[428:365], r[428:365], r[428:365], r[428:365], r[428:365] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10823 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10823 = b[0:0];
- 9'b???????1?:
- \10823 = b[1:1];
- 9'b??????1??:
- \10823 = b[2:2];
- 9'b?????1???:
- \10823 = b[3:3];
- 9'b????1????:
- \10823 = b[4:4];
- 9'b???1?????:
- \10823 = b[5:5];
- 9'b??1??????:
- \10823 = b[6:6];
- 9'b?1???????:
- \10823 = b[7:7];
- 9'b1????????:
- \10823 = b[8:8];
- default:
- \10823 = a;
- endcase
- endfunction
- assign _277_ = \10823 (1'hx, { 2'h0, _256_[131], 2'h0, _193_[0], 2'h0, _163_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10827 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10827 = b[0:0];
- 9'b???????1?:
- \10827 = b[1:1];
- 9'b??????1??:
- \10827 = b[2:2];
- 9'b?????1???:
- \10827 = b[3:3];
- 9'b????1????:
- \10827 = b[4:4];
- 9'b???1?????:
- \10827 = b[5:5];
- 9'b??1??????:
- \10827 = b[6:6];
- 9'b?1???????:
- \10827 = b[7:7];
- 9'b1????????:
- \10827 = b[8:8];
- default:
- \10827 = a;
- endcase
- endfunction
- assign _278_ = \10827 (1'hx, { 2'h0, _256_[132], 1'h0, _211_, _193_[1], 3'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10829 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10829 = b[0:0];
- 9'b???????1?:
- \10829 = b[1:1];
- 9'b??????1??:
- \10829 = b[2:2];
- 9'b?????1???:
- \10829 = b[3:3];
- 9'b????1????:
- \10829 = b[4:4];
- 9'b???1?????:
- \10829 = b[5:5];
- 9'b??1??????:
- \10829 = b[6:6];
- 9'b?1???????:
- \10829 = b[7:7];
- 9'b1????????:
- \10829 = b[8:8];
- default:
- \10829 = a;
- endcase
- endfunction
- assign _279_ = \10829 (1'hx, { 4'h0, _212_, 4'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [1:0] \10832 ;
- input [1:0] a;
- input [17:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10832 = b[1:0];
- 9'b???????1?:
- \10832 = b[3:2];
- 9'b??????1??:
- \10832 = b[5:4];
- 9'b?????1???:
- \10832 = b[7:6];
- 9'b????1????:
- \10832 = b[9:8];
- 9'b???1?????:
- \10832 = b[11:10];
- 9'b??1??????:
- \10832 = b[13:12];
- 9'b?1???????:
- \10832 = b[15:14];
- 9'b1????????:
- \10832 = b[17:16];
- default:
- \10832 = a;
- endcase
- endfunction
- assign _280_ = \10832 (2'hx, { 4'h0, _257_, 12'h000 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10847 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10847 = b[0:0];
- 9'b???????1?:
- \10847 = b[1:1];
- 9'b??????1??:
- \10847 = b[2:2];
- 9'b?????1???:
- \10847 = b[3:3];
- 9'b????1????:
- \10847 = b[4:4];
- 9'b???1?????:
- \10847 = b[5:5];
- 9'b??1??????:
- \10847 = b[6:6];
- 9'b?1???????:
- \10847 = b[7:7];
- 9'b1????????:
- \10847 = b[8:8];
- default:
- \10847 = a;
- endcase
- endfunction
- assign _281_ = \10847 (1'hx, { 1'h0, _261_, 6'h12, _174_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10852 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10852 = b[0:0];
- 9'b???????1?:
- \10852 = b[1:1];
- 9'b??????1??:
- \10852 = b[2:2];
- 9'b?????1???:
- \10852 = b[3:3];
- 9'b????1????:
- \10852 = b[4:4];
- 9'b???1?????:
- \10852 = b[5:5];
- 9'b??1??????:
- \10852 = b[6:6];
- 9'b?1???????:
- \10852 = b[7:7];
- 9'b1????????:
- \10852 = b[8:8];
- default:
- \10852 = a;
- endcase
- endfunction
- assign _282_ = \10852 (1'hx, { 1'h1, _262_, 5'h00, _179_, 1'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10857 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10857 = b[0:0];
- 9'b???????1?:
- \10857 = b[1:1];
- 9'b??????1??:
- \10857 = b[2:2];
- 9'b?????1???:
- \10857 = b[3:3];
- 9'b????1????:
- \10857 = b[4:4];
- 9'b???1?????:
- \10857 = b[5:5];
- 9'b??1??????:
- \10857 = b[6:6];
- 9'b?1???????:
- \10857 = b[7:7];
- 9'b1????????:
- \10857 = b[8:8];
- default:
- \10857 = a;
- endcase
- endfunction
- assign _283_ = \10857 (1'hx, 9'h080, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10861 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10861 = b[0:0];
- 9'b???????1?:
- \10861 = b[1:1];
- 9'b??????1??:
- \10861 = b[2:2];
- 9'b?????1???:
- \10861 = b[3:3];
- 9'b????1????:
- \10861 = b[4:4];
- 9'b???1?????:
- \10861 = b[5:5];
- 9'b??1??????:
- \10861 = b[6:6];
- 9'b?1???????:
- \10861 = b[7:7];
- 9'b1????????:
- \10861 = b[8:8];
- default:
- \10861 = a;
- endcase
- endfunction
- assign _284_ = \10861 (1'hx, { 1'h0, _263_, 7'h00 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10865 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10865 = b[0:0];
- 9'b???????1?:
- \10865 = b[1:1];
- 9'b??????1??:
- \10865 = b[2:2];
- 9'b?????1???:
- \10865 = b[3:3];
- 9'b????1????:
- \10865 = b[4:4];
- 9'b???1?????:
- \10865 = b[5:5];
- 9'b??1??????:
- \10865 = b[6:6];
- 9'b?1???????:
- \10865 = b[7:7];
- 9'b1????????:
- \10865 = b[8:8];
- default:
- \10865 = a;
- endcase
- endfunction
- assign _285_ = \10865 (1'hx, { 8'h00, _175_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10869 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10869 = b[0:0];
- 9'b???????1?:
- \10869 = b[1:1];
- 9'b??????1??:
- \10869 = b[2:2];
- 9'b?????1???:
- \10869 = b[3:3];
- 9'b????1????:
- \10869 = b[4:4];
- 9'b???1?????:
- \10869 = b[5:5];
- 9'b??1??????:
- \10869 = b[6:6];
- 9'b?1???????:
- \10869 = b[7:7];
- 9'b1????????:
- \10869 = b[8:8];
- default:
- \10869 = a;
- endcase
- endfunction
- assign _286_ = \10869 (1'hx, { 8'h00, _176_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- function [0:0] \10874 ;
- input [0:0] a;
- input [8:0] b;
- input [8:0] s;
- (* parallel_case *)
- casez (s)
- 9'b????????1:
- \10874 = b[0:0];
- 9'b???????1?:
- \10874 = b[1:1];
- 9'b??????1??:
- \10874 = b[2:2];
- 9'b?????1???:
- \10874 = b[3:3];
- 9'b????1????:
- \10874 = b[4:4];
- 9'b???1?????:
- \10874 = b[5:5];
- 9'b??1??????:
- \10874 = b[6:6];
- 9'b?1???????:
- \10874 = b[7:7];
- 9'b1????????:
- \10874 = b[8:8];
- default:
- \10874 = a;
- endcase
- endfunction
- assign _287_ = \10874 (1'hx, 9'h004, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
- assign _288_ = r[67] ? 32'd0 : r[163:132];
- assign _289_ = ~ { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
- assign _290_ = r[103:80] & _289_;
- assign _291_ = _288_[31:8] & { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
- assign _292_ = _290_ | _291_;
- assign _293_ = ~ { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
- assign _294_ = r[327:312] & _293_;
- assign _295_ = addrsh & { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
- assign _296_ = _294_ | _295_;
- assign _297_ = ~ { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
- assign _298_ = r[420:377] & _297_;
- assign _299_ = r[59:16] & { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
- assign _300_ = _298_ | _299_;
- assign _301_ = _287_ ? { 8'h00, r[123:104], _292_, _288_[7:0], 4'h0 } : { 8'h00, r[364:328], _296_, 3'h0 };
- assign _302_ = _283_ ? { 8'h00, _300_, r[376:365] } : 64'h0000000000000000;
- assign _303_ = _283_ ? { r[67:16], 12'h000 } : _301_;
- assign _304_ = _285_ ? l_in[144:81] : _302_;
- assign _305_ = _285_ ? l_in[80:17] : _303_;
- assign _000_ = l_in[16] ? r[131:68] : { 32'h00000000, r[163:132] };
- assign _001_ = rst ? 1'h0 : _266_[0];
- assign _002_ = rst ? r[67:1] : _266_[67:1];
- assign _003_ = rst ? 64'h0000000000000000 : _267_[63:0];
- assign _004_ = rst ? r[163:132] : _267_[95:64];
- assign _005_ = rst ? 4'h0 : _268_;
- assign _006_ = rst ? r[231:168] : _269_;
- assign _007_ = rst ? 1'h0 : _270_;
- assign _008_ = rst ? r[296:233] : _271_;
- assign _009_ = rst ? 1'h0 : _272_;
- assign _010_ = rst ? r[433:298] : { _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_ };
- always @(posedge clk)
- r <= { _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
- assign _011_ = r[303:302] == 2'h0;
- assign _012_ = r[303:302] == 2'h1;
- function [30:0] \9811 ;
- input [30:0] a;
- input [61:0] b;
- input [1:0] s;
- (* parallel_case *)
- casez (s)
- 2'b?1:
- \9811 = b[30:0];
- 2'b1?:
- \9811 = b[61:31];
- default:
- \9811 = a;
- endcase
- endfunction
- assign _013_ = \9811 ({ 13'h0000, r[65:48] }, { r[62:32], r[46:16] }, { _012_, _011_ });
- assign _014_ = r[301:300] == 2'h0;
- assign _015_ = r[301:300] == 2'h1;
- assign _016_ = r[301:300] == 2'h2;
- function [18:0] \9824 ;
- input [18:0] a;
- input [56:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \9824 = b[18:0];
- 3'b?1?:
- \9824 = b[37:19];
- 3'b1??:
- \9824 = b[56:38];
- default:
- \9824 = a;
- endcase
- endfunction
- assign _017_ = \9824 (_013_[30:12], { _013_[26:8], _013_[22:4], _013_[18:0] }, { _016_, _015_, _014_ });
- assign _018_ = r[299:298] == 2'h0;
- assign _019_ = r[299:298] == 2'h1;
- assign _020_ = r[299:298] == 2'h2;
- function [15:0] \9837 ;
- input [15:0] a;
- input [47:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \9837 = b[15:0];
- 3'b?1?:
- \9837 = b[31:16];
- 3'b1??:
- \9837 = b[47:32];
- default:
- \9837 = a;
- endcase
- endfunction
- assign addrsh = \9837 (_017_[18:3], { _017_[17:2], _017_[16:1], _017_[15:0] }, { _020_, _019_, _018_ });
- assign _021_ = $signed(32'd5) < $signed({ 27'h0000000, r[308:304] });
- assign _022_ = _021_ ? 1'h1 : 1'h0;
- assign _023_ = $signed(32'd6) < $signed({ 27'h0000000, r[308:304] });
- assign _024_ = _023_ ? 1'h1 : 1'h0;
- assign _025_ = $signed(32'd7) < $signed({ 27'h0000000, r[308:304] });
- assign _026_ = _025_ ? 1'h1 : 1'h0;
- assign _027_ = $signed(32'd8) < $signed({ 27'h0000000, r[308:304] });
- assign _028_ = _027_ ? 1'h1 : 1'h0;
- assign _029_ = $signed(32'd9) < $signed({ 27'h0000000, r[308:304] });
- assign _030_ = _029_ ? 1'h1 : 1'h0;
- assign _031_ = $signed(32'd10) < $signed({ 27'h0000000, r[308:304] });
- assign _032_ = _031_ ? 1'h1 : 1'h0;
- assign _033_ = $signed(32'd11) < $signed({ 27'h0000000, r[308:304] });
- assign _034_ = _033_ ? 1'h1 : 1'h0;
- assign _035_ = $signed(32'd12) < $signed({ 27'h0000000, r[308:304] });
- assign _036_ = _035_ ? 1'h1 : 1'h0;
- assign _037_ = $signed(32'd13) < $signed({ 27'h0000000, r[308:304] });
- assign _038_ = _037_ ? 1'h1 : 1'h0;
- assign _039_ = $signed(32'd14) < $signed({ 27'h0000000, r[308:304] });
- assign _040_ = _039_ ? 1'h1 : 1'h0;
- assign _041_ = $signed(32'd15) < $signed({ 27'h0000000, r[308:304] });
- assign _042_ = _041_ ? 1'h1 : 1'h0;
- assign _043_ = $signed(32'd0) < $signed({ 26'h0000000, r[303:298] });
- assign _044_ = _043_ ? 1'h1 : 1'h0;
- assign _045_ = $signed(32'd1) < $signed({ 26'h0000000, r[303:298] });
- assign _046_ = _045_ ? 1'h1 : 1'h0;
- assign _047_ = $signed(32'd2) < $signed({ 26'h0000000, r[303:298] });
- assign _048_ = _047_ ? 1'h1 : 1'h0;
- assign _049_ = $signed(32'd3) < $signed({ 26'h0000000, r[303:298] });
- assign _050_ = _049_ ? 1'h1 : 1'h0;
- assign _051_ = $signed(32'd4) < $signed({ 26'h0000000, r[303:298] });
- assign _052_ = _051_ ? 1'h1 : 1'h0;
- assign _053_ = $signed(32'd5) < $signed({ 26'h0000000, r[303:298] });
- assign _054_ = _053_ ? 1'h1 : 1'h0;
- assign l_out = { _000_, r[433:429], _282_ };
- assign d_out = { _304_, _305_, _283_, _286_, _285_, _281_ };
- assign i_out = { _304_, _305_, _286_, _285_, _284_ };
-endmodule
-
-module multiply_16(clk, m_in, m_out);
- wire [129:0] _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- wire _08_;
- wire _09_;
- wire _10_;
- wire _11_;
- wire _12_;
- wire [63:0] _13_;
- wire _14_;
- wire _15_;
- input clk;
- reg [137:0] m;
- input [137:0] m_in;
- output [65:0] m_out;
- reg [2207:0] r = 2208'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
- always @(posedge clk)
- m <= m_in;
- always @(posedge clk)
- r <= { m[137], _00_, m[6:0], r[2207:138] };
- assign _00_ = $signed({ m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71:7] }) * $signed({ m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136:72] });
- assign _01_ = | r[208:176];
- assign _02_ = & r[208:176];
- assign _03_ = ~ _02_;
- assign _04_ = _01_ & _03_;
- assign _05_ = | r[272:208];
- assign _06_ = & r[272:208];
- assign _07_ = ~ _06_;
- assign _08_ = _05_ & _07_;
- assign _09_ = r[275] ? _04_ : _08_;
- assign _10_ = r[144:139] == 6'h2b;
- assign _11_ = r[144:139] == 6'h2d;
- assign _12_ = r[144:139] == 6'h2c;
- function [63:0] \20145 ;
- input [63:0] a;
- input [191:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \20145 = b[63:0];
- 3'b?1?:
- \20145 = b[127:64];
- 3'b1??:
- \20145 = b[191:128];
- default:
- \20145 = a;
- endcase
- endfunction
- assign _13_ = \20145 (64'h0000000000000000, { r[272:177], r[208:177], r[208:145] }, { _12_, _11_, _10_ });
- function [0:0] \20147 ;
- input [0:0] a;
- input [2:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \20147 = b[0:0];
- 3'b?1?:
- \20147 = b[1:1];
- 3'b1??:
- \20147 = b[2:2];
- default:
- \20147 = a;
- endcase
- endfunction
- assign _14_ = \20147 (1'h0, { 2'h0, _09_ }, { _12_, _11_, _10_ });
- assign _15_ = r[138] ? 1'h1 : 1'h0;
- assign m_out = { _14_, _13_, _15_ };
-endmodule
-
-module plru_1(clk, rst, acc, acc_en, lru);
- wire _0_;
- wire _1_;
- wire _2_;
- wire [1:0] _3_;
- wire [1:0] _4_;
- wire _5_;
- wire _6_;
- wire _7_;
- wire _8_;
- input acc;
- input acc_en;
- input clk;
- output lru;
- input rst;
- reg [1:0] tree;
- assign _0_ = 1'h1 - 1'h0;
- assign _1_ = 1'h1 - 1'h0;
- assign _2_ = ~ acc;
- assign _3_ = acc_en ? { _8_, _7_ } : tree;
- assign _4_ = rst ? 2'h0 : _3_;
- always @(posedge clk)
- tree <= _4_;
- assign _5_ = _0_ ? tree[1] : tree[0];
- assign _6_ = ~ _1_;
- assign _7_ = _6_ ? _2_ : tree[0];
- assign _8_ = _1_ ? _2_ : tree[1];
- assign lru = _5_;
-endmodule
-
-module register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, dbg_gpr_req, dbg_gpr_addr, sim_dump, d_out, dbg_gpr_ack, dbg_gpr_data, sim_dump_done);
- wire _00_;
- wire _01_;
- wire _02_;
- reg _03_ = 1'h1;
- wire _04_;
- wire _05_;
- wire _06_;
- wire _07_;
- wire [5:0] _08_;
- wire _09_;
- wire [63:0] _10_;
- wire _11_;
- wire [63:0] _12_;
- wire _13_;
- wire [63:0] _14_;
- wire [191:0] _15_;
- wire _16_;
- wire _17_;
- wire _18_;
- wire _19_;
- wire _20_;
- wire _21_;
- wire [63:0] _22_;
- wire [4095:0] _23_;
- wire [63:0] _24_;
- wire [4095:0] _25_;
- wire [4095:0] _26_;
- wire [63:0] _27_;
- input clk;
- input [19:0] d_in;
- output [191:0] d_out;
- reg dbg_ack;
- reg [63:0] dbg_data;
- output dbg_gpr_ack;
- input [5:0] dbg_gpr_addr;
- output [63:0] dbg_gpr_data;
- input dbg_gpr_req;
- wire [63:0] rd_port_b;
- input sim_dump;
- output sim_dump_done;
- input [70:0] w_in;
- reg [63:0] \$mem$\4359 [63:0];
- assign _00_ = ~ _02_;
- assign _01_ = _00_ | 1'h1;
- assign _02_ = w_in[70] ? 1'h1 : 1'h0;
- always @(posedge clk)
- _03_ <= _01_;
- assign _04_ = ~ d_in[7];
- assign _05_ = _04_ & dbg_gpr_req;
- assign _06_ = ~ dbg_ack;
- assign _07_ = _05_ & _06_;
- assign _08_ = _07_ ? dbg_gpr_addr : d_in[13:8];
- assign _09_ = d_in[6:1] == w_in[5:0];
- assign _10_ = _09_ ? w_in[69:6] : _27_;
- assign _11_ = d_in[13:8] == w_in[5:0];
- assign _12_ = _11_ ? w_in[69:6] : rd_port_b;
- assign _13_ = { 1'h0, d_in[19:15] } == w_in[5:0];
- assign _14_ = _13_ ? w_in[69:6] : _24_;
- assign _15_ = w_in[70] ? { _14_, _12_, _10_ } : { _24_, rd_port_b, _27_ };
- assign _16_ = ~ d_in[7];
- assign _17_ = ~ dbg_ack;
- assign _18_ = _16_ & _17_;
- assign _19_ = _18_ ? 1'h1 : dbg_ack;
- assign _20_ = dbg_gpr_req & _18_;
- assign _21_ = dbg_gpr_req ? _19_ : 1'h0;
- assign _22_ = _20_ ? rd_port_b : dbg_data;
- always @(posedge clk)
- dbg_data <= _22_;
- always @(posedge clk)
- dbg_ack <= _21_;
- reg [63:0] \4359 [63:0];
- initial begin
- \4359 [0] = 64'h0000000000000000;
- \4359 [1] = 64'h0000000000000000;
- \4359 [2] = 64'h0000000000000000;
- \4359 [3] = 64'h0000000000000000;
- \4359 [4] = 64'h0000000000000000;
- \4359 [5] = 64'h0000000000000000;
- \4359 [6] = 64'h0000000000000000;
- \4359 [7] = 64'h0000000000000000;
- \4359 [8] = 64'h0000000000000000;
- \4359 [9] = 64'h0000000000000000;
- \4359 [10] = 64'h0000000000000000;
- \4359 [11] = 64'h0000000000000000;
- \4359 [12] = 64'h0000000000000000;
- \4359 [13] = 64'h0000000000000000;
- \4359 [14] = 64'h0000000000000000;
- \4359 [15] = 64'h0000000000000000;
- \4359 [16] = 64'h0000000000000000;
- \4359 [17] = 64'h0000000000000000;
- \4359 [18] = 64'h0000000000000000;
- \4359 [19] = 64'h0000000000000000;
- \4359 [20] = 64'h0000000000000000;
- \4359 [21] = 64'h0000000000000000;
- \4359 [22] = 64'h0000000000000000;
- \4359 [23] = 64'h0000000000000000;
- \4359 [24] = 64'h0000000000000000;
- \4359 [25] = 64'h0000000000000000;
- \4359 [26] = 64'h0000000000000000;
- \4359 [27] = 64'h0000000000000000;
- \4359 [28] = 64'h0000000000000000;
- \4359 [29] = 64'h0000000000000000;
- \4359 [30] = 64'h0000000000000000;
- \4359 [31] = 64'h0000000000000000;
- \4359 [32] = 64'h0000000000000000;
- \4359 [33] = 64'h0000000000000000;
- \4359 [34] = 64'h0000000000000000;
- \4359 [35] = 64'h0000000000000000;
- \4359 [36] = 64'h0000000000000000;
- \4359 [37] = 64'h0000000000000000;
- \4359 [38] = 64'h0000000000000000;
- \4359 [39] = 64'h0000000000000000;
- \4359 [40] = 64'h0000000000000000;
- \4359 [41] = 64'h0000000000000000;
- \4359 [42] = 64'h0000000000000000;
- \4359 [43] = 64'h0000000000000000;
- \4359 [44] = 64'h0000000000000000;
- \4359 [45] = 64'h0000000000000000;
- \4359 [46] = 64'h0000000000000000;
- \4359 [47] = 64'h0000000000000000;
- \4359 [48] = 64'h0000000000000000;
- \4359 [49] = 64'h0000000000000000;
- \4359 [50] = 64'h0000000000000000;
- \4359 [51] = 64'h0000000000000000;
- \4359 [52] = 64'h0000000000000000;
- \4359 [53] = 64'h0000000000000000;
- \4359 [54] = 64'h0000000000000000;
- \4359 [55] = 64'h0000000000000000;
- \4359 [56] = 64'h0000000000000000;
- \4359 [57] = 64'h0000000000000000;
- \4359 [58] = 64'h0000000000000000;
- \4359 [59] = 64'h0000000000000000;
- \4359 [60] = 64'h0000000000000000;
- \4359 [61] = 64'h0000000000000000;
- \4359 [62] = 64'h0000000000000000;
- \4359 [63] = 64'h0000000000000000;
- end
- always @(posedge clk) begin
- if (w_in[70]) \4359 [w_in[5:0]] <= w_in[69:6];
- end
- assign _24_ = \4359 [{ 1'h0, d_in[19:15] }];
- assign rd_port_b = \4359 [_08_];
- assign _27_ = \4359 [d_in[6:1]];
- assign d_out = _15_;
- assign dbg_gpr_ack = dbg_ack;
- assign dbg_gpr_data = dbg_data;
- assign sim_dump_done = 1'h0;
-endmodule
-
-module rotator(rs, ra, shift, insn, is_32bit, right_shift, arith, clear_left, clear_right, sign_ext_rs, result, carry_out);
- wire [31:0] _000_;
- wire [31:0] _001_;
- wire [5:0] _002_;
- wire _003_;
- wire _004_;
- wire _005_;
- wire _006_;
- wire _007_;
- wire _008_;
- wire _009_;
- wire _010_;
- wire _011_;
- wire _012_;
- wire _013_;
- wire [6:0] _014_;
- wire _015_;
- wire [6:0] _016_;
- wire [6:0] _017_;
- wire _018_;
- wire _019_;
- wire _020_;
- wire [5:0] _021_;
- wire [6:0] _022_;
- wire _023_;
- wire _024_;
- wire _025_;
- wire _026_;
- wire _027_;
- wire _028_;
- wire _029_;
- wire _030_;
- wire _031_;
- wire _032_;
- wire _033_;
- wire _034_;
- wire _035_;
- wire _036_;
- wire _037_;
- wire _038_;
- wire _039_;
- wire _040_;
- wire _041_;
- wire _042_;
- wire _043_;
- wire _044_;
- wire _045_;
- wire _046_;
- wire _047_;
- wire _048_;
- wire _049_;
- wire _050_;
- wire _051_;
- wire _052_;
- wire _053_;
- wire _054_;
- wire _055_;
- wire _056_;
- wire _057_;
- wire _058_;
- wire _059_;
- wire _060_;
- wire _061_;
- wire _062_;
- wire _063_;
- wire _064_;
- wire _065_;
- wire _066_;
- wire _067_;
- wire _068_;
- wire _069_;
- wire _070_;
- wire _071_;
- wire _072_;
- wire _073_;
- wire _074_;
- wire _075_;
- wire _076_;
- wire _077_;
- wire _078_;
- wire _079_;
- wire _080_;
- wire _081_;
- wire _082_;
- wire _083_;
- wire _084_;
- wire _085_;
- wire _086_;
- wire _087_;
- wire _088_;
- wire _089_;
- wire _090_;
- wire _091_;
- wire _092_;
- wire _093_;
- wire _094_;
- wire _095_;
- wire _096_;
- wire _097_;
- wire _098_;
- wire _099_;
- wire _100_;
- wire _101_;
- wire _102_;
- wire _103_;
- wire _104_;
- wire _105_;
- wire _106_;
- wire _107_;
- wire _108_;
- wire _109_;
- wire _110_;
- wire _111_;
- wire _112_;
- wire _113_;
- wire _114_;
- wire _115_;
- wire _116_;
- wire _117_;
- wire _118_;
- wire _119_;
- wire _120_;
- wire _121_;
- wire _122_;
- wire _123_;
- wire _124_;
- wire _125_;
- wire _126_;
- wire _127_;
- wire _128_;
- wire _129_;
- wire _130_;
- wire _131_;
- wire _132_;
- wire _133_;
- wire _134_;
- wire _135_;
- wire _136_;
- wire _137_;
- wire _138_;
- wire _139_;
- wire _140_;
- wire _141_;
- wire _142_;
- wire _143_;
- wire _144_;
- wire _145_;
- wire _146_;
- wire _147_;
- wire _148_;
- wire _149_;
- wire _150_;
- wire _151_;
- wire _152_;
- wire _153_;
- wire _154_;
- wire _155_;
- wire _156_;
- wire _157_;
- wire _158_;
- wire _159_;
- wire _160_;
- wire _161_;
- wire _162_;
- wire _163_;
- wire _164_;
- wire _165_;
- wire _166_;
- wire _167_;
- wire _168_;
- wire _169_;
- wire _170_;
- wire _171_;
- wire _172_;
- wire _173_;
- wire _174_;
- wire _175_;
- wire _176_;
- wire _177_;
- wire _178_;
- wire _179_;
- wire _180_;
- wire _181_;
- wire _182_;
- wire _183_;
- wire _184_;
- wire _185_;
- wire _186_;
- wire _187_;
- wire _188_;
- wire _189_;
- wire _190_;
- wire _191_;
- wire _192_;
- wire _193_;
- wire _194_;
- wire _195_;
- wire _196_;
- wire _197_;
- wire _198_;
- wire _199_;
- wire _200_;
- wire _201_;
- wire _202_;
- wire _203_;
- wire _204_;
- wire _205_;
- wire _206_;
- wire _207_;
- wire _208_;
- wire _209_;
- wire _210_;
- wire _211_;
- wire _212_;
- wire _213_;
- wire _214_;
- wire _215_;
- wire _216_;
- wire _217_;
- wire _218_;
- wire _219_;
- wire _220_;
- wire _221_;
- wire _222_;
- wire _223_;
- wire _224_;
- wire _225_;
- wire _226_;
- wire _227_;
- wire _228_;
- wire _229_;
- wire _230_;
- wire _231_;
- wire _232_;
- wire _233_;
- wire _234_;
- wire _235_;
- wire _236_;
- wire _237_;
- wire _238_;
- wire _239_;
- wire _240_;
- wire _241_;
- wire _242_;
- wire _243_;
- wire _244_;
- wire _245_;
- wire _246_;
- wire _247_;
- wire _248_;
- wire _249_;
- wire _250_;
- wire _251_;
- wire _252_;
- wire _253_;
- wire _254_;
- wire _255_;
- wire _256_;
- wire _257_;
- wire _258_;
- wire _259_;
- wire _260_;
- wire _261_;
- wire _262_;
- wire _263_;
- wire _264_;
- wire _265_;
- wire _266_;
- wire _267_;
- wire _268_;
- wire _269_;
- wire _270_;
- wire _271_;
- wire _272_;
- wire _273_;
- wire _274_;
- wire _275_;
- wire _276_;
- wire _277_;
- wire _278_;
- wire _279_;
- wire _280_;
- wire _281_;
- wire _282_;
- wire _283_;
- wire _284_;
- wire _285_;
- wire _286_;
- wire [63:0] _287_;
- wire [63:0] _288_;
- wire [63:0] _289_;
- wire [63:0] _290_;
- wire [63:0] _291_;
- wire [63:0] _292_;
- wire _293_;
- wire [63:0] _294_;
- wire [63:0] _295_;
- wire [63:0] _296_;
- wire [63:0] _297_;
- wire [63:0] _298_;
- wire [63:0] _299_;
- wire _300_;
- wire [63:0] _301_;
- wire _302_;
- wire [63:0] _303_;
- wire [63:0] _304_;
- wire [63:0] _305_;
- wire _306_;
- wire [63:0] _307_;
- wire [63:0] _308_;
- wire _309_;
- wire _310_;
- input arith;
- output carry_out;
- input clear_left;
- input clear_right;
- input [31:0] insn;
- input is_32bit;
- wire [6:0] mb;
- wire [6:0] me;
- wire [63:0] ml;
- wire [1:0] output_mode;
- input [63:0] ra;
- output [63:0] result;
- input right_shift;
- wire [63:0] rot;
- wire [63:0] rot1;
- wire [63:0] rot2;
- wire [5:0] rot_count;
- input [63:0] rs;
- input [6:0] shift;
- input sign_ext_rs;
- assign _000_ = sign_ext_rs ? { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] } : rs[63:32];
- assign _001_ = is_32bit ? rs[31:0] : _000_;
- assign _002_ = - $signed(shift[5:0]);
- assign rot_count = right_shift ? _002_ : shift[5:0];
- assign _003_ = rot_count[1:0] == 2'h0;
- assign _004_ = rot_count[1:0] == 2'h1;
- assign _005_ = rot_count[1:0] == 2'h2;
- function [63:0] \18205 ;
- input [63:0] a;
- input [191:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \18205 = b[63:0];
- 3'b?1?:
- \18205 = b[127:64];
- 3'b1??:
- \18205 = b[191:128];
- default:
- \18205 = a;
- endcase
- endfunction
- assign rot1 = \18205 ({ _001_[28:0], rs[31:0], _001_[31:29] }, { _001_[29:0], rs[31:0], _001_[31:30], _001_[30:0], rs[31:0], _001_[31], _001_, rs[31:0] }, { _005_, _004_, _003_ });
- assign _006_ = rot_count[3:2] == 2'h0;
- assign _007_ = rot_count[3:2] == 2'h1;
- assign _008_ = rot_count[3:2] == 2'h2;
- function [63:0] \18223 ;
- input [63:0] a;
- input [191:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \18223 = b[63:0];
- 3'b?1?:
- \18223 = b[127:64];
- 3'b1??:
- \18223 = b[191:128];
- default:
- \18223 = a;
- endcase
- endfunction
- assign rot2 = \18223 ({ rot1[51:0], rot1[63:52] }, { rot1[55:0], rot1[63:56], rot1[59:0], rot1[63:60], rot1 }, { _008_, _007_, _006_ });
- assign _009_ = rot_count[5:4] == 2'h0;
- assign _010_ = rot_count[5:4] == 2'h1;
- assign _011_ = rot_count[5:4] == 2'h2;
- function [63:0] \18241 ;
- input [63:0] a;
- input [191:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \18241 = b[63:0];
- 3'b?1?:
- \18241 = b[127:64];
- 3'b1??:
- \18241 = b[191:128];
- default:
- \18241 = a;
- endcase
- endfunction
- assign rot = \18241 ({ rot2[15:0], rot2[63:16] }, { rot2[31:0], rot2[63:32], rot2[47:0], rot2[63:48], rot2 }, { _011_, _010_, _009_ });
- assign _012_ = ~ is_32bit;
- assign _013_ = shift[6] & _012_;
- assign _014_ = is_32bit ? { 2'h1, insn[10:6] } : { 1'h0, insn[5], insn[10:6] };
- assign _015_ = ~ shift[5];
- assign _016_ = is_32bit ? { shift[5], _015_, shift[4:0] } : { _013_, shift[5:0] };
- assign _017_ = right_shift ? _016_ : { 1'h0, is_32bit, 5'h00 };
- assign mb = clear_left ? _014_ : _017_;
- assign _018_ = clear_right & is_32bit;
- assign _019_ = ~ clear_left;
- assign _020_ = clear_right & _019_;
- assign _021_ = ~ shift[5:0];
- assign _022_ = _020_ ? { 1'h0, insn[5], insn[10:6] } : { _013_, _021_ };
- assign me = _018_ ? { 2'h1, insn[5:1] } : _022_;
- assign _023_ = $signed(32'd0) >= $signed({ 25'h0000000, mb });
- assign _024_ = _023_ ? 1'h1 : 1'h0;
- assign _025_ = $signed(32'd1) >= $signed({ 25'h0000000, mb });
- assign _026_ = _025_ ? 1'h1 : 1'h0;
- assign _027_ = $signed(32'd2) >= $signed({ 25'h0000000, mb });
- assign _028_ = _027_ ? 1'h1 : 1'h0;
- assign _029_ = $signed(32'd3) >= $signed({ 25'h0000000, mb });
- assign _030_ = _029_ ? 1'h1 : 1'h0;
- assign _031_ = $signed(32'd4) >= $signed({ 25'h0000000, mb });
- assign _032_ = _031_ ? 1'h1 : 1'h0;
- assign _033_ = $signed(32'd5) >= $signed({ 25'h0000000, mb });
- assign _034_ = _033_ ? 1'h1 : 1'h0;
- assign _035_ = $signed(32'd6) >= $signed({ 25'h0000000, mb });
- assign _036_ = _035_ ? 1'h1 : 1'h0;
- assign _037_ = $signed(32'd7) >= $signed({ 25'h0000000, mb });
- assign _038_ = _037_ ? 1'h1 : 1'h0;
- assign _039_ = $signed(32'd8) >= $signed({ 25'h0000000, mb });
- assign _040_ = _039_ ? 1'h1 : 1'h0;
- assign _041_ = $signed(32'd9) >= $signed({ 25'h0000000, mb });
- assign _042_ = _041_ ? 1'h1 : 1'h0;
- assign _043_ = $signed(32'd10) >= $signed({ 25'h0000000, mb });
- assign _044_ = _043_ ? 1'h1 : 1'h0;
- assign _045_ = $signed(32'd11) >= $signed({ 25'h0000000, mb });
- assign _046_ = _045_ ? 1'h1 : 1'h0;
- assign _047_ = $signed(32'd12) >= $signed({ 25'h0000000, mb });
- assign _048_ = _047_ ? 1'h1 : 1'h0;
- assign _049_ = $signed(32'd13) >= $signed({ 25'h0000000, mb });
- assign _050_ = _049_ ? 1'h1 : 1'h0;
- assign _051_ = $signed(32'd14) >= $signed({ 25'h0000000, mb });
- assign _052_ = _051_ ? 1'h1 : 1'h0;
- assign _053_ = $signed(32'd15) >= $signed({ 25'h0000000, mb });
- assign _054_ = _053_ ? 1'h1 : 1'h0;
- assign _055_ = $signed(32'd16) >= $signed({ 25'h0000000, mb });
- assign _056_ = _055_ ? 1'h1 : 1'h0;
- assign _057_ = $signed(32'd17) >= $signed({ 25'h0000000, mb });
- assign _058_ = _057_ ? 1'h1 : 1'h0;
- assign _059_ = $signed(32'd18) >= $signed({ 25'h0000000, mb });
- assign _060_ = _059_ ? 1'h1 : 1'h0;
- assign _061_ = $signed(32'd19) >= $signed({ 25'h0000000, mb });
- assign _062_ = _061_ ? 1'h1 : 1'h0;
- assign _063_ = $signed(32'd20) >= $signed({ 25'h0000000, mb });
- assign _064_ = _063_ ? 1'h1 : 1'h0;
- assign _065_ = $signed(32'd21) >= $signed({ 25'h0000000, mb });
- assign _066_ = _065_ ? 1'h1 : 1'h0;
- assign _067_ = $signed(32'd22) >= $signed({ 25'h0000000, mb });
- assign _068_ = _067_ ? 1'h1 : 1'h0;
- assign _069_ = $signed(32'd23) >= $signed({ 25'h0000000, mb });
- assign _070_ = _069_ ? 1'h1 : 1'h0;
- assign _071_ = $signed(32'd24) >= $signed({ 25'h0000000, mb });
- assign _072_ = _071_ ? 1'h1 : 1'h0;
- assign _073_ = $signed(32'd25) >= $signed({ 25'h0000000, mb });
- assign _074_ = _073_ ? 1'h1 : 1'h0;
- assign _075_ = $signed(32'd26) >= $signed({ 25'h0000000, mb });
- assign _076_ = _075_ ? 1'h1 : 1'h0;
- assign _077_ = $signed(32'd27) >= $signed({ 25'h0000000, mb });
- assign _078_ = _077_ ? 1'h1 : 1'h0;
- assign _079_ = $signed(32'd28) >= $signed({ 25'h0000000, mb });
- assign _080_ = _079_ ? 1'h1 : 1'h0;
- assign _081_ = $signed(32'd29) >= $signed({ 25'h0000000, mb });
- assign _082_ = _081_ ? 1'h1 : 1'h0;
- assign _083_ = $signed(32'd30) >= $signed({ 25'h0000000, mb });
- assign _084_ = _083_ ? 1'h1 : 1'h0;
- assign _085_ = $signed(32'd31) >= $signed({ 25'h0000000, mb });
- assign _086_ = _085_ ? 1'h1 : 1'h0;
- assign _087_ = $signed(32'd32) >= $signed({ 25'h0000000, mb });
- assign _088_ = _087_ ? 1'h1 : 1'h0;
- assign _089_ = $signed(32'd33) >= $signed({ 25'h0000000, mb });
- assign _090_ = _089_ ? 1'h1 : 1'h0;
- assign _091_ = $signed(32'd34) >= $signed({ 25'h0000000, mb });
- assign _092_ = _091_ ? 1'h1 : 1'h0;
- assign _093_ = $signed(32'd35) >= $signed({ 25'h0000000, mb });
- assign _094_ = _093_ ? 1'h1 : 1'h0;
- assign _095_ = $signed(32'd36) >= $signed({ 25'h0000000, mb });
- assign _096_ = _095_ ? 1'h1 : 1'h0;
- assign _097_ = $signed(32'd37) >= $signed({ 25'h0000000, mb });
- assign _098_ = _097_ ? 1'h1 : 1'h0;
- assign _099_ = $signed(32'd38) >= $signed({ 25'h0000000, mb });
- assign _100_ = _099_ ? 1'h1 : 1'h0;
- assign _101_ = $signed(32'd39) >= $signed({ 25'h0000000, mb });
- assign _102_ = _101_ ? 1'h1 : 1'h0;
- assign _103_ = $signed(32'd40) >= $signed({ 25'h0000000, mb });
- assign _104_ = _103_ ? 1'h1 : 1'h0;
- assign _105_ = $signed(32'd41) >= $signed({ 25'h0000000, mb });
- assign _106_ = _105_ ? 1'h1 : 1'h0;
- assign _107_ = $signed(32'd42) >= $signed({ 25'h0000000, mb });
- assign _108_ = _107_ ? 1'h1 : 1'h0;
- assign _109_ = $signed(32'd43) >= $signed({ 25'h0000000, mb });
- assign _110_ = _109_ ? 1'h1 : 1'h0;
- assign _111_ = $signed(32'd44) >= $signed({ 25'h0000000, mb });
- assign _112_ = _111_ ? 1'h1 : 1'h0;
- assign _113_ = $signed(32'd45) >= $signed({ 25'h0000000, mb });
- assign _114_ = _113_ ? 1'h1 : 1'h0;
- assign _115_ = $signed(32'd46) >= $signed({ 25'h0000000, mb });
- assign _116_ = _115_ ? 1'h1 : 1'h0;
- assign _117_ = $signed(32'd47) >= $signed({ 25'h0000000, mb });
- assign _118_ = _117_ ? 1'h1 : 1'h0;
- assign _119_ = $signed(32'd48) >= $signed({ 25'h0000000, mb });
- assign _120_ = _119_ ? 1'h1 : 1'h0;
- assign _121_ = $signed(32'd49) >= $signed({ 25'h0000000, mb });
- assign _122_ = _121_ ? 1'h1 : 1'h0;
- assign _123_ = $signed(32'd50) >= $signed({ 25'h0000000, mb });
- assign _124_ = _123_ ? 1'h1 : 1'h0;
- assign _125_ = $signed(32'd51) >= $signed({ 25'h0000000, mb });
- assign _126_ = _125_ ? 1'h1 : 1'h0;
- assign _127_ = $signed(32'd52) >= $signed({ 25'h0000000, mb });
- assign _128_ = _127_ ? 1'h1 : 1'h0;
- assign _129_ = $signed(32'd53) >= $signed({ 25'h0000000, mb });
- assign _130_ = _129_ ? 1'h1 : 1'h0;
- assign _131_ = $signed(32'd54) >= $signed({ 25'h0000000, mb });
- assign _132_ = _131_ ? 1'h1 : 1'h0;
- assign _133_ = $signed(32'd55) >= $signed({ 25'h0000000, mb });
- assign _134_ = _133_ ? 1'h1 : 1'h0;
- assign _135_ = $signed(32'd56) >= $signed({ 25'h0000000, mb });
- assign _136_ = _135_ ? 1'h1 : 1'h0;
- assign _137_ = $signed(32'd57) >= $signed({ 25'h0000000, mb });
- assign _138_ = _137_ ? 1'h1 : 1'h0;
- assign _139_ = $signed(32'd58) >= $signed({ 25'h0000000, mb });
- assign _140_ = _139_ ? 1'h1 : 1'h0;
- assign _141_ = $signed(32'd59) >= $signed({ 25'h0000000, mb });
- assign _142_ = _141_ ? 1'h1 : 1'h0;
- assign _143_ = $signed(32'd60) >= $signed({ 25'h0000000, mb });
- assign _144_ = _143_ ? 1'h1 : 1'h0;
- assign _145_ = $signed(32'd61) >= $signed({ 25'h0000000, mb });
- assign _146_ = _145_ ? 1'h1 : 1'h0;
- assign _147_ = $signed(32'd62) >= $signed({ 25'h0000000, mb });
- assign _148_ = _147_ ? 1'h1 : 1'h0;
- assign _149_ = $signed(32'd63) >= $signed({ 25'h0000000, mb });
- assign _150_ = _149_ ? 1'h1 : 1'h0;
- assign _151_ = ~ me[6];
- assign _152_ = $signed(32'd0) <= $signed({ 25'h0000000, me });
- assign _153_ = _152_ ? 1'h1 : 1'h0;
- assign _154_ = $signed(32'd1) <= $signed({ 25'h0000000, me });
- assign _155_ = _154_ ? 1'h1 : 1'h0;
- assign _156_ = $signed(32'd2) <= $signed({ 25'h0000000, me });
- assign _157_ = _156_ ? 1'h1 : 1'h0;
- assign _158_ = $signed(32'd3) <= $signed({ 25'h0000000, me });
- assign _159_ = _158_ ? 1'h1 : 1'h0;
- assign _160_ = $signed(32'd4) <= $signed({ 25'h0000000, me });
- assign _161_ = _160_ ? 1'h1 : 1'h0;
- assign _162_ = $signed(32'd5) <= $signed({ 25'h0000000, me });
- assign _163_ = _162_ ? 1'h1 : 1'h0;
- assign _164_ = $signed(32'd6) <= $signed({ 25'h0000000, me });
- assign _165_ = _164_ ? 1'h1 : 1'h0;
- assign _166_ = $signed(32'd7) <= $signed({ 25'h0000000, me });
- assign _167_ = _166_ ? 1'h1 : 1'h0;
- assign _168_ = $signed(32'd8) <= $signed({ 25'h0000000, me });
- assign _169_ = _168_ ? 1'h1 : 1'h0;
- assign _170_ = $signed(32'd9) <= $signed({ 25'h0000000, me });
- assign _171_ = _170_ ? 1'h1 : 1'h0;
- assign _172_ = $signed(32'd10) <= $signed({ 25'h0000000, me });
- assign _173_ = _172_ ? 1'h1 : 1'h0;
- assign _174_ = $signed(32'd11) <= $signed({ 25'h0000000, me });
- assign _175_ = _174_ ? 1'h1 : 1'h0;
- assign _176_ = $signed(32'd12) <= $signed({ 25'h0000000, me });
- assign _177_ = _176_ ? 1'h1 : 1'h0;
- assign _178_ = $signed(32'd13) <= $signed({ 25'h0000000, me });
- assign _179_ = _178_ ? 1'h1 : 1'h0;
- assign _180_ = $signed(32'd14) <= $signed({ 25'h0000000, me });
- assign _181_ = _180_ ? 1'h1 : 1'h0;
- assign _182_ = $signed(32'd15) <= $signed({ 25'h0000000, me });
- assign _183_ = _182_ ? 1'h1 : 1'h0;
- assign _184_ = $signed(32'd16) <= $signed({ 25'h0000000, me });
- assign _185_ = _184_ ? 1'h1 : 1'h0;
- assign _186_ = $signed(32'd17) <= $signed({ 25'h0000000, me });
- assign _187_ = _186_ ? 1'h1 : 1'h0;
- assign _188_ = $signed(32'd18) <= $signed({ 25'h0000000, me });
- assign _189_ = _188_ ? 1'h1 : 1'h0;
- assign _190_ = $signed(32'd19) <= $signed({ 25'h0000000, me });
- assign _191_ = _190_ ? 1'h1 : 1'h0;
- assign _192_ = $signed(32'd20) <= $signed({ 25'h0000000, me });
- assign _193_ = _192_ ? 1'h1 : 1'h0;
- assign _194_ = $signed(32'd21) <= $signed({ 25'h0000000, me });
- assign _195_ = _194_ ? 1'h1 : 1'h0;
- assign _196_ = $signed(32'd22) <= $signed({ 25'h0000000, me });
- assign _197_ = _196_ ? 1'h1 : 1'h0;
- assign _198_ = $signed(32'd23) <= $signed({ 25'h0000000, me });
- assign _199_ = _198_ ? 1'h1 : 1'h0;
- assign _200_ = $signed(32'd24) <= $signed({ 25'h0000000, me });
- assign _201_ = _200_ ? 1'h1 : 1'h0;
- assign _202_ = $signed(32'd25) <= $signed({ 25'h0000000, me });
- assign _203_ = _202_ ? 1'h1 : 1'h0;
- assign _204_ = $signed(32'd26) <= $signed({ 25'h0000000, me });
- assign _205_ = _204_ ? 1'h1 : 1'h0;
- assign _206_ = $signed(32'd27) <= $signed({ 25'h0000000, me });
- assign _207_ = _206_ ? 1'h1 : 1'h0;
- assign _208_ = $signed(32'd28) <= $signed({ 25'h0000000, me });
- assign _209_ = _208_ ? 1'h1 : 1'h0;
- assign _210_ = $signed(32'd29) <= $signed({ 25'h0000000, me });
- assign _211_ = _210_ ? 1'h1 : 1'h0;
- assign _212_ = $signed(32'd30) <= $signed({ 25'h0000000, me });
- assign _213_ = _212_ ? 1'h1 : 1'h0;
- assign _214_ = $signed(32'd31) <= $signed({ 25'h0000000, me });
- assign _215_ = _214_ ? 1'h1 : 1'h0;
- assign _216_ = $signed(32'd32) <= $signed({ 25'h0000000, me });
- assign _217_ = _216_ ? 1'h1 : 1'h0;
- assign _218_ = $signed(32'd33) <= $signed({ 25'h0000000, me });
- assign _219_ = _218_ ? 1'h1 : 1'h0;
- assign _220_ = $signed(32'd34) <= $signed({ 25'h0000000, me });
- assign _221_ = _220_ ? 1'h1 : 1'h0;
- assign _222_ = $signed(32'd35) <= $signed({ 25'h0000000, me });
- assign _223_ = _222_ ? 1'h1 : 1'h0;
- assign _224_ = $signed(32'd36) <= $signed({ 25'h0000000, me });
- assign _225_ = _224_ ? 1'h1 : 1'h0;
- assign _226_ = $signed(32'd37) <= $signed({ 25'h0000000, me });
- assign _227_ = _226_ ? 1'h1 : 1'h0;
- assign _228_ = $signed(32'd38) <= $signed({ 25'h0000000, me });
- assign _229_ = _228_ ? 1'h1 : 1'h0;
- assign _230_ = $signed(32'd39) <= $signed({ 25'h0000000, me });
- assign _231_ = _230_ ? 1'h1 : 1'h0;
- assign _232_ = $signed(32'd40) <= $signed({ 25'h0000000, me });
- assign _233_ = _232_ ? 1'h1 : 1'h0;
- assign _234_ = $signed(32'd41) <= $signed({ 25'h0000000, me });
- assign _235_ = _234_ ? 1'h1 : 1'h0;
- assign _236_ = $signed(32'd42) <= $signed({ 25'h0000000, me });
- assign _237_ = _236_ ? 1'h1 : 1'h0;
- assign _238_ = $signed(32'd43) <= $signed({ 25'h0000000, me });
- assign _239_ = _238_ ? 1'h1 : 1'h0;
- assign _240_ = $signed(32'd44) <= $signed({ 25'h0000000, me });
- assign _241_ = _240_ ? 1'h1 : 1'h0;
- assign _242_ = $signed(32'd45) <= $signed({ 25'h0000000, me });
- assign _243_ = _242_ ? 1'h1 : 1'h0;
- assign _244_ = $signed(32'd46) <= $signed({ 25'h0000000, me });
- assign _245_ = _244_ ? 1'h1 : 1'h0;
- assign _246_ = $signed(32'd47) <= $signed({ 25'h0000000, me });
- assign _247_ = _246_ ? 1'h1 : 1'h0;
- assign _248_ = $signed(32'd48) <= $signed({ 25'h0000000, me });
- assign _249_ = _248_ ? 1'h1 : 1'h0;
- assign _250_ = $signed(32'd49) <= $signed({ 25'h0000000, me });
- assign _251_ = _250_ ? 1'h1 : 1'h0;
- assign _252_ = $signed(32'd50) <= $signed({ 25'h0000000, me });
- assign _253_ = _252_ ? 1'h1 : 1'h0;
- assign _254_ = $signed(32'd51) <= $signed({ 25'h0000000, me });
- assign _255_ = _254_ ? 1'h1 : 1'h0;
- assign _256_ = $signed(32'd52) <= $signed({ 25'h0000000, me });
- assign _257_ = _256_ ? 1'h1 : 1'h0;
- assign _258_ = $signed(32'd53) <= $signed({ 25'h0000000, me });
- assign _259_ = _258_ ? 1'h1 : 1'h0;
- assign _260_ = $signed(32'd54) <= $signed({ 25'h0000000, me });
- assign _261_ = _260_ ? 1'h1 : 1'h0;
- assign _262_ = $signed(32'd55) <= $signed({ 25'h0000000, me });
- assign _263_ = _262_ ? 1'h1 : 1'h0;
- assign _264_ = $signed(32'd56) <= $signed({ 25'h0000000, me });
- assign _265_ = _264_ ? 1'h1 : 1'h0;
- assign _266_ = $signed(32'd57) <= $signed({ 25'h0000000, me });
- assign _267_ = _266_ ? 1'h1 : 1'h0;
- assign _268_ = $signed(32'd58) <= $signed({ 25'h0000000, me });
- assign _269_ = _268_ ? 1'h1 : 1'h0;
- assign _270_ = $signed(32'd59) <= $signed({ 25'h0000000, me });
- assign _271_ = _270_ ? 1'h1 : 1'h0;
- assign _272_ = $signed(32'd60) <= $signed({ 25'h0000000, me });
- assign _273_ = _272_ ? 1'h1 : 1'h0;
- assign _274_ = $signed(32'd61) <= $signed({ 25'h0000000, me });
- assign _275_ = _274_ ? 1'h1 : 1'h0;
- assign _276_ = $signed(32'd62) <= $signed({ 25'h0000000, me });
- assign _277_ = _276_ ? 1'h1 : 1'h0;
- assign _278_ = $signed(32'd63) <= $signed({ 25'h0000000, me });
- assign _279_ = _278_ ? 1'h1 : 1'h0;
- assign ml = _151_ ? { _153_, _155_, _157_, _159_, _161_, _163_, _165_, _167_, _169_, _171_, _173_, _175_, _177_, _179_, _181_, _183_, _185_, _187_, _189_, _191_, _193_, _195_, _197_, _199_, _201_, _203_, _205_, _207_, _209_, _211_, _213_, _215_, _217_, _219_, _221_, _223_, _225_, _227_, _229_, _231_, _233_, _235_, _237_, _239_, _241_, _243_, _245_, _247_, _249_, _251_, _253_, _255_, _257_, _259_, _261_, _263_, _265_, _267_, _269_, _271_, _273_, _275_, _277_, _279_ } : 64'h0000000000000000;
- assign _280_ = ~ clear_right;
- assign _281_ = clear_left & _280_;
- assign _282_ = _281_ | right_shift;
- assign _283_ = arith & _001_[31];
- assign _284_ = mb[5:0] > me[5:0];
- assign _285_ = clear_right & _284_;
- assign _286_ = _285_ ? 1'h1 : 1'h0;
- assign output_mode = _282_ ? { 1'h1, _283_ } : { 1'h0, _286_ };
- assign _287_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
- assign _288_ = rot & _287_;
- assign _289_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
- assign _290_ = ~ _289_;
- assign _291_ = ra & _290_;
- assign _292_ = _288_ | _291_;
- assign _293_ = output_mode == 2'h0;
- assign _294_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
- assign _295_ = rot & _294_;
- assign _296_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
- assign _297_ = ~ _296_;
- assign _298_ = ra & _297_;
- assign _299_ = _295_ | _298_;
- assign _300_ = output_mode == 2'h1;
- assign _301_ = rot & { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
- assign _302_ = output_mode == 2'h2;
- assign _303_ = ~ { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
- assign _304_ = rot | _303_;
- function [63:0] \19303 ;
- input [63:0] a;
- input [191:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \19303 = b[63:0];
- 3'b?1?:
- \19303 = b[127:64];
- 3'b1??:
- \19303 = b[191:128];
- default:
- \19303 = a;
- endcase
- endfunction
- assign _305_ = \19303 (_304_, { _301_, _299_, _292_ }, { _302_, _300_, _293_ });
- assign _306_ = output_mode == 2'h3;
- assign _307_ = ~ ml;
- assign _308_ = rs & _307_;
- assign _309_ = | _308_;
- assign _310_ = _306_ ? _309_ : 1'h0;
- assign result = _305_;
- assign carry_out = _310_;
-endmodule
-
-module writeback(clk, e_in, l_in, w_out, c_out, complete_out);
- wire [31:0] _00_;
- wire _01_;
- wire _02_;
- wire [31:0] _03_;
- wire _04_;
- wire _05_;
- wire [31:0] _06_;
- wire _07_;
- wire _08_;
- wire _09_;
- wire [70:0] _10_;
- wire [40:0] _11_;
- wire [5:0] _12_;
- wire [70:0] _13_;
- wire [8:0] _14_;
- wire [3:0] _15_;
- wire _16_;
- wire _17_;
- wire _18_;
- wire _19_;
- wire _20_;
- wire _21_;
- wire [8:0] _22_;
- wire [3:0] _23_;
- wire [70:0] _24_;
- wire [46:0] _25_;
- output [46:0] c_out;
- input clk;
- output complete_out;
- input [190:0] e_in;
- input [77:0] l_in;
- output [70:0] w_out;
- assign _00_ = { 31'h00000000, e_in[0] } + { 31'h00000000, l_in[0] };
- assign _01_ = $signed(_00_) <= $signed(32'd1);
- assign _02_ = e_in[2] | e_in[120];
- assign _03_ = { 31'h00000000, _02_ } + { 31'h00000000, l_in[1] };
- assign _04_ = $signed(_03_) <= $signed(32'd1);
- assign _05_ = e_in[2] & e_in[1];
- assign _06_ = { 31'h00000000, e_in[73] } + { 31'h00000000, _05_ };
- assign _07_ = $signed(_06_) <= $signed(32'd1);
- assign _08_ = e_in[0] | l_in[0];
- assign _09_ = _08_ ? 1'h1 : 1'h0;
- assign _10_ = e_in[2] ? { 1'h1, e_in[72:3] } : 71'h000000000000000000;
- assign _11_ = e_in[73] ? { e_in[113:74], 1'h1 } : 41'h00000000000;
- assign _12_ = e_in[114] ? { e_in[119:115], 1'h1 } : 6'h00;
- assign _13_ = l_in[1] ? { 1'h1, l_in[70:7], 1'h0, l_in[6:2] } : _10_;
- assign _14_ = l_in[76] ? 9'h101 : _11_[8:0];
- assign _15_ = l_in[76] ? { 2'h0, l_in[77], l_in[75] } : _11_[40:37];
- assign _16_ = e_in[1] & e_in[2];
- assign _17_ = | e_in[72:9];
- assign _18_ = ~ _17_;
- assign _19_ = ~ e_in[72];
- assign _20_ = ~ _18_;
- assign _21_ = _19_ & _20_;
- assign _22_ = _16_ ? 9'h101 : _14_;
- assign _23_ = _16_ ? { e_in[72], _21_, _18_, e_in[119] } : _15_;
- assign _24_ = e_in[120] ? { 1'h1, e_in[190:121] } : _13_;
- assign _25_ = e_in[120] ? 47'h000000000000 : { _12_, _23_, _11_[36:9], _22_ };
- assign w_out = _24_;
- assign c_out = _25_;
- assign complete_out = _09_;
-endmodule
-
-module zero_counter(clk, rs, count_right, is_32bit, result);
- wire _00_;
- wire _01_;
- wire _02_;
- wire _03_;
- wire _04_;
- wire _05_;
- wire [1:0] _06_;
- wire [1:0] _07_;
- wire [1:0] _08_;
- wire [1:0] _09_;
- wire [1:0] _10_;
- wire [1:0] _11_;
- wire [1:0] _12_;
- wire _13_;
- wire _14_;
- wire _15_;
- wire [1:0] _16_;
- wire _17_;
- wire _18_;
- wire _19_;
- wire [15:0] _20_;
- wire _21_;
- wire _22_;
- wire _23_;
- wire _24_;
- wire _25_;
- wire [1:0] _26_;
- wire [1:0] _27_;
- wire [1:0] _28_;
- wire [1:0] _29_;
- wire [1:0] _30_;
- wire [1:0] _31_;
- wire [1:0] _32_;
- wire _33_;
- wire _34_;
- wire _35_;
- wire [3:0] _36_;
- wire _37_;
- wire [1:0] _38_;
- wire [1:0] _39_;
- wire [1:0] _40_;
- wire [1:0] _41_;
- wire [1:0] _42_;
- wire [1:0] _43_;
- wire [1:0] _44_;
- wire _45_;
- wire _46_;
- wire _47_;
- wire _48_;
- wire _49_;
- wire _50_;
- wire [4:0] _51_;
- wire [63:0] _52_;
- wire [63:0] _53_;
- input clk;
- input count_right;
- input is_32bit;
- reg [19:0] r;
- output [63:0] result;
- input [63:0] rs;
- always @(posedge clk)
- r <= { count_right, is_32bit, _16_, _20_ };
- assign _00_ = | rs[15:0];
- assign _01_ = | rs[31:16];
- assign _02_ = | rs[47:32];
- assign _03_ = | rs[63:48];
- assign _04_ = ~ is_32bit;
- assign _05_ = ~ count_right;
- assign _06_ = _01_ ? 2'h1 : 2'h0;
- assign _07_ = _02_ ? 2'h2 : _06_;
- assign _08_ = _03_ ? 2'h3 : _07_;
- assign _09_ = _02_ ? 2'h2 : 2'h3;
- assign _10_ = _01_ ? 2'h1 : _09_;
- assign _11_ = _00_ ? 2'h0 : _10_;
- assign _12_ = _05_ ? _08_ : _11_;
- assign _13_ = ~ count_right;
- assign _14_ = ~ _00_;
- assign _15_ = _13_ ? _01_ : _14_;
- assign _16_ = _04_ ? _12_ : { 1'h0, _15_ };
- assign _17_ = _16_ == 2'h0;
- assign _18_ = _16_ == 2'h1;
- assign _19_ = _16_ == 2'h2;
- function [15:0] \19932 ;
- input [15:0] a;
- input [47:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \19932 = b[15:0];
- 3'b?1?:
- \19932 = b[31:16];
- 3'b1??:
- \19932 = b[47:32];
- default:
- \19932 = a;
- endcase
- endfunction
- assign _20_ = \19932 (rs[63:48], rs[47:0], { _19_, _18_, _17_ });
- assign _21_ = | r[3:0];
- assign _22_ = | r[7:4];
- assign _23_ = | r[11:8];
- assign _24_ = | r[15:12];
- assign _25_ = ~ r[19];
- assign _26_ = _22_ ? 2'h1 : 2'h0;
- assign _27_ = _23_ ? 2'h2 : _26_;
- assign _28_ = _24_ ? 2'h3 : _27_;
- assign _29_ = _23_ ? 2'h2 : 2'h3;
- assign _30_ = _22_ ? 2'h1 : _29_;
- assign _31_ = _21_ ? 2'h0 : _30_;
- assign _32_ = _25_ ? _28_ : _31_;
- assign _33_ = _32_ == 2'h0;
- assign _34_ = _32_ == 2'h1;
- assign _35_ = _32_ == 2'h2;
- function [3:0] \19991 ;
- input [3:0] a;
- input [11:0] b;
- input [2:0] s;
- (* parallel_case *)
- casez (s)
- 3'b??1:
- \19991 = b[3:0];
- 3'b?1?:
- \19991 = b[7:4];
- 3'b1??:
- \19991 = b[11:8];
- default:
- \19991 = a;
- endcase
- endfunction
- assign _36_ = \19991 (r[15:12], r[11:0], { _35_, _34_, _33_ });
- assign _37_ = ~ r[19];
- assign _38_ = _36_[1] ? 2'h1 : 2'h0;
- assign _39_ = _36_[2] ? 2'h2 : _38_;
- assign _40_ = _36_[3] ? 2'h3 : _39_;
- assign _41_ = _36_[2] ? 2'h2 : 2'h3;
- assign _42_ = _36_[1] ? 2'h1 : _41_;
- assign _43_ = _36_[0] ? 2'h0 : _42_;
- assign _44_ = _37_ ? _40_ : _43_;
- assign _45_ = _36_ == 4'h0;
- assign _46_ = ~ r[18];
- assign _47_ = ~ r[19];
- assign _48_ = ~ r[17];
- assign _49_ = ~ r[18];
- assign _50_ = _48_ & _49_;
- assign _51_ = ~ { r[16], _32_, _44_ };
- assign _52_ = _47_ ? { 58'h000000000000000, _50_, _51_ } : { 58'h000000000000000, r[17:16], _32_, _44_ };
- assign _53_ = _45_ ? { 57'h000000000000000, _46_, r[18], 5'h00 } : _52_;
- assign result = _53_;
-endmodule
+++ /dev/null
-#ifndef __SYSTEM_H
-#define __SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
-__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
-void flush_l2_cache(void);
-
-void busy_wait(unsigned int ms);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_H */
+++ /dev/null
-
-interface remote_bitbang
-remote_bitbang_port 44853
-remote_bitbang_host localhost
-
-# this should be irlen=4
-jtag newtap libresoc tap -irlen 4 -irmask 0xf -ircapture 0xf -expected-id 0x000018ff
-
-#set _TARGETNAME libresoc.tap
-#target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
-
-# Configure work area in on-chip SRAM
-#$_TARGETNAME.0 configure -work-area-phys 0x80000000 \
-# -work-area-size 1000 -work-area-backup 0
-
+++ /dev/null
-#!/usr/bin/env python3
-
-import os
-import argparse
-
-from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
-
-from litex.build.generic_platform import Pins, Subsignal
-from litex.build.sim import SimPlatform
-from litex.build.io import CRG
-from litex.build.sim.config import SimConfig
-
-from litex.soc.integration.soc import SoCRegion
-from litex.soc.integration.soc_core import SoCCore
-from litex.soc.integration.soc_sdram import SoCSDRAM
-from litex.soc.integration.builder import Builder
-from litex.soc.integration.common import get_mem_data
-
-from litedram import modules as litedram_modules
-from litedram.phy.model import SDRAMPHYModel
-from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
-
-from litex.tools.litex_sim import Platform
-
-from libresoc import LibreSoC
-from microwatt import Microwatt
-
-# HACK!
-from litex.soc.integration.soc import SoCCSRHandler
-SoCCSRHandler.supported_address_width.append(12)
-
-# LibreSoCSim -----------------------------------------------------------------
-
-class LibreSoCSim(SoCSDRAM):
- def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
- with_sdram=True,
- sdram_module = "AS4C16M16",
- #sdram_data_width = 16,
- #sdram_module = "MT48LC16M16",
- sdram_data_width = 16,
- irq_reserved_irqs = {'uart': 0},
- ):
- assert cpu in ["libresoc", "microwatt"]
- platform = Platform()
- sys_clk_freq = int(100e6)
-
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "hello_world/hello_world.bin"
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "tests/1.bin"
- #ram_fname = "/tmp/test.bin"
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "micropython/firmware.bin"
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "tests/xics/xics.bin"
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "tests/decrementer/decrementer.bin"
- #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- # "hello_world/hello_world.bin"
- ram_fname = None
-
- # reserve XICS ICP and XICS memory addresses.
- self.mem_map['icp'] = 0xc0004000
- self.mem_map['ics'] = 0xc0005000
- self.mem_map['gpio'] = 0xc0007000
- #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
- #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
-
- ram_init = []
- if ram_fname:
- #ram_init = get_mem_data({
- # ram_fname: "0x00000000",
- # }, "little")
- ram_init = get_mem_data(ram_fname, "little")
-
- # remap the main RAM to reset-start-address
- self.mem_map["main_ram"] = 0x00000000
-
- # without sram nothing works, therefore move it to higher up
- self.mem_map["sram"] = 0x90000000
-
- # put UART at 0xc000200 (w00t! this works!)
- self.csr_map["uart"] = 4
-
-
- # SoCCore -------------------------------------------------------------
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- cpu_type = "microwatt",
- cpu_cls = LibreSoC if cpu == "libresoc" \
- else Microwatt,
- #bus_data_width = 64,
- csr_address_width = 12, # limit to 0x4000
- cpu_variant = variant,
- csr_data_width = 8,
- l2_size = 0,
- uart_name = "sim",
- with_sdram = with_sdram,
- sdram_module = sdram_module,
- sdram_data_width = sdram_data_width,
- integrated_rom_size = 0 if ram_fname else 0x10000,
- integrated_sram_size = 0x40000,
- #integrated_main_ram_init = ram_init,
- integrated_main_ram_size = 0x00000000 if with_sdram \
- else 0x10000000 , # 256MB
- )
- self.platform.name = "sim"
-
- if cpu == "libresoc":
- # XICS interrupt devices
- icp_addr = self.mem_map['icp']
- icp_wb = self.cpu.xics_icp
- icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
- self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
-
- ics_addr = self.mem_map['ics']
- ics_wb = self.cpu.xics_ics
- ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
- self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
-
- if "gpio" in variant:
- # Simple GPIO peripheral
- gpio_addr = self.mem_map['gpio']
- gpio_wb = self.cpu.simple_gpio
- gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
- self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
-
-
- # CRG -----------------------------------------------------------------
- self.submodules.crg = CRG(platform.request("sys_clk"))
-
- #ram_init = []
-
- # SDRAM ----------------------------------------------------
- if with_sdram:
- sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
- sdram_module_cls = getattr(litedram_modules, sdram_module)
- sdram_rate = "1:{}".format(
- sdram_module_nphases[sdram_module_cls.memtype])
- sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
- phy_settings = get_sdram_phy_settings(
- memtype = sdram_module.memtype,
- data_width = sdram_data_width,
- clk_freq = sdram_clk_freq)
- self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
- phy_settings,
- init=ram_init
- )
- self.register_sdram(
- self.sdrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
- # FIXME: skip memtest to avoid corrupting memory
- self.add_constant("MEMTEST_BUS_SIZE", 128//16)
- self.add_constant("MEMTEST_DATA_SIZE", 128//16)
- self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
- self.add_constant("MEMTEST_BUS_DEBUG", 1)
- self.add_constant("MEMTEST_ADDR_DEBUG", 1)
- self.add_constant("MEMTEST_DATA_DEBUG", 1)
-
-
- # add JTAG platform pins
- platform.add_extension([
- ("jtag", 0,
- Subsignal("tck", Pins(1)),
- Subsignal("tms", Pins(1)),
- Subsignal("tdi", Pins(1)),
- Subsignal("tdo", Pins(1)),
- )
- ])
-
- jtagpads = platform.request("jtag")
- self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
- self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
- self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
- self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
-
-
- # Debug ---------------------------------------------------------------
- if not debug:
- return
-
- # setup running of DMI FSM
- dmi_addr = Signal(4)
- dmi_din = Signal(64)
- dmi_dout = Signal(64)
- dmi_wen = Signal(1)
- dmi_req = Signal(1)
-
- # debug log out
- dbg_addr = Signal(4)
- dbg_dout = Signal(64)
- dbg_msg = Signal(1)
-
- # capture pc from dmi
- pc = Signal(64)
- active_dbg = Signal()
- active_dbg_cr = Signal()
- active_dbg_xer = Signal()
-
- # xer flags
- xer_so = Signal()
- xer_ca = Signal()
- xer_ca32 = Signal()
- xer_ov = Signal()
- xer_ov32 = Signal()
-
- # increment counter, Stop after 100000 cycles
- uptime = Signal(64)
- self.sync += uptime.eq(uptime + 1)
- #self.sync += If(uptime == 1000000000000, Finish())
-
- # DMI FSM counter and FSM itself
- dmicount = Signal(10)
- dmirunning = Signal(1)
- dmi_monitor = Signal(1)
- dmifsm = FSM()
- self.submodules += dmifsm
-
- # DMI FSM
- dmifsm.act("START",
- If(dmi_req & dmi_wen,
- (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
- self.cpu.dmi_din.eq(dmi_din), # DMI in
- self.cpu.dmi_req.eq(1), # DMI request
- self.cpu.dmi_wr.eq(1), # DMI write
- If(self.cpu.dmi_ack,
- (NextState("IDLE"),
- )
- ),
- ),
- ),
- If(dmi_req & ~dmi_wen,
- (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
- self.cpu.dmi_req.eq(1), # DMI request
- self.cpu.dmi_wr.eq(0), # DMI read
- If(self.cpu.dmi_ack,
- # acknowledge received: capture data.
- (NextState("IDLE"),
- NextValue(dbg_addr, dmi_addr),
- NextValue(dbg_dout, self.cpu.dmi_dout),
- NextValue(dbg_msg, 1),
- ),
- ),
- ),
- )
- )
-
- # DMI response received: reset the dmi request and check if
- # in "monitor" mode
- dmifsm.act("IDLE",
- If(dmi_monitor,
- NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
- ).Else(
- NextState("START"), # back to start on next cycle
- ),
- NextValue(dmi_req, 0),
- NextValue(dmi_addr, 0),
- NextValue(dmi_din, 0),
- NextValue(dmi_wen, 0),
- )
-
- # "monitor" mode fires off a STAT request
- dmifsm.act("FIRE_MONITOR",
- (NextValue(dmi_req, 1),
- NextValue(dmi_addr, 1), # DMI STAT address
- NextValue(dmi_din, 0),
- NextValue(dmi_wen, 0), # read STAT
- NextState("START"), # back to start on next cycle
- )
- )
-
- self.comb += xer_so.eq((dbg_dout & 1) == 1)
- self.comb += xer_ca.eq((dbg_dout & 4) == 4)
- self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
- self.comb += xer_ov.eq((dbg_dout & 16) == 16)
- self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
-
- # debug messages out
- self.sync += If(dbg_msg,
- (If(active_dbg & (dbg_addr == 0b10), # PC
- Display("pc : %016x", dbg_dout),
- ),
- If(dbg_addr == 0b10, # PC
- pc.eq(dbg_dout), # capture PC
- ),
- #If(dbg_addr == 0b11, # MSR
- # Display(" msr: %016x", dbg_dout),
- #),
- If(dbg_addr == 0b1000, # CR
- Display(" cr : %016x", dbg_dout),
- ),
- If(dbg_addr == 0b1001, # XER
- Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
- xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
- ),
- If(dbg_addr == 0b101, # GPR
- Display(" gpr: %016x", dbg_dout),
- ),
- # also check if this is a "stat"
- If(dbg_addr == 1, # requested a STAT
- #Display(" stat: %x", dbg_dout),
- If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
- dmirunning.eq(1), # continue running
- dmi_monitor.eq(0), # and stop monitor mode
- ),
- ),
- dbg_msg.eq(0)
- )
- )
-
- # kick off a "stop"
- self.sync += If(uptime == 0,
- (dmi_addr.eq(0), # CTRL
- dmi_din.eq(1<<0), # STOP
- dmi_req.eq(1),
- dmi_wen.eq(1),
- )
- )
-
- self.sync += If(uptime == 4,
- dmirunning.eq(1),
- )
-
- self.sync += If(dmirunning,
- dmicount.eq(dmicount + 1),
- )
-
- # loop every 1<<N cycles
- cyclewid = 9
-
- # get the PC
- self.sync += If(dmicount == 4,
- (dmi_addr.eq(0b10), # NIA
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # kick off a "step"
- self.sync += If(dmicount == 8,
- (dmi_addr.eq(0), # CTRL
- dmi_din.eq(1<<3), # STEP
- dmi_req.eq(1),
- dmi_wen.eq(1),
- dmirunning.eq(0), # stop counter, need to fire "monitor"
- dmi_monitor.eq(1), # start "monitor" instead
- )
- )
-
- # limit range of pc for debug reporting
- #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
- #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
- self.comb += active_dbg.eq(1)
-
-
- # get the MSR
- self.sync += If(active_dbg & (dmicount == 12),
- (dmi_addr.eq(0b11), # MSR
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- if cpu == "libresoc":
- #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
- self.comb += active_dbg_cr.eq(0)
-
- # get the CR
- self.sync += If(active_dbg_cr & (dmicount == 16),
- (dmi_addr.eq(0b1000), # CR
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
- self.comb += active_dbg_xer.eq(active_dbg_cr)
-
- # get the CR
- self.sync += If(active_dbg_xer & (dmicount == 20),
- (dmi_addr.eq(0b1001), # XER
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # read all 32 GPRs
- for i in range(32):
- self.sync += If(active_dbg & (dmicount == 24+(i*8)),
- (dmi_addr.eq(0b100), # GSPR addr
- dmi_din.eq(i), # r1
- dmi_req.eq(1),
- dmi_wen.eq(1),
- )
- )
-
- self.sync += If(active_dbg & (dmicount == 28+(i*8)),
- (dmi_addr.eq(0b101), # GSPR data
- dmi_req.eq(1),
- dmi_wen.eq(0),
- )
- )
-
- # monitor bbus read/write
- self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
- Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
- #uptime,
- 0,
- self.cpu.dbus.adr,
- self.cpu.dbus.we,
- self.cpu.dbus.sel,
- self.cpu.dbus.dat_w,
- self.cpu.dbus.dat_r
- )
- )
-
- return
-
- # monitor ibus write
- self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
- self.cpu.ibus.we,
- Display(" [%06x] iadr: %8x, s %01x w %016x",
- #uptime,
- 0,
- self.cpu.ibus.adr,
- self.cpu.ibus.sel,
- self.cpu.ibus.dat_w,
- )
- )
- # monitor ibus read
- self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
- ~self.cpu.ibus.we,
- Display(" [%06x] iadr: %8x, s %01x r %016x",
- #uptime,
- 0,
- self.cpu.ibus.adr,
- self.cpu.ibus.sel,
- self.cpu.ibus.dat_r
- )
- )
-
-# Build -----------------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
- parser.add_argument("--cpu", default="libresoc",
- help="CPU to use: libresoc (default) or microwatt")
- parser.add_argument("--variant", default="standardjtag",
- help="Specify variant with different features")
- parser.add_argument("--debug", action="store_true",
- help="Enable debug traces")
- parser.add_argument("--trace", action="store_true",
- help="Enable tracing")
- parser.add_argument("--trace-start", default=0,
- help="Cycle to start FST tracing")
- parser.add_argument("--trace-end", default=-1,
- help="Cycle to end FST tracing")
- args = parser.parse_args()
-
- sim_config = SimConfig(default_clk="sys_clk")
- sim_config.add_module("serial2console", "serial")
- sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
-
- for i in range(2):
- soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
- builder = Builder(soc,compile_gateware = i!=0)
- builder.build(sim_config=sim_config,
- run = i!=0,
- trace = args.trace,
- trace_start = int(args.trace_start),
- trace_end = int(args.trace_end),
- trace_fst = 0)
- os.chdir("../")
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-#!/usr/bin/env python3
-
-import os
-import argparse
-
-import litex_boards.targets.versa_ecp5 as versa_ecp5
-import litex_boards.targets.ulx3s as ulx3s
-
-from litex.soc.integration.soc_sdram import (soc_sdram_args,
- soc_sdram_argdict)
-from litex.soc.integration.builder import (Builder, builder_args,
- builder_argdict)
-
-from libresoc import LibreSoC
-#from microwatt import Microwatt
-
-# TestSoC
-# ----------------------------------------------------------------------------
-
-from litex.build.generic_platform import Subsignal, Pins, IOStandard
-
-class VersaECP5TestSoC(versa_ecp5.BaseSoC):
- def __init__(self, sys_clk_freq=int(16e6), **kwargs):
- kwargs["integrated_rom_size"] = 0x10000
- #kwargs["integrated_main_ram_size"] = 0x1000
- kwargs["csr_data_width"] = 32
- kwargs["l2_size"] = 0
- #bus_data_width = 16,
-
- versa_ecp5.BaseSoC.__init__(self,
- sys_clk_freq = sys_clk_freq,
- cpu_type = "external",
- cpu_cls = LibreSoC,
- cpu_variant = "standardjtagnoirq",
- #cpu_cls = Microwatt,
- device = "LFE5UM",
- **kwargs)
-
- # (thanks to daveshah for this tip)
- # use platform.add_extension to first define the pins
- # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
-
- # define the pins, add as an extension, *then* request it
- jtag_ios = [
- ("jtag", 0,
- Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
- Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
- Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
- Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
- )
- ]
- self.platform.add_extension(jtag_ios)
- jtag = self.platform.request("jtag")
-
- # wire the pins up to CPU JTAG
- self.comb += self.cpu.jtag_tck.eq(jtag.tck)
- self.comb += self.cpu.jtag_tms.eq(jtag.tms)
- self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
- self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
-
-
- #self.add_constant("MEMTEST_BUS_SIZE", 256//16)
- #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
- #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
-
- #self.add_constant("MEMTEST_BUS_DEBUG", 1)
- #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
- #self.add_constant("MEMTEST_DATA_DEBUG", 1)
-
-
-class ULX3S85FTestSoC(ulx3s.BaseSoC):
- def __init__(self, sys_clk_freq=int(16e6), **kwargs):
- kwargs["integrated_rom_size"] = 0x10000
- #kwargs["integrated_main_ram_size"] = 0x1000
- kwargs["csr_data_width"] = 32
- kwargs["l2_size"] = 0
- #bus_data_width = 16,
-
- ulx3s.BaseSoC.__init__(self,
- sys_clk_freq = sys_clk_freq,
- cpu_type = "external",
- cpu_cls = LibreSoC,
- cpu_variant = "standardjtag",
- #cpu_cls = Microwatt,
- device = "LFE5U-85F",
- **kwargs)
-
- # get 4 arbitrarily assinged logical pins, each gpio has
- # 2 distinct physical single non-differential pins p and n
- gpio0 = self.platform.request("gpio", 0)
- gpio1 = self.platform.request("gpio", 1)
-
- # assign p, n litex 'subsignals' of each gpio to jtag pins
- jtag_tdi = gpio0.n
- jtag_tms = gpio0.p
- jtag_tck = gpio1.n
- jtag_tdo = gpio1.p
-
- # wire the pins up to CPU JTAG
- self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
- self.comb += self.cpu.jtag_tms.eq(jtag_tms)
- self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
- self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
-
-# Build
-# ----------------------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
- "CPU on Versa ECP5 or ULX3S LFE5U85F")
- parser.add_argument("--build", action="store_true", help="Build bitstream")
- parser.add_argument("--load", action="store_true", help="Load bitstream")
- parser.add_argument("--sys-clk-freq", default=int(16e6),
- help="System clock frequency (default=16MHz)")
- parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
- "to build for/load to")
-
- builder_args(parser)
- soc_sdram_args(parser)
- args = parser.parse_args()
-
- if args.fpga == "versa_ecp5":
- soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
- **soc_sdram_argdict(args))
-
- elif args.fpga == "ulx3s85f":
- soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
- **soc_sdram_argdict(args))
-
- else:
- soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
- **soc_sdram_argdict(args))
-
- builder = Builder(soc, **builder_argdict(args))
- builder.build(run=args.build)
-
- if args.load:
- prog = soc.platform.create_programmer()
- prog.load_bitstream(os.path.join(builder.gateware_dir,
- soc.build_name + ".svf"))
-
-if __name__ == "__main__":
- main()
--- /dev/null
+ls180:
+ ./ls180soc.py --build --platform=ls180
+ cp build/ls180/gateware/ls180.v .
+ cp build/ls180/gateware/mem.init .
+ cp build/ls180/gateware/mem_1.init .
+ cp build/ls180/gateware/mem_2.init .
+ cp build/ls180/gateware/mem_3.init .
+ cp build/ls180/gateware/mem_4.init .
+ cp libresoc/libresoc.v .
+ yosys -p 'read_verilog libresoc.v' \
+ -p 'write_ilang libresoc_cvt.il'
+ yosys -p 'read_verilog ls180.v' \
+ -p 'read_verilog SPBlock_512W64B8W.v' \
+ -p 'write_ilang ls180_cvt.il'
+ yosys -p 'read_ilang ls180_cvt.il' \
+ -p 'read_ilang libresoc_cvt.il' \
+ -p 'write_ilang ls180.il'
+
+versaecp5:
+ ./versa_ecp5.py --sys-clk-freq=55e6 --build
+
+versaecp5load:
+ ./versa_ecp5.py --sys-clk-freq=55e6 --load
--- /dev/null
+# sim openocd test
+
+create verilog file "python issuer_verilog libresoc.v"
+copy to libresoc/ directory
+terminal 1: ./sim.py
+terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
+
+# ecp5 build
+
+./versa_ecp5.py --sys-clk-freq=55e6 --build
+./versa_ecp5.py --sys-clk-freq=55e6 --load
--- /dev/null
+(* blackbox = 1 *)
+module SPBlock_512W64B8W(input [8:0] a,
+ input [63:0] d,
+ output [63:0] q,
+ input [7:0] we,
+ input clk);
+endmodule // SPBlock_512W64B8W
--- /dev/null
+// Created using Xilinx iMPACT Software [ISE WebPACK - 5.1i]
+TRST OFF;
+ENDIR IDLE;
+ENDDR IDLE;
+STATE RESET IDLE;
+TIR 0 ;
+HIR 0 ;
+TDR 0 ;
+HDR 0 ;
+// Validating chain...
+TIR 0 ;
+HIR 0 ;
+TDR 0 ;
+HDR 0 ;
+SIR 4 TDI (f) SMASK (f) ;
+TIR 0 ;
+HIR 5 TDI (1f) SMASK (1f) ;
+// don't set header to 1 extra bit
+//HDR 1 TDI (00) SMASK (01) ;
+TDR 0 ;
+//Loading device with 'idcode' instruction.
+SIR 4 TDI (1) SMASK (f) ;
+SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
+//Loading device with 'conld' instruction.
+//SIR 8 TDI (f0) ;
+RUNTEST 110000 TCK;
+
--- /dev/null
+STATE RESET IDLE;
+TIR 0 ;
+HIR 5 TDI (1f) SMASK (1f) ;
+//HDR 1 TDI (00) SMASK (01) ;
+TDR 0 ;
+//Loading device with 'idcode' instruction.
+SIR 4 TDI (1) SMASK (f) ;
+//SDR 32 TDI (00000000) SMASK (ffffffff) TDO (00000c7f) SMASK (ffffffff) ;
+SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
+
+// set to DMI "address"
+SIR 4 TDI (8) SMASK (f) ;
+// set DMI "PC" address (2)
+SDR 8 TDI (2) SMASK (ff) ;
+// set to DMI "data read"
+SIR 4 TDI (9) SMASK (f) ;
+// read 64 bit
+SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (0000000000000000) ;
+
+// set to DMI "address"
+SIR 4 TDI (8) SMASK (f) ;
+// set DMI "CR" address (8)
+SDR 8 TDI (8) SMASK (ff) ;
+// set to DMI "data read"
+SIR 4 TDI (9) SMASK (f) ;
+// read 64 bit
+SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (ffffffffffffffff) ;
+
--- /dev/null
+from libresoc.core import LibreSoC
\ No newline at end of file
--- /dev/null
+.section .text, "ax", @progbits
+.global boot_helper
+boot_helper:
+ nop # FIXME
--- /dev/null
+import os
+
+from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
+
+from litex.soc.interconnect import wishbone as wb
+from litex.soc.cores.cpu import CPU
+
+from soc.config.pinouts import get_pinspecs
+from soc.debug.jtag import Pins
+from c4m.nmigen.jtag.tap import IOType
+
+from libresoc.ls180 import io
+from litex.build.generic_platform import ConstraintManager
+
+
+CPU_VARIANTS = ["standard", "standard32", "standardjtag",
+ "standardjtagtestgpio", "ls180",
+ "standardjtagnoirq"]
+
+
+def make_wb_bus(prefix, obj, simple=False):
+ res = {}
+ outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
+ if not simple:
+ outpins += ['cti', 'bte']
+ for o in outpins:
+ res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
+ for i in ['ack', 'err', 'dat_r']:
+ res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
+ return res
+
+def make_wb_slave(prefix, obj, simple=False):
+ res = {}
+ inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
+ if not simple:
+ inpins += ['cti', 'bte']
+ for i in inpins:
+ res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
+ for o in ['ack', 'err', 'dat_r']:
+ res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
+ return res
+
+def make_pad(res, dirn, name, suffix, cpup, iop):
+ cpud, iod = ('i', 'o') if dirn else ('o', 'i')
+ cname = '%s_%s__core__%s' % (cpud, name, suffix)
+ pname = '%s_%s__pad__%s' % (iod, name, suffix)
+ print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
+ res[cname], res[pname] = cpup, iop
+
+def get_field(rec, name):
+ for f in rec.layout:
+ f = f[0]
+ if f.endswith(name):
+ return getattr(rec, f)
+
+
+def make_jtag_ioconn(res, pin, cpupads, iopads):
+ (fn, pin, iotype, pin_name, scan_idx) = pin
+ #serial_tx__core__o, serial_rx__pad__i,
+ # special-case sdram_clock
+ if pin == 'clock' and fn == 'sdr':
+ cpu = cpupads['sdram_clock']
+ io = iopads['sdram_clock']
+ else:
+ cpu = cpupads[fn]
+ io = iopads[fn]
+ print ("cpupads", cpupads)
+ print ("iopads", iopads)
+ print ("pin", fn, pin, iotype, pin_name)
+ print ("cpu fn", cpu)
+ print ("io fn", io)
+ name = "%s_%s" % (fn, pin)
+ print ("name", name)
+ sigs = []
+
+ if iotype in (IOType.In, IOType.Out):
+ ps = pin.split("_")
+ if pin == 'clock' and fn == 'sdr':
+ cpup = cpu
+ iop = io
+ elif len(ps) == 2 and ps[-1].isdigit():
+ pin, idx = ps
+ idx = int(idx)
+ print ("ps split", pin, idx)
+ cpup = getattr(cpu, pin)[idx]
+ iop = getattr(io, pin)[idx]
+ elif pin.isdigit():
+ idx = int(pin)
+ print ("digit", idx)
+ cpup = cpu[idx]
+ iop = io[idx]
+ else:
+ cpup = getattr(cpu, pin)
+ iop = getattr(io, pin)
+
+ if iotype == IOType.Out:
+ # output from the pad is routed through C4M JTAG and so
+ # is an *INPUT* into core. ls180soc connects this to "real" peripheral
+ make_pad(res, True, name, "o", cpup, iop)
+
+ elif iotype == IOType.In:
+ # input to the pad is routed through C4M JTAG and so
+ # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
+ make_pad(res, True, name, "i", cpup, iop)
+
+ elif iotype == IOType.InTriOut:
+ if fn == 'gpio': # sigh decode GPIO special-case
+ idx = int(pin[1:])
+ oe_idx = idx
+ elif fn == 'sdr': # sigh
+ idx = int(pin.split('_')[-1])
+ oe_idx = 0
+ else:
+ idx = 0
+ oe_idx = 0
+ print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
+ cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
+ make_pad(res, True, name, "i", cpup, iop)
+ cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
+ make_pad(res, True, name, "o", cpup, iop)
+ cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
+ make_pad(res, True, name, "oe", cpup, iop)
+
+ if iotype in (IOType.In, IOType.InTriOut):
+ sigs.append(("i", 1))
+ if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
+ sigs.append(("o", 1))
+ if iotype in (IOType.TriOut, IOType.InTriOut):
+ sigs.append(("oe", 1))
+
+
+class LibreSoC(CPU):
+ name = "libre_soc"
+ human_name = "Libre-SoC"
+ variants = CPU_VARIANTS
+ endianness = "little"
+ gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
+ linker_output_format = "elf64-powerpcle"
+ nop = "nop"
+ io_regions = {0xc0000000: 0x10000000} # origin, length
+
+ @property
+ def mem_map(self):
+ return {"csr": 0xc0000000}
+
+ @property
+ def gcc_flags(self):
+ flags = "-m64 "
+ flags += "-mabi=elfv2 "
+ flags += "-msoft-float "
+ flags += "-mno-string "
+ flags += "-mno-multiple "
+ flags += "-mno-vsx "
+ flags += "-mno-altivec "
+ flags += "-mlittle-endian "
+ flags += "-mstrict-align "
+ flags += "-fno-stack-protector "
+ flags += "-mcmodel=small "
+ flags += "-D__microwatt__ "
+ return flags
+
+ def __init__(self, platform, variant="standard"):
+ self.platform = platform
+ self.variant = variant
+ self.reset = Signal()
+
+ irq_en = "noirq" not in variant
+
+ if irq_en:
+ self.interrupt = Signal(16)
+
+ if variant == "standard32":
+ self.data_width = 32
+ self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
+ else:
+ self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
+ self.data_width = 64
+ self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
+
+ self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
+ self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
+
+ jtag_en = ('jtag' in variant) or variant == 'ls180'
+
+ if "testgpio" in variant:
+ self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
+ if jtag_en:
+ self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
+
+ if "sram4k" in variant or variant == 'ls180':
+ self.srams = srams = []
+ for i in range(4):
+ srams.append(wb.Interface(data_width=64, adr_width=29))
+
+ self.periph_buses = [ibus, dbus]
+ self.memory_buses = []
+
+ if jtag_en:
+ self.periph_buses.append(jtag_wb)
+ self.jtag_tck = Signal(1)
+ self.jtag_tms = Signal(1)
+ self.jtag_tdi = Signal(1)
+ self.jtag_tdo = Signal(1)
+ else:
+ self.dmi_addr = Signal(4)
+ self.dmi_din = Signal(64)
+ self.dmi_dout = Signal(64)
+ self.dmi_wr = Signal(1)
+ self.dmi_ack = Signal(1)
+ self.dmi_req = Signal(1)
+
+ # # #
+
+ self.cpu_params = dict(
+ # Clock / Reset
+ i_clk = ClockSignal(),
+ i_rst = ResetSignal() | self.reset,
+
+ # Monitoring / Debugging
+ i_pc_i = 0,
+ i_pc_i_ok = 0,
+ i_core_bigendian_i = 0, # Signal(),
+ o_busy_o = Signal(), # not connected
+ o_memerr_o = Signal(), # not connected
+ o_pc_o = Signal(64), # not connected
+ )
+
+ if irq_en:
+ # interrupts
+ self.cpu_params['i_int_level_i'] = self.interrupt
+
+ if jtag_en:
+ self.cpu_params.update(dict(
+ # JTAG Debug bus
+ o_TAP_bus__tdo = self.jtag_tdo,
+ i_TAP_bus__tdi = self.jtag_tdi,
+ i_TAP_bus__tms = self.jtag_tms,
+ i_TAP_bus__tck = self.jtag_tck,
+ ))
+ else:
+ self.cpu_params.update(dict(
+ # DMI Debug bus
+ i_dmi_addr_i = self.dmi_addr,
+ i_dmi_din = self.dmi_din,
+ o_dmi_dout = self.dmi_dout,
+ i_dmi_req_i = self.dmi_req,
+ i_dmi_we_i = self.dmi_wr,
+ o_dmi_ack_o = self.dmi_ack,
+ ))
+
+ # add clock select, pll output
+ if variant == "ls180":
+ self.pll_18_o = Signal()
+ self.clk_sel = Signal(2)
+ self.pll_lck_o = Signal()
+ self.cpu_params['i_clk_sel_i'] = self.clk_sel
+ self.cpu_params['o_pll_18_o'] = self.pll_18_o
+ self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
+
+ # add wishbone buses to cpu params
+ self.cpu_params.update(make_wb_bus("ibus", ibus, True))
+ self.cpu_params.update(make_wb_bus("dbus", dbus, True))
+ self.cpu_params.update(make_wb_slave("ics_wb", ics, True))
+ self.cpu_params.update(make_wb_slave("icp_wb", icp, True))
+ if "testgpio" in variant:
+ self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
+ if jtag_en:
+ self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+ if "sram4k" in variant or variant == 'ls180':
+ for i, sram in enumerate(srams):
+ self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i,
+ sram, simple=True))
+
+ # and set ibus advanced tags to zero (disable)
+ self.cpu_params['i_ibus__cti'] = 0
+ self.cpu_params['i_ibus__bte'] = 0
+ self.cpu_params['i_dbus__cti'] = 0
+ self.cpu_params['i_dbus__bte'] = 0
+
+ if variant == 'ls180':
+ # urr yuk. have to expose iopads / pins from core to litex
+ # then back again. cut _some_ of that out by connecting
+ self.padresources = io()
+ self.pad_cm = ConstraintManager(self.padresources, [])
+ self.cpupads = {}
+ iopads = {}
+ litexmap = {}
+ subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+ 'pwm', 'sd0', 'sdr'}
+ for periph in subset:
+ origperiph = periph
+ num = None
+ if periph[-1].isdigit():
+ periph, num = periph[:-1], int(periph[-1])
+ print ("periph request", periph, num)
+ if periph == 'mspi':
+ if num == 0:
+ periph, num = 'spimaster', None
+ else:
+ periph, num = 'spisdcard', None
+ elif periph == 'sdr':
+ periph = 'sdram'
+ elif periph == 'mtwi':
+ periph = 'i2c'
+ elif periph == 'sd':
+ periph, num = 'sdcard', None
+ litexmap[origperiph] = (periph, num)
+ self.cpupads[origperiph] = platform.request(periph, num)
+ iopads[origperiph] = self.pad_cm.request(periph, num)
+ if periph == 'sdram':
+ # special-case sdram clock
+ ck = platform.request("sdram_clock")
+ self.cpupads['sdram_clock'] = ck
+ ck = self.pad_cm.request("sdram_clock")
+ iopads['sdram_clock'] = ck
+
+ pinset = get_pinspecs(subset=subset)
+ p = Pins(pinset)
+ for pin in list(p):
+ make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
+
+ # add verilog sources
+ self.add_sources(platform)
+
+ def set_reset_address(self, reset_address):
+ assert not hasattr(self, "reset_address")
+ self.reset_address = reset_address
+ assert reset_address == 0x00000000
+
+ @staticmethod
+ def add_sources(platform):
+ cdir = os.path.dirname(__file__)
+ platform.add_source(os.path.join(cdir, "libresoc.v"))
+
+ def do_finalize(self):
+ self.specials += Instance("test_issuer", **self.cpu_params)
+
--- /dev/null
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define FIXUP_ENDIAN \
+ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
+ b 191f; /* Skip trampoline if endian is good */ \
+ .long 0xa600607d; /* mfmsr r11 */ \
+ .long 0x01006b69; /* xori r11,r11,1 */ \
+ .long 0x05009f42; /* bcl 20,31,$+4 */ \
+ .long 0xa602487d; /* mflr r10 */ \
+ .long 0x14004a39; /* addi r10,r10,20 */ \
+ .long 0xa64b5a7d; /* mthsrr0 r10 */ \
+ .long 0xa64b7b7d; /* mthsrr1 r11 */ \
+ .long 0x2402004c; /* hrfid */ \
+191:
+
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e) \
+ lis r,(e)@highest; \
+ ori r,r,(e)@higher; \
+ rldicr r,r, 32, 31; \
+ oris r,r, (e)@h; \
+ ori r,r, (e)@l;
+
+ . = 0
+.global _start
+_start:
+ FIXUP_ENDIAN
+
+ /* setup stack */
+ LOAD_IMM64(%r1, _fstack - 0x100)
+ LOAD_IMM64(%r12, main)
+ mtctr %r12,
+ bctrl
+ b .
+
+#define EXCEPTION(nr) \
+ .= nr; \
+ b .
+
+ /* More exception stubs */
+ EXCEPTION(0x100)
+ EXCEPTION(0x200)
+ EXCEPTION(0x300)
+ EXCEPTION(0x380)
+ EXCEPTION(0x400)
+ EXCEPTION(0x480)
+ EXCEPTION(0x500)
+ EXCEPTION(0x600)
+ EXCEPTION(0x700)
+ EXCEPTION(0x800)
+ EXCEPTION(0x900)
+ EXCEPTION(0x980)
+ EXCEPTION(0xa00)
+ EXCEPTION(0xb00)
+ EXCEPTION(0xc00)
+ EXCEPTION(0xd00)
+ EXCEPTION(0xe00)
+ EXCEPTION(0xe20)
+ EXCEPTION(0xe40)
+ EXCEPTION(0xe60)
+ EXCEPTION(0xe80)
+ EXCEPTION(0xf00)
+ EXCEPTION(0xf20)
+ EXCEPTION(0xf40)
+ EXCEPTION(0xf60)
+ EXCEPTION(0xf80)
+#if 0
+ EXCEPTION(0x1000)
+ EXCEPTION(0x1100)
+ EXCEPTION(0x1200)
+ EXCEPTION(0x1300)
+ EXCEPTION(0x1400)
+ EXCEPTION(0x1500)
+ EXCEPTION(0x1600)
+#endif
+
+ .text
+
--- /dev/null
+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline unsigned int irq_getie(void)
+{
+ return 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+ /*if(ie) csrs(); else csrc();*/
+}
+
+static inline unsigned int irq_getmask(void)
+{
+ unsigned int mask = 0;
+ //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+ return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+ //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+ unsigned int pending = 0;
+ //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+ return pending;
+}
+
+#endif /* __IRQ_H */
--- /dev/null
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+"""ls180 ASIC platform
+
+conceptually similar to the following:
+
+* https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
+* https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
+
+Total I/O pins: 84.
+Fits in a JEDEC QFP-100
+
+"""
+
+from migen.fhdl.structure import _Fragment
+from litex.build.generic_platform import (GenericPlatform, Pins,
+ Subsignal, IOStandard, Misc,
+ )
+import os
+
+
+def make_uart(name, num):
+ return (name, num,
+ Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
+ Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
+ )
+
+def make_gpio(name, num, n_gpio):
+ pins = []
+ for i in range(n_gpio):
+ pins.append("X%d" % i)
+ pins = ' '.join(pins)
+ return (name, 0,
+ Subsignal("i", Pins(pins), Misc("PULLMODE=UP")),
+ Subsignal("o", Pins(pins), Misc("PULLMODE=UP")),
+ Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")),
+ IOStandard("LVCMOS33"))
+
+
+
+# IOs ---------------------------------------------------------------------
+
+def io():
+ _io = [
+ # CLK/RST: 2 pins
+ ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
+ ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
+ ("sys_clksel_i", 0, Pins("R1 R2"), IOStandard("LVCMOS33")),
+ ("sys_pll_18_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
+ ("sys_pll_lck_o", 0, Pins("R1"), IOStandard("LVCMOS33")),
+
+ # JTAG0: 4 pins
+ ("jtag", 0,
+ Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
+ Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
+ Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
+ Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
+ ),
+
+ # I2C0: 2 pins
+ ("i2c", 0,
+ Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
+ Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")),
+ Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")),
+ Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")),
+ ),
+
+ # SPI0: 4 pins
+ ("spimaster", 0,
+ Subsignal("clk", Pins("J1")),
+ Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
+ Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
+ Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
+ Misc("SLEWRATE=FAST"),
+ IOStandard("LVCMOS33"),
+ ),
+
+ # SPICARD0: 4 pins
+ ("spisdcard", 0,
+ Subsignal("clk", Pins("J1")),
+ Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
+ Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
+ Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
+ Misc("SLEWRATE=FAST"),
+ IOStandard("LVCMOS33"),
+ ),
+
+ # SDCARD0: 6 pins
+ ("sdcard", 0,
+ Subsignal("clk", Pins("J1")),
+ Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")),
+ Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")),
+ Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")),
+ Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
+ Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
+ Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
+ Misc("SLEWRATE=FAST"),
+ IOStandard("LVCMOS33"),
+ ),
+
+ # SDRAM: 39 pins
+ ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
+ ("sdram", 0,
+ Subsignal("a", Pins(
+ "M20 M19 L20 L19 K20 K19 K18 J20",
+ "J19 H20 N19 G20 G19")),
+ Subsignal("dq_i", Pins(
+ "J16 L18 M18 N18 P18 T18 T17 U20",
+ "E19 D20 D19 C20 E18 F18 J18 J17")),
+ Subsignal("dq_o", Pins(
+ "J16 L18 M18 N18 P18 T18 T17 U20",
+ "E19 D20 D19 C20 E18 F18 J18 J17")),
+ Subsignal("dq_oe", Pins("J17")),
+ Subsignal("we_n", Pins("T20")),
+ Subsignal("ras_n", Pins("R20")),
+ Subsignal("cas_n", Pins("T19")),
+ Subsignal("cs_n", Pins("P30")),
+ Subsignal("cke", Pins("F21")),
+ Subsignal("ba", Pins("P19 N20")),
+ Subsignal("dm", Pins("U19 E20")),
+ IOStandard("LVCMOS33"),
+ Misc("SLEWRATE=FAST"),
+ ),
+
+ # PWM: 2 pins
+ ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")),
+ ]
+
+ n_gpio = 16
+
+ # 16 GPIOs
+ _io.append( make_gpio("gpio", 0, n_gpio) )
+
+ # EINT: 3 pins
+ _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
+
+ # UART0: 2 pins
+ _io.append(make_uart("uart", 0))
+ # UART1: 2 pins
+ _io.append(make_uart("uart", 1))
+
+ # not connected - eurgh have to adjust this to match the total pincount.
+ num_nc = 24
+ nc = ' '.join("NC%d" % i for i in range(num_nc))
+ _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
+
+ return _io
+
+# Platform ----------------------------------------------------------------
+
+class LS180Platform(GenericPlatform):
+ default_clk_name = "sys_clk"
+ default_clk_period = 1e9/50e6
+
+ def __init__(self, device="LS180", **kwargs):
+ assert device in ["LS180"]
+ GenericPlatform.__init__(self, device, io(), **kwargs)
+
+ def build(self, fragment,
+ build_dir = "build",
+ build_name = "top",
+ run = True,
+ timingstrict = True,
+ **kwargs):
+
+ platform = self
+
+ # Create build directory
+ os.makedirs(build_dir, exist_ok=True)
+ cwd = os.getcwd()
+ os.chdir(build_dir)
+
+ # Finalize design
+ if not isinstance(fragment, _Fragment):
+ fragment = fragment.get_fragment()
+ platform.finalize(fragment)
+
+ # Generate verilog
+ v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
+ named_sc, named_pc = platform.resolve_signals(v_output.ns)
+ v_file = build_name + ".v"
+ v_output.write(v_file)
+ platform.add_source(v_file)
+
+ os.chdir(cwd)
+
+ return v_output.ns
+
+ def do_finalize(self, fragment):
+ super().do_finalize(fragment)
+ return
+ self.add_period_constraint(self.lookup_request("clk", loose=True),
+ 1e9/50e6)
--- /dev/null
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
--- /dev/null
+N0 | VSS
+N1 | sys_clk
+N2 | VSS
+N3 | sys_rst
+N4 | JTAG0 tck
+N5 | JTAG0 tms
+N6 | JTAG0 tdi
+N7 | JTAG0 tdo
+N8 | UART0 tx
+N9 | UART0 rx
+N10 | GPIO0 gpio0
+N11 | GPIO0 gpio1
+N12 | VDD
+N13 | SPI0 clk
+N14 | SPI0 mosi
+N15 | SPI0 cs_n
+N16 | SPI0 miso
+N17 | VSS
+N18 | SDCARD0 clk
+N19 | SDCARD0 cmd
+N20 | SDCARD0 data0
+N21 | SDCARD0 data1
+N22 | SDCARD0 data2
+N23 | SDCARD0 data3
+N24 | VDD
+N25 | SDRAM0 cs0_n
+N26 | SDRAM0 cs1_n
+N27 | SDRAM0 cke0
+N28 | SDRAM0 cke1
+N29 | VDD
+N30 | nc
+N31 | VSS
+
+E0 | VDD
+E1 | SDRAM0 a0
+E2 | SDRAM0 a1
+E3 | SDRAM0 a2
+E4 | SDRAM0 a3
+E5 | SDRAM0 a4
+E6 | SDRAM0 a5
+E7 | SDRAM0 a6
+E8 | SDRAM0 a7
+E9 | VSS
+E10 | SDRAM0 a8
+E11 | SDRAM0 a9
+E12 | SDRAM0 a10
+E13 | SDRAM0 a11
+E14 | SDRAM0 a12
+E15 | SDRAM0 a13
+E16 | SDRAM0 a14
+E17 | SDRAM0 a15
+E18 | VDD
+E19 | nc
+E20 | VSS
+E21 | SDRAM0 we_n
+E22 | SDRAM0 ras_n
+E23 | SDRAM0 cas_n
+E24 | nc
+E25 | VDD
+E26 | SDRAM0 ba0
+E27 | SDRAM0 ba1
+E28 | SDRAM0 dm0
+E29 | SDRAM0 dm1
+E30 | VSS
+E31 | SDRAM0 sdram_clock
+
+S0 | nc
+S1 | VDD
+S2 | SDRAM0 dq0
+S3 | SDRAM0 dq1
+S4 | SDRAM0 dq2
+S5 | SDRAM0 dq3
+S6 | SDRAM0 dq4
+S7 | SDRAM0 dq5
+S8 | SDRAM0 dq6
+S9 | SDRAM0 dq7
+S10 | VSS
+S11 | SDRAM0 dq8
+S12 | SDRAM0 dq9
+S13 | SDRAM0 dq10
+S14 | SDRAM0 dq11
+S15 | SDRAM0 dq12
+S16 | SDRAM0 dq13
+S17 | SDRAM0 dq14
+S18 | SDRAM0 dq15
+S19 | VDD
+S20 | PWM0 pwm0
+S21 | PWM1 pwm1
+S22 | VSS
+S23 | EINT0 eint0
+S24 | GPIO0 gpio14
+S25 | GPIO0 gpio15
+S26 | nc
+S27 | nc
+S28 | nc
+S29 | nc
+S30 | nc
+S31 | VDD
+
+W0 | VSS
+W1 | SPI1 clk
+W2 | SPI1 mosi
+W3 | SPI1 cs_n
+W4 | SPI1 miso
+W5 | VDD
+W6 | UART1 tx
+W7 | UART1 rx
+W8 | GPIO0 gpio2
+W9 | GPIO0 gpio3
+W10 | GPIO0 gpio4
+W11 | GPIO0 gpio5
+W12 | GPIO0 gpio6
+W13 | GPIO0 gpio7
+W14 | GPIO0 gpio8
+W15 | GPIO0 gpio9
+W16 | GPIO0 gpio10
+W17 | GPIO0 gpio11
+W18 | GPIO0 gpio12
+W19 | GPIO0 gpio13
+W20 | VSS
+W21 | EINT0 eint1
+W22 | EINT0 eint2
+W23 | I2C0 sda
+W24 | I2C0 scl
+W25 | nc
+W26 | nc
+W27 | nc
+W28 | nc
+W29 | nc
+W30 | nc
+W31 | VDD
--- /dev/null
+#!/usr/bin/env python3
+
+import os
+import argparse
+from functools import reduce
+from operator import or_
+
+from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
+ Cat, Record, ClockSignal, wrap, ResetInserter)
+
+from litex.build.generic_platform import Pins, Subsignal
+from litex.build.sim import SimPlatform
+from litex.build.io import CRG
+from litex.build.sim.config import SimConfig
+
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.soc_core import SoCCore
+from litex.soc.integration.soc_sdram import SoCSDRAM
+from litex.soc.integration.builder import Builder
+from litex.soc.integration.common import get_mem_data
+
+from litedram import modules as litedram_modules
+from litedram.phy.model import SDRAMPHYModel
+#from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
+from litedram.common import PHYPadsCombiner, PhySettings
+from litedram.phy.dfi import Interface as DFIInterface
+from litex.soc.cores.spi import SPIMaster
+from litex.soc.cores.pwm import PWM
+#from litex.soc.cores.bitbang import I2CMaster
+from litex.soc.cores import uart
+
+from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
+
+from litex.tools.litex_sim import Platform
+from libresoc.ls180 import LS180Platform
+
+from migen import Module
+from litex.soc.interconnect.csr import AutoCSR
+
+from libresoc import LibreSoC
+from microwatt import Microwatt
+
+# HACK!
+from litex.soc.integration.soc import SoCCSRHandler
+SoCCSRHandler.supported_address_width.append(12)
+
+# GPIO Tristate -------------------------------------------------------
+# doesn't work properly.
+#from litex.soc.cores.gpio import GPIOTristate
+from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
+from migen.genlib.cdc import MultiReg
+
+# Imports
+from litex.soc.interconnect import wishbone
+from litesdcard.phy import (SDPHY, SDPHYClocker,
+ SDPHYInit, SDPHYCMDW, SDPHYCMDR,
+ SDPHYDATAW, SDPHYDATAR,
+ _sdpads_layout)
+from litesdcard.core import SDCore
+from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
+from litex.build.io import SDROutput, SDRInput
+
+
+# I2C Master Bit-Banging --------------------------------------------------
+
+class I2CMaster(Module, AutoCSR):
+ """I2C Master Bit-Banging
+
+ Provides the minimal hardware to do software I2C Master bit banging.
+
+ On the same write CSRStorage (_w), software can control SCL (I2C_SCL),
+ SDA direction and value (I2C_OE, I2C_W). Software get back SDA value
+ with the read CSRStatus (_r).
+ """
+ pads_layout = [("scl", 1), ("sda", 1)]
+ def __init__(self, pads):
+ self.pads = pads
+ self._w = CSRStorage(fields=[
+ CSRField("scl", size=1, offset=0),
+ CSRField("oe", size=1, offset=1),
+ CSRField("sda", size=1, offset=2)],
+ name="w")
+ self._r = CSRStatus(fields=[
+ CSRField("sda", size=1, offset=0)],
+ name="r")
+
+ self.connect(pads)
+
+ def connect(self, pads):
+ _sda_w = Signal()
+ _sda_oe = Signal()
+ _sda_r = Signal()
+ self.comb += [
+ pads.scl.eq(self._w.fields.scl),
+ pads.sda_oe.eq( self._w.fields.oe),
+ pads.sda_o.eq( self._w.fields.sda),
+ self._r.fields.sda.eq(pads.sda_i),
+ ]
+
+
+class GPIOTristateASIC(Module, AutoCSR):
+ def __init__(self, pads, prange=None):
+ nbits = len(pads.oe) # hack
+ self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
+ self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
+ self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
+
+ # # #
+
+ _pads = Record( (("i", nbits),
+ ("o", nbits),
+ ("oe", nbits)))
+ self.comb += _pads.i.eq(pads.i)
+ self.comb += pads.o.eq(_pads.o)
+ self.comb += pads.oe.eq(_pads.oe)
+
+ self.comb += _pads.oe.eq(self._oe.storage)
+ self.comb += _pads.o.eq(self._out.storage)
+ if prange is None:
+ prange = range(nbits)
+ for i in prange:
+ self.specials += MultiReg(_pads.i[i], self._in.status[i])
+
+# SDCard PHY IO -------------------------------------------------------
+
+class SDRPad(Module):
+ def __init__(self, pad, name, o, oe, i):
+ clk = ClockSignal()
+ _o = getattr(pad, "%s_o" % name)
+ _oe = getattr(pad, "%s_oe" % name)
+ _i = getattr(pad, "%s_i" % name)
+ self.specials += SDROutput(clk=clk, i=oe, o=_oe)
+ for j in range(len(_o)):
+ self.specials += SDROutput(clk=clk, i=o[j], o=_o[j])
+ self.specials += SDRInput(clk=clk, i=_i[j], o=i[j])
+
+
+class SDPHYIOGen(Module):
+ def __init__(self, clocker, sdpads, pads):
+ # Rst
+ if hasattr(pads, "rst"):
+ self.comb += pads.rst.eq(0)
+
+ # Clk
+ self.specials += SDROutput(
+ clk = ClockSignal(),
+ i = ~clocker.clk & sdpads.clk,
+ o = pads.clk
+ )
+
+ # Cmd
+ c = sdpads.cmd
+ self.submodules.sd_cmd = SDRPad(pads, "cmd", c.o, c.oe, c.i)
+
+ # Data
+ d = sdpads.data
+ self.submodules.sd_data = SDRPad(pads, "data", d.o, d.oe, d.i)
+
+
+class SDPHY(Module, AutoCSR):
+ def __init__(self, pads, device, sys_clk_freq,
+ cmd_timeout=10e-3, data_timeout=10e-3):
+ self.card_detect = CSRStatus() # Assume SDCard is present if no cd pin.
+ self.comb += self.card_detect.status.eq(getattr(pads, "cd", 0))
+
+ self.submodules.clocker = clocker = SDPHYClocker()
+ self.submodules.init = init = SDPHYInit()
+ self.submodules.cmdw = cmdw = SDPHYCMDW()
+ self.submodules.cmdr = cmdr = SDPHYCMDR(sys_clk_freq,
+ cmd_timeout, cmdw)
+ self.submodules.dataw = dataw = SDPHYDATAW()
+ self.submodules.datar = datar = SDPHYDATAR(sys_clk_freq,
+ data_timeout)
+
+ # # #
+
+ self.sdpads = sdpads = Record(_sdpads_layout)
+
+ # IOs
+ sdphy_cls = SDPHYIOGen
+ self.submodules.io = sdphy_cls(clocker, sdpads, pads)
+
+ # Connect pads_out of submodules to physical pads --------------
+ pl = [init, cmdw, cmdr, dataw, datar]
+ self.comb += [
+ sdpads.clk.eq( reduce(or_, [m.pads_out.clk for m in pl])),
+ sdpads.cmd.oe.eq( reduce(or_, [m.pads_out.cmd.oe for m in pl])),
+ sdpads.cmd.o.eq( reduce(or_, [m.pads_out.cmd.o for m in pl])),
+ sdpads.data.oe.eq(reduce(or_, [m.pads_out.data.oe for m in pl])),
+ sdpads.data.o.eq( reduce(or_, [m.pads_out.data.o for m in pl])),
+ ]
+ for m in pl:
+ self.comb += m.pads_out.ready.eq(self.clocker.ce)
+
+ # Connect physical pads to pads_in of submodules ---------------
+ for m in pl:
+ self.comb += m.pads_in.valid.eq(self.clocker.ce)
+ self.comb += m.pads_in.cmd.i.eq(sdpads.cmd.i)
+ self.comb += m.pads_in.data.i.eq(sdpads.data.i)
+
+ # Speed Throttling -------------------------------------------
+ self.comb += clocker.stop.eq(dataw.stop | datar.stop)
+
+
+# Generic SDR PHY ---------------------------------------------------------
+
+class GENSDRPHY(Module):
+ def __init__(self, pads, cl=2, cmd_latency=1):
+ pads = PHYPadsCombiner(pads)
+ addressbits = len(pads.a)
+ bankbits = len(pads.ba)
+ nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
+ databits = len(pads.dq_i)
+ assert cl in [2, 3]
+ assert databits%8 == 0
+
+ # PHY settings ----------------------------------------------------
+ self.settings = PhySettings(
+ phytype = "GENSDRPHY",
+ memtype = "SDR",
+ databits = databits,
+ dfi_databits = databits,
+ nranks = nranks,
+ nphases = 1,
+ rdphase = 0,
+ wrphase = 0,
+ rdcmdphase = 0,
+ wrcmdphase = 0,
+ cl = cl,
+ read_latency = cl + cmd_latency,
+ write_latency = 0
+ )
+
+ # DFI Interface ---------------------------------------------------
+ self.dfi = dfi = DFIInterface(addressbits, bankbits, nranks, databits)
+
+ # # #
+
+ # Iterate on pads groups ------------------------------------------
+ for pads_group in range(len(pads.groups)):
+ pads.sel_group(pads_group)
+
+ # Addresses and Commands --------------------------------------
+ p0 = dfi.p0
+ self.specials += [SDROutput(i=p0.address[i], o=pads.a[i])
+ for i in range(len(pads.a))]
+ self.specials += [SDROutput(i=p0.bank[i], o=pads.ba[i])
+ for i in range(len(pads.ba))]
+ self.specials += SDROutput(i=p0.cas_n, o=pads.cas_n)
+ self.specials += SDROutput(i=p0.ras_n, o=pads.ras_n)
+ self.specials += SDROutput(i=p0.we_n, o=pads.we_n)
+ if hasattr(pads, "cke"):
+ for i in range(len(pads.cke)):
+ self.specials += SDROutput(i=p0.cke[i], o=pads.cke[i])
+ if hasattr(pads, "cs_n"):
+ for i in range(len(pads.cs_n)):
+ self.specials += SDROutput(i=p0.cs_n[i], o=pads.cs_n[i])
+
+ # DQ/DM Data Path -------------------------------------------------
+
+ d = dfi.p0
+ wren = []
+ self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata)
+
+ if hasattr(pads, "dm"):
+ for i in range(len(pads.dm)):
+ self.specials += SDROutput(i=d.wrdata_mask[i], o=pads.dm[i])
+
+ # DQ/DM Control Path ----------------------------------------------
+ rddata_en = Signal(cl + cmd_latency)
+ self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en))
+ self.sync += dfi.p0.rddata_valid.eq(rddata_en[-1])
+
+
+# LibreSoC 180nm ASIC -------------------------------------------------------
+
+class LibreSoCSim(SoCCore):
+ def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
+ sdram_module = "AS4C16M16",
+ #sdram_data_width = 16,
+ #sdram_module = "MT48LC16M16",
+ sdram_data_width = 16,
+ irq_reserved_irqs = {'uart': 0},
+ platform='sim',
+ ):
+ assert cpu in ["libresoc", "microwatt"]
+ sys_clk_freq = int(50e6)
+
+ if platform == 'sim':
+ platform = Platform()
+ uart_name = "sim"
+ elif platform == 'ls180':
+ platform = LS180Platform()
+ uart_name = "uart"
+
+ #cpu_data_width = 32
+ cpu_data_width = 64
+
+ variant = "ls180"
+
+ # reserve XICS ICP and XICS memory addresses.
+ self.mem_map['icp'] = 0xc0010000
+ self.mem_map['ics'] = 0xc0011000
+ #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
+ #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
+
+ ram_init = []
+ if False:
+ #ram_init = get_mem_data({
+ # ram_fname: "0x00000000",
+ # }, "little")
+ ram_init = get_mem_data(ram_fname, "little")
+
+ # remap the main RAM to reset-start-address
+
+ # without sram nothing works, therefore move it to higher up
+ self.mem_map["sram"] = 0x90000000
+
+ # put UART at 0xc000200 (w00t! this works!)
+ self.csr_map["uart"] = 4
+
+ self.mem_map["main_ram"] = 0x90000000
+ self.mem_map["sram"] = 0x00000000
+ self.mem_map["sram1"] = 0x00000200
+ self.mem_map["sram2"] = 0x00000400
+ self.mem_map["sram3"] = 0x00000600
+ self.mem_map["sram4"] = 0x00000800
+ self.mem_map["sram4k_0"] = 0x00001000
+ self.mem_map["sram4k_1"] = 0x00002000
+ self.mem_map["sram4k_2"] = 0x00003000
+ self.mem_map["sram4k_3"] = 0x00004000
+
+ # SoCCore -------------------------------------------------------------
+ SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+ cpu_type = "microwatt",
+ cpu_cls = LibreSoC if cpu == "libresoc" \
+ else Microwatt,
+ bus_data_width = 64,
+ csr_address_width = 14, # limit to 0x8000
+ cpu_variant = variant,
+ csr_data_width = 8,
+ l2_size = 0,
+ with_uart = False,
+ uart_name = None,
+ with_sdram = with_sdram,
+ sdram_module = sdram_module,
+ sdram_data_width = sdram_data_width,
+ integrated_rom_size = 0, # if ram_fname else 0x10000,
+ #integrated_sram_size = 0x1000, - problem with yosys ABC
+ integrated_sram_size = 0x200,
+ #integrated_main_ram_init = ram_init,
+ integrated_main_ram_size = 0x00000000 if with_sdram \
+ else 0x10000000 , # 256MB
+ )
+ self.platform.name = "ls180"
+
+ # add 4 more 4k integrated SRAMs
+ self.add_ram("sram1", self.mem_map["sram1"], 0x200)
+ self.add_ram("sram2", self.mem_map["sram2"], 0x200)
+ self.add_ram("sram3", self.mem_map["sram3"], 0x200)
+ self.add_ram("sram4", self.mem_map["sram4"], 0x200)
+
+ # SDR SDRAM ----------------------------------------------
+ if False: # not self.integrated_main_ram_size:
+ self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
+
+ if cpu == "libresoc":
+ # XICS interrupt devices
+ icp_addr = self.mem_map['icp']
+ icp_wb = self.cpu.xics_icp
+ icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
+ self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+
+ ics_addr = self.mem_map['ics']
+ ics_wb = self.cpu.xics_ics
+ ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
+ self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+
+ # add 4x 4k SRAMs
+ for i, sram_wb in enumerate(self.cpu.srams):
+ name = 'sram4k_%d' % i
+ sram_adr = self.mem_map[name]
+ ics_region = SoCRegion(origin=sram_adr, size=0x1000)
+ self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
+
+ # CRG -----------------------------------------------------------------
+ self.submodules.crg = CRG(platform.request("sys_clk"),
+ platform.request("sys_rst"))
+
+ # PLL/Clock Select
+ clksel_i = platform.request("sys_clksel_i")
+ pll18_o = platform.request("sys_pll_18_o")
+ pll_lck_o = platform.request("sys_pll_lck_o")
+
+ self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
+ self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
+ self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
+
+ #ram_init = []
+
+ # SDRAM ----------------------------------------------------
+ if with_sdram:
+ sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
+ sdram_module_cls = getattr(litedram_modules, sdram_module)
+ sdram_rate = "1:{}".format(
+ sdram_module_nphases[sdram_module_cls.memtype])
+ sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
+ phy_settings = get_sdram_phy_settings(
+ memtype = sdram_module.memtype,
+ data_width = sdram_data_width,
+ clk_freq = sdram_clk_freq)
+ #sdrphy_cls = HalfRateGENSDRPHY
+ sdrphy_cls = GENSDRPHY
+ sdram_pads = self.cpu.cpupads['sdr']
+ self.submodules.sdrphy = sdrphy_cls(sdram_pads)
+ #self.submodules.sdrphy = sdrphy_cls(sdram_module,
+ # phy_settings,
+ # init=ram_init
+ # )
+ self.add_sdram("sdram",
+ phy = self.sdrphy,
+ module = sdram_module,
+ origin = self.mem_map["main_ram"],
+ size = 0x80000000,
+ l2_cache_size = 0, # 8192
+ l2_cache_min_data_width = 128,
+ l2_cache_reverse = True
+ )
+ # FIXME: skip memtest to avoid corrupting memory
+ self.add_constant("MEMTEST_BUS_SIZE", 128//16)
+ self.add_constant("MEMTEST_DATA_SIZE", 128//16)
+ self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
+ self.add_constant("MEMTEST_BUS_DEBUG", 1)
+ self.add_constant("MEMTEST_ADDR_DEBUG", 1)
+ self.add_constant("MEMTEST_DATA_DEBUG", 1)
+
+ # SDRAM clock
+ sys_clk = ClockSignal()
+ sdr_clk = self.cpu.cpupads['sdram_clock']
+ #self.specials += DDROutput(1, 0, , sdram_clk)
+ self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
+
+ # UART
+ uart_core_pads = self.cpu.cpupads['uart']
+ self.submodules.uart_phy = uart.UARTPHY(
+ pads = uart_core_pads,
+ clk_freq = self.sys_clk_freq,
+ baudrate = 115200)
+ self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
+ tx_fifo_depth = 16,
+ rx_fifo_depth = 16))
+
+ self.csr.add("uart_phy", use_loc_if_exists=True)
+ self.csr.add("uart", use_loc_if_exists=True)
+ self.irq.add("uart", use_loc_if_exists=True)
+
+ # GPIOs (bi-directional)
+ gpio_core_pads = self.cpu.cpupads['gpio']
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
+ self.add_csr("gpio")
+
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+ self.add_csr("gpio1")
+
+ # SPI Master
+ print ("cpupadkeys", self.cpu.cpupads.keys())
+ self.submodules.spimaster = SPIMaster(
+ pads = self.cpu.cpupads['mspi1'],
+ data_width = 8,
+ sys_clk_freq = sys_clk_freq,
+ spi_clk_freq = 8e6,
+ )
+ self.add_csr("spimaster")
+
+ # SPI SDCard (1 wide)
+ spi_clk_freq = 400e3
+ pads = self.cpu.cpupads['mspi0']
+ spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
+ spisdcard.add_clk_divider()
+ setattr(self.submodules, 'spisdcard', spisdcard)
+ self.add_csr('spisdcard')
+
+ # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
+ eintpads = self.cpu.cpupads['eint']
+ print ("eintpads", eintpads)
+ self.comb += self.cpu.interrupt[12:16].eq(eintpads)
+
+ # JTAG
+ jtagpads = platform.request("jtag")
+ self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+ self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+ self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+ self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+ # NC - allows some iopads to be connected up
+ # sigh, just do something, anything, to stop yosys optimising these out
+ nc_pads = platform.request("nc")
+ num_nc = len(nc_pads)
+ self.nc = Signal(num_nc)
+ self.comb += self.nc.eq(nc_pads)
+ self.dummy = Signal(num_nc)
+ for i in range(num_nc):
+ self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0])
+
+ # PWM
+ pwmpads = self.cpu.cpupads['pwm']
+ for i in range(2):
+ name = "pwm%d" % i
+ setattr(self.submodules, name, PWM(pwmpads[i]))
+ self.add_csr(name)
+
+ # I2C Master
+ i2c_core_pads = self.cpu.cpupads['mtwi']
+ self.submodules.i2c = I2CMaster(i2c_core_pads)
+ self.add_csr("i2c")
+
+ # SDCard -----------------------------------------------------
+
+ # Emulator / Pads
+ sdcard_pads = self.cpu.cpupads['sd0']
+
+ # Core
+ self.submodules.sdphy = SDPHY(sdcard_pads,
+ self.platform.device, self.clk_freq)
+ self.submodules.sdcore = SDCore(self.sdphy)
+ self.add_csr("sdphy")
+ self.add_csr("sdcore")
+
+ # Block2Mem DMA
+ bus = wishbone.Interface(data_width=self.bus.data_width,
+ adr_width=self.bus.address_width)
+ self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
+ endianness=self.cpu.endianness)
+ self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
+ dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+ dma_bus.add_master("sdblock2mem", master=bus)
+ self.add_csr("sdblock2mem")
+
+ # Mem2Block DMA
+ bus = wishbone.Interface(data_width=self.bus.data_width,
+ adr_width=self.bus.address_width)
+ self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
+ endianness=self.cpu.endianness)
+ self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
+ dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+ dma_bus.add_master("sdmem2block", master=bus)
+ self.add_csr("sdmem2block")
+
+ # Debug ---------------------------------------------------------------
+ if not debug:
+ return
+
+ jtag_en = ('jtag' in variant) or variant == 'ls180'
+
+ # setup running of DMI FSM
+ dmi_addr = Signal(4)
+ dmi_din = Signal(64)
+ dmi_dout = Signal(64)
+ dmi_wen = Signal(1)
+ dmi_req = Signal(1)
+
+ # debug log out
+ dbg_addr = Signal(4)
+ dbg_dout = Signal(64)
+ dbg_msg = Signal(1)
+
+ # capture pc from dmi
+ pc = Signal(64)
+ active_dbg = Signal()
+ active_dbg_cr = Signal()
+ active_dbg_xer = Signal()
+
+ # xer flags
+ xer_so = Signal()
+ xer_ca = Signal()
+ xer_ca32 = Signal()
+ xer_ov = Signal()
+ xer_ov32 = Signal()
+
+ # increment counter, Stop after 100000 cycles
+ uptime = Signal(64)
+ self.sync += uptime.eq(uptime + 1)
+ #self.sync += If(uptime == 1000000000000, Finish())
+
+ # DMI FSM counter and FSM itself
+ dmicount = Signal(10)
+ dmirunning = Signal(1)
+ dmi_monitor = Signal(1)
+ dmifsm = FSM()
+ self.submodules += dmifsm
+
+ # DMI FSM
+ dmifsm.act("START",
+ If(dmi_req & dmi_wen,
+ (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
+ self.cpu.dmi_din.eq(dmi_din), # DMI in
+ self.cpu.dmi_req.eq(1), # DMI request
+ self.cpu.dmi_wr.eq(1), # DMI write
+ If(self.cpu.dmi_ack,
+ (NextState("IDLE"),
+ )
+ ),
+ ),
+ ),
+ If(dmi_req & ~dmi_wen,
+ (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
+ self.cpu.dmi_req.eq(1), # DMI request
+ self.cpu.dmi_wr.eq(0), # DMI read
+ If(self.cpu.dmi_ack,
+ # acknowledge received: capture data.
+ (NextState("IDLE"),
+ NextValue(dbg_addr, dmi_addr),
+ NextValue(dbg_dout, self.cpu.dmi_dout),
+ NextValue(dbg_msg, 1),
+ ),
+ ),
+ ),
+ )
+ )
+
+ # DMI response received: reset the dmi request and check if
+ # in "monitor" mode
+ dmifsm.act("IDLE",
+ If(dmi_monitor,
+ NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
+ ).Else(
+ NextState("START"), # back to start on next cycle
+ ),
+ NextValue(dmi_req, 0),
+ NextValue(dmi_addr, 0),
+ NextValue(dmi_din, 0),
+ NextValue(dmi_wen, 0),
+ )
+
+ # "monitor" mode fires off a STAT request
+ dmifsm.act("FIRE_MONITOR",
+ (NextValue(dmi_req, 1),
+ NextValue(dmi_addr, 1), # DMI STAT address
+ NextValue(dmi_din, 0),
+ NextValue(dmi_wen, 0), # read STAT
+ NextState("START"), # back to start on next cycle
+ )
+ )
+
+ self.comb += xer_so.eq((dbg_dout & 1) == 1)
+ self.comb += xer_ca.eq((dbg_dout & 4) == 4)
+ self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
+ self.comb += xer_ov.eq((dbg_dout & 16) == 16)
+ self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
+
+ # debug messages out
+ self.sync += If(dbg_msg,
+ (If(active_dbg & (dbg_addr == 0b10), # PC
+ Display("pc : %016x", dbg_dout),
+ ),
+ If(dbg_addr == 0b10, # PC
+ pc.eq(dbg_dout), # capture PC
+ ),
+ #If(dbg_addr == 0b11, # MSR
+ # Display(" msr: %016x", dbg_dout),
+ #),
+ If(dbg_addr == 0b1000, # CR
+ Display(" cr : %016x", dbg_dout),
+ ),
+ If(dbg_addr == 0b1001, # XER
+ Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
+ xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
+ ),
+ If(dbg_addr == 0b101, # GPR
+ Display(" gpr: %016x", dbg_dout),
+ ),
+ # also check if this is a "stat"
+ If(dbg_addr == 1, # requested a STAT
+ #Display(" stat: %x", dbg_dout),
+ If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
+ dmirunning.eq(1), # continue running
+ dmi_monitor.eq(0), # and stop monitor mode
+ ),
+ ),
+ dbg_msg.eq(0)
+ )
+ )
+
+ # kick off a "stop"
+ self.sync += If(uptime == 0,
+ (dmi_addr.eq(0), # CTRL
+ dmi_din.eq(1<<0), # STOP
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ )
+ )
+
+ self.sync += If(uptime == 4,
+ dmirunning.eq(1),
+ )
+
+ self.sync += If(dmirunning,
+ dmicount.eq(dmicount + 1),
+ )
+
+ # loop every 1<<N cycles
+ cyclewid = 9
+
+ # get the PC
+ self.sync += If(dmicount == 4,
+ (dmi_addr.eq(0b10), # NIA
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # kick off a "step"
+ self.sync += If(dmicount == 8,
+ (dmi_addr.eq(0), # CTRL
+ dmi_din.eq(1<<3), # STEP
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ dmirunning.eq(0), # stop counter, need to fire "monitor"
+ dmi_monitor.eq(1), # start "monitor" instead
+ )
+ )
+
+ # limit range of pc for debug reporting
+ #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
+ #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
+ self.comb += active_dbg.eq(1)
+
+
+ # get the MSR
+ self.sync += If(active_dbg & (dmicount == 12),
+ (dmi_addr.eq(0b11), # MSR
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ if cpu == "libresoc":
+ #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
+ self.comb += active_dbg_cr.eq(0)
+
+ # get the CR
+ self.sync += If(active_dbg_cr & (dmicount == 16),
+ (dmi_addr.eq(0b1000), # CR
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
+ self.comb += active_dbg_xer.eq(active_dbg_cr)
+
+ # get the CR
+ self.sync += If(active_dbg_xer & (dmicount == 20),
+ (dmi_addr.eq(0b1001), # XER
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # read all 32 GPRs
+ for i in range(32):
+ self.sync += If(active_dbg & (dmicount == 24+(i*8)),
+ (dmi_addr.eq(0b100), # GSPR addr
+ dmi_din.eq(i), # r1
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ )
+ )
+
+ self.sync += If(active_dbg & (dmicount == 28+(i*8)),
+ (dmi_addr.eq(0b101), # GSPR data
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # monitor bbus read/write
+ self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
+ Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
+ #uptime,
+ 0,
+ self.cpu.dbus.adr,
+ self.cpu.dbus.we,
+ self.cpu.dbus.sel,
+ self.cpu.dbus.dat_w,
+ self.cpu.dbus.dat_r
+ )
+ )
+
+ return
+
+ # monitor ibus write
+ self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
+ self.cpu.ibus.we,
+ Display(" [%06x] iadr: %8x, s %01x w %016x",
+ #uptime,
+ 0,
+ self.cpu.ibus.adr,
+ self.cpu.ibus.sel,
+ self.cpu.ibus.dat_w,
+ )
+ )
+ # monitor ibus read
+ self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
+ ~self.cpu.ibus.we,
+ Display(" [%06x] iadr: %8x, s %01x r %016x",
+ #uptime,
+ 0,
+ self.cpu.ibus.adr,
+ self.cpu.ibus.sel,
+ self.cpu.ibus.dat_r
+ )
+ )
+
+# Build -----------------------------------------------------------------------
+
+def main():
+ parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
+ parser.add_argument("--cpu", default="libresoc",
+ help="CPU to use: libresoc (default) or microwatt")
+ parser.add_argument("--platform", default="sim",
+ help="platform (sim or ls180)")
+ parser.add_argument("--debug", action="store_true",
+ help="Enable debug traces")
+ parser.add_argument("--trace", action="store_true",
+ help="Enable tracing")
+ parser.add_argument("--trace-start", default=0,
+ help="Cycle to start FST tracing")
+ parser.add_argument("--trace-end", default=-1,
+ help="Cycle to end FST tracing")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ args = parser.parse_args()
+
+
+ if args.platform == 'ls180':
+ soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
+ platform=args.platform)
+ builder = Builder(soc, compile_gateware = True)
+ builder.build(run = True)
+ os.chdir("../")
+ else:
+
+ sim_config = SimConfig(default_clk="sys_clk")
+ sim_config.add_module("serial2console", "serial")
+
+ for i in range(2):
+ soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
+ platform=args.platform)
+ builder = Builder(soc, compile_gateware = i!=0)
+ builder.build(sim_config=sim_config,
+ run = i!=0,
+ trace = args.trace,
+ trace_start = int(args.trace_start),
+ trace_end = int(args.trace_end),
+ trace_fst = 0)
+ os.chdir("../")
+
+if __name__ == "__main__":
+ main()
--- /dev/null
+from microwatt.core import Microwatt
--- /dev/null
+.section .text, "ax", @progbits
+.global boot_helper
+boot_helper:
+ nop # FIXME
--- /dev/null
+# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019 Benjamin Herrenschmidt <benh@ozlabs.org>
+# License: BSD
+
+import os
+
+from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
+
+from litex.soc.interconnect import wishbone
+from litex.soc.cores.cpu import CPU
+
+
+CPU_VARIANTS = ["standard"]
+
+
+class Microwatt(CPU):
+ name = "microwatt"
+ human_name = "Microwatt"
+ variants = CPU_VARIANTS
+ data_width = 64
+ endianness = "little"
+ gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
+ linker_output_format = "elf64-powerpcle"
+ nop = "nop"
+ io_regions = {0xc0000000: 0x10000000} # origin, length
+
+ @property
+ def mem_map(self):
+ return {"csr": 0xc0000000}
+
+ @property
+ def gcc_flags(self):
+ flags = "-m64 "
+ flags += "-mabi=elfv2 "
+ flags += "-msoft-float "
+ flags += "-mno-string "
+ flags += "-mno-multiple "
+ flags += "-mno-vsx "
+ flags += "-mno-altivec "
+ flags += "-mlittle-endian "
+ flags += "-mstrict-align "
+ flags += "-fno-stack-protector "
+ flags += "-mcmodel=small "
+ flags += "-D__microwatt__ "
+ return flags
+
+ def __init__(self, platform, variant="standard"):
+ self.platform = platform
+ self.variant = variant
+ self.reset = Signal()
+ self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
+ self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
+ self.periph_buses = [ibus, dbus]
+ self.memory_buses = []
+
+ self.dmi_addr = Signal(4)
+ self.dmi_din = Signal(64)
+ self.dmi_dout = Signal(64)
+ self.dmi_wr = Signal(1)
+ self.dmi_ack = Signal(1)
+ self.dmi_req = Signal(1)
+
+ # # #
+
+ self.cpu_params = dict(
+ # Clock / Reset
+ i_clk = ClockSignal(),
+ i_rst = ResetSignal() | self.reset,
+
+ # Wishbone instruction bus
+ i_wishbone_insn_dat_r = ibus.dat_r,
+ i_wishbone_insn_ack = ibus.ack,
+ i_wishbone_insn_stall = ibus.cyc & ~ibus.ack, # No burst support
+
+ o_wishbone_insn_adr = Cat(Signal(3), ibus.adr),
+ o_wishbone_insn_dat_w = ibus.dat_w,
+ o_wishbone_insn_cyc = ibus.cyc,
+ o_wishbone_insn_stb = ibus.stb,
+ o_wishbone_insn_sel = ibus.sel,
+ o_wishbone_insn_we = ibus.we,
+
+ # Wishbone data bus
+ i_wishbone_data_dat_r = dbus.dat_r,
+ i_wishbone_data_ack = dbus.ack,
+ i_wishbone_data_stall = dbus.cyc & ~dbus.ack, # No burst support
+
+ o_wishbone_data_adr = Cat(Signal(3), dbus.adr),
+ o_wishbone_data_dat_w = dbus.dat_w,
+ o_wishbone_data_cyc = dbus.cyc,
+ o_wishbone_data_stb = dbus.stb,
+ o_wishbone_data_sel = dbus.sel,
+ o_wishbone_data_we = dbus.we,
+
+
+ # Debug bus
+ i_dmi_addr = self.dmi_addr,
+ i_dmi_din = self.dmi_din,
+ o_dmi_dout = self.dmi_dout,
+ i_dmi_req = self.dmi_req,
+ i_dmi_wr = self.dmi_wr,
+ o_dmi_ack = self.dmi_ack,
+ )
+
+ # add vhdl sources
+ self.add_sources(platform)
+
+ def set_reset_address(self, reset_address):
+ assert not hasattr(self, "reset_address")
+ self.reset_address = reset_address
+ assert reset_address == 0x00000000
+
+ @staticmethod
+ def add_sources(platform):
+ cdir = os.path.dirname(__file__)
+ platform.add_source(os.path.join(cdir, "microwatt.v"))
+
+ def do_finalize(self):
+ self.specials += Instance("microwatt_wrapper", **self.cpu_params)
--- /dev/null
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define FIXUP_ENDIAN \
+ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
+ b 191f; /* Skip trampoline if endian is good */ \
+ .long 0xa600607d; /* mfmsr r11 */ \
+ .long 0x01006b69; /* xori r11,r11,1 */ \
+ .long 0x05009f42; /* bcl 20,31,$+4 */ \
+ .long 0xa602487d; /* mflr r10 */ \
+ .long 0x14004a39; /* addi r10,r10,20 */ \
+ .long 0xa64b5a7d; /* mthsrr0 r10 */ \
+ .long 0xa64b7b7d; /* mthsrr1 r11 */ \
+ .long 0x2402004c; /* hrfid */ \
+191:
+
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e) \
+ lis r,(e)@highest; \
+ ori r,r,(e)@higher; \
+ rldicr r,r, 32, 31; \
+ oris r,r, (e)@h; \
+ ori r,r, (e)@l;
+
+ . = 0
+.global _start
+_start:
+ FIXUP_ENDIAN
+
+ /* setup stack */
+ LOAD_IMM64(%r1, _fstack - 0x100)
+ LOAD_IMM64(%r12, main)
+ mtctr %r12,
+ bctrl
+ b .
+
+#define EXCEPTION(nr) \
+ .= nr; \
+ b .
+
+ /* More exception stubs */
+ EXCEPTION(0x100)
+ EXCEPTION(0x200)
+ EXCEPTION(0x300)
+ EXCEPTION(0x380)
+ EXCEPTION(0x400)
+ EXCEPTION(0x480)
+ EXCEPTION(0x500)
+ EXCEPTION(0x600)
+ EXCEPTION(0x700)
+ EXCEPTION(0x800)
+ EXCEPTION(0x900)
+ EXCEPTION(0x980)
+ EXCEPTION(0xa00)
+ EXCEPTION(0xb00)
+ EXCEPTION(0xc00)
+ EXCEPTION(0xd00)
+ EXCEPTION(0xe00)
+ EXCEPTION(0xe20)
+ EXCEPTION(0xe40)
+ EXCEPTION(0xe60)
+ EXCEPTION(0xe80)
+ EXCEPTION(0xf00)
+ EXCEPTION(0xf20)
+ EXCEPTION(0xf40)
+ EXCEPTION(0xf60)
+ EXCEPTION(0xf80)
+#if 0
+ EXCEPTION(0x1000)
+ EXCEPTION(0x1100)
+ EXCEPTION(0x1200)
+ EXCEPTION(0x1300)
+ EXCEPTION(0x1400)
+ EXCEPTION(0x1500)
+ EXCEPTION(0x1600)
+#endif
+
+ .text
+
--- /dev/null
+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline unsigned int irq_getie(void)
+{
+ return 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+ /*if(ie) csrs(); else csrc();*/
+}
+
+static inline unsigned int irq_getmask(void)
+{
+ unsigned int mask = 0;
+ //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+ return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+ //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+ unsigned int pending = 0;
+ //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+ return pending;
+}
+
+#endif /* __IRQ_H */
--- /dev/null
+/* Generated by Yosys 0.9+3558 (git sha1 c66d1dfa, clang 9.0.1-12 -fPIC -Os) */
+
+module cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+ wire [2047:0] _00_;
+ wire [7:0] _01_;
+ wire [2047:0] _02_;
+ wire [7:0] _03_;
+ wire [2047:0] _04_;
+ wire [7:0] _05_;
+ wire [2047:0] _06_;
+ wire [7:0] _07_;
+ wire [2047:0] _08_;
+ wire [7:0] _09_;
+ wire [2047:0] _10_;
+ wire [7:0] _11_;
+ wire [2047:0] _12_;
+ wire [7:0] _13_;
+ wire [2047:0] _14_;
+ wire [7:0] _15_;
+ input clk;
+ input [7:0] rd_addr;
+ output [63:0] rd_data;
+ input rd_en;
+ input [7:0] wr_addr;
+ input [63:0] wr_data;
+ input [7:0] wr_sel;
+ reg [7:0] \$mem$\17901 [255:0];
+ reg [7:0] \$mem$\17902 [255:0];
+ reg [7:0] \$mem$\17903 [255:0];
+ reg [7:0] \$mem$\17904 [255:0];
+ reg [7:0] \$mem$\17905 [255:0];
+ reg [7:0] \$mem$\17906 [255:0];
+ reg [7:0] \$mem$\17907 [255:0];
+ reg [7:0] \$mem$\17908 [255:0];
+ (* ram_style = "block" *)
+ reg [7:0] \17901 [255:0];
+ reg [7:0] _16_;
+ always @(posedge clk) begin
+ if (rd_en) _16_ <= \17901 [rd_addr];
+ if (wr_sel[0]) \17901 [wr_addr] <= wr_data[7:0];
+ end
+ assign _01_ = _16_;
+ (* ram_style = "block" *)
+ reg [7:0] \17902 [255:0];
+ reg [7:0] _17_;
+ always @(posedge clk) begin
+ if (rd_en) _17_ <= \17902 [rd_addr];
+ if (wr_sel[1]) \17902 [wr_addr] <= wr_data[15:8];
+ end
+ assign _03_ = _17_;
+ (* ram_style = "block" *)
+ reg [7:0] \17903 [255:0];
+ reg [7:0] _18_;
+ always @(posedge clk) begin
+ if (rd_en) _18_ <= \17903 [rd_addr];
+ if (wr_sel[2]) \17903 [wr_addr] <= wr_data[23:16];
+ end
+ assign _05_ = _18_;
+ (* ram_style = "block" *)
+ reg [7:0] \17904 [255:0];
+ reg [7:0] _19_;
+ always @(posedge clk) begin
+ if (rd_en) _19_ <= \17904 [rd_addr];
+ if (wr_sel[3]) \17904 [wr_addr] <= wr_data[31:24];
+ end
+ assign _07_ = _19_;
+ (* ram_style = "block" *)
+ reg [7:0] \17905 [255:0];
+ reg [7:0] _20_;
+ always @(posedge clk) begin
+ if (rd_en) _20_ <= \17905 [rd_addr];
+ if (wr_sel[4]) \17905 [wr_addr] <= wr_data[39:32];
+ end
+ assign _09_ = _20_;
+ (* ram_style = "block" *)
+ reg [7:0] \17906 [255:0];
+ reg [7:0] _21_;
+ always @(posedge clk) begin
+ if (rd_en) _21_ <= \17906 [rd_addr];
+ if (wr_sel[5]) \17906 [wr_addr] <= wr_data[47:40];
+ end
+ assign _11_ = _21_;
+ (* ram_style = "block" *)
+ reg [7:0] \17907 [255:0];
+ reg [7:0] _22_;
+ always @(posedge clk) begin
+ if (rd_en) _22_ <= \17907 [rd_addr];
+ if (wr_sel[6]) \17907 [wr_addr] <= wr_data[55:48];
+ end
+ assign _13_ = _22_;
+ (* ram_style = "block" *)
+ reg [7:0] \17908 [255:0];
+ reg [7:0] _23_;
+ always @(posedge clk) begin
+ if (rd_en) _23_ <= \17908 [rd_addr];
+ if (wr_sel[7]) \17908 [wr_addr] <= wr_data[63:56];
+ end
+ assign _15_ = _23_;
+ assign rd_data = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
+endmodule
+
+module cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
+ reg [63:0] _00_;
+ wire [2047:0] _01_;
+ wire [7:0] _02_;
+ wire [2047:0] _03_;
+ wire [7:0] _04_;
+ wire [2047:0] _05_;
+ wire [7:0] _06_;
+ wire [2047:0] _07_;
+ wire [7:0] _08_;
+ wire [2047:0] _09_;
+ wire [7:0] _10_;
+ wire [2047:0] _11_;
+ wire [7:0] _12_;
+ wire [2047:0] _13_;
+ wire [7:0] _14_;
+ wire [2047:0] _15_;
+ wire [7:0] _16_;
+ input clk;
+ input [7:0] rd_addr;
+ output [63:0] rd_data;
+ input rd_en;
+ input [7:0] wr_addr;
+ input [63:0] wr_data;
+ input [7:0] wr_sel;
+ reg [7:0] \$mem$\20460 [255:0];
+ reg [7:0] \$mem$\20461 [255:0];
+ reg [7:0] \$mem$\20462 [255:0];
+ reg [7:0] \$mem$\20463 [255:0];
+ reg [7:0] \$mem$\20464 [255:0];
+ reg [7:0] \$mem$\20465 [255:0];
+ reg [7:0] \$mem$\20466 [255:0];
+ reg [7:0] \$mem$\20467 [255:0];
+ always @(posedge clk)
+ _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
+ (* ram_style = "block" *)
+ reg [7:0] \20460 [255:0];
+ reg [7:0] _17_;
+ always @(posedge clk) begin
+ if (rd_en) _17_ <= \20460 [rd_addr];
+ if (wr_sel[0]) \20460 [wr_addr] <= wr_data[7:0];
+ end
+ assign _02_ = _17_;
+ (* ram_style = "block" *)
+ reg [7:0] \20461 [255:0];
+ reg [7:0] _18_;
+ always @(posedge clk) begin
+ if (rd_en) _18_ <= \20461 [rd_addr];
+ if (wr_sel[1]) \20461 [wr_addr] <= wr_data[15:8];
+ end
+ assign _04_ = _18_;
+ (* ram_style = "block" *)
+ reg [7:0] \20462 [255:0];
+ reg [7:0] _19_;
+ always @(posedge clk) begin
+ if (rd_en) _19_ <= \20462 [rd_addr];
+ if (wr_sel[2]) \20462 [wr_addr] <= wr_data[23:16];
+ end
+ assign _06_ = _19_;
+ (* ram_style = "block" *)
+ reg [7:0] \20463 [255:0];
+ reg [7:0] _20_;
+ always @(posedge clk) begin
+ if (rd_en) _20_ <= \20463 [rd_addr];
+ if (wr_sel[3]) \20463 [wr_addr] <= wr_data[31:24];
+ end
+ assign _08_ = _20_;
+ (* ram_style = "block" *)
+ reg [7:0] \20464 [255:0];
+ reg [7:0] _21_;
+ always @(posedge clk) begin
+ if (rd_en) _21_ <= \20464 [rd_addr];
+ if (wr_sel[4]) \20464 [wr_addr] <= wr_data[39:32];
+ end
+ assign _10_ = _21_;
+ (* ram_style = "block" *)
+ reg [7:0] \20465 [255:0];
+ reg [7:0] _22_;
+ always @(posedge clk) begin
+ if (rd_en) _22_ <= \20465 [rd_addr];
+ if (wr_sel[5]) \20465 [wr_addr] <= wr_data[47:40];
+ end
+ assign _12_ = _22_;
+ (* ram_style = "block" *)
+ reg [7:0] \20466 [255:0];
+ reg [7:0] _23_;
+ always @(posedge clk) begin
+ if (rd_en) _23_ <= \20466 [rd_addr];
+ if (wr_sel[6]) \20466 [wr_addr] <= wr_data[55:48];
+ end
+ assign _14_ = _23_;
+ (* ram_style = "block" *)
+ reg [7:0] \20467 [255:0];
+ reg [7:0] _24_;
+ always @(posedge clk) begin
+ if (rd_en) _24_ <= \20467 [rd_addr];
+ if (wr_sel[7]) \20467 [wr_addr] <= wr_data[63:56];
+ end
+ assign _16_ = _24_;
+ assign rd_data = _00_;
+endmodule
+
+module control_1(clk, rst, complete_in, valid_in, flush_in, stall_in, sgl_pipe_in, stop_mark_in, gpr_write_valid_in, gpr_write_in, gpr_bypassable, gpr_a_read_valid_in, gpr_a_read_in, gpr_b_read_valid_in, gpr_b_read_in, gpr_c_read_valid_in, gpr_c_read_in, cr_read_in, cr_write_in, valid_out, stall_out, stopped_out, gpr_bypass_a, gpr_bypass_b, gpr_bypass_c);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ reg _08_ = 1'h1;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire [31:0] _13_;
+ wire [2:0] _14_;
+ wire [4:0] _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire [1:0] _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire [1:0] _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire [1:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire [1:0] _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire [1:0] _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire [1:0] _47_;
+ wire _48_;
+ wire _49_;
+ wire [1:0] _50_;
+ wire _51_;
+ wire _52_;
+ wire [31:0] _53_;
+ wire [2:0] _54_;
+ input clk;
+ input complete_in;
+ input cr_read_in;
+ wire cr_stall_out;
+ input cr_write_in;
+ wire cr_write_valid;
+ input flush_in;
+ input [5:0] gpr_a_read_in;
+ input gpr_a_read_valid_in;
+ input [5:0] gpr_b_read_in;
+ input gpr_b_read_valid_in;
+ output gpr_bypass_a;
+ output gpr_bypass_b;
+ output gpr_bypass_c;
+ input gpr_bypassable;
+ input [4:0] gpr_c_read_in;
+ input gpr_c_read_valid_in;
+ input [5:0] gpr_write_in;
+ wire gpr_write_valid;
+ input gpr_write_valid_in;
+ reg [4:0] r_int = 5'h00;
+ input rst;
+ input sgl_pipe_in;
+ wire stall_a_out;
+ wire stall_b_out;
+ wire stall_c_out;
+ input stall_in;
+ output stall_out;
+ input stop_mark_in;
+ output stopped_out;
+ input valid_in;
+ output valid_out;
+ assign _03_ = $signed({ r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] }) >= $signed(32'd0);
+ assign _04_ = $signed({ r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] }) <= $signed(32'd2);
+ assign _05_ = _03_ & _04_;
+ assign _06_ = ~ 1'h1;
+ assign _07_ = _06_ | _05_;
+ always @(posedge clk)
+ _08_ <= _07_;
+ always @(posedge clk)
+ r_int <= { _54_, _50_ };
+ assign _09_ = ~ flush_in;
+ assign _10_ = valid_in & _09_;
+ assign _11_ = ~ stall_in;
+ assign _12_ = _10_ & _11_;
+ assign _13_ = { r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4], r_int[4:2] } - 32'd1;
+ assign _14_ = complete_in ? _13_[2:0] : r_int[4:2];
+ assign _15_ = rst ? 5'h00 : { _14_, r_int[1:0] };
+ assign _16_ = rst ? 1'h0 : _12_;
+ assign _17_ = rst ? 1'h0 : stall_in;
+ assign _18_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
+ assign _19_ = stop_mark_in & _18_;
+ assign _20_ = _19_ ? 1'h1 : 1'h0;
+ assign _21_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } != 32'd0;
+ assign _22_ = _21_ ? 2'h1 : 2'h2;
+ assign _23_ = _21_ ? 1'h1 : _17_;
+ assign _24_ = stall_a_out | stall_b_out;
+ assign _25_ = _24_ | stall_c_out;
+ assign _26_ = _25_ | cr_stall_out;
+ assign _27_ = _29_ ? _22_ : _15_[1:0];
+ assign _28_ = sgl_pipe_in ? _23_ : _26_;
+ assign _29_ = _16_ & sgl_pipe_in;
+ assign _30_ = _16_ ? _28_ : _17_;
+ assign _31_ = r_int[1:0] == 2'h0;
+ assign _32_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
+ assign _33_ = _32_ ? 2'h2 : _15_[1:0];
+ assign _34_ = _32_ ? _17_ : 1'h1;
+ assign _35_ = r_int[1:0] == 2'h1;
+ assign _36_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } == 32'd0;
+ assign _37_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } != 32'd0;
+ assign _38_ = _37_ ? 2'h1 : 2'h2;
+ assign _39_ = _37_ ? 1'h1 : _17_;
+ assign _40_ = stall_a_out | stall_b_out;
+ assign _41_ = _40_ | stall_c_out;
+ assign _42_ = _41_ | cr_stall_out;
+ assign _43_ = _45_ ? _38_ : 2'h0;
+ assign _44_ = sgl_pipe_in ? _39_ : _42_;
+ assign _45_ = _16_ & sgl_pipe_in;
+ assign _46_ = _16_ ? _44_ : _17_;
+ assign _47_ = _36_ ? _43_ : _15_[1:0];
+ assign _48_ = _36_ ? _46_ : 1'h1;
+ assign _49_ = r_int[1:0] == 2'h2;
+ function [1:0] \18110 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \18110 = b[1:0];
+ 3'b?1?:
+ \18110 = b[3:2];
+ 3'b1??:
+ \18110 = b[5:4];
+ default:
+ \18110 = a;
+ endcase
+ endfunction
+ assign _50_ = \18110 (2'hx, { _47_, _33_, _27_ }, { _49_, _35_, _31_ });
+ function [0:0] \18113 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \18113 = b[0:0];
+ 3'b?1?:
+ \18113 = b[1:1];
+ 3'b1??:
+ \18113 = b[2:2];
+ default:
+ \18113 = a;
+ endcase
+ endfunction
+ assign _51_ = \18113 (1'hx, { _48_, _34_, _30_ }, { _49_, _35_, _31_ });
+ assign _52_ = _51_ ? 1'h0 : _16_;
+ assign _53_ = { _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4], _15_[4:2] } + 32'd1;
+ assign gpr_write_valid = _52_ ? gpr_write_valid_in : 1'h0;
+ assign cr_write_valid = _52_ ? cr_write_in : 1'h0;
+ assign _54_ = _52_ ? _53_[2:0] : _15_[4:2];
+ cr_hazard_1 cr_hazard0 (
+ .clk(clk),
+ .cr_read_in(cr_read_in),
+ .cr_write_in(cr_write_valid),
+ .stall_in(stall_in),
+ .stall_out(cr_stall_out)
+ );
+ gpr_hazard_1 gpr_hazard0 (
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .gpr_read_in(gpr_a_read_in),
+ .gpr_read_valid_in(gpr_a_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .stall_in(stall_in),
+ .stall_out(stall_a_out),
+ .use_bypass(_00_)
+ );
+ gpr_hazard_1 gpr_hazard1 (
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .gpr_read_in(gpr_b_read_in),
+ .gpr_read_valid_in(gpr_b_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .stall_in(stall_in),
+ .stall_out(stall_b_out),
+ .use_bypass(_01_)
+ );
+ gpr_hazard_1 gpr_hazard2 (
+ .bypass_avail(gpr_bypassable),
+ .clk(clk),
+ .gpr_read_in({ 1'h0, gpr_c_read_in }),
+ .gpr_read_valid_in(gpr_c_read_valid_in),
+ .gpr_write_in(gpr_write_in),
+ .gpr_write_valid_in(gpr_write_valid),
+ .stall_in(stall_in),
+ .stall_out(stall_c_out),
+ .use_bypass(_02_)
+ );
+ assign valid_out = _52_;
+ assign stall_out = _51_;
+ assign stopped_out = _20_;
+ assign gpr_bypass_a = _00_;
+ assign gpr_bypass_b = _01_;
+ assign gpr_bypass_c = _02_;
+endmodule
+
+module core_71ba14ecdd9e9507b1aeafd985ac12164cac4c4e(clk, rst, alt_reset, wishbone_insn_in, wishbone_data_in, dmi_addr, dmi_din, dmi_req, dmi_wr, ext_irq, wishbone_insn_out, wishbone_data_out, dmi_dout, dmi_ack, terminated_out);
+ wire [106:0] _0_;
+ wire _1_;
+ wire [106:0] _2_;
+ wire [63:0] _3_;
+ wire _4_;
+ wire _5_;
+ input alt_reset;
+ reg alt_reset_d;
+ input clk;
+ wire complete;
+ wire core_rst;
+ wire [36:0] cr_file_to_decode2;
+ wire dbg_core_is_stopped;
+ wire dbg_core_rst;
+ wire dbg_core_stop;
+ wire dbg_gpr_ack;
+ wire [5:0] dbg_gpr_addr;
+ wire [63:0] dbg_gpr_data;
+ wire dbg_gpr_req;
+ wire dbg_icache_rst;
+ wire dcache_stall_out;
+ wire [67:0] dcache_to_loadstore1;
+ wire [66:0] dcache_to_mmu;
+ wire [147:0] decode1_to_decode2;
+ wire decode2_stall_in;
+ wire decode2_stall_out;
+ wire decode2_to_cr_file;
+ wire [374:0] decode2_to_execute1;
+ wire [19:0] decode2_to_register_file;
+ output dmi_ack;
+ input [3:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ input dmi_req;
+ input dmi_wr;
+ wire ex1_icache_inval;
+ wire ex1_stall_out;
+ wire [66:0] execute1_to_fetch1;
+ wire [321:0] execute1_to_loadstore1;
+ wire [190:0] execute1_to_writeback;
+ input ext_irq;
+ wire fetch1_stall_in;
+ wire [67:0] fetch1_to_icache;
+ wire [98:0] fetch2_to_decode1;
+ wire flush;
+ wire icache_stall_out;
+ wire [98:0] icache_to_fetch2;
+ wire [142:0] loadstore1_to_dcache;
+ wire [6:0] loadstore1_to_execute1;
+ wire [144:0] loadstore1_to_mmu;
+ wire [77:0] loadstore1_to_writeback;
+ wire ls1_stall_out;
+ wire [131:0] mmu_to_dcache;
+ wire [130:0] mmu_to_icache;
+ wire [69:0] mmu_to_loadstore1;
+ wire [63:0] msr;
+ wire [191:0] register_file_to_decode2;
+ input rst;
+ reg rst_dbg = 1'h1;
+ reg rst_dcache = 1'h1;
+ reg rst_dec1 = 1'h1;
+ reg rst_dec2 = 1'h1;
+ reg rst_ex1 = 1'h1;
+ reg rst_fetch1 = 1'h1;
+ reg rst_fetch2 = 1'h1;
+ reg rst_icache = 1'h1;
+ reg rst_ls1 = 1'h1;
+ wire sim_cr_dump;
+ wire terminate;
+ output terminated_out;
+ input [65:0] wishbone_data_in;
+ output [106:0] wishbone_data_out;
+ input [65:0] wishbone_insn_in;
+ output [106:0] wishbone_insn_out;
+ wire [46:0] writeback_to_cr_file;
+ wire [70:0] writeback_to_register_file;
+ assign decode2_stall_in = ex1_stall_out | ls1_stall_out;
+ assign core_rst = dbg_core_rst | rst;
+ always @(posedge clk)
+ rst_fetch1 <= core_rst;
+ always @(posedge clk)
+ rst_fetch2 <= core_rst;
+ always @(posedge clk)
+ rst_icache <= core_rst;
+ always @(posedge clk)
+ rst_dcache <= core_rst;
+ always @(posedge clk)
+ rst_dec1 <= core_rst;
+ always @(posedge clk)
+ rst_dec2 <= core_rst;
+ always @(posedge clk)
+ rst_ex1 <= core_rst;
+ always @(posedge clk)
+ rst_ls1 <= core_rst;
+ always @(posedge clk)
+ rst_dbg <= rst;
+ always @(posedge clk)
+ alt_reset_d <= alt_reset;
+ assign fetch1_stall_in = icache_stall_out | decode2_stall_out;
+ assign _1_ = dbg_icache_rst | ex1_icache_inval;
+ cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f cr_file_0 (
+ .clk(clk),
+ .d_in(decode2_to_cr_file),
+ .d_out(cr_file_to_decode2),
+ .sim_dump(sim_cr_dump),
+ .w_in(writeback_to_cr_file)
+ );
+ dcache_64_32_2_64_2_12 dcache_0 (
+ .clk(clk),
+ .d_in(loadstore1_to_dcache),
+ .d_out(dcache_to_loadstore1),
+ .m_in(mmu_to_dcache),
+ .m_out(dcache_to_mmu),
+ .rst(rst_dcache),
+ .stall_out(dcache_stall_out),
+ .wishbone_in(wishbone_data_in),
+ .wishbone_out(_2_)
+ );
+ core_debug debug_0 (
+ .clk(clk),
+ .core_rst(dbg_core_rst),
+ .core_stop(dbg_core_stop),
+ .core_stopped(dbg_core_is_stopped),
+ .dbg_gpr_ack(dbg_gpr_ack),
+ .dbg_gpr_addr(dbg_gpr_addr),
+ .dbg_gpr_data(dbg_gpr_data),
+ .dbg_gpr_req(dbg_gpr_req),
+ .dmi_ack(_4_),
+ .dmi_addr(dmi_addr),
+ .dmi_din(dmi_din),
+ .dmi_dout(_3_),
+ .dmi_req(dmi_req),
+ .dmi_wr(dmi_wr),
+ .icache_rst(dbg_icache_rst),
+ .msr(msr),
+ .nia(fetch1_to_icache[67:4]),
+ .rst(rst_dbg),
+ .terminate(terminate),
+ .terminated_out(_5_)
+ );
+ decode1 decode1_0 (
+ .clk(clk),
+ .d_out(decode1_to_decode2),
+ .f_in(fetch2_to_decode1),
+ .flush_in(flush),
+ .rst(rst_dec1),
+ .stall_in(decode2_stall_out)
+ );
+ decode2_bf8b4530d8d246dd74ac53a13471bba17941dff7 decode2_0 (
+ .c_in(cr_file_to_decode2),
+ .c_out(decode2_to_cr_file),
+ .clk(clk),
+ .complete_in(complete),
+ .d_in(decode1_to_decode2),
+ .e_out(decode2_to_execute1),
+ .flush_in(flush),
+ .r_in(register_file_to_decode2),
+ .r_out(decode2_to_register_file),
+ .rst(rst_dec2),
+ .stall_in(decode2_stall_in),
+ .stall_out(decode2_stall_out),
+ .stopped_out(dbg_core_is_stopped)
+ );
+ execute1_bf8b4530d8d246dd74ac53a13471bba17941dff7 execute1_0 (
+ .clk(clk),
+ .dbg_msr_out(msr),
+ .e_in(decode2_to_execute1),
+ .e_out(execute1_to_writeback),
+ .ext_irq_in(ext_irq),
+ .f_out(execute1_to_fetch1),
+ .flush_out(flush),
+ .icache_inval(ex1_icache_inval),
+ .l_in(loadstore1_to_execute1),
+ .l_out(execute1_to_loadstore1),
+ .rst(rst_ex1),
+ .stall_out(ex1_stall_out),
+ .terminate_out(terminate)
+ );
+ fetch1_3f28fda38b1ec2f6fdb16c0bce5a53c28d1424e5 fetch1_0 (
+ .alt_reset_in(alt_reset_d),
+ .clk(clk),
+ .e_in(execute1_to_fetch1),
+ .flush_in(flush),
+ .i_out(fetch1_to_icache),
+ .rst(rst_fetch1),
+ .stall_in(fetch1_stall_in),
+ .stop_in(dbg_core_stop)
+ );
+ fetch2 fetch2_0 (
+ .clk(clk),
+ .f_out(fetch2_to_decode1),
+ .flush_in(flush),
+ .i_in(icache_to_fetch2),
+ .rst(rst_fetch2),
+ .stall_in(decode2_stall_out)
+ );
+ icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f icache_0 (
+ .clk(clk),
+ .flush_in(flush),
+ .i_in(fetch1_to_icache),
+ .i_out(icache_to_fetch2),
+ .inval_in(_1_),
+ .m_in(mmu_to_icache),
+ .rst(rst_icache),
+ .stall_out(icache_stall_out),
+ .wishbone_in(wishbone_insn_in),
+ .wishbone_out(_0_)
+ );
+ loadstore1 loadstore1_0 (
+ .clk(clk),
+ .d_in(dcache_to_loadstore1),
+ .d_out(loadstore1_to_dcache),
+ .dc_stall(dcache_stall_out),
+ .e_out(loadstore1_to_execute1),
+ .l_in(execute1_to_loadstore1),
+ .l_out(loadstore1_to_writeback),
+ .m_in(mmu_to_loadstore1),
+ .m_out(loadstore1_to_mmu),
+ .rst(rst_ls1),
+ .stall_out(ls1_stall_out)
+ );
+ mmu mmu_0 (
+ .clk(clk),
+ .d_in(dcache_to_mmu),
+ .d_out(mmu_to_dcache),
+ .i_out(mmu_to_icache),
+ .l_in(loadstore1_to_mmu),
+ .l_out(mmu_to_loadstore1),
+ .rst(core_rst)
+ );
+ register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0 (
+ .clk(clk),
+ .d_in(decode2_to_register_file),
+ .d_out(register_file_to_decode2),
+ .dbg_gpr_ack(dbg_gpr_ack),
+ .dbg_gpr_addr(dbg_gpr_addr),
+ .dbg_gpr_data(dbg_gpr_data),
+ .dbg_gpr_req(dbg_gpr_req),
+ .sim_dump(terminate),
+ .sim_dump_done(sim_cr_dump),
+ .w_in(writeback_to_register_file)
+ );
+ writeback writeback_0 (
+ .c_out(writeback_to_cr_file),
+ .clk(clk),
+ .complete_out(complete),
+ .e_in(execute1_to_writeback),
+ .l_in(loadstore1_to_writeback),
+ .w_out(writeback_to_register_file)
+ );
+ assign wishbone_insn_out = _0_;
+ assign wishbone_data_out = _2_;
+ assign dmi_dout = _3_;
+ assign dmi_ack = _4_;
+ assign terminated_out = _5_;
+endmodule
+
+module core_debug(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_stopped, nia, msr, dbg_gpr_ack, dbg_gpr_data, dmi_dout, dmi_ack, core_stop, core_rst, icache_rst, dbg_gpr_req, dbg_gpr_addr, terminated_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire [63:0] _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire [5:0] _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire [5:0] _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire [5:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire [5:0] _48_;
+ wire _49_;
+ wire _50_;
+ input clk;
+ output core_rst;
+ output core_stop;
+ input core_stopped;
+ input dbg_gpr_ack;
+ output [5:0] dbg_gpr_addr;
+ input [63:0] dbg_gpr_data;
+ output dbg_gpr_req;
+ output dmi_ack;
+ input [3:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ input dmi_req;
+ reg dmi_req_1;
+ input dmi_wr;
+ reg do_icreset;
+ reg do_reset;
+ reg do_step;
+ reg [5:0] gspr_index;
+ output icache_rst;
+ input [63:0] msr;
+ input [63:0] nia;
+ input rst;
+ reg stopping;
+ input terminate;
+ reg terminated;
+ output terminated_out;
+ assign _00_ = dmi_addr != 4'h5;
+ assign _01_ = _00_ ? dmi_req : dbg_gpr_ack;
+ assign _02_ = dmi_addr == 4'h5;
+ assign _03_ = _02_ ? dmi_req : 1'h0;
+ assign _04_ = dmi_addr == 4'h1;
+ assign _05_ = dmi_addr == 4'h2;
+ assign _06_ = dmi_addr == 4'h3;
+ assign _07_ = dmi_addr == 4'h5;
+ function [63:0] \17699 ;
+ input [63:0] a;
+ input [255:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \17699 = b[63:0];
+ 4'b??1?:
+ \17699 = b[127:64];
+ 4'b?1??:
+ \17699 = b[191:128];
+ 4'b1???:
+ \17699 = b[255:192];
+ default:
+ \17699 = a;
+ endcase
+ endfunction
+ assign _08_ = \17699 (64'h0000000000000000, { dbg_gpr_data, msr, nia, 61'h0000000000000000, terminated, core_stopped, stopping }, { _07_, _06_, _05_, _04_ });
+ assign _09_ = ~ dmi_req_1;
+ assign _10_ = dmi_req & _09_;
+ assign _11_ = dmi_addr == 4'h0;
+ assign _12_ = dmi_din[1] ? 1'h1 : 1'h0;
+ assign _13_ = dmi_din[1] ? 1'h0 : terminated;
+ assign _14_ = dmi_din[0] ? 1'h1 : stopping;
+ assign _15_ = dmi_din[3] ? 1'h1 : 1'h0;
+ assign _16_ = dmi_din[3] ? 1'h0 : _13_;
+ assign _17_ = dmi_din[2] ? 1'h1 : 1'h0;
+ assign _18_ = dmi_din[4] ? 1'h0 : _14_;
+ assign _19_ = dmi_din[4] ? 1'h0 : _16_;
+ assign _20_ = dmi_addr == 4'h4;
+ assign _21_ = _20_ ? dmi_din[5:0] : gspr_index;
+ assign _22_ = _34_ ? _18_ : stopping;
+ assign _23_ = _11_ ? _15_ : 1'h0;
+ assign _24_ = _11_ ? _12_ : 1'h0;
+ assign _25_ = _11_ ? _17_ : 1'h0;
+ assign _26_ = _38_ ? _19_ : terminated;
+ assign _27_ = _11_ ? gspr_index : _21_;
+ assign _28_ = dmi_wr & _11_;
+ assign _29_ = dmi_wr ? _23_ : 1'h0;
+ assign _30_ = dmi_wr ? _24_ : 1'h0;
+ assign _31_ = dmi_wr ? _25_ : 1'h0;
+ assign _32_ = dmi_wr & _11_;
+ assign _33_ = _39_ ? _27_ : gspr_index;
+ assign _34_ = _10_ & _28_;
+ assign _35_ = _10_ ? _29_ : 1'h0;
+ assign _36_ = _10_ ? _30_ : 1'h0;
+ assign _37_ = _10_ ? _31_ : 1'h0;
+ assign _38_ = _10_ & _32_;
+ assign _39_ = _10_ & dmi_wr;
+ assign _40_ = terminate ? 1'h1 : _22_;
+ assign _41_ = terminate ? 1'h1 : _26_;
+ assign _42_ = rst ? dmi_req_1 : dmi_req;
+ assign _43_ = rst ? 1'h0 : _40_;
+ assign _44_ = rst ? 1'h0 : _35_;
+ assign _45_ = rst ? 1'h0 : _36_;
+ assign _46_ = rst ? 1'h0 : _37_;
+ assign _47_ = rst ? 1'h0 : _41_;
+ assign _48_ = rst ? gspr_index : _33_;
+ always @(posedge clk)
+ dmi_req_1 <= _42_;
+ always @(posedge clk)
+ stopping <= _43_;
+ always @(posedge clk)
+ do_step <= _44_;
+ always @(posedge clk)
+ do_reset <= _45_;
+ always @(posedge clk)
+ do_icreset <= _46_;
+ always @(posedge clk)
+ terminated <= _47_;
+ always @(posedge clk)
+ gspr_index <= _48_;
+ assign _49_ = ~ do_step;
+ assign _50_ = stopping & _49_;
+ assign dmi_dout = _08_;
+ assign dmi_ack = _01_;
+ assign core_stop = _50_;
+ assign core_rst = do_reset;
+ assign icache_rst = do_icreset;
+ assign dbg_gpr_req = _03_;
+ assign dbg_gpr_addr = gspr_index;
+ assign terminated_out = terminated;
+endmodule
+
+module cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, sim_dump, d_out);
+ wire [3:0] _0_;
+ wire [3:0] _1_;
+ wire [3:0] _2_;
+ wire [3:0] _3_;
+ wire [3:0] _4_;
+ wire [3:0] _5_;
+ wire [3:0] _6_;
+ wire [3:0] _7_;
+ wire [31:0] _8_;
+ wire [4:0] _9_;
+ input clk;
+ reg [31:0] crs = 32'd0;
+ input d_in;
+ output [36:0] d_out;
+ input sim_dump;
+ input [46:0] w_in;
+ reg [4:0] xerc = 5'h00;
+ wire [4:0] xerc_updated;
+ assign _0_ = w_in[1] ? w_in[12:9] : crs[3:0];
+ assign _1_ = w_in[2] ? w_in[16:13] : crs[7:4];
+ assign _2_ = w_in[3] ? w_in[20:17] : crs[11:8];
+ assign _3_ = w_in[4] ? w_in[24:21] : crs[15:12];
+ assign _4_ = w_in[5] ? w_in[28:25] : crs[19:16];
+ assign _5_ = w_in[6] ? w_in[32:29] : crs[23:20];
+ assign _6_ = w_in[7] ? w_in[36:33] : crs[27:24];
+ assign _7_ = w_in[8] ? w_in[40:37] : crs[31:28];
+ assign xerc_updated = w_in[41] ? w_in[46:42] : xerc;
+ assign _8_ = w_in[0] ? { _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ } : crs;
+ always @(posedge clk)
+ crs <= _8_;
+ assign _9_ = w_in[41] ? xerc_updated : xerc;
+ always @(posedge clk)
+ xerc <= _9_;
+ assign d_out = { xerc_updated, _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
+endmodule
+
+module cr_hazard_1(clk, stall_in, cr_read_in, cr_write_in, stall_out);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ wire _4_;
+ wire _5_;
+ input clk;
+ input cr_read_in;
+ input cr_write_in;
+ reg r = 1'h0;
+ input stall_in;
+ output stall_out;
+ assign _0_ = ~ stall_in;
+ assign _1_ = _0_ ? cr_write_in : r;
+ always @(posedge clk)
+ r <= _1_;
+ assign _2_ = r == cr_read_in;
+ assign _3_ = _2_ ? 1'h1 : 1'h0;
+ assign _4_ = ~ cr_read_in;
+ assign _5_ = _4_ ? 1'h0 : _3_;
+ assign stall_out = _5_;
+endmodule
+
+module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire [146:0] _0007_;
+ wire [146:0] _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire [145:0] _0011_;
+ wire _0012_;
+ reg _0013_ = 1'h1;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire [5:0] _0017_;
+ wire [5:0] _0018_;
+ wire [5:0] _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire _0022_;
+ wire _0023_;
+ wire _0024_;
+ wire _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire [5:0] _0159_;
+ wire [127:0] _0160_;
+ wire [5:0] _0161_;
+ wire _0162_;
+ wire [5:0] _0163_;
+ wire [127:0] _0164_;
+ wire [127:0] _0165_;
+ wire [127:0] _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire [4:0] _0338_;
+ wire _0339_;
+ wire [4:0] _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire [4:0] _0346_;
+ wire _0347_;
+ wire [4:0] _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire [4:0] _0354_;
+ wire _0355_;
+ wire [4:0] _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire [4:0] _0362_;
+ wire _0363_;
+ wire [4:0] _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire [4:0] _0373_;
+ wire _0374_;
+ wire [4:0] _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire [4:0] _0379_;
+ wire _0380_;
+ wire [4:0] _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire [4:0] _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire [2:0] _0404_;
+ wire [2:0] _0405_;
+ wire _0406_;
+ wire [7:0] _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire [58:0] _0419_;
+ wire _0420_;
+ wire [57:0] _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire [1:0] _0432_;
+ wire [63:0] _0433_;
+ wire [65:0] _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire [1:0] _0438_;
+ wire _0439_;
+ wire [63:0] _0440_;
+ wire [67:0] _0441_;
+ wire [65:0] _0442_;
+ wire _0443_;
+ wire [63:0] _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire [63:0] _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire [143:0] _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire [1:0] _0504_;
+ wire [1:0] _0505_;
+ wire _0506_;
+ wire _0507_;
+ reg [145:0] _0508_;
+ reg [2:0] _0509_;
+ wire _0510_;
+ wire [4:0] _0511_;
+ wire _0512_;
+ wire [4:0] _0513_;
+ wire [4:0] _0514_;
+ wire [2879:0] _0515_;
+ wire _0516_;
+ wire [4:0] _0517_;
+ wire [4:0] _0518_;
+ wire [2879:0] _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire [2:0] _0525_;
+ wire [1:0] _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire [4:0] _0529_;
+ wire _0530_;
+ wire [4:0] _0531_;
+ wire [4:0] _0532_;
+ wire [2879:0] _0533_;
+ wire _0534_;
+ wire [4:0] _0535_;
+ wire [4:0] _0536_;
+ wire [2879:0] _0537_;
+ wire [2879:0] _0538_;
+ wire [63:0] _0539_;
+ wire _0540_;
+ wire [2879:0] _0541_;
+ wire [63:0] _0542_;
+ wire _0543_;
+ wire [109:0] _0544_;
+ wire [13:0] _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire [2879:0] _0552_;
+ wire [63:0] _0553_;
+ wire _0554_;
+ wire [2:0] _0555_;
+ wire [31:0] _0556_;
+ wire [63:0] _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire [7:0] _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire [7:0] _0563_;
+ wire [4:0] _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire [2:0] _0573_;
+ wire [31:0] _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire [63:0] _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire [4:0] _0583_;
+ wire [63:0] _0584_;
+ wire [2:0] _0585_;
+ wire _0586_;
+ wire [2:0] _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire [7:0] _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire [63:0] _0598_;
+ wire [64:0] _0599_;
+ wire [2:0] _0600_;
+ wire [1:0] _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire [2879:0] _0605_;
+ wire [63:0] _0606_;
+ wire [63:0] _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire [2:0] _0610_;
+ wire [31:0] _0611_;
+ wire [63:0] _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire [7:0] _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire [7:0] _0618_;
+ wire [4:0] _0619_;
+ wire [2879:0] _0620_;
+ wire [63:0] _0621_;
+ wire [63:0] _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire [34:0] _0625_;
+ wire [63:0] _0626_;
+ wire [1:0] _0627_;
+ wire [22:0] _0628_;
+ reg [189:0] _0629_;
+ wire [5887:0] _0630_;
+ wire [8191:0] _0631_;
+ wire [1:0] _0632_;
+ wire [1:0] _0633_;
+ wire [1:0] _0634_;
+ wire [1:0] _0635_;
+ wire [1:0] _0636_;
+ wire [1:0] _0637_;
+ wire [1:0] _0638_;
+ wire [1:0] _0639_;
+ wire [1:0] _0640_;
+ wire [1:0] _0641_;
+ wire [1:0] _0642_;
+ wire [1:0] _0643_;
+ wire [1:0] _0644_;
+ wire [1:0] _0645_;
+ wire [1:0] _0646_;
+ wire [1:0] _0647_;
+ wire [1:0] _0648_;
+ wire [1:0] _0649_;
+ wire [1:0] _0650_;
+ wire [1:0] _0651_;
+ wire [1:0] _0652_;
+ wire [63:0] _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0960_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0998_;
+ wire _0999_;
+ wire _1000_;
+ wire _1001_;
+ wire _1002_;
+ wire _1003_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
+ wire _1025_;
+ wire _1026_;
+ wire _1027_;
+ wire _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire _1031_;
+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
+ wire _1046_;
+ wire _1047_;
+ wire _1048_;
+ wire _1049_;
+ wire _1050_;
+ wire _1051_;
+ wire _1052_;
+ wire _1053_;
+ wire _1054_;
+ wire _1055_;
+ wire _1056_;
+ wire _1057_;
+ wire _1058_;
+ wire _1059_;
+ wire _1060_;
+ wire _1061_;
+ wire _1062_;
+ wire [45:0] _1063_;
+ wire [45:0] _1064_;
+ wire _1065_;
+ wire [63:0] _1066_;
+ wire [63:0] _1067_;
+ wire _1068_;
+ wire _1069_;
+ wire _1070_;
+ wire _1071_;
+ wire _1072_;
+ wire _1073_;
+ wire _1074_;
+ wire _1075_;
+ wire _1076_;
+ wire _1077_;
+ wire _1078_;
+ wire _1079_;
+ wire _1080_;
+ wire _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1089_;
+ wire _1090_;
+ wire _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1097_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire _1128_;
+ wire _1129_;
+ wire _1130_;
+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire _1151_;
+ wire _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1159_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1164_;
+ wire _1165_;
+ wire _1166_;
+ wire _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1188_;
+ wire _1189_;
+ wire _1190_;
+ wire _1191_;
+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
+ wire _1199_;
+ wire _1200_;
+ wire _1201_;
+ wire _1202_;
+ wire _1203_;
+ wire _1204_;
+ wire _1205_;
+ wire _1206_;
+ wire _1207_;
+ wire _1208_;
+ wire _1209_;
+ wire _1210_;
+ wire _1211_;
+ wire _1212_;
+ wire _1213_;
+ wire _1214_;
+ wire _1215_;
+ wire _1216_;
+ wire _1217_;
+ wire _1218_;
+ wire _1219_;
+ wire _1220_;
+ wire _1221_;
+ wire _1222_;
+ wire _1223_;
+ wire _1224_;
+ wire _1225_;
+ wire _1226_;
+ wire _1227_;
+ wire _1228_;
+ wire _1229_;
+ wire _1230_;
+ wire _1231_;
+ wire _1232_;
+ wire _1233_;
+ wire _1234_;
+ wire _1235_;
+ wire _1236_;
+ wire _1237_;
+ wire _1238_;
+ wire _1239_;
+ wire _1240_;
+ wire _1241_;
+ wire _1242_;
+ wire _1243_;
+ wire _1244_;
+ wire _1245_;
+ wire _1246_;
+ wire _1247_;
+ wire _1248_;
+ wire _1249_;
+ wire _1250_;
+ wire _1251_;
+ wire _1252_;
+ wire _1253_;
+ wire _1254_;
+ wire _1255_;
+ wire _1256_;
+ wire _1257_;
+ wire _1258_;
+ wire _1259_;
+ wire _1260_;
+ wire _1261_;
+ wire _1262_;
+ wire _1263_;
+ wire _1264_;
+ wire _1265_;
+ wire _1266_;
+ wire _1267_;
+ wire _1268_;
+ wire _1269_;
+ wire _1270_;
+ wire _1271_;
+ wire _1272_;
+ wire _1273_;
+ wire _1274_;
+ wire _1275_;
+ wire _1276_;
+ wire _1277_;
+ wire _1278_;
+ wire _1279_;
+ wire _1280_;
+ wire _1281_;
+ wire _1282_;
+ wire _1283_;
+ wire _1284_;
+ wire _1285_;
+ wire _1286_;
+ wire _1287_;
+ wire _1288_;
+ wire _1289_;
+ wire _1290_;
+ wire _1291_;
+ wire _1292_;
+ wire _1293_;
+ wire _1294_;
+ wire _1295_;
+ wire _1296_;
+ wire _1297_;
+ wire _1298_;
+ wire _1299_;
+ wire _1300_;
+ wire _1301_;
+ wire _1302_;
+ wire _1303_;
+ wire _1304_;
+ wire _1305_;
+ wire _1306_;
+ wire _1307_;
+ wire _1308_;
+ wire _1309_;
+ wire _1310_;
+ wire _1311_;
+ wire _1312_;
+ wire _1313_;
+ wire _1314_;
+ wire _1315_;
+ wire _1316_;
+ wire _1317_;
+ wire _1318_;
+ wire _1319_;
+ wire _1320_;
+ wire _1321_;
+ wire _1322_;
+ wire _1323_;
+ wire _1324_;
+ wire _1325_;
+ wire _1326_;
+ wire _1327_;
+ wire _1328_;
+ wire _1329_;
+ wire _1330_;
+ wire _1331_;
+ wire _1332_;
+ wire _1333_;
+ wire _1334_;
+ wire _1335_;
+ wire _1336_;
+ wire _1337_;
+ wire _1338_;
+ wire _1339_;
+ wire _1340_;
+ wire _1341_;
+ wire _1342_;
+ wire _1343_;
+ wire _1344_;
+ wire _1345_;
+ wire _1346_;
+ wire _1347_;
+ wire _1348_;
+ wire _1349_;
+ wire _1350_;
+ wire _1351_;
+ wire _1352_;
+ wire _1353_;
+ wire _1354_;
+ wire _1355_;
+ wire _1356_;
+ wire _1357_;
+ wire _1358_;
+ wire _1359_;
+ wire _1360_;
+ wire _1361_;
+ wire _1362_;
+ wire _1363_;
+ wire _1364_;
+ wire _1365_;
+ wire _1366_;
+ wire _1367_;
+ wire _1368_;
+ wire _1369_;
+ wire _1370_;
+ wire _1371_;
+ wire _1372_;
+ wire _1373_;
+ wire _1374_;
+ wire _1375_;
+ wire _1376_;
+ wire _1377_;
+ wire _1378_;
+ wire _1379_;
+ wire _1380_;
+ wire _1381_;
+ wire _1382_;
+ wire _1383_;
+ wire _1384_;
+ wire _1385_;
+ wire _1386_;
+ wire _1387_;
+ wire _1388_;
+ wire _1389_;
+ wire _1390_;
+ wire _1391_;
+ wire _1392_;
+ wire _1393_;
+ wire _1394_;
+ wire _1395_;
+ wire _1396_;
+ wire _1397_;
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+ wire _1403_;
+ wire _1404_;
+ wire _1405_;
+ wire _1406_;
+ wire _1407_;
+ wire _1408_;
+ wire _1409_;
+ wire _1410_;
+ wire _1411_;
+ wire _1412_;
+ wire _1413_;
+ wire _1414_;
+ wire _1415_;
+ wire _1416_;
+ wire _1417_;
+ wire _1418_;
+ wire _1419_;
+ wire _1420_;
+ wire _1421_;
+ wire _1422_;
+ wire _1423_;
+ wire _1424_;
+ wire _1425_;
+ wire _1426_;
+ wire _1427_;
+ wire _1428_;
+ wire _1429_;
+ wire _1430_;
+ wire _1431_;
+ wire _1432_;
+ wire _1433_;
+ wire _1434_;
+ wire _1435_;
+ wire _1436_;
+ wire _1437_;
+ wire _1438_;
+ wire _1439_;
+ wire _1440_;
+ wire _1441_;
+ wire _1442_;
+ wire _1443_;
+ wire _1444_;
+ wire _1445_;
+ wire _1446_;
+ wire _1447_;
+ wire _1448_;
+ wire _1449_;
+ wire _1450_;
+ wire _1451_;
+ wire _1452_;
+ wire _1453_;
+ wire _1454_;
+ wire _1455_;
+ wire _1456_;
+ wire _1457_;
+ wire _1458_;
+ wire _1459_;
+ wire _1460_;
+ wire _1461_;
+ wire _1462_;
+ wire _1463_;
+ wire _1464_;
+ wire _1465_;
+ wire [89:0] _1466_;
+ wire [89:0] _1467_;
+ wire [89:0] _1468_;
+ wire [89:0] _1469_;
+ wire [89:0] _1470_;
+ wire [89:0] _1471_;
+ wire [89:0] _1472_;
+ wire [89:0] _1473_;
+ wire [89:0] _1474_;
+ wire [89:0] _1475_;
+ wire [89:0] _1476_;
+ wire _1477_;
+ wire _1478_;
+ wire _1479_;
+ wire _1480_;
+ wire _1481_;
+ wire _1482_;
+ wire _1483_;
+ wire _1484_;
+ wire _1485_;
+ wire _1486_;
+ wire _1487_;
+ wire [89:0] _1488_;
+ wire [89:0] _1489_;
+ wire [89:0] _1490_;
+ wire [89:0] _1491_;
+ wire [89:0] _1492_;
+ wire [89:0] _1493_;
+ wire [89:0] _1494_;
+ wire [89:0] _1495_;
+ wire [89:0] _1496_;
+ wire [89:0] _1497_;
+ wire [89:0] _1498_;
+ wire _1499_;
+ wire _1500_;
+ wire _1501_;
+ wire _1502_;
+ wire _1503_;
+ wire _1504_;
+ wire _1505_;
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+ wire [89:0] _1511_;
+ wire [89:0] _1512_;
+ wire [89:0] _1513_;
+ wire [89:0] _1514_;
+ wire [89:0] _1515_;
+ wire [89:0] _1516_;
+ wire [89:0] _1517_;
+ wire [89:0] _1518_;
+ wire [89:0] _1519_;
+ wire [89:0] _1520_;
+ wire _1521_;
+ wire _1522_;
+ wire _1523_;
+ wire _1524_;
+ wire _1525_;
+ wire _1526_;
+ wire _1527_;
+ wire _1528_;
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+ wire _1530_;
+ wire _1531_;
+ wire [89:0] _1532_;
+ wire [89:0] _1533_;
+ wire [89:0] _1534_;
+ wire [89:0] _1535_;
+ wire [89:0] _1536_;
+ wire [89:0] _1537_;
+ wire [89:0] _1538_;
+ wire [89:0] _1539_;
+ wire [89:0] _1540_;
+ wire [89:0] _1541_;
+ wire [89:0] _1542_;
+ wire _1543_;
+ wire _1544_;
+ wire _1545_;
+ wire _1546_;
+ wire _1547_;
+ wire _1548_;
+ wire _1549_;
+ wire _1550_;
+ wire _1551_;
+ wire _1552_;
+ wire _1553_;
+ wire _1554_;
+ wire _1555_;
+ wire [89:0] _1556_;
+ wire [89:0] _1557_;
+ wire [89:0] _1558_;
+ wire [89:0] _1559_;
+ wire [89:0] _1560_;
+ wire [89:0] _1561_;
+ wire [89:0] _1562_;
+ wire [89:0] _1563_;
+ wire [89:0] _1564_;
+ wire [89:0] _1565_;
+ wire [89:0] _1566_;
+ wire _1567_;
+ wire _1568_;
+ wire _1569_;
+ wire _1570_;
+ wire _1571_;
+ wire _1572_;
+ wire _1573_;
+ wire _1574_;
+ wire _1575_;
+ wire _1576_;
+ wire _1577_;
+ wire [89:0] _1578_;
+ wire [89:0] _1579_;
+ wire [89:0] _1580_;
+ wire [89:0] _1581_;
+ wire [89:0] _1582_;
+ wire [89:0] _1583_;
+ wire [89:0] _1584_;
+ wire [89:0] _1585_;
+ wire [89:0] _1586_;
+ wire [89:0] _1587_;
+ wire [89:0] _1588_;
+ wire _1589_;
+ wire _1590_;
+ wire _1591_;
+ wire _1592_;
+ wire _1593_;
+ wire _1594_;
+ wire _1595_;
+ wire _1596_;
+ wire _1597_;
+ wire _1598_;
+ wire [63:0] _1599_;
+ wire [63:0] _1600_;
+ wire _1601_;
+ wire _1602_;
+ wire _1603_;
+ wire _1604_;
+ wire _1605_;
+ wire _1606_;
+ wire _1607_;
+ wire _1608_;
+ wire _1609_;
+ wire _1610_;
+ wire _1611_;
+ wire _1612_;
+ wire _1613_;
+ wire _1614_;
+ wire _1615_;
+ wire _1616_;
+ wire _1617_;
+ wire _1618_;
+ wire _1619_;
+ wire _1620_;
+ wire _1621_;
+ wire _1622_;
+ wire _1623_;
+ wire _1624_;
+ wire _1625_;
+ wire _1626_;
+ wire _1627_;
+ wire _1628_;
+ wire _1629_;
+ wire _1630_;
+ wire _1631_;
+ wire _1632_;
+ wire _1633_;
+ wire _1634_;
+ wire _1635_;
+ wire _1636_;
+ wire _1637_;
+ wire _1638_;
+ wire _1639_;
+ wire _1640_;
+ wire _1641_;
+ wire _1642_;
+ wire _1643_;
+ wire _1644_;
+ wire _1645_;
+ wire _1646_;
+ wire _1647_;
+ wire _1648_;
+ wire _1649_;
+ wire _1650_;
+ wire _1651_;
+ wire _1652_;
+ wire _1653_;
+ wire _1654_;
+ wire _1655_;
+ wire _1656_;
+ wire _1657_;
+ wire _1658_;
+ wire _1659_;
+ wire _1660_;
+ wire _1661_;
+ wire _1662_;
+ wire _1663_;
+ wire _1664_;
+ wire _1665_;
+ wire _1666_;
+ wire _1667_;
+ wire _1668_;
+ wire _1669_;
+ wire _1670_;
+ wire _1671_;
+ wire _1672_;
+ wire _1673_;
+ wire _1674_;
+ wire _1675_;
+ wire _1676_;
+ wire _1677_;
+ wire _1678_;
+ wire _1679_;
+ wire _1680_;
+ wire _1681_;
+ wire _1682_;
+ wire _1683_;
+ wire _1684_;
+ wire _1685_;
+ wire _1686_;
+ wire _1687_;
+ wire _1688_;
+ wire _1689_;
+ wire _1690_;
+ wire _1691_;
+ wire _1692_;
+ wire _1693_;
+ wire _1694_;
+ wire _1695_;
+ wire _1696_;
+ wire _1697_;
+ wire _1698_;
+ wire _1699_;
+ wire _1700_;
+ wire _1701_;
+ wire _1702_;
+ wire _1703_;
+ wire _1704_;
+ wire _1705_;
+ wire _1706_;
+ wire _1707_;
+ wire _1708_;
+ wire _1709_;
+ wire _1710_;
+ wire _1711_;
+ wire _1712_;
+ wire _1713_;
+ wire _1714_;
+ wire _1715_;
+ wire _1716_;
+ wire _1717_;
+ wire _1718_;
+ wire _1719_;
+ wire _1720_;
+ wire _1721_;
+ wire _1722_;
+ wire _1723_;
+ wire _1724_;
+ wire _1725_;
+ wire _1726_;
+ wire _1727_;
+ wire _1728_;
+ wire _1729_;
+ wire _1730_;
+ wire _1731_;
+ wire _1732_;
+ wire _1733_;
+ wire _1734_;
+ wire _1735_;
+ wire _1736_;
+ wire _1737_;
+ wire _1738_;
+ wire _1739_;
+ wire _1740_;
+ wire _1741_;
+ wire _1742_;
+ wire _1743_;
+ wire _1744_;
+ wire _1745_;
+ wire _1746_;
+ wire _1747_;
+ wire _1748_;
+ wire _1749_;
+ wire _1750_;
+ wire _1751_;
+ wire _1752_;
+ wire _1753_;
+ wire _1754_;
+ wire _1755_;
+ wire _1756_;
+ wire _1757_;
+ wire _1758_;
+ wire _1759_;
+ wire _1760_;
+ wire _1761_;
+ wire _1762_;
+ wire _1763_;
+ wire _1764_;
+ wire _1765_;
+ wire _1766_;
+ wire _1767_;
+ wire _1768_;
+ wire _1769_;
+ wire _1770_;
+ wire _1771_;
+ wire _1772_;
+ wire _1773_;
+ wire _1774_;
+ wire _1775_;
+ wire _1776_;
+ wire _1777_;
+ wire _1778_;
+ wire _1779_;
+ wire _1780_;
+ wire _1781_;
+ wire _1782_;
+ wire _1783_;
+ wire _1784_;
+ wire _1785_;
+ wire _1786_;
+ wire _1787_;
+ wire _1788_;
+ wire _1789_;
+ wire _1790_;
+ wire _1791_;
+ wire _1792_;
+ wire _1793_;
+ wire _1794_;
+ wire [89:0] _1795_;
+ wire [89:0] _1796_;
+ wire [89:0] _1797_;
+ wire [89:0] _1798_;
+ wire [89:0] _1799_;
+ wire [89:0] _1800_;
+ wire [89:0] _1801_;
+ wire [89:0] _1802_;
+ wire [89:0] _1803_;
+ wire [89:0] _1804_;
+ wire [89:0] _1805_;
+ wire _1806_;
+ wire _1807_;
+ wire _1808_;
+ wire _1809_;
+ wire _1810_;
+ wire _1811_;
+ wire _1812_;
+ wire _1813_;
+ wire _1814_;
+ wire _1815_;
+ wire _1816_;
+ wire _1817_;
+ wire _1818_;
+ wire _1819_;
+ wire _1820_;
+ wire _1821_;
+ wire _1822_;
+ wire _1823_;
+ wire _1824_;
+ wire _1825_;
+ wire _1826_;
+ wire _1827_;
+ wire _1828_;
+ wire _1829_;
+ wire _1830_;
+ wire _1831_;
+ wire _1832_;
+ wire _1833_;
+ wire _1834_;
+ wire _1835_;
+ wire _1836_;
+ wire _1837_;
+ wire _1838_;
+ wire _1839_;
+ wire _1840_;
+ wire _1841_;
+ wire _1842_;
+ wire _1843_;
+ wire _1844_;
+ wire _1845_;
+ wire _1846_;
+ wire _1847_;
+ wire _1848_;
+ wire _1849_;
+ wire _1850_;
+ wire _1851_;
+ wire _1852_;
+ wire _1853_;
+ wire _1854_;
+ wire _1855_;
+ wire _1856_;
+ wire _1857_;
+ wire _1858_;
+ wire _1859_;
+ wire _1860_;
+ wire _1861_;
+ wire _1862_;
+ wire _1863_;
+ wire _1864_;
+ wire _1865_;
+ wire _1866_;
+ wire _1867_;
+ wire _1868_;
+ wire _1869_;
+ wire _1870_;
+ wire [89:0] _1871_;
+ wire [89:0] _1872_;
+ wire [89:0] _1873_;
+ wire [89:0] _1874_;
+ wire [89:0] _1875_;
+ wire [89:0] _1876_;
+ wire [89:0] _1877_;
+ wire [89:0] _1878_;
+ wire [89:0] _1879_;
+ wire [89:0] _1880_;
+ wire [89:0] _1881_;
+ wire [89:0] _1882_;
+ wire [89:0] _1883_;
+ wire [89:0] _1884_;
+ wire [89:0] _1885_;
+ wire [89:0] _1886_;
+ wire [89:0] _1887_;
+ wire [89:0] _1888_;
+ wire [89:0] _1889_;
+ wire [89:0] _1890_;
+ wire [89:0] _1891_;
+ wire [89:0] _1892_;
+ wire [89:0] _1893_;
+ wire [89:0] _1894_;
+ wire [89:0] _1895_;
+ wire [89:0] _1896_;
+ wire [89:0] _1897_;
+ wire [89:0] _1898_;
+ wire [89:0] _1899_;
+ wire [89:0] _1900_;
+ wire [89:0] _1901_;
+ wire [89:0] _1902_;
+ wire [89:0] _1903_;
+ wire [89:0] _1904_;
+ wire [89:0] _1905_;
+ wire [89:0] _1906_;
+ wire [89:0] _1907_;
+ wire [89:0] _1908_;
+ wire [89:0] _1909_;
+ wire [89:0] _1910_;
+ wire [89:0] _1911_;
+ wire [89:0] _1912_;
+ wire [89:0] _1913_;
+ wire _1914_;
+ wire _1915_;
+ wire _1916_;
+ wire _1917_;
+ wire _1918_;
+ wire _1919_;
+ wire _1920_;
+ wire _1921_;
+ wire _1922_;
+ wire _1923_;
+ wire _1924_;
+ wire _1925_;
+ wire _1926_;
+ wire _1927_;
+ wire _1928_;
+ wire _1929_;
+ wire _1930_;
+ wire _1931_;
+ wire _1932_;
+ wire _1933_;
+ wire _1934_;
+ wire _1935_;
+ wire _1936_;
+ wire _1937_;
+ wire _1938_;
+ wire _1939_;
+ wire _1940_;
+ wire _1941_;
+ wire _1942_;
+ wire _1943_;
+ wire _1944_;
+ wire _1945_;
+ wire _1946_;
+ wire _1947_;
+ wire _1948_;
+ wire _1949_;
+ wire _1950_;
+ wire _1951_;
+ wire _1952_;
+ wire _1953_;
+ wire _1954_;
+ wire _1955_;
+ wire _1956_;
+ wire _1957_;
+ wire _1958_;
+ wire _1959_;
+ wire _1960_;
+ wire _1961_;
+ wire _1962_;
+ wire _1963_;
+ wire _1964_;
+ wire _1965_;
+ wire _1966_;
+ wire _1967_;
+ wire _1968_;
+ wire _1969_;
+ wire _1970_;
+ wire _1971_;
+ wire _1972_;
+ wire _1973_;
+ wire _1974_;
+ wire _1975_;
+ wire _1976_;
+ wire _1977_;
+ wire _1978_;
+ wire [89:0] _1979_;
+ wire [89:0] _1980_;
+ wire [89:0] _1981_;
+ wire [89:0] _1982_;
+ wire [89:0] _1983_;
+ wire [89:0] _1984_;
+ wire [89:0] _1985_;
+ wire [89:0] _1986_;
+ wire [89:0] _1987_;
+ wire [89:0] _1988_;
+ wire [89:0] _1989_;
+ wire [89:0] _1990_;
+ wire [89:0] _1991_;
+ wire [89:0] _1992_;
+ wire [89:0] _1993_;
+ wire [89:0] _1994_;
+ wire [89:0] _1995_;
+ wire [89:0] _1996_;
+ wire [89:0] _1997_;
+ wire [89:0] _1998_;
+ wire [89:0] _1999_;
+ wire [89:0] _2000_;
+ wire [89:0] _2001_;
+ wire [89:0] _2002_;
+ wire [89:0] _2003_;
+ wire [89:0] _2004_;
+ wire [89:0] _2005_;
+ wire [89:0] _2006_;
+ wire [89:0] _2007_;
+ wire [89:0] _2008_;
+ wire [89:0] _2009_;
+ wire [89:0] _2010_;
+ wire _2011_;
+ wire _2012_;
+ wire _2013_;
+ wire _2014_;
+ wire _2015_;
+ wire _2016_;
+ wire _2017_;
+ wire _2018_;
+ wire _2019_;
+ wire _2020_;
+ wire _2021_;
+ wire _2022_;
+ wire _2023_;
+ wire _2024_;
+ wire _2025_;
+ wire _2026_;
+ wire _2027_;
+ wire _2028_;
+ wire _2029_;
+ wire _2030_;
+ wire _2031_;
+ wire _2032_;
+ wire _2033_;
+ wire _2034_;
+ wire _2035_;
+ wire _2036_;
+ wire _2037_;
+ wire _2038_;
+ wire _2039_;
+ wire _2040_;
+ wire _2041_;
+ wire _2042_;
+ wire _2043_;
+ wire _2044_;
+ wire _2045_;
+ wire _2046_;
+ wire _2047_;
+ wire _2048_;
+ wire _2049_;
+ wire _2050_;
+ wire _2051_;
+ wire _2052_;
+ wire _2053_;
+ wire _2054_;
+ wire _2055_;
+ wire _2056_;
+ wire _2057_;
+ wire _2058_;
+ wire _2059_;
+ wire _2060_;
+ wire _2061_;
+ wire _2062_;
+ wire _2063_;
+ wire _2064_;
+ wire _2065_;
+ wire _2066_;
+ wire _2067_;
+ wire _2068_;
+ wire _2069_;
+ wire _2070_;
+ wire _2071_;
+ wire _2072_;
+ wire _2073_;
+ wire _2074_;
+ wire _2075_;
+ wire _2076_;
+ wire _2077_;
+ wire _2078_;
+ wire _2079_;
+ wire _2080_;
+ wire _2081_;
+ wire _2082_;
+ wire _2083_;
+ wire _2084_;
+ wire _2085_;
+ wire _2086_;
+ wire _2087_;
+ wire _2088_;
+ wire _2089_;
+ wire _2090_;
+ wire _2091_;
+ wire _2092_;
+ wire _2093_;
+ wire _2094_;
+ wire _2095_;
+ wire _2096_;
+ wire _2097_;
+ wire _2098_;
+ wire _2099_;
+ wire _2100_;
+ wire _2101_;
+ wire _2102_;
+ wire _2103_;
+ wire _2104_;
+ wire _2105_;
+ wire _2106_;
+ wire _2107_;
+ wire _2108_;
+ wire _2109_;
+ wire _2110_;
+ wire _2111_;
+ wire _2112_;
+ wire _2113_;
+ wire _2114_;
+ wire _2115_;
+ wire _2116_;
+ wire _2117_;
+ wire _2118_;
+ wire _2119_;
+ wire _2120_;
+ wire _2121_;
+ wire _2122_;
+ wire _2123_;
+ wire _2124_;
+ wire _2125_;
+ wire _2126_;
+ wire _2127_;
+ wire _2128_;
+ wire _2129_;
+ wire _2130_;
+ wire _2131_;
+ wire _2132_;
+ wire _2133_;
+ wire _2134_;
+ wire _2135_;
+ wire _2136_;
+ wire _2137_;
+ wire _2138_;
+ wire _2139_;
+ wire _2140_;
+ wire _2141_;
+ wire _2142_;
+ wire _2143_;
+ wire _2144_;
+ wire _2145_;
+ wire _2146_;
+ wire _2147_;
+ wire _2148_;
+ wire _2149_;
+ wire _2150_;
+ wire _2151_;
+ wire _2152_;
+ wire _2153_;
+ wire _2154_;
+ wire _2155_;
+ wire _2156_;
+ wire _2157_;
+ wire _2158_;
+ wire _2159_;
+ wire _2160_;
+ wire _2161_;
+ wire _2162_;
+ wire _2163_;
+ wire _2164_;
+ wire _2165_;
+ wire _2166_;
+ wire _2167_;
+ wire _2168_;
+ wire _2169_;
+ wire _2170_;
+ wire _2171_;
+ wire _2172_;
+ wire _2173_;
+ wire _2174_;
+ wire _2175_;
+ wire _2176_;
+ wire _2177_;
+ wire _2178_;
+ wire _2179_;
+ wire _2180_;
+ wire _2181_;
+ wire _2182_;
+ wire _2183_;
+ wire _2184_;
+ wire _2185_;
+ wire _2186_;
+ wire _2187_;
+ wire _2188_;
+ wire _2189_;
+ wire _2190_;
+ wire _2191_;
+ wire _2192_;
+ wire _2193_;
+ wire _2194_;
+ wire _2195_;
+ wire _2196_;
+ wire _2197_;
+ wire _2198_;
+ wire _2199_;
+ wire _2200_;
+ wire _2201_;
+ wire _2202_;
+ wire _2203_;
+ wire _2204_;
+ wire [89:0] _2205_;
+ wire [89:0] _2206_;
+ wire [89:0] _2207_;
+ wire [89:0] _2208_;
+ wire [89:0] _2209_;
+ wire [89:0] _2210_;
+ wire [89:0] _2211_;
+ wire [89:0] _2212_;
+ wire [89:0] _2213_;
+ wire [89:0] _2214_;
+ wire [89:0] _2215_;
+ wire _2216_;
+ wire _2217_;
+ wire _2218_;
+ wire _2219_;
+ wire _2220_;
+ wire _2221_;
+ wire _2222_;
+ wire _2223_;
+ wire _2224_;
+ wire _2225_;
+ wire _2226_;
+ wire _2227_;
+ wire _2228_;
+ wire _2229_;
+ wire _2230_;
+ wire _2231_;
+ wire _2232_;
+ wire _2233_;
+ wire _2234_;
+ wire _2235_;
+ wire _2236_;
+ wire _2237_;
+ wire _2238_;
+ wire _2239_;
+ wire _2240_;
+ wire _2241_;
+ wire _2242_;
+ wire _2243_;
+ wire _2244_;
+ wire _2245_;
+ wire _2246_;
+ wire _2247_;
+ wire _2248_;
+ wire _2249_;
+ wire _2250_;
+ wire _2251_;
+ wire _2252_;
+ wire _2253_;
+ wire _2254_;
+ wire _2255_;
+ wire _2256_;
+ wire _2257_;
+ wire _2258_;
+ wire _2259_;
+ wire _2260_;
+ wire _2261_;
+ wire _2262_;
+ wire _2263_;
+ wire _2264_;
+ wire _2265_;
+ wire _2266_;
+ wire _2267_;
+ wire _2268_;
+ wire _2269_;
+ wire _2270_;
+ wire _2271_;
+ wire _2272_;
+ wire _2273_;
+ wire _2274_;
+ wire _2275_;
+ wire _2276_;
+ wire _2277_;
+ wire _2278_;
+ wire _2279_;
+ wire _2280_;
+ wire [89:0] _2281_;
+ wire [89:0] _2282_;
+ wire [89:0] _2283_;
+ wire [89:0] _2284_;
+ wire [89:0] _2285_;
+ wire [89:0] _2286_;
+ wire [89:0] _2287_;
+ wire [89:0] _2288_;
+ wire [89:0] _2289_;
+ wire [89:0] _2290_;
+ wire [89:0] _2291_;
+ wire [89:0] _2292_;
+ wire [89:0] _2293_;
+ wire [89:0] _2294_;
+ wire [89:0] _2295_;
+ wire [89:0] _2296_;
+ wire [89:0] _2297_;
+ wire [89:0] _2298_;
+ wire [89:0] _2299_;
+ wire [89:0] _2300_;
+ wire [89:0] _2301_;
+ wire [89:0] _2302_;
+ wire [89:0] _2303_;
+ wire [89:0] _2304_;
+ wire [89:0] _2305_;
+ wire [89:0] _2306_;
+ wire [89:0] _2307_;
+ wire [89:0] _2308_;
+ wire [89:0] _2309_;
+ wire [89:0] _2310_;
+ wire [89:0] _2311_;
+ wire [89:0] _2312_;
+ wire [89:0] _2313_;
+ wire [89:0] _2314_;
+ wire [89:0] _2315_;
+ wire [89:0] _2316_;
+ wire [89:0] _2317_;
+ wire [89:0] _2318_;
+ wire [89:0] _2319_;
+ wire [89:0] _2320_;
+ wire [89:0] _2321_;
+ wire [89:0] _2322_;
+ wire [89:0] _2323_;
+ wire _2324_;
+ wire _2325_;
+ wire _2326_;
+ wire _2327_;
+ wire _2328_;
+ wire _2329_;
+ wire _2330_;
+ wire _2331_;
+ wire _2332_;
+ wire _2333_;
+ wire _2334_;
+ wire _2335_;
+ wire _2336_;
+ wire _2337_;
+ wire _2338_;
+ wire _2339_;
+ wire _2340_;
+ wire _2341_;
+ wire _2342_;
+ wire _2343_;
+ wire _2344_;
+ wire _2345_;
+ wire _2346_;
+ wire _2347_;
+ wire _2348_;
+ wire _2349_;
+ wire _2350_;
+ wire _2351_;
+ wire _2352_;
+ wire _2353_;
+ wire _2354_;
+ wire _2355_;
+ wire _2356_;
+ wire _2357_;
+ wire _2358_;
+ wire _2359_;
+ wire _2360_;
+ wire _2361_;
+ wire _2362_;
+ wire _2363_;
+ wire _2364_;
+ wire _2365_;
+ wire _2366_;
+ wire _2367_;
+ wire _2368_;
+ wire _2369_;
+ wire _2370_;
+ wire _2371_;
+ wire _2372_;
+ wire _2373_;
+ wire _2374_;
+ wire _2375_;
+ wire _2376_;
+ wire _2377_;
+ wire _2378_;
+ wire _2379_;
+ wire _2380_;
+ wire _2381_;
+ wire _2382_;
+ wire _2383_;
+ wire _2384_;
+ wire _2385_;
+ wire _2386_;
+ wire _2387_;
+ wire _2388_;
+ wire [89:0] _2389_;
+ wire [89:0] _2390_;
+ wire [89:0] _2391_;
+ wire [89:0] _2392_;
+ wire [89:0] _2393_;
+ wire [89:0] _2394_;
+ wire [89:0] _2395_;
+ wire [89:0] _2396_;
+ wire [89:0] _2397_;
+ wire [89:0] _2398_;
+ wire [89:0] _2399_;
+ wire [89:0] _2400_;
+ wire [89:0] _2401_;
+ wire [89:0] _2402_;
+ wire [89:0] _2403_;
+ wire [89:0] _2404_;
+ wire [89:0] _2405_;
+ wire [89:0] _2406_;
+ wire [89:0] _2407_;
+ wire [89:0] _2408_;
+ wire [89:0] _2409_;
+ wire [89:0] _2410_;
+ wire [89:0] _2411_;
+ wire [89:0] _2412_;
+ wire [89:0] _2413_;
+ wire [89:0] _2414_;
+ wire [89:0] _2415_;
+ wire [89:0] _2416_;
+ wire [89:0] _2417_;
+ wire [89:0] _2418_;
+ wire [89:0] _2419_;
+ wire [89:0] _2420_;
+ wire _2421_;
+ wire _2422_;
+ wire _2423_;
+ wire _2424_;
+ wire _2425_;
+ wire _2426_;
+ wire _2427_;
+ wire _2428_;
+ wire _2429_;
+ wire _2430_;
+ wire _2431_;
+ wire _2432_;
+ wire _2433_;
+ wire _2434_;
+ wire _2435_;
+ wire _2436_;
+ wire _2437_;
+ wire _2438_;
+ wire _2439_;
+ wire _2440_;
+ wire _2441_;
+ wire _2442_;
+ wire _2443_;
+ wire _2444_;
+ wire _2445_;
+ wire _2446_;
+ wire _2447_;
+ wire _2448_;
+ wire _2449_;
+ wire _2450_;
+ wire _2451_;
+ wire _2452_;
+ wire _2453_;
+ wire _2454_;
+ wire _2455_;
+ wire _2456_;
+ wire _2457_;
+ wire _2458_;
+ wire _2459_;
+ wire _2460_;
+ wire _2461_;
+ wire _2462_;
+ wire _2463_;
+ wire _2464_;
+ wire _2465_;
+ wire _2466_;
+ wire _2467_;
+ wire _2468_;
+ wire _2469_;
+ wire _2470_;
+ wire _2471_;
+ wire _2472_;
+ wire _2473_;
+ wire _2474_;
+ wire _2475_;
+ wire _2476_;
+ wire _2477_;
+ wire _2478_;
+ wire _2479_;
+ wire _2480_;
+ wire _2481_;
+ wire _2482_;
+ wire _2483_;
+ wire _2484_;
+ wire _2485_;
+ wire _2486_;
+ wire _2487_;
+ wire _2488_;
+ wire _2489_;
+ wire _2490_;
+ wire _2491_;
+ wire _2492_;
+ wire _2493_;
+ wire _2494_;
+ wire _2495_;
+ wire _2496_;
+ wire _2497_;
+ wire _2498_;
+ wire _2499_;
+ wire _2500_;
+ wire _2501_;
+ wire _2502_;
+ wire _2503_;
+ wire _2504_;
+ wire _2505_;
+ wire _2506_;
+ wire _2507_;
+ wire _2508_;
+ wire _2509_;
+ wire _2510_;
+ wire _2511_;
+ wire _2512_;
+ wire _2513_;
+ wire _2514_;
+ wire _2515_;
+ wire _2516_;
+ wire _2517_;
+ wire _2518_;
+ wire _2519_;
+ wire _2520_;
+ wire _2521_;
+ wire _2522_;
+ wire _2523_;
+ wire _2524_;
+ wire _2525_;
+ wire _2526_;
+ wire _2527_;
+ wire _2528_;
+ wire _2529_;
+ wire _2530_;
+ wire _2531_;
+ wire _2532_;
+ wire _2533_;
+ wire _2534_;
+ wire _2535_;
+ wire _2536_;
+ wire _2537_;
+ wire _2538_;
+ wire _2539_;
+ wire _2540_;
+ wire _2541_;
+ wire _2542_;
+ wire _2543_;
+ wire _2544_;
+ wire _2545_;
+ wire _2546_;
+ wire _2547_;
+ wire _2548_;
+ wire _2549_;
+ wire _2550_;
+ wire _2551_;
+ wire _2552_;
+ wire _2553_;
+ wire _2554_;
+ wire _2555_;
+ wire _2556_;
+ wire _2557_;
+ wire _2558_;
+ wire _2559_;
+ wire _2560_;
+ wire _2561_;
+ wire _2562_;
+ wire _2563_;
+ wire _2564_;
+ wire _2565_;
+ wire _2566_;
+ wire _2567_;
+ wire _2568_;
+ wire _2569_;
+ wire _2570_;
+ wire _2571_;
+ wire _2572_;
+ wire _2573_;
+ wire _2574_;
+ wire _2575_;
+ wire _2576_;
+ wire _2577_;
+ wire _2578_;
+ wire _2579_;
+ wire _2580_;
+ wire _2581_;
+ wire _2582_;
+ wire _2583_;
+ wire _2584_;
+ wire _2585_;
+ wire _2586_;
+ wire _2587_;
+ wire _2588_;
+ wire _2589_;
+ wire _2590_;
+ wire _2591_;
+ wire _2592_;
+ wire _2593_;
+ wire _2594_;
+ wire _2595_;
+ wire _2596_;
+ wire _2597_;
+ wire _2598_;
+ wire _2599_;
+ wire _2600_;
+ wire _2601_;
+ wire _2602_;
+ wire _2603_;
+ wire _2604_;
+ wire _2605_;
+ wire _2606_;
+ wire _2607_;
+ wire _2608_;
+ wire _2609_;
+ wire _2610_;
+ wire _2611_;
+ wire _2612_;
+ wire _2613_;
+ wire _2614_;
+ wire [1:0] _2615_;
+ wire [1:0] _2616_;
+ wire [1:0] _2617_;
+ wire [1:0] _2618_;
+ wire [1:0] _2619_;
+ wire [1:0] _2620_;
+ wire [1:0] _2621_;
+ wire [1:0] _2622_;
+ wire [1:0] _2623_;
+ wire [1:0] _2624_;
+ wire [1:0] _2625_;
+ wire [1:0] _2626_;
+ wire [1:0] _2627_;
+ wire [1:0] _2628_;
+ wire [1:0] _2629_;
+ wire [1:0] _2630_;
+ wire [1:0] _2631_;
+ wire [1:0] _2632_;
+ wire [1:0] _2633_;
+ wire [1:0] _2634_;
+ wire [1:0] _2635_;
+ wire _2636_;
+ wire _2637_;
+ wire _2638_;
+ wire _2639_;
+ wire _2640_;
+ wire _2641_;
+ wire _2642_;
+ wire _2643_;
+ wire _2644_;
+ wire _2645_;
+ wire _2646_;
+ wire _2647_;
+ wire _2648_;
+ wire _2649_;
+ wire _2650_;
+ wire _2651_;
+ wire _2652_;
+ wire _2653_;
+ wire _2654_;
+ wire _2655_;
+ wire _2656_;
+ wire _2657_;
+ wire _2658_;
+ wire _2659_;
+ wire _2660_;
+ wire _2661_;
+ wire _2662_;
+ wire _2663_;
+ wire _2664_;
+ wire _2665_;
+ wire _2666_;
+ wire [89:0] _2667_;
+ wire [89:0] _2668_;
+ wire [89:0] _2669_;
+ wire [89:0] _2670_;
+ wire [89:0] _2671_;
+ wire [89:0] _2672_;
+ wire [89:0] _2673_;
+ wire [89:0] _2674_;
+ wire [89:0] _2675_;
+ wire [89:0] _2676_;
+ wire _2677_;
+ wire _2678_;
+ wire _2679_;
+ wire _2680_;
+ wire _2681_;
+ wire _2682_;
+ wire _2683_;
+ wire _2684_;
+ wire _2685_;
+ wire _2686_;
+ wire [89:0] _2687_;
+ wire [89:0] _2688_;
+ wire [89:0] _2689_;
+ wire [89:0] _2690_;
+ wire [89:0] _2691_;
+ wire [89:0] _2692_;
+ wire [89:0] _2693_;
+ wire [89:0] _2694_;
+ wire [89:0] _2695_;
+ wire [89:0] _2696_;
+ wire _2697_;
+ wire _2698_;
+ wire _2699_;
+ wire _2700_;
+ wire _2701_;
+ wire _2702_;
+ wire _2703_;
+ wire _2704_;
+ wire _2705_;
+ wire _2706_;
+ wire [89:0] _2707_;
+ wire [89:0] _2708_;
+ wire [89:0] _2709_;
+ wire [89:0] _2710_;
+ wire [89:0] _2711_;
+ wire [89:0] _2712_;
+ wire [89:0] _2713_;
+ wire [89:0] _2714_;
+ wire [89:0] _2715_;
+ wire [89:0] _2716_;
+ wire _2717_;
+ wire _2718_;
+ wire _2719_;
+ wire _2720_;
+ wire _2721_;
+ wire _2722_;
+ wire _2723_;
+ wire _2724_;
+ wire _2725_;
+ wire _2726_;
+ wire [89:0] _2727_;
+ wire [89:0] _2728_;
+ wire [89:0] _2729_;
+ wire [89:0] _2730_;
+ wire [89:0] _2731_;
+ wire [89:0] _2732_;
+ wire [89:0] _2733_;
+ wire [89:0] _2734_;
+ wire [89:0] _2735_;
+ wire [89:0] _2736_;
+ wire _2737_;
+ wire _2738_;
+ wire _2739_;
+ wire _2740_;
+ wire _2741_;
+ wire _2742_;
+ wire _2743_;
+ wire _2744_;
+ wire _2745_;
+ wire _2746_;
+ wire [89:0] _2747_;
+ wire [89:0] _2748_;
+ wire [89:0] _2749_;
+ wire [89:0] _2750_;
+ wire [89:0] _2751_;
+ wire [89:0] _2752_;
+ wire [89:0] _2753_;
+ wire [89:0] _2754_;
+ wire [89:0] _2755_;
+ wire [89:0] _2756_;
+ wire _2757_;
+ wire _2758_;
+ wire _2759_;
+ wire _2760_;
+ wire _2761_;
+ wire _2762_;
+ wire _2763_;
+ wire _2764_;
+ wire _2765_;
+ wire _2766_;
+ wire [89:0] _2767_;
+ wire [89:0] _2768_;
+ wire [89:0] _2769_;
+ wire [89:0] _2770_;
+ wire [89:0] _2771_;
+ wire [89:0] _2772_;
+ wire [89:0] _2773_;
+ wire [89:0] _2774_;
+ wire [89:0] _2775_;
+ wire [89:0] _2776_;
+ wire _2777_;
+ wire _2778_;
+ wire _2779_;
+ wire _2780_;
+ wire _2781_;
+ wire _2782_;
+ wire _2783_;
+ wire _2784_;
+ wire _2785_;
+ wire _2786_;
+ wire [89:0] _2787_;
+ wire [89:0] _2788_;
+ wire [89:0] _2789_;
+ wire [89:0] _2790_;
+ wire [89:0] _2791_;
+ wire [89:0] _2792_;
+ wire [89:0] _2793_;
+ wire [89:0] _2794_;
+ wire [89:0] _2795_;
+ wire [89:0] _2796_;
+ wire [89:0] _2797_;
+ wire [89:0] _2798_;
+ wire [89:0] _2799_;
+ wire [89:0] _2800_;
+ wire [89:0] _2801_;
+ wire [89:0] _2802_;
+ wire [89:0] _2803_;
+ wire [89:0] _2804_;
+ wire [89:0] _2805_;
+ wire [89:0] _2806_;
+ wire [89:0] _2807_;
+ wire [89:0] _2808_;
+ wire [89:0] _2809_;
+ wire [89:0] _2810_;
+ wire [89:0] _2811_;
+ wire [89:0] _2812_;
+ wire [89:0] _2813_;
+ wire [89:0] _2814_;
+ wire [89:0] _2815_;
+ wire [89:0] _2816_;
+ wire [89:0] _2817_;
+ wire [89:0] _2818_;
+ wire [89:0] _2819_;
+ wire [89:0] _2820_;
+ wire [89:0] _2821_;
+ wire [89:0] _2822_;
+ wire [89:0] _2823_;
+ wire [89:0] _2824_;
+ wire [89:0] _2825_;
+ wire [89:0] _2826_;
+ wire [1:0] _2827_;
+ wire [1:0] _2828_;
+ wire [1:0] _2829_;
+ wire [1:0] _2830_;
+ wire [1:0] _2831_;
+ wire [1:0] _2832_;
+ wire [1:0] _2833_;
+ wire [1:0] _2834_;
+ wire [1:0] _2835_;
+ wire [1:0] _2836_;
+ wire [1:0] _2837_;
+ wire [1:0] _2838_;
+ wire [1:0] _2839_;
+ wire [1:0] _2840_;
+ wire [1:0] _2841_;
+ wire [1:0] _2842_;
+ wire [1:0] _2843_;
+ wire [1:0] _2844_;
+ wire [1:0] _2845_;
+ wire [1:0] _2846_;
+ wire [1:0] _2847_;
+ wire _2848_;
+ wire _2849_;
+ wire _2850_;
+ wire _2851_;
+ wire _2852_;
+ wire _2853_;
+ wire _2854_;
+ wire _2855_;
+ wire _2856_;
+ wire _2857_;
+ wire _2858_;
+ wire _2859_;
+ wire _2860_;
+ wire _2861_;
+ wire _2862_;
+ wire _2863_;
+ wire _2864_;
+ wire _2865_;
+ wire _2866_;
+ wire _2867_;
+ wire _2868_;
+ wire _2869_;
+ wire _2870_;
+ wire _2871_;
+ wire _2872_;
+ wire _2873_;
+ wire _2874_;
+ wire _2875_;
+ wire _2876_;
+ wire _2877_;
+ wire _2878_;
+ wire [89:0] _2879_;
+ wire [89:0] _2880_;
+ wire [89:0] _2881_;
+ wire [89:0] _2882_;
+ wire [89:0] _2883_;
+ wire [89:0] _2884_;
+ wire [89:0] _2885_;
+ wire [89:0] _2886_;
+ wire [89:0] _2887_;
+ wire [89:0] _2888_;
+ wire _2889_;
+ wire _2890_;
+ wire _2891_;
+ wire _2892_;
+ wire _2893_;
+ wire _2894_;
+ wire _2895_;
+ wire _2896_;
+ wire _2897_;
+ wire _2898_;
+ wire [89:0] _2899_;
+ wire [89:0] _2900_;
+ wire [89:0] _2901_;
+ wire [89:0] _2902_;
+ wire [89:0] _2903_;
+ wire [89:0] _2904_;
+ wire [89:0] _2905_;
+ wire [89:0] _2906_;
+ wire [89:0] _2907_;
+ wire [89:0] _2908_;
+ wire _2909_;
+ wire _2910_;
+ wire _2911_;
+ wire _2912_;
+ wire _2913_;
+ wire _2914_;
+ wire _2915_;
+ wire _2916_;
+ wire _2917_;
+ wire _2918_;
+ wire [89:0] _2919_;
+ wire [89:0] _2920_;
+ wire [89:0] _2921_;
+ wire [89:0] _2922_;
+ wire [89:0] _2923_;
+ wire [89:0] _2924_;
+ wire [89:0] _2925_;
+ wire [89:0] _2926_;
+ wire [89:0] _2927_;
+ wire [89:0] _2928_;
+ wire _2929_;
+ wire _2930_;
+ wire _2931_;
+ wire _2932_;
+ wire _2933_;
+ wire _2934_;
+ wire _2935_;
+ wire _2936_;
+ wire _2937_;
+ wire _2938_;
+ wire [89:0] _2939_;
+ wire [89:0] _2940_;
+ wire [89:0] _2941_;
+ wire [89:0] _2942_;
+ wire [89:0] _2943_;
+ wire [89:0] _2944_;
+ wire [89:0] _2945_;
+ wire [89:0] _2946_;
+ wire [89:0] _2947_;
+ wire [89:0] _2948_;
+ wire _2949_;
+ wire _2950_;
+ wire _2951_;
+ wire _2952_;
+ wire _2953_;
+ wire _2954_;
+ wire _2955_;
+ wire _2956_;
+ wire _2957_;
+ wire _2958_;
+ wire [89:0] _2959_;
+ wire [89:0] _2960_;
+ wire [89:0] _2961_;
+ wire [89:0] _2962_;
+ wire [89:0] _2963_;
+ wire [89:0] _2964_;
+ wire [89:0] _2965_;
+ wire [89:0] _2966_;
+ wire [89:0] _2967_;
+ wire [89:0] _2968_;
+ wire _2969_;
+ wire _2970_;
+ wire _2971_;
+ wire _2972_;
+ wire _2973_;
+ wire _2974_;
+ wire _2975_;
+ wire _2976_;
+ wire _2977_;
+ wire _2978_;
+ wire [89:0] _2979_;
+ wire [89:0] _2980_;
+ wire [89:0] _2981_;
+ wire [89:0] _2982_;
+ wire [89:0] _2983_;
+ wire [89:0] _2984_;
+ wire [89:0] _2985_;
+ wire [89:0] _2986_;
+ wire [89:0] _2987_;
+ wire [89:0] _2988_;
+ wire _2989_;
+ wire _2990_;
+ wire _2991_;
+ wire _2992_;
+ wire _2993_;
+ wire _2994_;
+ wire _2995_;
+ wire _2996_;
+ wire _2997_;
+ wire _2998_;
+ wire [89:0] _2999_;
+ wire [89:0] _3000_;
+ wire [89:0] _3001_;
+ wire [89:0] _3002_;
+ wire [89:0] _3003_;
+ wire [89:0] _3004_;
+ wire [89:0] _3005_;
+ wire [89:0] _3006_;
+ wire [89:0] _3007_;
+ wire [89:0] _3008_;
+ wire [89:0] _3009_;
+ wire [89:0] _3010_;
+ wire [89:0] _3011_;
+ wire [89:0] _3012_;
+ wire [89:0] _3013_;
+ wire [89:0] _3014_;
+ wire [89:0] _3015_;
+ wire [89:0] _3016_;
+ wire [89:0] _3017_;
+ wire [89:0] _3018_;
+ wire [89:0] _3019_;
+ wire [89:0] _3020_;
+ wire [89:0] _3021_;
+ wire [89:0] _3022_;
+ wire [89:0] _3023_;
+ wire [89:0] _3024_;
+ wire [89:0] _3025_;
+ wire [89:0] _3026_;
+ wire [89:0] _3027_;
+ wire [89:0] _3028_;
+ wire [89:0] _3029_;
+ wire [89:0] _3030_;
+ wire [89:0] _3031_;
+ wire [89:0] _3032_;
+ wire [89:0] _3033_;
+ wire [89:0] _3034_;
+ wire [89:0] _3035_;
+ wire [89:0] _3036_;
+ wire [89:0] _3037_;
+ wire [89:0] _3038_;
+ reg [2879:0] cache_tags;
+ reg [63:0] cache_valids;
+ wire cancel_store;
+ wire clear_rsrv;
+ input clk;
+ input [142:0] d_in;
+ output [67:0] d_out;
+ reg [127:0] dtlb_valids;
+ wire [7:0] early_req_row;
+ input [131:0] m_in;
+ output [66:0] m_out;
+ wire \maybe_plrus.plrus%0.plru_acc_en ;
+ wire \maybe_plrus.plrus%0.plru_out ;
+ wire \maybe_plrus.plrus%1.plru_acc_en ;
+ wire \maybe_plrus.plrus%1.plru_out ;
+ wire \maybe_plrus.plrus%10.plru_acc_en ;
+ wire \maybe_plrus.plrus%10.plru_out ;
+ wire \maybe_plrus.plrus%11.plru_acc_en ;
+ wire \maybe_plrus.plrus%11.plru_out ;
+ wire \maybe_plrus.plrus%12.plru_acc_en ;
+ wire \maybe_plrus.plrus%12.plru_out ;
+ wire \maybe_plrus.plrus%13.plru_acc_en ;
+ wire \maybe_plrus.plrus%13.plru_out ;
+ wire \maybe_plrus.plrus%14.plru_acc_en ;
+ wire \maybe_plrus.plrus%14.plru_out ;
+ wire \maybe_plrus.plrus%15.plru_acc_en ;
+ wire \maybe_plrus.plrus%15.plru_out ;
+ wire \maybe_plrus.plrus%16.plru_acc_en ;
+ wire \maybe_plrus.plrus%16.plru_out ;
+ wire \maybe_plrus.plrus%17.plru_acc_en ;
+ wire \maybe_plrus.plrus%17.plru_out ;
+ wire \maybe_plrus.plrus%18.plru_acc_en ;
+ wire \maybe_plrus.plrus%18.plru_out ;
+ wire \maybe_plrus.plrus%19.plru_acc_en ;
+ wire \maybe_plrus.plrus%19.plru_out ;
+ wire \maybe_plrus.plrus%2.plru_acc_en ;
+ wire \maybe_plrus.plrus%2.plru_out ;
+ wire \maybe_plrus.plrus%20.plru_acc_en ;
+ wire \maybe_plrus.plrus%20.plru_out ;
+ wire \maybe_plrus.plrus%21.plru_acc_en ;
+ wire \maybe_plrus.plrus%21.plru_out ;
+ wire \maybe_plrus.plrus%22.plru_acc_en ;
+ wire \maybe_plrus.plrus%22.plru_out ;
+ wire \maybe_plrus.plrus%23.plru_acc_en ;
+ wire \maybe_plrus.plrus%23.plru_out ;
+ wire \maybe_plrus.plrus%24.plru_acc_en ;
+ wire \maybe_plrus.plrus%24.plru_out ;
+ wire \maybe_plrus.plrus%25.plru_acc_en ;
+ wire \maybe_plrus.plrus%25.plru_out ;
+ wire \maybe_plrus.plrus%26.plru_acc_en ;
+ wire \maybe_plrus.plrus%26.plru_out ;
+ wire \maybe_plrus.plrus%27.plru_acc_en ;
+ wire \maybe_plrus.plrus%27.plru_out ;
+ wire \maybe_plrus.plrus%28.plru_acc_en ;
+ wire \maybe_plrus.plrus%28.plru_out ;
+ wire \maybe_plrus.plrus%29.plru_acc_en ;
+ wire \maybe_plrus.plrus%29.plru_out ;
+ wire \maybe_plrus.plrus%3.plru_acc_en ;
+ wire \maybe_plrus.plrus%3.plru_out ;
+ wire \maybe_plrus.plrus%30.plru_acc_en ;
+ wire \maybe_plrus.plrus%30.plru_out ;
+ wire \maybe_plrus.plrus%31.plru_acc_en ;
+ wire \maybe_plrus.plrus%31.plru_out ;
+ wire \maybe_plrus.plrus%4.plru_acc_en ;
+ wire \maybe_plrus.plrus%4.plru_out ;
+ wire \maybe_plrus.plrus%5.plru_acc_en ;
+ wire \maybe_plrus.plrus%5.plru_out ;
+ wire \maybe_plrus.plrus%6.plru_acc_en ;
+ wire \maybe_plrus.plrus%6.plru_out ;
+ wire \maybe_plrus.plrus%7.plru_acc_en ;
+ wire \maybe_plrus.plrus%7.plru_out ;
+ wire \maybe_plrus.plrus%8.plru_acc_en ;
+ wire \maybe_plrus.plrus%8.plru_out ;
+ wire \maybe_plrus.plrus%9.plru_acc_en ;
+ wire \maybe_plrus.plrus%9.plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out ;
+ wire \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en ;
+ wire \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ;
+ wire [5:0] perm_attr;
+ wire perm_ok;
+ wire [63:0] pte;
+ reg [146:0] r0;
+ wire r0_valid;
+ wire [55:0] ra;
+ wire \rams%0.do_write ;
+ wire [63:0] \rams%0.dout ;
+ wire [7:0] \rams%0.wr_addr ;
+ wire [63:0] \rams%0.wr_data ;
+ wire [7:0] \rams%0.wr_sel ;
+ wire \rams%1.do_write ;
+ wire [63:0] \rams%1.dout ;
+ wire [7:0] \rams%1.wr_addr ;
+ wire [63:0] \rams%1.wr_data ;
+ wire [7:0] \rams%1.wr_sel ;
+ wire rc_ok;
+ wire replace_way;
+ wire req_hit_way;
+ wire [2:0] req_op;
+ reg [58:0] reservation;
+ input rst;
+ wire set_rsrv;
+ output stall_out;
+ wire tlb_hit;
+ wire tlb_hit_way;
+ wire [127:0] tlb_pte_way;
+ wire [91:0] tlb_tag_way;
+ reg [1:0] tlb_valid_way;
+ wire valid_ra;
+ input [65:0] wishbone_in;
+ output [106:0] wishbone_out;
+ reg [91:0] \$mem$\13892 [63:0];
+ reg [127:0] \$mem$\13896 [63:0];
+ assign _2615_ = _0019_[0] ? dtlb_valids[3:2] : dtlb_valids[1:0];
+ assign _2616_ = _0019_[0] ? dtlb_valids[11:10] : dtlb_valids[9:8];
+ assign _2617_ = _0019_[0] ? dtlb_valids[19:18] : dtlb_valids[17:16];
+ assign _2618_ = _0019_[0] ? dtlb_valids[27:26] : dtlb_valids[25:24];
+ assign _2619_ = _0019_[0] ? dtlb_valids[35:34] : dtlb_valids[33:32];
+ assign _2620_ = _0019_[0] ? dtlb_valids[43:42] : dtlb_valids[41:40];
+ assign _2621_ = _0019_[0] ? dtlb_valids[51:50] : dtlb_valids[49:48];
+ assign _2622_ = _0019_[0] ? dtlb_valids[59:58] : dtlb_valids[57:56];
+ assign _2623_ = _0019_[0] ? dtlb_valids[67:66] : dtlb_valids[65:64];
+ assign _2624_ = _0019_[0] ? dtlb_valids[75:74] : dtlb_valids[73:72];
+ assign _2625_ = _0019_[0] ? dtlb_valids[83:82] : dtlb_valids[81:80];
+ assign _2626_ = _0019_[0] ? dtlb_valids[91:90] : dtlb_valids[89:88];
+ assign _2627_ = _0019_[0] ? dtlb_valids[99:98] : dtlb_valids[97:96];
+ assign _2628_ = _0019_[0] ? dtlb_valids[107:106] : dtlb_valids[105:104];
+ assign _2629_ = _0019_[0] ? dtlb_valids[115:114] : dtlb_valids[113:112];
+ assign _2630_ = _0019_[0] ? dtlb_valids[123:122] : dtlb_valids[121:120];
+ assign _2631_ = _0019_[2] ? _0633_ : _0632_;
+ assign _2632_ = _0019_[2] ? _0637_ : _0636_;
+ assign _2633_ = _0019_[2] ? _0641_ : _0640_;
+ assign _2634_ = _0019_[2] ? _0645_ : _0644_;
+ assign _2635_ = _0019_[4] ? _0649_ : _0648_;
+ assign _2636_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ;
+ assign _2637_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ;
+ assign _2638_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ;
+ assign _2639_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ;
+ assign _2640_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ;
+ assign _2641_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ;
+ assign _2642_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ;
+ assign _2643_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ;
+ assign _2644_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ;
+ assign _2645_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ;
+ assign _2646_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ;
+ assign _2647_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ;
+ assign _2648_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ;
+ assign _2649_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ;
+ assign _2650_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ;
+ assign _2651_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ;
+ assign _2652_ = _0161_[2] ? _1042_ : _1041_;
+ assign _2653_ = _0161_[2] ? _1046_ : _1045_;
+ assign _2654_ = _0161_[2] ? _1050_ : _1049_;
+ assign _2655_ = _0161_[2] ? _1054_ : _1053_;
+ assign _2656_ = _0161_[4] ? _1058_ : _1057_;
+ assign _2657_ = _0338_[0] ? cache_valids[2] : cache_valids[0];
+ assign _2658_ = _0338_[0] ? cache_valids[10] : cache_valids[8];
+ assign _2659_ = _0338_[0] ? cache_valids[18] : cache_valids[16];
+ assign _2660_ = _0338_[0] ? cache_valids[26] : cache_valids[24];
+ assign _2661_ = _0338_[0] ? cache_valids[34] : cache_valids[32];
+ assign _2662_ = _0338_[0] ? cache_valids[42] : cache_valids[40];
+ assign _2663_ = _0338_[0] ? cache_valids[50] : cache_valids[48];
+ assign _2664_ = _0338_[0] ? cache_valids[58] : cache_valids[56];
+ assign _2665_ = _0338_[2] ? _1456_ : _1455_;
+ assign _2666_ = _0338_[2] ? _1460_ : _1459_;
+ assign _2667_ = _0340_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2668_ = _0340_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2669_ = _0340_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2670_ = _0340_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2671_ = _0340_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2672_ = _0340_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2673_ = _0340_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2674_ = _0340_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2675_ = _0340_[2] ? _1467_ : _1466_;
+ assign _2676_ = _0340_[2] ? _1471_ : _1470_;
+ assign _2677_ = _0346_[0] ? cache_valids[3] : cache_valids[1];
+ assign _2678_ = _0346_[0] ? cache_valids[11] : cache_valids[9];
+ assign _2679_ = _0346_[0] ? cache_valids[19] : cache_valids[17];
+ assign _2680_ = _0346_[0] ? cache_valids[27] : cache_valids[25];
+ assign _2681_ = _0346_[0] ? cache_valids[35] : cache_valids[33];
+ assign _2682_ = _0346_[0] ? cache_valids[43] : cache_valids[41];
+ assign _2683_ = _0346_[0] ? cache_valids[51] : cache_valids[49];
+ assign _2684_ = _0346_[0] ? cache_valids[59] : cache_valids[57];
+ assign _2685_ = _0346_[2] ? _1478_ : _1477_;
+ assign _2686_ = _0346_[2] ? _1482_ : _1481_;
+ assign _2687_ = _0348_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2688_ = _0348_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2689_ = _0348_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2690_ = _0348_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2691_ = _0348_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2692_ = _0348_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2693_ = _0348_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2694_ = _0348_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2695_ = _0348_[2] ? _1489_ : _1488_;
+ assign _2696_ = _0348_[2] ? _1493_ : _1492_;
+ assign _2697_ = _0354_[0] ? cache_valids[2] : cache_valids[0];
+ assign _2698_ = _0354_[0] ? cache_valids[10] : cache_valids[8];
+ assign _2699_ = _0354_[0] ? cache_valids[18] : cache_valids[16];
+ assign _2700_ = _0354_[0] ? cache_valids[26] : cache_valids[24];
+ assign _2701_ = _0354_[0] ? cache_valids[34] : cache_valids[32];
+ assign _2702_ = _0354_[0] ? cache_valids[42] : cache_valids[40];
+ assign _2703_ = _0354_[0] ? cache_valids[50] : cache_valids[48];
+ assign _2704_ = _0354_[0] ? cache_valids[58] : cache_valids[56];
+ assign _2705_ = _0354_[2] ? _1500_ : _1499_;
+ assign _2706_ = _0354_[2] ? _1504_ : _1503_;
+ assign _2707_ = _0356_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2708_ = _0356_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2709_ = _0356_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2710_ = _0356_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2711_ = _0356_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2712_ = _0356_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2713_ = _0356_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2714_ = _0356_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2715_ = _0356_[2] ? _1511_ : _1510_;
+ assign _2716_ = _0356_[2] ? _1515_ : _1514_;
+ assign _2717_ = _0362_[0] ? cache_valids[3] : cache_valids[1];
+ assign _2718_ = _0362_[0] ? cache_valids[11] : cache_valids[9];
+ assign _2719_ = _0362_[0] ? cache_valids[19] : cache_valids[17];
+ assign _2720_ = _0362_[0] ? cache_valids[27] : cache_valids[25];
+ assign _2721_ = _0362_[0] ? cache_valids[35] : cache_valids[33];
+ assign _2722_ = _0362_[0] ? cache_valids[43] : cache_valids[41];
+ assign _2723_ = _0362_[0] ? cache_valids[51] : cache_valids[49];
+ assign _2724_ = _0362_[0] ? cache_valids[59] : cache_valids[57];
+ assign _2725_ = _0362_[2] ? _1522_ : _1521_;
+ assign _2726_ = _0362_[2] ? _1526_ : _1525_;
+ assign _2727_ = _0364_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2728_ = _0364_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2729_ = _0364_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2730_ = _0364_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2731_ = _0364_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2732_ = _0364_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2733_ = _0364_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2734_ = _0364_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2735_ = _0364_[2] ? _1533_ : _1532_;
+ assign _2736_ = _0364_[2] ? _1537_ : _1536_;
+ assign _2737_ = _0373_[0] ? cache_valids[2] : cache_valids[0];
+ assign _2738_ = _0373_[0] ? cache_valids[10] : cache_valids[8];
+ assign _2739_ = _0373_[0] ? cache_valids[18] : cache_valids[16];
+ assign _2740_ = _0373_[0] ? cache_valids[26] : cache_valids[24];
+ assign _2741_ = _0373_[0] ? cache_valids[34] : cache_valids[32];
+ assign _2742_ = _0373_[0] ? cache_valids[42] : cache_valids[40];
+ assign _2743_ = _0373_[0] ? cache_valids[50] : cache_valids[48];
+ assign _2744_ = _0373_[0] ? cache_valids[58] : cache_valids[56];
+ assign _2745_ = _0373_[2] ? _1546_ : _1545_;
+ assign _2746_ = _0373_[2] ? _1550_ : _1549_;
+ assign _2747_ = _0375_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2748_ = _0375_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2749_ = _0375_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2750_ = _0375_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2751_ = _0375_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2752_ = _0375_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2753_ = _0375_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2754_ = _0375_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2755_ = _0375_[2] ? _1557_ : _1556_;
+ assign _2756_ = _0375_[2] ? _1561_ : _1560_;
+ assign _2757_ = _0379_[0] ? cache_valids[3] : cache_valids[1];
+ assign _2758_ = _0379_[0] ? cache_valids[11] : cache_valids[9];
+ assign _2759_ = _0379_[0] ? cache_valids[19] : cache_valids[17];
+ assign _2760_ = _0379_[0] ? cache_valids[27] : cache_valids[25];
+ assign _2761_ = _0379_[0] ? cache_valids[35] : cache_valids[33];
+ assign _2762_ = _0379_[0] ? cache_valids[43] : cache_valids[41];
+ assign _2763_ = _0379_[0] ? cache_valids[51] : cache_valids[49];
+ assign _2764_ = _0379_[0] ? cache_valids[59] : cache_valids[57];
+ assign _2765_ = _0379_[2] ? _1568_ : _1567_;
+ assign _2766_ = _0379_[2] ? _1572_ : _1571_;
+ assign _2767_ = _0381_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2768_ = _0381_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2769_ = _0381_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2770_ = _0381_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2771_ = _0381_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2772_ = _0381_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2773_ = _0381_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2774_ = _0381_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2775_ = _0381_[2] ? _1579_ : _1578_;
+ assign _2776_ = _0381_[2] ? _1583_ : _1582_;
+ assign _2777_ = _0387_[0] ? \maybe_plrus.plrus%30.plru_out : \maybe_plrus.plrus%31.plru_out ;
+ assign _2778_ = _0387_[0] ? \maybe_plrus.plrus%26.plru_out : \maybe_plrus.plrus%27.plru_out ;
+ assign _2779_ = _0387_[0] ? \maybe_plrus.plrus%22.plru_out : \maybe_plrus.plrus%23.plru_out ;
+ assign _2780_ = _0387_[0] ? \maybe_plrus.plrus%18.plru_out : \maybe_plrus.plrus%19.plru_out ;
+ assign _2781_ = _0387_[0] ? \maybe_plrus.plrus%14.plru_out : \maybe_plrus.plrus%15.plru_out ;
+ assign _2782_ = _0387_[0] ? \maybe_plrus.plrus%10.plru_out : \maybe_plrus.plrus%11.plru_out ;
+ assign _2783_ = _0387_[0] ? \maybe_plrus.plrus%6.plru_out : \maybe_plrus.plrus%7.plru_out ;
+ assign _2784_ = _0387_[0] ? \maybe_plrus.plrus%2.plru_out : \maybe_plrus.plrus%3.plru_out ;
+ assign _2785_ = _0387_[2] ? _1590_ : _1589_;
+ assign _2786_ = _0387_[2] ? _1594_ : _1593_;
+ assign _2787_ = _0513_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2788_ = _0513_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2789_ = _0513_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2790_ = _0513_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2791_ = _0513_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2792_ = _0513_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2793_ = _0513_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2794_ = _0513_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2795_ = _0513_[2] ? _1796_ : _1795_;
+ assign _2796_ = _0513_[2] ? _1800_ : _1799_;
+ assign _2797_ = _0517_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2798_ = _0517_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2799_ = _0517_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2800_ = _0517_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2801_ = _0517_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2802_ = _0517_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2803_ = _0517_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2804_ = _0517_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2805_ = _0517_[2] ? _1904_ : _1903_;
+ assign _2806_ = _0517_[2] ? _1908_ : _1907_;
+ assign _2807_ = _0531_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2808_ = _0531_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2809_ = _0531_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2810_ = _0531_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2811_ = _0531_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2812_ = _0531_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2813_ = _0531_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2814_ = _0531_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2815_ = _0531_[2] ? _2206_ : _2205_;
+ assign _2816_ = _0531_[2] ? _2210_ : _2209_;
+ assign _2817_ = _0535_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _2818_ = _0535_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _2819_ = _0535_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _2820_ = _0535_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _2821_ = _0535_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _2822_ = _0535_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _2823_ = _0535_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _2824_ = _0535_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _2825_ = _0535_[2] ? _2314_ : _2313_;
+ assign _2826_ = _0535_[2] ? _2318_ : _2317_;
+ assign _2827_ = _0019_[0] ? dtlb_valids[7:6] : dtlb_valids[5:4];
+ assign _2828_ = _0019_[0] ? dtlb_valids[15:14] : dtlb_valids[13:12];
+ assign _2829_ = _0019_[0] ? dtlb_valids[23:22] : dtlb_valids[21:20];
+ assign _2830_ = _0019_[0] ? dtlb_valids[31:30] : dtlb_valids[29:28];
+ assign _2831_ = _0019_[0] ? dtlb_valids[39:38] : dtlb_valids[37:36];
+ assign _2832_ = _0019_[0] ? dtlb_valids[47:46] : dtlb_valids[45:44];
+ assign _2833_ = _0019_[0] ? dtlb_valids[55:54] : dtlb_valids[53:52];
+ assign _2834_ = _0019_[0] ? dtlb_valids[63:62] : dtlb_valids[61:60];
+ assign _2835_ = _0019_[0] ? dtlb_valids[71:70] : dtlb_valids[69:68];
+ assign _2836_ = _0019_[0] ? dtlb_valids[79:78] : dtlb_valids[77:76];
+ assign _2837_ = _0019_[0] ? dtlb_valids[87:86] : dtlb_valids[85:84];
+ assign _2838_ = _0019_[0] ? dtlb_valids[95:94] : dtlb_valids[93:92];
+ assign _2839_ = _0019_[0] ? dtlb_valids[103:102] : dtlb_valids[101:100];
+ assign _2840_ = _0019_[0] ? dtlb_valids[111:110] : dtlb_valids[109:108];
+ assign _2841_ = _0019_[0] ? dtlb_valids[119:118] : dtlb_valids[117:116];
+ assign _2842_ = _0019_[0] ? dtlb_valids[127:126] : dtlb_valids[125:124];
+ assign _2843_ = _0019_[2] ? _0635_ : _0634_;
+ assign _2844_ = _0019_[2] ? _0639_ : _0638_;
+ assign _2845_ = _0019_[2] ? _0643_ : _0642_;
+ assign _2846_ = _0019_[2] ? _0647_ : _0646_;
+ assign _2847_ = _0019_[4] ? _0651_ : _0650_;
+ assign _2848_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ;
+ assign _2849_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ;
+ assign _2850_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ;
+ assign _2851_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ;
+ assign _2852_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ;
+ assign _2853_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ;
+ assign _2854_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ;
+ assign _2855_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ;
+ assign _2856_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ;
+ assign _2857_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ;
+ assign _2858_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ;
+ assign _2859_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ;
+ assign _2860_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ;
+ assign _2861_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ;
+ assign _2862_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ;
+ assign _2863_ = _0161_[0] ? \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out : \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ;
+ assign _2864_ = _0161_[2] ? _1044_ : _1043_;
+ assign _2865_ = _0161_[2] ? _1048_ : _1047_;
+ assign _2866_ = _0161_[2] ? _1052_ : _1051_;
+ assign _2867_ = _0161_[2] ? _1056_ : _1055_;
+ assign _2868_ = _0161_[4] ? _1060_ : _1059_;
+ assign _2869_ = _0338_[0] ? cache_valids[6] : cache_valids[4];
+ assign _2870_ = _0338_[0] ? cache_valids[14] : cache_valids[12];
+ assign _2871_ = _0338_[0] ? cache_valids[22] : cache_valids[20];
+ assign _2872_ = _0338_[0] ? cache_valids[30] : cache_valids[28];
+ assign _2873_ = _0338_[0] ? cache_valids[38] : cache_valids[36];
+ assign _2874_ = _0338_[0] ? cache_valids[46] : cache_valids[44];
+ assign _2875_ = _0338_[0] ? cache_valids[54] : cache_valids[52];
+ assign _2876_ = _0338_[0] ? cache_valids[62] : cache_valids[60];
+ assign _2877_ = _0338_[2] ? _1458_ : _1457_;
+ assign _2878_ = _0338_[2] ? _1462_ : _1461_;
+ assign _2879_ = _0340_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2880_ = _0340_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2881_ = _0340_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2882_ = _0340_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2883_ = _0340_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2884_ = _0340_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2885_ = _0340_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2886_ = _0340_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2887_ = _0340_[2] ? _1469_ : _1468_;
+ assign _2888_ = _0340_[2] ? _1473_ : _1472_;
+ assign _2889_ = _0346_[0] ? cache_valids[7] : cache_valids[5];
+ assign _2890_ = _0346_[0] ? cache_valids[15] : cache_valids[13];
+ assign _2891_ = _0346_[0] ? cache_valids[23] : cache_valids[21];
+ assign _2892_ = _0346_[0] ? cache_valids[31] : cache_valids[29];
+ assign _2893_ = _0346_[0] ? cache_valids[39] : cache_valids[37];
+ assign _2894_ = _0346_[0] ? cache_valids[47] : cache_valids[45];
+ assign _2895_ = _0346_[0] ? cache_valids[55] : cache_valids[53];
+ assign _2896_ = _0346_[0] ? cache_valids[63] : cache_valids[61];
+ assign _2897_ = _0346_[2] ? _1480_ : _1479_;
+ assign _2898_ = _0346_[2] ? _1484_ : _1483_;
+ assign _2899_ = _0348_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2900_ = _0348_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2901_ = _0348_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2902_ = _0348_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2903_ = _0348_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2904_ = _0348_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2905_ = _0348_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2906_ = _0348_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2907_ = _0348_[2] ? _1491_ : _1490_;
+ assign _2908_ = _0348_[2] ? _1495_ : _1494_;
+ assign _2909_ = _0354_[0] ? cache_valids[6] : cache_valids[4];
+ assign _2910_ = _0354_[0] ? cache_valids[14] : cache_valids[12];
+ assign _2911_ = _0354_[0] ? cache_valids[22] : cache_valids[20];
+ assign _2912_ = _0354_[0] ? cache_valids[30] : cache_valids[28];
+ assign _2913_ = _0354_[0] ? cache_valids[38] : cache_valids[36];
+ assign _2914_ = _0354_[0] ? cache_valids[46] : cache_valids[44];
+ assign _2915_ = _0354_[0] ? cache_valids[54] : cache_valids[52];
+ assign _2916_ = _0354_[0] ? cache_valids[62] : cache_valids[60];
+ assign _2917_ = _0354_[2] ? _1502_ : _1501_;
+ assign _2918_ = _0354_[2] ? _1506_ : _1505_;
+ assign _2919_ = _0356_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2920_ = _0356_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2921_ = _0356_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2922_ = _0356_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2923_ = _0356_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2924_ = _0356_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2925_ = _0356_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2926_ = _0356_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2927_ = _0356_[2] ? _1513_ : _1512_;
+ assign _2928_ = _0356_[2] ? _1517_ : _1516_;
+ assign _2929_ = _0362_[0] ? cache_valids[7] : cache_valids[5];
+ assign _2930_ = _0362_[0] ? cache_valids[15] : cache_valids[13];
+ assign _2931_ = _0362_[0] ? cache_valids[23] : cache_valids[21];
+ assign _2932_ = _0362_[0] ? cache_valids[31] : cache_valids[29];
+ assign _2933_ = _0362_[0] ? cache_valids[39] : cache_valids[37];
+ assign _2934_ = _0362_[0] ? cache_valids[47] : cache_valids[45];
+ assign _2935_ = _0362_[0] ? cache_valids[55] : cache_valids[53];
+ assign _2936_ = _0362_[0] ? cache_valids[63] : cache_valids[61];
+ assign _2937_ = _0362_[2] ? _1524_ : _1523_;
+ assign _2938_ = _0362_[2] ? _1528_ : _1527_;
+ assign _2939_ = _0364_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2940_ = _0364_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2941_ = _0364_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2942_ = _0364_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2943_ = _0364_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2944_ = _0364_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2945_ = _0364_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2946_ = _0364_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2947_ = _0364_[2] ? _1535_ : _1534_;
+ assign _2948_ = _0364_[2] ? _1539_ : _1538_;
+ assign _2949_ = _0373_[0] ? cache_valids[6] : cache_valids[4];
+ assign _2950_ = _0373_[0] ? cache_valids[14] : cache_valids[12];
+ assign _2951_ = _0373_[0] ? cache_valids[22] : cache_valids[20];
+ assign _2952_ = _0373_[0] ? cache_valids[30] : cache_valids[28];
+ assign _2953_ = _0373_[0] ? cache_valids[38] : cache_valids[36];
+ assign _2954_ = _0373_[0] ? cache_valids[46] : cache_valids[44];
+ assign _2955_ = _0373_[0] ? cache_valids[54] : cache_valids[52];
+ assign _2956_ = _0373_[0] ? cache_valids[62] : cache_valids[60];
+ assign _2957_ = _0373_[2] ? _1548_ : _1547_;
+ assign _2958_ = _0373_[2] ? _1552_ : _1551_;
+ assign _2959_ = _0375_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2960_ = _0375_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2961_ = _0375_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2962_ = _0375_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2963_ = _0375_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2964_ = _0375_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2965_ = _0375_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2966_ = _0375_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2967_ = _0375_[2] ? _1559_ : _1558_;
+ assign _2968_ = _0375_[2] ? _1563_ : _1562_;
+ assign _2969_ = _0379_[0] ? cache_valids[7] : cache_valids[5];
+ assign _2970_ = _0379_[0] ? cache_valids[15] : cache_valids[13];
+ assign _2971_ = _0379_[0] ? cache_valids[23] : cache_valids[21];
+ assign _2972_ = _0379_[0] ? cache_valids[31] : cache_valids[29];
+ assign _2973_ = _0379_[0] ? cache_valids[39] : cache_valids[37];
+ assign _2974_ = _0379_[0] ? cache_valids[47] : cache_valids[45];
+ assign _2975_ = _0379_[0] ? cache_valids[55] : cache_valids[53];
+ assign _2976_ = _0379_[0] ? cache_valids[63] : cache_valids[61];
+ assign _2977_ = _0379_[2] ? _1570_ : _1569_;
+ assign _2978_ = _0379_[2] ? _1574_ : _1573_;
+ assign _2979_ = _0381_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _2980_ = _0381_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _2981_ = _0381_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _2982_ = _0381_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _2983_ = _0381_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _2984_ = _0381_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _2985_ = _0381_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _2986_ = _0381_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _2987_ = _0381_[2] ? _1581_ : _1580_;
+ assign _2988_ = _0381_[2] ? _1585_ : _1584_;
+ assign _2989_ = _0387_[0] ? \maybe_plrus.plrus%28.plru_out : \maybe_plrus.plrus%29.plru_out ;
+ assign _2990_ = _0387_[0] ? \maybe_plrus.plrus%24.plru_out : \maybe_plrus.plrus%25.plru_out ;
+ assign _2991_ = _0387_[0] ? \maybe_plrus.plrus%20.plru_out : \maybe_plrus.plrus%21.plru_out ;
+ assign _2992_ = _0387_[0] ? \maybe_plrus.plrus%16.plru_out : \maybe_plrus.plrus%17.plru_out ;
+ assign _2993_ = _0387_[0] ? \maybe_plrus.plrus%12.plru_out : \maybe_plrus.plrus%13.plru_out ;
+ assign _2994_ = _0387_[0] ? \maybe_plrus.plrus%8.plru_out : \maybe_plrus.plrus%9.plru_out ;
+ assign _2995_ = _0387_[0] ? \maybe_plrus.plrus%4.plru_out : \maybe_plrus.plrus%5.plru_out ;
+ assign _2996_ = _0387_[0] ? \maybe_plrus.plrus%0.plru_out : \maybe_plrus.plrus%1.plru_out ;
+ assign _2997_ = _0387_[2] ? _1592_ : _1591_;
+ assign _2998_ = _0387_[2] ? _1596_ : _1595_;
+ assign _2999_ = _0513_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _3000_ = _0513_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _3001_ = _0513_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _3002_ = _0513_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _3003_ = _0513_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _3004_ = _0513_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _3005_ = _0513_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _3006_ = _0513_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _3007_ = _0513_[2] ? _1798_ : _1797_;
+ assign _3008_ = _0513_[2] ? _1802_ : _1801_;
+ assign _3009_ = _0517_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _3010_ = _0517_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _3011_ = _0517_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _3012_ = _0517_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _3013_ = _0517_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _3014_ = _0517_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _3015_ = _0517_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _3016_ = _0517_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _3017_ = _0517_[2] ? _1906_ : _1905_;
+ assign _3018_ = _0517_[2] ? _1910_ : _1909_;
+ assign _3019_ = _0531_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _3020_ = _0531_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _3021_ = _0531_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _3022_ = _0531_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _3023_ = _0531_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _3024_ = _0531_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _3025_ = _0531_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _3026_ = _0531_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _3027_ = _0531_[2] ? _2208_ : _2207_;
+ assign _3028_ = _0531_[2] ? _2212_ : _2211_;
+ assign _3029_ = _0535_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _3030_ = _0535_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _3031_ = _0535_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _3032_ = _0535_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _3033_ = _0535_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _3034_ = _0535_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _3035_ = _0535_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _3036_ = _0535_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _3037_ = _0535_[2] ? _2316_ : _2315_;
+ assign _3038_ = _0535_[2] ? _2320_ : _2319_;
+ assign _0632_ = _0019_[1] ? _2827_ : _2615_;
+ assign _0633_ = _0019_[1] ? _2828_ : _2616_;
+ assign _0634_ = _0019_[1] ? _2829_ : _2617_;
+ assign _0635_ = _0019_[1] ? _2830_ : _2618_;
+ assign _0636_ = _0019_[1] ? _2831_ : _2619_;
+ assign _0637_ = _0019_[1] ? _2832_ : _2620_;
+ assign _0638_ = _0019_[1] ? _2833_ : _2621_;
+ assign _0639_ = _0019_[1] ? _2834_ : _2622_;
+ assign _0640_ = _0019_[1] ? _2835_ : _2623_;
+ assign _0641_ = _0019_[1] ? _2836_ : _2624_;
+ assign _0642_ = _0019_[1] ? _2837_ : _2625_;
+ assign _0643_ = _0019_[1] ? _2838_ : _2626_;
+ assign _0644_ = _0019_[1] ? _2839_ : _2627_;
+ assign _0645_ = _0019_[1] ? _2840_ : _2628_;
+ assign _0646_ = _0019_[1] ? _2841_ : _2629_;
+ assign _0647_ = _0019_[1] ? _2842_ : _2630_;
+ assign _0648_ = _0019_[3] ? _2843_ : _2631_;
+ assign _0649_ = _0019_[3] ? _2844_ : _2632_;
+ assign _0650_ = _0019_[3] ? _2845_ : _2633_;
+ assign _0651_ = _0019_[3] ? _2846_ : _2634_;
+ assign _0652_ = _0019_[5] ? _2847_ : _2635_;
+ assign _1041_ = _0161_[1] ? _2848_ : _2636_;
+ assign _1042_ = _0161_[1] ? _2849_ : _2637_;
+ assign _1043_ = _0161_[1] ? _2850_ : _2638_;
+ assign _1044_ = _0161_[1] ? _2851_ : _2639_;
+ assign _1045_ = _0161_[1] ? _2852_ : _2640_;
+ assign _1046_ = _0161_[1] ? _2853_ : _2641_;
+ assign _1047_ = _0161_[1] ? _2854_ : _2642_;
+ assign _1048_ = _0161_[1] ? _2855_ : _2643_;
+ assign _1049_ = _0161_[1] ? _2856_ : _2644_;
+ assign _1050_ = _0161_[1] ? _2857_ : _2645_;
+ assign _1051_ = _0161_[1] ? _2858_ : _2646_;
+ assign _1052_ = _0161_[1] ? _2859_ : _2647_;
+ assign _1053_ = _0161_[1] ? _2860_ : _2648_;
+ assign _1054_ = _0161_[1] ? _2861_ : _2649_;
+ assign _1055_ = _0161_[1] ? _2862_ : _2650_;
+ assign _1056_ = _0161_[1] ? _2863_ : _2651_;
+ assign _1057_ = _0161_[3] ? _2864_ : _2652_;
+ assign _1058_ = _0161_[3] ? _2865_ : _2653_;
+ assign _1059_ = _0161_[3] ? _2866_ : _2654_;
+ assign _1060_ = _0161_[3] ? _2867_ : _2655_;
+ assign _1061_ = _0161_[5] ? _2868_ : _2656_;
+ assign _1455_ = _0338_[1] ? _2869_ : _2657_;
+ assign _1456_ = _0338_[1] ? _2870_ : _2658_;
+ assign _1457_ = _0338_[1] ? _2871_ : _2659_;
+ assign _1458_ = _0338_[1] ? _2872_ : _2660_;
+ assign _1459_ = _0338_[1] ? _2873_ : _2661_;
+ assign _1460_ = _0338_[1] ? _2874_ : _2662_;
+ assign _1461_ = _0338_[1] ? _2875_ : _2663_;
+ assign _1462_ = _0338_[1] ? _2876_ : _2664_;
+ assign _1463_ = _0338_[3] ? _2877_ : _2665_;
+ assign _1464_ = _0338_[3] ? _2878_ : _2666_;
+ assign _1466_ = _0340_[1] ? _2879_ : _2667_;
+ assign _1467_ = _0340_[1] ? _2880_ : _2668_;
+ assign _1468_ = _0340_[1] ? _2881_ : _2669_;
+ assign _1469_ = _0340_[1] ? _2882_ : _2670_;
+ assign _1470_ = _0340_[1] ? _2883_ : _2671_;
+ assign _1471_ = _0340_[1] ? _2884_ : _2672_;
+ assign _1472_ = _0340_[1] ? _2885_ : _2673_;
+ assign _1473_ = _0340_[1] ? _2886_ : _2674_;
+ assign _1474_ = _0340_[3] ? _2887_ : _2675_;
+ assign _1475_ = _0340_[3] ? _2888_ : _2676_;
+ assign _1477_ = _0346_[1] ? _2889_ : _2677_;
+ assign _1478_ = _0346_[1] ? _2890_ : _2678_;
+ assign _1479_ = _0346_[1] ? _2891_ : _2679_;
+ assign _1480_ = _0346_[1] ? _2892_ : _2680_;
+ assign _1481_ = _0346_[1] ? _2893_ : _2681_;
+ assign _1482_ = _0346_[1] ? _2894_ : _2682_;
+ assign _1483_ = _0346_[1] ? _2895_ : _2683_;
+ assign _1484_ = _0346_[1] ? _2896_ : _2684_;
+ assign _1485_ = _0346_[3] ? _2897_ : _2685_;
+ assign _1486_ = _0346_[3] ? _2898_ : _2686_;
+ assign _1488_ = _0348_[1] ? _2899_ : _2687_;
+ assign _1489_ = _0348_[1] ? _2900_ : _2688_;
+ assign _1490_ = _0348_[1] ? _2901_ : _2689_;
+ assign _1491_ = _0348_[1] ? _2902_ : _2690_;
+ assign _1492_ = _0348_[1] ? _2903_ : _2691_;
+ assign _1493_ = _0348_[1] ? _2904_ : _2692_;
+ assign _1494_ = _0348_[1] ? _2905_ : _2693_;
+ assign _1495_ = _0348_[1] ? _2906_ : _2694_;
+ assign _1496_ = _0348_[3] ? _2907_ : _2695_;
+ assign _1497_ = _0348_[3] ? _2908_ : _2696_;
+ assign _1499_ = _0354_[1] ? _2909_ : _2697_;
+ assign _1500_ = _0354_[1] ? _2910_ : _2698_;
+ assign _1501_ = _0354_[1] ? _2911_ : _2699_;
+ assign _1502_ = _0354_[1] ? _2912_ : _2700_;
+ assign _1503_ = _0354_[1] ? _2913_ : _2701_;
+ assign _1504_ = _0354_[1] ? _2914_ : _2702_;
+ assign _1505_ = _0354_[1] ? _2915_ : _2703_;
+ assign _1506_ = _0354_[1] ? _2916_ : _2704_;
+ assign _1507_ = _0354_[3] ? _2917_ : _2705_;
+ assign _1508_ = _0354_[3] ? _2918_ : _2706_;
+ assign _1510_ = _0356_[1] ? _2919_ : _2707_;
+ assign _1511_ = _0356_[1] ? _2920_ : _2708_;
+ assign _1512_ = _0356_[1] ? _2921_ : _2709_;
+ assign _1513_ = _0356_[1] ? _2922_ : _2710_;
+ assign _1514_ = _0356_[1] ? _2923_ : _2711_;
+ assign _1515_ = _0356_[1] ? _2924_ : _2712_;
+ assign _1516_ = _0356_[1] ? _2925_ : _2713_;
+ assign _1517_ = _0356_[1] ? _2926_ : _2714_;
+ assign _1518_ = _0356_[3] ? _2927_ : _2715_;
+ assign _1519_ = _0356_[3] ? _2928_ : _2716_;
+ assign _1521_ = _0362_[1] ? _2929_ : _2717_;
+ assign _1522_ = _0362_[1] ? _2930_ : _2718_;
+ assign _1523_ = _0362_[1] ? _2931_ : _2719_;
+ assign _1524_ = _0362_[1] ? _2932_ : _2720_;
+ assign _1525_ = _0362_[1] ? _2933_ : _2721_;
+ assign _1526_ = _0362_[1] ? _2934_ : _2722_;
+ assign _1527_ = _0362_[1] ? _2935_ : _2723_;
+ assign _1528_ = _0362_[1] ? _2936_ : _2724_;
+ assign _1529_ = _0362_[3] ? _2937_ : _2725_;
+ assign _1530_ = _0362_[3] ? _2938_ : _2726_;
+ assign _1532_ = _0364_[1] ? _2939_ : _2727_;
+ assign _1533_ = _0364_[1] ? _2940_ : _2728_;
+ assign _1534_ = _0364_[1] ? _2941_ : _2729_;
+ assign _1535_ = _0364_[1] ? _2942_ : _2730_;
+ assign _1536_ = _0364_[1] ? _2943_ : _2731_;
+ assign _1537_ = _0364_[1] ? _2944_ : _2732_;
+ assign _1538_ = _0364_[1] ? _2945_ : _2733_;
+ assign _1539_ = _0364_[1] ? _2946_ : _2734_;
+ assign _1540_ = _0364_[3] ? _2947_ : _2735_;
+ assign _1541_ = _0364_[3] ? _2948_ : _2736_;
+ assign _1545_ = _0373_[1] ? _2949_ : _2737_;
+ assign _1546_ = _0373_[1] ? _2950_ : _2738_;
+ assign _1547_ = _0373_[1] ? _2951_ : _2739_;
+ assign _1548_ = _0373_[1] ? _2952_ : _2740_;
+ assign _1549_ = _0373_[1] ? _2953_ : _2741_;
+ assign _1550_ = _0373_[1] ? _2954_ : _2742_;
+ assign _1551_ = _0373_[1] ? _2955_ : _2743_;
+ assign _1552_ = _0373_[1] ? _2956_ : _2744_;
+ assign _1553_ = _0373_[3] ? _2957_ : _2745_;
+ assign _1554_ = _0373_[3] ? _2958_ : _2746_;
+ assign _1556_ = _0375_[1] ? _2959_ : _2747_;
+ assign _1557_ = _0375_[1] ? _2960_ : _2748_;
+ assign _1558_ = _0375_[1] ? _2961_ : _2749_;
+ assign _1559_ = _0375_[1] ? _2962_ : _2750_;
+ assign _1560_ = _0375_[1] ? _2963_ : _2751_;
+ assign _1561_ = _0375_[1] ? _2964_ : _2752_;
+ assign _1562_ = _0375_[1] ? _2965_ : _2753_;
+ assign _1563_ = _0375_[1] ? _2966_ : _2754_;
+ assign _1564_ = _0375_[3] ? _2967_ : _2755_;
+ assign _1565_ = _0375_[3] ? _2968_ : _2756_;
+ assign _1567_ = _0379_[1] ? _2969_ : _2757_;
+ assign _1568_ = _0379_[1] ? _2970_ : _2758_;
+ assign _1569_ = _0379_[1] ? _2971_ : _2759_;
+ assign _1570_ = _0379_[1] ? _2972_ : _2760_;
+ assign _1571_ = _0379_[1] ? _2973_ : _2761_;
+ assign _1572_ = _0379_[1] ? _2974_ : _2762_;
+ assign _1573_ = _0379_[1] ? _2975_ : _2763_;
+ assign _1574_ = _0379_[1] ? _2976_ : _2764_;
+ assign _1575_ = _0379_[3] ? _2977_ : _2765_;
+ assign _1576_ = _0379_[3] ? _2978_ : _2766_;
+ assign _1578_ = _0381_[1] ? _2979_ : _2767_;
+ assign _1579_ = _0381_[1] ? _2980_ : _2768_;
+ assign _1580_ = _0381_[1] ? _2981_ : _2769_;
+ assign _1581_ = _0381_[1] ? _2982_ : _2770_;
+ assign _1582_ = _0381_[1] ? _2983_ : _2771_;
+ assign _1583_ = _0381_[1] ? _2984_ : _2772_;
+ assign _1584_ = _0381_[1] ? _2985_ : _2773_;
+ assign _1585_ = _0381_[1] ? _2986_ : _2774_;
+ assign _1586_ = _0381_[3] ? _2987_ : _2775_;
+ assign _1587_ = _0381_[3] ? _2988_ : _2776_;
+ assign _1589_ = _0387_[1] ? _2989_ : _2777_;
+ assign _1590_ = _0387_[1] ? _2990_ : _2778_;
+ assign _1591_ = _0387_[1] ? _2991_ : _2779_;
+ assign _1592_ = _0387_[1] ? _2992_ : _2780_;
+ assign _1593_ = _0387_[1] ? _2993_ : _2781_;
+ assign _1594_ = _0387_[1] ? _2994_ : _2782_;
+ assign _1595_ = _0387_[1] ? _2995_ : _2783_;
+ assign _1596_ = _0387_[1] ? _2996_ : _2784_;
+ assign _1597_ = _0387_[3] ? _2997_ : _2785_;
+ assign _1598_ = _0387_[3] ? _2998_ : _2786_;
+ assign _1795_ = _0513_[1] ? _2999_ : _2787_;
+ assign _1796_ = _0513_[1] ? _3000_ : _2788_;
+ assign _1797_ = _0513_[1] ? _3001_ : _2789_;
+ assign _1798_ = _0513_[1] ? _3002_ : _2790_;
+ assign _1799_ = _0513_[1] ? _3003_ : _2791_;
+ assign _1800_ = _0513_[1] ? _3004_ : _2792_;
+ assign _1801_ = _0513_[1] ? _3005_ : _2793_;
+ assign _1802_ = _0513_[1] ? _3006_ : _2794_;
+ assign _1803_ = _0513_[3] ? _3007_ : _2795_;
+ assign _1804_ = _0513_[3] ? _3008_ : _2796_;
+ assign _1903_ = _0517_[1] ? _3009_ : _2797_;
+ assign _1904_ = _0517_[1] ? _3010_ : _2798_;
+ assign _1905_ = _0517_[1] ? _3011_ : _2799_;
+ assign _1906_ = _0517_[1] ? _3012_ : _2800_;
+ assign _1907_ = _0517_[1] ? _3013_ : _2801_;
+ assign _1908_ = _0517_[1] ? _3014_ : _2802_;
+ assign _1909_ = _0517_[1] ? _3015_ : _2803_;
+ assign _1910_ = _0517_[1] ? _3016_ : _2804_;
+ assign _1911_ = _0517_[3] ? _3017_ : _2805_;
+ assign _1912_ = _0517_[3] ? _3018_ : _2806_;
+ assign _2205_ = _0531_[1] ? _3019_ : _2807_;
+ assign _2206_ = _0531_[1] ? _3020_ : _2808_;
+ assign _2207_ = _0531_[1] ? _3021_ : _2809_;
+ assign _2208_ = _0531_[1] ? _3022_ : _2810_;
+ assign _2209_ = _0531_[1] ? _3023_ : _2811_;
+ assign _2210_ = _0531_[1] ? _3024_ : _2812_;
+ assign _2211_ = _0531_[1] ? _3025_ : _2813_;
+ assign _2212_ = _0531_[1] ? _3026_ : _2814_;
+ assign _2213_ = _0531_[3] ? _3027_ : _2815_;
+ assign _2214_ = _0531_[3] ? _3028_ : _2816_;
+ assign _2313_ = _0535_[1] ? _3029_ : _2817_;
+ assign _2314_ = _0535_[1] ? _3030_ : _2818_;
+ assign _2315_ = _0535_[1] ? _3031_ : _2819_;
+ assign _2316_ = _0535_[1] ? _3032_ : _2820_;
+ assign _2317_ = _0535_[1] ? _3033_ : _2821_;
+ assign _2318_ = _0535_[1] ? _3034_ : _2822_;
+ assign _2319_ = _0535_[1] ? _3035_ : _2823_;
+ assign _2320_ = _0535_[1] ? _3036_ : _2824_;
+ assign _2321_ = _0535_[3] ? _3037_ : _2825_;
+ assign _2322_ = _0535_[3] ? _3038_ : _2826_;
+ assign _0000_ = ~ _0409_;
+ assign _0001_ = d_in[0] & m_in[0];
+ assign _0002_ = ~ _0001_;
+ assign _0003_ = ~ _0012_;
+ assign _0004_ = _0003_ | _0002_;
+ assign _0005_ = m_in[1] | m_in[3];
+ assign _0006_ = ~ _0005_;
+ assign _0007_ = m_in[0] ? { 1'h1, m_in[3:1], 8'hff, m_in[131:4], 5'h10, _0006_, 1'h1 } : { 4'h0, d_in };
+ assign _0008_ = _0000_ ? _0007_ : r0;
+ assign _0009_ = _0000_ ? 1'h1 : 1'h0;
+ assign _0010_ = rst ? 1'h0 : _0008_[0];
+ assign _0011_ = rst ? r0[146:1] : _0008_[146:1];
+ assign _0012_ = rst ? 1'h0 : _0009_;
+ always @(posedge clk)
+ _0013_ <= _0004_;
+ always @(posedge clk)
+ r0 <= { _0011_, _0010_ };
+ assign _0014_ = ~ _0409_;
+ assign _0015_ = r0[0] & _0014_;
+ assign _0016_ = ~ _0509_[0];
+ assign r0_valid = _0015_ & _0016_;
+ assign _0017_ = m_in[0] ? m_in[21:16] : d_in[24:19];
+ assign _0018_ = _0409_ ? r0[24:19] : _0017_;
+ assign _0019_ = 6'h3f - _0018_;
+ always @(posedge clk)
+ tlb_valid_way <= _0652_;
+ assign _0020_ = { 26'h0000000, r0[24:19] } == 32'd0;
+ assign _0021_ = tlb_hit & _0020_;
+ assign \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en = _0021_ ? 1'h1 : 1'h0;
+ assign _0022_ = { 26'h0000000, r0[24:19] } == 32'd1;
+ assign _0023_ = tlb_hit & _0022_;
+ assign \maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en = _0023_ ? 1'h1 : 1'h0;
+ assign _0024_ = { 26'h0000000, r0[24:19] } == 32'd2;
+ assign _0025_ = tlb_hit & _0024_;
+ assign \maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en = _0025_ ? 1'h1 : 1'h0;
+ assign _0026_ = { 26'h0000000, r0[24:19] } == 32'd3;
+ assign _0027_ = tlb_hit & _0026_;
+ assign \maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en = _0027_ ? 1'h1 : 1'h0;
+ assign _0028_ = { 26'h0000000, r0[24:19] } == 32'd4;
+ assign _0029_ = tlb_hit & _0028_;
+ assign \maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en = _0029_ ? 1'h1 : 1'h0;
+ assign _0030_ = { 26'h0000000, r0[24:19] } == 32'd5;
+ assign _0031_ = tlb_hit & _0030_;
+ assign \maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en = _0031_ ? 1'h1 : 1'h0;
+ assign _0032_ = { 26'h0000000, r0[24:19] } == 32'd6;
+ assign _0033_ = tlb_hit & _0032_;
+ assign \maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en = _0033_ ? 1'h1 : 1'h0;
+ assign _0034_ = { 26'h0000000, r0[24:19] } == 32'd7;
+ assign _0035_ = tlb_hit & _0034_;
+ assign \maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en = _0035_ ? 1'h1 : 1'h0;
+ assign _0036_ = { 26'h0000000, r0[24:19] } == 32'd8;
+ assign _0037_ = tlb_hit & _0036_;
+ assign \maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en = _0037_ ? 1'h1 : 1'h0;
+ assign _0038_ = { 26'h0000000, r0[24:19] } == 32'd9;
+ assign _0039_ = tlb_hit & _0038_;
+ assign \maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en = _0039_ ? 1'h1 : 1'h0;
+ assign _0040_ = { 26'h0000000, r0[24:19] } == 32'd10;
+ assign _0041_ = tlb_hit & _0040_;
+ assign \maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en = _0041_ ? 1'h1 : 1'h0;
+ assign _0042_ = { 26'h0000000, r0[24:19] } == 32'd11;
+ assign _0043_ = tlb_hit & _0042_;
+ assign \maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en = _0043_ ? 1'h1 : 1'h0;
+ assign _0044_ = { 26'h0000000, r0[24:19] } == 32'd12;
+ assign _0045_ = tlb_hit & _0044_;
+ assign \maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en = _0045_ ? 1'h1 : 1'h0;
+ assign _0046_ = { 26'h0000000, r0[24:19] } == 32'd13;
+ assign _0047_ = tlb_hit & _0046_;
+ assign \maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en = _0047_ ? 1'h1 : 1'h0;
+ assign _0048_ = { 26'h0000000, r0[24:19] } == 32'd14;
+ assign _0049_ = tlb_hit & _0048_;
+ assign \maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en = _0049_ ? 1'h1 : 1'h0;
+ assign _0050_ = { 26'h0000000, r0[24:19] } == 32'd15;
+ assign _0051_ = tlb_hit & _0050_;
+ assign \maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en = _0051_ ? 1'h1 : 1'h0;
+ assign _0052_ = { 26'h0000000, r0[24:19] } == 32'd16;
+ assign _0053_ = tlb_hit & _0052_;
+ assign \maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en = _0053_ ? 1'h1 : 1'h0;
+ assign _0054_ = { 26'h0000000, r0[24:19] } == 32'd17;
+ assign _0055_ = tlb_hit & _0054_;
+ assign \maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en = _0055_ ? 1'h1 : 1'h0;
+ assign _0056_ = { 26'h0000000, r0[24:19] } == 32'd18;
+ assign _0057_ = tlb_hit & _0056_;
+ assign \maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en = _0057_ ? 1'h1 : 1'h0;
+ assign _0058_ = { 26'h0000000, r0[24:19] } == 32'd19;
+ assign _0059_ = tlb_hit & _0058_;
+ assign \maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en = _0059_ ? 1'h1 : 1'h0;
+ assign _0060_ = { 26'h0000000, r0[24:19] } == 32'd20;
+ assign _0061_ = tlb_hit & _0060_;
+ assign \maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en = _0061_ ? 1'h1 : 1'h0;
+ assign _0062_ = { 26'h0000000, r0[24:19] } == 32'd21;
+ assign _0063_ = tlb_hit & _0062_;
+ assign \maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en = _0063_ ? 1'h1 : 1'h0;
+ assign _0064_ = { 26'h0000000, r0[24:19] } == 32'd22;
+ assign _0065_ = tlb_hit & _0064_;
+ assign \maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en = _0065_ ? 1'h1 : 1'h0;
+ assign _0066_ = { 26'h0000000, r0[24:19] } == 32'd23;
+ assign _0067_ = tlb_hit & _0066_;
+ assign \maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en = _0067_ ? 1'h1 : 1'h0;
+ assign _0068_ = { 26'h0000000, r0[24:19] } == 32'd24;
+ assign _0069_ = tlb_hit & _0068_;
+ assign \maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en = _0069_ ? 1'h1 : 1'h0;
+ assign _0070_ = { 26'h0000000, r0[24:19] } == 32'd25;
+ assign _0071_ = tlb_hit & _0070_;
+ assign \maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en = _0071_ ? 1'h1 : 1'h0;
+ assign _0072_ = { 26'h0000000, r0[24:19] } == 32'd26;
+ assign _0073_ = tlb_hit & _0072_;
+ assign \maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en = _0073_ ? 1'h1 : 1'h0;
+ assign _0074_ = { 26'h0000000, r0[24:19] } == 32'd27;
+ assign _0075_ = tlb_hit & _0074_;
+ assign \maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en = _0075_ ? 1'h1 : 1'h0;
+ assign _0076_ = { 26'h0000000, r0[24:19] } == 32'd28;
+ assign _0077_ = tlb_hit & _0076_;
+ assign \maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en = _0077_ ? 1'h1 : 1'h0;
+ assign _0078_ = { 26'h0000000, r0[24:19] } == 32'd29;
+ assign _0079_ = tlb_hit & _0078_;
+ assign \maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en = _0079_ ? 1'h1 : 1'h0;
+ assign _0080_ = { 26'h0000000, r0[24:19] } == 32'd30;
+ assign _0081_ = tlb_hit & _0080_;
+ assign \maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en = _0081_ ? 1'h1 : 1'h0;
+ assign _0082_ = { 26'h0000000, r0[24:19] } == 32'd31;
+ assign _0083_ = tlb_hit & _0082_;
+ assign \maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en = _0083_ ? 1'h1 : 1'h0;
+ assign _0084_ = { 26'h0000000, r0[24:19] } == 32'd32;
+ assign _0085_ = tlb_hit & _0084_;
+ assign \maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en = _0085_ ? 1'h1 : 1'h0;
+ assign _0086_ = { 26'h0000000, r0[24:19] } == 32'd33;
+ assign _0087_ = tlb_hit & _0086_;
+ assign \maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en = _0087_ ? 1'h1 : 1'h0;
+ assign _0088_ = { 26'h0000000, r0[24:19] } == 32'd34;
+ assign _0089_ = tlb_hit & _0088_;
+ assign \maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en = _0089_ ? 1'h1 : 1'h0;
+ assign _0090_ = { 26'h0000000, r0[24:19] } == 32'd35;
+ assign _0091_ = tlb_hit & _0090_;
+ assign \maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en = _0091_ ? 1'h1 : 1'h0;
+ assign _0092_ = { 26'h0000000, r0[24:19] } == 32'd36;
+ assign _0093_ = tlb_hit & _0092_;
+ assign \maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en = _0093_ ? 1'h1 : 1'h0;
+ assign _0094_ = { 26'h0000000, r0[24:19] } == 32'd37;
+ assign _0095_ = tlb_hit & _0094_;
+ assign \maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en = _0095_ ? 1'h1 : 1'h0;
+ assign _0096_ = { 26'h0000000, r0[24:19] } == 32'd38;
+ assign _0097_ = tlb_hit & _0096_;
+ assign \maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en = _0097_ ? 1'h1 : 1'h0;
+ assign _0098_ = { 26'h0000000, r0[24:19] } == 32'd39;
+ assign _0099_ = tlb_hit & _0098_;
+ assign \maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en = _0099_ ? 1'h1 : 1'h0;
+ assign _0100_ = { 26'h0000000, r0[24:19] } == 32'd40;
+ assign _0101_ = tlb_hit & _0100_;
+ assign \maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en = _0101_ ? 1'h1 : 1'h0;
+ assign _0102_ = { 26'h0000000, r0[24:19] } == 32'd41;
+ assign _0103_ = tlb_hit & _0102_;
+ assign \maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en = _0103_ ? 1'h1 : 1'h0;
+ assign _0104_ = { 26'h0000000, r0[24:19] } == 32'd42;
+ assign _0105_ = tlb_hit & _0104_;
+ assign \maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en = _0105_ ? 1'h1 : 1'h0;
+ assign _0106_ = { 26'h0000000, r0[24:19] } == 32'd43;
+ assign _0107_ = tlb_hit & _0106_;
+ assign \maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en = _0107_ ? 1'h1 : 1'h0;
+ assign _0108_ = { 26'h0000000, r0[24:19] } == 32'd44;
+ assign _0109_ = tlb_hit & _0108_;
+ assign \maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en = _0109_ ? 1'h1 : 1'h0;
+ assign _0110_ = { 26'h0000000, r0[24:19] } == 32'd45;
+ assign _0111_ = tlb_hit & _0110_;
+ assign \maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en = _0111_ ? 1'h1 : 1'h0;
+ assign _0112_ = { 26'h0000000, r0[24:19] } == 32'd46;
+ assign _0113_ = tlb_hit & _0112_;
+ assign \maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en = _0113_ ? 1'h1 : 1'h0;
+ assign _0114_ = { 26'h0000000, r0[24:19] } == 32'd47;
+ assign _0115_ = tlb_hit & _0114_;
+ assign \maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en = _0115_ ? 1'h1 : 1'h0;
+ assign _0116_ = { 26'h0000000, r0[24:19] } == 32'd48;
+ assign _0117_ = tlb_hit & _0116_;
+ assign \maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en = _0117_ ? 1'h1 : 1'h0;
+ assign _0118_ = { 26'h0000000, r0[24:19] } == 32'd49;
+ assign _0119_ = tlb_hit & _0118_;
+ assign \maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en = _0119_ ? 1'h1 : 1'h0;
+ assign _0120_ = { 26'h0000000, r0[24:19] } == 32'd50;
+ assign _0121_ = tlb_hit & _0120_;
+ assign \maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en = _0121_ ? 1'h1 : 1'h0;
+ assign _0122_ = { 26'h0000000, r0[24:19] } == 32'd51;
+ assign _0123_ = tlb_hit & _0122_;
+ assign \maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en = _0123_ ? 1'h1 : 1'h0;
+ assign _0124_ = { 26'h0000000, r0[24:19] } == 32'd52;
+ assign _0125_ = tlb_hit & _0124_;
+ assign \maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en = _0125_ ? 1'h1 : 1'h0;
+ assign _0126_ = { 26'h0000000, r0[24:19] } == 32'd53;
+ assign _0127_ = tlb_hit & _0126_;
+ assign \maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en = _0127_ ? 1'h1 : 1'h0;
+ assign _0128_ = { 26'h0000000, r0[24:19] } == 32'd54;
+ assign _0129_ = tlb_hit & _0128_;
+ assign \maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en = _0129_ ? 1'h1 : 1'h0;
+ assign _0130_ = { 26'h0000000, r0[24:19] } == 32'd55;
+ assign _0131_ = tlb_hit & _0130_;
+ assign \maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en = _0131_ ? 1'h1 : 1'h0;
+ assign _0132_ = { 26'h0000000, r0[24:19] } == 32'd56;
+ assign _0133_ = tlb_hit & _0132_;
+ assign \maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en = _0133_ ? 1'h1 : 1'h0;
+ assign _0134_ = { 26'h0000000, r0[24:19] } == 32'd57;
+ assign _0135_ = tlb_hit & _0134_;
+ assign \maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en = _0135_ ? 1'h1 : 1'h0;
+ assign _0136_ = { 26'h0000000, r0[24:19] } == 32'd58;
+ assign _0137_ = tlb_hit & _0136_;
+ assign \maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en = _0137_ ? 1'h1 : 1'h0;
+ assign _0138_ = { 26'h0000000, r0[24:19] } == 32'd59;
+ assign _0139_ = tlb_hit & _0138_;
+ assign \maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en = _0139_ ? 1'h1 : 1'h0;
+ assign _0140_ = { 26'h0000000, r0[24:19] } == 32'd60;
+ assign _0141_ = tlb_hit & _0140_;
+ assign \maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en = _0141_ ? 1'h1 : 1'h0;
+ assign _0142_ = { 26'h0000000, r0[24:19] } == 32'd61;
+ assign _0143_ = tlb_hit & _0142_;
+ assign \maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en = _0143_ ? 1'h1 : 1'h0;
+ assign _0144_ = { 26'h0000000, r0[24:19] } == 32'd62;
+ assign _0145_ = tlb_hit & _0144_;
+ assign \maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en = _0145_ ? 1'h1 : 1'h0;
+ assign _0146_ = { 26'h0000000, r0[24:19] } == 32'd63;
+ assign _0147_ = tlb_hit & _0146_;
+ assign \maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en = _0147_ ? 1'h1 : 1'h0;
+ assign _0148_ = tlb_tag_way[45:0] == r0[70:25];
+ assign _0149_ = tlb_valid_way[0] & _0148_;
+ assign _0150_ = _0149_ ? 1'h1 : 1'h0;
+ assign _0151_ = tlb_tag_way[91:46] == r0[70:25];
+ assign _0152_ = tlb_valid_way[1] & _0151_;
+ assign tlb_hit_way = _0152_ ? 1'h1 : 1'h0;
+ assign _0153_ = _0152_ ? 1'h1 : _0150_;
+ assign tlb_hit = _0153_ & r0_valid;
+ assign pte = tlb_hit ? _0653_ : 64'h0000000000000000;
+ assign _0154_ = ~ r0[5];
+ assign valid_ra = tlb_hit | _0154_;
+ assign ra = r0[5] ? { pte[55:12], r0[18:7] } : r0[62:7];
+ assign perm_attr = r0[5] ? { pte[1], pte[2], pte[3], pte[5], pte[7], pte[8] } : 6'h3b;
+ assign _0155_ = r0_valid & r0[143];
+ assign _0156_ = r0_valid & r0[145];
+ assign _0157_ = _0155_ & r0[144];
+ assign _0158_ = rst | _0157_;
+ assign _0159_ = 6'h3f - r0[24:19];
+ assign _0160_ = tlb_hit ? { _1040_, _1039_, _1038_, _1037_, _1036_, _1035_, _1034_, _1033_, _1032_, _1031_, _1030_, _1029_, _1028_, _1027_, _1026_, _1025_, _1024_, _1023_, _1022_, _1021_, _1020_, _1019_, _1018_, _1017_, _1016_, _1015_, _1014_, _1013_, _1012_, _1011_, _1010_, _1009_, _1008_, _1007_, _1006_, _1005_, _1004_, _1003_, _1002_, _1001_, _1000_, _0999_, _0998_, _0997_, _0996_, _0995_, _0994_, _0993_, _0992_, _0991_, _0990_, _0989_, _0988_, _0987_, _0986_, _0985_, _0984_, _0983_, _0982_, _0981_, _0980_, _0979_, _0978_, _0977_, _0976_, _0975_, _0974_, _0973_, _0972_, _0971_, _0970_, _0969_, _0968_, _0967_, _0966_, _0965_, _0964_, _0963_, _0962_, _0961_, _0960_, _0959_, _0958_, _0957_, _0956_, _0955_, _0954_, _0953_, _0952_, _0951_, _0950_, _0949_, _0948_, _0947_, _0946_, _0945_, _0944_, _0943_, _0942_, _0941_, _0940_, _0939_, _0938_, _0937_, _0936_, _0935_, _0934_, _0933_, _0932_, _0931_, _0930_, _0929_, _0928_, _0927_, _0926_, _0925_, _0924_, _0923_, _0922_, _0921_, _0920_, _0919_, _0918_, _0917_, _0916_, _0915_, _0914_, _0913_ } : dtlb_valids;
+ assign _0161_ = 6'h3f - r0[24:19];
+ assign _0162_ = tlb_hit ? tlb_hit_way : _1061_;
+ assign _0163_ = 6'h3f - r0[24:19];
+ assign _0164_ = _0156_ ? { _1454_, _1453_, _1452_, _1451_, _1450_, _1449_, _1448_, _1447_, _1446_, _1445_, _1444_, _1443_, _1442_, _1441_, _1440_, _1439_, _1438_, _1437_, _1436_, _1435_, _1434_, _1433_, _1432_, _1431_, _1430_, _1429_, _1428_, _1427_, _1426_, _1425_, _1424_, _1423_, _1422_, _1421_, _1420_, _1419_, _1418_, _1417_, _1416_, _1415_, _1414_, _1413_, _1412_, _1411_, _1410_, _1409_, _1408_, _1407_, _1406_, _1405_, _1404_, _1403_, _1402_, _1401_, _1400_, _1399_, _1398_, _1397_, _1396_, _1395_, _1394_, _1393_, _1392_, _1391_, _1390_, _1389_, _1388_, _1387_, _1386_, _1385_, _1384_, _1383_, _1382_, _1381_, _1380_, _1379_, _1378_, _1377_, _1376_, _1375_, _1374_, _1373_, _1372_, _1371_, _1370_, _1369_, _1368_, _1367_, _1366_, _1365_, _1364_, _1363_, _1362_, _1361_, _1360_, _1359_, _1358_, _1357_, _1356_, _1355_, _1354_, _1353_, _1352_, _1351_, _1350_, _1349_, _1348_, _1347_, _1346_, _1345_, _1344_, _1343_, _1342_, _1341_, _1340_, _1339_, _1338_, _1337_, _1336_, _1335_, _1334_, _1333_, _1332_, _1331_, _1330_, _1329_, _1328_, _1327_ } : dtlb_valids;
+ assign _0165_ = _0155_ ? _0160_ : _0164_;
+ assign _0166_ = _0158_ ? 128'h00000000000000000000000000000000 : _0165_;
+ always @(posedge clk)
+ dtlb_valids <= _0166_;
+ assign _0167_ = ~ _0158_;
+ assign _0168_ = ~ _0155_;
+ assign _0169_ = _0167_ & _0168_;
+ assign _0170_ = _0169_ & _0156_;
+ assign _0171_ = ~ _0158_;
+ assign _0172_ = ~ _0155_;
+ assign _0173_ = _0171_ & _0172_;
+ assign _0174_ = _0173_ & _0156_;
+ assign _0175_ = req_op == 3'h1;
+ assign _0176_ = req_op == 3'h6;
+ assign _0177_ = _0175_ | _0176_;
+ assign _0178_ = { 27'h0000000, r0[17:13] } == 32'd0;
+ assign _0179_ = _0177_ & _0178_;
+ assign \maybe_plrus.plrus%0.plru_acc_en = _0179_ ? 1'h1 : 1'h0;
+ assign _0180_ = req_op == 3'h1;
+ assign _0181_ = req_op == 3'h6;
+ assign _0182_ = _0180_ | _0181_;
+ assign _0183_ = { 27'h0000000, r0[17:13] } == 32'd1;
+ assign _0184_ = _0182_ & _0183_;
+ assign \maybe_plrus.plrus%1.plru_acc_en = _0184_ ? 1'h1 : 1'h0;
+ assign _0185_ = req_op == 3'h1;
+ assign _0186_ = req_op == 3'h6;
+ assign _0187_ = _0185_ | _0186_;
+ assign _0188_ = { 27'h0000000, r0[17:13] } == 32'd2;
+ assign _0189_ = _0187_ & _0188_;
+ assign \maybe_plrus.plrus%2.plru_acc_en = _0189_ ? 1'h1 : 1'h0;
+ assign _0190_ = req_op == 3'h1;
+ assign _0191_ = req_op == 3'h6;
+ assign _0192_ = _0190_ | _0191_;
+ assign _0193_ = { 27'h0000000, r0[17:13] } == 32'd3;
+ assign _0194_ = _0192_ & _0193_;
+ assign \maybe_plrus.plrus%3.plru_acc_en = _0194_ ? 1'h1 : 1'h0;
+ assign _0195_ = req_op == 3'h1;
+ assign _0196_ = req_op == 3'h6;
+ assign _0197_ = _0195_ | _0196_;
+ assign _0198_ = { 27'h0000000, r0[17:13] } == 32'd4;
+ assign _0199_ = _0197_ & _0198_;
+ assign \maybe_plrus.plrus%4.plru_acc_en = _0199_ ? 1'h1 : 1'h0;
+ assign _0200_ = req_op == 3'h1;
+ assign _0201_ = req_op == 3'h6;
+ assign _0202_ = _0200_ | _0201_;
+ assign _0203_ = { 27'h0000000, r0[17:13] } == 32'd5;
+ assign _0204_ = _0202_ & _0203_;
+ assign \maybe_plrus.plrus%5.plru_acc_en = _0204_ ? 1'h1 : 1'h0;
+ assign _0205_ = req_op == 3'h1;
+ assign _0206_ = req_op == 3'h6;
+ assign _0207_ = _0205_ | _0206_;
+ assign _0208_ = { 27'h0000000, r0[17:13] } == 32'd6;
+ assign _0209_ = _0207_ & _0208_;
+ assign \maybe_plrus.plrus%6.plru_acc_en = _0209_ ? 1'h1 : 1'h0;
+ assign _0210_ = req_op == 3'h1;
+ assign _0211_ = req_op == 3'h6;
+ assign _0212_ = _0210_ | _0211_;
+ assign _0213_ = { 27'h0000000, r0[17:13] } == 32'd7;
+ assign _0214_ = _0212_ & _0213_;
+ assign \maybe_plrus.plrus%7.plru_acc_en = _0214_ ? 1'h1 : 1'h0;
+ assign _0215_ = req_op == 3'h1;
+ assign _0216_ = req_op == 3'h6;
+ assign _0217_ = _0215_ | _0216_;
+ assign _0218_ = { 27'h0000000, r0[17:13] } == 32'd8;
+ assign _0219_ = _0217_ & _0218_;
+ assign \maybe_plrus.plrus%8.plru_acc_en = _0219_ ? 1'h1 : 1'h0;
+ assign _0220_ = req_op == 3'h1;
+ assign _0221_ = req_op == 3'h6;
+ assign _0222_ = _0220_ | _0221_;
+ assign _0223_ = { 27'h0000000, r0[17:13] } == 32'd9;
+ assign _0224_ = _0222_ & _0223_;
+ assign \maybe_plrus.plrus%9.plru_acc_en = _0224_ ? 1'h1 : 1'h0;
+ assign _0225_ = req_op == 3'h1;
+ assign _0226_ = req_op == 3'h6;
+ assign _0227_ = _0225_ | _0226_;
+ assign _0228_ = { 27'h0000000, r0[17:13] } == 32'd10;
+ assign _0229_ = _0227_ & _0228_;
+ assign \maybe_plrus.plrus%10.plru_acc_en = _0229_ ? 1'h1 : 1'h0;
+ assign _0230_ = req_op == 3'h1;
+ assign _0231_ = req_op == 3'h6;
+ assign _0232_ = _0230_ | _0231_;
+ assign _0233_ = { 27'h0000000, r0[17:13] } == 32'd11;
+ assign _0234_ = _0232_ & _0233_;
+ assign \maybe_plrus.plrus%11.plru_acc_en = _0234_ ? 1'h1 : 1'h0;
+ assign _0235_ = req_op == 3'h1;
+ assign _0236_ = req_op == 3'h6;
+ assign _0237_ = _0235_ | _0236_;
+ assign _0238_ = { 27'h0000000, r0[17:13] } == 32'd12;
+ assign _0239_ = _0237_ & _0238_;
+ assign \maybe_plrus.plrus%12.plru_acc_en = _0239_ ? 1'h1 : 1'h0;
+ assign _0240_ = req_op == 3'h1;
+ assign _0241_ = req_op == 3'h6;
+ assign _0242_ = _0240_ | _0241_;
+ assign _0243_ = { 27'h0000000, r0[17:13] } == 32'd13;
+ assign _0244_ = _0242_ & _0243_;
+ assign \maybe_plrus.plrus%13.plru_acc_en = _0244_ ? 1'h1 : 1'h0;
+ assign _0245_ = req_op == 3'h1;
+ assign _0246_ = req_op == 3'h6;
+ assign _0247_ = _0245_ | _0246_;
+ assign _0248_ = { 27'h0000000, r0[17:13] } == 32'd14;
+ assign _0249_ = _0247_ & _0248_;
+ assign \maybe_plrus.plrus%14.plru_acc_en = _0249_ ? 1'h1 : 1'h0;
+ assign _0250_ = req_op == 3'h1;
+ assign _0251_ = req_op == 3'h6;
+ assign _0252_ = _0250_ | _0251_;
+ assign _0253_ = { 27'h0000000, r0[17:13] } == 32'd15;
+ assign _0254_ = _0252_ & _0253_;
+ assign \maybe_plrus.plrus%15.plru_acc_en = _0254_ ? 1'h1 : 1'h0;
+ assign _0255_ = req_op == 3'h1;
+ assign _0256_ = req_op == 3'h6;
+ assign _0257_ = _0255_ | _0256_;
+ assign _0258_ = { 27'h0000000, r0[17:13] } == 32'd16;
+ assign _0259_ = _0257_ & _0258_;
+ assign \maybe_plrus.plrus%16.plru_acc_en = _0259_ ? 1'h1 : 1'h0;
+ assign _0260_ = req_op == 3'h1;
+ assign _0261_ = req_op == 3'h6;
+ assign _0262_ = _0260_ | _0261_;
+ assign _0263_ = { 27'h0000000, r0[17:13] } == 32'd17;
+ assign _0264_ = _0262_ & _0263_;
+ assign \maybe_plrus.plrus%17.plru_acc_en = _0264_ ? 1'h1 : 1'h0;
+ assign _0265_ = req_op == 3'h1;
+ assign _0266_ = req_op == 3'h6;
+ assign _0267_ = _0265_ | _0266_;
+ assign _0268_ = { 27'h0000000, r0[17:13] } == 32'd18;
+ assign _0269_ = _0267_ & _0268_;
+ assign \maybe_plrus.plrus%18.plru_acc_en = _0269_ ? 1'h1 : 1'h0;
+ assign _0270_ = req_op == 3'h1;
+ assign _0271_ = req_op == 3'h6;
+ assign _0272_ = _0270_ | _0271_;
+ assign _0273_ = { 27'h0000000, r0[17:13] } == 32'd19;
+ assign _0274_ = _0272_ & _0273_;
+ assign \maybe_plrus.plrus%19.plru_acc_en = _0274_ ? 1'h1 : 1'h0;
+ assign _0275_ = req_op == 3'h1;
+ assign _0276_ = req_op == 3'h6;
+ assign _0277_ = _0275_ | _0276_;
+ assign _0278_ = { 27'h0000000, r0[17:13] } == 32'd20;
+ assign _0279_ = _0277_ & _0278_;
+ assign \maybe_plrus.plrus%20.plru_acc_en = _0279_ ? 1'h1 : 1'h0;
+ assign _0280_ = req_op == 3'h1;
+ assign _0281_ = req_op == 3'h6;
+ assign _0282_ = _0280_ | _0281_;
+ assign _0283_ = { 27'h0000000, r0[17:13] } == 32'd21;
+ assign _0284_ = _0282_ & _0283_;
+ assign \maybe_plrus.plrus%21.plru_acc_en = _0284_ ? 1'h1 : 1'h0;
+ assign _0285_ = req_op == 3'h1;
+ assign _0286_ = req_op == 3'h6;
+ assign _0287_ = _0285_ | _0286_;
+ assign _0288_ = { 27'h0000000, r0[17:13] } == 32'd22;
+ assign _0289_ = _0287_ & _0288_;
+ assign \maybe_plrus.plrus%22.plru_acc_en = _0289_ ? 1'h1 : 1'h0;
+ assign _0290_ = req_op == 3'h1;
+ assign _0291_ = req_op == 3'h6;
+ assign _0292_ = _0290_ | _0291_;
+ assign _0293_ = { 27'h0000000, r0[17:13] } == 32'd23;
+ assign _0294_ = _0292_ & _0293_;
+ assign \maybe_plrus.plrus%23.plru_acc_en = _0294_ ? 1'h1 : 1'h0;
+ assign _0295_ = req_op == 3'h1;
+ assign _0296_ = req_op == 3'h6;
+ assign _0297_ = _0295_ | _0296_;
+ assign _0298_ = { 27'h0000000, r0[17:13] } == 32'd24;
+ assign _0299_ = _0297_ & _0298_;
+ assign \maybe_plrus.plrus%24.plru_acc_en = _0299_ ? 1'h1 : 1'h0;
+ assign _0300_ = req_op == 3'h1;
+ assign _0301_ = req_op == 3'h6;
+ assign _0302_ = _0300_ | _0301_;
+ assign _0303_ = { 27'h0000000, r0[17:13] } == 32'd25;
+ assign _0304_ = _0302_ & _0303_;
+ assign \maybe_plrus.plrus%25.plru_acc_en = _0304_ ? 1'h1 : 1'h0;
+ assign _0305_ = req_op == 3'h1;
+ assign _0306_ = req_op == 3'h6;
+ assign _0307_ = _0305_ | _0306_;
+ assign _0308_ = { 27'h0000000, r0[17:13] } == 32'd26;
+ assign _0309_ = _0307_ & _0308_;
+ assign \maybe_plrus.plrus%26.plru_acc_en = _0309_ ? 1'h1 : 1'h0;
+ assign _0310_ = req_op == 3'h1;
+ assign _0311_ = req_op == 3'h6;
+ assign _0312_ = _0310_ | _0311_;
+ assign _0313_ = { 27'h0000000, r0[17:13] } == 32'd27;
+ assign _0314_ = _0312_ & _0313_;
+ assign \maybe_plrus.plrus%27.plru_acc_en = _0314_ ? 1'h1 : 1'h0;
+ assign _0315_ = req_op == 3'h1;
+ assign _0316_ = req_op == 3'h6;
+ assign _0317_ = _0315_ | _0316_;
+ assign _0318_ = { 27'h0000000, r0[17:13] } == 32'd28;
+ assign _0319_ = _0317_ & _0318_;
+ assign \maybe_plrus.plrus%28.plru_acc_en = _0319_ ? 1'h1 : 1'h0;
+ assign _0320_ = req_op == 3'h1;
+ assign _0321_ = req_op == 3'h6;
+ assign _0322_ = _0320_ | _0321_;
+ assign _0323_ = { 27'h0000000, r0[17:13] } == 32'd29;
+ assign _0324_ = _0322_ & _0323_;
+ assign \maybe_plrus.plrus%29.plru_acc_en = _0324_ ? 1'h1 : 1'h0;
+ assign _0325_ = req_op == 3'h1;
+ assign _0326_ = req_op == 3'h6;
+ assign _0327_ = _0325_ | _0326_;
+ assign _0328_ = { 27'h0000000, r0[17:13] } == 32'd30;
+ assign _0329_ = _0327_ & _0328_;
+ assign \maybe_plrus.plrus%30.plru_acc_en = _0329_ ? 1'h1 : 1'h0;
+ assign _0330_ = req_op == 3'h1;
+ assign _0331_ = req_op == 3'h6;
+ assign _0332_ = _0330_ | _0331_;
+ assign _0333_ = { 27'h0000000, r0[17:13] } == 32'd31;
+ assign _0334_ = _0332_ & _0333_;
+ assign \maybe_plrus.plrus%31.plru_acc_en = _0334_ ? 1'h1 : 1'h0;
+ assign _0335_ = r0[143] | r0[145];
+ assign _0336_ = ~ _0335_;
+ assign _0337_ = r0_valid & _0336_;
+ assign _0338_ = 5'h1f - r0[17:13];
+ assign _0339_ = _0337_ & _1465_;
+ assign _0340_ = 5'h1f - r0[17:13];
+ assign _0341_ = _1476_[44:0] == { tlb_pte_way[55:12], r0[18] };
+ assign _0342_ = _0339_ & _0341_;
+ assign _0343_ = _0342_ & tlb_valid_way[0];
+ assign _0344_ = _0343_ ? 1'h1 : 1'h0;
+ assign _0345_ = _0343_ ? 1'h0 : 1'h0;
+ assign _0346_ = 5'h1f - r0[17:13];
+ assign _0347_ = _0337_ & _1487_;
+ assign _0348_ = 5'h1f - r0[17:13];
+ assign _0349_ = _1498_[89:45] == { tlb_pte_way[55:12], r0[18] };
+ assign _0350_ = _0347_ & _0349_;
+ assign _0351_ = _0350_ & tlb_valid_way[0];
+ assign _0352_ = _0351_ ? 1'h1 : _0344_;
+ assign _0353_ = _0351_ ? 1'h1 : _0345_;
+ assign _0354_ = 5'h1f - r0[17:13];
+ assign _0355_ = _0337_ & _1509_;
+ assign _0356_ = 5'h1f - r0[17:13];
+ assign _0357_ = _1520_[44:0] == { tlb_pte_way[119:76], r0[18] };
+ assign _0358_ = _0355_ & _0357_;
+ assign _0359_ = _0358_ & tlb_valid_way[1];
+ assign _0360_ = _0359_ ? 1'h1 : 1'h0;
+ assign _0361_ = _0359_ ? 1'h0 : 1'h0;
+ assign _0362_ = 5'h1f - r0[17:13];
+ assign _0363_ = _0337_ & _1531_;
+ assign _0364_ = 5'h1f - r0[17:13];
+ assign _0365_ = _1542_[89:45] == { tlb_pte_way[119:76], r0[18] };
+ assign _0366_ = _0363_ & _0365_;
+ assign _0367_ = _0366_ & tlb_valid_way[1];
+ assign _0368_ = _0367_ ? 1'h1 : _0360_;
+ assign _0369_ = _0367_ ? 1'h1 : _0361_;
+ assign _0370_ = 1'h1 - tlb_hit_way;
+ assign _0371_ = tlb_hit ? _1543_ : 1'h0;
+ assign _0372_ = tlb_hit ? _1544_ : 1'h0;
+ assign _0373_ = 5'h1f - r0[17:13];
+ assign _0374_ = _0337_ & _1555_;
+ assign _0375_ = 5'h1f - r0[17:13];
+ assign _0376_ = _1566_[44:0] == r0[62:18];
+ assign _0377_ = _0374_ & _0376_;
+ assign _0378_ = _0377_ ? 1'h1 : 1'h0;
+ assign _0379_ = 5'h1f - r0[17:13];
+ assign _0380_ = _0337_ & _1577_;
+ assign _0381_ = 5'h1f - r0[17:13];
+ assign _0382_ = _1588_[89:45] == r0[62:18];
+ assign _0383_ = _0380_ & _0382_;
+ assign _0384_ = _0383_ ? 1'h1 : _0378_;
+ assign _0385_ = _0383_ ? 1'h1 : 1'h0;
+ assign _0386_ = r0[5] ? _0371_ : _0384_;
+ assign req_hit_way = r0[5] ? _0372_ : _0385_;
+ assign _0387_ = 5'h1f - r0[17:13];
+ assign _0388_ = r0[1] | perm_attr[1];
+ assign rc_ok = perm_attr[0] & _0388_;
+ assign _0389_ = ~ perm_attr[3];
+ assign _0390_ = r0[6] | _0389_;
+ assign _0391_ = r0[1] & perm_attr[4];
+ assign _0392_ = perm_attr[5] | _0391_;
+ assign perm_ok = _0390_ & _0392_;
+ assign _0393_ = r0[3] | perm_attr[2];
+ assign _0394_ = valid_ra & rc_ok;
+ assign _0395_ = _0394_ & perm_ok;
+ assign _0396_ = { r0[1], _0393_, _0386_ } == 3'h5;
+ assign _0397_ = { r0[1], _0393_, _0386_ } == 3'h4;
+ assign _0398_ = { r0[1], _0393_, _0386_ } == 3'h6;
+ assign _0399_ = { r0[1], _0393_, _0386_ } == 3'h1;
+ assign _0400_ = { r0[1], _0393_, _0386_ } == 3'h0;
+ assign _0401_ = { r0[1], _0393_, _0386_ } == 3'h2;
+ assign _0402_ = { r0[1], _0393_, _0386_ } == 3'h3;
+ assign _0403_ = { r0[1], _0393_, _0386_ } == 3'h7;
+ function [2:0] \12974 ;
+ input [2:0] a;
+ input [23:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \12974 = b[2:0];
+ 8'b??????1?:
+ \12974 = b[5:3];
+ 8'b?????1??:
+ \12974 = b[8:6];
+ 8'b????1???:
+ \12974 = b[11:9];
+ 8'b???1????:
+ \12974 = b[14:12];
+ 8'b??1?????:
+ \12974 = b[17:15];
+ 8'b?1??????:
+ \12974 = b[20:18];
+ 8'b1???????:
+ \12974 = b[23:21];
+ default:
+ \12974 = a;
+ endcase
+ endfunction
+ assign _0404_ = \12974 (3'h0, 24'h93fcd1, { _0403_, _0402_, _0401_, _0400_, _0399_, _0398_, _0397_, _0396_ });
+ assign _0405_ = _0395_ ? _0404_ : 3'h5;
+ assign req_op = _0337_ ? _0405_ : 3'h0;
+ assign _0406_ = ~ _0409_;
+ assign _0407_ = m_in[0] ? m_in[14:7] : d_in[17:10];
+ assign early_req_row = _0406_ ? _0407_ : r0[17:10];
+ assign _0408_ = _0629_[68:66] != 3'h0;
+ assign _0409_ = _0408_ ? 1'h1 : 1'h0;
+ assign _0410_ = r0_valid & r0[4];
+ assign _0411_ = ~ reservation[0];
+ assign _0412_ = r0[70:13] != reservation[58:1];
+ assign _0413_ = _0411_ | _0412_;
+ assign _0414_ = _0413_ ? 1'h1 : 1'h0;
+ assign _0415_ = r0[1] ? 1'h0 : _0414_;
+ assign _0416_ = r0[1] ? 1'h1 : 1'h0;
+ assign _0417_ = r0[1] ? 1'h0 : 1'h1;
+ assign cancel_store = _0410_ ? _0415_ : 1'h0;
+ assign set_rsrv = _0410_ ? _0416_ : 1'h0;
+ assign clear_rsrv = _0410_ ? _0417_ : 1'h0;
+ assign _0418_ = rst | clear_rsrv;
+ assign _0419_ = set_rsrv ? { r0[70:13], 1'h1 } : reservation;
+ assign _0420_ = _0418_ ? 1'h0 : _0419_[0];
+ assign _0421_ = _0418_ ? reservation[58:1] : _0419_[58:1];
+ always @(posedge clk)
+ reservation <= { _0421_, _0420_ };
+ assign _0422_ = 1'h1 - _0508_[144];
+ assign _0423_ = 1'h1 - _0508_[144];
+ assign _0424_ = _0629_[64] & _0629_[65];
+ assign _0425_ = _0424_ != 1'h1;
+ assign _0426_ = _0629_[64] | _0629_[65];
+ assign _0427_ = _0426_ & _0508_[145];
+ assign _0428_ = _0427_ != 1'h1;
+ assign _0429_ = ~ _0508_[143];
+ assign _0430_ = _0508_[145] ? 1'h1 : 1'h0;
+ assign _0431_ = _0509_[0] ? 1'h1 : _0430_;
+ assign _0432_ = _0509_[0] ? { _0509_[1], 1'h1 } : 2'h0;
+ assign _0433_ = _0508_[1] ? _0629_[63:0] : _1599_;
+ assign _0434_ = _0629_[64] ? { 1'h1, _0433_, 1'h1 } : { 1'h0, _1599_, _0431_ };
+ assign _0435_ = _0629_[65] ? 1'h1 : _0434_[0];
+ assign _0436_ = _0629_[65] ? 1'h0 : _0434_[65];
+ assign _0437_ = _0508_[145] ? 1'h1 : _0509_[2];
+ assign _0438_ = _0509_[0] ? 2'h3 : { 1'h0, _0437_ };
+ assign _0439_ = _0629_[64] ? 1'h1 : _0438_[0];
+ assign _0440_ = _0629_[64] ? _0629_[63:0] : _1600_;
+ assign _0441_ = _0429_ ? { _0432_, _0436_, _0434_[64:1], _0435_ } : { 3'h0, _1599_, 1'h0 };
+ assign _0442_ = _0429_ ? { _1600_, 1'h0, _0509_[2] } : { _0440_, _0438_[1], _0439_ };
+ assign _0443_ = _0629_[68:66] == 3'h0;
+ assign _0444_ = _0508_[2] ? 64'h0000000000000000 : wishbone_in[63:0];
+ assign \rams%0.wr_addr = _0443_ ? r0[17:10] : _0629_[184:177];
+ assign \rams%0.wr_data = _0443_ ? r0[134:71] : _0444_;
+ assign \rams%0.wr_sel = _0443_ ? r0[142:135] : 8'hff;
+ assign _0445_ = _0629_[68:66] == 3'h1;
+ assign _0446_ = _0445_ & wishbone_in[64];
+ assign _0447_ = { 31'h00000000, _0629_[176] } == 32'd0;
+ assign _0448_ = _0446_ & _0447_;
+ assign _0449_ = _0448_ ? 1'h1 : 1'h0;
+ assign _0450_ = req_op == 3'h6;
+ assign _0451_ = { 31'h00000000, req_hit_way } == 32'd0;
+ assign _0452_ = _0450_ & _0451_;
+ assign _0453_ = ~ cancel_store;
+ assign _0454_ = _0452_ & _0453_;
+ assign _0455_ = ~ r0[2];
+ assign _0456_ = _0454_ & _0455_;
+ assign _0457_ = ~ _0445_;
+ assign _0458_ = ~ _0460_;
+ assign _0459_ = _0458_ | _0457_;
+ assign \rams%0.do_write = _0456_ ? 1'h1 : _0449_;
+ assign _0460_ = _0456_ ? 1'h1 : 1'h0;
+ assign _0461_ = \rams%0.wr_sel [0] & \rams%0.do_write ;
+ assign _0462_ = \rams%0.wr_sel [1] & \rams%0.do_write ;
+ assign _0463_ = \rams%0.wr_sel [2] & \rams%0.do_write ;
+ assign _0464_ = \rams%0.wr_sel [3] & \rams%0.do_write ;
+ assign _0465_ = \rams%0.wr_sel [4] & \rams%0.do_write ;
+ assign _0466_ = \rams%0.wr_sel [5] & \rams%0.do_write ;
+ assign _0467_ = \rams%0.wr_sel [6] & \rams%0.do_write ;
+ assign _0468_ = \rams%0.wr_sel [7] & \rams%0.do_write ;
+ assign _0469_ = _0629_[68:66] == 3'h0;
+ assign _0470_ = _0508_[2] ? 64'h0000000000000000 : wishbone_in[63:0];
+ assign \rams%1.wr_addr = _0469_ ? r0[17:10] : _0629_[184:177];
+ assign \rams%1.wr_data = _0469_ ? r0[134:71] : _0470_;
+ assign \rams%1.wr_sel = _0469_ ? r0[142:135] : 8'hff;
+ assign _0471_ = _0629_[68:66] == 3'h1;
+ assign _0472_ = _0471_ & wishbone_in[64];
+ assign _0473_ = { 31'h00000000, _0629_[176] } == 32'd1;
+ assign _0474_ = _0472_ & _0473_;
+ assign _0475_ = _0474_ ? 1'h1 : 1'h0;
+ assign _0476_ = req_op == 3'h6;
+ assign _0477_ = { 31'h00000000, req_hit_way } == 32'd1;
+ assign _0478_ = _0476_ & _0477_;
+ assign _0479_ = ~ cancel_store;
+ assign _0480_ = _0478_ & _0479_;
+ assign _0481_ = ~ r0[2];
+ assign _0482_ = _0480_ & _0481_;
+ assign _0483_ = ~ _0471_;
+ assign _0484_ = ~ _0486_;
+ assign _0485_ = _0484_ | _0483_;
+ assign \rams%1.do_write = _0482_ ? 1'h1 : _0475_;
+ assign _0486_ = _0482_ ? 1'h1 : 1'h0;
+ assign _0487_ = \rams%1.wr_sel [0] & \rams%1.do_write ;
+ assign _0488_ = \rams%1.wr_sel [1] & \rams%1.do_write ;
+ assign _0489_ = \rams%1.wr_sel [2] & \rams%1.do_write ;
+ assign _0490_ = \rams%1.wr_sel [3] & \rams%1.do_write ;
+ assign _0491_ = \rams%1.wr_sel [4] & \rams%1.do_write ;
+ assign _0492_ = \rams%1.wr_sel [5] & \rams%1.do_write ;
+ assign _0493_ = \rams%1.wr_sel [6] & \rams%1.do_write ;
+ assign _0494_ = \rams%1.wr_sel [7] & \rams%1.do_write ;
+ assign _0495_ = req_op != 3'h0;
+ assign _0496_ = ~ _0409_;
+ assign _0497_ = _0495_ & _0496_;
+ assign _0498_ = _0497_ ? { r0[146], r0[142:0] } : _0508_[143:0];
+ assign _0499_ = req_op == 3'h1;
+ assign _0500_ = _0499_ ? req_hit_way : _0508_[144];
+ assign _0501_ = _0499_ ? 1'h1 : 1'h0;
+ assign _0502_ = req_op == 3'h5;
+ assign _0503_ = req_op == 3'h4;
+ assign _0504_ = _0503_ ? 2'h3 : 2'h0;
+ assign _0505_ = _0502_ ? 2'h1 : _0504_;
+ assign _0506_ = r0[143] | r0[145];
+ assign _0507_ = r0_valid & _0506_;
+ always @(posedge clk)
+ _0508_ <= { _0501_, _0500_, _0498_ };
+ always @(posedge clk)
+ _0509_ <= { _0507_, _0505_ };
+ assign _0510_ = req_op == 3'h1;
+ assign _0511_ = 5'h1f - r0[17:13];
+ assign _0512_ = 32'd0 == { 31'h00000000, replace_way };
+ assign _0513_ = 5'h1f - r0[17:13];
+ assign _0514_ = 5'h1f - r0[17:13];
+ assign _0515_ = _0512_ ? { _1902_, _1901_, _1900_, _1899_, _1898_, _1897_, _1896_, _1895_, _1894_, _1893_, _1892_, _1891_, _1890_, _1889_, _1888_, _1887_, _1886_, _1885_, _1884_, _1883_, _1882_, _1881_, _1880_, _1879_, _1878_, _1877_, _1876_, _1875_, _1874_, _1873_, _1872_, _1871_ } : cache_tags;
+ assign _0516_ = 32'd1 == { 31'h00000000, replace_way };
+ assign _0517_ = 5'h1f - r0[17:13];
+ assign _0518_ = 5'h1f - r0[17:13];
+ assign _0519_ = _0516_ ? { _2010_, _2009_, _2008_, _2007_, _2006_, _2005_, _2004_, _2003_, _2002_, _2001_, _2000_, _1999_, _1998_, _1997_, _1996_, _1995_, _1994_, _1993_, _1992_, _1991_, _1990_, _1989_, _1988_, _1987_, _1986_, _1985_, _1984_, _1983_, _1982_, _1981_, _1980_, _1979_ } : _0515_;
+ assign _0520_ = req_op == 3'h2;
+ assign _0521_ = req_op == 3'h3;
+ assign _0522_ = ~ r0[2];
+ assign _0523_ = ~ cancel_store;
+ assign _0524_ = _0523_ ? 1'h0 : 1'h1;
+ assign _0525_ = _0523_ ? 3'h3 : 3'h0;
+ assign _0526_ = _0523_ ? 2'h3 : _0629_[166:165];
+ assign _0527_ = _0523_ ? 1'h1 : _0629_[175];
+ assign _0528_ = req_op == 3'h6;
+ assign _0529_ = 5'h1f - r0[17:13];
+ assign _0530_ = 32'd0 == { 31'h00000000, replace_way };
+ assign _0531_ = 5'h1f - r0[17:13];
+ assign _0532_ = 5'h1f - r0[17:13];
+ assign _0533_ = _0530_ ? { _2312_, _2311_, _2310_, _2309_, _2308_, _2307_, _2306_, _2305_, _2304_, _2303_, _2302_, _2301_, _2300_, _2299_, _2298_, _2297_, _2296_, _2295_, _2294_, _2293_, _2292_, _2291_, _2290_, _2289_, _2288_, _2287_, _2286_, _2285_, _2284_, _2283_, _2282_, _2281_ } : cache_tags;
+ assign _0534_ = 32'd1 == { 31'h00000000, replace_way };
+ assign _0535_ = 5'h1f - r0[17:13];
+ assign _0536_ = 5'h1f - r0[17:13];
+ assign _0537_ = _0534_ ? { _2420_, _2419_, _2418_, _2417_, _2416_, _2415_, _2414_, _2413_, _2412_, _2411_, _2410_, _2409_, _2408_, _2407_, _2406_, _2405_, _2404_, _2403_, _2402_, _2401_, _2400_, _2399_, _2398_, _2397_, _2396_, _2395_, _2394_, _2393_, _2392_, _2391_, _2390_, _2389_ } : _0533_;
+ assign _0538_ = _0528_ ? cache_tags : _0537_;
+ assign _0539_ = _0528_ ? cache_valids : { _2204_, _2203_, _2202_, _2201_, _2200_, _2199_, _2198_, _2197_, _2196_, _2195_, _2194_, _2193_, _2192_, _2191_, _2190_, _2189_, _2188_, _2187_, _2186_, _2185_, _2184_, _2183_, _2182_, _2181_, _2180_, _2179_, _2178_, _2177_, _2176_, _2175_, _2174_, _2173_, _2172_, _2171_, _2170_, _2169_, _2168_, _2167_, _2166_, _2165_, _2164_, _2163_, _2162_, _2161_, _2160_, _2159_, _2158_, _2157_, _2156_, _2155_, _2154_, _2153_, _2152_, _2151_, _2150_, _2149_, _2148_, _2147_, _2146_, _2145_, _2144_, _2143_, _2142_, _2141_ };
+ assign _0540_ = _0528_ ? req_hit_way : replace_way;
+ assign _0541_ = _0522_ ? cache_tags : _0538_;
+ assign _0542_ = _0522_ ? cache_valids : _0539_;
+ assign _0543_ = _0522_ ? _0524_ : 1'h0;
+ assign _0544_ = _0522_ ? { _0527_, r0[142:135], _0526_, r0[134:71], ra[31:3], 3'h0, _0525_ } : { 75'h7ff0000000000000000, ra[31:6], 9'h001 };
+ assign _0545_ = _0522_ ? _0629_[189:176] : { r0[17:13], ra[10:6], 3'h0, _0540_ };
+ assign _0546_ = req_op == 3'h6;
+ assign _0547_ = req_op == 3'h7;
+ assign _0548_ = _0546_ | _0547_;
+ assign _0549_ = req_op == 3'h0;
+ assign _0550_ = req_op == 3'h4;
+ assign _0551_ = req_op == 3'h5;
+ function [2879:0] \13588 ;
+ input [2879:0] a;
+ input [20159:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13588 = b[2879:0];
+ 7'b?????1?:
+ \13588 = b[5759:2880];
+ 7'b????1??:
+ \13588 = b[8639:5760];
+ 7'b???1???:
+ \13588 = b[11519:8640];
+ 7'b??1????:
+ \13588 = b[14399:11520];
+ 7'b?1?????:
+ \13588 = b[17279:14400];
+ 7'b1??????:
+ \13588 = b[20159:17280];
+ default:
+ \13588 = a;
+ endcase
+ endfunction
+ assign _0552_ = \13588 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, cache_tags, cache_tags, _0541_, cache_tags, _0519_, cache_tags }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [63:0] \13590 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13590 = b[63:0];
+ 7'b?????1?:
+ \13590 = b[127:64];
+ 7'b????1??:
+ \13590 = b[191:128];
+ 7'b???1???:
+ \13590 = b[255:192];
+ 7'b??1????:
+ \13590 = b[319:256];
+ 7'b?1?????:
+ \13590 = b[383:320];
+ 7'b1??????:
+ \13590 = b[447:384];
+ default:
+ \13590 = a;
+ endcase
+ endfunction
+ assign _0553_ = \13590 (64'hxxxxxxxxxxxxxxxx, { cache_valids, cache_valids, cache_valids, _0542_, cache_valids, _1794_, _1793_, _1792_, _1791_, _1790_, _1789_, _1788_, _1787_, _1786_, _1785_, _1784_, _1783_, _1782_, _1781_, _1780_, _1779_, _1778_, _1777_, _1776_, _1775_, _1774_, _1773_, _1772_, _1771_, _1770_, _1769_, _1768_, _1767_, _1766_, _1765_, _1764_, _1763_, _1762_, _1761_, _1760_, _1759_, _1758_, _1757_, _1756_, _1755_, _1754_, _1753_, _1752_, _1751_, _1750_, _1749_, _1748_, _1747_, _1746_, _1745_, _1744_, _1743_, _1742_, _1741_, _1740_, _1739_, _1738_, _1737_, _1736_, _1735_, _1734_, _1733_, _1732_, _1731_, cache_valids }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [0:0] \13592 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13592 = b[0:0];
+ 7'b?????1?:
+ \13592 = b[1:1];
+ 7'b????1??:
+ \13592 = b[2:2];
+ 7'b???1???:
+ \13592 = b[3:3];
+ 7'b??1????:
+ \13592 = b[4:4];
+ 7'b?1?????:
+ \13592 = b[5:5];
+ 7'b1??????:
+ \13592 = b[6:6];
+ default:
+ \13592 = a;
+ endcase
+ endfunction
+ assign _0554_ = \13592 (1'hx, { 3'h0, _0543_, 3'h0 }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [2:0] \13596 ;
+ input [2:0] a;
+ input [20:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13596 = b[2:0];
+ 7'b?????1?:
+ \13596 = b[5:3];
+ 7'b????1??:
+ \13596 = b[8:6];
+ 7'b???1???:
+ \13596 = b[11:9];
+ 7'b??1????:
+ \13596 = b[14:12];
+ 7'b?1?????:
+ \13596 = b[17:15];
+ 7'b1??????:
+ \13596 = b[20:18];
+ default:
+ \13596 = a;
+ endcase
+ endfunction
+ assign _0555_ = \13596 (3'hx, { _0629_[68:66], _0629_[68:66], _0629_[68:66], _0544_[2:0], 6'h21, _0629_[68:66] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [31:0] \13600 ;
+ input [31:0] a;
+ input [223:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13600 = b[31:0];
+ 7'b?????1?:
+ \13600 = b[63:32];
+ 7'b????1??:
+ \13600 = b[95:64];
+ 7'b???1???:
+ \13600 = b[127:96];
+ 7'b??1????:
+ \13600 = b[159:128];
+ 7'b?1?????:
+ \13600 = b[191:160];
+ 7'b1??????:
+ \13600 = b[223:192];
+ default:
+ \13600 = a;
+ endcase
+ endfunction
+ assign _0556_ = \13600 (32'hxxxxxxxx, { _0629_[100:69], _0629_[100:69], _0629_[100:69], _0544_[34:3], ra[31:3], 3'h0, ra[31:6], 6'h00, _0629_[100:69] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [63:0] \13604 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13604 = b[63:0];
+ 7'b?????1?:
+ \13604 = b[127:64];
+ 7'b????1??:
+ \13604 = b[191:128];
+ 7'b???1???:
+ \13604 = b[255:192];
+ 7'b??1????:
+ \13604 = b[319:256];
+ 7'b?1?????:
+ \13604 = b[383:320];
+ 7'b1??????:
+ \13604 = b[447:384];
+ default:
+ \13604 = a;
+ endcase
+ endfunction
+ assign _0557_ = \13604 (64'hxxxxxxxxxxxxxxxx, { _0629_[164:101], _0629_[164:101], _0629_[164:101], _0544_[98:35], _0629_[164:101], _0629_[164:101], _0629_[164:101] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [0:0] \13608 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13608 = b[0:0];
+ 7'b?????1?:
+ \13608 = b[1:1];
+ 7'b????1??:
+ \13608 = b[2:2];
+ 7'b???1???:
+ \13608 = b[3:3];
+ 7'b??1????:
+ \13608 = b[4:4];
+ 7'b?1?????:
+ \13608 = b[5:5];
+ 7'b1??????:
+ \13608 = b[6:6];
+ default:
+ \13608 = a;
+ endcase
+ endfunction
+ assign _0558_ = \13608 (1'hx, { _0629_[165], _0629_[165], _0629_[165], _0544_[99], 2'h3, _0629_[165] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [0:0] \13612 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13612 = b[0:0];
+ 7'b?????1?:
+ \13612 = b[1:1];
+ 7'b????1??:
+ \13612 = b[2:2];
+ 7'b???1???:
+ \13612 = b[3:3];
+ 7'b??1????:
+ \13612 = b[4:4];
+ 7'b?1?????:
+ \13612 = b[5:5];
+ 7'b1??????:
+ \13612 = b[6:6];
+ default:
+ \13612 = a;
+ endcase
+ endfunction
+ assign _0559_ = \13612 (1'hx, { _0629_[166], _0629_[166], _0629_[166], _0544_[100], 2'h3, _0629_[166] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [7:0] \13616 ;
+ input [7:0] a;
+ input [55:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13616 = b[7:0];
+ 7'b?????1?:
+ \13616 = b[15:8];
+ 7'b????1??:
+ \13616 = b[23:16];
+ 7'b???1???:
+ \13616 = b[31:24];
+ 7'b??1????:
+ \13616 = b[39:32];
+ 7'b?1?????:
+ \13616 = b[47:40];
+ 7'b1??????:
+ \13616 = b[55:48];
+ default:
+ \13616 = a;
+ endcase
+ endfunction
+ assign _0560_ = \13616 (8'hxx, { _0629_[174:167], _0629_[174:167], _0629_[174:167], _0544_[108:101], r0[142:135], 8'hff, _0629_[174:167] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [0:0] \13620 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13620 = b[0:0];
+ 7'b?????1?:
+ \13620 = b[1:1];
+ 7'b????1??:
+ \13620 = b[2:2];
+ 7'b???1???:
+ \13620 = b[3:3];
+ 7'b??1????:
+ \13620 = b[4:4];
+ 7'b?1?????:
+ \13620 = b[5:5];
+ 7'b1??????:
+ \13620 = b[6:6];
+ default:
+ \13620 = a;
+ endcase
+ endfunction
+ assign _0561_ = \13620 (1'hx, { _0629_[175], _0629_[175], _0629_[175], _0544_[109], 2'h0, _0629_[175] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [0:0] \13624 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13624 = b[0:0];
+ 7'b?????1?:
+ \13624 = b[1:1];
+ 7'b????1??:
+ \13624 = b[2:2];
+ 7'b???1???:
+ \13624 = b[3:3];
+ 7'b??1????:
+ \13624 = b[4:4];
+ 7'b?1?????:
+ \13624 = b[5:5];
+ 7'b1??????:
+ \13624 = b[6:6];
+ default:
+ \13624 = a;
+ endcase
+ endfunction
+ assign _0562_ = \13624 (1'hx, { _0629_[176], _0629_[176], _0629_[176], _0545_[0], _0629_[176], replace_way, _0629_[176] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [7:0] \13628 ;
+ input [7:0] a;
+ input [55:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13628 = b[7:0];
+ 7'b?????1?:
+ \13628 = b[15:8];
+ 7'b????1??:
+ \13628 = b[23:16];
+ 7'b???1???:
+ \13628 = b[31:24];
+ 7'b??1????:
+ \13628 = b[39:32];
+ 7'b?1?????:
+ \13628 = b[47:40];
+ 7'b1??????:
+ \13628 = b[55:48];
+ default:
+ \13628 = a;
+ endcase
+ endfunction
+ assign _0563_ = \13628 (8'hxx, { _0629_[184:177], _0629_[184:177], _0629_[184:177], _0545_[8:1], _0629_[184:177], ra[10:6], 3'h0, _0629_[184:177] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ function [4:0] \13632 ;
+ input [4:0] a;
+ input [34:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \13632 = b[4:0];
+ 7'b?????1?:
+ \13632 = b[9:5];
+ 7'b????1??:
+ \13632 = b[14:10];
+ 7'b???1???:
+ \13632 = b[19:15];
+ 7'b??1????:
+ \13632 = b[24:20];
+ 7'b?1?????:
+ \13632 = b[29:25];
+ 7'b1??????:
+ \13632 = b[34:30];
+ default:
+ \13632 = a;
+ endcase
+ endfunction
+ assign _0564_ = \13632 (5'hxx, { _0629_[189:185], _0629_[189:185], _0629_[189:185], _0545_[13:9], _0629_[189:185], r0[17:13], _0629_[189:185] }, { _0551_, _0550_, _0549_, _0548_, _0521_, _0520_, _0510_ });
+ assign _0565_ = _0629_[68:66] == 3'h0;
+ assign _0566_ = ~ _0629_[166];
+ assign _0567_ = ~ wishbone_in[65];
+ assign _0568_ = ~ _0566_;
+ assign _0569_ = _0567_ & _0568_;
+ assign _0570_ = _0629_[74:72] == 3'h7;
+ assign _0571_ = _0575_ ? 1'h0 : _0629_[166];
+ assign _0572_ = _0576_ ? 1'h1 : _0566_;
+ assign _0573_ = _0629_[74:72] + 3'h1;
+ assign _0574_ = _0569_ ? { _0629_[100:75], _0573_, _0629_[71:69] } : _0629_[100:69];
+ assign _0575_ = _0569_ & _0570_;
+ assign _0576_ = _0569_ & _0570_;
+ assign _0577_ = { 24'h000000, _0629_[184:177] } == { 24'h000000, _0508_[17:10] };
+ assign _0578_ = ~ _0508_[2];
+ assign _0579_ = _0577_ & _0578_;
+ assign _0580_ = _0589_ ? wishbone_in[63:0] : _0629_[63:0];
+ assign _0581_ = _0629_[179:177] == 3'h7;
+ assign _0582_ = _0572_ & _0581_;
+ assign _0583_ = 5'h1f - _0629_[189:185];
+ assign _0584_ = _0588_ ? { _2614_, _2613_, _2612_, _2611_, _2610_, _2609_, _2608_, _2607_, _2606_, _2605_, _2604_, _2603_, _2602_, _2601_, _2600_, _2599_, _2598_, _2597_, _2596_, _2595_, _2594_, _2593_, _2592_, _2591_, _2590_, _2589_, _2588_, _2587_, _2586_, _2585_, _2584_, _2583_, _2582_, _2581_, _2580_, _2579_, _2578_, _2577_, _2576_, _2575_, _2574_, _2573_, _2572_, _2571_, _2570_, _2569_, _2568_, _2567_, _2566_, _2565_, _2564_, _2563_, _2562_, _2561_, _2560_, _2559_, _2558_, _2557_, _2556_, _2555_, _2554_, _2553_, _2552_, _2551_ } : cache_valids;
+ assign _0585_ = _0590_ ? 3'h2 : _0629_[68:66];
+ assign _0586_ = _0591_ ? 1'h0 : _0629_[165];
+ assign _0587_ = _0629_[179:177] + 3'h1;
+ assign _0588_ = wishbone_in[64] & _0582_;
+ assign _0589_ = wishbone_in[64] & _0579_;
+ assign _0590_ = wishbone_in[64] & _0582_;
+ assign _0591_ = wishbone_in[64] & _0582_;
+ assign _0592_ = wishbone_in[64] ? { _0629_[184:180], _0587_ } : _0629_[184:177];
+ assign _0593_ = _0629_[68:66] == 3'h1;
+ assign _0594_ = _0629_[68:66] == 3'h2;
+ assign _0595_ = ~ wishbone_in[65];
+ assign _0596_ = _0595_ ? 1'h0 : _0629_[166];
+ assign _0597_ = _0629_[68:66] == 3'h4;
+ assign _0598_ = _0597_ ? wishbone_in[63:0] : _0629_[63:0];
+ assign _0599_ = wishbone_in[64] ? { 1'h1, _0598_ } : { 1'h0, _0629_[63:0] };
+ assign _0600_ = wishbone_in[64] ? 3'h0 : _0629_[68:66];
+ assign _0601_ = wishbone_in[64] ? 2'h0 : { _0596_, _0629_[165] };
+ assign _0602_ = _0629_[68:66] == 3'h3;
+ assign _0603_ = _0629_[68:66] == 3'h4;
+ assign _0604_ = _0602_ | _0603_;
+ function [2879:0] \13797 ;
+ input [2879:0] a;
+ input [11519:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13797 = b[2879:0];
+ 4'b??1?:
+ \13797 = b[5759:2880];
+ 4'b?1??:
+ \13797 = b[8639:5760];
+ 4'b1???:
+ \13797 = b[11519:8640];
+ default:
+ \13797 = a;
+ endcase
+ endfunction
+ assign _0605_ = \13797 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, cache_tags, cache_tags, _0552_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [63:0] \13799 ;
+ input [63:0] a;
+ input [255:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13799 = b[63:0];
+ 4'b??1?:
+ \13799 = b[127:64];
+ 4'b?1??:
+ \13799 = b[191:128];
+ 4'b1???:
+ \13799 = b[255:192];
+ default:
+ \13799 = a;
+ endcase
+ endfunction
+ assign _0606_ = \13799 (64'hxxxxxxxxxxxxxxxx, { cache_valids, cache_valids, _0584_, _0553_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [63:0] \13803 ;
+ input [63:0] a;
+ input [255:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13803 = b[63:0];
+ 4'b??1?:
+ \13803 = b[127:64];
+ 4'b?1??:
+ \13803 = b[191:128];
+ 4'b1???:
+ \13803 = b[255:192];
+ default:
+ \13803 = a;
+ endcase
+ endfunction
+ assign _0607_ = \13803 (64'hxxxxxxxxxxxxxxxx, { _0599_[63:0], _0629_[63:0], _0580_, _0629_[63:0] }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13806 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13806 = b[0:0];
+ 4'b??1?:
+ \13806 = b[1:1];
+ 4'b?1??:
+ \13806 = b[2:2];
+ 4'b1???:
+ \13806 = b[3:3];
+ default:
+ \13806 = a;
+ endcase
+ endfunction
+ assign _0608_ = \13806 (1'hx, { _0599_[64], 3'h4 }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13808 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13808 = b[0:0];
+ 4'b??1?:
+ \13808 = b[1:1];
+ 4'b?1??:
+ \13808 = b[2:2];
+ 4'b1???:
+ \13808 = b[3:3];
+ default:
+ \13808 = a;
+ endcase
+ endfunction
+ assign _0609_ = \13808 (1'hx, { 3'h0, _0554_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [2:0] \13810 ;
+ input [2:0] a;
+ input [11:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13810 = b[2:0];
+ 4'b??1?:
+ \13810 = b[5:3];
+ 4'b?1??:
+ \13810 = b[8:6];
+ 4'b1???:
+ \13810 = b[11:9];
+ default:
+ \13810 = a;
+ endcase
+ endfunction
+ assign _0610_ = \13810 (3'hx, { _0600_, 3'h0, _0585_, _0555_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [31:0] \13813 ;
+ input [31:0] a;
+ input [127:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13813 = b[31:0];
+ 4'b??1?:
+ \13813 = b[63:32];
+ 4'b?1??:
+ \13813 = b[95:64];
+ 4'b1???:
+ \13813 = b[127:96];
+ default:
+ \13813 = a;
+ endcase
+ endfunction
+ assign _0611_ = \13813 (32'hxxxxxxxx, { _0629_[100:69], _0629_[100:69], _0574_, _0556_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [63:0] \13816 ;
+ input [63:0] a;
+ input [255:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13816 = b[63:0];
+ 4'b??1?:
+ \13816 = b[127:64];
+ 4'b?1??:
+ \13816 = b[191:128];
+ 4'b1???:
+ \13816 = b[255:192];
+ default:
+ \13816 = a;
+ endcase
+ endfunction
+ assign _0612_ = \13816 (64'hxxxxxxxxxxxxxxxx, { _0629_[164:101], _0629_[164:101], _0629_[164:101], _0557_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13820 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13820 = b[0:0];
+ 4'b??1?:
+ \13820 = b[1:1];
+ 4'b?1??:
+ \13820 = b[2:2];
+ 4'b1???:
+ \13820 = b[3:3];
+ default:
+ \13820 = a;
+ endcase
+ endfunction
+ assign _0613_ = \13820 (1'hx, { _0601_[0], _0629_[165], _0586_, _0558_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13824 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13824 = b[0:0];
+ 4'b??1?:
+ \13824 = b[1:1];
+ 4'b?1??:
+ \13824 = b[2:2];
+ 4'b1???:
+ \13824 = b[3:3];
+ default:
+ \13824 = a;
+ endcase
+ endfunction
+ assign _0614_ = \13824 (1'hx, { _0601_[1], _0629_[166], _0571_, _0559_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [7:0] \13827 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13827 = b[7:0];
+ 4'b??1?:
+ \13827 = b[15:8];
+ 4'b?1??:
+ \13827 = b[23:16];
+ 4'b1???:
+ \13827 = b[31:24];
+ default:
+ \13827 = a;
+ endcase
+ endfunction
+ assign _0615_ = \13827 (8'hxx, { _0629_[174:167], _0629_[174:167], _0629_[174:167], _0560_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13830 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13830 = b[0:0];
+ 4'b??1?:
+ \13830 = b[1:1];
+ 4'b?1??:
+ \13830 = b[2:2];
+ 4'b1???:
+ \13830 = b[3:3];
+ default:
+ \13830 = a;
+ endcase
+ endfunction
+ assign _0616_ = \13830 (1'hx, { _0629_[175], _0629_[175], _0629_[175], _0561_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [0:0] \13833 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13833 = b[0:0];
+ 4'b??1?:
+ \13833 = b[1:1];
+ 4'b?1??:
+ \13833 = b[2:2];
+ 4'b1???:
+ \13833 = b[3:3];
+ default:
+ \13833 = a;
+ endcase
+ endfunction
+ assign _0617_ = \13833 (1'hx, { _0629_[176], _0629_[176], _0629_[176], _0562_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [7:0] \13836 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13836 = b[7:0];
+ 4'b??1?:
+ \13836 = b[15:8];
+ 4'b?1??:
+ \13836 = b[23:16];
+ 4'b1???:
+ \13836 = b[31:24];
+ default:
+ \13836 = a;
+ endcase
+ endfunction
+ assign _0618_ = \13836 (8'hxx, { _0629_[184:177], _0629_[184:177], _0592_, _0563_ }, { _0604_, _0594_, _0593_, _0565_ });
+ function [4:0] \13839 ;
+ input [4:0] a;
+ input [19:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \13839 = b[4:0];
+ 4'b??1?:
+ \13839 = b[9:5];
+ 4'b?1??:
+ \13839 = b[14:10];
+ 4'b1???:
+ \13839 = b[19:15];
+ default:
+ \13839 = a;
+ endcase
+ endfunction
+ assign _0619_ = \13839 (5'hxx, { _0629_[189:185], _0629_[189:185], _0629_[189:185], _0564_ }, { _0604_, _0594_, _0593_, _0565_ });
+ assign _0620_ = rst ? cache_tags : _0605_;
+ assign _0621_ = rst ? 64'h0000000000000000 : _0606_;
+ assign _0622_ = rst ? _0629_[63:0] : _0607_;
+ assign _0623_ = rst ? 1'h0 : _0608_;
+ assign _0624_ = rst ? _0629_[65] : _0609_;
+ assign _0625_ = rst ? 35'h000000000 : { _0611_, _0610_ };
+ assign _0626_ = rst ? _0629_[164:101] : _0612_;
+ assign _0627_ = rst ? 2'h0 : { _0614_, _0613_ };
+ assign _0628_ = rst ? _0629_[189:167] : { _0619_, _0618_, _0617_, _0616_, _0615_ };
+ always @(posedge clk)
+ cache_tags <= _0620_;
+ always @(posedge clk)
+ cache_valids <= _0621_;
+ always @(posedge clk)
+ _0629_ <= { _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_ };
+ (* ram_style = "distributed" *)
+ reg [91:0] \13892 [63:0];
+ reg [91:0] _3675_;
+ always @(posedge clk) begin
+ _3675_ <= \13892 [_0018_];
+ if (_0170_) \13892 [r0[24:19]] <= { _1064_, _1063_ };
+ end
+ assign tlb_tag_way = _3675_;
+ (* ram_style = "distributed" *)
+ reg [127:0] \13896 [63:0];
+ reg [127:0] _3676_;
+ always @(posedge clk) begin
+ _3676_ <= \13896 [_0018_];
+ if (_0174_) \13896 [r0[24:19]] <= { _1067_, _1066_ };
+ end
+ assign tlb_pte_way = _3676_;
+ assign _0653_ = tlb_hit_way ? tlb_pte_way[127:64] : tlb_pte_way[63:0];
+ assign _0654_ = ~ _0159_[5];
+ assign _0655_ = ~ _0159_[4];
+ assign _0656_ = _0654_ & _0655_;
+ assign _0657_ = _0654_ & _0159_[4];
+ assign _0658_ = _0159_[5] & _0655_;
+ assign _0659_ = _0159_[5] & _0159_[4];
+ assign _0660_ = ~ _0159_[3];
+ assign _0661_ = _0656_ & _0660_;
+ assign _0662_ = _0656_ & _0159_[3];
+ assign _0663_ = _0657_ & _0660_;
+ assign _0664_ = _0657_ & _0159_[3];
+ assign _0665_ = _0658_ & _0660_;
+ assign _0666_ = _0658_ & _0159_[3];
+ assign _0667_ = _0659_ & _0660_;
+ assign _0668_ = _0659_ & _0159_[3];
+ assign _0669_ = ~ _0159_[2];
+ assign _0670_ = _0661_ & _0669_;
+ assign _0671_ = _0661_ & _0159_[2];
+ assign _0672_ = _0662_ & _0669_;
+ assign _0673_ = _0662_ & _0159_[2];
+ assign _0674_ = _0663_ & _0669_;
+ assign _0675_ = _0663_ & _0159_[2];
+ assign _0676_ = _0664_ & _0669_;
+ assign _0677_ = _0664_ & _0159_[2];
+ assign _0678_ = _0665_ & _0669_;
+ assign _0679_ = _0665_ & _0159_[2];
+ assign _0680_ = _0666_ & _0669_;
+ assign _0681_ = _0666_ & _0159_[2];
+ assign _0682_ = _0667_ & _0669_;
+ assign _0683_ = _0667_ & _0159_[2];
+ assign _0684_ = _0668_ & _0669_;
+ assign _0685_ = _0668_ & _0159_[2];
+ assign _0686_ = ~ _0159_[1];
+ assign _0687_ = _0670_ & _0686_;
+ assign _0688_ = _0670_ & _0159_[1];
+ assign _0689_ = _0671_ & _0686_;
+ assign _0690_ = _0671_ & _0159_[1];
+ assign _0691_ = _0672_ & _0686_;
+ assign _0692_ = _0672_ & _0159_[1];
+ assign _0693_ = _0673_ & _0686_;
+ assign _0694_ = _0673_ & _0159_[1];
+ assign _0695_ = _0674_ & _0686_;
+ assign _0696_ = _0674_ & _0159_[1];
+ assign _0697_ = _0675_ & _0686_;
+ assign _0698_ = _0675_ & _0159_[1];
+ assign _0699_ = _0676_ & _0686_;
+ assign _0700_ = _0676_ & _0159_[1];
+ assign _0701_ = _0677_ & _0686_;
+ assign _0702_ = _0677_ & _0159_[1];
+ assign _0703_ = _0678_ & _0686_;
+ assign _0704_ = _0678_ & _0159_[1];
+ assign _0705_ = _0679_ & _0686_;
+ assign _0706_ = _0679_ & _0159_[1];
+ assign _0707_ = _0680_ & _0686_;
+ assign _0708_ = _0680_ & _0159_[1];
+ assign _0709_ = _0681_ & _0686_;
+ assign _0710_ = _0681_ & _0159_[1];
+ assign _0711_ = _0682_ & _0686_;
+ assign _0712_ = _0682_ & _0159_[1];
+ assign _0713_ = _0683_ & _0686_;
+ assign _0714_ = _0683_ & _0159_[1];
+ assign _0715_ = _0684_ & _0686_;
+ assign _0716_ = _0684_ & _0159_[1];
+ assign _0717_ = _0685_ & _0686_;
+ assign _0718_ = _0685_ & _0159_[1];
+ assign _0719_ = ~ _0159_[0];
+ assign _0720_ = _0687_ & _0719_;
+ assign _0721_ = _0687_ & _0159_[0];
+ assign _0722_ = _0688_ & _0719_;
+ assign _0723_ = _0688_ & _0159_[0];
+ assign _0724_ = _0689_ & _0719_;
+ assign _0725_ = _0689_ & _0159_[0];
+ assign _0726_ = _0690_ & _0719_;
+ assign _0727_ = _0690_ & _0159_[0];
+ assign _0728_ = _0691_ & _0719_;
+ assign _0729_ = _0691_ & _0159_[0];
+ assign _0730_ = _0692_ & _0719_;
+ assign _0731_ = _0692_ & _0159_[0];
+ assign _0732_ = _0693_ & _0719_;
+ assign _0733_ = _0693_ & _0159_[0];
+ assign _0734_ = _0694_ & _0719_;
+ assign _0735_ = _0694_ & _0159_[0];
+ assign _0736_ = _0695_ & _0719_;
+ assign _0737_ = _0695_ & _0159_[0];
+ assign _0738_ = _0696_ & _0719_;
+ assign _0739_ = _0696_ & _0159_[0];
+ assign _0740_ = _0697_ & _0719_;
+ assign _0741_ = _0697_ & _0159_[0];
+ assign _0742_ = _0698_ & _0719_;
+ assign _0743_ = _0698_ & _0159_[0];
+ assign _0744_ = _0699_ & _0719_;
+ assign _0745_ = _0699_ & _0159_[0];
+ assign _0746_ = _0700_ & _0719_;
+ assign _0747_ = _0700_ & _0159_[0];
+ assign _0748_ = _0701_ & _0719_;
+ assign _0749_ = _0701_ & _0159_[0];
+ assign _0750_ = _0702_ & _0719_;
+ assign _0751_ = _0702_ & _0159_[0];
+ assign _0752_ = _0703_ & _0719_;
+ assign _0753_ = _0703_ & _0159_[0];
+ assign _0754_ = _0704_ & _0719_;
+ assign _0755_ = _0704_ & _0159_[0];
+ assign _0756_ = _0705_ & _0719_;
+ assign _0757_ = _0705_ & _0159_[0];
+ assign _0758_ = _0706_ & _0719_;
+ assign _0759_ = _0706_ & _0159_[0];
+ assign _0760_ = _0707_ & _0719_;
+ assign _0761_ = _0707_ & _0159_[0];
+ assign _0762_ = _0708_ & _0719_;
+ assign _0763_ = _0708_ & _0159_[0];
+ assign _0764_ = _0709_ & _0719_;
+ assign _0765_ = _0709_ & _0159_[0];
+ assign _0766_ = _0710_ & _0719_;
+ assign _0767_ = _0710_ & _0159_[0];
+ assign _0768_ = _0711_ & _0719_;
+ assign _0769_ = _0711_ & _0159_[0];
+ assign _0770_ = _0712_ & _0719_;
+ assign _0771_ = _0712_ & _0159_[0];
+ assign _0772_ = _0713_ & _0719_;
+ assign _0773_ = _0713_ & _0159_[0];
+ assign _0774_ = _0714_ & _0719_;
+ assign _0775_ = _0714_ & _0159_[0];
+ assign _0776_ = _0715_ & _0719_;
+ assign _0777_ = _0715_ & _0159_[0];
+ assign _0778_ = _0716_ & _0719_;
+ assign _0779_ = _0716_ & _0159_[0];
+ assign _0780_ = _0717_ & _0719_;
+ assign _0781_ = _0717_ & _0159_[0];
+ assign _0782_ = _0718_ & _0719_;
+ assign _0783_ = _0718_ & _0159_[0];
+ assign _0784_ = ~ tlb_hit_way;
+ assign _0785_ = _0720_ & _0784_;
+ assign _0786_ = _0720_ & tlb_hit_way;
+ assign _0787_ = _0721_ & _0784_;
+ assign _0788_ = _0721_ & tlb_hit_way;
+ assign _0789_ = _0722_ & _0784_;
+ assign _0790_ = _0722_ & tlb_hit_way;
+ assign _0791_ = _0723_ & _0784_;
+ assign _0792_ = _0723_ & tlb_hit_way;
+ assign _0793_ = _0724_ & _0784_;
+ assign _0794_ = _0724_ & tlb_hit_way;
+ assign _0795_ = _0725_ & _0784_;
+ assign _0796_ = _0725_ & tlb_hit_way;
+ assign _0797_ = _0726_ & _0784_;
+ assign _0798_ = _0726_ & tlb_hit_way;
+ assign _0799_ = _0727_ & _0784_;
+ assign _0800_ = _0727_ & tlb_hit_way;
+ assign _0801_ = _0728_ & _0784_;
+ assign _0802_ = _0728_ & tlb_hit_way;
+ assign _0803_ = _0729_ & _0784_;
+ assign _0804_ = _0729_ & tlb_hit_way;
+ assign _0805_ = _0730_ & _0784_;
+ assign _0806_ = _0730_ & tlb_hit_way;
+ assign _0807_ = _0731_ & _0784_;
+ assign _0808_ = _0731_ & tlb_hit_way;
+ assign _0809_ = _0732_ & _0784_;
+ assign _0810_ = _0732_ & tlb_hit_way;
+ assign _0811_ = _0733_ & _0784_;
+ assign _0812_ = _0733_ & tlb_hit_way;
+ assign _0813_ = _0734_ & _0784_;
+ assign _0814_ = _0734_ & tlb_hit_way;
+ assign _0815_ = _0735_ & _0784_;
+ assign _0816_ = _0735_ & tlb_hit_way;
+ assign _0817_ = _0736_ & _0784_;
+ assign _0818_ = _0736_ & tlb_hit_way;
+ assign _0819_ = _0737_ & _0784_;
+ assign _0820_ = _0737_ & tlb_hit_way;
+ assign _0821_ = _0738_ & _0784_;
+ assign _0822_ = _0738_ & tlb_hit_way;
+ assign _0823_ = _0739_ & _0784_;
+ assign _0824_ = _0739_ & tlb_hit_way;
+ assign _0825_ = _0740_ & _0784_;
+ assign _0826_ = _0740_ & tlb_hit_way;
+ assign _0827_ = _0741_ & _0784_;
+ assign _0828_ = _0741_ & tlb_hit_way;
+ assign _0829_ = _0742_ & _0784_;
+ assign _0830_ = _0742_ & tlb_hit_way;
+ assign _0831_ = _0743_ & _0784_;
+ assign _0832_ = _0743_ & tlb_hit_way;
+ assign _0833_ = _0744_ & _0784_;
+ assign _0834_ = _0744_ & tlb_hit_way;
+ assign _0835_ = _0745_ & _0784_;
+ assign _0836_ = _0745_ & tlb_hit_way;
+ assign _0837_ = _0746_ & _0784_;
+ assign _0838_ = _0746_ & tlb_hit_way;
+ assign _0839_ = _0747_ & _0784_;
+ assign _0840_ = _0747_ & tlb_hit_way;
+ assign _0841_ = _0748_ & _0784_;
+ assign _0842_ = _0748_ & tlb_hit_way;
+ assign _0843_ = _0749_ & _0784_;
+ assign _0844_ = _0749_ & tlb_hit_way;
+ assign _0845_ = _0750_ & _0784_;
+ assign _0846_ = _0750_ & tlb_hit_way;
+ assign _0847_ = _0751_ & _0784_;
+ assign _0848_ = _0751_ & tlb_hit_way;
+ assign _0849_ = _0752_ & _0784_;
+ assign _0850_ = _0752_ & tlb_hit_way;
+ assign _0851_ = _0753_ & _0784_;
+ assign _0852_ = _0753_ & tlb_hit_way;
+ assign _0853_ = _0754_ & _0784_;
+ assign _0854_ = _0754_ & tlb_hit_way;
+ assign _0855_ = _0755_ & _0784_;
+ assign _0856_ = _0755_ & tlb_hit_way;
+ assign _0857_ = _0756_ & _0784_;
+ assign _0858_ = _0756_ & tlb_hit_way;
+ assign _0859_ = _0757_ & _0784_;
+ assign _0860_ = _0757_ & tlb_hit_way;
+ assign _0861_ = _0758_ & _0784_;
+ assign _0862_ = _0758_ & tlb_hit_way;
+ assign _0863_ = _0759_ & _0784_;
+ assign _0864_ = _0759_ & tlb_hit_way;
+ assign _0865_ = _0760_ & _0784_;
+ assign _0866_ = _0760_ & tlb_hit_way;
+ assign _0867_ = _0761_ & _0784_;
+ assign _0868_ = _0761_ & tlb_hit_way;
+ assign _0869_ = _0762_ & _0784_;
+ assign _0870_ = _0762_ & tlb_hit_way;
+ assign _0871_ = _0763_ & _0784_;
+ assign _0872_ = _0763_ & tlb_hit_way;
+ assign _0873_ = _0764_ & _0784_;
+ assign _0874_ = _0764_ & tlb_hit_way;
+ assign _0875_ = _0765_ & _0784_;
+ assign _0876_ = _0765_ & tlb_hit_way;
+ assign _0877_ = _0766_ & _0784_;
+ assign _0878_ = _0766_ & tlb_hit_way;
+ assign _0879_ = _0767_ & _0784_;
+ assign _0880_ = _0767_ & tlb_hit_way;
+ assign _0881_ = _0768_ & _0784_;
+ assign _0882_ = _0768_ & tlb_hit_way;
+ assign _0883_ = _0769_ & _0784_;
+ assign _0884_ = _0769_ & tlb_hit_way;
+ assign _0885_ = _0770_ & _0784_;
+ assign _0886_ = _0770_ & tlb_hit_way;
+ assign _0887_ = _0771_ & _0784_;
+ assign _0888_ = _0771_ & tlb_hit_way;
+ assign _0889_ = _0772_ & _0784_;
+ assign _0890_ = _0772_ & tlb_hit_way;
+ assign _0891_ = _0773_ & _0784_;
+ assign _0892_ = _0773_ & tlb_hit_way;
+ assign _0893_ = _0774_ & _0784_;
+ assign _0894_ = _0774_ & tlb_hit_way;
+ assign _0895_ = _0775_ & _0784_;
+ assign _0896_ = _0775_ & tlb_hit_way;
+ assign _0897_ = _0776_ & _0784_;
+ assign _0898_ = _0776_ & tlb_hit_way;
+ assign _0899_ = _0777_ & _0784_;
+ assign _0900_ = _0777_ & tlb_hit_way;
+ assign _0901_ = _0778_ & _0784_;
+ assign _0902_ = _0778_ & tlb_hit_way;
+ assign _0903_ = _0779_ & _0784_;
+ assign _0904_ = _0779_ & tlb_hit_way;
+ assign _0905_ = _0780_ & _0784_;
+ assign _0906_ = _0780_ & tlb_hit_way;
+ assign _0907_ = _0781_ & _0784_;
+ assign _0908_ = _0781_ & tlb_hit_way;
+ assign _0909_ = _0782_ & _0784_;
+ assign _0910_ = _0782_ & tlb_hit_way;
+ assign _0911_ = _0783_ & _0784_;
+ assign _0912_ = _0783_ & tlb_hit_way;
+ assign _0913_ = _0785_ ? 1'h0 : dtlb_valids[0];
+ assign _0914_ = _0786_ ? 1'h0 : dtlb_valids[1];
+ assign _0915_ = _0787_ ? 1'h0 : dtlb_valids[2];
+ assign _0916_ = _0788_ ? 1'h0 : dtlb_valids[3];
+ assign _0917_ = _0789_ ? 1'h0 : dtlb_valids[4];
+ assign _0918_ = _0790_ ? 1'h0 : dtlb_valids[5];
+ assign _0919_ = _0791_ ? 1'h0 : dtlb_valids[6];
+ assign _0920_ = _0792_ ? 1'h0 : dtlb_valids[7];
+ assign _0921_ = _0793_ ? 1'h0 : dtlb_valids[8];
+ assign _0922_ = _0794_ ? 1'h0 : dtlb_valids[9];
+ assign _0923_ = _0795_ ? 1'h0 : dtlb_valids[10];
+ assign _0924_ = _0796_ ? 1'h0 : dtlb_valids[11];
+ assign _0925_ = _0797_ ? 1'h0 : dtlb_valids[12];
+ assign _0926_ = _0798_ ? 1'h0 : dtlb_valids[13];
+ assign _0927_ = _0799_ ? 1'h0 : dtlb_valids[14];
+ assign _0928_ = _0800_ ? 1'h0 : dtlb_valids[15];
+ assign _0929_ = _0801_ ? 1'h0 : dtlb_valids[16];
+ assign _0930_ = _0802_ ? 1'h0 : dtlb_valids[17];
+ assign _0931_ = _0803_ ? 1'h0 : dtlb_valids[18];
+ assign _0932_ = _0804_ ? 1'h0 : dtlb_valids[19];
+ assign _0933_ = _0805_ ? 1'h0 : dtlb_valids[20];
+ assign _0934_ = _0806_ ? 1'h0 : dtlb_valids[21];
+ assign _0935_ = _0807_ ? 1'h0 : dtlb_valids[22];
+ assign _0936_ = _0808_ ? 1'h0 : dtlb_valids[23];
+ assign _0937_ = _0809_ ? 1'h0 : dtlb_valids[24];
+ assign _0938_ = _0810_ ? 1'h0 : dtlb_valids[25];
+ assign _0939_ = _0811_ ? 1'h0 : dtlb_valids[26];
+ assign _0940_ = _0812_ ? 1'h0 : dtlb_valids[27];
+ assign _0941_ = _0813_ ? 1'h0 : dtlb_valids[28];
+ assign _0942_ = _0814_ ? 1'h0 : dtlb_valids[29];
+ assign _0943_ = _0815_ ? 1'h0 : dtlb_valids[30];
+ assign _0944_ = _0816_ ? 1'h0 : dtlb_valids[31];
+ assign _0945_ = _0817_ ? 1'h0 : dtlb_valids[32];
+ assign _0946_ = _0818_ ? 1'h0 : dtlb_valids[33];
+ assign _0947_ = _0819_ ? 1'h0 : dtlb_valids[34];
+ assign _0948_ = _0820_ ? 1'h0 : dtlb_valids[35];
+ assign _0949_ = _0821_ ? 1'h0 : dtlb_valids[36];
+ assign _0950_ = _0822_ ? 1'h0 : dtlb_valids[37];
+ assign _0951_ = _0823_ ? 1'h0 : dtlb_valids[38];
+ assign _0952_ = _0824_ ? 1'h0 : dtlb_valids[39];
+ assign _0953_ = _0825_ ? 1'h0 : dtlb_valids[40];
+ assign _0954_ = _0826_ ? 1'h0 : dtlb_valids[41];
+ assign _0955_ = _0827_ ? 1'h0 : dtlb_valids[42];
+ assign _0956_ = _0828_ ? 1'h0 : dtlb_valids[43];
+ assign _0957_ = _0829_ ? 1'h0 : dtlb_valids[44];
+ assign _0958_ = _0830_ ? 1'h0 : dtlb_valids[45];
+ assign _0959_ = _0831_ ? 1'h0 : dtlb_valids[46];
+ assign _0960_ = _0832_ ? 1'h0 : dtlb_valids[47];
+ assign _0961_ = _0833_ ? 1'h0 : dtlb_valids[48];
+ assign _0962_ = _0834_ ? 1'h0 : dtlb_valids[49];
+ assign _0963_ = _0835_ ? 1'h0 : dtlb_valids[50];
+ assign _0964_ = _0836_ ? 1'h0 : dtlb_valids[51];
+ assign _0965_ = _0837_ ? 1'h0 : dtlb_valids[52];
+ assign _0966_ = _0838_ ? 1'h0 : dtlb_valids[53];
+ assign _0967_ = _0839_ ? 1'h0 : dtlb_valids[54];
+ assign _0968_ = _0840_ ? 1'h0 : dtlb_valids[55];
+ assign _0969_ = _0841_ ? 1'h0 : dtlb_valids[56];
+ assign _0970_ = _0842_ ? 1'h0 : dtlb_valids[57];
+ assign _0971_ = _0843_ ? 1'h0 : dtlb_valids[58];
+ assign _0972_ = _0844_ ? 1'h0 : dtlb_valids[59];
+ assign _0973_ = _0845_ ? 1'h0 : dtlb_valids[60];
+ assign _0974_ = _0846_ ? 1'h0 : dtlb_valids[61];
+ assign _0975_ = _0847_ ? 1'h0 : dtlb_valids[62];
+ assign _0976_ = _0848_ ? 1'h0 : dtlb_valids[63];
+ assign _0977_ = _0849_ ? 1'h0 : dtlb_valids[64];
+ assign _0978_ = _0850_ ? 1'h0 : dtlb_valids[65];
+ assign _0979_ = _0851_ ? 1'h0 : dtlb_valids[66];
+ assign _0980_ = _0852_ ? 1'h0 : dtlb_valids[67];
+ assign _0981_ = _0853_ ? 1'h0 : dtlb_valids[68];
+ assign _0982_ = _0854_ ? 1'h0 : dtlb_valids[69];
+ assign _0983_ = _0855_ ? 1'h0 : dtlb_valids[70];
+ assign _0984_ = _0856_ ? 1'h0 : dtlb_valids[71];
+ assign _0985_ = _0857_ ? 1'h0 : dtlb_valids[72];
+ assign _0986_ = _0858_ ? 1'h0 : dtlb_valids[73];
+ assign _0987_ = _0859_ ? 1'h0 : dtlb_valids[74];
+ assign _0988_ = _0860_ ? 1'h0 : dtlb_valids[75];
+ assign _0989_ = _0861_ ? 1'h0 : dtlb_valids[76];
+ assign _0990_ = _0862_ ? 1'h0 : dtlb_valids[77];
+ assign _0991_ = _0863_ ? 1'h0 : dtlb_valids[78];
+ assign _0992_ = _0864_ ? 1'h0 : dtlb_valids[79];
+ assign _0993_ = _0865_ ? 1'h0 : dtlb_valids[80];
+ assign _0994_ = _0866_ ? 1'h0 : dtlb_valids[81];
+ assign _0995_ = _0867_ ? 1'h0 : dtlb_valids[82];
+ assign _0996_ = _0868_ ? 1'h0 : dtlb_valids[83];
+ assign _0997_ = _0869_ ? 1'h0 : dtlb_valids[84];
+ assign _0998_ = _0870_ ? 1'h0 : dtlb_valids[85];
+ assign _0999_ = _0871_ ? 1'h0 : dtlb_valids[86];
+ assign _1000_ = _0872_ ? 1'h0 : dtlb_valids[87];
+ assign _1001_ = _0873_ ? 1'h0 : dtlb_valids[88];
+ assign _1002_ = _0874_ ? 1'h0 : dtlb_valids[89];
+ assign _1003_ = _0875_ ? 1'h0 : dtlb_valids[90];
+ assign _1004_ = _0876_ ? 1'h0 : dtlb_valids[91];
+ assign _1005_ = _0877_ ? 1'h0 : dtlb_valids[92];
+ assign _1006_ = _0878_ ? 1'h0 : dtlb_valids[93];
+ assign _1007_ = _0879_ ? 1'h0 : dtlb_valids[94];
+ assign _1008_ = _0880_ ? 1'h0 : dtlb_valids[95];
+ assign _1009_ = _0881_ ? 1'h0 : dtlb_valids[96];
+ assign _1010_ = _0882_ ? 1'h0 : dtlb_valids[97];
+ assign _1011_ = _0883_ ? 1'h0 : dtlb_valids[98];
+ assign _1012_ = _0884_ ? 1'h0 : dtlb_valids[99];
+ assign _1013_ = _0885_ ? 1'h0 : dtlb_valids[100];
+ assign _1014_ = _0886_ ? 1'h0 : dtlb_valids[101];
+ assign _1015_ = _0887_ ? 1'h0 : dtlb_valids[102];
+ assign _1016_ = _0888_ ? 1'h0 : dtlb_valids[103];
+ assign _1017_ = _0889_ ? 1'h0 : dtlb_valids[104];
+ assign _1018_ = _0890_ ? 1'h0 : dtlb_valids[105];
+ assign _1019_ = _0891_ ? 1'h0 : dtlb_valids[106];
+ assign _1020_ = _0892_ ? 1'h0 : dtlb_valids[107];
+ assign _1021_ = _0893_ ? 1'h0 : dtlb_valids[108];
+ assign _1022_ = _0894_ ? 1'h0 : dtlb_valids[109];
+ assign _1023_ = _0895_ ? 1'h0 : dtlb_valids[110];
+ assign _1024_ = _0896_ ? 1'h0 : dtlb_valids[111];
+ assign _1025_ = _0897_ ? 1'h0 : dtlb_valids[112];
+ assign _1026_ = _0898_ ? 1'h0 : dtlb_valids[113];
+ assign _1027_ = _0899_ ? 1'h0 : dtlb_valids[114];
+ assign _1028_ = _0900_ ? 1'h0 : dtlb_valids[115];
+ assign _1029_ = _0901_ ? 1'h0 : dtlb_valids[116];
+ assign _1030_ = _0902_ ? 1'h0 : dtlb_valids[117];
+ assign _1031_ = _0903_ ? 1'h0 : dtlb_valids[118];
+ assign _1032_ = _0904_ ? 1'h0 : dtlb_valids[119];
+ assign _1033_ = _0905_ ? 1'h0 : dtlb_valids[120];
+ assign _1034_ = _0906_ ? 1'h0 : dtlb_valids[121];
+ assign _1035_ = _0907_ ? 1'h0 : dtlb_valids[122];
+ assign _1036_ = _0908_ ? 1'h0 : dtlb_valids[123];
+ assign _1037_ = _0909_ ? 1'h0 : dtlb_valids[124];
+ assign _1038_ = _0910_ ? 1'h0 : dtlb_valids[125];
+ assign _1039_ = _0911_ ? 1'h0 : dtlb_valids[126];
+ assign _1040_ = _0912_ ? 1'h0 : dtlb_valids[127];
+ assign _1062_ = ~ _0162_;
+ assign _1063_ = _1062_ ? r0[70:25] : tlb_tag_way[45:0];
+ assign _1064_ = _0162_ ? r0[70:25] : tlb_tag_way[91:46];
+ assign _1065_ = ~ _0162_;
+ assign _1066_ = _1065_ ? r0[134:71] : tlb_pte_way[63:0];
+ assign _1067_ = _0162_ ? r0[134:71] : tlb_pte_way[127:64];
+ assign _1068_ = ~ _0163_[5];
+ assign _1069_ = ~ _0163_[4];
+ assign _1070_ = _1068_ & _1069_;
+ assign _1071_ = _1068_ & _0163_[4];
+ assign _1072_ = _0163_[5] & _1069_;
+ assign _1073_ = _0163_[5] & _0163_[4];
+ assign _1074_ = ~ _0163_[3];
+ assign _1075_ = _1070_ & _1074_;
+ assign _1076_ = _1070_ & _0163_[3];
+ assign _1077_ = _1071_ & _1074_;
+ assign _1078_ = _1071_ & _0163_[3];
+ assign _1079_ = _1072_ & _1074_;
+ assign _1080_ = _1072_ & _0163_[3];
+ assign _1081_ = _1073_ & _1074_;
+ assign _1082_ = _1073_ & _0163_[3];
+ assign _1083_ = ~ _0163_[2];
+ assign _1084_ = _1075_ & _1083_;
+ assign _1085_ = _1075_ & _0163_[2];
+ assign _1086_ = _1076_ & _1083_;
+ assign _1087_ = _1076_ & _0163_[2];
+ assign _1088_ = _1077_ & _1083_;
+ assign _1089_ = _1077_ & _0163_[2];
+ assign _1090_ = _1078_ & _1083_;
+ assign _1091_ = _1078_ & _0163_[2];
+ assign _1092_ = _1079_ & _1083_;
+ assign _1093_ = _1079_ & _0163_[2];
+ assign _1094_ = _1080_ & _1083_;
+ assign _1095_ = _1080_ & _0163_[2];
+ assign _1096_ = _1081_ & _1083_;
+ assign _1097_ = _1081_ & _0163_[2];
+ assign _1098_ = _1082_ & _1083_;
+ assign _1099_ = _1082_ & _0163_[2];
+ assign _1100_ = ~ _0163_[1];
+ assign _1101_ = _1084_ & _1100_;
+ assign _1102_ = _1084_ & _0163_[1];
+ assign _1103_ = _1085_ & _1100_;
+ assign _1104_ = _1085_ & _0163_[1];
+ assign _1105_ = _1086_ & _1100_;
+ assign _1106_ = _1086_ & _0163_[1];
+ assign _1107_ = _1087_ & _1100_;
+ assign _1108_ = _1087_ & _0163_[1];
+ assign _1109_ = _1088_ & _1100_;
+ assign _1110_ = _1088_ & _0163_[1];
+ assign _1111_ = _1089_ & _1100_;
+ assign _1112_ = _1089_ & _0163_[1];
+ assign _1113_ = _1090_ & _1100_;
+ assign _1114_ = _1090_ & _0163_[1];
+ assign _1115_ = _1091_ & _1100_;
+ assign _1116_ = _1091_ & _0163_[1];
+ assign _1117_ = _1092_ & _1100_;
+ assign _1118_ = _1092_ & _0163_[1];
+ assign _1119_ = _1093_ & _1100_;
+ assign _1120_ = _1093_ & _0163_[1];
+ assign _1121_ = _1094_ & _1100_;
+ assign _1122_ = _1094_ & _0163_[1];
+ assign _1123_ = _1095_ & _1100_;
+ assign _1124_ = _1095_ & _0163_[1];
+ assign _1125_ = _1096_ & _1100_;
+ assign _1126_ = _1096_ & _0163_[1];
+ assign _1127_ = _1097_ & _1100_;
+ assign _1128_ = _1097_ & _0163_[1];
+ assign _1129_ = _1098_ & _1100_;
+ assign _1130_ = _1098_ & _0163_[1];
+ assign _1131_ = _1099_ & _1100_;
+ assign _1132_ = _1099_ & _0163_[1];
+ assign _1133_ = ~ _0163_[0];
+ assign _1134_ = _1101_ & _1133_;
+ assign _1135_ = _1101_ & _0163_[0];
+ assign _1136_ = _1102_ & _1133_;
+ assign _1137_ = _1102_ & _0163_[0];
+ assign _1138_ = _1103_ & _1133_;
+ assign _1139_ = _1103_ & _0163_[0];
+ assign _1140_ = _1104_ & _1133_;
+ assign _1141_ = _1104_ & _0163_[0];
+ assign _1142_ = _1105_ & _1133_;
+ assign _1143_ = _1105_ & _0163_[0];
+ assign _1144_ = _1106_ & _1133_;
+ assign _1145_ = _1106_ & _0163_[0];
+ assign _1146_ = _1107_ & _1133_;
+ assign _1147_ = _1107_ & _0163_[0];
+ assign _1148_ = _1108_ & _1133_;
+ assign _1149_ = _1108_ & _0163_[0];
+ assign _1150_ = _1109_ & _1133_;
+ assign _1151_ = _1109_ & _0163_[0];
+ assign _1152_ = _1110_ & _1133_;
+ assign _1153_ = _1110_ & _0163_[0];
+ assign _1154_ = _1111_ & _1133_;
+ assign _1155_ = _1111_ & _0163_[0];
+ assign _1156_ = _1112_ & _1133_;
+ assign _1157_ = _1112_ & _0163_[0];
+ assign _1158_ = _1113_ & _1133_;
+ assign _1159_ = _1113_ & _0163_[0];
+ assign _1160_ = _1114_ & _1133_;
+ assign _1161_ = _1114_ & _0163_[0];
+ assign _1162_ = _1115_ & _1133_;
+ assign _1163_ = _1115_ & _0163_[0];
+ assign _1164_ = _1116_ & _1133_;
+ assign _1165_ = _1116_ & _0163_[0];
+ assign _1166_ = _1117_ & _1133_;
+ assign _1167_ = _1117_ & _0163_[0];
+ assign _1168_ = _1118_ & _1133_;
+ assign _1169_ = _1118_ & _0163_[0];
+ assign _1170_ = _1119_ & _1133_;
+ assign _1171_ = _1119_ & _0163_[0];
+ assign _1172_ = _1120_ & _1133_;
+ assign _1173_ = _1120_ & _0163_[0];
+ assign _1174_ = _1121_ & _1133_;
+ assign _1175_ = _1121_ & _0163_[0];
+ assign _1176_ = _1122_ & _1133_;
+ assign _1177_ = _1122_ & _0163_[0];
+ assign _1178_ = _1123_ & _1133_;
+ assign _1179_ = _1123_ & _0163_[0];
+ assign _1180_ = _1124_ & _1133_;
+ assign _1181_ = _1124_ & _0163_[0];
+ assign _1182_ = _1125_ & _1133_;
+ assign _1183_ = _1125_ & _0163_[0];
+ assign _1184_ = _1126_ & _1133_;
+ assign _1185_ = _1126_ & _0163_[0];
+ assign _1186_ = _1127_ & _1133_;
+ assign _1187_ = _1127_ & _0163_[0];
+ assign _1188_ = _1128_ & _1133_;
+ assign _1189_ = _1128_ & _0163_[0];
+ assign _1190_ = _1129_ & _1133_;
+ assign _1191_ = _1129_ & _0163_[0];
+ assign _1192_ = _1130_ & _1133_;
+ assign _1193_ = _1130_ & _0163_[0];
+ assign _1194_ = _1131_ & _1133_;
+ assign _1195_ = _1131_ & _0163_[0];
+ assign _1196_ = _1132_ & _1133_;
+ assign _1197_ = _1132_ & _0163_[0];
+ assign _1198_ = ~ _0162_;
+ assign _1199_ = _1134_ & _1198_;
+ assign _1200_ = _1134_ & _0162_;
+ assign _1201_ = _1135_ & _1198_;
+ assign _1202_ = _1135_ & _0162_;
+ assign _1203_ = _1136_ & _1198_;
+ assign _1204_ = _1136_ & _0162_;
+ assign _1205_ = _1137_ & _1198_;
+ assign _1206_ = _1137_ & _0162_;
+ assign _1207_ = _1138_ & _1198_;
+ assign _1208_ = _1138_ & _0162_;
+ assign _1209_ = _1139_ & _1198_;
+ assign _1210_ = _1139_ & _0162_;
+ assign _1211_ = _1140_ & _1198_;
+ assign _1212_ = _1140_ & _0162_;
+ assign _1213_ = _1141_ & _1198_;
+ assign _1214_ = _1141_ & _0162_;
+ assign _1215_ = _1142_ & _1198_;
+ assign _1216_ = _1142_ & _0162_;
+ assign _1217_ = _1143_ & _1198_;
+ assign _1218_ = _1143_ & _0162_;
+ assign _1219_ = _1144_ & _1198_;
+ assign _1220_ = _1144_ & _0162_;
+ assign _1221_ = _1145_ & _1198_;
+ assign _1222_ = _1145_ & _0162_;
+ assign _1223_ = _1146_ & _1198_;
+ assign _1224_ = _1146_ & _0162_;
+ assign _1225_ = _1147_ & _1198_;
+ assign _1226_ = _1147_ & _0162_;
+ assign _1227_ = _1148_ & _1198_;
+ assign _1228_ = _1148_ & _0162_;
+ assign _1229_ = _1149_ & _1198_;
+ assign _1230_ = _1149_ & _0162_;
+ assign _1231_ = _1150_ & _1198_;
+ assign _1232_ = _1150_ & _0162_;
+ assign _1233_ = _1151_ & _1198_;
+ assign _1234_ = _1151_ & _0162_;
+ assign _1235_ = _1152_ & _1198_;
+ assign _1236_ = _1152_ & _0162_;
+ assign _1237_ = _1153_ & _1198_;
+ assign _1238_ = _1153_ & _0162_;
+ assign _1239_ = _1154_ & _1198_;
+ assign _1240_ = _1154_ & _0162_;
+ assign _1241_ = _1155_ & _1198_;
+ assign _1242_ = _1155_ & _0162_;
+ assign _1243_ = _1156_ & _1198_;
+ assign _1244_ = _1156_ & _0162_;
+ assign _1245_ = _1157_ & _1198_;
+ assign _1246_ = _1157_ & _0162_;
+ assign _1247_ = _1158_ & _1198_;
+ assign _1248_ = _1158_ & _0162_;
+ assign _1249_ = _1159_ & _1198_;
+ assign _1250_ = _1159_ & _0162_;
+ assign _1251_ = _1160_ & _1198_;
+ assign _1252_ = _1160_ & _0162_;
+ assign _1253_ = _1161_ & _1198_;
+ assign _1254_ = _1161_ & _0162_;
+ assign _1255_ = _1162_ & _1198_;
+ assign _1256_ = _1162_ & _0162_;
+ assign _1257_ = _1163_ & _1198_;
+ assign _1258_ = _1163_ & _0162_;
+ assign _1259_ = _1164_ & _1198_;
+ assign _1260_ = _1164_ & _0162_;
+ assign _1261_ = _1165_ & _1198_;
+ assign _1262_ = _1165_ & _0162_;
+ assign _1263_ = _1166_ & _1198_;
+ assign _1264_ = _1166_ & _0162_;
+ assign _1265_ = _1167_ & _1198_;
+ assign _1266_ = _1167_ & _0162_;
+ assign _1267_ = _1168_ & _1198_;
+ assign _1268_ = _1168_ & _0162_;
+ assign _1269_ = _1169_ & _1198_;
+ assign _1270_ = _1169_ & _0162_;
+ assign _1271_ = _1170_ & _1198_;
+ assign _1272_ = _1170_ & _0162_;
+ assign _1273_ = _1171_ & _1198_;
+ assign _1274_ = _1171_ & _0162_;
+ assign _1275_ = _1172_ & _1198_;
+ assign _1276_ = _1172_ & _0162_;
+ assign _1277_ = _1173_ & _1198_;
+ assign _1278_ = _1173_ & _0162_;
+ assign _1279_ = _1174_ & _1198_;
+ assign _1280_ = _1174_ & _0162_;
+ assign _1281_ = _1175_ & _1198_;
+ assign _1282_ = _1175_ & _0162_;
+ assign _1283_ = _1176_ & _1198_;
+ assign _1284_ = _1176_ & _0162_;
+ assign _1285_ = _1177_ & _1198_;
+ assign _1286_ = _1177_ & _0162_;
+ assign _1287_ = _1178_ & _1198_;
+ assign _1288_ = _1178_ & _0162_;
+ assign _1289_ = _1179_ & _1198_;
+ assign _1290_ = _1179_ & _0162_;
+ assign _1291_ = _1180_ & _1198_;
+ assign _1292_ = _1180_ & _0162_;
+ assign _1293_ = _1181_ & _1198_;
+ assign _1294_ = _1181_ & _0162_;
+ assign _1295_ = _1182_ & _1198_;
+ assign _1296_ = _1182_ & _0162_;
+ assign _1297_ = _1183_ & _1198_;
+ assign _1298_ = _1183_ & _0162_;
+ assign _1299_ = _1184_ & _1198_;
+ assign _1300_ = _1184_ & _0162_;
+ assign _1301_ = _1185_ & _1198_;
+ assign _1302_ = _1185_ & _0162_;
+ assign _1303_ = _1186_ & _1198_;
+ assign _1304_ = _1186_ & _0162_;
+ assign _1305_ = _1187_ & _1198_;
+ assign _1306_ = _1187_ & _0162_;
+ assign _1307_ = _1188_ & _1198_;
+ assign _1308_ = _1188_ & _0162_;
+ assign _1309_ = _1189_ & _1198_;
+ assign _1310_ = _1189_ & _0162_;
+ assign _1311_ = _1190_ & _1198_;
+ assign _1312_ = _1190_ & _0162_;
+ assign _1313_ = _1191_ & _1198_;
+ assign _1314_ = _1191_ & _0162_;
+ assign _1315_ = _1192_ & _1198_;
+ assign _1316_ = _1192_ & _0162_;
+ assign _1317_ = _1193_ & _1198_;
+ assign _1318_ = _1193_ & _0162_;
+ assign _1319_ = _1194_ & _1198_;
+ assign _1320_ = _1194_ & _0162_;
+ assign _1321_ = _1195_ & _1198_;
+ assign _1322_ = _1195_ & _0162_;
+ assign _1323_ = _1196_ & _1198_;
+ assign _1324_ = _1196_ & _0162_;
+ assign _1325_ = _1197_ & _1198_;
+ assign _1326_ = _1197_ & _0162_;
+ assign _1327_ = _1199_ ? 1'h1 : dtlb_valids[0];
+ assign _1328_ = _1200_ ? 1'h1 : dtlb_valids[1];
+ assign _1329_ = _1201_ ? 1'h1 : dtlb_valids[2];
+ assign _1330_ = _1202_ ? 1'h1 : dtlb_valids[3];
+ assign _1331_ = _1203_ ? 1'h1 : dtlb_valids[4];
+ assign _1332_ = _1204_ ? 1'h1 : dtlb_valids[5];
+ assign _1333_ = _1205_ ? 1'h1 : dtlb_valids[6];
+ assign _1334_ = _1206_ ? 1'h1 : dtlb_valids[7];
+ assign _1335_ = _1207_ ? 1'h1 : dtlb_valids[8];
+ assign _1336_ = _1208_ ? 1'h1 : dtlb_valids[9];
+ assign _1337_ = _1209_ ? 1'h1 : dtlb_valids[10];
+ assign _1338_ = _1210_ ? 1'h1 : dtlb_valids[11];
+ assign _1339_ = _1211_ ? 1'h1 : dtlb_valids[12];
+ assign _1340_ = _1212_ ? 1'h1 : dtlb_valids[13];
+ assign _1341_ = _1213_ ? 1'h1 : dtlb_valids[14];
+ assign _1342_ = _1214_ ? 1'h1 : dtlb_valids[15];
+ assign _1343_ = _1215_ ? 1'h1 : dtlb_valids[16];
+ assign _1344_ = _1216_ ? 1'h1 : dtlb_valids[17];
+ assign _1345_ = _1217_ ? 1'h1 : dtlb_valids[18];
+ assign _1346_ = _1218_ ? 1'h1 : dtlb_valids[19];
+ assign _1347_ = _1219_ ? 1'h1 : dtlb_valids[20];
+ assign _1348_ = _1220_ ? 1'h1 : dtlb_valids[21];
+ assign _1349_ = _1221_ ? 1'h1 : dtlb_valids[22];
+ assign _1350_ = _1222_ ? 1'h1 : dtlb_valids[23];
+ assign _1351_ = _1223_ ? 1'h1 : dtlb_valids[24];
+ assign _1352_ = _1224_ ? 1'h1 : dtlb_valids[25];
+ assign _1353_ = _1225_ ? 1'h1 : dtlb_valids[26];
+ assign _1354_ = _1226_ ? 1'h1 : dtlb_valids[27];
+ assign _1355_ = _1227_ ? 1'h1 : dtlb_valids[28];
+ assign _1356_ = _1228_ ? 1'h1 : dtlb_valids[29];
+ assign _1357_ = _1229_ ? 1'h1 : dtlb_valids[30];
+ assign _1358_ = _1230_ ? 1'h1 : dtlb_valids[31];
+ assign _1359_ = _1231_ ? 1'h1 : dtlb_valids[32];
+ assign _1360_ = _1232_ ? 1'h1 : dtlb_valids[33];
+ assign _1361_ = _1233_ ? 1'h1 : dtlb_valids[34];
+ assign _1362_ = _1234_ ? 1'h1 : dtlb_valids[35];
+ assign _1363_ = _1235_ ? 1'h1 : dtlb_valids[36];
+ assign _1364_ = _1236_ ? 1'h1 : dtlb_valids[37];
+ assign _1365_ = _1237_ ? 1'h1 : dtlb_valids[38];
+ assign _1366_ = _1238_ ? 1'h1 : dtlb_valids[39];
+ assign _1367_ = _1239_ ? 1'h1 : dtlb_valids[40];
+ assign _1368_ = _1240_ ? 1'h1 : dtlb_valids[41];
+ assign _1369_ = _1241_ ? 1'h1 : dtlb_valids[42];
+ assign _1370_ = _1242_ ? 1'h1 : dtlb_valids[43];
+ assign _1371_ = _1243_ ? 1'h1 : dtlb_valids[44];
+ assign _1372_ = _1244_ ? 1'h1 : dtlb_valids[45];
+ assign _1373_ = _1245_ ? 1'h1 : dtlb_valids[46];
+ assign _1374_ = _1246_ ? 1'h1 : dtlb_valids[47];
+ assign _1375_ = _1247_ ? 1'h1 : dtlb_valids[48];
+ assign _1376_ = _1248_ ? 1'h1 : dtlb_valids[49];
+ assign _1377_ = _1249_ ? 1'h1 : dtlb_valids[50];
+ assign _1378_ = _1250_ ? 1'h1 : dtlb_valids[51];
+ assign _1379_ = _1251_ ? 1'h1 : dtlb_valids[52];
+ assign _1380_ = _1252_ ? 1'h1 : dtlb_valids[53];
+ assign _1381_ = _1253_ ? 1'h1 : dtlb_valids[54];
+ assign _1382_ = _1254_ ? 1'h1 : dtlb_valids[55];
+ assign _1383_ = _1255_ ? 1'h1 : dtlb_valids[56];
+ assign _1384_ = _1256_ ? 1'h1 : dtlb_valids[57];
+ assign _1385_ = _1257_ ? 1'h1 : dtlb_valids[58];
+ assign _1386_ = _1258_ ? 1'h1 : dtlb_valids[59];
+ assign _1387_ = _1259_ ? 1'h1 : dtlb_valids[60];
+ assign _1388_ = _1260_ ? 1'h1 : dtlb_valids[61];
+ assign _1389_ = _1261_ ? 1'h1 : dtlb_valids[62];
+ assign _1390_ = _1262_ ? 1'h1 : dtlb_valids[63];
+ assign _1391_ = _1263_ ? 1'h1 : dtlb_valids[64];
+ assign _1392_ = _1264_ ? 1'h1 : dtlb_valids[65];
+ assign _1393_ = _1265_ ? 1'h1 : dtlb_valids[66];
+ assign _1394_ = _1266_ ? 1'h1 : dtlb_valids[67];
+ assign _1395_ = _1267_ ? 1'h1 : dtlb_valids[68];
+ assign _1396_ = _1268_ ? 1'h1 : dtlb_valids[69];
+ assign _1397_ = _1269_ ? 1'h1 : dtlb_valids[70];
+ assign _1398_ = _1270_ ? 1'h1 : dtlb_valids[71];
+ assign _1399_ = _1271_ ? 1'h1 : dtlb_valids[72];
+ assign _1400_ = _1272_ ? 1'h1 : dtlb_valids[73];
+ assign _1401_ = _1273_ ? 1'h1 : dtlb_valids[74];
+ assign _1402_ = _1274_ ? 1'h1 : dtlb_valids[75];
+ assign _1403_ = _1275_ ? 1'h1 : dtlb_valids[76];
+ assign _1404_ = _1276_ ? 1'h1 : dtlb_valids[77];
+ assign _1405_ = _1277_ ? 1'h1 : dtlb_valids[78];
+ assign _1406_ = _1278_ ? 1'h1 : dtlb_valids[79];
+ assign _1407_ = _1279_ ? 1'h1 : dtlb_valids[80];
+ assign _1408_ = _1280_ ? 1'h1 : dtlb_valids[81];
+ assign _1409_ = _1281_ ? 1'h1 : dtlb_valids[82];
+ assign _1410_ = _1282_ ? 1'h1 : dtlb_valids[83];
+ assign _1411_ = _1283_ ? 1'h1 : dtlb_valids[84];
+ assign _1412_ = _1284_ ? 1'h1 : dtlb_valids[85];
+ assign _1413_ = _1285_ ? 1'h1 : dtlb_valids[86];
+ assign _1414_ = _1286_ ? 1'h1 : dtlb_valids[87];
+ assign _1415_ = _1287_ ? 1'h1 : dtlb_valids[88];
+ assign _1416_ = _1288_ ? 1'h1 : dtlb_valids[89];
+ assign _1417_ = _1289_ ? 1'h1 : dtlb_valids[90];
+ assign _1418_ = _1290_ ? 1'h1 : dtlb_valids[91];
+ assign _1419_ = _1291_ ? 1'h1 : dtlb_valids[92];
+ assign _1420_ = _1292_ ? 1'h1 : dtlb_valids[93];
+ assign _1421_ = _1293_ ? 1'h1 : dtlb_valids[94];
+ assign _1422_ = _1294_ ? 1'h1 : dtlb_valids[95];
+ assign _1423_ = _1295_ ? 1'h1 : dtlb_valids[96];
+ assign _1424_ = _1296_ ? 1'h1 : dtlb_valids[97];
+ assign _1425_ = _1297_ ? 1'h1 : dtlb_valids[98];
+ assign _1426_ = _1298_ ? 1'h1 : dtlb_valids[99];
+ assign _1427_ = _1299_ ? 1'h1 : dtlb_valids[100];
+ assign _1428_ = _1300_ ? 1'h1 : dtlb_valids[101];
+ assign _1429_ = _1301_ ? 1'h1 : dtlb_valids[102];
+ assign _1430_ = _1302_ ? 1'h1 : dtlb_valids[103];
+ assign _1431_ = _1303_ ? 1'h1 : dtlb_valids[104];
+ assign _1432_ = _1304_ ? 1'h1 : dtlb_valids[105];
+ assign _1433_ = _1305_ ? 1'h1 : dtlb_valids[106];
+ assign _1434_ = _1306_ ? 1'h1 : dtlb_valids[107];
+ assign _1435_ = _1307_ ? 1'h1 : dtlb_valids[108];
+ assign _1436_ = _1308_ ? 1'h1 : dtlb_valids[109];
+ assign _1437_ = _1309_ ? 1'h1 : dtlb_valids[110];
+ assign _1438_ = _1310_ ? 1'h1 : dtlb_valids[111];
+ assign _1439_ = _1311_ ? 1'h1 : dtlb_valids[112];
+ assign _1440_ = _1312_ ? 1'h1 : dtlb_valids[113];
+ assign _1441_ = _1313_ ? 1'h1 : dtlb_valids[114];
+ assign _1442_ = _1314_ ? 1'h1 : dtlb_valids[115];
+ assign _1443_ = _1315_ ? 1'h1 : dtlb_valids[116];
+ assign _1444_ = _1316_ ? 1'h1 : dtlb_valids[117];
+ assign _1445_ = _1317_ ? 1'h1 : dtlb_valids[118];
+ assign _1446_ = _1318_ ? 1'h1 : dtlb_valids[119];
+ assign _1447_ = _1319_ ? 1'h1 : dtlb_valids[120];
+ assign _1448_ = _1320_ ? 1'h1 : dtlb_valids[121];
+ assign _1449_ = _1321_ ? 1'h1 : dtlb_valids[122];
+ assign _1450_ = _1322_ ? 1'h1 : dtlb_valids[123];
+ assign _1451_ = _1323_ ? 1'h1 : dtlb_valids[124];
+ assign _1452_ = _1324_ ? 1'h1 : dtlb_valids[125];
+ assign _1453_ = _1325_ ? 1'h1 : dtlb_valids[126];
+ assign _1454_ = _1326_ ? 1'h1 : dtlb_valids[127];
+ assign _1465_ = _0338_[4] ? _1464_ : _1463_;
+ assign _1476_ = _0340_[4] ? _1475_ : _1474_;
+ assign _1487_ = _0346_[4] ? _1486_ : _1485_;
+ assign _1498_ = _0348_[4] ? _1497_ : _1496_;
+ assign _1509_ = _0354_[4] ? _1508_ : _1507_;
+ assign _1520_ = _0356_[4] ? _1519_ : _1518_;
+ assign _1531_ = _0362_[4] ? _1530_ : _1529_;
+ assign _1542_ = _0364_[4] ? _1541_ : _1540_;
+ assign _1543_ = tlb_hit_way ? _0368_ : _0352_;
+ assign _1544_ = _0370_ ? _0353_ : _0369_;
+ assign _1555_ = _0373_[4] ? _1554_ : _1553_;
+ assign _1566_ = _0375_[4] ? _1565_ : _1564_;
+ assign _1577_ = _0379_[4] ? _1576_ : _1575_;
+ assign _1588_ = _0381_[4] ? _1587_ : _1586_;
+ assign replace_way = _0387_[4] ? _1598_ : _1597_;
+ assign _1599_ = _0422_ ? \rams%0.dout : \rams%1.dout ;
+ assign _1600_ = _0423_ ? \rams%0.dout : \rams%1.dout ;
+ assign _1601_ = ~ _0511_[4];
+ assign _1602_ = ~ _0511_[3];
+ assign _1603_ = _1601_ & _1602_;
+ assign _1604_ = _1601_ & _0511_[3];
+ assign _1605_ = _0511_[4] & _1602_;
+ assign _1606_ = _0511_[4] & _0511_[3];
+ assign _1607_ = ~ _0511_[2];
+ assign _1608_ = _1603_ & _1607_;
+ assign _1609_ = _1603_ & _0511_[2];
+ assign _1610_ = _1604_ & _1607_;
+ assign _1611_ = _1604_ & _0511_[2];
+ assign _1612_ = _1605_ & _1607_;
+ assign _1613_ = _1605_ & _0511_[2];
+ assign _1614_ = _1606_ & _1607_;
+ assign _1615_ = _1606_ & _0511_[2];
+ assign _1616_ = ~ _0511_[1];
+ assign _1617_ = _1608_ & _1616_;
+ assign _1618_ = _1608_ & _0511_[1];
+ assign _1619_ = _1609_ & _1616_;
+ assign _1620_ = _1609_ & _0511_[1];
+ assign _1621_ = _1610_ & _1616_;
+ assign _1622_ = _1610_ & _0511_[1];
+ assign _1623_ = _1611_ & _1616_;
+ assign _1624_ = _1611_ & _0511_[1];
+ assign _1625_ = _1612_ & _1616_;
+ assign _1626_ = _1612_ & _0511_[1];
+ assign _1627_ = _1613_ & _1616_;
+ assign _1628_ = _1613_ & _0511_[1];
+ assign _1629_ = _1614_ & _1616_;
+ assign _1630_ = _1614_ & _0511_[1];
+ assign _1631_ = _1615_ & _1616_;
+ assign _1632_ = _1615_ & _0511_[1];
+ assign _1633_ = ~ _0511_[0];
+ assign _1634_ = _1617_ & _1633_;
+ assign _1635_ = _1617_ & _0511_[0];
+ assign _1636_ = _1618_ & _1633_;
+ assign _1637_ = _1618_ & _0511_[0];
+ assign _1638_ = _1619_ & _1633_;
+ assign _1639_ = _1619_ & _0511_[0];
+ assign _1640_ = _1620_ & _1633_;
+ assign _1641_ = _1620_ & _0511_[0];
+ assign _1642_ = _1621_ & _1633_;
+ assign _1643_ = _1621_ & _0511_[0];
+ assign _1644_ = _1622_ & _1633_;
+ assign _1645_ = _1622_ & _0511_[0];
+ assign _1646_ = _1623_ & _1633_;
+ assign _1647_ = _1623_ & _0511_[0];
+ assign _1648_ = _1624_ & _1633_;
+ assign _1649_ = _1624_ & _0511_[0];
+ assign _1650_ = _1625_ & _1633_;
+ assign _1651_ = _1625_ & _0511_[0];
+ assign _1652_ = _1626_ & _1633_;
+ assign _1653_ = _1626_ & _0511_[0];
+ assign _1654_ = _1627_ & _1633_;
+ assign _1655_ = _1627_ & _0511_[0];
+ assign _1656_ = _1628_ & _1633_;
+ assign _1657_ = _1628_ & _0511_[0];
+ assign _1658_ = _1629_ & _1633_;
+ assign _1659_ = _1629_ & _0511_[0];
+ assign _1660_ = _1630_ & _1633_;
+ assign _1661_ = _1630_ & _0511_[0];
+ assign _1662_ = _1631_ & _1633_;
+ assign _1663_ = _1631_ & _0511_[0];
+ assign _1664_ = _1632_ & _1633_;
+ assign _1665_ = _1632_ & _0511_[0];
+ assign _1666_ = ~ replace_way;
+ assign _1667_ = _1634_ & _1666_;
+ assign _1668_ = _1634_ & replace_way;
+ assign _1669_ = _1635_ & _1666_;
+ assign _1670_ = _1635_ & replace_way;
+ assign _1671_ = _1636_ & _1666_;
+ assign _1672_ = _1636_ & replace_way;
+ assign _1673_ = _1637_ & _1666_;
+ assign _1674_ = _1637_ & replace_way;
+ assign _1675_ = _1638_ & _1666_;
+ assign _1676_ = _1638_ & replace_way;
+ assign _1677_ = _1639_ & _1666_;
+ assign _1678_ = _1639_ & replace_way;
+ assign _1679_ = _1640_ & _1666_;
+ assign _1680_ = _1640_ & replace_way;
+ assign _1681_ = _1641_ & _1666_;
+ assign _1682_ = _1641_ & replace_way;
+ assign _1683_ = _1642_ & _1666_;
+ assign _1684_ = _1642_ & replace_way;
+ assign _1685_ = _1643_ & _1666_;
+ assign _1686_ = _1643_ & replace_way;
+ assign _1687_ = _1644_ & _1666_;
+ assign _1688_ = _1644_ & replace_way;
+ assign _1689_ = _1645_ & _1666_;
+ assign _1690_ = _1645_ & replace_way;
+ assign _1691_ = _1646_ & _1666_;
+ assign _1692_ = _1646_ & replace_way;
+ assign _1693_ = _1647_ & _1666_;
+ assign _1694_ = _1647_ & replace_way;
+ assign _1695_ = _1648_ & _1666_;
+ assign _1696_ = _1648_ & replace_way;
+ assign _1697_ = _1649_ & _1666_;
+ assign _1698_ = _1649_ & replace_way;
+ assign _1699_ = _1650_ & _1666_;
+ assign _1700_ = _1650_ & replace_way;
+ assign _1701_ = _1651_ & _1666_;
+ assign _1702_ = _1651_ & replace_way;
+ assign _1703_ = _1652_ & _1666_;
+ assign _1704_ = _1652_ & replace_way;
+ assign _1705_ = _1653_ & _1666_;
+ assign _1706_ = _1653_ & replace_way;
+ assign _1707_ = _1654_ & _1666_;
+ assign _1708_ = _1654_ & replace_way;
+ assign _1709_ = _1655_ & _1666_;
+ assign _1710_ = _1655_ & replace_way;
+ assign _1711_ = _1656_ & _1666_;
+ assign _1712_ = _1656_ & replace_way;
+ assign _1713_ = _1657_ & _1666_;
+ assign _1714_ = _1657_ & replace_way;
+ assign _1715_ = _1658_ & _1666_;
+ assign _1716_ = _1658_ & replace_way;
+ assign _1717_ = _1659_ & _1666_;
+ assign _1718_ = _1659_ & replace_way;
+ assign _1719_ = _1660_ & _1666_;
+ assign _1720_ = _1660_ & replace_way;
+ assign _1721_ = _1661_ & _1666_;
+ assign _1722_ = _1661_ & replace_way;
+ assign _1723_ = _1662_ & _1666_;
+ assign _1724_ = _1662_ & replace_way;
+ assign _1725_ = _1663_ & _1666_;
+ assign _1726_ = _1663_ & replace_way;
+ assign _1727_ = _1664_ & _1666_;
+ assign _1728_ = _1664_ & replace_way;
+ assign _1729_ = _1665_ & _1666_;
+ assign _1730_ = _1665_ & replace_way;
+ assign _1731_ = _1667_ ? 1'h0 : cache_valids[0];
+ assign _1732_ = _1668_ ? 1'h0 : cache_valids[1];
+ assign _1733_ = _1669_ ? 1'h0 : cache_valids[2];
+ assign _1734_ = _1670_ ? 1'h0 : cache_valids[3];
+ assign _1735_ = _1671_ ? 1'h0 : cache_valids[4];
+ assign _1736_ = _1672_ ? 1'h0 : cache_valids[5];
+ assign _1737_ = _1673_ ? 1'h0 : cache_valids[6];
+ assign _1738_ = _1674_ ? 1'h0 : cache_valids[7];
+ assign _1739_ = _1675_ ? 1'h0 : cache_valids[8];
+ assign _1740_ = _1676_ ? 1'h0 : cache_valids[9];
+ assign _1741_ = _1677_ ? 1'h0 : cache_valids[10];
+ assign _1742_ = _1678_ ? 1'h0 : cache_valids[11];
+ assign _1743_ = _1679_ ? 1'h0 : cache_valids[12];
+ assign _1744_ = _1680_ ? 1'h0 : cache_valids[13];
+ assign _1745_ = _1681_ ? 1'h0 : cache_valids[14];
+ assign _1746_ = _1682_ ? 1'h0 : cache_valids[15];
+ assign _1747_ = _1683_ ? 1'h0 : cache_valids[16];
+ assign _1748_ = _1684_ ? 1'h0 : cache_valids[17];
+ assign _1749_ = _1685_ ? 1'h0 : cache_valids[18];
+ assign _1750_ = _1686_ ? 1'h0 : cache_valids[19];
+ assign _1751_ = _1687_ ? 1'h0 : cache_valids[20];
+ assign _1752_ = _1688_ ? 1'h0 : cache_valids[21];
+ assign _1753_ = _1689_ ? 1'h0 : cache_valids[22];
+ assign _1754_ = _1690_ ? 1'h0 : cache_valids[23];
+ assign _1755_ = _1691_ ? 1'h0 : cache_valids[24];
+ assign _1756_ = _1692_ ? 1'h0 : cache_valids[25];
+ assign _1757_ = _1693_ ? 1'h0 : cache_valids[26];
+ assign _1758_ = _1694_ ? 1'h0 : cache_valids[27];
+ assign _1759_ = _1695_ ? 1'h0 : cache_valids[28];
+ assign _1760_ = _1696_ ? 1'h0 : cache_valids[29];
+ assign _1761_ = _1697_ ? 1'h0 : cache_valids[30];
+ assign _1762_ = _1698_ ? 1'h0 : cache_valids[31];
+ assign _1763_ = _1699_ ? 1'h0 : cache_valids[32];
+ assign _1764_ = _1700_ ? 1'h0 : cache_valids[33];
+ assign _1765_ = _1701_ ? 1'h0 : cache_valids[34];
+ assign _1766_ = _1702_ ? 1'h0 : cache_valids[35];
+ assign _1767_ = _1703_ ? 1'h0 : cache_valids[36];
+ assign _1768_ = _1704_ ? 1'h0 : cache_valids[37];
+ assign _1769_ = _1705_ ? 1'h0 : cache_valids[38];
+ assign _1770_ = _1706_ ? 1'h0 : cache_valids[39];
+ assign _1771_ = _1707_ ? 1'h0 : cache_valids[40];
+ assign _1772_ = _1708_ ? 1'h0 : cache_valids[41];
+ assign _1773_ = _1709_ ? 1'h0 : cache_valids[42];
+ assign _1774_ = _1710_ ? 1'h0 : cache_valids[43];
+ assign _1775_ = _1711_ ? 1'h0 : cache_valids[44];
+ assign _1776_ = _1712_ ? 1'h0 : cache_valids[45];
+ assign _1777_ = _1713_ ? 1'h0 : cache_valids[46];
+ assign _1778_ = _1714_ ? 1'h0 : cache_valids[47];
+ assign _1779_ = _1715_ ? 1'h0 : cache_valids[48];
+ assign _1780_ = _1716_ ? 1'h0 : cache_valids[49];
+ assign _1781_ = _1717_ ? 1'h0 : cache_valids[50];
+ assign _1782_ = _1718_ ? 1'h0 : cache_valids[51];
+ assign _1783_ = _1719_ ? 1'h0 : cache_valids[52];
+ assign _1784_ = _1720_ ? 1'h0 : cache_valids[53];
+ assign _1785_ = _1721_ ? 1'h0 : cache_valids[54];
+ assign _1786_ = _1722_ ? 1'h0 : cache_valids[55];
+ assign _1787_ = _1723_ ? 1'h0 : cache_valids[56];
+ assign _1788_ = _1724_ ? 1'h0 : cache_valids[57];
+ assign _1789_ = _1725_ ? 1'h0 : cache_valids[58];
+ assign _1790_ = _1726_ ? 1'h0 : cache_valids[59];
+ assign _1791_ = _1727_ ? 1'h0 : cache_valids[60];
+ assign _1792_ = _1728_ ? 1'h0 : cache_valids[61];
+ assign _1793_ = _1729_ ? 1'h0 : cache_valids[62];
+ assign _1794_ = _1730_ ? 1'h0 : cache_valids[63];
+ assign _1805_ = _0513_[4] ? _1804_ : _1803_;
+ assign _1806_ = ~ _0514_[4];
+ assign _1807_ = ~ _0514_[3];
+ assign _1808_ = _1806_ & _1807_;
+ assign _1809_ = _1806_ & _0514_[3];
+ assign _1810_ = _0514_[4] & _1807_;
+ assign _1811_ = _0514_[4] & _0514_[3];
+ assign _1812_ = ~ _0514_[2];
+ assign _1813_ = _1808_ & _1812_;
+ assign _1814_ = _1808_ & _0514_[2];
+ assign _1815_ = _1809_ & _1812_;
+ assign _1816_ = _1809_ & _0514_[2];
+ assign _1817_ = _1810_ & _1812_;
+ assign _1818_ = _1810_ & _0514_[2];
+ assign _1819_ = _1811_ & _1812_;
+ assign _1820_ = _1811_ & _0514_[2];
+ assign _1821_ = ~ _0514_[1];
+ assign _1822_ = _1813_ & _1821_;
+ assign _1823_ = _1813_ & _0514_[1];
+ assign _1824_ = _1814_ & _1821_;
+ assign _1825_ = _1814_ & _0514_[1];
+ assign _1826_ = _1815_ & _1821_;
+ assign _1827_ = _1815_ & _0514_[1];
+ assign _1828_ = _1816_ & _1821_;
+ assign _1829_ = _1816_ & _0514_[1];
+ assign _1830_ = _1817_ & _1821_;
+ assign _1831_ = _1817_ & _0514_[1];
+ assign _1832_ = _1818_ & _1821_;
+ assign _1833_ = _1818_ & _0514_[1];
+ assign _1834_ = _1819_ & _1821_;
+ assign _1835_ = _1819_ & _0514_[1];
+ assign _1836_ = _1820_ & _1821_;
+ assign _1837_ = _1820_ & _0514_[1];
+ assign _1838_ = ~ _0514_[0];
+ assign _1839_ = _1822_ & _1838_;
+ assign _1840_ = _1822_ & _0514_[0];
+ assign _1841_ = _1823_ & _1838_;
+ assign _1842_ = _1823_ & _0514_[0];
+ assign _1843_ = _1824_ & _1838_;
+ assign _1844_ = _1824_ & _0514_[0];
+ assign _1845_ = _1825_ & _1838_;
+ assign _1846_ = _1825_ & _0514_[0];
+ assign _1847_ = _1826_ & _1838_;
+ assign _1848_ = _1826_ & _0514_[0];
+ assign _1849_ = _1827_ & _1838_;
+ assign _1850_ = _1827_ & _0514_[0];
+ assign _1851_ = _1828_ & _1838_;
+ assign _1852_ = _1828_ & _0514_[0];
+ assign _1853_ = _1829_ & _1838_;
+ assign _1854_ = _1829_ & _0514_[0];
+ assign _1855_ = _1830_ & _1838_;
+ assign _1856_ = _1830_ & _0514_[0];
+ assign _1857_ = _1831_ & _1838_;
+ assign _1858_ = _1831_ & _0514_[0];
+ assign _1859_ = _1832_ & _1838_;
+ assign _1860_ = _1832_ & _0514_[0];
+ assign _1861_ = _1833_ & _1838_;
+ assign _1862_ = _1833_ & _0514_[0];
+ assign _1863_ = _1834_ & _1838_;
+ assign _1864_ = _1834_ & _0514_[0];
+ assign _1865_ = _1835_ & _1838_;
+ assign _1866_ = _1835_ & _0514_[0];
+ assign _1867_ = _1836_ & _1838_;
+ assign _1868_ = _1836_ & _0514_[0];
+ assign _1869_ = _1837_ & _1838_;
+ assign _1870_ = _1837_ & _0514_[0];
+ assign _1871_ = _1839_ ? { _1805_[89:45], ra[55:11] } : cache_tags[89:0];
+ assign _1872_ = _1840_ ? { _1805_[89:45], ra[55:11] } : cache_tags[179:90];
+ assign _1873_ = _1841_ ? { _1805_[89:45], ra[55:11] } : cache_tags[269:180];
+ assign _1874_ = _1842_ ? { _1805_[89:45], ra[55:11] } : cache_tags[359:270];
+ assign _1875_ = _1843_ ? { _1805_[89:45], ra[55:11] } : cache_tags[449:360];
+ assign _1876_ = _1844_ ? { _1805_[89:45], ra[55:11] } : cache_tags[539:450];
+ assign _1877_ = _1845_ ? { _1805_[89:45], ra[55:11] } : cache_tags[629:540];
+ assign _1878_ = _1846_ ? { _1805_[89:45], ra[55:11] } : cache_tags[719:630];
+ assign _1879_ = _1847_ ? { _1805_[89:45], ra[55:11] } : cache_tags[809:720];
+ assign _1880_ = _1848_ ? { _1805_[89:45], ra[55:11] } : cache_tags[899:810];
+ assign _1881_ = _1849_ ? { _1805_[89:45], ra[55:11] } : cache_tags[989:900];
+ assign _1882_ = _1850_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1079:990];
+ assign _1883_ = _1851_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1169:1080];
+ assign _1884_ = _1852_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1259:1170];
+ assign _1885_ = _1853_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1349:1260];
+ assign _1886_ = _1854_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1439:1350];
+ assign _1887_ = _1855_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1529:1440];
+ assign _1888_ = _1856_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1619:1530];
+ assign _1889_ = _1857_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1709:1620];
+ assign _1890_ = _1858_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1799:1710];
+ assign _1891_ = _1859_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1889:1800];
+ assign _1892_ = _1860_ ? { _1805_[89:45], ra[55:11] } : cache_tags[1979:1890];
+ assign _1893_ = _1861_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2069:1980];
+ assign _1894_ = _1862_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2159:2070];
+ assign _1895_ = _1863_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2249:2160];
+ assign _1896_ = _1864_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2339:2250];
+ assign _1897_ = _1865_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2429:2340];
+ assign _1898_ = _1866_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2519:2430];
+ assign _1899_ = _1867_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2609:2520];
+ assign _1900_ = _1868_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2699:2610];
+ assign _1901_ = _1869_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2789:2700];
+ assign _1902_ = _1870_ ? { _1805_[89:45], ra[55:11] } : cache_tags[2879:2790];
+ assign _1913_ = _0517_[4] ? _1912_ : _1911_;
+ assign _1914_ = ~ _0518_[4];
+ assign _1915_ = ~ _0518_[3];
+ assign _1916_ = _1914_ & _1915_;
+ assign _1917_ = _1914_ & _0518_[3];
+ assign _1918_ = _0518_[4] & _1915_;
+ assign _1919_ = _0518_[4] & _0518_[3];
+ assign _1920_ = ~ _0518_[2];
+ assign _1921_ = _1916_ & _1920_;
+ assign _1922_ = _1916_ & _0518_[2];
+ assign _1923_ = _1917_ & _1920_;
+ assign _1924_ = _1917_ & _0518_[2];
+ assign _1925_ = _1918_ & _1920_;
+ assign _1926_ = _1918_ & _0518_[2];
+ assign _1927_ = _1919_ & _1920_;
+ assign _1928_ = _1919_ & _0518_[2];
+ assign _1929_ = ~ _0518_[1];
+ assign _1930_ = _1921_ & _1929_;
+ assign _1931_ = _1921_ & _0518_[1];
+ assign _1932_ = _1922_ & _1929_;
+ assign _1933_ = _1922_ & _0518_[1];
+ assign _1934_ = _1923_ & _1929_;
+ assign _1935_ = _1923_ & _0518_[1];
+ assign _1936_ = _1924_ & _1929_;
+ assign _1937_ = _1924_ & _0518_[1];
+ assign _1938_ = _1925_ & _1929_;
+ assign _1939_ = _1925_ & _0518_[1];
+ assign _1940_ = _1926_ & _1929_;
+ assign _1941_ = _1926_ & _0518_[1];
+ assign _1942_ = _1927_ & _1929_;
+ assign _1943_ = _1927_ & _0518_[1];
+ assign _1944_ = _1928_ & _1929_;
+ assign _1945_ = _1928_ & _0518_[1];
+ assign _1946_ = ~ _0518_[0];
+ assign _1947_ = _1930_ & _1946_;
+ assign _1948_ = _1930_ & _0518_[0];
+ assign _1949_ = _1931_ & _1946_;
+ assign _1950_ = _1931_ & _0518_[0];
+ assign _1951_ = _1932_ & _1946_;
+ assign _1952_ = _1932_ & _0518_[0];
+ assign _1953_ = _1933_ & _1946_;
+ assign _1954_ = _1933_ & _0518_[0];
+ assign _1955_ = _1934_ & _1946_;
+ assign _1956_ = _1934_ & _0518_[0];
+ assign _1957_ = _1935_ & _1946_;
+ assign _1958_ = _1935_ & _0518_[0];
+ assign _1959_ = _1936_ & _1946_;
+ assign _1960_ = _1936_ & _0518_[0];
+ assign _1961_ = _1937_ & _1946_;
+ assign _1962_ = _1937_ & _0518_[0];
+ assign _1963_ = _1938_ & _1946_;
+ assign _1964_ = _1938_ & _0518_[0];
+ assign _1965_ = _1939_ & _1946_;
+ assign _1966_ = _1939_ & _0518_[0];
+ assign _1967_ = _1940_ & _1946_;
+ assign _1968_ = _1940_ & _0518_[0];
+ assign _1969_ = _1941_ & _1946_;
+ assign _1970_ = _1941_ & _0518_[0];
+ assign _1971_ = _1942_ & _1946_;
+ assign _1972_ = _1942_ & _0518_[0];
+ assign _1973_ = _1943_ & _1946_;
+ assign _1974_ = _1943_ & _0518_[0];
+ assign _1975_ = _1944_ & _1946_;
+ assign _1976_ = _1944_ & _0518_[0];
+ assign _1977_ = _1945_ & _1946_;
+ assign _1978_ = _1945_ & _0518_[0];
+ assign _1979_ = _1947_ ? { ra[55:11], _1913_[44:0] } : _0515_[89:0];
+ assign _1980_ = _1948_ ? { ra[55:11], _1913_[44:0] } : _0515_[179:90];
+ assign _1981_ = _1949_ ? { ra[55:11], _1913_[44:0] } : _0515_[269:180];
+ assign _1982_ = _1950_ ? { ra[55:11], _1913_[44:0] } : _0515_[359:270];
+ assign _1983_ = _1951_ ? { ra[55:11], _1913_[44:0] } : _0515_[449:360];
+ assign _1984_ = _1952_ ? { ra[55:11], _1913_[44:0] } : _0515_[539:450];
+ assign _1985_ = _1953_ ? { ra[55:11], _1913_[44:0] } : _0515_[629:540];
+ assign _1986_ = _1954_ ? { ra[55:11], _1913_[44:0] } : _0515_[719:630];
+ assign _1987_ = _1955_ ? { ra[55:11], _1913_[44:0] } : _0515_[809:720];
+ assign _1988_ = _1956_ ? { ra[55:11], _1913_[44:0] } : _0515_[899:810];
+ assign _1989_ = _1957_ ? { ra[55:11], _1913_[44:0] } : _0515_[989:900];
+ assign _1990_ = _1958_ ? { ra[55:11], _1913_[44:0] } : _0515_[1079:990];
+ assign _1991_ = _1959_ ? { ra[55:11], _1913_[44:0] } : _0515_[1169:1080];
+ assign _1992_ = _1960_ ? { ra[55:11], _1913_[44:0] } : _0515_[1259:1170];
+ assign _1993_ = _1961_ ? { ra[55:11], _1913_[44:0] } : _0515_[1349:1260];
+ assign _1994_ = _1962_ ? { ra[55:11], _1913_[44:0] } : _0515_[1439:1350];
+ assign _1995_ = _1963_ ? { ra[55:11], _1913_[44:0] } : _0515_[1529:1440];
+ assign _1996_ = _1964_ ? { ra[55:11], _1913_[44:0] } : _0515_[1619:1530];
+ assign _1997_ = _1965_ ? { ra[55:11], _1913_[44:0] } : _0515_[1709:1620];
+ assign _1998_ = _1966_ ? { ra[55:11], _1913_[44:0] } : _0515_[1799:1710];
+ assign _1999_ = _1967_ ? { ra[55:11], _1913_[44:0] } : _0515_[1889:1800];
+ assign _2000_ = _1968_ ? { ra[55:11], _1913_[44:0] } : _0515_[1979:1890];
+ assign _2001_ = _1969_ ? { ra[55:11], _1913_[44:0] } : _0515_[2069:1980];
+ assign _2002_ = _1970_ ? { ra[55:11], _1913_[44:0] } : _0515_[2159:2070];
+ assign _2003_ = _1971_ ? { ra[55:11], _1913_[44:0] } : _0515_[2249:2160];
+ assign _2004_ = _1972_ ? { ra[55:11], _1913_[44:0] } : _0515_[2339:2250];
+ assign _2005_ = _1973_ ? { ra[55:11], _1913_[44:0] } : _0515_[2429:2340];
+ assign _2006_ = _1974_ ? { ra[55:11], _1913_[44:0] } : _0515_[2519:2430];
+ assign _2007_ = _1975_ ? { ra[55:11], _1913_[44:0] } : _0515_[2609:2520];
+ assign _2008_ = _1976_ ? { ra[55:11], _1913_[44:0] } : _0515_[2699:2610];
+ assign _2009_ = _1977_ ? { ra[55:11], _1913_[44:0] } : _0515_[2789:2700];
+ assign _2010_ = _1978_ ? { ra[55:11], _1913_[44:0] } : _0515_[2879:2790];
+ assign _2011_ = ~ _0529_[4];
+ assign _2012_ = ~ _0529_[3];
+ assign _2013_ = _2011_ & _2012_;
+ assign _2014_ = _2011_ & _0529_[3];
+ assign _2015_ = _0529_[4] & _2012_;
+ assign _2016_ = _0529_[4] & _0529_[3];
+ assign _2017_ = ~ _0529_[2];
+ assign _2018_ = _2013_ & _2017_;
+ assign _2019_ = _2013_ & _0529_[2];
+ assign _2020_ = _2014_ & _2017_;
+ assign _2021_ = _2014_ & _0529_[2];
+ assign _2022_ = _2015_ & _2017_;
+ assign _2023_ = _2015_ & _0529_[2];
+ assign _2024_ = _2016_ & _2017_;
+ assign _2025_ = _2016_ & _0529_[2];
+ assign _2026_ = ~ _0529_[1];
+ assign _2027_ = _2018_ & _2026_;
+ assign _2028_ = _2018_ & _0529_[1];
+ assign _2029_ = _2019_ & _2026_;
+ assign _2030_ = _2019_ & _0529_[1];
+ assign _2031_ = _2020_ & _2026_;
+ assign _2032_ = _2020_ & _0529_[1];
+ assign _2033_ = _2021_ & _2026_;
+ assign _2034_ = _2021_ & _0529_[1];
+ assign _2035_ = _2022_ & _2026_;
+ assign _2036_ = _2022_ & _0529_[1];
+ assign _2037_ = _2023_ & _2026_;
+ assign _2038_ = _2023_ & _0529_[1];
+ assign _2039_ = _2024_ & _2026_;
+ assign _2040_ = _2024_ & _0529_[1];
+ assign _2041_ = _2025_ & _2026_;
+ assign _2042_ = _2025_ & _0529_[1];
+ assign _2043_ = ~ _0529_[0];
+ assign _2044_ = _2027_ & _2043_;
+ assign _2045_ = _2027_ & _0529_[0];
+ assign _2046_ = _2028_ & _2043_;
+ assign _2047_ = _2028_ & _0529_[0];
+ assign _2048_ = _2029_ & _2043_;
+ assign _2049_ = _2029_ & _0529_[0];
+ assign _2050_ = _2030_ & _2043_;
+ assign _2051_ = _2030_ & _0529_[0];
+ assign _2052_ = _2031_ & _2043_;
+ assign _2053_ = _2031_ & _0529_[0];
+ assign _2054_ = _2032_ & _2043_;
+ assign _2055_ = _2032_ & _0529_[0];
+ assign _2056_ = _2033_ & _2043_;
+ assign _2057_ = _2033_ & _0529_[0];
+ assign _2058_ = _2034_ & _2043_;
+ assign _2059_ = _2034_ & _0529_[0];
+ assign _2060_ = _2035_ & _2043_;
+ assign _2061_ = _2035_ & _0529_[0];
+ assign _2062_ = _2036_ & _2043_;
+ assign _2063_ = _2036_ & _0529_[0];
+ assign _2064_ = _2037_ & _2043_;
+ assign _2065_ = _2037_ & _0529_[0];
+ assign _2066_ = _2038_ & _2043_;
+ assign _2067_ = _2038_ & _0529_[0];
+ assign _2068_ = _2039_ & _2043_;
+ assign _2069_ = _2039_ & _0529_[0];
+ assign _2070_ = _2040_ & _2043_;
+ assign _2071_ = _2040_ & _0529_[0];
+ assign _2072_ = _2041_ & _2043_;
+ assign _2073_ = _2041_ & _0529_[0];
+ assign _2074_ = _2042_ & _2043_;
+ assign _2075_ = _2042_ & _0529_[0];
+ assign _2076_ = ~ replace_way;
+ assign _2077_ = _2044_ & _2076_;
+ assign _2078_ = _2044_ & replace_way;
+ assign _2079_ = _2045_ & _2076_;
+ assign _2080_ = _2045_ & replace_way;
+ assign _2081_ = _2046_ & _2076_;
+ assign _2082_ = _2046_ & replace_way;
+ assign _2083_ = _2047_ & _2076_;
+ assign _2084_ = _2047_ & replace_way;
+ assign _2085_ = _2048_ & _2076_;
+ assign _2086_ = _2048_ & replace_way;
+ assign _2087_ = _2049_ & _2076_;
+ assign _2088_ = _2049_ & replace_way;
+ assign _2089_ = _2050_ & _2076_;
+ assign _2090_ = _2050_ & replace_way;
+ assign _2091_ = _2051_ & _2076_;
+ assign _2092_ = _2051_ & replace_way;
+ assign _2093_ = _2052_ & _2076_;
+ assign _2094_ = _2052_ & replace_way;
+ assign _2095_ = _2053_ & _2076_;
+ assign _2096_ = _2053_ & replace_way;
+ assign _2097_ = _2054_ & _2076_;
+ assign _2098_ = _2054_ & replace_way;
+ assign _2099_ = _2055_ & _2076_;
+ assign _2100_ = _2055_ & replace_way;
+ assign _2101_ = _2056_ & _2076_;
+ assign _2102_ = _2056_ & replace_way;
+ assign _2103_ = _2057_ & _2076_;
+ assign _2104_ = _2057_ & replace_way;
+ assign _2105_ = _2058_ & _2076_;
+ assign _2106_ = _2058_ & replace_way;
+ assign _2107_ = _2059_ & _2076_;
+ assign _2108_ = _2059_ & replace_way;
+ assign _2109_ = _2060_ & _2076_;
+ assign _2110_ = _2060_ & replace_way;
+ assign _2111_ = _2061_ & _2076_;
+ assign _2112_ = _2061_ & replace_way;
+ assign _2113_ = _2062_ & _2076_;
+ assign _2114_ = _2062_ & replace_way;
+ assign _2115_ = _2063_ & _2076_;
+ assign _2116_ = _2063_ & replace_way;
+ assign _2117_ = _2064_ & _2076_;
+ assign _2118_ = _2064_ & replace_way;
+ assign _2119_ = _2065_ & _2076_;
+ assign _2120_ = _2065_ & replace_way;
+ assign _2121_ = _2066_ & _2076_;
+ assign _2122_ = _2066_ & replace_way;
+ assign _2123_ = _2067_ & _2076_;
+ assign _2124_ = _2067_ & replace_way;
+ assign _2125_ = _2068_ & _2076_;
+ assign _2126_ = _2068_ & replace_way;
+ assign _2127_ = _2069_ & _2076_;
+ assign _2128_ = _2069_ & replace_way;
+ assign _2129_ = _2070_ & _2076_;
+ assign _2130_ = _2070_ & replace_way;
+ assign _2131_ = _2071_ & _2076_;
+ assign _2132_ = _2071_ & replace_way;
+ assign _2133_ = _2072_ & _2076_;
+ assign _2134_ = _2072_ & replace_way;
+ assign _2135_ = _2073_ & _2076_;
+ assign _2136_ = _2073_ & replace_way;
+ assign _2137_ = _2074_ & _2076_;
+ assign _2138_ = _2074_ & replace_way;
+ assign _2139_ = _2075_ & _2076_;
+ assign _2140_ = _2075_ & replace_way;
+ assign _2141_ = _2077_ ? 1'h0 : cache_valids[0];
+ assign _2142_ = _2078_ ? 1'h0 : cache_valids[1];
+ assign _2143_ = _2079_ ? 1'h0 : cache_valids[2];
+ assign _2144_ = _2080_ ? 1'h0 : cache_valids[3];
+ assign _2145_ = _2081_ ? 1'h0 : cache_valids[4];
+ assign _2146_ = _2082_ ? 1'h0 : cache_valids[5];
+ assign _2147_ = _2083_ ? 1'h0 : cache_valids[6];
+ assign _2148_ = _2084_ ? 1'h0 : cache_valids[7];
+ assign _2149_ = _2085_ ? 1'h0 : cache_valids[8];
+ assign _2150_ = _2086_ ? 1'h0 : cache_valids[9];
+ assign _2151_ = _2087_ ? 1'h0 : cache_valids[10];
+ assign _2152_ = _2088_ ? 1'h0 : cache_valids[11];
+ assign _2153_ = _2089_ ? 1'h0 : cache_valids[12];
+ assign _2154_ = _2090_ ? 1'h0 : cache_valids[13];
+ assign _2155_ = _2091_ ? 1'h0 : cache_valids[14];
+ assign _2156_ = _2092_ ? 1'h0 : cache_valids[15];
+ assign _2157_ = _2093_ ? 1'h0 : cache_valids[16];
+ assign _2158_ = _2094_ ? 1'h0 : cache_valids[17];
+ assign _2159_ = _2095_ ? 1'h0 : cache_valids[18];
+ assign _2160_ = _2096_ ? 1'h0 : cache_valids[19];
+ assign _2161_ = _2097_ ? 1'h0 : cache_valids[20];
+ assign _2162_ = _2098_ ? 1'h0 : cache_valids[21];
+ assign _2163_ = _2099_ ? 1'h0 : cache_valids[22];
+ assign _2164_ = _2100_ ? 1'h0 : cache_valids[23];
+ assign _2165_ = _2101_ ? 1'h0 : cache_valids[24];
+ assign _2166_ = _2102_ ? 1'h0 : cache_valids[25];
+ assign _2167_ = _2103_ ? 1'h0 : cache_valids[26];
+ assign _2168_ = _2104_ ? 1'h0 : cache_valids[27];
+ assign _2169_ = _2105_ ? 1'h0 : cache_valids[28];
+ assign _2170_ = _2106_ ? 1'h0 : cache_valids[29];
+ assign _2171_ = _2107_ ? 1'h0 : cache_valids[30];
+ assign _2172_ = _2108_ ? 1'h0 : cache_valids[31];
+ assign _2173_ = _2109_ ? 1'h0 : cache_valids[32];
+ assign _2174_ = _2110_ ? 1'h0 : cache_valids[33];
+ assign _2175_ = _2111_ ? 1'h0 : cache_valids[34];
+ assign _2176_ = _2112_ ? 1'h0 : cache_valids[35];
+ assign _2177_ = _2113_ ? 1'h0 : cache_valids[36];
+ assign _2178_ = _2114_ ? 1'h0 : cache_valids[37];
+ assign _2179_ = _2115_ ? 1'h0 : cache_valids[38];
+ assign _2180_ = _2116_ ? 1'h0 : cache_valids[39];
+ assign _2181_ = _2117_ ? 1'h0 : cache_valids[40];
+ assign _2182_ = _2118_ ? 1'h0 : cache_valids[41];
+ assign _2183_ = _2119_ ? 1'h0 : cache_valids[42];
+ assign _2184_ = _2120_ ? 1'h0 : cache_valids[43];
+ assign _2185_ = _2121_ ? 1'h0 : cache_valids[44];
+ assign _2186_ = _2122_ ? 1'h0 : cache_valids[45];
+ assign _2187_ = _2123_ ? 1'h0 : cache_valids[46];
+ assign _2188_ = _2124_ ? 1'h0 : cache_valids[47];
+ assign _2189_ = _2125_ ? 1'h0 : cache_valids[48];
+ assign _2190_ = _2126_ ? 1'h0 : cache_valids[49];
+ assign _2191_ = _2127_ ? 1'h0 : cache_valids[50];
+ assign _2192_ = _2128_ ? 1'h0 : cache_valids[51];
+ assign _2193_ = _2129_ ? 1'h0 : cache_valids[52];
+ assign _2194_ = _2130_ ? 1'h0 : cache_valids[53];
+ assign _2195_ = _2131_ ? 1'h0 : cache_valids[54];
+ assign _2196_ = _2132_ ? 1'h0 : cache_valids[55];
+ assign _2197_ = _2133_ ? 1'h0 : cache_valids[56];
+ assign _2198_ = _2134_ ? 1'h0 : cache_valids[57];
+ assign _2199_ = _2135_ ? 1'h0 : cache_valids[58];
+ assign _2200_ = _2136_ ? 1'h0 : cache_valids[59];
+ assign _2201_ = _2137_ ? 1'h0 : cache_valids[60];
+ assign _2202_ = _2138_ ? 1'h0 : cache_valids[61];
+ assign _2203_ = _2139_ ? 1'h0 : cache_valids[62];
+ assign _2204_ = _2140_ ? 1'h0 : cache_valids[63];
+ assign _2215_ = _0531_[4] ? _2214_ : _2213_;
+ assign _2216_ = ~ _0532_[4];
+ assign _2217_ = ~ _0532_[3];
+ assign _2218_ = _2216_ & _2217_;
+ assign _2219_ = _2216_ & _0532_[3];
+ assign _2220_ = _0532_[4] & _2217_;
+ assign _2221_ = _0532_[4] & _0532_[3];
+ assign _2222_ = ~ _0532_[2];
+ assign _2223_ = _2218_ & _2222_;
+ assign _2224_ = _2218_ & _0532_[2];
+ assign _2225_ = _2219_ & _2222_;
+ assign _2226_ = _2219_ & _0532_[2];
+ assign _2227_ = _2220_ & _2222_;
+ assign _2228_ = _2220_ & _0532_[2];
+ assign _2229_ = _2221_ & _2222_;
+ assign _2230_ = _2221_ & _0532_[2];
+ assign _2231_ = ~ _0532_[1];
+ assign _2232_ = _2223_ & _2231_;
+ assign _2233_ = _2223_ & _0532_[1];
+ assign _2234_ = _2224_ & _2231_;
+ assign _2235_ = _2224_ & _0532_[1];
+ assign _2236_ = _2225_ & _2231_;
+ assign _2237_ = _2225_ & _0532_[1];
+ assign _2238_ = _2226_ & _2231_;
+ assign _2239_ = _2226_ & _0532_[1];
+ assign _2240_ = _2227_ & _2231_;
+ assign _2241_ = _2227_ & _0532_[1];
+ assign _2242_ = _2228_ & _2231_;
+ assign _2243_ = _2228_ & _0532_[1];
+ assign _2244_ = _2229_ & _2231_;
+ assign _2245_ = _2229_ & _0532_[1];
+ assign _2246_ = _2230_ & _2231_;
+ assign _2247_ = _2230_ & _0532_[1];
+ assign _2248_ = ~ _0532_[0];
+ assign _2249_ = _2232_ & _2248_;
+ assign _2250_ = _2232_ & _0532_[0];
+ assign _2251_ = _2233_ & _2248_;
+ assign _2252_ = _2233_ & _0532_[0];
+ assign _2253_ = _2234_ & _2248_;
+ assign _2254_ = _2234_ & _0532_[0];
+ assign _2255_ = _2235_ & _2248_;
+ assign _2256_ = _2235_ & _0532_[0];
+ assign _2257_ = _2236_ & _2248_;
+ assign _2258_ = _2236_ & _0532_[0];
+ assign _2259_ = _2237_ & _2248_;
+ assign _2260_ = _2237_ & _0532_[0];
+ assign _2261_ = _2238_ & _2248_;
+ assign _2262_ = _2238_ & _0532_[0];
+ assign _2263_ = _2239_ & _2248_;
+ assign _2264_ = _2239_ & _0532_[0];
+ assign _2265_ = _2240_ & _2248_;
+ assign _2266_ = _2240_ & _0532_[0];
+ assign _2267_ = _2241_ & _2248_;
+ assign _2268_ = _2241_ & _0532_[0];
+ assign _2269_ = _2242_ & _2248_;
+ assign _2270_ = _2242_ & _0532_[0];
+ assign _2271_ = _2243_ & _2248_;
+ assign _2272_ = _2243_ & _0532_[0];
+ assign _2273_ = _2244_ & _2248_;
+ assign _2274_ = _2244_ & _0532_[0];
+ assign _2275_ = _2245_ & _2248_;
+ assign _2276_ = _2245_ & _0532_[0];
+ assign _2277_ = _2246_ & _2248_;
+ assign _2278_ = _2246_ & _0532_[0];
+ assign _2279_ = _2247_ & _2248_;
+ assign _2280_ = _2247_ & _0532_[0];
+ assign _2281_ = _2249_ ? { _2215_[89:45], ra[55:11] } : cache_tags[89:0];
+ assign _2282_ = _2250_ ? { _2215_[89:45], ra[55:11] } : cache_tags[179:90];
+ assign _2283_ = _2251_ ? { _2215_[89:45], ra[55:11] } : cache_tags[269:180];
+ assign _2284_ = _2252_ ? { _2215_[89:45], ra[55:11] } : cache_tags[359:270];
+ assign _2285_ = _2253_ ? { _2215_[89:45], ra[55:11] } : cache_tags[449:360];
+ assign _2286_ = _2254_ ? { _2215_[89:45], ra[55:11] } : cache_tags[539:450];
+ assign _2287_ = _2255_ ? { _2215_[89:45], ra[55:11] } : cache_tags[629:540];
+ assign _2288_ = _2256_ ? { _2215_[89:45], ra[55:11] } : cache_tags[719:630];
+ assign _2289_ = _2257_ ? { _2215_[89:45], ra[55:11] } : cache_tags[809:720];
+ assign _2290_ = _2258_ ? { _2215_[89:45], ra[55:11] } : cache_tags[899:810];
+ assign _2291_ = _2259_ ? { _2215_[89:45], ra[55:11] } : cache_tags[989:900];
+ assign _2292_ = _2260_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1079:990];
+ assign _2293_ = _2261_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1169:1080];
+ assign _2294_ = _2262_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1259:1170];
+ assign _2295_ = _2263_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1349:1260];
+ assign _2296_ = _2264_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1439:1350];
+ assign _2297_ = _2265_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1529:1440];
+ assign _2298_ = _2266_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1619:1530];
+ assign _2299_ = _2267_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1709:1620];
+ assign _2300_ = _2268_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1799:1710];
+ assign _2301_ = _2269_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1889:1800];
+ assign _2302_ = _2270_ ? { _2215_[89:45], ra[55:11] } : cache_tags[1979:1890];
+ assign _2303_ = _2271_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2069:1980];
+ assign _2304_ = _2272_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2159:2070];
+ assign _2305_ = _2273_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2249:2160];
+ assign _2306_ = _2274_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2339:2250];
+ assign _2307_ = _2275_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2429:2340];
+ assign _2308_ = _2276_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2519:2430];
+ assign _2309_ = _2277_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2609:2520];
+ assign _2310_ = _2278_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2699:2610];
+ assign _2311_ = _2279_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2789:2700];
+ assign _2312_ = _2280_ ? { _2215_[89:45], ra[55:11] } : cache_tags[2879:2790];
+ assign _2323_ = _0535_[4] ? _2322_ : _2321_;
+ assign _2324_ = ~ _0536_[4];
+ assign _2325_ = ~ _0536_[3];
+ assign _2326_ = _2324_ & _2325_;
+ assign _2327_ = _2324_ & _0536_[3];
+ assign _2328_ = _0536_[4] & _2325_;
+ assign _2329_ = _0536_[4] & _0536_[3];
+ assign _2330_ = ~ _0536_[2];
+ assign _2331_ = _2326_ & _2330_;
+ assign _2332_ = _2326_ & _0536_[2];
+ assign _2333_ = _2327_ & _2330_;
+ assign _2334_ = _2327_ & _0536_[2];
+ assign _2335_ = _2328_ & _2330_;
+ assign _2336_ = _2328_ & _0536_[2];
+ assign _2337_ = _2329_ & _2330_;
+ assign _2338_ = _2329_ & _0536_[2];
+ assign _2339_ = ~ _0536_[1];
+ assign _2340_ = _2331_ & _2339_;
+ assign _2341_ = _2331_ & _0536_[1];
+ assign _2342_ = _2332_ & _2339_;
+ assign _2343_ = _2332_ & _0536_[1];
+ assign _2344_ = _2333_ & _2339_;
+ assign _2345_ = _2333_ & _0536_[1];
+ assign _2346_ = _2334_ & _2339_;
+ assign _2347_ = _2334_ & _0536_[1];
+ assign _2348_ = _2335_ & _2339_;
+ assign _2349_ = _2335_ & _0536_[1];
+ assign _2350_ = _2336_ & _2339_;
+ assign _2351_ = _2336_ & _0536_[1];
+ assign _2352_ = _2337_ & _2339_;
+ assign _2353_ = _2337_ & _0536_[1];
+ assign _2354_ = _2338_ & _2339_;
+ assign _2355_ = _2338_ & _0536_[1];
+ assign _2356_ = ~ _0536_[0];
+ assign _2357_ = _2340_ & _2356_;
+ assign _2358_ = _2340_ & _0536_[0];
+ assign _2359_ = _2341_ & _2356_;
+ assign _2360_ = _2341_ & _0536_[0];
+ assign _2361_ = _2342_ & _2356_;
+ assign _2362_ = _2342_ & _0536_[0];
+ assign _2363_ = _2343_ & _2356_;
+ assign _2364_ = _2343_ & _0536_[0];
+ assign _2365_ = _2344_ & _2356_;
+ assign _2366_ = _2344_ & _0536_[0];
+ assign _2367_ = _2345_ & _2356_;
+ assign _2368_ = _2345_ & _0536_[0];
+ assign _2369_ = _2346_ & _2356_;
+ assign _2370_ = _2346_ & _0536_[0];
+ assign _2371_ = _2347_ & _2356_;
+ assign _2372_ = _2347_ & _0536_[0];
+ assign _2373_ = _2348_ & _2356_;
+ assign _2374_ = _2348_ & _0536_[0];
+ assign _2375_ = _2349_ & _2356_;
+ assign _2376_ = _2349_ & _0536_[0];
+ assign _2377_ = _2350_ & _2356_;
+ assign _2378_ = _2350_ & _0536_[0];
+ assign _2379_ = _2351_ & _2356_;
+ assign _2380_ = _2351_ & _0536_[0];
+ assign _2381_ = _2352_ & _2356_;
+ assign _2382_ = _2352_ & _0536_[0];
+ assign _2383_ = _2353_ & _2356_;
+ assign _2384_ = _2353_ & _0536_[0];
+ assign _2385_ = _2354_ & _2356_;
+ assign _2386_ = _2354_ & _0536_[0];
+ assign _2387_ = _2355_ & _2356_;
+ assign _2388_ = _2355_ & _0536_[0];
+ assign _2389_ = _2357_ ? { ra[55:11], _2323_[44:0] } : _0533_[89:0];
+ assign _2390_ = _2358_ ? { ra[55:11], _2323_[44:0] } : _0533_[179:90];
+ assign _2391_ = _2359_ ? { ra[55:11], _2323_[44:0] } : _0533_[269:180];
+ assign _2392_ = _2360_ ? { ra[55:11], _2323_[44:0] } : _0533_[359:270];
+ assign _2393_ = _2361_ ? { ra[55:11], _2323_[44:0] } : _0533_[449:360];
+ assign _2394_ = _2362_ ? { ra[55:11], _2323_[44:0] } : _0533_[539:450];
+ assign _2395_ = _2363_ ? { ra[55:11], _2323_[44:0] } : _0533_[629:540];
+ assign _2396_ = _2364_ ? { ra[55:11], _2323_[44:0] } : _0533_[719:630];
+ assign _2397_ = _2365_ ? { ra[55:11], _2323_[44:0] } : _0533_[809:720];
+ assign _2398_ = _2366_ ? { ra[55:11], _2323_[44:0] } : _0533_[899:810];
+ assign _2399_ = _2367_ ? { ra[55:11], _2323_[44:0] } : _0533_[989:900];
+ assign _2400_ = _2368_ ? { ra[55:11], _2323_[44:0] } : _0533_[1079:990];
+ assign _2401_ = _2369_ ? { ra[55:11], _2323_[44:0] } : _0533_[1169:1080];
+ assign _2402_ = _2370_ ? { ra[55:11], _2323_[44:0] } : _0533_[1259:1170];
+ assign _2403_ = _2371_ ? { ra[55:11], _2323_[44:0] } : _0533_[1349:1260];
+ assign _2404_ = _2372_ ? { ra[55:11], _2323_[44:0] } : _0533_[1439:1350];
+ assign _2405_ = _2373_ ? { ra[55:11], _2323_[44:0] } : _0533_[1529:1440];
+ assign _2406_ = _2374_ ? { ra[55:11], _2323_[44:0] } : _0533_[1619:1530];
+ assign _2407_ = _2375_ ? { ra[55:11], _2323_[44:0] } : _0533_[1709:1620];
+ assign _2408_ = _2376_ ? { ra[55:11], _2323_[44:0] } : _0533_[1799:1710];
+ assign _2409_ = _2377_ ? { ra[55:11], _2323_[44:0] } : _0533_[1889:1800];
+ assign _2410_ = _2378_ ? { ra[55:11], _2323_[44:0] } : _0533_[1979:1890];
+ assign _2411_ = _2379_ ? { ra[55:11], _2323_[44:0] } : _0533_[2069:1980];
+ assign _2412_ = _2380_ ? { ra[55:11], _2323_[44:0] } : _0533_[2159:2070];
+ assign _2413_ = _2381_ ? { ra[55:11], _2323_[44:0] } : _0533_[2249:2160];
+ assign _2414_ = _2382_ ? { ra[55:11], _2323_[44:0] } : _0533_[2339:2250];
+ assign _2415_ = _2383_ ? { ra[55:11], _2323_[44:0] } : _0533_[2429:2340];
+ assign _2416_ = _2384_ ? { ra[55:11], _2323_[44:0] } : _0533_[2519:2430];
+ assign _2417_ = _2385_ ? { ra[55:11], _2323_[44:0] } : _0533_[2609:2520];
+ assign _2418_ = _2386_ ? { ra[55:11], _2323_[44:0] } : _0533_[2699:2610];
+ assign _2419_ = _2387_ ? { ra[55:11], _2323_[44:0] } : _0533_[2789:2700];
+ assign _2420_ = _2388_ ? { ra[55:11], _2323_[44:0] } : _0533_[2879:2790];
+ assign _2421_ = ~ _0583_[4];
+ assign _2422_ = ~ _0583_[3];
+ assign _2423_ = _2421_ & _2422_;
+ assign _2424_ = _2421_ & _0583_[3];
+ assign _2425_ = _0583_[4] & _2422_;
+ assign _2426_ = _0583_[4] & _0583_[3];
+ assign _2427_ = ~ _0583_[2];
+ assign _2428_ = _2423_ & _2427_;
+ assign _2429_ = _2423_ & _0583_[2];
+ assign _2430_ = _2424_ & _2427_;
+ assign _2431_ = _2424_ & _0583_[2];
+ assign _2432_ = _2425_ & _2427_;
+ assign _2433_ = _2425_ & _0583_[2];
+ assign _2434_ = _2426_ & _2427_;
+ assign _2435_ = _2426_ & _0583_[2];
+ assign _2436_ = ~ _0583_[1];
+ assign _2437_ = _2428_ & _2436_;
+ assign _2438_ = _2428_ & _0583_[1];
+ assign _2439_ = _2429_ & _2436_;
+ assign _2440_ = _2429_ & _0583_[1];
+ assign _2441_ = _2430_ & _2436_;
+ assign _2442_ = _2430_ & _0583_[1];
+ assign _2443_ = _2431_ & _2436_;
+ assign _2444_ = _2431_ & _0583_[1];
+ assign _2445_ = _2432_ & _2436_;
+ assign _2446_ = _2432_ & _0583_[1];
+ assign _2447_ = _2433_ & _2436_;
+ assign _2448_ = _2433_ & _0583_[1];
+ assign _2449_ = _2434_ & _2436_;
+ assign _2450_ = _2434_ & _0583_[1];
+ assign _2451_ = _2435_ & _2436_;
+ assign _2452_ = _2435_ & _0583_[1];
+ assign _2453_ = ~ _0583_[0];
+ assign _2454_ = _2437_ & _2453_;
+ assign _2455_ = _2437_ & _0583_[0];
+ assign _2456_ = _2438_ & _2453_;
+ assign _2457_ = _2438_ & _0583_[0];
+ assign _2458_ = _2439_ & _2453_;
+ assign _2459_ = _2439_ & _0583_[0];
+ assign _2460_ = _2440_ & _2453_;
+ assign _2461_ = _2440_ & _0583_[0];
+ assign _2462_ = _2441_ & _2453_;
+ assign _2463_ = _2441_ & _0583_[0];
+ assign _2464_ = _2442_ & _2453_;
+ assign _2465_ = _2442_ & _0583_[0];
+ assign _2466_ = _2443_ & _2453_;
+ assign _2467_ = _2443_ & _0583_[0];
+ assign _2468_ = _2444_ & _2453_;
+ assign _2469_ = _2444_ & _0583_[0];
+ assign _2470_ = _2445_ & _2453_;
+ assign _2471_ = _2445_ & _0583_[0];
+ assign _2472_ = _2446_ & _2453_;
+ assign _2473_ = _2446_ & _0583_[0];
+ assign _2474_ = _2447_ & _2453_;
+ assign _2475_ = _2447_ & _0583_[0];
+ assign _2476_ = _2448_ & _2453_;
+ assign _2477_ = _2448_ & _0583_[0];
+ assign _2478_ = _2449_ & _2453_;
+ assign _2479_ = _2449_ & _0583_[0];
+ assign _2480_ = _2450_ & _2453_;
+ assign _2481_ = _2450_ & _0583_[0];
+ assign _2482_ = _2451_ & _2453_;
+ assign _2483_ = _2451_ & _0583_[0];
+ assign _2484_ = _2452_ & _2453_;
+ assign _2485_ = _2452_ & _0583_[0];
+ assign _2486_ = ~ _0629_[176];
+ assign _2487_ = _2454_ & _2486_;
+ assign _2488_ = _2454_ & _0629_[176];
+ assign _2489_ = _2455_ & _2486_;
+ assign _2490_ = _2455_ & _0629_[176];
+ assign _2491_ = _2456_ & _2486_;
+ assign _2492_ = _2456_ & _0629_[176];
+ assign _2493_ = _2457_ & _2486_;
+ assign _2494_ = _2457_ & _0629_[176];
+ assign _2495_ = _2458_ & _2486_;
+ assign _2496_ = _2458_ & _0629_[176];
+ assign _2497_ = _2459_ & _2486_;
+ assign _2498_ = _2459_ & _0629_[176];
+ assign _2499_ = _2460_ & _2486_;
+ assign _2500_ = _2460_ & _0629_[176];
+ assign _2501_ = _2461_ & _2486_;
+ assign _2502_ = _2461_ & _0629_[176];
+ assign _2503_ = _2462_ & _2486_;
+ assign _2504_ = _2462_ & _0629_[176];
+ assign _2505_ = _2463_ & _2486_;
+ assign _2506_ = _2463_ & _0629_[176];
+ assign _2507_ = _2464_ & _2486_;
+ assign _2508_ = _2464_ & _0629_[176];
+ assign _2509_ = _2465_ & _2486_;
+ assign _2510_ = _2465_ & _0629_[176];
+ assign _2511_ = _2466_ & _2486_;
+ assign _2512_ = _2466_ & _0629_[176];
+ assign _2513_ = _2467_ & _2486_;
+ assign _2514_ = _2467_ & _0629_[176];
+ assign _2515_ = _2468_ & _2486_;
+ assign _2516_ = _2468_ & _0629_[176];
+ assign _2517_ = _2469_ & _2486_;
+ assign _2518_ = _2469_ & _0629_[176];
+ assign _2519_ = _2470_ & _2486_;
+ assign _2520_ = _2470_ & _0629_[176];
+ assign _2521_ = _2471_ & _2486_;
+ assign _2522_ = _2471_ & _0629_[176];
+ assign _2523_ = _2472_ & _2486_;
+ assign _2524_ = _2472_ & _0629_[176];
+ assign _2525_ = _2473_ & _2486_;
+ assign _2526_ = _2473_ & _0629_[176];
+ assign _2527_ = _2474_ & _2486_;
+ assign _2528_ = _2474_ & _0629_[176];
+ assign _2529_ = _2475_ & _2486_;
+ assign _2530_ = _2475_ & _0629_[176];
+ assign _2531_ = _2476_ & _2486_;
+ assign _2532_ = _2476_ & _0629_[176];
+ assign _2533_ = _2477_ & _2486_;
+ assign _2534_ = _2477_ & _0629_[176];
+ assign _2535_ = _2478_ & _2486_;
+ assign _2536_ = _2478_ & _0629_[176];
+ assign _2537_ = _2479_ & _2486_;
+ assign _2538_ = _2479_ & _0629_[176];
+ assign _2539_ = _2480_ & _2486_;
+ assign _2540_ = _2480_ & _0629_[176];
+ assign _2541_ = _2481_ & _2486_;
+ assign _2542_ = _2481_ & _0629_[176];
+ assign _2543_ = _2482_ & _2486_;
+ assign _2544_ = _2482_ & _0629_[176];
+ assign _2545_ = _2483_ & _2486_;
+ assign _2546_ = _2483_ & _0629_[176];
+ assign _2547_ = _2484_ & _2486_;
+ assign _2548_ = _2484_ & _0629_[176];
+ assign _2549_ = _2485_ & _2486_;
+ assign _2550_ = _2485_ & _0629_[176];
+ assign _2551_ = _2487_ ? 1'h1 : cache_valids[0];
+ assign _2552_ = _2488_ ? 1'h1 : cache_valids[1];
+ assign _2553_ = _2489_ ? 1'h1 : cache_valids[2];
+ assign _2554_ = _2490_ ? 1'h1 : cache_valids[3];
+ assign _2555_ = _2491_ ? 1'h1 : cache_valids[4];
+ assign _2556_ = _2492_ ? 1'h1 : cache_valids[5];
+ assign _2557_ = _2493_ ? 1'h1 : cache_valids[6];
+ assign _2558_ = _2494_ ? 1'h1 : cache_valids[7];
+ assign _2559_ = _2495_ ? 1'h1 : cache_valids[8];
+ assign _2560_ = _2496_ ? 1'h1 : cache_valids[9];
+ assign _2561_ = _2497_ ? 1'h1 : cache_valids[10];
+ assign _2562_ = _2498_ ? 1'h1 : cache_valids[11];
+ assign _2563_ = _2499_ ? 1'h1 : cache_valids[12];
+ assign _2564_ = _2500_ ? 1'h1 : cache_valids[13];
+ assign _2565_ = _2501_ ? 1'h1 : cache_valids[14];
+ assign _2566_ = _2502_ ? 1'h1 : cache_valids[15];
+ assign _2567_ = _2503_ ? 1'h1 : cache_valids[16];
+ assign _2568_ = _2504_ ? 1'h1 : cache_valids[17];
+ assign _2569_ = _2505_ ? 1'h1 : cache_valids[18];
+ assign _2570_ = _2506_ ? 1'h1 : cache_valids[19];
+ assign _2571_ = _2507_ ? 1'h1 : cache_valids[20];
+ assign _2572_ = _2508_ ? 1'h1 : cache_valids[21];
+ assign _2573_ = _2509_ ? 1'h1 : cache_valids[22];
+ assign _2574_ = _2510_ ? 1'h1 : cache_valids[23];
+ assign _2575_ = _2511_ ? 1'h1 : cache_valids[24];
+ assign _2576_ = _2512_ ? 1'h1 : cache_valids[25];
+ assign _2577_ = _2513_ ? 1'h1 : cache_valids[26];
+ assign _2578_ = _2514_ ? 1'h1 : cache_valids[27];
+ assign _2579_ = _2515_ ? 1'h1 : cache_valids[28];
+ assign _2580_ = _2516_ ? 1'h1 : cache_valids[29];
+ assign _2581_ = _2517_ ? 1'h1 : cache_valids[30];
+ assign _2582_ = _2518_ ? 1'h1 : cache_valids[31];
+ assign _2583_ = _2519_ ? 1'h1 : cache_valids[32];
+ assign _2584_ = _2520_ ? 1'h1 : cache_valids[33];
+ assign _2585_ = _2521_ ? 1'h1 : cache_valids[34];
+ assign _2586_ = _2522_ ? 1'h1 : cache_valids[35];
+ assign _2587_ = _2523_ ? 1'h1 : cache_valids[36];
+ assign _2588_ = _2524_ ? 1'h1 : cache_valids[37];
+ assign _2589_ = _2525_ ? 1'h1 : cache_valids[38];
+ assign _2590_ = _2526_ ? 1'h1 : cache_valids[39];
+ assign _2591_ = _2527_ ? 1'h1 : cache_valids[40];
+ assign _2592_ = _2528_ ? 1'h1 : cache_valids[41];
+ assign _2593_ = _2529_ ? 1'h1 : cache_valids[42];
+ assign _2594_ = _2530_ ? 1'h1 : cache_valids[43];
+ assign _2595_ = _2531_ ? 1'h1 : cache_valids[44];
+ assign _2596_ = _2532_ ? 1'h1 : cache_valids[45];
+ assign _2597_ = _2533_ ? 1'h1 : cache_valids[46];
+ assign _2598_ = _2534_ ? 1'h1 : cache_valids[47];
+ assign _2599_ = _2535_ ? 1'h1 : cache_valids[48];
+ assign _2600_ = _2536_ ? 1'h1 : cache_valids[49];
+ assign _2601_ = _2537_ ? 1'h1 : cache_valids[50];
+ assign _2602_ = _2538_ ? 1'h1 : cache_valids[51];
+ assign _2603_ = _2539_ ? 1'h1 : cache_valids[52];
+ assign _2604_ = _2540_ ? 1'h1 : cache_valids[53];
+ assign _2605_ = _2541_ ? 1'h1 : cache_valids[54];
+ assign _2606_ = _2542_ ? 1'h1 : cache_valids[55];
+ assign _2607_ = _2543_ ? 1'h1 : cache_valids[56];
+ assign _2608_ = _2544_ ? 1'h1 : cache_valids[57];
+ assign _2609_ = _2545_ ? 1'h1 : cache_valids[58];
+ assign _2610_ = _2546_ ? 1'h1 : cache_valids[59];
+ assign _2611_ = _2547_ ? 1'h1 : cache_valids[60];
+ assign _2612_ = _2548_ ? 1'h1 : cache_valids[61];
+ assign _2613_ = _2549_ ? 1'h1 : cache_valids[62];
+ assign _2614_ = _2550_ ? 1'h1 : cache_valids[63];
+ plru_1 \maybe_plrus.plrus%0.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%0.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%0.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%1.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%1.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%1.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%10.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%10.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%10.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%11.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%11.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%11.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%12.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%12.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%12.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%13.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%13.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%13.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%14.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%14.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%14.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%15.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%15.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%15.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%16.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%16.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%16.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%17.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%17.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%17.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%18.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%18.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%18.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%19.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%19.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%19.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%2.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%2.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%2.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%20.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%20.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%20.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%21.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%21.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%21.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%22.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%22.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%22.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%23.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%23.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%23.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%24.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%24.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%24.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%25.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%25.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%25.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%26.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%26.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%26.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%27.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%27.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%27.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%28.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%28.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%28.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%29.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%29.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%29.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%3.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%3.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%3.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%30.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%30.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%30.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%31.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%31.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%31.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%4.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%4.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%4.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%5.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%5.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%5.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%6.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%6.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%6.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%7.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%7.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%7.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%8.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%8.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%8.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%9.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%9.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%9.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%0.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%0.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%1.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%1.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%1.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%10.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%10.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%10.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%11.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%11.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%11.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%12.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%12.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%12.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%13.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%13.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%13.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%14.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%14.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%14.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%15.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%15.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%15.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%16.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%16.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%16.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%17.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%17.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%17.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%18.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%18.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%18.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%19.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%19.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%19.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%2.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%2.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%2.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%20.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%20.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%20.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%21.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%21.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%21.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%22.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%22.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%22.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%23.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%23.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%23.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%24.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%24.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%24.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%25.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%25.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%25.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%26.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%26.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%26.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%27.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%27.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%27.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%28.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%28.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%28.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%29.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%29.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%29.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%3.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%3.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%3.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%30.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%30.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%30.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%31.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%31.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%31.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%32.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%32.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%32.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%33.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%33.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%33.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%34.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%34.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%34.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%35.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%35.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%35.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%36.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%36.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%36.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%37.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%37.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%37.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%38.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%38.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%38.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%39.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%39.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%39.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%4.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%4.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%4.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%40.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%40.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%40.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%41.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%41.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%41.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%42.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%42.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%42.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%43.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%43.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%43.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%44.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%44.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%44.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%45.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%45.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%45.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%46.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%46.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%46.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%47.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%47.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%47.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%48.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%48.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%48.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%49.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%49.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%49.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%5.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%5.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%5.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%50.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%50.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%50.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%51.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%51.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%51.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%52.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%52.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%52.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%53.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%53.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%53.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%54.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%54.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%54.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%55.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%55.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%55.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%56.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%56.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%56.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%57.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%57.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%57.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%58.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%58.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%58.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%59.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%59.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%59.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%6.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%6.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%6.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%60.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%60.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%60.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%61.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%61.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%61.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%62.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%62.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%62.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%63.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%63.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%63.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%7.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%7.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%7.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%8.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%8.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%8.tlb_plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_tlb_plrus.tlb_plrus%9.tlb_plru (
+ .acc(tlb_hit_way),
+ .acc_en(\maybe_tlb_plrus.tlb_plrus%9.tlb_plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_tlb_plrus.tlb_plrus%9.tlb_plru_out ),
+ .rst(rst)
+ );
+ cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546 \rams%0.way (
+ .clk(clk),
+ .rd_addr(early_req_row),
+ .rd_data(\rams%0.dout ),
+ .rd_en(1'h1),
+ .wr_addr(\rams%0.wr_addr ),
+ .wr_data(\rams%0.wr_data ),
+ .wr_sel({ _0468_, _0467_, _0466_, _0465_, _0464_, _0463_, _0462_, _0461_ })
+ );
+ cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546 \rams%1.way (
+ .clk(clk),
+ .rd_addr(early_req_row),
+ .rd_data(\rams%1.dout ),
+ .rd_en(1'h1),
+ .wr_addr(\rams%1.wr_addr ),
+ .wr_data(\rams%1.wr_data ),
+ .wr_sel({ _0494_, _0493_, _0492_, _0491_, _0490_, _0489_, _0488_, _0487_ })
+ );
+ assign d_out = _0441_;
+ assign m_out = { _0442_, 1'h0 };
+ assign stall_out = _0409_;
+ assign wishbone_out = _0629_[175:69];
+endmodule
+
+module decode1(clk, rst, stall_in, flush_in, f_in, d_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [147:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire [9:0] _07_;
+ wire _08_;
+ wire [9:0] _09_;
+ wire _10_;
+ wire [2:0] _11_;
+ wire [37:0] _12_;
+ wire _13_;
+ wire [3:0] _14_;
+ wire _15_;
+ wire [1:0] _16_;
+ wire _17_;
+ wire [1:0] _18_;
+ wire [31:0] _19_;
+ wire _20_;
+ wire [5:0] _21_;
+ wire [37:0] _22_;
+ wire [37:0] _23_;
+ wire [37:0] _24_;
+ wire [37:0] _25_;
+ wire [37:0] _26_;
+ wire [37:0] _27_;
+ wire _28_;
+ wire [37:0] _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire [5:0] _34_;
+ wire _35_;
+ wire _36_;
+ wire [5:0] _37_;
+ wire [5:0] _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire [5:0] _58_;
+ wire [4:0] _59_;
+ wire [4:0] _60_;
+ wire [5:0] _61_;
+ wire _62_;
+ wire _63_;
+ wire _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ wire [1:0] _70_;
+ wire [1:0] _71_;
+ wire _72_;
+ wire _73_;
+ wire [11:0] _74_;
+ wire [5:0] _75_;
+ wire [5:0] _76_;
+ wire _77_;
+ wire _78_;
+ wire [11:0] _79_;
+ wire [1:0] _80_;
+ wire _81_;
+ wire _82_;
+ wire [38911:0] _83_;
+ wire [37:0] _84_;
+ wire [1023:0] _85_;
+ wire _86_;
+ wire [303:0] _87_;
+ wire [37:0] _88_;
+ wire [607:0] _89_;
+ wire [37:0] _90_;
+ wire [151:0] _91_;
+ wire [37:0] _92_;
+ wire [151:0] _93_;
+ wire [37:0] _94_;
+ wire [2431:0] _95_;
+ wire [37:0] _96_;
+ input clk;
+ output [147:0] d_out;
+ input [98:0] f_in;
+ input flush_in;
+ reg [147:0] r;
+ wire [147:0] rin;
+ input rst;
+ input stall_in;
+ reg [37:0] \$mem$\3502 [1023:0];
+ reg [0:0] \$mem$\3504 [1023:0];
+ reg [37:0] \$mem$\3506 [7:0];
+ reg [37:0] \$mem$\3508 [15:0];
+ reg [37:0] \$mem$\3510 [3:0];
+ reg [37:0] \$mem$\3512 [3:0];
+ reg [37:0] \$mem$\3514 [63:0];
+ assign _00_ = rst | flush_in;
+ assign _01_ = ~ stall_in;
+ assign _02_ = _00_ | _01_;
+ assign _03_ = _02_ ? rin : r;
+ always @(posedge clk)
+ r <= _03_;
+ assign _04_ = r[117:112] == 6'h3d;
+ assign _05_ = _04_ ? 1'h0 : 1'h1;
+ assign _06_ = f_in[98:93] == 6'h1f;
+ assign _07_ = 10'h3ff - f_in[77:68];
+ assign _08_ = f_in[98:93] == 6'h13;
+ assign _09_ = 10'h3ff - f_in[77:68];
+ assign _10_ = ~ _86_;
+ assign _11_ = 3'h7 - { f_in[72], f_in[70:69] };
+ assign _12_ = _10_ ? 38'h2800000001 : _88_;
+ assign _13_ = f_in[98:93] == 6'h1e;
+ assign _14_ = 4'hf - f_in[71:68];
+ assign _15_ = f_in[98:93] == 6'h3a;
+ assign _16_ = 2'h3 - f_in[68:67];
+ assign _17_ = f_in[98:93] == 6'h3e;
+ assign _18_ = 2'h3 - f_in[68:67];
+ assign _19_ = f_in[98:67] & 32'd4294967295;
+ assign _20_ = _19_ == 32'd1610612736;
+ assign _21_ = 6'h3f - f_in[98:93];
+ assign _22_ = _20_ ? 38'h0000000005 : _96_;
+ assign _23_ = _17_ ? _94_ : _22_;
+ assign _24_ = _15_ ? _92_ : _23_;
+ assign _25_ = _13_ ? _90_ : _24_;
+ assign _26_ = _08_ ? _12_ : _25_;
+ assign _27_ = _06_ ? _84_ : _26_;
+ assign _28_ = f_in[2] ? _05_ : f_in[0];
+ assign _29_ = f_in[2] ? 38'h00000000f6 : _27_;
+ assign _30_ = _29_[7:2] == 6'h06;
+ assign _31_ = _29_[7:2] == 6'h07;
+ assign _32_ = _30_ | _31_;
+ assign _33_ = ~ f_in[90];
+ assign _34_ = _33_ ? 6'h21 : 6'h00;
+ assign _35_ = _29_[7:2] == 6'h07;
+ assign _36_ = ~ f_in[77];
+ assign _37_ = _36_ ? 6'h20 : 6'h21;
+ assign _38_ = _35_ ? _37_ : 6'h00;
+ assign _39_ = _29_[7:2] == 6'h26;
+ assign _40_ = _29_[7:2] == 6'h2a;
+ assign _41_ = _39_ | _40_;
+ assign _42_ = { f_in[82:78], f_in[87:83] } == 10'h008;
+ assign _43_ = { f_in[82:78], f_in[87:83] } == 10'h009;
+ assign _44_ = { f_in[82:78], f_in[87:83] } == 10'h01a;
+ assign _45_ = { f_in[82:78], f_in[87:83] } == 10'h01b;
+ assign _46_ = { f_in[82:78], f_in[87:83] } == 10'h13a;
+ assign _47_ = { f_in[82:78], f_in[87:83] } == 10'h13b;
+ assign _48_ = { f_in[82:78], f_in[87:83] } == 10'h110;
+ assign _49_ = { f_in[82:78], f_in[87:83] } == 10'h111;
+ assign _50_ = { f_in[82:78], f_in[87:83] } == 10'h112;
+ assign _51_ = { f_in[82:78], f_in[87:83] } == 10'h113;
+ assign _52_ = { f_in[82:78], f_in[87:83] } == 10'h103;
+ assign _53_ = _51_ | _52_;
+ assign _54_ = { f_in[82:78], f_in[87:83] } == 10'h130;
+ assign _55_ = { f_in[82:78], f_in[87:83] } == 10'h131;
+ assign _56_ = { f_in[82:78], f_in[87:83] } == 10'h001;
+ function [0:0] \3398 ;
+ input [0:0] a;
+ input [12:0] b;
+ input [12:0] s;
+ (* parallel_case *)
+ casez (s)
+ 13'b????????????1:
+ \3398 = b[0:0];
+ 13'b???????????1?:
+ \3398 = b[1:1];
+ 13'b??????????1??:
+ \3398 = b[2:2];
+ 13'b?????????1???:
+ \3398 = b[3:3];
+ 13'b????????1????:
+ \3398 = b[4:4];
+ 13'b???????1?????:
+ \3398 = b[5:5];
+ 13'b??????1??????:
+ \3398 = b[6:6];
+ 13'b?????1???????:
+ \3398 = b[7:7];
+ 13'b????1????????:
+ \3398 = b[8:8];
+ 13'b???1?????????:
+ \3398 = b[9:9];
+ 13'b??1??????????:
+ \3398 = b[10:10];
+ 13'b?1???????????:
+ \3398 = b[11:11];
+ 13'b1????????????:
+ \3398 = b[12:12];
+ default:
+ \3398 = a;
+ endcase
+ endfunction
+ assign _57_ = \3398 (1'h0, 13'h1fff, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
+ function [5:0] \3404 ;
+ input [5:0] a;
+ input [77:0] b;
+ input [12:0] s;
+ (* parallel_case *)
+ casez (s)
+ 13'b????????????1:
+ \3404 = b[5:0];
+ 13'b???????????1?:
+ \3404 = b[11:6];
+ 13'b??????????1??:
+ \3404 = b[17:12];
+ 13'b?????????1???:
+ \3404 = b[23:18];
+ 13'b????????1????:
+ \3404 = b[29:24];
+ 13'b???????1?????:
+ \3404 = b[35:30];
+ 13'b??????1??????:
+ \3404 = b[41:36];
+ 13'b?????1???????:
+ \3404 = b[47:42];
+ 13'b????1????????:
+ \3404 = b[53:48];
+ 13'b???1?????????:
+ \3404 = b[59:54];
+ 13'b??1??????????:
+ \3404 = b[65:60];
+ 13'b?1???????????:
+ \3404 = b[71:66];
+ 13'b1????????????:
+ \3404 = b[77:72];
+ default:
+ \3404 = a;
+ endcase
+ endfunction
+ assign _58_ = \3404 (6'h00, 78'hxxxxxxxxxxxxxxxxxxxx, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
+ function [4:0] \3419 ;
+ input [4:0] a;
+ input [64:0] b;
+ input [12:0] s;
+ (* parallel_case *)
+ casez (s)
+ 13'b????????????1:
+ \3419 = b[4:0];
+ 13'b???????????1?:
+ \3419 = b[9:5];
+ 13'b??????????1??:
+ \3419 = b[14:10];
+ 13'b?????????1???:
+ \3419 = b[19:15];
+ 13'b????????1????:
+ \3419 = b[24:20];
+ 13'b???????1?????:
+ \3419 = b[29:25];
+ 13'b??????1??????:
+ \3419 = b[34:30];
+ 13'b?????1???????:
+ \3419 = b[39:35];
+ 13'b????1????????:
+ \3419 = b[44:40];
+ 13'b???1?????????:
+ \3419 = b[49:45];
+ 13'b??1??????????:
+ \3419 = b[54:50];
+ 13'b?1???????????:
+ \3419 = b[59:55];
+ 13'b1????????????:
+ \3419 = b[64:60];
+ default:
+ \3419 = a;
+ endcase
+ endfunction
+ assign _59_ = \3419 (5'h00, 65'h0c5a928398a418820, { _56_, _55_, _54_, _53_, _50_, _49_, _48_, _47_, _46_, _45_, _44_, _43_, _42_ });
+ assign _60_ = _57_ ? _59_ : 5'hxx;
+ assign _61_ = _57_ ? { 1'h1, _60_ } : _58_;
+ assign _62_ = ~ _61_[5];
+ assign _63_ = { f_in[82:78], f_in[87:83] } == 10'h013;
+ assign _64_ = { f_in[82:78], f_in[87:83] } == 10'h012;
+ assign _65_ = _63_ | _64_;
+ assign _66_ = { f_in[82:78], f_in[87:83] } == 10'h030;
+ assign _67_ = _65_ | _66_;
+ assign _68_ = { f_in[82:78], f_in[87:83] } == 10'h2d0;
+ assign _69_ = _67_ | _68_;
+ function [1:0] \3455 ;
+ input [1:0] a;
+ input [1:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \3455 = b[1:0];
+ default:
+ \3455 = a;
+ endcase
+ endfunction
+ assign _70_ = \3455 (_29_[1:0], 2'h2, _69_);
+ assign _71_ = _77_ ? _70_ : _29_[1:0];
+ assign _72_ = _78_ ? 1'h1 : _29_[37];
+ assign _73_ = _29_[7:2] == 6'h31;
+ assign _74_ = _73_ ? 12'h8e2 : 12'h000;
+ assign _75_ = _41_ ? _61_ : _74_[5:0];
+ assign _76_ = _41_ ? 6'h00 : _74_[11:6];
+ assign _77_ = _41_ & _62_;
+ assign _78_ = _41_ & _62_;
+ assign _79_ = _32_ ? { _38_, _34_ } : { _76_, _75_ };
+ assign _80_ = _32_ ? _29_[1:0] : _71_;
+ assign _81_ = _32_ ? _29_[37] : _72_;
+ assign _82_ = flush_in ? 1'h0 : _28_;
+ assign rin = rst ? 148'h0000000000000000000000000000000000000 : { _81_, _29_[36:2], _80_, _79_, f_in[98:3], f_in[1], _82_ };
+ reg [37:0] \3502 [1023:0];
+ initial begin
+ \3502 [0] = 38'h2800000001;
+ \3502 [1] = 38'h2800000001;
+ \3502 [2] = 38'h2800000001;
+ \3502 [3] = 38'h2800000001;
+ \3502 [4] = 38'h2800000001;
+ \3502 [5] = 38'h2800000001;
+ \3502 [6] = 38'h2800000001;
+ \3502 [7] = 38'h2800000001;
+ \3502 [8] = 38'h2800000001;
+ \3502 [9] = 38'h0000000a52;
+ \3502 [10] = 38'h0008008a7a;
+ \3502 [11] = 38'h2800000001;
+ \3502 [12] = 38'h2800000001;
+ \3502 [13] = 38'h2800000001;
+ \3502 [14] = 38'h2800000001;
+ \3502 [15] = 38'h2800000001;
+ \3502 [16] = 38'h0000050a6d;
+ \3502 [17] = 38'h2800000001;
+ \3502 [18] = 38'h2800000001;
+ \3502 [19] = 38'h2800000001;
+ \3502 [20] = 38'h0b00010955;
+ \3502 [21] = 38'h2800000001;
+ \3502 [22] = 38'h0a00010955;
+ \3502 [23] = 38'h2800000001;
+ \3502 [24] = 38'h2800000001;
+ \3502 [25] = 38'h2800000001;
+ \3502 [26] = 38'h2800000001;
+ \3502 [27] = 38'h2800000001;
+ \3502 [28] = 38'h2800000001;
+ \3502 [29] = 38'h2800000001;
+ \3502 [30] = 38'h2800000001;
+ \3502 [31] = 38'h2800000001;
+ \3502 [32] = 38'h2800000001;
+ \3502 [33] = 38'h2800000001;
+ \3502 [34] = 38'h2800000001;
+ \3502 [35] = 38'h2800000001;
+ \3502 [36] = 38'h2800000001;
+ \3502 [37] = 38'h080602805d;
+ \3502 [38] = 38'h2800000001;
+ \3502 [39] = 38'h2800000001;
+ \3502 [40] = 38'h2800000001;
+ \3502 [41] = 38'h2000000065;
+ \3502 [42] = 38'h0002008a7a;
+ \3502 [43] = 38'h2800000001;
+ \3502 [44] = 38'h2800000001;
+ \3502 [45] = 38'h2800000001;
+ \3502 [46] = 38'h2800000001;
+ \3502 [47] = 38'h2800000001;
+ \3502 [48] = 38'h0000050a6d;
+ \3502 [49] = 38'h2800000001;
+ \3502 [50] = 38'h2800000001;
+ \3502 [51] = 38'h2800000001;
+ \3502 [52] = 38'h0900010955;
+ \3502 [53] = 38'h2800000001;
+ \3502 [54] = 38'h0800010955;
+ \3502 [55] = 38'h2800000001;
+ \3502 [56] = 38'h2800000001;
+ \3502 [57] = 38'h2800000001;
+ \3502 [58] = 38'h2800000001;
+ \3502 [59] = 38'h2800000001;
+ \3502 [60] = 38'h2800000001;
+ \3502 [61] = 38'h2800000001;
+ \3502 [62] = 38'h2800000001;
+ \3502 [63] = 38'h2800000001;
+ \3502 [64] = 38'h2800000001;
+ \3502 [65] = 38'h2800000001;
+ \3502 [66] = 38'h2800000001;
+ \3502 [67] = 38'h2800000001;
+ \3502 [68] = 38'h2800000001;
+ \3502 [69] = 38'h080202805d;
+ \3502 [70] = 38'h2800000001;
+ \3502 [71] = 38'h2800000001;
+ \3502 [72] = 38'h2800000001;
+ \3502 [73] = 38'h2800000001;
+ \3502 [74] = 38'h0004008a7a;
+ \3502 [75] = 38'h2800000001;
+ \3502 [76] = 38'h2800000001;
+ \3502 [77] = 38'h2800000001;
+ \3502 [78] = 38'h2800000001;
+ \3502 [79] = 38'h2800000001;
+ \3502 [80] = 38'h0000050a6d;
+ \3502 [81] = 38'h2800000001;
+ \3502 [82] = 38'h2800000001;
+ \3502 [83] = 38'h2800000001;
+ \3502 [84] = 38'h0b00010959;
+ \3502 [85] = 38'h2800000001;
+ \3502 [86] = 38'h0a00010959;
+ \3502 [87] = 38'h2800000001;
+ \3502 [88] = 38'h2800000001;
+ \3502 [89] = 38'h2800000001;
+ \3502 [90] = 38'h2800000001;
+ \3502 [91] = 38'h2800000001;
+ \3502 [92] = 38'h2800000001;
+ \3502 [93] = 38'h2800000001;
+ \3502 [94] = 38'h2800000001;
+ \3502 [95] = 38'h2800000001;
+ \3502 [96] = 38'h2800000001;
+ \3502 [97] = 38'h2800000001;
+ \3502 [98] = 38'h2800000001;
+ \3502 [99] = 38'h2800000001;
+ \3502 [100] = 38'h2800000001;
+ \3502 [101] = 38'h080402805d;
+ \3502 [102] = 38'h2800000001;
+ \3502 [103] = 38'h2800000001;
+ \3502 [104] = 38'h2800000001;
+ \3502 [105] = 38'h0014008a7a;
+ \3502 [106] = 38'h0006008a7a;
+ \3502 [107] = 38'h2800000001;
+ \3502 [108] = 38'h2800000001;
+ \3502 [109] = 38'h2800000001;
+ \3502 [110] = 38'h2800000001;
+ \3502 [111] = 38'h2800000001;
+ \3502 [112] = 38'h0000050a6d;
+ \3502 [113] = 38'h2800000001;
+ \3502 [114] = 38'h2800000001;
+ \3502 [115] = 38'h2800000001;
+ \3502 [116] = 38'h0900010959;
+ \3502 [117] = 38'h2800000001;
+ \3502 [118] = 38'h0800010959;
+ \3502 [119] = 38'h2800000001;
+ \3502 [120] = 38'h2800000001;
+ \3502 [121] = 38'h2800000001;
+ \3502 [122] = 38'h2800000001;
+ \3502 [123] = 38'h2800000001;
+ \3502 [124] = 38'h2800000001;
+ \3502 [125] = 38'h2800000001;
+ \3502 [126] = 38'h2800000001;
+ \3502 [127] = 38'h2800000001;
+ \3502 [128] = 38'h2800000001;
+ \3502 [129] = 38'h2800000001;
+ \3502 [130] = 38'h2800000001;
+ \3502 [131] = 38'h2800000001;
+ \3502 [132] = 38'h080002d861;
+ \3502 [133] = 38'h080002d861;
+ \3502 [134] = 38'h2800000001;
+ \3502 [135] = 38'h2800000001;
+ \3502 [136] = 38'h2800000001;
+ \3502 [137] = 38'h2800000001;
+ \3502 [138] = 38'h0008010a76;
+ \3502 [139] = 38'h2800000001;
+ \3502 [140] = 38'h2800000001;
+ \3502 [141] = 38'h2800000001;
+ \3502 [142] = 38'h2800000001;
+ \3502 [143] = 38'h2800000001;
+ \3502 [144] = 38'h0000050a6d;
+ \3502 [145] = 38'h2800000001;
+ \3502 [146] = 38'h2800000001;
+ \3502 [147] = 38'h2800000001;
+ \3502 [148] = 38'h2800000001;
+ \3502 [149] = 38'h2800000001;
+ \3502 [150] = 38'h2800000001;
+ \3502 [151] = 38'h2800000001;
+ \3502 [152] = 38'h2800000001;
+ \3502 [153] = 38'h2800000001;
+ \3502 [154] = 38'h2800000001;
+ \3502 [155] = 38'h2800000001;
+ \3502 [156] = 38'h2800000001;
+ \3502 [157] = 38'h2800000001;
+ \3502 [158] = 38'h2800000001;
+ \3502 [159] = 38'h2800000001;
+ \3502 [160] = 38'h2800000001;
+ \3502 [161] = 38'h2800000001;
+ \3502 [162] = 38'h2800000001;
+ \3502 [163] = 38'h2800000001;
+ \3502 [164] = 38'h2800000001;
+ \3502 [165] = 38'h2800000001;
+ \3502 [166] = 38'h2800000001;
+ \3502 [167] = 38'h2800000001;
+ \3502 [168] = 38'h2800000001;
+ \3502 [169] = 38'h2000000005;
+ \3502 [170] = 38'h0002010a76;
+ \3502 [171] = 38'h2800000001;
+ \3502 [172] = 38'h2800000001;
+ \3502 [173] = 38'h2800000001;
+ \3502 [174] = 38'h2800000001;
+ \3502 [175] = 38'h2800000001;
+ \3502 [176] = 38'h0000050a6d;
+ \3502 [177] = 38'h2800000001;
+ \3502 [178] = 38'h2800000001;
+ \3502 [179] = 38'h2800000001;
+ \3502 [180] = 38'h2800000001;
+ \3502 [181] = 38'h2800000001;
+ \3502 [182] = 38'h2800000001;
+ \3502 [183] = 38'h2800000001;
+ \3502 [184] = 38'h2800000001;
+ \3502 [185] = 38'h2800000001;
+ \3502 [186] = 38'h2800000001;
+ \3502 [187] = 38'h2800000001;
+ \3502 [188] = 38'h2800000001;
+ \3502 [189] = 38'h2800000001;
+ \3502 [190] = 38'h2800000001;
+ \3502 [191] = 38'h2800000001;
+ \3502 [192] = 38'h2800000001;
+ \3502 [193] = 38'h2800000001;
+ \3502 [194] = 38'h2800000001;
+ \3502 [195] = 38'h2800000001;
+ \3502 [196] = 38'h0a0102d8e1;
+ \3502 [197] = 38'h0a0102d8e1;
+ \3502 [198] = 38'h2800000001;
+ \3502 [199] = 38'h0b0102e0e1;
+ \3502 [200] = 38'h2800000001;
+ \3502 [201] = 38'h2800000001;
+ \3502 [202] = 38'h0004010a76;
+ \3502 [203] = 38'h2800000001;
+ \3502 [204] = 38'h2800000001;
+ \3502 [205] = 38'h2800000001;
+ \3502 [206] = 38'h2800000001;
+ \3502 [207] = 38'h2800000001;
+ \3502 [208] = 38'h0000050a6d;
+ \3502 [209] = 38'h2800000001;
+ \3502 [210] = 38'h2800000001;
+ \3502 [211] = 38'h2800000001;
+ \3502 [212] = 38'h2800000001;
+ \3502 [213] = 38'h2800000001;
+ \3502 [214] = 38'h2800000001;
+ \3502 [215] = 38'h2800000001;
+ \3502 [216] = 38'h2800000001;
+ \3502 [217] = 38'h2800000001;
+ \3502 [218] = 38'h2800000001;
+ \3502 [219] = 38'h2800000001;
+ \3502 [220] = 38'h2800000001;
+ \3502 [221] = 38'h2800000001;
+ \3502 [222] = 38'h2800000001;
+ \3502 [223] = 38'h2800000001;
+ \3502 [224] = 38'h2800000001;
+ \3502 [225] = 38'h2800000001;
+ \3502 [226] = 38'h2800000001;
+ \3502 [227] = 38'h2800000001;
+ \3502 [228] = 38'h2800000001;
+ \3502 [229] = 38'h0a010288e1;
+ \3502 [230] = 38'h2800000001;
+ \3502 [231] = 38'h0b010288e1;
+ \3502 [232] = 38'h2800000001;
+ \3502 [233] = 38'h0014010a76;
+ \3502 [234] = 38'h0006010a76;
+ \3502 [235] = 38'h2800000001;
+ \3502 [236] = 38'h2800000001;
+ \3502 [237] = 38'h2800000001;
+ \3502 [238] = 38'h2800000001;
+ \3502 [239] = 38'h2800000001;
+ \3502 [240] = 38'h0000050a6d;
+ \3502 [241] = 38'h2800000001;
+ \3502 [242] = 38'h2800000001;
+ \3502 [243] = 38'h2800000001;
+ \3502 [244] = 38'h030001099d;
+ \3502 [245] = 38'h0800010909;
+ \3502 [246] = 38'h020001099d;
+ \3502 [247] = 38'h2800000001;
+ \3502 [248] = 38'h2800000001;
+ \3502 [249] = 38'h2800000001;
+ \3502 [250] = 38'h2800000001;
+ \3502 [251] = 38'h2800000001;
+ \3502 [252] = 38'h2800000001;
+ \3502 [253] = 38'h2800000001;
+ \3502 [254] = 38'h2800000001;
+ \3502 [255] = 38'h2800000001;
+ \3502 [256] = 38'h2800000001;
+ \3502 [257] = 38'h2800000001;
+ \3502 [258] = 38'h2800000001;
+ \3502 [259] = 38'h2800000001;
+ \3502 [260] = 38'h2800000001;
+ \3502 [261] = 38'h2800000001;
+ \3502 [262] = 38'h2800000001;
+ \3502 [263] = 38'h2800000001;
+ \3502 [264] = 38'h2800000001;
+ \3502 [265] = 38'h2800000001;
+ \3502 [266] = 38'h2800000001;
+ \3502 [267] = 38'h2800000001;
+ \3502 [268] = 38'h2800000001;
+ \3502 [269] = 38'h2800000001;
+ \3502 [270] = 38'h2800000001;
+ \3502 [271] = 38'h2800000001;
+ \3502 [272] = 38'h0000050a6d;
+ \3502 [273] = 38'h2800000001;
+ \3502 [274] = 38'h2800000001;
+ \3502 [275] = 38'h2800000001;
+ \3502 [276] = 38'h0b000909ad;
+ \3502 [277] = 38'h0801415109;
+ \3502 [278] = 38'h0a000909ad;
+ \3502 [279] = 38'h0801515109;
+ \3502 [280] = 38'h2800000001;
+ \3502 [281] = 38'h2800000001;
+ \3502 [282] = 38'h2800000001;
+ \3502 [283] = 38'h2800000001;
+ \3502 [284] = 38'h2800000001;
+ \3502 [285] = 38'h2800000001;
+ \3502 [286] = 38'h2800000001;
+ \3502 [287] = 38'h2800000001;
+ \3502 [288] = 38'h2800000001;
+ \3502 [289] = 38'h2800000001;
+ \3502 [290] = 38'h2800000001;
+ \3502 [291] = 38'h2800000001;
+ \3502 [292] = 38'h2800000001;
+ \3502 [293] = 38'h2800000001;
+ \3502 [294] = 38'h2800000001;
+ \3502 [295] = 38'h2800000001;
+ \3502 [296] = 38'h2800000001;
+ \3502 [297] = 38'h0484008a7a;
+ \3502 [298] = 38'h2800000001;
+ \3502 [299] = 38'h2800000001;
+ \3502 [300] = 38'h2800000001;
+ \3502 [301] = 38'h2800000001;
+ \3502 [302] = 38'h2800000001;
+ \3502 [303] = 38'h2800000001;
+ \3502 [304] = 38'h0000050a6d;
+ \3502 [305] = 38'h2800000001;
+ \3502 [306] = 38'h2800000001;
+ \3502 [307] = 38'h2800000001;
+ \3502 [308] = 38'h2800000001;
+ \3502 [309] = 38'h0801410109;
+ \3502 [310] = 38'h2800000001;
+ \3502 [311] = 38'h0801510109;
+ \3502 [312] = 38'h2800000001;
+ \3502 [313] = 38'h2800000001;
+ \3502 [314] = 38'h2800000001;
+ \3502 [315] = 38'h2800000001;
+ \3502 [316] = 38'h2800000001;
+ \3502 [317] = 38'h2800000001;
+ \3502 [318] = 38'h2800000001;
+ \3502 [319] = 38'h2800000001;
+ \3502 [320] = 38'h2800000001;
+ \3502 [321] = 38'h2800000001;
+ \3502 [322] = 38'h2800000001;
+ \3502 [323] = 38'h2800000001;
+ \3502 [324] = 38'h2800000001;
+ \3502 [325] = 38'h2800000001;
+ \3502 [326] = 38'h2800000001;
+ \3502 [327] = 38'h2800000001;
+ \3502 [328] = 38'h2800000001;
+ \3502 [329] = 38'h0482008a7a;
+ \3502 [330] = 38'h2800000001;
+ \3502 [331] = 38'h2800000001;
+ \3502 [332] = 38'h2800000001;
+ \3502 [333] = 38'h2800000001;
+ \3502 [334] = 38'h2800000001;
+ \3502 [335] = 38'h2800000001;
+ \3502 [336] = 38'h0000050a6d;
+ \3502 [337] = 38'h2800000001;
+ \3502 [338] = 38'h2800000001;
+ \3502 [339] = 38'h2800000001;
+ \3502 [340] = 38'h2800000001;
+ \3502 [341] = 38'h2800000001;
+ \3502 [342] = 38'h2800000001;
+ \3502 [343] = 38'h2800000001;
+ \3502 [344] = 38'h2800000001;
+ \3502 [345] = 38'h2800000001;
+ \3502 [346] = 38'h2800000001;
+ \3502 [347] = 38'h2800000001;
+ \3502 [348] = 38'h2800000001;
+ \3502 [349] = 38'h2800000001;
+ \3502 [350] = 38'h2800000001;
+ \3502 [351] = 38'h2800000001;
+ \3502 [352] = 38'h2800000001;
+ \3502 [353] = 38'h2800000001;
+ \3502 [354] = 38'h2800000001;
+ \3502 [355] = 38'h2800000001;
+ \3502 [356] = 38'h2800000001;
+ \3502 [357] = 38'h2800000001;
+ \3502 [358] = 38'h2800000001;
+ \3502 [359] = 38'h2800000001;
+ \3502 [360] = 38'h2800000001;
+ \3502 [361] = 38'h0016008a7a;
+ \3502 [362] = 38'h2800000001;
+ \3502 [363] = 38'h0018008a7a;
+ \3502 [364] = 38'h2800000001;
+ \3502 [365] = 38'h2800000001;
+ \3502 [366] = 38'h2800000001;
+ \3502 [367] = 38'h2800000001;
+ \3502 [368] = 38'h0000050a6d;
+ \3502 [369] = 38'h2800000001;
+ \3502 [370] = 38'h2800000001;
+ \3502 [371] = 38'h2800000001;
+ \3502 [372] = 38'h2800000001;
+ \3502 [373] = 38'h0801410909;
+ \3502 [374] = 38'h2800000001;
+ \3502 [375] = 38'h0801510909;
+ \3502 [376] = 38'h2800000001;
+ \3502 [377] = 38'h2800000001;
+ \3502 [378] = 38'h2800000001;
+ \3502 [379] = 38'h2800000001;
+ \3502 [380] = 38'h2800000001;
+ \3502 [381] = 38'h2800000001;
+ \3502 [382] = 38'h2800000001;
+ \3502 [383] = 38'h2800000001;
+ \3502 [384] = 38'h2800000001;
+ \3502 [385] = 38'h2800000001;
+ \3502 [386] = 38'h2800000001;
+ \3502 [387] = 38'h2800000001;
+ \3502 [388] = 38'h2800000001;
+ \3502 [389] = 38'h2800000001;
+ \3502 [390] = 38'h2800000001;
+ \3502 [391] = 38'h2800000001;
+ \3502 [392] = 38'h2800000001;
+ \3502 [393] = 38'h2800000001;
+ \3502 [394] = 38'h2800000001;
+ \3502 [395] = 38'h2800000001;
+ \3502 [396] = 38'h2800000001;
+ \3502 [397] = 38'h2800000001;
+ \3502 [398] = 38'h2800000001;
+ \3502 [399] = 38'h2800000001;
+ \3502 [400] = 38'h0000050a6d;
+ \3502 [401] = 38'h2800000001;
+ \3502 [402] = 38'h2800000001;
+ \3502 [403] = 38'h2800000001;
+ \3502 [404] = 38'h2800000001;
+ \3502 [405] = 38'h2800000001;
+ \3502 [406] = 38'h2800000001;
+ \3502 [407] = 38'h0800910109;
+ \3502 [408] = 38'h2800000001;
+ \3502 [409] = 38'h2800000001;
+ \3502 [410] = 38'h2800000001;
+ \3502 [411] = 38'h2800000001;
+ \3502 [412] = 38'h2800000001;
+ \3502 [413] = 38'h2800000001;
+ \3502 [414] = 38'h2800000001;
+ \3502 [415] = 38'h2800000001;
+ \3502 [416] = 38'h2800000001;
+ \3502 [417] = 38'h2800000001;
+ \3502 [418] = 38'h2800000001;
+ \3502 [419] = 38'h2800000001;
+ \3502 [420] = 38'h2800000001;
+ \3502 [421] = 38'h2800000001;
+ \3502 [422] = 38'h2800000001;
+ \3502 [423] = 38'h2800000001;
+ \3502 [424] = 38'h2800000001;
+ \3502 [425] = 38'h2000000005;
+ \3502 [426] = 38'h2800000001;
+ \3502 [427] = 38'h2800000001;
+ \3502 [428] = 38'h2800000001;
+ \3502 [429] = 38'h2800000001;
+ \3502 [430] = 38'h2800000001;
+ \3502 [431] = 38'h2800000001;
+ \3502 [432] = 38'h0000050a6d;
+ \3502 [433] = 38'h2800000001;
+ \3502 [434] = 38'h2800000001;
+ \3502 [435] = 38'h2800000001;
+ \3502 [436] = 38'h0b000909b5;
+ \3502 [437] = 38'h2800000001;
+ \3502 [438] = 38'h0a000909b1;
+ \3502 [439] = 38'h2800000001;
+ \3502 [440] = 38'h2800000001;
+ \3502 [441] = 38'h2800000001;
+ \3502 [442] = 38'h2800000001;
+ \3502 [443] = 38'h2800000001;
+ \3502 [444] = 38'h2800000001;
+ \3502 [445] = 38'h2800000001;
+ \3502 [446] = 38'h2800000001;
+ \3502 [447] = 38'h2800000001;
+ \3502 [448] = 38'h2800000001;
+ \3502 [449] = 38'h2800000001;
+ \3502 [450] = 38'h2800000001;
+ \3502 [451] = 38'h2800000001;
+ \3502 [452] = 38'h2800000001;
+ \3502 [453] = 38'h0800028035;
+ \3502 [454] = 38'h2800000001;
+ \3502 [455] = 38'h2800000001;
+ \3502 [456] = 38'h2800000001;
+ \3502 [457] = 38'h2800000001;
+ \3502 [458] = 38'h2800000001;
+ \3502 [459] = 38'h2800000001;
+ \3502 [460] = 38'h2800000001;
+ \3502 [461] = 38'h2800000001;
+ \3502 [462] = 38'h2800000001;
+ \3502 [463] = 38'h2800000001;
+ \3502 [464] = 38'h0000050a6d;
+ \3502 [465] = 38'h2800000001;
+ \3502 [466] = 38'h2800000001;
+ \3502 [467] = 38'h2800000001;
+ \3502 [468] = 38'h2800000001;
+ \3502 [469] = 38'h2800000001;
+ \3502 [470] = 38'h2800000001;
+ \3502 [471] = 38'h0800910909;
+ \3502 [472] = 38'h2800000001;
+ \3502 [473] = 38'h2800000001;
+ \3502 [474] = 38'h2800000001;
+ \3502 [475] = 38'h2800000001;
+ \3502 [476] = 38'h2800000001;
+ \3502 [477] = 38'h2800000001;
+ \3502 [478] = 38'h2800000001;
+ \3502 [479] = 38'h2800000001;
+ \3502 [480] = 38'h2800000001;
+ \3502 [481] = 38'h2800000001;
+ \3502 [482] = 38'h2800000001;
+ \3502 [483] = 38'h2800000001;
+ \3502 [484] = 38'h08000288e1;
+ \3502 [485] = 38'h0900028035;
+ \3502 [486] = 38'h2800000001;
+ \3502 [487] = 38'h09000288e1;
+ \3502 [488] = 38'h2800000001;
+ \3502 [489] = 38'h0016010a76;
+ \3502 [490] = 38'h2800000001;
+ \3502 [491] = 38'h0018010a76;
+ \3502 [492] = 38'h2800000001;
+ \3502 [493] = 38'h2800000001;
+ \3502 [494] = 38'h2800000001;
+ \3502 [495] = 38'h2800000001;
+ \3502 [496] = 38'h0000050a6d;
+ \3502 [497] = 38'h2800000001;
+ \3502 [498] = 38'h2800000001;
+ \3502 [499] = 38'h2800000001;
+ \3502 [500] = 38'h09000909b5;
+ \3502 [501] = 38'h0801010909;
+ \3502 [502] = 38'h08000909b1;
+ \3502 [503] = 38'h0801910909;
+ \3502 [504] = 38'h2800000001;
+ \3502 [505] = 38'h2800000001;
+ \3502 [506] = 38'h2800000001;
+ \3502 [507] = 38'h2800000001;
+ \3502 [508] = 38'h2800000001;
+ \3502 [509] = 38'h2800000001;
+ \3502 [510] = 38'h2800000001;
+ \3502 [511] = 38'h2800000001;
+ \3502 [512] = 38'h2800000001;
+ \3502 [513] = 38'h2800000001;
+ \3502 [514] = 38'h2800000001;
+ \3502 [515] = 38'h00000a8829;
+ \3502 [516] = 38'h2800000001;
+ \3502 [517] = 38'h00080280bd;
+ \3502 [518] = 38'h2800000001;
+ \3502 [519] = 38'h2800000001;
+ \3502 [520] = 38'h2800000001;
+ \3502 [521] = 38'h2800000001;
+ \3502 [522] = 38'h2800000001;
+ \3502 [523] = 38'h2800000001;
+ \3502 [524] = 38'h2800000001;
+ \3502 [525] = 38'h00000000ea;
+ \3502 [526] = 38'h2800000001;
+ \3502 [527] = 38'h2800000001;
+ \3502 [528] = 38'h0000050a6d;
+ \3502 [529] = 38'h2800000001;
+ \3502 [530] = 38'h2800000001;
+ \3502 [531] = 38'h2800000001;
+ \3502 [532] = 38'h0b00010955;
+ \3502 [533] = 38'h2800000001;
+ \3502 [534] = 38'h0a00010955;
+ \3502 [535] = 38'h2800000001;
+ \3502 [536] = 38'h2800000001;
+ \3502 [537] = 38'h2800000001;
+ \3502 [538] = 38'h2800000001;
+ \3502 [539] = 38'h2800000001;
+ \3502 [540] = 38'h2800000001;
+ \3502 [541] = 38'h2800000001;
+ \3502 [542] = 38'h2800000001;
+ \3502 [543] = 38'h2800000001;
+ \3502 [544] = 38'h2800000001;
+ \3502 [545] = 38'h2800000001;
+ \3502 [546] = 38'h2800000001;
+ \3502 [547] = 38'h080022880d;
+ \3502 [548] = 38'h2800000001;
+ \3502 [549] = 38'h2800000001;
+ \3502 [550] = 38'h2800000001;
+ \3502 [551] = 38'h2800000001;
+ \3502 [552] = 38'h2800000001;
+ \3502 [553] = 38'h2800000001;
+ \3502 [554] = 38'h2800000001;
+ \3502 [555] = 38'h2800000001;
+ \3502 [556] = 38'h00000380a9;
+ \3502 [557] = 38'h2800000001;
+ \3502 [558] = 38'h2800000001;
+ \3502 [559] = 38'h2800000001;
+ \3502 [560] = 38'h0000050a6d;
+ \3502 [561] = 38'h2800000001;
+ \3502 [562] = 38'h2800000001;
+ \3502 [563] = 38'h2800000001;
+ \3502 [564] = 38'h0900010955;
+ \3502 [565] = 38'h2800000001;
+ \3502 [566] = 38'h0800010955;
+ \3502 [567] = 38'h2800000001;
+ \3502 [568] = 38'h2800000001;
+ \3502 [569] = 38'h2800000001;
+ \3502 [570] = 38'h2800000001;
+ \3502 [571] = 38'h2800000001;
+ \3502 [572] = 38'h2800000001;
+ \3502 [573] = 38'h2800000001;
+ \3502 [574] = 38'h2800000001;
+ \3502 [575] = 38'h2800000001;
+ \3502 [576] = 38'h2800000001;
+ \3502 [577] = 38'h2800000001;
+ \3502 [578] = 38'h2800000001;
+ \3502 [579] = 38'h08000288b9;
+ \3502 [580] = 38'h2800000001;
+ \3502 [581] = 38'h2800000001;
+ \3502 [582] = 38'h2800000001;
+ \3502 [583] = 38'h2800000001;
+ \3502 [584] = 38'h0044008a7a;
+ \3502 [585] = 38'h2800000001;
+ \3502 [586] = 38'h2800000001;
+ \3502 [587] = 38'h2800000001;
+ \3502 [588] = 38'h2800000001;
+ \3502 [589] = 38'h2800000001;
+ \3502 [590] = 38'h2800000001;
+ \3502 [591] = 38'h2800000001;
+ \3502 [592] = 38'h0000050a6d;
+ \3502 [593] = 38'h2800000001;
+ \3502 [594] = 38'h2800000001;
+ \3502 [595] = 38'h2800000001;
+ \3502 [596] = 38'h0b00010959;
+ \3502 [597] = 38'h2800000001;
+ \3502 [598] = 38'h0a00010959;
+ \3502 [599] = 38'h2800000001;
+ \3502 [600] = 38'h2800000001;
+ \3502 [601] = 38'h2800000001;
+ \3502 [602] = 38'h2800000001;
+ \3502 [603] = 38'h2800000001;
+ \3502 [604] = 38'h2800000001;
+ \3502 [605] = 38'h2800000001;
+ \3502 [606] = 38'h2800000001;
+ \3502 [607] = 38'h2800000001;
+ \3502 [608] = 38'h2800000001;
+ \3502 [609] = 38'h2800000001;
+ \3502 [610] = 38'h2800000001;
+ \3502 [611] = 38'h08001288b9;
+ \3502 [612] = 38'h2800000001;
+ \3502 [613] = 38'h2800000001;
+ \3502 [614] = 38'h2800000001;
+ \3502 [615] = 38'h2800000001;
+ \3502 [616] = 38'h0004008a7a;
+ \3502 [617] = 38'h2800000001;
+ \3502 [618] = 38'h2800000001;
+ \3502 [619] = 38'h2800000001;
+ \3502 [620] = 38'h2800000001;
+ \3502 [621] = 38'h2800000001;
+ \3502 [622] = 38'h2800000001;
+ \3502 [623] = 38'h2800000001;
+ \3502 [624] = 38'h0000050a6d;
+ \3502 [625] = 38'h2800000001;
+ \3502 [626] = 38'h2800000001;
+ \3502 [627] = 38'h2800000001;
+ \3502 [628] = 38'h0900010959;
+ \3502 [629] = 38'h2800000001;
+ \3502 [630] = 38'h0800010959;
+ \3502 [631] = 38'h2800000001;
+ \3502 [632] = 38'h2800000001;
+ \3502 [633] = 38'h2800000001;
+ \3502 [634] = 38'h2800000001;
+ \3502 [635] = 38'h2800000001;
+ \3502 [636] = 38'h2800000001;
+ \3502 [637] = 38'h2800000001;
+ \3502 [638] = 38'h2800000001;
+ \3502 [639] = 38'h2800000001;
+ \3502 [640] = 38'h2800000001;
+ \3502 [641] = 38'h2800000001;
+ \3502 [642] = 38'h2800000001;
+ \3502 [643] = 38'h2800000001;
+ \3502 [644] = 38'h2800000001;
+ \3502 [645] = 38'h00060280bd;
+ \3502 [646] = 38'h2800000001;
+ \3502 [647] = 38'h2800000001;
+ \3502 [648] = 38'h0064010a76;
+ \3502 [649] = 38'h2800000001;
+ \3502 [650] = 38'h0066010a76;
+ \3502 [651] = 38'h2800000001;
+ \3502 [652] = 38'h2800000001;
+ \3502 [653] = 38'h2800000001;
+ \3502 [654] = 38'h2800000001;
+ \3502 [655] = 38'h2800000001;
+ \3502 [656] = 38'h0000050a6d;
+ \3502 [657] = 38'h2800000001;
+ \3502 [658] = 38'h2800000001;
+ \3502 [659] = 38'h2800000001;
+ \3502 [660] = 38'h2800000001;
+ \3502 [661] = 38'h2800000001;
+ \3502 [662] = 38'h2800000001;
+ \3502 [663] = 38'h2800000001;
+ \3502 [664] = 38'h2800000001;
+ \3502 [665] = 38'h2800000001;
+ \3502 [666] = 38'h2800000001;
+ \3502 [667] = 38'h2800000001;
+ \3502 [668] = 38'h2800000001;
+ \3502 [669] = 38'h2800000001;
+ \3502 [670] = 38'h2800000001;
+ \3502 [671] = 38'h2800000001;
+ \3502 [672] = 38'h2800000001;
+ \3502 [673] = 38'h2800000001;
+ \3502 [674] = 38'h2800000001;
+ \3502 [675] = 38'h2800000001;
+ \3502 [676] = 38'h2800000001;
+ \3502 [677] = 38'h2800000001;
+ \3502 [678] = 38'h2800000001;
+ \3502 [679] = 38'h2800000001;
+ \3502 [680] = 38'h0024010a76;
+ \3502 [681] = 38'h2800000001;
+ \3502 [682] = 38'h0026010a76;
+ \3502 [683] = 38'h2800000001;
+ \3502 [684] = 38'h0000018399;
+ \3502 [685] = 38'h2800000001;
+ \3502 [686] = 38'h2800000001;
+ \3502 [687] = 38'h2800000001;
+ \3502 [688] = 38'h0000050a6d;
+ \3502 [689] = 38'h2800000001;
+ \3502 [690] = 38'h2800000001;
+ \3502 [691] = 38'h2800000001;
+ \3502 [692] = 38'h2800000001;
+ \3502 [693] = 38'h2800000001;
+ \3502 [694] = 38'h2800000001;
+ \3502 [695] = 38'h2800000001;
+ \3502 [696] = 38'h2800000001;
+ \3502 [697] = 38'h2800000001;
+ \3502 [698] = 38'h2800000001;
+ \3502 [699] = 38'h2800000001;
+ \3502 [700] = 38'h2800000001;
+ \3502 [701] = 38'h2800000001;
+ \3502 [702] = 38'h2800000001;
+ \3502 [703] = 38'h2800000001;
+ \3502 [704] = 38'h2800000001;
+ \3502 [705] = 38'h2800000001;
+ \3502 [706] = 38'h2800000001;
+ \3502 [707] = 38'h08000288f1;
+ \3502 [708] = 38'h2800000001;
+ \3502 [709] = 38'h2800000001;
+ \3502 [710] = 38'h2800000001;
+ \3502 [711] = 38'h2800000001;
+ \3502 [712] = 38'h0044010a76;
+ \3502 [713] = 38'h2800000001;
+ \3502 [714] = 38'h2800000001;
+ \3502 [715] = 38'h2800000001;
+ \3502 [716] = 38'h2800000001;
+ \3502 [717] = 38'h00000088ea;
+ \3502 [718] = 38'h2800000001;
+ \3502 [719] = 38'h2800000001;
+ \3502 [720] = 38'h0000050a6d;
+ \3502 [721] = 38'h2800000001;
+ \3502 [722] = 38'h2800000001;
+ \3502 [723] = 38'h2800000001;
+ \3502 [724] = 38'h2800000001;
+ \3502 [725] = 38'h2800000001;
+ \3502 [726] = 38'h2800000001;
+ \3502 [727] = 38'h2800000001;
+ \3502 [728] = 38'h2800000001;
+ \3502 [729] = 38'h2800000001;
+ \3502 [730] = 38'h2800000001;
+ \3502 [731] = 38'h2800000001;
+ \3502 [732] = 38'h2800000001;
+ \3502 [733] = 38'h2800000001;
+ \3502 [734] = 38'h2800000001;
+ \3502 [735] = 38'h2800000001;
+ \3502 [736] = 38'h2800000001;
+ \3502 [737] = 38'h2800000001;
+ \3502 [738] = 38'h2800000001;
+ \3502 [739] = 38'h08002288f1;
+ \3502 [740] = 38'h2800000001;
+ \3502 [741] = 38'h2800000001;
+ \3502 [742] = 38'h2800000001;
+ \3502 [743] = 38'h2800000001;
+ \3502 [744] = 38'h0004010a76;
+ \3502 [745] = 38'h2000000005;
+ \3502 [746] = 38'h2800000001;
+ \3502 [747] = 38'h2800000001;
+ \3502 [748] = 38'h2800000001;
+ \3502 [749] = 38'h00000088ea;
+ \3502 [750] = 38'h2800000001;
+ \3502 [751] = 38'h2800000001;
+ \3502 [752] = 38'h0000050a6d;
+ \3502 [753] = 38'h2800000001;
+ \3502 [754] = 38'h2800000001;
+ \3502 [755] = 38'h2800000001;
+ \3502 [756] = 38'h010001099d;
+ \3502 [757] = 38'h0800010909;
+ \3502 [758] = 38'h000001099d;
+ \3502 [759] = 38'h2800000001;
+ \3502 [760] = 38'h2800000001;
+ \3502 [761] = 38'h2800000001;
+ \3502 [762] = 38'h2800000001;
+ \3502 [763] = 38'h2800000001;
+ \3502 [764] = 38'h2800000001;
+ \3502 [765] = 38'h2800000001;
+ \3502 [766] = 38'h2800000001;
+ \3502 [767] = 38'h2800000001;
+ \3502 [768] = 38'h2800000001;
+ \3502 [769] = 38'h2800000001;
+ \3502 [770] = 38'h2800000001;
+ \3502 [771] = 38'h2800000001;
+ \3502 [772] = 38'h2800000001;
+ \3502 [773] = 38'h2800000001;
+ \3502 [774] = 38'h2800000001;
+ \3502 [775] = 38'h2800000001;
+ \3502 [776] = 38'h0042008a7a;
+ \3502 [777] = 38'h2000000005;
+ \3502 [778] = 38'h2800000001;
+ \3502 [779] = 38'h2800000001;
+ \3502 [780] = 38'h2800000001;
+ \3502 [781] = 38'h2800000001;
+ \3502 [782] = 38'h2800000001;
+ \3502 [783] = 38'h2800000001;
+ \3502 [784] = 38'h0000050a6d;
+ \3502 [785] = 38'h2800000001;
+ \3502 [786] = 38'h2800000001;
+ \3502 [787] = 38'h2800000001;
+ \3502 [788] = 38'h0b000909ad;
+ \3502 [789] = 38'h0801415109;
+ \3502 [790] = 38'h0a000909ad;
+ \3502 [791] = 38'h0801515109;
+ \3502 [792] = 38'h2800000001;
+ \3502 [793] = 38'h2800000001;
+ \3502 [794] = 38'h2800000001;
+ \3502 [795] = 38'h2800000001;
+ \3502 [796] = 38'h2800000001;
+ \3502 [797] = 38'h2800000001;
+ \3502 [798] = 38'h2800000001;
+ \3502 [799] = 38'h2800000001;
+ \3502 [800] = 38'h2800000001;
+ \3502 [801] = 38'h2800000001;
+ \3502 [802] = 38'h2800000001;
+ \3502 [803] = 38'h2800000001;
+ \3502 [804] = 38'h2800000001;
+ \3502 [805] = 38'h2800000001;
+ \3502 [806] = 38'h2800000001;
+ \3502 [807] = 38'h2800000001;
+ \3502 [808] = 38'h0002008a7a;
+ \3502 [809] = 38'h0488008a7a;
+ \3502 [810] = 38'h2800000001;
+ \3502 [811] = 38'h2800000001;
+ \3502 [812] = 38'h2800000001;
+ \3502 [813] = 38'h2800000001;
+ \3502 [814] = 38'h2800000001;
+ \3502 [815] = 38'h2800000001;
+ \3502 [816] = 38'h0000050a6d;
+ \3502 [817] = 38'h2800000001;
+ \3502 [818] = 38'h2800000001;
+ \3502 [819] = 38'h2800000001;
+ \3502 [820] = 38'h2800000001;
+ \3502 [821] = 38'h0801410109;
+ \3502 [822] = 38'h2800000001;
+ \3502 [823] = 38'h0801510109;
+ \3502 [824] = 38'h2800000001;
+ \3502 [825] = 38'h2800000001;
+ \3502 [826] = 38'h2800000001;
+ \3502 [827] = 38'h2800000001;
+ \3502 [828] = 38'h2800000001;
+ \3502 [829] = 38'h2800000001;
+ \3502 [830] = 38'h2800000001;
+ \3502 [831] = 38'h2800000001;
+ \3502 [832] = 38'h2800000001;
+ \3502 [833] = 38'h2800000001;
+ \3502 [834] = 38'h2800000001;
+ \3502 [835] = 38'h2800000001;
+ \3502 [836] = 38'h2800000001;
+ \3502 [837] = 38'h00080280c1;
+ \3502 [838] = 38'h2800000001;
+ \3502 [839] = 38'h2800000001;
+ \3502 [840] = 38'h0046008a7a;
+ \3502 [841] = 38'h2800000001;
+ \3502 [842] = 38'h0048008a7a;
+ \3502 [843] = 38'h2800000001;
+ \3502 [844] = 38'h2800000001;
+ \3502 [845] = 38'h20000080a5;
+ \3502 [846] = 38'h2800000001;
+ \3502 [847] = 38'h2800000001;
+ \3502 [848] = 38'h0000050a6d;
+ \3502 [849] = 38'h2800000001;
+ \3502 [850] = 38'h2800000001;
+ \3502 [851] = 38'h2800000001;
+ \3502 [852] = 38'h2800000001;
+ \3502 [853] = 38'h2800000001;
+ \3502 [854] = 38'h2800000001;
+ \3502 [855] = 38'h2800000001;
+ \3502 [856] = 38'h2800000001;
+ \3502 [857] = 38'h2800000001;
+ \3502 [858] = 38'h2800000001;
+ \3502 [859] = 38'h2800000001;
+ \3502 [860] = 38'h2800000001;
+ \3502 [861] = 38'h2800000001;
+ \3502 [862] = 38'h2800000001;
+ \3502 [863] = 38'h2800000001;
+ \3502 [864] = 38'h2800000001;
+ \3502 [865] = 38'h2800000001;
+ \3502 [866] = 38'h2800000001;
+ \3502 [867] = 38'h2800000001;
+ \3502 [868] = 38'h2800000001;
+ \3502 [869] = 38'h00060280c1;
+ \3502 [870] = 38'h2800000001;
+ \3502 [871] = 38'h2800000001;
+ \3502 [872] = 38'h0006008a7a;
+ \3502 [873] = 38'h0486008a7a;
+ \3502 [874] = 38'h0008008a7a;
+ \3502 [875] = 38'h2800000001;
+ \3502 [876] = 38'h2800000001;
+ \3502 [877] = 38'h2800000001;
+ \3502 [878] = 38'h2800000001;
+ \3502 [879] = 38'h00000880a1;
+ \3502 [880] = 38'h0000050a6d;
+ \3502 [881] = 38'h2800000001;
+ \3502 [882] = 38'h2800000001;
+ \3502 [883] = 38'h2800000001;
+ \3502 [884] = 38'h2800000001;
+ \3502 [885] = 38'h0801410909;
+ \3502 [886] = 38'h2800000001;
+ \3502 [887] = 38'h0801510909;
+ \3502 [888] = 38'h2800000001;
+ \3502 [889] = 38'h2800000001;
+ \3502 [890] = 38'h2800000001;
+ \3502 [891] = 38'h2800000001;
+ \3502 [892] = 38'h2800000001;
+ \3502 [893] = 38'h2800000001;
+ \3502 [894] = 38'h2800000001;
+ \3502 [895] = 38'h2800000001;
+ \3502 [896] = 38'h2800000001;
+ \3502 [897] = 38'h2800000001;
+ \3502 [898] = 38'h2800000001;
+ \3502 [899] = 38'h08002288b9;
+ \3502 [900] = 38'h2800000001;
+ \3502 [901] = 38'h00020280bd;
+ \3502 [902] = 38'h2800000001;
+ \3502 [903] = 38'h2800000001;
+ \3502 [904] = 38'h0042010a76;
+ \3502 [905] = 38'h2800000001;
+ \3502 [906] = 38'h2800000001;
+ \3502 [907] = 38'h0084010a76;
+ \3502 [908] = 38'h2800000001;
+ \3502 [909] = 38'h2800000001;
+ \3502 [910] = 38'h2800000001;
+ \3502 [911] = 38'h2800000001;
+ \3502 [912] = 38'h0000050a6d;
+ \3502 [913] = 38'h2800000001;
+ \3502 [914] = 38'h2800000001;
+ \3502 [915] = 38'h2800000001;
+ \3502 [916] = 38'h2800000001;
+ \3502 [917] = 38'h2800000001;
+ \3502 [918] = 38'h2800000001;
+ \3502 [919] = 38'h0800910109;
+ \3502 [920] = 38'h2800000001;
+ \3502 [921] = 38'h2800000001;
+ \3502 [922] = 38'h2800000001;
+ \3502 [923] = 38'h2800000001;
+ \3502 [924] = 38'h2800000001;
+ \3502 [925] = 38'h2800000001;
+ \3502 [926] = 38'h2800000001;
+ \3502 [927] = 38'h2800000001;
+ \3502 [928] = 38'h2800000001;
+ \3502 [929] = 38'h2800000001;
+ \3502 [930] = 38'h2800000001;
+ \3502 [931] = 38'h2800000001;
+ \3502 [932] = 38'h2800000001;
+ \3502 [933] = 38'h2800000001;
+ \3502 [934] = 38'h2800000001;
+ \3502 [935] = 38'h2800000001;
+ \3502 [936] = 38'h0002010a76;
+ \3502 [937] = 38'h2000000005;
+ \3502 [938] = 38'h2800000001;
+ \3502 [939] = 38'h0088010a76;
+ \3502 [940] = 38'h2000010095;
+ \3502 [941] = 38'h2800000001;
+ \3502 [942] = 38'h2800000001;
+ \3502 [943] = 38'h2800000001;
+ \3502 [944] = 38'h0000050a6d;
+ \3502 [945] = 38'h2800000001;
+ \3502 [946] = 38'h2800000001;
+ \3502 [947] = 38'h2800000001;
+ \3502 [948] = 38'h0b000909b5;
+ \3502 [949] = 38'h2800000001;
+ \3502 [950] = 38'h0a000909b1;
+ \3502 [951] = 38'h2800000001;
+ \3502 [952] = 38'h2800000001;
+ \3502 [953] = 38'h2800000001;
+ \3502 [954] = 38'h2800000001;
+ \3502 [955] = 38'h20000009ed;
+ \3502 [956] = 38'h2800000001;
+ \3502 [957] = 38'h2800000001;
+ \3502 [958] = 38'h2800000001;
+ \3502 [959] = 38'h2800000001;
+ \3502 [960] = 38'h2800000001;
+ \3502 [961] = 38'h2800000001;
+ \3502 [962] = 38'h2800000001;
+ \3502 [963] = 38'h080012880d;
+ \3502 [964] = 38'h2800000001;
+ \3502 [965] = 38'h0800028035;
+ \3502 [966] = 38'h2800000001;
+ \3502 [967] = 38'h2800000001;
+ \3502 [968] = 38'h0046010a76;
+ \3502 [969] = 38'h2000000005;
+ \3502 [970] = 38'h0048010a76;
+ \3502 [971] = 38'h0082010a76;
+ \3502 [972] = 38'h2800000001;
+ \3502 [973] = 38'h2800000001;
+ \3502 [974] = 38'h2800000001;
+ \3502 [975] = 38'h2800000001;
+ \3502 [976] = 38'h0000050a6d;
+ \3502 [977] = 38'h2800000001;
+ \3502 [978] = 38'h2800000001;
+ \3502 [979] = 38'h2800000001;
+ \3502 [980] = 38'h2800000001;
+ \3502 [981] = 38'h2800000001;
+ \3502 [982] = 38'h2800000001;
+ \3502 [983] = 38'h0800910909;
+ \3502 [984] = 38'h2800000001;
+ \3502 [985] = 38'h2800000001;
+ \3502 [986] = 38'h2800000001;
+ \3502 [987] = 38'h2800000001;
+ \3502 [988] = 38'h2800000001;
+ \3502 [989] = 38'h2800000001;
+ \3502 [990] = 38'h2800000001;
+ \3502 [991] = 38'h0000980925;
+ \3502 [992] = 38'h2800000001;
+ \3502 [993] = 38'h2800000001;
+ \3502 [994] = 38'h2800000001;
+ \3502 [995] = 38'h080002880d;
+ \3502 [996] = 38'h08000288dd;
+ \3502 [997] = 38'h0900028035;
+ \3502 [998] = 38'h2800000001;
+ \3502 [999] = 38'h09000288dd;
+ \3502 [1000] = 38'h0006010a76;
+ \3502 [1001] = 38'h2000000005;
+ \3502 [1002] = 38'h0008010a76;
+ \3502 [1003] = 38'h0086010a76;
+ \3502 [1004] = 38'h0000050091;
+ \3502 [1005] = 38'h2800000001;
+ \3502 [1006] = 38'h2800000001;
+ \3502 [1007] = 38'h2800000001;
+ \3502 [1008] = 38'h2000050a6d;
+ \3502 [1009] = 38'h2800000001;
+ \3502 [1010] = 38'h2800000001;
+ \3502 [1011] = 38'h2800000001;
+ \3502 [1012] = 38'h09000909b5;
+ \3502 [1013] = 38'h0801010909;
+ \3502 [1014] = 38'h08000909b1;
+ \3502 [1015] = 38'h0801910909;
+ \3502 [1016] = 38'h2800000001;
+ \3502 [1017] = 38'h2800000001;
+ \3502 [1018] = 38'h2800000001;
+ \3502 [1019] = 38'h21000009ed;
+ \3502 [1020] = 38'h2800000001;
+ \3502 [1021] = 38'h2800000001;
+ \3502 [1022] = 38'h2800000001;
+ \3502 [1023] = 38'h0200980925;
+ end
+ assign _84_ = \3502 [_07_];
+ reg [0:0] \3504 [1023:0];
+ initial begin
+ \3504 [0] = 1'h0;
+ \3504 [1] = 1'h0;
+ \3504 [2] = 1'h0;
+ \3504 [3] = 1'h0;
+ \3504 [4] = 1'h0;
+ \3504 [5] = 1'h0;
+ \3504 [6] = 1'h0;
+ \3504 [7] = 1'h0;
+ \3504 [8] = 1'h0;
+ \3504 [9] = 1'h0;
+ \3504 [10] = 1'h0;
+ \3504 [11] = 1'h0;
+ \3504 [12] = 1'h0;
+ \3504 [13] = 1'h0;
+ \3504 [14] = 1'h0;
+ \3504 [15] = 1'h0;
+ \3504 [16] = 1'h0;
+ \3504 [17] = 1'h0;
+ \3504 [18] = 1'h0;
+ \3504 [19] = 1'h0;
+ \3504 [20] = 1'h0;
+ \3504 [21] = 1'h0;
+ \3504 [22] = 1'h0;
+ \3504 [23] = 1'h0;
+ \3504 [24] = 1'h0;
+ \3504 [25] = 1'h0;
+ \3504 [26] = 1'h0;
+ \3504 [27] = 1'h0;
+ \3504 [28] = 1'h0;
+ \3504 [29] = 1'h1;
+ \3504 [30] = 1'h0;
+ \3504 [31] = 1'h0;
+ \3504 [32] = 1'h0;
+ \3504 [33] = 1'h0;
+ \3504 [34] = 1'h0;
+ \3504 [35] = 1'h0;
+ \3504 [36] = 1'h0;
+ \3504 [37] = 1'h0;
+ \3504 [38] = 1'h0;
+ \3504 [39] = 1'h0;
+ \3504 [40] = 1'h0;
+ \3504 [41] = 1'h0;
+ \3504 [42] = 1'h0;
+ \3504 [43] = 1'h0;
+ \3504 [44] = 1'h0;
+ \3504 [45] = 1'h0;
+ \3504 [46] = 1'h0;
+ \3504 [47] = 1'h0;
+ \3504 [48] = 1'h0;
+ \3504 [49] = 1'h0;
+ \3504 [50] = 1'h0;
+ \3504 [51] = 1'h0;
+ \3504 [52] = 1'h0;
+ \3504 [53] = 1'h0;
+ \3504 [54] = 1'h0;
+ \3504 [55] = 1'h0;
+ \3504 [56] = 1'h0;
+ \3504 [57] = 1'h0;
+ \3504 [58] = 1'h0;
+ \3504 [59] = 1'h0;
+ \3504 [60] = 1'h0;
+ \3504 [61] = 1'h1;
+ \3504 [62] = 1'h0;
+ \3504 [63] = 1'h0;
+ \3504 [64] = 1'h0;
+ \3504 [65] = 1'h0;
+ \3504 [66] = 1'h0;
+ \3504 [67] = 1'h0;
+ \3504 [68] = 1'h0;
+ \3504 [69] = 1'h0;
+ \3504 [70] = 1'h0;
+ \3504 [71] = 1'h0;
+ \3504 [72] = 1'h0;
+ \3504 [73] = 1'h0;
+ \3504 [74] = 1'h0;
+ \3504 [75] = 1'h0;
+ \3504 [76] = 1'h0;
+ \3504 [77] = 1'h0;
+ \3504 [78] = 1'h0;
+ \3504 [79] = 1'h0;
+ \3504 [80] = 1'h0;
+ \3504 [81] = 1'h0;
+ \3504 [82] = 1'h0;
+ \3504 [83] = 1'h0;
+ \3504 [84] = 1'h0;
+ \3504 [85] = 1'h0;
+ \3504 [86] = 1'h0;
+ \3504 [87] = 1'h0;
+ \3504 [88] = 1'h0;
+ \3504 [89] = 1'h0;
+ \3504 [90] = 1'h0;
+ \3504 [91] = 1'h0;
+ \3504 [92] = 1'h0;
+ \3504 [93] = 1'h1;
+ \3504 [94] = 1'h0;
+ \3504 [95] = 1'h0;
+ \3504 [96] = 1'h0;
+ \3504 [97] = 1'h0;
+ \3504 [98] = 1'h0;
+ \3504 [99] = 1'h0;
+ \3504 [100] = 1'h0;
+ \3504 [101] = 1'h0;
+ \3504 [102] = 1'h0;
+ \3504 [103] = 1'h0;
+ \3504 [104] = 1'h0;
+ \3504 [105] = 1'h0;
+ \3504 [106] = 1'h0;
+ \3504 [107] = 1'h0;
+ \3504 [108] = 1'h0;
+ \3504 [109] = 1'h0;
+ \3504 [110] = 1'h0;
+ \3504 [111] = 1'h0;
+ \3504 [112] = 1'h0;
+ \3504 [113] = 1'h0;
+ \3504 [114] = 1'h0;
+ \3504 [115] = 1'h0;
+ \3504 [116] = 1'h0;
+ \3504 [117] = 1'h0;
+ \3504 [118] = 1'h0;
+ \3504 [119] = 1'h0;
+ \3504 [120] = 1'h0;
+ \3504 [121] = 1'h0;
+ \3504 [122] = 1'h0;
+ \3504 [123] = 1'h0;
+ \3504 [124] = 1'h0;
+ \3504 [125] = 1'h1;
+ \3504 [126] = 1'h0;
+ \3504 [127] = 1'h0;
+ \3504 [128] = 1'h0;
+ \3504 [129] = 1'h0;
+ \3504 [130] = 1'h0;
+ \3504 [131] = 1'h0;
+ \3504 [132] = 1'h0;
+ \3504 [133] = 1'h0;
+ \3504 [134] = 1'h0;
+ \3504 [135] = 1'h0;
+ \3504 [136] = 1'h0;
+ \3504 [137] = 1'h0;
+ \3504 [138] = 1'h0;
+ \3504 [139] = 1'h0;
+ \3504 [140] = 1'h0;
+ \3504 [141] = 1'h0;
+ \3504 [142] = 1'h0;
+ \3504 [143] = 1'h0;
+ \3504 [144] = 1'h0;
+ \3504 [145] = 1'h0;
+ \3504 [146] = 1'h0;
+ \3504 [147] = 1'h0;
+ \3504 [148] = 1'h0;
+ \3504 [149] = 1'h0;
+ \3504 [150] = 1'h0;
+ \3504 [151] = 1'h0;
+ \3504 [152] = 1'h0;
+ \3504 [153] = 1'h0;
+ \3504 [154] = 1'h0;
+ \3504 [155] = 1'h0;
+ \3504 [156] = 1'h0;
+ \3504 [157] = 1'h1;
+ \3504 [158] = 1'h0;
+ \3504 [159] = 1'h0;
+ \3504 [160] = 1'h0;
+ \3504 [161] = 1'h0;
+ \3504 [162] = 1'h0;
+ \3504 [163] = 1'h0;
+ \3504 [164] = 1'h0;
+ \3504 [165] = 1'h0;
+ \3504 [166] = 1'h0;
+ \3504 [167] = 1'h0;
+ \3504 [168] = 1'h0;
+ \3504 [169] = 1'h0;
+ \3504 [170] = 1'h0;
+ \3504 [171] = 1'h0;
+ \3504 [172] = 1'h0;
+ \3504 [173] = 1'h0;
+ \3504 [174] = 1'h0;
+ \3504 [175] = 1'h0;
+ \3504 [176] = 1'h0;
+ \3504 [177] = 1'h0;
+ \3504 [178] = 1'h0;
+ \3504 [179] = 1'h0;
+ \3504 [180] = 1'h0;
+ \3504 [181] = 1'h0;
+ \3504 [182] = 1'h0;
+ \3504 [183] = 1'h0;
+ \3504 [184] = 1'h0;
+ \3504 [185] = 1'h0;
+ \3504 [186] = 1'h0;
+ \3504 [187] = 1'h0;
+ \3504 [188] = 1'h0;
+ \3504 [189] = 1'h1;
+ \3504 [190] = 1'h0;
+ \3504 [191] = 1'h0;
+ \3504 [192] = 1'h0;
+ \3504 [193] = 1'h0;
+ \3504 [194] = 1'h0;
+ \3504 [195] = 1'h0;
+ \3504 [196] = 1'h0;
+ \3504 [197] = 1'h0;
+ \3504 [198] = 1'h0;
+ \3504 [199] = 1'h0;
+ \3504 [200] = 1'h0;
+ \3504 [201] = 1'h0;
+ \3504 [202] = 1'h0;
+ \3504 [203] = 1'h0;
+ \3504 [204] = 1'h0;
+ \3504 [205] = 1'h0;
+ \3504 [206] = 1'h0;
+ \3504 [207] = 1'h0;
+ \3504 [208] = 1'h0;
+ \3504 [209] = 1'h0;
+ \3504 [210] = 1'h0;
+ \3504 [211] = 1'h0;
+ \3504 [212] = 1'h0;
+ \3504 [213] = 1'h0;
+ \3504 [214] = 1'h0;
+ \3504 [215] = 1'h0;
+ \3504 [216] = 1'h0;
+ \3504 [217] = 1'h0;
+ \3504 [218] = 1'h0;
+ \3504 [219] = 1'h0;
+ \3504 [220] = 1'h0;
+ \3504 [221] = 1'h1;
+ \3504 [222] = 1'h0;
+ \3504 [223] = 1'h0;
+ \3504 [224] = 1'h0;
+ \3504 [225] = 1'h0;
+ \3504 [226] = 1'h0;
+ \3504 [227] = 1'h0;
+ \3504 [228] = 1'h0;
+ \3504 [229] = 1'h0;
+ \3504 [230] = 1'h0;
+ \3504 [231] = 1'h0;
+ \3504 [232] = 1'h0;
+ \3504 [233] = 1'h0;
+ \3504 [234] = 1'h0;
+ \3504 [235] = 1'h0;
+ \3504 [236] = 1'h0;
+ \3504 [237] = 1'h0;
+ \3504 [238] = 1'h0;
+ \3504 [239] = 1'h0;
+ \3504 [240] = 1'h0;
+ \3504 [241] = 1'h0;
+ \3504 [242] = 1'h0;
+ \3504 [243] = 1'h0;
+ \3504 [244] = 1'h0;
+ \3504 [245] = 1'h0;
+ \3504 [246] = 1'h0;
+ \3504 [247] = 1'h0;
+ \3504 [248] = 1'h0;
+ \3504 [249] = 1'h0;
+ \3504 [250] = 1'h0;
+ \3504 [251] = 1'h0;
+ \3504 [252] = 1'h0;
+ \3504 [253] = 1'h1;
+ \3504 [254] = 1'h0;
+ \3504 [255] = 1'h0;
+ \3504 [256] = 1'h0;
+ \3504 [257] = 1'h0;
+ \3504 [258] = 1'h0;
+ \3504 [259] = 1'h0;
+ \3504 [260] = 1'h0;
+ \3504 [261] = 1'h0;
+ \3504 [262] = 1'h0;
+ \3504 [263] = 1'h0;
+ \3504 [264] = 1'h0;
+ \3504 [265] = 1'h0;
+ \3504 [266] = 1'h0;
+ \3504 [267] = 1'h0;
+ \3504 [268] = 1'h0;
+ \3504 [269] = 1'h0;
+ \3504 [270] = 1'h0;
+ \3504 [271] = 1'h0;
+ \3504 [272] = 1'h0;
+ \3504 [273] = 1'h0;
+ \3504 [274] = 1'h0;
+ \3504 [275] = 1'h0;
+ \3504 [276] = 1'h0;
+ \3504 [277] = 1'h0;
+ \3504 [278] = 1'h0;
+ \3504 [279] = 1'h0;
+ \3504 [280] = 1'h0;
+ \3504 [281] = 1'h0;
+ \3504 [282] = 1'h0;
+ \3504 [283] = 1'h0;
+ \3504 [284] = 1'h0;
+ \3504 [285] = 1'h1;
+ \3504 [286] = 1'h0;
+ \3504 [287] = 1'h0;
+ \3504 [288] = 1'h0;
+ \3504 [289] = 1'h0;
+ \3504 [290] = 1'h0;
+ \3504 [291] = 1'h0;
+ \3504 [292] = 1'h0;
+ \3504 [293] = 1'h0;
+ \3504 [294] = 1'h0;
+ \3504 [295] = 1'h0;
+ \3504 [296] = 1'h0;
+ \3504 [297] = 1'h0;
+ \3504 [298] = 1'h0;
+ \3504 [299] = 1'h0;
+ \3504 [300] = 1'h0;
+ \3504 [301] = 1'h0;
+ \3504 [302] = 1'h0;
+ \3504 [303] = 1'h0;
+ \3504 [304] = 1'h0;
+ \3504 [305] = 1'h0;
+ \3504 [306] = 1'h0;
+ \3504 [307] = 1'h0;
+ \3504 [308] = 1'h0;
+ \3504 [309] = 1'h0;
+ \3504 [310] = 1'h0;
+ \3504 [311] = 1'h0;
+ \3504 [312] = 1'h0;
+ \3504 [313] = 1'h0;
+ \3504 [314] = 1'h0;
+ \3504 [315] = 1'h0;
+ \3504 [316] = 1'h0;
+ \3504 [317] = 1'h1;
+ \3504 [318] = 1'h0;
+ \3504 [319] = 1'h0;
+ \3504 [320] = 1'h0;
+ \3504 [321] = 1'h0;
+ \3504 [322] = 1'h0;
+ \3504 [323] = 1'h0;
+ \3504 [324] = 1'h0;
+ \3504 [325] = 1'h0;
+ \3504 [326] = 1'h0;
+ \3504 [327] = 1'h0;
+ \3504 [328] = 1'h0;
+ \3504 [329] = 1'h0;
+ \3504 [330] = 1'h0;
+ \3504 [331] = 1'h0;
+ \3504 [332] = 1'h0;
+ \3504 [333] = 1'h0;
+ \3504 [334] = 1'h0;
+ \3504 [335] = 1'h0;
+ \3504 [336] = 1'h0;
+ \3504 [337] = 1'h0;
+ \3504 [338] = 1'h0;
+ \3504 [339] = 1'h0;
+ \3504 [340] = 1'h0;
+ \3504 [341] = 1'h0;
+ \3504 [342] = 1'h0;
+ \3504 [343] = 1'h0;
+ \3504 [344] = 1'h0;
+ \3504 [345] = 1'h0;
+ \3504 [346] = 1'h0;
+ \3504 [347] = 1'h0;
+ \3504 [348] = 1'h0;
+ \3504 [349] = 1'h1;
+ \3504 [350] = 1'h0;
+ \3504 [351] = 1'h0;
+ \3504 [352] = 1'h0;
+ \3504 [353] = 1'h0;
+ \3504 [354] = 1'h0;
+ \3504 [355] = 1'h0;
+ \3504 [356] = 1'h0;
+ \3504 [357] = 1'h0;
+ \3504 [358] = 1'h0;
+ \3504 [359] = 1'h0;
+ \3504 [360] = 1'h0;
+ \3504 [361] = 1'h0;
+ \3504 [362] = 1'h0;
+ \3504 [363] = 1'h0;
+ \3504 [364] = 1'h0;
+ \3504 [365] = 1'h0;
+ \3504 [366] = 1'h0;
+ \3504 [367] = 1'h0;
+ \3504 [368] = 1'h0;
+ \3504 [369] = 1'h0;
+ \3504 [370] = 1'h0;
+ \3504 [371] = 1'h0;
+ \3504 [372] = 1'h0;
+ \3504 [373] = 1'h0;
+ \3504 [374] = 1'h0;
+ \3504 [375] = 1'h0;
+ \3504 [376] = 1'h0;
+ \3504 [377] = 1'h0;
+ \3504 [378] = 1'h0;
+ \3504 [379] = 1'h0;
+ \3504 [380] = 1'h0;
+ \3504 [381] = 1'h1;
+ \3504 [382] = 1'h0;
+ \3504 [383] = 1'h0;
+ \3504 [384] = 1'h0;
+ \3504 [385] = 1'h0;
+ \3504 [386] = 1'h0;
+ \3504 [387] = 1'h0;
+ \3504 [388] = 1'h0;
+ \3504 [389] = 1'h0;
+ \3504 [390] = 1'h0;
+ \3504 [391] = 1'h0;
+ \3504 [392] = 1'h0;
+ \3504 [393] = 1'h0;
+ \3504 [394] = 1'h0;
+ \3504 [395] = 1'h0;
+ \3504 [396] = 1'h0;
+ \3504 [397] = 1'h0;
+ \3504 [398] = 1'h0;
+ \3504 [399] = 1'h0;
+ \3504 [400] = 1'h0;
+ \3504 [401] = 1'h0;
+ \3504 [402] = 1'h0;
+ \3504 [403] = 1'h0;
+ \3504 [404] = 1'h0;
+ \3504 [405] = 1'h0;
+ \3504 [406] = 1'h0;
+ \3504 [407] = 1'h0;
+ \3504 [408] = 1'h0;
+ \3504 [409] = 1'h0;
+ \3504 [410] = 1'h0;
+ \3504 [411] = 1'h0;
+ \3504 [412] = 1'h0;
+ \3504 [413] = 1'h1;
+ \3504 [414] = 1'h0;
+ \3504 [415] = 1'h0;
+ \3504 [416] = 1'h0;
+ \3504 [417] = 1'h0;
+ \3504 [418] = 1'h0;
+ \3504 [419] = 1'h0;
+ \3504 [420] = 1'h0;
+ \3504 [421] = 1'h0;
+ \3504 [422] = 1'h0;
+ \3504 [423] = 1'h0;
+ \3504 [424] = 1'h0;
+ \3504 [425] = 1'h0;
+ \3504 [426] = 1'h0;
+ \3504 [427] = 1'h0;
+ \3504 [428] = 1'h0;
+ \3504 [429] = 1'h0;
+ \3504 [430] = 1'h0;
+ \3504 [431] = 1'h0;
+ \3504 [432] = 1'h0;
+ \3504 [433] = 1'h0;
+ \3504 [434] = 1'h0;
+ \3504 [435] = 1'h0;
+ \3504 [436] = 1'h0;
+ \3504 [437] = 1'h0;
+ \3504 [438] = 1'h0;
+ \3504 [439] = 1'h0;
+ \3504 [440] = 1'h0;
+ \3504 [441] = 1'h0;
+ \3504 [442] = 1'h0;
+ \3504 [443] = 1'h0;
+ \3504 [444] = 1'h0;
+ \3504 [445] = 1'h1;
+ \3504 [446] = 1'h0;
+ \3504 [447] = 1'h0;
+ \3504 [448] = 1'h0;
+ \3504 [449] = 1'h0;
+ \3504 [450] = 1'h0;
+ \3504 [451] = 1'h0;
+ \3504 [452] = 1'h0;
+ \3504 [453] = 1'h0;
+ \3504 [454] = 1'h0;
+ \3504 [455] = 1'h0;
+ \3504 [456] = 1'h0;
+ \3504 [457] = 1'h0;
+ \3504 [458] = 1'h0;
+ \3504 [459] = 1'h0;
+ \3504 [460] = 1'h0;
+ \3504 [461] = 1'h0;
+ \3504 [462] = 1'h0;
+ \3504 [463] = 1'h0;
+ \3504 [464] = 1'h0;
+ \3504 [465] = 1'h0;
+ \3504 [466] = 1'h0;
+ \3504 [467] = 1'h0;
+ \3504 [468] = 1'h0;
+ \3504 [469] = 1'h0;
+ \3504 [470] = 1'h0;
+ \3504 [471] = 1'h0;
+ \3504 [472] = 1'h0;
+ \3504 [473] = 1'h0;
+ \3504 [474] = 1'h0;
+ \3504 [475] = 1'h0;
+ \3504 [476] = 1'h0;
+ \3504 [477] = 1'h1;
+ \3504 [478] = 1'h0;
+ \3504 [479] = 1'h0;
+ \3504 [480] = 1'h0;
+ \3504 [481] = 1'h0;
+ \3504 [482] = 1'h0;
+ \3504 [483] = 1'h0;
+ \3504 [484] = 1'h0;
+ \3504 [485] = 1'h0;
+ \3504 [486] = 1'h0;
+ \3504 [487] = 1'h0;
+ \3504 [488] = 1'h0;
+ \3504 [489] = 1'h0;
+ \3504 [490] = 1'h0;
+ \3504 [491] = 1'h0;
+ \3504 [492] = 1'h0;
+ \3504 [493] = 1'h0;
+ \3504 [494] = 1'h0;
+ \3504 [495] = 1'h1;
+ \3504 [496] = 1'h0;
+ \3504 [497] = 1'h0;
+ \3504 [498] = 1'h0;
+ \3504 [499] = 1'h0;
+ \3504 [500] = 1'h0;
+ \3504 [501] = 1'h0;
+ \3504 [502] = 1'h0;
+ \3504 [503] = 1'h0;
+ \3504 [504] = 1'h0;
+ \3504 [505] = 1'h0;
+ \3504 [506] = 1'h0;
+ \3504 [507] = 1'h0;
+ \3504 [508] = 1'h0;
+ \3504 [509] = 1'h1;
+ \3504 [510] = 1'h0;
+ \3504 [511] = 1'h0;
+ \3504 [512] = 1'h0;
+ \3504 [513] = 1'h0;
+ \3504 [514] = 1'h0;
+ \3504 [515] = 1'h0;
+ \3504 [516] = 1'h0;
+ \3504 [517] = 1'h0;
+ \3504 [518] = 1'h0;
+ \3504 [519] = 1'h0;
+ \3504 [520] = 1'h0;
+ \3504 [521] = 1'h0;
+ \3504 [522] = 1'h0;
+ \3504 [523] = 1'h0;
+ \3504 [524] = 1'h0;
+ \3504 [525] = 1'h0;
+ \3504 [526] = 1'h0;
+ \3504 [527] = 1'h0;
+ \3504 [528] = 1'h0;
+ \3504 [529] = 1'h0;
+ \3504 [530] = 1'h0;
+ \3504 [531] = 1'h0;
+ \3504 [532] = 1'h0;
+ \3504 [533] = 1'h0;
+ \3504 [534] = 1'h0;
+ \3504 [535] = 1'h0;
+ \3504 [536] = 1'h0;
+ \3504 [537] = 1'h0;
+ \3504 [538] = 1'h0;
+ \3504 [539] = 1'h0;
+ \3504 [540] = 1'h0;
+ \3504 [541] = 1'h1;
+ \3504 [542] = 1'h0;
+ \3504 [543] = 1'h0;
+ \3504 [544] = 1'h0;
+ \3504 [545] = 1'h0;
+ \3504 [546] = 1'h0;
+ \3504 [547] = 1'h0;
+ \3504 [548] = 1'h0;
+ \3504 [549] = 1'h0;
+ \3504 [550] = 1'h0;
+ \3504 [551] = 1'h0;
+ \3504 [552] = 1'h0;
+ \3504 [553] = 1'h0;
+ \3504 [554] = 1'h0;
+ \3504 [555] = 1'h0;
+ \3504 [556] = 1'h0;
+ \3504 [557] = 1'h0;
+ \3504 [558] = 1'h0;
+ \3504 [559] = 1'h0;
+ \3504 [560] = 1'h0;
+ \3504 [561] = 1'h0;
+ \3504 [562] = 1'h0;
+ \3504 [563] = 1'h0;
+ \3504 [564] = 1'h0;
+ \3504 [565] = 1'h0;
+ \3504 [566] = 1'h0;
+ \3504 [567] = 1'h0;
+ \3504 [568] = 1'h0;
+ \3504 [569] = 1'h0;
+ \3504 [570] = 1'h0;
+ \3504 [571] = 1'h0;
+ \3504 [572] = 1'h0;
+ \3504 [573] = 1'h1;
+ \3504 [574] = 1'h1;
+ \3504 [575] = 1'h0;
+ \3504 [576] = 1'h0;
+ \3504 [577] = 1'h0;
+ \3504 [578] = 1'h0;
+ \3504 [579] = 1'h0;
+ \3504 [580] = 1'h0;
+ \3504 [581] = 1'h0;
+ \3504 [582] = 1'h0;
+ \3504 [583] = 1'h0;
+ \3504 [584] = 1'h0;
+ \3504 [585] = 1'h0;
+ \3504 [586] = 1'h0;
+ \3504 [587] = 1'h0;
+ \3504 [588] = 1'h0;
+ \3504 [589] = 1'h0;
+ \3504 [590] = 1'h0;
+ \3504 [591] = 1'h0;
+ \3504 [592] = 1'h0;
+ \3504 [593] = 1'h0;
+ \3504 [594] = 1'h0;
+ \3504 [595] = 1'h0;
+ \3504 [596] = 1'h0;
+ \3504 [597] = 1'h0;
+ \3504 [598] = 1'h0;
+ \3504 [599] = 1'h0;
+ \3504 [600] = 1'h0;
+ \3504 [601] = 1'h0;
+ \3504 [602] = 1'h0;
+ \3504 [603] = 1'h0;
+ \3504 [604] = 1'h0;
+ \3504 [605] = 1'h1;
+ \3504 [606] = 1'h1;
+ \3504 [607] = 1'h0;
+ \3504 [608] = 1'h0;
+ \3504 [609] = 1'h0;
+ \3504 [610] = 1'h0;
+ \3504 [611] = 1'h0;
+ \3504 [612] = 1'h0;
+ \3504 [613] = 1'h0;
+ \3504 [614] = 1'h0;
+ \3504 [615] = 1'h0;
+ \3504 [616] = 1'h0;
+ \3504 [617] = 1'h0;
+ \3504 [618] = 1'h0;
+ \3504 [619] = 1'h0;
+ \3504 [620] = 1'h0;
+ \3504 [621] = 1'h0;
+ \3504 [622] = 1'h0;
+ \3504 [623] = 1'h0;
+ \3504 [624] = 1'h0;
+ \3504 [625] = 1'h0;
+ \3504 [626] = 1'h0;
+ \3504 [627] = 1'h0;
+ \3504 [628] = 1'h0;
+ \3504 [629] = 1'h0;
+ \3504 [630] = 1'h0;
+ \3504 [631] = 1'h0;
+ \3504 [632] = 1'h0;
+ \3504 [633] = 1'h0;
+ \3504 [634] = 1'h0;
+ \3504 [635] = 1'h0;
+ \3504 [636] = 1'h0;
+ \3504 [637] = 1'h1;
+ \3504 [638] = 1'h0;
+ \3504 [639] = 1'h0;
+ \3504 [640] = 1'h0;
+ \3504 [641] = 1'h0;
+ \3504 [642] = 1'h0;
+ \3504 [643] = 1'h0;
+ \3504 [644] = 1'h0;
+ \3504 [645] = 1'h0;
+ \3504 [646] = 1'h0;
+ \3504 [647] = 1'h0;
+ \3504 [648] = 1'h0;
+ \3504 [649] = 1'h0;
+ \3504 [650] = 1'h0;
+ \3504 [651] = 1'h0;
+ \3504 [652] = 1'h0;
+ \3504 [653] = 1'h0;
+ \3504 [654] = 1'h0;
+ \3504 [655] = 1'h0;
+ \3504 [656] = 1'h0;
+ \3504 [657] = 1'h0;
+ \3504 [658] = 1'h0;
+ \3504 [659] = 1'h0;
+ \3504 [660] = 1'h0;
+ \3504 [661] = 1'h0;
+ \3504 [662] = 1'h0;
+ \3504 [663] = 1'h0;
+ \3504 [664] = 1'h0;
+ \3504 [665] = 1'h0;
+ \3504 [666] = 1'h0;
+ \3504 [667] = 1'h0;
+ \3504 [668] = 1'h0;
+ \3504 [669] = 1'h1;
+ \3504 [670] = 1'h0;
+ \3504 [671] = 1'h0;
+ \3504 [672] = 1'h0;
+ \3504 [673] = 1'h0;
+ \3504 [674] = 1'h0;
+ \3504 [675] = 1'h0;
+ \3504 [676] = 1'h0;
+ \3504 [677] = 1'h0;
+ \3504 [678] = 1'h0;
+ \3504 [679] = 1'h0;
+ \3504 [680] = 1'h0;
+ \3504 [681] = 1'h0;
+ \3504 [682] = 1'h0;
+ \3504 [683] = 1'h0;
+ \3504 [684] = 1'h0;
+ \3504 [685] = 1'h0;
+ \3504 [686] = 1'h0;
+ \3504 [687] = 1'h0;
+ \3504 [688] = 1'h0;
+ \3504 [689] = 1'h0;
+ \3504 [690] = 1'h0;
+ \3504 [691] = 1'h0;
+ \3504 [692] = 1'h0;
+ \3504 [693] = 1'h0;
+ \3504 [694] = 1'h0;
+ \3504 [695] = 1'h0;
+ \3504 [696] = 1'h0;
+ \3504 [697] = 1'h0;
+ \3504 [698] = 1'h0;
+ \3504 [699] = 1'h0;
+ \3504 [700] = 1'h0;
+ \3504 [701] = 1'h1;
+ \3504 [702] = 1'h0;
+ \3504 [703] = 1'h0;
+ \3504 [704] = 1'h0;
+ \3504 [705] = 1'h0;
+ \3504 [706] = 1'h0;
+ \3504 [707] = 1'h0;
+ \3504 [708] = 1'h0;
+ \3504 [709] = 1'h0;
+ \3504 [710] = 1'h0;
+ \3504 [711] = 1'h0;
+ \3504 [712] = 1'h0;
+ \3504 [713] = 1'h0;
+ \3504 [714] = 1'h0;
+ \3504 [715] = 1'h0;
+ \3504 [716] = 1'h0;
+ \3504 [717] = 1'h0;
+ \3504 [718] = 1'h0;
+ \3504 [719] = 1'h0;
+ \3504 [720] = 1'h0;
+ \3504 [721] = 1'h0;
+ \3504 [722] = 1'h0;
+ \3504 [723] = 1'h0;
+ \3504 [724] = 1'h0;
+ \3504 [725] = 1'h0;
+ \3504 [726] = 1'h0;
+ \3504 [727] = 1'h0;
+ \3504 [728] = 1'h0;
+ \3504 [729] = 1'h0;
+ \3504 [730] = 1'h0;
+ \3504 [731] = 1'h0;
+ \3504 [732] = 1'h0;
+ \3504 [733] = 1'h1;
+ \3504 [734] = 1'h1;
+ \3504 [735] = 1'h0;
+ \3504 [736] = 1'h0;
+ \3504 [737] = 1'h0;
+ \3504 [738] = 1'h0;
+ \3504 [739] = 1'h0;
+ \3504 [740] = 1'h0;
+ \3504 [741] = 1'h0;
+ \3504 [742] = 1'h0;
+ \3504 [743] = 1'h0;
+ \3504 [744] = 1'h0;
+ \3504 [745] = 1'h0;
+ \3504 [746] = 1'h0;
+ \3504 [747] = 1'h0;
+ \3504 [748] = 1'h0;
+ \3504 [749] = 1'h0;
+ \3504 [750] = 1'h0;
+ \3504 [751] = 1'h0;
+ \3504 [752] = 1'h0;
+ \3504 [753] = 1'h0;
+ \3504 [754] = 1'h0;
+ \3504 [755] = 1'h0;
+ \3504 [756] = 1'h0;
+ \3504 [757] = 1'h0;
+ \3504 [758] = 1'h0;
+ \3504 [759] = 1'h0;
+ \3504 [760] = 1'h0;
+ \3504 [761] = 1'h0;
+ \3504 [762] = 1'h0;
+ \3504 [763] = 1'h0;
+ \3504 [764] = 1'h0;
+ \3504 [765] = 1'h1;
+ \3504 [766] = 1'h1;
+ \3504 [767] = 1'h0;
+ \3504 [768] = 1'h0;
+ \3504 [769] = 1'h0;
+ \3504 [770] = 1'h0;
+ \3504 [771] = 1'h0;
+ \3504 [772] = 1'h0;
+ \3504 [773] = 1'h0;
+ \3504 [774] = 1'h0;
+ \3504 [775] = 1'h0;
+ \3504 [776] = 1'h0;
+ \3504 [777] = 1'h0;
+ \3504 [778] = 1'h0;
+ \3504 [779] = 1'h0;
+ \3504 [780] = 1'h0;
+ \3504 [781] = 1'h0;
+ \3504 [782] = 1'h0;
+ \3504 [783] = 1'h0;
+ \3504 [784] = 1'h0;
+ \3504 [785] = 1'h0;
+ \3504 [786] = 1'h0;
+ \3504 [787] = 1'h0;
+ \3504 [788] = 1'h0;
+ \3504 [789] = 1'h0;
+ \3504 [790] = 1'h0;
+ \3504 [791] = 1'h0;
+ \3504 [792] = 1'h0;
+ \3504 [793] = 1'h0;
+ \3504 [794] = 1'h0;
+ \3504 [795] = 1'h0;
+ \3504 [796] = 1'h0;
+ \3504 [797] = 1'h1;
+ \3504 [798] = 1'h1;
+ \3504 [799] = 1'h0;
+ \3504 [800] = 1'h0;
+ \3504 [801] = 1'h0;
+ \3504 [802] = 1'h0;
+ \3504 [803] = 1'h0;
+ \3504 [804] = 1'h0;
+ \3504 [805] = 1'h0;
+ \3504 [806] = 1'h0;
+ \3504 [807] = 1'h0;
+ \3504 [808] = 1'h0;
+ \3504 [809] = 1'h0;
+ \3504 [810] = 1'h0;
+ \3504 [811] = 1'h0;
+ \3504 [812] = 1'h0;
+ \3504 [813] = 1'h0;
+ \3504 [814] = 1'h0;
+ \3504 [815] = 1'h0;
+ \3504 [816] = 1'h0;
+ \3504 [817] = 1'h0;
+ \3504 [818] = 1'h0;
+ \3504 [819] = 1'h0;
+ \3504 [820] = 1'h0;
+ \3504 [821] = 1'h0;
+ \3504 [822] = 1'h0;
+ \3504 [823] = 1'h0;
+ \3504 [824] = 1'h0;
+ \3504 [825] = 1'h0;
+ \3504 [826] = 1'h0;
+ \3504 [827] = 1'h0;
+ \3504 [828] = 1'h0;
+ \3504 [829] = 1'h1;
+ \3504 [830] = 1'h1;
+ \3504 [831] = 1'h0;
+ \3504 [832] = 1'h0;
+ \3504 [833] = 1'h0;
+ \3504 [834] = 1'h0;
+ \3504 [835] = 1'h0;
+ \3504 [836] = 1'h0;
+ \3504 [837] = 1'h0;
+ \3504 [838] = 1'h0;
+ \3504 [839] = 1'h0;
+ \3504 [840] = 1'h0;
+ \3504 [841] = 1'h0;
+ \3504 [842] = 1'h0;
+ \3504 [843] = 1'h0;
+ \3504 [844] = 1'h0;
+ \3504 [845] = 1'h0;
+ \3504 [846] = 1'h0;
+ \3504 [847] = 1'h0;
+ \3504 [848] = 1'h0;
+ \3504 [849] = 1'h0;
+ \3504 [850] = 1'h0;
+ \3504 [851] = 1'h0;
+ \3504 [852] = 1'h0;
+ \3504 [853] = 1'h0;
+ \3504 [854] = 1'h0;
+ \3504 [855] = 1'h0;
+ \3504 [856] = 1'h0;
+ \3504 [857] = 1'h0;
+ \3504 [858] = 1'h0;
+ \3504 [859] = 1'h0;
+ \3504 [860] = 1'h0;
+ \3504 [861] = 1'h1;
+ \3504 [862] = 1'h0;
+ \3504 [863] = 1'h0;
+ \3504 [864] = 1'h0;
+ \3504 [865] = 1'h0;
+ \3504 [866] = 1'h0;
+ \3504 [867] = 1'h0;
+ \3504 [868] = 1'h0;
+ \3504 [869] = 1'h0;
+ \3504 [870] = 1'h0;
+ \3504 [871] = 1'h0;
+ \3504 [872] = 1'h0;
+ \3504 [873] = 1'h1;
+ \3504 [874] = 1'h0;
+ \3504 [875] = 1'h0;
+ \3504 [876] = 1'h0;
+ \3504 [877] = 1'h0;
+ \3504 [878] = 1'h0;
+ \3504 [879] = 1'h0;
+ \3504 [880] = 1'h0;
+ \3504 [881] = 1'h0;
+ \3504 [882] = 1'h0;
+ \3504 [883] = 1'h0;
+ \3504 [884] = 1'h0;
+ \3504 [885] = 1'h0;
+ \3504 [886] = 1'h0;
+ \3504 [887] = 1'h0;
+ \3504 [888] = 1'h0;
+ \3504 [889] = 1'h0;
+ \3504 [890] = 1'h0;
+ \3504 [891] = 1'h0;
+ \3504 [892] = 1'h0;
+ \3504 [893] = 1'h1;
+ \3504 [894] = 1'h1;
+ \3504 [895] = 1'h0;
+ \3504 [896] = 1'h0;
+ \3504 [897] = 1'h0;
+ \3504 [898] = 1'h0;
+ \3504 [899] = 1'h0;
+ \3504 [900] = 1'h0;
+ \3504 [901] = 1'h0;
+ \3504 [902] = 1'h0;
+ \3504 [903] = 1'h0;
+ \3504 [904] = 1'h0;
+ \3504 [905] = 1'h0;
+ \3504 [906] = 1'h0;
+ \3504 [907] = 1'h0;
+ \3504 [908] = 1'h0;
+ \3504 [909] = 1'h0;
+ \3504 [910] = 1'h0;
+ \3504 [911] = 1'h0;
+ \3504 [912] = 1'h0;
+ \3504 [913] = 1'h0;
+ \3504 [914] = 1'h0;
+ \3504 [915] = 1'h0;
+ \3504 [916] = 1'h0;
+ \3504 [917] = 1'h0;
+ \3504 [918] = 1'h0;
+ \3504 [919] = 1'h0;
+ \3504 [920] = 1'h0;
+ \3504 [921] = 1'h0;
+ \3504 [922] = 1'h0;
+ \3504 [923] = 1'h0;
+ \3504 [924] = 1'h0;
+ \3504 [925] = 1'h1;
+ \3504 [926] = 1'h0;
+ \3504 [927] = 1'h0;
+ \3504 [928] = 1'h0;
+ \3504 [929] = 1'h0;
+ \3504 [930] = 1'h0;
+ \3504 [931] = 1'h0;
+ \3504 [932] = 1'h0;
+ \3504 [933] = 1'h0;
+ \3504 [934] = 1'h0;
+ \3504 [935] = 1'h0;
+ \3504 [936] = 1'h0;
+ \3504 [937] = 1'h0;
+ \3504 [938] = 1'h0;
+ \3504 [939] = 1'h0;
+ \3504 [940] = 1'h0;
+ \3504 [941] = 1'h0;
+ \3504 [942] = 1'h0;
+ \3504 [943] = 1'h0;
+ \3504 [944] = 1'h0;
+ \3504 [945] = 1'h0;
+ \3504 [946] = 1'h0;
+ \3504 [947] = 1'h0;
+ \3504 [948] = 1'h0;
+ \3504 [949] = 1'h0;
+ \3504 [950] = 1'h0;
+ \3504 [951] = 1'h0;
+ \3504 [952] = 1'h0;
+ \3504 [953] = 1'h0;
+ \3504 [954] = 1'h0;
+ \3504 [955] = 1'h0;
+ \3504 [956] = 1'h0;
+ \3504 [957] = 1'h1;
+ \3504 [958] = 1'h0;
+ \3504 [959] = 1'h0;
+ \3504 [960] = 1'h0;
+ \3504 [961] = 1'h0;
+ \3504 [962] = 1'h0;
+ \3504 [963] = 1'h0;
+ \3504 [964] = 1'h0;
+ \3504 [965] = 1'h0;
+ \3504 [966] = 1'h0;
+ \3504 [967] = 1'h0;
+ \3504 [968] = 1'h0;
+ \3504 [969] = 1'h0;
+ \3504 [970] = 1'h0;
+ \3504 [971] = 1'h0;
+ \3504 [972] = 1'h0;
+ \3504 [973] = 1'h0;
+ \3504 [974] = 1'h0;
+ \3504 [975] = 1'h0;
+ \3504 [976] = 1'h0;
+ \3504 [977] = 1'h0;
+ \3504 [978] = 1'h0;
+ \3504 [979] = 1'h0;
+ \3504 [980] = 1'h0;
+ \3504 [981] = 1'h0;
+ \3504 [982] = 1'h0;
+ \3504 [983] = 1'h0;
+ \3504 [984] = 1'h0;
+ \3504 [985] = 1'h0;
+ \3504 [986] = 1'h0;
+ \3504 [987] = 1'h0;
+ \3504 [988] = 1'h0;
+ \3504 [989] = 1'h1;
+ \3504 [990] = 1'h1;
+ \3504 [991] = 1'h0;
+ \3504 [992] = 1'h0;
+ \3504 [993] = 1'h0;
+ \3504 [994] = 1'h0;
+ \3504 [995] = 1'h0;
+ \3504 [996] = 1'h0;
+ \3504 [997] = 1'h0;
+ \3504 [998] = 1'h0;
+ \3504 [999] = 1'h0;
+ \3504 [1000] = 1'h0;
+ \3504 [1001] = 1'h0;
+ \3504 [1002] = 1'h0;
+ \3504 [1003] = 1'h0;
+ \3504 [1004] = 1'h0;
+ \3504 [1005] = 1'h1;
+ \3504 [1006] = 1'h0;
+ \3504 [1007] = 1'h1;
+ \3504 [1008] = 1'h0;
+ \3504 [1009] = 1'h0;
+ \3504 [1010] = 1'h0;
+ \3504 [1011] = 1'h0;
+ \3504 [1012] = 1'h0;
+ \3504 [1013] = 1'h0;
+ \3504 [1014] = 1'h0;
+ \3504 [1015] = 1'h0;
+ \3504 [1016] = 1'h0;
+ \3504 [1017] = 1'h0;
+ \3504 [1018] = 1'h0;
+ \3504 [1019] = 1'h0;
+ \3504 [1020] = 1'h0;
+ \3504 [1021] = 1'h1;
+ \3504 [1022] = 1'h0;
+ \3504 [1023] = 1'h1;
+ end
+ assign _86_ = \3504 [_09_];
+ reg [37:0] \3506 [7:0];
+ initial begin
+ \3506 [0] = 38'h2000000071;
+ \3506 [1] = 38'h2800000001;
+ \3506 [2] = 38'h0000006bc5;
+ \3506 [3] = 38'h1000076b1d;
+ \3506 [4] = 38'h2800000001;
+ \3506 [5] = 38'h2800000001;
+ \3506 [6] = 38'h0800014409;
+ \3506 [7] = 38'h00000c0039;
+ end
+ assign _88_ = \3506 [_11_];
+ reg [37:0] \3508 [15:0];
+ initial begin
+ \3508 [0] = 38'h2800000001;
+ \3508 [1] = 38'h2800000001;
+ \3508 [2] = 38'h2800000001;
+ \3508 [3] = 38'h2800000001;
+ \3508 [4] = 38'h2800000001;
+ \3508 [5] = 38'h2800000001;
+ \3508 [6] = 38'h08000288d1;
+ \3508 [7] = 38'h08000288cd;
+ \3508 [8] = 38'h080002d9c9;
+ \3508 [9] = 38'h080002d9c9;
+ \3508 [10] = 38'h080002d8c9;
+ \3508 [11] = 38'h080002d8c9;
+ \3508 [12] = 38'h080002d8d1;
+ \3508 [13] = 38'h080002d8d1;
+ \3508 [14] = 38'h080002d8cd;
+ \3508 [15] = 38'h080002d8cd;
+ end
+ assign _90_ = \3508 [_14_];
+ reg [37:0] \3510 [3:0];
+ initial begin
+ \3510 [0] = 38'h0000000000;
+ \3510 [1] = 38'h0026014a76;
+ \3510 [2] = 38'h0048014a76;
+ \3510 [3] = 38'h0008014a76;
+ end
+ assign _92_ = \3510 [_16_];
+ reg [37:0] \3512 [3:0];
+ initial begin
+ \3512 [0] = 38'h0000000000;
+ \3512 [1] = 38'h0000000000;
+ \3512 [2] = 38'h004800ca7a;
+ \3512 [3] = 38'h000800ca7a;
+ end
+ assign _94_ = \3512 [_18_];
+ reg [37:0] \3514 [63:0];
+ initial begin
+ \3514 [0] = 38'h2800000001;
+ \3514 [1] = 38'h2800000001;
+ \3514 [2] = 38'h2800000001;
+ \3514 [3] = 38'h2800000001;
+ \3514 [4] = 38'h2800000001;
+ \3514 [5] = 38'h2800000001;
+ \3514 [6] = 38'h2800000001;
+ \3514 [7] = 38'h2800000001;
+ \3514 [8] = 38'h2800000001;
+ \3514 [9] = 38'h2800000001;
+ \3514 [10] = 38'h2800000001;
+ \3514 [11] = 38'h2800000001;
+ \3514 [12] = 38'h2800000001;
+ \3514 [13] = 38'h2800000001;
+ \3514 [14] = 38'h2800000001;
+ \3514 [15] = 38'h2800000001;
+ \3514 [16] = 38'h2800000001;
+ \3514 [17] = 38'h2800000001;
+ \3514 [18] = 38'h0044009a7a;
+ \3514 [19] = 38'h0004009a7a;
+ \3514 [20] = 38'h0064011a76;
+ \3514 [21] = 38'h0024011a76;
+ \3514 [22] = 38'h0044011a76;
+ \3514 [23] = 38'h0004011a76;
+ \3514 [24] = 38'h0042009a7a;
+ \3514 [25] = 38'h0002009a7a;
+ \3514 [26] = 38'h0046009a7a;
+ \3514 [27] = 38'h0006009a7a;
+ \3514 [28] = 38'h0042011a76;
+ \3514 [29] = 38'h0002011a76;
+ \3514 [30] = 38'h0046011a76;
+ \3514 [31] = 38'h0006011a76;
+ \3514 [32] = 38'h2800000001;
+ \3514 [33] = 38'h2800000001;
+ \3514 [34] = 38'h040002a80d;
+ \3514 [35] = 38'h040002900d;
+ \3514 [36] = 38'h000002a8f1;
+ \3514 [37] = 38'h00000290f1;
+ \3514 [38] = 38'h000002a8b9;
+ \3514 [39] = 38'h00000290b9;
+ \3514 [40] = 38'h09000288c9;
+ \3514 [41] = 38'h2800000001;
+ \3514 [42] = 38'h090002e0c9;
+ \3514 [43] = 38'h090002e1c9;
+ \3514 [44] = 38'h2800000001;
+ \3514 [45] = 38'h1000003015;
+ \3514 [46] = 38'h00000000d5;
+ \3514 [47] = 38'h1000073b19;
+ \3514 [48] = 38'h0000012209;
+ \3514 [49] = 38'h0000011a09;
+ \3514 [50] = 38'h0401011909;
+ \3514 [51] = 38'h0001011909;
+ \3514 [52] = 38'h0200981925;
+ \3514 [53] = 38'h0000981125;
+ \3514 [54] = 38'h2800000001;
+ \3514 [55] = 38'h0001911909;
+ \3514 [56] = 38'h02000919ad;
+ \3514 [57] = 38'h2800000001;
+ \3514 [58] = 38'h2800000001;
+ \3514 [59] = 38'h2800000001;
+ \3514 [60] = 38'h21000019ed;
+ \3514 [61] = 38'h20000019ed;
+ \3514 [62] = 38'h2800000001;
+ \3514 [63] = 38'h2000000011;
+ end
+ assign _96_ = \3514 [_21_];
+ assign d_out = r;
+endmodule
+
+module decode2_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, complete_in, stall_in, flush_in, d_in, r_in, c_in, stall_out, stopped_out, e_out, r_out, c_out);
+ wire _00_;
+ wire _01_;
+ wire [5:0] _02_;
+ wire [5:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire [70:0] _18_;
+ wire [70:0] _19_;
+ wire [70:0] _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire [70:0] _42_;
+ wire _43_;
+ wire _44_;
+ wire [70:0] _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire [6:0] _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire _62_;
+ wire [3:0] _63_;
+ wire _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ wire _70_;
+ wire _71_;
+ wire _72_;
+ wire _73_;
+ wire _74_;
+ wire _75_;
+ wire _76_;
+ wire _77_;
+ wire _78_;
+ wire _79_;
+ wire _80_;
+ wire _81_;
+ wire _82_;
+ wire [5:0] _83_;
+ input [36:0] c_in;
+ output c_out;
+ input clk;
+ input complete_in;
+ wire control_valid_out;
+ wire cr_write_valid;
+ input [147:0] d_in;
+ output [374:0] e_out;
+ input flush_in;
+ wire gpr_a_bypass;
+ wire gpr_b_bypass;
+ wire gpr_bypassable;
+ wire gpr_c_bypass;
+ reg [374:0] r;
+ input [191:0] r_in;
+ output [19:0] r_out;
+ wire [374:0] rin;
+ input rst;
+ input stall_in;
+ output stall_out;
+ output stopped_out;
+ always @(posedge clk)
+ r <= rin;
+ assign _02_ = d_in[103] ? d_in[103:98] : { 1'h0, d_in[86:82] };
+ assign _03_ = d_in[109] ? d_in[109:104] : { 1'h0, d_in[81:77] };
+ assign _04_ = d_in[120:118] == 3'h1;
+ assign _05_ = d_in[120:118] == 3'h2;
+ assign _06_ = d_in[86:82] != 5'h00;
+ assign _07_ = _05_ & _06_;
+ assign _08_ = _04_ | _07_;
+ assign _09_ = ~ d_in[103];
+ assign _10_ = ~ 1'h0;
+ assign _11_ = _10_ | _09_;
+ assign _12_ = d_in[120:118] == 3'h3;
+ assign _13_ = d_in[103:98] == 6'h00;
+ assign _14_ = d_in[103] | _13_;
+ assign _15_ = ~ 1'h0;
+ assign _16_ = _15_ | _14_;
+ assign _17_ = d_in[120:118] == 3'h4;
+ assign _18_ = _17_ ? { d_in[65:2], 7'h00 } : 71'h000000000000000000;
+ assign _19_ = _12_ ? { r_in[63:0], d_in[103:98], d_in[103] } : _18_;
+ assign _20_ = _08_ ? { r_in[63:0], 1'h0, d_in[86:82], 1'h1 } : _19_;
+ assign _21_ = ~ d_in[109];
+ assign _22_ = ~ 1'h0;
+ assign _23_ = _22_ | _21_;
+ assign _24_ = d_in[124:121] == 4'h1;
+ assign _25_ = d_in[124:121] == 4'h2;
+ assign _26_ = d_in[124:121] == 4'h3;
+ assign _27_ = d_in[124:121] == 4'h4;
+ assign _28_ = d_in[124:121] == 4'h5;
+ assign _29_ = d_in[124:121] == 4'h6;
+ assign _30_ = d_in[124:121] == 4'h7;
+ assign _31_ = d_in[124:121] == 4'h9;
+ assign _32_ = d_in[124:121] == 4'h8;
+ assign _33_ = d_in[124:121] == 4'ha;
+ assign _34_ = d_in[124:121] == 4'hb;
+ assign _35_ = d_in[124:121] == 4'hc;
+ assign _36_ = d_in[109:104] == 6'h00;
+ assign _37_ = d_in[109] | _36_;
+ assign _38_ = ~ 1'h0;
+ assign _39_ = _38_ | _37_;
+ assign _40_ = d_in[124:121] == 4'hd;
+ assign _41_ = d_in[124:121] == 4'h0;
+ function [70:0] \3888 ;
+ input [70:0] a;
+ input [993:0] b;
+ input [13:0] s;
+ (* parallel_case *)
+ casez (s)
+ 14'b?????????????1:
+ \3888 = b[70:0];
+ 14'b????????????1?:
+ \3888 = b[141:71];
+ 14'b???????????1??:
+ \3888 = b[212:142];
+ 14'b??????????1???:
+ \3888 = b[283:213];
+ 14'b?????????1????:
+ \3888 = b[354:284];
+ 14'b????????1?????:
+ \3888 = b[425:355];
+ 14'b???????1??????:
+ \3888 = b[496:426];
+ 14'b??????1???????:
+ \3888 = b[567:497];
+ 14'b?????1????????:
+ \3888 = b[638:568];
+ 14'b????1?????????:
+ \3888 = b[709:639];
+ 14'b???1??????????:
+ \3888 = b[780:710];
+ 14'b??1???????????:
+ \3888 = b[851:781];
+ 14'b?1????????????:
+ \3888 = b[922:852];
+ 14'b1?????????????:
+ \3888 = b[993:923];
+ default:
+ \3888 = a;
+ endcase
+ endfunction
+ assign _42_ = \3888 (71'hxxxxxxxxxxxxxxxxxx, { 71'h000000000000000000, r_in[127:64], d_in[109:104], d_in[109], 59'h000000000000000, d_in[81:77], 65'h00000000000000000, d_in[67], d_in[81:77], 78'h007fffffffffffffff80, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:72], d_in[86:82], d_in[66], 23'h000200, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 9'h000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:68], 9'h000, d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91], d_in[91:68], 41'h00000000000, d_in[81:66], 23'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 23'h000000, d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81], d_in[81:66], 55'h00000000000000, d_in[81:66], 7'h00, r_in[127:64], 1'h0, d_in[81:77], 1'h1 }, { _41_, _40_, _35_, _34_, _33_, _32_, _31_, _30_, _29_, _28_, _27_, _26_, _25_, _24_ });
+ assign _43_ = d_in[125] == 1'h1;
+ assign _44_ = d_in[125] == 1'h0;
+ function [70:0] \3929 ;
+ input [70:0] a;
+ input [141:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \3929 = b[70:0];
+ 2'b1?:
+ \3929 = b[141:71];
+ default:
+ \3929 = a;
+ endcase
+ endfunction
+ assign _45_ = \3929 (71'hxxxxxxxxxxxxxxxxxx, { 71'h000000000000000000, r_in[191:128], 1'h0, d_in[91:87], 1'h1 }, { _44_, _43_ });
+ assign _46_ = d_in[127:126] == 2'h1;
+ assign _47_ = d_in[127:126] == 2'h2;
+ assign _48_ = d_in[103:98] == 6'h00;
+ assign _49_ = d_in[103] | _48_;
+ assign _50_ = ~ 1'h0;
+ assign _51_ = _50_ | _49_;
+ assign _52_ = d_in[127:126] == 2'h3;
+ assign _53_ = d_in[127:126] == 2'h0;
+ function [6:0] \4000 ;
+ input [6:0] a;
+ input [27:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \4000 = b[6:0];
+ 4'b??1?:
+ \4000 = b[13:7];
+ 4'b?1??:
+ \4000 = b[20:14];
+ 4'b1???:
+ \4000 = b[27:21];
+ default:
+ \4000 = a;
+ endcase
+ endfunction
+ assign _54_ = \4000 (7'hxx, { 7'h00, d_in[103:98], d_in[103], 1'h0, d_in[86:82], 2'h2, d_in[91:87], 1'h1 }, { _53_, _52_, _47_, _46_ });
+ assign _55_ = _20_[0] & d_in[0];
+ assign _56_ = _42_[0] & d_in[0];
+ assign _57_ = _45_[0] & d_in[0];
+ assign _58_ = d_in[137:135] == 3'h1;
+ assign _59_ = d_in[137:135] == 3'h2;
+ assign _60_ = d_in[137:135] == 3'h3;
+ assign _61_ = d_in[137:135] == 3'h4;
+ assign _62_ = d_in[137:135] == 3'h0;
+ function [3:0] \4033 ;
+ input [3:0] a;
+ input [19:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \4033 = b[3:0];
+ 5'b???1?:
+ \4033 = b[7:4];
+ 5'b??1??:
+ \4033 = b[11:8];
+ 5'b?1???:
+ \4033 = b[15:12];
+ 5'b1????:
+ \4033 = b[19:16];
+ default:
+ \4033 = a;
+ endcase
+ endfunction
+ assign _63_ = \4033 (4'hx, 20'h08421, { _62_, _61_, _60_, _59_, _58_ });
+ assign _64_ = d_in[145:144] == 2'h2;
+ assign _65_ = d_in[145:144] == 2'h1;
+ assign _66_ = d_in[145:144] == 2'h0;
+ function [0:0] \4083 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \4083 = b[0:0];
+ 3'b?1?:
+ \4083 = b[1:1];
+ 3'b1??:
+ \4083 = b[2:2];
+ default:
+ \4083 = a;
+ endcase
+ endfunction
+ assign _67_ = \4083 (1'hx, { 2'h1, d_in[66] }, { _66_, _65_, _64_ });
+ assign _68_ = d_in[117:112] == 6'h2d;
+ assign _69_ = d_in[117:112] == 6'h2c;
+ assign _70_ = _68_ | _69_;
+ assign _71_ = ~ _70_;
+ assign _72_ = d_in[145:144] == 2'h2;
+ function [0:0] \4113 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \4113 = b[0:0];
+ default:
+ \4113 = a;
+ endcase
+ endfunction
+ assign _73_ = \4113 (1'h0, d_in[76], _72_);
+ assign _74_ = _71_ ? _73_ : 1'h0;
+ assign _75_ = d_in[146] ? d_in[66] : 1'h0;
+ assign _76_ = d_in[111:110] == 2'h1;
+ assign _77_ = 1'h1 & _76_;
+ assign gpr_bypassable = _77_ ? 1'h1 : 1'h0;
+ assign _78_ = d_in[145:144] == 2'h2;
+ assign _79_ = d_in[145:144] == 2'h1;
+ assign _80_ = d_in[145:144] == 2'h0;
+ function [0:0] \4217 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \4217 = b[0:0];
+ 3'b?1?:
+ \4217 = b[1:1];
+ 3'b1??:
+ \4217 = b[2:2];
+ default:
+ \4217 = a;
+ endcase
+ endfunction
+ assign _81_ = \4217 (1'hx, { 2'h1, d_in[66] }, { _80_, _79_, _78_ });
+ assign cr_write_valid = d_in[129] | _81_;
+ assign _82_ = d_in[111:110] == 2'h0;
+ assign _83_ = _82_ ? 6'h00 : d_in[117:112];
+ assign rin = rst ? 375'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { d_in[141:138], _63_, d_in[97:66], d_in[143:142], 2'h0, d_in[134:130], _74_, _67_, _75_, c_in, gpr_c_bypass, gpr_b_bypass, gpr_a_bypass, _45_[70:7], _42_[70:7], _20_[70:7], _42_[6:1], _20_[6:1], _54_[6:1], d_in[65:2], _83_, d_in[111:110], control_valid_out };
+ control_1 control_0 (
+ .clk(clk),
+ .complete_in(complete_in),
+ .cr_read_in(d_in[128]),
+ .cr_write_in(cr_write_valid),
+ .flush_in(flush_in),
+ .gpr_a_read_in(_20_[6:1]),
+ .gpr_a_read_valid_in(_20_[0]),
+ .gpr_b_read_in(_42_[6:1]),
+ .gpr_b_read_valid_in(_42_[0]),
+ .gpr_bypass_a(gpr_a_bypass),
+ .gpr_bypass_b(gpr_b_bypass),
+ .gpr_bypass_c(gpr_c_bypass),
+ .gpr_bypassable(gpr_bypassable),
+ .gpr_c_read_in(_45_[5:1]),
+ .gpr_c_read_valid_in(_45_[0]),
+ .gpr_write_in(_54_[6:1]),
+ .gpr_write_valid_in(_54_[0]),
+ .rst(rst),
+ .sgl_pipe_in(d_in[147]),
+ .stall_in(stall_in),
+ .stall_out(_00_),
+ .stop_mark_in(d_in[1]),
+ .stopped_out(_01_),
+ .valid_in(d_in[0]),
+ .valid_out(control_valid_out)
+ );
+ assign stall_out = _00_;
+ assign stopped_out = _01_;
+ assign e_out = r;
+ assign r_out = { d_in[91:87], _57_, _03_, _56_, _02_, _55_ };
+ assign c_out = d_in[128];
+endmodule
+
+module divider(clk, rst, d_in, d_out);
+ wire [128:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [63:0] _06_;
+ wire [6:0] _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [6:0] _12_;
+ wire _13_;
+ wire [6:0] _14_;
+ wire [128:0] _15_;
+ wire [63:0] _16_;
+ wire [6:0] _17_;
+ wire _18_;
+ wire [128:0] _19_;
+ wire [63:0] _20_;
+ wire [6:0] _21_;
+ wire _22_;
+ wire [128:0] _23_;
+ wire [63:0] _24_;
+ wire _25_;
+ wire [6:0] _26_;
+ wire _27_;
+ wire _28_;
+ wire [128:0] _29_;
+ wire [63:0] _30_;
+ wire [63:0] _31_;
+ wire _32_;
+ wire [6:0] _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire [128:0] _40_;
+ wire [63:0] _41_;
+ wire [63:0] _42_;
+ wire _43_;
+ wire [6:0] _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire [64:0] _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire [63:0] _62_;
+ wire _63_;
+ wire _64_;
+ reg [65:0] _65_;
+ input clk;
+ reg [6:0] count;
+ input [133:0] d_in;
+ output [65:0] d_out;
+ reg [128:0] dend;
+ wire did_ovf;
+ reg [63:0] div;
+ reg is_32bit;
+ reg is_modulus;
+ reg is_signed;
+ reg neg_result;
+ wire [63:0] oresult;
+ reg overflow;
+ reg ovf32;
+ reg [63:0] quot;
+ wire [63:0] result;
+ input rst;
+ reg running;
+ wire [64:0] sresult;
+ assign _00_ = d_in[131] ? { 1'h0, d_in[64:1], 64'h0000000000000000 } : { 65'h00000000000000000, d_in[64:1] };
+ assign _01_ = count == 7'h3f;
+ assign _02_ = _25_ ? 1'h0 : running;
+ assign _03_ = dend[127:64] >= div;
+ assign _04_ = dend[128] | _03_;
+ assign _05_ = ovf32 | quot[31];
+ assign _06_ = dend[127:64] - div;
+ assign _07_ = count + 7'h01;
+ assign _08_ = dend[128:57] == 72'h000000000000000000;
+ assign _09_ = count[6:3] != 4'h7;
+ assign _10_ = _08_ & _09_;
+ assign _11_ = | { ovf32, quot[31:24] };
+ assign _12_ = count + 7'h08;
+ assign _13_ = ovf32 | quot[31];
+ assign _14_ = count + 7'h01;
+ assign _15_ = _10_ ? { dend[120:0], 8'h00 } : { dend[127:0], 1'h0 };
+ assign _16_ = _10_ ? { quot[55:0], 8'h00 } : { quot[62:0], 1'h0 };
+ assign _17_ = _10_ ? _12_ : _14_;
+ assign _18_ = _10_ ? _11_ : _13_;
+ assign _19_ = _04_ ? { _06_, dend[63:0], 1'h0 } : _15_;
+ assign _20_ = _04_ ? { quot[62:0], 1'h1 } : _16_;
+ assign _21_ = _04_ ? _07_ : _17_;
+ assign _22_ = _04_ ? _05_ : _18_;
+ assign _23_ = running ? _19_ : dend;
+ assign _24_ = running ? _20_ : quot;
+ assign _25_ = running & _01_;
+ assign _26_ = running ? _21_ : 7'h00;
+ assign _27_ = running ? quot[63] : overflow;
+ assign _28_ = running ? _22_ : ovf32;
+ assign _29_ = d_in[0] ? _00_ : _23_;
+ assign _30_ = d_in[0] ? d_in[128:65] : div;
+ assign _31_ = d_in[0] ? 64'h0000000000000000 : _24_;
+ assign _32_ = d_in[0] ? 1'h1 : _02_;
+ assign _33_ = d_in[0] ? 7'h7f : _26_;
+ assign _34_ = d_in[0] ? d_in[133] : neg_result;
+ assign _35_ = d_in[0] ? d_in[132] : is_modulus;
+ assign _36_ = d_in[0] ? d_in[130] : is_32bit;
+ assign _37_ = d_in[0] ? d_in[129] : is_signed;
+ assign _38_ = d_in[0] ? 1'h0 : _27_;
+ assign _39_ = d_in[0] ? 1'h0 : _28_;
+ assign _40_ = rst ? 129'h000000000000000000000000000000000 : _29_;
+ assign _41_ = rst ? 64'h0000000000000000 : _30_;
+ assign _42_ = rst ? 64'h0000000000000000 : _31_;
+ assign _43_ = rst ? 1'h0 : _32_;
+ assign _44_ = rst ? 7'h00 : _33_;
+ assign _45_ = rst ? neg_result : _34_;
+ assign _46_ = rst ? is_modulus : _35_;
+ assign _47_ = rst ? is_32bit : _36_;
+ assign _48_ = rst ? is_signed : _37_;
+ assign _49_ = rst ? overflow : _38_;
+ assign _50_ = rst ? ovf32 : _39_;
+ always @(posedge clk)
+ dend <= _40_;
+ always @(posedge clk)
+ div <= _41_;
+ always @(posedge clk)
+ quot <= _42_;
+ always @(posedge clk)
+ running <= _43_;
+ always @(posedge clk)
+ count <= _44_;
+ always @(posedge clk)
+ neg_result <= _45_;
+ always @(posedge clk)
+ is_modulus <= _46_;
+ always @(posedge clk)
+ is_32bit <= _47_;
+ always @(posedge clk)
+ is_signed <= _48_;
+ always @(posedge clk)
+ overflow <= _49_;
+ always @(posedge clk)
+ ovf32 <= _50_;
+ assign result = is_modulus ? dend[128:65] : quot;
+ assign _51_ = - $signed({ 1'h0, result });
+ assign sresult = neg_result ? _51_ : { 1'h0, result };
+ assign _52_ = ~ is_32bit;
+ assign _53_ = sresult[64] ^ sresult[63];
+ assign _54_ = is_signed & _53_;
+ assign _55_ = overflow | _54_;
+ assign _56_ = sresult[32] != sresult[31];
+ assign _57_ = ovf32 | _56_;
+ assign _58_ = _57_ ? 1'h1 : 1'h0;
+ assign _59_ = is_signed ? _58_ : ovf32;
+ assign did_ovf = _52_ ? _55_ : _59_;
+ assign _60_ = ~ is_modulus;
+ assign _61_ = is_32bit & _60_;
+ assign _62_ = _61_ ? { 32'h00000000, sresult[31:0] } : sresult[63:0];
+ assign oresult = did_ovf ? 64'h0000000000000000 : _62_;
+ assign _63_ = count == 7'h40;
+ assign _64_ = _63_ ? 1'h1 : 1'h0;
+ always @(posedge clk)
+ _65_ <= { did_ovf, oresult, _64_ };
+ assign d_out = _65_;
+endmodule
+
+module execute1_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, e_in, l_in, ext_irq_in, flush_out, stall_out, l_out, f_out, e_out, dbg_msr_out, icache_inval, terminate_out);
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire [334:0] _0007_;
+ wire [127:0] _0008_;
+ wire [64:0] _0009_;
+ wire [127:0] _0010_;
+ wire _0011_;
+ reg _0012_ = 1'h1;
+ wire [4:0] _0013_;
+ wire [129:0] _0014_;
+ wire [129:0] _0015_;
+ wire [129:0] _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire [63:0] _0022_;
+ wire [63:0] _0023_;
+ wire _0024_;
+ wire [63:0] _0025_;
+ wire [63:0] _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire [63:0] _0036_;
+ wire [127:0] _0037_;
+ wire _0038_;
+ wire [63:0] _0039_;
+ wire [63:0] _0040_;
+ wire [63:0] _0041_;
+ wire _0042_;
+ wire [63:0] _0043_;
+ wire _0044_;
+ wire [63:0] _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire [63:0] _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire [5:0] _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire [127:0] _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire [63:0] _0082_;
+ wire [63:0] _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire [64:0] _0088_;
+ wire [64:0] _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire [190:0] _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire [190:0] _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire [31:0] _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire [31:0] _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire [4:0] _0125_;
+ wire [4:0] _0126_;
+ wire _0127_;
+ wire [3:0] _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire [7:0] _0137_;
+ wire [4:0] _0138_;
+ wire _0139_;
+ wire [127:0] _0140_;
+ wire _0141_;
+ wire [127:0] _0142_;
+ wire [40:0] _0143_;
+ wire _0144_;
+ wire [127:0] _0145_;
+ wire [72:0] _0146_;
+ wire [40:0] _0147_;
+ wire [76:0] _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire [63:0] _0161_;
+ wire [63:0] _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire [63:0] _0165_;
+ wire [5:0] _0166_;
+ wire [63:0] _0167_;
+ wire _0168_;
+ wire [31:0] _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire [31:0] _0178_;
+ wire _0179_;
+ wire [63:0] _0180_;
+ wire [63:0] _0181_;
+ wire _0182_;
+ wire [63:0] _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire [63:0] _0188_;
+ wire [5:0] _0189_;
+ wire [63:0] _0190_;
+ wire _0191_;
+ wire [31:0] _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire [31:0] _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire [63:0] _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire [1:0] _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire [7:0] _0212_;
+ wire _0213_;
+ wire [7:0] _0214_;
+ wire _0215_;
+ wire [7:0] _0216_;
+ wire _0217_;
+ wire [7:0] _0218_;
+ wire _0219_;
+ wire [7:0] _0220_;
+ wire _0221_;
+ wire [7:0] _0222_;
+ wire _0223_;
+ wire [7:0] _0224_;
+ wire _0225_;
+ wire [7:0] _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire [15:0] _0234_;
+ wire _0235_;
+ wire [7:0] _0236_;
+ wire _0237_;
+ wire [31:0] _0238_;
+ wire [63:0] _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire [7:0] _0250_;
+ wire _0251_;
+ wire [3:0] _0252_;
+ wire _0253_;
+ wire [3:0] _0254_;
+ wire _0255_;
+ wire [3:0] _0256_;
+ wire _0257_;
+ wire [3:0] _0258_;
+ wire _0259_;
+ wire [3:0] _0260_;
+ wire _0261_;
+ wire [3:0] _0262_;
+ wire _0263_;
+ wire [3:0] _0264_;
+ wire _0265_;
+ wire [3:0] _0266_;
+ wire [31:0] _0267_;
+ wire [31:0] _0268_;
+ wire [31:0] _0269_;
+ wire [31:0] _0270_;
+ wire [31:0] _0271_;
+ wire [31:0] _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire [7:0] _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire [40:0] _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire [45:0] _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire [63:0] _0354_;
+ wire _0355_;
+ wire [63:0] _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire [2:0] _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire [2:0] _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire [2:0] _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire [2:0] _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire [2:0] _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire [2:0] _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire [2:0] _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire [2:0] _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire [2:0] _0423_;
+ wire _0424_;
+ wire [3:0] _0425_;
+ wire _0426_;
+ wire [3:0] _0427_;
+ wire _0428_;
+ wire [3:0] _0429_;
+ wire _0430_;
+ wire [3:0] _0431_;
+ wire _0432_;
+ wire [3:0] _0433_;
+ wire _0434_;
+ wire [3:0] _0435_;
+ wire _0436_;
+ wire [3:0] _0437_;
+ wire _0438_;
+ wire [3:0] _0439_;
+ wire [63:0] _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire [2:0] _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire [2:0] _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire [2:0] _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire [2:0] _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire [2:0] _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire [2:0] _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire [2:0] _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire [2:0] _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire [2:0] _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire [7:0] _0515_;
+ wire [7:0] _0516_;
+ wire _0517_;
+ wire [1:0] _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire [9:0] _0521_;
+ wire [1:0] _0522_;
+ wire _0523_;
+ wire [43:0] _0524_;
+ wire [2:0] _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire [5:0] _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire [63:0] _0531_;
+ wire _0532_;
+ wire [63:0] _0533_;
+ wire [5:0] _0534_;
+ wire [63:0] _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire [190:0] _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire [63:0] _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire [63:0] _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire [1:0] _0575_;
+ wire [1:0] _0576_;
+ wire [5:0] _0577_;
+ wire _0578_;
+ wire [1:0] _0579_;
+ wire _0580_;
+ wire [5:0] _0581_;
+ wire [4:0] _0582_;
+ wire [3:0] _0583_;
+ wire [28:0] _0584_;
+ wire _0585_;
+ wire [2:0] _0586_;
+ wire [127:0] _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire [1:0] _0591_;
+ wire [5:0] _0592_;
+ wire [63:0] _0593_;
+ wire _0594_;
+ wire [7:0] _0595_;
+ wire [31:0] _0596_;
+ wire [5:0] _0597_;
+ wire [70:0] _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire [7:0] _0602_;
+ wire [7:0] _0603_;
+ wire [15:0] _0604_;
+ wire [31:0] _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire [64:0] _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire [63:0] _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire [2:0] _0623_;
+ wire _0624_;
+ wire [1:0] _0625_;
+ wire [5:0] _0626_;
+ wire [5:0] _0627_;
+ wire [1:0] _0628_;
+ wire [63:0] _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire [5:0] _0634_;
+ wire [1:0] _0635_;
+ wire [63:0] _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire [1:0] _0639_;
+ wire [5:0] _0640_;
+ wire _0641_;
+ wire [4:0] _0642_;
+ wire [1:0] _0643_;
+ wire [63:0] _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire [5:0] _0649_;
+ wire [5:0] _0650_;
+ wire [1:0] _0651_;
+ wire [63:0] _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire [5:0] _0657_;
+ wire [5:0] _0658_;
+ wire [1:0] _0659_;
+ wire [63:0] _0660_;
+ wire [63:0] _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire [66:0] _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire [127:0] _0668_;
+ wire [127:0] _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire [1:0] _0672_;
+ wire _0673_;
+ wire [5:0] _0674_;
+ wire [104:0] _0675_;
+ wire [5:0] _0676_;
+ wire [135:0] _0677_;
+ wire [1:0] _0678_;
+ wire [12:0] _0679_;
+ wire [63:0] _0680_;
+ wire [63:0] _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire [66:0] _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire [127:0] _0691_;
+ wire [127:0] _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire [334:0] _0695_;
+ wire [63:0] _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire [66:0] _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire [127:0] _0706_;
+ wire [63:0] _0707_;
+ wire [63:0] _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire [334:0] _0711_;
+ wire [63:0] _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire [66:0] _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire [63:0] _0722_;
+ wire [1:0] _0723_;
+ wire [1:0] _0724_;
+ wire [1:0] _0725_;
+ wire [7:0] _0726_;
+ wire [1:0] _0727_;
+ wire [46:0] _0728_;
+ wire _0729_;
+ wire [127:0] _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire [118:0] _0734_;
+ wire [70:0] _0735_;
+ wire [143:0] _0736_;
+ wire [63:0] _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire [127:0] _0743_;
+ wire _0744_;
+ wire [63:0] _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire [63:0] _0752_;
+ wire _0753_;
+ wire [63:0] _0754_;
+ wire [1:0] _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire [63:0] _0758_;
+ wire [1:0] _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire [128:0] _0762_;
+ wire _0763_;
+ wire [70:0] _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire [61:0] _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire [63:0] a_in;
+ wire [63:0] b_in;
+ wire [63:0] c_in;
+ input clk;
+ wire [63:0] countzero_result;
+ reg [320:0] ctrl = 321'h000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ output [63:0] dbg_msr_out;
+ wire [65:0] divider_to_x;
+ input [374:0] e_in;
+ output [190:0] e_out;
+ input ext_irq_in;
+ output [66:0] f_out;
+ output flush_out;
+ output icache_inval;
+ input [6:0] l_in;
+ output [321:0] l_out;
+ wire [63:0] logical_result;
+ wire [65:0] multiply_to_x;
+ wire [63:0] parity_result;
+ wire [63:0] popcnt_result;
+ reg [334:0] r;
+ wire right_shift;
+ wire rot_clear_left;
+ wire rot_clear_right;
+ wire rot_sign_ext;
+ wire rotator_carry;
+ wire [63:0] rotator_result;
+ input rst;
+ output stall_out;
+ output terminate_out;
+ reg [0:0] \$mem$\7795 [61:0];
+ assign _0834_ = _0169_[0] ? e_in[287] : e_in[286];
+ assign _0835_ = _0169_[0] ? e_in[291] : e_in[290];
+ assign _0836_ = _0169_[0] ? e_in[295] : e_in[294];
+ assign _0837_ = _0169_[0] ? e_in[299] : e_in[298];
+ assign _0838_ = _0169_[0] ? e_in[303] : e_in[302];
+ assign _0839_ = _0169_[0] ? e_in[307] : e_in[306];
+ assign _0840_ = _0169_[0] ? e_in[311] : e_in[310];
+ assign _0841_ = _0169_[0] ? e_in[315] : e_in[314];
+ assign _0842_ = _0169_[2] ? _0775_ : _0774_;
+ assign _0843_ = _0169_[2] ? _0779_ : _0778_;
+ assign _0844_ = _0192_[0] ? e_in[287] : e_in[286];
+ assign _0845_ = _0192_[0] ? e_in[291] : e_in[290];
+ assign _0846_ = _0192_[0] ? e_in[295] : e_in[294];
+ assign _0847_ = _0192_[0] ? e_in[299] : e_in[298];
+ assign _0848_ = _0192_[0] ? e_in[303] : e_in[302];
+ assign _0849_ = _0192_[0] ? e_in[307] : e_in[306];
+ assign _0850_ = _0192_[0] ? e_in[311] : e_in[310];
+ assign _0851_ = _0192_[0] ? e_in[315] : e_in[314];
+ assign _0852_ = _0192_[2] ? _0786_ : _0785_;
+ assign _0853_ = _0192_[2] ? _0790_ : _0789_;
+ assign _0854_ = _0238_[0] ? e_in[287] : e_in[286];
+ assign _0855_ = _0238_[0] ? e_in[291] : e_in[290];
+ assign _0856_ = _0238_[0] ? e_in[295] : e_in[294];
+ assign _0857_ = _0238_[0] ? e_in[299] : e_in[298];
+ assign _0858_ = _0238_[0] ? e_in[303] : e_in[302];
+ assign _0859_ = _0238_[0] ? e_in[307] : e_in[306];
+ assign _0860_ = _0238_[0] ? e_in[311] : e_in[310];
+ assign _0861_ = _0238_[0] ? e_in[315] : e_in[314];
+ assign _0862_ = _0238_[2] ? _0797_ : _0796_;
+ assign _0863_ = _0238_[2] ? _0801_ : _0800_;
+ assign _0864_ = _0268_[0] ? e_in[287] : e_in[286];
+ assign _0865_ = _0268_[0] ? e_in[291] : e_in[290];
+ assign _0866_ = _0268_[0] ? e_in[295] : e_in[294];
+ assign _0867_ = _0268_[0] ? e_in[299] : e_in[298];
+ assign _0868_ = _0268_[0] ? e_in[303] : e_in[302];
+ assign _0869_ = _0268_[0] ? e_in[307] : e_in[306];
+ assign _0870_ = _0268_[0] ? e_in[311] : e_in[310];
+ assign _0871_ = _0268_[0] ? e_in[315] : e_in[314];
+ assign _0872_ = _0268_[2] ? _0808_ : _0807_;
+ assign _0873_ = _0268_[2] ? _0812_ : _0811_;
+ assign _0874_ = _0269_[0] ? e_in[287] : e_in[286];
+ assign _0875_ = _0269_[0] ? e_in[291] : e_in[290];
+ assign _0876_ = _0269_[0] ? e_in[295] : e_in[294];
+ assign _0877_ = _0269_[0] ? e_in[299] : e_in[298];
+ assign _0878_ = _0269_[0] ? e_in[303] : e_in[302];
+ assign _0879_ = _0269_[0] ? e_in[307] : e_in[306];
+ assign _0880_ = _0269_[0] ? e_in[311] : e_in[310];
+ assign _0881_ = _0269_[0] ? e_in[315] : e_in[314];
+ assign _0882_ = _0269_[2] ? _0819_ : _0818_;
+ assign _0883_ = _0269_[2] ? _0823_ : _0822_;
+ assign _0884_ = _0270_[0] ? e_in[337] : e_in[336];
+ assign _0885_ = _0270_[0] ? e_in[341] : e_in[340];
+ assign _0886_ = _0169_[0] ? e_in[289] : e_in[288];
+ assign _0887_ = _0169_[0] ? e_in[293] : e_in[292];
+ assign _0888_ = _0169_[0] ? e_in[297] : e_in[296];
+ assign _0889_ = _0169_[0] ? e_in[301] : e_in[300];
+ assign _0890_ = _0169_[0] ? e_in[305] : e_in[304];
+ assign _0891_ = _0169_[0] ? e_in[309] : e_in[308];
+ assign _0892_ = _0169_[0] ? e_in[313] : e_in[312];
+ assign _0893_ = _0169_[0] ? e_in[317] : e_in[316];
+ assign _0894_ = _0169_[2] ? _0777_ : _0776_;
+ assign _0895_ = _0169_[2] ? _0781_ : _0780_;
+ assign _0896_ = _0192_[0] ? e_in[289] : e_in[288];
+ assign _0897_ = _0192_[0] ? e_in[293] : e_in[292];
+ assign _0898_ = _0192_[0] ? e_in[297] : e_in[296];
+ assign _0899_ = _0192_[0] ? e_in[301] : e_in[300];
+ assign _0900_ = _0192_[0] ? e_in[305] : e_in[304];
+ assign _0901_ = _0192_[0] ? e_in[309] : e_in[308];
+ assign _0902_ = _0192_[0] ? e_in[313] : e_in[312];
+ assign _0903_ = _0192_[0] ? e_in[317] : e_in[316];
+ assign _0904_ = _0192_[2] ? _0788_ : _0787_;
+ assign _0905_ = _0192_[2] ? _0792_ : _0791_;
+ assign _0906_ = _0238_[0] ? e_in[289] : e_in[288];
+ assign _0907_ = _0238_[0] ? e_in[293] : e_in[292];
+ assign _0908_ = _0238_[0] ? e_in[297] : e_in[296];
+ assign _0909_ = _0238_[0] ? e_in[301] : e_in[300];
+ assign _0910_ = _0238_[0] ? e_in[305] : e_in[304];
+ assign _0911_ = _0238_[0] ? e_in[309] : e_in[308];
+ assign _0912_ = _0238_[0] ? e_in[313] : e_in[312];
+ assign _0913_ = _0238_[0] ? e_in[317] : e_in[316];
+ assign _0914_ = _0238_[2] ? _0799_ : _0798_;
+ assign _0915_ = _0238_[2] ? _0803_ : _0802_;
+ assign _0916_ = _0268_[0] ? e_in[289] : e_in[288];
+ assign _0917_ = _0268_[0] ? e_in[293] : e_in[292];
+ assign _0918_ = _0268_[0] ? e_in[297] : e_in[296];
+ assign _0919_ = _0268_[0] ? e_in[301] : e_in[300];
+ assign _0920_ = _0268_[0] ? e_in[305] : e_in[304];
+ assign _0921_ = _0268_[0] ? e_in[309] : e_in[308];
+ assign _0922_ = _0268_[0] ? e_in[313] : e_in[312];
+ assign _0923_ = _0268_[0] ? e_in[317] : e_in[316];
+ assign _0924_ = _0268_[2] ? _0810_ : _0809_;
+ assign _0925_ = _0268_[2] ? _0814_ : _0813_;
+ assign _0926_ = _0269_[0] ? e_in[289] : e_in[288];
+ assign _0927_ = _0269_[0] ? e_in[293] : e_in[292];
+ assign _0928_ = _0269_[0] ? e_in[297] : e_in[296];
+ assign _0929_ = _0269_[0] ? e_in[301] : e_in[300];
+ assign _0930_ = _0269_[0] ? e_in[305] : e_in[304];
+ assign _0931_ = _0269_[0] ? e_in[309] : e_in[308];
+ assign _0932_ = _0269_[0] ? e_in[313] : e_in[312];
+ assign _0933_ = _0269_[0] ? e_in[317] : e_in[316];
+ assign _0934_ = _0269_[2] ? _0821_ : _0820_;
+ assign _0935_ = _0269_[2] ? _0825_ : _0824_;
+ assign _0936_ = _0270_[0] ? e_in[339] : e_in[338];
+ assign _0937_ = _0270_[0] ? e_in[343] : e_in[342];
+ assign _0774_ = _0169_[1] ? _0886_ : _0834_;
+ assign _0775_ = _0169_[1] ? _0887_ : _0835_;
+ assign _0776_ = _0169_[1] ? _0888_ : _0836_;
+ assign _0777_ = _0169_[1] ? _0889_ : _0837_;
+ assign _0778_ = _0169_[1] ? _0890_ : _0838_;
+ assign _0779_ = _0169_[1] ? _0891_ : _0839_;
+ assign _0780_ = _0169_[1] ? _0892_ : _0840_;
+ assign _0781_ = _0169_[1] ? _0893_ : _0841_;
+ assign _0782_ = _0169_[3] ? _0894_ : _0842_;
+ assign _0783_ = _0169_[3] ? _0895_ : _0843_;
+ assign _0785_ = _0192_[1] ? _0896_ : _0844_;
+ assign _0786_ = _0192_[1] ? _0897_ : _0845_;
+ assign _0787_ = _0192_[1] ? _0898_ : _0846_;
+ assign _0788_ = _0192_[1] ? _0899_ : _0847_;
+ assign _0789_ = _0192_[1] ? _0900_ : _0848_;
+ assign _0790_ = _0192_[1] ? _0901_ : _0849_;
+ assign _0791_ = _0192_[1] ? _0902_ : _0850_;
+ assign _0792_ = _0192_[1] ? _0903_ : _0851_;
+ assign _0793_ = _0192_[3] ? _0904_ : _0852_;
+ assign _0794_ = _0192_[3] ? _0905_ : _0853_;
+ assign _0796_ = _0238_[1] ? _0906_ : _0854_;
+ assign _0797_ = _0238_[1] ? _0907_ : _0855_;
+ assign _0798_ = _0238_[1] ? _0908_ : _0856_;
+ assign _0799_ = _0238_[1] ? _0909_ : _0857_;
+ assign _0800_ = _0238_[1] ? _0910_ : _0858_;
+ assign _0801_ = _0238_[1] ? _0911_ : _0859_;
+ assign _0802_ = _0238_[1] ? _0912_ : _0860_;
+ assign _0803_ = _0238_[1] ? _0913_ : _0861_;
+ assign _0804_ = _0238_[3] ? _0914_ : _0862_;
+ assign _0805_ = _0238_[3] ? _0915_ : _0863_;
+ assign _0807_ = _0268_[1] ? _0916_ : _0864_;
+ assign _0808_ = _0268_[1] ? _0917_ : _0865_;
+ assign _0809_ = _0268_[1] ? _0918_ : _0866_;
+ assign _0810_ = _0268_[1] ? _0919_ : _0867_;
+ assign _0811_ = _0268_[1] ? _0920_ : _0868_;
+ assign _0812_ = _0268_[1] ? _0921_ : _0869_;
+ assign _0813_ = _0268_[1] ? _0922_ : _0870_;
+ assign _0814_ = _0268_[1] ? _0923_ : _0871_;
+ assign _0815_ = _0268_[3] ? _0924_ : _0872_;
+ assign _0816_ = _0268_[3] ? _0925_ : _0873_;
+ assign _0818_ = _0269_[1] ? _0926_ : _0874_;
+ assign _0819_ = _0269_[1] ? _0927_ : _0875_;
+ assign _0820_ = _0269_[1] ? _0928_ : _0876_;
+ assign _0821_ = _0269_[1] ? _0929_ : _0877_;
+ assign _0822_ = _0269_[1] ? _0930_ : _0878_;
+ assign _0823_ = _0269_[1] ? _0931_ : _0879_;
+ assign _0824_ = _0269_[1] ? _0932_ : _0880_;
+ assign _0825_ = _0269_[1] ? _0933_ : _0881_;
+ assign _0826_ = _0269_[3] ? _0934_ : _0882_;
+ assign _0827_ = _0269_[3] ? _0935_ : _0883_;
+ assign _0829_ = _0270_[1] ? _0936_ : _0884_;
+ assign _0830_ = _0270_[1] ? _0937_ : _0885_;
+ assign _0000_ = 1'h1 & e_in[283];
+ assign a_in = _0000_ ? r[72:9] : e_in[154:91];
+ assign _0001_ = 1'h1 & e_in[284];
+ assign b_in = _0001_ ? r[72:9] : e_in[218:155];
+ assign _0002_ = 1'h1 & e_in[285];
+ assign c_in = _0002_ ? r[72:9] : e_in[282:219];
+ assign _0003_ = r[191] & e_in[0];
+ assign _0004_ = ~ _0003_;
+ assign _0005_ = ~ _0011_;
+ assign _0006_ = _0005_ | _0004_;
+ assign _0007_ = rst ? 335'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : { _0736_, _0764_, _0734_[118:72], _0737_, _0734_[7:2], _0738_, _0734_[0], _0763_ };
+ assign _0008_ = rst ? ctrl[127:0] : { _0722_, _0039_ };
+ assign _0009_ = rst ? 65'h08000000000000001 : { _0762_[0], _0729_, _0728_, _0727_, _0726_, _0725_, _0724_, _0723_ };
+ assign _0010_ = rst ? ctrl[320:193] : _0762_[128:1];
+ assign _0011_ = rst ? 1'h0 : 1'h1;
+ always @(posedge clk)
+ _0012_ <= _0006_;
+ always @(posedge clk)
+ r <= _0007_;
+ always @(posedge clk)
+ ctrl <= { _0010_, _0009_, _0008_ };
+ assign _0013_ = r[114] ? r[119:115] : e_in[322:318];
+ assign _0014_ = e_in[334] ? { b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31:0], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31:0] } : { 33'h000000000, b_in[31:0], 33'h000000000, a_in[31:0] };
+ assign _0015_ = e_in[334] ? { b_in[63], b_in, a_in[63], a_in } : { 1'h0, b_in, 1'h0, a_in };
+ assign _0016_ = e_in[333] ? _0014_ : _0015_;
+ assign _0017_ = e_in[333] ? a_in[31] : a_in[63];
+ assign _0018_ = e_in[333] ? b_in[31] : b_in[63];
+ assign _0019_ = e_in[334] ? _0017_ : 1'h0;
+ assign _0020_ = e_in[334] ? _0018_ : 1'h0;
+ assign _0021_ = ~ _0019_;
+ assign _0022_ = - $signed(a_in);
+ assign _0023_ = _0021_ ? a_in : _0022_;
+ assign _0024_ = ~ _0020_;
+ assign _0025_ = - $signed(b_in);
+ assign _0026_ = _0024_ ? b_in : _0025_;
+ assign _0027_ = e_in[8:3] == 6'h27;
+ assign _0028_ = _0027_ ? 1'h1 : 1'h0;
+ assign _0029_ = ~ _0028_;
+ assign _0030_ = _0020_ & _0029_;
+ assign _0031_ = _0019_ ^ _0030_;
+ assign _0032_ = ~ e_in[333];
+ assign _0033_ = e_in[8:3] == 6'h16;
+ assign _0034_ = _0033_ ? 1'h1 : 1'h0;
+ assign _0035_ = e_in[8:3] == 6'h16;
+ assign _0036_ = _0035_ ? { _0023_[31:0], 32'h00000000 } : { 32'h00000000, _0023_[31:0] };
+ assign _0037_ = _0032_ ? { _0026_, _0023_ } : { 32'h00000000, _0026_[31:0], _0036_ };
+ assign _0038_ = _0032_ ? _0034_ : 1'h0;
+ assign _0039_ = ctrl[63:0] + 64'h0000000000000001;
+ assign _0040_ = ctrl[127:64] - 64'h0000000000000001;
+ assign _0041_ = ext_irq_in ? 64'h0000000000000500 : ctrl[256:193];
+ assign _0042_ = ext_irq_in ? 1'h1 : 1'h0;
+ assign _0043_ = ctrl[127] ? 64'h0000000000000900 : _0041_;
+ assign _0044_ = ctrl[127] ? 1'h1 : _0042_;
+ assign _0045_ = ctrl[143] ? _0043_ : ctrl[256:193];
+ assign _0046_ = ctrl[143] ? _0044_ : 1'h0;
+ assign _0047_ = ~ ctrl[142];
+ assign _0048_ = e_in[72:9] + 64'h0000000000000004;
+ assign _0049_ = e_in[8:3] == 6'h38;
+ assign right_shift = _0049_ ? 1'h1 : 1'h0;
+ assign _0050_ = e_in[8:3] == 6'h32;
+ assign _0051_ = e_in[8:3] == 6'h33;
+ assign _0052_ = _0050_ | _0051_;
+ assign rot_clear_left = _0052_ ? 1'h1 : 1'h0;
+ assign _0053_ = e_in[8:3] == 6'h32;
+ assign _0054_ = e_in[8:3] == 6'h34;
+ assign _0055_ = _0053_ | _0054_;
+ assign rot_clear_right = _0055_ ? 1'h1 : 1'h0;
+ assign _0056_ = e_in[8:3] == 6'h18;
+ assign rot_sign_ext = _0056_ ? 1'h1 : 1'h0;
+ assign _0057_ = ctrl[192] == 1'h1;
+ assign _0058_ = _0046_ & e_in[0];
+ assign _0059_ = e_in[0] & ctrl[142];
+ assign _0060_ = 6'h3d - e_in[8:3];
+ assign _0061_ = _0773_ == 1'h1;
+ assign _0062_ = e_in[8:3] == 6'h26;
+ assign _0063_ = e_in[8:3] == 6'h2a;
+ assign _0064_ = _0062_ | _0063_;
+ assign _0065_ = _0064_ ? e_in[355] : 1'h0;
+ assign _0066_ = _0061_ ? 1'h1 : _0065_;
+ assign _0067_ = _0059_ & _0066_;
+ assign _0068_ = e_in[2:1] == 2'h1;
+ assign _0069_ = e_in[0] & _0068_;
+ assign _0070_ = e_in[8:3] == 6'h00;
+ assign _0071_ = e_in[336] ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h00, ctrl[143:128], 64'h0000000000000c00 } : { ctrl[320:257], _0045_ };
+ assign _0072_ = e_in[336] ? 1'h1 : 1'h0;
+ assign _0073_ = e_in[336] ? 1'h1 : 1'h0;
+ assign _0074_ = e_in[336] ? 1'h0 : 1'h1;
+ assign _0075_ = e_in[8:3] == 6'h35;
+ assign _0076_ = e_in[345:336] == 10'h100;
+ assign _0077_ = _0076_ ? 1'h1 : 1'h0;
+ assign _0078_ = _0076_ ? 1'h0 : 1'h1;
+ assign _0079_ = e_in[8:3] == 6'h04;
+ assign _0080_ = e_in[8:3] == 6'h01;
+ assign _0081_ = ~ e_in[326];
+ assign _0082_ = ~ a_in;
+ assign _0083_ = _0081_ ? a_in : _0082_;
+ assign _0084_ = e_in[329:328] == 2'h0;
+ assign _0085_ = e_in[329:328] == 2'h1;
+ assign _0086_ = e_in[329:328] == 2'h2;
+ function [0:0] \5155 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \5155 = b[0:0];
+ 3'b?1?:
+ \5155 = b[1:1];
+ 3'b1??:
+ \5155 = b[2:2];
+ default:
+ \5155 = a;
+ endcase
+ endfunction
+ assign _0087_ = \5155 (1'hx, { 1'h1, _0013_[0], 1'h0 }, { _0086_, _0085_, _0084_ });
+ assign _0088_ = { 1'h0, _0083_ } + { 1'h0, b_in };
+ assign _0089_ = _0088_ + { 64'h0000000000000000, _0087_ };
+ assign _0090_ = _0089_[32] ^ _0083_[32];
+ assign _0091_ = _0090_ ^ b_in[32];
+ assign _0092_ = e_in[8:3] == 6'h02;
+ assign _0093_ = e_in[330] ? { e_in[72:9], 7'h44, _0013_[4:2], _0091_, _0089_[64], 106'h200000000000000000000000000, e_in[78:73], 3'h1 } : { e_in[72:9], 7'h44, _0013_, 106'h000000000000000000000000000, e_in[78:73], 3'h1 };
+ assign _0094_ = _0089_[64] ^ _0089_[63];
+ assign _0095_ = _0083_[63] ^ b_in[63];
+ assign _0096_ = ~ _0095_;
+ assign _0097_ = _0094_ & _0096_;
+ assign _0098_ = _0091_ ^ _0089_[31];
+ assign _0099_ = _0083_[31] ^ b_in[31];
+ assign _0100_ = ~ _0099_;
+ assign _0101_ = _0098_ & _0100_;
+ assign _0102_ = _0097_ ? 1'h1 : _0093_[119];
+ assign _0103_ = e_in[325] ? { _0093_[190:120], _0102_, _0101_, _0097_, _0093_[116:115], 1'h1, _0093_[113:0] } : _0093_;
+ assign _0104_ = e_in[8:3] == 6'h09;
+ assign _0105_ = ~ e_in[333];
+ assign _0106_ = _0104_ ? e_in[356] : _0105_;
+ assign _0107_ = a_in[31:0] ^ b_in[31:0];
+ assign _0108_ = | _0107_;
+ assign _0109_ = ~ _0108_;
+ assign _0110_ = a_in[63:32] ^ b_in[63:32];
+ assign _0111_ = | _0110_;
+ assign _0112_ = ~ _0111_;
+ assign _0113_ = ~ _0106_;
+ assign _0114_ = _0113_ | _0112_;
+ assign _0115_ = _0109_ & _0114_;
+ assign _0116_ = _0106_ ? a_in[63] : a_in[31];
+ assign _0117_ = _0106_ ? b_in[63] : b_in[31];
+ assign _0118_ = _0116_ != _0117_;
+ assign _0119_ = ~ _0106_;
+ assign _0120_ = _0119_ & _0091_;
+ assign _0121_ = _0106_ & _0089_[64];
+ assign _0122_ = _0120_ | _0121_;
+ assign _0123_ = ~ _0122_;
+ assign _0124_ = ~ _0122_;
+ assign _0125_ = _0118_ ? { _0116_, _0117_, 1'h0, _0117_, _0116_ } : { _0122_, _0123_, 1'h0, _0122_, _0124_ };
+ assign _0126_ = _0115_ ? 5'h04 : _0125_;
+ assign _0127_ = e_in[8:3] == 6'h09;
+ assign _0128_ = e_in[334] ? { _0126_[4:2], _0013_[4] } : { _0126_[1:0], _0126_[2], _0013_[4] };
+ assign _0129_ = e_in[360:358] == 3'h0;
+ assign _0130_ = e_in[360:358] == 3'h1;
+ assign _0131_ = e_in[360:358] == 3'h2;
+ assign _0132_ = e_in[360:358] == 3'h3;
+ assign _0133_ = e_in[360:358] == 3'h4;
+ assign _0134_ = e_in[360:358] == 3'h5;
+ assign _0135_ = e_in[360:358] == 3'h6;
+ assign _0136_ = e_in[360:358] == 3'h7;
+ function [7:0] \5353 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \5353 = b[7:0];
+ 8'b??????1?:
+ \5353 = b[15:8];
+ 8'b?????1??:
+ \5353 = b[23:16];
+ 8'b????1???:
+ \5353 = b[31:24];
+ 8'b???1????:
+ \5353 = b[39:32];
+ 8'b??1?????:
+ \5353 = b[47:40];
+ 8'b?1??????:
+ \5353 = b[55:48];
+ 8'b1???????:
+ \5353 = b[63:56];
+ default:
+ \5353 = a;
+ endcase
+ endfunction
+ assign _0137_ = \5353 (8'h00, 64'h0102040810204080, { _0136_, _0135_, _0134_, _0133_, _0132_, _0131_, _0130_, _0129_ });
+ assign _0138_ = _0126_ & e_in[360:356];
+ assign _0139_ = | _0138_;
+ assign _0140_ = _0139_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h02, ctrl[143:128], 64'h0000000000000700 } : { ctrl[320:257], _0045_ };
+ assign _0141_ = _0139_ ? 1'h1 : 1'h0;
+ assign _0142_ = _0127_ ? { ctrl[320:257], _0045_ } : _0140_;
+ assign _0143_ = _0127_ ? { _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0128_, _0137_, 1'h1 } : 41'h00000000000;
+ assign _0144_ = _0127_ ? 1'h0 : _0141_;
+ assign _0145_ = _0092_ ? { ctrl[320:257], _0045_ } : _0142_;
+ assign _0146_ = _0092_ ? _0103_[72:0] : { 64'h0000000000000000, e_in[78:73], 3'h1 };
+ assign _0147_ = _0092_ ? _0103_[113:73] : _0143_;
+ assign _0148_ = _0092_ ? _0103_[190:114] : { e_in[72:9], 7'h44, _0013_, 1'h0 };
+ assign _0149_ = _0092_ ? 1'h1 : 1'h0;
+ assign _0150_ = _0092_ ? 1'h0 : _0144_;
+ assign _0151_ = e_in[8:3] == 6'h02;
+ assign _0152_ = e_in[8:3] == 6'h09;
+ assign _0153_ = _0151_ | _0152_;
+ assign _0154_ = e_in[8:3] == 6'h3b;
+ assign _0155_ = _0153_ | _0154_;
+ assign _0156_ = e_in[8:3] == 6'h03;
+ assign _0157_ = e_in[8:3] == 6'h2e;
+ assign _0158_ = _0156_ | _0157_;
+ assign _0159_ = e_in[8:3] == 6'h3c;
+ assign _0160_ = _0158_ | _0159_;
+ assign _0161_ = e_in[72:9] + b_in;
+ assign _0162_ = e_in[336] ? b_in : _0161_;
+ assign _0163_ = e_in[8:3] == 6'h05;
+ assign _0164_ = ~ e_in[358];
+ assign _0165_ = a_in - 64'h0000000000000001;
+ assign _0166_ = _0164_ ? 6'h21 : e_in[78:73];
+ assign _0167_ = _0164_ ? _0165_ : 64'h0000000000000000;
+ assign _0168_ = _0164_ ? 1'h1 : 1'h0;
+ assign _0169_ = 32'd31 - { 27'h0000000, e_in[355:351] };
+ assign _0170_ = _0784_ == e_in[359];
+ assign _0171_ = _0170_ ? 1'h1 : 1'h0;
+ assign _0172_ = a_in != 64'h0000000000000001;
+ assign _0173_ = _0172_ ? 1'h1 : 1'h0;
+ assign _0174_ = _0173_ ^ e_in[357];
+ assign _0175_ = e_in[358] | _0174_;
+ assign _0176_ = e_in[360] | _0171_;
+ assign _0177_ = _0175_ & _0176_;
+ assign _0178_ = _0177_ ? 32'd1 : 32'd0;
+ assign _0179_ = _0178_ == 32'd1;
+ assign _0180_ = e_in[72:9] + b_in;
+ assign _0181_ = e_in[336] ? b_in : _0180_;
+ assign _0182_ = _0179_ ? 1'h1 : 1'h0;
+ assign _0183_ = _0179_ ? _0181_ : 64'h0000000000000000;
+ assign _0184_ = e_in[8:3] == 6'h06;
+ assign _0185_ = ~ e_in[358];
+ assign _0186_ = ~ e_in[345];
+ assign _0187_ = _0185_ & _0186_;
+ assign _0188_ = a_in - 64'h0000000000000001;
+ assign _0189_ = _0187_ ? 6'h21 : e_in[78:73];
+ assign _0190_ = _0187_ ? _0188_ : 64'h0000000000000000;
+ assign _0191_ = _0187_ ? 1'h1 : 1'h0;
+ assign _0192_ = 32'd31 - { 27'h0000000, e_in[355:351] };
+ assign _0193_ = _0795_ == e_in[359];
+ assign _0194_ = _0193_ ? 1'h1 : 1'h0;
+ assign _0195_ = a_in != 64'h0000000000000001;
+ assign _0196_ = _0195_ ? 1'h1 : 1'h0;
+ assign _0197_ = _0196_ ^ e_in[357];
+ assign _0198_ = e_in[358] | _0197_;
+ assign _0199_ = e_in[360] | _0194_;
+ assign _0200_ = _0198_ & _0199_;
+ assign _0201_ = _0200_ ? 32'd1 : 32'd0;
+ assign _0202_ = _0201_ == 32'd1;
+ assign _0203_ = _0202_ ? 1'h1 : 1'h0;
+ assign _0204_ = _0202_ ? { b_in[63:2], 2'h0 } : 64'h0000000000000000;
+ assign _0205_ = e_in[8:3] == 6'h07;
+ assign _0206_ = b_in[5] | b_in[14];
+ assign _0207_ = ~ b_in[14];
+ assign _0208_ = b_in[14] ? 2'h3 : b_in[5:4];
+ assign _0209_ = b_in[14] ? 1'h1 : b_in[15];
+ assign _0210_ = e_in[8:3] == 6'h31;
+ assign _0211_ = c_in[7:0] == b_in[7:0];
+ assign _0212_ = _0211_ ? 8'hff : 8'h00;
+ assign _0213_ = c_in[15:8] == b_in[15:8];
+ assign _0214_ = _0213_ ? 8'hff : 8'h00;
+ assign _0215_ = c_in[23:16] == b_in[23:16];
+ assign _0216_ = _0215_ ? 8'hff : 8'h00;
+ assign _0217_ = c_in[31:24] == b_in[31:24];
+ assign _0218_ = _0217_ ? 8'hff : 8'h00;
+ assign _0219_ = c_in[39:32] == b_in[39:32];
+ assign _0220_ = _0219_ ? 8'hff : 8'h00;
+ assign _0221_ = c_in[47:40] == b_in[47:40];
+ assign _0222_ = _0221_ ? 8'hff : 8'h00;
+ assign _0223_ = c_in[55:48] == b_in[55:48];
+ assign _0224_ = _0223_ ? 8'hff : 8'h00;
+ assign _0225_ = c_in[63:56] == b_in[63:56];
+ assign _0226_ = _0225_ ? 8'hff : 8'h00;
+ assign _0227_ = e_in[8:3] == 6'h0a;
+ assign _0228_ = e_in[8:3] == 6'h0d;
+ assign _0229_ = e_in[367] & c_in[7];
+ assign _0230_ = e_in[368] & c_in[15];
+ assign _0231_ = _0229_ | _0230_;
+ assign _0232_ = e_in[369] & c_in[31];
+ assign _0233_ = _0231_ | _0232_;
+ assign _0234_ = e_in[369] ? c_in[31:16] : { _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_ };
+ assign _0235_ = e_in[369] | e_in[368];
+ assign _0236_ = _0235_ ? c_in[15:8] : { _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_ };
+ assign _0237_ = e_in[8:3] == 6'h17;
+ assign _0238_ = 32'd31 - { 27'h0000000, e_in[345:341] };
+ assign _0239_ = _0806_ ? a_in : b_in;
+ assign _0240_ = e_in[8:3] == 6'h1b;
+ assign _0241_ = ~ e_in[336];
+ assign _0242_ = e_in[360:358] == 3'h0;
+ assign _0243_ = e_in[360:358] == 3'h1;
+ assign _0244_ = e_in[360:358] == 3'h2;
+ assign _0245_ = e_in[360:358] == 3'h3;
+ assign _0246_ = e_in[360:358] == 3'h4;
+ assign _0247_ = e_in[360:358] == 3'h5;
+ assign _0248_ = e_in[360:358] == 3'h6;
+ assign _0249_ = e_in[360:358] == 3'h7;
+ function [7:0] \5912 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \5912 = b[7:0];
+ 8'b??????1?:
+ \5912 = b[15:8];
+ 8'b?????1??:
+ \5912 = b[23:16];
+ 8'b????1???:
+ \5912 = b[31:24];
+ 8'b???1????:
+ \5912 = b[39:32];
+ 8'b??1?????:
+ \5912 = b[47:40];
+ 8'b?1??????:
+ \5912 = b[55:48];
+ 8'b1???????:
+ \5912 = b[63:56];
+ default:
+ \5912 = a;
+ endcase
+ endfunction
+ assign _0250_ = \5912 (8'h00, 64'h0102040810204080, { _0249_, _0248_, _0247_, _0246_, _0245_, _0244_, _0243_, _0242_ });
+ assign _0251_ = 32'd0 == { 29'h00000000, e_in[355:353] };
+ assign _0252_ = _0251_ ? e_in[317:314] : 4'h0;
+ assign _0253_ = 32'd1 == { 29'h00000000, e_in[355:353] };
+ assign _0254_ = _0253_ ? e_in[313:310] : _0252_;
+ assign _0255_ = 32'd2 == { 29'h00000000, e_in[355:353] };
+ assign _0256_ = _0255_ ? e_in[309:306] : _0254_;
+ assign _0257_ = 32'd3 == { 29'h00000000, e_in[355:353] };
+ assign _0258_ = _0257_ ? e_in[305:302] : _0256_;
+ assign _0259_ = 32'd4 == { 29'h00000000, e_in[355:353] };
+ assign _0260_ = _0259_ ? e_in[301:298] : _0258_;
+ assign _0261_ = 32'd5 == { 29'h00000000, e_in[355:353] };
+ assign _0262_ = _0261_ ? e_in[297:294] : _0260_;
+ assign _0263_ = 32'd6 == { 29'h00000000, e_in[355:353] };
+ assign _0264_ = _0263_ ? e_in[293:290] : _0262_;
+ assign _0265_ = 32'd7 == { 29'h00000000, e_in[355:353] };
+ assign _0266_ = _0265_ ? e_in[289:286] : _0264_;
+ assign _0267_ = 32'd31 - { 27'h0000000, e_in[360:356] };
+ assign _0268_ = 32'd31 - { 27'h0000000, e_in[355:351] };
+ assign _0269_ = 32'd31 - { 27'h0000000, e_in[350:346] };
+ assign _0270_ = 32'd5 + { 30'h00000000, _0817_, _0828_ };
+ assign _0271_ = 32'd31 - { 27'h0000000, _0267_[4:0] };
+ assign _0272_ = $signed(_0271_) / $signed(32'd4);
+ assign _0273_ = _0272_[2:0] == 3'h0;
+ assign _0274_ = _0272_[2:0] == 3'h1;
+ assign _0275_ = _0272_[2:0] == 3'h2;
+ assign _0276_ = _0272_[2:0] == 3'h3;
+ assign _0277_ = _0272_[2:0] == 3'h4;
+ assign _0278_ = _0272_[2:0] == 3'h5;
+ assign _0279_ = _0272_[2:0] == 3'h6;
+ assign _0280_ = _0272_[2:0] == 3'h7;
+ function [7:0] \6042 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \6042 = b[7:0];
+ 8'b??????1?:
+ \6042 = b[15:8];
+ 8'b?????1??:
+ \6042 = b[23:16];
+ 8'b????1???:
+ \6042 = b[31:24];
+ 8'b???1????:
+ \6042 = b[39:32];
+ 8'b??1?????:
+ \6042 = b[47:40];
+ 8'b?1??????:
+ \6042 = b[55:48];
+ 8'b1???????:
+ \6042 = b[63:56];
+ default:
+ \6042 = a;
+ endcase
+ endfunction
+ assign _0281_ = \6042 (8'h00, 64'h0102040810204080, { _0280_, _0279_, _0278_, _0277_, _0276_, _0275_, _0274_, _0273_ });
+ assign _0282_ = 32'd0 == { 27'h0000000, _0267_[4:0] };
+ assign _0283_ = _0282_ ? _0833_ : e_in[286];
+ assign _0284_ = 32'd1 == { 27'h0000000, _0267_[4:0] };
+ assign _0285_ = _0284_ ? _0833_ : e_in[287];
+ assign _0286_ = 32'd2 == { 27'h0000000, _0267_[4:0] };
+ assign _0287_ = _0286_ ? _0833_ : e_in[288];
+ assign _0288_ = 32'd3 == { 27'h0000000, _0267_[4:0] };
+ assign _0289_ = _0288_ ? _0833_ : e_in[289];
+ assign _0290_ = 32'd4 == { 27'h0000000, _0267_[4:0] };
+ assign _0291_ = _0290_ ? _0833_ : e_in[290];
+ assign _0292_ = 32'd5 == { 27'h0000000, _0267_[4:0] };
+ assign _0293_ = _0292_ ? _0833_ : e_in[291];
+ assign _0294_ = 32'd6 == { 27'h0000000, _0267_[4:0] };
+ assign _0295_ = _0294_ ? _0833_ : e_in[292];
+ assign _0296_ = 32'd7 == { 27'h0000000, _0267_[4:0] };
+ assign _0297_ = _0296_ ? _0833_ : e_in[293];
+ assign _0298_ = 32'd8 == { 27'h0000000, _0267_[4:0] };
+ assign _0299_ = _0298_ ? _0833_ : e_in[294];
+ assign _0300_ = 32'd9 == { 27'h0000000, _0267_[4:0] };
+ assign _0301_ = _0300_ ? _0833_ : e_in[295];
+ assign _0302_ = 32'd10 == { 27'h0000000, _0267_[4:0] };
+ assign _0303_ = _0302_ ? _0833_ : e_in[296];
+ assign _0304_ = 32'd11 == { 27'h0000000, _0267_[4:0] };
+ assign _0305_ = _0304_ ? _0833_ : e_in[297];
+ assign _0306_ = 32'd12 == { 27'h0000000, _0267_[4:0] };
+ assign _0307_ = _0306_ ? _0833_ : e_in[298];
+ assign _0308_ = 32'd13 == { 27'h0000000, _0267_[4:0] };
+ assign _0309_ = _0308_ ? _0833_ : e_in[299];
+ assign _0310_ = 32'd14 == { 27'h0000000, _0267_[4:0] };
+ assign _0311_ = _0310_ ? _0833_ : e_in[300];
+ assign _0312_ = 32'd15 == { 27'h0000000, _0267_[4:0] };
+ assign _0313_ = _0312_ ? _0833_ : e_in[301];
+ assign _0314_ = 32'd16 == { 27'h0000000, _0267_[4:0] };
+ assign _0315_ = _0314_ ? _0833_ : e_in[302];
+ assign _0316_ = 32'd17 == { 27'h0000000, _0267_[4:0] };
+ assign _0317_ = _0316_ ? _0833_ : e_in[303];
+ assign _0318_ = 32'd18 == { 27'h0000000, _0267_[4:0] };
+ assign _0319_ = _0318_ ? _0833_ : e_in[304];
+ assign _0320_ = 32'd19 == { 27'h0000000, _0267_[4:0] };
+ assign _0321_ = _0320_ ? _0833_ : e_in[305];
+ assign _0322_ = 32'd20 == { 27'h0000000, _0267_[4:0] };
+ assign _0323_ = _0322_ ? _0833_ : e_in[306];
+ assign _0324_ = 32'd21 == { 27'h0000000, _0267_[4:0] };
+ assign _0325_ = _0324_ ? _0833_ : e_in[307];
+ assign _0326_ = 32'd22 == { 27'h0000000, _0267_[4:0] };
+ assign _0327_ = _0326_ ? _0833_ : e_in[308];
+ assign _0328_ = 32'd23 == { 27'h0000000, _0267_[4:0] };
+ assign _0329_ = _0328_ ? _0833_ : e_in[309];
+ assign _0330_ = 32'd24 == { 27'h0000000, _0267_[4:0] };
+ assign _0331_ = _0330_ ? _0833_ : e_in[310];
+ assign _0332_ = 32'd25 == { 27'h0000000, _0267_[4:0] };
+ assign _0333_ = _0332_ ? _0833_ : e_in[311];
+ assign _0334_ = 32'd26 == { 27'h0000000, _0267_[4:0] };
+ assign _0335_ = _0334_ ? _0833_ : e_in[312];
+ assign _0336_ = 32'd27 == { 27'h0000000, _0267_[4:0] };
+ assign _0337_ = _0336_ ? _0833_ : e_in[313];
+ assign _0338_ = 32'd28 == { 27'h0000000, _0267_[4:0] };
+ assign _0339_ = _0338_ ? _0833_ : e_in[314];
+ assign _0340_ = 32'd29 == { 27'h0000000, _0267_[4:0] };
+ assign _0341_ = _0340_ ? _0833_ : e_in[315];
+ assign _0342_ = 32'd30 == { 27'h0000000, _0267_[4:0] };
+ assign _0343_ = _0342_ ? _0833_ : e_in[316];
+ assign _0344_ = 32'd31 == { 27'h0000000, _0267_[4:0] };
+ assign _0345_ = _0344_ ? _0833_ : e_in[317];
+ assign _0346_ = _0241_ ? { _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0266_, _0250_, 1'h1 } : { _0345_, _0343_, _0341_, _0339_, _0337_, _0335_, _0333_, _0331_, _0329_, _0327_, _0325_, _0323_, _0321_, _0319_, _0317_, _0315_, _0313_, _0311_, _0309_, _0307_, _0305_, _0303_, _0301_, _0299_, _0297_, _0295_, _0293_, _0291_, _0289_, _0287_, _0285_, _0283_, _0281_, 1'h1 };
+ assign _0347_ = e_in[8:3] == 6'h0e;
+ assign _0348_ = e_in[8:3] == 6'h25;
+ assign _0349_ = { 22'h000000, e_in[350:346], e_in[355:351] } == 32'd1;
+ assign _0350_ = _0349_ ? { 32'h00000000, _0013_[4], _0013_[2], _0013_[0], 9'h000, _0013_[3], _0013_[1] } : a_in[63:18];
+ assign _0351_ = { e_in[350:346], e_in[355:351] } == 10'h10c;
+ assign _0352_ = { e_in[350:346], e_in[355:351] } == 10'h016;
+ assign _0353_ = ctrl[142] ? 1'h1 : 1'h0;
+ function [63:0] \6311 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \6311 = b[63:0];
+ 2'b1?:
+ \6311 = b[127:64];
+ default:
+ \6311 = a;
+ endcase
+ endfunction
+ assign _0354_ = \6311 (c_in, ctrl[127:0], { _0352_, _0351_ });
+ function [0:0] \6313 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \6313 = b[0:0];
+ 2'b1?:
+ \6313 = b[1:1];
+ default:
+ \6313 = a;
+ endcase
+ endfunction
+ assign _0355_ = \6313 (_0353_, 2'h0, { _0352_, _0351_ });
+ assign _0356_ = e_in[84] ? { _0350_, a_in[17:0] } : _0354_;
+ assign _0357_ = e_in[84] ? 1'h0 : _0355_;
+ assign _0358_ = e_in[8:3] == 6'h26;
+ assign _0359_ = ~ e_in[355];
+ assign _0360_ = e_in[354] ? 1'h0 : 1'h1;
+ assign _0361_ = e_in[354] ? 1'h0 : 1'h1;
+ assign _0362_ = e_in[354] ? 3'h0 : 3'hx;
+ assign _0363_ = _0369_ ? 1'h0 : _0360_;
+ assign _0364_ = _0370_ ? 1'h0 : _0361_;
+ assign _0365_ = _0371_ ? 3'h1 : _0362_;
+ assign _0366_ = e_in[353] & _0360_;
+ assign _0367_ = e_in[353] & _0360_;
+ assign _0368_ = e_in[353] & _0360_;
+ assign _0369_ = _0360_ & _0366_;
+ assign _0370_ = _0360_ & _0367_;
+ assign _0371_ = _0360_ & _0368_;
+ assign _0372_ = _0378_ ? 1'h0 : _0363_;
+ assign _0373_ = _0379_ ? 1'h0 : _0364_;
+ assign _0374_ = _0380_ ? 3'h2 : _0365_;
+ assign _0375_ = e_in[352] & _0363_;
+ assign _0376_ = e_in[352] & _0363_;
+ assign _0377_ = e_in[352] & _0363_;
+ assign _0378_ = _0363_ & _0375_;
+ assign _0379_ = _0363_ & _0376_;
+ assign _0380_ = _0363_ & _0377_;
+ assign _0381_ = _0387_ ? 1'h0 : _0372_;
+ assign _0382_ = _0388_ ? 1'h0 : _0373_;
+ assign _0383_ = _0389_ ? 3'h3 : _0374_;
+ assign _0384_ = e_in[351] & _0372_;
+ assign _0385_ = e_in[351] & _0372_;
+ assign _0386_ = e_in[351] & _0372_;
+ assign _0387_ = _0372_ & _0384_;
+ assign _0388_ = _0372_ & _0385_;
+ assign _0389_ = _0372_ & _0386_;
+ assign _0390_ = _0396_ ? 1'h0 : _0381_;
+ assign _0391_ = _0397_ ? 1'h0 : _0382_;
+ assign _0392_ = _0398_ ? 3'h4 : _0383_;
+ assign _0393_ = e_in[350] & _0381_;
+ assign _0394_ = e_in[350] & _0381_;
+ assign _0395_ = e_in[350] & _0381_;
+ assign _0396_ = _0381_ & _0393_;
+ assign _0397_ = _0381_ & _0394_;
+ assign _0398_ = _0381_ & _0395_;
+ assign _0399_ = _0405_ ? 1'h0 : _0390_;
+ assign _0400_ = _0406_ ? 1'h0 : _0391_;
+ assign _0401_ = _0407_ ? 3'h5 : _0392_;
+ assign _0402_ = e_in[349] & _0390_;
+ assign _0403_ = e_in[349] & _0390_;
+ assign _0404_ = e_in[349] & _0390_;
+ assign _0405_ = _0390_ & _0402_;
+ assign _0406_ = _0390_ & _0403_;
+ assign _0407_ = _0390_ & _0404_;
+ assign _0408_ = _0414_ ? 1'h0 : _0399_;
+ assign _0409_ = _0415_ ? 1'h0 : _0400_;
+ assign _0410_ = _0416_ ? 3'h6 : _0401_;
+ assign _0411_ = e_in[348] & _0399_;
+ assign _0412_ = e_in[348] & _0399_;
+ assign _0413_ = e_in[348] & _0399_;
+ assign _0414_ = _0399_ & _0411_;
+ assign _0415_ = _0399_ & _0412_;
+ assign _0416_ = _0399_ & _0413_;
+ assign _0417_ = _0421_ ? 1'h0 : _0409_;
+ assign _0418_ = _0422_ ? 3'h7 : _0410_;
+ assign _0419_ = e_in[347] & _0408_;
+ assign _0420_ = e_in[347] & _0408_;
+ assign _0421_ = _0408_ & _0419_;
+ assign _0422_ = _0408_ & _0420_;
+ assign _0423_ = _0417_ ? 3'h7 : _0418_;
+ assign _0424_ = { 29'h00000000, _0423_ } == 32'd0;
+ assign _0425_ = _0424_ ? e_in[317:314] : 4'h0;
+ assign _0426_ = { 29'h00000000, _0423_ } == 32'd1;
+ assign _0427_ = _0426_ ? e_in[313:310] : 4'h0;
+ assign _0428_ = { 29'h00000000, _0423_ } == 32'd2;
+ assign _0429_ = _0428_ ? e_in[309:306] : 4'h0;
+ assign _0430_ = { 29'h00000000, _0423_ } == 32'd3;
+ assign _0431_ = _0430_ ? e_in[305:302] : 4'h0;
+ assign _0432_ = { 29'h00000000, _0423_ } == 32'd4;
+ assign _0433_ = _0432_ ? e_in[301:298] : 4'h0;
+ assign _0434_ = { 29'h00000000, _0423_ } == 32'd5;
+ assign _0435_ = _0434_ ? e_in[297:294] : 4'h0;
+ assign _0436_ = { 29'h00000000, _0423_ } == 32'd6;
+ assign _0437_ = _0436_ ? e_in[293:290] : 4'h0;
+ assign _0438_ = { 29'h00000000, _0423_ } == 32'd7;
+ assign _0439_ = _0438_ ? e_in[289:286] : 4'h0;
+ assign _0440_ = _0359_ ? { 32'h00000000, e_in[317:286] } : { 32'h00000000, _0425_, _0427_, _0429_, _0431_, _0433_, _0435_, _0437_, _0439_ };
+ assign _0441_ = e_in[8:3] == 6'h24;
+ assign _0442_ = ~ e_in[355];
+ assign _0443_ = e_in[354] ? 1'h0 : 1'h1;
+ assign _0444_ = e_in[354] ? 1'h0 : 1'h1;
+ assign _0445_ = e_in[354] ? 3'h0 : 3'hx;
+ assign _0446_ = _0452_ ? 1'h0 : _0443_;
+ assign _0447_ = _0453_ ? 1'h0 : _0444_;
+ assign _0448_ = _0454_ ? 3'h1 : _0445_;
+ assign _0449_ = e_in[353] & _0443_;
+ assign _0450_ = e_in[353] & _0443_;
+ assign _0451_ = e_in[353] & _0443_;
+ assign _0452_ = _0443_ & _0449_;
+ assign _0453_ = _0443_ & _0450_;
+ assign _0454_ = _0443_ & _0451_;
+ assign _0455_ = _0461_ ? 1'h0 : _0446_;
+ assign _0456_ = _0462_ ? 1'h0 : _0447_;
+ assign _0457_ = _0463_ ? 3'h2 : _0448_;
+ assign _0458_ = e_in[352] & _0446_;
+ assign _0459_ = e_in[352] & _0446_;
+ assign _0460_ = e_in[352] & _0446_;
+ assign _0461_ = _0446_ & _0458_;
+ assign _0462_ = _0446_ & _0459_;
+ assign _0463_ = _0446_ & _0460_;
+ assign _0464_ = _0470_ ? 1'h0 : _0455_;
+ assign _0465_ = _0471_ ? 1'h0 : _0456_;
+ assign _0466_ = _0472_ ? 3'h3 : _0457_;
+ assign _0467_ = e_in[351] & _0455_;
+ assign _0468_ = e_in[351] & _0455_;
+ assign _0469_ = e_in[351] & _0455_;
+ assign _0470_ = _0455_ & _0467_;
+ assign _0471_ = _0455_ & _0468_;
+ assign _0472_ = _0455_ & _0469_;
+ assign _0473_ = _0479_ ? 1'h0 : _0464_;
+ assign _0474_ = _0480_ ? 1'h0 : _0465_;
+ assign _0475_ = _0481_ ? 3'h4 : _0466_;
+ assign _0476_ = e_in[350] & _0464_;
+ assign _0477_ = e_in[350] & _0464_;
+ assign _0478_ = e_in[350] & _0464_;
+ assign _0479_ = _0464_ & _0476_;
+ assign _0480_ = _0464_ & _0477_;
+ assign _0481_ = _0464_ & _0478_;
+ assign _0482_ = _0488_ ? 1'h0 : _0473_;
+ assign _0483_ = _0489_ ? 1'h0 : _0474_;
+ assign _0484_ = _0490_ ? 3'h5 : _0475_;
+ assign _0485_ = e_in[349] & _0473_;
+ assign _0486_ = e_in[349] & _0473_;
+ assign _0487_ = e_in[349] & _0473_;
+ assign _0488_ = _0473_ & _0485_;
+ assign _0489_ = _0473_ & _0486_;
+ assign _0490_ = _0473_ & _0487_;
+ assign _0491_ = _0497_ ? 1'h0 : _0482_;
+ assign _0492_ = _0498_ ? 1'h0 : _0483_;
+ assign _0493_ = _0499_ ? 3'h6 : _0484_;
+ assign _0494_ = e_in[348] & _0482_;
+ assign _0495_ = e_in[348] & _0482_;
+ assign _0496_ = e_in[348] & _0482_;
+ assign _0497_ = _0482_ & _0494_;
+ assign _0498_ = _0482_ & _0495_;
+ assign _0499_ = _0482_ & _0496_;
+ assign _0500_ = _0504_ ? 1'h0 : _0492_;
+ assign _0501_ = _0505_ ? 3'h7 : _0493_;
+ assign _0502_ = e_in[347] & _0491_;
+ assign _0503_ = e_in[347] & _0491_;
+ assign _0504_ = _0491_ & _0502_;
+ assign _0505_ = _0491_ & _0503_;
+ assign _0506_ = _0500_ ? 3'h7 : _0501_;
+ assign _0507_ = _0506_ == 3'h0;
+ assign _0508_ = _0506_ == 3'h1;
+ assign _0509_ = _0506_ == 3'h2;
+ assign _0510_ = _0506_ == 3'h3;
+ assign _0511_ = _0506_ == 3'h4;
+ assign _0512_ = _0506_ == 3'h5;
+ assign _0513_ = _0506_ == 3'h6;
+ assign _0514_ = _0506_ == 3'h7;
+ function [7:0] \6671 ;
+ input [7:0] a;
+ input [63:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \6671 = b[7:0];
+ 8'b??????1?:
+ \6671 = b[15:8];
+ 8'b?????1??:
+ \6671 = b[23:16];
+ 8'b????1???:
+ \6671 = b[31:24];
+ 8'b???1????:
+ \6671 = b[39:32];
+ 8'b??1?????:
+ \6671 = b[47:40];
+ 8'b?1??????:
+ \6671 = b[55:48];
+ 8'b1???????:
+ \6671 = b[63:56];
+ default:
+ \6671 = a;
+ endcase
+ endfunction
+ assign _0515_ = \6671 (8'h00, 64'h0102040810204080, { _0514_, _0513_, _0512_, _0511_, _0510_, _0509_, _0508_, _0507_ });
+ assign _0516_ = _0442_ ? e_in[354:347] : _0515_;
+ assign _0517_ = e_in[8:3] == 6'h28;
+ assign _0518_ = c_in[14] ? 2'h3 : c_in[5:4];
+ assign _0519_ = c_in[14] ? 1'h1 : c_in[15];
+ assign _0520_ = e_in[351] ? c_in[1] : c_in[1];
+ assign _0521_ = e_in[351] ? ctrl[139:130] : { c_in[11:6], _0518_, c_in[3:2] };
+ assign _0522_ = e_in[351] ? ctrl[142:141] : c_in[14:13];
+ assign _0523_ = e_in[351] ? c_in[15] : _0519_;
+ assign _0524_ = e_in[351] ? ctrl[187:144] : c_in[59:16];
+ assign _0525_ = e_in[351] ? ctrl[191:189] : c_in[63:61];
+ assign _0526_ = e_in[8:3] == 6'h29;
+ assign _0527_ = { 22'h000000, e_in[350:346], e_in[355:351] } == 32'd1;
+ assign _0528_ = _0527_ ? { c_in[31], c_in[19], c_in[30], c_in[18], c_in[29], 1'h1 } : { _0013_, 1'h0 };
+ assign _0529_ = { e_in[350:346], e_in[355:351] } == 10'h016;
+ assign _0530_ = ctrl[142] ? 1'h1 : 1'h0;
+ function [63:0] \6761 ;
+ input [63:0] a;
+ input [63:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \6761 = b[63:0];
+ default:
+ \6761 = a;
+ endcase
+ endfunction
+ assign _0531_ = \6761 (_0040_, c_in, _0529_);
+ function [0:0] \6763 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \6763 = b[0:0];
+ default:
+ \6763 = a;
+ endcase
+ endfunction
+ assign _0532_ = \6763 (_0530_, 1'h0, _0529_);
+ assign _0533_ = e_in[78] ? _0040_ : _0531_;
+ assign _0534_ = e_in[78] ? _0528_ : { _0013_, 1'h0 };
+ assign _0535_ = e_in[78] ? c_in : 64'h0000000000000000;
+ assign _0536_ = e_in[78] ? 1'h1 : 1'h0;
+ assign _0537_ = e_in[78] ? 1'h0 : _0532_;
+ assign _0538_ = e_in[8:3] == 6'h2a;
+ assign _0539_ = e_in[8:3] == 6'h2f;
+ assign _0540_ = e_in[8:3] == 6'h30;
+ assign _0541_ = e_in[330] ? { e_in[72:9], 7'h44, _0013_[4:2], rotator_carry, rotator_carry, 106'h200000000000000000000000000, e_in[78:73], 3'h1 } : { e_in[72:9], 7'h44, _0013_, 106'h000000000000000000000000000, e_in[78:73], 3'h1 };
+ assign _0542_ = e_in[8:3] == 6'h32;
+ assign _0543_ = e_in[8:3] == 6'h33;
+ assign _0544_ = _0542_ | _0543_;
+ assign _0545_ = e_in[8:3] == 6'h34;
+ assign _0546_ = _0544_ | _0545_;
+ assign _0547_ = e_in[8:3] == 6'h37;
+ assign _0548_ = _0546_ | _0547_;
+ assign _0549_ = e_in[8:3] == 6'h38;
+ assign _0550_ = _0548_ | _0549_;
+ assign _0551_ = e_in[8:3] == 6'h18;
+ assign _0552_ = _0550_ | _0551_;
+ assign _0553_ = e_in[8:3] == 6'h1c;
+ assign _0554_ = e_in[8:3] == 6'h19;
+ assign _0555_ = e_in[8:3] == 6'h2b;
+ assign _0556_ = e_in[8:3] == 6'h2c;
+ assign _0557_ = _0555_ | _0556_;
+ assign _0558_ = e_in[8:3] == 6'h2d;
+ assign _0559_ = _0557_ | _0558_;
+ assign _0560_ = e_in[8:3] == 6'h15;
+ assign _0561_ = e_in[8:3] == 6'h16;
+ assign _0562_ = _0560_ | _0561_;
+ assign _0563_ = e_in[8:3] == 6'h27;
+ assign _0564_ = _0562_ | _0563_;
+ function [0:0] \6847 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6847 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6847 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6847 = b[2:2];
+ 28'b????????????????????????1???:
+ \6847 = b[3:3];
+ 28'b???????????????????????1????:
+ \6847 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6847 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6847 = b[6:6];
+ 28'b????????????????????1???????:
+ \6847 = b[7:7];
+ 28'b???????????????????1????????:
+ \6847 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6847 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6847 = b[10:10];
+ 28'b????????????????1???????????:
+ \6847 = b[11:11];
+ 28'b???????????????1????????????:
+ \6847 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6847 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6847 = b[14:14];
+ 28'b????????????1???????????????:
+ \6847 = b[15:15];
+ 28'b???????????1????????????????:
+ \6847 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6847 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6847 = b[18:18];
+ 28'b????????1???????????????????:
+ \6847 = b[19:19];
+ 28'b???????1????????????????????:
+ \6847 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6847 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6847 = b[22:22];
+ 28'b????1???????????????????????:
+ \6847 = b[23:23];
+ 28'b???1????????????????????????:
+ \6847 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6847 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6847 = b[26:26];
+ 28'b1???????????????????????????:
+ \6847 = b[27:27];
+ default:
+ \6847 = a;
+ endcase
+ endfunction
+ assign _0565_ = \6847 (1'h0, 28'hc000800, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6848 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6848 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6848 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6848 = b[2:2];
+ 28'b????????????????????????1???:
+ \6848 = b[3:3];
+ 28'b???????????????????????1????:
+ \6848 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6848 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6848 = b[6:6];
+ 28'b????????????????????1???????:
+ \6848 = b[7:7];
+ 28'b???????????????????1????????:
+ \6848 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6848 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6848 = b[10:10];
+ 28'b????????????????1???????????:
+ \6848 = b[11:11];
+ 28'b???????????????1????????????:
+ \6848 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6848 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6848 = b[14:14];
+ 28'b????????????1???????????????:
+ \6848 = b[15:15];
+ 28'b???????????1????????????????:
+ \6848 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6848 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6848 = b[18:18];
+ 28'b????????1???????????????????:
+ \6848 = b[19:19];
+ 28'b???????1????????????????????:
+ \6848 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6848 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6848 = b[22:22];
+ 28'b????1???????????????????????:
+ \6848 = b[23:23];
+ 28'b???1????????????????????????:
+ \6848 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6848 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6848 = b[26:26];
+ 28'b1???????????????????????????:
+ \6848 = b[27:27];
+ default:
+ \6848 = a;
+ endcase
+ endfunction
+ assign _0566_ = \6848 (1'h0, { 19'h08001, _0203_, _0182_, 7'h40 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6849 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6849 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6849 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6849 = b[2:2];
+ 28'b????????????????????????1???:
+ \6849 = b[3:3];
+ 28'b???????????????????????1????:
+ \6849 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6849 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6849 = b[6:6];
+ 28'b????????????????????1???????:
+ \6849 = b[7:7];
+ 28'b???????????????????1????????:
+ \6849 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6849 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6849 = b[10:10];
+ 28'b????????????????1???????????:
+ \6849 = b[11:11];
+ 28'b???????????????1????????????:
+ \6849 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6849 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6849 = b[14:14];
+ 28'b????????????1???????????????:
+ \6849 = b[15:15];
+ 28'b???????????1????????????????:
+ \6849 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6849 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6849 = b[18:18];
+ 28'b????????1???????????????????:
+ \6849 = b[19:19];
+ 28'b???????1????????????????????:
+ \6849 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6849 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6849 = b[22:22];
+ 28'b????1???????????????????????:
+ \6849 = b[23:23];
+ 28'b???1????????????????????????:
+ \6849 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6849 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6849 = b[26:26];
+ 28'b1???????????????????????????:
+ \6849 = b[27:27];
+ default:
+ \6849 = a;
+ endcase
+ endfunction
+ assign _0567_ = \6849 (ctrl[133], { ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], _0206_, ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133], ctrl[133] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6850 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6850 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6850 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6850 = b[2:2];
+ 28'b????????????????????????1???:
+ \6850 = b[3:3];
+ 28'b???????????????????????1????:
+ \6850 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6850 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6850 = b[6:6];
+ 28'b????????????????????1???????:
+ \6850 = b[7:7];
+ 28'b???????????????????1????????:
+ \6850 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6850 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6850 = b[10:10];
+ 28'b????????????????1???????????:
+ \6850 = b[11:11];
+ 28'b???????????????1????????????:
+ \6850 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6850 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6850 = b[14:14];
+ 28'b????????????1???????????????:
+ \6850 = b[15:15];
+ 28'b???????????1????????????????:
+ \6850 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6850 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6850 = b[18:18];
+ 28'b????????1???????????????????:
+ \6850 = b[19:19];
+ 28'b???????1????????????????????:
+ \6850 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6850 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6850 = b[22:22];
+ 28'b????1???????????????????????:
+ \6850 = b[23:23];
+ 28'b???1????????????????????????:
+ \6850 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6850 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6850 = b[26:26];
+ 28'b1???????????????????????????:
+ \6850 = b[27:27];
+ default:
+ \6850 = a;
+ endcase
+ endfunction
+ assign _0568_ = \6850 (_0047_, { _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0207_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_, _0047_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [63:0] \6851 ;
+ input [63:0] a;
+ input [1791:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6851 = b[63:0];
+ 28'b??????????????????????????1?:
+ \6851 = b[127:64];
+ 28'b?????????????????????????1??:
+ \6851 = b[191:128];
+ 28'b????????????????????????1???:
+ \6851 = b[255:192];
+ 28'b???????????????????????1????:
+ \6851 = b[319:256];
+ 28'b??????????????????????1?????:
+ \6851 = b[383:320];
+ 28'b?????????????????????1??????:
+ \6851 = b[447:384];
+ 28'b????????????????????1???????:
+ \6851 = b[511:448];
+ 28'b???????????????????1????????:
+ \6851 = b[575:512];
+ 28'b??????????????????1?????????:
+ \6851 = b[639:576];
+ 28'b?????????????????1??????????:
+ \6851 = b[703:640];
+ 28'b????????????????1???????????:
+ \6851 = b[767:704];
+ 28'b???????????????1????????????:
+ \6851 = b[831:768];
+ 28'b??????????????1?????????????:
+ \6851 = b[895:832];
+ 28'b?????????????1??????????????:
+ \6851 = b[959:896];
+ 28'b????????????1???????????????:
+ \6851 = b[1023:960];
+ 28'b???????????1????????????????:
+ \6851 = b[1087:1024];
+ 28'b??????????1?????????????????:
+ \6851 = b[1151:1088];
+ 28'b?????????1??????????????????:
+ \6851 = b[1215:1152];
+ 28'b????????1???????????????????:
+ \6851 = b[1279:1216];
+ 28'b???????1????????????????????:
+ \6851 = b[1343:1280];
+ 28'b??????1?????????????????????:
+ \6851 = b[1407:1344];
+ 28'b?????1??????????????????????:
+ \6851 = b[1471:1408];
+ 28'b????1???????????????????????:
+ \6851 = b[1535:1472];
+ 28'b???1????????????????????????:
+ \6851 = b[1599:1536];
+ 28'b??1?????????????????????????:
+ \6851 = b[1663:1600];
+ 28'b?1??????????????????????????:
+ \6851 = b[1727:1664];
+ 28'b1???????????????????????????:
+ \6851 = b[1791:1728];
+ default:
+ \6851 = a;
+ endcase
+ endfunction
+ assign _0569_ = \6851 (64'h0000000000000000, { 192'h000000000000000000000000000000000000000000000000, _0048_, 896'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, a_in[63:2], 2'h0, _0204_, _0183_, _0162_, 384'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6854 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6854 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6854 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6854 = b[2:2];
+ 28'b????????????????????????1???:
+ \6854 = b[3:3];
+ 28'b???????????????????????1????:
+ \6854 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6854 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6854 = b[6:6];
+ 28'b????????????????????1???????:
+ \6854 = b[7:7];
+ 28'b???????????????????1????????:
+ \6854 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6854 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6854 = b[10:10];
+ 28'b????????????????1???????????:
+ \6854 = b[11:11];
+ 28'b???????????????1????????????:
+ \6854 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6854 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6854 = b[14:14];
+ 28'b????????????1???????????????:
+ \6854 = b[15:15];
+ 28'b???????????1????????????????:
+ \6854 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6854 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6854 = b[18:18];
+ 28'b????????1???????????????????:
+ \6854 = b[19:19];
+ 28'b???????1????????????????????:
+ \6854 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6854 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6854 = b[22:22];
+ 28'b????1???????????????????????:
+ \6854 = b[23:23];
+ 28'b???1????????????????????????:
+ \6854 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6854 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6854 = b[26:26];
+ 28'b1???????????????????????????:
+ \6854 = b[27:27];
+ default:
+ \6854 = a;
+ endcase
+ endfunction
+ assign _0570_ = \6854 (1'h0, 28'h2000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6857 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6857 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6857 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6857 = b[2:2];
+ 28'b????????????????????????1???:
+ \6857 = b[3:3];
+ 28'b???????????????????????1????:
+ \6857 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6857 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6857 = b[6:6];
+ 28'b????????????????????1???????:
+ \6857 = b[7:7];
+ 28'b???????????????????1????????:
+ \6857 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6857 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6857 = b[10:10];
+ 28'b????????????????1???????????:
+ \6857 = b[11:11];
+ 28'b???????????????1????????????:
+ \6857 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6857 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6857 = b[14:14];
+ 28'b????????????1???????????????:
+ \6857 = b[15:15];
+ 28'b???????????1????????????????:
+ \6857 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6857 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6857 = b[18:18];
+ 28'b????????1???????????????????:
+ \6857 = b[19:19];
+ 28'b???????1????????????????????:
+ \6857 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6857 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6857 = b[22:22];
+ 28'b????1???????????????????????:
+ \6857 = b[23:23];
+ 28'b???1????????????????????????:
+ \6857 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6857 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6857 = b[26:26];
+ 28'b1???????????????????????????:
+ \6857 = b[27:27];
+ default:
+ \6857 = a;
+ endcase
+ endfunction
+ assign _0571_ = \6857 (1'h1, { 25'h0000000, _0077_, 2'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [63:0] \6858 ;
+ input [63:0] a;
+ input [1791:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6858 = b[63:0];
+ 28'b??????????????????????????1?:
+ \6858 = b[127:64];
+ 28'b?????????????????????????1??:
+ \6858 = b[191:128];
+ 28'b????????????????????????1???:
+ \6858 = b[255:192];
+ 28'b???????????????????????1????:
+ \6858 = b[319:256];
+ 28'b??????????????????????1?????:
+ \6858 = b[383:320];
+ 28'b?????????????????????1??????:
+ \6858 = b[447:384];
+ 28'b????????????????????1???????:
+ \6858 = b[511:448];
+ 28'b???????????????????1????????:
+ \6858 = b[575:512];
+ 28'b??????????????????1?????????:
+ \6858 = b[639:576];
+ 28'b?????????????????1??????????:
+ \6858 = b[703:640];
+ 28'b????????????????1???????????:
+ \6858 = b[767:704];
+ 28'b???????????????1????????????:
+ \6858 = b[831:768];
+ 28'b??????????????1?????????????:
+ \6858 = b[895:832];
+ 28'b?????????????1??????????????:
+ \6858 = b[959:896];
+ 28'b????????????1???????????????:
+ \6858 = b[1023:960];
+ 28'b???????????1????????????????:
+ \6858 = b[1087:1024];
+ 28'b??????????1?????????????????:
+ \6858 = b[1151:1088];
+ 28'b?????????1??????????????????:
+ \6858 = b[1215:1152];
+ 28'b????????1???????????????????:
+ \6858 = b[1279:1216];
+ 28'b???????1????????????????????:
+ \6858 = b[1343:1280];
+ 28'b??????1?????????????????????:
+ \6858 = b[1407:1344];
+ 28'b?????1??????????????????????:
+ \6858 = b[1471:1408];
+ 28'b????1???????????????????????:
+ \6858 = b[1535:1472];
+ 28'b???1????????????????????????:
+ \6858 = b[1599:1536];
+ 28'b??1?????????????????????????:
+ \6858 = b[1663:1600];
+ 28'b?1??????????????????????????:
+ \6858 = b[1727:1664];
+ 28'b1???????????????????????????:
+ \6858 = b[1791:1728];
+ default:
+ \6858 = a;
+ endcase
+ endfunction
+ assign _0572_ = \6858 (_0040_, { _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0533_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_, _0040_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6861 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6861 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6861 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6861 = b[2:2];
+ 28'b????????????????????????1???:
+ \6861 = b[3:3];
+ 28'b???????????????????????1????:
+ \6861 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6861 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6861 = b[6:6];
+ 28'b????????????????????1???????:
+ \6861 = b[7:7];
+ 28'b???????????????????1????????:
+ \6861 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6861 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6861 = b[10:10];
+ 28'b????????????????1???????????:
+ \6861 = b[11:11];
+ 28'b???????????????1????????????:
+ \6861 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6861 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6861 = b[14:14];
+ 28'b????????????1???????????????:
+ \6861 = b[15:15];
+ 28'b???????????1????????????????:
+ \6861 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6861 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6861 = b[18:18];
+ 28'b????????1???????????????????:
+ \6861 = b[19:19];
+ 28'b???????1????????????????????:
+ \6861 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6861 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6861 = b[22:22];
+ 28'b????1???????????????????????:
+ \6861 = b[23:23];
+ 28'b???1????????????????????????:
+ \6861 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6861 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6861 = b[26:26];
+ 28'b1???????????????????????????:
+ \6861 = b[27:27];
+ default:
+ \6861 = a;
+ endcase
+ endfunction
+ assign _0573_ = \6861 (ctrl[128], { ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], b_in[0], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128], ctrl[128] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6864 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6864 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6864 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6864 = b[2:2];
+ 28'b????????????????????????1???:
+ \6864 = b[3:3];
+ 28'b???????????????????????1????:
+ \6864 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6864 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6864 = b[6:6];
+ 28'b????????????????????1???????:
+ \6864 = b[7:7];
+ 28'b???????????????????1????????:
+ \6864 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6864 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6864 = b[10:10];
+ 28'b????????????????1???????????:
+ \6864 = b[11:11];
+ 28'b???????????????1????????????:
+ \6864 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6864 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6864 = b[14:14];
+ 28'b????????????1???????????????:
+ \6864 = b[15:15];
+ 28'b???????????1????????????????:
+ \6864 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6864 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6864 = b[18:18];
+ 28'b????????1???????????????????:
+ \6864 = b[19:19];
+ 28'b???????1????????????????????:
+ \6864 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6864 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6864 = b[22:22];
+ 28'b????1???????????????????????:
+ \6864 = b[23:23];
+ 28'b???1????????????????????????:
+ \6864 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6864 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6864 = b[26:26];
+ 28'b1???????????????????????????:
+ \6864 = b[27:27];
+ default:
+ \6864 = a;
+ endcase
+ endfunction
+ assign _0574_ = \6864 (ctrl[129], { ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], _0520_, ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], b_in[1], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129], ctrl[129] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [1:0] \6868 ;
+ input [1:0] a;
+ input [55:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6868 = b[1:0];
+ 28'b??????????????????????????1?:
+ \6868 = b[3:2];
+ 28'b?????????????????????????1??:
+ \6868 = b[5:4];
+ 28'b????????????????????????1???:
+ \6868 = b[7:6];
+ 28'b???????????????????????1????:
+ \6868 = b[9:8];
+ 28'b??????????????????????1?????:
+ \6868 = b[11:10];
+ 28'b?????????????????????1??????:
+ \6868 = b[13:12];
+ 28'b????????????????????1???????:
+ \6868 = b[15:14];
+ 28'b???????????????????1????????:
+ \6868 = b[17:16];
+ 28'b??????????????????1?????????:
+ \6868 = b[19:18];
+ 28'b?????????????????1??????????:
+ \6868 = b[21:20];
+ 28'b????????????????1???????????:
+ \6868 = b[23:22];
+ 28'b???????????????1????????????:
+ \6868 = b[25:24];
+ 28'b??????????????1?????????????:
+ \6868 = b[27:26];
+ 28'b?????????????1??????????????:
+ \6868 = b[29:28];
+ 28'b????????????1???????????????:
+ \6868 = b[31:30];
+ 28'b???????????1????????????????:
+ \6868 = b[33:32];
+ 28'b??????????1?????????????????:
+ \6868 = b[35:34];
+ 28'b?????????1??????????????????:
+ \6868 = b[37:36];
+ 28'b????????1???????????????????:
+ \6868 = b[39:38];
+ 28'b???????1????????????????????:
+ \6868 = b[41:40];
+ 28'b??????1?????????????????????:
+ \6868 = b[43:42];
+ 28'b?????1??????????????????????:
+ \6868 = b[45:44];
+ 28'b????1???????????????????????:
+ \6868 = b[47:46];
+ 28'b???1????????????????????????:
+ \6868 = b[49:48];
+ 28'b??1?????????????????????????:
+ \6868 = b[51:50];
+ 28'b?1??????????????????????????:
+ \6868 = b[53:52];
+ 28'b1???????????????????????????:
+ \6868 = b[55:54];
+ default:
+ \6868 = a;
+ endcase
+ endfunction
+ assign _0575_ = \6868 (ctrl[131:130], { ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], _0521_[1:0], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], b_in[3:2], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130], ctrl[131:130] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [1:0] \6871 ;
+ input [1:0] a;
+ input [55:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6871 = b[1:0];
+ 28'b??????????????????????????1?:
+ \6871 = b[3:2];
+ 28'b?????????????????????????1??:
+ \6871 = b[5:4];
+ 28'b????????????????????????1???:
+ \6871 = b[7:6];
+ 28'b???????????????????????1????:
+ \6871 = b[9:8];
+ 28'b??????????????????????1?????:
+ \6871 = b[11:10];
+ 28'b?????????????????????1??????:
+ \6871 = b[13:12];
+ 28'b????????????????????1???????:
+ \6871 = b[15:14];
+ 28'b???????????????????1????????:
+ \6871 = b[17:16];
+ 28'b??????????????????1?????????:
+ \6871 = b[19:18];
+ 28'b?????????????????1??????????:
+ \6871 = b[21:20];
+ 28'b????????????????1???????????:
+ \6871 = b[23:22];
+ 28'b???????????????1????????????:
+ \6871 = b[25:24];
+ 28'b??????????????1?????????????:
+ \6871 = b[27:26];
+ 28'b?????????????1??????????????:
+ \6871 = b[29:28];
+ 28'b????????????1???????????????:
+ \6871 = b[31:30];
+ 28'b???????????1????????????????:
+ \6871 = b[33:32];
+ 28'b??????????1?????????????????:
+ \6871 = b[35:34];
+ 28'b?????????1??????????????????:
+ \6871 = b[37:36];
+ 28'b????????1???????????????????:
+ \6871 = b[39:38];
+ 28'b???????1????????????????????:
+ \6871 = b[41:40];
+ 28'b??????1?????????????????????:
+ \6871 = b[43:42];
+ 28'b?????1??????????????????????:
+ \6871 = b[45:44];
+ 28'b????1???????????????????????:
+ \6871 = b[47:46];
+ 28'b???1????????????????????????:
+ \6871 = b[49:48];
+ 28'b??1?????????????????????????:
+ \6871 = b[51:50];
+ 28'b?1??????????????????????????:
+ \6871 = b[53:52];
+ 28'b1???????????????????????????:
+ \6871 = b[55:54];
+ default:
+ \6871 = a;
+ endcase
+ endfunction
+ assign _0576_ = \6871 (ctrl[133:132], { ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0521_[3:2], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], _0208_, ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132], ctrl[133:132] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [5:0] \6875 ;
+ input [5:0] a;
+ input [167:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6875 = b[5:0];
+ 28'b??????????????????????????1?:
+ \6875 = b[11:6];
+ 28'b?????????????????????????1??:
+ \6875 = b[17:12];
+ 28'b????????????????????????1???:
+ \6875 = b[23:18];
+ 28'b???????????????????????1????:
+ \6875 = b[29:24];
+ 28'b??????????????????????1?????:
+ \6875 = b[35:30];
+ 28'b?????????????????????1??????:
+ \6875 = b[41:36];
+ 28'b????????????????????1???????:
+ \6875 = b[47:42];
+ 28'b???????????????????1????????:
+ \6875 = b[53:48];
+ 28'b??????????????????1?????????:
+ \6875 = b[59:54];
+ 28'b?????????????????1??????????:
+ \6875 = b[65:60];
+ 28'b????????????????1???????????:
+ \6875 = b[71:66];
+ 28'b???????????????1????????????:
+ \6875 = b[77:72];
+ 28'b??????????????1?????????????:
+ \6875 = b[83:78];
+ 28'b?????????????1??????????????:
+ \6875 = b[89:84];
+ 28'b????????????1???????????????:
+ \6875 = b[95:90];
+ 28'b???????????1????????????????:
+ \6875 = b[101:96];
+ 28'b??????????1?????????????????:
+ \6875 = b[107:102];
+ 28'b?????????1??????????????????:
+ \6875 = b[113:108];
+ 28'b????????1???????????????????:
+ \6875 = b[119:114];
+ 28'b???????1????????????????????:
+ \6875 = b[125:120];
+ 28'b??????1?????????????????????:
+ \6875 = b[131:126];
+ 28'b?????1??????????????????????:
+ \6875 = b[137:132];
+ 28'b????1???????????????????????:
+ \6875 = b[143:138];
+ 28'b???1????????????????????????:
+ \6875 = b[149:144];
+ 28'b??1?????????????????????????:
+ \6875 = b[155:150];
+ 28'b?1??????????????????????????:
+ \6875 = b[161:156];
+ 28'b1???????????????????????????:
+ \6875 = b[167:162];
+ default:
+ \6875 = a;
+ endcase
+ endfunction
+ assign _0577_ = \6875 (ctrl[139:134], { ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], _0521_[9:4], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], b_in[11:6], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134], ctrl[139:134] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6878 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6878 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6878 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6878 = b[2:2];
+ 28'b????????????????????????1???:
+ \6878 = b[3:3];
+ 28'b???????????????????????1????:
+ \6878 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6878 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6878 = b[6:6];
+ 28'b????????????????????1???????:
+ \6878 = b[7:7];
+ 28'b???????????????????1????????:
+ \6878 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6878 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6878 = b[10:10];
+ 28'b????????????????1???????????:
+ \6878 = b[11:11];
+ 28'b???????????????1????????????:
+ \6878 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6878 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6878 = b[14:14];
+ 28'b????????????1???????????????:
+ \6878 = b[15:15];
+ 28'b???????????1????????????????:
+ \6878 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6878 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6878 = b[18:18];
+ 28'b????????1???????????????????:
+ \6878 = b[19:19];
+ 28'b???????1????????????????????:
+ \6878 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6878 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6878 = b[22:22];
+ 28'b????1???????????????????????:
+ \6878 = b[23:23];
+ 28'b???1????????????????????????:
+ \6878 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6878 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6878 = b[26:26];
+ 28'b1???????????????????????????:
+ \6878 = b[27:27];
+ default:
+ \6878 = a;
+ endcase
+ endfunction
+ assign _0578_ = \6878 (ctrl[140], { ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], b_in[12], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140], ctrl[140] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [1:0] \6881 ;
+ input [1:0] a;
+ input [55:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6881 = b[1:0];
+ 28'b??????????????????????????1?:
+ \6881 = b[3:2];
+ 28'b?????????????????????????1??:
+ \6881 = b[5:4];
+ 28'b????????????????????????1???:
+ \6881 = b[7:6];
+ 28'b???????????????????????1????:
+ \6881 = b[9:8];
+ 28'b??????????????????????1?????:
+ \6881 = b[11:10];
+ 28'b?????????????????????1??????:
+ \6881 = b[13:12];
+ 28'b????????????????????1???????:
+ \6881 = b[15:14];
+ 28'b???????????????????1????????:
+ \6881 = b[17:16];
+ 28'b??????????????????1?????????:
+ \6881 = b[19:18];
+ 28'b?????????????????1??????????:
+ \6881 = b[21:20];
+ 28'b????????????????1???????????:
+ \6881 = b[23:22];
+ 28'b???????????????1????????????:
+ \6881 = b[25:24];
+ 28'b??????????????1?????????????:
+ \6881 = b[27:26];
+ 28'b?????????????1??????????????:
+ \6881 = b[29:28];
+ 28'b????????????1???????????????:
+ \6881 = b[31:30];
+ 28'b???????????1????????????????:
+ \6881 = b[33:32];
+ 28'b??????????1?????????????????:
+ \6881 = b[35:34];
+ 28'b?????????1??????????????????:
+ \6881 = b[37:36];
+ 28'b????????1???????????????????:
+ \6881 = b[39:38];
+ 28'b???????1????????????????????:
+ \6881 = b[41:40];
+ 28'b??????1?????????????????????:
+ \6881 = b[43:42];
+ 28'b?????1??????????????????????:
+ \6881 = b[45:44];
+ 28'b????1???????????????????????:
+ \6881 = b[47:46];
+ 28'b???1????????????????????????:
+ \6881 = b[49:48];
+ 28'b??1?????????????????????????:
+ \6881 = b[51:50];
+ 28'b?1??????????????????????????:
+ \6881 = b[53:52];
+ 28'b1???????????????????????????:
+ \6881 = b[55:54];
+ default:
+ \6881 = a;
+ endcase
+ endfunction
+ assign _0579_ = \6881 (ctrl[142:141], { ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], _0522_, ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], b_in[14:13], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141], ctrl[142:141] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6883 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6883 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6883 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6883 = b[2:2];
+ 28'b????????????????????????1???:
+ \6883 = b[3:3];
+ 28'b???????????????????????1????:
+ \6883 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6883 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6883 = b[6:6];
+ 28'b????????????????????1???????:
+ \6883 = b[7:7];
+ 28'b???????????????????1????????:
+ \6883 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6883 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6883 = b[10:10];
+ 28'b????????????????1???????????:
+ \6883 = b[11:11];
+ 28'b???????????????1????????????:
+ \6883 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6883 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6883 = b[14:14];
+ 28'b????????????1???????????????:
+ \6883 = b[15:15];
+ 28'b???????????1????????????????:
+ \6883 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6883 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6883 = b[18:18];
+ 28'b????????1???????????????????:
+ \6883 = b[19:19];
+ 28'b???????1????????????????????:
+ \6883 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6883 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6883 = b[22:22];
+ 28'b????1???????????????????????:
+ \6883 = b[23:23];
+ 28'b???1????????????????????????:
+ \6883 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6883 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6883 = b[26:26];
+ 28'b1???????????????????????????:
+ \6883 = b[27:27];
+ default:
+ \6883 = a;
+ endcase
+ endfunction
+ assign _0580_ = \6883 (ctrl[143], { ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0523_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], _0209_, ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143], ctrl[143] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [5:0] \6886 ;
+ input [5:0] a;
+ input [167:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6886 = b[5:0];
+ 28'b??????????????????????????1?:
+ \6886 = b[11:6];
+ 28'b?????????????????????????1??:
+ \6886 = b[17:12];
+ 28'b????????????????????????1???:
+ \6886 = b[23:18];
+ 28'b???????????????????????1????:
+ \6886 = b[29:24];
+ 28'b??????????????????????1?????:
+ \6886 = b[35:30];
+ 28'b?????????????????????1??????:
+ \6886 = b[41:36];
+ 28'b????????????????????1???????:
+ \6886 = b[47:42];
+ 28'b???????????????????1????????:
+ \6886 = b[53:48];
+ 28'b??????????????????1?????????:
+ \6886 = b[59:54];
+ 28'b?????????????????1??????????:
+ \6886 = b[65:60];
+ 28'b????????????????1???????????:
+ \6886 = b[71:66];
+ 28'b???????????????1????????????:
+ \6886 = b[77:72];
+ 28'b??????????????1?????????????:
+ \6886 = b[83:78];
+ 28'b?????????????1??????????????:
+ \6886 = b[89:84];
+ 28'b????????????1???????????????:
+ \6886 = b[95:90];
+ 28'b???????????1????????????????:
+ \6886 = b[101:96];
+ 28'b??????????1?????????????????:
+ \6886 = b[107:102];
+ 28'b?????????1??????????????????:
+ \6886 = b[113:108];
+ 28'b????????1???????????????????:
+ \6886 = b[119:114];
+ 28'b???????1????????????????????:
+ \6886 = b[125:120];
+ 28'b??????1?????????????????????:
+ \6886 = b[131:126];
+ 28'b?????1??????????????????????:
+ \6886 = b[137:132];
+ 28'b????1???????????????????????:
+ \6886 = b[143:138];
+ 28'b???1????????????????????????:
+ \6886 = b[149:144];
+ 28'b??1?????????????????????????:
+ \6886 = b[155:150];
+ 28'b?1??????????????????????????:
+ \6886 = b[161:156];
+ 28'b1???????????????????????????:
+ \6886 = b[167:162];
+ default:
+ \6886 = a;
+ endcase
+ endfunction
+ assign _0581_ = \6886 (ctrl[149:144], { ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], _0524_[5:0], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144], ctrl[149:144] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [4:0] \6889 ;
+ input [4:0] a;
+ input [139:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6889 = b[4:0];
+ 28'b??????????????????????????1?:
+ \6889 = b[9:5];
+ 28'b?????????????????????????1??:
+ \6889 = b[14:10];
+ 28'b????????????????????????1???:
+ \6889 = b[19:15];
+ 28'b???????????????????????1????:
+ \6889 = b[24:20];
+ 28'b??????????????????????1?????:
+ \6889 = b[29:25];
+ 28'b?????????????????????1??????:
+ \6889 = b[34:30];
+ 28'b????????????????????1???????:
+ \6889 = b[39:35];
+ 28'b???????????????????1????????:
+ \6889 = b[44:40];
+ 28'b??????????????????1?????????:
+ \6889 = b[49:45];
+ 28'b?????????????????1??????????:
+ \6889 = b[54:50];
+ 28'b????????????????1???????????:
+ \6889 = b[59:55];
+ 28'b???????????????1????????????:
+ \6889 = b[64:60];
+ 28'b??????????????1?????????????:
+ \6889 = b[69:65];
+ 28'b?????????????1??????????????:
+ \6889 = b[74:70];
+ 28'b????????????1???????????????:
+ \6889 = b[79:75];
+ 28'b???????????1????????????????:
+ \6889 = b[84:80];
+ 28'b??????????1?????????????????:
+ \6889 = b[89:85];
+ 28'b?????????1??????????????????:
+ \6889 = b[94:90];
+ 28'b????????1???????????????????:
+ \6889 = b[99:95];
+ 28'b???????1????????????????????:
+ \6889 = b[104:100];
+ 28'b??????1?????????????????????:
+ \6889 = b[109:105];
+ 28'b?????1??????????????????????:
+ \6889 = b[114:110];
+ 28'b????1???????????????????????:
+ \6889 = b[119:115];
+ 28'b???1????????????????????????:
+ \6889 = b[124:120];
+ 28'b??1?????????????????????????:
+ \6889 = b[129:125];
+ 28'b?1??????????????????????????:
+ \6889 = b[134:130];
+ 28'b1???????????????????????????:
+ \6889 = b[139:135];
+ default:
+ \6889 = a;
+ endcase
+ endfunction
+ assign _0582_ = \6889 (ctrl[154:150], { ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], _0524_[10:6], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], b_in[26:22], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150], ctrl[154:150] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [3:0] \6892 ;
+ input [3:0] a;
+ input [111:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6892 = b[3:0];
+ 28'b??????????????????????????1?:
+ \6892 = b[7:4];
+ 28'b?????????????????????????1??:
+ \6892 = b[11:8];
+ 28'b????????????????????????1???:
+ \6892 = b[15:12];
+ 28'b???????????????????????1????:
+ \6892 = b[19:16];
+ 28'b??????????????????????1?????:
+ \6892 = b[23:20];
+ 28'b?????????????????????1??????:
+ \6892 = b[27:24];
+ 28'b????????????????????1???????:
+ \6892 = b[31:28];
+ 28'b???????????????????1????????:
+ \6892 = b[35:32];
+ 28'b??????????????????1?????????:
+ \6892 = b[39:36];
+ 28'b?????????????????1??????????:
+ \6892 = b[43:40];
+ 28'b????????????????1???????????:
+ \6892 = b[47:44];
+ 28'b???????????????1????????????:
+ \6892 = b[51:48];
+ 28'b??????????????1?????????????:
+ \6892 = b[55:52];
+ 28'b?????????????1??????????????:
+ \6892 = b[59:56];
+ 28'b????????????1???????????????:
+ \6892 = b[63:60];
+ 28'b???????????1????????????????:
+ \6892 = b[67:64];
+ 28'b??????????1?????????????????:
+ \6892 = b[71:68];
+ 28'b?????????1??????????????????:
+ \6892 = b[75:72];
+ 28'b????????1???????????????????:
+ \6892 = b[79:76];
+ 28'b???????1????????????????????:
+ \6892 = b[83:80];
+ 28'b??????1?????????????????????:
+ \6892 = b[87:84];
+ 28'b?????1??????????????????????:
+ \6892 = b[91:88];
+ 28'b????1???????????????????????:
+ \6892 = b[95:92];
+ 28'b???1????????????????????????:
+ \6892 = b[99:96];
+ 28'b??1?????????????????????????:
+ \6892 = b[103:100];
+ 28'b?1??????????????????????????:
+ \6892 = b[107:104];
+ 28'b1???????????????????????????:
+ \6892 = b[111:108];
+ default:
+ \6892 = a;
+ endcase
+ endfunction
+ assign _0583_ = \6892 (ctrl[158:155], { ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], _0524_[14:11], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155], ctrl[158:155] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [28:0] \6896 ;
+ input [28:0] a;
+ input [811:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6896 = b[28:0];
+ 28'b??????????????????????????1?:
+ \6896 = b[57:29];
+ 28'b?????????????????????????1??:
+ \6896 = b[86:58];
+ 28'b????????????????????????1???:
+ \6896 = b[115:87];
+ 28'b???????????????????????1????:
+ \6896 = b[144:116];
+ 28'b??????????????????????1?????:
+ \6896 = b[173:145];
+ 28'b?????????????????????1??????:
+ \6896 = b[202:174];
+ 28'b????????????????????1???????:
+ \6896 = b[231:203];
+ 28'b???????????????????1????????:
+ \6896 = b[260:232];
+ 28'b??????????????????1?????????:
+ \6896 = b[289:261];
+ 28'b?????????????????1??????????:
+ \6896 = b[318:290];
+ 28'b????????????????1???????????:
+ \6896 = b[347:319];
+ 28'b???????????????1????????????:
+ \6896 = b[376:348];
+ 28'b??????????????1?????????????:
+ \6896 = b[405:377];
+ 28'b?????????????1??????????????:
+ \6896 = b[434:406];
+ 28'b????????????1???????????????:
+ \6896 = b[463:435];
+ 28'b???????????1????????????????:
+ \6896 = b[492:464];
+ 28'b??????????1?????????????????:
+ \6896 = b[521:493];
+ 28'b?????????1??????????????????:
+ \6896 = b[550:522];
+ 28'b????????1???????????????????:
+ \6896 = b[579:551];
+ 28'b???????1????????????????????:
+ \6896 = b[608:580];
+ 28'b??????1?????????????????????:
+ \6896 = b[637:609];
+ 28'b?????1??????????????????????:
+ \6896 = b[666:638];
+ 28'b????1???????????????????????:
+ \6896 = b[695:667];
+ 28'b???1????????????????????????:
+ \6896 = b[724:696];
+ 28'b??1?????????????????????????:
+ \6896 = b[753:725];
+ 28'b?1??????????????????????????:
+ \6896 = b[782:754];
+ 28'b1???????????????????????????:
+ \6896 = b[811:783];
+ default:
+ \6896 = a;
+ endcase
+ endfunction
+ assign _0584_ = \6896 (ctrl[187:159], { ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], _0524_[43:15], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], b_in[59:31], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159], ctrl[187:159] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6899 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6899 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6899 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6899 = b[2:2];
+ 28'b????????????????????????1???:
+ \6899 = b[3:3];
+ 28'b???????????????????????1????:
+ \6899 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6899 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6899 = b[6:6];
+ 28'b????????????????????1???????:
+ \6899 = b[7:7];
+ 28'b???????????????????1????????:
+ \6899 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6899 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6899 = b[10:10];
+ 28'b????????????????1???????????:
+ \6899 = b[11:11];
+ 28'b???????????????1????????????:
+ \6899 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6899 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6899 = b[14:14];
+ 28'b????????????1???????????????:
+ \6899 = b[15:15];
+ 28'b???????????1????????????????:
+ \6899 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6899 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6899 = b[18:18];
+ 28'b????????1???????????????????:
+ \6899 = b[19:19];
+ 28'b???????1????????????????????:
+ \6899 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6899 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6899 = b[22:22];
+ 28'b????1???????????????????????:
+ \6899 = b[23:23];
+ 28'b???1????????????????????????:
+ \6899 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6899 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6899 = b[26:26];
+ 28'b1???????????????????????????:
+ \6899 = b[27:27];
+ default:
+ \6899 = a;
+ endcase
+ endfunction
+ assign _0585_ = \6899 (ctrl[188], { ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], b_in[60], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188], ctrl[188] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [2:0] \6902 ;
+ input [2:0] a;
+ input [83:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6902 = b[2:0];
+ 28'b??????????????????????????1?:
+ \6902 = b[5:3];
+ 28'b?????????????????????????1??:
+ \6902 = b[8:6];
+ 28'b????????????????????????1???:
+ \6902 = b[11:9];
+ 28'b???????????????????????1????:
+ \6902 = b[14:12];
+ 28'b??????????????????????1?????:
+ \6902 = b[17:15];
+ 28'b?????????????????????1??????:
+ \6902 = b[20:18];
+ 28'b????????????????????1???????:
+ \6902 = b[23:21];
+ 28'b???????????????????1????????:
+ \6902 = b[26:24];
+ 28'b??????????????????1?????????:
+ \6902 = b[29:27];
+ 28'b?????????????????1??????????:
+ \6902 = b[32:30];
+ 28'b????????????????1???????????:
+ \6902 = b[35:33];
+ 28'b???????????????1????????????:
+ \6902 = b[38:36];
+ 28'b??????????????1?????????????:
+ \6902 = b[41:39];
+ 28'b?????????????1??????????????:
+ \6902 = b[44:42];
+ 28'b????????????1???????????????:
+ \6902 = b[47:45];
+ 28'b???????????1????????????????:
+ \6902 = b[50:48];
+ 28'b??????????1?????????????????:
+ \6902 = b[53:51];
+ 28'b?????????1??????????????????:
+ \6902 = b[56:54];
+ 28'b????????1???????????????????:
+ \6902 = b[59:57];
+ 28'b???????1????????????????????:
+ \6902 = b[62:60];
+ 28'b??????1?????????????????????:
+ \6902 = b[65:63];
+ 28'b?????1??????????????????????:
+ \6902 = b[68:66];
+ 28'b????1???????????????????????:
+ \6902 = b[71:69];
+ 28'b???1????????????????????????:
+ \6902 = b[74:72];
+ 28'b??1?????????????????????????:
+ \6902 = b[77:75];
+ 28'b?1??????????????????????????:
+ \6902 = b[80:78];
+ 28'b1???????????????????????????:
+ \6902 = b[83:81];
+ default:
+ \6902 = a;
+ endcase
+ endfunction
+ assign _0586_ = \6902 (ctrl[191:189], { ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], _0525_, ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], b_in[63:61], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189], ctrl[191:189] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [127:0] \6904 ;
+ input [127:0] a;
+ input [3583:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6904 = b[127:0];
+ 28'b??????????????????????????1?:
+ \6904 = b[255:128];
+ 28'b?????????????????????????1??:
+ \6904 = b[383:256];
+ 28'b????????????????????????1???:
+ \6904 = b[511:384];
+ 28'b???????????????????????1????:
+ \6904 = b[639:512];
+ 28'b??????????????????????1?????:
+ \6904 = b[767:640];
+ 28'b?????????????????????1??????:
+ \6904 = b[895:768];
+ 28'b????????????????????1???????:
+ \6904 = b[1023:896];
+ 28'b???????????????????1????????:
+ \6904 = b[1151:1024];
+ 28'b??????????????????1?????????:
+ \6904 = b[1279:1152];
+ 28'b?????????????????1??????????:
+ \6904 = b[1407:1280];
+ 28'b????????????????1???????????:
+ \6904 = b[1535:1408];
+ 28'b???????????????1????????????:
+ \6904 = b[1663:1536];
+ 28'b??????????????1?????????????:
+ \6904 = b[1791:1664];
+ 28'b?????????????1??????????????:
+ \6904 = b[1919:1792];
+ 28'b????????????1???????????????:
+ \6904 = b[2047:1920];
+ 28'b???????????1????????????????:
+ \6904 = b[2175:2048];
+ 28'b??????????1?????????????????:
+ \6904 = b[2303:2176];
+ 28'b?????????1??????????????????:
+ \6904 = b[2431:2304];
+ 28'b????????1???????????????????:
+ \6904 = b[2559:2432];
+ 28'b???????1????????????????????:
+ \6904 = b[2687:2560];
+ 28'b??????1?????????????????????:
+ \6904 = b[2815:2688];
+ 28'b?????1??????????????????????:
+ \6904 = b[2943:2816];
+ 28'b????1???????????????????????:
+ \6904 = b[3071:2944];
+ 28'b???1????????????????????????:
+ \6904 = b[3199:3072];
+ 28'b??1?????????????????????????:
+ \6904 = b[3327:3200];
+ 28'b?1??????????????????????????:
+ \6904 = b[3455:3328];
+ 28'b1???????????????????????????:
+ \6904 = b[3583:3456];
+ default:
+ \6904 = a;
+ endcase
+ endfunction
+ assign _0587_ = \6904 ({ ctrl[320:257], _0045_ }, { ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, _0145_, ctrl[320:257], _0045_, ctrl[320:257], _0045_, _0071_, ctrl[320:257], _0045_ }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6905 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6905 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6905 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6905 = b[2:2];
+ 28'b????????????????????????1???:
+ \6905 = b[3:3];
+ 28'b???????????????????????1????:
+ \6905 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6905 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6905 = b[6:6];
+ 28'b????????????????????1???????:
+ \6905 = b[7:7];
+ 28'b???????????????????1????????:
+ \6905 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6905 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6905 = b[10:10];
+ 28'b????????????????1???????????:
+ \6905 = b[11:11];
+ 28'b???????????????1????????????:
+ \6905 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6905 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6905 = b[14:14];
+ 28'b????????????1???????????????:
+ \6905 = b[15:15];
+ 28'b???????????1????????????????:
+ \6905 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6905 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6905 = b[18:18];
+ 28'b????????1???????????????????:
+ \6905 = b[19:19];
+ 28'b???????1????????????????????:
+ \6905 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6905 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6905 = b[22:22];
+ 28'b????1???????????????????????:
+ \6905 = b[23:23];
+ 28'b???1????????????????????????:
+ \6905 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6905 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6905 = b[26:26];
+ 28'b1???????????????????????????:
+ \6905 = b[27:27];
+ default:
+ \6905 = a;
+ endcase
+ endfunction
+ assign _0588_ = \6905 (1'h0, 28'h4000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6906 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6906 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6906 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6906 = b[2:2];
+ 28'b????????????????????????1???:
+ \6906 = b[3:3];
+ 28'b???????????????????????1????:
+ \6906 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6906 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6906 = b[6:6];
+ 28'b????????????????????1???????:
+ \6906 = b[7:7];
+ 28'b???????????????????1????????:
+ \6906 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6906 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6906 = b[10:10];
+ 28'b????????????????1???????????:
+ \6906 = b[11:11];
+ 28'b???????????????1????????????:
+ \6906 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6906 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6906 = b[14:14];
+ 28'b????????????1???????????????:
+ \6906 = b[15:15];
+ 28'b???????????1????????????????:
+ \6906 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6906 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6906 = b[18:18];
+ 28'b????????1???????????????????:
+ \6906 = b[19:19];
+ 28'b???????1????????????????????:
+ \6906 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6906 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6906 = b[22:22];
+ 28'b????1???????????????????????:
+ \6906 = b[23:23];
+ 28'b???1????????????????????????:
+ \6906 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6906 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6906 = b[26:26];
+ 28'b1???????????????????????????:
+ \6906 = b[27:27];
+ default:
+ \6906 = a;
+ endcase
+ endfunction
+ assign _0589_ = \6906 (1'h0, 28'h8000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6909 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6909 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6909 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6909 = b[2:2];
+ 28'b????????????????????????1???:
+ \6909 = b[3:3];
+ 28'b???????????????????????1????:
+ \6909 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6909 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6909 = b[6:6];
+ 28'b????????????????????1???????:
+ \6909 = b[7:7];
+ 28'b???????????????????1????????:
+ \6909 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6909 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6909 = b[10:10];
+ 28'b????????????????1???????????:
+ \6909 = b[11:11];
+ 28'b???????????????1????????????:
+ \6909 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6909 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6909 = b[14:14];
+ 28'b????????????1???????????????:
+ \6909 = b[15:15];
+ 28'b???????????1????????????????:
+ \6909 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6909 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6909 = b[18:18];
+ 28'b????????1???????????????????:
+ \6909 = b[19:19];
+ 28'b???????1????????????????????:
+ \6909 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6909 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6909 = b[22:22];
+ 28'b????1???????????????????????:
+ \6909 = b[23:23];
+ 28'b???1????????????????????????:
+ \6909 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6909 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6909 = b[26:26];
+ 28'b1???????????????????????????:
+ \6909 = b[27:27];
+ default:
+ \6909 = a;
+ endcase
+ endfunction
+ assign _0590_ = \6909 (1'h1, { 4'h3, _0541_[0], 18'h3ffbf, _0146_[0], 4'hf }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [1:0] \6913 ;
+ input [1:0] a;
+ input [55:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6913 = b[1:0];
+ 28'b??????????????????????????1?:
+ \6913 = b[3:2];
+ 28'b?????????????????????????1??:
+ \6913 = b[5:4];
+ 28'b????????????????????????1???:
+ \6913 = b[7:6];
+ 28'b???????????????????????1????:
+ \6913 = b[9:8];
+ 28'b??????????????????????1?????:
+ \6913 = b[11:10];
+ 28'b?????????????????????1??????:
+ \6913 = b[13:12];
+ 28'b????????????????????1???????:
+ \6913 = b[15:14];
+ 28'b???????????????????1????????:
+ \6913 = b[17:16];
+ 28'b??????????????????1?????????:
+ \6913 = b[19:18];
+ 28'b?????????????????1??????????:
+ \6913 = b[21:20];
+ 28'b????????????????1???????????:
+ \6913 = b[23:22];
+ 28'b???????????????1????????????:
+ \6913 = b[25:24];
+ 28'b??????????????1?????????????:
+ \6913 = b[27:26];
+ 28'b?????????????1??????????????:
+ \6913 = b[29:28];
+ 28'b????????????1???????????????:
+ \6913 = b[31:30];
+ 28'b???????????1????????????????:
+ \6913 = b[33:32];
+ 28'b??????????1?????????????????:
+ \6913 = b[35:34];
+ 28'b?????????1??????????????????:
+ \6913 = b[37:36];
+ 28'b????????1???????????????????:
+ \6913 = b[39:38];
+ 28'b???????1????????????????????:
+ \6913 = b[41:40];
+ 28'b??????1?????????????????????:
+ \6913 = b[43:42];
+ 28'b?????1??????????????????????:
+ \6913 = b[45:44];
+ 28'b????1???????????????????????:
+ \6913 = b[47:46];
+ 28'b???1????????????????????????:
+ \6913 = b[49:48];
+ 28'b??1?????????????????????????:
+ \6913 = b[51:50];
+ 28'b?1??????????????????????????:
+ \6913 = b[53:52];
+ 28'b1???????????????????????????:
+ \6913 = b[55:54];
+ default:
+ \6913 = a;
+ endcase
+ endfunction
+ assign _0591_ = \6913 (2'h0, { 8'h00, _0541_[2:1], 36'h000000000, _0146_[2:1], 8'h00 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [5:0] \6916 ;
+ input [5:0] a;
+ input [167:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6916 = b[5:0];
+ 28'b??????????????????????????1?:
+ \6916 = b[11:6];
+ 28'b?????????????????????????1??:
+ \6916 = b[17:12];
+ 28'b????????????????????????1???:
+ \6916 = b[23:18];
+ 28'b???????????????????????1????:
+ \6916 = b[29:24];
+ 28'b??????????????????????1?????:
+ \6916 = b[35:30];
+ 28'b?????????????????????1??????:
+ \6916 = b[41:36];
+ 28'b????????????????????1???????:
+ \6916 = b[47:42];
+ 28'b???????????????????1????????:
+ \6916 = b[53:48];
+ 28'b??????????????????1?????????:
+ \6916 = b[59:54];
+ 28'b?????????????????1??????????:
+ \6916 = b[65:60];
+ 28'b????????????????1???????????:
+ \6916 = b[71:66];
+ 28'b???????????????1????????????:
+ \6916 = b[77:72];
+ 28'b??????????????1?????????????:
+ \6916 = b[83:78];
+ 28'b?????????????1??????????????:
+ \6916 = b[89:84];
+ 28'b????????????1???????????????:
+ \6916 = b[95:90];
+ 28'b???????????1????????????????:
+ \6916 = b[101:96];
+ 28'b??????????1?????????????????:
+ \6916 = b[107:102];
+ 28'b?????????1??????????????????:
+ \6916 = b[113:108];
+ 28'b????????1???????????????????:
+ \6916 = b[119:114];
+ 28'b???????1????????????????????:
+ \6916 = b[125:120];
+ 28'b??????1?????????????????????:
+ \6916 = b[131:126];
+ 28'b?????1??????????????????????:
+ \6916 = b[137:132];
+ 28'b????1???????????????????????:
+ \6916 = b[143:138];
+ 28'b???1????????????????????????:
+ \6916 = b[149:144];
+ 28'b??1?????????????????????????:
+ \6916 = b[155:150];
+ 28'b?1??????????????????????????:
+ \6916 = b[161:156];
+ 28'b1???????????????????????????:
+ \6916 = b[167:162];
+ default:
+ \6916 = a;
+ endcase
+ endfunction
+ assign _0592_ = \6916 (e_in[78:73], { e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], _0541_[8:3], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73], _0189_, _0166_, e_in[78:73], e_in[78:73], _0146_[8:3], e_in[78:73], e_in[78:73], e_in[78:73], e_in[78:73] }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [63:0] \6920 ;
+ input [63:0] a;
+ input [1791:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6920 = b[63:0];
+ 28'b??????????????????????????1?:
+ \6920 = b[127:64];
+ 28'b?????????????????????????1??:
+ \6920 = b[191:128];
+ 28'b????????????????????????1???:
+ \6920 = b[255:192];
+ 28'b???????????????????????1????:
+ \6920 = b[319:256];
+ 28'b??????????????????????1?????:
+ \6920 = b[383:320];
+ 28'b?????????????????????1??????:
+ \6920 = b[447:384];
+ 28'b????????????????????1???????:
+ \6920 = b[511:448];
+ 28'b???????????????????1????????:
+ \6920 = b[575:512];
+ 28'b??????????????????1?????????:
+ \6920 = b[639:576];
+ 28'b?????????????????1??????????:
+ \6920 = b[703:640];
+ 28'b????????????????1???????????:
+ \6920 = b[767:704];
+ 28'b???????????????1????????????:
+ \6920 = b[831:768];
+ 28'b??????????????1?????????????:
+ \6920 = b[895:832];
+ 28'b?????????????1??????????????:
+ \6920 = b[959:896];
+ 28'b????????????1???????????????:
+ \6920 = b[1023:960];
+ 28'b???????????1????????????????:
+ \6920 = b[1087:1024];
+ 28'b??????????1?????????????????:
+ \6920 = b[1151:1088];
+ 28'b?????????1??????????????????:
+ \6920 = b[1215:1152];
+ 28'b????????1???????????????????:
+ \6920 = b[1279:1216];
+ 28'b???????1????????????????????:
+ \6920 = b[1343:1280];
+ 28'b??????1?????????????????????:
+ \6920 = b[1407:1344];
+ 28'b?????1??????????????????????:
+ \6920 = b[1471:1408];
+ 28'b????1???????????????????????:
+ \6920 = b[1535:1472];
+ 28'b???1????????????????????????:
+ \6920 = b[1599:1536];
+ 28'b??1?????????????????????????:
+ \6920 = b[1663:1600];
+ 28'b?1??????????????????????????:
+ \6920 = b[1727:1664];
+ 28'b1???????????????????????????:
+ \6920 = b[1791:1728];
+ default:
+ \6920 = a;
+ endcase
+ endfunction
+ assign _0593_ = \6920 (64'h0000000000000000, { 256'h0000000000000000000000000000000000000000000000000000000000000000, _0541_[72:9], 1152'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, _0146_[72:9], 256'h0000000000000000000000000000000000000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6925 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6925 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6925 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6925 = b[2:2];
+ 28'b????????????????????????1???:
+ \6925 = b[3:3];
+ 28'b???????????????????????1????:
+ \6925 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6925 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6925 = b[6:6];
+ 28'b????????????????????1???????:
+ \6925 = b[7:7];
+ 28'b???????????????????1????????:
+ \6925 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6925 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6925 = b[10:10];
+ 28'b????????????????1???????????:
+ \6925 = b[11:11];
+ 28'b???????????????1????????????:
+ \6925 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6925 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6925 = b[14:14];
+ 28'b????????????1???????????????:
+ \6925 = b[15:15];
+ 28'b???????????1????????????????:
+ \6925 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6925 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6925 = b[18:18];
+ 28'b????????1???????????????????:
+ \6925 = b[19:19];
+ 28'b???????1????????????????????:
+ \6925 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6925 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6925 = b[22:22];
+ 28'b????1???????????????????????:
+ \6925 = b[23:23];
+ 28'b???1????????????????????????:
+ \6925 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6925 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6925 = b[26:26];
+ 28'b1???????????????????????????:
+ \6925 = b[27:27];
+ default:
+ \6925 = a;
+ endcase
+ endfunction
+ assign _0594_ = \6925 (1'h0, { 4'h0, _0541_[73], 8'h08, _0346_[0], 9'h000, _0147_[0], 4'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [7:0] \6930 ;
+ input [7:0] a;
+ input [223:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6930 = b[7:0];
+ 28'b??????????????????????????1?:
+ \6930 = b[15:8];
+ 28'b?????????????????????????1??:
+ \6930 = b[23:16];
+ 28'b????????????????????????1???:
+ \6930 = b[31:24];
+ 28'b???????????????????????1????:
+ \6930 = b[39:32];
+ 28'b??????????????????????1?????:
+ \6930 = b[47:40];
+ 28'b?????????????????????1??????:
+ \6930 = b[55:48];
+ 28'b????????????????????1???????:
+ \6930 = b[63:56];
+ 28'b???????????????????1????????:
+ \6930 = b[71:64];
+ 28'b??????????????????1?????????:
+ \6930 = b[79:72];
+ 28'b?????????????????1??????????:
+ \6930 = b[87:80];
+ 28'b????????????????1???????????:
+ \6930 = b[95:88];
+ 28'b???????????????1????????????:
+ \6930 = b[103:96];
+ 28'b??????????????1?????????????:
+ \6930 = b[111:104];
+ 28'b?????????????1??????????????:
+ \6930 = b[119:112];
+ 28'b????????????1???????????????:
+ \6930 = b[127:120];
+ 28'b???????????1????????????????:
+ \6930 = b[135:128];
+ 28'b??????????1?????????????????:
+ \6930 = b[143:136];
+ 28'b?????????1??????????????????:
+ \6930 = b[151:144];
+ 28'b????????1???????????????????:
+ \6930 = b[159:152];
+ 28'b???????1????????????????????:
+ \6930 = b[167:160];
+ 28'b??????1?????????????????????:
+ \6930 = b[175:168];
+ 28'b?????1??????????????????????:
+ \6930 = b[183:176];
+ 28'b????1???????????????????????:
+ \6930 = b[191:184];
+ 28'b???1????????????????????????:
+ \6930 = b[199:192];
+ 28'b??1?????????????????????????:
+ \6930 = b[207:200];
+ 28'b?1??????????????????????????:
+ \6930 = b[215:208];
+ 28'b1???????????????????????????:
+ \6930 = b[223:216];
+ default:
+ \6930 = a;
+ endcase
+ endfunction
+ assign _0595_ = \6930 (8'h00, { 32'h00000000, _0541_[81:74], 32'h00000000, _0516_, 24'h000000, _0346_[8:1], 72'h000000000000000000, _0147_[8:1], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [31:0] \6935 ;
+ input [31:0] a;
+ input [895:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6935 = b[31:0];
+ 28'b??????????????????????????1?:
+ \6935 = b[63:32];
+ 28'b?????????????????????????1??:
+ \6935 = b[95:64];
+ 28'b????????????????????????1???:
+ \6935 = b[127:96];
+ 28'b???????????????????????1????:
+ \6935 = b[159:128];
+ 28'b??????????????????????1?????:
+ \6935 = b[191:160];
+ 28'b?????????????????????1??????:
+ \6935 = b[223:192];
+ 28'b????????????????????1???????:
+ \6935 = b[255:224];
+ 28'b???????????????????1????????:
+ \6935 = b[287:256];
+ 28'b??????????????????1?????????:
+ \6935 = b[319:288];
+ 28'b?????????????????1??????????:
+ \6935 = b[351:320];
+ 28'b????????????????1???????????:
+ \6935 = b[383:352];
+ 28'b???????????????1????????????:
+ \6935 = b[415:384];
+ 28'b??????????????1?????????????:
+ \6935 = b[447:416];
+ 28'b?????????????1??????????????:
+ \6935 = b[479:448];
+ 28'b????????????1???????????????:
+ \6935 = b[511:480];
+ 28'b???????????1????????????????:
+ \6935 = b[543:512];
+ 28'b??????????1?????????????????:
+ \6935 = b[575:544];
+ 28'b?????????1??????????????????:
+ \6935 = b[607:576];
+ 28'b????????1???????????????????:
+ \6935 = b[639:608];
+ 28'b???????1????????????????????:
+ \6935 = b[671:640];
+ 28'b??????1?????????????????????:
+ \6935 = b[703:672];
+ 28'b?????1??????????????????????:
+ \6935 = b[735:704];
+ 28'b????1???????????????????????:
+ \6935 = b[767:736];
+ 28'b???1????????????????????????:
+ \6935 = b[799:768];
+ 28'b??1?????????????????????????:
+ \6935 = b[831:800];
+ 28'b?1??????????????????????????:
+ \6935 = b[863:832];
+ 28'b1???????????????????????????:
+ \6935 = b[895:864];
+ default:
+ \6935 = a;
+ endcase
+ endfunction
+ assign _0596_ = \6935 (32'd0, { 128'h00000000000000000000000000000000, _0541_[113:82], 128'h00000000000000000000000000000000, c_in[31:0], 96'h000000000000000000000000, _0346_[40:9], 288'h000000000000000000000000000000000000000000000000000000000000000000000000, _0147_[40:9], 128'h00000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [5:0] \6940 ;
+ input [5:0] a;
+ input [167:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6940 = b[5:0];
+ 28'b??????????????????????????1?:
+ \6940 = b[11:6];
+ 28'b?????????????????????????1??:
+ \6940 = b[17:12];
+ 28'b????????????????????????1???:
+ \6940 = b[23:18];
+ 28'b???????????????????????1????:
+ \6940 = b[29:24];
+ 28'b??????????????????????1?????:
+ \6940 = b[35:30];
+ 28'b?????????????????????1??????:
+ \6940 = b[41:36];
+ 28'b????????????????????1???????:
+ \6940 = b[47:42];
+ 28'b???????????????????1????????:
+ \6940 = b[53:48];
+ 28'b??????????????????1?????????:
+ \6940 = b[59:54];
+ 28'b?????????????????1??????????:
+ \6940 = b[65:60];
+ 28'b????????????????1???????????:
+ \6940 = b[71:66];
+ 28'b???????????????1????????????:
+ \6940 = b[77:72];
+ 28'b??????????????1?????????????:
+ \6940 = b[83:78];
+ 28'b?????????????1??????????????:
+ \6940 = b[89:84];
+ 28'b????????????1???????????????:
+ \6940 = b[95:90];
+ 28'b???????????1????????????????:
+ \6940 = b[101:96];
+ 28'b??????????1?????????????????:
+ \6940 = b[107:102];
+ 28'b?????????1??????????????????:
+ \6940 = b[113:108];
+ 28'b????????1???????????????????:
+ \6940 = b[119:114];
+ 28'b???????1????????????????????:
+ \6940 = b[125:120];
+ 28'b??????1?????????????????????:
+ \6940 = b[131:126];
+ 28'b?????1??????????????????????:
+ \6940 = b[137:132];
+ 28'b????1???????????????????????:
+ \6940 = b[143:138];
+ 28'b???1????????????????????????:
+ \6940 = b[149:144];
+ 28'b??1?????????????????????????:
+ \6940 = b[155:150];
+ 28'b?1??????????????????????????:
+ \6940 = b[161:156];
+ 28'b1???????????????????????????:
+ \6940 = b[167:162];
+ default:
+ \6940 = a;
+ endcase
+ endfunction
+ assign _0597_ = \6940 ({ _0013_, 1'h0 }, { _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0541_[119:114], _0013_, 1'h0, _0013_, 1'h0, _0534_, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0148_[5:0], _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0, _0013_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [70:0] \6944 ;
+ input [70:0] a;
+ input [1987:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6944 = b[70:0];
+ 28'b??????????????????????????1?:
+ \6944 = b[141:71];
+ 28'b?????????????????????????1??:
+ \6944 = b[212:142];
+ 28'b????????????????????????1???:
+ \6944 = b[283:213];
+ 28'b???????????????????????1????:
+ \6944 = b[354:284];
+ 28'b??????????????????????1?????:
+ \6944 = b[425:355];
+ 28'b?????????????????????1??????:
+ \6944 = b[496:426];
+ 28'b????????????????????1???????:
+ \6944 = b[567:497];
+ 28'b???????????????????1????????:
+ \6944 = b[638:568];
+ 28'b??????????????????1?????????:
+ \6944 = b[709:639];
+ 28'b?????????????????1??????????:
+ \6944 = b[780:710];
+ 28'b????????????????1???????????:
+ \6944 = b[851:781];
+ 28'b???????????????1????????????:
+ \6944 = b[922:852];
+ 28'b??????????????1?????????????:
+ \6944 = b[993:923];
+ 28'b?????????????1??????????????:
+ \6944 = b[1064:994];
+ 28'b????????????1???????????????:
+ \6944 = b[1135:1065];
+ 28'b???????????1????????????????:
+ \6944 = b[1206:1136];
+ 28'b??????????1?????????????????:
+ \6944 = b[1277:1207];
+ 28'b?????????1??????????????????:
+ \6944 = b[1348:1278];
+ 28'b????????1???????????????????:
+ \6944 = b[1419:1349];
+ 28'b???????1????????????????????:
+ \6944 = b[1490:1420];
+ 28'b??????1?????????????????????:
+ \6944 = b[1561:1491];
+ 28'b?????1??????????????????????:
+ \6944 = b[1632:1562];
+ 28'b????1???????????????????????:
+ \6944 = b[1703:1633];
+ 28'b???1????????????????????????:
+ \6944 = b[1774:1704];
+ 28'b??1?????????????????????????:
+ \6944 = b[1845:1775];
+ 28'b?1??????????????????????????:
+ \6944 = b[1916:1846];
+ 28'b1???????????????????????????:
+ \6944 = b[1987:1917];
+ default:
+ \6944 = a;
+ endcase
+ endfunction
+ assign _0598_ = \6944 ({ e_in[72:9], 7'h44 }, { e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, _0541_[190:120], e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, _0148_[76:6], e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44, e_in[72:9], 7'h44 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6945 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6945 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6945 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6945 = b[2:2];
+ 28'b????????????????????????1???:
+ \6945 = b[3:3];
+ 28'b???????????????????????1????:
+ \6945 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6945 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6945 = b[6:6];
+ 28'b????????????????????1???????:
+ \6945 = b[7:7];
+ 28'b???????????????????1????????:
+ \6945 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6945 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6945 = b[10:10];
+ 28'b????????????????1???????????:
+ \6945 = b[11:11];
+ 28'b???????????????1????????????:
+ \6945 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6945 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6945 = b[14:14];
+ 28'b????????????1???????????????:
+ \6945 = b[15:15];
+ 28'b???????????1????????????????:
+ \6945 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6945 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6945 = b[18:18];
+ 28'b????????1???????????????????:
+ \6945 = b[19:19];
+ 28'b???????1????????????????????:
+ \6945 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6945 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6945 = b[22:22];
+ 28'b????1???????????????????????:
+ \6945 = b[23:23];
+ 28'b???1????????????????????????:
+ \6945 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6945 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6945 = b[26:26];
+ 28'b1???????????????????????????:
+ \6945 = b[27:27];
+ default:
+ \6945 = a;
+ endcase
+ endfunction
+ assign _0599_ = \6945 (1'h0, 28'h4000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6946 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6946 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6946 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6946 = b[2:2];
+ 28'b????????????????????????1???:
+ \6946 = b[3:3];
+ 28'b???????????????????????1????:
+ \6946 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6946 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6946 = b[6:6];
+ 28'b????????????????????1???????:
+ \6946 = b[7:7];
+ 28'b???????????????????1????????:
+ \6946 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6946 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6946 = b[10:10];
+ 28'b????????????????1???????????:
+ \6946 = b[11:11];
+ 28'b???????????????1????????????:
+ \6946 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6946 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6946 = b[14:14];
+ 28'b????????????1???????????????:
+ \6946 = b[15:15];
+ 28'b???????????1????????????????:
+ \6946 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6946 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6946 = b[18:18];
+ 28'b????????1???????????????????:
+ \6946 = b[19:19];
+ 28'b???????1????????????????????:
+ \6946 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6946 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6946 = b[22:22];
+ 28'b????1???????????????????????:
+ \6946 = b[23:23];
+ 28'b???1????????????????????????:
+ \6946 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6946 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6946 = b[26:26];
+ 28'b1???????????????????????????:
+ \6946 = b[27:27];
+ default:
+ \6946 = a;
+ endcase
+ endfunction
+ assign _0600_ = \6946 (1'h0, 28'h8000000, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \6947 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6947 = b[0:0];
+ 28'b??????????????????????????1?:
+ \6947 = b[1:1];
+ 28'b?????????????????????????1??:
+ \6947 = b[2:2];
+ 28'b????????????????????????1???:
+ \6947 = b[3:3];
+ 28'b???????????????????????1????:
+ \6947 = b[4:4];
+ 28'b??????????????????????1?????:
+ \6947 = b[5:5];
+ 28'b?????????????????????1??????:
+ \6947 = b[6:6];
+ 28'b????????????????????1???????:
+ \6947 = b[7:7];
+ 28'b???????????????????1????????:
+ \6947 = b[8:8];
+ 28'b??????????????????1?????????:
+ \6947 = b[9:9];
+ 28'b?????????????????1??????????:
+ \6947 = b[10:10];
+ 28'b????????????????1???????????:
+ \6947 = b[11:11];
+ 28'b???????????????1????????????:
+ \6947 = b[12:12];
+ 28'b??????????????1?????????????:
+ \6947 = b[13:13];
+ 28'b?????????????1??????????????:
+ \6947 = b[14:14];
+ 28'b????????????1???????????????:
+ \6947 = b[15:15];
+ 28'b???????????1????????????????:
+ \6947 = b[16:16];
+ 28'b??????????1?????????????????:
+ \6947 = b[17:17];
+ 28'b?????????1??????????????????:
+ \6947 = b[18:18];
+ 28'b????????1???????????????????:
+ \6947 = b[19:19];
+ 28'b???????1????????????????????:
+ \6947 = b[20:20];
+ 28'b??????1?????????????????????:
+ \6947 = b[21:21];
+ 28'b?????1??????????????????????:
+ \6947 = b[22:22];
+ 28'b????1???????????????????????:
+ \6947 = b[23:23];
+ 28'b???1????????????????????????:
+ \6947 = b[24:24];
+ 28'b??1?????????????????????????:
+ \6947 = b[25:25];
+ 28'b?1??????????????????????????:
+ \6947 = b[26:26];
+ 28'b1???????????????????????????:
+ \6947 = b[27:27];
+ default:
+ \6947 = a;
+ endcase
+ endfunction
+ assign _0601_ = \6947 (1'h0, 28'h0000800, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [7:0] \6963 ;
+ input [7:0] a;
+ input [223:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6963 = b[7:0];
+ 28'b??????????????????????????1?:
+ \6963 = b[15:8];
+ 28'b?????????????????????????1??:
+ \6963 = b[23:16];
+ 28'b????????????????????????1???:
+ \6963 = b[31:24];
+ 28'b???????????????????????1????:
+ \6963 = b[39:32];
+ 28'b??????????????????????1?????:
+ \6963 = b[47:40];
+ 28'b?????????????????????1??????:
+ \6963 = b[55:48];
+ 28'b????????????????????1???????:
+ \6963 = b[63:56];
+ 28'b???????????????????1????????:
+ \6963 = b[71:64];
+ 28'b??????????????????1?????????:
+ \6963 = b[79:72];
+ 28'b?????????????????1??????????:
+ \6963 = b[87:80];
+ 28'b????????????????1???????????:
+ \6963 = b[95:88];
+ 28'b???????????????1????????????:
+ \6963 = b[103:96];
+ 28'b??????????????1?????????????:
+ \6963 = b[111:104];
+ 28'b?????????????1??????????????:
+ \6963 = b[119:112];
+ 28'b????????????1???????????????:
+ \6963 = b[127:120];
+ 28'b???????????1????????????????:
+ \6963 = b[135:128];
+ 28'b??????????1?????????????????:
+ \6963 = b[143:136];
+ 28'b?????????1??????????????????:
+ \6963 = b[151:144];
+ 28'b????????1???????????????????:
+ \6963 = b[159:152];
+ 28'b???????1????????????????????:
+ \6963 = b[167:160];
+ 28'b??????1?????????????????????:
+ \6963 = b[175:168];
+ 28'b?????1??????????????????????:
+ \6963 = b[183:176];
+ 28'b????1???????????????????????:
+ \6963 = b[191:184];
+ 28'b???1????????????????????????:
+ \6963 = b[199:192];
+ 28'b??1?????????????????????????:
+ \6963 = b[207:200];
+ 28'b?1??????????????????????????:
+ \6963 = b[215:208];
+ 28'b1???????????????????????????:
+ \6963 = b[223:216];
+ default:
+ \6963 = a;
+ endcase
+ endfunction
+ assign _0602_ = \6963 (8'h00, { 32'h00000000, rotator_result[7:0], parity_result[7:0], popcnt_result[7:0], _0535_[7:0], 16'h0000, _0440_[7:0], _0356_[7:0], ctrl[135:128], 8'h00, _0239_[7:0], c_in[7:0], 8'h00, _0212_, 8'h00, _0190_[7:0], _0167_[7:0], 8'h00, logical_result[7:0], _0089_[7:0], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [7:0] \6978 ;
+ input [7:0] a;
+ input [223:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6978 = b[7:0];
+ 28'b??????????????????????????1?:
+ \6978 = b[15:8];
+ 28'b?????????????????????????1??:
+ \6978 = b[23:16];
+ 28'b????????????????????????1???:
+ \6978 = b[31:24];
+ 28'b???????????????????????1????:
+ \6978 = b[39:32];
+ 28'b??????????????????????1?????:
+ \6978 = b[47:40];
+ 28'b?????????????????????1??????:
+ \6978 = b[55:48];
+ 28'b????????????????????1???????:
+ \6978 = b[63:56];
+ 28'b???????????????????1????????:
+ \6978 = b[71:64];
+ 28'b??????????????????1?????????:
+ \6978 = b[79:72];
+ 28'b?????????????????1??????????:
+ \6978 = b[87:80];
+ 28'b????????????????1???????????:
+ \6978 = b[95:88];
+ 28'b???????????????1????????????:
+ \6978 = b[103:96];
+ 28'b??????????????1?????????????:
+ \6978 = b[111:104];
+ 28'b?????????????1??????????????:
+ \6978 = b[119:112];
+ 28'b????????????1???????????????:
+ \6978 = b[127:120];
+ 28'b???????????1????????????????:
+ \6978 = b[135:128];
+ 28'b??????????1?????????????????:
+ \6978 = b[143:136];
+ 28'b?????????1??????????????????:
+ \6978 = b[151:144];
+ 28'b????????1???????????????????:
+ \6978 = b[159:152];
+ 28'b???????1????????????????????:
+ \6978 = b[167:160];
+ 28'b??????1?????????????????????:
+ \6978 = b[175:168];
+ 28'b?????1??????????????????????:
+ \6978 = b[183:176];
+ 28'b????1???????????????????????:
+ \6978 = b[191:184];
+ 28'b???1????????????????????????:
+ \6978 = b[199:192];
+ 28'b??1?????????????????????????:
+ \6978 = b[207:200];
+ 28'b?1??????????????????????????:
+ \6978 = b[215:208];
+ 28'b1???????????????????????????:
+ \6978 = b[223:216];
+ default:
+ \6978 = a;
+ endcase
+ endfunction
+ assign _0603_ = \6978 (8'h00, { 32'h00000000, rotator_result[15:8], parity_result[15:8], popcnt_result[15:8], _0535_[15:8], 16'h0000, _0440_[15:8], _0356_[15:8], ctrl[143:136], 8'h00, _0239_[15:8], _0236_, 8'h00, _0214_, 8'h00, _0190_[15:8], _0167_[15:8], 8'h00, logical_result[15:8], _0089_[15:8], 32'h00000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [15:0] \6993 ;
+ input [15:0] a;
+ input [447:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \6993 = b[15:0];
+ 28'b??????????????????????????1?:
+ \6993 = b[31:16];
+ 28'b?????????????????????????1??:
+ \6993 = b[47:32];
+ 28'b????????????????????????1???:
+ \6993 = b[63:48];
+ 28'b???????????????????????1????:
+ \6993 = b[79:64];
+ 28'b??????????????????????1?????:
+ \6993 = b[95:80];
+ 28'b?????????????????????1??????:
+ \6993 = b[111:96];
+ 28'b????????????????????1???????:
+ \6993 = b[127:112];
+ 28'b???????????????????1????????:
+ \6993 = b[143:128];
+ 28'b??????????????????1?????????:
+ \6993 = b[159:144];
+ 28'b?????????????????1??????????:
+ \6993 = b[175:160];
+ 28'b????????????????1???????????:
+ \6993 = b[191:176];
+ 28'b???????????????1????????????:
+ \6993 = b[207:192];
+ 28'b??????????????1?????????????:
+ \6993 = b[223:208];
+ 28'b?????????????1??????????????:
+ \6993 = b[239:224];
+ 28'b????????????1???????????????:
+ \6993 = b[255:240];
+ 28'b???????????1????????????????:
+ \6993 = b[271:256];
+ 28'b??????????1?????????????????:
+ \6993 = b[287:272];
+ 28'b?????????1??????????????????:
+ \6993 = b[303:288];
+ 28'b????????1???????????????????:
+ \6993 = b[319:304];
+ 28'b???????1????????????????????:
+ \6993 = b[335:320];
+ 28'b??????1?????????????????????:
+ \6993 = b[351:336];
+ 28'b?????1??????????????????????:
+ \6993 = b[367:352];
+ 28'b????1???????????????????????:
+ \6993 = b[383:368];
+ 28'b???1????????????????????????:
+ \6993 = b[399:384];
+ 28'b??1?????????????????????????:
+ \6993 = b[415:400];
+ 28'b?1??????????????????????????:
+ \6993 = b[431:416];
+ 28'b1???????????????????????????:
+ \6993 = b[447:432];
+ default:
+ \6993 = a;
+ endcase
+ endfunction
+ assign _0604_ = \6993 (16'h0000, { 64'h0000000000000000, rotator_result[31:16], parity_result[31:16], popcnt_result[31:16], _0535_[31:16], 32'h00000000, _0440_[31:16], _0356_[31:16], ctrl[159:144], 16'h0000, _0239_[31:16], _0234_, 16'h0000, _0218_, _0216_, 16'h0000, _0190_[31:16], _0167_[31:16], 16'h0000, logical_result[31:16], _0089_[31:16], 64'h0000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [31:0] \7008 ;
+ input [31:0] a;
+ input [895:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \7008 = b[31:0];
+ 28'b??????????????????????????1?:
+ \7008 = b[63:32];
+ 28'b?????????????????????????1??:
+ \7008 = b[95:64];
+ 28'b????????????????????????1???:
+ \7008 = b[127:96];
+ 28'b???????????????????????1????:
+ \7008 = b[159:128];
+ 28'b??????????????????????1?????:
+ \7008 = b[191:160];
+ 28'b?????????????????????1??????:
+ \7008 = b[223:192];
+ 28'b????????????????????1???????:
+ \7008 = b[255:224];
+ 28'b???????????????????1????????:
+ \7008 = b[287:256];
+ 28'b??????????????????1?????????:
+ \7008 = b[319:288];
+ 28'b?????????????????1??????????:
+ \7008 = b[351:320];
+ 28'b????????????????1???????????:
+ \7008 = b[383:352];
+ 28'b???????????????1????????????:
+ \7008 = b[415:384];
+ 28'b??????????????1?????????????:
+ \7008 = b[447:416];
+ 28'b?????????????1??????????????:
+ \7008 = b[479:448];
+ 28'b????????????1???????????????:
+ \7008 = b[511:480];
+ 28'b???????????1????????????????:
+ \7008 = b[543:512];
+ 28'b??????????1?????????????????:
+ \7008 = b[575:544];
+ 28'b?????????1??????????????????:
+ \7008 = b[607:576];
+ 28'b????????1???????????????????:
+ \7008 = b[639:608];
+ 28'b???????1????????????????????:
+ \7008 = b[671:640];
+ 28'b??????1?????????????????????:
+ \7008 = b[703:672];
+ 28'b?????1??????????????????????:
+ \7008 = b[735:704];
+ 28'b????1???????????????????????:
+ \7008 = b[767:736];
+ 28'b???1????????????????????????:
+ \7008 = b[799:768];
+ 28'b??1?????????????????????????:
+ \7008 = b[831:800];
+ 28'b?1??????????????????????????:
+ \7008 = b[863:832];
+ 28'b1???????????????????????????:
+ \7008 = b[895:864];
+ default:
+ \7008 = a;
+ endcase
+ endfunction
+ assign _0605_ = \7008 (32'd0, { 128'h00000000000000000000000000000000, rotator_result[63:32], parity_result[63:32], popcnt_result[63:32], _0535_[63:32], 64'h0000000000000000, _0440_[63:32], _0356_[63:32], ctrl[191:160], 32'h00000000, _0239_[63:32], _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, _0233_, 32'h00000000, _0226_, _0224_, _0222_, _0220_, 32'h00000000, _0190_[63:32], _0167_[63:32], 32'h00000000, logical_result[63:32], _0089_[63:32], 128'h00000000000000000000000000000000 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \7024 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \7024 = b[0:0];
+ 28'b??????????????????????????1?:
+ \7024 = b[1:1];
+ 28'b?????????????????????????1??:
+ \7024 = b[2:2];
+ 28'b????????????????????????1???:
+ \7024 = b[3:3];
+ 28'b???????????????????????1????:
+ \7024 = b[4:4];
+ 28'b??????????????????????1?????:
+ \7024 = b[5:5];
+ 28'b?????????????????????1??????:
+ \7024 = b[6:6];
+ 28'b????????????????????1???????:
+ \7024 = b[7:7];
+ 28'b???????????????????1????????:
+ \7024 = b[8:8];
+ 28'b??????????????????1?????????:
+ \7024 = b[9:9];
+ 28'b?????????????????1??????????:
+ \7024 = b[10:10];
+ 28'b????????????????1???????????:
+ \7024 = b[11:11];
+ 28'b???????????????1????????????:
+ \7024 = b[12:12];
+ 28'b??????????????1?????????????:
+ \7024 = b[13:13];
+ 28'b?????????????1??????????????:
+ \7024 = b[14:14];
+ 28'b????????????1???????????????:
+ \7024 = b[15:15];
+ 28'b???????????1????????????????:
+ \7024 = b[16:16];
+ 28'b??????????1?????????????????:
+ \7024 = b[17:17];
+ 28'b?????????1??????????????????:
+ \7024 = b[18:18];
+ 28'b????????1???????????????????:
+ \7024 = b[19:19];
+ 28'b???????1????????????????????:
+ \7024 = b[20:20];
+ 28'b??????1?????????????????????:
+ \7024 = b[21:21];
+ 28'b?????1??????????????????????:
+ \7024 = b[22:22];
+ 28'b????1???????????????????????:
+ \7024 = b[23:23];
+ 28'b???1????????????????????????:
+ \7024 = b[24:24];
+ 28'b??1?????????????????????????:
+ \7024 = b[25:25];
+ 28'b?1??????????????????????????:
+ \7024 = b[26:26];
+ 28'b1???????????????????????????:
+ \7024 = b[27:27];
+ default:
+ \7024 = a;
+ endcase
+ endfunction
+ assign _0606_ = \7024 (1'h0, { 7'h07, _0536_, 11'h1da, _0191_, _0168_, 2'h1, _0149_, 4'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \7053 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \7053 = b[0:0];
+ 28'b??????????????????????????1?:
+ \7053 = b[1:1];
+ 28'b?????????????????????????1??:
+ \7053 = b[2:2];
+ 28'b????????????????????????1???:
+ \7053 = b[3:3];
+ 28'b???????????????????????1????:
+ \7053 = b[4:4];
+ 28'b??????????????????????1?????:
+ \7053 = b[5:5];
+ 28'b?????????????????????1??????:
+ \7053 = b[6:6];
+ 28'b????????????????????1???????:
+ \7053 = b[7:7];
+ 28'b???????????????????1????????:
+ \7053 = b[8:8];
+ 28'b??????????????????1?????????:
+ \7053 = b[9:9];
+ 28'b?????????????????1??????????:
+ \7053 = b[10:10];
+ 28'b????????????????1???????????:
+ \7053 = b[11:11];
+ 28'b???????????????1????????????:
+ \7053 = b[12:12];
+ 28'b??????????????1?????????????:
+ \7053 = b[13:13];
+ 28'b?????????????1??????????????:
+ \7053 = b[14:14];
+ 28'b????????????1???????????????:
+ \7053 = b[15:15];
+ 28'b???????????1????????????????:
+ \7053 = b[16:16];
+ 28'b??????????1?????????????????:
+ \7053 = b[17:17];
+ 28'b?????????1??????????????????:
+ \7053 = b[18:18];
+ 28'b????????1???????????????????:
+ \7053 = b[19:19];
+ 28'b???????1????????????????????:
+ \7053 = b[20:20];
+ 28'b??????1?????????????????????:
+ \7053 = b[21:21];
+ 28'b?????1??????????????????????:
+ \7053 = b[22:22];
+ 28'b????1???????????????????????:
+ \7053 = b[23:23];
+ 28'b???1????????????????????????:
+ \7053 = b[24:24];
+ 28'b??1?????????????????????????:
+ \7053 = b[25:25];
+ 28'b?1??????????????????????????:
+ \7053 = b[26:26];
+ 28'b1???????????????????????????:
+ \7053 = b[27:27];
+ default:
+ \7053 = a;
+ endcase
+ endfunction
+ assign _0607_ = \7053 (1'h0, { 23'h000000, _0150_, 2'h0, _0072_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \7055 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \7055 = b[0:0];
+ 28'b??????????????????????????1?:
+ \7055 = b[1:1];
+ 28'b?????????????????????????1??:
+ \7055 = b[2:2];
+ 28'b????????????????????????1???:
+ \7055 = b[3:3];
+ 28'b???????????????????????1????:
+ \7055 = b[4:4];
+ 28'b??????????????????????1?????:
+ \7055 = b[5:5];
+ 28'b?????????????????????1??????:
+ \7055 = b[6:6];
+ 28'b????????????????????1???????:
+ \7055 = b[7:7];
+ 28'b???????????????????1????????:
+ \7055 = b[8:8];
+ 28'b??????????????????1?????????:
+ \7055 = b[9:9];
+ 28'b?????????????????1??????????:
+ \7055 = b[10:10];
+ 28'b????????????????1???????????:
+ \7055 = b[11:11];
+ 28'b???????????????1????????????:
+ \7055 = b[12:12];
+ 28'b??????????????1?????????????:
+ \7055 = b[13:13];
+ 28'b?????????????1??????????????:
+ \7055 = b[14:14];
+ 28'b????????????1???????????????:
+ \7055 = b[15:15];
+ 28'b???????????1????????????????:
+ \7055 = b[16:16];
+ 28'b??????????1?????????????????:
+ \7055 = b[17:17];
+ 28'b?????????1??????????????????:
+ \7055 = b[18:18];
+ 28'b????????1???????????????????:
+ \7055 = b[19:19];
+ 28'b???????1????????????????????:
+ \7055 = b[20:20];
+ 28'b??????1?????????????????????:
+ \7055 = b[21:21];
+ 28'b?????1??????????????????????:
+ \7055 = b[22:22];
+ 28'b????1???????????????????????:
+ \7055 = b[23:23];
+ 28'b???1????????????????????????:
+ \7055 = b[24:24];
+ 28'b??1?????????????????????????:
+ \7055 = b[25:25];
+ 28'b?1??????????????????????????:
+ \7055 = b[26:26];
+ 28'b1???????????????????????????:
+ \7055 = b[27:27];
+ default:
+ \7055 = a;
+ endcase
+ endfunction
+ assign _0608_ = \7055 (1'h0, { 26'h0000000, _0073_, 1'h0 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ function [0:0] \7059 ;
+ input [0:0] a;
+ input [27:0] b;
+ input [27:0] s;
+ (* parallel_case *)
+ casez (s)
+ 28'b???????????????????????????1:
+ \7059 = b[0:0];
+ 28'b??????????????????????????1?:
+ \7059 = b[1:1];
+ 28'b?????????????????????????1??:
+ \7059 = b[2:2];
+ 28'b????????????????????????1???:
+ \7059 = b[3:3];
+ 28'b???????????????????????1????:
+ \7059 = b[4:4];
+ 28'b??????????????????????1?????:
+ \7059 = b[5:5];
+ 28'b?????????????????????1??????:
+ \7059 = b[6:6];
+ 28'b????????????????????1???????:
+ \7059 = b[7:7];
+ 28'b???????????????????1????????:
+ \7059 = b[8:8];
+ 28'b??????????????????1?????????:
+ \7059 = b[9:9];
+ 28'b?????????????????1??????????:
+ \7059 = b[10:10];
+ 28'b????????????????1???????????:
+ \7059 = b[11:11];
+ 28'b???????????????1????????????:
+ \7059 = b[12:12];
+ 28'b??????????????1?????????????:
+ \7059 = b[13:13];
+ 28'b?????????????1??????????????:
+ \7059 = b[14:14];
+ 28'b????????????1???????????????:
+ \7059 = b[15:15];
+ 28'b???????????1????????????????:
+ \7059 = b[16:16];
+ 28'b??????????1?????????????????:
+ \7059 = b[17:17];
+ 28'b?????????1??????????????????:
+ \7059 = b[18:18];
+ 28'b????????1???????????????????:
+ \7059 = b[19:19];
+ 28'b???????1????????????????????:
+ \7059 = b[20:20];
+ 28'b??????1?????????????????????:
+ \7059 = b[21:21];
+ 28'b?????1??????????????????????:
+ \7059 = b[22:22];
+ 28'b????1???????????????????????:
+ \7059 = b[23:23];
+ 28'b???1????????????????????????:
+ \7059 = b[24:24];
+ 28'b??1?????????????????????????:
+ \7059 = b[25:25];
+ 28'b?1??????????????????????????:
+ \7059 = b[26:26];
+ 28'b1???????????????????????????:
+ \7059 = b[27:27];
+ default:
+ \7059 = a;
+ endcase
+ endfunction
+ assign _0609_ = \7059 (1'h0, { 7'h00, _0537_, 3'h0, _0357_, 13'h0000, _0078_, _0074_, 1'h1 }, { _0564_, _0559_, _0554_, _0553_, _0552_, _0540_, _0539_, _0538_, _0526_, _0517_, _0441_, _0358_, _0348_, _0347_, _0240_, _0237_, _0228_, _0227_, _0210_, _0205_, _0184_, _0163_, _0160_, _0155_, _0080_, _0079_, _0075_, _0070_ });
+ assign _0610_ = e_in[324] & e_in[0];
+ assign _0611_ = e_in[323] ? 1'h1 : _0565_;
+ assign _0612_ = e_in[323] ? 1'h0 : _0590_;
+ assign _0613_ = e_in[323] ? { _0048_, 1'h1 } : { r[255:192], 1'h0 };
+ assign _0614_ = e_in[2:1] == 2'h2;
+ assign _0615_ = _0614_ ? 1'h1 : 1'h0;
+ assign _0616_ = r[256] | r[257];
+ assign _0617_ = r[256] & multiply_to_x[0];
+ assign _0618_ = r[257] & divider_to_x[0];
+ assign _0619_ = _0617_ | _0618_;
+ assign _0620_ = r[256] ? multiply_to_x[64:1] : divider_to_x[64:1];
+ assign _0621_ = r[256] ? multiply_to_x[65] : divider_to_x[65];
+ assign _0622_ = r[270] | _0621_;
+ assign _0623_ = r[265] ? { _0622_, _0621_, _0621_ } : r[270:268];
+ assign _0624_ = _0619_ ? 1'h0 : 1'h1;
+ assign _0625_ = _0632_ ? { r[264], 1'h1 } : 2'h0;
+ assign _0626_ = _0633_ ? { 1'h0, r[263:259] } : 6'h00;
+ assign _0627_ = _0619_ ? { _0623_, r[267:265] } : { _0013_, 1'h0 };
+ assign _0628_ = _0619_ ? 2'h0 : r[257:256];
+ assign _0629_ = _0619_ ? _0620_ : 64'h0000000000000000;
+ assign _0630_ = _0619_ ? 1'h1 : 1'h0;
+ assign _0631_ = _0616_ ? _0624_ : 1'h0;
+ assign _0632_ = _0616_ & _0619_;
+ assign _0633_ = _0616_ & _0619_;
+ assign _0634_ = _0616_ ? _0627_ : { _0013_, 1'h0 };
+ assign _0635_ = _0616_ ? _0628_ : 2'h0;
+ assign _0636_ = _0616_ ? _0629_ : 64'h0000000000000000;
+ assign _0637_ = _0616_ ? _0630_ : 1'h0;
+ assign _0638_ = r[258] ? 1'h0 : _0631_;
+ assign _0639_ = r[258] ? { r[264], 1'h1 } : _0625_;
+ assign _0640_ = r[258] ? { 1'h0, r[263:259] } : _0626_;
+ assign _0641_ = r[258] ? 1'h0 : _0634_[0];
+ assign _0642_ = r[258] ? r[270:266] : _0634_[5:1];
+ assign _0643_ = r[258] ? 2'h0 : _0635_;
+ assign _0644_ = r[258] ? countzero_result : _0636_;
+ assign _0645_ = r[258] ? 1'h1 : _0637_;
+ assign _0646_ = r[191] ? 1'h0 : _0638_;
+ assign _0647_ = r[191] ? 1'h1 : _0639_[0];
+ assign _0648_ = r[191] ? 1'h0 : _0639_[1];
+ assign _0649_ = r[191] ? 6'h20 : _0640_;
+ assign _0650_ = r[191] ? { _0013_, 1'h0 } : { _0642_, _0641_ };
+ assign _0651_ = r[191] ? 2'h0 : _0643_;
+ assign _0652_ = r[191] ? r[255:192] : _0644_;
+ assign _0653_ = r[191] ? 1'h1 : _0645_;
+ assign _0654_ = e_in[0] ? 1'h0 : _0646_;
+ assign _0655_ = e_in[0] ? 1'h0 : _0647_;
+ assign _0656_ = e_in[0] ? 1'h0 : _0648_;
+ assign _0657_ = e_in[0] ? 6'h00 : _0649_;
+ assign _0658_ = e_in[0] ? { _0013_, 1'h0 } : _0650_;
+ assign _0659_ = e_in[0] ? 2'h0 : _0651_;
+ assign _0660_ = e_in[0] ? e_in[72:9] : r[334:271];
+ assign _0661_ = e_in[0] ? 64'h0000000000000000 : _0652_;
+ assign _0662_ = e_in[0] ? 1'h0 : _0653_;
+ assign _0663_ = e_in[0] ? _0615_ : 1'h0;
+ assign _0664_ = _0069_ ? _0611_ : _0654_;
+ assign _0665_ = _0069_ ? { _0569_, _0568_, _0567_, _0566_ } : { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 };
+ assign _0666_ = _0069_ ? _0570_ : 1'h0;
+ assign _0667_ = _0069_ ? _0571_ : 1'h0;
+ assign _0668_ = _0069_ ? { _0586_, _0585_, _0584_, _0583_, _0582_, _0581_, _0580_, _0579_, _0578_, _0577_, _0576_, _0575_, _0574_, _0573_, _0572_ } : { ctrl[191:128], _0040_ };
+ assign _0669_ = _0069_ ? _0587_ : { ctrl[320:257], _0045_ };
+ assign _0670_ = _0069_ ? _0588_ : 1'h0;
+ assign _0671_ = _0069_ ? _0589_ : 1'h0;
+ assign _0672_ = _0069_ ? { _0610_, _0612_ } : { _0656_, _0655_ };
+ assign _0673_ = _0069_ ? _0591_[1] : 1'h0;
+ assign _0674_ = _0069_ ? _0592_ : _0657_;
+ assign _0675_ = _0069_ ? { _0596_, _0595_, _0594_, _0593_ } : 105'h000000000000000000000000000;
+ assign _0676_ = _0069_ ? _0597_ : _0658_;
+ assign _0677_ = _0069_ ? { _0613_, _0598_ } : { r[255:192], 1'h0, e_in[72:9], 7'h44 };
+ assign _0678_ = _0069_ ? { _0600_, _0599_ } : _0659_;
+ assign _0679_ = _0069_ ? { _0013_, e_in[325:324], e_in[77:73], _0601_ } : { r[270:259], 1'h0 };
+ assign _0680_ = _0069_ ? r[334:271] : _0660_;
+ assign _0681_ = _0069_ ? { _0605_, _0604_, _0603_, _0602_ } : _0661_;
+ assign _0682_ = _0069_ ? _0606_ : _0662_;
+ assign _0683_ = _0069_ ? 1'h0 : _0663_;
+ assign _0684_ = _0069_ ? _0607_ : 1'h0;
+ assign _0685_ = _0069_ ? _0608_ : 1'h0;
+ assign _0686_ = _0069_ ? _0609_ : 1'h0;
+ assign _0687_ = _0067_ ? 1'h0 : _0664_;
+ assign _0688_ = _0067_ ? { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 } : _0665_;
+ assign _0689_ = _0067_ ? 1'h0 : _0666_;
+ assign _0690_ = _0067_ ? 1'h0 : _0667_;
+ assign _0691_ = _0067_ ? { ctrl[191:128], _0040_ } : _0668_;
+ assign _0692_ = _0067_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h04, ctrl[143:128], 64'h0000000000000700 } : _0669_;
+ assign _0693_ = _0067_ ? 1'h0 : _0670_;
+ assign _0694_ = _0067_ ? 1'h0 : _0671_;
+ assign _0695_ = _0067_ ? { r[334:259], 3'h0, r[255:192], 1'h0, e_in[72:9], 7'h44, _0013_, 115'h00000000000000000000000000000 } : { _0680_, _0679_, _0678_, _0677_, _0676_, _0675_, _0674_, _0673_, _0672_ };
+ assign _0696_ = _0067_ ? 64'h0000000000000000 : _0681_;
+ assign _0697_ = _0067_ ? 1'h0 : _0682_;
+ assign _0698_ = _0067_ ? 1'h0 : _0683_;
+ assign _0699_ = _0067_ ? 1'h1 : _0684_;
+ assign _0700_ = _0067_ ? 1'h0 : _0685_;
+ assign _0701_ = _0067_ ? 1'h0 : _0686_;
+ assign _0702_ = _0058_ ? 1'h0 : _0687_;
+ assign _0703_ = _0058_ ? { 64'h0000000000000000, _0047_, ctrl[133], 1'h0 } : _0688_;
+ assign _0704_ = _0058_ ? 1'h0 : _0689_;
+ assign _0705_ = _0058_ ? 1'h0 : _0690_;
+ assign _0706_ = _0058_ ? { ctrl[191:128], _0040_ } : _0691_;
+ assign _0707_ = _0058_ ? _0045_ : _0692_[63:0];
+ assign _0708_ = _0058_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h00, ctrl[143:128] } : _0692_[127:64];
+ assign _0709_ = _0058_ ? 1'h0 : _0693_;
+ assign _0710_ = _0058_ ? 1'h0 : _0694_;
+ assign _0711_ = _0058_ ? { r[334:259], 3'h0, r[255:192], 1'h0, e_in[72:9], 7'h44, _0013_, 115'h00000000000000000000000000000 } : _0695_;
+ assign _0712_ = _0058_ ? 64'h0000000000000000 : _0696_;
+ assign _0713_ = _0058_ ? 1'h0 : _0697_;
+ assign _0714_ = _0058_ ? 1'h0 : _0698_;
+ assign _0715_ = _0058_ ? 1'h1 : _0699_;
+ assign _0716_ = _0058_ ? 1'h0 : _0700_;
+ assign _0717_ = _0058_ ? 1'h0 : _0701_;
+ assign _0718_ = _0057_ ? 1'h0 : _0702_;
+ assign _0719_ = _0057_ ? { ctrl[256:193], 3'h5 } : _0703_;
+ assign _0720_ = _0057_ ? 1'h0 : _0704_;
+ assign _0721_ = _0057_ ? 1'h0 : _0705_;
+ assign _0722_ = _0057_ ? _0040_ : _0706_[63:0];
+ assign _0723_ = _0057_ ? 2'h1 : _0706_[65:64];
+ assign _0724_ = _0057_ ? ctrl[131:130] : _0706_[67:66];
+ assign _0725_ = _0057_ ? 2'h0 : _0706_[69:68];
+ assign _0726_ = _0057_ ? ctrl[141:134] : _0706_[77:70];
+ assign _0727_ = _0057_ ? 2'h0 : _0706_[79:78];
+ assign _0728_ = _0057_ ? ctrl[190:144] : _0706_[126:80];
+ assign _0729_ = _0057_ ? 1'h1 : _0706_[127];
+ assign _0730_ = _0057_ ? { ctrl[320:257], _0045_ } : { _0708_, _0707_ };
+ assign _0731_ = _0057_ ? 1'h0 : _0709_;
+ assign _0732_ = _0057_ ? 1'h0 : _0710_;
+ assign _0733_ = _0057_ ? e_in[0] : _0711_[0];
+ assign _0734_ = _0057_ ? { _0013_, 114'h00000000000000000000000000000 } : _0711_[119:1];
+ assign _0735_ = _0057_ ? { ctrl[320:257], 7'h47 } : _0711_[190:120];
+ assign _0736_ = _0057_ ? { r[334:259], 3'h0, r[255:192], 1'h0 } : _0711_[334:191];
+ assign _0737_ = _0057_ ? 64'h0000000000000000 : _0712_;
+ assign _0738_ = _0057_ ? 1'h0 : _0713_;
+ assign _0739_ = _0057_ ? 1'h0 : _0714_;
+ assign _0740_ = _0057_ ? 1'h0 : _0715_;
+ assign _0741_ = _0057_ ? 1'h0 : _0716_;
+ assign _0742_ = _0057_ ? 1'h0 : _0717_;
+ assign _0743_ = _0742_ ? { ctrl[191:159], 4'h0, ctrl[154:150], 6'h08, ctrl[143:128], 64'h0000000000000700 } : _0730_;
+ assign _0744_ = _0742_ ? 1'h1 : _0740_;
+ assign _0745_ = _0749_ ? _0048_ : _0735_[70:7];
+ assign _0746_ = _0744_ ? 1'h1 : 1'h0;
+ assign _0747_ = _0744_ ? 1'h1 : _0733_;
+ assign _0748_ = _0744_ ? 1'h1 : _0735_[0];
+ assign _0749_ = _0744_ & _0741_;
+ assign _0750_ = ~ l_in[6];
+ assign _0751_ = ~ l_in[5];
+ assign _0752_ = _0751_ ? 64'h0000000000000300 : 64'h0000000000000380;
+ assign _0753_ = ~ l_in[5];
+ assign _0754_ = _0753_ ? 64'h0000000000000400 : 64'h0000000000000480;
+ assign _0755_ = _0753_ ? l_in[4:3] : 2'h0;
+ assign _0756_ = _0753_ ? l_in[2] : 1'h0;
+ assign _0757_ = _0753_ ? l_in[1] : 1'h0;
+ assign _0758_ = _0750_ ? _0752_ : _0754_;
+ assign _0759_ = _0750_ ? 2'h0 : _0755_;
+ assign _0760_ = _0750_ ? 1'h0 : _0756_;
+ assign _0761_ = _0750_ ? 1'h0 : _0757_;
+ assign _0762_ = l_in[0] ? { ctrl[191:159], _0761_, 1'h0, _0760_, 1'h0, ctrl[154:150], 2'h0, _0759_, 2'h0, ctrl[143:128], _0758_, 1'h1 } : { _0743_, _0746_ };
+ assign _0763_ = l_in[0] ? 1'h1 : _0747_;
+ assign _0764_ = l_in[0] ? { r[334:271], 7'h45 } : { _0745_, _0735_[6:1], _0748_ };
+ assign _0765_ = e_in[366:361] == 6'h1f;
+ assign _0766_ = e_in[345:344] == 2'h3;
+ assign _0767_ = _0765_ & _0766_;
+ assign _0768_ = e_in[340:336] == 5'h15;
+ assign _0769_ = _0767_ & _0768_;
+ assign _0770_ = _0769_ ? 1'h1 : 1'h0;
+ assign _0771_ = ~ ctrl[142];
+ reg [0:0] \7795 [61:0];
+ initial begin
+ \7795 [0] = 1'h0;
+ \7795 [1] = 1'h0;
+ \7795 [2] = 1'h0;
+ \7795 [3] = 1'h1;
+ \7795 [4] = 1'h0;
+ \7795 [5] = 1'h0;
+ \7795 [6] = 1'h0;
+ \7795 [7] = 1'h0;
+ \7795 [8] = 1'h0;
+ \7795 [9] = 1'h0;
+ \7795 [10] = 1'h0;
+ \7795 [11] = 1'h0;
+ \7795 [12] = 1'h1;
+ \7795 [13] = 1'h0;
+ \7795 [14] = 1'h0;
+ \7795 [15] = 1'h0;
+ \7795 [16] = 1'h0;
+ \7795 [17] = 1'h0;
+ \7795 [18] = 1'h0;
+ \7795 [19] = 1'h0;
+ \7795 [20] = 1'h1;
+ \7795 [21] = 1'h0;
+ \7795 [22] = 1'h0;
+ \7795 [23] = 1'h0;
+ \7795 [24] = 1'h1;
+ \7795 [25] = 1'h0;
+ \7795 [26] = 1'h0;
+ \7795 [27] = 1'h0;
+ \7795 [28] = 1'h0;
+ \7795 [29] = 1'h0;
+ \7795 [30] = 1'h0;
+ \7795 [31] = 1'h0;
+ \7795 [32] = 1'h0;
+ \7795 [33] = 1'h0;
+ \7795 [34] = 1'h0;
+ \7795 [35] = 1'h0;
+ \7795 [36] = 1'h0;
+ \7795 [37] = 1'h0;
+ \7795 [38] = 1'h0;
+ \7795 [39] = 1'h0;
+ \7795 [40] = 1'h0;
+ \7795 [41] = 1'h0;
+ \7795 [42] = 1'h0;
+ \7795 [43] = 1'h0;
+ \7795 [44] = 1'h0;
+ \7795 [45] = 1'h0;
+ \7795 [46] = 1'h0;
+ \7795 [47] = 1'h0;
+ \7795 [48] = 1'h0;
+ \7795 [49] = 1'h0;
+ \7795 [50] = 1'h0;
+ \7795 [51] = 1'h0;
+ \7795 [52] = 1'h0;
+ \7795 [53] = 1'h0;
+ \7795 [54] = 1'h0;
+ \7795 [55] = 1'h0;
+ \7795 [56] = 1'h0;
+ \7795 [57] = 1'h1;
+ \7795 [58] = 1'h0;
+ \7795 [59] = 1'h0;
+ \7795 [60] = 1'h0;
+ \7795 [61] = 1'h0;
+ end
+ assign _0773_ = \7795 [_0060_];
+ assign _0784_ = _0169_[4] ? _0783_ : _0782_;
+ assign _0795_ = _0192_[4] ? _0794_ : _0793_;
+ assign _0806_ = _0238_[4] ? _0805_ : _0804_;
+ assign _0817_ = _0268_[4] ? _0816_ : _0815_;
+ assign _0828_ = _0269_[4] ? _0827_ : _0826_;
+ assign _0831_ = _0270_[0] ? e_in[345] : e_in[344];
+ assign _0832_ = _0270_[2] ? _0830_ : _0829_;
+ assign _0833_ = _0270_[3] ? _0831_ : _0832_;
+ zero_counter countzero_0 (
+ .clk(clk),
+ .count_right(e_in[345]),
+ .is_32bit(e_in[333]),
+ .result(countzero_result),
+ .rs(c_in)
+ );
+ divider divider_0 (
+ .clk(clk),
+ .d_in({ _0031_, _0028_, _0038_, e_in[333], e_in[334], _0037_, _0732_ }),
+ .d_out(divider_to_x),
+ .rst(rst)
+ );
+ logical logical_0 (
+ .datalen(e_in[370:367]),
+ .invert_in(e_in[326]),
+ .invert_out(e_in[327]),
+ .op(e_in[8:3]),
+ .parity(parity_result),
+ .popcnt(popcnt_result),
+ .rb(b_in),
+ .result(logical_result),
+ .rs(c_in)
+ );
+ multiply_16 multiply_0 (
+ .clk(clk),
+ .m_in({ e_in[333], _0016_, e_in[8:3], _0731_ }),
+ .m_out(multiply_to_x)
+ );
+ rotator rotator_0 (
+ .arith(e_in[334]),
+ .carry_out(rotator_carry),
+ .clear_left(rot_clear_left),
+ .clear_right(rot_clear_right),
+ .insn(e_in[366:335]),
+ .is_32bit(e_in[333]),
+ .ra(a_in),
+ .result(rotator_result),
+ .right_shift(right_shift),
+ .rs(c_in),
+ .shift(b_in[6:0]),
+ .sign_ext_rs(rot_sign_ext)
+ );
+ assign flush_out = _0719_[0];
+ assign stall_out = _0718_;
+ assign l_out = { _0771_, ctrl[132], e_in[324], e_in[374], _0734_[118:114], e_in[83:79], e_in[373:371], _0770_, e_in[370:367], e_in[77:73], c_in, b_in, a_in, e_in[366:335], e_in[72:3], _0739_ };
+ assign f_out = _0719_;
+ assign e_out = r[190:0];
+ assign dbg_msr_out = ctrl[191:128];
+ assign icache_inval = _0720_;
+ assign terminate_out = _0721_;
+endmodule
+
+module fetch1_3f28fda38b1ec2f6fdb16c0bce5a53c28d1424e5(clk, rst, stall_in, flush_in, stop_in, alt_reset_in, e_in, i_out);
+ wire [63:0] _00_;
+ wire _01_;
+ wire [1:0] _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [1:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire [1:0] _09_;
+ wire _10_;
+ wire [1:0] _11_;
+ wire _12_;
+ wire [63:0] _13_;
+ wire [63:0] _14_;
+ wire _15_;
+ wire [1:0] _16_;
+ wire [1:0] _17_;
+ wire [63:0] _18_;
+ wire [1:0] _19_;
+ wire [1:0] _20_;
+ wire [63:0] _21_;
+ wire _22_;
+ input alt_reset_in;
+ input clk;
+ input [66:0] e_in;
+ input flush_in;
+ output [67:0] i_out;
+ reg [67:0] r;
+ reg [1:0] r_int;
+ wire [1:0] r_next_int;
+ input rst;
+ input stall_in;
+ input stop_in;
+ always @(posedge clk)
+ r <= { _21_, stop_in, _20_, _22_ };
+ always @(posedge clk)
+ r_int <= r_next_int;
+ assign _00_ = alt_reset_in ? 64'h0000000000000000 : 64'h0000000000000000;
+ assign _01_ = ~ stall_in;
+ assign _02_ = stop_in ? 2'h1 : r_int;
+ assign _03_ = stop_in ? 1'h0 : 1'h1;
+ assign _04_ = r_int == 2'h0;
+ assign _05_ = ~ stop_in;
+ assign _06_ = _05_ ? 2'h2 : r_int;
+ assign _07_ = r_int == 2'h1;
+ assign _08_ = ~ stop_in;
+ assign _09_ = _08_ ? 2'h0 : 2'h1;
+ assign _10_ = r_int == 2'h2;
+ function [1:0] \183 ;
+ input [1:0] a;
+ input [5:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \183 = b[1:0];
+ 3'b?1?:
+ \183 = b[3:2];
+ 3'b1??:
+ \183 = b[5:4];
+ default:
+ \183 = a;
+ endcase
+ endfunction
+ assign _11_ = \183 (2'hx, { _09_, _06_, _02_ }, { _10_, _07_, _04_ });
+ function [0:0] \187 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \187 = b[0:0];
+ 3'b?1?:
+ \187 = b[1:1];
+ 3'b1??:
+ \187 = b[2:2];
+ default:
+ \187 = a;
+ endcase
+ endfunction
+ assign _12_ = \187 (1'hx, { 2'h2, _03_ }, { _10_, _07_, _04_ });
+ assign _13_ = r[67:4] + 64'h0000000000000004;
+ assign _14_ = _15_ ? _13_ : r[67:4];
+ assign _15_ = _01_ & _12_;
+ assign _16_ = _01_ ? _11_ : r_int;
+ assign _17_ = e_in[0] ? e_in[2:1] : r[2:1];
+ assign _18_ = e_in[0] ? e_in[66:3] : _14_;
+ assign _19_ = e_in[0] ? r_int : _16_;
+ assign _20_ = rst ? 2'h2 : _17_;
+ assign _21_ = rst ? _00_ : _18_;
+ assign r_next_int = rst ? 2'h0 : _19_;
+ assign _22_ = ~ rst;
+ assign i_out = r;
+endmodule
+
+module fetch2(clk, rst, stall_in, flush_in, i_in, f_out);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire [98:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire [99:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire [98:0] _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ input clk;
+ output [98:0] f_out;
+ input flush_in;
+ input [98:0] i_in;
+ reg [98:0] r;
+ reg [100:0] r_int;
+ input rst;
+ input stall_in;
+ assign _00_ = rst | flush_in;
+ assign _01_ = ~ stall_in;
+ assign _02_ = _00_ | _01_;
+ always @(posedge clk)
+ r_int <= { r_int[100], _17_, _06_[98:3], _12_, _06_[1], _11_ };
+ assign _03_ = _02_ ? { _10_[98:3], _15_, _10_[1], _16_ } : r;
+ always @(posedge clk)
+ r <= _03_;
+ assign _04_ = ~ r_int[99];
+ assign _05_ = stall_in & _04_;
+ assign _06_ = _05_ ? { 1'h1, i_in } : r_int[99:0];
+ assign _07_ = ~ stall_in;
+ assign _08_ = _06_[99] & _07_;
+ assign _09_ = _08_ ? 1'h0 : _06_[99];
+ assign _10_ = _08_ ? _06_[98:0] : i_in;
+ assign _11_ = flush_in ? 1'h0 : _06_[0];
+ assign _12_ = flush_in ? 1'h0 : _06_[2];
+ assign _13_ = flush_in | _10_[1];
+ assign _14_ = _13_ ? 1'h0 : _10_[0];
+ assign _15_ = _13_ ? 1'h0 : _10_[2];
+ assign _16_ = rst ? 1'h0 : _14_;
+ assign _17_ = rst ? 1'h0 : _09_;
+ assign f_out = r;
+endmodule
+
+module gpr_hazard_1(clk, stall_in, gpr_write_valid_in, gpr_write_in, bypass_avail, gpr_read_valid_in, gpr_read_in, stall_out, use_bypass);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ input bypass_avail;
+ input clk;
+ input [5:0] gpr_read_in;
+ input gpr_read_valid_in;
+ input [5:0] gpr_write_in;
+ input gpr_write_valid_in;
+ reg [7:0] r = 8'h00;
+ wire [7:0] rin;
+ input stall_in;
+ output stall_out;
+ output use_bypass;
+ always @(posedge clk)
+ r <= rin;
+ assign _00_ = r[7:2] == gpr_read_in;
+ assign _01_ = r[0] & _00_;
+ assign _02_ = ~ stall_in;
+ assign _03_ = r[1] & _02_;
+ assign _04_ = _03_ ? 1'h0 : 1'h1;
+ assign _05_ = _03_ ? 1'h1 : 1'h0;
+ assign _06_ = _01_ ? _04_ : 1'h0;
+ assign _07_ = _01_ ? _05_ : 1'h0;
+ assign _08_ = gpr_read_valid_in ? _06_ : 1'h0;
+ assign _09_ = gpr_read_valid_in ? _07_ : 1'h0;
+ assign _10_ = ~ stall_in;
+ assign rin = _10_ ? { gpr_write_in, bypass_avail, gpr_write_valid_in } : r;
+ assign stall_out = _08_;
+ assign use_bypass = _09_;
+endmodule
+
+module icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst, i_in, m_in, flush_in, inval_in, wishbone_in, i_out, stall_out, wishbone_out);
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire _0007_;
+ wire _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire [89:0] _0019_;
+ wire _0020_;
+ wire [89:0] _0021_;
+ wire [89:0] _0022_;
+ wire [89:0] _0023_;
+ wire [89:0] _0024_;
+ wire [89:0] _0025_;
+ wire [89:0] _0026_;
+ wire [89:0] _0027_;
+ wire [89:0] _0028_;
+ wire [89:0] _0029_;
+ wire [89:0] _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire [89:0] _0099_;
+ wire [89:0] _0100_;
+ wire [89:0] _0101_;
+ wire [89:0] _0102_;
+ wire [89:0] _0103_;
+ wire _0104_;
+ wire [89:0] _0105_;
+ wire [89:0] _0106_;
+ wire [89:0] _0107_;
+ wire [89:0] _0108_;
+ wire [89:0] _0109_;
+ wire [89:0] _0110_;
+ wire [89:0] _0111_;
+ wire [89:0] _0112_;
+ wire [89:0] _0113_;
+ wire [89:0] _0114_;
+ wire _0115_;
+ wire [89:0] _0116_;
+ wire [89:0] _0117_;
+ wire [89:0] _0118_;
+ wire [89:0] _0119_;
+ wire [89:0] _0120_;
+ wire [89:0] _0121_;
+ wire [89:0] _0122_;
+ wire [89:0] _0123_;
+ wire [89:0] _0124_;
+ wire [89:0] _0125_;
+ wire [89:0] _0126_;
+ wire [89:0] _0127_;
+ wire [89:0] _0128_;
+ wire [89:0] _0129_;
+ wire [89:0] _0130_;
+ wire [89:0] _0131_;
+ wire [89:0] _0132_;
+ wire [89:0] _0133_;
+ wire [89:0] _0134_;
+ wire [89:0] _0135_;
+ wire [89:0] _0136_;
+ wire [89:0] _0137_;
+ wire [89:0] _0138_;
+ wire [89:0] _0139_;
+ wire [89:0] _0140_;
+ wire [89:0] _0141_;
+ wire [89:0] _0142_;
+ wire [89:0] _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire [89:0] _0213_;
+ wire [89:0] _0214_;
+ wire [89:0] _0215_;
+ wire [89:0] _0216_;
+ wire [89:0] _0217_;
+ wire [89:0] _0218_;
+ wire [89:0] _0219_;
+ wire [89:0] _0220_;
+ wire [89:0] _0221_;
+ wire [89:0] _0222_;
+ wire [89:0] _0223_;
+ wire [89:0] _0224_;
+ wire [89:0] _0225_;
+ wire [89:0] _0226_;
+ wire [89:0] _0227_;
+ wire [89:0] _0228_;
+ wire [89:0] _0229_;
+ wire _0230_;
+ wire [89:0] _0231_;
+ wire [89:0] _0232_;
+ wire [89:0] _0233_;
+ wire [89:0] _0234_;
+ wire [89:0] _0235_;
+ wire [89:0] _0236_;
+ wire [89:0] _0237_;
+ wire [89:0] _0238_;
+ wire [89:0] _0239_;
+ wire [89:0] _0240_;
+ wire _0241_;
+ wire [89:0] _0242_;
+ wire [89:0] _0243_;
+ wire [89:0] _0244_;
+ wire [89:0] _0245_;
+ wire [89:0] _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire [5:0] _0493_;
+ wire _0494_;
+ wire [5:0] _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire [5:0] _0499_;
+ wire [5:0] _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire [5:0] _0503_;
+ wire [5:0] _0504_;
+ wire [63:0] _0505_;
+ wire [63:0] _0506_;
+ wire [63:0] _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire [4:0] _0516_;
+ wire _0517_;
+ wire [4:0] _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire [4:0] _0522_;
+ wire _0523_;
+ wire [4:0] _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire [4:0] _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ reg [66:0] _0541_;
+ wire [63:0] _0542_;
+ wire _0543_;
+ wire [4:0] _0544_;
+ wire _0545_;
+ wire [4:0] _0546_;
+ wire [4:0] _0547_;
+ wire [2879:0] _0548_;
+ wire _0549_;
+ wire [4:0] _0550_;
+ wire [4:0] _0551_;
+ wire [2879:0] _0552_;
+ wire [2879:0] _0553_;
+ wire [63:0] _0554_;
+ wire [32:0] _0555_;
+ wire [1:0] _0556_;
+ wire [14:0] _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire [2:0] _0566_;
+ wire [31:0] _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire [4:0] _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire [63:0] _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire [2:0] _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire [7:0] _0582_;
+ wire _0583_;
+ wire [2879:0] _0584_;
+ wire [63:0] _0585_;
+ wire _0586_;
+ wire [31:0] _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire [5:0] _0590_;
+ wire [7:0] _0591_;
+ wire _0592_;
+ wire [2879:0] _0593_;
+ wire [63:0] _0594_;
+ wire [32:0] _0595_;
+ wire [63:0] _0596_;
+ wire [1:0] _0597_;
+ wire [8:0] _0598_;
+ wire [14:0] _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ reg [123:0] _0606_;
+ wire [4095:0] _0607_;
+ wire [63:0] _0608_;
+ wire [2943:0] _0609_;
+ wire [45:0] _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0960_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0998_;
+ wire _0999_;
+ wire _1000_;
+ wire _1001_;
+ wire _1002_;
+ wire _1003_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
+ wire _1025_;
+ wire _1026_;
+ wire _1027_;
+ wire _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire [89:0] _1031_;
+ wire [89:0] _1032_;
+ wire [89:0] _1033_;
+ wire [89:0] _1034_;
+ wire [89:0] _1035_;
+ wire [89:0] _1036_;
+ wire [89:0] _1037_;
+ wire [89:0] _1038_;
+ wire [89:0] _1039_;
+ wire [89:0] _1040_;
+ wire [89:0] _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
+ wire _1046_;
+ wire _1047_;
+ wire _1048_;
+ wire _1049_;
+ wire _1050_;
+ wire _1051_;
+ wire _1052_;
+ wire [89:0] _1053_;
+ wire [89:0] _1054_;
+ wire [89:0] _1055_;
+ wire [89:0] _1056_;
+ wire [89:0] _1057_;
+ wire [89:0] _1058_;
+ wire [89:0] _1059_;
+ wire [89:0] _1060_;
+ wire [89:0] _1061_;
+ wire [89:0] _1062_;
+ wire [89:0] _1063_;
+ wire _1064_;
+ wire _1065_;
+ wire _1066_;
+ wire _1067_;
+ wire _1068_;
+ wire _1069_;
+ wire _1070_;
+ wire _1071_;
+ wire _1072_;
+ wire _1073_;
+ wire [63:0] _1074_;
+ wire [31:0] _1075_;
+ wire _1076_;
+ wire _1077_;
+ wire _1078_;
+ wire _1079_;
+ wire _1080_;
+ wire _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1089_;
+ wire _1090_;
+ wire _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1097_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire _1128_;
+ wire _1129_;
+ wire _1130_;
+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire _1151_;
+ wire _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1159_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1164_;
+ wire _1165_;
+ wire _1166_;
+ wire _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1188_;
+ wire _1189_;
+ wire _1190_;
+ wire _1191_;
+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
+ wire _1199_;
+ wire _1200_;
+ wire _1201_;
+ wire _1202_;
+ wire _1203_;
+ wire _1204_;
+ wire _1205_;
+ wire _1206_;
+ wire _1207_;
+ wire _1208_;
+ wire _1209_;
+ wire _1210_;
+ wire _1211_;
+ wire _1212_;
+ wire _1213_;
+ wire _1214_;
+ wire _1215_;
+ wire _1216_;
+ wire _1217_;
+ wire _1218_;
+ wire _1219_;
+ wire _1220_;
+ wire _1221_;
+ wire _1222_;
+ wire _1223_;
+ wire _1224_;
+ wire _1225_;
+ wire _1226_;
+ wire _1227_;
+ wire _1228_;
+ wire _1229_;
+ wire _1230_;
+ wire _1231_;
+ wire _1232_;
+ wire _1233_;
+ wire _1234_;
+ wire _1235_;
+ wire _1236_;
+ wire _1237_;
+ wire _1238_;
+ wire _1239_;
+ wire _1240_;
+ wire _1241_;
+ wire _1242_;
+ wire _1243_;
+ wire _1244_;
+ wire _1245_;
+ wire _1246_;
+ wire _1247_;
+ wire _1248_;
+ wire _1249_;
+ wire _1250_;
+ wire _1251_;
+ wire _1252_;
+ wire _1253_;
+ wire _1254_;
+ wire _1255_;
+ wire _1256_;
+ wire _1257_;
+ wire _1258_;
+ wire _1259_;
+ wire _1260_;
+ wire _1261_;
+ wire _1262_;
+ wire _1263_;
+ wire _1264_;
+ wire _1265_;
+ wire _1266_;
+ wire _1267_;
+ wire _1268_;
+ wire _1269_;
+ wire _1270_;
+ wire _1271_;
+ wire _1272_;
+ wire _1273_;
+ wire _1274_;
+ wire _1275_;
+ wire _1276_;
+ wire _1277_;
+ wire _1278_;
+ wire _1279_;
+ wire _1280_;
+ wire _1281_;
+ wire _1282_;
+ wire _1283_;
+ wire _1284_;
+ wire _1285_;
+ wire [89:0] _1286_;
+ wire [89:0] _1287_;
+ wire [89:0] _1288_;
+ wire [89:0] _1289_;
+ wire [89:0] _1290_;
+ wire [89:0] _1291_;
+ wire [89:0] _1292_;
+ wire [89:0] _1293_;
+ wire [89:0] _1294_;
+ wire [89:0] _1295_;
+ wire _1296_;
+ wire _1297_;
+ wire _1298_;
+ wire _1299_;
+ wire _1300_;
+ wire _1301_;
+ wire _1302_;
+ wire _1303_;
+ wire _1304_;
+ wire _1305_;
+ wire [89:0] _1306_;
+ wire [89:0] _1307_;
+ wire [89:0] _1308_;
+ wire [89:0] _1309_;
+ wire [89:0] _1310_;
+ wire [89:0] _1311_;
+ wire [89:0] _1312_;
+ wire [89:0] _1313_;
+ wire [89:0] _1314_;
+ wire [89:0] _1315_;
+ wire _1316_;
+ wire _1317_;
+ wire _1318_;
+ wire _1319_;
+ wire _1320_;
+ wire _1321_;
+ wire _1322_;
+ wire _1323_;
+ wire _1324_;
+ wire _1325_;
+ wire [89:0] _1326_;
+ wire [89:0] _1327_;
+ wire [89:0] _1328_;
+ wire [89:0] _1329_;
+ wire [89:0] _1330_;
+ wire [89:0] _1331_;
+ wire [89:0] _1332_;
+ wire [89:0] _1333_;
+ wire [89:0] _1334_;
+ wire [89:0] _1335_;
+ wire [89:0] _1336_;
+ wire [89:0] _1337_;
+ wire [89:0] _1338_;
+ wire [89:0] _1339_;
+ wire [89:0] _1340_;
+ wire [89:0] _1341_;
+ wire [89:0] _1342_;
+ wire [89:0] _1343_;
+ wire [89:0] _1344_;
+ wire [89:0] _1345_;
+ wire _1346_;
+ wire _1347_;
+ wire _1348_;
+ wire _1349_;
+ wire _1350_;
+ wire _1351_;
+ wire _1352_;
+ wire _1353_;
+ wire _1354_;
+ wire _1355_;
+ wire _1356_;
+ wire _1357_;
+ wire _1358_;
+ wire _1359_;
+ wire _1360_;
+ wire _1361_;
+ wire _1362_;
+ wire _1363_;
+ wire _1364_;
+ wire _1365_;
+ wire _1366_;
+ wire _1367_;
+ wire _1368_;
+ wire _1369_;
+ wire _1370_;
+ wire _1371_;
+ wire _1372_;
+ wire _1373_;
+ wire _1374_;
+ wire _1375_;
+ wire _1376_;
+ wire [89:0] _1377_;
+ wire [89:0] _1378_;
+ wire [89:0] _1379_;
+ wire [89:0] _1380_;
+ wire [89:0] _1381_;
+ wire [89:0] _1382_;
+ wire [89:0] _1383_;
+ wire [89:0] _1384_;
+ wire [89:0] _1385_;
+ wire [89:0] _1386_;
+ wire _1387_;
+ wire _1388_;
+ wire _1389_;
+ wire _1390_;
+ wire _1391_;
+ wire _1392_;
+ wire _1393_;
+ wire _1394_;
+ wire _1395_;
+ wire _1396_;
+ wire [89:0] _1397_;
+ wire [89:0] _1398_;
+ wire [89:0] _1399_;
+ wire [89:0] _1400_;
+ wire [89:0] _1401_;
+ wire [89:0] _1402_;
+ wire [89:0] _1403_;
+ wire [89:0] _1404_;
+ wire [89:0] _1405_;
+ wire [89:0] _1406_;
+ wire _1407_;
+ wire _1408_;
+ wire _1409_;
+ wire _1410_;
+ wire _1411_;
+ wire _1412_;
+ wire _1413_;
+ wire _1414_;
+ wire _1415_;
+ wire _1416_;
+ wire [89:0] _1417_;
+ wire [89:0] _1418_;
+ wire [89:0] _1419_;
+ wire [89:0] _1420_;
+ wire [89:0] _1421_;
+ wire [89:0] _1422_;
+ wire [89:0] _1423_;
+ wire [89:0] _1424_;
+ wire [89:0] _1425_;
+ wire [89:0] _1426_;
+ wire [89:0] _1427_;
+ wire [89:0] _1428_;
+ wire [89:0] _1429_;
+ wire [89:0] _1430_;
+ wire [89:0] _1431_;
+ wire [89:0] _1432_;
+ wire [89:0] _1433_;
+ wire [89:0] _1434_;
+ wire [89:0] _1435_;
+ wire [89:0] _1436_;
+ wire access_ok;
+ reg [2879:0] cache_tags;
+ reg [63:0] cache_valids;
+ input clk;
+ wire eaa_priv;
+ input flush_in;
+ input [67:0] i_in;
+ output [98:0] i_out;
+ input inval_in;
+ reg [63:0] itlb_valids;
+ input [130:0] m_in;
+ wire \maybe_plrus.plrus%0.plru_acc_en ;
+ wire \maybe_plrus.plrus%0.plru_out ;
+ wire \maybe_plrus.plrus%1.plru_acc_en ;
+ wire \maybe_plrus.plrus%1.plru_out ;
+ wire \maybe_plrus.plrus%10.plru_acc_en ;
+ wire \maybe_plrus.plrus%10.plru_out ;
+ wire \maybe_plrus.plrus%11.plru_acc_en ;
+ wire \maybe_plrus.plrus%11.plru_out ;
+ wire \maybe_plrus.plrus%12.plru_acc_en ;
+ wire \maybe_plrus.plrus%12.plru_out ;
+ wire \maybe_plrus.plrus%13.plru_acc_en ;
+ wire \maybe_plrus.plrus%13.plru_out ;
+ wire \maybe_plrus.plrus%14.plru_acc_en ;
+ wire \maybe_plrus.plrus%14.plru_out ;
+ wire \maybe_plrus.plrus%15.plru_acc_en ;
+ wire \maybe_plrus.plrus%15.plru_out ;
+ wire \maybe_plrus.plrus%16.plru_acc_en ;
+ wire \maybe_plrus.plrus%16.plru_out ;
+ wire \maybe_plrus.plrus%17.plru_acc_en ;
+ wire \maybe_plrus.plrus%17.plru_out ;
+ wire \maybe_plrus.plrus%18.plru_acc_en ;
+ wire \maybe_plrus.plrus%18.plru_out ;
+ wire \maybe_plrus.plrus%19.plru_acc_en ;
+ wire \maybe_plrus.plrus%19.plru_out ;
+ wire \maybe_plrus.plrus%2.plru_acc_en ;
+ wire \maybe_plrus.plrus%2.plru_out ;
+ wire \maybe_plrus.plrus%20.plru_acc_en ;
+ wire \maybe_plrus.plrus%20.plru_out ;
+ wire \maybe_plrus.plrus%21.plru_acc_en ;
+ wire \maybe_plrus.plrus%21.plru_out ;
+ wire \maybe_plrus.plrus%22.plru_acc_en ;
+ wire \maybe_plrus.plrus%22.plru_out ;
+ wire \maybe_plrus.plrus%23.plru_acc_en ;
+ wire \maybe_plrus.plrus%23.plru_out ;
+ wire \maybe_plrus.plrus%24.plru_acc_en ;
+ wire \maybe_plrus.plrus%24.plru_out ;
+ wire \maybe_plrus.plrus%25.plru_acc_en ;
+ wire \maybe_plrus.plrus%25.plru_out ;
+ wire \maybe_plrus.plrus%26.plru_acc_en ;
+ wire \maybe_plrus.plrus%26.plru_out ;
+ wire \maybe_plrus.plrus%27.plru_acc_en ;
+ wire \maybe_plrus.plrus%27.plru_out ;
+ wire \maybe_plrus.plrus%28.plru_acc_en ;
+ wire \maybe_plrus.plrus%28.plru_out ;
+ wire \maybe_plrus.plrus%29.plru_acc_en ;
+ wire \maybe_plrus.plrus%29.plru_out ;
+ wire \maybe_plrus.plrus%3.plru_acc_en ;
+ wire \maybe_plrus.plrus%3.plru_out ;
+ wire \maybe_plrus.plrus%30.plru_acc_en ;
+ wire \maybe_plrus.plrus%30.plru_out ;
+ wire \maybe_plrus.plrus%31.plru_acc_en ;
+ wire \maybe_plrus.plrus%31.plru_out ;
+ wire \maybe_plrus.plrus%4.plru_acc_en ;
+ wire \maybe_plrus.plrus%4.plru_out ;
+ wire \maybe_plrus.plrus%5.plru_acc_en ;
+ wire \maybe_plrus.plrus%5.plru_out ;
+ wire \maybe_plrus.plrus%6.plru_acc_en ;
+ wire \maybe_plrus.plrus%6.plru_out ;
+ wire \maybe_plrus.plrus%7.plru_acc_en ;
+ wire \maybe_plrus.plrus%7.plru_out ;
+ wire \maybe_plrus.plrus%8.plru_acc_en ;
+ wire \maybe_plrus.plrus%8.plru_out ;
+ wire \maybe_plrus.plrus%9.plru_acc_en ;
+ wire \maybe_plrus.plrus%9.plru_out ;
+ wire priv_fault;
+ wire ra_valid;
+ wire \rams%0.do_write ;
+ wire [63:0] \rams%0.dout ;
+ wire \rams%1.do_write ;
+ wire [63:0] \rams%1.dout ;
+ wire [55:0] real_addr;
+ wire replace_way;
+ wire req_hit_way;
+ wire req_is_hit;
+ wire req_is_miss;
+ input rst;
+ output stall_out;
+ wire [5:0] tlb_req_index;
+ input [65:0] wishbone_in;
+ output [106:0] wishbone_out;
+ reg [63:0] \$mem$\1287 [63:0];
+ reg [45:0] \$mem$\1290 [63:0];
+ assign _1255_ = _0495_[0] ? itlb_valids[1] : itlb_valids[0];
+ assign _1256_ = _0495_[0] ? itlb_valids[5] : itlb_valids[4];
+ assign _1257_ = _0495_[0] ? itlb_valids[9] : itlb_valids[8];
+ assign _1258_ = _0495_[0] ? itlb_valids[13] : itlb_valids[12];
+ assign _1259_ = _0495_[0] ? itlb_valids[17] : itlb_valids[16];
+ assign _1260_ = _0495_[0] ? itlb_valids[21] : itlb_valids[20];
+ assign _1261_ = _0495_[0] ? itlb_valids[25] : itlb_valids[24];
+ assign _1262_ = _0495_[0] ? itlb_valids[29] : itlb_valids[28];
+ assign _1263_ = _0495_[0] ? itlb_valids[33] : itlb_valids[32];
+ assign _1264_ = _0495_[0] ? itlb_valids[37] : itlb_valids[36];
+ assign _1265_ = _0495_[0] ? itlb_valids[41] : itlb_valids[40];
+ assign _1266_ = _0495_[0] ? itlb_valids[45] : itlb_valids[44];
+ assign _1267_ = _0495_[0] ? itlb_valids[49] : itlb_valids[48];
+ assign _1268_ = _0495_[0] ? itlb_valids[53] : itlb_valids[52];
+ assign _1269_ = _0495_[0] ? itlb_valids[57] : itlb_valids[56];
+ assign _1270_ = _0495_[0] ? itlb_valids[61] : itlb_valids[60];
+ assign _1271_ = _0495_[2] ? _0612_ : _0611_;
+ assign _1272_ = _0495_[2] ? _0616_ : _0615_;
+ assign _1273_ = _0495_[2] ? _0620_ : _0619_;
+ assign _1274_ = _0495_[2] ? _0624_ : _0623_;
+ assign _1275_ = _0495_[4] ? _0628_ : _0627_;
+ assign _1276_ = _0516_[0] ? cache_valids[2] : cache_valids[0];
+ assign _1277_ = _0516_[0] ? cache_valids[10] : cache_valids[8];
+ assign _1278_ = _0516_[0] ? cache_valids[18] : cache_valids[16];
+ assign _1279_ = _0516_[0] ? cache_valids[26] : cache_valids[24];
+ assign _1280_ = _0516_[0] ? cache_valids[34] : cache_valids[32];
+ assign _1281_ = _0516_[0] ? cache_valids[42] : cache_valids[40];
+ assign _1282_ = _0516_[0] ? cache_valids[50] : cache_valids[48];
+ assign _1283_ = _0516_[0] ? cache_valids[58] : cache_valids[56];
+ assign _1284_ = _0516_[2] ? _1021_ : _1020_;
+ assign _1285_ = _0516_[2] ? _1025_ : _1024_;
+ assign _1286_ = _0518_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _1287_ = _0518_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _1288_ = _0518_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _1289_ = _0518_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _1290_ = _0518_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _1291_ = _0518_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _1292_ = _0518_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _1293_ = _0518_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _1294_ = _0518_[2] ? _1032_ : _1031_;
+ assign _1295_ = _0518_[2] ? _1036_ : _1035_;
+ assign _1296_ = _0522_[0] ? cache_valids[3] : cache_valids[1];
+ assign _1297_ = _0522_[0] ? cache_valids[11] : cache_valids[9];
+ assign _1298_ = _0522_[0] ? cache_valids[19] : cache_valids[17];
+ assign _1299_ = _0522_[0] ? cache_valids[27] : cache_valids[25];
+ assign _1300_ = _0522_[0] ? cache_valids[35] : cache_valids[33];
+ assign _1301_ = _0522_[0] ? cache_valids[43] : cache_valids[41];
+ assign _1302_ = _0522_[0] ? cache_valids[51] : cache_valids[49];
+ assign _1303_ = _0522_[0] ? cache_valids[59] : cache_valids[57];
+ assign _1304_ = _0522_[2] ? _1043_ : _1042_;
+ assign _1305_ = _0522_[2] ? _1047_ : _1046_;
+ assign _1306_ = _0524_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _1307_ = _0524_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _1308_ = _0524_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _1309_ = _0524_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _1310_ = _0524_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _1311_ = _0524_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _1312_ = _0524_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _1313_ = _0524_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _1314_ = _0524_[2] ? _1054_ : _1053_;
+ assign _1315_ = _0524_[2] ? _1058_ : _1057_;
+ assign _1316_ = _0535_[0] ? \maybe_plrus.plrus%30.plru_out : \maybe_plrus.plrus%31.plru_out ;
+ assign _1317_ = _0535_[0] ? \maybe_plrus.plrus%26.plru_out : \maybe_plrus.plrus%27.plru_out ;
+ assign _1318_ = _0535_[0] ? \maybe_plrus.plrus%22.plru_out : \maybe_plrus.plrus%23.plru_out ;
+ assign _1319_ = _0535_[0] ? \maybe_plrus.plrus%18.plru_out : \maybe_plrus.plrus%19.plru_out ;
+ assign _1320_ = _0535_[0] ? \maybe_plrus.plrus%14.plru_out : \maybe_plrus.plrus%15.plru_out ;
+ assign _1321_ = _0535_[0] ? \maybe_plrus.plrus%10.plru_out : \maybe_plrus.plrus%11.plru_out ;
+ assign _1322_ = _0535_[0] ? \maybe_plrus.plrus%6.plru_out : \maybe_plrus.plrus%7.plru_out ;
+ assign _1323_ = _0535_[0] ? \maybe_plrus.plrus%2.plru_out : \maybe_plrus.plrus%3.plru_out ;
+ assign _1324_ = _0535_[2] ? _1065_ : _1064_;
+ assign _1325_ = _0535_[2] ? _1069_ : _1068_;
+ assign _1326_ = _0546_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _1327_ = _0546_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _1328_ = _0546_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _1329_ = _0546_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _1330_ = _0546_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _1331_ = _0546_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _1332_ = _0546_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _1333_ = _0546_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _1334_ = _0546_[2] ? _0021_ : _0019_;
+ assign _1335_ = _0546_[2] ? _0025_ : _0024_;
+ assign _1336_ = _0550_[0] ? cache_tags[179:90] : cache_tags[89:0];
+ assign _1337_ = _0550_[0] ? cache_tags[539:450] : cache_tags[449:360];
+ assign _1338_ = _0550_[0] ? cache_tags[899:810] : cache_tags[809:720];
+ assign _1339_ = _0550_[0] ? cache_tags[1259:1170] : cache_tags[1169:1080];
+ assign _1340_ = _0550_[0] ? cache_tags[1619:1530] : cache_tags[1529:1440];
+ assign _1341_ = _0550_[0] ? cache_tags[1979:1890] : cache_tags[1889:1800];
+ assign _1342_ = _0550_[0] ? cache_tags[2339:2250] : cache_tags[2249:2160];
+ assign _1343_ = _0550_[0] ? cache_tags[2699:2610] : cache_tags[2609:2520];
+ assign _1344_ = _0550_[2] ? _0134_ : _0133_;
+ assign _1345_ = _0550_[2] ? _0138_ : _0137_;
+ assign _1346_ = _0495_[0] ? itlb_valids[3] : itlb_valids[2];
+ assign _1347_ = _0495_[0] ? itlb_valids[7] : itlb_valids[6];
+ assign _1348_ = _0495_[0] ? itlb_valids[11] : itlb_valids[10];
+ assign _1349_ = _0495_[0] ? itlb_valids[15] : itlb_valids[14];
+ assign _1350_ = _0495_[0] ? itlb_valids[19] : itlb_valids[18];
+ assign _1351_ = _0495_[0] ? itlb_valids[23] : itlb_valids[22];
+ assign _1352_ = _0495_[0] ? itlb_valids[27] : itlb_valids[26];
+ assign _1353_ = _0495_[0] ? itlb_valids[31] : itlb_valids[30];
+ assign _1354_ = _0495_[0] ? itlb_valids[35] : itlb_valids[34];
+ assign _1355_ = _0495_[0] ? itlb_valids[39] : itlb_valids[38];
+ assign _1356_ = _0495_[0] ? itlb_valids[43] : itlb_valids[42];
+ assign _1357_ = _0495_[0] ? itlb_valids[47] : itlb_valids[46];
+ assign _1358_ = _0495_[0] ? itlb_valids[51] : itlb_valids[50];
+ assign _1359_ = _0495_[0] ? itlb_valids[55] : itlb_valids[54];
+ assign _1360_ = _0495_[0] ? itlb_valids[59] : itlb_valids[58];
+ assign _1361_ = _0495_[0] ? itlb_valids[63] : itlb_valids[62];
+ assign _1362_ = _0495_[2] ? _0614_ : _0613_;
+ assign _1363_ = _0495_[2] ? _0618_ : _0617_;
+ assign _1364_ = _0495_[2] ? _0622_ : _0621_;
+ assign _1365_ = _0495_[2] ? _0626_ : _0625_;
+ assign _1366_ = _0495_[4] ? _0630_ : _0629_;
+ assign _1367_ = _0516_[0] ? cache_valids[6] : cache_valids[4];
+ assign _1368_ = _0516_[0] ? cache_valids[14] : cache_valids[12];
+ assign _1369_ = _0516_[0] ? cache_valids[22] : cache_valids[20];
+ assign _1370_ = _0516_[0] ? cache_valids[30] : cache_valids[28];
+ assign _1371_ = _0516_[0] ? cache_valids[38] : cache_valids[36];
+ assign _1372_ = _0516_[0] ? cache_valids[46] : cache_valids[44];
+ assign _1373_ = _0516_[0] ? cache_valids[54] : cache_valids[52];
+ assign _1374_ = _0516_[0] ? cache_valids[62] : cache_valids[60];
+ assign _1375_ = _0516_[2] ? _1023_ : _1022_;
+ assign _1376_ = _0516_[2] ? _1027_ : _1026_;
+ assign _1377_ = _0518_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _1378_ = _0518_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _1379_ = _0518_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _1380_ = _0518_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _1381_ = _0518_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _1382_ = _0518_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _1383_ = _0518_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _1384_ = _0518_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _1385_ = _0518_[2] ? _1034_ : _1033_;
+ assign _1386_ = _0518_[2] ? _1038_ : _1037_;
+ assign _1387_ = _0522_[0] ? cache_valids[7] : cache_valids[5];
+ assign _1388_ = _0522_[0] ? cache_valids[15] : cache_valids[13];
+ assign _1389_ = _0522_[0] ? cache_valids[23] : cache_valids[21];
+ assign _1390_ = _0522_[0] ? cache_valids[31] : cache_valids[29];
+ assign _1391_ = _0522_[0] ? cache_valids[39] : cache_valids[37];
+ assign _1392_ = _0522_[0] ? cache_valids[47] : cache_valids[45];
+ assign _1393_ = _0522_[0] ? cache_valids[55] : cache_valids[53];
+ assign _1394_ = _0522_[0] ? cache_valids[63] : cache_valids[61];
+ assign _1395_ = _0522_[2] ? _1045_ : _1044_;
+ assign _1396_ = _0522_[2] ? _1049_ : _1048_;
+ assign _1397_ = _0524_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _1398_ = _0524_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _1399_ = _0524_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _1400_ = _0524_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _1401_ = _0524_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _1402_ = _0524_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _1403_ = _0524_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _1404_ = _0524_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _1405_ = _0524_[2] ? _1056_ : _1055_;
+ assign _1406_ = _0524_[2] ? _1060_ : _1059_;
+ assign _1407_ = _0535_[0] ? \maybe_plrus.plrus%28.plru_out : \maybe_plrus.plrus%29.plru_out ;
+ assign _1408_ = _0535_[0] ? \maybe_plrus.plrus%24.plru_out : \maybe_plrus.plrus%25.plru_out ;
+ assign _1409_ = _0535_[0] ? \maybe_plrus.plrus%20.plru_out : \maybe_plrus.plrus%21.plru_out ;
+ assign _1410_ = _0535_[0] ? \maybe_plrus.plrus%16.plru_out : \maybe_plrus.plrus%17.plru_out ;
+ assign _1411_ = _0535_[0] ? \maybe_plrus.plrus%12.plru_out : \maybe_plrus.plrus%13.plru_out ;
+ assign _1412_ = _0535_[0] ? \maybe_plrus.plrus%8.plru_out : \maybe_plrus.plrus%9.plru_out ;
+ assign _1413_ = _0535_[0] ? \maybe_plrus.plrus%4.plru_out : \maybe_plrus.plrus%5.plru_out ;
+ assign _1414_ = _0535_[0] ? \maybe_plrus.plrus%0.plru_out : \maybe_plrus.plrus%1.plru_out ;
+ assign _1415_ = _0535_[2] ? _1067_ : _1066_;
+ assign _1416_ = _0535_[2] ? _1071_ : _1070_;
+ assign _1417_ = _0546_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _1418_ = _0546_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _1419_ = _0546_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _1420_ = _0546_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _1421_ = _0546_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _1422_ = _0546_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _1423_ = _0546_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _1424_ = _0546_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _1425_ = _0546_[2] ? _0023_ : _0022_;
+ assign _1426_ = _0546_[2] ? _0027_ : _0026_;
+ assign _1427_ = _0550_[0] ? cache_tags[359:270] : cache_tags[269:180];
+ assign _1428_ = _0550_[0] ? cache_tags[719:630] : cache_tags[629:540];
+ assign _1429_ = _0550_[0] ? cache_tags[1079:990] : cache_tags[989:900];
+ assign _1430_ = _0550_[0] ? cache_tags[1439:1350] : cache_tags[1349:1260];
+ assign _1431_ = _0550_[0] ? cache_tags[1799:1710] : cache_tags[1709:1620];
+ assign _1432_ = _0550_[0] ? cache_tags[2159:2070] : cache_tags[2069:1980];
+ assign _1433_ = _0550_[0] ? cache_tags[2519:2430] : cache_tags[2429:2340];
+ assign _1434_ = _0550_[0] ? cache_tags[2879:2790] : cache_tags[2789:2700];
+ assign _1435_ = _0550_[2] ? _0136_ : _0135_;
+ assign _1436_ = _0550_[2] ? _0140_ : _0139_;
+ assign _0611_ = _0495_[1] ? _1346_ : _1255_;
+ assign _0612_ = _0495_[1] ? _1347_ : _1256_;
+ assign _0613_ = _0495_[1] ? _1348_ : _1257_;
+ assign _0614_ = _0495_[1] ? _1349_ : _1258_;
+ assign _0615_ = _0495_[1] ? _1350_ : _1259_;
+ assign _0616_ = _0495_[1] ? _1351_ : _1260_;
+ assign _0617_ = _0495_[1] ? _1352_ : _1261_;
+ assign _0618_ = _0495_[1] ? _1353_ : _1262_;
+ assign _0619_ = _0495_[1] ? _1354_ : _1263_;
+ assign _0620_ = _0495_[1] ? _1355_ : _1264_;
+ assign _0621_ = _0495_[1] ? _1356_ : _1265_;
+ assign _0622_ = _0495_[1] ? _1357_ : _1266_;
+ assign _0623_ = _0495_[1] ? _1358_ : _1267_;
+ assign _0624_ = _0495_[1] ? _1359_ : _1268_;
+ assign _0625_ = _0495_[1] ? _1360_ : _1269_;
+ assign _0626_ = _0495_[1] ? _1361_ : _1270_;
+ assign _0627_ = _0495_[3] ? _1362_ : _1271_;
+ assign _0628_ = _0495_[3] ? _1363_ : _1272_;
+ assign _0629_ = _0495_[3] ? _1364_ : _1273_;
+ assign _0630_ = _0495_[3] ? _1365_ : _1274_;
+ assign _0631_ = _0495_[5] ? _1366_ : _1275_;
+ assign _1020_ = _0516_[1] ? _1367_ : _1276_;
+ assign _1021_ = _0516_[1] ? _1368_ : _1277_;
+ assign _1022_ = _0516_[1] ? _1369_ : _1278_;
+ assign _1023_ = _0516_[1] ? _1370_ : _1279_;
+ assign _1024_ = _0516_[1] ? _1371_ : _1280_;
+ assign _1025_ = _0516_[1] ? _1372_ : _1281_;
+ assign _1026_ = _0516_[1] ? _1373_ : _1282_;
+ assign _1027_ = _0516_[1] ? _1374_ : _1283_;
+ assign _1028_ = _0516_[3] ? _1375_ : _1284_;
+ assign _1029_ = _0516_[3] ? _1376_ : _1285_;
+ assign _1031_ = _0518_[1] ? _1377_ : _1286_;
+ assign _1032_ = _0518_[1] ? _1378_ : _1287_;
+ assign _1033_ = _0518_[1] ? _1379_ : _1288_;
+ assign _1034_ = _0518_[1] ? _1380_ : _1289_;
+ assign _1035_ = _0518_[1] ? _1381_ : _1290_;
+ assign _1036_ = _0518_[1] ? _1382_ : _1291_;
+ assign _1037_ = _0518_[1] ? _1383_ : _1292_;
+ assign _1038_ = _0518_[1] ? _1384_ : _1293_;
+ assign _1039_ = _0518_[3] ? _1385_ : _1294_;
+ assign _1040_ = _0518_[3] ? _1386_ : _1295_;
+ assign _1042_ = _0522_[1] ? _1387_ : _1296_;
+ assign _1043_ = _0522_[1] ? _1388_ : _1297_;
+ assign _1044_ = _0522_[1] ? _1389_ : _1298_;
+ assign _1045_ = _0522_[1] ? _1390_ : _1299_;
+ assign _1046_ = _0522_[1] ? _1391_ : _1300_;
+ assign _1047_ = _0522_[1] ? _1392_ : _1301_;
+ assign _1048_ = _0522_[1] ? _1393_ : _1302_;
+ assign _1049_ = _0522_[1] ? _1394_ : _1303_;
+ assign _1050_ = _0522_[3] ? _1395_ : _1304_;
+ assign _1051_ = _0522_[3] ? _1396_ : _1305_;
+ assign _1053_ = _0524_[1] ? _1397_ : _1306_;
+ assign _1054_ = _0524_[1] ? _1398_ : _1307_;
+ assign _1055_ = _0524_[1] ? _1399_ : _1308_;
+ assign _1056_ = _0524_[1] ? _1400_ : _1309_;
+ assign _1057_ = _0524_[1] ? _1401_ : _1310_;
+ assign _1058_ = _0524_[1] ? _1402_ : _1311_;
+ assign _1059_ = _0524_[1] ? _1403_ : _1312_;
+ assign _1060_ = _0524_[1] ? _1404_ : _1313_;
+ assign _1061_ = _0524_[3] ? _1405_ : _1314_;
+ assign _1062_ = _0524_[3] ? _1406_ : _1315_;
+ assign _1064_ = _0535_[1] ? _1407_ : _1316_;
+ assign _1065_ = _0535_[1] ? _1408_ : _1317_;
+ assign _1066_ = _0535_[1] ? _1409_ : _1318_;
+ assign _1067_ = _0535_[1] ? _1410_ : _1319_;
+ assign _1068_ = _0535_[1] ? _1411_ : _1320_;
+ assign _1069_ = _0535_[1] ? _1412_ : _1321_;
+ assign _1070_ = _0535_[1] ? _1413_ : _1322_;
+ assign _1071_ = _0535_[1] ? _1414_ : _1323_;
+ assign _1072_ = _0535_[3] ? _1415_ : _1324_;
+ assign _1073_ = _0535_[3] ? _1416_ : _1325_;
+ assign _0019_ = _0546_[1] ? _1417_ : _1326_;
+ assign _0021_ = _0546_[1] ? _1418_ : _1327_;
+ assign _0022_ = _0546_[1] ? _1419_ : _1328_;
+ assign _0023_ = _0546_[1] ? _1420_ : _1329_;
+ assign _0024_ = _0546_[1] ? _1421_ : _1330_;
+ assign _0025_ = _0546_[1] ? _1422_ : _1331_;
+ assign _0026_ = _0546_[1] ? _1423_ : _1332_;
+ assign _0027_ = _0546_[1] ? _1424_ : _1333_;
+ assign _0028_ = _0546_[3] ? _1425_ : _1334_;
+ assign _0029_ = _0546_[3] ? _1426_ : _1335_;
+ assign _0133_ = _0550_[1] ? _1427_ : _1336_;
+ assign _0134_ = _0550_[1] ? _1428_ : _1337_;
+ assign _0135_ = _0550_[1] ? _1429_ : _1338_;
+ assign _0136_ = _0550_[1] ? _1430_ : _1339_;
+ assign _0137_ = _0550_[1] ? _1431_ : _1340_;
+ assign _0138_ = _0550_[1] ? _1432_ : _1341_;
+ assign _0139_ = _0550_[1] ? _1433_ : _1342_;
+ assign _0140_ = _0550_[1] ? _1434_ : _1343_;
+ assign _0141_ = _0550_[3] ? _1435_ : _1344_;
+ assign _0142_ = _0550_[3] ? _1436_ : _1345_;
+ assign _0542_ = inval_in ? 64'h0000000000000000 : cache_valids;
+ assign _0543_ = inval_in ? 1'h0 : _0606_[122];
+ assign _0544_ = 5'h1f - i_in[14:10];
+ assign _0545_ = 32'd0 == { 31'h00000000, replace_way };
+ assign _0546_ = 5'h1f - i_in[14:10];
+ assign _0547_ = 5'h1f - i_in[14:10];
+ assign _0548_ = _0545_ ? { _0132_, _0131_, _0130_, _0129_, _0128_, _0127_, _0126_, _0125_, _0124_, _0123_, _0122_, _0121_, _0120_, _0119_, _0118_, _0117_, _0116_, _0114_, _0113_, _0112_, _0111_, _0110_, _0109_, _0108_, _0107_, _0106_, _0105_, _0103_, _0102_, _0101_, _0100_, _0099_ } : cache_tags;
+ assign _0549_ = 32'd1 == { 31'h00000000, replace_way };
+ assign _0550_ = 5'h1f - i_in[14:10];
+ assign _0551_ = 5'h1f - i_in[14:10];
+ assign _0552_ = _0549_ ? { _0246_, _0245_, _0244_, _0243_, _0242_, _0240_, _0239_, _0238_, _0237_, _0236_, _0235_, _0234_, _0233_, _0232_, _0231_, _0229_, _0228_, _0227_, _0226_, _0225_, _0224_, _0223_, _0222_, _0221_, _0220_, _0219_, _0218_, _0217_, _0216_, _0215_, _0214_, _0213_ } : _0548_;
+ assign _0553_ = req_is_miss ? _0552_ : cache_tags;
+ assign _0554_ = req_is_miss ? { _0018_, _0017_, _0016_, _0015_, _0014_, _0013_, _0012_, _0011_, _0010_, _0009_, _0008_, _0007_, _0006_, _0005_, _0004_, _0003_, _0002_, _0001_, _0000_, _1254_, _1253_, _1252_, _1251_, _1250_, _1249_, _1248_, _1247_, _1246_, _1245_, _1243_, _1242_, _1241_, _1240_, _1239_, _1238_, _1237_, _1236_, _1235_, _1234_, _1232_, _1231_, _1230_, _1229_, _1228_, _1227_, _1226_, _1225_, _1224_, _1223_, _1222_, _1221_, _1220_, _1219_, _1218_, _1217_, _1216_, _1215_, _1214_, _1213_, _1212_, _1211_, _1210_, _1209_, _1208_ } : _0542_;
+ assign _0555_ = req_is_miss ? { real_addr[31:6], 7'h01 } : _0606_[32:0];
+ assign _0556_ = req_is_miss ? 2'h3 : _0606_[98:97];
+ assign _0557_ = req_is_miss ? { 1'h1, real_addr[10:6], 3'h0, i_in[14:10], replace_way } : { _0543_, _0606_[121:108] };
+ assign _0558_ = _0606_[0] == 1'h0;
+ assign _0559_ = ~ _0606_[98];
+ assign _0560_ = ~ wishbone_in[65];
+ assign _0561_ = ~ _0559_;
+ assign _0562_ = _0560_ & _0561_;
+ assign _0563_ = _0606_[6:4] == 3'h7;
+ assign _0564_ = _0568_ ? 1'h0 : _0606_[98];
+ assign _0565_ = _0569_ ? 1'h1 : _0559_;
+ assign _0566_ = _0606_[6:4] + 3'h1;
+ assign _0567_ = _0562_ ? { _0606_[32:7], _0566_, _0606_[3:1] } : _0606_[32:1];
+ assign _0568_ = _0562_ & _0563_;
+ assign _0569_ = _0562_ & _0563_;
+ assign _0570_ = _0606_[116:114] == 3'h7;
+ assign _0571_ = _0565_ & _0570_;
+ assign _0572_ = 5'h1f - _0606_[113:109];
+ assign _0573_ = ~ inval_in;
+ assign _0574_ = _0606_[122] & _0573_;
+ assign _0575_ = _0579_ ? { _0449_, _0448_, _0447_, _0446_, _0445_, _0444_, _0443_, _0442_, _0441_, _0439_, _0438_, _0437_, _0436_, _0435_, _0434_, _0433_, _0432_, _0431_, _0430_, _0429_, _0428_, _0427_, _0426_, _0425_, _0424_, _0423_, _0422_, _0421_, _0420_, _0419_, _0418_, _0417_, _0416_, _0415_, _0414_, _0413_, _0412_, _0411_, _0410_, _0408_, _0407_, _0406_, _0405_, _0404_, _0403_, _0402_, _0401_, _0400_, _0399_, _0397_, _0396_, _0395_, _0394_, _0393_, _0392_, _0391_, _0390_, _0389_, _0388_, _0387_, _0386_, _0385_, _0384_, _0383_ } : _0542_;
+ assign _0576_ = _0580_ ? 1'h0 : _0606_[0];
+ assign _0577_ = _0581_ ? 1'h0 : _0606_[97];
+ assign _0578_ = _0606_[116:114] + 3'h1;
+ assign _0579_ = wishbone_in[64] & _0571_;
+ assign _0580_ = wishbone_in[64] & _0571_;
+ assign _0581_ = wishbone_in[64] & _0571_;
+ assign _0582_ = wishbone_in[64] ? { _0606_[121:117], _0578_ } : _0606_[121:114];
+ assign _0583_ = _0606_[0] == 1'h1;
+ function [2879:0] \1207 ;
+ input [2879:0] a;
+ input [5759:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1207 = b[2879:0];
+ 2'b1?:
+ \1207 = b[5759:2880];
+ default:
+ \1207 = a;
+ endcase
+ endfunction
+ assign _0584_ = \1207 (2880'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { cache_tags, _0553_ }, { _0583_, _0558_ });
+ function [63:0] \1209 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1209 = b[63:0];
+ 2'b1?:
+ \1209 = b[127:64];
+ default:
+ \1209 = a;
+ endcase
+ endfunction
+ assign _0585_ = \1209 (64'hxxxxxxxxxxxxxxxx, { _0575_, _0554_ }, { _0583_, _0558_ });
+ function [0:0] \1212 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1212 = b[0:0];
+ 2'b1?:
+ \1212 = b[1:1];
+ default:
+ \1212 = a;
+ endcase
+ endfunction
+ assign _0586_ = \1212 (1'hx, { _0576_, _0555_[0] }, { _0583_, _0558_ });
+ function [31:0] \1215 ;
+ input [31:0] a;
+ input [63:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1215 = b[31:0];
+ 2'b1?:
+ \1215 = b[63:32];
+ default:
+ \1215 = a;
+ endcase
+ endfunction
+ assign _0587_ = \1215 (32'hxxxxxxxx, { _0567_, _0555_[32:1] }, { _0583_, _0558_ });
+ function [0:0] \1218 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1218 = b[0:0];
+ 2'b1?:
+ \1218 = b[1:1];
+ default:
+ \1218 = a;
+ endcase
+ endfunction
+ assign _0588_ = \1218 (1'hx, { _0577_, _0556_[0] }, { _0583_, _0558_ });
+ function [0:0] \1221 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1221 = b[0:0];
+ 2'b1?:
+ \1221 = b[1:1];
+ default:
+ \1221 = a;
+ endcase
+ endfunction
+ assign _0589_ = \1221 (1'hx, { _0564_, _0556_[1] }, { _0583_, _0558_ });
+ function [5:0] \1225 ;
+ input [5:0] a;
+ input [11:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1225 = b[5:0];
+ 2'b1?:
+ \1225 = b[11:6];
+ default:
+ \1225 = a;
+ endcase
+ endfunction
+ assign _0590_ = \1225 (6'hxx, { _0606_[113:108], _0557_[5:0] }, { _0583_, _0558_ });
+ function [7:0] \1228 ;
+ input [7:0] a;
+ input [15:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1228 = b[7:0];
+ 2'b1?:
+ \1228 = b[15:8];
+ default:
+ \1228 = a;
+ endcase
+ endfunction
+ assign _0591_ = \1228 (8'hxx, { _0582_, _0557_[13:6] }, { _0583_, _0558_ });
+ function [0:0] \1231 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1231 = b[0:0];
+ 2'b1?:
+ \1231 = b[1:1];
+ default:
+ \1231 = a;
+ endcase
+ endfunction
+ assign _0592_ = \1231 (1'hx, { _0543_, _0557_[14] }, { _0583_, _0558_ });
+ assign _0593_ = rst ? cache_tags : _0584_;
+ assign _0594_ = rst ? 64'h0000000000000000 : _0585_;
+ assign _0595_ = rst ? 33'h000000000 : { _0587_, _0586_ };
+ assign _0596_ = rst ? 64'h0000000000000000 : _0606_[96:33];
+ assign _0597_ = rst ? 2'h0 : { _0589_, _0588_ };
+ assign _0598_ = rst ? 9'h0ff : _0606_[107:99];
+ assign _0599_ = rst ? _0606_[122:108] : { _0592_, _0591_, _0590_ };
+ assign _0600_ = rst | flush_in;
+ assign _0601_ = _0600_ | m_in[0];
+ assign _0602_ = ~ access_ok;
+ assign _0603_ = i_in[0] & _0602_;
+ assign _0604_ = _0603_ ? 1'h1 : _0606_[123];
+ assign _0605_ = _0601_ ? 1'h0 : _0604_;
+ always @(posedge clk)
+ cache_tags <= _0593_;
+ always @(posedge clk)
+ cache_valids <= _0594_;
+ always @(posedge clk)
+ _0606_ <= { _0605_, _0599_, _0598_, _0597_, _0596_, _0595_ };
+ (* ram_style = "distributed" *)
+ reg [63:0] \1287 [63:0];
+ always @(posedge clk) begin
+ if (_0515_) \1287 [_0500_] <= m_in[130:67];
+ end
+ assign _0608_ = \1287 [tlb_req_index];
+ (* ram_style = "distributed" *)
+ reg [45:0] \1290 [63:0];
+ always @(posedge clk) begin
+ if (_0511_) \1290 [_0500_] <= m_in[66:21];
+ end
+ assign _0610_ = \1290 [tlb_req_index];
+ assign _0632_ = ~ _0503_[5];
+ assign _0633_ = ~ _0503_[4];
+ assign _0634_ = _0632_ & _0633_;
+ assign _0635_ = _0632_ & _0503_[4];
+ assign _0636_ = _0503_[5] & _0633_;
+ assign _0637_ = _0503_[5] & _0503_[4];
+ assign _0638_ = ~ _0503_[3];
+ assign _0639_ = _0634_ & _0638_;
+ assign _0640_ = _0634_ & _0503_[3];
+ assign _0641_ = _0635_ & _0638_;
+ assign _0642_ = _0635_ & _0503_[3];
+ assign _0643_ = _0636_ & _0638_;
+ assign _0644_ = _0636_ & _0503_[3];
+ assign _0645_ = _0637_ & _0638_;
+ assign _0646_ = _0637_ & _0503_[3];
+ assign _0647_ = ~ _0503_[2];
+ assign _0648_ = _0639_ & _0647_;
+ assign _0649_ = _0639_ & _0503_[2];
+ assign _0650_ = _0640_ & _0647_;
+ assign _0651_ = _0640_ & _0503_[2];
+ assign _0652_ = _0641_ & _0647_;
+ assign _0653_ = _0641_ & _0503_[2];
+ assign _0654_ = _0642_ & _0647_;
+ assign _0655_ = _0642_ & _0503_[2];
+ assign _0656_ = _0643_ & _0647_;
+ assign _0657_ = _0643_ & _0503_[2];
+ assign _0658_ = _0644_ & _0647_;
+ assign _0659_ = _0644_ & _0503_[2];
+ assign _0660_ = _0645_ & _0647_;
+ assign _0661_ = _0645_ & _0503_[2];
+ assign _0662_ = _0646_ & _0647_;
+ assign _0663_ = _0646_ & _0503_[2];
+ assign _0664_ = ~ _0503_[1];
+ assign _0665_ = _0648_ & _0664_;
+ assign _0666_ = _0648_ & _0503_[1];
+ assign _0667_ = _0649_ & _0664_;
+ assign _0668_ = _0649_ & _0503_[1];
+ assign _0669_ = _0650_ & _0664_;
+ assign _0670_ = _0650_ & _0503_[1];
+ assign _0671_ = _0651_ & _0664_;
+ assign _0672_ = _0651_ & _0503_[1];
+ assign _0673_ = _0652_ & _0664_;
+ assign _0674_ = _0652_ & _0503_[1];
+ assign _0675_ = _0653_ & _0664_;
+ assign _0676_ = _0653_ & _0503_[1];
+ assign _0677_ = _0654_ & _0664_;
+ assign _0678_ = _0654_ & _0503_[1];
+ assign _0679_ = _0655_ & _0664_;
+ assign _0680_ = _0655_ & _0503_[1];
+ assign _0681_ = _0656_ & _0664_;
+ assign _0682_ = _0656_ & _0503_[1];
+ assign _0683_ = _0657_ & _0664_;
+ assign _0684_ = _0657_ & _0503_[1];
+ assign _0685_ = _0658_ & _0664_;
+ assign _0686_ = _0658_ & _0503_[1];
+ assign _0687_ = _0659_ & _0664_;
+ assign _0688_ = _0659_ & _0503_[1];
+ assign _0689_ = _0660_ & _0664_;
+ assign _0690_ = _0660_ & _0503_[1];
+ assign _0691_ = _0661_ & _0664_;
+ assign _0692_ = _0661_ & _0503_[1];
+ assign _0693_ = _0662_ & _0664_;
+ assign _0694_ = _0662_ & _0503_[1];
+ assign _0695_ = _0663_ & _0664_;
+ assign _0696_ = _0663_ & _0503_[1];
+ assign _0697_ = ~ _0503_[0];
+ assign _0698_ = _0665_ & _0697_;
+ assign _0699_ = _0665_ & _0503_[0];
+ assign _0700_ = _0666_ & _0697_;
+ assign _0701_ = _0666_ & _0503_[0];
+ assign _0702_ = _0667_ & _0697_;
+ assign _0703_ = _0667_ & _0503_[0];
+ assign _0704_ = _0668_ & _0697_;
+ assign _0705_ = _0668_ & _0503_[0];
+ assign _0706_ = _0669_ & _0697_;
+ assign _0707_ = _0669_ & _0503_[0];
+ assign _0708_ = _0670_ & _0697_;
+ assign _0709_ = _0670_ & _0503_[0];
+ assign _0710_ = _0671_ & _0697_;
+ assign _0711_ = _0671_ & _0503_[0];
+ assign _0712_ = _0672_ & _0697_;
+ assign _0713_ = _0672_ & _0503_[0];
+ assign _0714_ = _0673_ & _0697_;
+ assign _0715_ = _0673_ & _0503_[0];
+ assign _0716_ = _0674_ & _0697_;
+ assign _0717_ = _0674_ & _0503_[0];
+ assign _0718_ = _0675_ & _0697_;
+ assign _0719_ = _0675_ & _0503_[0];
+ assign _0720_ = _0676_ & _0697_;
+ assign _0721_ = _0676_ & _0503_[0];
+ assign _0722_ = _0677_ & _0697_;
+ assign _0723_ = _0677_ & _0503_[0];
+ assign _0724_ = _0678_ & _0697_;
+ assign _0725_ = _0678_ & _0503_[0];
+ assign _0726_ = _0679_ & _0697_;
+ assign _0727_ = _0679_ & _0503_[0];
+ assign _0728_ = _0680_ & _0697_;
+ assign _0729_ = _0680_ & _0503_[0];
+ assign _0730_ = _0681_ & _0697_;
+ assign _0731_ = _0681_ & _0503_[0];
+ assign _0732_ = _0682_ & _0697_;
+ assign _0733_ = _0682_ & _0503_[0];
+ assign _0734_ = _0683_ & _0697_;
+ assign _0735_ = _0683_ & _0503_[0];
+ assign _0736_ = _0684_ & _0697_;
+ assign _0737_ = _0684_ & _0503_[0];
+ assign _0738_ = _0685_ & _0697_;
+ assign _0739_ = _0685_ & _0503_[0];
+ assign _0740_ = _0686_ & _0697_;
+ assign _0741_ = _0686_ & _0503_[0];
+ assign _0742_ = _0687_ & _0697_;
+ assign _0743_ = _0687_ & _0503_[0];
+ assign _0744_ = _0688_ & _0697_;
+ assign _0745_ = _0688_ & _0503_[0];
+ assign _0746_ = _0689_ & _0697_;
+ assign _0747_ = _0689_ & _0503_[0];
+ assign _0748_ = _0690_ & _0697_;
+ assign _0749_ = _0690_ & _0503_[0];
+ assign _0750_ = _0691_ & _0697_;
+ assign _0751_ = _0691_ & _0503_[0];
+ assign _0752_ = _0692_ & _0697_;
+ assign _0753_ = _0692_ & _0503_[0];
+ assign _0754_ = _0693_ & _0697_;
+ assign _0755_ = _0693_ & _0503_[0];
+ assign _0756_ = _0694_ & _0697_;
+ assign _0757_ = _0694_ & _0503_[0];
+ assign _0758_ = _0695_ & _0697_;
+ assign _0759_ = _0695_ & _0503_[0];
+ assign _0760_ = _0696_ & _0697_;
+ assign _0761_ = _0696_ & _0503_[0];
+ assign _0762_ = _0698_ ? 1'h0 : itlb_valids[0];
+ assign _0763_ = _0699_ ? 1'h0 : itlb_valids[1];
+ assign _0764_ = _0700_ ? 1'h0 : itlb_valids[2];
+ assign _0765_ = _0701_ ? 1'h0 : itlb_valids[3];
+ assign _0766_ = _0702_ ? 1'h0 : itlb_valids[4];
+ assign _0767_ = _0703_ ? 1'h0 : itlb_valids[5];
+ assign _0768_ = _0704_ ? 1'h0 : itlb_valids[6];
+ assign _0769_ = _0705_ ? 1'h0 : itlb_valids[7];
+ assign _0770_ = _0706_ ? 1'h0 : itlb_valids[8];
+ assign _0771_ = _0707_ ? 1'h0 : itlb_valids[9];
+ assign _0772_ = _0708_ ? 1'h0 : itlb_valids[10];
+ assign _0773_ = _0709_ ? 1'h0 : itlb_valids[11];
+ assign _0774_ = _0710_ ? 1'h0 : itlb_valids[12];
+ assign _0775_ = _0711_ ? 1'h0 : itlb_valids[13];
+ assign _0776_ = _0712_ ? 1'h0 : itlb_valids[14];
+ assign _0777_ = _0713_ ? 1'h0 : itlb_valids[15];
+ assign _0778_ = _0714_ ? 1'h0 : itlb_valids[16];
+ assign _0779_ = _0715_ ? 1'h0 : itlb_valids[17];
+ assign _0780_ = _0716_ ? 1'h0 : itlb_valids[18];
+ assign _0781_ = _0717_ ? 1'h0 : itlb_valids[19];
+ assign _0782_ = _0718_ ? 1'h0 : itlb_valids[20];
+ assign _0783_ = _0719_ ? 1'h0 : itlb_valids[21];
+ assign _0784_ = _0720_ ? 1'h0 : itlb_valids[22];
+ assign _0785_ = _0721_ ? 1'h0 : itlb_valids[23];
+ assign _0786_ = _0722_ ? 1'h0 : itlb_valids[24];
+ assign _0787_ = _0723_ ? 1'h0 : itlb_valids[25];
+ assign _0788_ = _0724_ ? 1'h0 : itlb_valids[26];
+ assign _0789_ = _0725_ ? 1'h0 : itlb_valids[27];
+ assign _0790_ = _0726_ ? 1'h0 : itlb_valids[28];
+ assign _0791_ = _0727_ ? 1'h0 : itlb_valids[29];
+ assign _0792_ = _0728_ ? 1'h0 : itlb_valids[30];
+ assign _0793_ = _0729_ ? 1'h0 : itlb_valids[31];
+ assign _0794_ = _0730_ ? 1'h0 : itlb_valids[32];
+ assign _0795_ = _0731_ ? 1'h0 : itlb_valids[33];
+ assign _0796_ = _0732_ ? 1'h0 : itlb_valids[34];
+ assign _0797_ = _0733_ ? 1'h0 : itlb_valids[35];
+ assign _0798_ = _0734_ ? 1'h0 : itlb_valids[36];
+ assign _0799_ = _0735_ ? 1'h0 : itlb_valids[37];
+ assign _0800_ = _0736_ ? 1'h0 : itlb_valids[38];
+ assign _0801_ = _0737_ ? 1'h0 : itlb_valids[39];
+ assign _0802_ = _0738_ ? 1'h0 : itlb_valids[40];
+ assign _0803_ = _0739_ ? 1'h0 : itlb_valids[41];
+ assign _0804_ = _0740_ ? 1'h0 : itlb_valids[42];
+ assign _0805_ = _0741_ ? 1'h0 : itlb_valids[43];
+ assign _0806_ = _0742_ ? 1'h0 : itlb_valids[44];
+ assign _0807_ = _0743_ ? 1'h0 : itlb_valids[45];
+ assign _0808_ = _0744_ ? 1'h0 : itlb_valids[46];
+ assign _0809_ = _0745_ ? 1'h0 : itlb_valids[47];
+ assign _0810_ = _0746_ ? 1'h0 : itlb_valids[48];
+ assign _0811_ = _0747_ ? 1'h0 : itlb_valids[49];
+ assign _0812_ = _0748_ ? 1'h0 : itlb_valids[50];
+ assign _0813_ = _0749_ ? 1'h0 : itlb_valids[51];
+ assign _0814_ = _0750_ ? 1'h0 : itlb_valids[52];
+ assign _0815_ = _0751_ ? 1'h0 : itlb_valids[53];
+ assign _0816_ = _0752_ ? 1'h0 : itlb_valids[54];
+ assign _0817_ = _0753_ ? 1'h0 : itlb_valids[55];
+ assign _0818_ = _0754_ ? 1'h0 : itlb_valids[56];
+ assign _0819_ = _0755_ ? 1'h0 : itlb_valids[57];
+ assign _0820_ = _0756_ ? 1'h0 : itlb_valids[58];
+ assign _0821_ = _0757_ ? 1'h0 : itlb_valids[59];
+ assign _0822_ = _0758_ ? 1'h0 : itlb_valids[60];
+ assign _0823_ = _0759_ ? 1'h0 : itlb_valids[61];
+ assign _0824_ = _0760_ ? 1'h0 : itlb_valids[62];
+ assign _0825_ = _0761_ ? 1'h0 : itlb_valids[63];
+ assign _0826_ = ~ _0504_[5];
+ assign _0827_ = ~ _0504_[4];
+ assign _0828_ = _0826_ & _0827_;
+ assign _0829_ = _0826_ & _0504_[4];
+ assign _0830_ = _0504_[5] & _0827_;
+ assign _0831_ = _0504_[5] & _0504_[4];
+ assign _0832_ = ~ _0504_[3];
+ assign _0833_ = _0828_ & _0832_;
+ assign _0834_ = _0828_ & _0504_[3];
+ assign _0835_ = _0829_ & _0832_;
+ assign _0836_ = _0829_ & _0504_[3];
+ assign _0837_ = _0830_ & _0832_;
+ assign _0838_ = _0830_ & _0504_[3];
+ assign _0839_ = _0831_ & _0832_;
+ assign _0840_ = _0831_ & _0504_[3];
+ assign _0841_ = ~ _0504_[2];
+ assign _0842_ = _0833_ & _0841_;
+ assign _0843_ = _0833_ & _0504_[2];
+ assign _0844_ = _0834_ & _0841_;
+ assign _0845_ = _0834_ & _0504_[2];
+ assign _0846_ = _0835_ & _0841_;
+ assign _0847_ = _0835_ & _0504_[2];
+ assign _0848_ = _0836_ & _0841_;
+ assign _0849_ = _0836_ & _0504_[2];
+ assign _0850_ = _0837_ & _0841_;
+ assign _0851_ = _0837_ & _0504_[2];
+ assign _0852_ = _0838_ & _0841_;
+ assign _0853_ = _0838_ & _0504_[2];
+ assign _0854_ = _0839_ & _0841_;
+ assign _0855_ = _0839_ & _0504_[2];
+ assign _0856_ = _0840_ & _0841_;
+ assign _0857_ = _0840_ & _0504_[2];
+ assign _0858_ = ~ _0504_[1];
+ assign _0859_ = _0842_ & _0858_;
+ assign _0860_ = _0842_ & _0504_[1];
+ assign _0861_ = _0843_ & _0858_;
+ assign _0862_ = _0843_ & _0504_[1];
+ assign _0863_ = _0844_ & _0858_;
+ assign _0864_ = _0844_ & _0504_[1];
+ assign _0865_ = _0845_ & _0858_;
+ assign _0866_ = _0845_ & _0504_[1];
+ assign _0867_ = _0846_ & _0858_;
+ assign _0868_ = _0846_ & _0504_[1];
+ assign _0869_ = _0847_ & _0858_;
+ assign _0870_ = _0847_ & _0504_[1];
+ assign _0871_ = _0848_ & _0858_;
+ assign _0872_ = _0848_ & _0504_[1];
+ assign _0873_ = _0849_ & _0858_;
+ assign _0874_ = _0849_ & _0504_[1];
+ assign _0875_ = _0850_ & _0858_;
+ assign _0876_ = _0850_ & _0504_[1];
+ assign _0877_ = _0851_ & _0858_;
+ assign _0878_ = _0851_ & _0504_[1];
+ assign _0879_ = _0852_ & _0858_;
+ assign _0880_ = _0852_ & _0504_[1];
+ assign _0881_ = _0853_ & _0858_;
+ assign _0882_ = _0853_ & _0504_[1];
+ assign _0883_ = _0854_ & _0858_;
+ assign _0884_ = _0854_ & _0504_[1];
+ assign _0885_ = _0855_ & _0858_;
+ assign _0886_ = _0855_ & _0504_[1];
+ assign _0887_ = _0856_ & _0858_;
+ assign _0888_ = _0856_ & _0504_[1];
+ assign _0889_ = _0857_ & _0858_;
+ assign _0890_ = _0857_ & _0504_[1];
+ assign _0891_ = ~ _0504_[0];
+ assign _0892_ = _0859_ & _0891_;
+ assign _0893_ = _0859_ & _0504_[0];
+ assign _0894_ = _0860_ & _0891_;
+ assign _0895_ = _0860_ & _0504_[0];
+ assign _0896_ = _0861_ & _0891_;
+ assign _0897_ = _0861_ & _0504_[0];
+ assign _0898_ = _0862_ & _0891_;
+ assign _0899_ = _0862_ & _0504_[0];
+ assign _0900_ = _0863_ & _0891_;
+ assign _0901_ = _0863_ & _0504_[0];
+ assign _0902_ = _0864_ & _0891_;
+ assign _0903_ = _0864_ & _0504_[0];
+ assign _0904_ = _0865_ & _0891_;
+ assign _0905_ = _0865_ & _0504_[0];
+ assign _0906_ = _0866_ & _0891_;
+ assign _0907_ = _0866_ & _0504_[0];
+ assign _0908_ = _0867_ & _0891_;
+ assign _0909_ = _0867_ & _0504_[0];
+ assign _0910_ = _0868_ & _0891_;
+ assign _0911_ = _0868_ & _0504_[0];
+ assign _0912_ = _0869_ & _0891_;
+ assign _0913_ = _0869_ & _0504_[0];
+ assign _0914_ = _0870_ & _0891_;
+ assign _0915_ = _0870_ & _0504_[0];
+ assign _0916_ = _0871_ & _0891_;
+ assign _0917_ = _0871_ & _0504_[0];
+ assign _0918_ = _0872_ & _0891_;
+ assign _0919_ = _0872_ & _0504_[0];
+ assign _0920_ = _0873_ & _0891_;
+ assign _0921_ = _0873_ & _0504_[0];
+ assign _0922_ = _0874_ & _0891_;
+ assign _0923_ = _0874_ & _0504_[0];
+ assign _0924_ = _0875_ & _0891_;
+ assign _0925_ = _0875_ & _0504_[0];
+ assign _0926_ = _0876_ & _0891_;
+ assign _0927_ = _0876_ & _0504_[0];
+ assign _0928_ = _0877_ & _0891_;
+ assign _0929_ = _0877_ & _0504_[0];
+ assign _0930_ = _0878_ & _0891_;
+ assign _0931_ = _0878_ & _0504_[0];
+ assign _0932_ = _0879_ & _0891_;
+ assign _0933_ = _0879_ & _0504_[0];
+ assign _0934_ = _0880_ & _0891_;
+ assign _0935_ = _0880_ & _0504_[0];
+ assign _0936_ = _0881_ & _0891_;
+ assign _0937_ = _0881_ & _0504_[0];
+ assign _0938_ = _0882_ & _0891_;
+ assign _0939_ = _0882_ & _0504_[0];
+ assign _0940_ = _0883_ & _0891_;
+ assign _0941_ = _0883_ & _0504_[0];
+ assign _0942_ = _0884_ & _0891_;
+ assign _0943_ = _0884_ & _0504_[0];
+ assign _0944_ = _0885_ & _0891_;
+ assign _0945_ = _0885_ & _0504_[0];
+ assign _0946_ = _0886_ & _0891_;
+ assign _0947_ = _0886_ & _0504_[0];
+ assign _0948_ = _0887_ & _0891_;
+ assign _0949_ = _0887_ & _0504_[0];
+ assign _0950_ = _0888_ & _0891_;
+ assign _0951_ = _0888_ & _0504_[0];
+ assign _0952_ = _0889_ & _0891_;
+ assign _0953_ = _0889_ & _0504_[0];
+ assign _0954_ = _0890_ & _0891_;
+ assign _0955_ = _0890_ & _0504_[0];
+ assign _0956_ = _0892_ ? 1'h1 : itlb_valids[0];
+ assign _0957_ = _0893_ ? 1'h1 : itlb_valids[1];
+ assign _0958_ = _0894_ ? 1'h1 : itlb_valids[2];
+ assign _0959_ = _0895_ ? 1'h1 : itlb_valids[3];
+ assign _0960_ = _0896_ ? 1'h1 : itlb_valids[4];
+ assign _0961_ = _0897_ ? 1'h1 : itlb_valids[5];
+ assign _0962_ = _0898_ ? 1'h1 : itlb_valids[6];
+ assign _0963_ = _0899_ ? 1'h1 : itlb_valids[7];
+ assign _0964_ = _0900_ ? 1'h1 : itlb_valids[8];
+ assign _0965_ = _0901_ ? 1'h1 : itlb_valids[9];
+ assign _0966_ = _0902_ ? 1'h1 : itlb_valids[10];
+ assign _0967_ = _0903_ ? 1'h1 : itlb_valids[11];
+ assign _0968_ = _0904_ ? 1'h1 : itlb_valids[12];
+ assign _0969_ = _0905_ ? 1'h1 : itlb_valids[13];
+ assign _0970_ = _0906_ ? 1'h1 : itlb_valids[14];
+ assign _0971_ = _0907_ ? 1'h1 : itlb_valids[15];
+ assign _0972_ = _0908_ ? 1'h1 : itlb_valids[16];
+ assign _0973_ = _0909_ ? 1'h1 : itlb_valids[17];
+ assign _0974_ = _0910_ ? 1'h1 : itlb_valids[18];
+ assign _0975_ = _0911_ ? 1'h1 : itlb_valids[19];
+ assign _0976_ = _0912_ ? 1'h1 : itlb_valids[20];
+ assign _0977_ = _0913_ ? 1'h1 : itlb_valids[21];
+ assign _0978_ = _0914_ ? 1'h1 : itlb_valids[22];
+ assign _0979_ = _0915_ ? 1'h1 : itlb_valids[23];
+ assign _0980_ = _0916_ ? 1'h1 : itlb_valids[24];
+ assign _0981_ = _0917_ ? 1'h1 : itlb_valids[25];
+ assign _0982_ = _0918_ ? 1'h1 : itlb_valids[26];
+ assign _0983_ = _0919_ ? 1'h1 : itlb_valids[27];
+ assign _0984_ = _0920_ ? 1'h1 : itlb_valids[28];
+ assign _0985_ = _0921_ ? 1'h1 : itlb_valids[29];
+ assign _0986_ = _0922_ ? 1'h1 : itlb_valids[30];
+ assign _0987_ = _0923_ ? 1'h1 : itlb_valids[31];
+ assign _0988_ = _0924_ ? 1'h1 : itlb_valids[32];
+ assign _0989_ = _0925_ ? 1'h1 : itlb_valids[33];
+ assign _0990_ = _0926_ ? 1'h1 : itlb_valids[34];
+ assign _0991_ = _0927_ ? 1'h1 : itlb_valids[35];
+ assign _0992_ = _0928_ ? 1'h1 : itlb_valids[36];
+ assign _0993_ = _0929_ ? 1'h1 : itlb_valids[37];
+ assign _0994_ = _0930_ ? 1'h1 : itlb_valids[38];
+ assign _0995_ = _0931_ ? 1'h1 : itlb_valids[39];
+ assign _0996_ = _0932_ ? 1'h1 : itlb_valids[40];
+ assign _0997_ = _0933_ ? 1'h1 : itlb_valids[41];
+ assign _0998_ = _0934_ ? 1'h1 : itlb_valids[42];
+ assign _0999_ = _0935_ ? 1'h1 : itlb_valids[43];
+ assign _1000_ = _0936_ ? 1'h1 : itlb_valids[44];
+ assign _1001_ = _0937_ ? 1'h1 : itlb_valids[45];
+ assign _1002_ = _0938_ ? 1'h1 : itlb_valids[46];
+ assign _1003_ = _0939_ ? 1'h1 : itlb_valids[47];
+ assign _1004_ = _0940_ ? 1'h1 : itlb_valids[48];
+ assign _1005_ = _0941_ ? 1'h1 : itlb_valids[49];
+ assign _1006_ = _0942_ ? 1'h1 : itlb_valids[50];
+ assign _1007_ = _0943_ ? 1'h1 : itlb_valids[51];
+ assign _1008_ = _0944_ ? 1'h1 : itlb_valids[52];
+ assign _1009_ = _0945_ ? 1'h1 : itlb_valids[53];
+ assign _1010_ = _0946_ ? 1'h1 : itlb_valids[54];
+ assign _1011_ = _0947_ ? 1'h1 : itlb_valids[55];
+ assign _1012_ = _0948_ ? 1'h1 : itlb_valids[56];
+ assign _1013_ = _0949_ ? 1'h1 : itlb_valids[57];
+ assign _1014_ = _0950_ ? 1'h1 : itlb_valids[58];
+ assign _1015_ = _0951_ ? 1'h1 : itlb_valids[59];
+ assign _1016_ = _0952_ ? 1'h1 : itlb_valids[60];
+ assign _1017_ = _0953_ ? 1'h1 : itlb_valids[61];
+ assign _1018_ = _0954_ ? 1'h1 : itlb_valids[62];
+ assign _1019_ = _0955_ ? 1'h1 : itlb_valids[63];
+ assign _1030_ = _0516_[4] ? _1029_ : _1028_;
+ assign _1041_ = _0518_[4] ? _1040_ : _1039_;
+ assign _1052_ = _0522_[4] ? _1051_ : _1050_;
+ assign _1063_ = _0524_[4] ? _1062_ : _1061_;
+ assign replace_way = _0535_[4] ? _1073_ : _1072_;
+ assign _1074_ = _0536_ ? \rams%0.dout : \rams%1.dout ;
+ assign _1075_ = _0541_[3] ? _1074_[63:32] : _1074_[31:0];
+ assign _1076_ = ~ _0544_[4];
+ assign _1077_ = ~ _0544_[3];
+ assign _1078_ = _1076_ & _1077_;
+ assign _1079_ = _1076_ & _0544_[3];
+ assign _1080_ = _0544_[4] & _1077_;
+ assign _1081_ = _0544_[4] & _0544_[3];
+ assign _1082_ = ~ _0544_[2];
+ assign _1083_ = _1078_ & _1082_;
+ assign _1084_ = _1078_ & _0544_[2];
+ assign _1085_ = _1079_ & _1082_;
+ assign _1086_ = _1079_ & _0544_[2];
+ assign _1087_ = _1080_ & _1082_;
+ assign _1088_ = _1080_ & _0544_[2];
+ assign _1089_ = _1081_ & _1082_;
+ assign _1090_ = _1081_ & _0544_[2];
+ assign _1091_ = ~ _0544_[1];
+ assign _1092_ = _1083_ & _1091_;
+ assign _1093_ = _1083_ & _0544_[1];
+ assign _1094_ = _1084_ & _1091_;
+ assign _1095_ = _1084_ & _0544_[1];
+ assign _1096_ = _1085_ & _1091_;
+ assign _1097_ = _1085_ & _0544_[1];
+ assign _1098_ = _1086_ & _1091_;
+ assign _1099_ = _1086_ & _0544_[1];
+ assign _1100_ = _1087_ & _1091_;
+ assign _1101_ = _1087_ & _0544_[1];
+ assign _1102_ = _1088_ & _1091_;
+ assign _1103_ = _1088_ & _0544_[1];
+ assign _1104_ = _1089_ & _1091_;
+ assign _1105_ = _1089_ & _0544_[1];
+ assign _1106_ = _1090_ & _1091_;
+ assign _1107_ = _1090_ & _0544_[1];
+ assign _1108_ = ~ _0544_[0];
+ assign _1109_ = _1092_ & _1108_;
+ assign _1110_ = _1092_ & _0544_[0];
+ assign _1111_ = _1093_ & _1108_;
+ assign _1112_ = _1093_ & _0544_[0];
+ assign _1113_ = _1094_ & _1108_;
+ assign _1114_ = _1094_ & _0544_[0];
+ assign _1115_ = _1095_ & _1108_;
+ assign _1116_ = _1095_ & _0544_[0];
+ assign _1117_ = _1096_ & _1108_;
+ assign _1118_ = _1096_ & _0544_[0];
+ assign _1119_ = _1097_ & _1108_;
+ assign _1120_ = _1097_ & _0544_[0];
+ assign _1121_ = _1098_ & _1108_;
+ assign _1122_ = _1098_ & _0544_[0];
+ assign _1123_ = _1099_ & _1108_;
+ assign _1124_ = _1099_ & _0544_[0];
+ assign _1125_ = _1100_ & _1108_;
+ assign _1126_ = _1100_ & _0544_[0];
+ assign _1127_ = _1101_ & _1108_;
+ assign _1128_ = _1101_ & _0544_[0];
+ assign _1129_ = _1102_ & _1108_;
+ assign _1130_ = _1102_ & _0544_[0];
+ assign _1131_ = _1103_ & _1108_;
+ assign _1132_ = _1103_ & _0544_[0];
+ assign _1133_ = _1104_ & _1108_;
+ assign _1134_ = _1104_ & _0544_[0];
+ assign _1135_ = _1105_ & _1108_;
+ assign _1136_ = _1105_ & _0544_[0];
+ assign _1137_ = _1106_ & _1108_;
+ assign _1138_ = _1106_ & _0544_[0];
+ assign _1139_ = _1107_ & _1108_;
+ assign _1140_ = _1107_ & _0544_[0];
+ assign _1141_ = ~ replace_way;
+ assign _1142_ = _1109_ & _1141_;
+ assign _1143_ = _1109_ & replace_way;
+ assign _1144_ = _1110_ & _1141_;
+ assign _1145_ = _1110_ & replace_way;
+ assign _1146_ = _1111_ & _1141_;
+ assign _1147_ = _1111_ & replace_way;
+ assign _1148_ = _1112_ & _1141_;
+ assign _1149_ = _1112_ & replace_way;
+ assign _1150_ = _1113_ & _1141_;
+ assign _1151_ = _1113_ & replace_way;
+ assign _1152_ = _1114_ & _1141_;
+ assign _1153_ = _1114_ & replace_way;
+ assign _1154_ = _1115_ & _1141_;
+ assign _1155_ = _1115_ & replace_way;
+ assign _1156_ = _1116_ & _1141_;
+ assign _1157_ = _1116_ & replace_way;
+ assign _1158_ = _1117_ & _1141_;
+ assign _1159_ = _1117_ & replace_way;
+ assign _1160_ = _1118_ & _1141_;
+ assign _1161_ = _1118_ & replace_way;
+ assign _1162_ = _1119_ & _1141_;
+ assign _1163_ = _1119_ & replace_way;
+ assign _1164_ = _1120_ & _1141_;
+ assign _1165_ = _1120_ & replace_way;
+ assign _1166_ = _1121_ & _1141_;
+ assign _1167_ = _1121_ & replace_way;
+ assign _1168_ = _1122_ & _1141_;
+ assign _1169_ = _1122_ & replace_way;
+ assign _1170_ = _1123_ & _1141_;
+ assign _1171_ = _1123_ & replace_way;
+ assign _1172_ = _1124_ & _1141_;
+ assign _1173_ = _1124_ & replace_way;
+ assign _1174_ = _1125_ & _1141_;
+ assign _1175_ = _1125_ & replace_way;
+ assign _1176_ = _1126_ & _1141_;
+ assign _1177_ = _1126_ & replace_way;
+ assign _1178_ = _1127_ & _1141_;
+ assign _1179_ = _1127_ & replace_way;
+ assign _1180_ = _1128_ & _1141_;
+ assign _1181_ = _1128_ & replace_way;
+ assign _1182_ = _1129_ & _1141_;
+ assign _1183_ = _1129_ & replace_way;
+ assign _1184_ = _1130_ & _1141_;
+ assign _1185_ = _1130_ & replace_way;
+ assign _1186_ = _1131_ & _1141_;
+ assign _1187_ = _1131_ & replace_way;
+ assign _1188_ = _1132_ & _1141_;
+ assign _1189_ = _1132_ & replace_way;
+ assign _1190_ = _1133_ & _1141_;
+ assign _1192_ = _1133_ & replace_way;
+ assign _1193_ = _1134_ & _1141_;
+ assign _1194_ = _1134_ & replace_way;
+ assign _1195_ = _1135_ & _1141_;
+ assign _1196_ = _1135_ & replace_way;
+ assign _1197_ = _1136_ & _1141_;
+ assign _1198_ = _1136_ & replace_way;
+ assign _1199_ = _1137_ & _1141_;
+ assign _1200_ = _1137_ & replace_way;
+ assign _1201_ = _1138_ & _1141_;
+ assign _1203_ = _1138_ & replace_way;
+ assign _1204_ = _1139_ & _1141_;
+ assign _1205_ = _1139_ & replace_way;
+ assign _1206_ = _1140_ & _1141_;
+ assign _1207_ = _1140_ & replace_way;
+ assign _1208_ = _1142_ ? 1'h0 : _0542_[0];
+ assign _1209_ = _1143_ ? 1'h0 : _0542_[1];
+ assign _1210_ = _1144_ ? 1'h0 : _0542_[2];
+ assign _1211_ = _1145_ ? 1'h0 : _0542_[3];
+ assign _1212_ = _1146_ ? 1'h0 : _0542_[4];
+ assign _1213_ = _1147_ ? 1'h0 : _0542_[5];
+ assign _1214_ = _1148_ ? 1'h0 : _0542_[6];
+ assign _1215_ = _1149_ ? 1'h0 : _0542_[7];
+ assign _1216_ = _1150_ ? 1'h0 : _0542_[8];
+ assign _1217_ = _1151_ ? 1'h0 : _0542_[9];
+ assign _1218_ = _1152_ ? 1'h0 : _0542_[10];
+ assign _1219_ = _1153_ ? 1'h0 : _0542_[11];
+ assign _1220_ = _1154_ ? 1'h0 : _0542_[12];
+ assign _1221_ = _1155_ ? 1'h0 : _0542_[13];
+ assign _1222_ = _1156_ ? 1'h0 : _0542_[14];
+ assign _1223_ = _1157_ ? 1'h0 : _0542_[15];
+ assign _1224_ = _1158_ ? 1'h0 : _0542_[16];
+ assign _1225_ = _1159_ ? 1'h0 : _0542_[17];
+ assign _1226_ = _1160_ ? 1'h0 : _0542_[18];
+ assign _1227_ = _1161_ ? 1'h0 : _0542_[19];
+ assign _1228_ = _1162_ ? 1'h0 : _0542_[20];
+ assign _1229_ = _1163_ ? 1'h0 : _0542_[21];
+ assign _1230_ = _1164_ ? 1'h0 : _0542_[22];
+ assign _1231_ = _1165_ ? 1'h0 : _0542_[23];
+ assign _1232_ = _1166_ ? 1'h0 : _0542_[24];
+ assign _1234_ = _1167_ ? 1'h0 : _0542_[25];
+ assign _1235_ = _1168_ ? 1'h0 : _0542_[26];
+ assign _1236_ = _1169_ ? 1'h0 : _0542_[27];
+ assign _1237_ = _1170_ ? 1'h0 : _0542_[28];
+ assign _1238_ = _1171_ ? 1'h0 : _0542_[29];
+ assign _1239_ = _1172_ ? 1'h0 : _0542_[30];
+ assign _1240_ = _1173_ ? 1'h0 : _0542_[31];
+ assign _1241_ = _1174_ ? 1'h0 : _0542_[32];
+ assign _1242_ = _1175_ ? 1'h0 : _0542_[33];
+ assign _1243_ = _1176_ ? 1'h0 : _0542_[34];
+ assign _1245_ = _1177_ ? 1'h0 : _0542_[35];
+ assign _1246_ = _1178_ ? 1'h0 : _0542_[36];
+ assign _1247_ = _1179_ ? 1'h0 : _0542_[37];
+ assign _1248_ = _1180_ ? 1'h0 : _0542_[38];
+ assign _1191_ = { 31'h00000000, _0606_[108] } == 32'd0;
+ assign _1249_ = _1181_ ? 1'h0 : _0542_[39];
+ assign _1250_ = _1182_ ? 1'h0 : _0542_[40];
+ assign _1251_ = _1183_ ? 1'h0 : _0542_[41];
+ assign _1252_ = _1184_ ? 1'h0 : _0542_[42];
+ assign _1253_ = _1185_ ? 1'h0 : _0542_[43];
+ assign _1202_ = wishbone_in[64] & _1191_;
+ assign _1254_ = _1186_ ? 1'h0 : _0542_[44];
+ assign _0000_ = _1187_ ? 1'h0 : _0542_[45];
+ assign _0001_ = _1188_ ? 1'h0 : _0542_[46];
+ assign _0002_ = _1189_ ? 1'h0 : _0542_[47];
+ assign _0003_ = _1190_ ? 1'h0 : _0542_[48];
+ assign _0004_ = _1192_ ? 1'h0 : _0542_[49];
+ assign _0005_ = _1193_ ? 1'h0 : _0542_[50];
+ assign _0006_ = _1194_ ? 1'h0 : _0542_[51];
+ assign _0007_ = _1195_ ? 1'h0 : _0542_[52];
+ assign _0008_ = _1196_ ? 1'h0 : _0542_[53];
+ assign _0009_ = _1197_ ? 1'h0 : _0542_[54];
+ assign _0010_ = _1198_ ? 1'h0 : _0542_[55];
+ assign _0011_ = _1199_ ? 1'h0 : _0542_[56];
+ assign _0012_ = _1200_ ? 1'h0 : _0542_[57];
+ assign _0013_ = _1201_ ? 1'h0 : _0542_[58];
+ assign \rams%0.do_write = _1202_ ? 1'h1 : 1'h0;
+ assign _0014_ = _1203_ ? 1'h0 : _0542_[59];
+ assign _0015_ = _1204_ ? 1'h0 : _0542_[60];
+ assign _0016_ = _1205_ ? 1'h0 : _0542_[61];
+ assign _0017_ = _1206_ ? 1'h0 : _0542_[62];
+ assign _0018_ = _1207_ ? 1'h0 : _0542_[63];
+ assign _0030_ = _0546_[4] ? _0029_ : _0028_;
+ assign _0032_ = ~ _0547_[4];
+ assign _0033_ = ~ _0547_[3];
+ assign _0034_ = _0032_ & _0033_;
+ assign _0035_ = _0032_ & _0547_[3];
+ assign _0036_ = _0547_[4] & _0033_;
+ assign _0037_ = _0547_[4] & _0547_[3];
+ assign _0038_ = ~ _0547_[2];
+ assign _0039_ = _0034_ & _0038_;
+ assign _0040_ = _0034_ & _0547_[2];
+ assign _0041_ = _0035_ & _0038_;
+ assign _0042_ = _0035_ & _0547_[2];
+ assign _0043_ = _0036_ & _0038_;
+ assign _0044_ = _0036_ & _0547_[2];
+ assign _0045_ = _0037_ & _0038_;
+ assign _0046_ = _0037_ & _0547_[2];
+ assign _0047_ = ~ _0547_[1];
+ assign _0048_ = _0039_ & _0047_;
+ assign _0049_ = _0039_ & _0547_[1];
+ assign _0050_ = _0040_ & _0047_;
+ assign _0051_ = _0040_ & _0547_[1];
+ assign _0052_ = _0041_ & _0047_;
+ assign _0053_ = _0041_ & _0547_[1];
+ assign _0054_ = _0042_ & _0047_;
+ assign _0055_ = _0042_ & _0547_[1];
+ assign _0056_ = _0043_ & _0047_;
+ assign _0057_ = _0043_ & _0547_[1];
+ assign _0058_ = _0044_ & _0047_;
+ assign _0059_ = _0044_ & _0547_[1];
+ assign _0060_ = _0045_ & _0047_;
+ assign _0061_ = _0045_ & _0547_[1];
+ assign _0063_ = _0046_ & _0047_;
+ assign _0064_ = _0046_ & _0547_[1];
+ assign _0065_ = ~ _0547_[0];
+ assign _0066_ = _0048_ & _0065_;
+ assign _0067_ = _0048_ & _0547_[0];
+ assign _0068_ = _0049_ & _0065_;
+ assign _0069_ = _0049_ & _0547_[0];
+ assign _0070_ = _0050_ & _0065_;
+ assign _0071_ = _0050_ & _0547_[0];
+ assign _0072_ = _0051_ & _0065_;
+ assign _0074_ = _0051_ & _0547_[0];
+ assign _0075_ = _0052_ & _0065_;
+ assign _0076_ = _0052_ & _0547_[0];
+ assign _0077_ = _0053_ & _0065_;
+ assign _0078_ = _0053_ & _0547_[0];
+ assign _0079_ = _0054_ & _0065_;
+ assign _0080_ = _0054_ & _0547_[0];
+ assign _0081_ = _0055_ & _0065_;
+ assign _0082_ = _0055_ & _0547_[0];
+ assign _0083_ = _0056_ & _0065_;
+ assign _0084_ = _0056_ & _0547_[0];
+ assign _0085_ = _0057_ & _0065_;
+ assign _0086_ = _0057_ & _0547_[0];
+ assign _0087_ = _0058_ & _0065_;
+ assign _0088_ = _0058_ & _0547_[0];
+ assign _0089_ = _0059_ & _0065_;
+ assign _0090_ = _0059_ & _0547_[0];
+ assign _0091_ = _0060_ & _0065_;
+ assign _0092_ = _0060_ & _0547_[0];
+ assign _0093_ = _0061_ & _0065_;
+ assign _0094_ = _0061_ & _0547_[0];
+ assign _0095_ = _0063_ & _0065_;
+ assign _0096_ = _0063_ & _0547_[0];
+ assign _0097_ = _0064_ & _0065_;
+ assign _0098_ = _0064_ & _0547_[0];
+ assign _0099_ = _0066_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[89:0];
+ assign _0100_ = _0067_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[179:90];
+ assign _0101_ = _0068_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[269:180];
+ assign _0102_ = _0069_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[359:270];
+ assign _0103_ = _0070_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[449:360];
+ assign _0105_ = _0071_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[539:450];
+ assign _0106_ = _0072_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[629:540];
+ assign _1233_ = { 31'h00000000, _0606_[108] } == 32'd1;
+ assign _0107_ = _0074_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[719:630];
+ assign _0108_ = _0075_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[809:720];
+ assign _0109_ = _0076_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[899:810];
+ assign _0110_ = _0077_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[989:900];
+ assign _0111_ = _0078_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1079:990];
+ assign _1244_ = wishbone_in[64] & _1233_;
+ assign _0112_ = _0079_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1169:1080];
+ assign _0113_ = _0080_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1259:1170];
+ assign _0114_ = _0081_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1349:1260];
+ assign _0116_ = _0082_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1439:1350];
+ assign _0117_ = _0083_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1529:1440];
+ assign _0118_ = _0084_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1619:1530];
+ assign _0119_ = _0085_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1709:1620];
+ assign _0120_ = _0086_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1799:1710];
+ assign _0121_ = _0087_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1889:1800];
+ assign _0122_ = _0088_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[1979:1890];
+ assign _0123_ = _0089_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2069:1980];
+ assign _0124_ = _0090_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2159:2070];
+ assign _0125_ = _0091_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2249:2160];
+ assign _0126_ = _0092_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2339:2250];
+ assign _0127_ = _0093_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2429:2340];
+ assign \rams%1.do_write = _1244_ ? 1'h1 : 1'h0;
+ assign _0128_ = _0094_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2519:2430];
+ assign _0129_ = _0095_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2609:2520];
+ assign _0130_ = _0096_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2699:2610];
+ assign _0131_ = _0097_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2789:2700];
+ assign _0132_ = _0098_ ? { _0030_[89:45], real_addr[55:11] } : cache_tags[2879:2790];
+ assign _0143_ = _0550_[4] ? _0142_ : _0141_;
+ assign _0144_ = ~ _0551_[4];
+ assign _0145_ = ~ _0551_[3];
+ assign _0147_ = _0144_ & _0145_;
+ assign _0148_ = _0144_ & _0551_[3];
+ assign _0149_ = _0551_[4] & _0145_;
+ assign _0150_ = _0551_[4] & _0551_[3];
+ assign _0151_ = ~ _0551_[2];
+ assign _0152_ = _0147_ & _0151_;
+ assign _0153_ = _0147_ & _0551_[2];
+ assign _0154_ = _0148_ & _0151_;
+ assign _0155_ = _0148_ & _0551_[2];
+ assign _0156_ = _0149_ & _0151_;
+ assign _0158_ = _0149_ & _0551_[2];
+ assign _0159_ = _0150_ & _0151_;
+ assign _0160_ = _0150_ & _0551_[2];
+ assign _0161_ = ~ _0551_[1];
+ assign _0162_ = _0152_ & _0161_;
+ assign _0163_ = _0152_ & _0551_[1];
+ assign _0164_ = _0153_ & _0161_;
+ assign _0165_ = _0153_ & _0551_[1];
+ assign _0166_ = _0154_ & _0161_;
+ assign _0167_ = _0154_ & _0551_[1];
+ assign _0168_ = _0155_ & _0161_;
+ assign _0169_ = _0155_ & _0551_[1];
+ assign _0170_ = _0156_ & _0161_;
+ assign _0171_ = _0156_ & _0551_[1];
+ assign _0172_ = _0158_ & _0161_;
+ assign _0173_ = _0158_ & _0551_[1];
+ assign _0174_ = _0159_ & _0161_;
+ assign _0175_ = _0159_ & _0551_[1];
+ assign _0176_ = _0160_ & _0161_;
+ assign _0177_ = _0160_ & _0551_[1];
+ assign _0178_ = ~ _0551_[0];
+ assign _0179_ = _0162_ & _0178_;
+ assign _0180_ = _0162_ & _0551_[0];
+ assign _0181_ = _0163_ & _0178_;
+ assign _0182_ = _0163_ & _0551_[0];
+ assign _0183_ = _0164_ & _0178_;
+ assign _0184_ = _0164_ & _0551_[0];
+ assign _0185_ = _0165_ & _0178_;
+ assign _0186_ = _0165_ & _0551_[0];
+ assign _0187_ = _0166_ & _0178_;
+ assign _0189_ = _0166_ & _0551_[0];
+ assign _0190_ = _0167_ & _0178_;
+ assign _0191_ = _0167_ & _0551_[0];
+ assign _0192_ = _0168_ & _0178_;
+ assign _0193_ = _0168_ & _0551_[0];
+ assign _0194_ = _0169_ & _0178_;
+ assign _0195_ = _0169_ & _0551_[0];
+ assign _0196_ = _0170_ & _0178_;
+ assign _0197_ = _0170_ & _0551_[0];
+ assign _0020_ = { 27'h0000000, i_in[14:10] } == 32'd0;
+ assign _0198_ = _0171_ & _0178_;
+ assign _0200_ = _0171_ & _0551_[0];
+ assign _0201_ = _0172_ & _0178_;
+ assign _0202_ = _0172_ & _0551_[0];
+ assign _0203_ = _0173_ & _0178_;
+ assign _0204_ = _0173_ & _0551_[0];
+ assign _0205_ = _0174_ & _0178_;
+ assign _0206_ = _0174_ & _0551_[0];
+ assign _0207_ = _0175_ & _0178_;
+ assign _0208_ = _0175_ & _0551_[0];
+ assign _0031_ = req_is_hit & _0020_;
+ assign _0209_ = _0176_ & _0178_;
+ assign _0210_ = _0176_ & _0551_[0];
+ assign _0211_ = _0177_ & _0178_;
+ assign _0212_ = _0177_ & _0551_[0];
+ assign _0213_ = _0179_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[89:0];
+ assign _0214_ = _0180_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[179:90];
+ assign _0215_ = _0181_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[269:180];
+ assign _0216_ = _0182_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[359:270];
+ assign _0217_ = _0183_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[449:360];
+ assign _0218_ = _0184_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[539:450];
+ assign _0219_ = _0185_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[629:540];
+ assign _0220_ = _0186_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[719:630];
+ assign \maybe_plrus.plrus%0.plru_acc_en = _0031_ ? req_is_hit : 1'h0;
+ assign _0221_ = _0187_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[809:720];
+ assign _0222_ = _0189_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[899:810];
+ assign _0223_ = _0190_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[989:900];
+ assign _0224_ = _0191_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1079:990];
+ assign _0225_ = _0192_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1169:1080];
+ assign _0226_ = _0193_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1259:1170];
+ assign _0227_ = _0194_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1349:1260];
+ assign _0228_ = _0195_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1439:1350];
+ assign _0229_ = _0196_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1529:1440];
+ assign _0231_ = _0197_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1619:1530];
+ assign _0232_ = _0198_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1709:1620];
+ assign _0233_ = _0200_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1799:1710];
+ assign _0234_ = _0201_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1889:1800];
+ assign _0235_ = _0202_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[1979:1890];
+ assign _0236_ = _0203_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2069:1980];
+ assign _0237_ = _0204_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2159:2070];
+ assign _0238_ = _0205_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2249:2160];
+ assign _0239_ = _0206_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2339:2250];
+ assign _0240_ = _0207_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2429:2340];
+ assign _0242_ = _0208_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2519:2430];
+ assign _0243_ = _0209_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2609:2520];
+ assign _0244_ = _0210_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2699:2610];
+ assign _0245_ = _0211_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2789:2700];
+ assign _0246_ = _0212_ ? { real_addr[55:11], _0143_[44:0] } : _0548_[2879:2790];
+ assign _0247_ = ~ _0572_[4];
+ assign _0248_ = ~ _0572_[3];
+ assign _0249_ = _0247_ & _0248_;
+ assign _0250_ = _0247_ & _0572_[3];
+ assign _0251_ = _0572_[4] & _0248_;
+ assign _0252_ = _0572_[4] & _0572_[3];
+ assign _0253_ = ~ _0572_[2];
+ assign _0254_ = _0249_ & _0253_;
+ assign _0255_ = _0249_ & _0572_[2];
+ assign _0256_ = _0250_ & _0253_;
+ assign _0257_ = _0250_ & _0572_[2];
+ assign _0258_ = _0251_ & _0253_;
+ assign _0259_ = _0251_ & _0572_[2];
+ assign _0260_ = _0252_ & _0253_;
+ assign _0261_ = _0252_ & _0572_[2];
+ assign _0262_ = ~ _0572_[1];
+ assign _0263_ = _0254_ & _0262_;
+ assign _0264_ = _0254_ & _0572_[1];
+ assign _0265_ = _0255_ & _0262_;
+ assign _0266_ = _0255_ & _0572_[1];
+ assign _0267_ = _0256_ & _0262_;
+ assign _0268_ = _0256_ & _0572_[1];
+ assign _0269_ = _0257_ & _0262_;
+ assign _0270_ = _0257_ & _0572_[1];
+ assign _0271_ = _0258_ & _0262_;
+ assign _0273_ = _0258_ & _0572_[1];
+ assign _0062_ = { 27'h0000000, i_in[14:10] } == 32'd1;
+ assign _0274_ = _0259_ & _0262_;
+ assign _0275_ = _0259_ & _0572_[1];
+ assign _0276_ = _0260_ & _0262_;
+ assign _0277_ = _0260_ & _0572_[1];
+ assign _0278_ = _0261_ & _0262_;
+ assign _0279_ = _0261_ & _0572_[1];
+ assign _0280_ = ~ _0572_[0];
+ assign _0281_ = _0263_ & _0280_;
+ assign _0282_ = _0263_ & _0572_[0];
+ assign _0073_ = req_is_hit & _0062_;
+ assign _0284_ = _0264_ & _0280_;
+ assign _0285_ = _0264_ & _0572_[0];
+ assign _0286_ = _0265_ & _0280_;
+ assign _0287_ = _0265_ & _0572_[0];
+ assign _0288_ = _0266_ & _0280_;
+ assign _0289_ = _0266_ & _0572_[0];
+ assign _0290_ = _0267_ & _0280_;
+ assign _0291_ = _0267_ & _0572_[0];
+ assign _0292_ = _0268_ & _0280_;
+ assign _0293_ = _0268_ & _0572_[0];
+ assign _0294_ = _0269_ & _0280_;
+ assign _0295_ = _0269_ & _0572_[0];
+ assign _0296_ = _0270_ & _0280_;
+ assign _0297_ = _0270_ & _0572_[0];
+ assign _0298_ = _0271_ & _0280_;
+ assign _0299_ = _0271_ & _0572_[0];
+ assign _0300_ = _0273_ & _0280_;
+ assign _0301_ = _0273_ & _0572_[0];
+ assign _0302_ = _0274_ & _0280_;
+ assign _0303_ = _0274_ & _0572_[0];
+ assign \maybe_plrus.plrus%1.plru_acc_en = _0073_ ? req_is_hit : 1'h0;
+ assign _0304_ = _0275_ & _0280_;
+ assign _0305_ = _0275_ & _0572_[0];
+ assign _0306_ = _0276_ & _0280_;
+ assign _0307_ = _0276_ & _0572_[0];
+ assign _0308_ = _0277_ & _0280_;
+ assign _0309_ = _0277_ & _0572_[0];
+ assign _0310_ = _0278_ & _0280_;
+ assign _0311_ = _0278_ & _0572_[0];
+ assign _0312_ = _0279_ & _0280_;
+ assign _0313_ = _0279_ & _0572_[0];
+ assign _0315_ = ~ _0606_[108];
+ assign _0316_ = _0281_ & _0315_;
+ assign _0317_ = _0281_ & _0606_[108];
+ assign _0318_ = _0282_ & _0315_;
+ assign _0319_ = _0282_ & _0606_[108];
+ assign _0320_ = _0284_ & _0315_;
+ assign _0321_ = _0284_ & _0606_[108];
+ assign _0322_ = _0285_ & _0315_;
+ assign _0323_ = _0285_ & _0606_[108];
+ assign _0324_ = _0286_ & _0315_;
+ assign _0326_ = _0286_ & _0606_[108];
+ assign _0327_ = _0287_ & _0315_;
+ assign _0328_ = _0287_ & _0606_[108];
+ assign _0329_ = _0288_ & _0315_;
+ assign _0330_ = _0288_ & _0606_[108];
+ assign _0331_ = _0289_ & _0315_;
+ assign _0332_ = _0289_ & _0606_[108];
+ assign _0333_ = _0290_ & _0315_;
+ assign _0334_ = _0290_ & _0606_[108];
+ assign _0335_ = _0291_ & _0315_;
+ assign _0336_ = _0291_ & _0606_[108];
+ assign _0337_ = _0292_ & _0315_;
+ assign _0338_ = _0292_ & _0606_[108];
+ assign _0339_ = _0293_ & _0315_;
+ assign _0340_ = _0293_ & _0606_[108];
+ assign _0341_ = _0294_ & _0315_;
+ assign _0342_ = _0294_ & _0606_[108];
+ assign _0343_ = _0295_ & _0315_;
+ assign _0344_ = _0295_ & _0606_[108];
+ assign _0345_ = _0296_ & _0315_;
+ assign _0346_ = _0296_ & _0606_[108];
+ assign _0347_ = _0297_ & _0315_;
+ assign _0348_ = _0297_ & _0606_[108];
+ assign _0349_ = _0298_ & _0315_;
+ assign _0350_ = _0298_ & _0606_[108];
+ assign _0351_ = _0299_ & _0315_;
+ assign _0352_ = _0299_ & _0606_[108];
+ assign _0353_ = _0300_ & _0315_;
+ assign _0354_ = _0300_ & _0606_[108];
+ assign _0355_ = _0301_ & _0315_;
+ assign _0357_ = _0301_ & _0606_[108];
+ assign _0358_ = _0302_ & _0315_;
+ assign _0359_ = _0302_ & _0606_[108];
+ assign _0360_ = _0303_ & _0315_;
+ assign _0361_ = _0303_ & _0606_[108];
+ assign _0362_ = _0304_ & _0315_;
+ assign _0363_ = _0304_ & _0606_[108];
+ assign _0364_ = _0305_ & _0315_;
+ assign _0365_ = _0305_ & _0606_[108];
+ assign _0366_ = _0306_ & _0315_;
+ assign _0368_ = _0306_ & _0606_[108];
+ assign _0369_ = _0307_ & _0315_;
+ assign _0370_ = _0307_ & _0606_[108];
+ assign _0371_ = _0308_ & _0315_;
+ assign _0372_ = _0308_ & _0606_[108];
+ assign _0373_ = _0309_ & _0315_;
+ assign _0374_ = _0309_ & _0606_[108];
+ assign _0375_ = _0310_ & _0315_;
+ assign _0376_ = _0310_ & _0606_[108];
+ assign _0377_ = _0311_ & _0315_;
+ assign _0378_ = _0311_ & _0606_[108];
+ assign _0379_ = _0312_ & _0315_;
+ assign _0380_ = _0312_ & _0606_[108];
+ assign _0381_ = _0313_ & _0315_;
+ assign _0382_ = _0313_ & _0606_[108];
+ assign _0383_ = _0316_ ? _0574_ : _0542_[0];
+ assign _0384_ = _0317_ ? _0574_ : _0542_[1];
+ assign _0104_ = { 27'h0000000, i_in[14:10] } == 32'd2;
+ assign _0385_ = _0318_ ? _0574_ : _0542_[2];
+ assign _0386_ = _0319_ ? _0574_ : _0542_[3];
+ assign _0387_ = _0320_ ? _0574_ : _0542_[4];
+ assign _0388_ = _0321_ ? _0574_ : _0542_[5];
+ assign _0389_ = _0322_ ? _0574_ : _0542_[6];
+ assign _0115_ = req_is_hit & _0104_;
+ assign _0390_ = _0323_ ? _0574_ : _0542_[7];
+ assign _0391_ = _0324_ ? _0574_ : _0542_[8];
+ assign _0392_ = _0326_ ? _0574_ : _0542_[9];
+ assign _0393_ = _0327_ ? _0574_ : _0542_[10];
+ assign _0394_ = _0328_ ? _0574_ : _0542_[11];
+ assign _0395_ = _0329_ ? _0574_ : _0542_[12];
+ assign _0396_ = _0330_ ? _0574_ : _0542_[13];
+ assign _0397_ = _0331_ ? _0574_ : _0542_[14];
+ assign _0399_ = _0332_ ? _0574_ : _0542_[15];
+ assign _0400_ = _0333_ ? _0574_ : _0542_[16];
+ assign \maybe_plrus.plrus%2.plru_acc_en = _0115_ ? req_is_hit : 1'h0;
+ assign _0401_ = _0334_ ? _0574_ : _0542_[17];
+ assign _0402_ = _0335_ ? _0574_ : _0542_[18];
+ assign _0403_ = _0336_ ? _0574_ : _0542_[19];
+ assign _0404_ = _0337_ ? _0574_ : _0542_[20];
+ assign _0405_ = _0338_ ? _0574_ : _0542_[21];
+ assign _0406_ = _0339_ ? _0574_ : _0542_[22];
+ assign _0407_ = _0340_ ? _0574_ : _0542_[23];
+ assign _0408_ = _0341_ ? _0574_ : _0542_[24];
+ assign _0410_ = _0342_ ? _0574_ : _0542_[25];
+ assign _0411_ = _0343_ ? _0574_ : _0542_[26];
+ assign _0412_ = _0344_ ? _0574_ : _0542_[27];
+ assign _0413_ = _0345_ ? _0574_ : _0542_[28];
+ assign _0414_ = _0346_ ? _0574_ : _0542_[29];
+ assign _0415_ = _0347_ ? _0574_ : _0542_[30];
+ assign _0416_ = _0348_ ? _0574_ : _0542_[31];
+ assign _0417_ = _0349_ ? _0574_ : _0542_[32];
+ assign _0418_ = _0350_ ? _0574_ : _0542_[33];
+ assign _0419_ = _0351_ ? _0574_ : _0542_[34];
+ assign _0420_ = _0352_ ? _0574_ : _0542_[35];
+ assign _0421_ = _0353_ ? _0574_ : _0542_[36];
+ assign _0422_ = _0354_ ? _0574_ : _0542_[37];
+ assign _0423_ = _0355_ ? _0574_ : _0542_[38];
+ assign _0424_ = _0357_ ? _0574_ : _0542_[39];
+ assign _0425_ = _0358_ ? _0574_ : _0542_[40];
+ assign _0426_ = _0359_ ? _0574_ : _0542_[41];
+ assign _0427_ = _0360_ ? _0574_ : _0542_[42];
+ assign _0428_ = _0361_ ? _0574_ : _0542_[43];
+ assign _0429_ = _0362_ ? _0574_ : _0542_[44];
+ assign _0430_ = _0363_ ? _0574_ : _0542_[45];
+ assign _0431_ = _0364_ ? _0574_ : _0542_[46];
+ assign _0432_ = _0365_ ? _0574_ : _0542_[47];
+ assign _0433_ = _0366_ ? _0574_ : _0542_[48];
+ assign _0434_ = _0368_ ? _0574_ : _0542_[49];
+ assign _0435_ = _0369_ ? _0574_ : _0542_[50];
+ assign _0436_ = _0370_ ? _0574_ : _0542_[51];
+ assign _0437_ = _0371_ ? _0574_ : _0542_[52];
+ assign _0438_ = _0372_ ? _0574_ : _0542_[53];
+ assign _0439_ = _0373_ ? _0574_ : _0542_[54];
+ assign _0441_ = _0374_ ? _0574_ : _0542_[55];
+ assign _0442_ = _0375_ ? _0574_ : _0542_[56];
+ assign _0146_ = { 27'h0000000, i_in[14:10] } == 32'd3;
+ assign _0443_ = _0376_ ? _0574_ : _0542_[57];
+ assign _0444_ = _0377_ ? _0574_ : _0542_[58];
+ assign _0445_ = _0378_ ? _0574_ : _0542_[59];
+ assign _0446_ = _0379_ ? _0574_ : _0542_[60];
+ assign _0447_ = _0380_ ? _0574_ : _0542_[61];
+ assign _0157_ = req_is_hit & _0146_;
+ assign _0448_ = _0381_ ? _0574_ : _0542_[62];
+ assign _0449_ = _0382_ ? _0574_ : _0542_[63];
+ assign \maybe_plrus.plrus%3.plru_acc_en = _0157_ ? req_is_hit : 1'h0;
+ assign _0188_ = { 27'h0000000, i_in[14:10] } == 32'd4;
+ assign _0199_ = req_is_hit & _0188_;
+ assign \maybe_plrus.plrus%4.plru_acc_en = _0199_ ? req_is_hit : 1'h0;
+ assign _0230_ = { 27'h0000000, i_in[14:10] } == 32'd5;
+ assign _0241_ = req_is_hit & _0230_;
+ assign \maybe_plrus.plrus%5.plru_acc_en = _0241_ ? req_is_hit : 1'h0;
+ assign _0272_ = { 27'h0000000, i_in[14:10] } == 32'd6;
+ assign _0283_ = req_is_hit & _0272_;
+ assign \maybe_plrus.plrus%6.plru_acc_en = _0283_ ? req_is_hit : 1'h0;
+ assign _0314_ = { 27'h0000000, i_in[14:10] } == 32'd7;
+ assign _0325_ = req_is_hit & _0314_;
+ assign \maybe_plrus.plrus%7.plru_acc_en = _0325_ ? req_is_hit : 1'h0;
+ assign _0356_ = { 27'h0000000, i_in[14:10] } == 32'd8;
+ assign _0367_ = req_is_hit & _0356_;
+ assign \maybe_plrus.plrus%8.plru_acc_en = _0367_ ? req_is_hit : 1'h0;
+ assign _0398_ = { 27'h0000000, i_in[14:10] } == 32'd9;
+ assign _0409_ = req_is_hit & _0398_;
+ assign \maybe_plrus.plrus%9.plru_acc_en = _0409_ ? req_is_hit : 1'h0;
+ assign _0440_ = { 27'h0000000, i_in[14:10] } == 32'd10;
+ assign _0450_ = req_is_hit & _0440_;
+ assign \maybe_plrus.plrus%10.plru_acc_en = _0450_ ? req_is_hit : 1'h0;
+ assign _0451_ = { 27'h0000000, i_in[14:10] } == 32'd11;
+ assign _0452_ = req_is_hit & _0451_;
+ assign \maybe_plrus.plrus%11.plru_acc_en = _0452_ ? req_is_hit : 1'h0;
+ assign _0453_ = { 27'h0000000, i_in[14:10] } == 32'd12;
+ assign _0454_ = req_is_hit & _0453_;
+ assign \maybe_plrus.plrus%12.plru_acc_en = _0454_ ? req_is_hit : 1'h0;
+ assign _0455_ = { 27'h0000000, i_in[14:10] } == 32'd13;
+ assign _0456_ = req_is_hit & _0455_;
+ assign \maybe_plrus.plrus%13.plru_acc_en = _0456_ ? req_is_hit : 1'h0;
+ assign _0457_ = { 27'h0000000, i_in[14:10] } == 32'd14;
+ assign _0458_ = req_is_hit & _0457_;
+ assign \maybe_plrus.plrus%14.plru_acc_en = _0458_ ? req_is_hit : 1'h0;
+ assign _0459_ = { 27'h0000000, i_in[14:10] } == 32'd15;
+ assign _0460_ = req_is_hit & _0459_;
+ assign \maybe_plrus.plrus%15.plru_acc_en = _0460_ ? req_is_hit : 1'h0;
+ assign _0461_ = { 27'h0000000, i_in[14:10] } == 32'd16;
+ assign _0462_ = req_is_hit & _0461_;
+ assign \maybe_plrus.plrus%16.plru_acc_en = _0462_ ? req_is_hit : 1'h0;
+ assign _0463_ = { 27'h0000000, i_in[14:10] } == 32'd17;
+ assign _0464_ = req_is_hit & _0463_;
+ assign \maybe_plrus.plrus%17.plru_acc_en = _0464_ ? req_is_hit : 1'h0;
+ assign _0465_ = { 27'h0000000, i_in[14:10] } == 32'd18;
+ assign _0466_ = req_is_hit & _0465_;
+ assign \maybe_plrus.plrus%18.plru_acc_en = _0466_ ? req_is_hit : 1'h0;
+ assign _0467_ = { 27'h0000000, i_in[14:10] } == 32'd19;
+ assign _0468_ = req_is_hit & _0467_;
+ assign \maybe_plrus.plrus%19.plru_acc_en = _0468_ ? req_is_hit : 1'h0;
+ assign _0469_ = { 27'h0000000, i_in[14:10] } == 32'd20;
+ assign _0470_ = req_is_hit & _0469_;
+ assign \maybe_plrus.plrus%20.plru_acc_en = _0470_ ? req_is_hit : 1'h0;
+ assign _0471_ = { 27'h0000000, i_in[14:10] } == 32'd21;
+ assign _0472_ = req_is_hit & _0471_;
+ assign \maybe_plrus.plrus%21.plru_acc_en = _0472_ ? req_is_hit : 1'h0;
+ assign _0473_ = { 27'h0000000, i_in[14:10] } == 32'd22;
+ assign _0474_ = req_is_hit & _0473_;
+ assign \maybe_plrus.plrus%22.plru_acc_en = _0474_ ? req_is_hit : 1'h0;
+ assign _0475_ = { 27'h0000000, i_in[14:10] } == 32'd23;
+ assign _0476_ = req_is_hit & _0475_;
+ assign \maybe_plrus.plrus%23.plru_acc_en = _0476_ ? req_is_hit : 1'h0;
+ assign _0477_ = { 27'h0000000, i_in[14:10] } == 32'd24;
+ assign _0478_ = req_is_hit & _0477_;
+ assign \maybe_plrus.plrus%24.plru_acc_en = _0478_ ? req_is_hit : 1'h0;
+ assign _0479_ = { 27'h0000000, i_in[14:10] } == 32'd25;
+ assign _0480_ = req_is_hit & _0479_;
+ assign \maybe_plrus.plrus%25.plru_acc_en = _0480_ ? req_is_hit : 1'h0;
+ assign _0481_ = { 27'h0000000, i_in[14:10] } == 32'd26;
+ assign _0482_ = req_is_hit & _0481_;
+ assign \maybe_plrus.plrus%26.plru_acc_en = _0482_ ? req_is_hit : 1'h0;
+ assign _0483_ = { 27'h0000000, i_in[14:10] } == 32'd27;
+ assign _0484_ = req_is_hit & _0483_;
+ assign \maybe_plrus.plrus%27.plru_acc_en = _0484_ ? req_is_hit : 1'h0;
+ assign _0485_ = { 27'h0000000, i_in[14:10] } == 32'd28;
+ assign _0486_ = req_is_hit & _0485_;
+ assign \maybe_plrus.plrus%28.plru_acc_en = _0486_ ? req_is_hit : 1'h0;
+ assign _0487_ = { 27'h0000000, i_in[14:10] } == 32'd29;
+ assign _0488_ = req_is_hit & _0487_;
+ assign \maybe_plrus.plrus%29.plru_acc_en = _0488_ ? req_is_hit : 1'h0;
+ assign _0489_ = { 27'h0000000, i_in[14:10] } == 32'd30;
+ assign _0490_ = req_is_hit & _0489_;
+ assign \maybe_plrus.plrus%30.plru_acc_en = _0490_ ? req_is_hit : 1'h0;
+ assign _0491_ = { 27'h0000000, i_in[14:10] } == 32'd31;
+ assign _0492_ = req_is_hit & _0491_;
+ assign \maybe_plrus.plrus%31.plru_acc_en = _0492_ ? req_is_hit : 1'h0;
+ assign _0493_ = i_in[21:16] ^ i_in[27:22];
+ assign tlb_req_index = _0493_ ^ i_in[33:28];
+ assign _0494_ = _0610_ == i_in[67:22];
+ assign _0495_ = 6'h3f - tlb_req_index;
+ assign _0496_ = _0494_ ? _0631_ : 1'h0;
+ assign eaa_priv = i_in[1] ? _0608_[3] : 1'h1;
+ assign real_addr = i_in[1] ? { _0608_[55:12], i_in[15:4] } : i_in[59:4];
+ assign ra_valid = i_in[1] ? _0496_ : 1'h1;
+ assign _0497_ = ~ i_in[2];
+ assign priv_fault = eaa_priv & _0497_;
+ assign _0498_ = ~ priv_fault;
+ assign access_ok = ra_valid & _0498_;
+ assign _0499_ = m_in[20:15] ^ m_in[26:21];
+ assign _0500_ = _0499_ ^ m_in[32:27];
+ assign _0501_ = m_in[1] & m_in[2];
+ assign _0502_ = rst | _0501_;
+ assign _0503_ = 6'h3f - _0500_;
+ assign _0504_ = 6'h3f - _0500_;
+ assign _0505_ = m_in[0] ? { _1019_, _1018_, _1017_, _1016_, _1015_, _1014_, _1013_, _1012_, _1011_, _1010_, _1009_, _1008_, _1007_, _1006_, _1005_, _1004_, _1003_, _1002_, _1001_, _1000_, _0999_, _0998_, _0997_, _0996_, _0995_, _0994_, _0993_, _0992_, _0991_, _0990_, _0989_, _0988_, _0987_, _0986_, _0985_, _0984_, _0983_, _0982_, _0981_, _0980_, _0979_, _0978_, _0977_, _0976_, _0975_, _0974_, _0973_, _0972_, _0971_, _0970_, _0969_, _0968_, _0967_, _0966_, _0965_, _0964_, _0963_, _0962_, _0961_, _0960_, _0959_, _0958_, _0957_, _0956_ } : itlb_valids;
+ assign _0506_ = m_in[1] ? { _0825_, _0824_, _0823_, _0822_, _0821_, _0820_, _0819_, _0818_, _0817_, _0816_, _0815_, _0814_, _0813_, _0812_, _0811_, _0810_, _0809_, _0808_, _0807_, _0806_, _0805_, _0804_, _0803_, _0802_, _0801_, _0800_, _0799_, _0798_, _0797_, _0796_, _0795_, _0794_, _0793_, _0792_, _0791_, _0790_, _0789_, _0788_, _0787_, _0786_, _0785_, _0784_, _0783_, _0782_, _0781_, _0780_, _0779_, _0778_, _0777_, _0776_, _0775_, _0774_, _0773_, _0772_, _0771_, _0770_, _0769_, _0768_, _0767_, _0766_, _0765_, _0764_, _0763_, _0762_ } : _0505_;
+ assign _0507_ = _0502_ ? 64'h0000000000000000 : _0506_;
+ always @(posedge clk)
+ itlb_valids <= _0507_;
+ assign _0508_ = ~ _0502_;
+ assign _0509_ = ~ m_in[1];
+ assign _0510_ = _0508_ & _0509_;
+ assign _0511_ = _0510_ & m_in[0];
+ assign _0512_ = ~ _0502_;
+ assign _0513_ = ~ m_in[1];
+ assign _0514_ = _0512_ & _0513_;
+ assign _0515_ = _0514_ & m_in[0];
+ assign _0516_ = 5'h1f - i_in[14:10];
+ assign _0517_ = i_in[0] & _1030_;
+ assign _0518_ = 5'h1f - i_in[14:10];
+ assign _0519_ = _1041_[44:0] == real_addr[55:11];
+ assign _0520_ = _0519_ ? 1'h1 : 1'h0;
+ assign _0521_ = _0517_ ? _0520_ : 1'h0;
+ assign _0522_ = 5'h1f - i_in[14:10];
+ assign _0523_ = i_in[0] & _1052_;
+ assign _0524_ = 5'h1f - i_in[14:10];
+ assign _0525_ = _1063_[89:45] == real_addr[55:11];
+ assign _0526_ = _0528_ ? 1'h1 : _0521_;
+ assign _0527_ = _0525_ ? 1'h1 : 1'h0;
+ assign _0528_ = _0523_ & _0525_;
+ assign req_hit_way = _0523_ ? _0527_ : 1'h0;
+ assign _0529_ = i_in[0] & access_ok;
+ assign _0530_ = ~ flush_in;
+ assign _0531_ = _0529_ & _0530_;
+ assign _0532_ = ~ rst;
+ assign _0533_ = _0531_ & _0532_;
+ assign _0534_ = ~ _0526_;
+ assign req_is_hit = _0533_ ? _0526_ : 1'h0;
+ assign req_is_miss = _0533_ ? _0534_ : 1'h0;
+ assign _0535_ = 5'h1f - i_in[14:10];
+ assign _0536_ = 1'h1 - _0541_[0];
+ assign _0537_ = _0526_ & access_ok;
+ assign _0538_ = ~ _0537_;
+ assign _0539_ = req_is_hit ? req_hit_way : _0541_[0];
+ assign _0540_ = req_is_hit ? i_in[3] : i_in[3];
+ always @(posedge clk)
+ _0541_ <= { req_is_hit, _0540_, i_in[67:4], _0539_ };
+ plru_1 \maybe_plrus.plrus%0.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%0.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%0.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%1.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%1.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%1.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%10.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%10.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%10.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%11.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%11.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%11.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%12.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%12.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%12.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%13.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%13.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%13.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%14.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%14.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%14.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%15.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%15.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%15.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%16.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%16.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%16.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%17.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%17.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%17.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%18.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%18.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%18.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%19.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%19.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%19.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%2.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%2.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%2.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%20.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%20.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%20.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%21.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%21.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%21.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%22.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%22.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%22.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%23.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%23.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%23.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%24.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%24.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%24.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%25.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%25.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%25.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%26.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%26.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%26.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%27.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%27.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%27.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%28.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%28.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%28.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%29.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%29.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%29.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%3.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%3.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%3.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%30.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%30.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%30.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%31.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%31.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%31.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%4.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%4.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%4.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%5.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%5.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%5.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%6.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%6.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%6.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%7.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%7.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%7.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%8.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%8.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%8.plru_out ),
+ .rst(rst)
+ );
+ plru_1 \maybe_plrus.plrus%9.plru (
+ .acc(req_hit_way),
+ .acc_en(\maybe_plrus.plrus%9.plru_acc_en ),
+ .clk(clk),
+ .lru(\maybe_plrus.plrus%9.plru_out ),
+ .rst(rst)
+ );
+ cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams%0.way (
+ .clk(clk),
+ .rd_addr(i_in[14:7]),
+ .rd_data(\rams%0.dout ),
+ .rd_en(1'h1),
+ .wr_addr(_0606_[121:114]),
+ .wr_data(wishbone_in[63:0]),
+ .wr_sel({ \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write , \rams%0.do_write })
+ );
+ cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29 \rams%1.way (
+ .clk(clk),
+ .rd_addr(i_in[14:7]),
+ .rd_data(\rams%1.dout ),
+ .rd_en(1'h1),
+ .wr_addr(_0606_[121:114]),
+ .wr_data(wishbone_in[63:0]),
+ .wr_sel({ \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write , \rams%1.do_write })
+ );
+ assign i_out = { _1075_, _0541_[64:1], _0606_[123], _0541_[65], _0541_[66] };
+ assign stall_out = _0538_;
+ assign wishbone_out = _0606_[107:1];
+endmodule
+
+module loadstore1(clk, rst, l_in, d_in, m_in, dc_stall, e_out, l_out, d_out, m_out, stall_out);
+ wire [63:0] _000_;
+ wire [221:0] _001_;
+ wire [2:0] _002_;
+ wire [113:0] _003_;
+ wire _004_;
+ wire [2:0] _005_;
+ wire [2:0] _006_;
+ wire [2:0] _007_;
+ wire [3:0] _008_;
+ wire [2:0] _009_;
+ wire [3:0] _010_;
+ wire [2:0] _011_;
+ wire [3:0] _012_;
+ wire [2:0] _013_;
+ wire [3:0] _014_;
+ wire [2:0] _015_;
+ wire [3:0] _016_;
+ wire [2:0] _017_;
+ wire [3:0] _018_;
+ wire [2:0] _019_;
+ wire [3:0] _020_;
+ wire [2:0] _021_;
+ wire [3:0] _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire [1:0] _033_;
+ wire _034_;
+ wire [1:0] _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire [7:0] _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire [1:0] _043_;
+ wire _044_;
+ wire [1:0] _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire [7:0] _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire [1:0] _053_;
+ wire _054_;
+ wire [1:0] _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire [7:0] _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire [1:0] _063_;
+ wire _064_;
+ wire [1:0] _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire [7:0] _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire [1:0] _073_;
+ wire _074_;
+ wire [1:0] _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire [7:0] _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire [1:0] _083_;
+ wire _084_;
+ wire [1:0] _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire [7:0] _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire [1:0] _093_;
+ wire _094_;
+ wire [1:0] _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire [7:0] _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire [1:0] _103_;
+ wire _104_;
+ wire [1:0] _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire [7:0] _109_;
+ wire [60:0] _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire [63:0] _119_;
+ wire [63:0] _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire [63:0] _126_;
+ wire [31:0] _127_;
+ wire [2:0] _128_;
+ wire [95:0] _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire [63:0] _140_;
+ wire [2:0] _141_;
+ wire [95:0] _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire [63:0] _146_;
+ wire _147_;
+ wire _148_;
+ wire [63:0] _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire [7:0] _161_;
+ wire [15:0] _162_;
+ wire [2:0] _163_;
+ wire [2:0] _164_;
+ wire [2:0] _165_;
+ wire [2:0] _166_;
+ wire [2:0] _167_;
+ wire [2:0] _168_;
+ wire [2:0] _169_;
+ wire [2:0] _170_;
+ wire [2:0] _171_;
+ wire [2:0] _172_;
+ wire [2:0] _173_;
+ wire [2:0] _174_;
+ wire [2:0] _175_;
+ wire [2:0] _176_;
+ wire [2:0] _177_;
+ wire [2:0] _178_;
+ wire [2:0] _179_;
+ wire [2:0] _180_;
+ wire _181_;
+ wire [2:0] _182_;
+ wire [2:0] _183_;
+ wire _184_;
+ wire [130:0] _185_;
+ wire [143:0] _186_;
+ wire [7:0] _187_;
+ wire _188_;
+ wire _189_;
+ wire [63:0] _190_;
+ wire _191_;
+ wire _192_;
+ wire [63:0] _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire _198_;
+ wire [63:0] _199_;
+ wire _200_;
+ wire [2:0] _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire [63:0] _208_;
+ wire _209_;
+ wire [2:0] _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire [2:0] _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire [63:0] _221_;
+ wire [2:0] _222_;
+ wire _223_;
+ wire _224_;
+ wire [63:0] _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire [63:0] _233_;
+ wire [3:0] _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire [7:0] _245_;
+ wire [63:0] _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire [2:0] _259_;
+ wire [2:0] _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire [2:0] _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire [1:0] _270_;
+ wire _271_;
+ wire _272_;
+ wire _273_;
+ wire [2:0] _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire [1:0] _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire [2:0] _284_;
+ wire _285_;
+ wire _286_;
+ wire _287_;
+ wire _288_;
+ wire [130:0] _289_;
+ wire [63:0] _290_;
+ wire [26:0] _291_;
+ wire [2:0] _292_;
+ wire _293_;
+ wire [112:0] _294_;
+ wire [7:0] _295_;
+ wire _296_;
+ wire _297_;
+ wire [63:0] _298_;
+ wire _299_;
+ wire _300_;
+ wire _301_;
+ wire _302_;
+ wire [63:0] _303_;
+ wire _304_;
+ wire _305_;
+ wire [1:0] _306_;
+ wire _307_;
+ wire _308_;
+ wire _309_;
+ wire _310_;
+ wire _311_;
+ wire _312_;
+ wire [69:0] _313_;
+ wire [69:0] _314_;
+ wire _315_;
+ wire _316_;
+ wire _317_;
+ wire _318_;
+ wire [31:0] _319_;
+ wire [95:0] _320_;
+ wire [7:0] _321_;
+ wire [7:0] _322_;
+ wire [7:0] _323_;
+ wire [7:0] _324_;
+ wire [7:0] _325_;
+ wire [7:0] _326_;
+ wire [7:0] _327_;
+ wire [7:0] _328_;
+ wire [7:0] _329_;
+ wire [7:0] _330_;
+ wire [7:0] _331_;
+ wire [7:0] _332_;
+ wire [7:0] _333_;
+ wire [7:0] _334_;
+ wire [7:0] _335_;
+ wire [7:0] _336_;
+ wire [7:0] _337_;
+ wire [7:0] _338_;
+ wire [7:0] _339_;
+ wire [7:0] _340_;
+ wire [7:0] _341_;
+ wire [7:0] _342_;
+ wire [7:0] _343_;
+ wire [7:0] _344_;
+ wire _345_;
+ wire _346_;
+ wire _347_;
+ wire _348_;
+ wire _349_;
+ wire _350_;
+ wire _351_;
+ wire _352_;
+ wire _353_;
+ wire _354_;
+ wire _355_;
+ wire _356_;
+ wire _357_;
+ wire _358_;
+ wire _359_;
+ wire [7:0] _360_;
+ wire [7:0] _361_;
+ wire [7:0] _362_;
+ wire [7:0] _363_;
+ wire [7:0] _364_;
+ wire [7:0] _365_;
+ wire [7:0] _366_;
+ wire [7:0] _367_;
+ wire _368_;
+ wire _369_;
+ wire _370_;
+ wire _371_;
+ wire _372_;
+ wire _373_;
+ wire _374_;
+ wire _375_;
+ wire _376_;
+ wire _377_;
+ wire _378_;
+ wire _379_;
+ wire _380_;
+ wire _381_;
+ wire _382_;
+ wire [7:0] _383_;
+ wire [7:0] _384_;
+ wire [7:0] _385_;
+ wire [7:0] _386_;
+ wire [7:0] _387_;
+ wire [7:0] _388_;
+ wire [7:0] _389_;
+ wire [7:0] _390_;
+ wire _391_;
+ wire _392_;
+ wire _393_;
+ wire _394_;
+ wire _395_;
+ wire _396_;
+ wire _397_;
+ wire _398_;
+ wire _399_;
+ wire _400_;
+ wire _401_;
+ wire _402_;
+ wire _403_;
+ wire _404_;
+ wire _405_;
+ wire [7:0] _406_;
+ wire [7:0] _407_;
+ wire [7:0] _408_;
+ wire [7:0] _409_;
+ wire [7:0] _410_;
+ wire [7:0] _411_;
+ wire [7:0] _412_;
+ wire [7:0] _413_;
+ wire _414_;
+ wire _415_;
+ wire _416_;
+ wire _417_;
+ wire _418_;
+ wire _419_;
+ wire _420_;
+ wire _421_;
+ wire _422_;
+ wire _423_;
+ wire _424_;
+ wire _425_;
+ wire _426_;
+ wire _427_;
+ wire _428_;
+ wire [7:0] _429_;
+ wire [7:0] _430_;
+ wire [7:0] _431_;
+ wire [7:0] _432_;
+ wire [7:0] _433_;
+ wire [7:0] _434_;
+ wire [7:0] _435_;
+ wire [7:0] _436_;
+ wire _437_;
+ wire _438_;
+ wire _439_;
+ wire _440_;
+ wire _441_;
+ wire _442_;
+ wire _443_;
+ wire _444_;
+ wire _445_;
+ wire _446_;
+ wire _447_;
+ wire _448_;
+ wire _449_;
+ wire _450_;
+ wire _451_;
+ wire [7:0] _452_;
+ wire [7:0] _453_;
+ wire [7:0] _454_;
+ wire [7:0] _455_;
+ wire [7:0] _456_;
+ wire [7:0] _457_;
+ wire [7:0] _458_;
+ wire [7:0] _459_;
+ wire _460_;
+ wire _461_;
+ wire _462_;
+ wire _463_;
+ wire _464_;
+ wire _465_;
+ wire _466_;
+ wire _467_;
+ wire _468_;
+ wire _469_;
+ wire _470_;
+ wire _471_;
+ wire _472_;
+ wire _473_;
+ wire _474_;
+ wire [7:0] _475_;
+ wire [7:0] _476_;
+ wire [7:0] _477_;
+ wire [7:0] _478_;
+ wire [7:0] _479_;
+ wire [7:0] _480_;
+ wire [7:0] _481_;
+ wire [7:0] _482_;
+ wire _483_;
+ wire _484_;
+ wire _485_;
+ wire _486_;
+ wire _487_;
+ wire _488_;
+ wire _489_;
+ wire _490_;
+ wire _491_;
+ wire _492_;
+ wire _493_;
+ wire _494_;
+ wire _495_;
+ wire _496_;
+ wire _497_;
+ wire [7:0] _498_;
+ wire [7:0] _499_;
+ wire [7:0] _500_;
+ wire [7:0] _501_;
+ wire [7:0] _502_;
+ wire [7:0] _503_;
+ wire [7:0] _504_;
+ wire [7:0] _505_;
+ wire _506_;
+ wire _507_;
+ wire _508_;
+ wire _509_;
+ wire _510_;
+ wire _511_;
+ wire _512_;
+ wire _513_;
+ wire _514_;
+ wire _515_;
+ wire _516_;
+ wire _517_;
+ wire _518_;
+ wire _519_;
+ wire _520_;
+ wire [7:0] _521_;
+ wire [7:0] _522_;
+ wire [7:0] _523_;
+ wire [7:0] _524_;
+ wire [7:0] _525_;
+ wire [7:0] _526_;
+ wire [7:0] _527_;
+ wire [7:0] _528_;
+ wire [7:0] _529_;
+ wire [7:0] _530_;
+ wire [7:0] _531_;
+ wire [7:0] _532_;
+ wire [7:0] _533_;
+ wire [7:0] _534_;
+ wire [7:0] _535_;
+ wire [7:0] _536_;
+ wire [7:0] _537_;
+ wire [7:0] _538_;
+ wire [7:0] _539_;
+ wire [7:0] _540_;
+ wire [7:0] _541_;
+ wire [7:0] _542_;
+ wire [7:0] _543_;
+ wire [7:0] _544_;
+ wire [7:0] _545_;
+ wire [7:0] _546_;
+ wire [7:0] _547_;
+ wire [7:0] _548_;
+ wire [7:0] _549_;
+ wire [7:0] _550_;
+ wire [7:0] _551_;
+ wire [7:0] _552_;
+ wire [7:0] _553_;
+ wire [7:0] _554_;
+ wire [7:0] _555_;
+ wire [7:0] _556_;
+ wire [7:0] _557_;
+ wire [7:0] _558_;
+ wire [7:0] _559_;
+ wire [7:0] _560_;
+ input clk;
+ input [67:0] d_in;
+ output [142:0] d_out;
+ input dc_stall;
+ output [6:0] e_out;
+ input [321:0] l_in;
+ output [77:0] l_out;
+ wire [63:0] lsu_sum;
+ input [69:0] m_in;
+ output [144:0] m_out;
+ reg [338:0] r;
+ input rst;
+ output stall_out;
+ assign _529_ = _008_[0] ? d_in[16:9] : d_in[8:1];
+ assign _530_ = _008_[0] ? d_in[48:41] : d_in[40:33];
+ assign _531_ = _010_[0] ? d_in[16:9] : d_in[8:1];
+ assign _532_ = _010_[0] ? d_in[48:41] : d_in[40:33];
+ assign _533_ = _012_[0] ? d_in[16:9] : d_in[8:1];
+ assign _534_ = _012_[0] ? d_in[48:41] : d_in[40:33];
+ assign _535_ = _014_[0] ? d_in[16:9] : d_in[8:1];
+ assign _536_ = _014_[0] ? d_in[48:41] : d_in[40:33];
+ assign _537_ = _016_[0] ? d_in[16:9] : d_in[8:1];
+ assign _538_ = _016_[0] ? d_in[48:41] : d_in[40:33];
+ assign _539_ = _018_[0] ? d_in[16:9] : d_in[8:1];
+ assign _540_ = _018_[0] ? d_in[48:41] : d_in[40:33];
+ assign _541_ = _020_[0] ? d_in[16:9] : d_in[8:1];
+ assign _542_ = _020_[0] ? d_in[48:41] : d_in[40:33];
+ assign _543_ = _022_[0] ? d_in[16:9] : d_in[8:1];
+ assign _544_ = _022_[0] ? d_in[48:41] : d_in[40:33];
+ assign _545_ = _008_[0] ? d_in[32:25] : d_in[24:17];
+ assign _546_ = _008_[0] ? d_in[64:57] : d_in[56:49];
+ assign _547_ = _010_[0] ? d_in[32:25] : d_in[24:17];
+ assign _548_ = _010_[0] ? d_in[64:57] : d_in[56:49];
+ assign _549_ = _012_[0] ? d_in[32:25] : d_in[24:17];
+ assign _550_ = _012_[0] ? d_in[64:57] : d_in[56:49];
+ assign _551_ = _014_[0] ? d_in[32:25] : d_in[24:17];
+ assign _552_ = _014_[0] ? d_in[64:57] : d_in[56:49];
+ assign _553_ = _016_[0] ? d_in[32:25] : d_in[24:17];
+ assign _554_ = _016_[0] ? d_in[64:57] : d_in[56:49];
+ assign _555_ = _018_[0] ? d_in[32:25] : d_in[24:17];
+ assign _556_ = _018_[0] ? d_in[64:57] : d_in[56:49];
+ assign _557_ = _020_[0] ? d_in[32:25] : d_in[24:17];
+ assign _558_ = _020_[0] ? d_in[64:57] : d_in[56:49];
+ assign _559_ = _022_[0] ? d_in[32:25] : d_in[24:17];
+ assign _560_ = _022_[0] ? d_in[64:57] : d_in[56:49];
+ assign _321_ = _008_[1] ? _545_ : _529_;
+ assign _322_ = _008_[1] ? _546_ : _530_;
+ assign _324_ = _010_[1] ? _547_ : _531_;
+ assign _325_ = _010_[1] ? _548_ : _532_;
+ assign _327_ = _012_[1] ? _549_ : _533_;
+ assign _328_ = _012_[1] ? _550_ : _534_;
+ assign _330_ = _014_[1] ? _551_ : _535_;
+ assign _331_ = _014_[1] ? _552_ : _536_;
+ assign _333_ = _016_[1] ? _553_ : _537_;
+ assign _334_ = _016_[1] ? _554_ : _538_;
+ assign _336_ = _018_[1] ? _555_ : _539_;
+ assign _337_ = _018_[1] ? _556_ : _540_;
+ assign _339_ = _020_[1] ? _557_ : _541_;
+ assign _340_ = _020_[1] ? _558_ : _542_;
+ assign _342_ = _022_[1] ? _559_ : _543_;
+ assign _343_ = _022_[1] ? _560_ : _544_;
+ assign _000_ = l_in[166:103] + l_in[230:167];
+ assign lsu_sum = l_in[0] ? _000_ : 64'h0000000000000000;
+ assign _001_ = rst ? r[221:0] : { _291_, _290_, _289_ };
+ assign _002_ = rst ? 3'h0 : _292_;
+ assign _003_ = rst ? r[338:225] : { _294_[112], _320_, _294_[15:0], _293_ };
+ always @(posedge clk)
+ r <= { _003_, _002_, _001_ };
+ assign _004_ = | r[241:234];
+ assign _005_ = r[202:200] - 3'h1;
+ assign _006_ = r[204] ? _005_ : 3'h0;
+ assign _007_ = 3'h0 ^ _006_;
+ assign _008_ = { 1'h0, _007_ } + { 1'h0, r[5:3] };
+ assign _009_ = 3'h1 ^ _006_;
+ assign _010_ = { 1'h0, _009_ } + { 1'h0, r[5:3] };
+ assign _011_ = 3'h2 ^ _006_;
+ assign _012_ = { 1'h0, _011_ } + { 1'h0, r[5:3] };
+ assign _013_ = 3'h3 ^ _006_;
+ assign _014_ = { 1'h0, _013_ } + { 1'h0, r[5:3] };
+ assign _015_ = 3'h4 ^ _006_;
+ assign _016_ = { 1'h0, _015_ } + { 1'h0, r[5:3] };
+ assign _017_ = 3'h5 ^ _006_;
+ assign _018_ = { 1'h0, _017_ } + { 1'h0, r[5:3] };
+ assign _019_ = 3'h6 ^ _006_;
+ assign _020_ = { 1'h0, _019_ } + { 1'h0, r[5:3] };
+ assign _021_ = 3'h7 ^ _006_;
+ assign _022_ = { 1'h0, _021_ } + { 1'h0, r[5:3] };
+ assign _023_ = r[203] & _344_[7];
+ assign _024_ = r[202] & _332_[7];
+ assign _025_ = _023_ | _024_;
+ assign _026_ = r[201] & _326_[7];
+ assign _027_ = _025_ | _026_;
+ assign _028_ = r[200] & _323_[7];
+ assign _029_ = _027_ | _028_;
+ assign _030_ = $signed(32'd0) < $signed({ 28'h0000000, r[203:200] });
+ assign _031_ = ~ _008_[3];
+ assign _032_ = ~ _008_[3];
+ assign _033_ = _004_ ? { 1'h1, _031_ } : { _032_, 1'h0 };
+ assign _034_ = _029_ & r[205];
+ assign _035_ = _030_ ? _033_ : { 1'h0, _034_ };
+ assign _036_ = _035_ == 2'h3;
+ assign _037_ = _035_ == 2'h2;
+ assign _038_ = _035_ == 2'h1;
+ function [7:0] \8364 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8364 = b[7:0];
+ 3'b?1?:
+ \8364 = b[15:8];
+ 3'b1??:
+ \8364 = b[23:16];
+ default:
+ \8364 = a;
+ endcase
+ endfunction
+ assign _039_ = \8364 (8'h00, { 8'hff, _323_, r[138:131] }, { _038_, _037_, _036_ });
+ assign _040_ = $signed(32'd1) < $signed({ 28'h0000000, r[203:200] });
+ assign _041_ = ~ _010_[3];
+ assign _042_ = ~ _010_[3];
+ assign _043_ = _004_ ? { 1'h1, _041_ } : { _042_, 1'h0 };
+ assign _044_ = _029_ & r[205];
+ assign _045_ = _040_ ? _043_ : { 1'h0, _044_ };
+ assign _046_ = _045_ == 2'h3;
+ assign _047_ = _045_ == 2'h2;
+ assign _048_ = _045_ == 2'h1;
+ function [7:0] \8401 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8401 = b[7:0];
+ 3'b?1?:
+ \8401 = b[15:8];
+ 3'b1??:
+ \8401 = b[23:16];
+ default:
+ \8401 = a;
+ endcase
+ endfunction
+ assign _049_ = \8401 (8'h00, { 8'hff, _326_, r[146:139] }, { _048_, _047_, _046_ });
+ assign _050_ = $signed(32'd2) < $signed({ 28'h0000000, r[203:200] });
+ assign _051_ = ~ _012_[3];
+ assign _052_ = ~ _012_[3];
+ assign _053_ = _004_ ? { 1'h1, _051_ } : { _052_, 1'h0 };
+ assign _054_ = _029_ & r[205];
+ assign _055_ = _050_ ? _053_ : { 1'h0, _054_ };
+ assign _056_ = _055_ == 2'h3;
+ assign _057_ = _055_ == 2'h2;
+ assign _058_ = _055_ == 2'h1;
+ function [7:0] \8438 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8438 = b[7:0];
+ 3'b?1?:
+ \8438 = b[15:8];
+ 3'b1??:
+ \8438 = b[23:16];
+ default:
+ \8438 = a;
+ endcase
+ endfunction
+ assign _059_ = \8438 (8'h00, { 8'hff, _329_, r[154:147] }, { _058_, _057_, _056_ });
+ assign _060_ = $signed(32'd3) < $signed({ 28'h0000000, r[203:200] });
+ assign _061_ = ~ _014_[3];
+ assign _062_ = ~ _014_[3];
+ assign _063_ = _004_ ? { 1'h1, _061_ } : { _062_, 1'h0 };
+ assign _064_ = _029_ & r[205];
+ assign _065_ = _060_ ? _063_ : { 1'h0, _064_ };
+ assign _066_ = _065_ == 2'h3;
+ assign _067_ = _065_ == 2'h2;
+ assign _068_ = _065_ == 2'h1;
+ function [7:0] \8475 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8475 = b[7:0];
+ 3'b?1?:
+ \8475 = b[15:8];
+ 3'b1??:
+ \8475 = b[23:16];
+ default:
+ \8475 = a;
+ endcase
+ endfunction
+ assign _069_ = \8475 (8'h00, { 8'hff, _332_, r[162:155] }, { _068_, _067_, _066_ });
+ assign _070_ = $signed(32'd4) < $signed({ 28'h0000000, r[203:200] });
+ assign _071_ = ~ _016_[3];
+ assign _072_ = ~ _016_[3];
+ assign _073_ = _004_ ? { 1'h1, _071_ } : { _072_, 1'h0 };
+ assign _074_ = _029_ & r[205];
+ assign _075_ = _070_ ? _073_ : { 1'h0, _074_ };
+ assign _076_ = _075_ == 2'h3;
+ assign _077_ = _075_ == 2'h2;
+ assign _078_ = _075_ == 2'h1;
+ function [7:0] \8512 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8512 = b[7:0];
+ 3'b?1?:
+ \8512 = b[15:8];
+ 3'b1??:
+ \8512 = b[23:16];
+ default:
+ \8512 = a;
+ endcase
+ endfunction
+ assign _079_ = \8512 (8'h00, { 8'hff, _335_, r[170:163] }, { _078_, _077_, _076_ });
+ assign _080_ = $signed(32'd5) < $signed({ 28'h0000000, r[203:200] });
+ assign _081_ = ~ _018_[3];
+ assign _082_ = ~ _018_[3];
+ assign _083_ = _004_ ? { 1'h1, _081_ } : { _082_, 1'h0 };
+ assign _084_ = _029_ & r[205];
+ assign _085_ = _080_ ? _083_ : { 1'h0, _084_ };
+ assign _086_ = _085_ == 2'h3;
+ assign _087_ = _085_ == 2'h2;
+ assign _088_ = _085_ == 2'h1;
+ function [7:0] \8549 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8549 = b[7:0];
+ 3'b?1?:
+ \8549 = b[15:8];
+ 3'b1??:
+ \8549 = b[23:16];
+ default:
+ \8549 = a;
+ endcase
+ endfunction
+ assign _089_ = \8549 (8'h00, { 8'hff, _338_, r[178:171] }, { _088_, _087_, _086_ });
+ assign _090_ = $signed(32'd6) < $signed({ 28'h0000000, r[203:200] });
+ assign _091_ = ~ _020_[3];
+ assign _092_ = ~ _020_[3];
+ assign _093_ = _004_ ? { 1'h1, _091_ } : { _092_, 1'h0 };
+ assign _094_ = _029_ & r[205];
+ assign _095_ = _090_ ? _093_ : { 1'h0, _094_ };
+ assign _096_ = _095_ == 2'h3;
+ assign _097_ = _095_ == 2'h2;
+ assign _098_ = _095_ == 2'h1;
+ function [7:0] \8586 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8586 = b[7:0];
+ 3'b?1?:
+ \8586 = b[15:8];
+ 3'b1??:
+ \8586 = b[23:16];
+ default:
+ \8586 = a;
+ endcase
+ endfunction
+ assign _099_ = \8586 (8'h00, { 8'hff, _341_, r[186:179] }, { _098_, _097_, _096_ });
+ assign _100_ = $signed(32'd7) < $signed({ 28'h0000000, r[203:200] });
+ assign _101_ = ~ _022_[3];
+ assign _102_ = ~ _022_[3];
+ assign _103_ = _004_ ? { 1'h1, _101_ } : { _102_, 1'h0 };
+ assign _104_ = _029_ & r[205];
+ assign _105_ = _100_ ? _103_ : { 1'h0, _104_ };
+ assign _106_ = _105_ == 2'h3;
+ assign _107_ = _105_ == 2'h2;
+ assign _108_ = _105_ == 2'h1;
+ function [7:0] \8622 ;
+ input [7:0] a;
+ input [23:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \8622 = b[7:0];
+ 3'b?1?:
+ \8622 = b[15:8];
+ 3'b1??:
+ \8622 = b[23:16];
+ default:
+ \8622 = a;
+ endcase
+ endfunction
+ assign _109_ = \8622 (8'h00, { 8'hff, _344_, r[194:187] }, { _108_, _107_, _106_ });
+ assign _110_ = r[66:6] + 61'h0000000000000001;
+ assign _111_ = l_in[6:1] == 6'h1e;
+ assign _112_ = l_in[6:1] == 6'h1d;
+ assign _113_ = l_in[6:1] == 6'h14;
+ assign _114_ = l_in[6:1] == 6'h3a;
+ assign _115_ = ~ l_in[86];
+ assign _116_ = ~ l_in[82];
+ assign _117_ = _115_ & _116_;
+ assign _118_ = ~ l_in[87];
+ assign _119_ = _118_ ? { 32'h00000000, r[337:306] } : r[305:242];
+ assign _120_ = _117_ ? _119_ : m_in[69:6];
+ assign _121_ = l_in[6:1] == 6'h26;
+ assign _122_ = ~ l_in[86];
+ assign _123_ = ~ l_in[82];
+ assign _124_ = _122_ & _123_;
+ assign _125_ = ~ l_in[87];
+ assign _126_ = _125_ ? r[305:242] : l_in[294:231];
+ assign _127_ = _125_ ? l_in[262:231] : r[337:306];
+ assign _128_ = _124_ ? r[224:222] : 3'h5;
+ assign _129_ = _124_ ? { _127_, _126_ } : r[337:242];
+ assign _130_ = _124_ ? 1'h0 : 1'h1;
+ assign _131_ = _124_ ? 1'h1 : 1'h0;
+ assign _132_ = _124_ ? 1'h0 : 1'h1;
+ assign _133_ = l_in[6:1] == 6'h2a;
+ assign _134_ = l_in[6:1] == 6'h3d;
+ assign _135_ = ~ _312_;
+ assign _136_ = _135_ | 1'h0;
+ function [0:0] \8706 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8706 = b[0:0];
+ 7'b?????1?:
+ \8706 = b[1:1];
+ 7'b????1??:
+ \8706 = b[2:2];
+ 7'b???1???:
+ \8706 = b[3:3];
+ 7'b??1????:
+ \8706 = b[4:4];
+ 7'b?1?????:
+ \8706 = b[5:5];
+ 7'b1??????:
+ \8706 = b[6:6];
+ default:
+ \8706 = a;
+ endcase
+ endfunction
+ assign _137_ = \8706 (1'h0, 7'h02, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8707 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8707 = b[0:0];
+ 7'b?????1?:
+ \8707 = b[1:1];
+ 7'b????1??:
+ \8707 = b[2:2];
+ 7'b???1???:
+ \8707 = b[3:3];
+ 7'b??1????:
+ \8707 = b[4:4];
+ 7'b?1?????:
+ \8707 = b[5:5];
+ 7'b1??????:
+ \8707 = b[6:6];
+ default:
+ \8707 = a;
+ endcase
+ endfunction
+ assign _138_ = \8707 (1'h0, 7'h08, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8708 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8708 = b[0:0];
+ 7'b?????1?:
+ \8708 = b[1:1];
+ 7'b????1??:
+ \8708 = b[2:2];
+ 7'b???1???:
+ \8708 = b[3:3];
+ 7'b??1????:
+ \8708 = b[4:4];
+ 7'b?1?????:
+ \8708 = b[5:5];
+ 7'b1??????:
+ \8708 = b[6:6];
+ default:
+ \8708 = a;
+ endcase
+ endfunction
+ assign _139_ = \8708 (1'h0, 7'h04, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [63:0] \8709 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8709 = b[63:0];
+ 7'b?????1?:
+ \8709 = b[127:64];
+ 7'b????1??:
+ \8709 = b[191:128];
+ 7'b???1???:
+ \8709 = b[255:192];
+ 7'b??1????:
+ \8709 = b[319:256];
+ 7'b?1?????:
+ \8709 = b[383:320];
+ 7'b1??????:
+ \8709 = b[447:384];
+ default:
+ \8709 = a;
+ endcase
+ endfunction
+ assign _140_ = \8709 (lsu_sum, { l_in[70:7], lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [2:0] \8711 ;
+ input [2:0] a;
+ input [20:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8711 = b[2:0];
+ 7'b?????1?:
+ \8711 = b[5:3];
+ 7'b????1??:
+ \8711 = b[8:6];
+ 7'b???1???:
+ \8711 = b[11:9];
+ 7'b??1????:
+ \8711 = b[14:12];
+ 7'b?1?????:
+ \8711 = b[17:15];
+ 7'b1??????:
+ \8711 = b[20:18];
+ default:
+ \8711 = a;
+ endcase
+ endfunction
+ assign _141_ = \8711 (r[224:222], { 3'h4, _128_, r[224:222], 3'h5, r[224:222], r[224:222], r[224:222] }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [95:0] \8713 ;
+ input [95:0] a;
+ input [671:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8713 = b[95:0];
+ 7'b?????1?:
+ \8713 = b[191:96];
+ 7'b????1??:
+ \8713 = b[287:192];
+ 7'b???1???:
+ \8713 = b[383:288];
+ 7'b??1????:
+ \8713 = b[479:384];
+ 7'b?1?????:
+ \8713 = b[575:480];
+ 7'b1??????:
+ \8713 = b[671:576];
+ default:
+ \8713 = a;
+ endcase
+ endfunction
+ assign _142_ = \8713 (r[337:242], { r[337:242], _129_, r[337:242], r[337:242], r[337:242], r[337:242], r[337:242] }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8714 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8714 = b[0:0];
+ 7'b?????1?:
+ \8714 = b[1:1];
+ 7'b????1??:
+ \8714 = b[2:2];
+ 7'b???1???:
+ \8714 = b[3:3];
+ 7'b??1????:
+ \8714 = b[4:4];
+ 7'b?1?????:
+ \8714 = b[5:5];
+ 7'b1??????:
+ \8714 = b[6:6];
+ default:
+ \8714 = a;
+ endcase
+ endfunction
+ assign _143_ = \8714 (1'h0, 7'h40, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8719 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8719 = b[0:0];
+ 7'b?????1?:
+ \8719 = b[1:1];
+ 7'b????1??:
+ \8719 = b[2:2];
+ 7'b???1???:
+ \8719 = b[3:3];
+ 7'b??1????:
+ \8719 = b[4:4];
+ 7'b?1?????:
+ \8719 = b[5:5];
+ 7'b1??????:
+ \8719 = b[6:6];
+ default:
+ \8719 = a;
+ endcase
+ endfunction
+ assign _144_ = \8719 (1'h0, 7'h07, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8723 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8723 = b[0:0];
+ 7'b?????1?:
+ \8723 = b[1:1];
+ 7'b????1??:
+ \8723 = b[2:2];
+ 7'b???1???:
+ \8723 = b[3:3];
+ 7'b??1????:
+ \8723 = b[4:4];
+ 7'b?1?????:
+ \8723 = b[5:5];
+ 7'b1??????:
+ \8723 = b[6:6];
+ default:
+ \8723 = a;
+ endcase
+ endfunction
+ assign _145_ = \8723 (1'h0, { 1'h1, _130_, 5'h08 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [63:0] \8724 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8724 = b[63:0];
+ 7'b?????1?:
+ \8724 = b[127:64];
+ 7'b????1??:
+ \8724 = b[191:128];
+ 7'b???1???:
+ \8724 = b[255:192];
+ 7'b??1????:
+ \8724 = b[319:256];
+ 7'b?1?????:
+ \8724 = b[383:320];
+ 7'b1??????:
+ \8724 = b[447:384];
+ default:
+ \8724 = a;
+ endcase
+ endfunction
+ assign _146_ = \8724 (lsu_sum, { l_in[70:7], lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum, lsu_sum }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8727 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8727 = b[0:0];
+ 7'b?????1?:
+ \8727 = b[1:1];
+ 7'b????1??:
+ \8727 = b[2:2];
+ 7'b???1???:
+ \8727 = b[3:3];
+ 7'b??1????:
+ \8727 = b[4:4];
+ 7'b?1?????:
+ \8727 = b[5:5];
+ 7'b1??????:
+ \8727 = b[6:6];
+ default:
+ \8727 = a;
+ endcase
+ endfunction
+ assign _147_ = \8727 (1'h0, { 1'h0, _131_, 5'h10 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8730 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8730 = b[0:0];
+ 7'b?????1?:
+ \8730 = b[1:1];
+ 7'b????1??:
+ \8730 = b[2:2];
+ 7'b???1???:
+ \8730 = b[3:3];
+ 7'b??1????:
+ \8730 = b[4:4];
+ 7'b?1?????:
+ \8730 = b[5:5];
+ 7'b1??????:
+ \8730 = b[6:6];
+ default:
+ \8730 = a;
+ endcase
+ endfunction
+ assign _148_ = \8730 (1'h0, 7'h10, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [63:0] \8732 ;
+ input [63:0] a;
+ input [447:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8732 = b[63:0];
+ 7'b?????1?:
+ \8732 = b[127:64];
+ 7'b????1??:
+ \8732 = b[191:128];
+ 7'b???1???:
+ \8732 = b[255:192];
+ 7'b??1????:
+ \8732 = b[319:256];
+ 7'b?1?????:
+ \8732 = b[383:320];
+ 7'b1??????:
+ \8732 = b[447:384];
+ default:
+ \8732 = a;
+ endcase
+ endfunction
+ assign _149_ = \8732 (64'h0000000000000000, { 128'h00000000000000000000000000000000, _120_, 256'h0000000000000000000000000000000000000000000000000000000000000000 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8736 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8736 = b[0:0];
+ 7'b?????1?:
+ \8736 = b[1:1];
+ 7'b????1??:
+ \8736 = b[2:2];
+ 7'b???1???:
+ \8736 = b[3:3];
+ 7'b??1????:
+ \8736 = b[4:4];
+ 7'b?1?????:
+ \8736 = b[5:5];
+ 7'b1??????:
+ \8736 = b[6:6];
+ default:
+ \8736 = a;
+ endcase
+ endfunction
+ assign _150_ = \8736 (1'h0, 7'h48, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8738 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8738 = b[0:0];
+ 7'b?????1?:
+ \8738 = b[1:1];
+ 7'b????1??:
+ \8738 = b[2:2];
+ 7'b???1???:
+ \8738 = b[3:3];
+ 7'b??1????:
+ \8738 = b[4:4];
+ 7'b?1?????:
+ \8738 = b[5:5];
+ 7'b1??????:
+ \8738 = b[6:6];
+ default:
+ \8738 = a;
+ endcase
+ endfunction
+ assign _151_ = \8738 (1'h0, { 1'h0, _132_, 5'h00 }, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ function [0:0] \8741 ;
+ input [0:0] a;
+ input [6:0] b;
+ input [6:0] s;
+ (* parallel_case *)
+ casez (s)
+ 7'b??????1:
+ \8741 = b[0:0];
+ 7'b?????1?:
+ \8741 = b[1:1];
+ 7'b????1??:
+ \8741 = b[2:2];
+ 7'b???1???:
+ \8741 = b[3:3];
+ 7'b??1????:
+ \8741 = b[4:4];
+ 7'b?1?????:
+ \8741 = b[5:5];
+ 7'b1??????:
+ \8741 = b[6:6];
+ default:
+ \8741 = a;
+ endcase
+ endfunction
+ assign _152_ = \8741 (1'h1, 7'h00, { _134_, _133_, _121_, _114_, _113_, _112_, _111_ });
+ assign _153_ = lsu_sum[31:28] == 4'hc;
+ assign _154_ = ~ l_in[320];
+ assign _155_ = _153_ & _154_;
+ assign _156_ = _155_ ? 1'h1 : l_in[304];
+ assign _157_ = l_in[303:300] == 4'h1;
+ assign _158_ = l_in[303:300] == 4'h2;
+ assign _159_ = l_in[303:300] == 4'h4;
+ assign _160_ = l_in[303:300] == 4'h8;
+ function [7:0] \8792 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \8792 = b[7:0];
+ 4'b??1?:
+ \8792 = b[15:8];
+ 4'b?1??:
+ \8792 = b[23:16];
+ 4'b1???:
+ \8792 = b[31:24];
+ default:
+ \8792 = a;
+ endcase
+ endfunction
+ assign _161_ = \8792 (8'h00, 32'd4279173889, { _160_, _159_, _158_, _157_ });
+ assign _162_ = { 8'h00, _161_ } << { 28'h0000000, _140_[2:0] };
+ assign _163_ = l_in[302:300] - 3'h1;
+ assign _164_ = l_in[305] ? _163_ : 3'h0;
+ assign _165_ = 3'h0 ^ _164_;
+ assign _166_ = _165_ + lsu_sum[2:0];
+ assign _167_ = 3'h1 ^ _164_;
+ assign _168_ = _167_ + lsu_sum[2:0];
+ assign _169_ = 3'h2 ^ _164_;
+ assign _170_ = _169_ + lsu_sum[2:0];
+ assign _171_ = 3'h3 ^ _164_;
+ assign _172_ = _171_ + lsu_sum[2:0];
+ assign _173_ = 3'h4 ^ _164_;
+ assign _174_ = _173_ + lsu_sum[2:0];
+ assign _175_ = 3'h5 ^ _164_;
+ assign _176_ = _175_ + lsu_sum[2:0];
+ assign _177_ = 3'h6 ^ _164_;
+ assign _178_ = _177_ + lsu_sum[2:0];
+ assign _179_ = 3'h7 ^ _164_;
+ assign _180_ = _179_ + lsu_sum[2:0];
+ assign _181_ = _162_[15:8] == 8'h00;
+ assign _182_ = _181_ ? 3'h2 : 3'h1;
+ assign _183_ = _144_ ? _182_ : _141_;
+ assign _184_ = _144_ ? 1'h1 : _145_;
+ assign _185_ = l_in[0] ? { _528_, _527_, _526_, _525_, _524_, _523_, _522_, _521_, _140_, _139_, _138_, _137_ } : r[130:0];
+ assign _186_ = l_in[0] ? { _143_, _142_, _162_, 1'h0, _183_, l_in[321:320], _156_, l_in[319:305], l_in[303:295] } : r[338:195];
+ assign _187_ = l_in[0] ? _162_[7:0] : 8'h00;
+ assign _188_ = l_in[0] ? _144_ : 1'h0;
+ assign _189_ = l_in[0] ? _184_ : 1'h0;
+ assign _190_ = l_in[0] ? _146_ : lsu_sum;
+ assign _191_ = l_in[0] ? _147_ : 1'h0;
+ assign _192_ = l_in[0] ? _148_ : 1'h0;
+ assign _193_ = l_in[0] ? _149_ : 64'h0000000000000000;
+ assign _194_ = l_in[0] ? _150_ : 1'h0;
+ assign _195_ = l_in[0] ? _151_ : 1'h0;
+ assign _196_ = l_in[0] ? _152_ : 1'h0;
+ assign _197_ = r[224:222] == 3'h0;
+ assign _198_ = r[224:222] == 3'h1;
+ assign _199_ = r[225] ? { _110_, 3'h0 } : r[66:3];
+ assign _200_ = ~ r[0];
+ assign _201_ = d_in[67] ? 3'h0 : 3'h4;
+ assign _202_ = d_in[67] ? 1'h1 : 1'h0;
+ assign _203_ = d_in[67] ? 1'h0 : 1'h1;
+ assign _204_ = d_in[67] ? _200_ : 1'h0;
+ assign _205_ = d_in[67] ? d_in[67] : 1'h0;
+ assign _206_ = ~ r[225];
+ assign _207_ = _004_ & _206_;
+ assign _208_ = _214_ ? { _344_, _341_, _338_, _335_, _332_, _329_, _326_, _323_ } : r[194:131];
+ assign _209_ = r[0] & r[206];
+ assign _210_ = _209_ ? 3'h3 : 3'h0;
+ assign _211_ = _209_ ? 1'h1 : 1'h0;
+ assign _212_ = _209_ ? 1'h0 : r[206];
+ assign _213_ = _209_ ? 1'h0 : 1'h1;
+ assign _214_ = _207_ & r[0];
+ assign _215_ = _207_ ? r[224:222] : _210_;
+ assign _216_ = _207_ ? 1'h1 : r[225];
+ assign _217_ = _207_ ? 1'h1 : _211_;
+ assign _218_ = _207_ ? 1'h0 : r[0];
+ assign _219_ = _207_ ? 1'h0 : _212_;
+ assign _220_ = _207_ ? 1'h0 : _213_;
+ assign _221_ = d_in[66] ? r[194:131] : _208_;
+ assign _222_ = d_in[66] ? _201_ : _215_;
+ assign _223_ = d_in[66] ? r[225] : _216_;
+ assign _224_ = d_in[66] ? 1'h1 : _217_;
+ assign _225_ = _236_ ? _199_ : lsu_sum;
+ assign _226_ = d_in[66] ? 1'h0 : _218_;
+ assign _227_ = d_in[66] ? 1'h0 : _219_;
+ assign _228_ = d_in[66] ? 1'h0 : _220_;
+ assign _229_ = d_in[66] ? _202_ : 1'h0;
+ assign _230_ = d_in[66] ? _203_ : 1'h0;
+ assign _231_ = d_in[66] ? _204_ : 1'h0;
+ assign _232_ = d_in[66] ? _205_ : 1'h0;
+ assign _233_ = d_in[0] ? _221_ : r[194:131];
+ assign _234_ = d_in[0] ? { _223_, _222_ } : r[225:222];
+ assign _235_ = d_in[0] ? _224_ : 1'h1;
+ assign _236_ = d_in[0] & d_in[66];
+ assign _237_ = d_in[0] ? _226_ : 1'h0;
+ assign _238_ = d_in[0] ? _227_ : 1'h0;
+ assign _239_ = d_in[0] ? _228_ : 1'h0;
+ assign _240_ = d_in[0] ? _229_ : 1'h0;
+ assign _241_ = d_in[0] ? _230_ : 1'h0;
+ assign _242_ = d_in[0] ? _231_ : 1'h0;
+ assign _243_ = d_in[0] ? _232_ : 1'h0;
+ assign _244_ = r[224:222] == 3'h2;
+ assign _245_ = r[225] ? r[241:234] : r[233:226];
+ assign _246_ = r[225] ? { _110_, 3'h0 } : r[66:3];
+ assign _247_ = ~ m_in[1];
+ assign _248_ = ~ m_in[4];
+ assign _249_ = _247_ & _248_;
+ assign _250_ = ~ m_in[5];
+ assign _251_ = _249_ & _250_;
+ assign _252_ = ~ m_in[2];
+ assign _253_ = _251_ & _252_;
+ assign _254_ = ~ m_in[3];
+ assign _255_ = _253_ & _254_;
+ assign _256_ = ~ r[338];
+ assign _257_ = ~ r[225];
+ assign _258_ = _004_ & _257_;
+ assign _259_ = _258_ ? 3'h1 : 3'h2;
+ assign _260_ = _256_ ? _259_ : 3'h0;
+ assign _261_ = _256_ ? 1'h1 : 1'h0;
+ assign _262_ = _256_ ? 1'h1 : 1'h0;
+ assign _263_ = _256_ ? 1'h0 : 1'h1;
+ assign _264_ = ~ r[0];
+ assign _265_ = _255_ ? _260_ : 3'h0;
+ assign _266_ = _255_ ? _261_ : 1'h0;
+ assign _267_ = _255_ ? _262_ : 1'h1;
+ assign _268_ = _255_ ? _263_ : 1'h0;
+ assign _269_ = _255_ ? 1'h0 : 1'h1;
+ assign _270_ = _255_ ? 2'h0 : { m_in[2], m_in[5] };
+ assign _271_ = _255_ ? 1'h0 : _264_;
+ assign _272_ = _255_ ? 1'h0 : m_in[4];
+ assign _273_ = _255_ ? 1'h0 : m_in[1];
+ assign _274_ = m_in[0] ? _265_ : r[224:222];
+ assign _275_ = m_in[0] ? _266_ : 1'h0;
+ assign _276_ = m_in[0] ? _267_ : 1'h1;
+ assign _277_ = m_in[0] ? _268_ : 1'h0;
+ assign _278_ = m_in[0] ? _269_ : 1'h0;
+ assign _279_ = m_in[0] ? _270_ : 2'h0;
+ assign _280_ = m_in[0] ? _271_ : 1'h0;
+ assign _281_ = m_in[0] ? _272_ : 1'h0;
+ assign _282_ = m_in[0] ? _273_ : 1'h0;
+ assign _283_ = r[224:222] == 3'h4;
+ assign _284_ = m_in[0] ? 3'h0 : r[224:222];
+ assign _285_ = m_in[0] ? 1'h0 : 1'h1;
+ assign _286_ = m_in[0] ? 1'h1 : 1'h0;
+ assign _287_ = r[224:222] == 3'h5;
+ assign _288_ = r[224:222] == 3'h3;
+ function [130:0] \9166 ;
+ input [130:0] a;
+ input [785:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9166 = b[130:0];
+ 6'b????1?:
+ \9166 = b[261:131];
+ 6'b???1??:
+ \9166 = b[392:262];
+ 6'b??1???:
+ \9166 = b[523:393];
+ 6'b?1????:
+ \9166 = b[654:524];
+ 6'b1?????:
+ \9166 = b[785:655];
+ default:
+ \9166 = a;
+ endcase
+ endfunction
+ assign _289_ = \9166 (131'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { r[130:0], r[130:0], r[130:0], r[130:0], r[130:0], _185_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [63:0] \9169 ;
+ input [63:0] a;
+ input [383:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9169 = b[63:0];
+ 6'b????1?:
+ \9169 = b[127:64];
+ 6'b???1??:
+ \9169 = b[191:128];
+ 6'b??1???:
+ \9169 = b[255:192];
+ 6'b?1????:
+ \9169 = b[319:256];
+ 6'b1?????:
+ \9169 = b[383:320];
+ default:
+ \9169 = a;
+ endcase
+ endfunction
+ assign _290_ = \9169 (64'hxxxxxxxxxxxxxxxx, { r[194:131], r[194:131], r[194:131], _233_, r[194:131], r[194:131] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [26:0] \9173 ;
+ input [26:0] a;
+ input [161:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9173 = b[26:0];
+ 6'b????1?:
+ \9173 = b[53:27];
+ 6'b???1??:
+ \9173 = b[80:54];
+ 6'b??1???:
+ \9173 = b[107:81];
+ 6'b?1????:
+ \9173 = b[134:108];
+ 6'b1?????:
+ \9173 = b[161:135];
+ default:
+ \9173 = a;
+ endcase
+ endfunction
+ assign _291_ = \9173 (27'hxxxxxxx, { r[221:195], r[221:195], r[221:195], r[221:195], r[221:195], _186_[26:0] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [2:0] \9177 ;
+ input [2:0] a;
+ input [17:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9177 = b[2:0];
+ 6'b????1?:
+ \9177 = b[5:3];
+ 6'b???1??:
+ \9177 = b[8:6];
+ 6'b??1???:
+ \9177 = b[11:9];
+ 6'b?1????:
+ \9177 = b[14:12];
+ 6'b1?????:
+ \9177 = b[17:15];
+ default:
+ \9177 = a;
+ endcase
+ endfunction
+ assign _292_ = \9177 (3'hx, { 3'h0, _284_, _274_, _234_[2:0], 3'h2, _186_[29:27] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9182 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9182 = b[0:0];
+ 6'b????1?:
+ \9182 = b[1:1];
+ 6'b???1??:
+ \9182 = b[2:2];
+ 6'b??1???:
+ \9182 = b[3:3];
+ 6'b?1????:
+ \9182 = b[4:4];
+ 6'b1?????:
+ \9182 = b[5:5];
+ default:
+ \9182 = a;
+ endcase
+ endfunction
+ assign _293_ = \9182 (1'hx, { r[225], r[225], r[225], _234_[3], r[225], _186_[30] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [112:0] \9186 ;
+ input [112:0] a;
+ input [677:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9186 = b[112:0];
+ 6'b????1?:
+ \9186 = b[225:113];
+ 6'b???1??:
+ \9186 = b[338:226];
+ 6'b??1???:
+ \9186 = b[451:339];
+ 6'b?1????:
+ \9186 = b[564:452];
+ 6'b1?????:
+ \9186 = b[677:565];
+ default:
+ \9186 = a;
+ endcase
+ endfunction
+ assign _294_ = \9186 (113'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { r[338:226], r[338:226], r[338:226], r[338:226], r[338:226], _186_[143:31] }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [7:0] \9204 ;
+ input [7:0] a;
+ input [47:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9204 = b[7:0];
+ 6'b????1?:
+ \9204 = b[15:8];
+ 6'b???1??:
+ \9204 = b[23:16];
+ 6'b??1???:
+ \9204 = b[31:24];
+ 6'b?1????:
+ \9204 = b[39:32];
+ 6'b1?????:
+ \9204 = b[47:40];
+ default:
+ \9204 = a;
+ endcase
+ endfunction
+ assign _295_ = \9204 (8'hxx, { 16'h0000, _245_, 8'h00, r[241:234], _187_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9209 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9209 = b[0:0];
+ 6'b????1?:
+ \9209 = b[1:1];
+ 6'b???1??:
+ \9209 = b[2:2];
+ 6'b??1???:
+ \9209 = b[3:3];
+ 6'b?1????:
+ \9209 = b[4:4];
+ 6'b1?????:
+ \9209 = b[5:5];
+ default:
+ \9209 = a;
+ endcase
+ endfunction
+ assign _296_ = \9209 (1'hx, { 2'h0, _275_, 2'h1, _188_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9214 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9214 = b[0:0];
+ 6'b????1?:
+ \9214 = b[1:1];
+ 6'b???1??:
+ \9214 = b[2:2];
+ 6'b??1???:
+ \9214 = b[3:3];
+ 6'b?1????:
+ \9214 = b[4:4];
+ 6'b1?????:
+ \9214 = b[5:5];
+ default:
+ \9214 = a;
+ endcase
+ endfunction
+ assign _297_ = \9214 (1'hx, { 1'h0, _285_, _276_, _235_, 1'h1, _189_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [63:0] \9217 ;
+ input [63:0] a;
+ input [383:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9217 = b[63:0];
+ 6'b????1?:
+ \9217 = b[127:64];
+ 6'b???1??:
+ \9217 = b[191:128];
+ 6'b??1???:
+ \9217 = b[255:192];
+ 6'b?1????:
+ \9217 = b[319:256];
+ 6'b1?????:
+ \9217 = b[383:320];
+ default:
+ \9217 = a;
+ endcase
+ endfunction
+ assign _298_ = \9217 (64'hxxxxxxxxxxxxxxxx, { lsu_sum, lsu_sum, _246_, _225_, _110_, 3'h0, _190_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9220 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9220 = b[0:0];
+ 6'b????1?:
+ \9220 = b[1:1];
+ 6'b???1??:
+ \9220 = b[2:2];
+ 6'b??1???:
+ \9220 = b[3:3];
+ 6'b?1????:
+ \9220 = b[4:4];
+ 6'b1?????:
+ \9220 = b[5:5];
+ default:
+ \9220 = a;
+ endcase
+ endfunction
+ assign _299_ = \9220 (1'hx, { 3'h0, _237_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9225 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9225 = b[0:0];
+ 6'b????1?:
+ \9225 = b[1:1];
+ 6'b???1??:
+ \9225 = b[2:2];
+ 6'b??1???:
+ \9225 = b[3:3];
+ 6'b?1????:
+ \9225 = b[4:4];
+ 6'b1?????:
+ \9225 = b[5:5];
+ default:
+ \9225 = a;
+ endcase
+ endfunction
+ assign _300_ = \9225 (1'hx, { 3'h4, _238_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9230 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9230 = b[0:0];
+ 6'b????1?:
+ \9230 = b[1:1];
+ 6'b???1??:
+ \9230 = b[2:2];
+ 6'b??1???:
+ \9230 = b[3:3];
+ 6'b?1????:
+ \9230 = b[4:4];
+ 6'b1?????:
+ \9230 = b[5:5];
+ default:
+ \9230 = a;
+ endcase
+ endfunction
+ assign _301_ = \9230 (1'hx, { 1'h1, _286_, _277_, _239_, 1'h0, _191_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9234 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9234 = b[0:0];
+ 6'b????1?:
+ \9234 = b[1:1];
+ 6'b???1??:
+ \9234 = b[2:2];
+ 6'b??1???:
+ \9234 = b[3:3];
+ 6'b?1????:
+ \9234 = b[4:4];
+ 6'b1?????:
+ \9234 = b[5:5];
+ default:
+ \9234 = a;
+ endcase
+ endfunction
+ assign _302_ = \9234 (1'hx, { 5'h00, _192_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [63:0] \9238 ;
+ input [63:0] a;
+ input [383:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9238 = b[63:0];
+ 6'b????1?:
+ \9238 = b[127:64];
+ 6'b???1??:
+ \9238 = b[191:128];
+ 6'b??1???:
+ \9238 = b[255:192];
+ 6'b?1????:
+ \9238 = b[319:256];
+ 6'b1?????:
+ \9238 = b[383:320];
+ default:
+ \9238 = a;
+ endcase
+ endfunction
+ assign _303_ = \9238 (64'hxxxxxxxxxxxxxxxx, { 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000, _193_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9242 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9242 = b[0:0];
+ 6'b????1?:
+ \9242 = b[1:1];
+ 6'b???1??:
+ \9242 = b[2:2];
+ 6'b??1???:
+ \9242 = b[3:3];
+ 6'b?1????:
+ \9242 = b[4:4];
+ 6'b1?????:
+ \9242 = b[5:5];
+ default:
+ \9242 = a;
+ endcase
+ endfunction
+ assign _304_ = \9242 (1'hx, { 2'h0, _278_, _240_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9246 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9246 = b[0:0];
+ 6'b????1?:
+ \9246 = b[1:1];
+ 6'b???1??:
+ \9246 = b[2:2];
+ 6'b??1???:
+ \9246 = b[3:3];
+ 6'b?1????:
+ \9246 = b[4:4];
+ 6'b1?????:
+ \9246 = b[5:5];
+ default:
+ \9246 = a;
+ endcase
+ endfunction
+ assign _305_ = \9246 (1'hx, { 3'h0, _241_, 1'h0, _194_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [1:0] \9250 ;
+ input [1:0] a;
+ input [11:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9250 = b[1:0];
+ 6'b????1?:
+ \9250 = b[3:2];
+ 6'b???1??:
+ \9250 = b[5:4];
+ 6'b??1???:
+ \9250 = b[7:6];
+ 6'b?1????:
+ \9250 = b[9:8];
+ 6'b1?????:
+ \9250 = b[11:10];
+ default:
+ \9250 = a;
+ endcase
+ endfunction
+ assign _306_ = \9250 (2'hx, { 4'h0, _279_, 6'h00 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9253 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9253 = b[0:0];
+ 6'b????1?:
+ \9253 = b[1:1];
+ 6'b???1??:
+ \9253 = b[2:2];
+ 6'b??1???:
+ \9253 = b[3:3];
+ 6'b?1????:
+ \9253 = b[4:4];
+ 6'b1?????:
+ \9253 = b[5:5];
+ default:
+ \9253 = a;
+ endcase
+ endfunction
+ assign _307_ = \9253 (1'hx, { 2'h0, _280_, _242_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9256 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9256 = b[0:0];
+ 6'b????1?:
+ \9256 = b[1:1];
+ 6'b???1??:
+ \9256 = b[2:2];
+ 6'b??1???:
+ \9256 = b[3:3];
+ 6'b?1????:
+ \9256 = b[4:4];
+ 6'b1?????:
+ \9256 = b[5:5];
+ default:
+ \9256 = a;
+ endcase
+ endfunction
+ assign _308_ = \9256 (1'hx, { 2'h0, _281_, 3'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9259 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9259 = b[0:0];
+ 6'b????1?:
+ \9259 = b[1:1];
+ 6'b???1??:
+ \9259 = b[2:2];
+ 6'b??1???:
+ \9259 = b[3:3];
+ 6'b?1????:
+ \9259 = b[4:4];
+ 6'b1?????:
+ \9259 = b[5:5];
+ default:
+ \9259 = a;
+ endcase
+ endfunction
+ assign _309_ = \9259 (1'hx, { 3'h0, _243_, 2'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9262 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9262 = b[0:0];
+ 6'b????1?:
+ \9262 = b[1:1];
+ 6'b???1??:
+ \9262 = b[2:2];
+ 6'b??1???:
+ \9262 = b[3:3];
+ 6'b?1????:
+ \9262 = b[4:4];
+ 6'b1?????:
+ \9262 = b[5:5];
+ default:
+ \9262 = a;
+ endcase
+ endfunction
+ assign _310_ = \9262 (1'hx, { 2'h0, _282_, 3'h0 }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9275 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9275 = b[0:0];
+ 6'b????1?:
+ \9275 = b[1:1];
+ 6'b???1??:
+ \9275 = b[2:2];
+ 6'b??1???:
+ \9275 = b[3:3];
+ 6'b?1????:
+ \9275 = b[4:4];
+ 6'b1?????:
+ \9275 = b[5:5];
+ default:
+ \9275 = a;
+ endcase
+ endfunction
+ assign _311_ = \9275 (1'hx, { 5'h00, _195_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ function [0:0] \9279 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \9279 = b[0:0];
+ 6'b????1?:
+ \9279 = b[1:1];
+ 6'b???1??:
+ \9279 = b[2:2];
+ 6'b??1???:
+ \9279 = b[3:3];
+ 6'b?1????:
+ \9279 = b[4:4];
+ 6'b1?????:
+ \9279 = b[5:5];
+ default:
+ \9279 = a;
+ endcase
+ endfunction
+ assign _312_ = \9279 (1'hx, { 5'h00, _196_ }, { _288_, _287_, _283_, _244_, _198_, _197_ });
+ assign _313_ = _300_ ? { r[66:3], r[211:207], 1'h1 } : { _109_, _099_, _089_, _079_, _069_, _059_, _049_, _039_, r[199:195], _299_ };
+ assign _314_ = _302_ ? { _303_, l_in[299:295], 1'h1 } : _313_;
+ assign _315_ = r[218] & _301_;
+ assign _316_ = ~ r[338];
+ assign _317_ = _304_ & _316_;
+ assign _318_ = ~ m_in[3];
+ assign _319_ = _318_ ? { 1'h0, _310_, 1'h0, _309_, _308_, 1'h0, _307_, 5'h00, _306_, 18'h00000 } : _294_[111:80];
+ assign _320_ = _317_ ? { _319_, _298_ } : _294_[111:16];
+ assign _323_ = _008_[2] ? _322_ : _321_;
+ assign _326_ = _010_[2] ? _325_ : _324_;
+ assign _329_ = _012_[2] ? _328_ : _327_;
+ assign _332_ = _014_[2] ? _331_ : _330_;
+ assign _335_ = _016_[2] ? _334_ : _333_;
+ assign _338_ = _018_[2] ? _337_ : _336_;
+ assign _341_ = _020_[2] ? _340_ : _339_;
+ assign _344_ = _022_[2] ? _343_ : _342_;
+ assign _345_ = ~ _166_[2];
+ assign _346_ = ~ _166_[1];
+ assign _347_ = _345_ & _346_;
+ assign _348_ = _345_ & _166_[1];
+ assign _349_ = _166_[2] & _346_;
+ assign _350_ = _166_[2] & _166_[1];
+ assign _351_ = ~ _166_[0];
+ assign _352_ = _347_ & _351_;
+ assign _353_ = _347_ & _166_[0];
+ assign _354_ = _348_ & _351_;
+ assign _355_ = _348_ & _166_[0];
+ assign _356_ = _349_ & _351_;
+ assign _357_ = _349_ & _166_[0];
+ assign _358_ = _350_ & _351_;
+ assign _359_ = _350_ & _166_[0];
+ assign _360_ = _352_ ? l_in[238:231] : r[74:67];
+ assign _361_ = _353_ ? l_in[238:231] : r[82:75];
+ assign _362_ = _354_ ? l_in[238:231] : r[90:83];
+ assign _363_ = _355_ ? l_in[238:231] : r[98:91];
+ assign _364_ = _356_ ? l_in[238:231] : r[106:99];
+ assign _365_ = _357_ ? l_in[238:231] : r[114:107];
+ assign _366_ = _358_ ? l_in[238:231] : r[122:115];
+ assign _367_ = _359_ ? l_in[238:231] : r[130:123];
+ assign _368_ = ~ _168_[2];
+ assign _369_ = ~ _168_[1];
+ assign _370_ = _368_ & _369_;
+ assign _371_ = _368_ & _168_[1];
+ assign _372_ = _168_[2] & _369_;
+ assign _373_ = _168_[2] & _168_[1];
+ assign _374_ = ~ _168_[0];
+ assign _375_ = _370_ & _374_;
+ assign _376_ = _370_ & _168_[0];
+ assign _377_ = _371_ & _374_;
+ assign _378_ = _371_ & _168_[0];
+ assign _379_ = _372_ & _374_;
+ assign _380_ = _372_ & _168_[0];
+ assign _381_ = _373_ & _374_;
+ assign _382_ = _373_ & _168_[0];
+ assign _383_ = _375_ ? l_in[246:239] : _360_;
+ assign _384_ = _376_ ? l_in[246:239] : _361_;
+ assign _385_ = _377_ ? l_in[246:239] : _362_;
+ assign _386_ = _378_ ? l_in[246:239] : _363_;
+ assign _387_ = _379_ ? l_in[246:239] : _364_;
+ assign _388_ = _380_ ? l_in[246:239] : _365_;
+ assign _389_ = _381_ ? l_in[246:239] : _366_;
+ assign _390_ = _382_ ? l_in[246:239] : _367_;
+ assign _391_ = ~ _170_[2];
+ assign _392_ = ~ _170_[1];
+ assign _393_ = _391_ & _392_;
+ assign _394_ = _391_ & _170_[1];
+ assign _395_ = _170_[2] & _392_;
+ assign _396_ = _170_[2] & _170_[1];
+ assign _397_ = ~ _170_[0];
+ assign _398_ = _393_ & _397_;
+ assign _399_ = _393_ & _170_[0];
+ assign _400_ = _394_ & _397_;
+ assign _401_ = _394_ & _170_[0];
+ assign _402_ = _395_ & _397_;
+ assign _403_ = _395_ & _170_[0];
+ assign _404_ = _396_ & _397_;
+ assign _405_ = _396_ & _170_[0];
+ assign _406_ = _398_ ? l_in[254:247] : _383_;
+ assign _407_ = _399_ ? l_in[254:247] : _384_;
+ assign _408_ = _400_ ? l_in[254:247] : _385_;
+ assign _409_ = _401_ ? l_in[254:247] : _386_;
+ assign _410_ = _402_ ? l_in[254:247] : _387_;
+ assign _411_ = _403_ ? l_in[254:247] : _388_;
+ assign _412_ = _404_ ? l_in[254:247] : _389_;
+ assign _413_ = _405_ ? l_in[254:247] : _390_;
+ assign _414_ = ~ _172_[2];
+ assign _415_ = ~ _172_[1];
+ assign _416_ = _414_ & _415_;
+ assign _417_ = _414_ & _172_[1];
+ assign _418_ = _172_[2] & _415_;
+ assign _419_ = _172_[2] & _172_[1];
+ assign _420_ = ~ _172_[0];
+ assign _421_ = _416_ & _420_;
+ assign _422_ = _416_ & _172_[0];
+ assign _423_ = _417_ & _420_;
+ assign _424_ = _417_ & _172_[0];
+ assign _425_ = _418_ & _420_;
+ assign _426_ = _418_ & _172_[0];
+ assign _427_ = _419_ & _420_;
+ assign _428_ = _419_ & _172_[0];
+ assign _429_ = _421_ ? l_in[262:255] : _406_;
+ assign _430_ = _422_ ? l_in[262:255] : _407_;
+ assign _431_ = _423_ ? l_in[262:255] : _408_;
+ assign _432_ = _424_ ? l_in[262:255] : _409_;
+ assign _433_ = _425_ ? l_in[262:255] : _410_;
+ assign _434_ = _426_ ? l_in[262:255] : _411_;
+ assign _435_ = _427_ ? l_in[262:255] : _412_;
+ assign _436_ = _428_ ? l_in[262:255] : _413_;
+ assign _437_ = ~ _174_[2];
+ assign _438_ = ~ _174_[1];
+ assign _439_ = _437_ & _438_;
+ assign _440_ = _437_ & _174_[1];
+ assign _441_ = _174_[2] & _438_;
+ assign _442_ = _174_[2] & _174_[1];
+ assign _443_ = ~ _174_[0];
+ assign _444_ = _439_ & _443_;
+ assign _445_ = _439_ & _174_[0];
+ assign _446_ = _440_ & _443_;
+ assign _447_ = _440_ & _174_[0];
+ assign _448_ = _441_ & _443_;
+ assign _449_ = _441_ & _174_[0];
+ assign _450_ = _442_ & _443_;
+ assign _451_ = _442_ & _174_[0];
+ assign _452_ = _444_ ? l_in[270:263] : _429_;
+ assign _453_ = _445_ ? l_in[270:263] : _430_;
+ assign _454_ = _446_ ? l_in[270:263] : _431_;
+ assign _455_ = _447_ ? l_in[270:263] : _432_;
+ assign _456_ = _448_ ? l_in[270:263] : _433_;
+ assign _457_ = _449_ ? l_in[270:263] : _434_;
+ assign _458_ = _450_ ? l_in[270:263] : _435_;
+ assign _459_ = _451_ ? l_in[270:263] : _436_;
+ assign _460_ = ~ _176_[2];
+ assign _461_ = ~ _176_[1];
+ assign _462_ = _460_ & _461_;
+ assign _463_ = _460_ & _176_[1];
+ assign _464_ = _176_[2] & _461_;
+ assign _465_ = _176_[2] & _176_[1];
+ assign _466_ = ~ _176_[0];
+ assign _467_ = _462_ & _466_;
+ assign _468_ = _462_ & _176_[0];
+ assign _469_ = _463_ & _466_;
+ assign _470_ = _463_ & _176_[0];
+ assign _471_ = _464_ & _466_;
+ assign _472_ = _464_ & _176_[0];
+ assign _473_ = _465_ & _466_;
+ assign _474_ = _465_ & _176_[0];
+ assign _475_ = _467_ ? l_in[278:271] : _452_;
+ assign _476_ = _468_ ? l_in[278:271] : _453_;
+ assign _477_ = _469_ ? l_in[278:271] : _454_;
+ assign _478_ = _470_ ? l_in[278:271] : _455_;
+ assign _479_ = _471_ ? l_in[278:271] : _456_;
+ assign _480_ = _472_ ? l_in[278:271] : _457_;
+ assign _481_ = _473_ ? l_in[278:271] : _458_;
+ assign _482_ = _474_ ? l_in[278:271] : _459_;
+ assign _483_ = ~ _178_[2];
+ assign _484_ = ~ _178_[1];
+ assign _485_ = _483_ & _484_;
+ assign _486_ = _483_ & _178_[1];
+ assign _487_ = _178_[2] & _484_;
+ assign _488_ = _178_[2] & _178_[1];
+ assign _489_ = ~ _178_[0];
+ assign _490_ = _485_ & _489_;
+ assign _491_ = _485_ & _178_[0];
+ assign _492_ = _486_ & _489_;
+ assign _493_ = _486_ & _178_[0];
+ assign _494_ = _487_ & _489_;
+ assign _495_ = _487_ & _178_[0];
+ assign _496_ = _488_ & _489_;
+ assign _497_ = _488_ & _178_[0];
+ assign _498_ = _490_ ? l_in[286:279] : _475_;
+ assign _499_ = _491_ ? l_in[286:279] : _476_;
+ assign _500_ = _492_ ? l_in[286:279] : _477_;
+ assign _501_ = _493_ ? l_in[286:279] : _478_;
+ assign _502_ = _494_ ? l_in[286:279] : _479_;
+ assign _503_ = _495_ ? l_in[286:279] : _480_;
+ assign _504_ = _496_ ? l_in[286:279] : _481_;
+ assign _505_ = _497_ ? l_in[286:279] : _482_;
+ assign _506_ = ~ _180_[2];
+ assign _507_ = ~ _180_[1];
+ assign _508_ = _506_ & _507_;
+ assign _509_ = _506_ & _180_[1];
+ assign _510_ = _180_[2] & _507_;
+ assign _511_ = _180_[2] & _180_[1];
+ assign _512_ = ~ _180_[0];
+ assign _513_ = _508_ & _512_;
+ assign _514_ = _508_ & _180_[0];
+ assign _515_ = _509_ & _512_;
+ assign _516_ = _509_ & _180_[0];
+ assign _517_ = _510_ & _512_;
+ assign _518_ = _510_ & _180_[0];
+ assign _519_ = _511_ & _512_;
+ assign _520_ = _511_ & _180_[0];
+ assign _521_ = _513_ ? l_in[294:287] : _498_;
+ assign _522_ = _514_ ? l_in[294:287] : _499_;
+ assign _523_ = _515_ ? l_in[294:287] : _500_;
+ assign _524_ = _516_ ? l_in[294:287] : _501_;
+ assign _525_ = _517_ ? l_in[294:287] : _502_;
+ assign _526_ = _518_ ? l_in[294:287] : _503_;
+ assign _527_ = _519_ ? l_in[294:287] : _504_;
+ assign _528_ = _520_ ? l_in[294:287] : _505_;
+ assign e_out = { r[338], m_in[3:2], m_in[5:4], m_in[1], _304_ };
+ assign l_out = { d_in[65], _315_, r[216:212], _314_, _301_ };
+ assign d_out = { _295_, _289_[130:67], _298_, _291_[26:25], _291_[22], _291_[24], _289_[2], _289_[0], _296_ };
+ assign m_out = { l_in[294:231], _298_, l_in[86:82], l_in[91:87], r[221], r[0], _294_[112], _311_, l_in[78], _289_[1], _305_ };
+ assign stall_out = _297_;
+endmodule
+
+module logical(rs, rb, op, invert_in, invert_out, datalen, result, popcnt, parity);
+ wire [63:0] _00_;
+ wire [63:0] _01_;
+ wire [63:0] _02_;
+ wire _03_;
+ wire [63:0] _04_;
+ wire _05_;
+ wire [63:0] _06_;
+ wire [63:0] _07_;
+ wire [63:0] _08_;
+ wire [63:0] _09_;
+ wire [1:0] _10_;
+ wire [1:0] _11_;
+ wire [1:0] _12_;
+ wire [1:0] _13_;
+ wire [1:0] _14_;
+ wire [1:0] _15_;
+ wire [1:0] _16_;
+ wire [1:0] _17_;
+ wire [1:0] _18_;
+ wire [1:0] _19_;
+ wire [1:0] _20_;
+ wire [1:0] _21_;
+ wire [1:0] _22_;
+ wire [1:0] _23_;
+ wire [1:0] _24_;
+ wire [1:0] _25_;
+ wire [1:0] _26_;
+ wire [1:0] _27_;
+ wire [1:0] _28_;
+ wire [1:0] _29_;
+ wire [1:0] _30_;
+ wire [1:0] _31_;
+ wire [1:0] _32_;
+ wire [1:0] _33_;
+ wire [1:0] _34_;
+ wire [1:0] _35_;
+ wire [1:0] _36_;
+ wire [1:0] _37_;
+ wire [1:0] _38_;
+ wire [1:0] _39_;
+ wire [1:0] _40_;
+ wire [1:0] _41_;
+ wire [2:0] _42_;
+ wire [2:0] _43_;
+ wire [2:0] _44_;
+ wire [2:0] _45_;
+ wire [2:0] _46_;
+ wire [2:0] _47_;
+ wire [2:0] _48_;
+ wire [2:0] _49_;
+ wire [2:0] _50_;
+ wire [2:0] _51_;
+ wire [2:0] _52_;
+ wire [2:0] _53_;
+ wire [2:0] _54_;
+ wire [2:0] _55_;
+ wire [2:0] _56_;
+ wire [2:0] _57_;
+ wire [3:0] _58_;
+ wire [3:0] _59_;
+ wire [3:0] _60_;
+ wire [3:0] _61_;
+ wire [3:0] _62_;
+ wire [3:0] _63_;
+ wire [3:0] _64_;
+ wire [3:0] _65_;
+ wire [5:0] _66_;
+ wire [5:0] _67_;
+ wire [5:0] _68_;
+ wire [5:0] _69_;
+ wire [5:0] _70_;
+ wire [5:0] _71_;
+ wire _72_;
+ wire _73_;
+ wire [6:0] _74_;
+ wire [5:0] _75_;
+ wire _76_;
+ wire [5:0] _77_;
+ wire [3:0] _78_;
+ wire [2:0] _79_;
+ wire [3:0] _80_;
+ wire [3:0] _81_;
+ wire [3:0] _82_;
+ wire [3:0] _83_;
+ wire [1:0] _84_;
+ wire [3:0] _85_;
+ wire [3:0] _86_;
+ wire [3:0] _87_;
+ wire _88_;
+ wire _89_;
+ wire _90_;
+ wire _91_;
+ wire _92_;
+ wire _93_;
+ wire _94_;
+ input [3:0] datalen;
+ input invert_in;
+ input invert_out;
+ input [5:0] op;
+ wire par0;
+ wire par1;
+ output [63:0] parity;
+ output [63:0] popcnt;
+ input [63:0] rb;
+ output [63:0] result;
+ input [63:0] rs;
+ assign _00_ = ~ rb;
+ assign _01_ = invert_in ? _00_ : rb;
+ assign _02_ = rs & _01_;
+ assign _03_ = op == 6'h03;
+ assign _04_ = rs | _01_;
+ assign _05_ = op == 6'h2e;
+ assign _06_ = rs ^ _01_;
+ function [63:0] \19328 ;
+ input [63:0] a;
+ input [127:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \19328 = b[63:0];
+ 2'b1?:
+ \19328 = b[127:64];
+ default:
+ \19328 = a;
+ endcase
+ endfunction
+ assign _07_ = \19328 (_06_, { _04_, _02_ }, { _05_, _03_ });
+ assign _08_ = ~ _07_;
+ assign _09_ = invert_out ? _08_ : _07_;
+ assign _10_ = { 1'h0, rs[0] } + { 1'h0, rs[1] };
+ assign _11_ = { 1'h0, rs[2] } + { 1'h0, rs[3] };
+ assign _12_ = { 1'h0, rs[4] } + { 1'h0, rs[5] };
+ assign _13_ = { 1'h0, rs[6] } + { 1'h0, rs[7] };
+ assign _14_ = { 1'h0, rs[8] } + { 1'h0, rs[9] };
+ assign _15_ = { 1'h0, rs[10] } + { 1'h0, rs[11] };
+ assign _16_ = { 1'h0, rs[12] } + { 1'h0, rs[13] };
+ assign _17_ = { 1'h0, rs[14] } + { 1'h0, rs[15] };
+ assign _18_ = { 1'h0, rs[16] } + { 1'h0, rs[17] };
+ assign _19_ = { 1'h0, rs[18] } + { 1'h0, rs[19] };
+ assign _20_ = { 1'h0, rs[20] } + { 1'h0, rs[21] };
+ assign _21_ = { 1'h0, rs[22] } + { 1'h0, rs[23] };
+ assign _22_ = { 1'h0, rs[24] } + { 1'h0, rs[25] };
+ assign _23_ = { 1'h0, rs[26] } + { 1'h0, rs[27] };
+ assign _24_ = { 1'h0, rs[28] } + { 1'h0, rs[29] };
+ assign _25_ = { 1'h0, rs[30] } + { 1'h0, rs[31] };
+ assign _26_ = { 1'h0, rs[32] } + { 1'h0, rs[33] };
+ assign _27_ = { 1'h0, rs[34] } + { 1'h0, rs[35] };
+ assign _28_ = { 1'h0, rs[36] } + { 1'h0, rs[37] };
+ assign _29_ = { 1'h0, rs[38] } + { 1'h0, rs[39] };
+ assign _30_ = { 1'h0, rs[40] } + { 1'h0, rs[41] };
+ assign _31_ = { 1'h0, rs[42] } + { 1'h0, rs[43] };
+ assign _32_ = { 1'h0, rs[44] } + { 1'h0, rs[45] };
+ assign _33_ = { 1'h0, rs[46] } + { 1'h0, rs[47] };
+ assign _34_ = { 1'h0, rs[48] } + { 1'h0, rs[49] };
+ assign _35_ = { 1'h0, rs[50] } + { 1'h0, rs[51] };
+ assign _36_ = { 1'h0, rs[52] } + { 1'h0, rs[53] };
+ assign _37_ = { 1'h0, rs[54] } + { 1'h0, rs[55] };
+ assign _38_ = { 1'h0, rs[56] } + { 1'h0, rs[57] };
+ assign _39_ = { 1'h0, rs[58] } + { 1'h0, rs[59] };
+ assign _40_ = { 1'h0, rs[60] } + { 1'h0, rs[61] };
+ assign _41_ = { 1'h0, rs[62] } + { 1'h0, rs[63] };
+ assign _42_ = { 1'h0, _10_ } + { 1'h0, _11_ };
+ assign _43_ = { 1'h0, _12_ } + { 1'h0, _13_ };
+ assign _44_ = { 1'h0, _14_ } + { 1'h0, _15_ };
+ assign _45_ = { 1'h0, _16_ } + { 1'h0, _17_ };
+ assign _46_ = { 1'h0, _18_ } + { 1'h0, _19_ };
+ assign _47_ = { 1'h0, _20_ } + { 1'h0, _21_ };
+ assign _48_ = { 1'h0, _22_ } + { 1'h0, _23_ };
+ assign _49_ = { 1'h0, _24_ } + { 1'h0, _25_ };
+ assign _50_ = { 1'h0, _26_ } + { 1'h0, _27_ };
+ assign _51_ = { 1'h0, _28_ } + { 1'h0, _29_ };
+ assign _52_ = { 1'h0, _30_ } + { 1'h0, _31_ };
+ assign _53_ = { 1'h0, _32_ } + { 1'h0, _33_ };
+ assign _54_ = { 1'h0, _34_ } + { 1'h0, _35_ };
+ assign _55_ = { 1'h0, _36_ } + { 1'h0, _37_ };
+ assign _56_ = { 1'h0, _38_ } + { 1'h0, _39_ };
+ assign _57_ = { 1'h0, _40_ } + { 1'h0, _41_ };
+ assign _58_ = { 1'h0, _42_ } + { 1'h0, _43_ };
+ assign _59_ = { 1'h0, _44_ } + { 1'h0, _45_ };
+ assign _60_ = { 1'h0, _46_ } + { 1'h0, _47_ };
+ assign _61_ = { 1'h0, _48_ } + { 1'h0, _49_ };
+ assign _62_ = { 1'h0, _50_ } + { 1'h0, _51_ };
+ assign _63_ = { 1'h0, _52_ } + { 1'h0, _53_ };
+ assign _64_ = { 1'h0, _54_ } + { 1'h0, _55_ };
+ assign _65_ = { 1'h0, _56_ } + { 1'h0, _57_ };
+ assign _66_ = { 2'h0, _58_ } + { 2'h0, _59_ };
+ assign _67_ = _66_ + { 2'h0, _60_ };
+ assign _68_ = _67_ + { 2'h0, _61_ };
+ assign _69_ = { 2'h0, _62_ } + { 2'h0, _63_ };
+ assign _70_ = _69_ + { 2'h0, _64_ };
+ assign _71_ = _70_ + { 2'h0, _65_ };
+ assign _72_ = datalen[3:2] == 2'h0;
+ assign _73_ = ~ datalen[3];
+ assign _74_ = { 1'h0, _68_ } + { 1'h0, _71_ };
+ assign _75_ = _73_ ? _68_ : _74_[5:0];
+ assign _76_ = _73_ ? 1'h0 : _74_[6];
+ assign _77_ = _73_ ? _71_ : 6'h00;
+ assign _78_ = _72_ ? _58_ : _75_[3:0];
+ assign _79_ = _72_ ? 3'h0 : { _76_, _75_[5:4] };
+ assign _80_ = _72_ ? _59_ : 4'h0;
+ assign _81_ = _72_ ? _60_ : 4'h0;
+ assign _82_ = _72_ ? _61_ : 4'h0;
+ assign _83_ = _72_ ? _62_ : _77_[3:0];
+ assign _84_ = _72_ ? 2'h0 : _77_[5:4];
+ assign _85_ = _72_ ? _63_ : 4'h0;
+ assign _86_ = _72_ ? _64_ : 4'h0;
+ assign _87_ = _72_ ? _65_ : 4'h0;
+ assign _88_ = rs[0] ^ rs[8];
+ assign _89_ = _88_ ^ rs[16];
+ assign par0 = _89_ ^ rs[24];
+ assign _90_ = rs[32] ^ rs[40];
+ assign _91_ = _90_ ^ rs[48];
+ assign par1 = _91_ ^ rs[56];
+ assign _92_ = par0 ^ par1;
+ assign _93_ = datalen[3] ? _92_ : par0;
+ assign _94_ = datalen[3] ? 1'h0 : par1;
+ assign result = _09_;
+ assign popcnt = { 4'h0, _87_, 4'h0, _86_, 4'h0, _85_, 2'h0, _84_, _83_, 4'h0, _82_, 4'h0, _81_, 4'h0, _80_, 1'h0, _79_, _78_ };
+ assign parity = { 31'h00000000, _94_, 31'h00000000, _93_ };
+endmodule
+
+module microwatt_wrapper(clk, rst, wishbone_insn_dat_r, wishbone_insn_ack, wishbone_insn_stall, wishbone_data_dat_r, wishbone_data_ack, wishbone_data_stall, dmi_addr, dmi_din, dmi_req, dmi_wr, wishbone_insn_adr, wishbone_insn_dat_w, wishbone_insn_cyc, wishbone_insn_stb, wishbone_insn_sel, wishbone_insn_we, wishbone_data_adr, wishbone_data_dat_w, wishbone_data_cyc, wishbone_data_stb, wishbone_data_sel, wishbone_data_we, dmi_dout, dmi_ack, terminated_out);
+ wire [63:0] _0_;
+ wire _1_;
+ wire _2_;
+ input clk;
+ output dmi_ack;
+ input [3:0] dmi_addr;
+ input [63:0] dmi_din;
+ output [63:0] dmi_dout;
+ input dmi_req;
+ input dmi_wr;
+ input rst;
+ output terminated_out;
+ input wishbone_data_ack;
+ output [31:0] wishbone_data_adr;
+ output wishbone_data_cyc;
+ input [63:0] wishbone_data_dat_r;
+ output [63:0] wishbone_data_dat_w;
+ wire [106:0] wishbone_data_out;
+ output [7:0] wishbone_data_sel;
+ input wishbone_data_stall;
+ output wishbone_data_stb;
+ output wishbone_data_we;
+ input wishbone_insn_ack;
+ output [31:0] wishbone_insn_adr;
+ output wishbone_insn_cyc;
+ input [63:0] wishbone_insn_dat_r;
+ output [63:0] wishbone_insn_dat_w;
+ wire [106:0] wishbone_insn_out;
+ output [7:0] wishbone_insn_sel;
+ input wishbone_insn_stall;
+ output wishbone_insn_stb;
+ output wishbone_insn_we;
+ core_71ba14ecdd9e9507b1aeafd985ac12164cac4c4e microwatt_core (
+ .alt_reset(1'h0),
+ .clk(clk),
+ .dmi_ack(_1_),
+ .dmi_addr(dmi_addr),
+ .dmi_din(dmi_din),
+ .dmi_dout(_0_),
+ .dmi_req(dmi_req),
+ .dmi_wr(dmi_wr),
+ .ext_irq(1'h0),
+ .rst(rst),
+ .terminated_out(_2_),
+ .wishbone_data_in({ wishbone_data_stall, wishbone_data_ack, wishbone_data_dat_r }),
+ .wishbone_data_out(wishbone_data_out),
+ .wishbone_insn_in({ wishbone_insn_stall, wishbone_insn_ack, wishbone_insn_dat_r }),
+ .wishbone_insn_out(wishbone_insn_out)
+ );
+ assign wishbone_insn_adr = wishbone_insn_out[31:0];
+ assign wishbone_insn_dat_w = wishbone_insn_out[95:32];
+ assign wishbone_insn_cyc = wishbone_insn_out[96];
+ assign wishbone_insn_stb = wishbone_insn_out[97];
+ assign wishbone_insn_sel = wishbone_insn_out[105:98];
+ assign wishbone_insn_we = wishbone_insn_out[106];
+ assign wishbone_data_adr = wishbone_data_out[31:0];
+ assign wishbone_data_dat_w = wishbone_data_out[95:32];
+ assign wishbone_data_cyc = wishbone_data_out[96];
+ assign wishbone_data_stb = wishbone_data_out[97];
+ assign wishbone_data_sel = wishbone_data_out[105:98];
+ assign wishbone_data_we = wishbone_data_out[106];
+ assign dmi_dout = _0_;
+ assign dmi_ack = _1_;
+ assign terminated_out = _2_;
+endmodule
+
+module mmu(clk, rst, l_in, d_in, l_out, d_out, i_out);
+ wire [63:0] _000_;
+ wire _001_;
+ wire [66:0] _002_;
+ wire [63:0] _003_;
+ wire [31:0] _004_;
+ wire [3:0] _005_;
+ wire [63:0] _006_;
+ wire _007_;
+ wire [63:0] _008_;
+ wire _009_;
+ wire [135:0] _010_;
+ wire _011_;
+ wire _012_;
+ wire [30:0] _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire [18:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire [63:0] _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire [3:0] _145_;
+ wire _146_;
+ wire [3:0] _147_;
+ wire [5:0] _148_;
+ wire _149_;
+ wire _150_;
+ wire [3:0] _151_;
+ wire _152_;
+ wire _153_;
+ wire [5:0] _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire [67:0] _159_;
+ wire [3:0] _160_;
+ wire _161_;
+ wire [6:0] _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire [63:0] _168_;
+ wire [31:0] _169_;
+ wire _170_;
+ wire [99:0] _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire [3:0] _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire [64:0] _183_;
+ wire [64:0] _184_;
+ wire _185_;
+ wire [3:0] _186_;
+ wire _187_;
+ wire [3:0] _188_;
+ wire [196:0] _189_;
+ wire _190_;
+ wire _191_;
+ wire [200:0] _192_;
+ wire [1:0] _193_;
+ wire _194_;
+ wire [5:0] _195_;
+ wire [5:0] _196_;
+ wire [30:0] _197_;
+ wire [30:0] _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire [5:0] _205_;
+ wire _206_;
+ wire _207_;
+ wire [3:0] _208_;
+ wire _209_;
+ wire [3:0] _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire [3:0] _231_;
+ wire [1:0] _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire [5:0] _238_;
+ wire [3:0] _239_;
+ wire [66:0] _240_;
+ wire _241_;
+ wire [3:0] _242_;
+ wire [66:0] _243_;
+ wire _244_;
+ wire [1:0] _245_;
+ wire [3:0] _246_;
+ wire [66:0] _247_;
+ wire _248_;
+ wire _249_;
+ wire [1:0] _250_;
+ wire [3:0] _251_;
+ wire [131:0] _252_;
+ wire _253_;
+ wire [1:0] _254_;
+ wire [3:0] _255_;
+ wire [132:0] _256_;
+ wire [1:0] _257_;
+ wire _258_;
+ wire _259_;
+ wire [3:0] _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire [67:0] _266_;
+ wire [95:0] _267_;
+ wire [3:0] _268_;
+ wire [63:0] _269_;
+ wire _270_;
+ wire [63:0] _271_;
+ wire _272_;
+ wire [5:0] _273_;
+ wire [4:0] _274_;
+ wire [55:0] _275_;
+ wire [63:0] _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire [1:0] _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire _284_;
+ wire _285_;
+ wire _286_;
+ wire _287_;
+ wire [31:0] _288_;
+ wire [23:0] _289_;
+ wire [23:0] _290_;
+ wire [23:0] _291_;
+ wire [23:0] _292_;
+ wire [15:0] _293_;
+ wire [15:0] _294_;
+ wire [15:0] _295_;
+ wire [15:0] _296_;
+ wire [43:0] _297_;
+ wire [43:0] _298_;
+ wire [43:0] _299_;
+ wire [43:0] _300_;
+ wire [63:0] _301_;
+ wire [63:0] _302_;
+ wire [63:0] _303_;
+ wire [63:0] _304_;
+ wire [63:0] _305_;
+ wire [15:0] addrsh;
+ input clk;
+ input [66:0] d_in;
+ output [131:0] d_out;
+ output [130:0] i_out;
+ input [144:0] l_in;
+ output [69:0] l_out;
+ reg [433:0] r;
+ input rst;
+ assign _055_ = $signed(32'd6) < $signed({ 26'h0000000, r[303:298] });
+ assign _056_ = _055_ ? 1'h1 : 1'h0;
+ assign _057_ = $signed(32'd7) < $signed({ 26'h0000000, r[303:298] });
+ assign _058_ = _057_ ? 1'h1 : 1'h0;
+ assign _059_ = $signed(32'd8) < $signed({ 26'h0000000, r[303:298] });
+ assign _060_ = _059_ ? 1'h1 : 1'h0;
+ assign _061_ = $signed(32'd9) < $signed({ 26'h0000000, r[303:298] });
+ assign _062_ = _061_ ? 1'h1 : 1'h0;
+ assign _063_ = $signed(32'd10) < $signed({ 26'h0000000, r[303:298] });
+ assign _064_ = _063_ ? 1'h1 : 1'h0;
+ assign _065_ = $signed(32'd11) < $signed({ 26'h0000000, r[303:298] });
+ assign _066_ = _065_ ? 1'h1 : 1'h0;
+ assign _067_ = $signed(32'd12) < $signed({ 26'h0000000, r[303:298] });
+ assign _068_ = _067_ ? 1'h1 : 1'h0;
+ assign _069_ = $signed(32'd13) < $signed({ 26'h0000000, r[303:298] });
+ assign _070_ = _069_ ? 1'h1 : 1'h0;
+ assign _071_ = $signed(32'd14) < $signed({ 26'h0000000, r[303:298] });
+ assign _072_ = _071_ ? 1'h1 : 1'h0;
+ assign _073_ = $signed(32'd15) < $signed({ 26'h0000000, r[303:298] });
+ assign _074_ = _073_ ? 1'h1 : 1'h0;
+ assign _075_ = $signed(32'd16) < $signed({ 26'h0000000, r[303:298] });
+ assign _076_ = _075_ ? 1'h1 : 1'h0;
+ assign _077_ = $signed(32'd17) < $signed({ 26'h0000000, r[303:298] });
+ assign _078_ = _077_ ? 1'h1 : 1'h0;
+ assign _079_ = $signed(32'd18) < $signed({ 26'h0000000, r[303:298] });
+ assign _080_ = _079_ ? 1'h1 : 1'h0;
+ assign _081_ = $signed(32'd19) < $signed({ 26'h0000000, r[303:298] });
+ assign _082_ = _081_ ? 1'h1 : 1'h0;
+ assign _083_ = $signed(32'd20) < $signed({ 26'h0000000, r[303:298] });
+ assign _084_ = _083_ ? 1'h1 : 1'h0;
+ assign _085_ = $signed(32'd21) < $signed({ 26'h0000000, r[303:298] });
+ assign _086_ = _085_ ? 1'h1 : 1'h0;
+ assign _087_ = $signed(32'd22) < $signed({ 26'h0000000, r[303:298] });
+ assign _088_ = _087_ ? 1'h1 : 1'h0;
+ assign _089_ = $signed(32'd23) < $signed({ 26'h0000000, r[303:298] });
+ assign _090_ = _089_ ? 1'h1 : 1'h0;
+ assign _091_ = $signed(32'd24) < $signed({ 26'h0000000, r[303:298] });
+ assign _092_ = _091_ ? 1'h1 : 1'h0;
+ assign _093_ = $signed(32'd25) < $signed({ 26'h0000000, r[303:298] });
+ assign _094_ = _093_ ? 1'h1 : 1'h0;
+ assign _095_ = $signed(32'd26) < $signed({ 26'h0000000, r[303:298] });
+ assign _096_ = _095_ ? 1'h1 : 1'h0;
+ assign _097_ = $signed(32'd27) < $signed({ 26'h0000000, r[303:298] });
+ assign _098_ = _097_ ? 1'h1 : 1'h0;
+ assign _099_ = $signed(32'd28) < $signed({ 26'h0000000, r[303:298] });
+ assign _100_ = _099_ ? 1'h1 : 1'h0;
+ assign _101_ = $signed(32'd29) < $signed({ 26'h0000000, r[303:298] });
+ assign _102_ = _101_ ? 1'h1 : 1'h0;
+ assign _103_ = $signed(32'd30) < $signed({ 26'h0000000, r[303:298] });
+ assign _104_ = _103_ ? 1'h1 : 1'h0;
+ assign _105_ = $signed(32'd31) < $signed({ 26'h0000000, r[303:298] });
+ assign _106_ = _105_ ? 1'h1 : 1'h0;
+ assign _107_ = $signed(32'd32) < $signed({ 26'h0000000, r[303:298] });
+ assign _108_ = _107_ ? 1'h1 : 1'h0;
+ assign _109_ = $signed(32'd33) < $signed({ 26'h0000000, r[303:298] });
+ assign _110_ = _109_ ? 1'h1 : 1'h0;
+ assign _111_ = $signed(32'd34) < $signed({ 26'h0000000, r[303:298] });
+ assign _112_ = _111_ ? 1'h1 : 1'h0;
+ assign _113_ = $signed(32'd35) < $signed({ 26'h0000000, r[303:298] });
+ assign _114_ = _113_ ? 1'h1 : 1'h0;
+ assign _115_ = $signed(32'd36) < $signed({ 26'h0000000, r[303:298] });
+ assign _116_ = _115_ ? 1'h1 : 1'h0;
+ assign _117_ = $signed(32'd37) < $signed({ 26'h0000000, r[303:298] });
+ assign _118_ = _117_ ? 1'h1 : 1'h0;
+ assign _119_ = $signed(32'd38) < $signed({ 26'h0000000, r[303:298] });
+ assign _120_ = _119_ ? 1'h1 : 1'h0;
+ assign _121_ = $signed(32'd39) < $signed({ 26'h0000000, r[303:298] });
+ assign _122_ = _121_ ? 1'h1 : 1'h0;
+ assign _123_ = $signed(32'd40) < $signed({ 26'h0000000, r[303:298] });
+ assign _124_ = _123_ ? 1'h1 : 1'h0;
+ assign _125_ = $signed(32'd41) < $signed({ 26'h0000000, r[303:298] });
+ assign _126_ = _125_ ? 1'h1 : 1'h0;
+ assign _127_ = $signed(32'd42) < $signed({ 26'h0000000, r[303:298] });
+ assign _128_ = _127_ ? 1'h1 : 1'h0;
+ assign _129_ = $signed(32'd43) < $signed({ 26'h0000000, r[303:298] });
+ assign _130_ = _129_ ? 1'h1 : 1'h0;
+ assign _131_ = ~ l_in[80];
+ assign _132_ = _131_ ? r[232] : r[297];
+ assign _133_ = _131_ ? r[231:168] : r[296:233];
+ assign _134_ = l_in[5] | l_in[4];
+ assign _135_ = ~ _134_;
+ assign _136_ = l_in[2] | l_in[28];
+ assign _137_ = _136_ | l_in[27];
+ assign _138_ = _137_ | l_in[24];
+ assign _139_ = _138_ | l_in[23];
+ assign _140_ = _139_ | l_in[22];
+ assign _141_ = _161_ ? 1'h0 : r[232];
+ assign _142_ = _153_ ? 1'h0 : r[297];
+ assign _143_ = ~ _132_;
+ assign _144_ = { 1'h0, _133_[4:0] } == 6'h00;
+ assign _145_ = _144_ ? 4'h8 : 4'h4;
+ assign _146_ = _144_ ? 1'h1 : 1'h0;
+ assign _147_ = _143_ ? 4'h2 : _145_;
+ assign _148_ = _143_ ? { 1'h0, r[72:68] } : { 1'h0, _133_[62:61], _133_[7:5] };
+ assign _149_ = _143_ ? 1'h0 : _146_;
+ assign _150_ = l_in[1] ? 1'h0 : 1'h1;
+ assign _151_ = l_in[1] ? 4'h1 : _147_;
+ assign _152_ = l_in[1] & l_in[10];
+ assign _153_ = l_in[1] & l_in[10];
+ assign _154_ = l_in[1] ? { 1'h0, _133_[62:61], _133_[7:5] } : _148_;
+ assign _155_ = l_in[1] ? 1'h0 : _149_;
+ assign _156_ = l_in[1] ? 1'h1 : 1'h0;
+ assign _157_ = l_in[1] ? 1'h1 : 1'h0;
+ assign _158_ = l_in[1] ? _140_ : 1'h0;
+ assign _159_ = l_in[0] ? { l_in[80:17], l_in[6], _135_, l_in[4], _150_ } : { r[67:1], 1'h0 };
+ assign _160_ = l_in[0] ? _151_ : r[167:164];
+ assign _161_ = l_in[0] & _152_;
+ assign _162_ = l_in[0] ? { _154_, _142_ } : { 1'h0, _133_[62:61], _133_[7:5], r[297] };
+ assign _163_ = l_in[0] ? _155_ : 1'h0;
+ assign _164_ = l_in[0] ? _156_ : 1'h0;
+ assign _165_ = l_in[0] ? _157_ : 1'h0;
+ assign _166_ = l_in[0] ? _158_ : 1'h0;
+ assign _167_ = ~ l_in[16];
+ assign _168_ = _167_ ? r[131:68] : l_in[144:81];
+ assign _169_ = _167_ ? l_in[112:81] : r[163:132];
+ assign _170_ = _167_ ? _162_[0] : 1'h0;
+ assign _171_ = l_in[3] ? { 4'h1, _169_, _168_ } : { _160_, r[163:68] };
+ assign _172_ = l_in[3] ? 1'h0 : _141_;
+ assign _173_ = l_in[3] ? _170_ : _162_[0];
+ assign _174_ = l_in[3] ? 1'h1 : _164_;
+ assign _175_ = l_in[3] ? 1'h1 : _165_;
+ assign _176_ = l_in[3] ? 1'h1 : _166_;
+ assign _177_ = r[167:164] == 4'h0;
+ assign _178_ = d_in[1] ? 4'h0 : r[167:164];
+ assign _179_ = d_in[1] ? 1'h1 : 1'h0;
+ assign _180_ = r[167:164] == 4'h1;
+ assign _181_ = r[167:164] == 4'h2;
+ assign _182_ = ~ d_in[2];
+ assign _183_ = r[67] ? r[232:168] : { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] };
+ assign _184_ = r[67] ? { 1'h1, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59] } : r[297:233];
+ assign _185_ = { 1'h0, d_in[63:59] } == 6'h00;
+ assign _186_ = _185_ ? 4'h8 : 4'h4;
+ assign _187_ = _190_ ? 1'h1 : 1'h0;
+ assign _188_ = _182_ ? _186_ : 4'h8;
+ assign _189_ = _182_ ? { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], 1'h0, d_in[9:8], d_in[66:64], _184_, _183_ } : r[364:168];
+ assign _190_ = _182_ & _185_;
+ assign _191_ = _182_ ? 1'h0 : 1'h1;
+ assign _192_ = d_in[1] ? { _189_, _188_ } : r[364:164];
+ assign _193_ = d_in[1] ? { _191_, _187_ } : 2'h0;
+ assign _194_ = r[167:164] == 4'h3;
+ assign _195_ = r[303:298] + 6'h13;
+ assign _196_ = _195_ - { 1'h0, r[308:304] };
+ assign _197_ = ~ { _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _198_ = r[65:35] & _197_;
+ assign _199_ = | _198_;
+ assign _200_ = r[67] != r[66];
+ assign _201_ = _200_ | _199_;
+ assign _202_ = { 1'h0, r[308:304] } < 6'h05;
+ assign _203_ = { 1'h0, r[308:304] } > 6'h10;
+ assign _204_ = _202_ | _203_;
+ assign _205_ = r[303:298] + 6'h13;
+ assign _206_ = { 1'h0, r[308:304] } > _205_;
+ assign _207_ = _204_ | _206_;
+ assign _208_ = _207_ ? 4'h8 : 4'h5;
+ assign _209_ = _207_ ? 1'h1 : 1'h0;
+ assign _210_ = _201_ ? 4'h8 : _208_;
+ assign _211_ = _201_ ? 1'h0 : _209_;
+ assign _212_ = _201_ ? 1'h1 : 1'h0;
+ assign _213_ = r[167:164] == 4'h4;
+ assign _214_ = r[167:164] == 4'h5;
+ assign _215_ = ~ d_in[2];
+ assign _216_ = ~ d_in[62];
+ assign _217_ = r[3] | _216_;
+ assign _218_ = ~ r[1];
+ assign _219_ = ~ r[2];
+ assign _220_ = d_in[61] & _219_;
+ assign _221_ = d_in[60] | _220_;
+ assign _222_ = ~ d_in[64];
+ assign _223_ = d_in[59] & _222_;
+ assign _224_ = _218_ ? _221_ : _223_;
+ assign _225_ = _217_ ? _224_ : 1'h0;
+ assign _226_ = ~ r[2];
+ assign _227_ = d_in[66] | _226_;
+ assign _228_ = d_in[51] & _227_;
+ assign _229_ = _225_ & _228_;
+ assign _230_ = ~ _225_;
+ assign _231_ = _229_ ? 4'h7 : 4'h8;
+ assign _232_ = _229_ ? 2'h0 : { _225_, _230_ };
+ assign _233_ = { 1'h0, d_in[63:59] } < 6'h05;
+ assign _234_ = { 1'h0, d_in[63:59] } > 6'h10;
+ assign _235_ = _233_ | _234_;
+ assign _236_ = { 1'h0, d_in[63:59] } > r[303:298];
+ assign _237_ = _235_ | _236_;
+ assign _238_ = r[303:298] - { 1'h0, d_in[63:59] };
+ assign _239_ = _237_ ? 4'h8 : 4'h5;
+ assign _240_ = _237_ ? r[364:298] : { d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], 8'h00, d_in[63:59], _238_ };
+ assign _241_ = _237_ ? 1'h1 : 1'h0;
+ assign _242_ = d_in[9] ? _231_ : _239_;
+ assign _243_ = d_in[9] ? r[364:298] : _240_;
+ assign _244_ = d_in[9] ? 1'h0 : _241_;
+ assign _245_ = d_in[9] ? _232_ : 2'h0;
+ assign _246_ = d_in[10] ? _242_ : 4'h8;
+ assign _247_ = d_in[10] ? _243_ : r[364:298];
+ assign _248_ = d_in[10] ? 1'h0 : 1'h1;
+ assign _249_ = d_in[10] ? _244_ : 1'h0;
+ assign _250_ = d_in[10] ? _245_ : 2'h0;
+ assign _251_ = _215_ ? _246_ : 4'h8;
+ assign _252_ = _215_ ? { _248_, d_in[10:3], d_in[18:11], d_in[26:19], d_in[34:27], d_in[42:35], d_in[50:43], d_in[58:51], d_in[66:59], _247_ } : { 1'h0, r[428:298] };
+ assign _253_ = _215_ ? _249_ : 1'h1;
+ assign _254_ = _215_ ? _250_ : 2'h0;
+ assign _255_ = d_in[1] ? _251_ : r[167:164];
+ assign _256_ = d_in[1] ? { _253_, _252_ } : { 2'h0, r[428:298] };
+ assign _257_ = d_in[1] ? _254_ : 2'h0;
+ assign _258_ = r[167:164] == 4'h6;
+ assign _259_ = ~ r[1];
+ assign _260_ = _259_ ? 4'h1 : 4'h0;
+ assign _261_ = _259_ ? 1'h1 : 1'h0;
+ assign _262_ = _259_ ? 1'h0 : 1'h1;
+ assign _263_ = _259_ ? 1'h0 : 1'h1;
+ assign _264_ = r[167:164] == 4'h7;
+ assign _265_ = r[167:164] == 4'h8;
+ function [67:0] \10776 ;
+ input [67:0] a;
+ input [611:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10776 = b[67:0];
+ 9'b???????1?:
+ \10776 = b[135:68];
+ 9'b??????1??:
+ \10776 = b[203:136];
+ 9'b?????1???:
+ \10776 = b[271:204];
+ 9'b????1????:
+ \10776 = b[339:272];
+ 9'b???1?????:
+ \10776 = b[407:340];
+ 9'b??1??????:
+ \10776 = b[475:408];
+ 9'b?1???????:
+ \10776 = b[543:476];
+ 9'b1????????:
+ \10776 = b[611:544];
+ default:
+ \10776 = a;
+ endcase
+ endfunction
+ assign _266_ = \10776 (68'hxxxxxxxxxxxxxxxxx, { r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, r[67:1], 1'h0, _159_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [95:0] \10780 ;
+ input [95:0] a;
+ input [863:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10780 = b[95:0];
+ 9'b???????1?:
+ \10780 = b[191:96];
+ 9'b??????1??:
+ \10780 = b[287:192];
+ 9'b?????1???:
+ \10780 = b[383:288];
+ 9'b????1????:
+ \10780 = b[479:384];
+ 9'b???1?????:
+ \10780 = b[575:480];
+ 9'b??1??????:
+ \10780 = b[671:576];
+ 9'b?1???????:
+ \10780 = b[767:672];
+ 9'b1????????:
+ \10780 = b[863:768];
+ default:
+ \10780 = a;
+ endcase
+ endfunction
+ assign _267_ = \10780 (96'hxxxxxxxxxxxxxxxxxxxxxxxx, { r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], r[163:68], _171_[95:0] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [3:0] \10784 ;
+ input [3:0] a;
+ input [35:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10784 = b[3:0];
+ 9'b???????1?:
+ \10784 = b[7:4];
+ 9'b??????1??:
+ \10784 = b[11:8];
+ 9'b?????1???:
+ \10784 = b[15:12];
+ 9'b????1????:
+ \10784 = b[19:16];
+ 9'b???1?????:
+ \10784 = b[23:20];
+ 9'b??1??????:
+ \10784 = b[27:24];
+ 9'b?1???????:
+ \10784 = b[31:28];
+ 9'b1????????:
+ \10784 = b[35:32];
+ default:
+ \10784 = a;
+ endcase
+ endfunction
+ assign _268_ = \10784 (4'hx, { 4'h0, _260_, _255_, 4'h6, _210_, _192_[3:0], 4'h3, _178_, _171_[99:96] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [63:0] \10788 ;
+ input [63:0] a;
+ input [575:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10788 = b[63:0];
+ 9'b???????1?:
+ \10788 = b[127:64];
+ 9'b??????1??:
+ \10788 = b[191:128];
+ 9'b?????1???:
+ \10788 = b[255:192];
+ 9'b????1????:
+ \10788 = b[319:256];
+ 9'b???1?????:
+ \10788 = b[383:320];
+ 9'b??1??????:
+ \10788 = b[447:384];
+ 9'b?1???????:
+ \10788 = b[511:448];
+ 9'b1????????:
+ \10788 = b[575:512];
+ default:
+ \10788 = a;
+ endcase
+ endfunction
+ assign _269_ = \10788 (64'hxxxxxxxxxxxxxxxx, { r[231:168], r[231:168], r[231:168], r[231:168], r[231:168], _192_[67:4], r[231:168], r[231:168], r[231:168] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10792 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10792 = b[0:0];
+ 9'b???????1?:
+ \10792 = b[1:1];
+ 9'b??????1??:
+ \10792 = b[2:2];
+ 9'b?????1???:
+ \10792 = b[3:3];
+ 9'b????1????:
+ \10792 = b[4:4];
+ 9'b???1?????:
+ \10792 = b[5:5];
+ 9'b??1??????:
+ \10792 = b[6:6];
+ 9'b?1???????:
+ \10792 = b[7:7];
+ 9'b1????????:
+ \10792 = b[8:8];
+ default:
+ \10792 = a;
+ endcase
+ endfunction
+ assign _270_ = \10792 (1'hx, { r[232], r[232], r[232], r[232], r[232], _192_[68], r[232], r[232], _172_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [63:0] \10796 ;
+ input [63:0] a;
+ input [575:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10796 = b[63:0];
+ 9'b???????1?:
+ \10796 = b[127:64];
+ 9'b??????1??:
+ \10796 = b[191:128];
+ 9'b?????1???:
+ \10796 = b[255:192];
+ 9'b????1????:
+ \10796 = b[319:256];
+ 9'b???1?????:
+ \10796 = b[383:320];
+ 9'b??1??????:
+ \10796 = b[447:384];
+ 9'b?1???????:
+ \10796 = b[511:448];
+ 9'b1????????:
+ \10796 = b[575:512];
+ default:
+ \10796 = a;
+ endcase
+ endfunction
+ assign _271_ = \10796 (64'hxxxxxxxxxxxxxxxx, { r[296:233], r[296:233], r[296:233], r[296:233], r[296:233], _192_[132:69], r[296:233], r[296:233], r[296:233] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10800 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10800 = b[0:0];
+ 9'b???????1?:
+ \10800 = b[1:1];
+ 9'b??????1??:
+ \10800 = b[2:2];
+ 9'b?????1???:
+ \10800 = b[3:3];
+ 9'b????1????:
+ \10800 = b[4:4];
+ 9'b???1?????:
+ \10800 = b[5:5];
+ 9'b??1??????:
+ \10800 = b[6:6];
+ 9'b?1???????:
+ \10800 = b[7:7];
+ 9'b1????????:
+ \10800 = b[8:8];
+ default:
+ \10800 = a;
+ endcase
+ endfunction
+ assign _272_ = \10800 (1'hx, { r[297], r[297], r[297], r[297], r[297], _192_[133], r[297], r[297], _173_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [5:0] \10805 ;
+ input [5:0] a;
+ input [53:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10805 = b[5:0];
+ 9'b???????1?:
+ \10805 = b[11:6];
+ 9'b??????1??:
+ \10805 = b[17:12];
+ 9'b?????1???:
+ \10805 = b[23:18];
+ 9'b????1????:
+ \10805 = b[29:24];
+ 9'b???1?????:
+ \10805 = b[35:30];
+ 9'b??1??????:
+ \10805 = b[41:36];
+ 9'b?1???????:
+ \10805 = b[47:42];
+ 9'b1????????:
+ \10805 = b[53:48];
+ default:
+ \10805 = a;
+ endcase
+ endfunction
+ assign _273_ = \10805 (6'hxx, { r[303:298], r[303:298], _256_[5:0], r[303:298], _196_, _192_[139:134], r[303:298], r[303:298], _162_[6:1] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [4:0] \10810 ;
+ input [4:0] a;
+ input [44:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10810 = b[4:0];
+ 9'b???????1?:
+ \10810 = b[9:5];
+ 9'b??????1??:
+ \10810 = b[14:10];
+ 9'b?????1???:
+ \10810 = b[19:15];
+ 9'b????1????:
+ \10810 = b[24:20];
+ 9'b???1?????:
+ \10810 = b[29:25];
+ 9'b??1??????:
+ \10810 = b[34:30];
+ 9'b?1???????:
+ \10810 = b[39:35];
+ 9'b1????????:
+ \10810 = b[44:40];
+ default:
+ \10810 = a;
+ endcase
+ endfunction
+ assign _274_ = \10810 (5'hxx, { r[308:304], r[308:304], _256_[10:6], r[308:304], r[308:304], _192_[144:140], r[308:304], r[308:304], _133_[4:0] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [55:0] \10815 ;
+ input [55:0] a;
+ input [503:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10815 = b[55:0];
+ 9'b???????1?:
+ \10815 = b[111:56];
+ 9'b??????1??:
+ \10815 = b[167:112];
+ 9'b?????1???:
+ \10815 = b[223:168];
+ 9'b????1????:
+ \10815 = b[279:224];
+ 9'b???1?????:
+ \10815 = b[335:280];
+ 9'b??1??????:
+ \10815 = b[391:336];
+ 9'b?1???????:
+ \10815 = b[447:392];
+ 9'b1????????:
+ \10815 = b[503:448];
+ default:
+ \10815 = a;
+ endcase
+ endfunction
+ assign _275_ = \10815 (56'hxxxxxxxxxxxxxx, { r[364:309], r[364:309], _256_[66:11], r[364:309], r[364:309], _192_[200:145], r[364:309], r[364:309], _133_[55:8], 8'h00 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [63:0] \10819 ;
+ input [63:0] a;
+ input [575:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10819 = b[63:0];
+ 9'b???????1?:
+ \10819 = b[127:64];
+ 9'b??????1??:
+ \10819 = b[191:128];
+ 9'b?????1???:
+ \10819 = b[255:192];
+ 9'b????1????:
+ \10819 = b[319:256];
+ 9'b???1?????:
+ \10819 = b[383:320];
+ 9'b??1??????:
+ \10819 = b[447:384];
+ 9'b?1???????:
+ \10819 = b[511:448];
+ 9'b1????????:
+ \10819 = b[575:512];
+ default:
+ \10819 = a;
+ endcase
+ endfunction
+ assign _276_ = \10819 (64'hxxxxxxxxxxxxxxxx, { r[428:365], r[428:365], _256_[130:67], r[428:365], r[428:365], r[428:365], r[428:365], r[428:365], r[428:365] }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10823 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10823 = b[0:0];
+ 9'b???????1?:
+ \10823 = b[1:1];
+ 9'b??????1??:
+ \10823 = b[2:2];
+ 9'b?????1???:
+ \10823 = b[3:3];
+ 9'b????1????:
+ \10823 = b[4:4];
+ 9'b???1?????:
+ \10823 = b[5:5];
+ 9'b??1??????:
+ \10823 = b[6:6];
+ 9'b?1???????:
+ \10823 = b[7:7];
+ 9'b1????????:
+ \10823 = b[8:8];
+ default:
+ \10823 = a;
+ endcase
+ endfunction
+ assign _277_ = \10823 (1'hx, { 2'h0, _256_[131], 2'h0, _193_[0], 2'h0, _163_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10827 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10827 = b[0:0];
+ 9'b???????1?:
+ \10827 = b[1:1];
+ 9'b??????1??:
+ \10827 = b[2:2];
+ 9'b?????1???:
+ \10827 = b[3:3];
+ 9'b????1????:
+ \10827 = b[4:4];
+ 9'b???1?????:
+ \10827 = b[5:5];
+ 9'b??1??????:
+ \10827 = b[6:6];
+ 9'b?1???????:
+ \10827 = b[7:7];
+ 9'b1????????:
+ \10827 = b[8:8];
+ default:
+ \10827 = a;
+ endcase
+ endfunction
+ assign _278_ = \10827 (1'hx, { 2'h0, _256_[132], 1'h0, _211_, _193_[1], 3'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10829 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10829 = b[0:0];
+ 9'b???????1?:
+ \10829 = b[1:1];
+ 9'b??????1??:
+ \10829 = b[2:2];
+ 9'b?????1???:
+ \10829 = b[3:3];
+ 9'b????1????:
+ \10829 = b[4:4];
+ 9'b???1?????:
+ \10829 = b[5:5];
+ 9'b??1??????:
+ \10829 = b[6:6];
+ 9'b?1???????:
+ \10829 = b[7:7];
+ 9'b1????????:
+ \10829 = b[8:8];
+ default:
+ \10829 = a;
+ endcase
+ endfunction
+ assign _279_ = \10829 (1'hx, { 4'h0, _212_, 4'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [1:0] \10832 ;
+ input [1:0] a;
+ input [17:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10832 = b[1:0];
+ 9'b???????1?:
+ \10832 = b[3:2];
+ 9'b??????1??:
+ \10832 = b[5:4];
+ 9'b?????1???:
+ \10832 = b[7:6];
+ 9'b????1????:
+ \10832 = b[9:8];
+ 9'b???1?????:
+ \10832 = b[11:10];
+ 9'b??1??????:
+ \10832 = b[13:12];
+ 9'b?1???????:
+ \10832 = b[15:14];
+ 9'b1????????:
+ \10832 = b[17:16];
+ default:
+ \10832 = a;
+ endcase
+ endfunction
+ assign _280_ = \10832 (2'hx, { 4'h0, _257_, 12'h000 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10847 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10847 = b[0:0];
+ 9'b???????1?:
+ \10847 = b[1:1];
+ 9'b??????1??:
+ \10847 = b[2:2];
+ 9'b?????1???:
+ \10847 = b[3:3];
+ 9'b????1????:
+ \10847 = b[4:4];
+ 9'b???1?????:
+ \10847 = b[5:5];
+ 9'b??1??????:
+ \10847 = b[6:6];
+ 9'b?1???????:
+ \10847 = b[7:7];
+ 9'b1????????:
+ \10847 = b[8:8];
+ default:
+ \10847 = a;
+ endcase
+ endfunction
+ assign _281_ = \10847 (1'hx, { 1'h0, _261_, 6'h12, _174_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10852 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10852 = b[0:0];
+ 9'b???????1?:
+ \10852 = b[1:1];
+ 9'b??????1??:
+ \10852 = b[2:2];
+ 9'b?????1???:
+ \10852 = b[3:3];
+ 9'b????1????:
+ \10852 = b[4:4];
+ 9'b???1?????:
+ \10852 = b[5:5];
+ 9'b??1??????:
+ \10852 = b[6:6];
+ 9'b?1???????:
+ \10852 = b[7:7];
+ 9'b1????????:
+ \10852 = b[8:8];
+ default:
+ \10852 = a;
+ endcase
+ endfunction
+ assign _282_ = \10852 (1'hx, { 1'h1, _262_, 5'h00, _179_, 1'h0 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10857 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10857 = b[0:0];
+ 9'b???????1?:
+ \10857 = b[1:1];
+ 9'b??????1??:
+ \10857 = b[2:2];
+ 9'b?????1???:
+ \10857 = b[3:3];
+ 9'b????1????:
+ \10857 = b[4:4];
+ 9'b???1?????:
+ \10857 = b[5:5];
+ 9'b??1??????:
+ \10857 = b[6:6];
+ 9'b?1???????:
+ \10857 = b[7:7];
+ 9'b1????????:
+ \10857 = b[8:8];
+ default:
+ \10857 = a;
+ endcase
+ endfunction
+ assign _283_ = \10857 (1'hx, 9'h080, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10861 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10861 = b[0:0];
+ 9'b???????1?:
+ \10861 = b[1:1];
+ 9'b??????1??:
+ \10861 = b[2:2];
+ 9'b?????1???:
+ \10861 = b[3:3];
+ 9'b????1????:
+ \10861 = b[4:4];
+ 9'b???1?????:
+ \10861 = b[5:5];
+ 9'b??1??????:
+ \10861 = b[6:6];
+ 9'b?1???????:
+ \10861 = b[7:7];
+ 9'b1????????:
+ \10861 = b[8:8];
+ default:
+ \10861 = a;
+ endcase
+ endfunction
+ assign _284_ = \10861 (1'hx, { 1'h0, _263_, 7'h00 }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10865 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10865 = b[0:0];
+ 9'b???????1?:
+ \10865 = b[1:1];
+ 9'b??????1??:
+ \10865 = b[2:2];
+ 9'b?????1???:
+ \10865 = b[3:3];
+ 9'b????1????:
+ \10865 = b[4:4];
+ 9'b???1?????:
+ \10865 = b[5:5];
+ 9'b??1??????:
+ \10865 = b[6:6];
+ 9'b?1???????:
+ \10865 = b[7:7];
+ 9'b1????????:
+ \10865 = b[8:8];
+ default:
+ \10865 = a;
+ endcase
+ endfunction
+ assign _285_ = \10865 (1'hx, { 8'h00, _175_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10869 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10869 = b[0:0];
+ 9'b???????1?:
+ \10869 = b[1:1];
+ 9'b??????1??:
+ \10869 = b[2:2];
+ 9'b?????1???:
+ \10869 = b[3:3];
+ 9'b????1????:
+ \10869 = b[4:4];
+ 9'b???1?????:
+ \10869 = b[5:5];
+ 9'b??1??????:
+ \10869 = b[6:6];
+ 9'b?1???????:
+ \10869 = b[7:7];
+ 9'b1????????:
+ \10869 = b[8:8];
+ default:
+ \10869 = a;
+ endcase
+ endfunction
+ assign _286_ = \10869 (1'hx, { 8'h00, _176_ }, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ function [0:0] \10874 ;
+ input [0:0] a;
+ input [8:0] b;
+ input [8:0] s;
+ (* parallel_case *)
+ casez (s)
+ 9'b????????1:
+ \10874 = b[0:0];
+ 9'b???????1?:
+ \10874 = b[1:1];
+ 9'b??????1??:
+ \10874 = b[2:2];
+ 9'b?????1???:
+ \10874 = b[3:3];
+ 9'b????1????:
+ \10874 = b[4:4];
+ 9'b???1?????:
+ \10874 = b[5:5];
+ 9'b??1??????:
+ \10874 = b[6:6];
+ 9'b?1???????:
+ \10874 = b[7:7];
+ 9'b1????????:
+ \10874 = b[8:8];
+ default:
+ \10874 = a;
+ endcase
+ endfunction
+ assign _287_ = \10874 (1'hx, 9'h004, { _265_, _264_, _258_, _214_, _213_, _194_, _181_, _180_, _177_ });
+ assign _288_ = r[67] ? 32'd0 : r[163:132];
+ assign _289_ = ~ { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _290_ = r[103:80] & _289_;
+ assign _291_ = _288_[31:8] & { _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _292_ = _290_ | _291_;
+ assign _293_ = ~ { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
+ assign _294_ = r[327:312] & _293_;
+ assign _295_ = addrsh & { _042_, _040_, _038_, _036_, _034_, _032_, _030_, _028_, _026_, _024_, _022_, 5'h1f };
+ assign _296_ = _294_ | _295_;
+ assign _297_ = ~ { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _298_ = r[420:377] & _297_;
+ assign _299_ = r[59:16] & { _130_, _128_, _126_, _124_, _122_, _120_, _118_, _116_, _114_, _112_, _110_, _108_, _106_, _104_, _102_, _100_, _098_, _096_, _094_, _092_, _090_, _088_, _086_, _084_, _082_, _080_, _078_, _076_, _074_, _072_, _070_, _068_, _066_, _064_, _062_, _060_, _058_, _056_, _054_, _052_, _050_, _048_, _046_, _044_ };
+ assign _300_ = _298_ | _299_;
+ assign _301_ = _287_ ? { 8'h00, r[123:104], _292_, _288_[7:0], 4'h0 } : { 8'h00, r[364:328], _296_, 3'h0 };
+ assign _302_ = _283_ ? { 8'h00, _300_, r[376:365] } : 64'h0000000000000000;
+ assign _303_ = _283_ ? { r[67:16], 12'h000 } : _301_;
+ assign _304_ = _285_ ? l_in[144:81] : _302_;
+ assign _305_ = _285_ ? l_in[80:17] : _303_;
+ assign _000_ = l_in[16] ? r[131:68] : { 32'h00000000, r[163:132] };
+ assign _001_ = rst ? 1'h0 : _266_[0];
+ assign _002_ = rst ? r[67:1] : _266_[67:1];
+ assign _003_ = rst ? 64'h0000000000000000 : _267_[63:0];
+ assign _004_ = rst ? r[163:132] : _267_[95:64];
+ assign _005_ = rst ? 4'h0 : _268_;
+ assign _006_ = rst ? r[231:168] : _269_;
+ assign _007_ = rst ? 1'h0 : _270_;
+ assign _008_ = rst ? r[296:233] : _271_;
+ assign _009_ = rst ? 1'h0 : _272_;
+ assign _010_ = rst ? r[433:298] : { _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_ };
+ always @(posedge clk)
+ r <= { _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
+ assign _011_ = r[303:302] == 2'h0;
+ assign _012_ = r[303:302] == 2'h1;
+ function [30:0] \9811 ;
+ input [30:0] a;
+ input [61:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \9811 = b[30:0];
+ 2'b1?:
+ \9811 = b[61:31];
+ default:
+ \9811 = a;
+ endcase
+ endfunction
+ assign _013_ = \9811 ({ 13'h0000, r[65:48] }, { r[62:32], r[46:16] }, { _012_, _011_ });
+ assign _014_ = r[301:300] == 2'h0;
+ assign _015_ = r[301:300] == 2'h1;
+ assign _016_ = r[301:300] == 2'h2;
+ function [18:0] \9824 ;
+ input [18:0] a;
+ input [56:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \9824 = b[18:0];
+ 3'b?1?:
+ \9824 = b[37:19];
+ 3'b1??:
+ \9824 = b[56:38];
+ default:
+ \9824 = a;
+ endcase
+ endfunction
+ assign _017_ = \9824 (_013_[30:12], { _013_[26:8], _013_[22:4], _013_[18:0] }, { _016_, _015_, _014_ });
+ assign _018_ = r[299:298] == 2'h0;
+ assign _019_ = r[299:298] == 2'h1;
+ assign _020_ = r[299:298] == 2'h2;
+ function [15:0] \9837 ;
+ input [15:0] a;
+ input [47:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \9837 = b[15:0];
+ 3'b?1?:
+ \9837 = b[31:16];
+ 3'b1??:
+ \9837 = b[47:32];
+ default:
+ \9837 = a;
+ endcase
+ endfunction
+ assign addrsh = \9837 (_017_[18:3], { _017_[17:2], _017_[16:1], _017_[15:0] }, { _020_, _019_, _018_ });
+ assign _021_ = $signed(32'd5) < $signed({ 27'h0000000, r[308:304] });
+ assign _022_ = _021_ ? 1'h1 : 1'h0;
+ assign _023_ = $signed(32'd6) < $signed({ 27'h0000000, r[308:304] });
+ assign _024_ = _023_ ? 1'h1 : 1'h0;
+ assign _025_ = $signed(32'd7) < $signed({ 27'h0000000, r[308:304] });
+ assign _026_ = _025_ ? 1'h1 : 1'h0;
+ assign _027_ = $signed(32'd8) < $signed({ 27'h0000000, r[308:304] });
+ assign _028_ = _027_ ? 1'h1 : 1'h0;
+ assign _029_ = $signed(32'd9) < $signed({ 27'h0000000, r[308:304] });
+ assign _030_ = _029_ ? 1'h1 : 1'h0;
+ assign _031_ = $signed(32'd10) < $signed({ 27'h0000000, r[308:304] });
+ assign _032_ = _031_ ? 1'h1 : 1'h0;
+ assign _033_ = $signed(32'd11) < $signed({ 27'h0000000, r[308:304] });
+ assign _034_ = _033_ ? 1'h1 : 1'h0;
+ assign _035_ = $signed(32'd12) < $signed({ 27'h0000000, r[308:304] });
+ assign _036_ = _035_ ? 1'h1 : 1'h0;
+ assign _037_ = $signed(32'd13) < $signed({ 27'h0000000, r[308:304] });
+ assign _038_ = _037_ ? 1'h1 : 1'h0;
+ assign _039_ = $signed(32'd14) < $signed({ 27'h0000000, r[308:304] });
+ assign _040_ = _039_ ? 1'h1 : 1'h0;
+ assign _041_ = $signed(32'd15) < $signed({ 27'h0000000, r[308:304] });
+ assign _042_ = _041_ ? 1'h1 : 1'h0;
+ assign _043_ = $signed(32'd0) < $signed({ 26'h0000000, r[303:298] });
+ assign _044_ = _043_ ? 1'h1 : 1'h0;
+ assign _045_ = $signed(32'd1) < $signed({ 26'h0000000, r[303:298] });
+ assign _046_ = _045_ ? 1'h1 : 1'h0;
+ assign _047_ = $signed(32'd2) < $signed({ 26'h0000000, r[303:298] });
+ assign _048_ = _047_ ? 1'h1 : 1'h0;
+ assign _049_ = $signed(32'd3) < $signed({ 26'h0000000, r[303:298] });
+ assign _050_ = _049_ ? 1'h1 : 1'h0;
+ assign _051_ = $signed(32'd4) < $signed({ 26'h0000000, r[303:298] });
+ assign _052_ = _051_ ? 1'h1 : 1'h0;
+ assign _053_ = $signed(32'd5) < $signed({ 26'h0000000, r[303:298] });
+ assign _054_ = _053_ ? 1'h1 : 1'h0;
+ assign l_out = { _000_, r[433:429], _282_ };
+ assign d_out = { _304_, _305_, _283_, _286_, _285_, _281_ };
+ assign i_out = { _304_, _305_, _286_, _285_, _284_ };
+endmodule
+
+module multiply_16(clk, m_in, m_out);
+ wire [129:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire [63:0] _13_;
+ wire _14_;
+ wire _15_;
+ input clk;
+ reg [137:0] m;
+ input [137:0] m_in;
+ output [65:0] m_out;
+ reg [2207:0] r = 2208'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ always @(posedge clk)
+ m <= m_in;
+ always @(posedge clk)
+ r <= { m[137], _00_, m[6:0], r[2207:138] };
+ assign _00_ = $signed({ m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71:7] }) * $signed({ m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136:72] });
+ assign _01_ = | r[208:176];
+ assign _02_ = & r[208:176];
+ assign _03_ = ~ _02_;
+ assign _04_ = _01_ & _03_;
+ assign _05_ = | r[272:208];
+ assign _06_ = & r[272:208];
+ assign _07_ = ~ _06_;
+ assign _08_ = _05_ & _07_;
+ assign _09_ = r[275] ? _04_ : _08_;
+ assign _10_ = r[144:139] == 6'h2b;
+ assign _11_ = r[144:139] == 6'h2d;
+ assign _12_ = r[144:139] == 6'h2c;
+ function [63:0] \20145 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20145 = b[63:0];
+ 3'b?1?:
+ \20145 = b[127:64];
+ 3'b1??:
+ \20145 = b[191:128];
+ default:
+ \20145 = a;
+ endcase
+ endfunction
+ assign _13_ = \20145 (64'h0000000000000000, { r[272:177], r[208:177], r[208:145] }, { _12_, _11_, _10_ });
+ function [0:0] \20147 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \20147 = b[0:0];
+ 3'b?1?:
+ \20147 = b[1:1];
+ 3'b1??:
+ \20147 = b[2:2];
+ default:
+ \20147 = a;
+ endcase
+ endfunction
+ assign _14_ = \20147 (1'h0, { 2'h0, _09_ }, { _12_, _11_, _10_ });
+ assign _15_ = r[138] ? 1'h1 : 1'h0;
+ assign m_out = { _14_, _13_, _15_ };
+endmodule
+
+module plru_1(clk, rst, acc, acc_en, lru);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire [1:0] _3_;
+ wire [1:0] _4_;
+ wire _5_;
+ wire _6_;
+ wire _7_;
+ wire _8_;
+ input acc;
+ input acc_en;
+ input clk;
+ output lru;
+ input rst;
+ reg [1:0] tree;
+ assign _0_ = 1'h1 - 1'h0;
+ assign _1_ = 1'h1 - 1'h0;
+ assign _2_ = ~ acc;
+ assign _3_ = acc_en ? { _8_, _7_ } : tree;
+ assign _4_ = rst ? 2'h0 : _3_;
+ always @(posedge clk)
+ tree <= _4_;
+ assign _5_ = _0_ ? tree[1] : tree[0];
+ assign _6_ = ~ _1_;
+ assign _7_ = _6_ ? _2_ : tree[0];
+ assign _8_ = _1_ ? _2_ : tree[1];
+ assign lru = _5_;
+endmodule
+
+module register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, dbg_gpr_req, dbg_gpr_addr, sim_dump, d_out, dbg_gpr_ack, dbg_gpr_data, sim_dump_done);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ reg _03_ = 1'h1;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire [5:0] _08_;
+ wire _09_;
+ wire [63:0] _10_;
+ wire _11_;
+ wire [63:0] _12_;
+ wire _13_;
+ wire [63:0] _14_;
+ wire [191:0] _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire [63:0] _22_;
+ wire [4095:0] _23_;
+ wire [63:0] _24_;
+ wire [4095:0] _25_;
+ wire [4095:0] _26_;
+ wire [63:0] _27_;
+ input clk;
+ input [19:0] d_in;
+ output [191:0] d_out;
+ reg dbg_ack;
+ reg [63:0] dbg_data;
+ output dbg_gpr_ack;
+ input [5:0] dbg_gpr_addr;
+ output [63:0] dbg_gpr_data;
+ input dbg_gpr_req;
+ wire [63:0] rd_port_b;
+ input sim_dump;
+ output sim_dump_done;
+ input [70:0] w_in;
+ reg [63:0] \$mem$\4359 [63:0];
+ assign _00_ = ~ _02_;
+ assign _01_ = _00_ | 1'h1;
+ assign _02_ = w_in[70] ? 1'h1 : 1'h0;
+ always @(posedge clk)
+ _03_ <= _01_;
+ assign _04_ = ~ d_in[7];
+ assign _05_ = _04_ & dbg_gpr_req;
+ assign _06_ = ~ dbg_ack;
+ assign _07_ = _05_ & _06_;
+ assign _08_ = _07_ ? dbg_gpr_addr : d_in[13:8];
+ assign _09_ = d_in[6:1] == w_in[5:0];
+ assign _10_ = _09_ ? w_in[69:6] : _27_;
+ assign _11_ = d_in[13:8] == w_in[5:0];
+ assign _12_ = _11_ ? w_in[69:6] : rd_port_b;
+ assign _13_ = { 1'h0, d_in[19:15] } == w_in[5:0];
+ assign _14_ = _13_ ? w_in[69:6] : _24_;
+ assign _15_ = w_in[70] ? { _14_, _12_, _10_ } : { _24_, rd_port_b, _27_ };
+ assign _16_ = ~ d_in[7];
+ assign _17_ = ~ dbg_ack;
+ assign _18_ = _16_ & _17_;
+ assign _19_ = _18_ ? 1'h1 : dbg_ack;
+ assign _20_ = dbg_gpr_req & _18_;
+ assign _21_ = dbg_gpr_req ? _19_ : 1'h0;
+ assign _22_ = _20_ ? rd_port_b : dbg_data;
+ always @(posedge clk)
+ dbg_data <= _22_;
+ always @(posedge clk)
+ dbg_ack <= _21_;
+ reg [63:0] \4359 [63:0];
+ initial begin
+ \4359 [0] = 64'h0000000000000000;
+ \4359 [1] = 64'h0000000000000000;
+ \4359 [2] = 64'h0000000000000000;
+ \4359 [3] = 64'h0000000000000000;
+ \4359 [4] = 64'h0000000000000000;
+ \4359 [5] = 64'h0000000000000000;
+ \4359 [6] = 64'h0000000000000000;
+ \4359 [7] = 64'h0000000000000000;
+ \4359 [8] = 64'h0000000000000000;
+ \4359 [9] = 64'h0000000000000000;
+ \4359 [10] = 64'h0000000000000000;
+ \4359 [11] = 64'h0000000000000000;
+ \4359 [12] = 64'h0000000000000000;
+ \4359 [13] = 64'h0000000000000000;
+ \4359 [14] = 64'h0000000000000000;
+ \4359 [15] = 64'h0000000000000000;
+ \4359 [16] = 64'h0000000000000000;
+ \4359 [17] = 64'h0000000000000000;
+ \4359 [18] = 64'h0000000000000000;
+ \4359 [19] = 64'h0000000000000000;
+ \4359 [20] = 64'h0000000000000000;
+ \4359 [21] = 64'h0000000000000000;
+ \4359 [22] = 64'h0000000000000000;
+ \4359 [23] = 64'h0000000000000000;
+ \4359 [24] = 64'h0000000000000000;
+ \4359 [25] = 64'h0000000000000000;
+ \4359 [26] = 64'h0000000000000000;
+ \4359 [27] = 64'h0000000000000000;
+ \4359 [28] = 64'h0000000000000000;
+ \4359 [29] = 64'h0000000000000000;
+ \4359 [30] = 64'h0000000000000000;
+ \4359 [31] = 64'h0000000000000000;
+ \4359 [32] = 64'h0000000000000000;
+ \4359 [33] = 64'h0000000000000000;
+ \4359 [34] = 64'h0000000000000000;
+ \4359 [35] = 64'h0000000000000000;
+ \4359 [36] = 64'h0000000000000000;
+ \4359 [37] = 64'h0000000000000000;
+ \4359 [38] = 64'h0000000000000000;
+ \4359 [39] = 64'h0000000000000000;
+ \4359 [40] = 64'h0000000000000000;
+ \4359 [41] = 64'h0000000000000000;
+ \4359 [42] = 64'h0000000000000000;
+ \4359 [43] = 64'h0000000000000000;
+ \4359 [44] = 64'h0000000000000000;
+ \4359 [45] = 64'h0000000000000000;
+ \4359 [46] = 64'h0000000000000000;
+ \4359 [47] = 64'h0000000000000000;
+ \4359 [48] = 64'h0000000000000000;
+ \4359 [49] = 64'h0000000000000000;
+ \4359 [50] = 64'h0000000000000000;
+ \4359 [51] = 64'h0000000000000000;
+ \4359 [52] = 64'h0000000000000000;
+ \4359 [53] = 64'h0000000000000000;
+ \4359 [54] = 64'h0000000000000000;
+ \4359 [55] = 64'h0000000000000000;
+ \4359 [56] = 64'h0000000000000000;
+ \4359 [57] = 64'h0000000000000000;
+ \4359 [58] = 64'h0000000000000000;
+ \4359 [59] = 64'h0000000000000000;
+ \4359 [60] = 64'h0000000000000000;
+ \4359 [61] = 64'h0000000000000000;
+ \4359 [62] = 64'h0000000000000000;
+ \4359 [63] = 64'h0000000000000000;
+ end
+ always @(posedge clk) begin
+ if (w_in[70]) \4359 [w_in[5:0]] <= w_in[69:6];
+ end
+ assign _24_ = \4359 [{ 1'h0, d_in[19:15] }];
+ assign rd_port_b = \4359 [_08_];
+ assign _27_ = \4359 [d_in[6:1]];
+ assign d_out = _15_;
+ assign dbg_gpr_ack = dbg_ack;
+ assign dbg_gpr_data = dbg_data;
+ assign sim_dump_done = 1'h0;
+endmodule
+
+module rotator(rs, ra, shift, insn, is_32bit, right_shift, arith, clear_left, clear_right, sign_ext_rs, result, carry_out);
+ wire [31:0] _000_;
+ wire [31:0] _001_;
+ wire [5:0] _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire [6:0] _014_;
+ wire _015_;
+ wire [6:0] _016_;
+ wire [6:0] _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire [5:0] _021_;
+ wire [6:0] _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire _259_;
+ wire _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire _270_;
+ wire _271_;
+ wire _272_;
+ wire _273_;
+ wire _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire _284_;
+ wire _285_;
+ wire _286_;
+ wire [63:0] _287_;
+ wire [63:0] _288_;
+ wire [63:0] _289_;
+ wire [63:0] _290_;
+ wire [63:0] _291_;
+ wire [63:0] _292_;
+ wire _293_;
+ wire [63:0] _294_;
+ wire [63:0] _295_;
+ wire [63:0] _296_;
+ wire [63:0] _297_;
+ wire [63:0] _298_;
+ wire [63:0] _299_;
+ wire _300_;
+ wire [63:0] _301_;
+ wire _302_;
+ wire [63:0] _303_;
+ wire [63:0] _304_;
+ wire [63:0] _305_;
+ wire _306_;
+ wire [63:0] _307_;
+ wire [63:0] _308_;
+ wire _309_;
+ wire _310_;
+ input arith;
+ output carry_out;
+ input clear_left;
+ input clear_right;
+ input [31:0] insn;
+ input is_32bit;
+ wire [6:0] mb;
+ wire [6:0] me;
+ wire [63:0] ml;
+ wire [1:0] output_mode;
+ input [63:0] ra;
+ output [63:0] result;
+ input right_shift;
+ wire [63:0] rot;
+ wire [63:0] rot1;
+ wire [63:0] rot2;
+ wire [5:0] rot_count;
+ input [63:0] rs;
+ input [6:0] shift;
+ input sign_ext_rs;
+ assign _000_ = sign_ext_rs ? { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] } : rs[63:32];
+ assign _001_ = is_32bit ? rs[31:0] : _000_;
+ assign _002_ = - $signed(shift[5:0]);
+ assign rot_count = right_shift ? _002_ : shift[5:0];
+ assign _003_ = rot_count[1:0] == 2'h0;
+ assign _004_ = rot_count[1:0] == 2'h1;
+ assign _005_ = rot_count[1:0] == 2'h2;
+ function [63:0] \18205 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \18205 = b[63:0];
+ 3'b?1?:
+ \18205 = b[127:64];
+ 3'b1??:
+ \18205 = b[191:128];
+ default:
+ \18205 = a;
+ endcase
+ endfunction
+ assign rot1 = \18205 ({ _001_[28:0], rs[31:0], _001_[31:29] }, { _001_[29:0], rs[31:0], _001_[31:30], _001_[30:0], rs[31:0], _001_[31], _001_, rs[31:0] }, { _005_, _004_, _003_ });
+ assign _006_ = rot_count[3:2] == 2'h0;
+ assign _007_ = rot_count[3:2] == 2'h1;
+ assign _008_ = rot_count[3:2] == 2'h2;
+ function [63:0] \18223 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \18223 = b[63:0];
+ 3'b?1?:
+ \18223 = b[127:64];
+ 3'b1??:
+ \18223 = b[191:128];
+ default:
+ \18223 = a;
+ endcase
+ endfunction
+ assign rot2 = \18223 ({ rot1[51:0], rot1[63:52] }, { rot1[55:0], rot1[63:56], rot1[59:0], rot1[63:60], rot1 }, { _008_, _007_, _006_ });
+ assign _009_ = rot_count[5:4] == 2'h0;
+ assign _010_ = rot_count[5:4] == 2'h1;
+ assign _011_ = rot_count[5:4] == 2'h2;
+ function [63:0] \18241 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \18241 = b[63:0];
+ 3'b?1?:
+ \18241 = b[127:64];
+ 3'b1??:
+ \18241 = b[191:128];
+ default:
+ \18241 = a;
+ endcase
+ endfunction
+ assign rot = \18241 ({ rot2[15:0], rot2[63:16] }, { rot2[31:0], rot2[63:32], rot2[47:0], rot2[63:48], rot2 }, { _011_, _010_, _009_ });
+ assign _012_ = ~ is_32bit;
+ assign _013_ = shift[6] & _012_;
+ assign _014_ = is_32bit ? { 2'h1, insn[10:6] } : { 1'h0, insn[5], insn[10:6] };
+ assign _015_ = ~ shift[5];
+ assign _016_ = is_32bit ? { shift[5], _015_, shift[4:0] } : { _013_, shift[5:0] };
+ assign _017_ = right_shift ? _016_ : { 1'h0, is_32bit, 5'h00 };
+ assign mb = clear_left ? _014_ : _017_;
+ assign _018_ = clear_right & is_32bit;
+ assign _019_ = ~ clear_left;
+ assign _020_ = clear_right & _019_;
+ assign _021_ = ~ shift[5:0];
+ assign _022_ = _020_ ? { 1'h0, insn[5], insn[10:6] } : { _013_, _021_ };
+ assign me = _018_ ? { 2'h1, insn[5:1] } : _022_;
+ assign _023_ = $signed(32'd0) >= $signed({ 25'h0000000, mb });
+ assign _024_ = _023_ ? 1'h1 : 1'h0;
+ assign _025_ = $signed(32'd1) >= $signed({ 25'h0000000, mb });
+ assign _026_ = _025_ ? 1'h1 : 1'h0;
+ assign _027_ = $signed(32'd2) >= $signed({ 25'h0000000, mb });
+ assign _028_ = _027_ ? 1'h1 : 1'h0;
+ assign _029_ = $signed(32'd3) >= $signed({ 25'h0000000, mb });
+ assign _030_ = _029_ ? 1'h1 : 1'h0;
+ assign _031_ = $signed(32'd4) >= $signed({ 25'h0000000, mb });
+ assign _032_ = _031_ ? 1'h1 : 1'h0;
+ assign _033_ = $signed(32'd5) >= $signed({ 25'h0000000, mb });
+ assign _034_ = _033_ ? 1'h1 : 1'h0;
+ assign _035_ = $signed(32'd6) >= $signed({ 25'h0000000, mb });
+ assign _036_ = _035_ ? 1'h1 : 1'h0;
+ assign _037_ = $signed(32'd7) >= $signed({ 25'h0000000, mb });
+ assign _038_ = _037_ ? 1'h1 : 1'h0;
+ assign _039_ = $signed(32'd8) >= $signed({ 25'h0000000, mb });
+ assign _040_ = _039_ ? 1'h1 : 1'h0;
+ assign _041_ = $signed(32'd9) >= $signed({ 25'h0000000, mb });
+ assign _042_ = _041_ ? 1'h1 : 1'h0;
+ assign _043_ = $signed(32'd10) >= $signed({ 25'h0000000, mb });
+ assign _044_ = _043_ ? 1'h1 : 1'h0;
+ assign _045_ = $signed(32'd11) >= $signed({ 25'h0000000, mb });
+ assign _046_ = _045_ ? 1'h1 : 1'h0;
+ assign _047_ = $signed(32'd12) >= $signed({ 25'h0000000, mb });
+ assign _048_ = _047_ ? 1'h1 : 1'h0;
+ assign _049_ = $signed(32'd13) >= $signed({ 25'h0000000, mb });
+ assign _050_ = _049_ ? 1'h1 : 1'h0;
+ assign _051_ = $signed(32'd14) >= $signed({ 25'h0000000, mb });
+ assign _052_ = _051_ ? 1'h1 : 1'h0;
+ assign _053_ = $signed(32'd15) >= $signed({ 25'h0000000, mb });
+ assign _054_ = _053_ ? 1'h1 : 1'h0;
+ assign _055_ = $signed(32'd16) >= $signed({ 25'h0000000, mb });
+ assign _056_ = _055_ ? 1'h1 : 1'h0;
+ assign _057_ = $signed(32'd17) >= $signed({ 25'h0000000, mb });
+ assign _058_ = _057_ ? 1'h1 : 1'h0;
+ assign _059_ = $signed(32'd18) >= $signed({ 25'h0000000, mb });
+ assign _060_ = _059_ ? 1'h1 : 1'h0;
+ assign _061_ = $signed(32'd19) >= $signed({ 25'h0000000, mb });
+ assign _062_ = _061_ ? 1'h1 : 1'h0;
+ assign _063_ = $signed(32'd20) >= $signed({ 25'h0000000, mb });
+ assign _064_ = _063_ ? 1'h1 : 1'h0;
+ assign _065_ = $signed(32'd21) >= $signed({ 25'h0000000, mb });
+ assign _066_ = _065_ ? 1'h1 : 1'h0;
+ assign _067_ = $signed(32'd22) >= $signed({ 25'h0000000, mb });
+ assign _068_ = _067_ ? 1'h1 : 1'h0;
+ assign _069_ = $signed(32'd23) >= $signed({ 25'h0000000, mb });
+ assign _070_ = _069_ ? 1'h1 : 1'h0;
+ assign _071_ = $signed(32'd24) >= $signed({ 25'h0000000, mb });
+ assign _072_ = _071_ ? 1'h1 : 1'h0;
+ assign _073_ = $signed(32'd25) >= $signed({ 25'h0000000, mb });
+ assign _074_ = _073_ ? 1'h1 : 1'h0;
+ assign _075_ = $signed(32'd26) >= $signed({ 25'h0000000, mb });
+ assign _076_ = _075_ ? 1'h1 : 1'h0;
+ assign _077_ = $signed(32'd27) >= $signed({ 25'h0000000, mb });
+ assign _078_ = _077_ ? 1'h1 : 1'h0;
+ assign _079_ = $signed(32'd28) >= $signed({ 25'h0000000, mb });
+ assign _080_ = _079_ ? 1'h1 : 1'h0;
+ assign _081_ = $signed(32'd29) >= $signed({ 25'h0000000, mb });
+ assign _082_ = _081_ ? 1'h1 : 1'h0;
+ assign _083_ = $signed(32'd30) >= $signed({ 25'h0000000, mb });
+ assign _084_ = _083_ ? 1'h1 : 1'h0;
+ assign _085_ = $signed(32'd31) >= $signed({ 25'h0000000, mb });
+ assign _086_ = _085_ ? 1'h1 : 1'h0;
+ assign _087_ = $signed(32'd32) >= $signed({ 25'h0000000, mb });
+ assign _088_ = _087_ ? 1'h1 : 1'h0;
+ assign _089_ = $signed(32'd33) >= $signed({ 25'h0000000, mb });
+ assign _090_ = _089_ ? 1'h1 : 1'h0;
+ assign _091_ = $signed(32'd34) >= $signed({ 25'h0000000, mb });
+ assign _092_ = _091_ ? 1'h1 : 1'h0;
+ assign _093_ = $signed(32'd35) >= $signed({ 25'h0000000, mb });
+ assign _094_ = _093_ ? 1'h1 : 1'h0;
+ assign _095_ = $signed(32'd36) >= $signed({ 25'h0000000, mb });
+ assign _096_ = _095_ ? 1'h1 : 1'h0;
+ assign _097_ = $signed(32'd37) >= $signed({ 25'h0000000, mb });
+ assign _098_ = _097_ ? 1'h1 : 1'h0;
+ assign _099_ = $signed(32'd38) >= $signed({ 25'h0000000, mb });
+ assign _100_ = _099_ ? 1'h1 : 1'h0;
+ assign _101_ = $signed(32'd39) >= $signed({ 25'h0000000, mb });
+ assign _102_ = _101_ ? 1'h1 : 1'h0;
+ assign _103_ = $signed(32'd40) >= $signed({ 25'h0000000, mb });
+ assign _104_ = _103_ ? 1'h1 : 1'h0;
+ assign _105_ = $signed(32'd41) >= $signed({ 25'h0000000, mb });
+ assign _106_ = _105_ ? 1'h1 : 1'h0;
+ assign _107_ = $signed(32'd42) >= $signed({ 25'h0000000, mb });
+ assign _108_ = _107_ ? 1'h1 : 1'h0;
+ assign _109_ = $signed(32'd43) >= $signed({ 25'h0000000, mb });
+ assign _110_ = _109_ ? 1'h1 : 1'h0;
+ assign _111_ = $signed(32'd44) >= $signed({ 25'h0000000, mb });
+ assign _112_ = _111_ ? 1'h1 : 1'h0;
+ assign _113_ = $signed(32'd45) >= $signed({ 25'h0000000, mb });
+ assign _114_ = _113_ ? 1'h1 : 1'h0;
+ assign _115_ = $signed(32'd46) >= $signed({ 25'h0000000, mb });
+ assign _116_ = _115_ ? 1'h1 : 1'h0;
+ assign _117_ = $signed(32'd47) >= $signed({ 25'h0000000, mb });
+ assign _118_ = _117_ ? 1'h1 : 1'h0;
+ assign _119_ = $signed(32'd48) >= $signed({ 25'h0000000, mb });
+ assign _120_ = _119_ ? 1'h1 : 1'h0;
+ assign _121_ = $signed(32'd49) >= $signed({ 25'h0000000, mb });
+ assign _122_ = _121_ ? 1'h1 : 1'h0;
+ assign _123_ = $signed(32'd50) >= $signed({ 25'h0000000, mb });
+ assign _124_ = _123_ ? 1'h1 : 1'h0;
+ assign _125_ = $signed(32'd51) >= $signed({ 25'h0000000, mb });
+ assign _126_ = _125_ ? 1'h1 : 1'h0;
+ assign _127_ = $signed(32'd52) >= $signed({ 25'h0000000, mb });
+ assign _128_ = _127_ ? 1'h1 : 1'h0;
+ assign _129_ = $signed(32'd53) >= $signed({ 25'h0000000, mb });
+ assign _130_ = _129_ ? 1'h1 : 1'h0;
+ assign _131_ = $signed(32'd54) >= $signed({ 25'h0000000, mb });
+ assign _132_ = _131_ ? 1'h1 : 1'h0;
+ assign _133_ = $signed(32'd55) >= $signed({ 25'h0000000, mb });
+ assign _134_ = _133_ ? 1'h1 : 1'h0;
+ assign _135_ = $signed(32'd56) >= $signed({ 25'h0000000, mb });
+ assign _136_ = _135_ ? 1'h1 : 1'h0;
+ assign _137_ = $signed(32'd57) >= $signed({ 25'h0000000, mb });
+ assign _138_ = _137_ ? 1'h1 : 1'h0;
+ assign _139_ = $signed(32'd58) >= $signed({ 25'h0000000, mb });
+ assign _140_ = _139_ ? 1'h1 : 1'h0;
+ assign _141_ = $signed(32'd59) >= $signed({ 25'h0000000, mb });
+ assign _142_ = _141_ ? 1'h1 : 1'h0;
+ assign _143_ = $signed(32'd60) >= $signed({ 25'h0000000, mb });
+ assign _144_ = _143_ ? 1'h1 : 1'h0;
+ assign _145_ = $signed(32'd61) >= $signed({ 25'h0000000, mb });
+ assign _146_ = _145_ ? 1'h1 : 1'h0;
+ assign _147_ = $signed(32'd62) >= $signed({ 25'h0000000, mb });
+ assign _148_ = _147_ ? 1'h1 : 1'h0;
+ assign _149_ = $signed(32'd63) >= $signed({ 25'h0000000, mb });
+ assign _150_ = _149_ ? 1'h1 : 1'h0;
+ assign _151_ = ~ me[6];
+ assign _152_ = $signed(32'd0) <= $signed({ 25'h0000000, me });
+ assign _153_ = _152_ ? 1'h1 : 1'h0;
+ assign _154_ = $signed(32'd1) <= $signed({ 25'h0000000, me });
+ assign _155_ = _154_ ? 1'h1 : 1'h0;
+ assign _156_ = $signed(32'd2) <= $signed({ 25'h0000000, me });
+ assign _157_ = _156_ ? 1'h1 : 1'h0;
+ assign _158_ = $signed(32'd3) <= $signed({ 25'h0000000, me });
+ assign _159_ = _158_ ? 1'h1 : 1'h0;
+ assign _160_ = $signed(32'd4) <= $signed({ 25'h0000000, me });
+ assign _161_ = _160_ ? 1'h1 : 1'h0;
+ assign _162_ = $signed(32'd5) <= $signed({ 25'h0000000, me });
+ assign _163_ = _162_ ? 1'h1 : 1'h0;
+ assign _164_ = $signed(32'd6) <= $signed({ 25'h0000000, me });
+ assign _165_ = _164_ ? 1'h1 : 1'h0;
+ assign _166_ = $signed(32'd7) <= $signed({ 25'h0000000, me });
+ assign _167_ = _166_ ? 1'h1 : 1'h0;
+ assign _168_ = $signed(32'd8) <= $signed({ 25'h0000000, me });
+ assign _169_ = _168_ ? 1'h1 : 1'h0;
+ assign _170_ = $signed(32'd9) <= $signed({ 25'h0000000, me });
+ assign _171_ = _170_ ? 1'h1 : 1'h0;
+ assign _172_ = $signed(32'd10) <= $signed({ 25'h0000000, me });
+ assign _173_ = _172_ ? 1'h1 : 1'h0;
+ assign _174_ = $signed(32'd11) <= $signed({ 25'h0000000, me });
+ assign _175_ = _174_ ? 1'h1 : 1'h0;
+ assign _176_ = $signed(32'd12) <= $signed({ 25'h0000000, me });
+ assign _177_ = _176_ ? 1'h1 : 1'h0;
+ assign _178_ = $signed(32'd13) <= $signed({ 25'h0000000, me });
+ assign _179_ = _178_ ? 1'h1 : 1'h0;
+ assign _180_ = $signed(32'd14) <= $signed({ 25'h0000000, me });
+ assign _181_ = _180_ ? 1'h1 : 1'h0;
+ assign _182_ = $signed(32'd15) <= $signed({ 25'h0000000, me });
+ assign _183_ = _182_ ? 1'h1 : 1'h0;
+ assign _184_ = $signed(32'd16) <= $signed({ 25'h0000000, me });
+ assign _185_ = _184_ ? 1'h1 : 1'h0;
+ assign _186_ = $signed(32'd17) <= $signed({ 25'h0000000, me });
+ assign _187_ = _186_ ? 1'h1 : 1'h0;
+ assign _188_ = $signed(32'd18) <= $signed({ 25'h0000000, me });
+ assign _189_ = _188_ ? 1'h1 : 1'h0;
+ assign _190_ = $signed(32'd19) <= $signed({ 25'h0000000, me });
+ assign _191_ = _190_ ? 1'h1 : 1'h0;
+ assign _192_ = $signed(32'd20) <= $signed({ 25'h0000000, me });
+ assign _193_ = _192_ ? 1'h1 : 1'h0;
+ assign _194_ = $signed(32'd21) <= $signed({ 25'h0000000, me });
+ assign _195_ = _194_ ? 1'h1 : 1'h0;
+ assign _196_ = $signed(32'd22) <= $signed({ 25'h0000000, me });
+ assign _197_ = _196_ ? 1'h1 : 1'h0;
+ assign _198_ = $signed(32'd23) <= $signed({ 25'h0000000, me });
+ assign _199_ = _198_ ? 1'h1 : 1'h0;
+ assign _200_ = $signed(32'd24) <= $signed({ 25'h0000000, me });
+ assign _201_ = _200_ ? 1'h1 : 1'h0;
+ assign _202_ = $signed(32'd25) <= $signed({ 25'h0000000, me });
+ assign _203_ = _202_ ? 1'h1 : 1'h0;
+ assign _204_ = $signed(32'd26) <= $signed({ 25'h0000000, me });
+ assign _205_ = _204_ ? 1'h1 : 1'h0;
+ assign _206_ = $signed(32'd27) <= $signed({ 25'h0000000, me });
+ assign _207_ = _206_ ? 1'h1 : 1'h0;
+ assign _208_ = $signed(32'd28) <= $signed({ 25'h0000000, me });
+ assign _209_ = _208_ ? 1'h1 : 1'h0;
+ assign _210_ = $signed(32'd29) <= $signed({ 25'h0000000, me });
+ assign _211_ = _210_ ? 1'h1 : 1'h0;
+ assign _212_ = $signed(32'd30) <= $signed({ 25'h0000000, me });
+ assign _213_ = _212_ ? 1'h1 : 1'h0;
+ assign _214_ = $signed(32'd31) <= $signed({ 25'h0000000, me });
+ assign _215_ = _214_ ? 1'h1 : 1'h0;
+ assign _216_ = $signed(32'd32) <= $signed({ 25'h0000000, me });
+ assign _217_ = _216_ ? 1'h1 : 1'h0;
+ assign _218_ = $signed(32'd33) <= $signed({ 25'h0000000, me });
+ assign _219_ = _218_ ? 1'h1 : 1'h0;
+ assign _220_ = $signed(32'd34) <= $signed({ 25'h0000000, me });
+ assign _221_ = _220_ ? 1'h1 : 1'h0;
+ assign _222_ = $signed(32'd35) <= $signed({ 25'h0000000, me });
+ assign _223_ = _222_ ? 1'h1 : 1'h0;
+ assign _224_ = $signed(32'd36) <= $signed({ 25'h0000000, me });
+ assign _225_ = _224_ ? 1'h1 : 1'h0;
+ assign _226_ = $signed(32'd37) <= $signed({ 25'h0000000, me });
+ assign _227_ = _226_ ? 1'h1 : 1'h0;
+ assign _228_ = $signed(32'd38) <= $signed({ 25'h0000000, me });
+ assign _229_ = _228_ ? 1'h1 : 1'h0;
+ assign _230_ = $signed(32'd39) <= $signed({ 25'h0000000, me });
+ assign _231_ = _230_ ? 1'h1 : 1'h0;
+ assign _232_ = $signed(32'd40) <= $signed({ 25'h0000000, me });
+ assign _233_ = _232_ ? 1'h1 : 1'h0;
+ assign _234_ = $signed(32'd41) <= $signed({ 25'h0000000, me });
+ assign _235_ = _234_ ? 1'h1 : 1'h0;
+ assign _236_ = $signed(32'd42) <= $signed({ 25'h0000000, me });
+ assign _237_ = _236_ ? 1'h1 : 1'h0;
+ assign _238_ = $signed(32'd43) <= $signed({ 25'h0000000, me });
+ assign _239_ = _238_ ? 1'h1 : 1'h0;
+ assign _240_ = $signed(32'd44) <= $signed({ 25'h0000000, me });
+ assign _241_ = _240_ ? 1'h1 : 1'h0;
+ assign _242_ = $signed(32'd45) <= $signed({ 25'h0000000, me });
+ assign _243_ = _242_ ? 1'h1 : 1'h0;
+ assign _244_ = $signed(32'd46) <= $signed({ 25'h0000000, me });
+ assign _245_ = _244_ ? 1'h1 : 1'h0;
+ assign _246_ = $signed(32'd47) <= $signed({ 25'h0000000, me });
+ assign _247_ = _246_ ? 1'h1 : 1'h0;
+ assign _248_ = $signed(32'd48) <= $signed({ 25'h0000000, me });
+ assign _249_ = _248_ ? 1'h1 : 1'h0;
+ assign _250_ = $signed(32'd49) <= $signed({ 25'h0000000, me });
+ assign _251_ = _250_ ? 1'h1 : 1'h0;
+ assign _252_ = $signed(32'd50) <= $signed({ 25'h0000000, me });
+ assign _253_ = _252_ ? 1'h1 : 1'h0;
+ assign _254_ = $signed(32'd51) <= $signed({ 25'h0000000, me });
+ assign _255_ = _254_ ? 1'h1 : 1'h0;
+ assign _256_ = $signed(32'd52) <= $signed({ 25'h0000000, me });
+ assign _257_ = _256_ ? 1'h1 : 1'h0;
+ assign _258_ = $signed(32'd53) <= $signed({ 25'h0000000, me });
+ assign _259_ = _258_ ? 1'h1 : 1'h0;
+ assign _260_ = $signed(32'd54) <= $signed({ 25'h0000000, me });
+ assign _261_ = _260_ ? 1'h1 : 1'h0;
+ assign _262_ = $signed(32'd55) <= $signed({ 25'h0000000, me });
+ assign _263_ = _262_ ? 1'h1 : 1'h0;
+ assign _264_ = $signed(32'd56) <= $signed({ 25'h0000000, me });
+ assign _265_ = _264_ ? 1'h1 : 1'h0;
+ assign _266_ = $signed(32'd57) <= $signed({ 25'h0000000, me });
+ assign _267_ = _266_ ? 1'h1 : 1'h0;
+ assign _268_ = $signed(32'd58) <= $signed({ 25'h0000000, me });
+ assign _269_ = _268_ ? 1'h1 : 1'h0;
+ assign _270_ = $signed(32'd59) <= $signed({ 25'h0000000, me });
+ assign _271_ = _270_ ? 1'h1 : 1'h0;
+ assign _272_ = $signed(32'd60) <= $signed({ 25'h0000000, me });
+ assign _273_ = _272_ ? 1'h1 : 1'h0;
+ assign _274_ = $signed(32'd61) <= $signed({ 25'h0000000, me });
+ assign _275_ = _274_ ? 1'h1 : 1'h0;
+ assign _276_ = $signed(32'd62) <= $signed({ 25'h0000000, me });
+ assign _277_ = _276_ ? 1'h1 : 1'h0;
+ assign _278_ = $signed(32'd63) <= $signed({ 25'h0000000, me });
+ assign _279_ = _278_ ? 1'h1 : 1'h0;
+ assign ml = _151_ ? { _153_, _155_, _157_, _159_, _161_, _163_, _165_, _167_, _169_, _171_, _173_, _175_, _177_, _179_, _181_, _183_, _185_, _187_, _189_, _191_, _193_, _195_, _197_, _199_, _201_, _203_, _205_, _207_, _209_, _211_, _213_, _215_, _217_, _219_, _221_, _223_, _225_, _227_, _229_, _231_, _233_, _235_, _237_, _239_, _241_, _243_, _245_, _247_, _249_, _251_, _253_, _255_, _257_, _259_, _261_, _263_, _265_, _267_, _269_, _271_, _273_, _275_, _277_, _279_ } : 64'h0000000000000000;
+ assign _280_ = ~ clear_right;
+ assign _281_ = clear_left & _280_;
+ assign _282_ = _281_ | right_shift;
+ assign _283_ = arith & _001_[31];
+ assign _284_ = mb[5:0] > me[5:0];
+ assign _285_ = clear_right & _284_;
+ assign _286_ = _285_ ? 1'h1 : 1'h0;
+ assign output_mode = _282_ ? { 1'h1, _283_ } : { 1'h0, _286_ };
+ assign _287_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
+ assign _288_ = rot & _287_;
+ assign _289_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } & ml;
+ assign _290_ = ~ _289_;
+ assign _291_ = ra & _290_;
+ assign _292_ = _288_ | _291_;
+ assign _293_ = output_mode == 2'h0;
+ assign _294_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
+ assign _295_ = rot & _294_;
+ assign _296_ = { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ } | ml;
+ assign _297_ = ~ _296_;
+ assign _298_ = ra & _297_;
+ assign _299_ = _295_ | _298_;
+ assign _300_ = output_mode == 2'h1;
+ assign _301_ = rot & { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
+ assign _302_ = output_mode == 2'h2;
+ assign _303_ = ~ { _024_, _026_, _028_, _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_ };
+ assign _304_ = rot | _303_;
+ function [63:0] \19303 ;
+ input [63:0] a;
+ input [191:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \19303 = b[63:0];
+ 3'b?1?:
+ \19303 = b[127:64];
+ 3'b1??:
+ \19303 = b[191:128];
+ default:
+ \19303 = a;
+ endcase
+ endfunction
+ assign _305_ = \19303 (_304_, { _301_, _299_, _292_ }, { _302_, _300_, _293_ });
+ assign _306_ = output_mode == 2'h3;
+ assign _307_ = ~ ml;
+ assign _308_ = rs & _307_;
+ assign _309_ = | _308_;
+ assign _310_ = _306_ ? _309_ : 1'h0;
+ assign result = _305_;
+ assign carry_out = _310_;
+endmodule
+
+module writeback(clk, e_in, l_in, w_out, c_out, complete_out);
+ wire [31:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire [31:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire [31:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire [70:0] _10_;
+ wire [40:0] _11_;
+ wire [5:0] _12_;
+ wire [70:0] _13_;
+ wire [8:0] _14_;
+ wire [3:0] _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire [8:0] _22_;
+ wire [3:0] _23_;
+ wire [70:0] _24_;
+ wire [46:0] _25_;
+ output [46:0] c_out;
+ input clk;
+ output complete_out;
+ input [190:0] e_in;
+ input [77:0] l_in;
+ output [70:0] w_out;
+ assign _00_ = { 31'h00000000, e_in[0] } + { 31'h00000000, l_in[0] };
+ assign _01_ = $signed(_00_) <= $signed(32'd1);
+ assign _02_ = e_in[2] | e_in[120];
+ assign _03_ = { 31'h00000000, _02_ } + { 31'h00000000, l_in[1] };
+ assign _04_ = $signed(_03_) <= $signed(32'd1);
+ assign _05_ = e_in[2] & e_in[1];
+ assign _06_ = { 31'h00000000, e_in[73] } + { 31'h00000000, _05_ };
+ assign _07_ = $signed(_06_) <= $signed(32'd1);
+ assign _08_ = e_in[0] | l_in[0];
+ assign _09_ = _08_ ? 1'h1 : 1'h0;
+ assign _10_ = e_in[2] ? { 1'h1, e_in[72:3] } : 71'h000000000000000000;
+ assign _11_ = e_in[73] ? { e_in[113:74], 1'h1 } : 41'h00000000000;
+ assign _12_ = e_in[114] ? { e_in[119:115], 1'h1 } : 6'h00;
+ assign _13_ = l_in[1] ? { 1'h1, l_in[70:7], 1'h0, l_in[6:2] } : _10_;
+ assign _14_ = l_in[76] ? 9'h101 : _11_[8:0];
+ assign _15_ = l_in[76] ? { 2'h0, l_in[77], l_in[75] } : _11_[40:37];
+ assign _16_ = e_in[1] & e_in[2];
+ assign _17_ = | e_in[72:9];
+ assign _18_ = ~ _17_;
+ assign _19_ = ~ e_in[72];
+ assign _20_ = ~ _18_;
+ assign _21_ = _19_ & _20_;
+ assign _22_ = _16_ ? 9'h101 : _14_;
+ assign _23_ = _16_ ? { e_in[72], _21_, _18_, e_in[119] } : _15_;
+ assign _24_ = e_in[120] ? { 1'h1, e_in[190:121] } : _13_;
+ assign _25_ = e_in[120] ? 47'h000000000000 : { _12_, _23_, _11_[36:9], _22_ };
+ assign w_out = _24_;
+ assign c_out = _25_;
+ assign complete_out = _09_;
+endmodule
+
+module zero_counter(clk, rs, count_right, is_32bit, result);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [1:0] _06_;
+ wire [1:0] _07_;
+ wire [1:0] _08_;
+ wire [1:0] _09_;
+ wire [1:0] _10_;
+ wire [1:0] _11_;
+ wire [1:0] _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire [1:0] _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire [15:0] _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire [1:0] _26_;
+ wire [1:0] _27_;
+ wire [1:0] _28_;
+ wire [1:0] _29_;
+ wire [1:0] _30_;
+ wire [1:0] _31_;
+ wire [1:0] _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire [3:0] _36_;
+ wire _37_;
+ wire [1:0] _38_;
+ wire [1:0] _39_;
+ wire [1:0] _40_;
+ wire [1:0] _41_;
+ wire [1:0] _42_;
+ wire [1:0] _43_;
+ wire [1:0] _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire [4:0] _51_;
+ wire [63:0] _52_;
+ wire [63:0] _53_;
+ input clk;
+ input count_right;
+ input is_32bit;
+ reg [19:0] r;
+ output [63:0] result;
+ input [63:0] rs;
+ always @(posedge clk)
+ r <= { count_right, is_32bit, _16_, _20_ };
+ assign _00_ = | rs[15:0];
+ assign _01_ = | rs[31:16];
+ assign _02_ = | rs[47:32];
+ assign _03_ = | rs[63:48];
+ assign _04_ = ~ is_32bit;
+ assign _05_ = ~ count_right;
+ assign _06_ = _01_ ? 2'h1 : 2'h0;
+ assign _07_ = _02_ ? 2'h2 : _06_;
+ assign _08_ = _03_ ? 2'h3 : _07_;
+ assign _09_ = _02_ ? 2'h2 : 2'h3;
+ assign _10_ = _01_ ? 2'h1 : _09_;
+ assign _11_ = _00_ ? 2'h0 : _10_;
+ assign _12_ = _05_ ? _08_ : _11_;
+ assign _13_ = ~ count_right;
+ assign _14_ = ~ _00_;
+ assign _15_ = _13_ ? _01_ : _14_;
+ assign _16_ = _04_ ? _12_ : { 1'h0, _15_ };
+ assign _17_ = _16_ == 2'h0;
+ assign _18_ = _16_ == 2'h1;
+ assign _19_ = _16_ == 2'h2;
+ function [15:0] \19932 ;
+ input [15:0] a;
+ input [47:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \19932 = b[15:0];
+ 3'b?1?:
+ \19932 = b[31:16];
+ 3'b1??:
+ \19932 = b[47:32];
+ default:
+ \19932 = a;
+ endcase
+ endfunction
+ assign _20_ = \19932 (rs[63:48], rs[47:0], { _19_, _18_, _17_ });
+ assign _21_ = | r[3:0];
+ assign _22_ = | r[7:4];
+ assign _23_ = | r[11:8];
+ assign _24_ = | r[15:12];
+ assign _25_ = ~ r[19];
+ assign _26_ = _22_ ? 2'h1 : 2'h0;
+ assign _27_ = _23_ ? 2'h2 : _26_;
+ assign _28_ = _24_ ? 2'h3 : _27_;
+ assign _29_ = _23_ ? 2'h2 : 2'h3;
+ assign _30_ = _22_ ? 2'h1 : _29_;
+ assign _31_ = _21_ ? 2'h0 : _30_;
+ assign _32_ = _25_ ? _28_ : _31_;
+ assign _33_ = _32_ == 2'h0;
+ assign _34_ = _32_ == 2'h1;
+ assign _35_ = _32_ == 2'h2;
+ function [3:0] \19991 ;
+ input [3:0] a;
+ input [11:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \19991 = b[3:0];
+ 3'b?1?:
+ \19991 = b[7:4];
+ 3'b1??:
+ \19991 = b[11:8];
+ default:
+ \19991 = a;
+ endcase
+ endfunction
+ assign _36_ = \19991 (r[15:12], r[11:0], { _35_, _34_, _33_ });
+ assign _37_ = ~ r[19];
+ assign _38_ = _36_[1] ? 2'h1 : 2'h0;
+ assign _39_ = _36_[2] ? 2'h2 : _38_;
+ assign _40_ = _36_[3] ? 2'h3 : _39_;
+ assign _41_ = _36_[2] ? 2'h2 : 2'h3;
+ assign _42_ = _36_[1] ? 2'h1 : _41_;
+ assign _43_ = _36_[0] ? 2'h0 : _42_;
+ assign _44_ = _37_ ? _40_ : _43_;
+ assign _45_ = _36_ == 4'h0;
+ assign _46_ = ~ r[18];
+ assign _47_ = ~ r[19];
+ assign _48_ = ~ r[17];
+ assign _49_ = ~ r[18];
+ assign _50_ = _48_ & _49_;
+ assign _51_ = ~ { r[16], _32_, _44_ };
+ assign _52_ = _47_ ? { 58'h000000000000000, _50_, _51_ } : { 58'h000000000000000, r[17:16], _32_, _44_ };
+ assign _53_ = _45_ ? { 57'h000000000000000, _46_, r[18], 5'h00 } : _52_;
+ assign result = _53_;
+endmodule
--- /dev/null
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
--- /dev/null
+
+interface remote_bitbang
+remote_bitbang_port 44853
+remote_bitbang_host localhost
+
+# this should be irlen=4
+jtag newtap libresoc tap -irlen 4 -irmask 0xf -ircapture 0xf -expected-id 0x000018ff
+
+#set _TARGETNAME libresoc.tap
+#target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
+
+# Configure work area in on-chip SRAM
+#$_TARGETNAME.0 configure -work-area-phys 0x80000000 \
+# -work-area-size 1000 -work-area-backup 0
+
--- /dev/null
+#!/usr/bin/env python3
+
+import os
+import argparse
+
+from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
+
+from litex.build.generic_platform import Pins, Subsignal
+from litex.build.sim import SimPlatform
+from litex.build.io import CRG
+from litex.build.sim.config import SimConfig
+
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.soc_core import SoCCore
+from litex.soc.integration.soc_sdram import SoCSDRAM
+from litex.soc.integration.builder import Builder
+from litex.soc.integration.common import get_mem_data
+
+from litedram import modules as litedram_modules
+from litedram.phy.model import SDRAMPHYModel
+from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
+
+from litex.tools.litex_sim import Platform
+
+from libresoc import LibreSoC
+from microwatt import Microwatt
+
+# HACK!
+from litex.soc.integration.soc import SoCCSRHandler
+SoCCSRHandler.supported_address_width.append(12)
+
+# LibreSoCSim -----------------------------------------------------------------
+
+class LibreSoCSim(SoCSDRAM):
+ def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
+ with_sdram=True,
+ sdram_module = "AS4C16M16",
+ #sdram_data_width = 16,
+ #sdram_module = "MT48LC16M16",
+ sdram_data_width = 16,
+ irq_reserved_irqs = {'uart': 0},
+ ):
+ assert cpu in ["libresoc", "microwatt"]
+ platform = Platform()
+ sys_clk_freq = int(100e6)
+
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "hello_world/hello_world.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/1.bin"
+ #ram_fname = "/tmp/test.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "micropython/firmware.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/xics/xics.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/decrementer/decrementer.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "hello_world/hello_world.bin"
+ ram_fname = None
+
+ # reserve XICS ICP and XICS memory addresses.
+ self.mem_map['icp'] = 0xc0004000
+ self.mem_map['ics'] = 0xc0005000
+ self.mem_map['gpio'] = 0xc0007000
+ #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
+ #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
+
+ ram_init = []
+ if ram_fname:
+ #ram_init = get_mem_data({
+ # ram_fname: "0x00000000",
+ # }, "little")
+ ram_init = get_mem_data(ram_fname, "little")
+
+ # remap the main RAM to reset-start-address
+ self.mem_map["main_ram"] = 0x00000000
+
+ # without sram nothing works, therefore move it to higher up
+ self.mem_map["sram"] = 0x90000000
+
+ # put UART at 0xc000200 (w00t! this works!)
+ self.csr_map["uart"] = 4
+
+
+ # SoCCore -------------------------------------------------------------
+ SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+ cpu_type = "microwatt",
+ cpu_cls = LibreSoC if cpu == "libresoc" \
+ else Microwatt,
+ #bus_data_width = 64,
+ csr_address_width = 12, # limit to 0x4000
+ cpu_variant = variant,
+ csr_data_width = 8,
+ l2_size = 0,
+ uart_name = "sim",
+ with_sdram = with_sdram,
+ sdram_module = sdram_module,
+ sdram_data_width = sdram_data_width,
+ integrated_rom_size = 0 if ram_fname else 0x10000,
+ integrated_sram_size = 0x40000,
+ #integrated_main_ram_init = ram_init,
+ integrated_main_ram_size = 0x00000000 if with_sdram \
+ else 0x10000000 , # 256MB
+ )
+ self.platform.name = "sim"
+
+ if cpu == "libresoc":
+ # XICS interrupt devices
+ icp_addr = self.mem_map['icp']
+ icp_wb = self.cpu.xics_icp
+ icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
+ self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+
+ ics_addr = self.mem_map['ics']
+ ics_wb = self.cpu.xics_ics
+ ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
+ self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+
+ if "gpio" in variant:
+ # Simple GPIO peripheral
+ gpio_addr = self.mem_map['gpio']
+ gpio_wb = self.cpu.simple_gpio
+ gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
+ self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
+
+
+ # CRG -----------------------------------------------------------------
+ self.submodules.crg = CRG(platform.request("sys_clk"))
+
+ #ram_init = []
+
+ # SDRAM ----------------------------------------------------
+ if with_sdram:
+ sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
+ sdram_module_cls = getattr(litedram_modules, sdram_module)
+ sdram_rate = "1:{}".format(
+ sdram_module_nphases[sdram_module_cls.memtype])
+ sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
+ phy_settings = get_sdram_phy_settings(
+ memtype = sdram_module.memtype,
+ data_width = sdram_data_width,
+ clk_freq = sdram_clk_freq)
+ self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
+ phy_settings,
+ init=ram_init
+ )
+ self.register_sdram(
+ self.sdrphy,
+ sdram_module.geom_settings,
+ sdram_module.timing_settings)
+ # FIXME: skip memtest to avoid corrupting memory
+ self.add_constant("MEMTEST_BUS_SIZE", 128//16)
+ self.add_constant("MEMTEST_DATA_SIZE", 128//16)
+ self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
+ self.add_constant("MEMTEST_BUS_DEBUG", 1)
+ self.add_constant("MEMTEST_ADDR_DEBUG", 1)
+ self.add_constant("MEMTEST_DATA_DEBUG", 1)
+
+
+ # add JTAG platform pins
+ platform.add_extension([
+ ("jtag", 0,
+ Subsignal("tck", Pins(1)),
+ Subsignal("tms", Pins(1)),
+ Subsignal("tdi", Pins(1)),
+ Subsignal("tdo", Pins(1)),
+ )
+ ])
+
+ jtagpads = platform.request("jtag")
+ self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+ self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+ self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+ self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+
+ # Debug ---------------------------------------------------------------
+ if not debug:
+ return
+
+ # setup running of DMI FSM
+ dmi_addr = Signal(4)
+ dmi_din = Signal(64)
+ dmi_dout = Signal(64)
+ dmi_wen = Signal(1)
+ dmi_req = Signal(1)
+
+ # debug log out
+ dbg_addr = Signal(4)
+ dbg_dout = Signal(64)
+ dbg_msg = Signal(1)
+
+ # capture pc from dmi
+ pc = Signal(64)
+ active_dbg = Signal()
+ active_dbg_cr = Signal()
+ active_dbg_xer = Signal()
+
+ # xer flags
+ xer_so = Signal()
+ xer_ca = Signal()
+ xer_ca32 = Signal()
+ xer_ov = Signal()
+ xer_ov32 = Signal()
+
+ # increment counter, Stop after 100000 cycles
+ uptime = Signal(64)
+ self.sync += uptime.eq(uptime + 1)
+ #self.sync += If(uptime == 1000000000000, Finish())
+
+ # DMI FSM counter and FSM itself
+ dmicount = Signal(10)
+ dmirunning = Signal(1)
+ dmi_monitor = Signal(1)
+ dmifsm = FSM()
+ self.submodules += dmifsm
+
+ # DMI FSM
+ dmifsm.act("START",
+ If(dmi_req & dmi_wen,
+ (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
+ self.cpu.dmi_din.eq(dmi_din), # DMI in
+ self.cpu.dmi_req.eq(1), # DMI request
+ self.cpu.dmi_wr.eq(1), # DMI write
+ If(self.cpu.dmi_ack,
+ (NextState("IDLE"),
+ )
+ ),
+ ),
+ ),
+ If(dmi_req & ~dmi_wen,
+ (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr
+ self.cpu.dmi_req.eq(1), # DMI request
+ self.cpu.dmi_wr.eq(0), # DMI read
+ If(self.cpu.dmi_ack,
+ # acknowledge received: capture data.
+ (NextState("IDLE"),
+ NextValue(dbg_addr, dmi_addr),
+ NextValue(dbg_dout, self.cpu.dmi_dout),
+ NextValue(dbg_msg, 1),
+ ),
+ ),
+ ),
+ )
+ )
+
+ # DMI response received: reset the dmi request and check if
+ # in "monitor" mode
+ dmifsm.act("IDLE",
+ If(dmi_monitor,
+ NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
+ ).Else(
+ NextState("START"), # back to start on next cycle
+ ),
+ NextValue(dmi_req, 0),
+ NextValue(dmi_addr, 0),
+ NextValue(dmi_din, 0),
+ NextValue(dmi_wen, 0),
+ )
+
+ # "monitor" mode fires off a STAT request
+ dmifsm.act("FIRE_MONITOR",
+ (NextValue(dmi_req, 1),
+ NextValue(dmi_addr, 1), # DMI STAT address
+ NextValue(dmi_din, 0),
+ NextValue(dmi_wen, 0), # read STAT
+ NextState("START"), # back to start on next cycle
+ )
+ )
+
+ self.comb += xer_so.eq((dbg_dout & 1) == 1)
+ self.comb += xer_ca.eq((dbg_dout & 4) == 4)
+ self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
+ self.comb += xer_ov.eq((dbg_dout & 16) == 16)
+ self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
+
+ # debug messages out
+ self.sync += If(dbg_msg,
+ (If(active_dbg & (dbg_addr == 0b10), # PC
+ Display("pc : %016x", dbg_dout),
+ ),
+ If(dbg_addr == 0b10, # PC
+ pc.eq(dbg_dout), # capture PC
+ ),
+ #If(dbg_addr == 0b11, # MSR
+ # Display(" msr: %016x", dbg_dout),
+ #),
+ If(dbg_addr == 0b1000, # CR
+ Display(" cr : %016x", dbg_dout),
+ ),
+ If(dbg_addr == 0b1001, # XER
+ Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
+ xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
+ ),
+ If(dbg_addr == 0b101, # GPR
+ Display(" gpr: %016x", dbg_dout),
+ ),
+ # also check if this is a "stat"
+ If(dbg_addr == 1, # requested a STAT
+ #Display(" stat: %x", dbg_dout),
+ If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
+ dmirunning.eq(1), # continue running
+ dmi_monitor.eq(0), # and stop monitor mode
+ ),
+ ),
+ dbg_msg.eq(0)
+ )
+ )
+
+ # kick off a "stop"
+ self.sync += If(uptime == 0,
+ (dmi_addr.eq(0), # CTRL
+ dmi_din.eq(1<<0), # STOP
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ )
+ )
+
+ self.sync += If(uptime == 4,
+ dmirunning.eq(1),
+ )
+
+ self.sync += If(dmirunning,
+ dmicount.eq(dmicount + 1),
+ )
+
+ # loop every 1<<N cycles
+ cyclewid = 9
+
+ # get the PC
+ self.sync += If(dmicount == 4,
+ (dmi_addr.eq(0b10), # NIA
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # kick off a "step"
+ self.sync += If(dmicount == 8,
+ (dmi_addr.eq(0), # CTRL
+ dmi_din.eq(1<<3), # STEP
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ dmirunning.eq(0), # stop counter, need to fire "monitor"
+ dmi_monitor.eq(1), # start "monitor" instead
+ )
+ )
+
+ # limit range of pc for debug reporting
+ #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
+ #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
+ self.comb += active_dbg.eq(1)
+
+
+ # get the MSR
+ self.sync += If(active_dbg & (dmicount == 12),
+ (dmi_addr.eq(0b11), # MSR
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ if cpu == "libresoc":
+ #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
+ self.comb += active_dbg_cr.eq(0)
+
+ # get the CR
+ self.sync += If(active_dbg_cr & (dmicount == 16),
+ (dmi_addr.eq(0b1000), # CR
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
+ self.comb += active_dbg_xer.eq(active_dbg_cr)
+
+ # get the CR
+ self.sync += If(active_dbg_xer & (dmicount == 20),
+ (dmi_addr.eq(0b1001), # XER
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # read all 32 GPRs
+ for i in range(32):
+ self.sync += If(active_dbg & (dmicount == 24+(i*8)),
+ (dmi_addr.eq(0b100), # GSPR addr
+ dmi_din.eq(i), # r1
+ dmi_req.eq(1),
+ dmi_wen.eq(1),
+ )
+ )
+
+ self.sync += If(active_dbg & (dmicount == 28+(i*8)),
+ (dmi_addr.eq(0b101), # GSPR data
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
+ # monitor bbus read/write
+ self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
+ Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
+ #uptime,
+ 0,
+ self.cpu.dbus.adr,
+ self.cpu.dbus.we,
+ self.cpu.dbus.sel,
+ self.cpu.dbus.dat_w,
+ self.cpu.dbus.dat_r
+ )
+ )
+
+ return
+
+ # monitor ibus write
+ self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
+ self.cpu.ibus.we,
+ Display(" [%06x] iadr: %8x, s %01x w %016x",
+ #uptime,
+ 0,
+ self.cpu.ibus.adr,
+ self.cpu.ibus.sel,
+ self.cpu.ibus.dat_w,
+ )
+ )
+ # monitor ibus read
+ self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
+ ~self.cpu.ibus.we,
+ Display(" [%06x] iadr: %8x, s %01x r %016x",
+ #uptime,
+ 0,
+ self.cpu.ibus.adr,
+ self.cpu.ibus.sel,
+ self.cpu.ibus.dat_r
+ )
+ )
+
+# Build -----------------------------------------------------------------------
+
+def main():
+ parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
+ parser.add_argument("--cpu", default="libresoc",
+ help="CPU to use: libresoc (default) or microwatt")
+ parser.add_argument("--variant", default="standardjtag",
+ help="Specify variant with different features")
+ parser.add_argument("--debug", action="store_true",
+ help="Enable debug traces")
+ parser.add_argument("--trace", action="store_true",
+ help="Enable tracing")
+ parser.add_argument("--trace-start", default=0,
+ help="Cycle to start FST tracing")
+ parser.add_argument("--trace-end", default=-1,
+ help="Cycle to end FST tracing")
+ args = parser.parse_args()
+
+ sim_config = SimConfig(default_clk="sys_clk")
+ sim_config.add_module("serial2console", "serial")
+ sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
+
+ for i in range(2):
+ soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
+ builder = Builder(soc,compile_gateware = i!=0)
+ builder.build(sim_config=sim_config,
+ run = i!=0,
+ trace = args.trace,
+ trace_start = int(args.trace_start),
+ trace_end = int(args.trace_end),
+ trace_fst = 0)
+ os.chdir("../")
+
+if __name__ == "__main__":
+ main()
--- /dev/null
+#!/usr/bin/env python3
+
+import os
+import argparse
+
+import litex_boards.targets.versa_ecp5 as versa_ecp5
+import litex_boards.targets.ulx3s as ulx3s
+
+from litex.soc.integration.soc_sdram import (soc_sdram_args,
+ soc_sdram_argdict)
+from litex.soc.integration.builder import (Builder, builder_args,
+ builder_argdict)
+
+from libresoc import LibreSoC
+#from microwatt import Microwatt
+
+# TestSoC
+# ----------------------------------------------------------------------------
+
+from litex.build.generic_platform import Subsignal, Pins, IOStandard
+
+class VersaECP5TestSoC(versa_ecp5.BaseSoC):
+ def __init__(self, sys_clk_freq=int(16e6), **kwargs):
+ kwargs["integrated_rom_size"] = 0x10000
+ #kwargs["integrated_main_ram_size"] = 0x1000
+ kwargs["csr_data_width"] = 32
+ kwargs["l2_size"] = 0
+ #bus_data_width = 16,
+
+ versa_ecp5.BaseSoC.__init__(self,
+ sys_clk_freq = sys_clk_freq,
+ cpu_type = "external",
+ cpu_cls = LibreSoC,
+ cpu_variant = "standardjtagnoirq",
+ #cpu_cls = Microwatt,
+ device = "LFE5UM",
+ **kwargs)
+
+ # (thanks to daveshah for this tip)
+ # use platform.add_extension to first define the pins
+ # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
+
+ # define the pins, add as an extension, *then* request it
+ jtag_ios = [
+ ("jtag", 0,
+ Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
+ Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
+ Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
+ Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
+ )
+ ]
+ self.platform.add_extension(jtag_ios)
+ jtag = self.platform.request("jtag")
+
+ # wire the pins up to CPU JTAG
+ self.comb += self.cpu.jtag_tck.eq(jtag.tck)
+ self.comb += self.cpu.jtag_tms.eq(jtag.tms)
+ self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
+ self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
+
+
+ #self.add_constant("MEMTEST_BUS_SIZE", 256//16)
+ #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
+ #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
+
+ #self.add_constant("MEMTEST_BUS_DEBUG", 1)
+ #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
+ #self.add_constant("MEMTEST_DATA_DEBUG", 1)
+
+
+class ULX3S85FTestSoC(ulx3s.BaseSoC):
+ def __init__(self, sys_clk_freq=int(16e6), **kwargs):
+ kwargs["integrated_rom_size"] = 0x10000
+ #kwargs["integrated_main_ram_size"] = 0x1000
+ kwargs["csr_data_width"] = 32
+ kwargs["l2_size"] = 0
+ #bus_data_width = 16,
+
+ ulx3s.BaseSoC.__init__(self,
+ sys_clk_freq = sys_clk_freq,
+ cpu_type = "external",
+ cpu_cls = LibreSoC,
+ cpu_variant = "standardjtag",
+ #cpu_cls = Microwatt,
+ device = "LFE5U-85F",
+ **kwargs)
+
+ # get 4 arbitrarily assinged logical pins, each gpio has
+ # 2 distinct physical single non-differential pins p and n
+ gpio0 = self.platform.request("gpio", 0)
+ gpio1 = self.platform.request("gpio", 1)
+
+ # assign p, n litex 'subsignals' of each gpio to jtag pins
+ jtag_tdi = gpio0.n
+ jtag_tms = gpio0.p
+ jtag_tck = gpio1.n
+ jtag_tdo = gpio1.p
+
+ # wire the pins up to CPU JTAG
+ self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
+ self.comb += self.cpu.jtag_tms.eq(jtag_tms)
+ self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
+ self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
+
+# Build
+# ----------------------------------------------------------------------------
+
+def main():
+ parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
+ "CPU on Versa ECP5 or ULX3S LFE5U85F")
+ parser.add_argument("--build", action="store_true", help="Build bitstream")
+ parser.add_argument("--load", action="store_true", help="Load bitstream")
+ parser.add_argument("--sys-clk-freq", default=int(16e6),
+ help="System clock frequency (default=16MHz)")
+ parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
+ "to build for/load to")
+
+ builder_args(parser)
+ soc_sdram_args(parser)
+ args = parser.parse_args()
+
+ if args.fpga == "versa_ecp5":
+ soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+ **soc_sdram_argdict(args))
+
+ elif args.fpga == "ulx3s85f":
+ soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+ **soc_sdram_argdict(args))
+
+ else:
+ soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+ **soc_sdram_argdict(args))
+
+ builder = Builder(soc, **builder_argdict(args))
+ builder.build(run=args.build)
+
+ if args.load:
+ prog = soc.platform.create_programmer()
+ prog.load_bitstream(os.path.join(builder.gateware_dir,
+ soc.build_name + ".svf"))
+
+if __name__ == "__main__":
+ main()
+++ /dev/null
-#ifndef __IRQ_H
-#define __IRQ_H
-
-static inline unsigned int irq_getie(void)
-{
- return 0;
-}
-
-static inline void irq_setie(unsigned int ie)
-{
- /*if(ie) csrs(); else csrc();*/
-}
-
-static inline unsigned int irq_getmask(void)
-{
- unsigned int mask = 0;
- //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
- return mask;
-}
-
-static inline void irq_setmask(unsigned int mask)
-{
- //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-}
-
-static inline unsigned int irq_pending(void)
-{
- unsigned int pending = 0;
- //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
- return pending;
-}
-
-#endif /* __IRQ_H */
+++ /dev/null
-#!/usr/bin/env python3
-
-# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
-# This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
-# License: BSD
-
-import os
-import argparse
-
-from litex.build.generic_platform import Pins, Subsignal
-from litex.build.sim import SimPlatform
-from litex.build.io import CRG
-from litex.build.sim.config import SimConfig
-
-from litex.soc.integration.soc import SoCRegion
-from litex.soc.integration.soc_core import SoCCore
-from litex.soc.integration.common import get_mem_data
-from litex.soc.integration.builder import Builder
-
-from litedram.modules import IS42S16160, MT41K128M16
-from litedram.phy.model import SDRAMPHYModel
-from litedram.core.controller import ControllerSettings
-
-from litex.tools.litex_sim import get_sdram_phy_settings
-
-from soc.litex.core import LibreSOC
-
-# IOs ------------------------------------------------------------------
-
-_io = [
- ("sys_clk", 0, Pins(1)),
- ("sys_rst", 0, Pins(1)),
- ("serial", 0,
- Subsignal("source_valid", Pins(1)),
- Subsignal("source_ready", Pins(1)),
- Subsignal("source_data", Pins(8)),
-
- Subsignal("sink_valid", Pins(1)),
- Subsignal("sink_ready", Pins(1)),
- Subsignal("sink_data", Pins(8)),
- ),
-]
-
-# Platform --------------------------------------------------------------
-
-class Platform(SimPlatform):
- def __init__(self):
- SimPlatform.__init__(self, "SIM", _io)
-
-# SoCSMP ----------------------------------------------------------------
-
-class SoCSMP(SoCCore):
- def __init__(self, cpu_variant, init_memories=False, with_sdcard=False):
- platform = Platform()
- sys_clk_freq = int(100e6)
-
- sdram_init = []
- if init_memories:
- sdram_init = get_mem_data({
- "images/fw_jump.bin": "0x00f00000",
- "images/Image": "0x00000000",
- "images/dtb" : "0x00ef0000",
- "images/rootfs.cpio": "0x01000000",
- }, "little")
-
- # SoCCore --------------------------------------------------------
- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
- cpu_type = "microwatt", # XXX use microwatt
- cpu_variant = cpu_variant,
- cpu_cls = LibreSOC,
- bus_data_width = 32, # XXX TODO 64 bit wishbone data bus
- uart_name = "sim",
- integrated_rom_size = 0x8000,
- integrated_main_ram_size = 0x00000000)
-
- self.platform.name = "sim"
- self.add_constant("SIM")
-
- # CRG -------------------------------------------------------
- self.submodules.crg = CRG(platform.request("sys_clk"))
-
- # SDRAM ----------------------------------------------------------
- if False:
- phy_settings = get_sdram_phy_settings(
- #memtype = "DDR3",
- memtype = "SDR",
- data_width = 16,
- clk_freq = 100e6)
- self.submodules.sdrphy = SDRAMPHYModel(
- #module = MT41K128M16(100e6, "1:4"),
- module = IS42S16160(100e6, "1:4"),
- settings = phy_settings,
- clk_freq = 100e6,
- init = sdram_init)
- self.add_sdram("sdram",
- phy = self.sdrphy,
- #module = MT41K128M16(100e6, "1:4"),
- module = IS42S16160(100e6, "1:4"),
- origin = self.mem_map["main_ram"],
- #controller_settings = ControllerSettings(
- # cmd_buffer_buffered = False,
- # with_auto_precharge = True
- #)
- )
- if init_memories:
- addr = 0x40f00000
- self.add_constant("MEMTEST_BUS_SIZE", 0) # Skip test if memory is
- self.add_constant("MEMTEST_ADDR_SIZE", 0) # initialized to avoid
- self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content.
- self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin
- else:
- self.add_constant("MEMTEST_BUS_SIZE", 4096//64)
- self.add_constant("MEMTEST_ADDR_SIZE", 4096//256)
- self.add_constant("MEMTEST_DATA_SIZE", 4096//32)
-
- # SDCard -----------------------------------------------------
- if with_sdcard:
- self.add_sdcard("sdcard", use_emulator=True)
-
-# Build -----------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(
- description="Linux on LiteX-LibreSOC Simulation")
- parser.add_argument("--cpu-variant", default="standard",
- help="Select CPU netlist variant")
- parser.add_argument("--sdram-init", action="store_true",
- help="Init SDRAM with Linux images")
- parser.add_argument("--with-sdcard", action="store_true",
- help="Enable SDCard support")
- parser.add_argument("--trace", action="store_true",
- help="Enable VCD tracing")
- parser.add_argument("--trace-start", default=0,
- help="Cycle to start VCD tracing")
- parser.add_argument("--trace-end", default=-1,
- help="Cycle to end VCD tracing")
- parser.add_argument("--opt-level", default="O3",
- help="Compilation optimization level")
- args = parser.parse_args()
-
- sim_config = SimConfig(default_clk="sys_clk")
- sim_config.add_module("serial2console", "serial")
-
- for i in range(2):
- to_run = (i != 0) # first build (i=0), then run (i=1)
- soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run,
- args.with_sdcard)
- builder = Builder(soc,
- compile_gateware = to_run,
- csr_json = "build/sim/csr.json")
- builder.build(sim_config=sim_config,
- run = to_run,
- opt_level = args.opt_level,
- trace = args.trace,
- trace_start = int(args.trace_start),
- trace_end = int(args.trace_end),
- trace_fst = 0)
- os.chdir("../")
- #if not to_run:
- # os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
- # os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME
- # os.system("cp verilog/*.bin build/sim/gateware/")
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-#ifndef __SYSTEM_H
-#define __SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
-__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
-void flush_l2_cache(void);
-
-void busy_wait(unsigned int ms);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_H */
projects / soc.git / commitdiff