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incorrect indentation in dcache rams
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 26 Apr 2021 09:19:26 +0000 (10:19 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 26 Apr 2021 09:19:26 +0000 (10:19 +0100)
src/soc/experiment/dcache.py patch | blob | history

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index aea4a28baa5b6a76fd91199b5912f656f41164e5..b94a7cad1d6ee98095a1284957bbd10f5a7544d2 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1128,9 +1128,9 @@ class DCache(Elaboratable):
                 comb += wr_addr.eq(r1.store_row)
                 comb += wr_sel.eq(~0) # all 1s
 
-            with m.If((r1.state == State.RELOAD_WAIT_ACK)
-                      & wb_in.ack & (replace_way == i)):
-                comb += do_write.eq(1)
+                with m.If((r1.state == State.RELOAD_WAIT_ACK)
+                          & wb_in.ack & (replace_way == i)):
+                    comb += do_write.eq(1)
 
             # Mask write selects with do_write since BRAM
             # doesn't have a global write-enable