fix wb_get error where data was being corrupted

(not WB classic compliant)

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index c529372a9c7c66cd5dee33c643999329d2f35fee..8688bd94d77e954ba1ba907c42c1ce0fe690cc35 100644 (file)
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -79,13 +79,14 @@ def wb_get(wb):
         yield wb.ack.eq(1)
         yield
         yield wb.ack.eq(0)
+        yield
 
 
 def mmu_lookup(dut, addr):
     mmu = dut.submodules.mmu
     global stop
 
-    print("pi_ld")
+    print("pi_ld", hex(addr))
     data = yield from pi_ld(dut.submodules.ldst.pi, addr, 4, msr_pr=1)
     print("pi_ld done, data", hex(data))
     """
@@ -123,20 +124,30 @@ def ldst_sim(dut):
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
     yield
 
+    # expecting this data to return
+    # 0x1000: 0xdeadbeef01234567,
+    # 0x1008: 0xfeedf00ff001a5a5
+
     addr = 0x1000
     print("pi_ld")
 
     # TODO mmu_lookup using port interface
     # set inputs 
-    phys_addr = yield from mmu_lookup(dut, addr)
-    #assert phys_addr == addr # happens to be the same (for this example)
+    data = yield from mmu_lookup(dut, addr)
+    assert data == 0x1234567
 
-    phys_addr = yield from mmu_lookup(dut, addr)
+    data = yield from mmu_lookup(dut, addr+8)
+    assert data == 0xf001a5a5
     #assert phys_addr == addr # happens to be the same (for this example)
 
-    phys_addr = yield from mmu_lookup(dut, addr+4)
+    data = yield from mmu_lookup(dut, addr+4)
+    assert data == 0xdeadbeef
 
-    phys_addr = yield from mmu_lookup(dut, addr+8)
+    data = yield from mmu_lookup(dut, addr+8)
+    assert data == 0xf001a5a5
+
+    yield
+    yield
 
     stop = True
 

diff --git a/src/soc/experiment/test/test_mmu_dcache.py b/src/soc/experiment/test/test_mmu_dcache.py
index 0748a05a8815e4323a6a2d5fc524f8747a1e2186..1528d7d40db31bbaed8f821a7a90663ef087bb26 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache.py
+++ b/src/soc/experiment/test/test_mmu_dcache.py
@@ -89,6 +89,7 @@ def wb_get(c, mem, name):
         yield c.wb_in.ack.eq(1)
         yield
         yield c.wb_in.ack.eq(0)
+        yield
 
 
 def icache_sim(dut, mem):

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index 35d5808118d919be76e39f5f6f69ca1a321704a0..2f219e63ebbd91043a54f81d8f06f88e9eaf7939 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -170,6 +170,7 @@ def wb_get(dc):
         yield dc.wb_in.ack.eq(1)
         yield
         yield dc.wb_in.ack.eq(0)
+        yield
 
 
 def mmu_lookup(dut, addr):