create array of in_a, in_b and out_z

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index d829e0ec1a114695695bdacf68df314df52d6861..d37de7ae75d96d833d868233306aba5530454f1d 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux
+from nmigen import Module, Signal, Cat, Mux, Array
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 
@@ -1423,7 +1423,7 @@ class FPADD(FPID):
         needs to be the thing that raises the incoming stb.
     """
 
-    def __init__(self, width, id_wid=None, single_cycle=False):
+    def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=1):
         """ IEEE754 FP Add
 
             * width: bit-width of IEEE754.  supported: 16, 32, 64
@@ -1434,10 +1434,19 @@ class FPADD(FPID):
         self.id_wid = id_wid
         self.single_cycle = single_cycle
 
+        #self.out_z = FPOp(width)
         self.ids = FPID(id_wid)
-        self.in_a  = FPOp(width)
-        self.in_b  = FPOp(width)
-        self.out_z = FPOp(width)
+
+        rs = []
+        for i in range(rs_sz):
+            in_a  = FPOp(width)
+            in_b  = FPOp(width)
+            out_z = FPOp(width)
+            in_a.name = "in_a_%d" % i
+            in_b.name = "in_b_%d" % i
+            out_z.name = "out_z_%d" % i
+            rs.append((in_a, in_b, out_z))
+        self.rs = Array(rs)
 
         self.states = []
 
@@ -1449,24 +1458,25 @@ class FPADD(FPID):
         """ creates the HDL code-fragment for FPAdd
         """
         m = Module()
-        m.submodules.in_a = self.in_a
-        m.submodules.in_b = self.in_b
-        m.submodules.out_z = self.out_z
+        m.submodules += self.rs
 
+        in_a = self.rs[0][0]
+        in_b = self.rs[0][1]
+        out_z = self.rs[0][2]
         geta = self.add_state(FPGetOp("get_a", "get_b",
-                                      self.in_a, self.width))
-        geta.setup(m, self.in_a)
+                                      in_a, self.width))
+        geta.setup(m, in_a)
         a = geta.out_op
 
         getb = self.add_state(FPGetOp("get_b", "fpadd",
-                                      self.in_b, self.width))
-        getb.setup(m, self.in_b)
+                                      in_b, self.width))
+        getb.setup(m, in_b)
         b = getb.out_op
 
         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
         ab = self.add_state(ab)
         ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
-                 self.out_z, self.ids.out_mid)
+                 out_z, self.ids.out_mid)
 
         #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
         #                            ab.out_mid, self.out_mid))

diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index e14d4f9246b829e93ceb816ee6317256c10b5efe..50ba8f713c61ac09db066f7efa788ad5293b9304 100644 (file)
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -37,41 +37,42 @@ def match(x, y):
         )
 
 def get_case(dut, a, b, mid):
+    in_a, in_b, out_z = dut.rs[0]
     yield dut.ids.in_mid.eq(mid)
-    yield dut.in_a.v.eq(a)
-    yield dut.in_a.stb.eq(1)
+    yield in_a.v.eq(a)
+    yield in_a.stb.eq(1)
     yield
     yield
     yield
     yield
-    a_ack = (yield dut.in_a.ack)
+    a_ack = (yield in_a.ack)
     assert a_ack == 0
 
-    yield dut.in_a.stb.eq(0)
+    yield in_a.stb.eq(0)
 
-    yield dut.in_b.v.eq(b)
-    yield dut.in_b.stb.eq(1)
+    yield in_b.v.eq(b)
+    yield in_b.stb.eq(1)
     yield
     yield
-    b_ack = (yield dut.in_b.ack)
+    b_ack = (yield in_b.ack)
     assert b_ack == 0
 
-    yield dut.in_b.stb.eq(0)
+    yield in_b.stb.eq(0)
 
-    yield dut.out_z.ack.eq(1)
+    yield out_z.ack.eq(1)
 
     while True:
-        out_z_stb = (yield dut.out_z.stb)
+        out_z_stb = (yield out_z.stb)
         if not out_z_stb:
             yield
             continue
-        out_z = yield dut.out_z.v
+        vout_z = yield out_z.v
         out_mid = yield dut.ids.out_mid
-        yield dut.out_z.ack.eq(0)
+        yield out_z.ack.eq(0)
         yield
         break
 
-    return out_z, out_mid
+    return vout_z, out_mid
 
 def check_case(dut, a, b, z, mid=None):
     if mid is None: