add quick print statements to show that elaborate() gets called as a

second phase after the creation of the AST tree
this gives a window of opportunity to tree-walk and set whether SimdSignals
are LHS or RHS as determined by encountering SimdSignal.__Assign__

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 9a761aad86abd0f798052cac25499088d01b05e6..9306f64d862ced34b5e96d8722c9bb4de8cbbe5a 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -158,6 +158,7 @@ class SimdSignal(UserValue):
         return PRepl(self.m, self, count, self.ptype)
 
     def __Cat__(self, *args, src_loc_at=0):
+        print ("partsig cat", self, args)
         # TODO: need SwizzledSimdValue-aware Cat
         args = [self] + list(args)
         for sig in args:
@@ -174,7 +175,7 @@ class SimdSignal(UserValue):
         return PMux(self.m, self.partpoints, self, val1, val2, self.ptype)
 
     def __Assign__(self, val, *, src_loc_at=0):
-        # print ("partsig ass", self, val)
+        print ("partsig assign", self, val)
         return PAssign(self.m, self, val, self.ptype)
 
     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458

diff --git a/src/ieee754/part/test/minitest_partsig.py b/src/ieee754/part/test/minitest_partsig.py
new file mode 100644 (file)
index 0000000..e18e39f
--- /dev/null
+++ b/src/ieee754/part/test/minitest_partsig.py
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: LGPL-2.1-or-later
+# See Notices.txt for copyright information
+
+"""
+Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+mini demo test of Cat and Assign
+"""
+
+from nmigen import Signal, Module, Elaboratable, Cat, Const, signed
+from nmigen.back.pysim import Simulator, Settle
+from nmutil.extend import ext
+
+from ieee754.part_mul_add.partpoints import PartitionPoints
+from ieee754.part.partsig import SimdSignal
+
+
+if __name__ == "__main__":
+    from ieee754.part.test.test_partsig import create_simulator
+    m = Module()
+    mask = Signal(3)
+    a = SimdSignal(mask, 16)
+    b = SimdSignal(mask, 16)
+    o = SimdSignal(mask, 32)
+    a.set_module(m)
+    b.set_module(m)
+    o.set_module(m)
+
+    omask = (1<<len(o)) - 1
+    m.d.comb += o.eq(Cat(a, b))
+
+    sim = create_simulator(m, [], "minitest")
+
+    def process():
+        yield mask.eq(0b000)
+        yield a.sig.eq(0x0123)
+        yield b.sig.eq(0x4567)
+        yield Settle()
+        out = yield o.sig
+        print("out 000", bin(out&omask), hex(out&omask))
+        yield mask.eq(0b010)
+        yield Settle()
+        out = yield o.sig
+        print("out 010", bin(out&omask), hex(out&omask))
+        yield mask.eq(0b110)
+        yield Settle()
+        out = yield o.sig
+        print("out 110", bin(out&omask), hex(out&omask))
+        yield mask.eq(0b111)
+        yield Settle()
+        out = yield o.sig
+        print("out 111", bin(out&omask), hex(out&omask))
+
+    sim.add_process(process)
+    with sim.write_vcd("partition_minitest.vcd", "partition_partition_ass.gtkw",
+                        traces=[]):
+        sim.run()
+

diff --git a/src/ieee754/part_ass/assign.py b/src/ieee754/part_ass/assign.py
index 81873bcbe7714f0167708832596f06110a04a29b..9d411ba26c2c74d1c11439e207b42dbe3b3f3a5e 100644 (file)
--- a/src/ieee754/part_ass/assign.py
+++ b/src/ieee754/part_ass/assign.py
@@ -75,6 +75,7 @@ class PartitionedAssign(Elaboratable):
         return x.sig[start:end]
 
     def elaborate(self, platform):
+        print ("PartitionedAssign start")
         m = Module()
         comb = m.d.comb
 
@@ -107,6 +108,7 @@ class PartitionedAssign(Elaboratable):
                     # direct access to the underlying Signal
                     comb += self.output.sig.eq(Cat(*output))
 
+        print ("PartitionedAssign end")
         return m
 
     def ports(self):

diff --git a/src/ieee754/part_cat/cat.py b/src/ieee754/part_cat/cat.py
index 09170898ad7a93b0e68ab5123baec6a18d9fa218..4fb5484cdee83c8cac857a8722caae8771598045 100644 (file)
--- a/src/ieee754/part_cat/cat.py
+++ b/src/ieee754/part_cat/cat.py
@@ -88,6 +88,7 @@ class PartitionedCat(Elaboratable):
         return x.sig[start:end]
 
     def elaborate(self, platform):
+        print ("PartitionedCat start")
         m = Module()
         comb = m.d.comb
 
@@ -113,6 +114,7 @@ class PartitionedCat(Elaboratable):
                     # direct access to the underlying Signal
                     comb += self.output.sig.eq(Cat(*output))
 
+        print ("PartitionedCat end")
         return m
 
     def ports(self):