Convert add and sub to return PartitionedSignal

Adjust the test suite accordingly.

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 9e6e78b6ffc7965e72af7a1f4ea4a23405072740..f09b972a4c93e3a07e1f869c1f9a8ff16952743a 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -163,7 +163,9 @@ class PartitionedSignal:
         comb += pa.a.eq(op1)
         comb += pa.b.eq(op2)
         comb += pa.carry_in.eq(carry)
-        return (pa.output, pa.carry_out)
+        result = PartitionedSignal.like(self)
+        comb += result.sig.eq(pa.output)
+        return result, pa.carry_out
 
     def sub_op(self, op1, op2, carry=~0):
         op1 = getsig(op1)
@@ -174,7 +176,9 @@ class PartitionedSignal:
         comb += pa.a.eq(op1)
         comb += pa.b.eq(~op2)
         comb += pa.carry_in.eq(carry)
-        return (pa.output, pa.carry_out)
+        result = PartitionedSignal.like(self)
+        comb += result.sig.eq(pa.output)
+        return result, pa.carry_out
 
     def __add__(self, other):
         result, _ = self.add_op(self, other, carry=0)

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 7d87eceebac77801362179bdb4a8ca50140ded55..2bf0ef837a7a6b5be5d26a645590962732b47577 100644 (file)
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -149,15 +149,15 @@ class TestAddMod(Elaboratable):
         # add
         add_out, add_carry = self.a.add_op(self.a, self.b,
                                            self.carry_in)
-        comb += self.add_output.eq(add_out)
+        comb += self.add_output.eq(add_out.sig)
         comb += self.add_carry_out.eq(add_carry)
         # sub
         sub_out, sub_carry = self.a.sub_op(self.a, self.b,
                                            self.carry_in)
-        comb += self.sub_output.eq(sub_out)
+        comb += self.sub_output.eq(sub_out.sig)
         comb += self.sub_carry_out.eq(sub_carry)
         # neg
-        comb += self.neg_output.eq(-self.a)
+        comb += self.neg_output.eq((-self.a).sig)
         # left shift
         comb += self.ls_output.eq(self.a << self.b)
         # right shift