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diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index ca1a96361bf9ba2dcaccfd9933feec4a491572ec..e5ae956a163e5d28627da4270b4ed31fceb663d4 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -292,6 +292,7 @@ class L0CacheBuffer(Elaboratable):
             comb += wrport.en.eq(1)                # enable write
             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 
+        # after waiting one cycle (reset_l is "sync" mode), reset the port
         with m.If(reset_l.q):
             comb += idx_l.s.eq(1)  # deactivate port-index selector
             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle