hooray, convert PartitionedCat over to new PartType API, using

get_num_elements and get_el_range

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index cf1e6678c84389c2e9868e3fbf06e5231be7d6f7..af2057a23966295afdf2928176d8eaebd1dd1c85 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -108,10 +108,10 @@ class PartType:  # TODO decide name
         runs = get_runlengths(pbit, len(keys))
         keys = [0] + keys + [len(self.psig.sig)]
         y = 0
-        numparts = runs[0]
         for i in range(el_num):
-            y += numparts
             numparts = runs[i]
+            y += numparts
+        numparts = runs[el_num]
         return range(keys[y], keys[y+numparts])
 
     @property

diff --git a/src/ieee754/part_cat/cat.py b/src/ieee754/part_cat/cat.py
index 1f42d3f034e191f77dc79988b2c0e4449cd90a42..9479a14579a9fc4d1f1742ee0a78fe5cf1d2c772 100644 (file)
--- a/src/ieee754/part_cat/cat.py
+++ b/src/ieee754/part_cat/cat.py
@@ -112,13 +112,14 @@ class PartitionedCat(Elaboratable):
                 # then when called below in the inner nested loop they give
                 # the relevant sequential chunk
                 output = []
-                y = [0] * len(self.catlist)
+                nelts = self.ptype.get_num_elements(pbit)
                 # get a list of the length of each partition run
-                runlengths = get_runlengths(pbit, len(keys))
-                print ("pbit", bin(pbit), "runs", runlengths)
-                for i in runlengths: # for each partition
-                    for yidx in range(len(y)):
-                        thing = self.get_chunk(y, yidx, i) # sequential chunks
+                #runlengths = get_runlengths(pbit, len(keys))
+                print ("pbit", bin(pbit), "nelts", nelts)
+                for i in range(nelts): # for each element
+                    for x in self.catlist:
+                        trange = x.ptype.get_el_range(pbit, i)
+                        thing = x.sig[trange.start:trange.stop:trange.step]
                         output.append(thing)
                 with m.Case(pbit):
                     # direct access to the underlying Signal
@@ -142,8 +143,11 @@ if __name__ == "__main__":
     mask = Signal(3)
     a = SimdSignal(mask, 32)
     b = SimdSignal(mask, 16)
+    a.set_module(m)
+    b.set_module(m)
     catlist = [a, b]
     m.submodules.cat = cat = PartitionedCat(catlist, a.ptype)
+    cat.set_lhs_mode(False)
 
     traces = cat.ports()
     sim = create_simulator(m, traces, "partcat")