corrections to flexbus line directions

diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index 88cbdcf5936b168ff6a9175dffd05e3752547a42..e1189898545367de88aa0064b164d02c4a9c3189 100644 (file)
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -88,17 +88,17 @@ def pinspec():
     flexspec = {
         'FB_TS': ('FB_ALE', 2),
         'FB_CS2': ('FB_BWE2', 2),
-        'FB_A0': ('FB_BWE2', 3),
+        'FB_AD0': ('FB_BWE2', 3),
         'FB_CS3': ('FB_BWE3', 2),
-        'FB_A1': ('FB_BWE3', 3),
+        'FB_AD1': ('FB_BWE3', 3),
         'FB_TBST': ('FB_OE', 2),
         'FB_TSIZ0': ('FB_BWE0', 2),
         'FB_TSIZ1': ('FB_BWE1', 2),
     }
-    ps.gpio("", ('B', 0), 0, 0, 32)
+    ps.gpio("", ('B', 0), 0, 0, 18)
     ps.flexbus1("", ('B', 0), 1, spec=flexspec)
 
-    ps.gpio("", ('C', 0), 0, 0, 32)
+    ps.gpio("", ('C', 0), 0, 0, 24)
     ps.flexbus2("", ('C', 0), 1)
 
     # Scenarios below can be spec'd out as either "find first interface"

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 33226e4ea4036c6c78bca43db590b067769a3aea..57611869913bfa989487e238a425182fc120858f 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -143,11 +143,11 @@ def flexbus1(suffix, bank):
         inout.append(pname)
     for i in range(2):
         buspins.append("CS%d+" % i)
-    buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
-                'A0', 'A1', 'TS', 'TBST',
-                'TSIZ0', 'TSIZ1']
+    buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
+                'TS+', 'TBST+',
+                'TSIZ0+', 'TSIZ1+']
     for i in range(4):
-        buspins.append("BWE%d" % i)
+        buspins.append("BWE%d+" % i)
     for i in range(2, 6):
         buspins.append("CS%d+" % i)
     return (buspins, inout)