adding support for JTAG pins

diff --git a/pinmap.txt b/pinmap.txt
index 3c94746b85eb284799a4dd0d8e7f8b31269113f2..82f9ffe395d04a0737dce25ca0f060d31442d81a 100644 (file)
--- a/pinmap.txt
+++ b/pinmap.txt
@@ -14,3 +14,8 @@ dedicated
 5              uart1_rx
 6              twi1_sda
 7              twi1_scl
+14   jtag0_tclk
+15   jtag0_tdo
+16  jtag0_tdi
+17  jtag0_tms
+18  jtag0_tdo

diff --git a/src/interface_decl.py b/src/interface_decl.py
index 8c390dd3cfe8c62d04a0e262bd0972e4503693a4..4569b4caf16e444f89795f9326dc1760775751fe 100644 (file)
--- a/src/interface_decl.py
+++ b/src/interface_decl.py
@@ -56,4 +56,12 @@ sdinterface_decl = '''
       (*always_ready,always_enabled*) method Action sd{0}_d3_outen (Bit#(1) in);
       (*always_ready,always_enabled*) method Bit#(1) sd{0}_d3_in;
 '''
+
+jtaginterface_decl = '''
+      (*always_ready,always_enabled*) method Bit#(1) jtag{0}_tdi;
+      (*always_ready,always_enabled*) method Bit#(1) jtag{0}_tms;
+      (*always_ready,always_enabled*) method Bit#(1) jtag{0}_tclk;
+      (*always_ready,always_enabled*) method Bit#(1) jtag{0}_trst;
+      (*always_ready,always_enabled*) method Action jtag{0}_tdo(Bit#(1) in);
+'''
 # ======================================= #

diff --git a/src/interface_def.py b/src/interface_def.py
index acf0d9f7c51fdb94c1e86d4ad4a93115cfefe119..07d3b3f580bdf6a89137dc1411e5cc85a5defd9f 100644 (file)
--- a/src/interface_def.py
+++ b/src/interface_def.py
@@ -92,4 +92,14 @@ sdinterface_def = '''
       endmethod
       method sd{0}_d3_in=wrsd{0}_d3_in;
 '''
+
+jtaginterface_def = '''
+      method Bit#(1) jtag{0}_tdi=wrjtag{0}_tdi;
+      method Bit#(1) jtag{0}_tms=wrjtag{0}_tms;
+      method Bit#(1) jtag{0}_tclk=wrjtag{0}_tclk;
+      method Bit#(1) jtag{0}_trst=wrjtag{0}_trst;
+      method Action jtag{0}_tdo(Bit#(1) in);
+        wrjtag{0}_tdo<=in;
+      endmethod
+'''
 # ============================================== #

diff --git a/src/parse.py b/src/parse.py
index ed7a9701b3cbaf6f4f6bf42ffda73fec73b0eb30..a9913ae972b385c62c4080f06e1582c438774a6e 100644 (file)
--- a/src/parse.py
+++ b/src/parse.py
@@ -6,6 +6,7 @@ N_UART = 4
 N_SPI = 1
 N_TWI = 2
 N_SD = 2
+N_JTAG = 2
 # ================ #
 
 

diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py
index 11c2593141bf7d6467a57f7cd4e96e692eac070e..e4ef9f672c51cbcdab7c96ccf6bfbd057ee49d2f 100644 (file)
--- a/src/pinmux_generator.py
+++ b/src/pinmux_generator.py
@@ -109,6 +109,11 @@ for i in range(0, N_SD):
     bsv_file.write('''
       // interface declaration between SD-{0} and pinmux'''.format(i))
     bsv_file.write(sdinterface_decl.format(i))
+
+for i in range(0, N_JTAG):
+    bsv_file.write('''
+      // interface declaration between JTAG-{0} and pinmux'''.format(i))
+    bsv_file.write(jtaginterface_decl.format(i))
 # ==============================================================
 
 # ===== finish interface definition and start module definition=======
@@ -156,6 +161,12 @@ for i in range(0, N_SD):
         '''\n      // following wires capture signals to IO CELL if sd-{0} is
       // allotted to it'''.format(i))
     bsv_file.write(sdwires.format(i))
+
+for i in range(0, N_JTAG):
+    bsv_file.write(
+        '''\n      // following wires capture signals to IO CELL if jtag-{0} is
+      // allotted to it'''.format(i))
+    bsv_file.write(jtagwires.format(i))
 bsv_file.write("\n")
 # ====================================================================
 # ========================= Actual pinmuxing ========================#
@@ -181,6 +192,8 @@ for i in range(0, N_TWI):
     bsv_file.write(twiinterface_def.format(i))
 for i in range(0, N_SD):
     bsv_file.write(sdinterface_def.format(i))
+for i in range(0, N_JTAG):
+    bsv_file.write(jtaginterface_def.format(i))
 bsv_file.write(footer)
 print("BSV file successfully generated: bsv_src/pinmux.bsv")
 # ======================================================================

diff --git a/src/wire_def.py b/src/wire_def.py
index b1a2f69c1697e9a2d34f77b31ebad9e0557afc88..398222228bb87c7b5eda46df7dc47690a74598bd 100644 (file)
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -91,4 +91,27 @@ sdwires = '''
                 pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0,
                 opendrain_en:0}};
 '''
+
+jtagwires = '''
+      Wire#(Bit#(1)) wrjtag{0}_tdi<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tms<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tclk<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_trst<-mkDWire(0);
+      Wire#(Bit#(1)) wrjtag{0}_tdo<-mkDWire(0);
+      GenericIOType jtag{0}_tdi_io=GenericIOType{{outputval:0, output_en:0,
+                input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
+                drivestrength:0, opendrain_en:0}};
+      GenericIOType jtag{0}_tdo_io=GenericIOType{{outputval:wrjtag{0}_tdo,
+                output_en:0, input_en:1, pullup_en:0, pulldown_en:0,
+                pushpull_en:0, drivestrength:0, opendrain_en:0}};
+      GenericIOType jtag{0}_tms_io=GenericIOType{{outputval:0, output_en:0,
+                input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
+                drivestrength:0, opendrain_en:0}};
+      GenericIOType jtag{0}_trst_io=GenericIOType{{outputval:0, output_en:0,
+                input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
+                drivestrength:0, opendrain_en:0}};
+      GenericIOType jtag{0}_tclk_io=GenericIOType{{outputval:0, output_en:0,
+                input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
+                drivestrength:0, opendrain_en:0}};
+'''
 # =================================== #