link MSR.PR into MMU FSM OP_FETCH_FAILED

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 5d0cc8140897f44983c64fd772256402869270a1..7f0b81b4a07665e4763b943caf1f2253221ebd24 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -91,6 +91,7 @@ class FSMMMUStage(ControlBase):
         i_data, o_data = self.p.i_data, self.n.o_data
         op = i_data.ctx.op
         nia_i = op.nia
+        msr_i = op.msr
         a_i, b_i, spr1_i = i_data.ra, i_data.rb, i_data.spr1
         o, exc_o, spr1_o = o_data.o, o_data.exception, o_data.spr1
 
@@ -223,6 +224,7 @@ class FSMMMUStage(ControlBase):
                     # from accepting any other LD/ST requests.
                     comb += valid.eq(1)   # start "pulse"
                     comb += ldst.instr_fault.eq(blip)
+                    comb += ldst.priv_mode.eq(msr_i[MSR.PR])
                     comb += ldst.maddr.eq(nia_i)
                     # XXX should not access this!
                     mmu_done_delay = Signal()