move Mask to nmutil

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 554367c7561de78c7aa94c053681cebe340dce9b..6af299aab9149273c0e029232a644d9031e55871 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -9,7 +9,8 @@ from nmigen.cli import main
 from nmigen.cli import rtlil
 from nmutil.iocontrol import RecordObject
 from nmutil.byterev import byte_reverse
-from nmigen.utils import log2_int
+from nmutil.mask import Mask
+
 
 from soc.experiment.mem_types import (LoadStore1ToMmuType,
                                  MmuToLoadStore1Type,
@@ -68,24 +69,6 @@ class RegStage(RecordObject):
         self.rc_error = Signal()
 
 
-class Mask(Elaboratable):
-    def __init__(self, sz):
-        self.sz = sz
-        self.shift = Signal(log2_int(sz, False))
-        self.mask = Signal(sz)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        comb = m.d.comb
-
-        for i in range(self.sz):
-            with m.If(self.shift > i):
-                comb += self.mask[i].eq(1)
-
-        return m
-
-
 class MMU(Elaboratable):
     """Radix MMU
 

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index a3545ec70e9343c19e4c8e63aeba30db9e90975f..d451e614d1de55f23a00e73a4a431738127acb70 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -31,7 +31,7 @@ class LibreSoCSim(SoCSDRAM):
             #sdram_module          = "AS4C16M16",
             #sdram_data_width      = 16,
             sdram_module          = "MT48LC16M16",
-            sdram_data_width      = 32,
+            sdram_data_width      = 16,
             ):
         assert cpu in ["libresoc", "microwatt"]
         platform     = Platform()
@@ -43,6 +43,8 @@ class LibreSoCSim(SoCSDRAM):
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
             #bus_data_width           = 64,
+            csr_data_width            = 32,
+            l2_cache_size             = 0,
             uart_name                = "sim",
             with_sdram               = with_sdram,
             sdram_module          = sdram_module,
@@ -78,10 +80,12 @@ class LibreSoCSim(SoCSDRAM):
                             sdram_module.geom_settings,
                             sdram_module.timing_settings)
             # FIXME: skip memtest to avoid corrupting memory
-            #self.add_constant("MEMTEST_BUS_SIZE",  64//16)
-            #self.add_constant("MEMTEST_DATA_SIZE", 64//16)
-            #self.add_constant("MEMTEST_ADDR_SIZE", 64//16)
+            self.add_constant("MEMTEST_BUS_SIZE",  128//16)
+            self.add_constant("MEMTEST_DATA_SIZE", 128//16)
+            self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
             self.add_constant("MEMTEST_BUS_DEBUG", 1)
+            self.add_constant("MEMTEST_ADDR_DEBUG", 1)
+            self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
 
         # Debug ---------------------------------------------------------------